diff --git a/sensor/stmemsc/CMakeLists.txt b/sensor/stmemsc/CMakeLists.txt index 215cab6af094d9a3bb9f0826d41a7ee133104e00..fb5fd795a26bc5348846a646b851804cd32bd795 100644 --- a/sensor/stmemsc/CMakeLists.txt +++ b/sensor/stmemsc/CMakeLists.txt @@ -6,10 +6,12 @@ set(stmems_pids a3g4250d + ais25ba ais2dw12 ais2ih ais328dq ais3624dq + asm330lhb asm330lhh asm330lhhx h3lis100dl @@ -24,9 +26,11 @@ set(stmems_pids iis3dhhc iis3dwb ilps22qs + ilps28qsw ism303dac ism330dhcx ism330dlc + ism330is l20g20is l3gd20h lis25ba @@ -35,6 +39,9 @@ set(stmems_pids lis2dh12 lis2ds12 lis2dtw12 + lis2du12 + lis2dux12 + lis2duxs12 lis2dw12 lis2hh12 lis2mdl @@ -62,11 +69,15 @@ set(stmems_pids lsm6dsl lsm6dsm lsm6dso + lsm6dso16is lsm6dso32 lsm6dso32x lsm6dsox lsm6dsr lsm6dsrx + lsm6dsv16bx + lsm6dsv16x + lsm6dsv lsm9ds1 stts22h stts751 diff --git a/sensor/stmemsc/README b/sensor/stmemsc/README index e4029564017e0b17a735cf1bc97ad7172cc1d96f..65decdb8a3ed36798297f03da01850ba032af4e4 100644 --- a/sensor/stmemsc/README +++ b/sensor/stmemsc/README @@ -6,7 +6,7 @@ Origin: https://www.st.com/en/embedded-software/c-driver-mems.html Status: - version v2.01 + version v2.02 Purpose: ST Microelectronics standard C platform-independent drivers for MEMS @@ -25,18 +25,26 @@ Description: The driver is platform-independent, you only need to define the two functions for read and write transactions from the sensor hardware bus - (ie. SPI or I2C). + (ie. SPI or I2C). In addition you may define a mdelay (milliseconds) + routine. Define in your 'xyz' driver code the read and write functions that use the - I2C or SPI platform driver like the following: + I2C or SPI platform driver (plus the optional mdelay function) like the following: /** Please note that is MANDATORY: return 0 -> no Error.**/ int platform_wr(void *handle, u8_t reg, const u8_t *bufp, u16_t len); int platform_rd(void *handle, u8_t reg, u8_t *bufp, u16_t len); + /** Component optional fields **/ + void platform_mdelay(u32_t millisec); + + stmdev_ctx_t stmdev_ctx = { .read_reg = (stmdev_read_ptr) platform_rd, .write_reg = (stmdev_write_ptr) platform_wr, + + /** Component optional fields **/ + .mdelay = (stmdev_mdelay_ptr) platform_mdelay, }; Dependencies: @@ -46,7 +54,7 @@ URL: https://www.st.com/en/embedded-software/c-driver-mems.html commit: - version v2.01 + version v2.02 Maintained-by: ST Microelectronics diff --git a/sensor/stmemsc/_resources/FIFO_Utility_Tool/main.c b/sensor/stmemsc/_resources/FIFO_Utility_Tool/main.c new file mode 100644 index 0000000000000000000000000000000000000000..3f7dc37d0c273b0de66aff3cd398ddb4e4d1e65f --- /dev/null +++ b/sensor/stmemsc/_resources/FIFO_Utility_Tool/main.c @@ -0,0 +1,101 @@ +#include +#include +#include + +#include "st_fifo.h" + +uint16_t out_slot_size; + +int main(int argc, char *argv[]) +{ + if (argc != 3) { + printf("Error: please specify input and output as commandline args\n"); + return -1; + } + + FILE *fp; + char *line = NULL; + fp = fopen(argv[1], "r"); + + size_t len = 0; + ssize_t read; + + FILE *out_file; + out_file = fopen(argv[2], "w"); + + int lines = 0; + size_t pos = ftell(fp); + while(!feof(fp)) { + char ch = fgetc(fp); + if(ch == '\n') { + lines++; + } + } + fseek(fp, pos, SEEK_SET); + + printf("File length: %d\n", lines); + + st_fifo_conf conf; + conf.device = ST_FIFO_LSM6DSV16X; + conf.bdr_xl = 0; + conf.bdr_gy = 0; + conf.bdr_vsens = 0; + + st_fifo_init(&conf); + st_fifo_raw_slot *raw_slot; + st_fifo_out_slot *out_slot; + + raw_slot = malloc(lines * sizeof(st_fifo_raw_slot)); + out_slot = malloc(lines * 3 * sizeof(st_fifo_out_slot)); + + int i = 0; + + printf("Running test...\n"); + + while((read = getline(&line, &len, fp)) != -1) { + + int data_in[7]; + + sscanf(line, "%d\t%d\t%d\t%d\t%d\t%d\t%d\r\n", &data_in[0], &data_in[1], &data_in[2], &data_in[3], &data_in[4], &data_in[5], &data_in[6]); + + for (uint8_t j = 0; j < 7; j++) + raw_slot[i].fifo_data_out[j] = data_in[j]; + + i++; + } + + st_fifo_decode(out_slot, raw_slot, &out_slot_size, lines); + st_fifo_sort(out_slot, out_slot_size); + + uint16_t acc_samples = st_fifo_get_sensor_occurrence(out_slot, out_slot_size, ST_FIFO_ACCELEROMETER); + uint16_t gyr_samples = st_fifo_get_sensor_occurrence(out_slot, out_slot_size, ST_FIFO_GYROSCOPE); + + printf("acc samples: %d\n", acc_samples); + printf("gyr samples: %d\n", gyr_samples); + + st_fifo_out_slot *acc_slot = malloc(acc_samples * sizeof(st_fifo_out_slot)); + st_fifo_out_slot *gyr_slot = malloc(gyr_samples * sizeof(st_fifo_out_slot)); + + st_fifo_extract_sensor(acc_slot, out_slot, out_slot_size, ST_FIFO_ACCELEROMETER); + st_fifo_extract_sensor(gyr_slot, out_slot, out_slot_size, ST_FIFO_GYROSCOPE); + + for (int i = 0; i < out_slot_size; i++) { + fprintf(out_file, "%u\t%d\t%d\t%d\t%d\r\n", out_slot[i].timestamp, out_slot[i].sensor_tag, out_slot[i].sensor_data.data[0], out_slot[i].sensor_data.data[1], out_slot[i].sensor_data.data[2]); + } + /* + for (int i = 0; i < acc_samples; i++) { + printf("ACC SLOT:\t%lld\t%d\t%d\t%d\t%d\r\n", acc_slot[i].timestamp, acc_slot[i].sensor_tag, acc_slot[i].data[0], acc_slot[i].data[1], acc_slot[i].data[2]); + } + + for (int i = 0; i < gyr_samples; i++) { + printf("GYR SLOT:\t%lld\t%d\t%d\t%d\t%d\r\n", gyr_slot[i].timestamp, gyr_slot[i].sensor_tag, gyr_slot[i].data[0], gyr_slot[i].data[1], gyr_slot[i].data[2]); + } + */ + + printf("Test finished: see %s file\n", argv[2]); + + fclose(fp); + fclose(out_file); + + return 0; +} diff --git a/sensor/stmemsc/_resources/FIFO_Utility_Tool/makefile b/sensor/stmemsc/_resources/FIFO_Utility_Tool/makefile new file mode 100644 index 0000000000000000000000000000000000000000..52e8242420023e74e7cb21647ff88e6d2050eee7 --- /dev/null +++ b/sensor/stmemsc/_resources/FIFO_Utility_Tool/makefile @@ -0,0 +1,11 @@ +CC = gcc +SRC = main.c st_fifo.c + +CFLAGS = -Wall -Wextra -Werror -std=gnu99 + +default: + $(CC) $(CFLAGS) $(SRC) -o st_fifo.run + +clean: + rm -fr *.o + rm -fr st_fifo.run diff --git a/sensor/stmemsc/_resources/FIFO_Utility_Tool/st_fifo.c b/sensor/stmemsc/_resources/FIFO_Utility_Tool/st_fifo.c new file mode 100644 index 0000000000000000000000000000000000000000..2fb423417471f493619c3d29270dc37bde71b4ed --- /dev/null +++ b/sensor/stmemsc/_resources/FIFO_Utility_Tool/st_fifo.c @@ -0,0 +1,937 @@ +/* + ****************************************************************************** + * @file fifo_utility.c + * @author Sensor Solutions Software Team + * @brief Utility for managing FIFO data decoding and decompression. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2022 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include +#include "st_fifo.h" + +/** + * @defgroup FIFO utility + * @brief This file provides a set of functions needed to manage FIFO data + * decoding and decompression. + * @{ + * + */ + +/* Private constants --------------------------------------------------------*/ +#define BDR_XL_MASK (0x0Fu) +#define BDR_XL_SHIFT (0x00u) + +#define BDR_GY_MASK (0xF0u) +#define BDR_GY_SHIFT (0x04u) + +#define BDR_VSENS_MASK (0x0Fu) +#define BDR_VSENS_SHIFT (0x00u) + +#define TAG_COUNTER_MASK (0x06u) +#define TAG_SENSOR_MASK (0xF8u) +#define TAG_COUNTER_SHIFT (0x01u) +#define TAG_SENSOR_SHIFT (0x03u) + +#define TAG_EMPTY (0x00u) +#define TAG_GY (0x01u) +#define TAG_XL (0x02u) +#define TAG_TEMP (0x03u) +#define TAG_TS (0x04u) +#define TAG_ODRCHG (0x05u) +#define TAG_XL_UNCOMPRESSED_T_2 (0x06u) +#define TAG_XL_UNCOMPRESSED_T_1 (0x07u) +#define TAG_XL_COMPRESSED_2X (0x08u) +#define TAG_XL_COMPRESSED_3X (0x09u) +#define TAG_GY_UNCOMPRESSED_T_2 (0x0Au) +#define TAG_GY_UNCOMPRESSED_T_1 (0x0Bu) +#define TAG_GY_COMPRESSED_2X (0x0Cu) +#define TAG_GY_COMPRESSED_3X (0x0Du) +#define TAG_EXT_SENS_0 (0x0Eu) +#define TAG_EXT_SENS_1 (0x0Fu) +#define TAG_EXT_SENS_2 (0x10u) +#define TAG_EXT_SENS_3 (0x11u) +#define TAG_STEP_COUNTER (0x12u) +#define TAG_GAME_RV (0x13u) +#define TAG_GEOM_RV (0x14u) +#define TAG_NORM_RV (0x15u) +#define TAG_GYRO_BIAS (0x16u) +#define TAG_GRAVITIY (0x17u) +#define TAG_MAG_CAL (0x18u) +#define TAG_EXT_SENS_NACK (0x19u) +#define TAG_MLC_RESULT (0x1Au) +#define TAG_MLC_FILTER (0x1Bu) +#define TAG_MLC_FEATURE (0x1Cu) +#define TAG_DUALC_XL (0x1Du) +#define TAG_EIS_GY (0x1Eu) + +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) + +/* Private typedef -----------------------------------------------------------*/ +typedef enum +{ + ST_FIFO_COMPRESSION_NC, + ST_FIFO_COMPRESSION_NC_T_1, + ST_FIFO_COMPRESSION_NC_T_2, + ST_FIFO_COMPRESSION_2X, + ST_FIFO_COMPRESSION_3X +} st_fifo_compression_type; + +/* Private functions ---------------------------------------------------------*/ +/* Functions declare in this section are defined at the end of this file. */ +static uint8_t bdr_get_index(const float *bdr, float n); +static uint8_t has_even_parity(uint8_t x); +static st_fifo_sensor_type get_sensor_type(uint8_t tag); +static st_fifo_compression_type get_compression_type(uint8_t tag); +static uint8_t is_tag_valid(uint8_t tag); +static void get_diff_2x(int16_t diff[6], uint8_t input[6]); +static void get_diff_3x(int16_t diff[9], uint8_t input[6]); + +/* Private variables ---------------------------------------------------------*/ +static const struct +{ + float bdr_acc[16]; + float bdr_gyr[16]; + float bdr_vsens[16]; + uint32_t dtime[16]; + uint8_t tag_valid_limit; +} device[] = +{ + { + .bdr_acc = { 0, 13, 26, 52, 104, 208, 416, 833, 1666, 3333, 6666, 1.625, 0, 0, 0, 0 }, + .bdr_gyr = { 0, 13, 26, 52, 104, 208, 416, 833, 1666, 3333, 6666, 0, 0, 0, 0, 0 }, + .bdr_vsens = { 0, 13, 26, 52, 104, 208, 416, 0, 0, 0, 0, 1.625, 0, 0, 0, 0 }, + .dtime = { 0, 3072, 1536, 768, 384, 192, 96, 48, 24, 12, 6, 24576, 0, 0, 0, 0 }, + .tag_valid_limit = 0x19, + }, + { + .bdr_acc = { 0, 1.875, 7.5, 15, 30, 60, 120, 240, 480, 960, 1920, 3840, 7680, 0, 0, 0 }, + .bdr_gyr = { 0, 1.875, 7.5, 15, 30, 60, 120, 240, 480, 960, 1920, 3840, 7680, 0, 0, 0 }, + .bdr_vsens = { 0, 1.875, 7.5, 15, 30, 60, 120, 240, 480, 960, 0, 0, 0, 0, 0, 0 }, + .dtime = { 0, 24576, 6144, 3072, 1536, 768, 384, 192, 96, 48, 24, 12, 6, 0, 0, 0 }, + .tag_valid_limit = 0x1E, + }, +}; + +static uint8_t fifo_ver; +static uint8_t tag_counter_old; +static uint32_t dtime_xl; +static uint32_t dtime_gy; +static uint32_t dtime_min; +static uint32_t dtime_xl_old; +static uint32_t dtime_gy_old; +static uint32_t timestamp; +static uint32_t last_timestamp_xl; +static uint32_t last_timestamp_gy; +static uint8_t bdr_chg_xl_flag; +static uint8_t bdr_chg_gy_flag; +static int16_t last_data_xl[3]; +static int16_t last_data_gy[3]; + +/** + * @defgroup FIFO public functions + * @brief This section provide a set of APIs for managing FIFO data + * decoding and decompression. + * @{ + * + */ + +/** + * @brief Initialize the FIFO utility library. + * + * @param conf library configuration to set (BDR parameters + * can be set to 0 Hz if ODR_CHG_EN is enabled + * or timestamp sensor is batched in FIFO). + * + * @retval st_fifo_status ST_FIFO_OK / ST_FIFO_ERR + * + */ +st_fifo_status st_fifo_init(st_fifo_conf *conf) +{ + float bdr_xl, bdr_gy, bdr_vsens, bdr_max; + + if (conf->bdr_xl < 0.0f || conf->bdr_gy < 0.0f || conf->bdr_vsens < 0.0f) + { + return ST_FIFO_ERR; + } + + if (conf->device < ST_FIFO_LSM6DSV) + { + fifo_ver = 0; + } + else + { + fifo_ver = 1; + } + + tag_counter_old = 0; + bdr_xl = conf->bdr_xl; + bdr_gy = conf->bdr_gy; + bdr_vsens = conf->bdr_vsens; + bdr_max = MAX(bdr_xl, bdr_gy); + bdr_max = MAX(bdr_max, bdr_vsens); + dtime_min = device[fifo_ver].dtime[bdr_get_index(device[fifo_ver].bdr_acc, bdr_max)]; + dtime_xl = device[fifo_ver].dtime[bdr_get_index(device[fifo_ver].bdr_acc, bdr_xl)]; + dtime_gy = device[fifo_ver].dtime[bdr_get_index(device[fifo_ver].bdr_gyr, bdr_gy)]; + dtime_xl_old = dtime_xl; + dtime_gy_old = dtime_gy; + timestamp = 0; + bdr_chg_xl_flag = 0; + bdr_chg_gy_flag = 0; + last_timestamp_xl = 0; + last_timestamp_gy = 0; + + for (uint8_t i = 0; i < 3u; i++) + { + last_data_xl[i] = 0; + last_data_gy[i] = 0; + } + + return ST_FIFO_OK; +} + +/** + * @brief Decode and decompress a raw FIFO stream. + * + * @param fifo_out_slot decoded output stream.(ptr) + * @param fifo_raw_slot compressed raw input data stream.(ptr) + * @param out_slot_size decoded stream size.(ptr) + * @param stream_size raw input stream size. + * + * @retval st_fifo_status ST_FIFO_OK / ST_FIFO_ERR + * + */ +st_fifo_status st_fifo_decode(st_fifo_out_slot *fifo_out_slot, + st_fifo_raw_slot *fifo_raw_slot, uint16_t *out_slot_size, uint16_t stream_size) +{ + uint16_t j = 0; + + for (uint16_t i = 0; i < stream_size; i++) + { + + uint8_t tag = (fifo_raw_slot[i].fifo_data_out[0] & TAG_SENSOR_MASK) >> TAG_SENSOR_SHIFT; + uint8_t tag_counter = (fifo_raw_slot[i].fifo_data_out[0] & TAG_COUNTER_MASK) >> TAG_COUNTER_SHIFT; + + if (fifo_ver == 0u && has_even_parity(fifo_raw_slot[i].fifo_data_out[0]) == 0u) + { + return ST_FIFO_ERR; + } + + if (is_tag_valid(tag) == 0u) + { + return ST_FIFO_ERR; + } + + if ((tag_counter != (tag_counter_old)) && dtime_min != 0u) + { + + uint8_t diff_tag_counter; + + if (tag_counter < tag_counter_old) + { + diff_tag_counter = tag_counter + 4u - tag_counter_old; + } + else + { + diff_tag_counter = tag_counter - tag_counter_old; + } + + timestamp += dtime_min * diff_tag_counter; + } + + if (tag == TAG_ODRCHG) + { + + uint8_t bdr_acc_cfg = (fifo_raw_slot[i].fifo_data_out[6] & BDR_XL_MASK) >> BDR_XL_SHIFT; + uint8_t bdr_gyr_cfg = (fifo_raw_slot[i].fifo_data_out[6] & BDR_GY_MASK) >> BDR_GY_SHIFT; + uint8_t bdr_vsens_cfg = (fifo_raw_slot[i].fifo_data_out[4] & BDR_VSENS_MASK) >> BDR_VSENS_SHIFT; + + float bdr_xl = device[fifo_ver].bdr_acc[bdr_acc_cfg]; + float bdr_gy = device[fifo_ver].bdr_gyr[bdr_gyr_cfg]; + float bdr_vsens = device[fifo_ver].bdr_vsens[bdr_vsens_cfg]; + float bdr_max = MAX(bdr_xl, bdr_gy); + bdr_max = MAX(bdr_max, bdr_vsens); + + dtime_xl_old = dtime_xl; + dtime_gy_old = dtime_gy; + dtime_min = device[fifo_ver].dtime[bdr_get_index(device[fifo_ver].bdr_acc, bdr_max)]; + dtime_xl = device[fifo_ver].dtime[bdr_get_index(device[fifo_ver].bdr_acc, bdr_xl)]; + dtime_gy = device[fifo_ver].dtime[bdr_get_index(device[fifo_ver].bdr_gyr, bdr_gy)]; + + bdr_chg_xl_flag = 1; + bdr_chg_gy_flag = 1; + + } + else if (tag == TAG_TS) + { + + (void)memcpy(×tamp, &fifo_raw_slot[i].fifo_data_out[1], 4); + + } + else + { + + st_fifo_compression_type compression_type = get_compression_type(tag); + st_fifo_sensor_type sensor_type = get_sensor_type(tag); + + if (compression_type == ST_FIFO_COMPRESSION_NC) + { + + if (tag == TAG_EMPTY) + { + continue; + } + + if (tag == TAG_STEP_COUNTER || tag == TAG_MLC_RESULT) + { + (void)memcpy(&fifo_out_slot[j].timestamp, &fifo_raw_slot[i].fifo_data_out[3], + 4); + } + else + { + fifo_out_slot[j].timestamp = timestamp; + } + + fifo_out_slot[j].sensor_tag = sensor_type; + (void)memcpy(fifo_out_slot[j].sensor_data.raw_data, + &fifo_raw_slot[i].fifo_data_out[1], 6); + + if (sensor_type == ST_FIFO_ACCELEROMETER) + { + (void)memcpy(last_data_xl, fifo_out_slot[j].sensor_data.raw_data, 6); + last_timestamp_xl = timestamp; + bdr_chg_xl_flag = 0; + } + + if (sensor_type == ST_FIFO_GYROSCOPE) + { + (void)memcpy(last_data_gy, fifo_out_slot[j].sensor_data.raw_data, 6); + last_timestamp_gy = timestamp; + bdr_chg_gy_flag = 0; + } + + j++; + + } + else if (compression_type == ST_FIFO_COMPRESSION_NC_T_1) + { + + fifo_out_slot[j].sensor_tag = get_sensor_type(tag); + (void)memcpy(fifo_out_slot[j].sensor_data.raw_data, + &fifo_raw_slot[i].fifo_data_out[1], 6); + + if (sensor_type == ST_FIFO_ACCELEROMETER) + { + uint32_t last_timestamp; + + if (bdr_chg_xl_flag == 1u) + { + last_timestamp = last_timestamp_xl + dtime_xl_old; + } + else + { + last_timestamp = timestamp - dtime_xl; + } + + fifo_out_slot[j].timestamp = last_timestamp; + (void)memcpy(last_data_xl, fifo_out_slot[j].sensor_data.raw_data, 6); + last_timestamp_xl = last_timestamp; + } + + if (sensor_type == ST_FIFO_GYROSCOPE) + { + uint32_t last_timestamp; + + if (bdr_chg_gy_flag == 1u) + { + last_timestamp = last_timestamp_gy + dtime_gy_old; + } + else + { + last_timestamp = timestamp - dtime_gy; + } + + fifo_out_slot[j].timestamp = last_timestamp; + (void)memcpy(last_data_gy, fifo_out_slot[j].sensor_data.raw_data, 6); + last_timestamp_gy = last_timestamp; + } + + j++; + + } + else if (compression_type == ST_FIFO_COMPRESSION_NC_T_2) + { + + fifo_out_slot[j].sensor_tag = get_sensor_type(tag); + (void)memcpy(fifo_out_slot[j].sensor_data.raw_data, + &fifo_raw_slot[i].fifo_data_out[1], 6); + + if (sensor_type == ST_FIFO_ACCELEROMETER) + { + uint32_t last_timestamp; + + if (bdr_chg_xl_flag == 1u) + { + last_timestamp = last_timestamp_xl + dtime_xl_old; + } + else + { + last_timestamp = timestamp - 2u * dtime_xl; + } + + fifo_out_slot[j].timestamp = last_timestamp; + (void)memcpy(last_data_xl, fifo_out_slot[j].sensor_data.raw_data, 6); + last_timestamp_xl = last_timestamp; + } + if (sensor_type == ST_FIFO_GYROSCOPE) + { + uint32_t last_timestamp; + + if (bdr_chg_gy_flag == 1u) + { + last_timestamp = last_timestamp_gy + dtime_gy_old; + } + else + { + last_timestamp = timestamp - 2u * dtime_gy; + } + + fifo_out_slot[j].timestamp = last_timestamp; + (void)memcpy(last_data_gy, fifo_out_slot[j].sensor_data.raw_data, 6); + last_timestamp_gy = last_timestamp; + } + + j++; + + } + else if (compression_type == ST_FIFO_COMPRESSION_2X) + { + + int16_t diff[6]; + get_diff_2x(diff, &fifo_raw_slot[i].fifo_data_out[1]); + + fifo_out_slot[j].sensor_tag = sensor_type; + + if (sensor_type == ST_FIFO_ACCELEROMETER) + { + fifo_out_slot[j].sensor_data.data[0] = last_data_xl[0] + diff[0]; + fifo_out_slot[j].sensor_data.data[1] = last_data_xl[1] + diff[1]; + fifo_out_slot[j].sensor_data.data[2] = last_data_xl[2] + diff[2]; + fifo_out_slot[j].timestamp = timestamp - 2u * dtime_xl; + (void)memcpy(last_data_xl, fifo_out_slot[j].sensor_data.raw_data, 6); + } + + if (sensor_type == ST_FIFO_GYROSCOPE) + { + fifo_out_slot[j].sensor_data.data[0] = last_data_gy[0] + diff[0]; + fifo_out_slot[j].sensor_data.data[1] = last_data_gy[1] + diff[1]; + fifo_out_slot[j].sensor_data.data[2] = last_data_gy[2] + diff[2]; + fifo_out_slot[j].timestamp = timestamp - 2u * dtime_gy; + (void)memcpy(last_data_gy, fifo_out_slot[j].sensor_data.raw_data, 6); + } + + j++; + + fifo_out_slot[j].sensor_tag = sensor_type; + + if (sensor_type == ST_FIFO_ACCELEROMETER) + { + uint32_t last_timestamp = timestamp - dtime_xl; + fifo_out_slot[j].sensor_data.data[0] = last_data_xl[0] + diff[3]; + fifo_out_slot[j].sensor_data.data[1] = last_data_xl[1] + diff[4]; + fifo_out_slot[j].sensor_data.data[2] = last_data_xl[2] + diff[5]; + fifo_out_slot[j].timestamp = last_timestamp; + (void)memcpy(last_data_xl, fifo_out_slot[j].sensor_data.raw_data, 6); + last_timestamp_xl = last_timestamp; + } + + if (sensor_type == ST_FIFO_GYROSCOPE) + { + uint32_t last_timestamp = timestamp - dtime_gy; + fifo_out_slot[j].sensor_data.data[0] = last_data_gy[0] + diff[3]; + fifo_out_slot[j].sensor_data.data[1] = last_data_gy[1] + diff[4]; + fifo_out_slot[j].sensor_data.data[2] = last_data_gy[2] + diff[5]; + fifo_out_slot[j].timestamp = last_timestamp; + (void)memcpy(last_data_gy, fifo_out_slot[j].sensor_data.raw_data, 6); + last_timestamp_gy = last_timestamp; + } + + j++; + + } + else /* compression_type == ST_FIFO_COMPRESSION_3X */ + { + int16_t diff[9]; + get_diff_3x(diff, &fifo_raw_slot[i].fifo_data_out[1]); + + fifo_out_slot[j].sensor_tag = sensor_type; + + if (sensor_type == ST_FIFO_ACCELEROMETER) + { + fifo_out_slot[j].sensor_data.data[0] = last_data_xl[0] + diff[0]; + fifo_out_slot[j].sensor_data.data[1] = last_data_xl[1] + diff[1]; + fifo_out_slot[j].sensor_data.data[2] = last_data_xl[2] + diff[2]; + fifo_out_slot[j].timestamp = timestamp - 2u * dtime_xl; + (void)memcpy(last_data_xl, fifo_out_slot[j].sensor_data.raw_data, 6); + } + + if (sensor_type == ST_FIFO_GYROSCOPE) + { + fifo_out_slot[j].sensor_data.data[0] = last_data_gy[0] + diff[0]; + fifo_out_slot[j].sensor_data.data[1] = last_data_gy[1] + diff[1]; + fifo_out_slot[j].sensor_data.data[2] = last_data_gy[2] + diff[2]; + fifo_out_slot[j].timestamp = timestamp - 2u * dtime_gy; + (void)memcpy(last_data_gy, fifo_out_slot[j].sensor_data.raw_data, 6); + } + + j++; + + fifo_out_slot[j].sensor_tag = sensor_type; + + if (sensor_type == ST_FIFO_ACCELEROMETER) + { + fifo_out_slot[j].sensor_data.data[0] = last_data_xl[0] + diff[3]; + fifo_out_slot[j].sensor_data.data[1] = last_data_xl[1] + diff[4]; + fifo_out_slot[j].sensor_data.data[2] = last_data_xl[2] + diff[5]; + fifo_out_slot[j].timestamp = timestamp - dtime_xl; + (void)memcpy(last_data_xl, fifo_out_slot[j].sensor_data.raw_data, 6); + } + + if (sensor_type == ST_FIFO_GYROSCOPE) + { + fifo_out_slot[j].sensor_data.data[0] = last_data_gy[0] + diff[3]; + fifo_out_slot[j].sensor_data.data[1] = last_data_gy[1] + diff[4]; + fifo_out_slot[j].sensor_data.data[2] = last_data_gy[2] + diff[5]; + fifo_out_slot[j].timestamp = timestamp - dtime_gy; + (void)memcpy(last_data_gy, fifo_out_slot[j].sensor_data.raw_data, 6); + } + + j++; + + fifo_out_slot[j].timestamp = timestamp; + fifo_out_slot[j].sensor_tag = sensor_type; + + if (sensor_type == ST_FIFO_ACCELEROMETER) + { + fifo_out_slot[j].sensor_data.data[0] = last_data_xl[0] + diff[6]; + fifo_out_slot[j].sensor_data.data[1] = last_data_xl[1] + diff[7]; + fifo_out_slot[j].sensor_data.data[2] = last_data_xl[2] + diff[8]; + (void)memcpy(last_data_xl, fifo_out_slot[j].sensor_data.raw_data, 6); + last_timestamp_xl = timestamp; + } + + if (sensor_type == ST_FIFO_GYROSCOPE) + { + fifo_out_slot[j].sensor_data.data[0] = last_data_gy[0] + diff[6]; + fifo_out_slot[j].sensor_data.data[1] = last_data_gy[1] + diff[7]; + fifo_out_slot[j].sensor_data.data[2] = last_data_gy[2] + diff[8]; + (void)memcpy(last_data_gy, fifo_out_slot[j].sensor_data.raw_data, 6); + last_timestamp_gy = timestamp; + } + + j++; + } + + *out_slot_size = j; + } + + tag_counter_old = tag_counter; + } + + return ST_FIFO_OK; +} + +/** + * @brief Sort FIFO stream from older to newer timestamp. + * + * @param fifo_out_slot decoded output stream to sort.(ptr) + * @param out_slot_size decoded stream size. + * + */ +void st_fifo_sort(st_fifo_out_slot *fifo_out_slot, uint16_t out_slot_size) +{ + int32_t i; + int32_t j; + st_fifo_out_slot temp; + + for (i = 1; i < (int32_t)out_slot_size; i++) + { + (void)memcpy(&temp, &fifo_out_slot[i], sizeof(st_fifo_out_slot)); + + j = i - 1; + + while (j >= 0 && fifo_out_slot[j].timestamp > temp.timestamp) + { + (void)memcpy(&fifo_out_slot[j + 1], &fifo_out_slot[j], + sizeof(st_fifo_out_slot)); + j--; + } + + (void)memcpy(&fifo_out_slot[j + 1], &temp, sizeof(st_fifo_out_slot)); + } + + return; +} + +/** + * @brief Return the number of a sensor tag occurrencies in a + * decoded FIFO stream. + * + * @param fifo_out_slot decoded output stream.(ptr) + * @param out_slot_size decoded stream size. + * @param sensor_type sensor type for the number of occurrencies count. + * + * @retval uint16_t the number of a sensor tag occurrencies in a + * decoded FIFO stream. + * + */ +uint16_t st_fifo_get_sensor_occurrence(st_fifo_out_slot *fifo_out_slot, + uint16_t out_slot_size, st_fifo_sensor_type sensor_type) +{ + uint16_t occurrence = 0; + + for (uint16_t i = 0; i < out_slot_size; i++) + { + if (fifo_out_slot[i].sensor_tag == sensor_type) + { + occurrence++; + } + } + + return occurrence; +} + +/** + * @brief This function extracts all the data of a specific sensor + * from a decoded FIFO stream. + * + * @param sensor_out_slot data of a specific sensor.(ptr) + * @param fifo_out_slot decoded output stream.(ptr) + * @param out_slot_size decoded stream size. + * @param sensor_type sensor type for the number of occurrencies count. + * + */ +void st_fifo_extract_sensor(st_fifo_out_slot *sensor_out_slot, + st_fifo_out_slot *fifo_out_slot, uint16_t out_slot_size, + st_fifo_sensor_type sensor_type) +{ + uint16_t temp_i = 0; + + for (uint16_t i = 0; i < out_slot_size; i++) + { + if (fifo_out_slot[i].sensor_tag == sensor_type) + { + (void)memcpy(&sensor_out_slot[temp_i], &fifo_out_slot[i], + sizeof(st_fifo_out_slot)); + temp_i++; + } + } +} + +/** + * @} + * + */ + +/** + * @defgroup FIFO private functions + * @brief This section provide a set of private functions + * used by the public APIs. + * @{ + * + */ + +/** + * @brief This function indicate if a raw tag is valid or not. + * + * @param tag tag to be analyzed. + * + * @retval uint8_t valid (1) or invalid (0) tag. + * + */ +static uint8_t is_tag_valid(uint8_t tag) +{ + if (tag > device[fifo_ver].tag_valid_limit) + { + return 0; + } + else + { + return 1; + } +} + +/** + * @brief This function convert a raw tag in a sensor type. + * + * @param tag tag to be analyzed. + * + * @retval st_fifo_sensor_type sensor type. + * + */ +static st_fifo_sensor_type get_sensor_type(uint8_t tag) +{ + st_fifo_sensor_type type; + + switch (tag) + { + case TAG_GY: + type = ST_FIFO_GYROSCOPE; + break; + case TAG_XL: + type = ST_FIFO_ACCELEROMETER; + break; + case TAG_TEMP: + type = ST_FIFO_TEMPERATURE; + break; + case TAG_EXT_SENS_0: + type = ST_FIFO_EXT_SENSOR0; + break; + case TAG_EXT_SENS_1: + type = ST_FIFO_EXT_SENSOR1; + break; + case TAG_EXT_SENS_2: + type = ST_FIFO_EXT_SENSOR2; + break; + case TAG_EXT_SENS_3: + type = ST_FIFO_EXT_SENSOR3; + break; + case TAG_STEP_COUNTER: + type = ST_FIFO_STEP_COUNTER; + break; + case TAG_XL_UNCOMPRESSED_T_2: + type = ST_FIFO_ACCELEROMETER; + break; + case TAG_XL_UNCOMPRESSED_T_1: + type = ST_FIFO_ACCELEROMETER; + break; + case TAG_XL_COMPRESSED_2X: + type = ST_FIFO_ACCELEROMETER; + break; + case TAG_XL_COMPRESSED_3X: + type = ST_FIFO_ACCELEROMETER; + break; + case TAG_GY_UNCOMPRESSED_T_2: + type = ST_FIFO_GYROSCOPE; + break; + case TAG_GY_UNCOMPRESSED_T_1: + type = ST_FIFO_GYROSCOPE; + break; + case TAG_GY_COMPRESSED_2X: + type = ST_FIFO_GYROSCOPE; + break; + case TAG_GY_COMPRESSED_3X: + type = ST_FIFO_GYROSCOPE; + break; + case TAG_GAME_RV: + type = ST_FIFO_6X_GAME_RV; + break; + case TAG_GEOM_RV: + type = ST_FIFO_6X_GEOM_RV; + break; + case TAG_NORM_RV: + type = ST_FIFO_9X_RV; + break; + case TAG_GYRO_BIAS: + type = ST_FIFO_GYRO_BIAS; + break; + case TAG_GRAVITIY: + type = ST_FIFO_GRAVITY; + break; + case TAG_MAG_CAL: + type = ST_FIFO_MAGNETOMETER_CALIB; + break; + case TAG_EXT_SENS_NACK: + type = ST_FIFO_EXT_SENSOR_NACK; + break; + case TAG_MLC_RESULT: + type = ST_FIFO_MLC_RESULT; + break; + case TAG_MLC_FILTER: + type = ST_FIFO_MLC_FILTER; + break; + case TAG_MLC_FEATURE: + type = ST_FIFO_MLC_FEATURE; + break; + case TAG_DUALC_XL: + type = ST_FIFO_DUALC_ACCELEROMETER; + break; + case TAG_EIS_GY: + type = ST_FIFO_EIS_GYROSCOPE; + break; + default: + type = ST_FIFO_NONE; + break; + } + + return type; +} + +/** + * @brief This function convert a raw tag in a type of compression. + * + * @param tag tag to be analyzed. + * + * @retval st_fifo_compression_type compression type. + * + */ +static st_fifo_compression_type get_compression_type(uint8_t tag) +{ + st_fifo_compression_type type; + + switch (tag) + { + case TAG_XL_UNCOMPRESSED_T_2: + type = ST_FIFO_COMPRESSION_NC_T_2; + break; + case TAG_XL_UNCOMPRESSED_T_1: + type = ST_FIFO_COMPRESSION_NC_T_1; + break; + case TAG_XL_COMPRESSED_2X: + type = ST_FIFO_COMPRESSION_2X; + break; + case TAG_XL_COMPRESSED_3X: + type = ST_FIFO_COMPRESSION_3X; + break; + case TAG_GY_UNCOMPRESSED_T_2: + type = ST_FIFO_COMPRESSION_NC_T_2; + break; + case TAG_GY_UNCOMPRESSED_T_1: + type = ST_FIFO_COMPRESSION_NC_T_1; + break; + case TAG_GY_COMPRESSED_2X: + type = ST_FIFO_COMPRESSION_2X; + break; + case TAG_GY_COMPRESSED_3X: + type = ST_FIFO_COMPRESSION_3X; + break; + default: + type = ST_FIFO_COMPRESSION_NC; + break; + } + + return type; +} + +/** + * @brief This function get the index of the nearest BDR. + * + * @param bdr array with the BDR values.(ptr) + * @param n input value to be considered + * + * @retval uint8_t index of the nearest BDR. + * + */ +static uint8_t bdr_get_index(const float *bdr, float n) +{ + float diff[16], min = FLT_MAX; + uint8_t idx = 0; + + for (uint8_t i = 0; i < 16u; i++) + { + diff[i] = fabsf(bdr[i] - n); + } + + for (uint8_t i = 0; i < 16u; i++) + { + if (diff[i] < min) + { + min = diff[i]; + idx = i; + } + } + + return idx; +} + +/** + * @brief This function check the parity of a byte. + * + * @param x byte to be analyzed. + * + * @retval uint8_t the byte has even parity (1) or not (0). + * + */ +static uint8_t has_even_parity(uint8_t x) +{ + uint8_t count = 0x00, b = 0x01; + + for (uint8_t i = 0; i < 8u; i++) + { + if ((x & (b << i)) != 0x00u) + { + count++; + } + } + + if ((count & 0x01u) == 0x01u) + { + return 0; + } + + return 1; +} + +/** + * @brief Convert raw data FIFO into compressed data (2x). + * + * @param diff[6] compressed data (2x). + * @param input[6] FIFO raw word without tag. + * + */ +static void get_diff_2x(int16_t diff[6], uint8_t input[6]) +{ + for (uint8_t i = 0; i < 6u; i++) + { + diff[i] = input[i] < 128u ? (int16_t)input[i] : (int16_t)input[i] - 256; + } +} + +/** + * @brief Convert raw data FIFO into compressed data (3x). + * + * @param diff[6] compressed data (3x). + * @param input[6] FIFO raw word without tag. + * + */ +static void get_diff_3x(int16_t diff[9], uint8_t input[6]) +{ + uint16_t decode_tmp; + + for (uint8_t i = 0; i < 3u; i++) + { + + (void)memcpy(&decode_tmp, &input[2u * i], 2); + + for (uint8_t j = 0; j < 3u; j++) + { + uint16_t utmp = (decode_tmp & ((uint16_t)0x1Fu << (5u * j))) >> (5u * j); + int16_t tmp = (int16_t)utmp; + diff[j + 3u * i] = tmp < 16 ? tmp : (tmp - 32); + } + } +} + +/** + * @} + * + */ + +/** + * @} + * + */ diff --git a/sensor/stmemsc/_resources/FIFO_Utility_Tool/st_fifo.h b/sensor/stmemsc/_resources/FIFO_Utility_Tool/st_fifo.h new file mode 100644 index 0000000000000000000000000000000000000000..10c534d6ef7b781d8117bd4b1e2fd7e756913076 --- /dev/null +++ b/sensor/stmemsc/_resources/FIFO_Utility_Tool/st_fifo.h @@ -0,0 +1,173 @@ +/* + ****************************************************************************** + * @file st_fifo.h + * @author Sensor Solutions Software Team + * @brief Utility for managing FIFO data decoding and decompression. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2022 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef ST_FIFO_H +#define ST_FIFO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include + +/** @addtogroup FIFO utility + * @{ + * + */ + +/** @defgroup FIFO public definitions + * @{ + * + */ + +typedef enum +{ + ST_FIFO_OK, + ST_FIFO_ERR +} st_fifo_status; + +typedef enum +{ + ST_FIFO_GYROSCOPE, + ST_FIFO_ACCELEROMETER, + ST_FIFO_TEMPERATURE, + ST_FIFO_EXT_SENSOR0, + ST_FIFO_EXT_SENSOR1, + ST_FIFO_EXT_SENSOR2, + ST_FIFO_EXT_SENSOR3, + ST_FIFO_STEP_COUNTER, + ST_FIFO_6X_GAME_RV, + ST_FIFO_6X_GEOM_RV, + ST_FIFO_9X_RV, + ST_FIFO_GYRO_BIAS, + ST_FIFO_GRAVITY, + ST_FIFO_MAGNETOMETER_CALIB, + ST_FIFO_EXT_SENSOR_NACK, + ST_FIFO_MLC_RESULT, + ST_FIFO_MLC_FILTER, + ST_FIFO_MLC_FEATURE, + ST_FIFO_DUALC_ACCELEROMETER, + ST_FIFO_EIS_GYROSCOPE, + ST_FIFO_NONE +} st_fifo_sensor_type; + +typedef struct +{ + uint8_t fifo_data_out[7]; /* registers from mems (78h -> 7Dh) */ +} st_fifo_raw_slot; + +typedef struct +{ + uint32_t timestamp; + st_fifo_sensor_type sensor_tag; + union + { + uint8_t raw_data[6]; /* bytes */ + int16_t data[3]; /* 3-axis mems */ + struct + { + int16_t x; + int16_t y; + int16_t z; + }; /* 3-axis mems */ + struct + { + int16_t temp; + }; /* temperature sensor */ + struct + { + uint16_t steps; + uint8_t steps_t[4]; + }; /* step counter */ + struct + { + uint16_t qx; + uint16_t qy; + uint16_t qz; + }; /* quaternion */ + struct + { + uint8_t nack; + }; /* ext sensor nack index */ + struct + { + uint8_t mlc_res; + uint8_t mlc_idx; + uint8_t mlc_t[4]; + }; /* mlc result */ + struct + { + uint16_t mlc_value; + uint16_t mlc_id; + uint16_t reserved; + }; /* mlc filter / feature */ + } sensor_data; +} st_fifo_out_slot; + +typedef enum +{ + ST_FIFO_LSM6DSR, + ST_FIFO_LSM6DSRX, + ST_FIFO_ASM330LHH, + ST_FIFO_ASM330LHHX, + ST_FIFO_ISM330DHCX, + ST_FIFO_LSM6DSO, + ST_FIFO_LSM6DSOX, + ST_FIFO_LSM6DSO32, + ST_FIFO_LSM6DSO32X, + ST_FIFO_LSM6DSV, + ST_FIFO_LSM6DSV16X, + ST_FIFO_LSM6DSV32X, +} st_fifo_device; + +typedef struct +{ + st_fifo_device device; /* device to select */ + float bdr_xl; /* accelerometer batch data rate in Hz */ + float bdr_gy; /* gyroscope batch data rate in Hz */ + float bdr_vsens; /* virtual sensor batch data rate in Hz */ +} st_fifo_conf; + +/** + * @} + * + */ + +st_fifo_status st_fifo_init(st_fifo_conf *conf); +st_fifo_status st_fifo_decode(st_fifo_out_slot *fifo_out_slot, + st_fifo_raw_slot *fifo_raw_slot, uint16_t *out_slot_size, uint16_t stream_size); +void st_fifo_sort(st_fifo_out_slot *fifo_out_slot, uint16_t out_slot_size); +uint16_t st_fifo_get_sensor_occurrence(st_fifo_out_slot *fifo_out_slot, + uint16_t out_slot_size, st_fifo_sensor_type sensor_type); +void st_fifo_extract_sensor(st_fifo_out_slot *sensor_out_slot, + st_fifo_out_slot *fifo_out_slot, uint16_t out_slot_size, + st_fifo_sensor_type sensor_type); + +#ifdef __cplusplus +} +#endif + +#endif /* ST_FIFO_H */ + +/** + * @} + * + */ diff --git a/sensor/stmemsc/_resources/FIFO_decompression_utility/fifo_utility.c b/sensor/stmemsc/_resources/FIFO_decompression_utility/fifo_utility.c deleted file mode 100644 index bfb70e8f050cb32bd0a1ec5cf1e8a3c4236c375a..0000000000000000000000000000000000000000 --- a/sensor/stmemsc/_resources/FIFO_decompression_utility/fifo_utility.c +++ /dev/null @@ -1,936 +0,0 @@ -/* - ****************************************************************************** - * @file fifo_utility.c - * @author Sensor Solutions Software Team - * @brief Utility for managing data compression in smart FIFO. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "fifo_utility.h" - -/** - * @defgroup FIFO utility - * @brief This file provides a set of functions needed to manage data - * compression in smart FIFO. - * @{ - * - */ - -/* Private constants --------------------------------------------------------*/ -#define ODR_XL_MASK (0x0FU) -#define ODR_XL_SHIFT (0x00U) -#define BDR_XL_MASK (0x0FU) -#define BDR_XL_SHIFT (0x00U) - -#define ODR_GY_MASK (0xF0U) -#define ODR_GY_SHIFT (0x04U) -#define BDR_GY_MASK (0xF0U) -#define BDR_GY_SHIFT (0x04U) - -#define BDR_VSENS_MASK (0x0FU) -#define BDR_VSENS_SHIFT (0x00U) - -#define TAG_COUNTER_MASK (0x06U) -#define TAG_SENSOR_MASK (0xF8U) -#define TAG_COUNTER_SHIFT (0x01U) -#define TAG_SENSOR_SHIFT (0x03U) - -#define TAG_GY (0x01U) -#define TAG_XL (0x02U) -#define TAG_TEMP (0x03U) -#define TAG_TS (0x04U) -#define TAG_ODRCHG (0x05U) -#define TAG_XL_UNCOMPRESSED_T_2 (0x06U) -#define TAG_XL_UNCOMPRESSED_T_1 (0x07U) -#define TAG_XL_COMPRESSED_2X (0x08U) -#define TAG_XL_COMPRESSED_3X (0x09U) -#define TAG_GY_UNCOMPRESSED_T_2 (0x0AU) -#define TAG_GY_UNCOMPRESSED_T_1 (0x0BU) -#define TAG_GY_COMPRESSED_2X (0x0CU) -#define TAG_GY_COMPRESSED_3X (0x0DU) -#define TAG_EXT_SENS_0 (0x0EU) -#define TAG_EXT_SENS_1 (0x0FU) -#define TAG_EXT_SENS_2 (0x10U) -#define TAG_EXT_SENS_3 (0x11U) -#define TAG_STEP_COUNTER (0x12U) -#define TAG_GAME_RV (0x13U) -#define TAG_GEOM_RV (0x14U) -#define TAG_NORM_RV (0x15U) -#define TAG_GYRO_BIAS (0x16U) -#define TAG_GRAVITIY (0x17U) -#define TAG_MAG_CAL (0x18U) -#define TAG_EXT_SENS_NACK (0x19U) - -#define TAG_VALID_LIMIT (0x19U) - -#define TIMESTAMP_FREQ (40000U) - -/* Private typedef -----------------------------------------------------------*/ -typedef enum { - ST_FIFO_COMPRESSION_NC, - ST_FIFO_COMPRESSION_NC_T_1, - ST_FIFO_COMPRESSION_NC_T_2, - ST_FIFO_COMPRESSION_2X, - ST_FIFO_COMPRESSION_3X -} st_fifo_compression_type; - -/* Private functions ---------------------------------------------------------*/ -/* Functions declare in this section are defined at the end of this file. */ -static uint8_t has_even_parity(uint8_t x); -static st_fifo_sensor_type get_sensor_type(uint8_t tag); -static st_fifo_compression_type get_compression_type(uint8_t tag); -static uint8_t is_tag_valid(uint8_t tag); -static void get_diff_2x(int16_t diff[6], uint8_t input[6]); -static void get_diff_3x(int16_t diff[9], uint8_t input[6]); -static void byte_cpy(uint8_t *destination, uint8_t *source, - uint32_t len); - -/* Private variables ---------------------------------------------------------*/ -static uint8_t tag_counter_old = 0x00U; -static float_t bdr_xl = 0.0f; -static float_t bdr_gy = 0.0f; -static float_t bdr_vsens = 0.0f; -static float_t bdr_xl_old = 0.0f; -static float_t bdr_gy_old = 0.0f; -static float_t bdr_max = 0.0f; -static uint32_t timestamp = 0; -static uint32_t last_timestamp_xl = 0; -static uint32_t last_timestamp_gy = 0; -static uint8_t bdr_chg_xl_flag = 0; -static uint8_t bdr_chg_gy_flag = 0; -static int16_t last_data_xl[3] = {0}; -static int16_t last_data_gy[3] = {0}; - -/** - * @defgroup FIFO_pubblic_functions - * @brief This section provide a set of useful APIs for managing data - * compression in smart FIFO. - * @{ - * - */ - -/** - * @brief Initialize the FIFO utility library. - * - * @param bdr_xl_in batch data rate for accelerometer sensor in Hz, - * pass 0 Hz if odrchg_en is set to 1 or timestamp - * is stored in FIFO. - * @param bdr_gy_in batch data rate for gyro sensor in Hz, - * pass 0 Hz if odrchg_en is set to 1 or timestamp - * is stored in FIFO. - * @param bdr_vsens_in batch data rate for virtual sensor in Hz, - * pass 0 Hz if odrchg_en is set to 1 or timestamp - * is stored in FIFO. - * - * @retval st_fifo_status ST_FIFO_OK / ST_FIFO_ERR - * - */ -st_fifo_status st_fifo_init(float_t bdr_xl_in, - float_t bdr_gy_in, - float_t bdr_vsens_in) -{ - uint32_t i; - st_fifo_status ret = ST_FIFO_ERR; - - if ((bdr_xl_in < 0.0f) || (bdr_gy_in < 0.0f) || - (bdr_vsens_in < 0.0f)) { - ret = ST_FIFO_ERR; - } - - else { - tag_counter_old = 0x00U; - bdr_xl = bdr_xl_in; - bdr_gy = bdr_gy_in; - bdr_vsens = bdr_vsens_in; - bdr_xl_old = bdr_xl_in; - bdr_gy_old = bdr_gy_in; - bdr_max = ( ( bdr_xl > bdr_gy ) ? bdr_xl : bdr_gy ); - bdr_max = ( ( bdr_max > bdr_vsens ) ? bdr_max : bdr_vsens ); - timestamp = 0; - bdr_chg_xl_flag = 0; - bdr_chg_gy_flag = 0; - last_timestamp_xl = 0; - last_timestamp_gy = 0; - - for (i = 0; i < 3U; i++) { - last_data_xl[i] = 0; - last_data_gy[i] = 0; - ret = ST_FIFO_OK; - } - } - - return ret; -} - -/** - * @brief Decompress a compressed raw FIFO stream. - * - * @param fifo_out_slot decoded output stream.(ptr) - * @param fifo_raw_slot compressed raw input data stream.(ptr) - * @param out_slot_size decoded stream size.(ptr) - * @param stream_size raw input stream size. - * - * @retval st_fifo_status ST_FIFO_OK / ST_FIFO_ERR - * - */ -st_fifo_status st_fifo_decompress(st_fifo_out_slot *fifo_out_slot, - st_fifo_raw_slot *fifo_raw_slot, - uint16_t *out_slot_size, - uint16_t stream_size) -{ - uint16_t j = 0; - int16_t data[3]; - uint8_t tag; - uint8_t tag_counter; - uint8_t diff_tag_counter; - uint8_t bdr_acc_cfg; - uint8_t bdr_gyr_cfg; - uint8_t bdr_vsens_cfg; - uint32_t last_timestamp; - int16_t diff[9]; - float_t bdr_acc_vect[] = { 0, 13, 26, 52, 104, - 208, 416, 833, 1666, 3333, - 6666, 1.625, 0, 0, 0, - 0 - }; - float_t bdr_gyr_vect[] = { 0, 13, 26, 52, 104, 208, 416, - 833, 1666, 3333, 6666, 0, 0, 0, - 0, 0 - }; - float_t bdr_vsens_vect[] = { 0, 13, 26, 52, 104, 208, 416, - 0, 0, 0, 0, 1.625, 0, 0, - 0, 0 - }; - - for (uint16_t i = 0; i < stream_size; i++) { - tag = (fifo_raw_slot[i].fifo_data_out[0] & TAG_SENSOR_MASK); - tag = tag >> TAG_SENSOR_SHIFT; - tag_counter = (fifo_raw_slot[i].fifo_data_out[0] & TAG_COUNTER_MASK); - tag_counter = tag_counter >> TAG_COUNTER_SHIFT; - - if ((has_even_parity(fifo_raw_slot[i].fifo_data_out[0]) == 0U) || - (is_tag_valid(tag) == 0U)) { - return ST_FIFO_ERR; - } - - if ((tag_counter != (tag_counter_old)) && (bdr_max != 0.0f)) { - if (tag_counter < tag_counter_old) { - diff_tag_counter = tag_counter + 4U - tag_counter_old; - } - - else { - diff_tag_counter = tag_counter - tag_counter_old; - } - - timestamp += (TIMESTAMP_FREQ / (uint32_t)bdr_max) * diff_tag_counter; - } - - if (tag == TAG_ODRCHG) { - bdr_acc_cfg = (fifo_raw_slot[i].fifo_data_out[6] & BDR_XL_MASK); - bdr_acc_cfg = bdr_acc_cfg >> BDR_XL_SHIFT; - bdr_gyr_cfg = (fifo_raw_slot[i].fifo_data_out[6] & BDR_GY_MASK); - bdr_gyr_cfg = bdr_gyr_cfg >> BDR_GY_SHIFT; - bdr_vsens_cfg = (fifo_raw_slot[i].fifo_data_out[3] & BDR_VSENS_MASK); - bdr_vsens_cfg = bdr_vsens_cfg >> BDR_VSENS_SHIFT; - bdr_xl_old = bdr_xl; - bdr_gy_old = bdr_gy; - bdr_xl = bdr_acc_vect[bdr_acc_cfg]; - bdr_gy = bdr_gyr_vect[bdr_gyr_cfg]; - bdr_vsens = bdr_vsens_vect[bdr_vsens_cfg]; - bdr_max = ((bdr_xl > bdr_gy) ? bdr_xl : bdr_gy); - bdr_max = ((bdr_max > bdr_vsens) ? bdr_max : bdr_vsens); - bdr_chg_xl_flag = 1; - bdr_chg_gy_flag = 1; - } - - else if (tag == TAG_TS) { - byte_cpy( (uint8_t *)×tamp, &fifo_raw_slot[i].fifo_data_out[1], - 4); - } - - else { - st_fifo_compression_type compression_type = get_compression_type(tag); - st_fifo_sensor_type sensor_type = get_sensor_type(tag); - - switch (compression_type) { - case ST_FIFO_COMPRESSION_NC: - if (tag == TAG_STEP_COUNTER) { - byte_cpy((uint8_t *)&fifo_out_slot[j].timestamp, - &fifo_raw_slot[i].fifo_data_out[3], 4); - } - - else { - fifo_out_slot[j].timestamp = timestamp; - } - - fifo_out_slot[j].sensor_tag = sensor_type; - byte_cpy(fifo_out_slot[j].raw_data, - &fifo_raw_slot[i].fifo_data_out[1], 6); - - if (sensor_type == ST_FIFO_ACCELEROMETER) { - byte_cpy((uint8_t *)last_data_xl, fifo_out_slot[j].raw_data, 6); - last_timestamp_xl = timestamp; - bdr_chg_xl_flag = 0; - } - - if (sensor_type == ST_FIFO_GYROSCOPE) { - byte_cpy((uint8_t *)last_data_gy, fifo_out_slot[j].raw_data, 6); - last_timestamp_gy = timestamp; - bdr_chg_gy_flag = 0; - } - - j++; - break; - - case ST_FIFO_COMPRESSION_NC_T_1: - fifo_out_slot[j].sensor_tag = get_sensor_type(tag); - byte_cpy(fifo_out_slot[j].raw_data, - &fifo_raw_slot[i].fifo_data_out[1], 6); - - if (sensor_type == ST_FIFO_ACCELEROMETER) { - if (bdr_chg_xl_flag != 0U) { - last_timestamp = (last_timestamp_xl + - (TIMESTAMP_FREQ / (uint32_t)bdr_xl_old)); - } - - else { - last_timestamp = ((uint32_t)timestamp - - ((uint32_t)TIMESTAMP_FREQ / (uint32_t)bdr_xl)); - } - - fifo_out_slot[j].timestamp = last_timestamp; - byte_cpy((uint8_t *)last_data_xl, - (uint8_t *) fifo_out_slot[j].raw_data, 6); - last_timestamp_xl = last_timestamp; - } - - if (sensor_type == ST_FIFO_GYROSCOPE) { - if (bdr_chg_gy_flag != 0U) { - last_timestamp = (last_timestamp_gy + - (TIMESTAMP_FREQ / (uint32_t)bdr_gy_old)); - } - - else { - last_timestamp = (timestamp - - (TIMESTAMP_FREQ / (uint32_t)bdr_gy)); - } - - fifo_out_slot[j].timestamp = last_timestamp; - byte_cpy((uint8_t *)last_data_gy, fifo_out_slot[j].raw_data, 6); - last_timestamp_gy = last_timestamp; - } - - j++; - break; - - case ST_FIFO_COMPRESSION_NC_T_2: - fifo_out_slot[j].sensor_tag = get_sensor_type(tag); - byte_cpy(fifo_out_slot[j].raw_data, - &fifo_raw_slot[i].fifo_data_out[1], 6); - - if (sensor_type == ST_FIFO_ACCELEROMETER) { - if (bdr_chg_xl_flag != 0U) { - last_timestamp = (last_timestamp_xl + - (TIMESTAMP_FREQ / (uint32_t)bdr_xl_old)); - } - - else { - last_timestamp = (timestamp - - ((2U * TIMESTAMP_FREQ) / (uint32_t) bdr_xl)); - } - - fifo_out_slot[j].timestamp = last_timestamp; - byte_cpy((uint8_t *)last_data_xl, fifo_out_slot[j].raw_data, 6); - last_timestamp_xl = last_timestamp; - } - - if (sensor_type == ST_FIFO_GYROSCOPE) { - if (bdr_chg_gy_flag != 0U) { - last_timestamp = (last_timestamp_gy + - (TIMESTAMP_FREQ / (uint32_t)bdr_gy_old)); - } - - else { - last_timestamp = (timestamp - - (2U * TIMESTAMP_FREQ / (uint32_t)bdr_gy)); - } - - fifo_out_slot[j].timestamp = last_timestamp; - byte_cpy((uint8_t *)last_data_gy, - (uint8_t *)fifo_out_slot[j].raw_data, 6); - last_timestamp_gy = last_timestamp; - } - - j++; - break; - - case ST_FIFO_COMPRESSION_2X: - get_diff_2x(diff, &fifo_raw_slot[i].fifo_data_out[1]); - fifo_out_slot[j].sensor_tag = sensor_type; - - if (sensor_type == ST_FIFO_ACCELEROMETER) { - data[0] = last_data_xl[0] + diff[0]; - data[1] = last_data_xl[1] + diff[1]; - data[2] = last_data_xl[2] + diff[2]; - byte_cpy(fifo_out_slot[j].raw_data, (uint8_t *)data, 6); - fifo_out_slot[j].timestamp = - (timestamp - (2U * TIMESTAMP_FREQ / (uint32_t)bdr_xl)); - byte_cpy((uint8_t *)last_data_xl, fifo_out_slot[j].raw_data, 6); - } - - if (sensor_type == ST_FIFO_GYROSCOPE) { - data[0] = last_data_gy[0] + diff[0]; - data[1] = last_data_gy[1] + diff[1]; - data[2] = last_data_gy[2] + diff[2]; - byte_cpy(fifo_out_slot[j].raw_data, (uint8_t *)data, 6); - fifo_out_slot[j].timestamp = - (timestamp - (2U * TIMESTAMP_FREQ / (uint32_t)bdr_gy)); - byte_cpy((uint8_t *)last_data_gy, fifo_out_slot[j].raw_data, 6); - } - - j++; - fifo_out_slot[j].sensor_tag = sensor_type; - - if (sensor_type == ST_FIFO_ACCELEROMETER) { - last_timestamp = (timestamp - (TIMESTAMP_FREQ / (uint32_t)bdr_xl)); - data[0] = last_data_xl[0] + diff[3]; - data[1] = last_data_xl[1] + diff[4]; - data[2] = last_data_xl[2] + diff[5]; - byte_cpy(fifo_out_slot[j].raw_data, (uint8_t *)data, 6); - fifo_out_slot[j].timestamp = last_timestamp; - byte_cpy((uint8_t *)last_data_xl, fifo_out_slot[j].raw_data, 6); - last_timestamp_xl = last_timestamp; - } - - if (sensor_type == ST_FIFO_GYROSCOPE) { - last_timestamp = (timestamp - (TIMESTAMP_FREQ / (uint32_t)bdr_gy)); - data[0] = last_data_gy[0] + diff[3]; - data[1] = last_data_gy[1] + diff[4]; - data[2] = last_data_gy[2] + diff[5]; - byte_cpy(fifo_out_slot[j].raw_data, (uint8_t *)data, 6); - fifo_out_slot[j].timestamp = last_timestamp; - byte_cpy((uint8_t *)last_data_gy, fifo_out_slot[j].raw_data, 6); - last_timestamp_gy = last_timestamp; - } - - j++; - break; - - default: //(compression_type == ST_FIFO_COMPRESSION_3X) - get_diff_3x(diff, &fifo_raw_slot[i].fifo_data_out[1]); - fifo_out_slot[j].sensor_tag = sensor_type; - - if (sensor_type == ST_FIFO_ACCELEROMETER) { - data[0] = last_data_xl[0] + diff[0]; - data[1] = last_data_xl[1] + diff[1]; - data[2] = last_data_xl[2] + diff[2]; - byte_cpy(fifo_out_slot[j].raw_data, (uint8_t *)data, 6); - fifo_out_slot[j].timestamp = - (timestamp - (2U * TIMESTAMP_FREQ / (uint32_t)bdr_xl)); - byte_cpy((uint8_t *)last_data_xl, fifo_out_slot[j].raw_data, 6); - } - - if (sensor_type == ST_FIFO_GYROSCOPE) { - data[0] = last_data_gy[0] + diff[0]; - data[1] = last_data_gy[1] + diff[1]; - data[2] = last_data_gy[2] + diff[2]; - byte_cpy(fifo_out_slot[j].raw_data, (uint8_t *)data, 6); - fifo_out_slot[j].timestamp = - (timestamp - (2U * TIMESTAMP_FREQ / (uint32_t)bdr_gy)); - byte_cpy((uint8_t *)last_data_gy, - (uint8_t *)fifo_out_slot[j].raw_data, 6); - } - - j++; - fifo_out_slot[j].sensor_tag = sensor_type; - - if (sensor_type == ST_FIFO_ACCELEROMETER) { - data[0] = last_data_xl[0] + diff[3]; - data[1] = last_data_xl[1] + diff[4]; - data[2] = last_data_xl[2] + diff[5]; - byte_cpy(fifo_out_slot[j].raw_data, (uint8_t *)data, 6); - fifo_out_slot[j].timestamp = - (timestamp - (TIMESTAMP_FREQ / (uint32_t)bdr_xl)); - byte_cpy((uint8_t *)last_data_xl, fifo_out_slot[j].raw_data, 6); - } - - if (sensor_type == ST_FIFO_GYROSCOPE) { - data[0] = last_data_gy[0] + diff[3]; - data[1] = last_data_gy[1] + diff[4]; - data[2] = last_data_gy[2] + diff[5]; - byte_cpy(fifo_out_slot[j].raw_data, (uint8_t *)data, 6); - fifo_out_slot[j].timestamp = - (timestamp - (TIMESTAMP_FREQ / (uint32_t)bdr_gy)); - byte_cpy((uint8_t *)last_data_gy, fifo_out_slot[j].raw_data, 6); - } - - j++; - fifo_out_slot[j].timestamp = timestamp; - fifo_out_slot[j].sensor_tag = sensor_type; - - if (sensor_type == ST_FIFO_ACCELEROMETER) { - data[0] = last_data_xl[0] + diff[6]; - data[1] = last_data_xl[1] + diff[7]; - data[2] = last_data_xl[2] + diff[8]; - byte_cpy(fifo_out_slot[j].raw_data, (uint8_t *)data, 6); - byte_cpy((uint8_t *)last_data_xl, fifo_out_slot[j].raw_data, 6); - last_timestamp_xl = timestamp; - } - - if (sensor_type == ST_FIFO_GYROSCOPE) { - data[0] = last_data_gy[0] + diff[6]; - data[1] = last_data_gy[1] + diff[7]; - data[2] = last_data_gy[2] + diff[8]; - byte_cpy(fifo_out_slot[j].raw_data, (uint8_t *)data, 6); - byte_cpy((uint8_t *)last_data_gy, fifo_out_slot[j].raw_data, 6); - last_timestamp_gy = timestamp; - } - - j++; - break; - } - - *out_slot_size = j; - } - - tag_counter_old = tag_counter; - } - - return ST_FIFO_OK; -} - -/** - * @brief Sort FIFO stream from older to newer timestamp. - * - * @param fifo_out_slot decoded output stream.(ptr) - * @param out_slot_size decoded srteam size. - * - */ -void st_fifo_sort(st_fifo_out_slot *fifo_out_slot, - uint16_t out_slot_size) -{ - int32_t j, i; - st_fifo_out_slot temp; - - for (i = 1; i < (int32_t)out_slot_size; i++) { - byte_cpy((uint8_t *)&temp, (uint8_t *)&fifo_out_slot[i], - sizeof(st_fifo_out_slot)); - j = i - 1; - - while ((j >= 0) && (fifo_out_slot[j].timestamp > temp.timestamp)) { - byte_cpy((uint8_t *)&fifo_out_slot[j + 1], - (uint8_t *)&fifo_out_slot[j], - sizeof(st_fifo_out_slot)); - j--; - } - - byte_cpy((uint8_t *)&fifo_out_slot[j + 1], (uint8_t *)&temp, - sizeof(st_fifo_out_slot)); - } -} - -/** - * @brief Return the number of a sensor tag occurrency in a - * decoded FIFO stream. - * - * @param fifo_out_slot decoded output stream.(ptr) - * @param out_slot_size decoded srteam size. - * @param sensor_type The name of the sensor that is need - * to count occurrences. - * - * @retval uint16_t the number of a sensor tag occurrency in a - * decoded FIFO stream. - * - */ -uint16_t st_fifo_get_sensor_occurrence(st_fifo_out_slot - *fifo_out_slot, - uint16_t out_slot_size, - st_fifo_sensor_type sensor_type) -{ - uint16_t occurrence = 0; - - for (uint16_t i = 0; i < out_slot_size; i++) { - if (fifo_out_slot[i].sensor_tag == sensor_type) { - occurrence++; - } - } - - return occurrence; -} - -/** - * @brief This function extracts all the data of a specific sensor - * from a decoded FIFO stream. - * - * @param sensor_out_slot data of a specific sensor.(ptr) - * @param fifo_out_slot decoded output stream.(ptr) - * @param out_slot_size decoded srteam size. - * @param sensor_type The name of the sensor that is need - * to extract data. - * - */ -void st_fifo_extract_sensor(st_fifo_out_slot *sensor_out_slot, - st_fifo_out_slot *fifo_out_slot, - uint16_t out_slot_size, - st_fifo_sensor_type sensor_type) -{ - uint16_t temp_i = 0; - - for (uint16_t i = 0; i < out_slot_size; i++) { - if (fifo_out_slot[i].sensor_tag == sensor_type) { - byte_cpy((uint8_t *)&sensor_out_slot[temp_i], - (uint8_t *)&fifo_out_slot[i], - sizeof(st_fifo_out_slot)); - temp_i++; - } - } -} - -/** - * @} - * - */ - -/** - * @defgroup FIFO private functions - * @brief This section provide a set of private low-level functions - * used by pubblic APIs. - * @{ - * - */ - -/** - * @brief This function indicate if a raw tag is valid or not. - * - * @param tag tag to be analyzed. - * - * @retval uint8_t valid(1) / invalid(0) tag. - * - */ -static uint8_t is_tag_valid(uint8_t tag) -{ - uint8_t ret; - - if (tag > TAG_VALID_LIMIT) { - ret = 0; - } - - else { - ret = 1; - } - - return ret; -} - -/** - * @brief This function convert a raw tag in a sensor type - * - * @param tag tag to be analyzed. - * - * @retval st_fifo_sensor_type Sensor type. - * - */ -static st_fifo_sensor_type get_sensor_type(uint8_t tag) -{ - st_fifo_sensor_type ret; - - switch (tag) { - case TAG_GY: - ret = ST_FIFO_GYROSCOPE; - break; - - case TAG_XL: - ret = ST_FIFO_ACCELEROMETER; - break; - - case TAG_TEMP: - ret = ST_FIFO_TEMPERATURE; - break; - - case TAG_EXT_SENS_0: - ret = ST_FIFO_EXT_SENSOR0; - break; - - case TAG_EXT_SENS_1: - ret = ST_FIFO_EXT_SENSOR1; - break; - - case TAG_EXT_SENS_2: - ret = ST_FIFO_EXT_SENSOR2; - break; - - case TAG_EXT_SENS_3: - ret = ST_FIFO_EXT_SENSOR3; - break; - - case TAG_STEP_COUNTER: - ret = ST_FIFO_STEP_COUNTER; - break; - - case TAG_XL_UNCOMPRESSED_T_2: - ret = ST_FIFO_ACCELEROMETER; - break; - - case TAG_XL_UNCOMPRESSED_T_1: - ret = ST_FIFO_ACCELEROMETER; - break; - - case TAG_XL_COMPRESSED_2X: - ret = ST_FIFO_ACCELEROMETER; - break; - - case TAG_XL_COMPRESSED_3X: - ret = ST_FIFO_ACCELEROMETER; - break; - - case TAG_GY_UNCOMPRESSED_T_2: - ret = ST_FIFO_GYROSCOPE; - break; - - case TAG_GY_UNCOMPRESSED_T_1: - ret = ST_FIFO_GYROSCOPE; - break; - - case TAG_GY_COMPRESSED_2X: - ret = ST_FIFO_GYROSCOPE; - break; - - case TAG_GY_COMPRESSED_3X: - ret = ST_FIFO_GYROSCOPE; - break; - - case TAG_GAME_RV: - ret = ST_FIFO_6X_GAME_RV; - break; - - case TAG_GEOM_RV: - ret = ST_FIFO_6X_GEOM_RV; - break; - - case TAG_NORM_RV: - ret = ST_FIFO_9X_RV; - break; - - case TAG_GYRO_BIAS: - ret = ST_FIFO_GYRO_BIAS; - break; - - case TAG_GRAVITIY: - ret = ST_FIFO_GRAVITY; - break; - - case TAG_MAG_CAL: - ret = ST_FIFO_MAGNETOMETER_CALIB; - break; - - case TAG_EXT_SENS_NACK: - ret = ST_FIFO_EXT_SENSOR_NACK; - break; - - default: - ret = ST_FIFO_NONE; - break; - } - - return ret; -} - -/** - * @brief This function convert a raw tag in a type of compression - * - * @param tag tag to be analyzed. - * - * @retval st_fifo_compression_type Compression type. - * - */ -static st_fifo_compression_type get_compression_type(uint8_t tag) -{ - st_fifo_compression_type ret; - - switch (tag) { - case TAG_GY: - ret = ST_FIFO_COMPRESSION_NC; - break; - - case TAG_XL: - ret = ST_FIFO_COMPRESSION_NC; - break; - - case TAG_TEMP: - ret = ST_FIFO_COMPRESSION_NC; - break; - - case TAG_EXT_SENS_0: - ret = ST_FIFO_COMPRESSION_NC; - break; - - case TAG_EXT_SENS_1: - ret = ST_FIFO_COMPRESSION_NC; - break; - - case TAG_EXT_SENS_2: - ret = ST_FIFO_COMPRESSION_NC; - break; - - case TAG_EXT_SENS_3: - ret = ST_FIFO_COMPRESSION_NC; - break; - - case TAG_STEP_COUNTER: - ret = ST_FIFO_COMPRESSION_NC; - break; - - case TAG_XL_UNCOMPRESSED_T_2: - ret = ST_FIFO_COMPRESSION_NC_T_2; - break; - - case TAG_XL_UNCOMPRESSED_T_1: - ret = ST_FIFO_COMPRESSION_NC_T_1; - break; - - case TAG_XL_COMPRESSED_2X: - ret = ST_FIFO_COMPRESSION_2X; - break; - - case TAG_XL_COMPRESSED_3X: - ret = ST_FIFO_COMPRESSION_3X; - break; - - case TAG_GY_UNCOMPRESSED_T_2: - ret = ST_FIFO_COMPRESSION_NC_T_2; - break; - - case TAG_GY_UNCOMPRESSED_T_1: - ret = ST_FIFO_COMPRESSION_NC_T_1; - break; - - case TAG_GY_COMPRESSED_2X: - ret = ST_FIFO_COMPRESSION_2X; - break; - - case TAG_GY_COMPRESSED_3X: - ret = ST_FIFO_COMPRESSION_3X; - break; - - default: - ret = ST_FIFO_COMPRESSION_NC; - break; - } - - return ret; -} - -/** - * @brief This function check the parity of a byte. - * - * @param x Byte to be analyzed. - * - * @retval uint8_t Sensor type defined in st_fifo_compression_type. - * - */ -static uint8_t has_even_parity(uint8_t x) -{ - uint8_t count = 0x00, i, b = 0x01; - uint8_t ret = 1; - - for (i = 0U; i < 8U; i++) { - if ( ( x & (b << i) ) != 0x00U) { - count++; - } - } - - if ((count & 0x01U) == 0x01U) { - ret = 0; - } - - return ret; -} - -/** - * @brief Convert raw data FIFO into compressed data (2x). - * - * @param diff[6] Compressed data (2x). - * @param input[6] FIFO raw word without tag. - * - */ -static void get_diff_2x(int16_t diff[6], uint8_t input[6]) -{ - uint8_t i; - - for (i = 0; i < 6U; i++) { - if (input[i] < 128U ) { - diff[i] = (int16_t)input[i]; - } - - else { - diff[i] = ((int16_t)input[i] - 256); - } - } -} - -/** - * @brief Convert raw data FIFO into compressed data (3x). - * - * @param diff[6] Compressed data (3x). - * @param input[6] fifo raw word without tag. - * - */ -static void get_diff_3x(int16_t diff[9], uint8_t input[6]) -{ - uint16_t decode_temp; - uint16_t dummy; - - for (uint8_t i = 0; i < 3U; i++) { - byte_cpy((uint8_t *)&decode_temp, &input[2U * i], 2); - - for (uint8_t j = 0; j < 3U; j++) { - dummy = decode_temp & ( (uint16_t)0x1FU << (5U * j) ); - dummy = dummy >> (5U * j); - - if (dummy >= 16U) { - dummy -= 32U; - } - - diff[j + (3U * i)] = (int16_t)dummy; - } - } -} - -/** - * @brief Copy source buffer in destination buffer. - * - * @param destination Destination buffer.(ptr) - * @param source Source buffer.(ptr) - * - */ -static void byte_cpy(uint8_t *destination, uint8_t *source, - uint32_t len) -{ - uint32_t i; - - for ( i = 0; i < len; i++ ) { - destination[i] = source[i]; - } -} - -/** - * @} - * - */ - -/** - * @} - * - */ \ No newline at end of file diff --git a/sensor/stmemsc/_resources/FIFO_decompression_utility/fifo_utility.h b/sensor/stmemsc/_resources/FIFO_decompression_utility/fifo_utility.h deleted file mode 100644 index 7fda6af29de7dd15def0967ec952ce53f298d345..0000000000000000000000000000000000000000 --- a/sensor/stmemsc/_resources/FIFO_decompression_utility/fifo_utility.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - ****************************************************************************** - * @file fifo_utility.h - * @author Sensor Solutions Software Team - * @brief This file contains all the functions prototypes for the - * fifo_utility.c. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef ST_FIFO_H -#define ST_FIFO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include -#include - -/** @addtogroup FIFO utility - * @{ - * - */ - -/** @defgroup FIFO_pubblic_definitions - * @{ - * - */ - -typedef enum { - ST_FIFO_OK = 0, - ST_FIFO_ERR -} st_fifo_status; - -typedef enum { - ST_FIFO_GYROSCOPE, - ST_FIFO_ACCELEROMETER, - ST_FIFO_TEMPERATURE, - ST_FIFO_EXT_SENSOR0, - ST_FIFO_EXT_SENSOR1, - ST_FIFO_EXT_SENSOR2, - ST_FIFO_EXT_SENSOR3, - ST_FIFO_STEP_COUNTER, - ST_FIFO_6X_GAME_RV, - ST_FIFO_6X_GEOM_RV, - ST_FIFO_9X_RV, - ST_FIFO_GYRO_BIAS, - ST_FIFO_GRAVITY, - ST_FIFO_MAGNETOMETER_CALIB, - ST_FIFO_EXT_SENSOR_NACK, - ST_FIFO_NONE -} st_fifo_sensor_type; - -typedef struct { - uint8_t fifo_data_out[7]; /* output fifo registers */ -} st_fifo_raw_slot; - -typedef struct { - uint32_t timestamp; - st_fifo_sensor_type sensor_tag; - uint8_t raw_data[6]; -} st_fifo_out_slot; - -/** - * @defgroup axisXbitXX_t - * @brief This union is useful to represent different sensors data type. - * This union are not need by the driver. - * - * REMOVING the union you are compliant with: - * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " - * - * @{ - * - */ -typedef union { - int16_t data[3]; /* 3 axes mems */ - int16_t temp; /* temperature sensor */ - uint16_t steps; /* step counter */ - uint16_t quat[3]; /* quaternion 3 axes format [x,y,z] */ - uint8_t nack; /* ext sensor nack index */ - uint8_t raw_data[6]; /* raw data */ -} sensor_data_t; - -/** - * @} - * - */ - -/** - * @} - * - */ - -st_fifo_status st_fifo_init(float_t bdr_xl, float_t bdr_gy, - float_t bdr_vsens); - -st_fifo_status st_fifo_decompress(st_fifo_out_slot *fifo_out_slot, - st_fifo_raw_slot *fifo_raw_slot, - uint16_t *out_slot_size, - uint16_t stream_size); - -void st_fifo_sort(st_fifo_out_slot *fifo_out_slot, - uint16_t out_slot_size); - -uint16_t st_fifo_get_sensor_occurrence(st_fifo_out_slot - *fifo_out_slot, - uint16_t out_slot_size, - st_fifo_sensor_type sensor_type); - -void st_fifo_extract_sensor(st_fifo_out_slot *sensor_out_slot, - st_fifo_out_slot *fifo_out_slot, - uint16_t out_slot_size, - st_fifo_sensor_type sensor_type); - -#ifdef __cplusplus -} -#endif - -#endif /* ST_FIFO_H */ - -/** - * @} - * - */ diff --git a/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.c b/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.c index 0ff649d26e2203f92365a855f5cc034f66ce9742..564c07ac49228eabad3921b086b522d0a4e6e32a 100644 --- a/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.c +++ b/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t a3g4250d_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak a3g4250d_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t a3g4250d_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t a3g4250d_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak a3g4250d_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.h b/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.h index d4e0c535525a061da04e8fa7003055dc45b6fa50..40a2e089060c03050a0e502acd34a7ec6bf189dd 100644 --- a/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.h +++ b/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.h @@ -108,12 +108,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -487,6 +490,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t a3g4250d_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/ais25ba_STdC/driver/ais25ba_reg.c b/sensor/stmemsc/ais25ba_STdC/driver/ais25ba_reg.c new file mode 100644 index 0000000000000000000000000000000000000000..d9f014bb3aeb0bcac3f388d352a21a445b27eec1 --- /dev/null +++ b/sensor/stmemsc/ais25ba_STdC/driver/ais25ba_reg.c @@ -0,0 +1,436 @@ +/** + ****************************************************************************** + * @file ais25ba_reg.c + * @author Sensors Software Solution Team + * @brief AIS25BA driver file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2022 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "ais25ba_reg.h" + +/** + * @defgroup AIS25BA + * @brief This file provides a set of functions needed to drive the + * ais25ba enhanced inertial module. + * @{ + * + */ + +/** + * @defgroup AIS25BA_Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +/** + * @brief Read generic device register + * + * @param ctx communication interface handler.(ptr) + * @param reg first register address to read. + * @param data buffer for data read.(ptr) + * @param len number of consecutive register to read. + * @retval interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t __weak ais25ba_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) +{ + int32_t ret; + + ret = ctx->read_reg(ctx->handle, reg, data, len); + + return ret; +} + +/** + * @brief Write generic device register + * + * @param ctx communication interface handler.(ptr) + * @param reg first register address to write. + * @param data the buffer contains data to be written.(ptr) + * @param len number of consecutive register to write. + * @retval interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t __weak ais25ba_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) +{ + int32_t ret; + + ret = ctx->write_reg(ctx->handle, reg, data, len); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup AIS25BA_Private_functions + * @brief Section collect all the utility functions needed by APIs. + * @{ + * + */ + +static void bytecpy(uint8_t *target, uint8_t *source) +{ + if ((target != NULL) && (source != NULL)) + { + *target = *source; + } +} + +/** + * @} + * + */ + +/** + * @defgroup AIS25BA_Sensitivity + * @brief These functions convert raw-data into engineering units. + * @{ + * + */ +float_t ais25ba_from_raw_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.122f; +} + +/** + * @} + * + */ + +/** + * @defgroup Basic configuration + * @brief This section groups all the functions concerning + * device basic configuration. + * @{ + * + */ + +/** + * @brief Device "Who am I".[get] + * + * @param ctx communication interface handler.(ptr) + * @param val ID values read from the I2C interface. + * + * @retval interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ais25ba_id_get(stmdev_ctx_t *ctx, ais25ba_id_t *val) +{ + int32_t ret = 0; + + if (ctx != NULL) + { + ret = ais25ba_read_reg(ctx, AIS25BA_WHO_AM_I, (uint8_t *) & (val->id), 1); + } + + return ret; +} + +/** + * @brief Configures the bus operating mode.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val configures the TDM bus operating mode.(ptr) + * + * @retval interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ais25ba_bus_mode_set(stmdev_ctx_t *ctx, + ais25ba_bus_mode_t *val) +{ + ais25ba_tdm_ctrl_reg_t tdm_ctrl_reg; + ais25ba_tdm_cmax_h_t tdm_cmax_h; + ais25ba_tdm_cmax_l_t tdm_cmax_l; + uint8_t reg[2]; + int32_t ret; + + ret = ais25ba_read_reg(ctx, AIS25BA_TDM_CTRL_REG, + (uint8_t *)&tdm_ctrl_reg, 1); + + if (ret == 0) + { + ret = ais25ba_read_reg(ctx, AIS25BA_TDM_CMAX_H, reg, 2); + bytecpy((uint8_t *)&tdm_cmax_h, ®[0]); + bytecpy((uint8_t *)&tdm_cmax_l, ®[1]); + tdm_ctrl_reg.tdm_pd = ~val->tdm.en; + tdm_ctrl_reg.data_valid = val->tdm.clk_pol; + tdm_ctrl_reg.delayed = val->tdm.clk_edge; + tdm_ctrl_reg.wclk_fq = val->tdm.mapping; + tdm_cmax_h.tdm_cmax = (uint8_t)(val->tdm.cmax / 256U); + tdm_cmax_l.tdm_cmax = (uint8_t)(val->tdm.cmax - tdm_cmax_h.tdm_cmax); + } + + if (ret == 0) + { + ret = ais25ba_write_reg(ctx, AIS25BA_TDM_CTRL_REG, + (uint8_t *)&tdm_ctrl_reg, 1); + } + + if (ret == 0) + { + bytecpy(®[0], (uint8_t *)&tdm_cmax_h); + bytecpy(®[1], (uint8_t *)&tdm_cmax_l); + ret = ais25ba_write_reg(ctx, AIS25BA_TDM_CMAX_H, reg, 2); + } + + return ret; +} + +/** + * @brief Get the bus operating mode.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val configures the TDM bus operating mode.(ptr) + * + * @retval interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ais25ba_bus_mode_get(stmdev_ctx_t *ctx, + ais25ba_bus_mode_t *val) +{ + ais25ba_tdm_ctrl_reg_t tdm_ctrl_reg; + ais25ba_tdm_cmax_h_t tdm_cmax_h; + ais25ba_tdm_cmax_l_t tdm_cmax_l; + uint8_t reg[2]; + int32_t ret; + + ret = ais25ba_read_reg(ctx, AIS25BA_TDM_CTRL_REG, + (uint8_t *)&tdm_ctrl_reg, 1); + + if (ret == 0) + { + ret = ais25ba_read_reg(ctx, AIS25BA_TDM_CMAX_H, reg, 2); + bytecpy((uint8_t *)&tdm_cmax_h, ®[0]); + bytecpy((uint8_t *)&tdm_cmax_l, ®[1]); + } + + val->tdm.en = ~tdm_ctrl_reg.tdm_pd; + val->tdm.clk_pol = tdm_ctrl_reg.data_valid; + val->tdm.clk_edge = tdm_ctrl_reg.delayed; + val->tdm.mapping = tdm_ctrl_reg.wclk_fq; + val->tdm.cmax = tdm_cmax_h.tdm_cmax * 256U; + val->tdm.cmax += tdm_cmax_l.tdm_cmax; + + return ret; +} + +/** + * @brief Sensor conversion parameters selection.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val set the sensor conversion parameters by checking + * the constraints of the device.(ptr) + * + * @retval interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ais25ba_mode_set(stmdev_ctx_t *ctx, ais25ba_md_t *val) +{ + ais25ba_axes_ctrl_reg_t axes_ctrl_reg; + ais25ba_tdm_ctrl_reg_t tdm_ctrl_reg; + ais25ba_ctrl_reg_t ctrl_reg; + uint8_t reg[2]; + int32_t ret; + + ret = ais25ba_read_reg(ctx, AIS25BA_CTRL_REG_1, (uint8_t *)&ctrl_reg, 1); + + if (ret == 0) + { + ret = ais25ba_read_reg(ctx, AIS25BA_TDM_CTRL_REG, reg, 2); + bytecpy((uint8_t *)&tdm_ctrl_reg, ®[0]); + bytecpy((uint8_t *)&axes_ctrl_reg, ®[1]); + } + + ctrl_reg.pd = (uint8_t)val->xl.odr & 0x01U; + tdm_ctrl_reg.wclk_fq = ((uint8_t)val->xl.odr & 0x06U) >> 1; + axes_ctrl_reg.odr_auto_en = ((uint8_t)val->xl.odr & 0x10U) >> 4; + + if (ret == 0) + { + ret = ais25ba_write_reg(ctx, AIS25BA_CTRL_REG_1, (uint8_t *)&ctrl_reg, 1); + } + + /* writing checked configuration */ + bytecpy(®[0], (uint8_t *)&tdm_ctrl_reg); + bytecpy(®[1], (uint8_t *)&axes_ctrl_reg); + + if (ret == 0) + { + ret = ais25ba_write_reg(ctx, AIS25BA_TDM_CTRL_REG, (uint8_t *)®, + 2); + } + + return ret; +} + +/** + * @brief Sensor conversion parameters selection.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val get the sensor conversion parameters.(ptr) + * + * @retval interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ais25ba_mode_get(stmdev_ctx_t *ctx, ais25ba_md_t *val) +{ + ais25ba_axes_ctrl_reg_t axes_ctrl_reg; + ais25ba_tdm_ctrl_reg_t tdm_ctrl_reg; + ais25ba_ctrl_reg_t ctrl_reg; + uint8_t reg[2]; + int32_t ret; + + ret = ais25ba_read_reg(ctx, AIS25BA_CTRL_REG_1, (uint8_t *)&ctrl_reg, 1); + + if (ret == 0) + { + ret = ais25ba_read_reg(ctx, AIS25BA_TDM_CTRL_REG, reg, 2); + bytecpy((uint8_t *)&tdm_ctrl_reg, ®[0]); + bytecpy((uint8_t *)&axes_ctrl_reg, ®[1]); + } + + switch ((axes_ctrl_reg.odr_auto_en << 4) | (tdm_ctrl_reg.wclk_fq << + 1) | + ctrl_reg.pd) + { + case AIS25BA_XL_OFF: + val->xl.odr = AIS25BA_XL_OFF; + break; + + case AIS25BA_XL_8kHz: + val->xl.odr = AIS25BA_XL_8kHz; + break; + + case AIS25BA_XL_16kHz: + val->xl.odr = AIS25BA_XL_16kHz; + break; + + case AIS25BA_XL_24kHz: + val->xl.odr = AIS25BA_XL_24kHz; + break; + + case AIS25BA_XL_HW_SEL: + val->xl.odr = AIS25BA_XL_HW_SEL; + break; + + default: + val->xl.odr = AIS25BA_XL_OFF; + break; + } + + return ret; +} + +/** + * @brief Read data in engineering unit.[get] + * + * @param tdm_stream data stream from TDM interface.(ptr) + * @param md the TDM interface configuration.(ptr) + * @param data data read by the sensor.(ptr) + * + * @retval interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ais25ba_data_get(uint16_t *tdm_stream, ais25ba_bus_mode_t *md, + ais25ba_data_t *data) +{ + uint8_t offset; + uint8_t i; + + if (md->tdm.mapping == PROPERTY_DISABLE) + { + offset = 0; /* slot0-1-2 */ + } + + else + { + offset = 4; /* slot4-5-6 */ + } + + for (i = 0U; i < 3U; i++) + { + data->xl.raw[i] = (int16_t) tdm_stream[i + offset]; + data->xl.mg[i] = ais25ba_from_raw_to_mg(data->xl.raw[i]); + } + + return 0; +} + +/** + * @brief Linear acceleration sensor self-test enable.[set] + * + * @param ctx read / write interface definitions.(ptr) + * @param val enable/ disable selftest + * + * @retval interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ais25ba_self_test_set(stmdev_ctx_t *ctx, uint8_t val) +{ + ais25ba_test_reg_t test_reg; + int32_t ret; + + ret = ais25ba_read_reg(ctx, AIS25BA_TEST_REG, (uint8_t *)&test_reg, 1); + + if (ret == 0) + { + test_reg.st = val; + ret = ais25ba_write_reg(ctx, AIS25BA_TEST_REG, (uint8_t *)&test_reg, 1); + } + + return ret; +} + +/** + * @brief Linear acceleration sensor self-test enable.[get] + * + * @param ctx read / write interface definitions.(ptr) + * @param val enable/ disable selftest.(ptr) + * + * @retval interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ais25ba_self_test_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + ais25ba_test_reg_t test_reg; + int32_t ret; + + ret = ais25ba_read_reg(ctx, AIS25BA_TEST_REG, (uint8_t *)&test_reg, 1); + *val = test_reg.st; + + return ret; +} + +/** + * @} + * + */ + +/** + * @} + * + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/ais25ba_STdC/driver/ais25ba_reg.h b/sensor/stmemsc/ais25ba_STdC/driver/ais25ba_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..2c8a2e818996710b614ab32df033f23403653132 --- /dev/null +++ b/sensor/stmemsc/ais25ba_STdC/driver/ais25ba_reg.h @@ -0,0 +1,380 @@ +/** + ****************************************************************************** + * @file ais25ba_reg.h + * @author Sensors Software Solution Team + * @brief This file contains all the functions prototypes for the + * ais25ba_reg.c driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2022 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef AIS25BA_REGS_H +#define AIS25BA_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include + +/** @addtogroup AIS25BA + * @{ + * + */ + +/** @defgroup Endianness definitions + * @{ + * + */ + +#ifndef DRV_BYTE_ORDER +#ifndef __BYTE_ORDER__ + +#define DRV_LITTLE_ENDIAN 1234 +#define DRV_BIG_ENDIAN 4321 + +/** if _BYTE_ORDER is not defined, choose the endianness of your architecture + * by uncommenting the define which fits your platform endianness + */ +//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN +#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN + +#else /* defined __BYTE_ORDER__ */ + +#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ +#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ +#define DRV_BYTE_ORDER __BYTE_ORDER__ + +#endif /* __BYTE_ORDER__*/ +#endif /* DRV_BYTE_ORDER */ + +/** + * @} + * + */ + +/** @defgroup STMicroelectronics sensors common types + * @{ + * + */ + +#ifndef MEMS_SHARED_TYPES +#define MEMS_SHARED_TYPES + +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} bitwise_t; + +#define PROPERTY_DISABLE (0U) +#define PROPERTY_ENABLE (1U) + +/** @addtogroup Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); +typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); + +typedef struct +{ + /** Component mandatory fields **/ + stmdev_write_ptr write_reg; + stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; + /** Customizable optional pointer **/ + void *handle; +} stmdev_ctx_t; + +/** + * @} + * + */ + +#endif /* MEMS_SHARED_TYPES */ + +#ifndef MEMS_UCF_SHARED_TYPES +#define MEMS_UCF_SHARED_TYPES + +/** @defgroup Generic address-data structure definition + * @brief This structure is useful to load a predefined configuration + * of a sensor. + * You can create a sensor configuration by your own or using + * Unico / Unicleo tools available on STMicroelectronics + * web site. + * + * @{ + * + */ + +typedef struct +{ + uint8_t address; + uint8_t data; +} ucf_line_t; + +/** + * @} + * + */ + +#endif /* MEMS_UCF_SHARED_TYPES */ + +/** + * @} + * + */ + +/** @defgroup AIS25BA_Infos + * @{ + * + */ + +/** I2C Device Address 8 bit format. SA0 = not(I2C_A0 pin) **/ +#define AIS25BA_I2C_ADD_L 0x33 +#define AIS25BA_I2C_ADD_H 0x31 + +/** Device Identification (Who am I) **/ +#define AIS25BA_ID 0x20 + +/** + * @} + * + */ + +#define AIS25BA_TEST_REG 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 3; + uint8_t st : 1; + uint8_t not_used_02 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 4; + uint8_t st : 1; + uint8_t not_used_01 : 3; +#endif /* DRV_BYTE_ORDER */ +} ais25ba_test_reg_t; + +#define AIS25BA_WHO_AM_I 0x0FU + +#define AIS25BA_TDM_CMAX_H 0x24U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tdm_cmax : 4; + uint8_t not_used_01 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 4; + uint8_t tdm_cmax : 4; +#endif /* DRV_BYTE_ORDER */ +} ais25ba_tdm_cmax_h_t; + +#define AIS25BA_TDM_CMAX_L 0x25U +typedef struct +{ + uint8_t tdm_cmax : 8; +} ais25ba_tdm_cmax_l_t; + +#define AIS25BA_CTRL_REG_1 0x26U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 5; + uint8_t pd : 1; + uint8_t not_used_02 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 2; + uint8_t pd : 1; + uint8_t not_used_01 : 5; +#endif /* DRV_BYTE_ORDER */ +} ais25ba_ctrl_reg_t; + +#define AIS25BA_TDM_CTRL_REG 0x2EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 1; + uint8_t wclk_fq : 2; + uint8_t not_used_02 : 1; + uint8_t mapping : 1; + uint8_t data_valid : 1; + uint8_t delayed : 1; + uint8_t tdm_pd : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tdm_pd : 1; + uint8_t delayed : 1; + uint8_t data_valid : 1; + uint8_t mapping : 1; + uint8_t not_used_02 : 1; + uint8_t wclk_fq : 2; + uint8_t not_used_01 : 1; +#endif /* DRV_BYTE_ORDER */ +} ais25ba_tdm_ctrl_reg_t; + +#define AIS25BA_CTRL_REG_2 0x2FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t odr_auto_en : 1; + uint8_t not_used_01 : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 7; + uint8_t odr_auto_en : 1; +#endif /* DRV_BYTE_ORDER */ +} ais25ba_axes_ctrl_reg_t; + +/** + * @defgroup AIS25BA_Register_Union + * @brief This union group all the registers that has a bitfield + * description. + * This union is useful but not need by the driver. + * + * REMOVING this union you are compliant with: + * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " + * + * @{ + * + */ +typedef union +{ + ais25ba_test_reg_t test_reg; + ais25ba_tdm_cmax_h_t tdm_cmax_h; + ais25ba_tdm_cmax_l_t tdm_cmax_l; + ais25ba_ctrl_reg_t ctrl_reg; + ais25ba_tdm_ctrl_reg_t tdm_ctrl_reg; + ais25ba_axes_ctrl_reg_t axes_ctrl_reg; + bitwise_t bitwise; + uint8_t byte; +} ais25ba_reg_t; + +/** + * @} + * + */ + +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + +int32_t ais25ba_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); +int32_t ais25ba_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); + +extern float_t ais25ba_from_raw_to_mg(int16_t lsb); + +typedef struct +{ + uint8_t id; +} ais25ba_id_t; +int32_t ais25ba_id_get(stmdev_ctx_t *ctx, ais25ba_id_t *val); + +typedef struct +{ + struct + { + uint8_t en : 1; /* TDM interface 1=on / 0=off) */ + uint8_t clk_pol : 1; /* data valid on 0=rise/1=falling edge of BCLK */ + uint8_t clk_edge : 1; /* data on 0=first / 1=second valid edge of BCLK */ + uint8_t mapping : 1; /* xl data in 0=slot0-1-2 / 1=slot4-5-6 */ + uint16_t cmax : 1; /* BCLK in a WCLK (unused if odr=_XL_HW_SEL) */ + } tdm; +} ais25ba_bus_mode_t; +int32_t ais25ba_bus_mode_set(stmdev_ctx_t *ctx, + ais25ba_bus_mode_t *val); +int32_t ais25ba_bus_mode_get(stmdev_ctx_t *ctx, + ais25ba_bus_mode_t *val); + +typedef struct +{ + struct + { + enum + { + AIS25BA_XL_OFF = 0x01, /* in power down */ + AIS25BA_XL_8kHz = 0x00, /* sampling rate equal to 8 kHz */ + AIS25BA_XL_16kHz = 0x02, /* sampling rate equal to 16 kHz */ + AIS25BA_XL_24kHz = 0x04, /* sampling rate equal to 24 kHz */ + AIS25BA_XL_HW_SEL = 0x10, /* ratio between the MCLK and WCLK */ + } odr; + } xl; +} ais25ba_md_t; +int32_t ais25ba_mode_set(stmdev_ctx_t *ctx, ais25ba_md_t *val); +int32_t ais25ba_mode_get(stmdev_ctx_t *ctx, ais25ba_md_t *val); + +typedef struct +{ + struct + { + float_t mg[3]; + int16_t raw[3]; + } xl; +} ais25ba_data_t; +int32_t ais25ba_data_get(uint16_t *tdm_stream, ais25ba_bus_mode_t *md, + ais25ba_data_t *data); + +int32_t ais25ba_self_test_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t ais25ba_self_test_get(stmdev_ctx_t *ctx, uint8_t *val); + +/** + * @} + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /*AIS25BA_DRIVER_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.c b/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.c index 66fac817de6da9344ba7ad102223545d114c6586..cc6c47878443a52ba3ec8c2f556128b2d184c58e 100644 --- a/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.c +++ b/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak ais2dw12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t ais2dw12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak ais2dw12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.h b/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.h index e06f042214117cfb28cdd7462fa8f52a557c63d1..df17ccc5c5a987acb942e4c21c742a52acab98c9 100644 --- a/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.h +++ b/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.h @@ -116,12 +116,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -576,6 +579,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t ais2dw12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/ais2ih_STdC/driver/ais2ih_reg.c b/sensor/stmemsc/ais2ih_STdC/driver/ais2ih_reg.c index f393607c2f0525c672ca73520f59096b562ba4b9..8fa9ebeef31407c689b7cacaa1d9fca103d03e0c 100644 --- a/sensor/stmemsc/ais2ih_STdC/driver/ais2ih_reg.c +++ b/sensor/stmemsc/ais2ih_STdC/driver/ais2ih_reg.c @@ -46,8 +46,8 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, - uint16_t len) +int32_t __weak ais2ih_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, + uint16_t len) { int32_t ret; @@ -66,9 +66,9 @@ int32_t ais2ih_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak ais2ih_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/ais2ih_STdC/driver/ais2ih_reg.h b/sensor/stmemsc/ais2ih_STdC/driver/ais2ih_reg.h index a6ed9ecce93f46c29365e2fa9342215f6dcd7ace..45ad9705cea6b1dd092833b07439685288a238de 100644 --- a/sensor/stmemsc/ais2ih_STdC/driver/ais2ih_reg.h +++ b/sensor/stmemsc/ais2ih_STdC/driver/ais2ih_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -649,6 +652,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t ais2ih_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); int32_t ais2ih_write_reg(stmdev_ctx_t *ctx, uint8_t reg, diff --git a/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.c b/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.c index c7dff8ce9d3095cc87cecfa91877d40de57bae0b..2af88d3f15c75b3d5d280a4022c20f53d40c207c 100644 --- a/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.c +++ b/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak ais328dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t ais328dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak ais328dq_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.h b/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.h index fb14038d6c75789babcbe5cc8a02cd7f8f9336d4..fbbbd151510e92bd7cc240cf03a5c58162656781 100644 --- a/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.h +++ b/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -501,6 +504,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t ais328dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.c b/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.c index a6fb76602992ccb9de496a8a8b910216ed1e338c..66962db6f3c2076a8bc29ddd9403ab5517fba57a 100644 --- a/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.c +++ b/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak ais3624dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t ais3624dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak ais3624dq_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.h b/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.h index 7161da6cc0027c9e4717c32c3235b52997c9c853..3ba16a9570fdd5a78032cd82c548f510f5cc4343 100644 --- a/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.h +++ b/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -480,6 +483,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t ais3624dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/asm330lhb_STdC/driver/asm330lhb_reg.c b/sensor/stmemsc/asm330lhb_STdC/driver/asm330lhb_reg.c new file mode 100644 index 0000000000000000000000000000000000000000..d2f87190c45f222688a426e8a6da883efde63f3c --- /dev/null +++ b/sensor/stmemsc/asm330lhb_STdC/driver/asm330lhb_reg.c @@ -0,0 +1,6605 @@ +/* + ****************************************************************************** + * @file asm330lhb_reg.c + * @author Sensors Software Solution Team + * @brief ASM330LHB driver file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2023 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "asm330lhb_reg.h" + +/** + * @defgroup ASM330LHB + * @brief This file provides a set of functions needed to drive the + * asm330lhb enhanced inertial module. + * @{ + * + */ + +/** + * @defgroup ASM330LHB_Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +/** + * @brief Read generic device register + * + * @param ctx read / write interface definitions(ptr) + * @param reg register to read + * @param data pointer to buffer that store the data read(ptr) + * @param len number of consecutive register to read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak asm330lhb_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, + uint16_t len) +{ + int32_t ret; + ret = ctx->read_reg(ctx->handle, reg, data, len); + return ret; +} + +/** + * @brief Write generic device register + * + * @param ctx read / write interface definitions(ptr) + * @param reg register to write + * @param data pointer to data to write in register reg(ptr) + * @param len number of consecutive register to write + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak asm330lhb_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, + uint16_t len) +{ + int32_t ret; + ret = ctx->write_reg(ctx->handle, reg, data, len); + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHB_Sensitivity + * @brief These functions convert raw-data into engineering units. + * @{ + * + */ + +float_t asm330lhb_from_fs2g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 0.061f); +} + +float_t asm330lhb_from_fs4g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 0.122f); +} + +float_t asm330lhb_from_fs8g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 0.244f); +} + +float_t asm330lhb_from_fs16g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 0.488f); +} + +float_t asm330lhb_from_fs125dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 4.375f); +} + +float_t asm330lhb_from_fs250dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 8.75f); +} + +float_t asm330lhb_from_fs500dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 17.50f); +} + +float_t asm330lhb_from_fs1000dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 35.0f); +} + +float_t asm330lhb_from_fs2000dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 70.0f); +} + +float_t asm330lhb_from_fs4000dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 140.0f); +} + +float_t asm330lhb_from_lsb_to_celsius(int16_t lsb) +{ + return (((float_t)lsb / 256.0f) + 25.0f); +} + +float_t asm330lhb_from_lsb_to_nsec(int32_t lsb) +{ + return ((float_t)lsb * 25000.0f); +} + +/** + * @} + * + */ + +/** + * @defgroup LSM9DS1_Data_generation + * @brief This section groups all the functions concerning data + * generation + * @{ + * + */ + +/** + * @brief Accelerometer full-scale selection[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fs_xl in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_xl_full_scale_set(stmdev_ctx_t *ctx, + asm330lhb_fs_xl_t val) +{ + asm330lhb_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret == 0) + { + ctrl1_xl.fs_xl = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL1_XL, + (uint8_t *)&ctrl1_xl, 1); + } + return ret; +} + +/** + * @brief Accelerometer full-scale selection.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of fs_xl in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_xl_full_scale_get(stmdev_ctx_t *ctx, + asm330lhb_fs_xl_t *val) +{ + asm330lhb_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + switch (ctrl1_xl.fs_xl) + { + case ASM330LHB_2g: + *val = ASM330LHB_2g; + break; + case ASM330LHB_16g: + *val = ASM330LHB_16g; + break; + case ASM330LHB_4g: + *val = ASM330LHB_4g; + break; + case ASM330LHB_8g: + *val = ASM330LHB_8g; + break; + default: + *val = ASM330LHB_2g; + break; + } + return ret; +} + +/** + * @brief Accelerometer UI data rate selection.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of odr_xl in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_xl_data_rate_set(stmdev_ctx_t *ctx, + asm330lhb_odr_xl_t val) +{ + asm330lhb_odr_xl_t odr_xl = val; + asm330lhb_emb_fsm_enable_t fsm_enable; + asm330lhb_fsm_odr_t fsm_odr; + asm330lhb_ctrl1_xl_t ctrl1_xl; + asm330lhb_mlc_odr_t mlc_odr; + uint8_t mlc_enable; + int32_t ret; + + /* Check the Finite State Machine data rate constraints */ + ret = asm330lhb_fsm_enable_get(ctx, &fsm_enable); + if (ret == 0) + { + if ((fsm_enable.fsm_enable_a.fsm1_en | + fsm_enable.fsm_enable_a.fsm2_en | + fsm_enable.fsm_enable_a.fsm3_en | + fsm_enable.fsm_enable_a.fsm4_en | + fsm_enable.fsm_enable_a.fsm5_en | + fsm_enable.fsm_enable_a.fsm6_en | + fsm_enable.fsm_enable_a.fsm7_en | + fsm_enable.fsm_enable_a.fsm8_en | + fsm_enable.fsm_enable_b.fsm9_en | + fsm_enable.fsm_enable_b.fsm10_en | + fsm_enable.fsm_enable_b.fsm11_en | + fsm_enable.fsm_enable_b.fsm12_en | + fsm_enable.fsm_enable_b.fsm13_en | + fsm_enable.fsm_enable_b.fsm14_en | + fsm_enable.fsm_enable_b.fsm15_en | + fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE) + { + + ret = asm330lhb_fsm_data_rate_get(ctx, &fsm_odr); + if (ret == 0) + { + switch (fsm_odr) + { + case ASM330LHB_ODR_FSM_12Hz5: + + if (val == ASM330LHB_XL_ODR_OFF) + { + odr_xl = ASM330LHB_XL_ODR_12Hz5; + + } + else + { + odr_xl = val; + } + break; + case ASM330LHB_ODR_FSM_26Hz: + + if (val == ASM330LHB_XL_ODR_OFF) + { + odr_xl = ASM330LHB_XL_ODR_26Hz; + + } + else if (val == ASM330LHB_XL_ODR_12Hz5) + { + odr_xl = ASM330LHB_XL_ODR_26Hz; + + } + else + { + odr_xl = val; + } + break; + case ASM330LHB_ODR_FSM_52Hz: + + if (val == ASM330LHB_XL_ODR_OFF) + { + odr_xl = ASM330LHB_XL_ODR_52Hz; + + } + else if (val == ASM330LHB_XL_ODR_12Hz5) + { + odr_xl = ASM330LHB_XL_ODR_52Hz; + + } + else if (val == ASM330LHB_XL_ODR_26Hz) + { + odr_xl = ASM330LHB_XL_ODR_52Hz; + + } + else + { + odr_xl = val; + } + break; + case ASM330LHB_ODR_FSM_104Hz: + + if (val == ASM330LHB_XL_ODR_OFF) + { + odr_xl = ASM330LHB_XL_ODR_104Hz; + + } + else if (val == ASM330LHB_XL_ODR_12Hz5) + { + odr_xl = ASM330LHB_XL_ODR_104Hz; + + } + else if (val == ASM330LHB_XL_ODR_26Hz) + { + odr_xl = ASM330LHB_XL_ODR_104Hz; + + } + else if (val == ASM330LHB_XL_ODR_52Hz) + { + odr_xl = ASM330LHB_XL_ODR_104Hz; + + } + else + { + odr_xl = val; + } + break; + default: + odr_xl = val; + break; + } + } + } + } + + /* Check the Machine Learning Core data rate constraints */ + mlc_enable = PROPERTY_DISABLE; + if (ret == 0) + { + ret = asm330lhb_mlc_get(ctx, &mlc_enable); + if (mlc_enable == PROPERTY_ENABLE) + { + + ret = asm330lhb_mlc_data_rate_get(ctx, &mlc_odr); + if (ret == 0) + { + switch (mlc_odr) + { + case ASM330LHB_ODR_PRGS_12Hz5: + + if (val == ASM330LHB_XL_ODR_OFF) + { + odr_xl = ASM330LHB_XL_ODR_12Hz5; + + } + else + { + odr_xl = val; + } + break; + case ASM330LHB_ODR_PRGS_26Hz: + if (val == ASM330LHB_XL_ODR_OFF) + { + odr_xl = ASM330LHB_XL_ODR_26Hz; + + } + else if (val == ASM330LHB_XL_ODR_12Hz5) + { + odr_xl = ASM330LHB_XL_ODR_26Hz; + + } + else + { + odr_xl = val; + } + break; + case ASM330LHB_ODR_PRGS_52Hz: + + if (val == ASM330LHB_XL_ODR_OFF) + { + odr_xl = ASM330LHB_XL_ODR_52Hz; + + } + else if (val == ASM330LHB_XL_ODR_12Hz5) + { + odr_xl = ASM330LHB_XL_ODR_52Hz; + + } + else if (val == ASM330LHB_XL_ODR_26Hz) + { + odr_xl = ASM330LHB_XL_ODR_52Hz; + + } + else + { + odr_xl = val; + } + break; + case ASM330LHB_ODR_PRGS_104Hz: + if (val == ASM330LHB_XL_ODR_OFF) + { + odr_xl = ASM330LHB_XL_ODR_104Hz; + + } + else if (val == ASM330LHB_XL_ODR_12Hz5) + { + odr_xl = ASM330LHB_XL_ODR_104Hz; + + } + else if (val == ASM330LHB_XL_ODR_26Hz) + { + odr_xl = ASM330LHB_XL_ODR_104Hz; + + } + else if (val == ASM330LHB_XL_ODR_52Hz) + { + odr_xl = ASM330LHB_XL_ODR_104Hz; + + } + else + { + odr_xl = val; + } + break; + default: + odr_xl = val; + break; + } + } + } + } + + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + } + if (ret == 0) + { + ctrl1_xl.odr_xl = (uint8_t)odr_xl; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL1_XL, + (uint8_t *)&ctrl1_xl, 1); + } + return ret; +} + +/** + * @brief Accelerometer UI data rate selection.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of odr_xl in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_xl_data_rate_get(stmdev_ctx_t *ctx, + asm330lhb_odr_xl_t *val) +{ + asm330lhb_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + switch (ctrl1_xl.odr_xl) + { + case ASM330LHB_XL_ODR_OFF: + *val = ASM330LHB_XL_ODR_OFF; + break; + case ASM330LHB_XL_ODR_12Hz5: + *val = ASM330LHB_XL_ODR_12Hz5; + break; + case ASM330LHB_XL_ODR_26Hz: + *val = ASM330LHB_XL_ODR_26Hz; + break; + case ASM330LHB_XL_ODR_52Hz: + *val = ASM330LHB_XL_ODR_52Hz; + break; + case ASM330LHB_XL_ODR_104Hz: + *val = ASM330LHB_XL_ODR_104Hz; + break; + case ASM330LHB_XL_ODR_208Hz: + *val = ASM330LHB_XL_ODR_208Hz; + break; + case ASM330LHB_XL_ODR_417Hz: + *val = ASM330LHB_XL_ODR_417Hz; + break; + case ASM330LHB_XL_ODR_833Hz: + *val = ASM330LHB_XL_ODR_833Hz; + break; + case ASM330LHB_XL_ODR_1667Hz: + *val = ASM330LHB_XL_ODR_1667Hz; + break; + case ASM330LHB_XL_ODR_1Hz6: + *val = ASM330LHB_XL_ODR_1Hz6; + break; + default: + *val = ASM330LHB_XL_ODR_OFF; + break; + } + return ret; +} + +/** + * @brief Gyroscope UI chain full-scale selection.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fs_g in reg CTRL2_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_gy_full_scale_set(stmdev_ctx_t *ctx, + asm330lhb_fs_g_t val) +{ + asm330lhb_ctrl2_g_t ctrl2_g; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + if (ret == 0) + { + ctrl2_g.fs_g = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + } + return ret; +} + +/** + * @brief Gyroscope UI chain full-scale selection.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of fs_g in reg CTRL2_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_gy_full_scale_get(stmdev_ctx_t *ctx, + asm330lhb_fs_g_t *val) +{ + asm330lhb_ctrl2_g_t ctrl2_g; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + switch (ctrl2_g.fs_g) + { + case ASM330LHB_125dps: + *val = ASM330LHB_125dps; + break; + case ASM330LHB_250dps: + *val = ASM330LHB_250dps; + break; + case ASM330LHB_500dps: + *val = ASM330LHB_500dps; + break; + case ASM330LHB_1000dps: + *val = ASM330LHB_1000dps; + break; + case ASM330LHB_2000dps: + *val = ASM330LHB_2000dps; + break; + case ASM330LHB_4000dps: + *val = ASM330LHB_4000dps; + break; + default: + *val = ASM330LHB_125dps; + break; + } + return ret; +} + +/** + * @brief Gyroscope data rate.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of odr_g in reg CTRL2_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_gy_data_rate_set(stmdev_ctx_t *ctx, + asm330lhb_odr_g_t val) +{ + asm330lhb_odr_g_t odr_gy = val; + asm330lhb_emb_fsm_enable_t fsm_enable; + asm330lhb_fsm_odr_t fsm_odr; + asm330lhb_ctrl2_g_t ctrl2_g; + asm330lhb_mlc_odr_t mlc_odr; + uint8_t mlc_enable; + int32_t ret; + + /* Check the Finite State Machine data rate constraints */ + ret = asm330lhb_fsm_enable_get(ctx, &fsm_enable); + if (ret == 0) + { + if ((fsm_enable.fsm_enable_a.fsm1_en | + fsm_enable.fsm_enable_a.fsm2_en | + fsm_enable.fsm_enable_a.fsm3_en | + fsm_enable.fsm_enable_a.fsm4_en | + fsm_enable.fsm_enable_a.fsm5_en | + fsm_enable.fsm_enable_a.fsm6_en | + fsm_enable.fsm_enable_a.fsm7_en | + fsm_enable.fsm_enable_a.fsm8_en | + fsm_enable.fsm_enable_b.fsm9_en | + fsm_enable.fsm_enable_b.fsm10_en | + fsm_enable.fsm_enable_b.fsm11_en | + fsm_enable.fsm_enable_b.fsm12_en | + fsm_enable.fsm_enable_b.fsm13_en | + fsm_enable.fsm_enable_b.fsm14_en | + fsm_enable.fsm_enable_b.fsm15_en | + fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE) + { + + ret = asm330lhb_fsm_data_rate_get(ctx, &fsm_odr); + if (ret == 0) + { + switch (fsm_odr) + { + case ASM330LHB_ODR_FSM_12Hz5: + + if (val == ASM330LHB_GY_ODR_OFF) + { + odr_gy = ASM330LHB_GY_ODR_12Hz5; + + } + else + { + odr_gy = val; + } + break; + case ASM330LHB_ODR_FSM_26Hz: + + if (val == ASM330LHB_GY_ODR_OFF) + { + odr_gy = ASM330LHB_GY_ODR_26Hz; + + } + else if (val == ASM330LHB_GY_ODR_12Hz5) + { + odr_gy = ASM330LHB_GY_ODR_26Hz; + + } + else + { + odr_gy = val; + } + break; + case ASM330LHB_ODR_FSM_52Hz: + + if (val == ASM330LHB_GY_ODR_OFF) + { + odr_gy = ASM330LHB_GY_ODR_52Hz; + + } + else if (val == ASM330LHB_GY_ODR_12Hz5) + { + odr_gy = ASM330LHB_GY_ODR_52Hz; + + } + else if (val == ASM330LHB_GY_ODR_26Hz) + { + odr_gy = ASM330LHB_GY_ODR_52Hz; + + } + else + { + odr_gy = val; + } + break; + case ASM330LHB_ODR_FSM_104Hz: + + if (val == ASM330LHB_GY_ODR_OFF) + { + odr_gy = ASM330LHB_GY_ODR_104Hz; + + } + else if (val == ASM330LHB_GY_ODR_12Hz5) + { + odr_gy = ASM330LHB_GY_ODR_104Hz; + + } + else if (val == ASM330LHB_GY_ODR_26Hz) + { + odr_gy = ASM330LHB_GY_ODR_104Hz; + + } + else if (val == ASM330LHB_GY_ODR_52Hz) + { + odr_gy = ASM330LHB_GY_ODR_104Hz; + + } + else + { + odr_gy = val; + } + break; + default: + odr_gy = val; + break; + } + } + } + } + + /* Check the Machine Learning Core data rate constraints */ + mlc_enable = PROPERTY_DISABLE; + if (ret == 0) + { + ret = asm330lhb_mlc_get(ctx, &mlc_enable); + if (mlc_enable == PROPERTY_ENABLE) + { + + ret = asm330lhb_mlc_data_rate_get(ctx, &mlc_odr); + if (ret == 0) + { + switch (mlc_odr) + { + case ASM330LHB_ODR_PRGS_12Hz5: + + if (val == ASM330LHB_GY_ODR_OFF) + { + odr_gy = ASM330LHB_GY_ODR_12Hz5; + + } + else + { + odr_gy = val; + } + break; + case ASM330LHB_ODR_PRGS_26Hz: + + if (val == ASM330LHB_GY_ODR_OFF) + { + odr_gy = ASM330LHB_GY_ODR_26Hz; + + } + else if (val == ASM330LHB_GY_ODR_12Hz5) + { + odr_gy = ASM330LHB_GY_ODR_26Hz; + + } + else + { + odr_gy = val; + } + break; + case ASM330LHB_ODR_PRGS_52Hz: + + if (val == ASM330LHB_GY_ODR_OFF) + { + odr_gy = ASM330LHB_GY_ODR_52Hz; + + } + else if (val == ASM330LHB_GY_ODR_12Hz5) + { + odr_gy = ASM330LHB_GY_ODR_52Hz; + + } + else if (val == ASM330LHB_GY_ODR_26Hz) + { + odr_gy = ASM330LHB_GY_ODR_52Hz; + + } + else + { + odr_gy = val; + } + break; + case ASM330LHB_ODR_PRGS_104Hz: + + if (val == ASM330LHB_GY_ODR_OFF) + { + odr_gy = ASM330LHB_GY_ODR_104Hz; + + } + else if (val == ASM330LHB_GY_ODR_12Hz5) + { + odr_gy = ASM330LHB_GY_ODR_104Hz; + + } + else if (val == ASM330LHB_GY_ODR_26Hz) + { + odr_gy = ASM330LHB_GY_ODR_104Hz; + + } + else if (val == ASM330LHB_GY_ODR_52Hz) + { + odr_gy = ASM330LHB_GY_ODR_104Hz; + + } + else + { + odr_gy = val; + } + break; + default: + odr_gy = val; + break; + } + } + } + } + + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + } + if (ret == 0) + { + ctrl2_g.odr_g = (uint8_t)odr_gy; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + } + return ret; +} + +/** + * @brief Gyroscope data rate.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of odr_g in reg CTRL2_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_gy_data_rate_get(stmdev_ctx_t *ctx, + asm330lhb_odr_g_t *val) +{ + asm330lhb_ctrl2_g_t ctrl2_g; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + switch (ctrl2_g.odr_g) + { + case ASM330LHB_GY_ODR_OFF: + *val = ASM330LHB_GY_ODR_OFF; + break; + case ASM330LHB_GY_ODR_12Hz5: + *val = ASM330LHB_GY_ODR_12Hz5; + break; + case ASM330LHB_GY_ODR_26Hz: + *val = ASM330LHB_GY_ODR_26Hz; + break; + case ASM330LHB_GY_ODR_52Hz: + *val = ASM330LHB_GY_ODR_52Hz; + break; + case ASM330LHB_GY_ODR_104Hz: + *val = ASM330LHB_GY_ODR_104Hz; + break; + case ASM330LHB_GY_ODR_208Hz: + *val = ASM330LHB_GY_ODR_208Hz; + break; + case ASM330LHB_GY_ODR_417Hz: + *val = ASM330LHB_GY_ODR_417Hz; + break; + case ASM330LHB_GY_ODR_833Hz: + *val = ASM330LHB_GY_ODR_833Hz; + break; + case ASM330LHB_GY_ODR_1667Hz: + *val = ASM330LHB_GY_ODR_1667Hz; + break; + default: + *val = ASM330LHB_GY_ODR_OFF; + break; + } + return ret; +} + +/** + * @brief Block data update.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of bdu in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhb_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret == 0) + { + ctrl3_c.bdu = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Block data update.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of bdu in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + *val = ctrl3_c.bdu; + + return ret; +} + +/** + * @brief Weight of XL user offset bits of registers X_OFS_USR (73h), + * Y_OFS_USR (74h), Z_OFS_USR (75h).[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of usr_off_w in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_xl_offset_weight_set(stmdev_ctx_t *ctx, + asm330lhb_usr_off_w_t val) +{ + asm330lhb_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret == 0) + { + ctrl6_c.usr_off_w = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + } + return ret; +} + +/** + * @brief Weight of XL user offset bits of registers X_OFS_USR (73h), + * Y_OFS_USR (74h), Z_OFS_USR (75h).[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of usr_off_w in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_xl_offset_weight_get(stmdev_ctx_t *ctx, + asm330lhb_usr_off_w_t *val) +{ + asm330lhb_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + + switch (ctrl6_c.usr_off_w) + { + case ASM330LHB_LSb_1mg: + *val = ASM330LHB_LSb_1mg; + break; + case ASM330LHB_LSb_16mg: + *val = ASM330LHB_LSb_16mg; + break; + default: + *val = ASM330LHB_LSb_1mg; + break; + } + return ret; +} + +/** + * @brief Accelerometer power mode.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of xl_hm_mode in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_xl_power_mode_set(stmdev_ctx_t *ctx, + asm330lhb_xl_hm_mode_t val) +{ + asm330lhb_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret == 0) + { + ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + } + return ret; +} + +/** + * @brief Accelerometer power mode[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of xl_hm_mode in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_xl_power_mode_get(stmdev_ctx_t *ctx, + asm330lhb_xl_hm_mode_t *val) +{ + asm330lhb_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + switch (ctrl6_c.xl_hm_mode) + { + case ASM330LHB_HIGH_PERFORMANCE_MD: + *val = ASM330LHB_HIGH_PERFORMANCE_MD; + break; + case ASM330LHB_LOW_NORMAL_POWER_MD: + *val = ASM330LHB_LOW_NORMAL_POWER_MD; + break; + default: + *val = ASM330LHB_HIGH_PERFORMANCE_MD; + break; + } + return ret; +} + +/** + * @brief Operating mode for gyroscope.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of g_hm_mode in reg CTRL7_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_gy_power_mode_set(stmdev_ctx_t *ctx, + asm330lhb_g_hm_mode_t val) +{ + asm330lhb_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret == 0) + { + ctrl7_g.g_hm_mode = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + } + return ret; +} + +/** + * @brief gy_power_mode: [get] Operating mode for gyroscope. + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of g_hm_mode in reg CTRL7_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_gy_power_mode_get(stmdev_ctx_t *ctx, + asm330lhb_g_hm_mode_t *val) +{ + asm330lhb_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + switch (ctrl7_g.g_hm_mode) + { + case ASM330LHB_GY_HIGH_PERFORMANCE: + *val = ASM330LHB_GY_HIGH_PERFORMANCE; + break; + case ASM330LHB_GY_NORMAL: + *val = ASM330LHB_GY_NORMAL; + break; + default: + *val = ASM330LHB_GY_HIGH_PERFORMANCE; + break; + } + return ret; +} + +/** + * @brief Read all the interrupt flag of the device. + *[get] + * @param ctx Read / write interface definitions.(ptr) + * @param val Get registers ALL_INT_SRC; WAKE_UP_SRC; + * TAP_SRC; D6D_SRC; STATUS_REG; + * EMB_FUNC_STATUS; FSM_STATUS_A/B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_all_sources_get(stmdev_ctx_t *ctx, + asm330lhb_all_sources_t *val) +{ + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_ALL_INT_SRC, + (uint8_t *)&val->all_int_src, 1); + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_SRC, + (uint8_t *)&val->wake_up_src, 1); + } + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_D6D_SRC, + (uint8_t *)&val->d6d_src, 1); + } + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_STATUS_REG, + (uint8_t *)&val->status_reg, 1); + } + if (ret == 0) + { + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + } + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_STATUS, + (uint8_t *)&val->emb_func_status, 1); + } + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_STATUS_A, + (uint8_t *)&val->fsm_status_a, 1); + } + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_STATUS_B, + (uint8_t *)&val->fsm_status_b, 1); + } + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_MLC_STATUS, + (uint8_t *)&val->mlc_status, 1); + } + if (ret == 0) + { + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + } + + return ret; +} + +/** + * @brief The STATUS_REG register is read by the primary interface.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get register STATUS_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_status_reg_get(stmdev_ctx_t *ctx, + asm330lhb_status_reg_t *val) +{ + int32_t ret; + ret = asm330lhb_read_reg(ctx, ASM330LHB_STATUS_REG, (uint8_t *) val, 1); + return ret; +} + +/** + * @brief Accelerometer new data available.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of xlda in reg STATUS_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_status_reg_t status_reg; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_STATUS_REG, + (uint8_t *)&status_reg, 1); + *val = status_reg.xlda; + + return ret; +} + +/** + * @brief Gyroscope new data available.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of gda in reg STATUS_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_status_reg_t status_reg; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_STATUS_REG, + (uint8_t *)&status_reg, 1); + *val = status_reg.gda; + + return ret; +} + +/** + * @brief Temperature new data available.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of tda in reg STATUS_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_status_reg_t status_reg; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_STATUS_REG, + (uint8_t *)&status_reg, 1); + *val = status_reg.tda; + + return ret; +} + +/** + * @brief Device boot status.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the device boot status in reg STATUS_REG. + * 0: OK, 1: FAIL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_boot_device_status_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_status_reg_t status_reg; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_STATUS_REG, + (uint8_t *)&status_reg, 1); + *val = status_reg.boot_check_fail; + + return ret; +} + +/** + * @brief Accelerometer X-axis user offset correction expressed in two’s + * complement, weight depends on USR_OFF_W in CTRL6_C (15h). + * The value must be in the range [-127 127].[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = asm330lhb_write_reg(ctx, ASM330LHB_X_OFS_USR, buff, 1); + return ret; +} + +/** + * @brief Accelerometer X-axis user offset correction expressed in two’s + * complement, weight depends on USR_OFF_W in CTRL6_C (15h). + * The value must be in the range [-127 127].[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = asm330lhb_read_reg(ctx, ASM330LHB_X_OFS_USR, buff, 1); + return ret; +} + +/** + * @brief Accelerometer Y-axis user offset correction expressed in two’s + * complement, weight depends on USR_OFF_W in CTRL6_C (15h). + * The value must be in the range [-127 127].[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = asm330lhb_write_reg(ctx, ASM330LHB_Y_OFS_USR, buff, 1); + return ret; +} + +/** + * @brief Accelerometer Y-axis user offset correction expressed in two’s + * complement, weight depends on USR_OFF_W in CTRL6_C (15h). + * The value must be in the range [-127 127].[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = asm330lhb_read_reg(ctx, ASM330LHB_Y_OFS_USR, buff, 1); + return ret; +} + +/** + * @brief Accelerometer Z-axis user offset correction expressed in two’s + * complement, weight depends on USR_OFF_W in CTRL6_C (15h). + * The value must be in the range [-127 127].[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = asm330lhb_write_reg(ctx, ASM330LHB_Z_OFS_USR, buff, 1); + return ret; +} + +/** + * @brief Accelerometer X-axis user offset correction expressed in two’s + * complement, weight depends on USR_OFF_W in CTRL6_C (15h). + * The value must be in the range [-127 127].[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = asm330lhb_read_reg(ctx, ASM330LHB_Z_OFS_USR, buff, 1); + return ret; +} + +/** + * @brief Enables user offset on out.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of usr_off_on_out in reg CTRL7_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhb_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret == 0) + { + ctrl7_g.usr_off_on_out = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + } + return ret; +} + +/** + * @brief Get user offset on out flag.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get values of usr_off_on_out in reg CTRL7_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + *val = ctrl7_g.usr_off_on_out; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHB_Timestamp + * @brief This section groups all the functions that manage the + * timestamp generation. + * @{ + * + */ + +/** + * @brief Reset timestamp counter.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_timestamp_rst(stmdev_ctx_t *ctx) +{ + uint8_t rst_val = 0xAA; + + return asm330lhb_write_reg(ctx, ASM330LHB_TIMESTAMP2, &rst_val, 1); +} + +/** + * @brief Enables timestamp counter.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of timestamp_en in reg CTRL10_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhb_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + if (ret == 0) + { + ctrl10_c.timestamp_en = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL10_C, + (uint8_t *)&ctrl10_c, 1); + } + return ret; +} + +/** + * @brief Enables timestamp counter.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of timestamp_en in reg CTRL10_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + *val = ctrl10_c.timestamp_en; + + return ret; +} + +/** + * @brief Timestamp first data output register (r). + * The value is expressed as a 32-bit word and the bit resolution + * is 25 μs.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) +{ + uint8_t buff[4]; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_TIMESTAMP0, buff, 4); + *val = buff[3]; + *val = (*val * 256U) + buff[2]; + *val = (*val * 256U) + buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHB_Data output + * @brief This section groups all the data output functions. + * @{ + * + */ + +/** + * @brief Circular burst-mode (rounding) read of the output registers.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of rounding in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_rounding_mode_set(stmdev_ctx_t *ctx, + asm330lhb_rounding_t val) +{ + asm330lhb_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret == 0) + { + ctrl5_c.rounding = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + } + return ret; +} + +/** + * @brief Gyroscope UI chain full-scale selection.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of rounding in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_rounding_mode_get(stmdev_ctx_t *ctx, + asm330lhb_rounding_t *val) +{ + asm330lhb_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + switch (ctrl5_c.rounding) + { + case ASM330LHB_NO_ROUND: + *val = ASM330LHB_NO_ROUND; + break; + case ASM330LHB_ROUND_XL: + *val = ASM330LHB_ROUND_XL; + break; + case ASM330LHB_ROUND_GY: + *val = ASM330LHB_ROUND_GY; + break; + case ASM330LHB_ROUND_GY_XL: + *val = ASM330LHB_ROUND_GY_XL; + break; + default: + *val = ASM330LHB_NO_ROUND; + break; + } + return ret; +} + +/** + * @brief Temperature data output register (r). + * L and H registers together express a 16-bit word in two’s + * complement.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_OUT_TEMP_L, buff, 2); + *val = (int16_t)buff[1]; + *val = (*val * 256) + (int16_t)buff[0]; + + return ret; +} + +/** + * @brief Angular rate sensor. The value is expressed as a 16-bit + * word in two’s complement.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + ret = asm330lhb_read_reg(ctx, ASM330LHB_OUTX_L_G, buff, 6); + + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Linear acceleration output register. The value is expressed as a + * 16-bit word in two’s complement.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + ret = asm330lhb_read_reg(ctx, ASM330LHB_OUTX_L_A, buff, 6); + + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief FIFO data output.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + int32_t ret; + ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_DATA_OUT_X_L, val, 6); + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHB_common + * @brief This section groups common useful functions. + * @{ + * + */ + +/** + * @brief Difference in percentage of the effective ODR (and timestamp rate) + * with respect to the typical.[set] + * Step: 0.15%. 8-bit format, 2's complement. + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhb_internal_freq_fine_t internal_freq_fine; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_INTERNAL_FREQ_FINE, + (uint8_t *)&internal_freq_fine, 1); + if (ret == 0) + { + internal_freq_fine.freq_fine = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_INTERNAL_FREQ_FINE, + (uint8_t *)&internal_freq_fine, 1); + } + return ret; +} + +/** + * @brief Difference in percentage of the effective ODR (and timestamp rate) + * with respect to the typical.[get] + * Step: 0.15%. 8-bit format, 2's complement. + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_internal_freq_fine_t internal_freq_fine; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_INTERNAL_FREQ_FINE, + (uint8_t *)&internal_freq_fine, 1); + *val = internal_freq_fine.freq_fine; + + return ret; +} + +/** + * @brief Enable access to the embedded functions/sensor hub configuration + * registers.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of reg_access in reg FUNC_CFG_ACCESS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_mem_bank_set(stmdev_ctx_t *ctx, + asm330lhb_reg_access_t val) +{ + asm330lhb_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_FUNC_CFG_ACCESS, + (uint8_t *)&func_cfg_access, 1); + if (ret == 0) + { + func_cfg_access.reg_access = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_FUNC_CFG_ACCESS, + (uint8_t *)&func_cfg_access, 1); + } + return ret; +} + +/** + * @brief Enable access to the embedded functions/sensor hub configuration + * registers.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of reg_access in reg FUNC_CFG_ACCESS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_mem_bank_get(stmdev_ctx_t *ctx, + asm330lhb_reg_access_t *val) +{ + asm330lhb_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_FUNC_CFG_ACCESS, + (uint8_t *)&func_cfg_access, 1); + switch (func_cfg_access.reg_access) + { + case ASM330LHB_USER_BANK: + *val = ASM330LHB_USER_BANK; + break; + case ASM330LHB_EMBEDDED_FUNC_BANK: + *val = ASM330LHB_EMBEDDED_FUNC_BANK; + break; + default: + *val = ASM330LHB_USER_BANK; + break; + } + return ret; +} + +/** + * @brief Write a line(byte) in a page.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param add Page line address + * @param val Value to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t add, + uint8_t *val) +{ + asm330lhb_page_rw_t page_rw; + asm330lhb_page_sel_t page_sel; + asm330lhb_page_address_t page_address; + int32_t ret; + + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + page_rw.page_rw = 0x02U; /* page_write enable */ + ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_SEL, (uint8_t *)&page_sel, 1); + } + if (ret == 0) + { + page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU); + page_sel.not_used_01 = 1; + ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_SEL, + (uint8_t *)&page_sel, 1); + } + if (ret == 0) + { + page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U)); + ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + } + if (ret == 0) + { + ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_VALUE, val, 1); + } + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + page_rw.page_rw = 0x00; /* page_write disable */ + ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + } + return ret; +} + +/** + * @brief Write buffer in a page.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buf Page line address.(ptr) + * @param val Value to write. + * @param len buffer lenght. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_ln_pg_write(stmdev_ctx_t *ctx, uint16_t add, + uint8_t *buf, uint8_t len) +{ + asm330lhb_page_rw_t page_rw; + asm330lhb_page_sel_t page_sel; + asm330lhb_page_address_t page_address; + int32_t ret; + uint8_t msb, lsb; + uint8_t i ; + + msb = (uint8_t)(add / 256U); + lsb = (uint8_t)(add - (msb * 256U)); + + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + page_rw.page_rw = 0x02U; /* page_write enable*/ + ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_SEL, (uint8_t *)&page_sel, 1); + } + if (ret == 0) + { + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; + ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_SEL, + (uint8_t *)&page_sel, 1); + } + if (ret == 0) + { + page_address.page_addr = lsb; + ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + } + for (i = 0; i < len; i++) + { + if (ret == 0) + { + ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_VALUE, &buf[i], 1); + if (ret == 0) + { + /* Check if page wrap */ + if (lsb == 0x00U) + { + msb++; + ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_SEL, + (uint8_t *)&page_sel, 1); + } + lsb++; + } + if (ret == 0) + { + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; + ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_SEL, + (uint8_t *)&page_sel, 1); + } + } + } + + if (ret == 0) + { + page_sel.page_sel = 0; + page_sel.not_used_01 = 1; + ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_SEL, + (uint8_t *)&page_sel, 1); + } + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + page_rw.page_rw = 0x00U; /* page_write disable */ + ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + } + return ret; +} + +/** + * @brief Read a line(byte) in a page.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param add Page line address. + * @param val Read value.(ptr) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add, + uint8_t *val) +{ + asm330lhb_page_rw_t page_rw; + asm330lhb_page_sel_t page_sel; + asm330lhb_page_address_t page_address; + int32_t ret; + + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + page_rw.page_rw = 0x01U; /* page_read enable*/ + ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_SEL, (uint8_t *)&page_sel, 1); + } + if (ret == 0) + { + page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU); + page_sel.not_used_01 = 1; + ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_SEL, + (uint8_t *)&page_sel, 1); + } + if (ret == 0) + { + page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U)); + ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + } + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_VALUE, val, 2); + } + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + page_rw.page_rw = 0x00U; /* page_read disable */ + ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + } + return ret; +} + +/** + * @brief Data-ready pulsed / letched mode.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of dataready_pulsed in + * reg COUNTER_BDR_REG1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_data_ready_mode_set(stmdev_ctx_t *ctx, + asm330lhb_dataready_pulsed_t val) +{ + asm330lhb_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + if (ret == 0) + { + counter_bdr_reg1.dataready_pulsed = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + } + return ret; +} + +/** + * @brief Data-ready pulsed / letched mode.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of dataready_pulsed in + * reg COUNTER_BDR_REG1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_data_ready_mode_get(stmdev_ctx_t *ctx, + asm330lhb_dataready_pulsed_t *val) +{ + asm330lhb_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + switch (counter_bdr_reg1.dataready_pulsed) + { + case ASM330LHB_DRDY_LATCHED: + *val = ASM330LHB_DRDY_LATCHED; + break; + case ASM330LHB_DRDY_PULSED: + *val = ASM330LHB_DRDY_PULSED; + break; + default: + *val = ASM330LHB_DRDY_LATCHED; + break; + } + return ret; +} + +/** + * @brief Device Who am I.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = asm330lhb_read_reg(ctx, ASM330LHB_WHO_AM_I, buff, 1); + return ret; +} + +/** + * @brief Software reset. Restore the default values in user registers.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of sw_reset in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_reset_set(stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhb_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret == 0) + { + ctrl3_c.sw_reset = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Software reset. Restore the default values in user registers.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of sw_reset in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + *val = ctrl3_c.sw_reset; + + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte + * access with a serial interface.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of if_inc in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhb_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret == 0) + { + ctrl3_c.if_inc = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte + * access with a serial interface.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of if_inc in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + *val = ctrl3_c.if_inc; + + return ret; +} + +/** + * @brief Reboot memory content. Reload the calibration parameters.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of boot in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_boot_set(stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhb_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret == 0) + { + ctrl3_c.boot = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Reboot memory content. Reload the calibration parameters.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of boot in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + *val = ctrl3_c.boot; + + return ret; +} + + + +/** + * @brief Linear acceleration sensor self-test enable.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of st_xl in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_xl_self_test_set(stmdev_ctx_t *ctx, + asm330lhb_st_xl_t val) +{ + asm330lhb_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret == 0) + { + ctrl5_c.st_xl = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + } + return ret; +} + +/** + * @brief Linear acceleration sensor self-test enable.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of st_xl in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_xl_self_test_get(stmdev_ctx_t *ctx, + asm330lhb_st_xl_t *val) +{ + asm330lhb_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + + switch (ctrl5_c.st_xl) + { + case ASM330LHB_XL_ST_DISABLE: + *val = ASM330LHB_XL_ST_DISABLE; + break; + case ASM330LHB_XL_ST_POSITIVE: + *val = ASM330LHB_XL_ST_POSITIVE; + break; + case ASM330LHB_XL_ST_NEGATIVE: + *val = ASM330LHB_XL_ST_NEGATIVE; + break; + default: + *val = ASM330LHB_XL_ST_DISABLE; + break; + } + return ret; +} + +/** + * @brief Angular rate sensor self-test enable.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of st_g in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_gy_self_test_set(stmdev_ctx_t *ctx, + asm330lhb_st_g_t val) +{ + asm330lhb_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret == 0) + { + ctrl5_c.st_g = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + } + return ret; +} + +/** + * @brief Angular rate sensor self-test enable.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of st_g in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_gy_self_test_get(stmdev_ctx_t *ctx, + asm330lhb_st_g_t *val) +{ + asm330lhb_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + + switch (ctrl5_c.st_g) + { + case ASM330LHB_GY_ST_DISABLE: + *val = ASM330LHB_GY_ST_DISABLE; + break; + case ASM330LHB_GY_ST_POSITIVE: + *val = ASM330LHB_GY_ST_POSITIVE; + break; + case ASM330LHB_GY_ST_NEGATIVE: + *val = ASM330LHB_GY_ST_NEGATIVE; + break; + default: + *val = ASM330LHB_GY_ST_DISABLE; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHB_filters + * @brief This section group all the functions concerning the + * filters configuration + * @{ + * + */ + +/** + * @brief Accelerometer output from LPF2 filtering stage selection.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of lpf2_xl_en in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhb_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret == 0) + { + ctrl1_xl.lpf2_xl_en = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL1_XL, + (uint8_t *)&ctrl1_xl, 1); + } + return ret; +} + +/** + * @brief Accelerometer output from LPF2 filtering stage selection.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of lpf2_xl_en in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + *val = ctrl1_xl.lpf2_xl_en; + + return ret; +} + +/** + * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled; + * the bandwidth can be selected through FTYPE [2:0] in CTRL6_C.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of lpf1_sel_g in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhb_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret == 0) + { + ctrl4_c.lpf1_sel_g = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + } + return ret; +} + +/** + * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled; + * the bandwidth can be selected through FTYPE [2:0] in CTRL6_C.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of lpf1_sel_g in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + *val = ctrl4_c.lpf1_sel_g; + + return ret; +} + +/** + * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends + * (XL and Gyro independently masked).[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of drdy_mask in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhb_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret == 0) + { + ctrl4_c.drdy_mask = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + } + return ret; +} + +/** + * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends + * (XL and Gyro independently masked).[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of drdy_mask in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_filter_settling_mask_get(stmdev_ctx_t *ctx, + uint8_t *val) +{ + asm330lhb_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + *val = ctrl4_c.drdy_mask; + + return ret; +} + +/** + * @brief Gyroscope low pass filter 1 bandwidth.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of ftype in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, + asm330lhb_ftype_t val) +{ + asm330lhb_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret == 0) + { + ctrl6_c.ftype = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + } + return ret; +} + +/** + * @brief Gyroscope low pass filter 1 bandwidth.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of ftype in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, + asm330lhb_ftype_t *val) +{ + asm330lhb_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + + switch (ctrl6_c.ftype) + { + case ASM330LHB_ULTRA_LIGHT: + *val = ASM330LHB_ULTRA_LIGHT; + break; + case ASM330LHB_VERY_LIGHT: + *val = ASM330LHB_VERY_LIGHT; + break; + case ASM330LHB_LIGHT: + *val = ASM330LHB_LIGHT; + break; + case ASM330LHB_MEDIUM: + *val = ASM330LHB_MEDIUM; + break; + case ASM330LHB_STRONG: + *val = ASM330LHB_STRONG; + break; + case ASM330LHB_VERY_STRONG: + *val = ASM330LHB_VERY_STRONG; + break; + case ASM330LHB_AGGRESSIVE: + *val = ASM330LHB_AGGRESSIVE; + break; + case ASM330LHB_XTREME: + *val = ASM330LHB_XTREME; + break; + default: + *val = ASM330LHB_ULTRA_LIGHT; + break; + } + return ret; +} + +/** + * @brief Low pass filter 2 on 6D function selection.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of low_pass_on_6d in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhb_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret == 0) + { + ctrl8_xl.low_pass_on_6d = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL8_XL, + (uint8_t *)&ctrl8_xl, 1); + } + return ret; +} + +/** + * @brief Low pass filter 2 on 6D function selection.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of low_pass_on_6d in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + *val = ctrl8_xl.low_pass_on_6d; + + return ret; +} + +/** + * @brief Accelerometer slope filter / high-pass filter selection + * on output.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of hp_slope_xl_en in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, + asm330lhb_hp_slope_xl_en_t val) +{ + asm330lhb_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret == 0) + { + ctrl8_xl.hp_slope_xl_en = (((uint8_t)val & 0x10U) >> 4); + ctrl8_xl.hp_ref_mode_xl = (((uint8_t)val & 0x20U) >> 5); + ctrl8_xl.hpcf_xl = (uint8_t)val & 0x07U; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL8_XL, + (uint8_t *)&ctrl8_xl, 1); + } + return ret; +} + +/** + * @brief Accelerometer slope filter / high-pass filter selection on + * output.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of hp_slope_xl_en in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, + asm330lhb_hp_slope_xl_en_t *val) +{ + asm330lhb_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + switch (((ctrl8_xl.hp_ref_mode_xl << 5) + (ctrl8_xl.hp_slope_xl_en << 4) + + ctrl8_xl.hpcf_xl)) + { + case ASM330LHB_HP_PATH_DISABLE_ON_OUT: + *val = ASM330LHB_HP_PATH_DISABLE_ON_OUT; + break; + case ASM330LHB_SLOPE_ODR_DIV_4: + *val = ASM330LHB_SLOPE_ODR_DIV_4; + break; + case ASM330LHB_HP_ODR_DIV_10: + *val = ASM330LHB_HP_ODR_DIV_10; + break; + case ASM330LHB_HP_ODR_DIV_20: + *val = ASM330LHB_HP_ODR_DIV_20; + break; + case ASM330LHB_HP_ODR_DIV_45: + *val = ASM330LHB_HP_ODR_DIV_45; + break; + case ASM330LHB_HP_ODR_DIV_100: + *val = ASM330LHB_HP_ODR_DIV_100; + break; + case ASM330LHB_HP_ODR_DIV_200: + *val = ASM330LHB_HP_ODR_DIV_200; + break; + case ASM330LHB_HP_ODR_DIV_400: + *val = ASM330LHB_HP_ODR_DIV_400; + break; + case ASM330LHB_HP_ODR_DIV_800: + *val = ASM330LHB_HP_ODR_DIV_800; + break; + case ASM330LHB_HP_REF_MD_ODR_DIV_10: + *val = ASM330LHB_HP_REF_MD_ODR_DIV_10; + break; + case ASM330LHB_HP_REF_MD_ODR_DIV_20: + *val = ASM330LHB_HP_REF_MD_ODR_DIV_20; + break; + case ASM330LHB_HP_REF_MD_ODR_DIV_45: + *val = ASM330LHB_HP_REF_MD_ODR_DIV_45; + break; + case ASM330LHB_HP_REF_MD_ODR_DIV_100: + *val = ASM330LHB_HP_REF_MD_ODR_DIV_100; + break; + case ASM330LHB_HP_REF_MD_ODR_DIV_200: + *val = ASM330LHB_HP_REF_MD_ODR_DIV_200; + break; + case ASM330LHB_HP_REF_MD_ODR_DIV_400: + *val = ASM330LHB_HP_REF_MD_ODR_DIV_400; + break; + case ASM330LHB_HP_REF_MD_ODR_DIV_800: + *val = ASM330LHB_HP_REF_MD_ODR_DIV_800; + break; + case ASM330LHB_LP_ODR_DIV_10: + *val = ASM330LHB_LP_ODR_DIV_10; + break; + case ASM330LHB_LP_ODR_DIV_20: + *val = ASM330LHB_LP_ODR_DIV_20; + break; + case ASM330LHB_LP_ODR_DIV_45: + *val = ASM330LHB_LP_ODR_DIV_45; + break; + case ASM330LHB_LP_ODR_DIV_100: + *val = ASM330LHB_LP_ODR_DIV_100; + break; + case ASM330LHB_LP_ODR_DIV_200: + *val = ASM330LHB_LP_ODR_DIV_200; + break; + case ASM330LHB_LP_ODR_DIV_400: + *val = ASM330LHB_LP_ODR_DIV_400; + break; + case ASM330LHB_LP_ODR_DIV_800: + *val = ASM330LHB_LP_ODR_DIV_800; + break; + default: + *val = ASM330LHB_HP_PATH_DISABLE_ON_OUT; + break; + } + return ret; +} + +/** + * @brief Enables accelerometer LPF2 and HPF fast-settling mode. + * The filter sets the second samples after writing this bit. + * Active only during device exit from powerdown mode.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fastsettl_mode_xl in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhb_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret == 0) + { + ctrl8_xl.fastsettl_mode_xl = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL8_XL, + (uint8_t *)&ctrl8_xl, 1); + } + return ret; +} + +/** + * @brief Enables accelerometer LPF2 and HPF fast-settling mode. + * The filter sets the second samples after writing + * this bit. Active only during device exit from powerdown mode.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fastsettl_mode_xl in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + *val = ctrl8_xl.fastsettl_mode_xl; + + return ret; +} + +/** + * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity + * functions.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of slope_fds in reg INT_CFG0 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_xl_hp_path_internal_set(stmdev_ctx_t *ctx, + asm330lhb_slope_fds_t val) +{ + asm330lhb_int_cfg0_t int_cfg0; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG0, (uint8_t *)&int_cfg0, 1); + if (ret == 0) + { + int_cfg0.slope_fds = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_INT_CFG0, + (uint8_t *)&int_cfg0, 1); + } + return ret; +} + +/** + * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity + * functions.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of slope_fds in reg INT_CFG0 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_xl_hp_path_internal_get(stmdev_ctx_t *ctx, + asm330lhb_slope_fds_t *val) +{ + asm330lhb_int_cfg0_t int_cfg0; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG0, (uint8_t *)&int_cfg0, 1); + switch (int_cfg0.slope_fds) + { + case ASM330LHB_USE_SLOPE: + *val = ASM330LHB_USE_SLOPE; + break; + case ASM330LHB_USE_HPF: + *val = ASM330LHB_USE_HPF; + break; + default: + *val = ASM330LHB_USE_SLOPE; + break; + } + return ret; +} + +/** + * @brief Enables gyroscope digital high-pass filter. The filter is enabled + * only if the gyro is in HP mode.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of hp_en_g and hp_en_g in reg CTRL7_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_gy_hp_path_internal_set(stmdev_ctx_t *ctx, + asm330lhb_hpm_g_t val) +{ + asm330lhb_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret == 0) + { + ctrl7_g.hp_en_g = (((uint8_t)val & 0x80U) >> 7); + ctrl7_g.hpm_g = (uint8_t)val & 0x03U; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + } + return ret; +} + +/** + * @brief Enables gyroscope digital high-pass filter. The filter is + * enabled only if the gyro is in HP mode.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of hp_en_g and hp_en_g in reg CTRL7_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_gy_hp_path_internal_get(stmdev_ctx_t *ctx, + asm330lhb_hpm_g_t *val) +{ + asm330lhb_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + + switch ((ctrl7_g.hp_en_g << 7) + ctrl7_g.hpm_g) + { + case ASM330LHB_HP_FILTER_NONE: + *val = ASM330LHB_HP_FILTER_NONE; + break; + case ASM330LHB_HP_FILTER_16mHz: + *val = ASM330LHB_HP_FILTER_16mHz; + break; + case ASM330LHB_HP_FILTER_65mHz: + *val = ASM330LHB_HP_FILTER_65mHz; + break; + case ASM330LHB_HP_FILTER_260mHz: + *val = ASM330LHB_HP_FILTER_260mHz; + break; + case ASM330LHB_HP_FILTER_1Hz04: + *val = ASM330LHB_HP_FILTER_1Hz04; + break; + default: + *val = ASM330LHB_HP_FILTER_NONE; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHB_ serial_interface + * @brief This section groups all the functions concerning main + * serial interface management (not auxiliary) + * @{ + * + */ + +/** + * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of sdo_pu_en in reg PIN_CTRL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_sdo_sa0_mode_set(stmdev_ctx_t *ctx, + asm330lhb_sdo_pu_en_t val) +{ + asm330lhb_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret == 0) + { + pin_ctrl.sdo_pu_en = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + return ret; +} + +/** + * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of sdo_pu_en in reg PIN_CTRL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_sdo_sa0_mode_get(stmdev_ctx_t *ctx, + asm330lhb_sdo_pu_en_t *val) +{ + asm330lhb_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + + switch (pin_ctrl.sdo_pu_en) + { + case ASM330LHB_PULL_UP_DISC: + *val = ASM330LHB_PULL_UP_DISC; + break; + case ASM330LHB_PULL_UP_CONNECT: + *val = ASM330LHB_PULL_UP_CONNECT; + break; + default: + *val = ASM330LHB_PULL_UP_DISC; + break; + } + return ret; +} + +/** + * @brief Connect/Disconnect INT1 pull-down.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of pd_dis_int1 in reg I3C_BUS_AVB + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_int1_mode_set(stmdev_ctx_t *ctx, + asm330lhb_pd_dis_int1_t val) +{ + asm330lhb_i3c_bus_avb_t i3c_bus_avb; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_I3C_BUS_AVB, (uint8_t *)&i3c_bus_avb, 1); + if (ret == 0) + { + i3c_bus_avb.pd_dis_int1 = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_I3C_BUS_AVB, + (uint8_t *)&i3c_bus_avb, 1); + } + return ret; +} + +/** + * @brief Connect/Disconnect INT1 pull-down.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of pd_dis_int1 in reg I3C_BUS_AVB + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_int1_mode_get(stmdev_ctx_t *ctx, + asm330lhb_pd_dis_int1_t *val) +{ + asm330lhb_i3c_bus_avb_t i3c_bus_avb; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_I3C_BUS_AVB, (uint8_t *)&i3c_bus_avb, 1); + + switch (i3c_bus_avb.pd_dis_int1) + { + case ASM330LHB_PULL_DOWN_CONNECT: + *val = ASM330LHB_PULL_DOWN_CONNECT; + break; + case ASM330LHB_PULL_DOWN_DISC: + *val = ASM330LHB_PULL_DOWN_DISC; + break; + default: + *val = ASM330LHB_PULL_DOWN_CONNECT; + break; + } + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of sim in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_spi_mode_set(stmdev_ctx_t *ctx, asm330lhb_sim_t val) +{ + asm330lhb_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret == 0) + { + ctrl3_c.sim = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of sim in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_spi_mode_get(stmdev_ctx_t *ctx, asm330lhb_sim_t *val) +{ + asm330lhb_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + switch (ctrl3_c.sim) + { + case ASM330LHB_SPI_4_WIRE: + *val = ASM330LHB_SPI_4_WIRE; + break; + case ASM330LHB_SPI_3_WIRE: + *val = ASM330LHB_SPI_3_WIRE; + break; + default: + *val = ASM330LHB_SPI_4_WIRE; + break; + } + return ret; +} + +/** + * @brief Disable / Enable I2C interface.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of i2c_disable in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_i2c_interface_set(stmdev_ctx_t *ctx, + asm330lhb_i2c_disable_t val) +{ + asm330lhb_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret == 0) + { + ctrl4_c.i2c_disable = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + } + return ret; +} + +/** + * @brief Disable / Enable I2C interface.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of i2c reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_i2c_interface_get(stmdev_ctx_t *ctx, + asm330lhb_i2c_disable_t *val) +{ + asm330lhb_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + + switch (ctrl4_c.i2c_disable) + { + case ASM330LHB_I2C_ENABLE: + *val = ASM330LHB_I2C_ENABLE; + break; + case ASM330LHB_I2C_DISABLE: + *val = ASM330LHB_I2C_DISABLE; + break; + default: + *val = ASM330LHB_I2C_ENABLE; + break; + } + return ret; +} + +/** + * @brief I3C Enable/Disable communication protocol.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of i3c_disable in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_i3c_disable_set(stmdev_ctx_t *ctx, + asm330lhb_i3c_disable_t val) +{ + asm330lhb_ctrl9_xl_t ctrl9_xl; + asm330lhb_i3c_bus_avb_t i3c_bus_avb; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret == 0) + { + ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL9_XL, + (uint8_t *)&ctrl9_xl, 1); + } + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_I3C_BUS_AVB, + (uint8_t *)&i3c_bus_avb, 1); + } + if (ret == 0) + { + i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U; + ret = asm330lhb_write_reg(ctx, ASM330LHB_I3C_BUS_AVB, + (uint8_t *)&i3c_bus_avb, 1); + } + return ret; +} + +/** + * @brief I3C Enable/Disable communication protocol.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of i3c_disable in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_i3c_disable_get(stmdev_ctx_t *ctx, + asm330lhb_i3c_disable_t *val) +{ + asm330lhb_ctrl9_xl_t ctrl9_xl; + asm330lhb_i3c_bus_avb_t i3c_bus_avb; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_I3C_BUS_AVB, + (uint8_t *)&i3c_bus_avb, 1); + } + switch ((ctrl9_xl.i3c_disable << 7) + i3c_bus_avb.i3c_bus_avb_sel) + { + case ASM330LHB_I3C_DISABLE: + *val = ASM330LHB_I3C_DISABLE; + break; + case ASM330LHB_I3C_ENABLE_T_50us: + *val = ASM330LHB_I3C_ENABLE_T_50us; + break; + case ASM330LHB_I3C_ENABLE_T_2us: + *val = ASM330LHB_I3C_ENABLE_T_2us; + break; + case ASM330LHB_I3C_ENABLE_T_1ms: + *val = ASM330LHB_I3C_ENABLE_T_1ms; + break; + case ASM330LHB_I3C_ENABLE_T_25ms: + *val = ASM330LHB_I3C_ENABLE_T_25ms; + break; + default: + *val = ASM330LHB_I3C_DISABLE; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHB_interrupt_pins + * @brief This section groups all the functions that manage + * interrupt pins + * @{ + * + */ + +/** + * @brief Select the signal that need to route on int1 pad.[set] + * + * @param ctx read / write interface definitions + * @param val struct of registers: INT1_CTRL, + * MD1_CFG, EMB_FUNC_INT1, FSM_INT1_A, + * FSM_INT1_B + * + */ +int32_t asm330lhb_pin_int1_route_set(stmdev_ctx_t *ctx, + asm330lhb_pin_int1_route_t *val) +{ + asm330lhb_pin_int2_route_t pin_int2_route; + asm330lhb_int_cfg1_t int_cfg1; + int32_t ret; + + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhb_write_reg(ctx, ASM330LHB_MLC_INT1, + (uint8_t *)&val->mlc_int1, 1); + } + if (ret == 0) + { + ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_INT1, + (uint8_t *)&val->emb_func_int1, 1); + } + if (ret == 0) + { + ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_INT1_A, + (uint8_t *)&val->fsm_int1_a, 1); + } + if (ret == 0) + { + ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_INT1_B, + (uint8_t *)&val->fsm_int1_b, 1); + } + if (ret == 0) + { + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + } + + if (ret == 0) + { + if ((val->emb_func_int1.int1_fsm_lc + | val->fsm_int1_a.int1_fsm1 + | val->fsm_int1_a.int1_fsm2 + | val->fsm_int1_a.int1_fsm3 + | val->fsm_int1_a.int1_fsm4 + | val->fsm_int1_a.int1_fsm5 + | val->fsm_int1_a.int1_fsm6 + | val->fsm_int1_a.int1_fsm7 + | val->fsm_int1_a.int1_fsm8 + | val->fsm_int1_b.int1_fsm9 + | val->fsm_int1_b.int1_fsm10 + | val->fsm_int1_b.int1_fsm11 + | val->fsm_int1_b.int1_fsm12 + | val->fsm_int1_b.int1_fsm13 + | val->fsm_int1_b.int1_fsm14 + | val->fsm_int1_b.int1_fsm15 + | val->fsm_int1_b.int1_fsm16 + | val->mlc_int1.int1_mlc1 + | val->mlc_int1.int1_mlc2 + | val->mlc_int1.int1_mlc3 + | val->mlc_int1.int1_mlc4 + | val->mlc_int1.int1_mlc5 + | val->mlc_int1.int1_mlc6 + | val->mlc_int1.int1_mlc7 + | val->mlc_int1.int1_mlc8) != PROPERTY_DISABLE) + { + val->md1_cfg.int1_emb_func = PROPERTY_ENABLE; + } + else + { + val->md1_cfg.int1_emb_func = PROPERTY_DISABLE; + } + ret = asm330lhb_write_reg(ctx, ASM330LHB_INT1_CTRL, + (uint8_t *)&val->int1_ctrl, 1); + } + if (ret == 0) + { + ret = asm330lhb_write_reg(ctx, ASM330LHB_MD1_CFG, (uint8_t *)&val->md1_cfg, 1); + } + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG1, (uint8_t *) &int_cfg1, 1); + } + + if (ret == 0) + { + ret = asm330lhb_pin_int2_route_get(ctx, &pin_int2_route); + } + if (ret == 0) + { + if ((pin_int2_route.int2_ctrl.int2_cnt_bdr + | pin_int2_route.int2_ctrl.int2_drdy_g + | pin_int2_route.int2_ctrl.int2_drdy_temp + | pin_int2_route.int2_ctrl.int2_drdy_xl + | pin_int2_route.int2_ctrl.int2_fifo_full + | pin_int2_route.int2_ctrl.int2_fifo_ovr + | pin_int2_route.int2_ctrl.int2_fifo_th + | pin_int2_route.md2_cfg.int2_6d + | pin_int2_route.md2_cfg.int2_ff + | pin_int2_route.md2_cfg.int2_wu + | pin_int2_route.md2_cfg.int2_sleep_change + | val->int1_ctrl.den_drdy_flag + | val->int1_ctrl.int1_boot + | val->int1_ctrl.int1_cnt_bdr + | val->int1_ctrl.int1_drdy_g + | val->int1_ctrl.int1_drdy_xl + | val->int1_ctrl.int1_fifo_full + | val->int1_ctrl.int1_fifo_ovr + | val->int1_ctrl.int1_fifo_th + | val->md1_cfg.int1_6d + | val->md1_cfg.int1_ff + | val->md1_cfg.int1_wu + | val->md1_cfg.int1_sleep_change) != PROPERTY_DISABLE) + { + int_cfg1.interrupts_enable = PROPERTY_ENABLE; + } + else + { + int_cfg1.interrupts_enable = PROPERTY_DISABLE; + } + ret = asm330lhb_write_reg(ctx, ASM330LHB_INT_CFG1, (uint8_t *) &int_cfg1, 1); + } + return ret; +} + +/** + * @brief Select the signal that need to route on int1 pad.[get] + * + * @param ctx read / write interface definitions + * @param val struct of registers: INT1_CTRL, MD1_CFG, + * EMB_FUNC_INT1, FSM_INT1_A, FSM_INT1_B + * + */ +int32_t asm330lhb_pin_int1_route_get(stmdev_ctx_t *ctx, + asm330lhb_pin_int1_route_t *val) +{ + int32_t ret; + + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_MLC_INT1, + (uint8_t *)&val->mlc_int1, 1); + } + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INT1, + (uint8_t *)&val->emb_func_int1, 1); + } + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_INT1_A, + (uint8_t *)&val->fsm_int1_a, 1); + } + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_INT1_B, + (uint8_t *)&val->fsm_int1_b, 1); + } + if (ret == 0) + { + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + } + if (ret == 0) + { + + ret = asm330lhb_read_reg(ctx, ASM330LHB_INT1_CTRL, + (uint8_t *)&val->int1_ctrl, 1); + } + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_MD1_CFG, (uint8_t *)&val->md1_cfg, 1); + } + + return ret; +} + +/** + * @brief Select the signal that need to route on int2 pad.[set] + * + * @param ctx read / write interface definitions + * @param val union of registers INT2_CTRL, MD2_CFG, + * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B + * + */ +int32_t asm330lhb_pin_int2_route_set(stmdev_ctx_t *ctx, + asm330lhb_pin_int2_route_t *val) +{ + asm330lhb_pin_int1_route_t pin_int1_route; + asm330lhb_int_cfg1_t int_cfg1; + int32_t ret; + + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhb_write_reg(ctx, ASM330LHB_MLC_INT2, + (uint8_t *)&val->mlc_int2, 1); + } + if (ret == 0) + { + ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_INT2, + (uint8_t *)&val->emb_func_int2, 1); + } + if (ret == 0) + { + ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_INT2_A, + (uint8_t *)&val->fsm_int2_a, 1); + } + if (ret == 0) + { + ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_INT2_B, + (uint8_t *)&val->fsm_int2_b, 1); + } + if (ret == 0) + { + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + } + + if (ret == 0) + { + if ((val->emb_func_int2.int2_fsm_lc + | val->fsm_int2_a.int2_fsm1 + | val->fsm_int2_a.int2_fsm2 + | val->fsm_int2_a.int2_fsm3 + | val->fsm_int2_a.int2_fsm4 + | val->fsm_int2_a.int2_fsm5 + | val->fsm_int2_a.int2_fsm6 + | val->fsm_int2_a.int2_fsm7 + | val->fsm_int2_a.int2_fsm8 + | val->fsm_int2_b.int2_fsm9 + | val->fsm_int2_b.int2_fsm10 + | val->fsm_int2_b.int2_fsm11 + | val->fsm_int2_b.int2_fsm12 + | val->fsm_int2_b.int2_fsm13 + | val->fsm_int2_b.int2_fsm14 + | val->fsm_int2_b.int2_fsm15 + | val->fsm_int2_b.int2_fsm16 + | val->mlc_int2.int2_mlc1 + | val->mlc_int2.int2_mlc2 + | val->mlc_int2.int2_mlc3 + | val->mlc_int2.int2_mlc4 + | val->mlc_int2.int2_mlc5 + | val->mlc_int2.int2_mlc6 + | val->mlc_int2.int2_mlc7 + | val->mlc_int2.int2_mlc8) != PROPERTY_DISABLE) + { + val->md2_cfg.int2_emb_func = PROPERTY_ENABLE; + } + else + { + val->md2_cfg.int2_emb_func = PROPERTY_DISABLE; + } + ret = asm330lhb_write_reg(ctx, ASM330LHB_INT2_CTRL, + (uint8_t *)&val->int2_ctrl, 1); + } + if (ret == 0) + { + ret = asm330lhb_write_reg(ctx, ASM330LHB_MD2_CFG, (uint8_t *)&val->md2_cfg, 1); + } + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG1, (uint8_t *) &int_cfg1, 1); + } + + if (ret == 0) + { + ret = asm330lhb_pin_int1_route_get(ctx, &pin_int1_route); + } + + if (ret == 0) + { + if ((val->int2_ctrl.int2_cnt_bdr + | val->int2_ctrl.int2_drdy_g + | val->int2_ctrl.int2_drdy_temp + | val->int2_ctrl.int2_drdy_xl + | val->int2_ctrl.int2_fifo_full + | val->int2_ctrl.int2_fifo_ovr + | val->int2_ctrl.int2_fifo_th + | val->md2_cfg.int2_6d + | val->md2_cfg.int2_ff + | val->md2_cfg.int2_wu + | val->md2_cfg.int2_sleep_change + | pin_int1_route.int1_ctrl.den_drdy_flag + | pin_int1_route.int1_ctrl.int1_boot + | pin_int1_route.int1_ctrl.int1_cnt_bdr + | pin_int1_route.int1_ctrl.int1_drdy_g + | pin_int1_route.int1_ctrl.int1_drdy_xl + | pin_int1_route.int1_ctrl.int1_fifo_full + | pin_int1_route.int1_ctrl.int1_fifo_ovr + | pin_int1_route.int1_ctrl.int1_fifo_th + | pin_int1_route.md1_cfg.int1_6d + | pin_int1_route.md1_cfg.int1_ff + | pin_int1_route.md1_cfg.int1_wu + | pin_int1_route.md1_cfg.int1_sleep_change) != PROPERTY_DISABLE) + { + int_cfg1.interrupts_enable = PROPERTY_ENABLE; + } + else + { + int_cfg1.interrupts_enable = PROPERTY_DISABLE; + } + ret = asm330lhb_write_reg(ctx, ASM330LHB_INT_CFG1, (uint8_t *) &int_cfg1, 1); + } + return ret; +} + +/** + * @brief Select the signal that need to route on int2 pad.[get] + * + * @param ctx read / write interface definitions + * @param val union of registers INT2_CTRL, MD2_CFG, + * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B + * + */ +int32_t asm330lhb_pin_int2_route_get(stmdev_ctx_t *ctx, + asm330lhb_pin_int2_route_t *val) +{ + int32_t ret; + + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_MLC_INT2, + (uint8_t *)&val->mlc_int2, 1); + } + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INT2, + (uint8_t *)&val->emb_func_int2, 1); + } + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_INT2_A, + (uint8_t *)&val->fsm_int2_a, 1); + } + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_INT2_B, + (uint8_t *)&val->fsm_int2_b, 1); + } + if (ret == 0) + { + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + } + if (ret == 0) + { + + ret = asm330lhb_read_reg(ctx, ASM330LHB_INT2_CTRL, + (uint8_t *)&val->int2_ctrl, 1); + } + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_MD2_CFG, (uint8_t *)&val->md2_cfg, 1); + } + return ret; +} + +/** + * @brief Push-pull/open drain selection on interrupt pads.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of pp_od in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_pin_mode_set(stmdev_ctx_t *ctx, asm330lhb_pp_od_t val) +{ + asm330lhb_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret == 0) + { + ctrl3_c.pp_od = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Push-pull/open drain selection on interrupt pads.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of pp_od in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_pin_mode_get(stmdev_ctx_t *ctx, asm330lhb_pp_od_t *val) +{ + asm330lhb_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + switch (ctrl3_c.pp_od) + { + case ASM330LHB_PUSH_PULL: + *val = ASM330LHB_PUSH_PULL; + break; + case ASM330LHB_OPEN_DRAIN: + *val = ASM330LHB_OPEN_DRAIN; + break; + default: + *val = ASM330LHB_PUSH_PULL; + break; + } + return ret; +} + +/** + * @brief Interrupt active-high/low.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of h_lactive in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_pin_polarity_set(stmdev_ctx_t *ctx, + asm330lhb_h_lactive_t val) +{ + asm330lhb_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret == 0) + { + ctrl3_c.h_lactive = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Interrupt active-high/low.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of h_lactive in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_pin_polarity_get(stmdev_ctx_t *ctx, + asm330lhb_h_lactive_t *val) +{ + asm330lhb_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + switch (ctrl3_c.h_lactive) + { + case ASM330LHB_ACTIVE_HIGH: + *val = ASM330LHB_ACTIVE_HIGH; + break; + case ASM330LHB_ACTIVE_LOW: + *val = ASM330LHB_ACTIVE_LOW; + break; + default: + *val = ASM330LHB_ACTIVE_HIGH; + break; + } + return ret; +} + +/** + * @brief All interrupt signals become available on INT1 pin.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of int2_on_int1 in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhb_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret == 0) + { + ctrl4_c.int2_on_int1 = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + } + return ret; +} + +/** + * @brief All interrupt signals become available on INT1 pin.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of int2_on_int1 in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + *val = ctrl4_c.int2_on_int1; + + return ret; +} + +/** + * @brief All interrupt signals notification mode.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of lir in reg INT_CFG0 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_int_notification_set(stmdev_ctx_t *ctx, + asm330lhb_lir_t val) +{ + asm330lhb_int_cfg0_t int_cfg0; + asm330lhb_page_rw_t page_rw; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG0, (uint8_t *)&int_cfg0, 1); + if (ret == 0) + { + int_cfg0.lir = (uint8_t)val & 0x01U; + int_cfg0.int_clr_on_read = (uint8_t)val & 0x01U; + ret = asm330lhb_write_reg(ctx, ASM330LHB_INT_CFG0, + (uint8_t *)&int_cfg0, 1); + } + if (ret == 0) + { + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + } + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; + ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + } + return ret; +} + +/** + * @brief All interrupt signals notification mode.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of lir in reg INT_CFG0 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_int_notification_get(stmdev_ctx_t *ctx, + asm330lhb_lir_t *val) +{ + asm330lhb_int_cfg0_t int_cfg0; + asm330lhb_page_rw_t page_rw; + int32_t ret; + + *val = ASM330LHB_ALL_INT_PULSED; + ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG0, (uint8_t *)&int_cfg0, 1); + + if (ret == 0) + { + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + } + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + } + switch ((page_rw.emb_func_lir << 1) + int_cfg0.lir) + { + case ASM330LHB_ALL_INT_PULSED: + *val = ASM330LHB_ALL_INT_PULSED; + break; + case ASM330LHB_BASE_LATCHED_EMB_PULSED: + *val = ASM330LHB_BASE_LATCHED_EMB_PULSED; + break; + case ASM330LHB_BASE_PULSED_EMB_LATCHED: + *val = ASM330LHB_BASE_PULSED_EMB_LATCHED; + break; + case ASM330LHB_ALL_INT_LATCHED: + *val = ASM330LHB_ALL_INT_LATCHED; + break; + default: + *val = ASM330LHB_ALL_INT_PULSED; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHB_Wake_Up_event + * @brief This section groups all the functions that manage the + * Wake Up event generation. + * @{ + * + */ + +/** + * @brief Weight of 1 LSB of wakeup threshold.[set] + * 0: 1 LSB =FS_XL / 64 + * 1: 1 LSB = FS_XL / 256 + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of wake_ths_w in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_wkup_ths_weight_set(stmdev_ctx_t *ctx, + asm330lhb_wake_ths_w_t val) +{ + asm330lhb_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + wake_up_dur.wake_ths_w = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + } + return ret; +} + +/** + * @brief Weight of 1 LSB of wakeup threshold.[get] + * 0: 1 LSB =FS_XL / 64 + * 1: 1 LSB = FS_XL / 256 + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of wake_ths_w in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_wkup_ths_weight_get(stmdev_ctx_t *ctx, + asm330lhb_wake_ths_w_t *val) +{ + asm330lhb_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + + switch (wake_up_dur.wake_ths_w) + { + case ASM330LHB_LSb_FS_DIV_64: + *val = ASM330LHB_LSb_FS_DIV_64; + break; + case ASM330LHB_LSb_FS_DIV_256: + *val = ASM330LHB_LSb_FS_DIV_256; + break; + default: + *val = ASM330LHB_LSb_FS_DIV_64; + break; + } + return ret; +} + +/** + * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in + * WAKE_UP_DUR.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of wk_ths in reg WAKE_UP_THS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhb_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_THS, + (uint8_t *)&wake_up_ths, 1); + if (ret == 0) + { + wake_up_ths.wk_ths = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_WAKE_UP_THS, + (uint8_t *)&wake_up_ths, 1); + } + return ret; +} + +/** + * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in + * WAKE_UP_DUR.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of wk_ths in reg WAKE_UP_THS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_THS, + (uint8_t *)&wake_up_ths, 1); + *val = wake_up_ths.wk_ths; + + return ret; +} + +/** + * @brief Wake up duration event( 1LSb = 1 / ODR ).[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of usr_off_on_wu in reg WAKE_UP_THS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhb_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_THS, + (uint8_t *)&wake_up_ths, 1); + if (ret == 0) + { + wake_up_ths.usr_off_on_wu = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_WAKE_UP_THS, + (uint8_t *)&wake_up_ths, 1); + } + return ret; +} + +/** + * @brief Wake up duration event( 1LSb = 1 / ODR ).[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of usr_off_on_wu in reg WAKE_UP_THS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, + uint8_t *val) +{ + asm330lhb_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_THS, + (uint8_t *)&wake_up_ths, 1); + *val = wake_up_ths.usr_off_on_wu; + + return ret; +} + +/** + * @brief Wake up duration event(1LSb = 1 / ODR).[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of wake_dur in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhb_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + wake_up_dur.wake_dur = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + } + return ret; +} + +/** + * @brief Wake up duration event(1LSb = 1 / ODR).[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of wake_dur in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + *val = wake_up_dur.wake_dur; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHB_ Activity/Inactivity_detection + * @brief This section groups all the functions concerning + * activity/inactivity detection. + * @{ + * + */ + +/** + * @brief Enables gyroscope Sleep mode.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of sleep_g in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhb_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret == 0) + { + ctrl4_c.sleep_g = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + } + return ret; +} + +/** + * @brief Enables gyroscope Sleep mode.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of sleep_g in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + *val = ctrl4_c.sleep_g; + + return ret; +} + +/** + * @brief Drives the sleep status instead of sleep change on INT pins + * (only if INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits + * are enabled).[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of sleep_status_on_int in reg INT_CFG0 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_act_pin_notification_set(stmdev_ctx_t *ctx, + asm330lhb_sleep_status_on_int_t val) +{ + asm330lhb_int_cfg0_t int_cfg0; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG0, (uint8_t *)&int_cfg0, 1); + if (ret == 0) + { + int_cfg0. sleep_status_on_int = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_INT_CFG0, + (uint8_t *)&int_cfg0, 1); + } + return ret; +} + +/** + * @brief Drives the sleep status instead of sleep change on INT pins + * (only if INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits + * are enabled).[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of sleep_status_on_int in reg INT_CFG0 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_act_pin_notification_get(stmdev_ctx_t *ctx, + asm330lhb_sleep_status_on_int_t *val) +{ + asm330lhb_int_cfg0_t int_cfg0; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG0, (uint8_t *)&int_cfg0, 1); + switch (int_cfg0. sleep_status_on_int) + { + case ASM330LHB_DRIVE_SLEEP_CHG_EVENT: + *val = ASM330LHB_DRIVE_SLEEP_CHG_EVENT; + break; + case ASM330LHB_DRIVE_SLEEP_STATUS: + *val = ASM330LHB_DRIVE_SLEEP_STATUS; + break; + default: + *val = ASM330LHB_DRIVE_SLEEP_CHG_EVENT; + break; + } + return ret; +} + +/** + * @brief Enable inactivity function.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of inact_en in reg INT_CFG1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_act_mode_set(stmdev_ctx_t *ctx, asm330lhb_inact_en_t val) +{ + asm330lhb_int_cfg1_t int_cfg1; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG1, (uint8_t *)&int_cfg1, 1); + if (ret == 0) + { + int_cfg1.inact_en = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_INT_CFG1, (uint8_t *)&int_cfg1, 1); + } + return ret; +} + +/** + * @brief Enable inactivity function.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of inact_en in reg INT_CFG1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_act_mode_get(stmdev_ctx_t *ctx, + asm330lhb_inact_en_t *val) +{ + asm330lhb_int_cfg1_t int_cfg1; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG1, (uint8_t *)&int_cfg1, 1); + + switch (int_cfg1.inact_en) + { + case ASM330LHB_XL_AND_GY_NOT_AFFECTED: + *val = ASM330LHB_XL_AND_GY_NOT_AFFECTED; + break; + case ASM330LHB_XL_12Hz5_GY_NOT_AFFECTED: + *val = ASM330LHB_XL_12Hz5_GY_NOT_AFFECTED; + break; + case ASM330LHB_XL_12Hz5_GY_SLEEP: + *val = ASM330LHB_XL_12Hz5_GY_SLEEP; + break; + case ASM330LHB_XL_12Hz5_GY_PD: + *val = ASM330LHB_XL_12Hz5_GY_PD; + break; + default: + *val = ASM330LHB_XL_AND_GY_NOT_AFFECTED; + break; + } + return ret; +} + +/** + * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of sleep_dur in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhb_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + wake_up_dur.sleep_dur = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + } + return ret; +} + +/** + * @brief Duration to go in sleep mode.(1 LSb = 512 / ODR).[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of sleep_dur in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + *val = wake_up_dur.sleep_dur; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHB_ Six_position_detection(6D/4D) + * @brief This section groups all the functions concerning six + * position detection (6D). + * @{ + * + */ + +/** + * @brief Threshold for 4D/6D function.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of sixd_ths in reg TAP_THS_6D + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_6d_threshold_set(stmdev_ctx_t *ctx, + asm330lhb_sixd_ths_t val) +{ + asm330lhb_ths_6d_t ths_6d; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_THS_6D, + (uint8_t *)&ths_6d, 1); + if (ret == 0) + { + ths_6d.sixd_ths = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_THS_6D, + (uint8_t *)&ths_6d, 1); + } + return ret; +} + +/** + * @brief Threshold for 4D/6D function.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of sixd_ths in reg TAP_THS_6D + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_6d_threshold_get(stmdev_ctx_t *ctx, + asm330lhb_sixd_ths_t *val) +{ + asm330lhb_ths_6d_t ths_6d; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_THS_6D, + (uint8_t *)&ths_6d, 1); + + switch (ths_6d.sixd_ths) + { + case ASM330LHB_DEG_80: + *val = ASM330LHB_DEG_80; + break; + case ASM330LHB_DEG_70: + *val = ASM330LHB_DEG_70; + break; + case ASM330LHB_DEG_60: + *val = ASM330LHB_DEG_60; + break; + case ASM330LHB_DEG_50: + *val = ASM330LHB_DEG_50; + break; + default: + *val = ASM330LHB_DEG_80; + break; + } + return ret; +} + +/** + * @brief 4D orientation detection enable.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of d4d_en in reg TAP_THS_6D + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhb_ths_6d_t ths_6d; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_THS_6D, + (uint8_t *)&ths_6d, 1); + if (ret == 0) + { + ths_6d.d4d_en = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_THS_6D, + (uint8_t *)&ths_6d, 1); + } + return ret; +} + +/** + * @brief 4D orientation detection enable.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of d4d_en in reg TAP_THS_6D + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_ths_6d_t ths_6d; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_THS_6D, + (uint8_t *)&ths_6d, 1); + *val = ths_6d.d4d_en; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHB_free_fall + * @brief This section group all the functions concerning the free + * fall detection. + * @{ + * + */ + +/** + * @brief Free fall threshold setting.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of ff_ths in reg FREE_FALL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_ff_threshold_set(stmdev_ctx_t *ctx, + asm330lhb_ff_ths_t val) +{ + asm330lhb_free_fall_t free_fall; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret == 0) + { + free_fall.ff_ths = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_FREE_FALL, + (uint8_t *)&free_fall, 1); + } + return ret; +} + +/** + * @brief Free fall threshold setting.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of ff_ths in reg FREE_FALL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_ff_threshold_get(stmdev_ctx_t *ctx, + asm330lhb_ff_ths_t *val) +{ + asm330lhb_free_fall_t free_fall; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_FREE_FALL, (uint8_t *)&free_fall, 1); + + switch (free_fall.ff_ths) + { + case ASM330LHB_FF_TSH_156mg: + *val = ASM330LHB_FF_TSH_156mg; + break; + case ASM330LHB_FF_TSH_219mg: + *val = ASM330LHB_FF_TSH_219mg; + break; + case ASM330LHB_FF_TSH_250mg: + *val = ASM330LHB_FF_TSH_250mg; + break; + case ASM330LHB_FF_TSH_312mg: + *val = ASM330LHB_FF_TSH_312mg; + break; + case ASM330LHB_FF_TSH_344mg: + *val = ASM330LHB_FF_TSH_344mg; + break; + case ASM330LHB_FF_TSH_406mg: + *val = ASM330LHB_FF_TSH_406mg; + break; + case ASM330LHB_FF_TSH_469mg: + *val = ASM330LHB_FF_TSH_469mg; + break; + case ASM330LHB_FF_TSH_500mg: + *val = ASM330LHB_FF_TSH_500mg; + break; + default: + *val = ASM330LHB_FF_TSH_156mg; + break; + } + return ret; +} + +/** + * @brief Free-fall duration event(1LSb = 1 / ODR).[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of ff_dur in reg FREE_FALL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhb_wake_up_dur_t wake_up_dur; + asm330lhb_free_fall_t free_fall; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + wake_up_dur.ff_dur = (val & 0x20U) >> 5; + ret = asm330lhb_write_reg(ctx, ASM330LHB_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + } + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_FREE_FALL, + (uint8_t *)&free_fall, 1); + } + if (ret == 0) + { + free_fall.ff_dur = val & 0x1FU; + ret = asm330lhb_write_reg(ctx, ASM330LHB_FREE_FALL, + (uint8_t *)&free_fall, 1); + } + return ret; +} + +/** + * @brief Free-fall duration event(1LSb = 1 / ODR).[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of ff_dur in reg FREE_FALL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_wake_up_dur_t wake_up_dur; + asm330lhb_free_fall_t free_fall; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_FREE_FALL, + (uint8_t *)&free_fall, 1); + } + *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHB_fifo + * @brief This section group all the functions concerning + * the fifo usage + * @{ + * + */ + +/** + * @brief FIFO watermark level selection.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of wtm in reg FIFO_CTRL1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) +{ + asm330lhb_fifo_ctrl1_t fifo_ctrl1; + asm330lhb_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.wtm = (uint8_t)((val / 256U) & 0x01U); + ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + } + if (ret == 0) + { + fifo_ctrl1.wtm = (uint8_t)(val - (fifo_ctrl2.wtm * 256U)); + ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL1, + (uint8_t *)&fifo_ctrl1, 1); + } + + return ret; +} + +/** + * @brief FIFO watermark level selection.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of wtm in reg FIFO_CTRL1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + asm330lhb_fifo_ctrl1_t fifo_ctrl1; + asm330lhb_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL1, + (uint8_t *)&fifo_ctrl1, 1); + } + *val = fifo_ctrl2.wtm; + *val = (*val * 256U) + fifo_ctrl1.wtm; + return ret; +} + +/** + * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of odrchg_en in reg FIFO_CTRL2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, + uint8_t val) +{ + asm330lhb_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.odrchg_en = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of odrchg_en in reg FIFO_CTRL2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, + uint8_t *val) +{ + asm330lhb_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + *val = fifo_ctrl2.odrchg_en; + + return ret; +} + +/** + * @brief Sensing chain FIFO stop values memorization at threshold + * level.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of stop_on_wtm in reg FIFO_CTRL2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhb_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.stop_on_wtm = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + } + return ret; +} + +/** + * @brief Sensing chain FIFO stop values memorization at threshold + * level.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of stop_on_wtm in reg FIFO_CTRL2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + *val = fifo_ctrl2.stop_on_wtm; + + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for accelerometer data.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of bdr_xl in reg FIFO_CTRL3 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fifo_xl_batch_set(stmdev_ctx_t *ctx, + asm330lhb_bdr_xl_t val) +{ + asm330lhb_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL3, + (uint8_t *)&fifo_ctrl3, 1); + if (ret == 0) + { + fifo_ctrl3.bdr_xl = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL3, + (uint8_t *)&fifo_ctrl3, 1); + } + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for accelerometer data.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of bdr_xl in reg FIFO_CTRL3 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fifo_xl_batch_get(stmdev_ctx_t *ctx, + asm330lhb_bdr_xl_t *val) +{ + asm330lhb_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL3, + (uint8_t *)&fifo_ctrl3, 1); + + switch (fifo_ctrl3.bdr_xl) + { + case ASM330LHB_XL_NOT_BATCHED: + *val = ASM330LHB_XL_NOT_BATCHED; + break; + case ASM330LHB_XL_BATCHED_AT_12Hz5: + *val = ASM330LHB_XL_BATCHED_AT_12Hz5; + break; + case ASM330LHB_XL_BATCHED_AT_26Hz: + *val = ASM330LHB_XL_BATCHED_AT_26Hz; + break; + case ASM330LHB_XL_BATCHED_AT_52Hz: + *val = ASM330LHB_XL_BATCHED_AT_52Hz; + break; + case ASM330LHB_XL_BATCHED_AT_104Hz: + *val = ASM330LHB_XL_BATCHED_AT_104Hz; + break; + case ASM330LHB_XL_BATCHED_AT_208Hz: + *val = ASM330LHB_XL_BATCHED_AT_208Hz; + break; + case ASM330LHB_XL_BATCHED_AT_417Hz: + *val = ASM330LHB_XL_BATCHED_AT_417Hz; + break; + case ASM330LHB_XL_BATCHED_AT_833Hz: + *val = ASM330LHB_XL_BATCHED_AT_833Hz; + break; + case ASM330LHB_XL_BATCHED_AT_1667Hz: + *val = ASM330LHB_XL_BATCHED_AT_1667Hz; + break; + case ASM330LHB_XL_BATCHED_AT_1Hz6: + *val = ASM330LHB_XL_BATCHED_AT_1Hz6; + break; + default: + *val = ASM330LHB_XL_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for gyroscope data.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of bdr_gy in reg FIFO_CTRL3 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fifo_gy_batch_set(stmdev_ctx_t *ctx, + asm330lhb_bdr_gy_t val) +{ + asm330lhb_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL3, + (uint8_t *)&fifo_ctrl3, 1); + if (ret == 0) + { + fifo_ctrl3.bdr_gy = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL3, + (uint8_t *)&fifo_ctrl3, 1); + } + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for gyroscope data.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of bdr_gy in reg FIFO_CTRL3 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fifo_gy_batch_get(stmdev_ctx_t *ctx, + asm330lhb_bdr_gy_t *val) +{ + asm330lhb_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL3, + (uint8_t *)&fifo_ctrl3, 1); + + switch (fifo_ctrl3.bdr_gy) + { + case ASM330LHB_GY_NOT_BATCHED: + *val = ASM330LHB_GY_NOT_BATCHED; + break; + case ASM330LHB_GY_BATCHED_AT_12Hz5: + *val = ASM330LHB_GY_BATCHED_AT_12Hz5; + break; + case ASM330LHB_GY_BATCHED_AT_26Hz: + *val = ASM330LHB_GY_BATCHED_AT_26Hz; + break; + case ASM330LHB_GY_BATCHED_AT_52Hz: + *val = ASM330LHB_GY_BATCHED_AT_52Hz; + break; + case ASM330LHB_GY_BATCHED_AT_104Hz: + *val = ASM330LHB_GY_BATCHED_AT_104Hz; + break; + case ASM330LHB_GY_BATCHED_AT_208Hz: + *val = ASM330LHB_GY_BATCHED_AT_208Hz; + break; + case ASM330LHB_GY_BATCHED_AT_417Hz: + *val = ASM330LHB_GY_BATCHED_AT_417Hz; + break; + case ASM330LHB_GY_BATCHED_AT_833Hz: + *val = ASM330LHB_GY_BATCHED_AT_833Hz; + break; + case ASM330LHB_GY_BATCHED_AT_1667Hz: + *val = ASM330LHB_GY_BATCHED_AT_1667Hz; + break; + case ASM330LHB_GY_BATCHED_AT_6Hz5: + *val = ASM330LHB_GY_BATCHED_AT_6Hz5; + break; + default: + *val = ASM330LHB_GY_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief FIFO mode selection.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fifo_mode in reg FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fifo_mode_set(stmdev_ctx_t *ctx, + asm330lhb_fifo_mode_t val) +{ + asm330lhb_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.fifo_mode = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + } + return ret; +} + +/** + * @brief FIFO mode selection.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of fifo_mode in reg FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fifo_mode_get(stmdev_ctx_t *ctx, + asm330lhb_fifo_mode_t *val) +{ + asm330lhb_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + + switch (fifo_ctrl4.fifo_mode) + { + case ASM330LHB_BYPASS_MODE: + *val = ASM330LHB_BYPASS_MODE; + break; + case ASM330LHB_FIFO_MODE: + *val = ASM330LHB_FIFO_MODE; + break; + case ASM330LHB_STREAM_TO_FIFO_MODE: + *val = ASM330LHB_STREAM_TO_FIFO_MODE; + break; + case ASM330LHB_BYPASS_TO_STREAM_MODE: + *val = ASM330LHB_BYPASS_TO_STREAM_MODE; + break; + case ASM330LHB_STREAM_MODE: + *val = ASM330LHB_STREAM_MODE; + break; + case ASM330LHB_BYPASS_TO_FIFO_MODE: + *val = ASM330LHB_BYPASS_TO_FIFO_MODE; + break; + default: + *val = ASM330LHB_BYPASS_MODE; + break; + } + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for temperature data.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of odr_t_batch in reg FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fifo_temp_batch_set(stmdev_ctx_t *ctx, + asm330lhb_odr_t_batch_t val) +{ + asm330lhb_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.odr_t_batch = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + } + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for temperature data.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of odr_t_batch in reg FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fifo_temp_batch_get(stmdev_ctx_t *ctx, + asm330lhb_odr_t_batch_t *val) +{ + asm330lhb_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + + switch (fifo_ctrl4.odr_t_batch) + { + case ASM330LHB_TEMP_NOT_BATCHED: + *val = ASM330LHB_TEMP_NOT_BATCHED; + break; + case ASM330LHB_TEMP_BATCHED_AT_52Hz: + *val = ASM330LHB_TEMP_BATCHED_AT_52Hz; + break; + case ASM330LHB_TEMP_BATCHED_AT_12Hz5: + *val = ASM330LHB_TEMP_BATCHED_AT_12Hz5; + break; + case ASM330LHB_TEMP_BATCHED_AT_1Hz6: + *val = ASM330LHB_TEMP_BATCHED_AT_1Hz6; + break; + default: + *val = ASM330LHB_TEMP_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief Selects decimation for timestamp batching in FIFO. + * Writing rate will be the maximum rate between XL and + * GYRO BDR divided by decimation decoder.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of dec_ts_batch in reg FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, + asm330lhb_dec_ts_batch_t val) +{ + asm330lhb_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.dec_ts_batch = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + } + return ret; +} + +/** + * @brief Selects decimation for timestamp batching in FIFO. + * Writing rate will be the maximum rate between XL and + * GYRO BDR divided by decimation decoder.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of dec_ts_batch in reg + * FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, + asm330lhb_dec_ts_batch_t *val) +{ + asm330lhb_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + + switch (fifo_ctrl4.dec_ts_batch) + { + case ASM330LHB_NO_DECIMATION: + *val = ASM330LHB_NO_DECIMATION; + break; + case ASM330LHB_DEC_1: + *val = ASM330LHB_DEC_1; + break; + case ASM330LHB_DEC_8: + *val = ASM330LHB_DEC_8; + break; + case ASM330LHB_DEC_32: + *val = ASM330LHB_DEC_32; + break; + default: + *val = ASM330LHB_NO_DECIMATION; + break; + } + return ret; +} + +/** + * @brief Selects the trigger for the internal counter of batching events + * between XL and gyro.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of trig_counter_bdr in + * reg COUNTER_BDR_REG1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, + asm330lhb_trig_counter_bdr_t val) +{ + asm330lhb_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + if (ret == 0) + { + counter_bdr_reg1.trig_counter_bdr = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + } + return ret; +} + +/** + * @brief Selects the trigger for the internal counter of batching events + * between XL and gyro.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of trig_counter_bdr + * in reg COUNTER_BDR_REG1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, + asm330lhb_trig_counter_bdr_t *val) +{ + asm330lhb_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + + switch (counter_bdr_reg1.trig_counter_bdr) + { + case ASM330LHB_XL_BATCH_EVENT: + *val = ASM330LHB_XL_BATCH_EVENT; + break; + case ASM330LHB_GYRO_BATCH_EVENT: + *val = ASM330LHB_GYRO_BATCH_EVENT; + break; + default: + *val = ASM330LHB_XL_BATCH_EVENT; + break; + } + return ret; +} + +/** + * @brief Resets the internal counter of batching events for a single sensor. + * This bit is automatically reset to zero if it was set to ‘1’.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of rst_counter_bdr in reg COUNTER_BDR_REG1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhb_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + if (ret == 0) + { + counter_bdr_reg1.rst_counter_bdr = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + } + return ret; +} + +/** + * @brief Resets the internal counter of batching events for a single sensor. + * This bit is automatically reset to zero if it was set to ‘1’.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of rst_counter_bdr in reg COUNTER_BDR_REG1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + *val = counter_bdr_reg1.rst_counter_bdr; + + return ret; +} + +/** + * @brief Batch data rate counter.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of cnt_bdr_th in reg COUNTER_BDR_REG2 + * and COUNTER_BDR_REG1. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_batch_counter_threshold_set(stmdev_ctx_t *ctx, uint16_t val) +{ + asm330lhb_counter_bdr_reg2_t counter_bdr_reg1; + asm330lhb_counter_bdr_reg2_t counter_bdr_reg2; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + if (ret == 0) + { + counter_bdr_reg1.cnt_bdr_th = (uint8_t)((val / 256U) & 0x07U); + ret = asm330lhb_write_reg(ctx, ASM330LHB_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + } + if (ret == 0) + { + counter_bdr_reg2.cnt_bdr_th = (uint8_t)(val - (counter_bdr_reg1.cnt_bdr_th * 256U)); + ret = asm330lhb_write_reg(ctx, ASM330LHB_COUNTER_BDR_REG2, + (uint8_t *)&counter_bdr_reg2, 1); + } + return ret; +} + +/** + * @brief Batch data rate counter.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of cnt_bdr_th in reg COUNTER_BDR_REG2 + * and COUNTER_BDR_REG1. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_batch_counter_threshold_get(stmdev_ctx_t *ctx, + uint16_t *val) +{ + asm330lhb_counter_bdr_reg1_t counter_bdr_reg1; + asm330lhb_counter_bdr_reg2_t counter_bdr_reg2; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG2, + (uint8_t *)&counter_bdr_reg2, 1); + } + + *val = counter_bdr_reg1.cnt_bdr_th; + *val = (*val * 256U) + counter_bdr_reg2.cnt_bdr_th; + return ret; +} + +/** + * @brief Number of unread sensor data (TAG + 6 bytes) stored in FIFO.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of diff_fifo in reg FIFO_STATUS1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + asm330lhb_fifo_status1_t fifo_status1; + asm330lhb_fifo_status2_t fifo_status2; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS1, + (uint8_t *)&fifo_status1, 1); + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS2, + (uint8_t *)&fifo_status2, 1); + + *val = fifo_status2.diff_fifo; + *val = (*val * 256U) + fifo_status1.diff_fifo; + } + return ret; +} + +/** + * @brief Smart FIFO status.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Registers FIFO_STATUS2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fifo_status_get(stmdev_ctx_t *ctx, + asm330lhb_fifo_status2_t *val) +{ + int32_t ret; + ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS2, (uint8_t *)val, 1); + return ret; +} + +/** + * @brief Smart FIFO full status.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fifo_full_ia in reg FIFO_STATUS2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_fifo_status2_t fifo_status2; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS2, + (uint8_t *)&fifo_status2, 1); + *val = fifo_status2.fifo_full_ia; + + return ret; +} + +/** + * @brief FIFO overrun status.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fifo_over_run_latched in + * reg FIFO_STATUS2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_fifo_status2_t fifo_status2; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS2, + (uint8_t *)&fifo_status2, 1); + *val = fifo_status2. fifo_ovr_ia; + + return ret; +} + +/** + * @brief FIFO watermark status.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fifo_wtm_ia in reg FIFO_STATUS2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_fifo_status2_t fifo_status2; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS2, + (uint8_t *)&fifo_status2, 1); + *val = fifo_status2.fifo_wtm_ia; + + return ret; +} + +/** + * @brief Identifies the sensor in FIFO_DATA_OUT.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of tag_sensor in reg FIFO_DATA_OUT_TAG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fifo_sensor_tag_get(stmdev_ctx_t *ctx, + asm330lhb_fifo_tag_t *val) +{ + asm330lhb_fifo_data_out_tag_t fifo_data_out_tag; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_DATA_OUT_TAG, + (uint8_t *)&fifo_data_out_tag, 1); + + switch (fifo_data_out_tag.tag_sensor) + { + case ASM330LHB_GYRO_NC_TAG: + *val = ASM330LHB_GYRO_NC_TAG; + break; + case ASM330LHB_XL_NC_TAG: + *val = ASM330LHB_XL_NC_TAG; + break; + case ASM330LHB_TEMPERATURE_TAG: + *val = ASM330LHB_TEMPERATURE_TAG; + break; + case ASM330LHB_TIMESTAMP_TAG: + *val = ASM330LHB_TIMESTAMP_TAG; + break; + case ASM330LHB_CFG_CHANGE_TAG: + *val = ASM330LHB_CFG_CHANGE_TAG; + break; + default: + *val = ASM330LHB_XL_NC_TAG; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHB_DEN_functionality + * @brief This section groups all the functions concerning + * DEN functionality. + * @{ + * + */ + +/** + * @brief DEN functionality marking mode.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of den_mode in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_den_mode_set(stmdev_ctx_t *ctx, asm330lhb_den_mode_t val) +{ + asm330lhb_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret == 0) + { + ctrl6_c.den_mode = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + } + return ret; +} + +/** + * @brief DEN functionality marking mode.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of den_mode in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_den_mode_get(stmdev_ctx_t *ctx, + asm330lhb_den_mode_t *val) +{ + asm330lhb_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + + switch (ctrl6_c.den_mode) + { + case ASM330LHB_DEN_DISABLE: + *val = ASM330LHB_DEN_DISABLE; + break; + case ASM330LHB_LEVEL_FIFO: + *val = ASM330LHB_LEVEL_FIFO; + break; + case ASM330LHB_LEVEL_LETCHED: + *val = ASM330LHB_LEVEL_LETCHED; + break; + case ASM330LHB_LEVEL_TRIGGER: + *val = ASM330LHB_LEVEL_TRIGGER; + break; + case ASM330LHB_EDGE_TRIGGER: + *val = ASM330LHB_EDGE_TRIGGER; + break; + default: + *val = ASM330LHB_DEN_DISABLE; + break; + } + return ret; +} + +/** + * @brief DEN active level configuration.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of den_lh in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_den_polarity_set(stmdev_ctx_t *ctx, + asm330lhb_den_lh_t val) +{ + asm330lhb_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret == 0) + { + ctrl9_xl.den_lh = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL9_XL, + (uint8_t *)&ctrl9_xl, 1); + } + return ret; +} + +/** + * @brief DEN active level configuration.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of den_lh in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_den_polarity_get(stmdev_ctx_t *ctx, + asm330lhb_den_lh_t *val) +{ + asm330lhb_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + + switch (ctrl9_xl.den_lh) + { + case ASM330LHB_DEN_ACT_LOW: + *val = ASM330LHB_DEN_ACT_LOW; + break; + case ASM330LHB_DEN_ACT_HIGH: + *val = ASM330LHB_DEN_ACT_HIGH; + break; + default: + *val = ASM330LHB_DEN_ACT_LOW; + break; + } + return ret; +} + +/** + * @brief DEN configuration.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of den_xl_g in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_den_enable_set(stmdev_ctx_t *ctx, + asm330lhb_den_xl_g_t val) +{ + asm330lhb_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret == 0) + { + ctrl9_xl.den_xl_g = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL9_XL, + (uint8_t *)&ctrl9_xl, 1); + } + return ret; +} + +/** + * @brief DEN configuration.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of den_xl_g in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_den_enable_get(stmdev_ctx_t *ctx, + asm330lhb_den_xl_g_t *val) +{ + asm330lhb_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + + switch (ctrl9_xl.den_xl_g) + { + case ASM330LHB_STAMP_IN_GY_DATA: + *val = ASM330LHB_STAMP_IN_GY_DATA; + break; + case ASM330LHB_STAMP_IN_XL_DATA: + *val = ASM330LHB_STAMP_IN_XL_DATA; + break; + case ASM330LHB_STAMP_IN_GY_XL_DATA: + *val = ASM330LHB_STAMP_IN_GY_XL_DATA; + break; + default: + *val = ASM330LHB_STAMP_IN_GY_DATA; + break; + } + return ret; +} + +/** + * @brief DEN value stored in LSB of X-axis.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of den_z in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhb_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret == 0) + { + ctrl9_xl.den_z = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL9_XL, + (uint8_t *)&ctrl9_xl, 1); + } + return ret; +} + +/** + * @brief DEN value stored in LSB of X-axis.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of den_z in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + *val = ctrl9_xl.den_z; + + return ret; +} + +/** + * @brief DEN value stored in LSB of Y-axis.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of den_y in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhb_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret == 0) + { + ctrl9_xl.den_y = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL9_XL, + (uint8_t *)&ctrl9_xl, 1); + } + return ret; +} + +/** + * @brief DEN value stored in LSB of Y-axis.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of den_y in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + *val = ctrl9_xl.den_y; + + return ret; +} + +/** + * @brief DEN value stored in LSB of Z-axis.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of den_x in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhb_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret == 0) + { + ctrl9_xl.den_x = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + } + return ret; +} + +/** + * @brief DEN value stored in LSB of Z-axis.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of den_x in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + *val = ctrl9_xl.den_x; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHB_finite_state_machine + * @brief This section groups all the functions that manage the + * state_machine. + * @{ + * + */ + +/** + * @brief FSM status register[get] + * + * @param ctx read / write interface definitions + * @param val register ASM330LHB_FSM_STATUS_A_MAINPAGE, + * ASM330LHB_FSM_STATUS_B_MAINPAGE + * + */ +int32_t asm330lhb_fsm_status_get(stmdev_ctx_t *ctx, + asm330lhb_fsm_status_t *val) +{ + asm330lhb_fsm_status_a_mainpage_t status_a; + asm330lhb_fsm_status_b_mainpage_t status_b; + int32_t ret; + + ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_STATUS_A_MAINPAGE, + (uint8_t *)&status_a, 1); + ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_STATUS_B_MAINPAGE, + (uint8_t *)&status_b, 1); + + val->fsm1 = status_a.is_fsm1; + val->fsm2 = status_a.is_fsm2; + val->fsm3 = status_a.is_fsm3; + val->fsm4 = status_a.is_fsm4; + val->fsm5 = status_a.is_fsm5; + val->fsm6 = status_a.is_fsm6; + val->fsm7 = status_a.is_fsm7; + val->fsm8 = status_a.is_fsm8; + val->fsm9 = status_b.is_fsm9; + val->fsm10 = status_b.is_fsm10; + val->fsm11 = status_b.is_fsm11; + val->fsm12 = status_b.is_fsm12; + val->fsm13 = status_b.is_fsm13; + val->fsm14 = status_b.is_fsm14; + val->fsm15 = status_b.is_fsm15; + val->fsm16 = status_b.is_fsm16; + return ret; +} + +/** + * @brief prgsens_out: [get] Output value of all FSMs. + * + * @param ctx_t *ctx: read / write interface definitions + * @param uint8_t * : buffer that stores data read + * + */ +int32_t asm330lhb_fsm_out_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_OUTS1, buff, 16); + } + if (ret == 0) + { + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + } + return ret; +} + +/** + * @brief Interrupt status bit for FSM long counter timeout interrupt + * event.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of is_fsm_lc in reg EMB_FUNC_STATUS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, + uint8_t *val) +{ + asm330lhb_emb_func_status_t emb_func_status; + int32_t ret; + + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_STATUS, + (uint8_t *)&emb_func_status, 1); + } + if (ret == 0) + { + *val = emb_func_status.is_fsm_lc; + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + } + return ret; +} + +int32_t asm330lhb_emb_func_clk_dis_set(stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhb_page_sel_t page_sel; + int32_t ret; + + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_SEL, + (uint8_t *)&page_sel, 1); + + page_sel.emb_func_clk_dis = val; + } + + ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + + return ret; +} + +int32_t asm330lhb_emb_func_clk_dis_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_page_sel_t page_sel; + int32_t ret; + + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_SEL, + (uint8_t *)&page_sel, 1); + + *val = page_sel.emb_func_clk_dis; + } + + ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + + return ret; +} + +/** + * @brief Embedded final state machine functions mode.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fsm_en in reg EMB_FUNC_EN_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val) +{ + int32_t ret; + asm330lhb_emb_func_en_b_t emb_func_en_b; + + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + emb_func_en_b.fsm_en = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + } + return ret; +} + +/** + * @brief Embedded final state machine functions mode.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of fsm_en in reg EMB_FUNC_EN_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + int32_t ret; + asm330lhb_emb_func_en_b_t emb_func_en_b; + + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + *val = emb_func_en_b.fsm_en; + ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + } + return ret; +} + +/** + * @brief Embedded final state machine functions mode.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fsm_enable_set(stmdev_ctx_t *ctx, + asm330lhb_emb_fsm_enable_t *val) +{ + asm330lhb_emb_func_en_b_t emb_func_en_b; + int32_t ret; + + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_ENABLE_A, + (uint8_t *)&val->fsm_enable_a, 1); + } + if (ret == 0) + { + ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_ENABLE_B, + (uint8_t *)&val->fsm_enable_b, 1); + } + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + if ((val->fsm_enable_a.fsm1_en | + val->fsm_enable_a.fsm2_en | + val->fsm_enable_a.fsm3_en | + val->fsm_enable_a.fsm4_en | + val->fsm_enable_a.fsm5_en | + val->fsm_enable_a.fsm6_en | + val->fsm_enable_a.fsm7_en | + val->fsm_enable_a.fsm8_en | + val->fsm_enable_b.fsm9_en | + val->fsm_enable_b.fsm10_en | + val->fsm_enable_b.fsm11_en | + val->fsm_enable_b.fsm12_en | + val->fsm_enable_b.fsm13_en | + val->fsm_enable_b.fsm14_en | + val->fsm_enable_b.fsm15_en | + val->fsm_enable_b.fsm16_en) != PROPERTY_DISABLE) + { + emb_func_en_b.fsm_en = PROPERTY_ENABLE; + } + else + { + emb_func_en_b.fsm_en = PROPERTY_DISABLE; + } + } + if (ret == 0) + { + ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + } + return ret; +} + +/** + * @brief Embedded final state machine functions mode.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fsm_enable_get(stmdev_ctx_t *ctx, + asm330lhb_emb_fsm_enable_t *val) +{ + int32_t ret; + + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_ENABLE_A, + (uint8_t *)&val->fsm_enable_a, 1); + } + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_ENABLE_B, + (uint8_t *)&val->fsm_enable_b, 1); + } + if (ret == 0) + { + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + } + return ret; +} + +/** + * @brief FSM long counter status register. Long counter value is an + * unsigned integer value (16-bit format).[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_LONG_COUNTER_L, buff, 2); + } + if (ret == 0) + { + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + } + return ret; +} + +/** + * @brief FSM long counter status register. Long counter value is an + * unsigned integer value (16-bit format).[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_LONG_COUNTER_L, buff, 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } + if (ret == 0) + { + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + } + return ret; +} + +/** + * @brief Clear FSM long counter value.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fsm_lc_clr in reg + * FSM_LONG_COUNTER_CLEAR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_long_clr_set(stmdev_ctx_t *ctx, + asm330lhb_fsm_lc_clr_t val) +{ + asm330lhb_fsm_long_counter_clear_t fsm_long_counter_clear; + int32_t ret; + + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_LONG_COUNTER_CLEAR, + (uint8_t *)&fsm_long_counter_clear, 1); + } + if (ret == 0) + { + fsm_long_counter_clear.fsm_lc_clr = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_LONG_COUNTER_CLEAR, + (uint8_t *)&fsm_long_counter_clear, 1); + } + if (ret == 0) + { + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + } + return ret; +} + +/** + * @brief Clear FSM long counter value.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of fsm_lc_clr in reg FSM_LONG_COUNTER_CLEAR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_long_clr_get(stmdev_ctx_t *ctx, + asm330lhb_fsm_lc_clr_t *val) +{ + asm330lhb_fsm_long_counter_clear_t fsm_long_counter_clear; + int32_t ret; + + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_LONG_COUNTER_CLEAR, + (uint8_t *)&fsm_long_counter_clear, 1); + } + if (ret == 0) + { + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + } + switch (fsm_long_counter_clear.fsm_lc_clr) + { + case ASM330LHB_LC_NORMAL: + *val = ASM330LHB_LC_NORMAL; + break; + case ASM330LHB_LC_CLEAR: + *val = ASM330LHB_LC_CLEAR; + break; + case ASM330LHB_LC_CLEAR_DONE: + *val = ASM330LHB_LC_CLEAR_DONE; + break; + default: + *val = ASM330LHB_LC_NORMAL; + break; + } + return ret; +} + +/** + * @brief Finite State Machine ODR configuration.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fsm_data_rate_set(stmdev_ctx_t *ctx, + asm330lhb_fsm_odr_t val) +{ + asm330lhb_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; + int32_t ret; + + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_ODR_CFG_B, + (uint8_t *)&emb_func_odr_cfg_b, 1); + } + if (ret == 0) + { + emb_func_odr_cfg_b.not_used_01 = 3; /* set default values */ + emb_func_odr_cfg_b.not_used_02 = 1; /* set default values */ + emb_func_odr_cfg_b.fsm_odr = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_ODR_CFG_B, + (uint8_t *)&emb_func_odr_cfg_b, 1); + } + if (ret == 0) + { + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + } + return ret; +} + +/** + * @brief Finite State Machine ODR configuration.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fsm_data_rate_get(stmdev_ctx_t *ctx, + asm330lhb_fsm_odr_t *val) +{ + asm330lhb_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; + int32_t ret; + + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_ODR_CFG_B, + (uint8_t *)&emb_func_odr_cfg_b, 1); + } + if (ret == 0) + { + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + } + switch (emb_func_odr_cfg_b.fsm_odr) + { + case ASM330LHB_ODR_FSM_12Hz5: + *val = ASM330LHB_ODR_FSM_12Hz5; + break; + case ASM330LHB_ODR_FSM_26Hz: + *val = ASM330LHB_ODR_FSM_26Hz; + break; + case ASM330LHB_ODR_FSM_52Hz: + *val = ASM330LHB_ODR_FSM_52Hz; + break; + case ASM330LHB_ODR_FSM_104Hz: + *val = ASM330LHB_ODR_FSM_104Hz; + break; + default: + *val = ASM330LHB_ODR_FSM_12Hz5; + break; + } + return ret; +} + +/** + * @brief FSM initialization request.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fsm_init in reg FSM_INIT + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhb_emb_func_init_b_t emb_func_init_b; + int32_t ret; + + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B, + (uint8_t *)&emb_func_init_b, 1); + } + if (ret == 0) + { + emb_func_init_b.fsm_init = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B, + (uint8_t *)&emb_func_init_b, 1); + } + if (ret == 0) + { + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + } + return ret; +} + +/** + * @brief FSM initialization request.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fsm_init in reg FSM_INIT + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_emb_func_init_b_t emb_func_init_b; + int32_t ret; + + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B, + (uint8_t *)&emb_func_init_b, 1); + } + if (ret == 0) + { + *val = emb_func_init_b.fsm_init; + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + } + return ret; +} + +/** + * @brief FSM long counter timeout register (r/w). The long counter + * timeout value is an unsigned integer value (16-bit format). + * When the long counter value reached this value, the FSM + * generates an interrupt.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = asm330lhb_ln_pg_write_byte(ctx, ASM330LHB_FSM_LC_TIMEOUT_L, &buff[0]); + + if (ret == 0) + { + ret = asm330lhb_ln_pg_write_byte(ctx, ASM330LHB_FSM_LC_TIMEOUT_H, + &buff[1]); + } + return ret; +} + +/** + * @brief FSM long counter timeout register (r/w). The long counter + * timeout value is an unsigned integer value (16-bit format). + * When the long counter value reached this value, the FSM generates + * an interrupt.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = asm330lhb_ln_pg_read_byte(ctx, ASM330LHB_FSM_LC_TIMEOUT_L, &buff[0]); + + if (ret == 0) + { + ret = asm330lhb_ln_pg_read_byte(ctx, ASM330LHB_FSM_LC_TIMEOUT_H, + &buff[1]); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } + return ret; +} + +/** + * @brief FSM number of programs register.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = asm330lhb_ln_pg_write_byte(ctx, ASM330LHB_FSM_PROGRAMS, buff); + + if (ret == 0) + { + ret = asm330lhb_ln_pg_write_byte(ctx, ASM330LHB_FSM_PROGRAMS + 0x01U, + buff); + } + return ret; +} + +/** + * @brief FSM number of programs register.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = asm330lhb_ln_pg_read_byte(ctx, ASM330LHB_FSM_PROGRAMS, buff); + + return ret; +} + +/** + * @brief FSM start address register (r/w). First available address is + * 0x033C.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + + ret = asm330lhb_ln_pg_write_byte(ctx, ASM330LHB_FSM_START_ADD_L, &buff[0]); + if (ret == 0) + { + ret = asm330lhb_ln_pg_write_byte(ctx, ASM330LHB_FSM_START_ADD_H, &buff[1]); + } + return ret; +} + +/** + * @brief FSM start address register (r/w). First available address + * is 0x033C.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = asm330lhb_ln_pg_read_byte(ctx, ASM330LHB_FSM_START_ADD_L, &buff[0]); + if (ret == 0) + { + ret = asm330lhb_ln_pg_read_byte(ctx, ASM330LHB_FSM_START_ADD_H, &buff[1]); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @addtogroup Machine Learning Core + * @brief This section group all the functions concerning the + * usage of Machine Learning Core + * @{ + * + */ + +/** + * @brief Enable Machine Learning Core.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of mlc_en in + * reg EMB_FUNC_EN_B and mlc_init + * in EMB_FUNC_INIT_B + * + */ +int32_t asm330lhb_mlc_set(stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhb_emb_func_en_b_t reg; + int32_t ret; + + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_EN_B, (uint8_t *)®, 1); + } + if (ret == 0) + { + reg.mlc_en = val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_EN_B, (uint8_t *)®, 1); + } + if ((val != PROPERTY_DISABLE) && (ret == 0)) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B, + (uint8_t *)®, 1); + if (ret == 0) + { + reg.mlc_en = val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B, + (uint8_t *)®, 1); + } + } + if (ret == 0) + { + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + } + return ret; +} + +/** + * @brief Enable Machine Learning Core.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of mlc_en in + * reg EMB_FUNC_EN_B + * + */ +int32_t asm330lhb_mlc_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_emb_func_en_b_t reg; + int32_t ret; + + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_EN_B, (uint8_t *)®, 1); + } + if (ret == 0) + { + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + *val = reg.mlc_en; + } + return ret; +} + +/** + * @brief Machine Learning Core status register[get] + * + * @param ctx read / write interface definitions + * @param val register MLC_STATUS_MAINPAGE + * + */ +int32_t asm330lhb_mlc_status_get(stmdev_ctx_t *ctx, + asm330lhb_mlc_status_mainpage_t *val) +{ + return asm330lhb_read_reg(ctx, ASM330LHB_MLC_STATUS_MAINPAGE, + (uint8_t *) val, 1); +} + +/** + * @brief Machine Learning Core data rate selection.[set] + * + * @param ctx read / write interface definitions + * @param val get the values of mlc_odr in + * reg EMB_FUNC_ODR_CFG_C + * + */ +int32_t asm330lhb_mlc_data_rate_set(stmdev_ctx_t *ctx, + asm330lhb_mlc_odr_t val) +{ + asm330lhb_emb_func_odr_cfg_c_t reg; + int32_t ret; + + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_ODR_CFG_C, + (uint8_t *)®, 1); + } + if (ret == 0) + { + reg.mlc_odr = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_ODR_CFG_C, + (uint8_t *)®, 1); + } + if (ret == 0) + { + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + } + + return ret; +} + +/** + * @brief Machine Learning Core data rate selection.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of mlc_odr in + * reg EMB_FUNC_ODR_CFG_C + * + */ +int32_t asm330lhb_mlc_data_rate_get(stmdev_ctx_t *ctx, + asm330lhb_mlc_odr_t *val) +{ + asm330lhb_emb_func_odr_cfg_c_t reg; + int32_t ret; + + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_ODR_CFG_C, + (uint8_t *)®, 1); + } + if (ret == 0) + { + switch (reg.mlc_odr) + { + case ASM330LHB_ODR_PRGS_12Hz5: + *val = ASM330LHB_ODR_PRGS_12Hz5; + break; + case ASM330LHB_ODR_PRGS_26Hz: + *val = ASM330LHB_ODR_PRGS_26Hz; + break; + case ASM330LHB_ODR_PRGS_52Hz: + *val = ASM330LHB_ODR_PRGS_52Hz; + break; + case ASM330LHB_ODR_PRGS_104Hz: + *val = ASM330LHB_ODR_PRGS_104Hz; + break; + default: + *val = ASM330LHB_ODR_PRGS_12Hz5; + break; + } + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + } + return ret; +} + +/** + * @brief MLC initialization request.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of mlc_init + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_mlc_init_set(stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhb_emb_func_init_b_t emb_func_init_b; + int32_t ret; + + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B, + (uint8_t *)&emb_func_init_b, 1); + } + if (ret == 0) + { + emb_func_init_b.mlc_init = (uint8_t)val; + ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B, + (uint8_t *)&emb_func_init_b, 1); + } + + ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + + return ret; +} + +/** + * @brief MLC initialization request.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of mlc_init + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhb_mlc_init_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhb_emb_func_init_b_t emb_func_init_b; + int32_t ret; + + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B, + (uint8_t *)&emb_func_init_b, 1); + } + if (ret == 0) + { + *val = emb_func_init_b.mlc_init; + } + + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + + return ret; +} + +/** + * @brief prgsens_out: [get] Output value of all MLCx decision trees. + * + * @param ctx_t *ctx: read / write interface definitions + * @param uint8_t * : buffer that stores data read + * + */ +int32_t asm330lhb_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhb_read_reg(ctx, ASM330LHB_MLC0_SRC, buff, 8); + } + if (ret == 0) + { + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + } + return ret; +} + +/** + * @} + * + */ + +/** + * @} + * + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/asm330lhb_STdC/driver/asm330lhb_reg.h b/sensor/stmemsc/asm330lhb_STdC/driver/asm330lhb_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..4aaa1ddd26e3bbf3fe60a35320428b83b8cf0282 --- /dev/null +++ b/sensor/stmemsc/asm330lhb_STdC/driver/asm330lhb_reg.h @@ -0,0 +1,2698 @@ +/* + ****************************************************************************** + * @file asm330lhb_reg.h + * @author Sensor Solutions Software Team + * @brief This file contains all the functions prototypes for the + * asm330lhb_reg.c driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2023 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef ASM330LHB_REGS_H +#define ASM330LHB_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include + +/** @addtogroup ASM330LHB + * @{ + * + */ + +/** @defgroup Endianness definitions + * @{ + * + */ + +#ifndef DRV_BYTE_ORDER +#ifndef __BYTE_ORDER__ + +#define DRV_LITTLE_ENDIAN 1234 +#define DRV_BIG_ENDIAN 4321 + +/** if _BYTE_ORDER is not defined, choose the endianness of your architecture + * by uncommenting the define which fits your platform endianness + */ +//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN +#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN + +#else /* defined __BYTE_ORDER__ */ + +#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ +#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ +#define DRV_BYTE_ORDER __BYTE_ORDER__ + +#endif /* __BYTE_ORDER__*/ +#endif /* DRV_BYTE_ORDER */ + +/** + * @} + * + */ + +/** @defgroup STMicroelectronics sensors common types + * @{ + * + */ + +#ifndef MEMS_SHARED_TYPES +#define MEMS_SHARED_TYPES + +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} bitwise_t; + +#define PROPERTY_DISABLE (0U) +#define PROPERTY_ENABLE (1U) + +/** @addtogroup Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); +typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); + +typedef struct +{ + /** Component mandatory fields **/ + stmdev_write_ptr write_reg; + stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; + /** Customizable optional pointer **/ + void *handle; +} stmdev_ctx_t; + +/** + * @} + * + */ + +#endif /* MEMS_SHARED_TYPES */ + +#ifndef MEMS_UCF_SHARED_TYPES +#define MEMS_UCF_SHARED_TYPES + +/** @defgroup Generic address-data structure definition + * @brief This structure is useful to load a predefined configuration + * of a sensor. + * You can create a sensor configuration by your own or using + * Unico / Unicleo tools available on STMicroelectronics + * web site. + * + * @{ + * + */ + +typedef struct +{ + uint8_t address; + uint8_t data; +} ucf_line_t; + +/** + * @} + * + */ + +#endif /* MEMS_UCF_SHARED_TYPES */ + +/** + * @} + * + */ + +/** @defgroup ASM330LHB Infos + * @{ + * + */ + +/** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ +#define ASM330LHB_I2C_ADD_L 0xD5U +#define ASM330LHB_I2C_ADD_H 0xD7U + +/** Device Identification (Who am I) **/ +#define ASM330LHB_ID 0x6BU + +/** + * @} + * + */ + +#define ASM330LHB_FUNC_CFG_ACCESS 0x01U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 7; + uint8_t reg_access : 1; /* func_cfg_access */ +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t reg_access : 1; /* func_cfg_access */ + uint8_t not_used_01 : 7; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_func_cfg_access_t; + +#define ASM330LHB_PIN_CTRL 0x02U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 6; + uint8_t sdo_pu_en : 1; + uint8_t not_used_02 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 1; + uint8_t sdo_pu_en : 1; + uint8_t not_used_01 : 6; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_pin_ctrl_t; + +#define ASM330LHB_FIFO_CTRL1 0x07U +typedef struct +{ + uint8_t wtm : 8; +} asm330lhb_fifo_ctrl1_t; + +#define ASM330LHB_FIFO_CTRL2 0x08U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wtm : 1; + uint8_t not_used_01 : 3; + uint8_t odrchg_en : 1; + uint8_t not_used_02 : 2; + uint8_t stop_on_wtm : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t stop_on_wtm : 1; + uint8_t not_used_02 : 2; + uint8_t odrchg_en : 1; + uint8_t not_used_01 : 3; + uint8_t wtm : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fifo_ctrl2_t; + +#define ASM330LHB_FIFO_CTRL3 0x09U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bdr_xl : 4; + uint8_t bdr_gy : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bdr_gy : 4; + uint8_t bdr_xl : 4; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fifo_ctrl3_t; + +#define ASM330LHB_FIFO_CTRL4 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_mode : 3; + uint8_t not_used_01 : 1; + uint8_t odr_t_batch : 2; + uint8_t dec_ts_batch : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dec_ts_batch : 2; + uint8_t odr_t_batch : 2; + uint8_t not_used_01 : 1; + uint8_t fifo_mode : 3; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fifo_ctrl4_t; + +#define ASM330LHB_COUNTER_BDR_REG1 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t cnt_bdr_th : 3; + uint8_t not_used_01 : 2; + uint8_t trig_counter_bdr : 1; + uint8_t rst_counter_bdr : 1; + uint8_t dataready_pulsed : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dataready_pulsed : 1; + uint8_t rst_counter_bdr : 1; + uint8_t trig_counter_bdr : 1; + uint8_t not_used_01 : 2; + uint8_t cnt_bdr_th : 3; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_counter_bdr_reg1_t; + +#define ASM330LHB_COUNTER_BDR_REG2 0x0CU +typedef struct +{ + uint8_t cnt_bdr_th : 8; +} asm330lhb_counter_bdr_reg2_t; + +#define ASM330LHB_INT1_CTRL 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_drdy_xl : 1; + uint8_t int1_drdy_g : 1; + uint8_t int1_boot : 1; + uint8_t int1_fifo_th : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_fifo_full : 1; + uint8_t int1_cnt_bdr : 1; + uint8_t den_drdy_flag : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t den_drdy_flag : 1; + uint8_t int1_cnt_bdr : 1; + uint8_t int1_fifo_full : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_fifo_th : 1; + uint8_t int1_boot : 1; + uint8_t int1_drdy_g : 1; + uint8_t int1_drdy_xl : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_int1_ctrl_t; + +#define ASM330LHB_INT2_CTRL 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_drdy_xl : 1; + uint8_t int2_drdy_g : 1; + uint8_t int2_drdy_temp : 1; + uint8_t int2_fifo_th : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_fifo_full : 1; + uint8_t int2_cnt_bdr : 1; + uint8_t not_used_01 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 1; + uint8_t int2_cnt_bdr : 1; + uint8_t int2_fifo_full : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_fifo_th : 1; + uint8_t int2_drdy_temp : 1; + uint8_t int2_drdy_g : 1; + uint8_t int2_drdy_xl : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_int2_ctrl_t; + +#define ASM330LHB_WHO_AM_I 0x0FU + +#define ASM330LHB_CTRL1_XL 0x10U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 1; + uint8_t lpf2_xl_en : 1; + uint8_t fs_xl : 2; + uint8_t odr_xl : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t odr_xl : 4; + uint8_t fs_xl : 2; + uint8_t lpf2_xl_en : 1; + uint8_t not_used_01 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_ctrl1_xl_t; + +#define ASM330LHB_CTRL2_G 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_g : 4; /* fs_4000 + fs_125 + fs_g */ + uint8_t odr_g : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t odr_g : 4; + uint8_t fs_g : 4; /* fs_4000 + fs_125 + fs_g */ +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_ctrl2_g_t; + +#define ASM330LHB_CTRL3_C 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sw_reset : 1; + uint8_t not_used_01 : 1; + uint8_t if_inc : 1; + uint8_t sim : 1; + uint8_t pp_od : 1; + uint8_t h_lactive : 1; + uint8_t bdu : 1; + uint8_t boot : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t boot : 1; + uint8_t bdu : 1; + uint8_t h_lactive : 1; + uint8_t pp_od : 1; + uint8_t sim : 1; + uint8_t if_inc : 1; + uint8_t not_used_01 : 1; + uint8_t sw_reset : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_ctrl3_c_t; + +#define ASM330LHB_CTRL4_C 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 1; + uint8_t lpf1_sel_g : 1; + uint8_t i2c_disable : 1; + uint8_t drdy_mask : 1; + uint8_t not_used_02 : 1; + uint8_t int2_on_int1 : 1; + uint8_t sleep_g : 1; + uint8_t not_used_03 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_03 : 1; + uint8_t sleep_g : 1; + uint8_t int2_on_int1 : 1; + uint8_t not_used_02 : 1; + uint8_t drdy_mask : 1; + uint8_t i2c_disable : 1; + uint8_t lpf1_sel_g : 1; + uint8_t not_used_01 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_ctrl4_c_t; + +#define ASM330LHB_CTRL5_C 0x14U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t st_xl : 2; + uint8_t st_g : 2; + uint8_t not_used_01 : 1; + uint8_t rounding : 2; + uint8_t not_used_02 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 1; + uint8_t rounding : 2; + uint8_t not_used_01 : 1; + uint8_t st_g : 2; + uint8_t st_xl : 2; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_ctrl5_c_t; + +#define ASM330LHB_CTRL6_C 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ftype : 3; + uint8_t usr_off_w : 1; + uint8_t xl_hm_mode : 1; + uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ + uint8_t xl_hm_mode : 1; + uint8_t usr_off_w : 1; + uint8_t ftype : 3; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_ctrl6_c_t; + +#define ASM330LHB_CTRL7_G 0x16U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_00 : 1; + uint8_t usr_off_on_out : 1; + uint8_t not_used_01 : 2; + uint8_t hpm_g : 2; + uint8_t hp_en_g : 1; + uint8_t g_hm_mode : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t g_hm_mode : 1; + uint8_t hp_en_g : 1; + uint8_t hpm_g : 2; + uint8_t not_used_01 : 2; + uint8_t usr_off_on_out : 1; + uint8_t not_used_00 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_ctrl7_g_t; + +#define ASM330LHB_CTRL8_XL 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t low_pass_on_6d : 1; + uint8_t not_used_01 : 1; + uint8_t hp_slope_xl_en : 1; + uint8_t fastsettl_mode_xl : 1; + uint8_t hp_ref_mode_xl : 1; + uint8_t hpcf_xl : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t hpcf_xl : 3; + uint8_t hp_ref_mode_xl : 1; + uint8_t fastsettl_mode_xl : 1; + uint8_t hp_slope_xl_en : 1; + uint8_t not_used_01 : 1; + uint8_t low_pass_on_6d : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_ctrl8_xl_t; + +#define ASM330LHB_CTRL9_XL 0x18U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 1; + uint8_t i3c_disable : 1; + uint8_t den_lh : 1; + uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ + uint8_t den_z : 1; + uint8_t den_y : 1; + uint8_t den_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t den_x : 1; + uint8_t den_y : 1; + uint8_t den_z : 1; + uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ + uint8_t den_lh : 1; + uint8_t i3c_disable : 1; + uint8_t not_used_01 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_ctrl9_xl_t; + +#define ASM330LHB_CTRL10_C 0x19U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 5; + uint8_t timestamp_en : 1; + uint8_t not_used_02 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 2; + uint8_t timestamp_en : 1; + uint8_t not_used_01 : 5; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_ctrl10_c_t; + +#define ASM330LHB_ALL_INT_SRC 0x1AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ff_ia : 1; + uint8_t wu_ia : 1; + uint8_t not_used_00 : 2; + uint8_t d6d_ia : 1; + uint8_t sleep_change_ia : 1; + uint8_t not_used_01 : 1; + uint8_t timestamp_endcount : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp_endcount : 1; + uint8_t not_used_01 : 1; + uint8_t sleep_change_ia : 1; + uint8_t d6d_ia : 1; + uint8_t not_used_00 : 2; + uint8_t wu_ia : 1; + uint8_t ff_ia : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_all_int_src_t; + +#define ASM330LHB_WAKE_UP_SRC 0x1BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t z_wu : 1; + uint8_t y_wu : 1; + uint8_t x_wu : 1; + uint8_t wu_ia : 1; + uint8_t sleep_state : 1; + uint8_t ff_ia : 1; + uint8_t sleep_change_ia : 1; + uint8_t not_used_01 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 1; + uint8_t sleep_change_ia : 1; + uint8_t ff_ia : 1; + uint8_t sleep_state : 1; + uint8_t wu_ia : 1; + uint8_t x_wu : 1; + uint8_t y_wu : 1; + uint8_t z_wu : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_wake_up_src_t; + +#define ASM330LHB_D6D_SRC 0x1DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xl : 1; + uint8_t xh : 1; + uint8_t yl : 1; + uint8_t yh : 1; + uint8_t zl : 1; + uint8_t zh : 1; + uint8_t d6d_ia : 1; + uint8_t den_drdy : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t den_drdy : 1; + uint8_t d6d_ia : 1; + uint8_t zh : 1; + uint8_t zl : 1; + uint8_t yh : 1; + uint8_t yl : 1; + uint8_t xh : 1; + uint8_t xl : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_d6d_src_t; + +#define ASM330LHB_STATUS_REG 0x1EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xlda : 1; + uint8_t gda : 1; + uint8_t tda : 1; + uint8_t boot_check_fail : 1; + uint8_t not_used_01 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 4; + uint8_t boot_check_fail : 1; + uint8_t tda : 1; + uint8_t gda : 1; + uint8_t xlda : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_status_reg_t; + +#define ASM330LHB_OUT_TEMP_L 0x20U +#define ASM330LHB_OUT_TEMP_H 0x21U +#define ASM330LHB_OUTX_L_G 0x22U +#define ASM330LHB_OUTX_H_G 0x23U +#define ASM330LHB_OUTY_L_G 0x24U +#define ASM330LHB_OUTY_H_G 0x25U +#define ASM330LHB_OUTZ_L_G 0x26U +#define ASM330LHB_OUTZ_H_G 0x27U +#define ASM330LHB_OUTX_L_A 0x28U +#define ASM330LHB_OUTX_H_A 0x29U +#define ASM330LHB_OUTY_L_A 0x2AU +#define ASM330LHB_OUTY_H_A 0x2BU +#define ASM330LHB_OUTZ_L_A 0x2CU +#define ASM330LHB_OUTZ_H_A 0x2DU +#define ASM330LHB_EMB_FUNC_STATUS_MAINPAGE 0x35U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 7; + uint8_t is_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm_lc : 1; + uint8_t not_used_01 : 7; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_emb_func_status_mainpage_t; + +#define ASM330LHB_FSM_STATUS_A_MAINPAGE 0x36U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm1 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm8 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fsm_status_a_mainpage_t; + +#define ASM330LHB_FSM_STATUS_B_MAINPAGE 0x37U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm9 : 1; + uint8_t is_fsm10 : 1; + uint8_t is_fsm11 : 1; + uint8_t is_fsm12 : 1; + uint8_t is_fsm13 : 1; + uint8_t is_fsm14 : 1; + uint8_t is_fsm15 : 1; + uint8_t is_fsm16 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm16 : 1; + uint8_t is_fsm15 : 1; + uint8_t is_fsm14 : 1; + uint8_t is_fsm13 : 1; + uint8_t is_fsm12 : 1; + uint8_t is_fsm11 : 1; + uint8_t is_fsm10 : 1; + uint8_t is_fsm9 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fsm_status_b_mainpage_t; + +#define ASM330LHB_MLC_STATUS_MAINPAGE 0x38U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_mlc1 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc4 : 1; + uint8_t is_mlc5 : 1; + uint8_t is_mlc6 : 1; + uint8_t is_mlc7 : 1; + uint8_t is_mlc8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_mlc8 : 1; + uint8_t is_mlc7 : 1; + uint8_t is_mlc6 : 1; + uint8_t is_mlc5 : 1; + uint8_t is_mlc4 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_mlc_status_mainpage_t; + +#define ASM330LHB_FIFO_STATUS1 0x3AU +typedef struct +{ + uint8_t diff_fifo : 8; +} asm330lhb_fifo_status1_t; + +#define ASM330LHB_FIFO_STATUS2 0x3BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t diff_fifo : 2; + uint8_t not_used_01 : 1; + uint8_t over_run_latched : 1; + uint8_t counter_bdr_ia : 1; + uint8_t fifo_full_ia : 1; + uint8_t fifo_ovr_ia : 1; + uint8_t fifo_wtm_ia : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_wtm_ia : 1; + uint8_t fifo_ovr_ia : 1; + uint8_t fifo_full_ia : 1; + uint8_t counter_bdr_ia : 1; + uint8_t over_run_latched : 1; + uint8_t not_used_01 : 1; + uint8_t diff_fifo : 2; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fifo_status2_t; + +#define ASM330LHB_TIMESTAMP0 0x40U +#define ASM330LHB_TIMESTAMP1 0x41U +#define ASM330LHB_TIMESTAMP2 0x42U +#define ASM330LHB_TIMESTAMP3 0x43U +#define ASM330LHB_INT_CFG0 0x56U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t lir : 1; + uint8_t not_used_01 : 3; + uint8_t slope_fds : 1; + uint8_t sleep_status_on_int : 1; + uint8_t int_clr_on_read : 1; + uint8_t not_used_02 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 1; + uint8_t int_clr_on_read : 1; + uint8_t sleep_status_on_int : 1; + uint8_t slope_fds : 1; + uint8_t not_used_01 : 3; + uint8_t lir : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_int_cfg0_t; + +#define ASM330LHB_INT_CFG1 0x58U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 5; + uint8_t inact_en : 2; + uint8_t interrupts_enable : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t interrupts_enable : 1; + uint8_t inact_en : 2; + uint8_t not_used_01 : 5; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_int_cfg1_t; + +#define ASM330LHB_THS_6D 0x59U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 5; + uint8_t sixd_ths : 2; + uint8_t d4d_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t d4d_en : 1; + uint8_t sixd_ths : 2; + uint8_t not_used_01 : 5; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_ths_6d_t; + +#define ASM330LHB_WAKE_UP_THS 0x5BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wk_ths : 6; + uint8_t usr_off_on_wu : 1; + uint8_t not_used_01 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 1; + uint8_t usr_off_on_wu : 1; + uint8_t wk_ths : 6; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_wake_up_ths_t; + +#define ASM330LHB_WAKE_UP_DUR 0x5CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sleep_dur : 4; + uint8_t wake_ths_w : 1; + uint8_t wake_dur : 2; + uint8_t ff_dur : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ff_dur : 1; + uint8_t wake_dur : 2; + uint8_t wake_ths_w : 1; + uint8_t sleep_dur : 4; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_wake_up_dur_t; + +#define ASM330LHB_FREE_FALL 0x5DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ff_ths : 3; + uint8_t ff_dur : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ff_dur : 5; + uint8_t ff_ths : 3; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_free_fall_t; + +#define ASM330LHB_MD1_CFG 0x5EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_00 : 1; + uint8_t int1_emb_func : 1; + uint8_t int1_6d : 1; + uint8_t not_used_01 : 1; + uint8_t int1_ff : 1; + uint8_t int1_wu : 1; + uint8_t not_used_02 : 1; + uint8_t int1_sleep_change : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_sleep_change : 1; + uint8_t not_used_02 : 1; + uint8_t int1_wu : 1; + uint8_t int1_ff : 1; + uint8_t not_used_01 : 1; + uint8_t int1_6d : 1; + uint8_t int1_emb_func : 1; + uint8_t not_used_00 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_md1_cfg_t; + +#define ASM330LHB_MD2_CFG 0x5FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_timestamp : 1; + uint8_t int2_emb_func : 1; + uint8_t int2_6d : 1; + uint8_t not_used_01 : 1; + uint8_t int2_ff : 1; + uint8_t int2_wu : 1; + uint8_t not_used_02 : 1; + uint8_t int2_sleep_change : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_sleep_change : 1; + uint8_t not_used_02 : 1; + uint8_t int2_wu : 1; + uint8_t int2_ff : 1; + uint8_t not_used_01 : 1; + uint8_t int2_6d : 1; + uint8_t int2_emb_func : 1; + uint8_t int2_timestamp : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_md2_cfg_t; + +#define ASM330LHB_I3C_BUS_AVB 0x62U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t pd_dis_int1 : 1; + uint8_t not_used_01 : 2; + uint8_t i3c_bus_avb_sel : 2; + uint8_t not_used_02 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 3; + uint8_t i3c_bus_avb_sel : 2; + uint8_t not_used_01 : 2; + uint8_t pd_dis_int1 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_i3c_bus_avb_t; + +#define ASM330LHB_INTERNAL_FREQ_FINE 0x63U +typedef struct +{ + uint8_t freq_fine : 8; +} asm330lhb_internal_freq_fine_t; + +#define ASM330LHB_X_OFS_USR 0x73U +#define ASM330LHB_Y_OFS_USR 0x74U +#define ASM330LHB_Z_OFS_USR 0x75U +#define ASM330LHB_FIFO_DATA_OUT_TAG 0x78U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tag_parity : 1; + uint8_t tag_cnt : 2; + uint8_t tag_sensor : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tag_sensor : 5; + uint8_t tag_cnt : 2; + uint8_t tag_parity : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fifo_data_out_tag_t; + +#define ASM330LHB_FIFO_DATA_OUT_X_L 0x79U +#define ASM330LHB_FIFO_DATA_OUT_X_H 0x7AU +#define ASM330LHB_FIFO_DATA_OUT_Y_L 0x7BU +#define ASM330LHB_FIFO_DATA_OUT_Y_H 0x7CU +#define ASM330LHB_FIFO_DATA_OUT_Z_L 0x7DU +#define ASM330LHB_FIFO_DATA_OUT_Z_H 0x7EU + +#define ASM330LHB_PAGE_SEL 0x02U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 1; + uint8_t emb_func_clk_dis : 1; + uint8_t not_used_02 : 2; + uint8_t page_sel : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_sel : 4; + uint8_t not_used_02 : 2; + uint8_t emb_func_clk_dis : 1; + uint8_t not_used_01 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_page_sel_t; + +#define ASM330LHB_EMB_FUNC_EN_B 0x05U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_en : 1; + uint8_t not_used_01 : 3; + uint8_t mlc_en : 1; + uint8_t not_used_02 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 3; + uint8_t mlc_en : 1; + uint8_t not_used_01 : 3; + uint8_t fsm_en : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_emb_func_en_b_t; + +#define ASM330LHB_PAGE_ADDRESS 0x08U +typedef struct +{ + uint8_t page_addr : 8; +} asm330lhb_page_address_t; + +#define ASM330LHB_PAGE_VALUE 0x09U +typedef struct +{ + uint8_t page_value : 8; +} asm330lhb_page_value_t; + +#define ASM330LHB_EMB_FUNC_INT1 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 7; + uint8_t int1_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_fsm_lc : 1; + uint8_t not_used_01 : 7; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_emb_func_int1_t; + +#define ASM330LHB_FSM_INT1_A 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_fsm1 : 1; + uint8_t int1_fsm2 : 1; + uint8_t int1_fsm3 : 1; + uint8_t int1_fsm4 : 1; + uint8_t int1_fsm5 : 1; + uint8_t int1_fsm6 : 1; + uint8_t int1_fsm7 : 1; + uint8_t int1_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_fsm8 : 1; + uint8_t int1_fsm7 : 1; + uint8_t int1_fsm6 : 1; + uint8_t int1_fsm5 : 1; + uint8_t int1_fsm4 : 1; + uint8_t int1_fsm3 : 1; + uint8_t int1_fsm2 : 1; + uint8_t int1_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fsm_int1_a_t; + +#define ASM330LHB_FSM_INT1_B 0x0CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_fsm9 : 1; + uint8_t int1_fsm10 : 1; + uint8_t int1_fsm11 : 1; + uint8_t int1_fsm12 : 1; + uint8_t int1_fsm13 : 1; + uint8_t int1_fsm14 : 1; + uint8_t int1_fsm15 : 1; + uint8_t int1_fsm16 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_fsm16 : 1; + uint8_t int1_fsm15 : 1; + uint8_t int1_fsm14 : 1; + uint8_t int1_fsm13 : 1; + uint8_t int1_fsm12 : 1; + uint8_t int1_fsm11 : 1; + uint8_t int1_fsm10 : 1; + uint8_t int1_fsm9 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fsm_int1_b_t; + +#define ASM330LHB_MLC_INT1 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_mlc1 : 1; + uint8_t int1_mlc2 : 1; + uint8_t int1_mlc3 : 1; + uint8_t int1_mlc4 : 1; + uint8_t int1_mlc5 : 1; + uint8_t int1_mlc6 : 1; + uint8_t int1_mlc7 : 1; + uint8_t int1_mlc8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_mlc8 : 1; + uint8_t int1_mlc7 : 1; + uint8_t int1_mlc6 : 1; + uint8_t int1_mlc5 : 1; + uint8_t int1_mlc4 : 1; + uint8_t int1_mlc3 : 1; + uint8_t int1_mlc2 : 1; + uint8_t int1_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_mlc_int1_t; + +#define ASM330LHB_EMB_FUNC_INT2 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 7; + uint8_t int2_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_fsm_lc : 1; + uint8_t not_used_01 : 7; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_emb_func_int2_t; + +#define ASM330LHB_FSM_INT2_A 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_fsm1 : 1; + uint8_t int2_fsm2 : 1; + uint8_t int2_fsm3 : 1; + uint8_t int2_fsm4 : 1; + uint8_t int2_fsm5 : 1; + uint8_t int2_fsm6 : 1; + uint8_t int2_fsm7 : 1; + uint8_t int2_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_fsm8 : 1; + uint8_t int2_fsm7 : 1; + uint8_t int2_fsm6 : 1; + uint8_t int2_fsm5 : 1; + uint8_t int2_fsm4 : 1; + uint8_t int2_fsm3 : 1; + uint8_t int2_fsm2 : 1; + uint8_t int2_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fsm_int2_a_t; + +#define ASM330LHB_FSM_INT2_B 0x10U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_fsm9 : 1; + uint8_t int2_fsm10 : 1; + uint8_t int2_fsm11 : 1; + uint8_t int2_fsm12 : 1; + uint8_t int2_fsm13 : 1; + uint8_t int2_fsm14 : 1; + uint8_t int2_fsm15 : 1; + uint8_t int2_fsm16 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_fsm16 : 1; + uint8_t int2_fsm15 : 1; + uint8_t int2_fsm14 : 1; + uint8_t int2_fsm13 : 1; + uint8_t int2_fsm12 : 1; + uint8_t int2_fsm11 : 1; + uint8_t int2_fsm10 : 1; + uint8_t int2_fsm9 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fsm_int2_b_t; + +#define ASM330LHB_MLC_INT2 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_mlc1 : 1; + uint8_t int2_mlc2 : 1; + uint8_t int2_mlc3 : 1; + uint8_t int2_mlc4 : 1; + uint8_t int2_mlc5 : 1; + uint8_t int2_mlc6 : 1; + uint8_t int2_mlc7 : 1; + uint8_t int2_mlc8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_mlc8 : 1; + uint8_t int2_mlc7 : 1; + uint8_t int2_mlc6 : 1; + uint8_t int2_mlc5 : 1; + uint8_t int2_mlc4 : 1; + uint8_t int2_mlc3 : 1; + uint8_t int2_mlc2 : 1; + uint8_t int2_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_mlc_int2_t; + +#define ASM330LHB_EMB_FUNC_STATUS 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 7; + uint8_t is_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm_lc : 1; + uint8_t not_used_01 : 7; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_emb_func_status_t; + +#define ASM330LHB_FSM_STATUS_A 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm1 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm8 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fsm_status_a_t; + +#define ASM330LHB_FSM_STATUS_B 0x14U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm9 : 1; + uint8_t is_fsm10 : 1; + uint8_t is_fsm11 : 1; + uint8_t is_fsm12 : 1; + uint8_t is_fsm13 : 1; + uint8_t is_fsm14 : 1; + uint8_t is_fsm15 : 1; + uint8_t is_fsm16 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm16 : 1; + uint8_t is_fsm15 : 1; + uint8_t is_fsm14 : 1; + uint8_t is_fsm13 : 1; + uint8_t is_fsm12 : 1; + uint8_t is_fsm11 : 1; + uint8_t is_fsm10 : 1; + uint8_t is_fsm9 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fsm_status_b_t; + +#define ASM330LHB_MLC_STATUS 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_mlc1 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc4 : 1; + uint8_t is_mlc5 : 1; + uint8_t is_mlc6 : 1; + uint8_t is_mlc7 : 1; + uint8_t is_mlc8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_mlc8 : 1; + uint8_t is_mlc7 : 1; + uint8_t is_mlc6 : 1; + uint8_t is_mlc5 : 1; + uint8_t is_mlc4 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_mlc_status_t; + +#define ASM330LHB_PAGE_RW 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 5; + uint8_t page_rw : 2; /* page_write + page_read */ + uint8_t emb_func_lir : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t emb_func_lir : 1; + uint8_t page_rw : 2; /* page_write + page_read */ + uint8_t not_used_01 : 5; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_page_rw_t; + +#define ASM330LHB_FSM_ENABLE_A 0x46U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm1_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm8_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm8_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm1_en : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fsm_enable_a_t; + +#define ASM330LHB_FSM_ENABLE_B 0x47U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm9_en : 1; + uint8_t fsm10_en : 1; + uint8_t fsm11_en : 1; + uint8_t fsm12_en : 1; + uint8_t fsm13_en : 1; + uint8_t fsm14_en : 1; + uint8_t fsm15_en : 1; + uint8_t fsm16_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm16_en : 1; + uint8_t fsm15_en : 1; + uint8_t fsm14_en : 1; + uint8_t fsm13_en : 1; + uint8_t fsm12_en : 1; + uint8_t fsm11_en : 1; + uint8_t fsm10_en : 1; + uint8_t fsm9_en : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fsm_enable_b_t; + +#define ASM330LHB_FSM_LONG_COUNTER_L 0x48U +#define ASM330LHB_FSM_LONG_COUNTER_H 0x49U +#define ASM330LHB_FSM_LONG_COUNTER_CLEAR 0x4AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ + uint8_t not_used_01 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 6; + uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fsm_long_counter_clear_t; + +#define ASM330LHB_FSM_OUTS1 0x4CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fsm_outs1_t; + +#define ASM330LHB_FSM_OUTS2 0x4DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fsm_outs2_t; + +#define ASM330LHB_FSM_OUTS3 0x4EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fsm_outs3_t; + +#define ASM330LHB_FSM_OUTS4 0x4FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fsm_outs4_t; + +#define ASM330LHB_FSM_OUTS5 0x50U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fsm_outs5_t; + +#define ASM330LHB_FSM_OUTS6 0x51U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fsm_outs6_t; + +#define ASM330LHB_FSM_OUTS7 0x52U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fsm_outs7_t; + +#define ASM330LHB_FSM_OUTS8 0x53U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fsm_outs8_t; + +#define ASM330LHB_FSM_OUTS9 0x54U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fsm_outs9_t; + +#define ASM330LHB_FSM_OUTS10 0x55U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fsm_outs10_t; + +#define ASM330LHB_FSM_OUTS11 0x56U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fsm_outs11_t; + +#define ASM330LHB_FSM_OUTS12 0x57U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fsm_outs12_t; + +#define ASM330LHB_FSM_OUTS13 0x58U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fsm_outs13_t; + +#define ASM330LHB_FSM_OUTS14 0x59U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fsm_outs14_t; + +#define ASM330LHB_FSM_OUTS15 0x5AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fsm_outs15_t; + +#define ASM330LHB_FSM_OUTS16 0x5BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_fsm_outs16_t; + +#define ASM330LHB_EMB_FUNC_ODR_CFG_B 0x5FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 3; + uint8_t fsm_odr : 2; + uint8_t not_used_02 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 3; + uint8_t fsm_odr : 2; + uint8_t not_used_01 : 3; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_emb_func_odr_cfg_b_t; + +#define ASM330LHB_EMB_FUNC_ODR_CFG_C 0x60U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 4; + uint8_t mlc_odr : 2; + uint8_t not_used_02 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 2; + uint8_t mlc_odr : 2; + uint8_t not_used_01 : 4; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_emb_func_odr_cfg_c_t; + +#define ASM330LHB_EMB_FUNC_INIT_B 0x67U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_init : 1; + uint8_t not_used_01 : 3; + uint8_t mlc_init : 1; + uint8_t not_used_02 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 3; + uint8_t mlc_init : 1; + uint8_t not_used_01 : 3; + uint8_t fsm_init : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhb_emb_func_init_b_t; + +#define ASM330LHB_MLC0_SRC 0x70U +#define ASM330LHB_MLC1_SRC 0x71U +#define ASM330LHB_MLC2_SRC 0x72U +#define ASM330LHB_MLC3_SRC 0x73U +#define ASM330LHB_MLC4_SRC 0x74U +#define ASM330LHB_MLC5_SRC 0x75U +#define ASM330LHB_MLC6_SRC 0x76U +#define ASM330LHB_MLC7_SRC 0x77U + +#define ASM330LHB_FSM_LC_TIMEOUT_L 0x17AU +#define ASM330LHB_FSM_LC_TIMEOUT_H 0x17BU +#define ASM330LHB_FSM_PROGRAMS 0x17CU +#define ASM330LHB_FSM_START_ADD_L 0x17EU +#define ASM330LHB_FSM_START_ADD_H 0x17FU + +/** + * @defgroup ASM330LHB_Register_Union + * @brief This union group all the registers that has a bit-field + * description. + * This union is useful but not need by the driver. + * + * REMOVING this union you are compliant with: + * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " + * + * @{ + * + */ +typedef union +{ + asm330lhb_func_cfg_access_t func_cfg_access; + asm330lhb_pin_ctrl_t pin_ctrl; + asm330lhb_fifo_ctrl1_t fifo_ctrl1; + asm330lhb_fifo_ctrl2_t fifo_ctrl2; + asm330lhb_fifo_ctrl3_t fifo_ctrl3; + asm330lhb_fifo_ctrl4_t fifo_ctrl4; + asm330lhb_counter_bdr_reg1_t counter_bdr_reg1; + asm330lhb_counter_bdr_reg2_t counter_bdr_reg2; + asm330lhb_int1_ctrl_t int1_ctrl; + asm330lhb_int2_ctrl_t int2_ctrl; + asm330lhb_ctrl1_xl_t ctrl1_xl; + asm330lhb_ctrl2_g_t ctrl2_g; + asm330lhb_ctrl3_c_t ctrl3_c; + asm330lhb_ctrl4_c_t ctrl4_c; + asm330lhb_ctrl5_c_t ctrl5_c; + asm330lhb_ctrl6_c_t ctrl6_c; + asm330lhb_ctrl7_g_t ctrl7_g; + asm330lhb_ctrl8_xl_t ctrl8_xl; + asm330lhb_ctrl9_xl_t ctrl9_xl; + asm330lhb_ctrl10_c_t ctrl10_c; + asm330lhb_all_int_src_t all_int_src; + asm330lhb_wake_up_src_t wake_up_src; + asm330lhb_d6d_src_t d6d_src; + asm330lhb_status_reg_t status_reg; + asm330lhb_fifo_status1_t fifo_status1; + asm330lhb_fifo_status2_t fifo_status2; + asm330lhb_int_cfg0_t int_cfg0; + asm330lhb_int_cfg1_t int_cfg1; + asm330lhb_ths_6d_t ths_6d; + asm330lhb_wake_up_ths_t wake_up_ths; + asm330lhb_wake_up_dur_t wake_up_dur; + asm330lhb_free_fall_t free_fall; + asm330lhb_md1_cfg_t md1_cfg; + asm330lhb_md2_cfg_t md2_cfg; + asm330lhb_i3c_bus_avb_t i3c_bus_avb; + asm330lhb_internal_freq_fine_t internal_freq_fine; + asm330lhb_fifo_data_out_tag_t fifo_data_out_tag; + asm330lhb_page_sel_t page_sel; + asm330lhb_emb_func_en_b_t emb_func_en_b; + asm330lhb_page_address_t page_address; + asm330lhb_page_value_t page_value; + asm330lhb_emb_func_int1_t emb_func_int1; + asm330lhb_fsm_int1_a_t fsm_int1_a; + asm330lhb_fsm_int1_b_t fsm_int1_b; + asm330lhb_mlc_int1_t mlc_int1; + asm330lhb_emb_func_int2_t emb_func_int2; + asm330lhb_fsm_int2_a_t fsm_int2_a; + asm330lhb_fsm_int2_b_t fsm_int2_b; + asm330lhb_mlc_int2_t mlc_int2; + asm330lhb_emb_func_status_t emb_func_status; + asm330lhb_fsm_status_a_t fsm_status_a; + asm330lhb_fsm_status_b_t fsm_status_b; + asm330lhb_mlc_status_mainpage_t mlc_status_mainpage; + asm330lhb_emb_func_odr_cfg_c_t emb_func_odr_cfg_c; + asm330lhb_page_rw_t page_rw; + asm330lhb_fsm_enable_a_t fsm_enable_a; + asm330lhb_fsm_enable_b_t fsm_enable_b; + asm330lhb_fsm_long_counter_clear_t fsm_long_counter_clear; + asm330lhb_fsm_outs1_t fsm_outs1; + asm330lhb_fsm_outs2_t fsm_outs2; + asm330lhb_fsm_outs3_t fsm_outs3; + asm330lhb_fsm_outs4_t fsm_outs4; + asm330lhb_fsm_outs5_t fsm_outs5; + asm330lhb_fsm_outs6_t fsm_outs6; + asm330lhb_fsm_outs7_t fsm_outs7; + asm330lhb_fsm_outs8_t fsm_outs8; + asm330lhb_fsm_outs9_t fsm_outs9; + asm330lhb_fsm_outs10_t fsm_outs10; + asm330lhb_fsm_outs11_t fsm_outs11; + asm330lhb_fsm_outs12_t fsm_outs12; + asm330lhb_fsm_outs13_t fsm_outs13; + asm330lhb_fsm_outs14_t fsm_outs14; + asm330lhb_fsm_outs15_t fsm_outs15; + asm330lhb_fsm_outs16_t fsm_outs16; + asm330lhb_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; + asm330lhb_emb_func_init_b_t emb_func_init_b; + bitwise_t bitwise; + uint8_t byte; +} asm330lhb_reg_t; + +/** + * @} + * + */ + +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + +int32_t asm330lhb_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, + uint16_t len); +int32_t asm330lhb_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, + uint16_t len); + +float_t asm330lhb_from_fs2g_to_mg(int16_t lsb); +float_t asm330lhb_from_fs4g_to_mg(int16_t lsb); +float_t asm330lhb_from_fs8g_to_mg(int16_t lsb); +float_t asm330lhb_from_fs16g_to_mg(int16_t lsb); +float_t asm330lhb_from_fs125dps_to_mdps(int16_t lsb); +float_t asm330lhb_from_fs250dps_to_mdps(int16_t lsb); +float_t asm330lhb_from_fs500dps_to_mdps(int16_t lsb); +float_t asm330lhb_from_fs1000dps_to_mdps(int16_t lsb); +float_t asm330lhb_from_fs2000dps_to_mdps(int16_t lsb); +float_t asm330lhb_from_fs4000dps_to_mdps(int16_t lsb); +float_t asm330lhb_from_lsb_to_celsius(int16_t lsb); +float_t asm330lhb_from_lsb_to_nsec(int32_t lsb); + +typedef enum +{ + ASM330LHB_2g = 0, + ASM330LHB_16g = 1, /* if XL_FS_MODE = '1' -> ASM330LHB_2g */ + ASM330LHB_4g = 2, + ASM330LHB_8g = 3, +} asm330lhb_fs_xl_t; +int32_t asm330lhb_xl_full_scale_set(stmdev_ctx_t *ctx, asm330lhb_fs_xl_t val); +int32_t asm330lhb_xl_full_scale_get(stmdev_ctx_t *ctx, + asm330lhb_fs_xl_t *val); + +typedef enum +{ + ASM330LHB_XL_ODR_OFF = 0, + ASM330LHB_XL_ODR_12Hz5 = 1, + ASM330LHB_XL_ODR_26Hz = 2, + ASM330LHB_XL_ODR_52Hz = 3, + ASM330LHB_XL_ODR_104Hz = 4, + ASM330LHB_XL_ODR_208Hz = 5, + ASM330LHB_XL_ODR_417Hz = 6, + ASM330LHB_XL_ODR_833Hz = 7, + ASM330LHB_XL_ODR_1667Hz = 8, + ASM330LHB_XL_ODR_1Hz6 = 11, /* (low power only) */ +} asm330lhb_odr_xl_t; +int32_t asm330lhb_xl_data_rate_set(stmdev_ctx_t *ctx, asm330lhb_odr_xl_t val); +int32_t asm330lhb_xl_data_rate_get(stmdev_ctx_t *ctx, + asm330lhb_odr_xl_t *val); + +typedef enum +{ + ASM330LHB_125dps = 2, + ASM330LHB_250dps = 0, + ASM330LHB_500dps = 4, + ASM330LHB_1000dps = 8, + ASM330LHB_2000dps = 12, + ASM330LHB_4000dps = 1, +} asm330lhb_fs_g_t; +int32_t asm330lhb_gy_full_scale_set(stmdev_ctx_t *ctx, asm330lhb_fs_g_t val); +int32_t asm330lhb_gy_full_scale_get(stmdev_ctx_t *ctx, asm330lhb_fs_g_t *val); + +typedef enum +{ + ASM330LHB_GY_ODR_OFF = 0, + ASM330LHB_GY_ODR_12Hz5 = 1, + ASM330LHB_GY_ODR_26Hz = 2, + ASM330LHB_GY_ODR_52Hz = 3, + ASM330LHB_GY_ODR_104Hz = 4, + ASM330LHB_GY_ODR_208Hz = 5, + ASM330LHB_GY_ODR_417Hz = 6, + ASM330LHB_GY_ODR_833Hz = 7, + ASM330LHB_GY_ODR_1667Hz = 8, +} asm330lhb_odr_g_t; +int32_t asm330lhb_gy_data_rate_set(stmdev_ctx_t *ctx, + asm330lhb_odr_g_t val); +int32_t asm330lhb_gy_data_rate_get(stmdev_ctx_t *ctx, + asm330lhb_odr_g_t *val); + +int32_t asm330lhb_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHB_LSb_1mg = 0, + ASM330LHB_LSb_16mg = 1, +} asm330lhb_usr_off_w_t; +int32_t asm330lhb_xl_offset_weight_set(stmdev_ctx_t *ctx, + asm330lhb_usr_off_w_t val); +int32_t asm330lhb_xl_offset_weight_get(stmdev_ctx_t *ctx, + asm330lhb_usr_off_w_t *val); + +typedef enum +{ + ASM330LHB_HIGH_PERFORMANCE_MD = 0, + ASM330LHB_LOW_NORMAL_POWER_MD = 1, +} asm330lhb_xl_hm_mode_t; +int32_t asm330lhb_xl_power_mode_set(stmdev_ctx_t *ctx, + asm330lhb_xl_hm_mode_t val); +int32_t asm330lhb_xl_power_mode_get(stmdev_ctx_t *ctx, + asm330lhb_xl_hm_mode_t *val); + +typedef enum +{ + ASM330LHB_GY_HIGH_PERFORMANCE = 0, + ASM330LHB_GY_NORMAL = 1, +} asm330lhb_g_hm_mode_t; +int32_t asm330lhb_gy_power_mode_set(stmdev_ctx_t *ctx, + asm330lhb_g_hm_mode_t val); +int32_t asm330lhb_gy_power_mode_get(stmdev_ctx_t *ctx, + asm330lhb_g_hm_mode_t *val); + +typedef struct +{ + asm330lhb_all_int_src_t all_int_src; + asm330lhb_wake_up_src_t wake_up_src; + asm330lhb_d6d_src_t d6d_src; + asm330lhb_status_reg_t status_reg; + asm330lhb_emb_func_status_t emb_func_status; + asm330lhb_fsm_status_a_t fsm_status_a; + asm330lhb_fsm_status_b_t fsm_status_b; + asm330lhb_mlc_status_mainpage_t mlc_status; +} asm330lhb_all_sources_t; +int32_t asm330lhb_all_sources_get(stmdev_ctx_t *ctx, + asm330lhb_all_sources_t *val); + +int32_t asm330lhb_status_reg_get(stmdev_ctx_t *ctx, + asm330lhb_status_reg_t *val); + +int32_t asm330lhb_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhb_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhb_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhb_boot_device_status_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhb_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t asm330lhb_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t asm330lhb_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t asm330lhb_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t asm330lhb_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t asm330lhb_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t asm330lhb_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhb_timestamp_rst(stmdev_ctx_t *ctx); + +int32_t asm330lhb_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhb_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); + +typedef enum +{ + ASM330LHB_NO_ROUND = 0, + ASM330LHB_ROUND_XL = 1, + ASM330LHB_ROUND_GY = 2, + ASM330LHB_ROUND_GY_XL = 3, +} asm330lhb_rounding_t; +int32_t asm330lhb_rounding_mode_set(stmdev_ctx_t *ctx, + asm330lhb_rounding_t val); +int32_t asm330lhb_rounding_mode_get(stmdev_ctx_t *ctx, + asm330lhb_rounding_t *val); + +int32_t asm330lhb_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); + +int32_t asm330lhb_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val); + +int32_t asm330lhb_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); + +int32_t asm330lhb_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhb_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHB_USER_BANK = 0, + ASM330LHB_EMBEDDED_FUNC_BANK = 1, +} asm330lhb_reg_access_t; +int32_t asm330lhb_mem_bank_set(stmdev_ctx_t *ctx, asm330lhb_reg_access_t val); +int32_t asm330lhb_mem_bank_get(stmdev_ctx_t *ctx, + asm330lhb_reg_access_t *val); + +int32_t asm330lhb_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address, + uint8_t *val); +int32_t asm330lhb_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, + uint8_t *buf, uint8_t len); +int32_t asm330lhb_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add, + uint8_t *val); +int32_t asm330lhb_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, + uint8_t *val); + +typedef enum +{ + ASM330LHB_DRDY_LATCHED = 0, + ASM330LHB_DRDY_PULSED = 1, +} asm330lhb_dataready_pulsed_t; +int32_t asm330lhb_data_ready_mode_set(stmdev_ctx_t *ctx, + asm330lhb_dataready_pulsed_t val); +int32_t asm330lhb_data_ready_mode_get(stmdev_ctx_t *ctx, + asm330lhb_dataready_pulsed_t *val); + +int32_t asm330lhb_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t asm330lhb_reset_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_reset_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhb_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhb_boot_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_boot_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHB_XL_ST_DISABLE = 0, + ASM330LHB_XL_ST_POSITIVE = 1, + ASM330LHB_XL_ST_NEGATIVE = 2, +} asm330lhb_st_xl_t; +int32_t asm330lhb_xl_self_test_set(stmdev_ctx_t *ctx, asm330lhb_st_xl_t val); +int32_t asm330lhb_xl_self_test_get(stmdev_ctx_t *ctx, asm330lhb_st_xl_t *val); + +typedef enum +{ + ASM330LHB_GY_ST_DISABLE = 0, + ASM330LHB_GY_ST_POSITIVE = 1, + ASM330LHB_GY_ST_NEGATIVE = 3, +} asm330lhb_st_g_t; +int32_t asm330lhb_gy_self_test_set(stmdev_ctx_t *ctx, asm330lhb_st_g_t val); +int32_t asm330lhb_gy_self_test_get(stmdev_ctx_t *ctx, asm330lhb_st_g_t *val); + +int32_t asm330lhb_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhb_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhb_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHB_ULTRA_LIGHT = 0, + ASM330LHB_VERY_LIGHT = 1, + ASM330LHB_LIGHT = 2, + ASM330LHB_MEDIUM = 3, + ASM330LHB_STRONG = 4, + ASM330LHB_VERY_STRONG = 5, + ASM330LHB_AGGRESSIVE = 6, + ASM330LHB_XTREME = 7, +} asm330lhb_ftype_t; +int32_t asm330lhb_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, + asm330lhb_ftype_t val); +int32_t asm330lhb_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, + asm330lhb_ftype_t *val); + +int32_t asm330lhb_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHB_HP_PATH_DISABLE_ON_OUT = 0x00, + ASM330LHB_SLOPE_ODR_DIV_4 = 0x10, + ASM330LHB_HP_ODR_DIV_10 = 0x11, + ASM330LHB_HP_ODR_DIV_20 = 0x12, + ASM330LHB_HP_ODR_DIV_45 = 0x13, + ASM330LHB_HP_ODR_DIV_100 = 0x14, + ASM330LHB_HP_ODR_DIV_200 = 0x15, + ASM330LHB_HP_ODR_DIV_400 = 0x16, + ASM330LHB_HP_ODR_DIV_800 = 0x17, + ASM330LHB_HP_REF_MD_ODR_DIV_10 = 0x31, + ASM330LHB_HP_REF_MD_ODR_DIV_20 = 0x32, + ASM330LHB_HP_REF_MD_ODR_DIV_45 = 0x33, + ASM330LHB_HP_REF_MD_ODR_DIV_100 = 0x34, + ASM330LHB_HP_REF_MD_ODR_DIV_200 = 0x35, + ASM330LHB_HP_REF_MD_ODR_DIV_400 = 0x36, + ASM330LHB_HP_REF_MD_ODR_DIV_800 = 0x37, + ASM330LHB_LP_ODR_DIV_10 = 0x01, + ASM330LHB_LP_ODR_DIV_20 = 0x02, + ASM330LHB_LP_ODR_DIV_45 = 0x03, + ASM330LHB_LP_ODR_DIV_100 = 0x04, + ASM330LHB_LP_ODR_DIV_200 = 0x05, + ASM330LHB_LP_ODR_DIV_400 = 0x06, + ASM330LHB_LP_ODR_DIV_800 = 0x07, +} asm330lhb_hp_slope_xl_en_t; +int32_t asm330lhb_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, + asm330lhb_hp_slope_xl_en_t val); +int32_t asm330lhb_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, + asm330lhb_hp_slope_xl_en_t *val); + +int32_t asm330lhb_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHB_USE_SLOPE = 0, + ASM330LHB_USE_HPF = 1, +} asm330lhb_slope_fds_t; +int32_t asm330lhb_xl_hp_path_internal_set(stmdev_ctx_t *ctx, + asm330lhb_slope_fds_t val); +int32_t asm330lhb_xl_hp_path_internal_get(stmdev_ctx_t *ctx, + asm330lhb_slope_fds_t *val); + +typedef enum +{ + ASM330LHB_HP_FILTER_NONE = 0x00, + ASM330LHB_HP_FILTER_16mHz = 0x80, + ASM330LHB_HP_FILTER_65mHz = 0x81, + ASM330LHB_HP_FILTER_260mHz = 0x82, + ASM330LHB_HP_FILTER_1Hz04 = 0x83, +} asm330lhb_hpm_g_t; +int32_t asm330lhb_gy_hp_path_internal_set(stmdev_ctx_t *ctx, + asm330lhb_hpm_g_t val); +int32_t asm330lhb_gy_hp_path_internal_get(stmdev_ctx_t *ctx, + asm330lhb_hpm_g_t *val); + +typedef enum +{ + ASM330LHB_PULL_UP_DISC = 0, + ASM330LHB_PULL_UP_CONNECT = 1, +} asm330lhb_sdo_pu_en_t; +int32_t asm330lhb_sdo_sa0_mode_set(stmdev_ctx_t *ctx, + asm330lhb_sdo_pu_en_t val); +int32_t asm330lhb_sdo_sa0_mode_get(stmdev_ctx_t *ctx, + asm330lhb_sdo_pu_en_t *val); + +typedef enum +{ + ASM330LHB_PULL_DOWN_CONNECT = 0, + ASM330LHB_PULL_DOWN_DISC = 1, +} asm330lhb_pd_dis_int1_t; +int32_t asm330lhb_int1_mode_set(stmdev_ctx_t *ctx, + asm330lhb_pd_dis_int1_t val); +int32_t asm330lhb_int1_mode_get(stmdev_ctx_t *ctx, + asm330lhb_pd_dis_int1_t *val); + +typedef enum +{ + ASM330LHB_SPI_4_WIRE = 0, + ASM330LHB_SPI_3_WIRE = 1, +} asm330lhb_sim_t; +int32_t asm330lhb_spi_mode_set(stmdev_ctx_t *ctx, asm330lhb_sim_t val); +int32_t asm330lhb_spi_mode_get(stmdev_ctx_t *ctx, asm330lhb_sim_t *val); + +typedef enum +{ + ASM330LHB_I2C_ENABLE = 0, + ASM330LHB_I2C_DISABLE = 1, +} asm330lhb_i2c_disable_t; +int32_t asm330lhb_i2c_interface_set(stmdev_ctx_t *ctx, + asm330lhb_i2c_disable_t val); +int32_t asm330lhb_i2c_interface_get(stmdev_ctx_t *ctx, + asm330lhb_i2c_disable_t *val); + +typedef enum +{ + ASM330LHB_I3C_DISABLE = 0x80, + ASM330LHB_I3C_ENABLE_T_50us = 0x00, + ASM330LHB_I3C_ENABLE_T_2us = 0x01, + ASM330LHB_I3C_ENABLE_T_1ms = 0x02, + ASM330LHB_I3C_ENABLE_T_25ms = 0x03, +} asm330lhb_i3c_disable_t; +int32_t asm330lhb_i3c_disable_set(stmdev_ctx_t *ctx, + asm330lhb_i3c_disable_t val); +int32_t asm330lhb_i3c_disable_get(stmdev_ctx_t *ctx, + asm330lhb_i3c_disable_t *val); + +typedef struct +{ + asm330lhb_int1_ctrl_t int1_ctrl; + asm330lhb_md1_cfg_t md1_cfg; + asm330lhb_emb_func_int1_t emb_func_int1; + asm330lhb_fsm_int1_a_t fsm_int1_a; + asm330lhb_fsm_int1_b_t fsm_int1_b; + asm330lhb_mlc_int1_t mlc_int1; +} asm330lhb_pin_int1_route_t; +int32_t asm330lhb_pin_int1_route_set(stmdev_ctx_t *ctx, + asm330lhb_pin_int1_route_t *val); +int32_t asm330lhb_pin_int1_route_get(stmdev_ctx_t *ctx, + asm330lhb_pin_int1_route_t *val); + +typedef struct +{ + asm330lhb_int2_ctrl_t int2_ctrl; + asm330lhb_md2_cfg_t md2_cfg; + asm330lhb_emb_func_int2_t emb_func_int2; + asm330lhb_fsm_int2_a_t fsm_int2_a; + asm330lhb_fsm_int2_b_t fsm_int2_b; + asm330lhb_mlc_int2_t mlc_int2; +} asm330lhb_pin_int2_route_t; +int32_t asm330lhb_pin_int2_route_set(stmdev_ctx_t *ctx, + asm330lhb_pin_int2_route_t *val); +int32_t asm330lhb_pin_int2_route_get(stmdev_ctx_t *ctx, + asm330lhb_pin_int2_route_t *val); + +typedef enum +{ + ASM330LHB_PUSH_PULL = 0, + ASM330LHB_OPEN_DRAIN = 1, +} asm330lhb_pp_od_t; +int32_t asm330lhb_pin_mode_set(stmdev_ctx_t *ctx, asm330lhb_pp_od_t val); +int32_t asm330lhb_pin_mode_get(stmdev_ctx_t *ctx, asm330lhb_pp_od_t *val); + +typedef enum +{ + ASM330LHB_ACTIVE_HIGH = 0, + ASM330LHB_ACTIVE_LOW = 1, +} asm330lhb_h_lactive_t; +int32_t asm330lhb_pin_polarity_set(stmdev_ctx_t *ctx, + asm330lhb_h_lactive_t val); +int32_t asm330lhb_pin_polarity_get(stmdev_ctx_t *ctx, + asm330lhb_h_lactive_t *val); + +int32_t asm330lhb_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHB_ALL_INT_PULSED = 0, + ASM330LHB_BASE_LATCHED_EMB_PULSED = 1, + ASM330LHB_BASE_PULSED_EMB_LATCHED = 2, + ASM330LHB_ALL_INT_LATCHED = 3, +} asm330lhb_lir_t; +int32_t asm330lhb_int_notification_set(stmdev_ctx_t *ctx, + asm330lhb_lir_t val); +int32_t asm330lhb_int_notification_get(stmdev_ctx_t *ctx, + asm330lhb_lir_t *val); + +typedef enum +{ + ASM330LHB_LSb_FS_DIV_64 = 0, + ASM330LHB_LSb_FS_DIV_256 = 1, +} asm330lhb_wake_ths_w_t; +int32_t asm330lhb_wkup_ths_weight_set(stmdev_ctx_t *ctx, + asm330lhb_wake_ths_w_t val); +int32_t asm330lhb_wkup_ths_weight_get(stmdev_ctx_t *ctx, + asm330lhb_wake_ths_w_t *val); + +int32_t asm330lhb_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhb_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, + uint8_t val); +int32_t asm330lhb_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t asm330lhb_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhb_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHB_DRIVE_SLEEP_CHG_EVENT = 0, + ASM330LHB_DRIVE_SLEEP_STATUS = 1, +} asm330lhb_sleep_status_on_int_t; +int32_t asm330lhb_act_pin_notification_set(stmdev_ctx_t *ctx, + asm330lhb_sleep_status_on_int_t val); +int32_t asm330lhb_act_pin_notification_get(stmdev_ctx_t *ctx, + asm330lhb_sleep_status_on_int_t *val); + +typedef enum +{ + ASM330LHB_XL_AND_GY_NOT_AFFECTED = 0, + ASM330LHB_XL_12Hz5_GY_NOT_AFFECTED = 1, + ASM330LHB_XL_12Hz5_GY_SLEEP = 2, + ASM330LHB_XL_12Hz5_GY_PD = 3, +} asm330lhb_inact_en_t; +int32_t asm330lhb_act_mode_set(stmdev_ctx_t *ctx, + asm330lhb_inact_en_t val); +int32_t asm330lhb_act_mode_get(stmdev_ctx_t *ctx, + asm330lhb_inact_en_t *val); + +int32_t asm330lhb_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHB_DEG_80 = 0, + ASM330LHB_DEG_70 = 1, + ASM330LHB_DEG_60 = 2, + ASM330LHB_DEG_50 = 3, +} asm330lhb_sixd_ths_t; +int32_t asm330lhb_6d_threshold_set(stmdev_ctx_t *ctx, + asm330lhb_sixd_ths_t val); +int32_t asm330lhb_6d_threshold_get(stmdev_ctx_t *ctx, + asm330lhb_sixd_ths_t *val); + +int32_t asm330lhb_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHB_FF_TSH_156mg = 0, + ASM330LHB_FF_TSH_219mg = 1, + ASM330LHB_FF_TSH_250mg = 2, + ASM330LHB_FF_TSH_312mg = 3, + ASM330LHB_FF_TSH_344mg = 4, + ASM330LHB_FF_TSH_406mg = 5, + ASM330LHB_FF_TSH_469mg = 6, + ASM330LHB_FF_TSH_500mg = 7, +} asm330lhb_ff_ths_t; +int32_t asm330lhb_ff_threshold_set(stmdev_ctx_t *ctx, + asm330lhb_ff_ths_t val); +int32_t asm330lhb_ff_threshold_get(stmdev_ctx_t *ctx, + asm330lhb_ff_ths_t *val); + +int32_t asm330lhb_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhb_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val); +int32_t asm330lhb_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val); + +int32_t asm330lhb_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, + uint8_t val); +int32_t asm330lhb_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t asm330lhb_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHB_XL_NOT_BATCHED = 0, + ASM330LHB_XL_BATCHED_AT_12Hz5 = 1, + ASM330LHB_XL_BATCHED_AT_26Hz = 2, + ASM330LHB_XL_BATCHED_AT_52Hz = 3, + ASM330LHB_XL_BATCHED_AT_104Hz = 4, + ASM330LHB_XL_BATCHED_AT_208Hz = 5, + ASM330LHB_XL_BATCHED_AT_417Hz = 6, + ASM330LHB_XL_BATCHED_AT_833Hz = 7, + ASM330LHB_XL_BATCHED_AT_1667Hz = 8, + ASM330LHB_XL_BATCHED_AT_1Hz6 = 11, +} asm330lhb_bdr_xl_t; +int32_t asm330lhb_fifo_xl_batch_set(stmdev_ctx_t *ctx, + asm330lhb_bdr_xl_t val); +int32_t asm330lhb_fifo_xl_batch_get(stmdev_ctx_t *ctx, + asm330lhb_bdr_xl_t *val); + +typedef enum +{ + ASM330LHB_GY_NOT_BATCHED = 0, + ASM330LHB_GY_BATCHED_AT_12Hz5 = 1, + ASM330LHB_GY_BATCHED_AT_26Hz = 2, + ASM330LHB_GY_BATCHED_AT_52Hz = 3, + ASM330LHB_GY_BATCHED_AT_104Hz = 4, + ASM330LHB_GY_BATCHED_AT_208Hz = 5, + ASM330LHB_GY_BATCHED_AT_417Hz = 6, + ASM330LHB_GY_BATCHED_AT_833Hz = 7, + ASM330LHB_GY_BATCHED_AT_1667Hz = 8, + ASM330LHB_GY_BATCHED_AT_6Hz5 = 11, +} asm330lhb_bdr_gy_t; +int32_t asm330lhb_fifo_gy_batch_set(stmdev_ctx_t *ctx, + asm330lhb_bdr_gy_t val); +int32_t asm330lhb_fifo_gy_batch_get(stmdev_ctx_t *ctx, + asm330lhb_bdr_gy_t *val); + +typedef enum +{ + ASM330LHB_BYPASS_MODE = 0, + ASM330LHB_FIFO_MODE = 1, + ASM330LHB_STREAM_TO_FIFO_MODE = 3, + ASM330LHB_BYPASS_TO_STREAM_MODE = 4, + ASM330LHB_STREAM_MODE = 6, + ASM330LHB_BYPASS_TO_FIFO_MODE = 7, +} asm330lhb_fifo_mode_t; +int32_t asm330lhb_fifo_mode_set(stmdev_ctx_t *ctx, asm330lhb_fifo_mode_t val); +int32_t asm330lhb_fifo_mode_get(stmdev_ctx_t *ctx, + asm330lhb_fifo_mode_t *val); + +typedef enum +{ + ASM330LHB_TEMP_NOT_BATCHED = 0, + ASM330LHB_TEMP_BATCHED_AT_52Hz = 1, + ASM330LHB_TEMP_BATCHED_AT_12Hz5 = 2, + ASM330LHB_TEMP_BATCHED_AT_1Hz6 = 3, +} asm330lhb_odr_t_batch_t; +int32_t asm330lhb_fifo_temp_batch_set(stmdev_ctx_t *ctx, + asm330lhb_odr_t_batch_t val); +int32_t asm330lhb_fifo_temp_batch_get(stmdev_ctx_t *ctx, + asm330lhb_odr_t_batch_t *val); + +typedef enum +{ + ASM330LHB_NO_DECIMATION = 0, + ASM330LHB_DEC_1 = 1, + ASM330LHB_DEC_8 = 2, + ASM330LHB_DEC_32 = 3, +} asm330lhb_dec_ts_batch_t; +int32_t asm330lhb_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, + asm330lhb_dec_ts_batch_t val); +int32_t asm330lhb_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, + asm330lhb_dec_ts_batch_t *val); + +typedef enum +{ + ASM330LHB_XL_BATCH_EVENT = 0, + ASM330LHB_GYRO_BATCH_EVENT = 1, +} asm330lhb_trig_counter_bdr_t; +int32_t asm330lhb_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, + asm330lhb_trig_counter_bdr_t val); +int32_t asm330lhb_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, + asm330lhb_trig_counter_bdr_t *val); + +int32_t asm330lhb_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhb_batch_counter_threshold_set(stmdev_ctx_t *ctx, + uint16_t val); +int32_t asm330lhb_batch_counter_threshold_get(stmdev_ctx_t *ctx, + uint16_t *val); + +int32_t asm330lhb_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val); + +int32_t asm330lhb_fifo_status_get(stmdev_ctx_t *ctx, + asm330lhb_fifo_status2_t *val); + +int32_t asm330lhb_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhb_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhb_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHB_GYRO_NC_TAG = 0x01, + ASM330LHB_XL_NC_TAG = 0x02, + ASM330LHB_TEMPERATURE_TAG = 0x03, + ASM330LHB_TIMESTAMP_TAG = 0x04, + ASM330LHB_CFG_CHANGE_TAG = 0x05, +} asm330lhb_fifo_tag_t; +int32_t asm330lhb_fifo_sensor_tag_get(stmdev_ctx_t *ctx, + asm330lhb_fifo_tag_t *val); + +typedef enum +{ + ASM330LHB_DEN_DISABLE = 0, + ASM330LHB_LEVEL_FIFO = 6, + ASM330LHB_LEVEL_LETCHED = 3, + ASM330LHB_LEVEL_TRIGGER = 2, + ASM330LHB_EDGE_TRIGGER = 4, +} asm330lhb_den_mode_t; +int32_t asm330lhb_den_mode_set(stmdev_ctx_t *ctx, + asm330lhb_den_mode_t val); +int32_t asm330lhb_den_mode_get(stmdev_ctx_t *ctx, + asm330lhb_den_mode_t *val); + +typedef enum +{ + ASM330LHB_DEN_ACT_LOW = 0, + ASM330LHB_DEN_ACT_HIGH = 1, +} asm330lhb_den_lh_t; +int32_t asm330lhb_den_polarity_set(stmdev_ctx_t *ctx, + asm330lhb_den_lh_t val); +int32_t asm330lhb_den_polarity_get(stmdev_ctx_t *ctx, + asm330lhb_den_lh_t *val); + +typedef enum +{ + ASM330LHB_STAMP_IN_GY_DATA = 0, + ASM330LHB_STAMP_IN_XL_DATA = 1, + ASM330LHB_STAMP_IN_GY_XL_DATA = 2, +} asm330lhb_den_xl_g_t; +int32_t asm330lhb_den_enable_set(stmdev_ctx_t *ctx, + asm330lhb_den_xl_g_t val); +int32_t asm330lhb_den_enable_get(stmdev_ctx_t *ctx, + asm330lhb_den_xl_g_t *val); + +int32_t asm330lhb_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhb_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhb_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhb_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val); +int32_t asm330lhb_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val); + +int32_t asm330lhb_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val); +int32_t asm330lhb_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val); + +int32_t asm330lhb_mag_soft_iron_set(stmdev_ctx_t *ctx, uint16_t *val); +int32_t asm330lhb_mag_soft_iron_get(stmdev_ctx_t *ctx, uint16_t *val); + +typedef enum +{ + ASM330LHB_Z_EQ_Y = 0, + ASM330LHB_Z_EQ_MIN_Y = 1, + ASM330LHB_Z_EQ_X = 2, + ASM330LHB_Z_EQ_MIN_X = 3, + ASM330LHB_Z_EQ_MIN_Z = 4, + ASM330LHB_Z_EQ_Z = 5, +} asm330lhb_mag_z_axis_t; +int32_t asm330lhb_mag_z_orient_set(stmdev_ctx_t *ctx, + asm330lhb_mag_z_axis_t val); +int32_t asm330lhb_mag_z_orient_get(stmdev_ctx_t *ctx, + asm330lhb_mag_z_axis_t *val); + +typedef enum +{ + ASM330LHB_Y_EQ_Y = 0, + ASM330LHB_Y_EQ_MIN_Y = 1, + ASM330LHB_Y_EQ_X = 2, + ASM330LHB_Y_EQ_MIN_X = 3, + ASM330LHB_Y_EQ_MIN_Z = 4, + ASM330LHB_Y_EQ_Z = 5, +} asm330lhb_mag_y_axis_t; +int32_t asm330lhb_mag_y_orient_set(stmdev_ctx_t *ctx, + asm330lhb_mag_y_axis_t val); +int32_t asm330lhb_mag_y_orient_get(stmdev_ctx_t *ctx, + asm330lhb_mag_y_axis_t *val); + +typedef enum +{ + ASM330LHB_X_EQ_Y = 0, + ASM330LHB_X_EQ_MIN_Y = 1, + ASM330LHB_X_EQ_X = 2, + ASM330LHB_X_EQ_MIN_X = 3, + ASM330LHB_X_EQ_MIN_Z = 4, + ASM330LHB_X_EQ_Z = 5, +} asm330lhb_mag_x_axis_t; +int32_t asm330lhb_mag_x_orient_set(stmdev_ctx_t *ctx, + asm330lhb_mag_x_axis_t val); +int32_t asm330lhb_mag_x_orient_get(stmdev_ctx_t *ctx, + asm330lhb_mag_x_axis_t *val); + +typedef struct +{ + uint16_t fsm1 : 1; + uint16_t fsm2 : 1; + uint16_t fsm3 : 1; + uint16_t fsm4 : 1; + uint16_t fsm5 : 1; + uint16_t fsm6 : 1; + uint16_t fsm7 : 1; + uint16_t fsm8 : 1; + uint16_t fsm9 : 1; + uint16_t fsm10 : 1; + uint16_t fsm11 : 1; + uint16_t fsm12 : 1; + uint16_t fsm13 : 1; + uint16_t fsm14 : 1; + uint16_t fsm15 : 1; + uint16_t fsm16 : 1; +} asm330lhb_fsm_status_t; +int32_t asm330lhb_fsm_status_get(stmdev_ctx_t *ctx, + asm330lhb_fsm_status_t *val); +int32_t asm330lhb_fsm_out_get(stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t asm330lhb_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t asm330lhb_emb_func_clk_dis_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_emb_func_clk_dis_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhb_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + asm330lhb_fsm_enable_a_t fsm_enable_a; + asm330lhb_fsm_enable_b_t fsm_enable_b; +} asm330lhb_emb_fsm_enable_t; +int32_t asm330lhb_fsm_enable_set(stmdev_ctx_t *ctx, + asm330lhb_emb_fsm_enable_t *val); +int32_t asm330lhb_fsm_enable_get(stmdev_ctx_t *ctx, + asm330lhb_emb_fsm_enable_t *val); + +int32_t asm330lhb_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val); +int32_t asm330lhb_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val); + +typedef enum +{ + ASM330LHB_LC_NORMAL = 0, + ASM330LHB_LC_CLEAR = 1, + ASM330LHB_LC_CLEAR_DONE = 2, +} asm330lhb_fsm_lc_clr_t; +int32_t asm330lhb_long_clr_set(stmdev_ctx_t *ctx, + asm330lhb_fsm_lc_clr_t val); +int32_t asm330lhb_long_clr_get(stmdev_ctx_t *ctx, + asm330lhb_fsm_lc_clr_t *val); + +typedef enum +{ + ASM330LHB_ODR_FSM_12Hz5 = 0, + ASM330LHB_ODR_FSM_26Hz = 1, + ASM330LHB_ODR_FSM_52Hz = 2, + ASM330LHB_ODR_FSM_104Hz = 3, +} asm330lhb_fsm_odr_t; +int32_t asm330lhb_fsm_data_rate_set(stmdev_ctx_t *ctx, + asm330lhb_fsm_odr_t val); +int32_t asm330lhb_fsm_data_rate_get(stmdev_ctx_t *ctx, + asm330lhb_fsm_odr_t *val); + +int32_t asm330lhb_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhb_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint16_t val); +int32_t asm330lhb_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint16_t *val); + +int32_t asm330lhb_fsm_number_of_programs_set(stmdev_ctx_t *ctx, + uint8_t *buff); +int32_t asm330lhb_fsm_number_of_programs_get(stmdev_ctx_t *ctx, + uint8_t *buff); + +int32_t asm330lhb_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val); +int32_t asm330lhb_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val); + +int32_t asm330lhb_mlc_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_mlc_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhb_mlc_status_get(stmdev_ctx_t *ctx, + asm330lhb_mlc_status_mainpage_t *val); + +typedef enum +{ + ASM330LHB_ODR_PRGS_12Hz5 = 0, + ASM330LHB_ODR_PRGS_26Hz = 1, + ASM330LHB_ODR_PRGS_52Hz = 2, + ASM330LHB_ODR_PRGS_104Hz = 3, +} asm330lhb_mlc_odr_t; +int32_t asm330lhb_mlc_data_rate_set(stmdev_ctx_t *ctx, + asm330lhb_mlc_odr_t val); +int32_t asm330lhb_mlc_data_rate_get(stmdev_ctx_t *ctx, + asm330lhb_mlc_odr_t *val); + +int32_t asm330lhb_mlc_init_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_mlc_init_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhb_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t asm330lhb_mlc_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val); +int32_t asm330lhb_mlc_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val); + +/** + *@} + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ASM330LHB_REGS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.c b/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.c index bb79669c33271fda525a52d5aa35358085174b91..4a8a5b4486119ffd637a17c48138738d741cae19 100644 --- a/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.c +++ b/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t asm330lhh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak asm330lhh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t asm330lhh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t asm330lhh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak asm330lhh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -303,8 +303,8 @@ int32_t asm330lhh_xl_data_rate_get(stmdev_ctx_t *ctx, *val = ASM330LHH_XL_ODR_208Hz; break; - case ASM330LHH_XL_ODR_416Hz: - *val = ASM330LHH_XL_ODR_416Hz; + case ASM330LHH_XL_ODR_417Hz: + *val = ASM330LHH_XL_ODR_417Hz; break; case ASM330LHH_XL_ODR_833Hz: @@ -473,8 +473,8 @@ int32_t asm330lhh_gy_data_rate_get(stmdev_ctx_t *ctx, *val = ASM330LHH_GY_ODR_208Hz; break; - case ASM330LHH_GY_ODR_416Hz: - *val = ASM330LHH_GY_ODR_416Hz; + case ASM330LHH_GY_ODR_417Hz: + *val = ASM330LHH_GY_ODR_417Hz; break; case ASM330LHH_GY_ODR_833Hz: @@ -612,7 +612,7 @@ int32_t asm330lhh_xl_offset_weight_get(stmdev_ctx_t *ctx, *[get] * @param ctx Read / write interface definitions.(ptr) * @param val Get registers ALL_INT_SRC; WAKE_UP_SRC; - * TAP_SRC; D6D_SRC; STATUS_REG; + * D6D_SRC; STATUS_REG; * EMB_FUNC_STATUS; FSM_STATUS_A/B * @retval Interface status (MANDATORY: return 0 -> no Error). * @@ -3949,8 +3949,8 @@ int32_t asm330lhh_fifo_gy_batch_get(stmdev_ctx_t *ctx, *val = ASM330LHH_GY_BATCHED_AT_6667Hz; break; - case ASM330LHH_GY_BATCHED_6Hz5: - *val = ASM330LHH_GY_BATCHED_6Hz5; + case ASM330LHH_GY_BATCHED_AT_6Hz5: + *val = ASM330LHH_GY_BATCHED_AT_6Hz5; break; default: @@ -4132,7 +4132,7 @@ int32_t asm330lhh_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, if (ret == 0) { - fifo_ctrl4.odr_ts_batch = (uint8_t)val; + fifo_ctrl4.dec_ts_batch = (uint8_t)val; ret = asm330lhh_write_reg(ctx, ASM330LHH_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); } @@ -4160,7 +4160,7 @@ int32_t asm330lhh_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); - switch (fifo_ctrl4.odr_ts_batch) + switch (fifo_ctrl4.dec_ts_batch) { case ASM330LHH_NO_DECIMATION: *val = ASM330LHH_NO_DECIMATION; @@ -4323,7 +4323,7 @@ int32_t asm330lhh_batch_counter_threshold_set(stmdev_ctx_t *ctx, if (ret == 0) { - counter_bdr_reg1.cnt_bdr_th = (uint8_t)((val / 256U) & 0x07U); + counter_bdr_reg1.cnt_bdr_th = (uint8_t)((val / 256U) & 0x03U); ret = asm330lhh_write_reg(ctx, ASM330LHH_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); } diff --git a/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.h b/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.h index bc714e4389c31840eae93ac7b104e8383069bf46..28cc0d985356ae26b10db40e1a0228870d7f8717 100644 --- a/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.h +++ b/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -234,9 +237,9 @@ typedef struct uint8_t fifo_mode : 3; uint8_t not_used_01 : 1; uint8_t odr_t_batch : 2; - uint8_t odr_ts_batch : 2; + uint8_t dec_ts_batch : 2; #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t odr_ts_batch : 2; + uint8_t dec_ts_batch : 2; uint8_t odr_t_batch : 2; uint8_t not_used_01 : 1; uint8_t fifo_mode : 3; @@ -247,8 +250,8 @@ typedef struct typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t cnt_bdr_th : 3; - uint8_t not_used_01 : 2; + uint8_t cnt_bdr_th : 2; + uint8_t not_used_01 : 3; uint8_t trig_counter_bdr : 1; uint8_t rst_counter_bdr : 1; uint8_t dataready_pulsed : 1; @@ -256,8 +259,8 @@ typedef struct uint8_t dataready_pulsed : 1; uint8_t rst_counter_bdr : 1; uint8_t trig_counter_bdr : 1; - uint8_t not_used_01 : 2; - uint8_t cnt_bdr_th : 3; + uint8_t not_used_01 : 3; + uint8_t cnt_bdr_th : 2; #endif /* DRV_BYTE_ORDER */ } asm330lhh_counter_bdr_reg1_t; @@ -417,11 +420,9 @@ typedef struct uint8_t ftype : 3; uint8_t usr_off_w : 1; uint8_t not_used_01 : 1; -uint8_t den_mode : - 3; /* trig_en + lvl1_en + lvl2_en */ + uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN -uint8_t den_mode : - 3; /* trig_en + lvl1_en + lvl2_en */ + uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ uint8_t not_used_01 : 1; uint8_t usr_off_w : 1; uint8_t ftype : 3; @@ -512,13 +513,13 @@ typedef struct uint8_t wu_ia : 1; uint8_t not_used_01 : 2; uint8_t d6d_ia : 1; - uint8_t sleep_change : 1; + uint8_t sleep_change_ia : 1; uint8_t not_used_02 : 1; uint8_t timestamp_endcount : 1; #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN uint8_t timestamp_endcount : 1; uint8_t not_used_02 : 1; - uint8_t sleep_change : 1; + uint8_t sleep_change_ia : 1; uint8_t d6d_ia : 1; uint8_t not_used_01 : 2; uint8_t wu_ia : 1; @@ -534,13 +535,15 @@ typedef struct uint8_t y_wu : 1; uint8_t x_wu : 1; uint8_t wu_ia : 1; - uint8_t sleep_change : 1; + uint8_t sleep_state : 1; uint8_t ff_ia : 1; - uint8_t not_used_01 : 2; + uint8_t sleep_change_ia : 1; + uint8_t not_used_01 : 1; #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 2; + uint8_t not_used_01 : 1; + uint8_t sleep_change_ia : 1; uint8_t ff_ia : 1; - uint8_t sleep_change : 1; + uint8_t sleep_state : 1; uint8_t wu_ia : 1; uint8_t x_wu : 1; uint8_t y_wu : 1; @@ -548,30 +551,6 @@ typedef struct #endif /* DRV_BYTE_ORDER */ } asm330lhh_wake_up_src_t; -#define ASM330LHH_TAP_SRC 0x1CU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t z_tap : 1; - uint8_t y_tap : 1; - uint8_t x_tap : 1; - uint8_t tap_sign : 1; - uint8_t double_tap : 1; - uint8_t single_tap : 1; - uint8_t tap_ia : 1; - uint8_t not_used_01 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 1; - uint8_t tap_ia : 1; - uint8_t single_tap : 1; - uint8_t double_tap : 1; - uint8_t tap_sign : 1; - uint8_t x_tap : 1; - uint8_t y_tap : 1; - uint8_t z_tap : 1; -#endif /* DRV_BYTE_ORDER */ -} asm330lhh_tap_src_t; - #define ASM330LHH_D6D_SRC 0x1DU typedef struct { @@ -638,7 +617,7 @@ typedef struct #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t diff_fifo : 2; uint8_t not_used_01 : 1; - uint8_t over_run_latched : 1; + uint8_t fifo_ovr_latched : 1; uint8_t counter_bdr_ia : 1; uint8_t fifo_full_ia : 1; uint8_t fifo_ovr_ia : 1; @@ -648,7 +627,7 @@ typedef struct uint8_t fifo_ovr_ia : 1; uint8_t fifo_full_ia : 1; uint8_t counter_bdr_ia : 1; - uint8_t over_run_latched : 1; + uint8_t fifo_ovr_latched : 1; uint8_t not_used_01 : 1; uint8_t diff_fifo : 2; #endif /* DRV_BYTE_ORDER */ @@ -706,20 +685,6 @@ typedef struct #endif /* DRV_BYTE_ORDER */ } asm330lhh_ths_6d_t; -#define ASM330LHH_INT_DUR2 0x5AU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t shock : 2; - uint8_t quiet : 2; - uint8_t dur : 4; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t dur : 4; - uint8_t quiet : 2; - uint8_t shock : 2; -#endif /* DRV_BYTE_ORDER */ -} asm330lhh_int_dur2_t; - #define ASM330LHH_WAKE_UP_THS 0x5BU typedef struct { @@ -880,7 +845,6 @@ typedef union asm330lhh_int_cfg0_t int_cfg0; asm330lhh_int_cfg1_t int_cfg1; asm330lhh_ths_6d_t ths_6d; - asm330lhh_int_dur2_t int_dur2; asm330lhh_wake_up_ths_t wake_up_ths; asm330lhh_wake_up_dur_t wake_up_dur; asm330lhh_free_fall_t free_fall; @@ -897,6 +861,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t asm330lhh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -940,7 +917,7 @@ typedef enum ASM330LHH_XL_ODR_52Hz = 3, ASM330LHH_XL_ODR_104Hz = 4, ASM330LHH_XL_ODR_208Hz = 5, - ASM330LHH_XL_ODR_416Hz = 6, + ASM330LHH_XL_ODR_417Hz = 6, ASM330LHH_XL_ODR_833Hz = 7, ASM330LHH_XL_ODR_1667Hz = 8, ASM330LHH_XL_ODR_3333Hz = 9, @@ -973,7 +950,7 @@ typedef enum ASM330LHH_GY_ODR_52Hz = 3, ASM330LHH_GY_ODR_104Hz = 4, ASM330LHH_GY_ODR_208Hz = 5, - ASM330LHH_GY_ODR_416Hz = 6, + ASM330LHH_GY_ODR_417Hz = 6, ASM330LHH_GY_ODR_833Hz = 7, ASM330LHH_GY_ODR_1667Hz = 8, ASM330LHH_GY_ODR_3333Hz = 9, @@ -1003,7 +980,6 @@ typedef struct { asm330lhh_all_int_src_t all_int_src; asm330lhh_wake_up_src_t wake_up_src; - asm330lhh_tap_src_t tap_src; asm330lhh_d6d_src_t d6d_src; asm330lhh_status_reg_t status_reg; } asm330lhh_all_sources_t; @@ -1421,7 +1397,7 @@ typedef enum ASM330LHH_GY_BATCHED_AT_1667Hz = 8, ASM330LHH_GY_BATCHED_AT_3333Hz = 9, ASM330LHH_GY_BATCHED_AT_6667Hz = 10, - ASM330LHH_GY_BATCHED_6Hz5 = 11, + ASM330LHH_GY_BATCHED_AT_6Hz5 = 11, } asm330lhh_bdr_gy_t; int32_t asm330lhh_fifo_gy_batch_set(stmdev_ctx_t *ctx, asm330lhh_bdr_gy_t val); diff --git a/sensor/stmemsc/asm330lhhx_STdC/driver/asm330lhhx_reg.c b/sensor/stmemsc/asm330lhhx_STdC/driver/asm330lhhx_reg.c index e682ef5915d9c1a4d5ef3d8660e6741b0542be09..d368a06c51cf0547603395ed1c4cfc8781806904 100644 --- a/sensor/stmemsc/asm330lhhx_STdC/driver/asm330lhhx_reg.c +++ b/sensor/stmemsc/asm330lhhx_STdC/driver/asm330lhhx_reg.c @@ -46,8 +46,8 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t asm330lhhx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, - uint16_t len) +int32_t __weak asm330lhhx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, + uint16_t len) { int32_t ret; ret = ctx->read_reg(ctx->handle, reg, data, len); @@ -64,8 +64,8 @@ int32_t asm330lhhx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t asm330lhhx_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, - uint16_t len) +int32_t __weak asm330lhhx_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, + uint16_t len) { int32_t ret; ret = ctx->write_reg(ctx->handle, reg, data, len); @@ -509,8 +509,8 @@ int32_t asm330lhhx_xl_data_rate_get(stmdev_ctx_t *ctx, case ASM330LHHX_XL_ODR_6667Hz: *val = ASM330LHHX_XL_ODR_6667Hz; break; - case ASM330LHHX_XL_ODR_6Hz5: - *val = ASM330LHHX_XL_ODR_6Hz5; + case ASM330LHHX_XL_ODR_1Hz6: + *val = ASM330LHHX_XL_ODR_1Hz6; break; default: *val = ASM330LHHX_XL_ODR_OFF; @@ -1171,7 +1171,7 @@ int32_t asm330lhhx_status_reg_get(stmdev_ctx_t *ctx, * @brief Accelerometer new data available.[get] * * @param ctx Read / write interface definitions.(ptr) - * @param val Change the values of xlda in reg STATUS_REG + * @param val Get the values of xlda in reg STATUS_REG * @retval Interface status (MANDATORY: return 0 -> no Error). * */ @@ -1191,7 +1191,7 @@ int32_t asm330lhhx_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @brief Gyroscope new data available.[get] * * @param ctx Read / write interface definitions.(ptr) - * @param val Change the values of gda in reg STATUS_REG + * @param val Get the values of gda in reg STATUS_REG * @retval Interface status (MANDATORY: return 0 -> no Error). * */ @@ -1211,7 +1211,7 @@ int32_t asm330lhhx_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @brief Temperature new data available.[get] * * @param ctx Read / write interface definitions.(ptr) - * @param val Change the values of tda in reg STATUS_REG + * @param val Get the values of tda in reg STATUS_REG * @retval Interface status (MANDATORY: return 0 -> no Error). * */ @@ -4690,8 +4690,8 @@ int32_t asm330lhhx_fifo_xl_batch_get(stmdev_ctx_t *ctx, case ASM330LHHX_XL_BATCHED_AT_6667Hz: *val = ASM330LHHX_XL_BATCHED_AT_6667Hz; break; - case ASM330LHHX_XL_BATCHED_AT_6Hz5: - *val = ASM330LHHX_XL_BATCHED_AT_6Hz5; + case ASM330LHHX_XL_BATCHED_AT_1Hz6: + *val = ASM330LHHX_XL_BATCHED_AT_1Hz6; break; default: *val = ASM330LHHX_XL_NOT_BATCHED; @@ -4779,8 +4779,8 @@ int32_t asm330lhhx_fifo_gy_batch_get(stmdev_ctx_t *ctx, case ASM330LHHX_GY_BATCHED_AT_6667Hz: *val = ASM330LHHX_GY_BATCHED_AT_6667Hz; break; - case ASM330LHHX_GY_BATCHED_6Hz5: - *val = ASM330LHHX_GY_BATCHED_6Hz5; + case ASM330LHHX_GY_BATCHED_AT_6Hz5: + *val = ASM330LHHX_GY_BATCHED_AT_6Hz5; break; default: *val = ASM330LHHX_GY_NOT_BATCHED; @@ -6454,6 +6454,67 @@ int32_t asm330lhhx_mag_x_orient_get(stmdev_ctx_t *ctx, * */ +/** + * @brief FSM status register[get] + * + * @param ctx read / write interface definitions + * @param val register ASM330LHHX_FSM_STATUS_A_MAINPAGE, + * ASM330LHHX_FSM_STATUS_B_MAINPAGE + * + */ +int32_t asm330lhhx_fsm_status_get(stmdev_ctx_t *ctx, + asm330lhhx_fsm_status_t *val) +{ + asm330lhhx_fsm_status_a_mainpage_t status_a; + asm330lhhx_fsm_status_b_mainpage_t status_b; + int32_t ret; + + ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_STATUS_A_MAINPAGE, + (uint8_t *)&status_a, 1); + ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_STATUS_B_MAINPAGE, + (uint8_t *)&status_b, 1); + + val->fsm1 = status_a.is_fsm1; + val->fsm2 = status_a.is_fsm2; + val->fsm3 = status_a.is_fsm3; + val->fsm4 = status_a.is_fsm4; + val->fsm5 = status_a.is_fsm5; + val->fsm6 = status_a.is_fsm6; + val->fsm7 = status_a.is_fsm7; + val->fsm8 = status_a.is_fsm8; + val->fsm9 = status_b.is_fsm9; + val->fsm10 = status_b.is_fsm10; + val->fsm11 = status_b.is_fsm11; + val->fsm12 = status_b.is_fsm12; + val->fsm13 = status_b.is_fsm13; + val->fsm14 = status_b.is_fsm14; + val->fsm15 = status_b.is_fsm15; + val->fsm16 = status_b.is_fsm16; + return ret; +} + +/** + * @brief prgsens_out: [get] Output value of all FSMs. + * + * @param ctx_t *ctx: read / write interface definitions + * @param uint8_t * : buffer that stores data read + * + */ +int32_t asm330lhhx_fsm_out_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_OUTS1, buff, 16); + } + if (ret == 0) + { + ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + } + return ret; +} + /** * @brief Interrupt status bit for FSM long counter timeout interrupt * event.[get] @@ -6819,32 +6880,6 @@ int32_t asm330lhhx_long_clr_get(stmdev_ctx_t *ctx, return ret; } -/** - * @brief FSM output registers.[get] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Structure of registers from FSM_OUTS1 to FSM_OUTS16 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t asm330lhhx_fsm_out_get(stmdev_ctx_t *ctx, asm330lhhx_fsm_out_t *val) -{ - int32_t ret; - - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_OUTS1, - (uint8_t *)&val->fsm_outs1, 16); - } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } - return ret; -} - /** * @brief Finite State Machine ODR configuration.[set] * diff --git a/sensor/stmemsc/asm330lhhx_STdC/driver/asm330lhhx_reg.h b/sensor/stmemsc/asm330lhhx_STdC/driver/asm330lhhx_reg.h index b3dba991c1c745cac5f0ca9917e2e6b12be7f604..4473f84e4ccad5e87d5a7d4f73f46efe37c4a759 100644 --- a/sensor/stmemsc/asm330lhhx_STdC/driver/asm330lhhx_reg.h +++ b/sensor/stmemsc/asm330lhhx_STdC/driver/asm330lhhx_reg.h @@ -108,14 +108,17 @@ typedef struct * */ -typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -1798,9 +1801,6 @@ typedef struct #define ASM330LHHX_FSM_PROGRAMS 0x17CU #define ASM330LHHX_FSM_START_ADD_L 0x17EU #define ASM330LHHX_FSM_START_ADD_H 0x17FU -#define ASM330LHHX_PEDO_DEB_STEPS_CONF 0x184U -#define ASM330LHHX_PEDO_SC_DELTAT_L 0x1D0U -#define ASM330LHHX_PEDO_SC_DELTAT_H 0x1D1U #define ASM330LHHX_MLC_MAG_SENSITIVITY_L 0x1E8U #define ASM330LHHX_MLC_MAG_SENSITIVITY_H 0x1E9U @@ -2551,6 +2551,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t asm330lhhx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); int32_t asm330lhhx_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, @@ -2593,7 +2606,7 @@ typedef enum ASM330LHHX_XL_ODR_1667Hz = 8, ASM330LHHX_XL_ODR_3333Hz = 9, ASM330LHHX_XL_ODR_6667Hz = 10, - ASM330LHHX_XL_ODR_6Hz5 = 11, /* (low power only) */ + ASM330LHHX_XL_ODR_1Hz6 = 11, /* (low power only) */ } asm330lhhx_odr_xl_t; int32_t asm330lhhx_xl_data_rate_set(stmdev_ctx_t *ctx, asm330lhhx_odr_xl_t val); int32_t asm330lhhx_xl_data_rate_get(stmdev_ctx_t *ctx, @@ -3090,7 +3103,7 @@ typedef enum ASM330LHHX_XL_BATCHED_AT_1667Hz = 8, ASM330LHHX_XL_BATCHED_AT_3333Hz = 9, ASM330LHHX_XL_BATCHED_AT_6667Hz = 10, - ASM330LHHX_XL_BATCHED_AT_6Hz5 = 11, + ASM330LHHX_XL_BATCHED_AT_1Hz6 = 11, } asm330lhhx_bdr_xl_t; int32_t asm330lhhx_fifo_xl_batch_set(stmdev_ctx_t *ctx, asm330lhhx_bdr_xl_t val); @@ -3110,7 +3123,7 @@ typedef enum ASM330LHHX_GY_BATCHED_AT_1667Hz = 8, ASM330LHHX_GY_BATCHED_AT_3333Hz = 9, ASM330LHHX_GY_BATCHED_AT_6667Hz = 10, - ASM330LHHX_GY_BATCHED_6Hz5 = 11, + ASM330LHHX_GY_BATCHED_AT_6Hz5 = 11, } asm330lhhx_bdr_gy_t; int32_t asm330lhhx_fifo_gy_batch_set(stmdev_ctx_t *ctx, asm330lhhx_bdr_gy_t val); @@ -3305,6 +3318,29 @@ int32_t asm330lhhx_mag_x_orient_set(stmdev_ctx_t *ctx, int32_t asm330lhhx_mag_x_orient_get(stmdev_ctx_t *ctx, asm330lhhx_mag_x_axis_t *val); +typedef struct +{ + uint16_t fsm1 : 1; + uint16_t fsm2 : 1; + uint16_t fsm3 : 1; + uint16_t fsm4 : 1; + uint16_t fsm5 : 1; + uint16_t fsm6 : 1; + uint16_t fsm7 : 1; + uint16_t fsm8 : 1; + uint16_t fsm9 : 1; + uint16_t fsm10 : 1; + uint16_t fsm11 : 1; + uint16_t fsm12 : 1; + uint16_t fsm13 : 1; + uint16_t fsm14 : 1; + uint16_t fsm15 : 1; + uint16_t fsm16 : 1; +} asm330lhhx_fsm_status_t; +int32_t asm330lhhx_fsm_status_get(stmdev_ctx_t *ctx, + asm330lhhx_fsm_status_t *val); +int32_t asm330lhhx_fsm_out_get(stmdev_ctx_t *ctx, uint8_t *buff); + int32_t asm330lhhx_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); @@ -3338,27 +3374,6 @@ int32_t asm330lhhx_long_clr_set(stmdev_ctx_t *ctx, int32_t asm330lhhx_long_clr_get(stmdev_ctx_t *ctx, asm330lhhx_fsm_lc_clr_t *val); -typedef struct -{ - asm330lhhx_fsm_outs1_t fsm_outs1; - asm330lhhx_fsm_outs2_t fsm_outs2; - asm330lhhx_fsm_outs3_t fsm_outs3; - asm330lhhx_fsm_outs4_t fsm_outs4; - asm330lhhx_fsm_outs5_t fsm_outs5; - asm330lhhx_fsm_outs6_t fsm_outs6; - asm330lhhx_fsm_outs7_t fsm_outs7; - asm330lhhx_fsm_outs8_t fsm_outs8; - asm330lhhx_fsm_outs9_t fsm_outs9; - asm330lhhx_fsm_outs10_t fsm_outs10; - asm330lhhx_fsm_outs11_t fsm_outs11; - asm330lhhx_fsm_outs12_t fsm_outs12; - asm330lhhx_fsm_outs13_t fsm_outs13; - asm330lhhx_fsm_outs14_t fsm_outs14; - asm330lhhx_fsm_outs15_t fsm_outs15; - asm330lhhx_fsm_outs16_t fsm_outs16; -} asm330lhhx_fsm_out_t; -int32_t asm330lhhx_fsm_out_get(stmdev_ctx_t *ctx, asm330lhhx_fsm_out_t *val); - typedef enum { ASM330LHHX_ODR_FSM_12Hz5 = 0, diff --git a/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.c b/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.c index b8a6dfba7cc09973447dfa06b5536368df49aa94..1f9f4129c68576ffab4effb1640ab8b054b1c4cd 100644 --- a/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.c +++ b/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak h3lis100dl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t h3lis100dl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak h3lis100dl_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -92,7 +92,7 @@ int32_t h3lis100dl_write_reg(stmdev_ctx_t *ctx, uint8_t reg, float_t h3lis100dl_from_fs100g_to_mg(int8_t lsb) { - return ((float_t)lsb / 256.0f) * 780.0f; + return (float_t)lsb * 780.0f; } /** @@ -460,18 +460,13 @@ int32_t h3lis100dl_flag_data_ready_get(stmdev_ctx_t *ctx, * */ int32_t h3lis100dl_acceleration_raw_get(stmdev_ctx_t *ctx, - int16_t *val) + int8_t *val) { - uint8_t buff[6]; int32_t ret; - ret = h3lis100dl_read_reg(ctx, (H3LIS100DL_OUT_X - 1U), buff, 6); - val[0] = (int16_t)buff[1]; - val[0] = (val[0] * 256) + (int16_t)buff[0]; - val[1] = (int16_t)buff[3]; - val[1] = (val[1] * 256) + (int16_t)buff[2]; - val[2] = (int16_t)buff[5]; - val[2] = (val[2] * 256) + (int16_t)buff[4]; + ret = h3lis100dl_read_reg(ctx, H3LIS100DL_OUT_X, (uint8_t *)&val[0], 1); + ret = h3lis100dl_read_reg(ctx, H3LIS100DL_OUT_Y, (uint8_t *)&val[1], 1); + ret = h3lis100dl_read_reg(ctx, H3LIS100DL_OUT_Z, (uint8_t *)&val[2], 1); return ret; } diff --git a/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.h b/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.h index 6a6249d28933f1b15f77cfc6f261beac610bf982..211cdd8c504a7ec7b2865111208cd27d991bdfba 100644 --- a/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.h +++ b/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -469,6 +472,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t h3lis100dl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -521,7 +537,7 @@ int32_t h3lis100dl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); int32_t h3lis100dl_acceleration_raw_get(stmdev_ctx_t *ctx, - int16_t *val); + int8_t *val); int32_t h3lis100dl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); diff --git a/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.c b/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.c index f23b05225702f89ba2c8f59e9dbf896c37db4aec..46bfcbedfbf100675f208b6bc46a7b61f8e7c30b 100644 --- a/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.c +++ b/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak h3lis331dl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t h3lis331dl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak h3lis331dl_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -315,8 +315,8 @@ int32_t h3lis331dl_data_rate_get(stmdev_ctx_t *ctx, *val = H3LIS331DL_ODR_1Hz; break; - case H3LIS331DL_ODR_5Hz2: - *val = H3LIS331DL_ODR_5Hz2; + case H3LIS331DL_ODR_2Hz: + *val = H3LIS331DL_ODR_2Hz; break; case H3LIS331DL_ODR_5Hz: diff --git a/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.h b/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.h index d47761538cbed9599b5f529f6ab1f7efa7f2878b..7de8a3b71ce9942474a8f57389020d61d8c57aea 100644 --- a/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.h +++ b/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -477,6 +480,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t h3lis331dl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -502,7 +518,7 @@ typedef enum H3LIS331DL_ODR_OFF = 0x00, H3LIS331DL_ODR_Hz5 = 0x02, H3LIS331DL_ODR_1Hz = 0x03, - H3LIS331DL_ODR_5Hz2 = 0x04, + H3LIS331DL_ODR_2Hz = 0x04, H3LIS331DL_ODR_5Hz = 0x05, H3LIS331DL_ODR_10Hz = 0x06, H3LIS331DL_ODR_50Hz = 0x01, diff --git a/sensor/stmemsc/hts221_STdC/driver/hts221_reg.c b/sensor/stmemsc/hts221_STdC/driver/hts221_reg.c index 6981bf0f0d8799128b467fd8ea88f8cb671fa0d8..1455299d0463495d8e91ec6284d50e39e2481eec 100644 --- a/sensor/stmemsc/hts221_STdC/driver/hts221_reg.c +++ b/sensor/stmemsc/hts221_STdC/driver/hts221_reg.c @@ -45,8 +45,8 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, - uint16_t len) +int32_t __weak hts221_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, + uint16_t len) { int32_t ret; @@ -65,9 +65,9 @@ int32_t hts221_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak hts221_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -888,7 +888,8 @@ int32_t hts221_hum_rh_point_1_get(stmdev_ctx_t *ctx, float_t *val) int32_t hts221_temp_deg_point_0_get(stmdev_ctx_t *ctx, float_t *val) { hts221_t1_t0_msb_t reg; - uint8_t coeff_h, coeff_l; + uint8_t coeff_h; + uint8_t coeff_l; int32_t ret; ret = hts221_read_reg(ctx, HTS221_T0_DEGC_X8, &coeff_l, 1); @@ -914,7 +915,8 @@ int32_t hts221_temp_deg_point_0_get(stmdev_ctx_t *ctx, float_t *val) int32_t hts221_temp_deg_point_1_get(stmdev_ctx_t *ctx, float_t *val) { hts221_t1_t0_msb_t reg; - uint8_t coeff_h, coeff_l; + uint8_t coeff_h; + uint8_t coeff_l; int32_t ret; ret = hts221_read_reg(ctx, HTS221_T1_DEGC_X8, &coeff_l, 1); diff --git a/sensor/stmemsc/hts221_STdC/driver/hts221_reg.h b/sensor/stmemsc/hts221_STdC/driver/hts221_reg.h index ca5f7e14248049c10486f6bb205c5a5f28f3c433..f25b69def932c3f391ba55155a8ddd4e13d4ba9a 100644 --- a/sensor/stmemsc/hts221_STdC/driver/hts221_reg.h +++ b/sensor/stmemsc/hts221_STdC/driver/hts221_reg.h @@ -50,7 +50,7 @@ extern "C" { /** if _BYTE_ORDER is not defined, choose the endianness of your architecture * by uncommenting the define which fits your platform endianness */ -//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN +/* #define DRV_BYTE_ORDER DRV_BIG_ENDIAN */ #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN #else /* defined __BYTE_ORDER__ */ @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -315,7 +318,20 @@ typedef union * */ -int32_t hts221_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ +int32_t hts221_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, uint16_t len); int32_t hts221_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, diff --git a/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.c b/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.c index cbd41af1ecc891b08554ead45415050486a39673..c33a22852255a9049f53115969f019c1d91394ec 100644 --- a/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.c +++ b/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak i3g4250d_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t i3g4250d_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak i3g4250d_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.h b/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.h index e6feb8fb78ba0382b7aadaac40758e9876872606..2779c236d2c33cae0f0ad84fedc9487bde932921 100644 --- a/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.h +++ b/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.h @@ -109,12 +109,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -490,6 +493,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t i3g4250d_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.c b/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.c index 2177ca29bea7325bbea9cd5add39dc3652b9a9d9..3c6baa9f45f7948f8ed95874281d0e18ff7f2548 100644 --- a/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.c +++ b/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.c @@ -46,8 +46,8 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, - uint16_t len) +int32_t __weak iis2dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, + uint16_t len) { int32_t ret; @@ -66,9 +66,9 @@ int32_t iis2dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak iis2dh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.h b/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.h index 587466d9d4293447245a1f1c60b9af8431fde1f6..48ef20459518bf6d60c8c14263b5728e075c744b 100644 --- a/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.h +++ b/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -689,6 +692,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t iis2dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); int32_t iis2dh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, diff --git a/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.c b/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.c index 8cf67d85ccec64f352c84c3b3c747a2c9e3df042..b5f65db9014bdee1a0027070275a5413b61e27c0 100644 --- a/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.c +++ b/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak iis2dlpc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t iis2dlpc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak iis2dlpc_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.h b/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.h index b47d5feaf46dc5a9eb82c134a82909e878d50be2..19cfadfde891a43c7c9d9e7610f685831e132e46 100644 --- a/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.h +++ b/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -649,6 +652,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t iis2dlpc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.c b/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.c index f6ca0f0a6efd1be1ded164c0307bd50135c261cd..2e393174e61ad708abce98cdd9f4f2732e38a7e4 100644 --- a/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.c +++ b/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2iclx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak iis2iclx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t iis2iclx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2iclx_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak iis2iclx_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.h b/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.h index e3d64a0e9eabcc745536a7d9db356f0f1b45015e..9bbcbb6c8acde4283588ec63ca7f39ed90b7203f 100644 --- a/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.h +++ b/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -2455,6 +2458,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t iis2iclx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.c b/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.c index 180dab2d4794cb0426339ce1a7b4a5c1110b80f7..7110a6883d6d1e438e5d24f18ead3acecb2dfda8 100644 --- a/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.c +++ b/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.c @@ -45,9 +45,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak iis2mdc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -66,9 +66,9 @@ int32_t iis2mdc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak iis2mdc_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -115,7 +115,7 @@ float_t iis2mdc_from_lsb_to_celsius(int16_t lsb) /** * @brief These registers comprise a 3 group of 16-bit number and represent * hard-iron offset in order to compensate environmental effects. - * Data format is the same of output data raw: two’s complement with + * Data format is the same of output data raw: two's complement with * 1LSb = 1.5mG. * These values act on the magnetic output data value in order to * delete the environmental offset.[set] @@ -144,7 +144,7 @@ int32_t iis2mdc_mag_user_offset_set(stmdev_ctx_t *ctx, int16_t *val) /** * @brief These registers comprise a 3 group of 16-bit number and represent * hard-iron offset in order to compensate environmental effects. - * Data format is the same of output data raw: two’s complement with + * Data format is the same of output data raw: two's complement with * 1LSb = 1.5mG. * These values act on the magnetic output data value in order to * delete the environmental offset.[get] @@ -1153,7 +1153,7 @@ int32_t iis2mdc_int_gen_source_get(stmdev_ctx_t *ctx, /** * @brief User-defined threshold value for xl interrupt event on generator. * Data format is the same of output data raw: - * two’s complement with 1LSb = 1.5mG.[set] + * two's complement with 1LSb = 1.5mG.[set] * * @param ctx read / write interface definitions * @param buff buffer that contains data to write @@ -1175,7 +1175,7 @@ int32_t iis2mdc_int_gen_treshold_set(stmdev_ctx_t *ctx, int16_t val) /** * @brief User-defined threshold value for xl interrupt event on generator. * Data format is the same of output data raw: - * two’s complement with 1LSb = 1.5mG.[get] + * two's complement with 1LSb = 1.5mG.[get] * * @param ctx read / write interface definitions * @param buff buffer that stores data read diff --git a/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.h b/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.h index b68d8f4bf14d0ecf16fc09034b6d5a045bc5a663..095b5364f320de26b7fcb0e566ef4afd2826afea 100644 --- a/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.h +++ b/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.h @@ -50,7 +50,7 @@ extern "C" { /** if _BYTE_ORDER is not defined, choose the endianness of your architecture * by uncommenting the define which fits your platform endianness */ -//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN +/* #define DRV_BYTE_ORDER DRV_BIG_ENDIAN */ #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN #else /* defined __BYTE_ORDER__ */ @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -339,6 +342,18 @@ typedef union uint8_t byte; } iis2mdc_reg_t; +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ int32_t iis2mdc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.c b/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.c index c8e91a9e433e2c87d68470b1493a964fa5636350..d48655583fbc84c39a0faa89122c8228c44301bc 100644 --- a/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.c +++ b/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.c @@ -46,9 +46,9 @@ * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak iis328dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t iis328dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak iis328dq_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.h b/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.h index 0164acfd89242d5b39d851ba2773eacc5ac7a4b5..d11453d81de40914402131399a146f15fd8b81ae 100644 --- a/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.h +++ b/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -478,6 +481,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t iis328dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.c b/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.c index 356805d6a963afb9573e4967458c6198953ad065..1bfd69a891c4df2bde2bae80e780dde664e7c9b3 100644 --- a/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.c +++ b/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis3dhhc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak iis3dhhc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t iis3dhhc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis3dhhc_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak iis3dhhc_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.h b/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.h index db5fbb49ffe5933f35916ee8355169f9d165ebce..03f7939c69e87d26b8427964b22d6e4a8c4c44a6 100644 --- a/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.h +++ b/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -369,6 +372,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t iis3dhhc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.c b/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.c index 80c707f83f262017c61258afcb22d2934bc7e94b..1b3c7b09bbab0525ececafa62cc6ba8922e740a9 100644 --- a/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.c +++ b/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.c @@ -18,6 +18,7 @@ */ #include "iis3dwb_reg.h" +#include /** * @defgroup IIS3DWB @@ -46,15 +47,11 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis3dwb_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak iis3dwb_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { - int32_t ret; - - ret = ctx->read_reg(ctx->handle, reg, data, len); - - return ret; + return ctx->read_reg(ctx->handle, reg, data, len); } /** @@ -67,15 +64,31 @@ int32_t iis3dwb_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis3dwb_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak iis3dwb_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { - int32_t ret; + return ctx->write_reg(ctx->handle, reg, data, len); +} - ret = ctx->write_reg(ctx->handle, reg, data, len); +/** + * @} + * + */ - return ret; +/** + * @defgroup Private functions + * @brief Section collect all the utility functions needed by APIs. + * @{ + * + */ + +static void bytecpy(uint8_t *target, const uint8_t *source) +{ + if ((target != NULL) && (source != NULL)) + { + *target = *source; + } } /** @@ -145,9 +158,8 @@ int32_t iis3dwb_xl_full_scale_set(stmdev_ctx_t *ctx, iis3dwb_fs_xl_t val) { iis3dwb_ctrl1_xl_t ctrl1_xl; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); if (ret == 0) { @@ -171,9 +183,8 @@ int32_t iis3dwb_xl_full_scale_get(stmdev_ctx_t *ctx, iis3dwb_fs_xl_t *val) { iis3dwb_ctrl1_xl_t ctrl1_xl; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); switch (ctrl1_xl.fs_xl) { @@ -213,9 +224,8 @@ int32_t iis3dwb_xl_data_rate_set(stmdev_ctx_t *ctx, iis3dwb_odr_xl_t val) { iis3dwb_ctrl1_xl_t ctrl1_xl; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); if (ret == 0) { @@ -239,9 +249,8 @@ int32_t iis3dwb_xl_data_rate_get(stmdev_ctx_t *ctx, iis3dwb_odr_xl_t *val) { iis3dwb_ctrl1_xl_t ctrl1_xl; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); switch (ctrl1_xl.xl_en) { @@ -272,9 +281,8 @@ int32_t iis3dwb_xl_data_rate_get(stmdev_ctx_t *ctx, int32_t iis3dwb_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) { iis3dwb_ctrl3_c_t ctrl3_c; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); if (ret == 0) { @@ -296,9 +304,8 @@ int32_t iis3dwb_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) int32_t iis3dwb_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_ctrl3_c_t ctrl3_c; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); *val = ctrl3_c.bdu; return ret; @@ -317,9 +324,8 @@ int32_t iis3dwb_xl_offset_weight_set(stmdev_ctx_t *ctx, iis3dwb_usr_off_w_t val) { iis3dwb_ctrl6_c_t ctrl6_c; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL6_C, (uint8_t *)&ctrl6_c, 1); if (ret == 0) { @@ -343,9 +349,8 @@ int32_t iis3dwb_xl_offset_weight_get(stmdev_ctx_t *ctx, iis3dwb_usr_off_w_t *val) { iis3dwb_ctrl6_c_t ctrl6_c; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL6_C, (uint8_t *)&ctrl6_c, 1); switch (ctrl6_c.usr_off_w) { @@ -379,9 +384,8 @@ int32_t iis3dwb_xl_axis_selection_set(stmdev_ctx_t *ctx, { iis3dwb_ctrl4_c_t ctrl4_c; iis3dwb_ctrl6_c_t ctrl6_c; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); if (ret == 0) { @@ -417,14 +421,14 @@ int32_t iis3dwb_xl_axis_selection_get(stmdev_ctx_t *ctx, { iis3dwb_ctrl4_c_t ctrl4_c; iis3dwb_ctrl6_c_t ctrl6_c; - int32_t ret; + + *val = IIS3DWB_ENABLE_ALL; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); - - if (ret == 0) - { - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL6_C, (uint8_t *)&ctrl6_c, 1); - } + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) { return ret; } + + ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) { return ret; } switch ((ctrl4_c._1ax_to_3regout << 4) + ctrl6_c.xl_axis_sel) { @@ -476,9 +480,7 @@ int32_t iis3dwb_xl_axis_selection_get(stmdev_ctx_t *ctx, int32_t iis3dwb_all_sources_get(stmdev_ctx_t *ctx, iis3dwb_all_sources_t *val) { - int32_t ret; - - ret = iis3dwb_read_reg(ctx, IIS3DWB_ALL_INT_SRC, + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_ALL_INT_SRC, (uint8_t *)&val->all_int_src, 1); if (ret == 0) @@ -507,9 +509,7 @@ int32_t iis3dwb_all_sources_get(stmdev_ctx_t *ctx, int32_t iis3dwb_status_reg_get(stmdev_ctx_t *ctx, iis3dwb_status_reg_t *val) { - int32_t ret; - - ret = iis3dwb_read_reg(ctx, IIS3DWB_STATUS_REG, (uint8_t *) val, 1); + const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_STATUS_REG, (uint8_t *) val, 1); return ret; } @@ -526,9 +526,8 @@ int32_t iis3dwb_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_status_reg_t status_reg; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_STATUS_REG, + const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_STATUS_REG, (uint8_t *)&status_reg, 1); *val = status_reg.xlda; @@ -547,9 +546,8 @@ int32_t iis3dwb_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_status_reg_t status_reg; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_STATUS_REG, + const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_STATUS_REG, (uint8_t *)&status_reg, 1); *val = status_reg.tda; @@ -568,9 +566,7 @@ int32_t iis3dwb_temp_flag_data_ready_get(stmdev_ctx_t *ctx, */ int32_t iis3dwb_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) { - int32_t ret; - - ret = iis3dwb_write_reg(ctx, IIS3DWB_X_OFS_USR, buff, 1); + const int32_t ret = iis3dwb_write_reg(ctx, IIS3DWB_X_OFS_USR, buff, 1); return ret; } @@ -587,9 +583,7 @@ int32_t iis3dwb_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) */ int32_t iis3dwb_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) { - int32_t ret; - - ret = iis3dwb_read_reg(ctx, IIS3DWB_X_OFS_USR, buff, 1); + const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_X_OFS_USR, buff, 1); return ret; } @@ -606,9 +600,7 @@ int32_t iis3dwb_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) */ int32_t iis3dwb_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) { - int32_t ret; - - ret = iis3dwb_write_reg(ctx, IIS3DWB_Y_OFS_USR, buff, 1); + const int32_t ret = iis3dwb_write_reg(ctx, IIS3DWB_Y_OFS_USR, buff, 1); return ret; } @@ -625,9 +617,7 @@ int32_t iis3dwb_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) */ int32_t iis3dwb_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) { - int32_t ret; - - ret = iis3dwb_read_reg(ctx, IIS3DWB_Y_OFS_USR, buff, 1); + const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_Y_OFS_USR, buff, 1); return ret; } @@ -644,9 +634,7 @@ int32_t iis3dwb_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) */ int32_t iis3dwb_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff) { - int32_t ret; - - ret = iis3dwb_write_reg(ctx, IIS3DWB_Z_OFS_USR, buff, 1); + const int32_t ret = iis3dwb_write_reg(ctx, IIS3DWB_Z_OFS_USR, buff, 1); return ret; } @@ -663,9 +651,7 @@ int32_t iis3dwb_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff) */ int32_t iis3dwb_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff) { - int32_t ret; - - ret = iis3dwb_read_reg(ctx, IIS3DWB_Z_OFS_USR, buff, 1); + const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_Z_OFS_USR, buff, 1); return ret; } @@ -707,9 +693,8 @@ int32_t iis3dwb_timestamp_rst(stmdev_ctx_t *ctx) int32_t iis3dwb_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) { iis3dwb_ctrl10_c_t ctrl10_c; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL10_C, (uint8_t *)&ctrl10_c, 1); if (ret == 0) { @@ -732,9 +717,8 @@ int32_t iis3dwb_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) int32_t iis3dwb_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_ctrl10_c_t ctrl10_c; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL10_C, (uint8_t *)&ctrl10_c, 1); *val = ctrl10_c.timestamp_en; return ret; @@ -746,16 +730,15 @@ int32_t iis3dwb_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) * is 25 μs.[get] * * @param ctx Read / write interface definitions.(ptr) - * @param buff Buffer that stores data read + * @param val Buffer that stores data read * @retval Interface status (MANDATORY: return 0 -> no Error). * */ int32_t iis3dwb_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) { uint8_t buff[4]; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_TIMESTAMP0, buff, 4); + const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_TIMESTAMP0, buff, 4); *val = buff[3]; *val = (*val * 256U) + buff[2]; *val = (*val * 256U) + buff[1]; @@ -788,9 +771,8 @@ int32_t iis3dwb_rounding_mode_set(stmdev_ctx_t *ctx, iis3dwb_rounding_t val) { iis3dwb_ctrl5_c_t ctrl5_c; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL5_C, (uint8_t *)&ctrl5_c, 1); if (ret == 0) { @@ -813,9 +795,8 @@ int32_t iis3dwb_rounding_mode_get(stmdev_ctx_t *ctx, iis3dwb_rounding_t *val) { iis3dwb_ctrl5_c_t ctrl5_c; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL5_C, (uint8_t *)&ctrl5_c, 1); switch (ctrl5_c.rounding) { @@ -841,16 +822,15 @@ int32_t iis3dwb_rounding_mode_get(stmdev_ctx_t *ctx, * complement.[get] * * @param ctx Read / write interface definitions.(ptr) - * @param buff Buffer that stores data read + * @param val Buffer that stores data read * @retval Interface status (MANDATORY: return 0 -> no Error). * */ int32_t iis3dwb_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_OUT_TEMP_L, buff, 2); + const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_OUT_TEMP_L, buff, 2); *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -862,16 +842,15 @@ int32_t iis3dwb_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * 16-bit word in two’s complement.[get] * * @param ctx Read / write interface definitions.(ptr) - * @param buff Buffer that stores data read + * @param val Buffer that stores data read * @retval Interface status (MANDATORY: return 0 -> no Error). * */ int32_t iis3dwb_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_OUTX_L_A, buff, 6); + const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_OUTX_L_A, buff, 6); val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -886,15 +865,72 @@ int32_t iis3dwb_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @brief FIFO data output.[get] * * @param ctx Read / write interface definitions.(ptr) - * @param buff Buffer that stores data read + * @param val Buffer that stores data read * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t iis3dwb_fifo_out_raw_get(stmdev_ctx_t *ctx, iis3dwb_fifo_out_raw_t *val) { - int32_t ret; + const int32_t ret = iis3dwb_fifo_out_multi_raw_get(ctx, val, 1); - ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_DATA_OUT_X_L, buff, 6); + return ret; +} + +/** + * @brief FIFO data multi output.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param fdata Buffer that stores data read + * @param num Number of FIFO entries to be read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t iis3dwb_fifo_out_multi_raw_get(stmdev_ctx_t *ctx, + iis3dwb_fifo_out_raw_t *fdata, + uint16_t num) +{ + /* read out all FIFO entries in a single read */ + const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_DATA_OUT_TAG, + (uint8_t *)fdata, + sizeof(iis3dwb_fifo_out_raw_t) * num); + + return ret; +} + +/** + * @brief Identifies the sensor in FIFO_DATA_OUT.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of tag_sensor in reg FIFO_DATA_OUT_TAG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t iis3dwb_fifo_sensor_tag_get(stmdev_ctx_t *ctx, + iis3dwb_fifo_tag_t *val) +{ + iis3dwb_fifo_data_out_tag_t fifo_data_out_tag; + + const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_DATA_OUT_TAG, + (uint8_t *)&fifo_data_out_tag, 1); + + switch (fifo_data_out_tag.tag_sensor) + { + case IIS3DWB_XL_TAG: + *val = IIS3DWB_XL_TAG; + break; + + case IIS3DWB_TEMPERATURE_TAG: + *val = IIS3DWB_TEMPERATURE_TAG; + break; + + case IIS3DWB_TIMESTAMP_TAG: + *val = IIS3DWB_TIMESTAMP_TAG; + break; + + default: + *val = IIS3DWB_XL_TAG; + break; + } return ret; } @@ -924,9 +960,8 @@ int32_t iis3dwb_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) int32_t iis3dwb_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) { iis3dwb_internal_freq_fine_t internal_freq_fine; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_INTERNAL_FREQ_FINE, + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_INTERNAL_FREQ_FINE, (uint8_t *)&internal_freq_fine, 1); if (ret == 0) @@ -952,9 +987,8 @@ int32_t iis3dwb_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) int32_t iis3dwb_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_internal_freq_fine_t internal_freq_fine; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_INTERNAL_FREQ_FINE, + const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_INTERNAL_FREQ_FINE, (uint8_t *)&internal_freq_fine, 1); *val = internal_freq_fine.freq_fine; @@ -974,9 +1008,8 @@ int32_t iis3dwb_data_ready_mode_set(stmdev_ctx_t *ctx, iis3dwb_dataready_pulsed_t val) { iis3dwb_counter_bdr_reg1_t counter_bdr_reg1; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_COUNTER_BDR_REG1, + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); if (ret == 0) @@ -1002,9 +1035,8 @@ int32_t iis3dwb_data_ready_mode_get(stmdev_ctx_t *ctx, iis3dwb_dataready_pulsed_t *val) { iis3dwb_counter_bdr_reg1_t counter_bdr_reg1; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_COUNTER_BDR_REG1, + const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); switch (counter_bdr_reg1.dataready_pulsed) @@ -1035,9 +1067,7 @@ int32_t iis3dwb_data_ready_mode_get(stmdev_ctx_t *ctx, */ int32_t iis3dwb_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) { - int32_t ret; - - ret = iis3dwb_read_reg(ctx, IIS3DWB_WHO_AM_I, buff, 1); + const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_WHO_AM_I, buff, 1); return ret; } @@ -1053,9 +1083,8 @@ int32_t iis3dwb_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) int32_t iis3dwb_reset_set(stmdev_ctx_t *ctx, uint8_t val) { iis3dwb_ctrl3_c_t ctrl3_c; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); if (ret == 0) { @@ -1077,9 +1106,8 @@ int32_t iis3dwb_reset_set(stmdev_ctx_t *ctx, uint8_t val) int32_t iis3dwb_reset_get(stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_ctrl3_c_t ctrl3_c; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); *val = ctrl3_c.sw_reset; return ret; @@ -1097,9 +1125,8 @@ int32_t iis3dwb_reset_get(stmdev_ctx_t *ctx, uint8_t *val) int32_t iis3dwb_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) { iis3dwb_ctrl3_c_t ctrl3_c; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); if (ret == 0) { @@ -1122,9 +1149,8 @@ int32_t iis3dwb_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) int32_t iis3dwb_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_ctrl3_c_t ctrl3_c; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); *val = ctrl3_c.if_inc; return ret; @@ -1141,9 +1167,8 @@ int32_t iis3dwb_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) int32_t iis3dwb_boot_set(stmdev_ctx_t *ctx, uint8_t val) { iis3dwb_ctrl3_c_t ctrl3_c; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); if (ret == 0) { @@ -1165,9 +1190,8 @@ int32_t iis3dwb_boot_set(stmdev_ctx_t *ctx, uint8_t val) int32_t iis3dwb_boot_get(stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_ctrl3_c_t ctrl3_c; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); *val = ctrl3_c.boot; return ret; @@ -1187,9 +1211,8 @@ int32_t iis3dwb_xl_self_test_set(stmdev_ctx_t *ctx, iis3dwb_st_xl_t val) { iis3dwb_ctrl5_c_t ctrl5_c; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL5_C, (uint8_t *)&ctrl5_c, 1); if (ret == 0) { @@ -1212,9 +1235,8 @@ int32_t iis3dwb_xl_self_test_get(stmdev_ctx_t *ctx, iis3dwb_st_xl_t *val) { iis3dwb_ctrl5_c_t ctrl5_c; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL5_C, (uint8_t *)&ctrl5_c, 1); switch (ctrl5_c.st_xl) { @@ -1266,9 +1288,8 @@ int32_t iis3dwb_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val) { iis3dwb_ctrl4_c_t ctrl4_c; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); if (ret == 0) { @@ -1292,9 +1313,7 @@ int32_t iis3dwb_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_ctrl4_c_t ctrl4_c; - int32_t ret; - - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); *val = ctrl4_c.drdy_mask; return ret; @@ -1313,9 +1332,8 @@ int32_t iis3dwb_xl_filt_path_on_out_set(stmdev_ctx_t *ctx, { iis3dwb_ctrl1_xl_t ctrl1_xl; iis3dwb_ctrl8_xl_t ctrl8_xl; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); if (ret == 0) { @@ -1352,14 +1370,14 @@ int32_t iis3dwb_xl_filt_path_on_out_get(stmdev_ctx_t *ctx, { iis3dwb_ctrl1_xl_t ctrl1_xl; iis3dwb_ctrl8_xl_t ctrl8_xl; - int32_t ret; - - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); - if (ret == 0) - { - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); - } + *val = IIS3DWB_HP_REF_MODE; + + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) { return ret; } + + ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) { return ret; } switch ((ctrl1_xl.lpf2_xl_en << 7) + (ctrl8_xl.hp_ref_mode_xl << 5) + (ctrl8_xl.fds << 4) + ctrl8_xl.hpcf_xl) @@ -1453,9 +1471,8 @@ int32_t iis3dwb_xl_filt_path_on_out_get(stmdev_ctx_t *ctx, int32_t iis3dwb_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) { iis3dwb_ctrl8_xl_t ctrl8_xl; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); if (ret == 0) { @@ -1480,9 +1497,8 @@ int32_t iis3dwb_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) int32_t iis3dwb_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_ctrl8_xl_t ctrl8_xl; - int32_t ret; - - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + + const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); *val = ctrl8_xl.fastsettl_mode_xl; return ret; @@ -1501,9 +1517,8 @@ int32_t iis3dwb_xl_hp_path_internal_set(stmdev_ctx_t *ctx, iis3dwb_slope_fds_t val) { iis3dwb_slope_en_t int_cfg0; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&int_cfg0, 1); + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&int_cfg0, 1); if (ret == 0) { @@ -1528,9 +1543,8 @@ int32_t iis3dwb_xl_hp_path_internal_get(stmdev_ctx_t *ctx, iis3dwb_slope_fds_t *val) { iis3dwb_slope_en_t int_cfg0; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&int_cfg0, 1); + const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&int_cfg0, 1); switch (int_cfg0.slope_fds) { @@ -1575,9 +1589,8 @@ int32_t iis3dwb_sdo_sa0_mode_set(stmdev_ctx_t *ctx, iis3dwb_sdo_pu_en_t val) { iis3dwb_pin_ctrl_t pin_ctrl; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); if (ret == 0) { @@ -1600,9 +1613,8 @@ int32_t iis3dwb_sdo_sa0_mode_get(stmdev_ctx_t *ctx, iis3dwb_sdo_pu_en_t *val) { iis3dwb_pin_ctrl_t pin_ctrl; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); switch (pin_ctrl.sdo_pu_en) { @@ -1633,9 +1645,8 @@ int32_t iis3dwb_sdo_sa0_mode_get(stmdev_ctx_t *ctx, int32_t iis3dwb_spi_mode_set(stmdev_ctx_t *ctx, iis3dwb_sim_t val) { iis3dwb_ctrl3_c_t ctrl3_c; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); if (ret == 0) { @@ -1657,9 +1668,8 @@ int32_t iis3dwb_spi_mode_set(stmdev_ctx_t *ctx, iis3dwb_sim_t val) int32_t iis3dwb_spi_mode_get(stmdev_ctx_t *ctx, iis3dwb_sim_t *val) { iis3dwb_ctrl3_c_t ctrl3_c; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); switch (ctrl3_c.sim) { @@ -1691,9 +1701,8 @@ int32_t iis3dwb_i2c_interface_set(stmdev_ctx_t *ctx, iis3dwb_i2c_disable_t val) { iis3dwb_ctrl4_c_t ctrl4_c; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); if (ret == 0) { @@ -1716,9 +1725,8 @@ int32_t iis3dwb_i2c_interface_get(stmdev_ctx_t *ctx, iis3dwb_i2c_disable_t *val) { iis3dwb_ctrl4_c_t ctrl4_c; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); switch (ctrl4_c.i2c_disable) { @@ -1765,19 +1773,15 @@ int32_t iis3dwb_pin_int1_route_set(stmdev_ctx_t *ctx, iis3dwb_int1_ctrl_t int1_ctrl; iis3dwb_slope_en_t slope_en; iis3dwb_md1_cfg_t md1_cfg; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + if (ret != 0) { return ret; } + + ret = iis3dwb_read_reg(ctx, IIS3DWB_MD1_CFG, (uint8_t *)&md1_cfg, 1); + if (ret != 0) { return ret; } - if (ret == 0) - { - ret = iis3dwb_read_reg(ctx, IIS3DWB_MD1_CFG, (uint8_t *)&md1_cfg, 1); - } - - if (ret == 0) - { - ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&slope_en, 1); - } + ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&slope_en, 1); + if (ret != 0) { return ret; } int1_ctrl.int1_drdy_xl = val->drdy_xl; int1_ctrl.int1_boot = val->boot; @@ -1789,20 +1793,13 @@ int32_t iis3dwb_pin_int1_route_set(stmdev_ctx_t *ctx, md1_cfg.int1_sleep_change = val->sleep_change | val->sleep_status; slope_en.sleep_status_on_int = val->sleep_status; - if (ret == 0) - { - ret = iis3dwb_write_reg(ctx, IIS3DWB_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); - } + ret = iis3dwb_write_reg(ctx, IIS3DWB_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + if (ret != 0) { return ret; } - if (ret == 0) - { - ret = iis3dwb_write_reg(ctx, IIS3DWB_MD1_CFG, (uint8_t *)&md1_cfg, 1); - } + ret = iis3dwb_write_reg(ctx, IIS3DWB_MD1_CFG, (uint8_t *)&md1_cfg, 1); + if (ret != 0) { return ret; } - if (ret == 0) - { - ret = iis3dwb_write_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&slope_en, 1); - } + ret = iis3dwb_write_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&slope_en, 1); return ret; } @@ -1821,19 +1818,17 @@ int32_t iis3dwb_pin_int1_route_get(stmdev_ctx_t *ctx, iis3dwb_int1_ctrl_t int1_ctrl; iis3dwb_slope_en_t slope_en; iis3dwb_md1_cfg_t md1_cfg; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + memset(val, 0, sizeof(iis3dwb_pin_int1_route_t)); + + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + if (ret != 0) { return ret; } + + ret = iis3dwb_read_reg(ctx, IIS3DWB_MD1_CFG, (uint8_t *)&md1_cfg, 1); + if (ret != 0) { return ret; } - if (ret == 0) - { - ret = iis3dwb_read_reg(ctx, IIS3DWB_MD1_CFG, (uint8_t *)&md1_cfg, 1); - } - - if (ret == 0) - { - ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&slope_en, 1); - } + ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&slope_en, 1); + if (ret != 0) { return ret; } val->drdy_xl = int1_ctrl.int1_drdy_xl; val->boot = int1_ctrl.int1_boot; @@ -1871,19 +1866,15 @@ int32_t iis3dwb_pin_int2_route_set(stmdev_ctx_t *ctx, iis3dwb_int2_ctrl_t int2_ctrl; iis3dwb_slope_en_t slope_en; iis3dwb_md2_cfg_t md2_cfg; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); - - if (ret == 0) - { - ret = iis3dwb_read_reg(ctx, IIS3DWB_MD2_CFG, (uint8_t *)&md2_cfg, 1); - } + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + if (ret != 0) { return ret; } + + ret = iis3dwb_read_reg(ctx, IIS3DWB_MD2_CFG, (uint8_t *)&md2_cfg, 1); + if (ret != 0) { return ret; } - if (ret == 0) - { - ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&slope_en, 1); - } + ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&slope_en, 1); + if (ret != 0) { return ret; } int2_ctrl.int2_drdy_xl = val->drdy_xl; int2_ctrl.int2_drdy_temp = val->drdy_temp; @@ -1896,20 +1887,13 @@ int32_t iis3dwb_pin_int2_route_set(stmdev_ctx_t *ctx, md2_cfg.int2_sleep_change = val->sleep_change | val->sleep_status; slope_en.sleep_status_on_int = val->sleep_status; - if (ret == 0) - { - ret = iis3dwb_write_reg(ctx, IIS3DWB_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); - } + ret = iis3dwb_write_reg(ctx, IIS3DWB_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + if (ret != 0) { return ret; } - if (ret == 0) - { - ret = iis3dwb_write_reg(ctx, IIS3DWB_MD2_CFG, (uint8_t *)&md2_cfg, 1); - } + ret = iis3dwb_write_reg(ctx, IIS3DWB_MD2_CFG, (uint8_t *)&md2_cfg, 1); + if (ret != 0) { return ret; } - if (ret == 0) - { - ret = iis3dwb_write_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&slope_en, 1); - } + ret = iis3dwb_write_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&slope_en, 1); return ret; } @@ -1928,19 +1912,17 @@ int32_t iis3dwb_pin_int2_route_get(stmdev_ctx_t *ctx, iis3dwb_int2_ctrl_t int2_ctrl; iis3dwb_slope_en_t slope_en; iis3dwb_md2_cfg_t md2_cfg; - int32_t ret; + + memset(val, 0, sizeof(iis3dwb_pin_int2_route_t)); - ret = iis3dwb_read_reg(ctx, IIS3DWB_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + if (ret != 0) { return ret; } + + ret = iis3dwb_read_reg(ctx, IIS3DWB_MD2_CFG, (uint8_t *)&md2_cfg, 1); + if (ret != 0) { return ret; } - if (ret == 0) - { - ret = iis3dwb_read_reg(ctx, IIS3DWB_MD2_CFG, (uint8_t *)&md2_cfg, 1); - } - - if (ret == 0) - { - ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&slope_en, 1); - } + ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&slope_en, 1); + if (ret != 0) { return ret; } val->drdy_xl = int2_ctrl.int2_drdy_xl; val->drdy_temp = int2_ctrl.int2_drdy_temp; @@ -1976,9 +1958,8 @@ int32_t iis3dwb_pin_int2_route_get(stmdev_ctx_t *ctx, int32_t iis3dwb_pin_mode_set(stmdev_ctx_t *ctx, iis3dwb_pp_od_t val) { iis3dwb_ctrl3_c_t ctrl3_c; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); if (ret == 0) { @@ -2000,9 +1981,8 @@ int32_t iis3dwb_pin_mode_set(stmdev_ctx_t *ctx, iis3dwb_pp_od_t val) int32_t iis3dwb_pin_mode_get(stmdev_ctx_t *ctx, iis3dwb_pp_od_t *val) { iis3dwb_ctrl3_c_t ctrl3_c; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); switch (ctrl3_c.pp_od) { @@ -2034,9 +2014,8 @@ int32_t iis3dwb_pin_polarity_set(stmdev_ctx_t *ctx, iis3dwb_h_lactive_t val) { iis3dwb_ctrl3_c_t ctrl3_c; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); if (ret == 0) { @@ -2059,9 +2038,8 @@ int32_t iis3dwb_pin_polarity_get(stmdev_ctx_t *ctx, iis3dwb_h_lactive_t *val) { iis3dwb_ctrl3_c_t ctrl3_c; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); switch (ctrl3_c.h_lactive) { @@ -2092,9 +2070,8 @@ int32_t iis3dwb_pin_polarity_get(stmdev_ctx_t *ctx, int32_t iis3dwb_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) { iis3dwb_ctrl4_c_t ctrl4_c; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); if (ret == 0) { @@ -2116,9 +2093,8 @@ int32_t iis3dwb_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) int32_t iis3dwb_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_ctrl4_c_t ctrl4_c; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); *val = ctrl4_c.int2_on_int1; return ret; @@ -2136,9 +2112,8 @@ int32_t iis3dwb_int_notification_set(stmdev_ctx_t *ctx, iis3dwb_lir_t val) { iis3dwb_slope_en_t slope_en; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&slope_en, 1); + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&slope_en, 1); if (ret == 0) { @@ -2161,9 +2136,8 @@ int32_t iis3dwb_int_notification_get(stmdev_ctx_t *ctx, iis3dwb_lir_t *val) { iis3dwb_slope_en_t slope_en; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&slope_en, 1); + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&slope_en, 1); switch (slope_en.lir) { @@ -2210,9 +2184,8 @@ int32_t iis3dwb_wkup_ths_weight_set(stmdev_ctx_t *ctx, iis3dwb_wake_ths_w_t val) { iis3dwb_wake_up_dur_t wake_up_dur; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_DUR, + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); if (ret == 0) @@ -2239,9 +2212,8 @@ int32_t iis3dwb_wkup_ths_weight_get(stmdev_ctx_t *ctx, iis3dwb_wake_ths_w_t *val) { iis3dwb_wake_up_dur_t wake_up_dur; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_DUR, + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); switch (wake_up_dur.wake_ths_w) @@ -2276,9 +2248,8 @@ int32_t iis3dwb_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) { iis3dwb_interrupts_en_t interrupts_en; iis3dwb_wake_up_ths_t wake_up_ths; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_THS, + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); if (ret == 0) @@ -2316,9 +2287,8 @@ int32_t iis3dwb_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) int32_t iis3dwb_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_wake_up_ths_t wake_up_ths; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_THS, + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); *val = wake_up_ths.wk_ths; @@ -2337,9 +2307,8 @@ int32_t iis3dwb_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, uint8_t val) { iis3dwb_wake_up_ths_t wake_up_ths; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_THS, + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); if (ret == 0) @@ -2364,9 +2333,8 @@ int32_t iis3dwb_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_wake_up_ths_t wake_up_ths; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_THS, + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); *val = wake_up_ths.usr_off_on_wu; @@ -2384,9 +2352,8 @@ int32_t iis3dwb_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, int32_t iis3dwb_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) { iis3dwb_wake_up_dur_t wake_up_dur; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_DUR, + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); if (ret == 0) @@ -2410,9 +2377,8 @@ int32_t iis3dwb_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) int32_t iis3dwb_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_wake_up_dur_t wake_up_dur; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_DUR, + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); *val = wake_up_dur.wake_dur; @@ -2443,9 +2409,8 @@ int32_t iis3dwb_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) int32_t iis3dwb_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) { iis3dwb_wake_up_dur_t wake_up_dur; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_DUR, + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); if (ret == 0) @@ -2469,9 +2434,8 @@ int32_t iis3dwb_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) int32_t iis3dwb_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_wake_up_dur_t wake_up_dur; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_DUR, + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); *val = wake_up_dur.sleep_dur; @@ -2503,9 +2467,8 @@ int32_t iis3dwb_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) { iis3dwb_fifo_ctrl1_t fifo_ctrl1; iis3dwb_fifo_ctrl2_t fifo_ctrl2; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL2, + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); if (ret == 0) @@ -2537,16 +2500,15 @@ int32_t iis3dwb_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) { iis3dwb_fifo_ctrl1_t fifo_ctrl1; iis3dwb_fifo_ctrl2_t fifo_ctrl2; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL2, + *val = 0; + + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); - - if (ret == 0) - { - ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL1, + if (ret != 0) { return ret; } + + ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); - } *val = fifo_ctrl2.wtm; *val = *val << 8; @@ -2567,9 +2529,8 @@ int32_t iis3dwb_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) int32_t iis3dwb_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) { iis3dwb_fifo_ctrl2_t fifo_ctrl2; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL2, + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); if (ret == 0) @@ -2594,9 +2555,8 @@ int32_t iis3dwb_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) int32_t iis3dwb_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_fifo_ctrl2_t fifo_ctrl2; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL2, + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); *val = fifo_ctrl2.stop_on_wtm; @@ -2616,9 +2576,8 @@ int32_t iis3dwb_fifo_xl_batch_set(stmdev_ctx_t *ctx, iis3dwb_bdr_xl_t val) { iis3dwb_fifo_ctrl3_t fifo_ctrl3; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL3, + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); if (ret == 0) @@ -2644,9 +2603,8 @@ int32_t iis3dwb_fifo_xl_batch_get(stmdev_ctx_t *ctx, iis3dwb_bdr_xl_t *val) { iis3dwb_fifo_ctrl3_t fifo_ctrl3; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL3, + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); switch (fifo_ctrl3.bdr_xl) @@ -2679,9 +2637,8 @@ int32_t iis3dwb_fifo_mode_set(stmdev_ctx_t *ctx, iis3dwb_fifo_mode_t val) { iis3dwb_fifo_ctrl4_t fifo_ctrl4; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL4, + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); if (ret == 0) @@ -2706,9 +2663,8 @@ int32_t iis3dwb_fifo_mode_get(stmdev_ctx_t *ctx, iis3dwb_fifo_mode_t *val) { iis3dwb_fifo_ctrl4_t fifo_ctrl4; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL4, + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); switch (fifo_ctrl4.fifo_mode) @@ -2758,9 +2714,8 @@ int32_t iis3dwb_fifo_temp_batch_set(stmdev_ctx_t *ctx, iis3dwb_odr_t_batch_t val) { iis3dwb_fifo_ctrl4_t fifo_ctrl4; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL4, + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); if (ret == 0) @@ -2786,9 +2741,8 @@ int32_t iis3dwb_fifo_temp_batch_get(stmdev_ctx_t *ctx, iis3dwb_odr_t_batch_t *val) { iis3dwb_fifo_ctrl4_t fifo_ctrl4; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL4, + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); switch (fifo_ctrl4.odr_t_batch) @@ -2819,13 +2773,12 @@ int32_t iis3dwb_fifo_temp_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, - iis3dwb_odr_ts_batch_t val) +int32_t iis3dwb_fifo_timestamp_batch_set(stmdev_ctx_t *ctx, + iis3dwb_fifo_timestamp_batch_t val) { iis3dwb_fifo_ctrl4_t fifo_ctrl4; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL4, + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); if (ret == 0) @@ -2849,13 +2802,12 @@ int32_t iis3dwb_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, - iis3dwb_odr_ts_batch_t *val) +int32_t iis3dwb_fifo_timestamp_batch_get(stmdev_ctx_t *ctx, + iis3dwb_fifo_timestamp_batch_t *val) { iis3dwb_fifo_ctrl4_t fifo_ctrl4; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL4, + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); switch (fifo_ctrl4.odr_ts_batch) @@ -2896,9 +2848,8 @@ int32_t iis3dwb_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, int32_t iis3dwb_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val) { iis3dwb_counter_bdr_reg1_t counter_bdr_reg1; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_COUNTER_BDR_REG1, + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); if (ret == 0) @@ -2923,9 +2874,8 @@ int32_t iis3dwb_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val) int32_t iis3dwb_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_counter_bdr_reg1_t counter_bdr_reg1; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_COUNTER_BDR_REG1, + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); *val = counter_bdr_reg1.rst_counter_bdr; @@ -2946,9 +2896,8 @@ int32_t iis3dwb_batch_counter_threshold_set(stmdev_ctx_t *ctx, { iis3dwb_counter_bdr_reg2_t counter_bdr_reg1; iis3dwb_counter_bdr_reg2_t counter_bdr_reg2; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_COUNTER_BDR_REG1, + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); if (ret == 0) @@ -2982,16 +2931,16 @@ int32_t iis3dwb_batch_counter_threshold_get(stmdev_ctx_t *ctx, { iis3dwb_counter_bdr_reg1_t counter_bdr_reg1; iis3dwb_counter_bdr_reg2_t counter_bdr_reg2; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_COUNTER_BDR_REG1, + *val = 0; + + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); - - if (ret == 0) - { - ret = iis3dwb_read_reg(ctx, IIS3DWB_COUNTER_BDR_REG2, + if (ret != 0) { return ret; } + + ret = iis3dwb_read_reg(ctx, IIS3DWB_COUNTER_BDR_REG2, (uint8_t *)&counter_bdr_reg2, 1); - } + if (ret != 0) { return ret; } *val = counter_bdr_reg1.cnt_bdr_th; *val = *val << 8; @@ -3012,9 +2961,8 @@ int32_t iis3dwb_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) { iis3dwb_fifo_status1_t fifo_status1; iis3dwb_fifo_status2_t fifo_status2; - int32_t ret; - ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_STATUS1, + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_STATUS1, (uint8_t *)&fifo_status1, 1); if (ret == 0) @@ -3033,125 +2981,30 @@ int32_t iis3dwb_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) * @brief Smart FIFO status.[get] * * @param ctx Read / write interface definitions.(ptr) - * @param val Registers FIFO_STATUS2 + * @param val Registers FIFO_STATUS1 and FIFO_STATUS2 * @retval Interface status (MANDATORY: return 0 -> no Error). * */ int32_t iis3dwb_fifo_status_get(stmdev_ctx_t *ctx, - iis3dwb_fifo_status2_t *val) -{ - int32_t ret; - - ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_STATUS2, (uint8_t *)val, 1); - - return ret; -} - -/** - * @brief Smart FIFO full status.[get] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Change the values of fifo_full_ia in reg FIFO_STATUS2 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t iis3dwb_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - iis3dwb_fifo_status2_t fifo_status2; - int32_t ret; - - ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_STATUS2, - (uint8_t *)&fifo_status2, 1); - *val = fifo_status2.fifo_full_ia; - - return ret; -} - -/** - * @brief FIFO overrun status.[get] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Change the values of fifo_over_run_latched in - * reg FIFO_STATUS2 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t iis3dwb_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - iis3dwb_fifo_status2_t fifo_status2; - int32_t ret; - - ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_STATUS2, - (uint8_t *)&fifo_status2, 1); - *val = fifo_status2. fifo_ovr_ia; - - return ret; -} - -/** - * @brief FIFO watermark status.[get] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Change the values of fifo_wtm_ia in reg FIFO_STATUS2 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t iis3dwb_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) + iis3dwb_fifo_status_t *val) { - iis3dwb_fifo_status2_t fifo_status2; - int32_t ret; - - ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_STATUS2, - (uint8_t *)&fifo_status2, 1); - *val = fifo_status2.fifo_wtm_ia; - - return ret; -} - -/** - * @brief Identifies the sensor in FIFO_DATA_OUT.[get] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Change the values of tag_sensor in reg FIFO_DATA_OUT_TAG - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t iis3dwb_fifo_sensor_tag_get(stmdev_ctx_t *ctx, - iis3dwb_fifo_tag_t *val) -{ - iis3dwb_fifo_data_out_tag_t fifo_data_out_tag; - int32_t ret; + uint8_t buff[2]; + iis3dwb_fifo_status2_t status; - ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_DATA_OUT_TAG, - (uint8_t *)&fifo_data_out_tag, 1); + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_STATUS1, (uint8_t *)&buff[0], 2); + bytecpy((uint8_t *)&status, &buff[1]); - switch (fifo_data_out_tag.tag_sensor) - { - case IIS3DWB_XL_TAG: - *val = IIS3DWB_XL_TAG; - break; + val->fifo_bdr = status.counter_bdr_ia; + val->fifo_ovr = status.fifo_ovr_ia | status.fifo_ovr_latched; + val->fifo_full = status.fifo_full_ia; + val->fifo_th = status.fifo_wtm_ia; - case IIS3DWB_TEMPERATURE_TAG: - *val = IIS3DWB_TEMPERATURE_TAG; - break; - - case IIS3DWB_TIMESTAMP_TAG: - *val = IIS3DWB_TIMESTAMP_TAG; - break; - - default: - *val = IIS3DWB_XL_TAG; - break; - } + val->fifo_level = (uint16_t)buff[1] & 0x03U; + val->fifo_level = (val->fifo_level * 256U) + buff[0]; return ret; } -/** - * @} - * - */ - /** * @} * diff --git a/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.h b/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.h index f7bcee1851eb06a7786d681f25ba4b9ab2d19c52..18217b13f84ec30dec63dd15d88513a04477623f 100644 --- a/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.h +++ b/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -520,7 +523,7 @@ typedef struct #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t diff_fifo : 2; uint8_t not_used_01 : 1; - uint8_t over_run_latched : 1; + uint8_t fifo_ovr_latched : 1; uint8_t counter_bdr_ia : 1; uint8_t fifo_full_ia : 1; uint8_t fifo_ovr_ia : 1; @@ -530,7 +533,7 @@ typedef struct uint8_t fifo_ovr_ia : 1; uint8_t fifo_full_ia : 1; uint8_t counter_bdr_ia : 1; - uint8_t over_run_latched : 1; + uint8_t fifo_ovr_latched : 1; uint8_t not_used_01 : 1; uint8_t diff_fifo : 2; #endif /* DRV_BYTE_ORDER */ @@ -716,6 +719,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t iis3dwb_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -735,7 +751,7 @@ extern float_t iis3dwb_from_lsb_to_nsec(int32_t lsb); typedef enum { IIS3DWB_2g = 0, - IIS3DWB_16g = 1, /* if XL_FS_MODE = ‘1’ -> IIS3DWB_2g */ + IIS3DWB_16g = 1, /* if XL_FS_MODE = '1' -> IIS3DWB_2g */ IIS3DWB_4g = 2, IIS3DWB_8g = 3, } iis3dwb_fs_xl_t; @@ -834,8 +850,6 @@ int32_t iis3dwb_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); int32_t iis3dwb_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); -int32_t iis3dwb_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff); - int32_t iis3dwb_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val); int32_t iis3dwb_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val); @@ -971,8 +985,7 @@ typedef struct uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */ uint8_t timestamp : 1; /* timestamp overflow */ uint8_t wake_up : 1; /* wake up event */ -uint8_t sleep_change : - 1; /* Act/Inact (or Vice-versa) status changed */ + uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ uint8_t sleep_status : 1; /* Act/Inact status */ } iis3dwb_pin_int2_route_t; int32_t iis3dwb_pin_int2_route_set(stmdev_ctx_t *ctx, @@ -1081,11 +1094,11 @@ typedef enum IIS3DWB_DEC_1 = 1, IIS3DWB_DEC_8 = 2, IIS3DWB_DEC_32 = 3, -} iis3dwb_odr_ts_batch_t; -int32_t iis3dwb_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, - iis3dwb_odr_ts_batch_t val); -int32_t iis3dwb_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, - iis3dwb_odr_ts_batch_t *val); +} iis3dwb_fifo_timestamp_batch_t; +int32_t iis3dwb_fifo_timestamp_batch_set(stmdev_ctx_t *ctx, + iis3dwb_fifo_timestamp_batch_t val); +int32_t iis3dwb_fifo_timestamp_batch_get(stmdev_ctx_t *ctx, + iis3dwb_fifo_timestamp_batch_t *val); int32_t iis3dwb_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val); int32_t iis3dwb_rst_batch_counter_get(stmdev_ctx_t *ctx, @@ -1098,14 +1111,26 @@ int32_t iis3dwb_batch_counter_threshold_get(stmdev_ctx_t *ctx, int32_t iis3dwb_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val); +typedef struct +{ + uint16_t fifo_level : 10; + uint8_t fifo_bdr : 1; + uint8_t fifo_full : 1; + uint8_t fifo_ovr : 1; + uint8_t fifo_th : 1; +} iis3dwb_fifo_status_t; int32_t iis3dwb_fifo_status_get(stmdev_ctx_t *ctx, - iis3dwb_fifo_status2_t *val); - -int32_t iis3dwb_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t iis3dwb_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); + iis3dwb_fifo_status_t *val); -int32_t iis3dwb_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +typedef struct +{ + uint8_t tag; + uint8_t data[6]; +} iis3dwb_fifo_out_raw_t; +int32_t iis3dwb_fifo_out_raw_get(stmdev_ctx_t *ctx, iis3dwb_fifo_out_raw_t *val); +int32_t iis3dwb_fifo_out_multi_raw_get(stmdev_ctx_t *ctx, + iis3dwb_fifo_out_raw_t *fdata, + uint16_t num); typedef enum { diff --git a/sensor/stmemsc/ilps22qs_STdC/driver/ilps22qs_reg.c b/sensor/stmemsc/ilps22qs_STdC/driver/ilps22qs_reg.c index 128ac8842d9d44213d558eed9139e18f90207710..e884df3fca6ba49a1b3fd280de86ec1ae7e040ab 100644 --- a/sensor/stmemsc/ilps22qs_STdC/driver/ilps22qs_reg.c +++ b/sensor/stmemsc/ilps22qs_STdC/driver/ilps22qs_reg.c @@ -46,8 +46,8 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps22qs_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, - uint16_t len) +int32_t __weak ilps22qs_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, + uint16_t len) { int32_t ret; ret = ctx->read_reg(ctx->handle, reg, data, len); @@ -64,8 +64,8 @@ int32_t ilps22qs_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps22qs_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, - uint16_t len) +int32_t __weak ilps22qs_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, + uint16_t len) { int32_t ret; ret = ctx->write_reg(ctx->handle, reg, data, len); @@ -161,7 +161,7 @@ int32_t ilps22qs_id_get(stmdev_ctx_t *ctx, ilps22qs_id_t *val) */ int32_t ilps22qs_bus_mode_set(stmdev_ctx_t *ctx, ilps22qs_bus_mode_t *val) { - ilps22qs_i3c_if_ctrl_add_t i3c_if_ctrl_add; + ilps22qs_i3c_if_ctrl_t i3c_if_ctrl; ilps22qs_if_ctrl_t if_ctrl; int32_t ret; @@ -174,14 +174,14 @@ int32_t ilps22qs_bus_mode_set(stmdev_ctx_t *ctx, ilps22qs_bus_mode_t *val) } if (ret == 0) { - ret = ilps22qs_read_reg(ctx, ILPS22QS_I3C_IF_CTRL_ADD, - (uint8_t *)&i3c_if_ctrl_add, 1); + ret = ilps22qs_read_reg(ctx, ILPS22QS_I3C_IF_CTRL, + (uint8_t *)&i3c_if_ctrl, 1); } if (ret == 0) { - i3c_if_ctrl_add.asf_on = (uint8_t)val->filter & 0x01U; - ret = ilps22qs_write_reg(ctx, ILPS22QS_I3C_IF_CTRL_ADD, - (uint8_t *)&i3c_if_ctrl_add, 1); + i3c_if_ctrl.asf_on = (uint8_t)val->filter & 0x01U; + ret = ilps22qs_write_reg(ctx, ILPS22QS_I3C_IF_CTRL, + (uint8_t *)&i3c_if_ctrl, 1); } return ret; } @@ -196,15 +196,15 @@ int32_t ilps22qs_bus_mode_set(stmdev_ctx_t *ctx, ilps22qs_bus_mode_t *val) */ int32_t ilps22qs_bus_mode_get(stmdev_ctx_t *ctx, ilps22qs_bus_mode_t *val) { - ilps22qs_i3c_if_ctrl_add_t i3c_if_ctrl_add; + ilps22qs_i3c_if_ctrl_t i3c_if_ctrl; ilps22qs_if_ctrl_t if_ctrl; int32_t ret; ret = ilps22qs_read_reg(ctx, ILPS22QS_IF_CTRL, (uint8_t *)&if_ctrl, 1); if (ret == 0) { - ret = ilps22qs_read_reg(ctx, ILPS22QS_I3C_IF_CTRL_ADD, - (uint8_t *)&i3c_if_ctrl_add, 1); + ret = ilps22qs_read_reg(ctx, ILPS22QS_I3C_IF_CTRL, + (uint8_t *)&i3c_if_ctrl, 1); switch (if_ctrl.i2c_i3c_dis << 1) { @@ -222,7 +222,7 @@ int32_t ilps22qs_bus_mode_get(stmdev_ctx_t *ctx, ilps22qs_bus_mode_t *val) break; } - switch (i3c_if_ctrl_add.asf_on) + switch (i3c_if_ctrl.asf_on) { case ILPS22QS_AUTO: val->filter = ILPS22QS_AUTO; @@ -431,15 +431,57 @@ int32_t ilps22qs_mode_set(stmdev_ctx_t *ctx, ilps22qs_md_t *val) { ilps22qs_ctrl_reg1_t ctrl_reg1; ilps22qs_ctrl_reg2_t ctrl_reg2; - uint8_t reg[2]; + ilps22qs_ctrl_reg3_t ctrl_reg3; + ilps22qs_fifo_ctrl_t fifo_ctrl; + uint8_t odr_save = 0, ah_qvar_en_save = 0; + uint8_t reg[3]; int32_t ret; - ret = ilps22qs_read_reg(ctx, ILPS22QS_CTRL_REG1, reg, 2); + ret = ilps22qs_read_reg(ctx, ILPS22QS_CTRL_REG1, reg, 3); if (ret == 0) { bytecpy((uint8_t *)&ctrl_reg1, ®[0]); bytecpy((uint8_t *)&ctrl_reg2, ®[1]); + bytecpy((uint8_t *)&ctrl_reg3, ®[2]); + + /* handle interleaved mode setting */ + if (ctrl_reg1.odr != 0x0U) + { + /* power-down */ + odr_save = ctrl_reg1.odr; + ctrl_reg1.odr = 0x0U; + ret += ilps22qs_write_reg(ctx, ILPS22QS_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + } + + if (ctrl_reg3.ah_qvar_en != 0U) + { + /* disable QVAR */ + ah_qvar_en_save = ctrl_reg3.ah_qvar_en; + ctrl_reg3.ah_qvar_en = 0; + ret += ilps22qs_write_reg(ctx, ILPS22QS_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + } + + /* set interleaved mode (0 or 1) */ + ctrl_reg3.ah_qvar_p_auto_en = val->interleaved_mode; + ret += ilps22qs_write_reg(ctx, ILPS22QS_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + + /* set FIFO interleaved mode (0 or 1) */ + ret += ilps22qs_read_reg(ctx, ILPS22QS_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + fifo_ctrl.ah_qvar_p_fifo_en = val->interleaved_mode; + ret += ilps22qs_write_reg(ctx, ILPS22QS_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + + if (ah_qvar_en_save != 0U) + { + /* restore ah_qvar_en back to previous setting */ + ctrl_reg3.ah_qvar_en = ah_qvar_en_save; + } + + if (odr_save != 0U) + { + /* restore odr back to previous setting */ + ctrl_reg1.odr = odr_save; + } ctrl_reg1.odr = (uint8_t)val->odr; ctrl_reg1.avg = (uint8_t)val->avg; @@ -449,7 +491,8 @@ int32_t ilps22qs_mode_set(stmdev_ctx_t *ctx, ilps22qs_md_t *val) bytecpy(®[0], (uint8_t *)&ctrl_reg1); bytecpy(®[1], (uint8_t *)&ctrl_reg2); - ret = ilps22qs_write_reg(ctx, ILPS22QS_CTRL_REG1, reg, 2); + bytecpy(®[2], (uint8_t *)&ctrl_reg3); + ret += ilps22qs_write_reg(ctx, ILPS22QS_CTRL_REG1, reg, 3); } return ret; @@ -467,15 +510,17 @@ int32_t ilps22qs_mode_get(stmdev_ctx_t *ctx, ilps22qs_md_t *val) { ilps22qs_ctrl_reg1_t ctrl_reg1; ilps22qs_ctrl_reg2_t ctrl_reg2; - uint8_t reg[2]; + ilps22qs_ctrl_reg3_t ctrl_reg3; + uint8_t reg[3]; int32_t ret; - ret = ilps22qs_read_reg(ctx, ILPS22QS_CTRL_REG1, reg, 2); + ret = ilps22qs_read_reg(ctx, ILPS22QS_CTRL_REG1, reg, 3); if (ret == 0) { bytecpy((uint8_t *)&ctrl_reg1, ®[0]); bytecpy((uint8_t *)&ctrl_reg2, ®[1]); + bytecpy((uint8_t *)&ctrl_reg3, ®[2]); switch (ctrl_reg2.fs_mode) { @@ -570,6 +615,8 @@ int32_t ilps22qs_mode_get(stmdev_ctx_t *ctx, ilps22qs_md_t *val) val->lpf = ILPS22QS_LPF_DISABLE; break; } + + val->interleaved_mode = ctrl_reg3.ah_qvar_p_auto_en; } return ret; } @@ -665,8 +712,32 @@ int32_t ilps22qs_data_get(stmdev_ctx_t *ctx, ilps22qs_md_t *md, data->pressure.raw = (data->pressure.raw * 256) + (int32_t) buff[0]; data->pressure.raw = data->pressure.raw * 256; - switch (md->fs) + if (md->interleaved_mode == 1U) { + if ((buff[0] & 0x1U) == 0U) + { + /* data is a pressure sample */ + switch (md->fs) + { + case ILPS22QS_1260hPa: + data->pressure.hpa = ilps22qs_from_fs1260_to_hPa(data->pressure.raw); + break; + case ILPS22QS_4060hPa: + data->pressure.hpa = ilps22qs_from_fs4000_to_hPa(data->pressure.raw); + break; + default: + data->pressure.hpa = 0.0f; + break; + } + data->ah_qvar.lsb = 0; + } else { + /* data is a AH_QVAR sample */ + data->ah_qvar.lsb = (data->pressure.raw / 256); /* shift 8bit left */ + data->pressure.hpa = 0.0f; + } + } else { + switch (md->fs) + { case ILPS22QS_1260hPa: data->pressure.hpa = ilps22qs_from_fs1260_to_hPa(data->pressure.raw); break; @@ -676,6 +747,8 @@ int32_t ilps22qs_data_get(stmdev_ctx_t *ctx, ilps22qs_md_t *md, default: data->pressure.hpa = 0.0f; break; + } + data->ah_qvar.lsb = 0; } /* temperature conversion */ @@ -867,17 +940,43 @@ int32_t ilps22qs_fifo_data_get(stmdev_ctx_t *ctx, uint8_t samp, data[i].raw = (data[i].raw * 256) + (int32_t)fifo_data[0]; data[i].raw = (data[i].raw * 256); - switch (md->fs) + if (md->interleaved_mode == 1U) { - case ILPS22QS_1260hPa: - data[i].hpa = ilps22qs_from_fs1260_to_hPa(data[i].raw); - break; - case ILPS22QS_4060hPa: - data[i].hpa = ilps22qs_from_fs4000_to_hPa(data[i].raw); - break; - default: + if ((fifo_data[0] & 0x1U) == 0U) + { + /* data is a pressure sample */ + switch (md->fs) + { + case ILPS22QS_1260hPa: + data[i].hpa = ilps22qs_from_fs1260_to_hPa(data[i].raw); + break; + case ILPS22QS_4060hPa: + data[i].hpa = ilps22qs_from_fs4000_to_hPa(data[i].raw); + break; + default: + data[i].hpa = 0.0f; + break; + } + data[i].lsb = 0; + } else { + /* data is a AH_QVAR sample */ + data[i].lsb = (data[i].raw / 256); /* shift 8bit left */ data[i].hpa = 0.0f; - break; + } + } else { + switch (md->fs) + { + case ILPS22QS_1260hPa: + data[i].hpa = ilps22qs_from_fs1260_to_hPa(data[i].raw); + break; + case ILPS22QS_4060hPa: + data[i].hpa = ilps22qs_from_fs4000_to_hPa(data[i].raw); + break; + default: + data[i].hpa = 0.0f; + break; + } + data[i].lsb = 0; } } diff --git a/sensor/stmemsc/ilps22qs_STdC/driver/ilps22qs_reg.h b/sensor/stmemsc/ilps22qs_STdC/driver/ilps22qs_reg.h index 2ae3169af25a7f0b967433df961c1a4b3e94b00e..0b4266ae6a6c2b40b186e2b485f07da8702e29c6 100644 --- a/sensor/stmemsc/ilps22qs_STdC/driver/ilps22qs_reg.h +++ b/sensor/stmemsc/ilps22qs_STdC/driver/ilps22qs_reg.h @@ -109,14 +109,17 @@ typedef struct * */ -typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -283,13 +286,17 @@ typedef struct typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t if_add_inc : 1; - uint8_t not_used_01 : 6; - uint8_t ah_qvar_en : 1; + uint8_t if_add_inc : 1; + uint8_t not_used_01 : 4; + uint8_t ah_qvar_p_auto_en : 1; + uint8_t not_used_02 : 1; + uint8_t ah_qvar_en : 1; #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t ah_qvar_en : 1; - uint8_t not_used_01 : 6; - uint8_t if_add_inc : 1; + uint8_t ah_qvar_en : 1; + uint8_t not_used_02 : 1; + uint8_t ah_qvar_p_auto_en : 1; + uint8_t not_used_01 : 4; + uint8_t if_add_inc : 1; #endif /* DRV_BYTE_ORDER */ } ilps22qs_ctrl_reg3_t; @@ -297,15 +304,17 @@ typedef struct typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t f_mode : 2; - uint8_t trig_modes : 1; - uint8_t stop_on_wtm : 1; - uint8_t not_used_01 : 4; + uint8_t f_mode : 2; + uint8_t trig_modes : 1; + uint8_t stop_on_wtm : 1; + uint8_t ah_qvar_p_fifo_en : 1; + uint8_t not_used_01 : 3; #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 4; - uint8_t stop_on_wtm : 1; - uint8_t trig_modes : 1; - uint8_t f_mode : 2; + uint8_t not_used_01 : 3; + uint8_t ah_qvar_p_fifo_en : 1; + uint8_t stop_on_wtm : 1; + uint8_t trig_modes : 1; + uint8_t f_mode : 2; #endif /* DRV_BYTE_ORDER */ } ilps22qs_fifo_ctrl_t; @@ -324,16 +333,16 @@ typedef struct #define ILPS22QS_REF_P_L 0x16U typedef struct { - uint8_t refl : 8; + uint8_t refp : 8; } ilps22qs_ref_p_l_t; #define ILPS22QS_REF_P_H 0x17U typedef struct { - uint8_t refl : 8; + uint8_t refp : 8; } ilps22qs_ref_p_h_t; -#define ILPS22QS_I3C_IF_CTRL_ADD 0x19U +#define ILPS22QS_I3C_IF_CTRL 0x19U typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN @@ -345,7 +354,7 @@ typedef struct uint8_t asf_on : 1; uint8_t not_used_02 : 5; #endif /* DRV_BYTE_ORDER */ -} ilps22qs_i3c_if_ctrl_add_t; +} ilps22qs_i3c_if_ctrl_t; #define ILPS22QS_RPDS_L 0x1AU #define ILPS22QS_RPDS_H 0x1BU @@ -445,7 +454,7 @@ typedef union ilps22qs_fifo_wtm_t fifo_wtm; ilps22qs_ref_p_l_t ref_p_l; ilps22qs_ref_p_h_t ref_p_h; - ilps22qs_i3c_if_ctrl_add_t i3c_if_ctrl_add; + ilps22qs_i3c_if_ctrl_t i3c_if_ctrl; ilps22qs_int_source_t int_source; ilps22qs_fifo_status1_t fifo_status1; ilps22qs_fifo_status2_t fifo_status2; @@ -454,6 +463,19 @@ typedef union uint8_t byte; } ilps22qs_reg_t; +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t ilps22qs_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); int32_t ilps22qs_write_reg(stmdev_ctx_t *ctx, uint8_t reg, @@ -566,6 +588,7 @@ typedef struct ILPS22QS_LPF_ODR_DIV_4 = 1, ILPS22QS_LPF_ODR_DIV_9 = 3, } lpf; + uint8_t interleaved_mode; } ilps22qs_md_t; int32_t ilps22qs_mode_set(stmdev_ctx_t *ctx, ilps22qs_md_t *val); int32_t ilps22qs_mode_get(stmdev_ctx_t *ctx, ilps22qs_md_t *val); @@ -584,6 +607,10 @@ typedef struct float_t deg_c; int16_t raw; } heat; + struct + { + int32_t lsb; /* 24 bit properly right aligned */ + } ah_qvar; } ilps22qs_data_t; int32_t ilps22qs_data_get(stmdev_ctx_t *ctx, ilps22qs_md_t *md, ilps22qs_data_t *data); @@ -606,7 +633,7 @@ typedef struct ILPS22QS_BYPASS_TO_STREAM = 6, /* Bypass, Dynamic-Stream on Trigger */ ILPS22QS_BYPASS_TO_FIFO = 5, /* Bypass, FIFO on Trigger */ } operation; - uint8_t watermark; /* (0 disable) max 128.*/ + uint8_t watermark : 7; /* (0 disable) max 128.*/ } ilps22qs_fifo_md_t; int32_t ilps22qs_fifo_mode_set(stmdev_ctx_t *ctx, ilps22qs_fifo_md_t *val); int32_t ilps22qs_fifo_mode_get(stmdev_ctx_t *ctx, ilps22qs_fifo_md_t *val); @@ -616,6 +643,7 @@ int32_t ilps22qs_fifo_level_get(stmdev_ctx_t *ctx, uint8_t *val); typedef struct { float_t hpa; + int32_t lsb; /* 24 bit properly right aligned */ int32_t raw; } ilps22qs_fifo_data_t; int32_t ilps22qs_fifo_data_get(stmdev_ctx_t *ctx, uint8_t samp, diff --git a/sensor/stmemsc/ilps28qsw_STdC/driver/ilps28qsw_reg.c b/sensor/stmemsc/ilps28qsw_STdC/driver/ilps28qsw_reg.c new file mode 100644 index 0000000000000000000000000000000000000000..d5fd97d29084217ea5fe61e3e9a891b44147b491 --- /dev/null +++ b/sensor/stmemsc/ilps28qsw_STdC/driver/ilps28qsw_reg.c @@ -0,0 +1,1249 @@ +/* + ****************************************************************************** + * @file ilps28qsw_reg.c + * @author Sensors Software Solution Team + * @brief ILPS28QSW driver file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2023 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "ilps28qsw_reg.h" + +/** + * @defgroup ILPS28QSW + * @brief This file provides a set of functions needed to drive the + * ilps28qsw nano pressure sensor. + * @{ + * + */ + +/** + * @defgroup Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +/** + * @brief Read generic device register + * + * @param ctx read / write interface definitions(ptr) + * @param reg register to read + * @param data pointer to buffer that store the data read(ptr) + * @param len number of consecutive register to read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak ilps28qsw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, + uint16_t len) +{ + int32_t ret; + ret = ctx->read_reg(ctx->handle, reg, data, len); + return ret; +} + +/** + * @brief Write generic device register + * + * @param ctx read / write interface definitions(ptr) + * @param reg register to write + * @param data pointer to data to write in register reg(ptr) + * @param len number of consecutive register to write + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak ilps28qsw_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) +{ + int32_t ret; + ret = ctx->write_reg(ctx->handle, reg, data, len); + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Private_functions + * @brief Section collect all the utility functions needed by APIs. + * @{ + * + */ + +static void bytecpy(uint8_t *target, uint8_t *source) +{ + if ((target != NULL) && (source != NULL)) + { + *target = *source; + } +} + +/** + * @} + * + */ + +/** + * @defgroup Sensitivity + * @brief These functions convert raw-data into engineering units. + * @{ + * + */ + +float_t ilps28qsw_from_fs1260_to_hPa(int32_t lsb) +{ + return ((float_t)lsb / 1048576.0f); /* 4096.0f * 256 */ +} + +float_t ilps28qsw_from_fs4000_to_hPa(int32_t lsb) +{ + return ((float_t)lsb / 524288.0f); /* 2048.0f * 256 */ +} + +float_t ilps28qsw_from_lsb_to_celsius(int16_t lsb) +{ + return ((float_t)lsb / 100.0f); +} + +/** + * @} + * + */ + +/** + * @defgroup Basic functions + * @brief This section groups all the functions concerning device basic + * configuration. + * @{ + * + */ + +/** + * @brief Device "Who am I".[get] + * + * @param ctx communication interface handler.(ptr) + * @param val ID values.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_id_get(stmdev_ctx_t *ctx, ilps28qsw_id_t *val) +{ + uint8_t reg; + int32_t ret; + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_WHO_AM_I, ®, 1); + val->whoami = reg; + + return ret; +} + +/** + * @brief Configures the bus operating mode.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val configures the bus operating mode.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_bus_mode_set(stmdev_ctx_t *ctx, ilps28qsw_bus_mode_t *val) +{ + ilps28qsw_i3c_if_ctrl_t i3c_if_ctrl; + int32_t ret; + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_I3C_IF_CTRL, + (uint8_t *)&i3c_if_ctrl, 1); + if (ret == 0) + { + i3c_if_ctrl.asf_on = (uint8_t)val->filter & 0x01U; + ret = ilps28qsw_write_reg(ctx, ILPS28QSW_I3C_IF_CTRL, + (uint8_t *)&i3c_if_ctrl, 1); + } + return ret; +} + +/** + * @brief Configures the bus operating mode.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val configures the bus operating mode.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_bus_mode_get(stmdev_ctx_t *ctx, ilps28qsw_bus_mode_t *val) +{ + ilps28qsw_i3c_if_ctrl_t i3c_if_ctrl; + int32_t ret; + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_I3C_IF_CTRL, + (uint8_t *)&i3c_if_ctrl, 1); + if (ret == 0) + { + switch (i3c_if_ctrl.asf_on) + { + case ILPS28QSW_AUTO: + val->filter = ILPS28QSW_AUTO; + break; + case ILPS28QSW_ALWAYS_ON: + val->filter = ILPS28QSW_ALWAYS_ON; + break; + default: + val->filter = ILPS28QSW_AUTO; + break; + } + } + return ret; +} + +/** + * @brief Configures the bus operating mode.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val configures the bus operating mode.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_init_set(stmdev_ctx_t *ctx, ilps28qsw_init_t val) +{ + ilps28qsw_ctrl_reg2_t ctrl_reg2; + ilps28qsw_ctrl_reg3_t ctrl_reg3; + uint8_t reg[2]; + int32_t ret; + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_CTRL_REG2, reg, 2); + if (ret == 0) + { + bytecpy((uint8_t *)&ctrl_reg2, ®[0]); + bytecpy((uint8_t *)&ctrl_reg3, ®[1]); + + switch (val) + { + case ILPS28QSW_BOOT: + ctrl_reg2.boot = PROPERTY_ENABLE; + ret = ilps28qsw_write_reg(ctx, ILPS28QSW_CTRL_REG2, + (uint8_t *)&ctrl_reg2, 1); + break; + case ILPS28QSW_RESET: + ctrl_reg2.swreset = PROPERTY_ENABLE; + ret = ilps28qsw_write_reg(ctx, ILPS28QSW_CTRL_REG2, + (uint8_t *)&ctrl_reg2, 1); + break; + case ILPS28QSW_DRV_RDY: + ctrl_reg2.bdu = PROPERTY_ENABLE; + ctrl_reg3.if_add_inc = PROPERTY_ENABLE; + bytecpy(®[0], (uint8_t *)&ctrl_reg2); + bytecpy(®[1], (uint8_t *)&ctrl_reg3); + ret = ilps28qsw_write_reg(ctx, ILPS28QSW_CTRL_REG2, reg, 2); + break; + default: + ctrl_reg2.swreset = PROPERTY_ENABLE; + ret = ilps28qsw_write_reg(ctx, ILPS28QSW_CTRL_REG2, + (uint8_t *)&ctrl_reg2, 1); + break; + } + } + + return ret; +} + +/** + * @brief Get the status of the device.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val the status of the device.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_status_get(stmdev_ctx_t *ctx, ilps28qsw_stat_t *val) +{ + ilps28qsw_interrupt_cfg_t interrupt_cfg; + ilps28qsw_int_source_t int_source; + ilps28qsw_ctrl_reg2_t ctrl_reg2; + ilps28qsw_status_t status; + int32_t ret; + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_CTRL_REG2, + (uint8_t *)&ctrl_reg2, 1); + if (ret == 0) + { + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INT_SOURCE, (uint8_t *)&int_source, 1); + } + if (ret == 0) + { + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_STATUS, (uint8_t *)&status, 1); + } + if (ret == 0) + { + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INTERRUPT_CFG, + (uint8_t *)&interrupt_cfg, 1); + } + val->sw_reset = ctrl_reg2.swreset; + val->boot = int_source.boot_on; + val->drdy_pres = status.p_da; + val->drdy_temp = status.t_da; + val->ovr_pres = status.p_or; + val->ovr_temp = status.t_or; + val->end_meas = ~ctrl_reg2.oneshot; + val->ref_done = ~interrupt_cfg.autozero; + + return ret; +} + +/** + * @brief Electrical pin configuration.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val the electrical settings for the configurable pins.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_pin_conf_set(stmdev_ctx_t *ctx, ilps28qsw_pin_conf_t *val) +{ + ilps28qsw_if_ctrl_t if_ctrl; + int32_t ret; + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_IF_CTRL, (uint8_t *)&if_ctrl, 1); + + if (ret == 0) + { + if_ctrl.sda_pu_en = val->sda_pull_up; + ret = ilps28qsw_write_reg(ctx, ILPS28QSW_IF_CTRL, (uint8_t *)&if_ctrl, 1); + } + + return ret; +} + +/** + * @brief Electrical pin configuration.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val the electrical settings for the configurable pins.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_pin_conf_get(stmdev_ctx_t *ctx, ilps28qsw_pin_conf_t *val) +{ + ilps28qsw_if_ctrl_t if_ctrl; + int32_t ret; + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_IF_CTRL, (uint8_t *)&if_ctrl, 1); + + val->sda_pull_up = if_ctrl.sda_pu_en; + + return ret; +} + +/** + * @brief Get the status of all the interrupt sources.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val the status of all the interrupt sources.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_all_sources_get(stmdev_ctx_t *ctx, + ilps28qsw_all_sources_t *val) +{ + ilps28qsw_fifo_status2_t fifo_status2; + ilps28qsw_int_source_t int_source; + ilps28qsw_status_t status; + int32_t ret; + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_STATUS, (uint8_t *)&status, 1); + if (ret == 0) + { + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INT_SOURCE, + (uint8_t *)&int_source, 1); + } + if (ret == 0) + { + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_FIFO_STATUS2, + (uint8_t *)&fifo_status2, 1); + } + + val->drdy_pres = status.p_da; + val->drdy_temp = status.t_da; + val->over_pres = int_source.ph; + val->under_pres = int_source.pl; + val->thrsld_pres = int_source.ia; + val->fifo_full = fifo_status2.fifo_full_ia; + val->fifo_ovr = fifo_status2.fifo_ovr_ia; + val->fifo_th = fifo_status2.fifo_wtm_ia; + + return ret; +} + + +/** + * @brief Sensor conversion parameters selection.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val set the sensor conversion parameters.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_mode_set(stmdev_ctx_t *ctx, ilps28qsw_md_t *val) +{ + ilps28qsw_ctrl_reg1_t ctrl_reg1; + ilps28qsw_ctrl_reg2_t ctrl_reg2; + ilps28qsw_ctrl_reg3_t ctrl_reg3; + ilps28qsw_fifo_ctrl_t fifo_ctrl; + uint8_t odr_save = 0, ah_qvar_en_save = 0; + uint8_t reg[3]; + int32_t ret; + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_CTRL_REG1, reg, 3); + + if (ret == 0) + { + bytecpy((uint8_t *)&ctrl_reg1, ®[0]); + bytecpy((uint8_t *)&ctrl_reg2, ®[1]); + bytecpy((uint8_t *)&ctrl_reg3, ®[2]); + + /* handle interleaved mode setting */ + if (ctrl_reg1.odr != 0x0U) + { + /* power-down */ + odr_save = ctrl_reg1.odr; + ctrl_reg1.odr = 0x0U; + ret += ilps28qsw_write_reg(ctx, ILPS28QSW_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + } + + if (ctrl_reg3.ah_qvar_en != 0U) + { + /* disable QVAR */ + ah_qvar_en_save = ctrl_reg3.ah_qvar_en; + ctrl_reg3.ah_qvar_en = 0; + ret += ilps28qsw_write_reg(ctx, ILPS28QSW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + } + + /* set interleaved mode (0 or 1) */ + ctrl_reg3.ah_qvar_p_auto_en = val->interleaved_mode; + ret += ilps28qsw_write_reg(ctx, ILPS28QSW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + + /* set FIFO interleaved mode (0 or 1) */ + ret += ilps28qsw_read_reg(ctx, ILPS28QSW_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + fifo_ctrl.ah_qvar_p_fifo_en = val->interleaved_mode; + ret += ilps28qsw_write_reg(ctx, ILPS28QSW_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + + if (ah_qvar_en_save != 0U) + { + /* restore ah_qvar_en back to previous setting */ + ctrl_reg3.ah_qvar_en = ah_qvar_en_save; + } + + if (odr_save != 0U) + { + /* restore odr back to previous setting */ + ctrl_reg1.odr = odr_save; + } + + ctrl_reg1.odr = (uint8_t)val->odr; + ctrl_reg1.avg = (uint8_t)val->avg; + ctrl_reg2.en_lpfp = (uint8_t)val->lpf & 0x01U; + ctrl_reg2.lfpf_cfg = ((uint8_t)val->lpf & 0x02U) >> 2; + ctrl_reg2.fs_mode = (uint8_t)val->fs; + + bytecpy(®[0], (uint8_t *)&ctrl_reg1); + bytecpy(®[1], (uint8_t *)&ctrl_reg2); + bytecpy(®[2], (uint8_t *)&ctrl_reg3); + ret += ilps28qsw_write_reg(ctx, ILPS28QSW_CTRL_REG1, reg, 3); + } + + return ret; +} + +/** + * @brief Sensor conversion parameters selection.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val get the sensor conversion parameters.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_mode_get(stmdev_ctx_t *ctx, ilps28qsw_md_t *val) +{ + ilps28qsw_ctrl_reg1_t ctrl_reg1; + ilps28qsw_ctrl_reg2_t ctrl_reg2; + ilps28qsw_ctrl_reg3_t ctrl_reg3; + uint8_t reg[3]; + int32_t ret; + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_CTRL_REG1, reg, 3); + + if (ret == 0) + { + bytecpy((uint8_t *)&ctrl_reg1, ®[0]); + bytecpy((uint8_t *)&ctrl_reg2, ®[1]); + bytecpy((uint8_t *)&ctrl_reg3, ®[2]); + + switch (ctrl_reg2.fs_mode) + { + case ILPS28QSW_1260hPa: + val->fs = ILPS28QSW_1260hPa; + break; + case ILPS28QSW_4060hPa: + val->fs = ILPS28QSW_4060hPa; + break; + default: + val->fs = ILPS28QSW_1260hPa; + break; + } + + switch (ctrl_reg1.odr) + { + case ILPS28QSW_ONE_SHOT: + val->odr = ILPS28QSW_ONE_SHOT; + break; + case ILPS28QSW_1Hz: + val->odr = ILPS28QSW_1Hz; + break; + case ILPS28QSW_4Hz: + val->odr = ILPS28QSW_4Hz; + break; + case ILPS28QSW_10Hz: + val->odr = ILPS28QSW_10Hz; + break; + case ILPS28QSW_25Hz: + val->odr = ILPS28QSW_25Hz; + break; + case ILPS28QSW_50Hz: + val->odr = ILPS28QSW_50Hz; + break; + case ILPS28QSW_75Hz: + val->odr = ILPS28QSW_75Hz; + break; + case ILPS28QSW_100Hz: + val->odr = ILPS28QSW_100Hz; + break; + case ILPS28QSW_200Hz: + val->odr = ILPS28QSW_200Hz; + break; + default: + val->odr = ILPS28QSW_ONE_SHOT; + break; + } + + switch (ctrl_reg1.avg) + { + case ILPS28QSW_4_AVG: + val->avg = ILPS28QSW_4_AVG; + break; + case ILPS28QSW_8_AVG: + val->avg = ILPS28QSW_8_AVG; + break; + case ILPS28QSW_16_AVG: + val->avg = ILPS28QSW_16_AVG; + break; + case ILPS28QSW_32_AVG: + val->avg = ILPS28QSW_32_AVG; + break; + case ILPS28QSW_64_AVG: + val->avg = ILPS28QSW_64_AVG; + break; + case ILPS28QSW_128_AVG: + val->avg = ILPS28QSW_128_AVG; + break; + case ILPS28QSW_256_AVG: + val->avg = ILPS28QSW_256_AVG; + break; + case ILPS28QSW_512_AVG: + val->avg = ILPS28QSW_512_AVG; + break; + default: + val->avg = ILPS28QSW_4_AVG; + break; + } + + switch ((ctrl_reg2.lfpf_cfg << 2) | ctrl_reg2.en_lpfp) + { + case ILPS28QSW_LPF_DISABLE: + val->lpf = ILPS28QSW_LPF_DISABLE; + break; + case ILPS28QSW_LPF_ODR_DIV_4: + val->lpf = ILPS28QSW_LPF_ODR_DIV_4; + break; + case ILPS28QSW_LPF_ODR_DIV_9: + val->lpf = ILPS28QSW_LPF_ODR_DIV_9; + break; + default: + val->lpf = ILPS28QSW_LPF_DISABLE; + break; + } + + val->interleaved_mode = ctrl_reg3.ah_qvar_p_auto_en; + } + return ret; +} + +/** + * @brief Software trigger for One-Shot.[get] + * + * @param ctx communication interface handler.(ptr) + * @param md the sensor conversion parameters.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_trigger_sw(stmdev_ctx_t *ctx, ilps28qsw_md_t *md) +{ + ilps28qsw_ctrl_reg2_t ctrl_reg2; + int32_t ret = 0; + + if (md->odr == ILPS28QSW_ONE_SHOT) + { + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + ctrl_reg2.oneshot = PROPERTY_ENABLE; + if (ret == 0) + { + ret = ilps28qsw_write_reg(ctx, ILPS28QSW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + } + } + return ret; +} + +/** + * @brief AH/QVAR function enable.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the value of ah_qvar_en in reg CTRL_REG3 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ilps28qsw_ah_qvar_en_set(stmdev_ctx_t *ctx, uint8_t val) +{ + ilps28qsw_ctrl_reg3_t ctrl_reg3; + int32_t ret; + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + + if (ret == 0) + { + ctrl_reg3.ah_qvar_en = val; + ret = ilps28qsw_write_reg(ctx, ILPS28QSW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + } + + return ret; +} + +/** + * @brief AH/QVAR function enable.[get] + * + * @param ctx Read / write interface definitions + * @param val Return the value of ah_qvar_en in reg CTRL_REG3 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ilps28qsw_ah_qvar_en_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + ilps28qsw_ctrl_reg3_t ctrl_reg3; + int32_t ret; + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + *val = ctrl_reg3.ah_qvar_en; + + return ret; +} + +/** + * @brief Software trigger for One-Shot.[get] + * + * @param ctx communication interface handler.(ptr) + * @param md the sensor conversion parameters.(ptr) + * @param data data retrived from the sensor.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_data_get(stmdev_ctx_t *ctx, ilps28qsw_md_t *md, + ilps28qsw_data_t *data) +{ + uint8_t buff[5]; + int32_t ret; + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_PRESS_OUT_XL, buff, 5); + + /* pressure conversion */ + data->pressure.raw = (int32_t)buff[2]; + data->pressure.raw = (data->pressure.raw * 256) + (int32_t) buff[1]; + data->pressure.raw = (data->pressure.raw * 256) + (int32_t) buff[0]; + data->pressure.raw = data->pressure.raw * 256; + + if (md->interleaved_mode == 1U) + { + if ((buff[0] & 0x1U) == 0U) + { + /* data is a pressure sample */ + switch (md->fs) + { + case ILPS28QSW_1260hPa: + data->pressure.hpa = ilps28qsw_from_fs1260_to_hPa(data->pressure.raw); + break; + case ILPS28QSW_4060hPa: + data->pressure.hpa = ilps28qsw_from_fs4000_to_hPa(data->pressure.raw); + break; + default: + data->pressure.hpa = 0.0f; + break; + } + data->ah_qvar.lsb = 0; + } + else + { + /* data is a AH_QVAR sample */ + data->ah_qvar.lsb = (data->pressure.raw / 256); /* shift 8bit left */ + data->pressure.hpa = 0.0f; + } + } + else + { + switch (md->fs) + { + case ILPS28QSW_1260hPa: + data->pressure.hpa = ilps28qsw_from_fs1260_to_hPa(data->pressure.raw); + break; + case ILPS28QSW_4060hPa: + data->pressure.hpa = ilps28qsw_from_fs4000_to_hPa(data->pressure.raw); + break; + default: + data->pressure.hpa = 0.0f; + break; + } + data->ah_qvar.lsb = 0; + } + + /* temperature conversion */ + data->heat.raw = (int16_t)buff[4]; + data->heat.raw = (data->heat.raw * 256) + (int16_t) buff[3]; + data->heat.deg_c = ilps28qsw_from_lsb_to_celsius(data->heat.raw); + + return ret; +} + +/** + * @brief AH/QVAR data read.[get] + * + * @param ctx communication interface handler.(ptr) + * @param md the sensor conversion parameters.(ptr) + * @param data data retrived from the sensor.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_ah_qvar_data_get(stmdev_ctx_t *ctx, + ilps28qsw_ah_qvar_data_t *data) +{ + uint8_t buff[5]; + int32_t ret; + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_PRESS_OUT_XL, buff, 3); + + /* QVAR conversion */ + data->raw = (int32_t)buff[2]; + data->raw = (data->raw * 256) + (int32_t) buff[1]; + data->raw = (data->raw * 256) + (int32_t) buff[0]; + data->raw = (data->raw * 256); + data->lsb = (data->raw / 256); /* shift 8bit left */ + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup FIFO functions + * @brief This section groups all the functions concerning the + * management of FIFO. + * @{ + * + */ + +/** + * @brief FIFO operation mode selection.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val set the FIFO operation mode.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_fifo_mode_set(stmdev_ctx_t *ctx, ilps28qsw_fifo_md_t *val) +{ + ilps28qsw_fifo_ctrl_t fifo_ctrl; + ilps28qsw_fifo_wtm_t fifo_wtm; + uint8_t reg[2]; + int32_t ret; + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_FIFO_CTRL, reg, 2); + if (ret == 0) + { + bytecpy((uint8_t *)&fifo_ctrl, ®[0]); + bytecpy((uint8_t *)&fifo_wtm, ®[1]); + + fifo_ctrl.f_mode = (uint8_t)val->operation & 0x03U; + fifo_ctrl.trig_modes = ((uint8_t)val->operation & 0x04U) >> 2; + + if (val->watermark != 0x00U) + { + fifo_ctrl.stop_on_wtm = PROPERTY_ENABLE; + } + else + { + fifo_ctrl.stop_on_wtm = PROPERTY_DISABLE; + } + + fifo_wtm.wtm = val->watermark; + + bytecpy(®[0], (uint8_t *)&fifo_ctrl); + bytecpy(®[1], (uint8_t *)&fifo_wtm); + + ret = ilps28qsw_write_reg(ctx, ILPS28QSW_FIFO_CTRL, reg, 2); + } + return ret; +} + +/** + * @brief FIFO operation mode selection.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val get the FIFO operation mode.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_fifo_mode_get(stmdev_ctx_t *ctx, ilps28qsw_fifo_md_t *val) +{ + ilps28qsw_fifo_ctrl_t fifo_ctrl; + ilps28qsw_fifo_wtm_t fifo_wtm; + uint8_t reg[2]; + int32_t ret; + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_FIFO_CTRL, reg, 2); + + bytecpy((uint8_t *)&fifo_ctrl, ®[0]); + bytecpy((uint8_t *)&fifo_wtm, ®[1]); + + switch ((fifo_ctrl.trig_modes << 2) | fifo_ctrl.f_mode) + { + case ILPS28QSW_BYPASS: + val->operation = ILPS28QSW_BYPASS; + break; + case ILPS28QSW_FIFO: + val->operation = ILPS28QSW_FIFO; + break; + case ILPS28QSW_STREAM: + val->operation = ILPS28QSW_STREAM; + break; + case ILPS28QSW_STREAM_TO_FIFO: + val->operation = ILPS28QSW_STREAM_TO_FIFO; + break; + case ILPS28QSW_BYPASS_TO_STREAM: + val->operation = ILPS28QSW_BYPASS_TO_STREAM; + break; + case ILPS28QSW_BYPASS_TO_FIFO: + val->operation = ILPS28QSW_BYPASS_TO_FIFO; + break; + default: + val->operation = ILPS28QSW_BYPASS; + break; + } + + val->watermark = fifo_wtm.wtm; + + return ret; +} + +/** + * @brief Get the number of samples stored in FIFO.[get] + * + * @param ctx communication interface handler.(ptr) + * @param md the sensor conversion parameters.(ptr) + * @param val number of samples stored in FIFO.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_fifo_level_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + ilps28qsw_fifo_status1_t fifo_status1; + int32_t ret; + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_FIFO_STATUS1, + (uint8_t *)&fifo_status1, 1); + + *val = fifo_status1.fss; + + return ret; +} + +/** + * @brief Software trigger for One-Shot.[get] + * + * @param ctx communication interface handler.(ptr) + * @param md the sensor conversion parameters.(ptr) + * @param fmd get the FIFO operation mode.(ptr) + * @param samp number of samples stored in FIFO.(ptr) + * @param data data retrived from FIFO.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_fifo_data_get(stmdev_ctx_t *ctx, uint8_t samp, + ilps28qsw_md_t *md, ilps28qsw_fifo_data_t *data) +{ + uint8_t fifo_data[3]; + uint8_t i; + int32_t ret = 0; + + for (i = 0U; i < samp; i++) + { + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_FIFO_DATA_OUT_PRESS_XL, fifo_data, 3); + data[i].raw = (int32_t)fifo_data[2]; + data[i].raw = (data[i].raw * 256) + (int32_t)fifo_data[1]; + data[i].raw = (data[i].raw * 256) + (int32_t)fifo_data[0]; + data[i].raw = (data[i].raw * 256); + + if (md->interleaved_mode == 1U) + { + if ((fifo_data[0] & 0x1U) == 0U) + { + /* data is a pressure sample */ + switch (md->fs) + { + case ILPS28QSW_1260hPa: + data[i].hpa = ilps28qsw_from_fs1260_to_hPa(data[i].raw); + break; + case ILPS28QSW_4060hPa: + data[i].hpa = ilps28qsw_from_fs4000_to_hPa(data[i].raw); + break; + default: + data[i].hpa = 0.0f; + break; + } + data[i].lsb = 0; + } + else + { + /* data is a AH_QVAR sample */ + data[i].lsb = (data[i].raw / 256); /* shift 8bit left */ + data[i].hpa = 0.0f; + } + } + else + { + switch (md->fs) + { + case ILPS28QSW_1260hPa: + data[i].hpa = ilps28qsw_from_fs1260_to_hPa(data[i].raw); + break; + case ILPS28QSW_4060hPa: + data[i].hpa = ilps28qsw_from_fs4000_to_hPa(data[i].raw); + break; + default: + data[i].hpa = 0.0f; + break; + } + data[i].lsb = 0; + } + + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Interrupt signals + * @brief This section groups all the functions concerning + * the management of interrupt signals. + * @{ + * + */ + +/** + * @brief Interrupt pins hardware signal configuration.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val the pins hardware signal settings.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_interrupt_mode_set(stmdev_ctx_t *ctx, + ilps28qsw_int_mode_t *val) +{ + ilps28qsw_interrupt_cfg_t interrupt_cfg; + int32_t ret; + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INTERRUPT_CFG, + (uint8_t *)&interrupt_cfg, 1); + if (ret == 0) + { + interrupt_cfg.lir = val->int_latched ; + ret = ilps28qsw_write_reg(ctx, ILPS28QSW_INTERRUPT_CFG, + (uint8_t *)&interrupt_cfg, 1); + } + return ret; +} + +/** + * @brief Interrupt pins hardware signal configuration.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val the pins hardware signal settings.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_interrupt_mode_get(stmdev_ctx_t *ctx, + ilps28qsw_int_mode_t *val) +{ + ilps28qsw_interrupt_cfg_t interrupt_cfg; + int32_t ret; + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INTERRUPT_CFG, + (uint8_t *)&interrupt_cfg, 1); + + val->int_latched = interrupt_cfg.lir; + + return ret; +} + +/** + * @brief AH function disable + * + * @param ctx communication interface handler.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_ah_qvar_disable(stmdev_ctx_t *ctx) +{ + uint32_t val = 0; + int32_t ret; + + ret = ilps28qsw_write_reg(ctx, ILPS28QSW_ANALOGIC_HUB_DISABLE, (uint8_t *)&val, 1); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Interrupt on threshold functions + * @brief This section groups all the functions concerning + * the wake up functionality. + * @{ + * + */ + +/** + * @brief Configuration of Wake-up and Wake-up to Sleep .[set] + * + * @param ctx communication interface handler.(ptr) + * @param val parameters of configuration.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_int_on_threshold_mode_set(stmdev_ctx_t *ctx, + ilps28qsw_int_th_md_t *val) +{ + ilps28qsw_interrupt_cfg_t interrupt_cfg; + ilps28qsw_ths_p_l_t ths_p_l; + ilps28qsw_ths_p_h_t ths_p_h; + uint8_t reg[3]; + int32_t ret; + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INTERRUPT_CFG, reg, 3); + if (ret == 0) + { + bytecpy((uint8_t *)&interrupt_cfg, ®[0]); + bytecpy((uint8_t *)&ths_p_l, ®[1]); + bytecpy((uint8_t *)&ths_p_h, ®[2]); + + interrupt_cfg.phe = val->over_th; + interrupt_cfg.ple = val->under_th; + ths_p_h.ths = (uint8_t)(val->threshold / 256U); + ths_p_l.ths = (uint8_t)(val->threshold - (ths_p_h.ths * 256U)); + + bytecpy(®[0], (uint8_t *)&interrupt_cfg); + bytecpy(®[1], (uint8_t *)&ths_p_l); + bytecpy(®[2], (uint8_t *)&ths_p_h); + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INTERRUPT_CFG, reg, 3); + } + return ret; +} + +/** + * @brief Configuration of Wake-up and Wake-up to Sleep .[set] + * + * @param ctx communication interface handler.(ptr) + * @param val parameters of configuration.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_int_on_threshold_mode_get(stmdev_ctx_t *ctx, + ilps28qsw_int_th_md_t *val) +{ + ilps28qsw_interrupt_cfg_t interrupt_cfg; + ilps28qsw_ths_p_l_t ths_p_l; + ilps28qsw_ths_p_h_t ths_p_h; + uint8_t reg[3]; + int32_t ret; + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INTERRUPT_CFG, reg, 3); + + bytecpy((uint8_t *)&interrupt_cfg, ®[0]); + bytecpy((uint8_t *)&ths_p_l, ®[1]); + bytecpy((uint8_t *)&ths_p_h, ®[2]); + + val->over_th = interrupt_cfg.phe; + val->under_th = interrupt_cfg.ple; + val->threshold = ths_p_h.ths; + val->threshold = (val->threshold * 256U) + ths_p_l.ths; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Reference value of pressure + * @brief This section groups all the functions concerning + * the wake up functionality. + * @{ + * + */ + +/** + * @brief Configuration of Wake-up and Wake-up to Sleep .[set] + * + * @param ctx communication interface handler.(ptr) + * @param val parameters of configuration.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_reference_mode_set(stmdev_ctx_t *ctx, ilps28qsw_ref_md_t *val) +{ + ilps28qsw_interrupt_cfg_t interrupt_cfg; + int32_t ret; + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INTERRUPT_CFG, + (uint8_t *)&interrupt_cfg, 1); + if (ret == 0) + { + + interrupt_cfg.autozero = val->get_ref; + interrupt_cfg.autorefp = (uint8_t)val->apply_ref & 0x01U; + + interrupt_cfg.reset_az = ((uint8_t)val->apply_ref & 0x02U) >> 1; + interrupt_cfg.reset_arp = ((uint8_t)val->apply_ref & 0x02U) >> 1; + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INTERRUPT_CFG, + (uint8_t *)&interrupt_cfg, 1); + } + return ret; +} + +/** + * @brief Configuration of Wake-up and Wake-up to Sleep .[set] + * + * @param ctx communication interface handler.(ptr) + * @param val parameters of configuration.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_reference_mode_get(stmdev_ctx_t *ctx, ilps28qsw_ref_md_t *val) +{ + ilps28qsw_interrupt_cfg_t interrupt_cfg; + int32_t ret; + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INTERRUPT_CFG, + (uint8_t *)&interrupt_cfg, 1); + + switch ((interrupt_cfg.reset_az << 1) | + interrupt_cfg.autorefp) + { + case ILPS28QSW_OUT_AND_INTERRUPT: + val->apply_ref = ILPS28QSW_OUT_AND_INTERRUPT; + break; + case ILPS28QSW_ONLY_INTERRUPT: + val->apply_ref = ILPS28QSW_ONLY_INTERRUPT; + break; + default: + val->apply_ref = ILPS28QSW_RST_REFS; + break; + } + val->get_ref = interrupt_cfg.autozero; + + return ret; +} + + +/** + * @brief Configuration of Wake-up and Wake-up to Sleep .[set] + * + * @param ctx communication interface handler.(ptr) + * @param val parameters of configuration.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_opc_set(stmdev_ctx_t *ctx, int16_t val) +{ + uint8_t reg[2]; + int32_t ret; + + reg[1] = (uint8_t)(((uint16_t)val & 0xFF00U) / 256U); + reg[0] = (uint8_t)((uint16_t)val & 0x00FFU); + + ret = ilps28qsw_write_reg(ctx, ILPS28QSW_RPDS_L, reg, 2); + + return ret; +} + +/** + * @brief Configuration of Wake-up and Wake-up to Sleep .[set] + * + * @param ctx communication interface handler.(ptr) + * @param val parameters of configuration.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_opc_get(stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t reg[2]; + int32_t ret; + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_RPDS_L, reg, 2); + + *val = (int16_t)reg[1]; + *val = *val * 256 + (int16_t)reg[0]; + + return ret; +} + + +/** + * @} + * + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/ilps28qsw_STdC/driver/ilps28qsw_reg.h b/sensor/stmemsc/ilps28qsw_STdC/driver/ilps28qsw_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..b0dc95261c9a85867e89d0295d282e8e3d67373c --- /dev/null +++ b/sensor/stmemsc/ilps28qsw_STdC/driver/ilps28qsw_reg.h @@ -0,0 +1,693 @@ +/* + ****************************************************************************** + * @file ilps28qsw_reg.h + * @author Sensors Software Solution Team + * @brief This file contains all the functions prototypes for the + * ilps28qsw_reg.c driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2023 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef ILPS28QSW_REGS_H +#define ILPS28QSW_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include + +/** @addtogroup ILPS28QSW + * @{ + * + */ + +/** @defgroup Endianness definitions + * @{ + * + */ + +#ifndef DRV_BYTE_ORDER +#ifndef __BYTE_ORDER__ + +#define DRV_LITTLE_ENDIAN 1234 +#define DRV_BIG_ENDIAN 4321 + +/** if _BYTE_ORDER is not defined, choose the endianness of your architecture + * by uncommenting the define which fits your platform endianness + */ +//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN +#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN + +#else /* defined __BYTE_ORDER__ */ + +#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ +#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ +#define DRV_BYTE_ORDER __BYTE_ORDER__ + +#endif /* __BYTE_ORDER__*/ +#endif /* DRV_BYTE_ORDER */ + +/** + * @} + * + */ + +/** @defgroup STMicroelectronics sensors common types + * @{ + * + */ + +#ifndef MEMS_SHARED_TYPES +#define MEMS_SHARED_TYPES + +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} bitwise_t; + +#define PROPERTY_DISABLE (0U) +#define PROPERTY_ENABLE (1U) + +/** @addtogroup Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); +typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); + +typedef struct +{ + /** Component mandatory fields **/ + stmdev_write_ptr write_reg; + stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; + /** Customizable optional pointer **/ + void *handle; +} stmdev_ctx_t; + +/** + * @} + * + */ + +#endif /* MEMS_SHARED_TYPES */ + +#ifndef MEMS_UCF_SHARED_TYPES +#define MEMS_UCF_SHARED_TYPES + +/** @defgroup Generic address-data structure definition + * @brief This structure is useful to load a predefined configuration + * of a sensor. + * You can create a sensor configuration by your own or using + * Unico / Unicleo tools available on STMicroelectronics + * web site. + * + * @{ + * + */ + +typedef struct +{ + uint8_t address; + uint8_t data; +} ucf_line_t; + +/** + * @} + * + */ + +#endif /* MEMS_UCF_SHARED_TYPES */ + +/** + * @} + * + */ + +/** @defgroup ILPS28QSW_Infos + * @{ + * + */ + +/** I2C Device Address 8 bit format **/ +#define ILPS28QSW_I2C_ADD 0xB9U + +/** Device Identification (Who am I) **/ +#define ILPS28QSW_ID 0xB4U + +/** + * @} + * + */ + +#define ILPS28QSW_INTERRUPT_CFG 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t phe : 1; + uint8_t ple : 1; + uint8_t lir : 1; + uint8_t not_used_01 : 1; + uint8_t reset_az : 1; + uint8_t autozero : 1; + uint8_t reset_arp : 1; + uint8_t autorefp : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t autorefp : 1; + uint8_t reset_arp : 1; + uint8_t autozero : 1; + uint8_t reset_az : 1; + uint8_t not_used_01 : 1; + uint8_t lir : 1; + uint8_t ple : 1; + uint8_t phe : 1; +#endif /* DRV_BYTE_ORDER */ +} ilps28qsw_interrupt_cfg_t; + +#define ILPS28QSW_THS_P_L 0x0CU +typedef struct +{ + uint8_t ths : 8; +} ilps28qsw_ths_p_l_t; + +#define ILPS28QSW_THS_P_H 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ths : 7; + uint8_t not_used_01 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 1; + uint8_t ths : 7; +#endif /* DRV_BYTE_ORDER */ +} ilps28qsw_ths_p_h_t; + +#define ILPS28QSW_IF_CTRL 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 4; + uint8_t sda_pu_en : 1; + uint8_t not_used_02 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 3; + uint8_t sda_pu_en : 1; + uint8_t not_used_01 : 4; +#endif /* DRV_BYTE_ORDER */ +} ilps28qsw_if_ctrl_t; + +#define ILPS28QSW_WHO_AM_I 0x0FU +#define ILPS28QSW_CTRL_REG1 0x10U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t avg : 3; + uint8_t odr : 4; + uint8_t not_used_01 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 1; + uint8_t odr : 4; + uint8_t avg : 3; +#endif /* DRV_BYTE_ORDER */ +} ilps28qsw_ctrl_reg1_t; + +#define ILPS28QSW_CTRL_REG2 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t oneshot : 1; + uint8_t not_used_01 : 1; + uint8_t swreset : 1; + uint8_t bdu : 1; + uint8_t en_lpfp : 1; + uint8_t lfpf_cfg : 1; + uint8_t fs_mode : 1; + uint8_t boot : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t boot : 1; + uint8_t fs_mode : 1; + uint8_t lfpf_cfg : 1; + uint8_t en_lpfp : 1; + uint8_t bdu : 1; + uint8_t swreset : 1; + uint8_t not_used_01 : 1; + uint8_t oneshot : 1; +#endif /* DRV_BYTE_ORDER */ +} ilps28qsw_ctrl_reg2_t; + +#define ILPS28QSW_CTRL_REG3 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t if_add_inc : 1; + uint8_t not_used_01 : 4; + uint8_t ah_qvar_p_auto_en : 1; + uint8_t not_used_02 : 1; + uint8_t ah_qvar_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ah_qvar_en : 1; + uint8_t not_used_02 : 1; + uint8_t ah_qvar_p_auto_en : 1; + uint8_t not_used_01 : 4; + uint8_t if_add_inc : 1; +#endif /* DRV_BYTE_ORDER */ +} ilps28qsw_ctrl_reg3_t; + +#define ILPS28QSW_FIFO_CTRL 0x14U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t f_mode : 2; + uint8_t trig_modes : 1; + uint8_t stop_on_wtm : 1; + uint8_t ah_qvar_p_fifo_en : 1; + uint8_t not_used_01 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 3; + uint8_t ah_qvar_p_fifo_en : 1; + uint8_t stop_on_wtm : 1; + uint8_t trig_modes : 1; + uint8_t f_mode : 2; +#endif /* DRV_BYTE_ORDER */ +} ilps28qsw_fifo_ctrl_t; + +#define ILPS28QSW_FIFO_WTM 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wtm : 7; + uint8_t not_used_01 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 1; + uint8_t wtm : 7; +#endif /* DRV_BYTE_ORDER */ +} ilps28qsw_fifo_wtm_t; + +#define ILPS28QSW_REF_P_L 0x16U +typedef struct +{ + uint8_t refp : 8; +} ilps28qsw_ref_p_l_t; + +#define ILPS28QSW_REF_P_H 0x17U +typedef struct +{ + uint8_t refp : 8; +} ilps28qsw_ref_p_h_t; + +#define ILPS28QSW_I3C_IF_CTRL 0x19U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_02 : 5; + uint8_t asf_on : 1; + uint8_t not_used_01 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 2; + uint8_t asf_on : 1; + uint8_t not_used_02 : 5; +#endif /* DRV_BYTE_ORDER */ +} ilps28qsw_i3c_if_ctrl_t; + +#define ILPS28QSW_RPDS_L 0x1AU +#define ILPS28QSW_RPDS_H 0x1BU +#define ILPS28QSW_INT_SOURCE 0x24U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ph : 1; + uint8_t pl : 1; + uint8_t ia : 1; + uint8_t not_used_01 : 4; + uint8_t boot_on : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t boot_on : 1; + uint8_t not_used_01 : 4; + uint8_t ia : 1; + uint8_t pl : 1; + uint8_t ph : 1; +#endif /* DRV_BYTE_ORDER */ +} ilps28qsw_int_source_t; + +#define ILPS28QSW_FIFO_STATUS1 0x25U +typedef struct +{ + uint8_t fss : 8; +} ilps28qsw_fifo_status1_t; + +#define ILPS28QSW_FIFO_STATUS2 0x26U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 5; + uint8_t fifo_full_ia : 1; + uint8_t fifo_ovr_ia : 1; + uint8_t fifo_wtm_ia : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_wtm_ia : 1; + uint8_t fifo_ovr_ia : 1; + uint8_t fifo_full_ia : 1; + uint8_t not_used_01 : 5; +#endif /* DRV_BYTE_ORDER */ +} ilps28qsw_fifo_status2_t; + +#define ILPS28QSW_STATUS 0x27U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t p_da : 1; + uint8_t t_da : 1; + uint8_t not_used_01 : 2; + uint8_t p_or : 1; + uint8_t t_or : 1; + uint8_t not_used_02 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 2; + uint8_t t_or : 1; + uint8_t p_or : 1; + uint8_t not_used_01 : 2; + uint8_t t_da : 1; + uint8_t p_da : 1; +#endif /* DRV_BYTE_ORDER */ +} ilps28qsw_status_t; + +#define ILPS28QSW_PRESS_OUT_XL 0x28U +#define ILPS28QSW_PRESS_OUT_L 0x29U +#define ILPS28QSW_PRESS_OUT_H 0x2AU +#define ILPS28QSW_TEMP_OUT_L 0x2BU +#define ILPS28QSW_TEMP_OUT_H 0x2CU +#define ILPS28QSW_ANALOGIC_HUB_DISABLE 0x5FU +#define ILPS28QSW_FIFO_DATA_OUT_PRESS_XL 0x78U +#define ILPS28QSW_FIFO_DATA_OUT_PRESS_L 0x79U +#define ILPS28QSW_FIFO_DATA_OUT_PRESS_H 0x7AU + +/** + * @defgroup ILPS28QSW_Register_Union + * @brief This union group all the registers that has a bitfield + * description. + * This union is useful but not need by the driver. + * + * REMOVING this union you are compliant with: + * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " + * + * @{ + * + */ + +typedef union +{ + ilps28qsw_interrupt_cfg_t interrupt_cfg; + ilps28qsw_ths_p_l_t ths_p_l; + ilps28qsw_ths_p_h_t ths_p_h; + ilps28qsw_if_ctrl_t if_ctrl; + ilps28qsw_ctrl_reg1_t ctrl_reg1; + ilps28qsw_ctrl_reg2_t ctrl_reg2; + ilps28qsw_ctrl_reg3_t ctrl_reg3; + ilps28qsw_fifo_ctrl_t fifo_ctrl; + ilps28qsw_fifo_wtm_t fifo_wtm; + ilps28qsw_ref_p_l_t ref_p_l; + ilps28qsw_ref_p_h_t ref_p_h; + ilps28qsw_i3c_if_ctrl_t i3c_if_ctrl; + ilps28qsw_int_source_t int_source; + ilps28qsw_fifo_status1_t fifo_status1; + ilps28qsw_fifo_status2_t fifo_status2; + ilps28qsw_status_t status; + bitwise_t bitwise; + uint8_t byte; +} ilps28qsw_reg_t; + +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + +int32_t ilps28qsw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, uint16_t len); +int32_t ilps28qsw_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, uint16_t len); + +extern float_t ilps28qsw_from_fs1260_to_hPa(int32_t lsb); +extern float_t ilps28qsw_from_fs4000_to_hPa(int32_t lsb); + +extern float_t ilps28qsw_from_lsb_to_celsius(int16_t lsb); + +typedef struct +{ + uint8_t whoami; +} ilps28qsw_id_t; +int32_t ilps28qsw_id_get(stmdev_ctx_t *ctx, ilps28qsw_id_t *val); + +typedef struct +{ + enum + { + ILPS28QSW_AUTO = 0x00, /* anti-spike filters managed by protocol */ + ILPS28QSW_ALWAYS_ON = 0x01, /* anti-spike filters always on */ + } filter; +} ilps28qsw_bus_mode_t; +int32_t ilps28qsw_bus_mode_set(stmdev_ctx_t *ctx, ilps28qsw_bus_mode_t *val); +int32_t ilps28qsw_bus_mode_get(stmdev_ctx_t *ctx, ilps28qsw_bus_mode_t *val); + +typedef enum +{ + ILPS28QSW_DRV_RDY = 0x00, /* Initialize the device for driver usage */ + ILPS28QSW_BOOT = 0x01, /* Restore calib. param. ( it takes 10ms ) */ + ILPS28QSW_RESET = 0x02, /* Reset configuration registers */ +} ilps28qsw_init_t; +int32_t ilps28qsw_init_set(stmdev_ctx_t *ctx, ilps28qsw_init_t val); + +typedef struct +{ + uint8_t sw_reset : 1; /* Restoring configuration registers. */ + uint8_t boot : 1; /* Restoring calibration parameters. */ + uint8_t drdy_pres : 1; /* Pressure data ready. */ + uint8_t drdy_temp : 1; /* Temperature data ready. */ + uint8_t ovr_pres : 1; /* Pressure data overrun. */ + uint8_t ovr_temp : 1; /* Temperature data overrun. */ + uint8_t end_meas : 1; /* Single measurement is finished. */ + uint8_t ref_done : 1; /* Auto-Zero value is set. */ +} ilps28qsw_stat_t; +int32_t ilps28qsw_status_get(stmdev_ctx_t *ctx, ilps28qsw_stat_t *val); + +typedef struct +{ + uint8_t sda_pull_up : 1; /* 1 = pull-up always disabled */ + uint8_t cs_pull_up : 1; /* 1 = pull-up always disabled */ +} ilps28qsw_pin_conf_t; +int32_t ilps28qsw_pin_conf_set(stmdev_ctx_t *ctx, ilps28qsw_pin_conf_t *val); +int32_t ilps28qsw_pin_conf_get(stmdev_ctx_t *ctx, ilps28qsw_pin_conf_t *val); + +typedef struct +{ + uint8_t drdy_pres : 1; /* Pressure data ready */ + uint8_t drdy_temp : 1; /* Temperature data ready */ + uint8_t over_pres : 1; /* Over pressure event */ + uint8_t under_pres : 1; /* Under pressure event */ + uint8_t thrsld_pres : 1; /* Over/Under pressure event */ + uint8_t fifo_full : 1; /* FIFO full */ + uint8_t fifo_ovr : 1; /* FIFO overrun */ + uint8_t fifo_th : 1; /* FIFO threshold reached */ +} ilps28qsw_all_sources_t; +int32_t ilps28qsw_all_sources_get(stmdev_ctx_t *ctx, + ilps28qsw_all_sources_t *val); + +typedef struct +{ + enum + { + ILPS28QSW_1260hPa = 0x00, + ILPS28QSW_4060hPa = 0x01, + } fs; + enum + { + ILPS28QSW_ONE_SHOT = 0x00, /* Device in power down till software trigger */ + ILPS28QSW_1Hz = 0x01, + ILPS28QSW_4Hz = 0x02, + ILPS28QSW_10Hz = 0x03, + ILPS28QSW_25Hz = 0x04, + ILPS28QSW_50Hz = 0x05, + ILPS28QSW_75Hz = 0x06, + ILPS28QSW_100Hz = 0x07, + ILPS28QSW_200Hz = 0x08, + } odr; + enum + { + ILPS28QSW_4_AVG = 0, + ILPS28QSW_8_AVG = 1, + ILPS28QSW_16_AVG = 2, + ILPS28QSW_32_AVG = 3, + ILPS28QSW_64_AVG = 4, + ILPS28QSW_128_AVG = 5, + ILPS28QSW_256_AVG = 6, + ILPS28QSW_512_AVG = 7, + } avg; + enum + { + ILPS28QSW_LPF_DISABLE = 0, + ILPS28QSW_LPF_ODR_DIV_4 = 1, + ILPS28QSW_LPF_ODR_DIV_9 = 3, + } lpf; + uint8_t interleaved_mode; +} ilps28qsw_md_t; +int32_t ilps28qsw_mode_set(stmdev_ctx_t *ctx, ilps28qsw_md_t *val); +int32_t ilps28qsw_mode_get(stmdev_ctx_t *ctx, ilps28qsw_md_t *val); + +int32_t ilps28qsw_trigger_sw(stmdev_ctx_t *ctx, ilps28qsw_md_t *md); + +typedef struct +{ + struct + { + float_t hpa; + int32_t raw; /* 32 bit signed-left algned format left */ + } pressure; + struct + { + float_t deg_c; + int16_t raw; + } heat; + struct + { + int32_t lsb; /* 24 bit properly right aligned */ + } ah_qvar; +} ilps28qsw_data_t; +int32_t ilps28qsw_data_get(stmdev_ctx_t *ctx, ilps28qsw_md_t *md, + ilps28qsw_data_t *data); +typedef struct +{ + int32_t lsb; /* 24 bit properly right aligned */ + int32_t raw; /* 32 bit signed-left algned format left */ +} ilps28qsw_ah_qvar_data_t; +int32_t ilps28qsw_ah_qvar_data_get(stmdev_ctx_t *ctx, + ilps28qsw_ah_qvar_data_t *data); + +typedef struct +{ + enum + { + ILPS28QSW_BYPASS = 0, + ILPS28QSW_FIFO = 1, + ILPS28QSW_STREAM = 2, + ILPS28QSW_STREAM_TO_FIFO = 7, /* Dynamic-Stream, FIFO on Trigger */ + ILPS28QSW_BYPASS_TO_STREAM = 6, /* Bypass, Dynamic-Stream on Trigger */ + ILPS28QSW_BYPASS_TO_FIFO = 5, /* Bypass, FIFO on Trigger */ + } operation; + uint8_t watermark : 7; /* (0 disable) max 128.*/ +} ilps28qsw_fifo_md_t; +int32_t ilps28qsw_fifo_mode_set(stmdev_ctx_t *ctx, ilps28qsw_fifo_md_t *val); +int32_t ilps28qsw_fifo_mode_get(stmdev_ctx_t *ctx, ilps28qsw_fifo_md_t *val); + +int32_t ilps28qsw_fifo_level_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + float_t hpa; + int32_t lsb; /* 24 bit properly right aligned */ + int32_t raw; +} ilps28qsw_fifo_data_t; +int32_t ilps28qsw_fifo_data_get(stmdev_ctx_t *ctx, uint8_t samp, + ilps28qsw_md_t *md, ilps28qsw_fifo_data_t *data); + +typedef struct +{ + uint8_t int_latched : 1; /* int events are: int on threshold, FIFO */ +} ilps28qsw_int_mode_t; +int32_t ilps28qsw_interrupt_mode_set(stmdev_ctx_t *ctx, + ilps28qsw_int_mode_t *val); +int32_t ilps28qsw_interrupt_mode_get(stmdev_ctx_t *ctx, + ilps28qsw_int_mode_t *val); + +int32_t ilps28qsw_ah_qvar_disable(stmdev_ctx_t *ctx); +int32_t ilps28qsw_ah_qvar_en_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t ilps28qsw_ah_qvar_en_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint16_t threshold; /* Threshold in hPa * 16 (@1260hPa) + * Threshold in hPa * 8 (@4060hPa) + */ + uint8_t over_th : 1; /* Pressure data over threshold event */ + uint8_t under_th : 1; /* Pressure data under threshold event */ +} ilps28qsw_int_th_md_t; +int32_t ilps28qsw_int_on_threshold_mode_set(stmdev_ctx_t *ctx, + ilps28qsw_int_th_md_t *val); +int32_t ilps28qsw_int_on_threshold_mode_get(stmdev_ctx_t *ctx, + ilps28qsw_int_th_md_t *val); + +typedef struct +{ + enum + { + ILPS28QSW_OUT_AND_INTERRUPT = 0, + ILPS28QSW_ONLY_INTERRUPT = 1, + ILPS28QSW_RST_REFS = 2, + } apply_ref; + uint8_t get_ref : 1; /* Use current pressure value as reference */ +} ilps28qsw_ref_md_t; +int32_t ilps28qsw_reference_mode_set(stmdev_ctx_t *ctx, + ilps28qsw_ref_md_t *val); +int32_t ilps28qsw_reference_mode_get(stmdev_ctx_t *ctx, + ilps28qsw_ref_md_t *val); + +int32_t ilps28qsw_opc_set(stmdev_ctx_t *ctx, int16_t val); +int32_t ilps28qsw_opc_get(stmdev_ctx_t *ctx, int16_t *val); + +/** + *@} + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ILPS28QSW_REGS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.c b/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.c index fad8ecd93d691bc2f5da22c3c4780425afcf5074..922725f679b06b8a5fbe03e6ef9176c37ca95776 100644 --- a/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.c +++ b/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism303dac_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak ism303dac_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t ism303dac_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism303dac_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak ism303dac_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.h b/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.h index 78da311c07dafc1c82e4f1bd95a8a34ae3b61645..31a9c5a5b2e198d63054fe37353bf512255df40b 100644 --- a/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.h +++ b/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -751,6 +754,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t ism303dac_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.c b/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.c index 12d824f0024fa6faec96c6f233b33c5b63832993..4a785df2450a226dc4dfdedd26378b503029df0b 100644 --- a/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.c +++ b/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330dhcx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak ism330dhcx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; ret = ctx->read_reg(ctx->handle, reg, data, len); @@ -66,9 +66,9 @@ int32_t ism330dhcx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330dhcx_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak ism330dhcx_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; ret = ctx->write_reg(ctx->handle, reg, data, len); @@ -1341,7 +1341,7 @@ int32_t ism330dhcx_temp_flag_data_ready_get(stmdev_ctx_t *ctx, } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * @@ -1360,7 +1360,7 @@ int32_t ism330dhcx_xl_usr_offset_x_set(stmdev_ctx_t *ctx, } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -1379,7 +1379,7 @@ int32_t ism330dhcx_xl_usr_offset_x_get(stmdev_ctx_t *ctx, } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * @@ -1398,7 +1398,7 @@ int32_t ism330dhcx_xl_usr_offset_y_set(stmdev_ctx_t *ctx, } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -1417,7 +1417,7 @@ int32_t ism330dhcx_xl_usr_offset_y_get(stmdev_ctx_t *ctx, } /** - * @brief Accelerometer Z-axis user offset correction expressed in two’s + * @brief Accelerometer Z-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * @@ -1436,7 +1436,7 @@ int32_t ism330dhcx_xl_usr_offset_z_set(stmdev_ctx_t *ctx, } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -1571,7 +1571,7 @@ int32_t ism330dhcx_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) /** * @brief Timestamp first data output register (r). * The value is expressed as a 32-bit word and the bit resolution - * is 25 μs.[get] + * is 25 us.[get] * * @param ctx Read / write interface definitions.(ptr) * @param buff Buffer that stores data read @@ -1673,7 +1673,7 @@ int32_t ism330dhcx_rounding_mode_get(stmdev_ctx_t *ctx, /** * @brief Temperature data output register (r). - * L and H registers together express a 16-bit word in two’s + * L and H registers together express a 16-bit word in two's * complement.[get] * * @param ctx Read / write interface definitions.(ptr) @@ -1695,7 +1695,7 @@ int32_t ism330dhcx_temperature_raw_get(stmdev_ctx_t *ctx, /** * @brief Angular rate sensor. The value is expressed as a 16-bit - * word in two’s complement.[get] + * word in two's complement.[get] * * @param ctx Read / write interface definitions.(ptr) * @param buff Buffer that stores data read @@ -1720,7 +1720,7 @@ int32_t ism330dhcx_angular_rate_raw_get(stmdev_ctx_t *ctx, /** * @brief Linear acceleration output register. The value is expressed as a - * 16-bit word in two’s complement.[get] + * 16-bit word in two's complement.[get] * * @param ctx Read / write interface definitions.(ptr) * @param buff Buffer that stores data read @@ -2112,7 +2112,8 @@ int32_t ism330dhcx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t add, ism330dhcx_page_rw_t page_rw; ism330dhcx_page_sel_t page_sel; ism330dhcx_page_address_t page_address; - uint8_t msb, lsb; + uint8_t msb; + uint8_t lsb; int32_t ret; uint8_t i ; msb = (uint8_t)((add / 256U) & 0x0FU); diff --git a/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.h b/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.h index ff0bdc9ecf5ca8d2dd80b62d33b80cfdd10da5b8..4007172e0c95cab2e709c4bd22fecc295ff0c3a9 100644 --- a/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.h +++ b/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.h @@ -50,7 +50,7 @@ extern "C" { /** if _BYTE_ORDER is not defined, choose the endianness of your architecture * by uncommenting the define which fits your platform endianness */ -//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN +/* #define DRV_BYTE_ORDER DRV_BIG_ENDIAN */ #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN #else /* defined __BYTE_ORDER__ */ @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -2821,6 +2824,18 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ int32_t ism330dhcx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -2847,7 +2862,7 @@ float_t ism330dhcx_from_lsb_to_nsec(int32_t lsb); typedef enum { ISM330DHCX_2g = 0, - ISM330DHCX_16g = 1, /* if XL_FS_MODE = ‘1’ -> ISM330DHCX_2g */ + ISM330DHCX_16g = 1, /* if XL_FS_MODE = '1' -> ISM330DHCX_2g */ ISM330DHCX_4g = 2, ISM330DHCX_8g = 3, } ism330dhcx_fs_xl_t; diff --git a/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.c b/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.c index 7fa81752749da85eb525953ec16a45524aa70e92..0c3e753fe753547f94e190ce637b8b7f4580e124 100644 --- a/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.c +++ b/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330dlc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak ism330dlc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; ret = ctx->read_reg(ctx->handle, reg, data, len); @@ -66,9 +66,9 @@ int32_t ism330dlc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330dlc_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak ism330dlc_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; ret = ctx->write_reg(ctx->handle, reg, data, len); diff --git a/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.h b/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.h index 2a2c8d8e80dc57e64685982681cb31e1c850471e..2c506a24eb6fa3aeeaf7263a8d381a3a3b1367ea 100644 --- a/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.h +++ b/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -1686,6 +1689,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t ism330dlc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/ism330is_STdC/driver/ism330is_reg.c b/sensor/stmemsc/ism330is_STdC/driver/ism330is_reg.c new file mode 100644 index 0000000000000000000000000000000000000000..32af1e6fcd23a38f1e45b7c5cccf9bb1a1000557 --- /dev/null +++ b/sensor/stmemsc/ism330is_STdC/driver/ism330is_reg.c @@ -0,0 +1,3755 @@ +/** + ****************************************************************************** + * @file ism330is_reg.c + * @author Sensors Software Solution Team + * @brief ISM330IS driver file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2022 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "ism330is_reg.h" + +/** + * @defgroup ISM330IS + * @brief This file provides a set of functions needed to drive the + * ism330is enhanced inertial module. + * @{ + * + */ + +/** + * @defgroup Interfaces functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +/** + * @brief Read generic device register + * + * @param ctx communication interface handler.(ptr) + * @param reg first register address to read. + * @param data buffer for data read.(ptr) + * @param len number of consecutive register to read. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak ism330is_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) +{ + int32_t ret; + + ret = ctx->read_reg(ctx->handle, reg, data, len); + + return ret; +} + +/** + * @brief Write generic device register + * + * @param ctx communication interface handler.(ptr) + * @param reg first register address to write. + * @param data the buffer contains data to be written.(ptr) + * @param len number of consecutive register to write. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak ism330is_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) +{ + int32_t ret; + + ret = ctx->write_reg(ctx->handle, reg, data, len); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ISM330IS_Sensitivity + * @brief These functions convert raw-data into engineering units. + * @{ + * + */ + +float_t ism330is_from_fs2g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 0.061f); +} + +float_t ism330is_from_fs4g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 0.122f); +} + +float_t ism330is_from_fs8g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 0.244f); +} + +float_t ism330is_from_fs16g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 0.488f); +} + +float_t ism330is_from_fs125dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 4.375f); +} + +float_t ism330is_from_fs250dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 8.75f); +} + +float_t ism330is_from_fs500dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 17.50f); +} + +float_t ism330is_from_fs1000dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 35.0f); +} + +float_t ism330is_from_fs2000dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 70.0f); +} + +float_t ism330is_from_lsb_to_celsius(int16_t lsb) +{ + return (((float_t)lsb / 256.0f) + 25.0f); +} + +/** + * @defgroup Common + * @brief Common + * @{/ + * + */ + +/** + * @brief Difference in percentage of the effective ODR (and timestamp rate) + * with respect to the typical.[set] + * Step: 0.15%. 8-bit format, 2's complement. + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ism330is_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) +{ + ism330is_internal_freq_fine_t internal_freq_fine; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_INTERNAL_FREQ_FINE, + (uint8_t *)&internal_freq_fine, 1); + + if (ret == 0) + { + internal_freq_fine.freq_fine = (uint8_t)val; + ret = ism330is_write_reg(ctx, ISM330IS_INTERNAL_FREQ_FINE, + (uint8_t *)&internal_freq_fine, 1); + } + + return ret; +} + +/** + * @brief Difference in percentage of the effective ODR (and timestamp rate) + * with respect to the typical.[get] + * Step: 0.15%. 8-bit format, 2's complement. + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ism330is_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330is_internal_freq_fine_t internal_freq_fine; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_INTERNAL_FREQ_FINE, + (uint8_t *)&internal_freq_fine, 1); + *val = internal_freq_fine.freq_fine; + + return ret; +} + +/** + * @brief Change memory bank.[set] + * + * @param ctx read / write interface definitions + * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, SENSOR_HUB_MEM_BANK, ISPU_MEM_BANK, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_mem_bank_set(stmdev_ctx_t *ctx, ism330is_mem_bank_t val) +{ + ism330is_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + if (ret == 0) + { + func_cfg_access.shub_reg_access = (val == ISM330IS_SENSOR_HUB_MEM_BANK) ? 0x1U : 0x0U; + func_cfg_access.ispu_reg_access = (val == ISM330IS_ISPU_MEM_BANK) ? 0x1U : 0x0U; + ret = ism330is_write_reg(ctx, ISM330IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Change memory bank.[get] + * + * @param ctx read / write interface definitions + * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, SENSOR_HUB_MEM_BANK, ISPU_MEM_BANK, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_mem_bank_get(stmdev_ctx_t *ctx, ism330is_mem_bank_t *val) +{ + ism330is_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + if (func_cfg_access.shub_reg_access == 1U) + { + *val = ISM330IS_SENSOR_HUB_MEM_BANK; + } + else if (func_cfg_access.ispu_reg_access == 1U) + { + *val = ISM330IS_ISPU_MEM_BANK; + } + else + { + *val = ISM330IS_MAIN_MEM_BANK; + } + + return ret; +} + +/** + * @brief Enables pulsed data-ready mode (~75 us).[set] + * + * @param ctx read / write interface definitions + * @param val DRDY_LATCHED, DRDY_PULSED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_data_ready_mode_set(stmdev_ctx_t *ctx, + ism330is_data_ready_mode_t val) +{ + ism330is_drdy_pulsed_reg_t drdy_pulsed_reg; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_DRDY_PULSED_REG, (uint8_t *)&drdy_pulsed_reg, 1); + + if (ret == 0) + { + drdy_pulsed_reg.drdy_pulsed = ((uint8_t)val & 0x1U); + ret = ism330is_write_reg(ctx, ISM330IS_DRDY_PULSED_REG, (uint8_t *)&drdy_pulsed_reg, 1); + } + + return ret; +} + +/** + * @brief Enables pulsed data-ready mode (~75 us).[get] + * + * @param ctx read / write interface definitions + * @param val DRDY_LATCHED, DRDY_PULSED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_data_ready_mode_get(stmdev_ctx_t *ctx, + ism330is_data_ready_mode_t *val) +{ + ism330is_drdy_pulsed_reg_t drdy_pulsed_reg; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_DRDY_PULSED_REG, (uint8_t *)&drdy_pulsed_reg, 1); + + switch ((drdy_pulsed_reg.drdy_pulsed)) + { + case ISM330IS_DRDY_LATCHED: + *val = ISM330IS_DRDY_LATCHED; + break; + + case ISM330IS_DRDY_PULSED: + *val = ISM330IS_DRDY_PULSED; + break; + + default: + *val = ISM330IS_DRDY_LATCHED; + break; + } + return ret; +} + +/** + * @brief Device ID.[get] + * + * @param ctx read / write interface definitions + * @param val Device ID. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_device_id_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_WHO_AM_I, (uint8_t *)val, 1); + + return ret; +} + +/** + * @brief Software reset. Restore the default values in user registers.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ism330is_software_reset(stmdev_ctx_t *ctx) +{ + ism330is_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret == 0) + { + ret += ism330is_xl_data_rate_set(ctx, ISM330IS_XL_ODR_OFF); + ret += ism330is_gy_data_rate_set(ctx, ISM330IS_GY_ODR_OFF); + + ctrl3_c.sw_reset = PROPERTY_ENABLE; + ret = ism330is_write_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + do { + ret += ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } while (ret == 0 && ctrl3_c.sw_reset == PROPERTY_ENABLE); + } + + return ret; +} + +/** + * @brief Reboot memory content. Reload the calibration parameters.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of boot in reg CTRL_REG1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ism330is_boot_set(stmdev_ctx_t *ctx, uint8_t val) +{ + ism330is_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret == 0) + { + ctrl3_c.boot = val; + ret = ism330is_write_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + + return ret; +} + +/** + * @brief Reboot memory content. Reload the calibration parameters.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of boot in reg CTRL_REG1.(ptr) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ism330is_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330is_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + *val = ctrl3_c.boot; + + return ret; +} + +/** + * @brief Enable disable high-performance mode[set] + * + * @param ctx read / write interface definitions + * @param val HIGH_PERFOMANCE_MODE_ENABLED, HIGH_PERFOMANCE_MODE_DISABLED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_xl_hm_mode_set(stmdev_ctx_t *ctx, ism330is_hm_mode_t val) +{ + ism330is_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + + if (ret == 0) + { + ctrl6_c.xl_hm_mode = ((uint8_t)val & 0x1U); + ret = ism330is_write_reg(ctx, ISM330IS_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + } + + return ret; +} + +/** + * @brief Enable disable high-performance mode[get] + * + * @param ctx read / write interface definitions + * @param val HIGH_PERFOMANCE_MODE_ENABLED, HIGH_PERFOMANCE_MODE_DISABLED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_xl_hm_mode_get(stmdev_ctx_t *ctx, ism330is_hm_mode_t *val) +{ + ism330is_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + + switch ((ctrl6_c.xl_hm_mode)) + { + case ISM330IS_HIGH_PERFOMANCE_MODE_ENABLED: + *val = ISM330IS_HIGH_PERFOMANCE_MODE_ENABLED; + break; + + case ISM330IS_HIGH_PERFOMANCE_MODE_DISABLED: + *val = ISM330IS_HIGH_PERFOMANCE_MODE_DISABLED; + break; + + default: + *val = ISM330IS_HIGH_PERFOMANCE_MODE_ENABLED; + break; + } + return ret; +} + +/** + * @brief Accelerometer full-scale selection.[set] + * + * @param ctx read / write interface definitions + * @param val 2g, 4g, 8g, 16g, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_xl_full_scale_set(stmdev_ctx_t *ctx, + ism330is_xl_full_scale_t val) +{ + ism330is_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + + if (ret == 0) + { + ctrl1_xl.fs_xl = ((uint8_t)val & 0x3U); + ret = ism330is_write_reg(ctx, ISM330IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + } + + return ret; +} + +/** + * @brief Accelerometer full-scale selection.[get] + * + * @param ctx read / write interface definitions + * @param val 2g, 4g, 8g, 16g, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_xl_full_scale_get(stmdev_ctx_t *ctx, + ism330is_xl_full_scale_t *val) +{ + ism330is_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + + switch ((ctrl1_xl.fs_xl)) + { + case ISM330IS_2g: + *val = ISM330IS_2g; + break; + + case ISM330IS_4g: + *val = ISM330IS_4g; + break; + + case ISM330IS_8g: + *val = ISM330IS_8g; + break; + + case ISM330IS_16g: + *val = ISM330IS_16g; + break; + + default: + *val = ISM330IS_2g; + break; + } + return ret; +} + +/** + * @brief Accelerometer output data rate (ODR) selection.[set] + * + * @param ctx read / write interface definitions + * @param val XL_ODR_OFF, XL_ODR_AT_1Hz875, XL_ODR_AT_7Hz5, XL_ODR_AT_15Hz, XL_ODR_AT_30Hz, XL_ODR_AT_60Hz, XL_ODR_AT_120Hz, XL_ODR_AT_240Hz, XL_ODR_AT_480Hz, XL_ODR_AT_960Hz, XL_ODR_AT_1920Hz, XL_ODR_AT_3840Hz, XL_ODR_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_xl_data_rate_set(stmdev_ctx_t *ctx, + ism330is_xl_data_rate_t val) +{ + ism330is_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + + if (ret == 0) + { + if (((uint8_t)val & 0x10U) == 0x10U) + { + ret += ism330is_xl_hm_mode_set(ctx, ISM330IS_HIGH_PERFOMANCE_MODE_DISABLED); + } + else + { + ret += ism330is_xl_hm_mode_set(ctx, ISM330IS_HIGH_PERFOMANCE_MODE_ENABLED); + } + + ctrl1_xl.odr_xl = ((uint8_t)val & 0xfU); + ret += ism330is_write_reg(ctx, ISM330IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + } + + return ret; +} + +/** + * @brief Accelerometer output data rate (ODR) selection.[get] + * + * @param ctx read / write interface definitions + * @param val XL_ODR_OFF, XL_ODR_AT_1Hz875, XL_ODR_AT_7Hz5, XL_ODR_AT_15Hz, XL_ODR_AT_30Hz, XL_ODR_AT_60Hz, XL_ODR_AT_120Hz, XL_ODR_AT_240Hz, XL_ODR_AT_480Hz, XL_ODR_AT_960Hz, XL_ODR_AT_1920Hz, XL_ODR_AT_3840Hz, XL_ODR_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_xl_data_rate_get(stmdev_ctx_t *ctx, + ism330is_xl_data_rate_t *val) +{ + ism330is_ctrl1_xl_t ctrl1_xl; + ism330is_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret == 0) + { + ret = ism330is_read_reg(ctx, ISM330IS_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + } + + switch ((ctrl6_c.xl_hm_mode << 4) | (ctrl1_xl.odr_xl)) + { + case ISM330IS_XL_ODR_OFF: + *val = ISM330IS_XL_ODR_OFF; + break; + + case ISM330IS_XL_ODR_AT_12Hz5_HP: + *val = ISM330IS_XL_ODR_AT_12Hz5_HP; + break; + + case ISM330IS_XL_ODR_AT_26H_HP: + *val = ISM330IS_XL_ODR_AT_26H_HP; + break; + + case ISM330IS_XL_ODR_AT_52Hz_HP: + *val = ISM330IS_XL_ODR_AT_52Hz_HP; + break; + + case ISM330IS_XL_ODR_AT_104Hz_HP: + *val = ISM330IS_XL_ODR_AT_104Hz_HP; + break; + + case ISM330IS_XL_ODR_AT_208Hz_HP: + *val = ISM330IS_XL_ODR_AT_208Hz_HP; + break; + + case ISM330IS_XL_ODR_AT_416Hz_HP: + *val = ISM330IS_XL_ODR_AT_416Hz_HP; + break; + + case ISM330IS_XL_ODR_AT_833Hz_HP: + *val = ISM330IS_XL_ODR_AT_833Hz_HP; + break; + + case ISM330IS_XL_ODR_AT_1667Hz_HP: + *val = ISM330IS_XL_ODR_AT_1667Hz_HP; + break; + + case ISM330IS_XL_ODR_AT_3333Hz_HP: + *val = ISM330IS_XL_ODR_AT_3333Hz_HP; + break; + + case ISM330IS_XL_ODR_AT_6667Hz_HP: + *val = ISM330IS_XL_ODR_AT_6667Hz_HP; + break; + + case ISM330IS_XL_ODR_AT_12Hz5_LP: + *val = ISM330IS_XL_ODR_AT_12Hz5_LP; + break; + + case ISM330IS_XL_ODR_AT_26H_LP: + *val = ISM330IS_XL_ODR_AT_26H_LP; + break; + + case ISM330IS_XL_ODR_AT_52Hz_LP: + *val = ISM330IS_XL_ODR_AT_52Hz_LP; + break; + + case ISM330IS_XL_ODR_AT_104Hz_LP: + *val = ISM330IS_XL_ODR_AT_104Hz_LP; + break; + + case ISM330IS_XL_ODR_AT_208Hz_LP: + *val = ISM330IS_XL_ODR_AT_208Hz_LP; + break; + + case ISM330IS_XL_ODR_AT_416Hz_LP: + *val = ISM330IS_XL_ODR_AT_416Hz_LP; + break; + + case ISM330IS_XL_ODR_AT_833Hz_LP: + *val = ISM330IS_XL_ODR_AT_833Hz_LP; + break; + + case ISM330IS_XL_ODR_AT_1667Hz_LP: + *val = ISM330IS_XL_ODR_AT_1667Hz_LP; + break; + + case ISM330IS_XL_ODR_AT_3333Hz_LP: + *val = ISM330IS_XL_ODR_AT_3333Hz_LP; + break; + + case ISM330IS_XL_ODR_AT_6667Hz_LP: + *val = ISM330IS_XL_ODR_AT_6667Hz_LP; + break; + + case ISM330IS_XL_ODR_AT_1Hz6_LP: + *val = ISM330IS_XL_ODR_AT_1Hz6_LP; + break; + + default: + *val = ISM330IS_XL_ODR_OFF; + break; + } + return ret; +} + +/** + * @brief Enable disable high-performance mode[set] + * + * @param ctx read / write interface definitions + * @param val HIGH_PERFOMANCE_MODE_ENABLED, HIGH_PERFOMANCE_MODE_DISABLED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_gy_hm_mode_set(stmdev_ctx_t *ctx, ism330is_hm_mode_t val) +{ + ism330is_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + + if (ret == 0) + { + ctrl7_g.g_hm_mode = ((uint8_t)val & 0x1U); + ret = ism330is_write_reg(ctx, ISM330IS_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + } + + return ret; +} + +/** + * @brief Enable disable high-performance mode[get] + * + * @param ctx read / write interface definitions + * @param val HIGH_PERFOMANCE_MODE_ENABLED, HIGH_PERFOMANCE_MODE_DISABLED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_gy_hm_mode_get(stmdev_ctx_t *ctx, ism330is_hm_mode_t *val) +{ + ism330is_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + + switch ((ctrl7_g.g_hm_mode)) + { + case ISM330IS_HIGH_PERFOMANCE_MODE_ENABLED: + *val = ISM330IS_HIGH_PERFOMANCE_MODE_ENABLED; + break; + + case ISM330IS_HIGH_PERFOMANCE_MODE_DISABLED: + *val = ISM330IS_HIGH_PERFOMANCE_MODE_DISABLED; + break; + + default: + *val = ISM330IS_HIGH_PERFOMANCE_MODE_ENABLED; + break; + } + return ret; +} + +/** + * @brief Gyroscope full-scale selection[set] + * + * @param ctx read / write interface definitions + * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_gy_full_scale_set(stmdev_ctx_t *ctx, + ism330is_gy_full_scale_t val) +{ + ism330is_ctrl2_g_t ctrl2_g; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + + if (ret == 0) + { + ctrl2_g.fs_g = ((uint8_t)val & 0x3U); + ctrl2_g.fs_125 = ((uint8_t)val >> 4); + ret = ism330is_write_reg(ctx, ISM330IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + } + + return ret; +} + +/** + * @brief Gyroscope full-scale selection[get] + * + * @param ctx read / write interface definitions + * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_gy_full_scale_get(stmdev_ctx_t *ctx, + ism330is_gy_full_scale_t *val) +{ + ism330is_ctrl2_g_t ctrl2_g; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + + switch ((ctrl2_g.fs_125 << 4) | (ctrl2_g.fs_g)) + { + case ISM330IS_125dps: + *val = ISM330IS_125dps; + break; + + case ISM330IS_250dps: + *val = ISM330IS_250dps; + break; + + case ISM330IS_500dps: + *val = ISM330IS_500dps; + break; + + case ISM330IS_1000dps: + *val = ISM330IS_1000dps; + break; + + case ISM330IS_2000dps: + *val = ISM330IS_2000dps; + break; + + default: + *val = ISM330IS_125dps; + break; + } + return ret; +} + +/** + * @brief Gyroscope output data rate (ODR) selection.[set] + * + * @param ctx read / write interface definitions + * @param val GY_ODR_OFF, GY_ODR_AT_7Hz5, GY_ODR_AT_15Hz, GY_ODR_AT_30Hz, GY_ODR_AT_60Hz, GY_ODR_AT_120Hz, GY_ODR_AT_240Hz, GY_ODR_AT_480Hz, GY_ODR_AT_960Hz, GY_ODR_AT_1920Hz, GY_ODR_AT_3840Hz, GY_ODR_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_gy_data_rate_set(stmdev_ctx_t *ctx, + ism330is_gy_data_rate_t val) +{ + ism330is_ctrl2_g_t ctrl2_g; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + + if (ret == 0) + { + if (((uint8_t)val & 0x10U) == 0x10U) + { + ret += ism330is_gy_hm_mode_set(ctx, ISM330IS_HIGH_PERFOMANCE_MODE_DISABLED); + } + else + { + ret += ism330is_gy_hm_mode_set(ctx, ISM330IS_HIGH_PERFOMANCE_MODE_ENABLED); + } + + ctrl2_g.odr_g = ((uint8_t)val & 0xfU); + ret += ism330is_write_reg(ctx, ISM330IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + } + + return ret; +} + +/** + * @brief Gyroscope output data rate (ODR) selection.[get] + * + * @param ctx read / write interface definitions + * @param val GY_ODR_OFF, GY_ODR_AT_7Hz5, GY_ODR_AT_15Hz, GY_ODR_AT_30Hz, GY_ODR_AT_60Hz, GY_ODR_AT_120Hz, GY_ODR_AT_240Hz, GY_ODR_AT_480Hz, GY_ODR_AT_960Hz, GY_ODR_AT_1920Hz, GY_ODR_AT_3840Hz, GY_ODR_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_gy_data_rate_get(stmdev_ctx_t *ctx, + ism330is_gy_data_rate_t *val) +{ + ism330is_ctrl2_g_t ctrl2_g; + ism330is_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + if (ret == 0) + { + ret = ism330is_read_reg(ctx, ISM330IS_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + } + + switch ((ctrl7_g.g_hm_mode << 4) | (ctrl2_g.odr_g)) + { + case ISM330IS_GY_ODR_OFF: + *val = ISM330IS_GY_ODR_OFF; + break; + + case ISM330IS_GY_ODR_AT_12Hz5_HP: + *val = ISM330IS_GY_ODR_AT_12Hz5_HP; + break; + + case ISM330IS_GY_ODR_AT_26H_HP: + *val = ISM330IS_GY_ODR_AT_26H_HP; + break; + + case ISM330IS_GY_ODR_AT_52Hz_HP: + *val = ISM330IS_GY_ODR_AT_52Hz_HP; + break; + + case ISM330IS_GY_ODR_AT_104Hz_HP: + *val = ISM330IS_GY_ODR_AT_104Hz_HP; + break; + + case ISM330IS_GY_ODR_AT_208Hz_HP: + *val = ISM330IS_GY_ODR_AT_208Hz_HP; + break; + + case ISM330IS_GY_ODR_AT_416Hz_HP: + *val = ISM330IS_GY_ODR_AT_416Hz_HP; + break; + + case ISM330IS_GY_ODR_AT_833Hz_HP: + *val = ISM330IS_GY_ODR_AT_833Hz_HP; + break; + + case ISM330IS_GY_ODR_AT_1667Hz_HP: + *val = ISM330IS_GY_ODR_AT_1667Hz_HP; + break; + + case ISM330IS_GY_ODR_AT_3333Hz_HP: + *val = ISM330IS_GY_ODR_AT_3333Hz_HP; + break; + + case ISM330IS_GY_ODR_AT_6667Hz_HP: + *val = ISM330IS_GY_ODR_AT_6667Hz_HP; + break; + + case ISM330IS_GY_ODR_AT_12Hz5_LP: + *val = ISM330IS_GY_ODR_AT_12Hz5_LP; + break; + + case ISM330IS_GY_ODR_AT_26H_LP: + *val = ISM330IS_GY_ODR_AT_26H_LP; + break; + + case ISM330IS_GY_ODR_AT_52Hz_LP: + *val = ISM330IS_GY_ODR_AT_52Hz_LP; + break; + + case ISM330IS_GY_ODR_AT_104Hz_LP: + *val = ISM330IS_GY_ODR_AT_104Hz_LP; + break; + + case ISM330IS_GY_ODR_AT_208Hz_LP: + *val = ISM330IS_GY_ODR_AT_208Hz_LP; + break; + + case ISM330IS_GY_ODR_AT_416Hz_LP: + *val = ISM330IS_GY_ODR_AT_416Hz_LP; + break; + + case ISM330IS_GY_ODR_AT_833Hz_LP: + *val = ISM330IS_GY_ODR_AT_833Hz_LP; + break; + + case ISM330IS_GY_ODR_AT_1667Hz_LP: + *val = ISM330IS_GY_ODR_AT_1667Hz_LP; + break; + + case ISM330IS_GY_ODR_AT_3333Hz_LP: + *val = ISM330IS_GY_ODR_AT_3333Hz_LP; + break; + + case ISM330IS_GY_ODR_AT_6667Hz_LP: + *val = ISM330IS_GY_ODR_AT_6667Hz_LP; + break; + + default: + *val = ISM330IS_GY_ODR_OFF; + break; + } + + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[set] + * + * @param ctx read / write interface definitions + * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +{ + ism330is_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret == 0) + { + ctrl3_c.if_inc = val; + ret = ism330is_write_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[get] + * + * @param ctx read / write interface definitions + * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330is_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + *val = ctrl3_c.if_inc; + + return ret; +} + +/** + * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [set] + * + * @param ctx read / write interface definitions + * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +{ + ism330is_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret == 0) + { + ctrl3_c.bdu = val; + ret = ism330is_write_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + + return ret; +} + +/** + * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [get] + * + * @param ctx read / write interface definitions + * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330is_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + *val = ctrl3_c.bdu; + + return ret; +} + +/** + * @brief Enables gyroscope sleep mode[set] + * + * @param ctx read / write interface definitions + * @param val SLEEP_G_ENABLE, SLEEP_G_DISABLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_sleep_set(stmdev_ctx_t *ctx, ism330is_sleep_t val) +{ + ism330is_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + + if (ret == 0) + { + ctrl4_c.sleep_g = ((uint8_t)val & 0x1U); + ret = ism330is_write_reg(ctx, ISM330IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + } + + return ret; +} + +/** + * @brief Enables gyroscope sleep mode[get] + * + * @param ctx read / write interface definitions + * @param val SLEEP_G_ENABLE, SLEEP_G_DISABLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_sleep_get(stmdev_ctx_t *ctx, ism330is_sleep_t *val) +{ + ism330is_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + + switch ((ctrl4_c.sleep_g)) + { + case ISM330IS_SLEEP_G_ENABLE: + *val = ISM330IS_SLEEP_G_ENABLE; + break; + + case ISM330IS_SLEEP_G_DISABLE: + *val = ISM330IS_SLEEP_G_DISABLE; + break; + + default: + *val = ISM330IS_SLEEP_G_ENABLE; + break; + } + return ret; +} + +/** + * @brief Accelerometer self-test selection.[set] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_xl_self_test_set(stmdev_ctx_t *ctx, + ism330is_xl_self_test_t val) +{ + ism330is_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + + if (ret == 0) + { + ctrl5_c.st_xl = ((uint8_t)val & 0x3U); + ret = ism330is_write_reg(ctx, ISM330IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + } + + return ret; +} + +/** + * @brief Accelerometer self-test selection.[get] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_xl_self_test_get(stmdev_ctx_t *ctx, + ism330is_xl_self_test_t *val) +{ + ism330is_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + + switch ((ctrl5_c.st_xl)) + { + case ISM330IS_XL_ST_DISABLE: + *val = ISM330IS_XL_ST_DISABLE; + break; + + case ISM330IS_XL_ST_POSITIVE: + *val = ISM330IS_XL_ST_POSITIVE; + break; + + case ISM330IS_XL_ST_NEGATIVE: + *val = ISM330IS_XL_ST_NEGATIVE; + break; + + default: + *val = ISM330IS_XL_ST_DISABLE; + break; + } + return ret; +} + +/** + * @brief Gyroscope self-test selection.[set] + * + * @param ctx read / write interface definitions + * @param val GY_ST_DISABLE, GY_ST_POSITIVE, GY_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_gy_self_test_set(stmdev_ctx_t *ctx, + ism330is_gy_self_test_t val) +{ + ism330is_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + + if (ret == 0) + { + ctrl5_c.st_g = ((uint8_t)val & 0x3U); + ret = ism330is_write_reg(ctx, ISM330IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + } + + return ret; +} + +/** + * @brief Gyroscope self-test selection.[get] + * + * @param ctx read / write interface definitions + * @param val GY_ST_DISABLE, GY_ST_POSITIVE, GY_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_gy_self_test_get(stmdev_ctx_t *ctx, + ism330is_gy_self_test_t *val) +{ + ism330is_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + + switch ((ctrl5_c.st_g)) + { + case ISM330IS_GY_ST_DISABLE: + *val = ISM330IS_GY_ST_DISABLE; + break; + + case ISM330IS_GY_ST_POSITIVE: + *val = ISM330IS_GY_ST_POSITIVE; + break; + + case ISM330IS_GY_ST_NEGATIVE: + *val = ISM330IS_GY_ST_NEGATIVE; + break; + + default: + *val = ISM330IS_GY_ST_DISABLE; + break; + } + return ret; +} + +/** + * @defgroup Serial Interfaces + * @brief Serial Interfaces + * @{/ + * + */ +/** + * @brief Enables pull-up on SDO pin of UI (User Interface).[set] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDO pin of UI (User Interface). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) +{ + ism330is_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + + if (ret == 0) + { + pin_ctrl.sdo_pu_en = val; + ret = ism330is_write_reg(ctx, ISM330IS_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + + return ret; +} + +/** + * @brief Enables pull-up on SDO pin of UI (User Interface).[get] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDO pin of UI (User Interface). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330is_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + + *val = pin_ctrl.sdo_pu_en; + + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val SPI_4_WIRE, SPI_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_spi_mode_set(stmdev_ctx_t *ctx, ism330is_spi_mode_t val) +{ + ism330is_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret == 0) + { + ctrl3_c.sim = ((uint8_t)val & 0x1U); + ret = ism330is_write_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val SPI_4_WIRE, SPI_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_spi_mode_get(stmdev_ctx_t *ctx, ism330is_spi_mode_t *val) +{ + ism330is_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + switch ((ctrl3_c.sim)) + { + case ISM330IS_SPI_4_WIRE: + *val = ISM330IS_SPI_4_WIRE; + break; + + case ISM330IS_SPI_3_WIRE: + *val = ISM330IS_SPI_3_WIRE; + break; + + default: + *val = ISM330IS_SPI_4_WIRE; + break; + } + return ret; +} + +/** + * @brief Disables I2C on UI (User Interface).[set] + * + * @param ctx read / write interface definitions + * @param val I2C_ENABLE, I2C_DISABLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_ui_i2c_mode_set(stmdev_ctx_t *ctx, ism330is_ui_i2c_mode_t val) +{ + ism330is_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + + if (ret == 0) + { + ctrl4_c.i2c_disable = ((uint8_t)val & 0x1U); + ret = ism330is_write_reg(ctx, ISM330IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + } + + return ret; +} + +/** + * @brief Disables I2C on UI (User Interface).[get] + * + * @param ctx read / write interface definitions + * @param val I2C_ENABLE, I2C_DISABLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_ui_i2c_mode_get(stmdev_ctx_t *ctx, ism330is_ui_i2c_mode_t *val) +{ + ism330is_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + + switch ((ctrl4_c.i2c_disable)) + { + case ISM330IS_I2C_ENABLE: + *val = ISM330IS_I2C_ENABLE; + break; + + case ISM330IS_I2C_DISABLE: + *val = ISM330IS_I2C_DISABLE; + break; + + default: + *val = ISM330IS_I2C_ENABLE; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Timestamp + * @brief Timestamp + * @{/ + * + */ +/** + * @brief Enables timestamp counter.[set] + * + * @param ctx read / write interface definitions + * @param val Enables timestamp counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +{ + ism330is_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + if (ret == 0) + { + ctrl10_c.timestamp_en = val; + ret = ism330is_write_reg(ctx, ISM330IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + } + + return ret; +} + +/** + * @brief Enables timestamp counter.[get] + * + * @param ctx read / write interface definitions + * @param val Enables timestamp counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330is_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + *val = ctrl10_c.timestamp_en; + + return ret; +} + +/** + * @brief Timestamp data output.[get] + * + * @param ctx read / write interface definitions + * @param val Timestamp data output. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) +{ + uint8_t buff[4]; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_TIMESTAMP0, &buff[0], 4); + + *val = (uint32_t)buff[3]; + *val = (*val * 256U) + (uint32_t)buff[2]; + *val = (*val * 256U) + (uint32_t)buff[1]; + *val = (*val * 256U) + (uint32_t)buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @brief Get the status of all the interrupt sources.[get] + * + * @param ctx read / write interface definitions + * @param val Get the status of all the interrupt sources. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_all_sources_get(stmdev_ctx_t *ctx, ism330is_all_sources_t *val) +{ + ism330is_status_reg_t status_reg; + ism330is_status_master_mainpage_t status_sh; + uint32_t status_ispu; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret == 0) + { + val->drdy_xl = status_reg.xlda; + val->drdy_gy = status_reg.gda; + val->drdy_temp = status_reg.tda; + } + + ret = ism330is_read_reg(ctx, ISM330IS_STATUS_MASTER_MAINPAGE, (uint8_t *)&status_sh, 1); + if (ret == 0) + { + val->sh_endop = status_sh.sens_hub_endop; + val->sh_slave0_nack = status_sh.sens_hub_endop; + val->sh_slave1_nack = status_sh.sens_hub_endop; + val->sh_slave2_nack = status_sh.sens_hub_endop; + val->sh_slave3_nack = status_sh.sens_hub_endop; + val->sh_wr_once = status_sh.sens_hub_endop; + } + + ret = ism330is_read_reg(ctx, ISM330IS_ISPU_INT_STATUS0_MAINPAGE, (uint8_t *)&status_ispu, 4); + if (ret == 0) + { + val->ispu = status_ispu; + } + + return ret; +} + +/** + * @brief The STATUS_REG register is read by the primary interface.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get register STATUS_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ism330is_status_reg_get(stmdev_ctx_t *ctx, + ism330is_status_reg_t *val) +{ + int32_t ret; + ret = ism330is_read_reg(ctx, ISM330IS_STATUS_REG, (uint8_t *) val, 1); + + return ret; +} + +/** + * @brief Accelerometer new data available.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of xlda in reg STATUS_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ism330is_xl_flag_data_ready_get(stmdev_ctx_t *ctx, + uint8_t *val) +{ + ism330is_status_reg_t status_reg; + int32_t ret; + ret = ism330is_read_reg(ctx, ISM330IS_STATUS_REG, + (uint8_t *)&status_reg, 1); + *val = status_reg.xlda; + + return ret; +} + +/** + * @brief Gyroscope new data available.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of gda in reg STATUS_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ism330is_gy_flag_data_ready_get(stmdev_ctx_t *ctx, + uint8_t *val) +{ + ism330is_status_reg_t status_reg; + int32_t ret; + ret = ism330is_read_reg(ctx, ISM330IS_STATUS_REG, + (uint8_t *)&status_reg, 1); + *val = status_reg.gda; + + return ret; +} + +/** + * @brief Temperature new data available.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of tda in reg STATUS_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ism330is_temp_flag_data_ready_get(stmdev_ctx_t *ctx, + uint8_t *val) +{ + ism330is_status_reg_t status_reg; + int32_t ret; + ret = ism330is_read_reg(ctx, ISM330IS_STATUS_REG, + (uint8_t *)&status_reg, 1); + *val = status_reg.tda; + + return ret; +} + +/** + * @brief Temperature data output register[get] + * + * @param ctx read / write interface definitions + * @param val Temperature data output register + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_OUT_TEMP_L, &buff[0], 2); + *val = (int16_t)buff[1]; + *val = (*val * 256) + (int16_t)buff[0]; + + return ret; +} + +/** + * @brief Angular rate sensor.[get] + * + * @param ctx read / write interface definitions + * @param val Angular rate sensor. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_OUTX_L_G, buff, 6); + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Linear acceleration sensor.[get] + * + * @param ctx read / write interface definitions + * @param val Linear acceleration sensor. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_OUTX_L_A, buff, 6); + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Interrupt PINs + * @brief Interrupt PINs + * @{/ + * + */ +/** + * @brief It routes interrupt signals on INT 1 pin.[set] + * + * @param ctx read / write interface definitions + * @param val It routes interrupt signals on INT 1 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_pin_int1_route_set(stmdev_ctx_t *ctx, + ism330is_pin_int1_route_t val) +{ + ism330is_int1_ctrl_t int1_ctrl; + ism330is_md1_cfg_t md1_cfg; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + if (ret == 0) + { + ret = ism330is_read_reg(ctx, ISM330IS_MD1_CFG, (uint8_t *)&md1_cfg, 1); + } + + if (ret == 0) + { + int1_ctrl.int1_drdy_xl = val.drdy_xl; + int1_ctrl.int1_drdy_g = val.drdy_gy; + int1_ctrl.int1_boot = val.boot; + ret += ism330is_write_reg(ctx, ISM330IS_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + + md1_cfg.int1_shub = val.sh_endop; + md1_cfg.int1_ispu = val.ispu; + ret += ism330is_write_reg(ctx, ISM330IS_MD1_CFG, (uint8_t *)&md1_cfg, 1); + } + + return ret; +} + +/** + * @brief It routes interrupt signals on INT 1 pin.[get] + * + * @param ctx read / write interface definitions + * @param val It routes interrupt signals on INT 1 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_pin_int1_route_get(stmdev_ctx_t *ctx, + ism330is_pin_int1_route_t *val) +{ + ism330is_int1_ctrl_t int1_ctrl; + ism330is_md1_cfg_t md1_cfg; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + if (ret == 0) + { + ret = ism330is_read_reg(ctx, ISM330IS_MD1_CFG, (uint8_t *)&md1_cfg, 1); + } + + if (ret == 0) + { + val->drdy_xl = int1_ctrl.int1_drdy_xl; + val->drdy_gy = int1_ctrl.int1_drdy_g; + val->boot = int1_ctrl.int1_boot; + val->sh_endop = md1_cfg.int1_shub; + val->ispu = md1_cfg.int1_ispu; + } + + return ret; +} + +/** + * @brief It routes interrupt signals on INT 2 pin.[set] + * + * @param ctx read / write interface definitions + * @param val It routes interrupt signals on INT 2 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_pin_int2_route_set(stmdev_ctx_t *ctx, + ism330is_pin_int2_route_t val) +{ + ism330is_int2_ctrl_t int2_ctrl; + ism330is_md2_cfg_t md2_cfg; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + if (ret == 0) + { + ret = ism330is_read_reg(ctx, ISM330IS_MD2_CFG, (uint8_t *)&md2_cfg, 1); + } + + if (ret == 0) + { + int2_ctrl.int2_drdy_xl = val.drdy_xl; + int2_ctrl.int2_drdy_g = val.drdy_gy; + int2_ctrl.int2_drdy_temp = val.drdy_temp; + int2_ctrl.int2_sleep_ispu = val.ispu_sleep; + ret += ism330is_write_reg(ctx, ISM330IS_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + + md2_cfg.int2_ispu = val.ispu; + md2_cfg.int2_timestamp = val.timestamp; + ret += ism330is_write_reg(ctx, ISM330IS_MD2_CFG, (uint8_t *)&md2_cfg, 1); + } + + return ret; +} + +/** + * @brief It routes interrupt signals on INT 2 pin.[get] + * + * @param ctx read / write interface definitions + * @param val It routes interrupt signals on INT 2 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_pin_int2_route_get(stmdev_ctx_t *ctx, + ism330is_pin_int2_route_t *val) +{ + ism330is_int2_ctrl_t int2_ctrl; + ism330is_md2_cfg_t md2_cfg; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + if (ret == 0) + { + ret = ism330is_read_reg(ctx, ISM330IS_MD2_CFG, (uint8_t *)&md2_cfg, 1); + } + + if (ret == 0) + { + val->drdy_xl = int2_ctrl.int2_drdy_xl; + val->drdy_gy = int2_ctrl.int2_drdy_g; + val->drdy_temp = int2_ctrl.int2_drdy_temp; + val->ispu_sleep = int2_ctrl.int2_sleep_ispu; + val->ispu = md2_cfg.int2_ispu; + val->timestamp = md2_cfg.int2_timestamp; + } + + return ret; +} + +/** + * @brief Push-pull/open-drain selection on INT1 and INT2 pins.[set] + * + * @param ctx read / write interface definitions + * @param val PUSH_PULL, OPEN_DRAIN, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_int_pin_mode_set(stmdev_ctx_t *ctx, + ism330is_int_pin_mode_t val) +{ + ism330is_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret == 0) + { + ctrl3_c.pp_od = ((uint8_t)val & 0x1U); + ret = ism330is_write_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + + return ret; +} + +/** + * @brief Push-pull/open-drain selection on INT1 and INT2 pins.[get] + * + * @param ctx read / write interface definitions + * @param val PUSH_PULL, OPEN_DRAIN, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_int_pin_mode_get(stmdev_ctx_t *ctx, + ism330is_int_pin_mode_t *val) +{ + ism330is_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + switch ((ctrl3_c.pp_od)) + { + case ISM330IS_PUSH_PULL: + *val = ISM330IS_PUSH_PULL; + break; + + case ISM330IS_OPEN_DRAIN: + *val = ISM330IS_OPEN_DRAIN; + break; + + default: + *val = ISM330IS_PUSH_PULL; + break; + } + return ret; +} + +/** + * @brief Interrupt activation level.[set] + * + * @param ctx read / write interface definitions + * @param val ACTIVE_HIGH, ACTIVE_LOW, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_pin_polarity_set(stmdev_ctx_t *ctx, + ism330is_pin_polarity_t val) +{ + ism330is_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret == 0) + { + ctrl3_c.h_lactive = ((uint8_t)val & 0x1U); + ret = ism330is_write_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + + return ret; +} + +/** + * @brief Interrupt activation level.[get] + * + * @param ctx read / write interface definitions + * @param val ACTIVE_HIGH, ACTIVE_LOW, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_pin_polarity_get(stmdev_ctx_t *ctx, + ism330is_pin_polarity_t *val) +{ + ism330is_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + switch ((ctrl3_c.h_lactive)) + { + case ISM330IS_ACTIVE_HIGH: + *val = ISM330IS_ACTIVE_HIGH; + break; + + case ISM330IS_ACTIVE_LOW: + *val = ISM330IS_ACTIVE_LOW; + break; + + default: + *val = ISM330IS_ACTIVE_HIGH; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Sensor hub + * @brief This section groups all the functions that manage the + * sensor hub. + * @{ + * + */ + +/** + * @brief Sensor hub output registers.[get] + * + * @param ctx read / write interface definitions + * @param val Sensor hub output registers. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_sh_read_data_raw_get(stmdev_ctx_t *ctx, + ism330is_emb_sh_read_t *val, + uint8_t len) +{ + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = ism330is_read_reg(ctx, ISM330IS_SENSOR_HUB_1, (uint8_t *) val, + len); + } + if (ret == 0) + { + ret = ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + } + + + return ret; +} + +/** + * @brief Number of external sensors to be read by the sensor hub.[set] + * + * @param ctx read / write interface definitions + * @param val SLV_0, SLV_0_1, SLV_0_1_2, SLV_0_1_2_3, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_sh_slave_connected_set(stmdev_ctx_t *ctx, + ism330is_sh_slave_connected_t val) +{ + ism330is_master_config_t master_config; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + master_config.aux_sens_on = (uint8_t)val & 0x3U; + ret = ism330is_write_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + ret = ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief Number of external sensors to be read by the sensor hub.[get] + * + * @param ctx read / write interface definitions + * @param val SLV_0, SLV_0_1, SLV_0_1_2, SLV_0_1_2_3, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_sh_slave_connected_get(stmdev_ctx_t *ctx, + ism330is_sh_slave_connected_t *val) +{ + ism330is_master_config_t master_config; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + ret = ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + } + + switch (master_config.aux_sens_on) + { + case ISM330IS_SLV_0: + *val = ISM330IS_SLV_0; + break; + + case ISM330IS_SLV_0_1: + *val = ISM330IS_SLV_0_1; + break; + + case ISM330IS_SLV_0_1_2: + *val = ISM330IS_SLV_0_1_2; + break; + + case ISM330IS_SLV_0_1_2_3: + *val = ISM330IS_SLV_0_1_2_3; + break; + + default: + *val = ISM330IS_SLV_0; + break; + } + return ret; +} + +/** + * @brief Sensor hub I2C master enable.[set] + * + * @param ctx read / write interface definitions + * @param val Sensor hub I2C master enable. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) +{ + ism330is_master_config_t master_config; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + master_config.master_on = val; + ret = ism330is_write_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + ret = ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief Sensor hub I2C master enable.[get] + * + * @param ctx read / write interface definitions + * @param val Sensor hub I2C master enable. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330is_master_config_t master_config; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + *val = master_config.master_on; + + if (ret == 0) + { + ret = ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief Sensor Hub master I2C pull-up enable.[set] + * + * @param ctx read / write interface definitions + * @param val Sensor Hub master I2C pull-up enable. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_sh_master_interface_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) +{ + ism330is_master_config_t master_config; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + master_config.shub_pu_en = val; + ret = ism330is_write_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + ret = ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief Sensor Hub master I2C pull-up enable.[get] + * + * @param ctx read / write interface definitions + * @param val Sensor Hub master I2C pull-up enable. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_sh_master_interface_pull_up_get(stmdev_ctx_t *ctx, + uint8_t *val) +{ + ism330is_master_config_t master_config; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + *val = master_config.shub_pu_en; + + if (ret == 0) + { + ret = ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief I2C interface pass-through.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of pass_through_mode in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ism330is_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) +{ + ism330is_master_config_t master_config; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); + + if (ret == 0) + { + ret = ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + master_config.pass_through_mode = (uint8_t)val; + ret = ism330is_write_reg(ctx, ISM330IS_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + ret = ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief I2C interface pass-through.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of pass_through_mode in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ism330is_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330is_master_config_t master_config; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); + + if (ret == 0) + { + ret = ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + *val = master_config.pass_through_mode; + ret = ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief Sensor hub trigger signal selection.[set] + * + * @param ctx read / write interface definitions + * @param val SH_TRG_XL_GY_DRDY, SH_TRIG_INT2, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_sh_syncro_mode_set(stmdev_ctx_t *ctx, + ism330is_sh_syncro_mode_t val) +{ + ism330is_master_config_t master_config; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + master_config.start_config = (uint8_t)val & 0x01U; + ret = ism330is_write_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + ret = ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief Sensor hub trigger signal selection.[get] + * + * @param ctx read / write interface definitions + * @param val SH_TRG_XL_GY_DRDY, SH_TRIG_INT2, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_sh_syncro_mode_get(stmdev_ctx_t *ctx, + ism330is_sh_syncro_mode_t *val) +{ + ism330is_master_config_t master_config; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + ret = ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + } + + switch (master_config.start_config) + { + case ISM330IS_SH_TRG_XL_GY_DRDY: + *val = ISM330IS_SH_TRG_XL_GY_DRDY; + break; + + case ISM330IS_SH_TRIG_INT2: + *val = ISM330IS_SH_TRIG_INT2; + break; + + default: + *val = ISM330IS_SH_TRG_XL_GY_DRDY; + break; + } + return ret; +} + +/** + * @brief Slave 0 write operation is performed only at the first sensor hub cycle.[set] + * + * @param ctx read / write interface definitions + * @param val EACH_SH_CYCLE, ONLY_FIRST_CYCLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_sh_write_mode_set(stmdev_ctx_t *ctx, + ism330is_sh_write_mode_t val) +{ + ism330is_master_config_t master_config; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + master_config.write_once = (uint8_t)val & 0x01U; + ret = ism330is_write_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + ret = ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief Slave 0 write operation is performed only at the first sensor hub cycle.[get] + * + * @param ctx read / write interface definitions + * @param val EACH_SH_CYCLE, ONLY_FIRST_CYCLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_sh_write_mode_get(stmdev_ctx_t *ctx, + ism330is_sh_write_mode_t *val) +{ + ism330is_master_config_t master_config; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + ret = ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + } + + + switch (master_config.write_once) + { + case ISM330IS_EACH_SH_CYCLE: + *val = ISM330IS_EACH_SH_CYCLE; + break; + + case ISM330IS_ONLY_FIRST_CYCLE: + *val = ISM330IS_ONLY_FIRST_CYCLE; + break; + + default: + *val = ISM330IS_EACH_SH_CYCLE; + break; + } + return ret; +} + +/** + * @brief Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.[set] + * + * @param ctx read / write interface definitions + * @param val Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_sh_reset_set(stmdev_ctx_t *ctx, uint8_t val) +{ + ism330is_master_config_t master_config; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + master_config.rst_master_regs = val; + ret = ism330is_write_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + ret = ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.[get] + * + * @param ctx read / write interface definitions + * @param val Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330is_master_config_t master_config; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + *val = master_config.rst_master_regs; + + if (ret == 0) + { + ret = ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief Configure slave 0 for perform a write.[set] + * + * @param ctx read / write interface definitions + * @param val a structure that contain + * - uint8_t slv1_add; 8 bit i2c device address + * - uint8_t slv1_subadd; 8 bit register device address + * - uint8_t slv1_data; 8 bit data to write + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_sh_cfg_write(stmdev_ctx_t *ctx, + ism330is_sh_cfg_write_t *val) +{ + ism330is_slv0_add_t reg; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + reg.slave0_add = val->slv0_add; + reg.rw_0 = 0; + ret = ism330is_write_reg(ctx, ISM330IS_SLV0_ADD, (uint8_t *)®, 1); + } + + if (ret == 0) + { + ret = ism330is_write_reg(ctx, ISM330IS_SLV0_SUBADD, + &(val->slv0_subadd), 1); + } + + if (ret == 0) + { + ret = ism330is_write_reg(ctx, ISM330IS_DATAWRITE_SLV0, + &(val->slv0_data), 1); + } + + if (ret == 0) + { + ret = ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief Rate at which the master communicates.[set] + * + * @param ctx read / write interface definitions + * @param val SH_12_5Hz, SH_26Hz, SH_52Hz, SH_104Hz + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_sh_data_rate_set(stmdev_ctx_t *ctx, + ism330is_sh_data_rate_t val) +{ + ism330is_slv0_config_t slv0_config; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = ism330is_read_reg(ctx, ISM330IS_SLAVE0_CONFIG, (uint8_t *)&slv0_config, 1); + } + + if (ret == 0) + { + slv0_config.shub_odr = (uint8_t)val & 0x07U; + ret = ism330is_write_reg(ctx, ISM330IS_SLAVE0_CONFIG, (uint8_t *)&slv0_config, 1); + } + if (ret == 0) + { + ret = ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief Rate at which the master communicates.[get] + * + * @param ctx read / write interface definitions + * @param val SH_12_5Hz, SH_26Hz, SH_52Hz, SH_104Hz + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_sh_data_rate_get(stmdev_ctx_t *ctx, + ism330is_sh_data_rate_t *val) +{ + ism330is_slv0_config_t slv0_config; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = ism330is_read_reg(ctx, ISM330IS_SLAVE0_CONFIG, (uint8_t *)&slv0_config, 1); + } + if (ret == 0) + { + ret = ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + } + + switch (slv0_config.shub_odr) + { + case ISM330IS_SH_12_5Hz: + *val = ISM330IS_SH_12_5Hz; + break; + + case ISM330IS_SH_26Hz: + *val = ISM330IS_SH_26Hz; + break; + + case ISM330IS_SH_52Hz: + *val = ISM330IS_SH_52Hz; + break; + + case ISM330IS_SH_104Hz: + *val = ISM330IS_SH_104Hz; + break; + + default: + *val = ISM330IS_SH_12_5Hz; + break; + } + return ret; +} + +/** + * @brief Configure slave 0 for perform a read.[set] + * + * @param ctx read / write interface definitions + * @param val Structure that contain + * - uint8_t slv1_add; 8 bit i2c device address + * - uint8_t slv1_subadd; 8 bit register device address + * - uint8_t slv1_len; num of bit to read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_sh_slv0_cfg_read(stmdev_ctx_t *ctx, + ism330is_sh_cfg_read_t *val) +{ + ism330is_slv0_add_t slv0_add; + ism330is_slv0_config_t slv0_config; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); + + if (ret == 0) + { + slv0_add.slave0_add = val->slv_add; + slv0_add.rw_0 = 1; + ret = ism330is_write_reg(ctx, ISM330IS_SLV0_ADD, (uint8_t *)&slv0_add, 1); + } + + if (ret == 0) + { + ret = ism330is_write_reg(ctx, ISM330IS_SLV0_SUBADD, + &(val->slv_subadd), 1); + } + + if (ret == 0) + { + ret = ism330is_read_reg(ctx, ISM330IS_SLAVE0_CONFIG, + (uint8_t *)&slv0_config, 1); + } + + if (ret == 0) + { + slv0_config.slave0_numop = val->slv_len; + ret = ism330is_write_reg(ctx, ISM330IS_SLAVE0_CONFIG, + (uint8_t *)&slv0_config, 1); + } + + if (ret == 0) + { + ret = ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief Configure slave 0 for perform a write/read.[set] + * + * @param ctx read / write interface definitions + * @param val Structure that contain + * - uint8_t slv1_add; 8 bit i2c device address + * - uint8_t slv1_subadd; 8 bit register device address + * - uint8_t slv1_len; num of bit to read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_sh_slv1_cfg_read(stmdev_ctx_t *ctx, + ism330is_sh_cfg_read_t *val) +{ + ism330is_slv1_add_t slv1_add; + ism330is_slv1_config_t slv1_config; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); + + if (ret == 0) + { + slv1_add.slave1_add = val->slv_add; + slv1_add.r_1 = 1; + ret = ism330is_write_reg(ctx, ISM330IS_SLV1_ADD, (uint8_t *)&slv1_add, 1); + } + + if (ret == 0) + { + ret = ism330is_write_reg(ctx, ISM330IS_SLV1_SUBADD, + &(val->slv_subadd), 1); + } + + if (ret == 0) + { + ret = ism330is_read_reg(ctx, ISM330IS_SLAVE1_CONFIG, + (uint8_t *)&slv1_config, 1); + } + + if (ret == 0) + { + slv1_config.slave1_numop = val->slv_len; + ret = ism330is_write_reg(ctx, ISM330IS_SLAVE1_CONFIG, + (uint8_t *)&slv1_config, 1); + } + + if (ret == 0) + { + ret = ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief Configure slave 0 for perform a write/read.[set] + * + * @param ctx read / write interface definitions + * @param val Structure that contain + * - uint8_t slv2_add; 8 bit i2c device address + * - uint8_t slv2_subadd; 8 bit register device address + * - uint8_t slv2_len; num of bit to read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_sh_slv2_cfg_read(stmdev_ctx_t *ctx, + ism330is_sh_cfg_read_t *val) +{ + ism330is_slv2_add_t slv2_add; + ism330is_slv2_config_t slv2_config; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); + + if (ret == 0) + { + slv2_add.slave2_add = val->slv_add; + slv2_add.r_2 = 1; + ret = ism330is_write_reg(ctx, ISM330IS_SLV2_ADD, (uint8_t *)&slv2_add, 1); + } + + if (ret == 0) + { + ret = ism330is_write_reg(ctx, ISM330IS_SLV2_SUBADD, + &(val->slv_subadd), 1); + } + + if (ret == 0) + { + ret = ism330is_read_reg(ctx, ISM330IS_SLAVE2_CONFIG, + (uint8_t *)&slv2_config, 1); + } + + if (ret == 0) + { + slv2_config.slave2_numop = val->slv_len; + ret = ism330is_write_reg(ctx, ISM330IS_SLAVE2_CONFIG, + (uint8_t *)&slv2_config, 1); + } + + if (ret == 0) + { + ret = ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief Configure slave 0 for perform a write/read.[set] + * + * @param ctx read / write interface definitions + * @param val Structure that contain + * - uint8_t slv3_add; 8 bit i2c device address + * - uint8_t slv3_subadd; 8 bit register device address + * - uint8_t slv3_len; num of bit to read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_sh_slv3_cfg_read(stmdev_ctx_t *ctx, + ism330is_sh_cfg_read_t *val) +{ + ism330is_slv3_add_t slv3_add; + ism330is_slv3_config_t slv3_config; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); + + if (ret == 0) + { + slv3_add.slave3_add = val->slv_add; + slv3_add.r_3 = 1; + ret = ism330is_write_reg(ctx, ISM330IS_SLV3_ADD, (uint8_t *)&slv3_add, 1); + } + + if (ret == 0) + { + ret = ism330is_write_reg(ctx, ISM330IS_SLV3_SUBADD, + &(val->slv_subadd), 1); + } + + if (ret == 0) + { + ret = ism330is_read_reg(ctx, ISM330IS_SLAVE3_CONFIG, + (uint8_t *)&slv3_config, 1); + } + + if (ret == 0) + { + slv3_config.slave3_numop = val->slv_len; + ret = ism330is_write_reg(ctx, ISM330IS_SLAVE3_CONFIG, + (uint8_t *)&slv3_config, 1); + } + + if (ret == 0) + { + ret = ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ispu + * @brief ispu + * @{/ + * + */ +/** + * @brief Software reset of ISPU core.[set] + * + * @param ctx read / write interface definitions + * @param val Software reset of ISPU core. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_ispu_reset_set(stmdev_ctx_t *ctx, uint8_t val) +{ + ism330is_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + if (ret == 0) + { + func_cfg_access.sw_reset_ispu = val; + ret = ism330is_write_reg(ctx, ISM330IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Software reset of ISPU core.[get] + * + * @param ctx read / write interface definitions + * @param val Software reset of ISPU core. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_ispu_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330is_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + *val = func_cfg_access.sw_reset_ispu; + + + return ret; +} + +int32_t ism330is_ispu_clock_set(stmdev_ctx_t *ctx, + ism330is_ispu_clock_sel_t val) +{ + ism330is_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + if (ret == 0) + { + ctrl10_c.ispu_clk_sel = (uint8_t)val; + ret += ism330is_write_reg(ctx, ISM330IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + } + + return ret; +} + +int32_t ism330is_ispu_clock_get(stmdev_ctx_t *ctx, + ism330is_ispu_clock_sel_t *val) +{ + ism330is_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + switch (ctrl10_c.ispu_clk_sel) + { + default: + case 0: + *val = ISM330IS_ISPU_CLK_5MHz; + break; + case 1: + *val = ISM330IS_ISPU_CLK_10MHz; + break; + } + + return ret; +} + +/** + * @brief ISPU irq rate selection.[set] + * + * @param ctx read / write interface definitions + * @param val ISPU_ODR_OFF, ISPU_ODR_AT_12Hz5, ISPU_ODR_AT_26Hz, ISPU_ODR_AT_52Hz, + * ISPU_ODR_AT_104Hz, ISPU_ODR_AT_208Hz, ISPU_ODR_AT_417Hz, ISPU_ODR_AT_833Hz, + * ISPU_ODR_AT_1667Hz, ISPU_ODR_AT_3333Hz, ISPU_ODR_AT_6667Hz + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_ispu_data_rate_set(stmdev_ctx_t *ctx, + ism330is_ispu_data_rate_t val) +{ + ism330is_ctrl9_c_t ctrl9_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1); + + if (ret == 0) + { + ctrl9_c.ispu_rate = ((uint8_t)val & 0xfU); + ret = ism330is_write_reg(ctx, ISM330IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1); + } + + return ret; +} + +/** + * @brief ISPU irq rate selection.[get] + * + * @param ctx read / write interface definitions + * @param val ISPU_ODR_OFF, ISPU_ODR_AT_12Hz5, ISPU_ODR_AT_26Hz, ISPU_ODR_AT_52Hz, + * ISPU_ODR_AT_104Hz, ISPU_ODR_AT_208Hz, ISPU_ODR_AT_417Hz, ISPU_ODR_AT_833Hz, + * ISPU_ODR_AT_1667Hz, ISPU_ODR_AT_3333Hz, ISPU_ODR_AT_6667Hz + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_ispu_data_rate_get(stmdev_ctx_t *ctx, + ism330is_ispu_data_rate_t *val) +{ + ism330is_ctrl9_c_t ctrl9_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1); + + switch ((ctrl9_c.ispu_rate)) + { + case ISM330IS_ISPU_ODR_OFF: + *val = ISM330IS_ISPU_ODR_OFF; + break; + + case ISM330IS_ISPU_ODR_AT_12Hz5: + *val = ISM330IS_ISPU_ODR_AT_12Hz5; + break; + + case ISM330IS_ISPU_ODR_AT_26Hz: + *val = ISM330IS_ISPU_ODR_AT_26Hz; + break; + + case ISM330IS_ISPU_ODR_AT_52Hz: + *val = ISM330IS_ISPU_ODR_AT_52Hz; + break; + + case ISM330IS_ISPU_ODR_AT_104Hz: + *val = ISM330IS_ISPU_ODR_AT_104Hz; + break; + + case ISM330IS_ISPU_ODR_AT_208Hz: + *val = ISM330IS_ISPU_ODR_AT_208Hz; + break; + + case ISM330IS_ISPU_ODR_AT_416Hz: + *val = ISM330IS_ISPU_ODR_AT_416Hz; + break; + + case ISM330IS_ISPU_ODR_AT_833Hz: + *val = ISM330IS_ISPU_ODR_AT_833Hz; + break; + + case ISM330IS_ISPU_ODR_AT_1667Hz: + *val = ISM330IS_ISPU_ODR_AT_1667Hz; + break; + + case ISM330IS_ISPU_ODR_AT_3333Hz: + *val = ISM330IS_ISPU_ODR_AT_3333Hz; + break; + + case ISM330IS_ISPU_ODR_AT_6667Hz: + *val = ISM330IS_ISPU_ODR_AT_6667Hz; + break; + + default: + *val = ISM330IS_ISPU_ODR_OFF; + break; + } + return ret; +} + +/** + * @brief ISPU bdu selection.[set] + * + * @param ctx read / write interface definitions + * @param val ISPU_BDU_OFF, ISPU_BDU_ON_2B_4B, ISPU_BDU_ON_2B_2B, ISPU_BDU_ON_4B_4B, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_ispu_bdu_set(stmdev_ctx_t *ctx, ism330is_ispu_bdu_t val) +{ + ism330is_ctrl9_c_t ctrl9_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1); + + if (ret == 0) + { + ctrl9_c.ispu_bdu = ((uint8_t)val & 0x3U); + ret = ism330is_write_reg(ctx, ISM330IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1); + } + + return ret; +} + +/** + * @brief ISPU bdu selection.[get] + * + * @param ctx read / write interface definitions + * @param val ISPU_BDU_OFF, ISPU_BDU_ON_2B_4B, ISPU_BDU_ON_2B_2B, ISPU_BDU_ON_4B_4B, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_ispu_bdu_get(stmdev_ctx_t *ctx, ism330is_ispu_bdu_t *val) +{ + ism330is_ctrl9_c_t ctrl9_c; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1); + + switch ((ctrl9_c.ispu_rate)) + { + case ISM330IS_ISPU_BDU_OFF: + *val = ISM330IS_ISPU_BDU_OFF; + break; + + case ISM330IS_ISPU_BDU_ON_2B_4B: + *val = ISM330IS_ISPU_BDU_ON_2B_4B; + break; + + case ISM330IS_ISPU_BDU_ON_2B_2B: + *val = ISM330IS_ISPU_BDU_ON_2B_2B; + break; + + case ISM330IS_ISPU_BDU_ON_4B_4B: + *val = ISM330IS_ISPU_BDU_ON_4B_4B; + break; + + default: + *val = ISM330IS_ISPU_BDU_OFF; + break; + } + return ret; +} + +/** + * @brief Generic Interrupt Flags from ISPU.[get] + * + * @param ctx read / write interface definitions + * @param val Generic Interrupt Flags from ISPU. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_ia_ispu_get(stmdev_ctx_t *ctx, uint32_t *val) +{ + uint8_t buff[4]; + int32_t ret; + + ret = ism330is_read_reg(ctx, ISM330IS_ISPU_INT_STATUS0_MAINPAGE, &buff[0], 4); + + *val = (uint32_t)buff[3]; + *val = (*val * 256U) + (uint32_t)buff[2]; + *val = (*val * 256U) + (uint32_t)buff[1]; + *val = (*val * 256U) + (uint32_t)buff[0]; + + return ret; +} + +/** + * @brief General purpose input configuration register for ISPU[set] + * + * @param ctx read / write interface definitions + * @param offset offset from ISPU_DUMMY_CFG_1 register + * @param val General purpose input configuration register for ISPU + * @param len number of bytes to write + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_ispu_write_dummy_cfg(stmdev_ctx_t *ctx, uint8_t offset, + uint8_t *val, uint8_t len) +{ + int32_t ret; + + /* check if we are writing outside of the range */ + if (ISM330IS_ISPU_DUMMY_CFG_1_L + offset + len > ISM330IS_ISPU_DUMMY_CFG_4_H) + { + return -1; + } + + ret = ism330is_write_reg(ctx, ISM330IS_ISPU_DUMMY_CFG_1_L + offset, val, len); + + return ret; +} + +/** + * @brief General purpose input configuration register for ISPU[set] + * + * @param ctx read / write interface definitions + * @param offset offset from ISPU_DUMMY_CFG_1 register + * @param val General purpose input configuration register for ISPU + * @param len number of bytes to write + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_ispu_ready_dummy_cfg(stmdev_ctx_t *ctx, uint8_t offset, + uint8_t *val, uint8_t len) +{ + int32_t ret; + + /* check if we are reading outside of the range */ + if (ISM330IS_ISPU_DUMMY_CFG_1_L + offset + len > ISM330IS_ISPU_DUMMY_CFG_4_H) + { + return -1; + } + + ret = ism330is_read_reg(ctx, ISM330IS_ISPU_DUMMY_CFG_1_L + offset, val, len); + + return ret; +} + +/** + * @brief Boot ISPU core[set] + * + * @param ctx read / write interface definitions + * @param val Boot ISPU core + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_ispu_boot_set(stmdev_ctx_t *ctx, + ism330is_ispu_boot_latched_t val) +{ + ism330is_ispu_config_t ispu_config; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK); + + if (ret == 0) + { + ret += ism330is_read_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1); + } + + if (ret == 0) + { + ispu_config.ispu_rst_n = (uint8_t)val; + ispu_config.clk_dis = (uint8_t)val; + ret += ism330is_write_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_config, + 1); + } + + ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Boot ISPU core[get] + * + * @param ctx read / write interface definitions + * @param val Boot ISPU core + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_ispu_boot_get(stmdev_ctx_t *ctx, + ism330is_ispu_boot_latched_t *val) +{ + ism330is_ispu_config_t ispu_config; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK); + + if (ret == 0) + { + ret += ism330is_read_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1); + } + + *val = ISM330IS_ISPU_TURN_OFF; + if (ispu_config.ispu_rst_n == 1U || ispu_config.clk_dis == 1U) + { + *val = ISM330IS_ISPU_TURN_ON; + } + + ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enables latched ISPU interrupt.[set] + * + * @param ctx read / write interface definitions + * @param val ISPU_INT_PULSED, ISPU_INT_LATCHED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_ispu_int_latched_set(stmdev_ctx_t *ctx, + ism330is_ispu_int_latched_t val) +{ + ism330is_ispu_config_t ispu_config; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK); + + if (ret == 0) + { + ret += ism330is_read_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1); + } + + if (ret == 0) + { + ispu_config.latched = ((uint8_t)val & 0x1U); + ret += ism330is_write_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_config, + 1); + } + + ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enables latched ISPU interrupt.[get] + * + * @param ctx read / write interface definitions + * @param val ISPU_INT_PULSED, ISPU_INT_LATCHED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_ispu_int_latched_get(stmdev_ctx_t *ctx, + ism330is_ispu_int_latched_t *val) +{ + ism330is_ispu_config_t ispu_config; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK); + + if (ret == 0) + { + ret += ism330is_read_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1); + } + + ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + + switch ((ispu_config.latched)) + { + case ISM330IS_ISPU_INT_PULSED: + *val = ISM330IS_ISPU_INT_PULSED; + break; + + case ISM330IS_ISPU_INT_LATCHED: + *val = ISM330IS_ISPU_INT_LATCHED; + break; + + default: + *val = ISM330IS_ISPU_INT_PULSED; + break; + } + return ret; +} + +/** + * @brief returns ISPU boot status + * + * @param ctx read / write interface definitions + * @param val ISM330IS_ISPU_BOOT_IN_PROGRESS, ISM330IS_ISPU_BOOT_ENDED + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_ispu_get_boot_status(stmdev_ctx_t *ctx, + ism330is_ispu_boot_end_t *val) +{ + ism330is_ispu_status_t ispu_boot_status; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK); + if (ret == 0) + { + ret += ism330is_read_reg(ctx, ISM330IS_ISPU_STATUS, + (uint8_t *)&ispu_boot_status, 1); + *val = (ism330is_ispu_boot_end_t)ispu_boot_status.boot_end; + ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + } + + return ret; +} + +static int32_t ism330is_ispu_sel_memory_addr(stmdev_ctx_t *ctx, uint16_t mem_addr) +{ + uint8_t mem_addr_l, mem_addr_h; + int32_t ret = 0; + + mem_addr_l = (uint8_t)(mem_addr & 0xFFU); + mem_addr_h = (uint8_t)(mem_addr / 256U); + ret += ism330is_write_reg(ctx, ISM330IS_ISPU_MEM_ADDR1, + (uint8_t *)&mem_addr_h, 1); + ret += ism330is_write_reg(ctx, ISM330IS_ISPU_MEM_ADDR0, + (uint8_t *)&mem_addr_l, 1); + + return ret; +} + +/** + * @brief ISPU write memory + * + * @param ctx read / write interface definitions + * @param mem_sel ISM330IS_ISPU_DATA_RAM_MEMORY, ISM330IS_ISPU_PROGRAM_RAM_MEMORY + * @param mem_addr memory address + * @param mem_data memory data + * @param len data length + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_ispu_write_memory(stmdev_ctx_t *ctx, + ism330is_ispu_memory_type_t mem_sel, + uint16_t mem_addr, uint8_t *mem_data, uint16_t len) +{ + ism330is_ispu_mem_sel_t ispu_mem_sel; + int32_t ret; + uint16_t i; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK); + if (ret == 0) + { + /* select memory to be written */ + ispu_mem_sel.read_mem_en = 0; + ispu_mem_sel.mem_sel = (uint8_t)mem_sel; + ret = ism330is_write_reg(ctx, ISM330IS_ISPU_MEM_SEL, (uint8_t *)&ispu_mem_sel, 1); + + if (mem_sel == ISM330IS_ISPU_PROGRAM_RAM_MEMORY) + { + uint16_t addr_s[4] = {0U, 0U, 0U, 0U}; + uint16_t len_s[4] = {0U, 0U, 0U, 0U}; + uint8_t j = 0; + uint16_t k; + + addr_s[0] = mem_addr; + for (i = 0, k = 0; i < len; i++, k++) + { + if ((mem_addr + i == 0x2000U) || (mem_addr + i == 0x4000U) || (mem_addr + i == 0x6000U)) + { + len_s[j++] = k; + addr_s[j] = mem_addr + i; + k = 0; + } + } + len_s[j++] = k; + + for (i = 0, k = 0; i < j; k+=len_s[i], i++) + { + ret += ism330is_ispu_sel_memory_addr(ctx, addr_s[i]); + ret += ism330is_write_reg(ctx, ISM330IS_ISPU_MEM_DATA, &mem_data[k], len_s[i]); + } + } else { + /* select memory address */ + ret += ism330is_ispu_sel_memory_addr(ctx, mem_addr); + ret += ism330is_write_reg(ctx, ISM330IS_ISPU_MEM_DATA, &mem_data[0], len); + } + } + + ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief ISPU read memory + * + * @param ctx read / write interface definitions + * @param mem_sel ISM330IS_ISPU_DATA_RAM_MEMORY, ISM330IS_ISPU_PROGRAM_RAM_MEMORY + * @param mem_addr memory address + * @param mem_data memory data + * @param len data length + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_ispu_read_memory(stmdev_ctx_t *ctx, + ism330is_ispu_memory_type_t mem_sel, + uint16_t mem_addr, uint8_t *mem_data, uint16_t len) +{ + ism330is_ispu_mem_sel_t ispu_mem_sel; + int32_t ret; + uint8_t dummy; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK); + if (ret == 0) + { + /* select memory to be read */ + ispu_mem_sel.read_mem_en = 1; + ispu_mem_sel.mem_sel = (uint8_t)mem_sel; + ret = ism330is_write_reg(ctx, ISM330IS_ISPU_MEM_SEL, (uint8_t *)&ispu_mem_sel, 1); + + /* select memory address */ + ret += ism330is_ispu_sel_memory_addr(ctx, mem_addr); + ret += ism330is_read_reg(ctx, ISM330IS_ISPU_MEM_DATA, &dummy, 1); + + ret += ism330is_read_reg(ctx, ISM330IS_ISPU_MEM_DATA, &mem_data[0], len); + } + + ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief ISPU write flags (IF2S) + * + * @param ctx read / write interface definitions + * @param data ISPU flags + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_ispu_write_flags(stmdev_ctx_t *ctx, uint16_t data) +{ + ism330is_ispu_if2s_flag_l_t flag_l; + ism330is_ispu_if2s_flag_h_t flag_h; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK); + if (ret == 0) + { + /* write the flags */ + flag_h.if2s = (uint8_t)(data / 256U); + ret += ism330is_write_reg(ctx, ISM330IS_ISPU_IF2S_FLAG_H, (uint8_t *)&flag_h, + 1); + flag_l.if2s = (uint8_t)(data & 0xffU); + ret += ism330is_write_reg(ctx, ISM330IS_ISPU_IF2S_FLAG_L, (uint8_t *)&flag_l, + 1); + } + + ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief ISPU read flags (S2IF) + * + * @param ctx read / write interface definitions + * @param data ISPU flags + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_ispu_read_flags(stmdev_ctx_t *ctx, uint16_t *data) +{ + uint8_t buff[2]; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK); + if (ret == 0) + { + /* read the flags */ + ret += ism330is_read_reg(ctx, ISM330IS_ISPU_S2IF_FLAG_L, buff, 2); + data[0] = (uint16_t)buff[1]; + data[0] = (data[0] * 256U) + (uint16_t)buff[0]; + } + + ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief ISPU clear flags (S2IF) + * + * @param ctx read / write interface definitions + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_ispu_clear_flags(stmdev_ctx_t *ctx) +{ + uint8_t data = 1; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK); + + if (ret == 0) + { + ret += ism330is_write_reg(ctx, ISM330IS_ISPU_S2IF_FLAG_H, &data, 1); + ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief ISPU DOUT registers.[get] + * + * @param ctx read / write interface definitions + * @param val ISPU DOUT output registers. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_ispu_read_data_raw_get(stmdev_ctx_t *ctx, + uint8_t *val, + uint8_t len) +{ + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK); + if (ret == 0) + { + ret += ism330is_read_reg(ctx, ISM330IS_ISPU_DOUT_00_L, (uint8_t *) val, + len); + } + + ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief ISPU int1_ctrl.[get] + * + * @param ctx read / write interface definitions + * @param val ISPU int1_ctrl register value + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_ispu_int1_ctrl_get(stmdev_ctx_t *ctx, uint32_t *val) +{ + uint8_t buff[4]; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK); + if (ret == 0) + { + /* read int1_ctrl reg */ + ret += ism330is_read_reg(ctx, ISM330IS_ISPU_INT1_CTRL0, &buff[0], 4); + + *val = (uint32_t)buff[3]; + *val = (*val * 256U) + (uint32_t)buff[2]; + *val = (*val * 256U) + (uint32_t)buff[1]; + *val = (*val * 256U) + (uint32_t)buff[0]; + } + + ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief ISPU int1_ctrl.[set] + * + * @param ctx read / write interface definitions + * @param val ISPU int1_ctrl register value + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_ispu_int1_ctrl_set(stmdev_ctx_t *ctx, uint32_t val) +{ + ism330is_ispu_int1_ctrl0_t int1_ctrl0; + ism330is_ispu_int1_ctrl1_t int1_ctrl1; + ism330is_ispu_int1_ctrl2_t int1_ctrl2; + ism330is_ispu_int1_ctrl3_t int1_ctrl3; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK); + if (ret == 0) + { + /* write the int1_ctrl reg */ + int1_ctrl3.ispu_int1_ctrl = (uint8_t)((val >> 24) & 0xffU); + ret += ism330is_write_reg(ctx, ISM330IS_ISPU_INT1_CTRL3, (uint8_t *)&int1_ctrl3, + 1); + + int1_ctrl2.ispu_int1_ctrl = (uint8_t)((val >> 16) & 0xffU); + ret += ism330is_write_reg(ctx, ISM330IS_ISPU_INT1_CTRL2, (uint8_t *)&int1_ctrl2, + 1); + + int1_ctrl1.ispu_int1_ctrl = (uint8_t)((val >> 8) & 0xffU); + ret += ism330is_write_reg(ctx, ISM330IS_ISPU_INT1_CTRL1, (uint8_t *)&int1_ctrl1, + 1); + + int1_ctrl0.ispu_int1_ctrl = (uint8_t)(val & 0xffU); + ret += ism330is_write_reg(ctx, ISM330IS_ISPU_INT1_CTRL0, (uint8_t *)&int1_ctrl0, + 1); + } + + ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief ISPU int2_ctrl.[get] + * + * @param ctx read / write interface definitions + * @param val ISPU int2_ctrl register value + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_ispu_int2_ctrl_get(stmdev_ctx_t *ctx, uint32_t *val) +{ + uint8_t buff[4]; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK); + if (ret == 0) + { + /* read int2_ctrl reg */ + ret += ism330is_read_reg(ctx, ISM330IS_ISPU_INT2_CTRL0, &buff[0], 4); + + *val = (uint32_t)buff[3]; + *val = (*val * 256U) + (uint32_t)buff[2]; + *val = (*val * 256U) + (uint32_t)buff[1]; + *val = (*val * 256U) + (uint32_t)buff[0]; + } + + ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief ISPU int2_ctrl.[set] + * + * @param ctx read / write interface definitions + * @param val ISPU int2_ctrl register value + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_ispu_int2_ctrl_set(stmdev_ctx_t *ctx, uint32_t val) +{ + ism330is_ispu_int2_ctrl0_t int2_ctrl0; + ism330is_ispu_int2_ctrl1_t int2_ctrl1; + ism330is_ispu_int2_ctrl2_t int2_ctrl2; + ism330is_ispu_int2_ctrl3_t int2_ctrl3; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK); + if (ret == 0) + { + /* write the int2_ctrl reg */ + int2_ctrl3.ispu_int2_ctrl = (uint8_t)((val >> 24) & 0xffU); + ret += ism330is_write_reg(ctx, ISM330IS_ISPU_INT2_CTRL3, (uint8_t *)&int2_ctrl3, + 1); + + int2_ctrl2.ispu_int2_ctrl = (uint8_t)((val >> 16) & 0xffU); + ret += ism330is_write_reg(ctx, ISM330IS_ISPU_INT2_CTRL2, (uint8_t *)&int2_ctrl2, + 1); + + int2_ctrl1.ispu_int2_ctrl = (uint8_t)((val >> 8) & 0xffU); + ret += ism330is_write_reg(ctx, ISM330IS_ISPU_INT2_CTRL1, (uint8_t *)&int2_ctrl1, + 1); + + int2_ctrl0.ispu_int2_ctrl = (uint8_t)(val & 0xffU); + ret += ism330is_write_reg(ctx, ISM330IS_ISPU_INT2_CTRL0, (uint8_t *)&int2_ctrl0, + 1); + } + + ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief ISPU int_status.[get] + * + * @param ctx read / write interface definitions + * @param val ISPU int2_status register value + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_ispu_int_status_get(stmdev_ctx_t *ctx, uint32_t *val) +{ + uint8_t buff[4]; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK); + if (ret == 0) + { + /* read int2_ctrl reg */ + ret += ism330is_read_reg(ctx, ISM330IS_ISPU_INT_STATUS0, &buff[0], 4); + + *val = (uint32_t)buff[3]; + *val = (*val * 256U) + (uint32_t)buff[2]; + *val = (*val * 256U) + (uint32_t)buff[1]; + *val = (*val * 256U) + (uint32_t)buff[0]; + } + + ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief ISPU algo.[get] + * + * @param ctx read / write interface definitions + * @param val ISPU algo register value + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_ispu_algo_get(stmdev_ctx_t *ctx, uint32_t *val) +{ + uint8_t buff[4]; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK); + if (ret == 0) + { + /* read int2_ctrl reg */ + ret += ism330is_read_reg(ctx, ISM330IS_ISPU_ALGO0, &buff[0], 4); + + *val = (uint32_t)buff[3]; + *val = (*val * 256U) + (uint32_t)buff[2]; + *val = (*val * 256U) + (uint32_t)buff[1]; + *val = (*val * 256U) + (uint32_t)buff[0]; + } + + ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief ISPU algo.[set] + * + * @param ctx read / write interface definitions + * @param val ISPU algo register value + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330is_ispu_algo_set(stmdev_ctx_t *ctx, uint32_t val) +{ + ism330is_ispu_algo0_t algo0; + ism330is_ispu_algo1_t algo1; + ism330is_ispu_algo2_t algo2; + ism330is_ispu_algo3_t algo3; + int32_t ret; + + ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK); + if (ret == 0) + { + /* write the algo reg */ + algo3.ispu_algo = (uint8_t)((val >> 24) & 0xffU); + ret += ism330is_write_reg(ctx, ISM330IS_ISPU_ALGO3, (uint8_t *)&algo3, 1); + + algo2.ispu_algo = (uint8_t)((val >> 16) & 0xffU); + ret += ism330is_write_reg(ctx, ISM330IS_ISPU_ALGO2, (uint8_t *)&algo2, 1); + + algo1.ispu_algo = (uint8_t)((val >> 8) & 0xffU); + ret += ism330is_write_reg(ctx, ISM330IS_ISPU_ALGO1, (uint8_t *)&algo1, 1); + + algo0.ispu_algo = (uint8_t)(val & 0xffU); + ret += ism330is_write_reg(ctx, ISM330IS_ISPU_ALGO0, (uint8_t *)&algo0, 1); + } + + ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ diff --git a/sensor/stmemsc/ism330is_STdC/driver/ism330is_reg.h b/sensor/stmemsc/ism330is_STdC/driver/ism330is_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..04a90b42f19cb9f87a62b0499d7cb70122041950 --- /dev/null +++ b/sensor/stmemsc/ism330is_STdC/driver/ism330is_reg.h @@ -0,0 +1,2832 @@ +/** + ****************************************************************************** + * @file ism330is_reg.h + * @author Sensors Software Solution Team + * @brief This file contains all the functions prototypes for the + * ism330is_reg.c driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2022 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef ISM330IS_REGS_H +#define ISM330IS_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include + +/** @addtogroup ISM330IS + * @{ + * + */ + +/** @defgroup Endianness definitions + * @{ + * + */ + +#ifndef DRV_BYTE_ORDER +#ifndef __BYTE_ORDER__ + +#define DRV_LITTLE_ENDIAN 1234 +#define DRV_BIG_ENDIAN 4321 + +/** if _BYTE_ORDER is not defined, choose the endianness of your architecture + * by uncommenting the define which fits your platform endianness + */ +//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN +#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN + +#else /* defined __BYTE_ORDER__ */ + +#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ +#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ +#define DRV_BYTE_ORDER __BYTE_ORDER__ + +#endif /* __BYTE_ORDER__*/ +#endif /* DRV_BYTE_ORDER */ + +/** + * @} + * + */ + +/** @defgroup STMicroelectronics sensors common types + * @{ + * + */ + +#ifndef MEMS_SHARED_TYPES +#define MEMS_SHARED_TYPES + +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} bitwise_t; + +#define PROPERTY_DISABLE (0U) +#define PROPERTY_ENABLE (1U) + +/** @addtogroup Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); +typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); + +typedef struct +{ + /** Component mandatory fields **/ + stmdev_write_ptr write_reg; + stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; + /** Customizable optional pointer **/ + void *handle; +} stmdev_ctx_t; + +/** + * @} + * + */ + +#endif /* MEMS_SHARED_TYPES */ + +#ifndef MEMS_UCF_SHARED_TYPES +#define MEMS_UCF_SHARED_TYPES + +/** @defgroup Generic address-data structure definition + * @brief This structure is useful to load a predefined configuration + * of a sensor. + * You can create a sensor configuration by your own or using + * Unico / Unicleo tools available on STMicroelectronics + * web site. + * + * @{ + * + */ + +typedef struct +{ + uint8_t address; + uint8_t data; +} ucf_line_t; + +/** + * @} + * + */ + +#endif /* MEMS_UCF_SHARED_TYPES */ + +/** + * @} + * + */ + +/** @defgroup ISM330IS_Infos + * @{ + * + */ + +/** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ +#define ISM330IS_I2C_ADD_L 0xD5U +#define ISM330IS_I2C_ADD_H 0xD7U + +/** Device Identification (Who am I) **/ +#define ISM330IS_ID 0x22U + +/** + * @} + * + */ + +/** @defgroup bitfields page main + * @{ + * + */ + +#define ISM330IS_FUNC_CFG_ACCESS 0x1U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t sw_reset_ispu : 1; + uint8_t not_used1 : 4; + uint8_t shub_reg_access : 1; + uint8_t ispu_reg_access : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_reg_access : 1; + uint8_t shub_reg_access : 1; + uint8_t not_used1 : 4; + uint8_t sw_reset_ispu : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330is_func_cfg_access_t; + +#define ISM330IS_PIN_CTRL 0x2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 6; + uint8_t sdo_pu_en : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t sdo_pu_en : 1; + uint8_t not_used0 : 6; +#endif /* DRV_BYTE_ORDER */ +} ism330is_pin_ctrl_t; + +#define ISM330IS_DRDY_PULSED_REG 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 7; + uint8_t drdy_pulsed : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t drdy_pulsed : 1; + uint8_t not_used0 : 7; +#endif /* DRV_BYTE_ORDER */ +} ism330is_drdy_pulsed_reg_t; + +#define ISM330IS_INT1_CTRL 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_drdy_xl : 1; + uint8_t int1_drdy_g : 1; + uint8_t int1_boot : 1; + uint8_t not_used0 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 5; + uint8_t int1_boot : 1; + uint8_t int1_drdy_g : 1; + uint8_t int1_drdy_xl : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330is_int1_ctrl_t; + +#define ISM330IS_INT2_CTRL 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_drdy_xl : 1; + uint8_t int2_drdy_g : 1; + uint8_t int2_drdy_temp : 1; + uint8_t not_used0 : 4; + uint8_t int2_sleep_ispu : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_sleep_ispu : 1; + uint8_t not_used0 : 4; + uint8_t int2_drdy_temp : 1; + uint8_t int2_drdy_g : 1; + uint8_t int2_drdy_xl : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330is_int2_ctrl_t; + +#define ISM330IS_WHO_AM_I 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t id : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t id : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_who_am_i_t; + +#define ISM330IS_CTRL1_XL 0x10U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t fs_xl : 2; + uint8_t odr_xl : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t odr_xl : 4; + uint8_t fs_xl : 2; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ctrl1_xl_t; + +#define ISM330IS_CTRL2_G 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t fs_125 : 1; + uint8_t fs_g : 2; + uint8_t odr_g : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t odr_g : 4; + uint8_t fs_g : 2; + uint8_t fs_125 : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ctrl2_g_t; + +#define ISM330IS_CTRL3_C 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sw_reset : 1; + uint8_t not_used0 : 1; + uint8_t if_inc : 1; + uint8_t sim : 1; + uint8_t pp_od : 1; + uint8_t h_lactive : 1; + uint8_t bdu : 1; + uint8_t boot : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t boot : 1; + uint8_t bdu : 1; + uint8_t h_lactive : 1; + uint8_t pp_od : 1; + uint8_t sim : 1; + uint8_t if_inc : 1; + uint8_t not_used0 : 1; + uint8_t sw_reset : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ctrl3_c_t; + +#define ISM330IS_CTRL4_C 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t i2c_disable : 1; + uint8_t not_used1 : 2; + uint8_t int2_on_int1 : 1; + uint8_t sleep_g : 1; + uint8_t not_used2 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used2 : 1; + uint8_t sleep_g : 1; + uint8_t int2_on_int1 : 1; + uint8_t not_used1 : 2; + uint8_t i2c_disable : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ctrl4_c_t; + +#define ISM330IS_CTRL5_C 0x14U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t st_xl : 2; + uint8_t st_g : 2; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t st_g : 2; + uint8_t st_xl : 2; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ctrl5_c_t; + +#define ISM330IS_CTRL6_C 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 4; + uint8_t xl_hm_mode : 1; + uint8_t not_used1 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 3; + uint8_t xl_hm_mode : 1; + uint8_t not_used0 : 4; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ctrl6_c_t; + +#define ISM330IS_CTRL7_G 0x16U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 7; + uint8_t g_hm_mode : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t g_hm_mode : 1; + uint8_t not_used0 : 7; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ctrl7_g_t; + +#define ISM330IS_CTRL9_C 0x18U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_bdu : 2; + uint8_t not_used0 : 2; + uint8_t ispu_rate : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_rate : 4; + uint8_t not_used0 : 2; + uint8_t ispu_bdu : 2; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ctrl9_c_t; + +#define ISM330IS_CTRL10_C 0x19U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t ispu_clk_sel : 1; + uint8_t not_used1 : 2; + uint8_t timestamp_en : 1; + uint8_t not_used2 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used2 : 2; + uint8_t timestamp_en : 1; + uint8_t not_used1 : 2; + uint8_t ispu_clk_sel : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ctrl10_c_t; + +#define ISM330IS_ISPU_INT_STATUS0_MAINPAGE 0x1AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ia_ispu : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ia_ispu : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_int_status0_mainpage_t; + +#define ISM330IS_ISPU_INT_STATUS1_MAINPAGE 0x1BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ia_ispu : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ia_ispu : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_int_status1_mainpage_t; + +#define ISM330IS_ISPU_INT_STATUS2_MAINPAGE 0x1CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ia_ispu : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ia_ispu : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_int_status2_mainpage_t; + +#define ISM330IS_ISPU_INT_STATUS3_MAINPAGE 0x1DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ia_ispu : 6; + uint8_t not_used0 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 2; + uint8_t ia_ispu : 6; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_int_status3_mainpage_t; + +#define ISM330IS_STATUS_REG 0x1EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xlda : 1; + uint8_t gda : 1; + uint8_t tda : 1; + uint8_t not_used0 : 4; + uint8_t timestamp_endcount : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp_endcount : 1; + uint8_t not_used0 : 4; + uint8_t tda : 1; + uint8_t gda : 1; + uint8_t xlda : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330is_status_reg_t; + +#define ISM330IS_OUT_TEMP_L 0x20U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t temp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t temp : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_out_temp_l_t; + +#define ISM330IS_OUT_TEMP_H 0x21U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t temp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t temp : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_out_temp_h_t; + +#define ISM330IS_OUTX_L_G 0x22U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_g : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_outx_l_g_t; + +#define ISM330IS_OUTX_H_G 0x23U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_g : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_outx_h_g_t; + +#define ISM330IS_OUTY_L_G 0x24U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_g : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_outy_l_g_t; + +#define ISM330IS_OUTY_H_G 0x25U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_g : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_outy_h_g_t; + +#define ISM330IS_OUTZ_L_G 0x26U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_g : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_outz_l_g_t; + +#define ISM330IS_OUTZ_H_G 0x27U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_g : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_outz_h_g_t; + +#define ISM330IS_OUTX_L_A 0x28U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_a : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_outx_l_a_t; + +#define ISM330IS_OUTX_H_A 0x29U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_a : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_outx_h_a_t; + +#define ISM330IS_OUTY_L_A 0x2AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_a : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_outy_l_a_t; + +#define ISM330IS_OUTY_H_A 0x2BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_a : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_outy_h_a_t; + +#define ISM330IS_OUTZ_L_A 0x2CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_a : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_outz_l_a_t; + +#define ISM330IS_OUTZ_H_A 0x2DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_a : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_outz_h_a_t; + +#define ISM330IS_STATUS_MASTER_MAINPAGE 0x39U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sens_hub_endop : 1; + uint8_t not_used0 : 2; + uint8_t slave0_nack : 1; + uint8_t slave1_nack : 1; + uint8_t slave2_nack : 1; + uint8_t slave3_nack : 1; + uint8_t wr_once_done : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t wr_once_done : 1; + uint8_t slave3_nack : 1; + uint8_t slave2_nack : 1; + uint8_t slave1_nack : 1; + uint8_t slave0_nack : 1; + uint8_t not_used0 : 2; + uint8_t sens_hub_endop : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330is_status_master_mainpage_t; + +#define ISM330IS_TIMESTAMP0 0x40U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_timestamp0_t; + +#define ISM330IS_TIMESTAMP1 0x41U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_timestamp1_t; + +#define ISM330IS_TIMESTAMP2 0x42U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_timestamp2_t; + +#define ISM330IS_TIMESTAMP3 0x43U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_timestamp3_t; + +#define ISM330IS_MD1_CFG 0x5EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_shub : 1; + uint8_t int1_ispu : 1; + uint8_t not_used0 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 6; + uint8_t int1_ispu : 1; + uint8_t int1_shub : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330is_md1_cfg_t; + +#define ISM330IS_MD2_CFG 0x5FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_timestamp : 1; + uint8_t int2_ispu : 1; + uint8_t not_used0 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 6; + uint8_t int2_ispu : 1; + uint8_t int2_timestamp : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330is_md2_cfg_t; + +#define ISM330IS_INTERNAL_FREQ_FINE 0x63U +typedef struct +{ + uint8_t freq_fine : 8; +} ism330is_internal_freq_fine_t; + +#define ISM330IS_ISPU_DUMMY_CFG_1_L 0x73U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_dummy_cfg_1 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_dummy_cfg_1 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dummy_cfg_1_l_t; + +#define ISM330IS_ISPU_DUMMY_CFG_1_H 0x74U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_dummy_cfg_1 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_dummy_cfg_1 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dummy_cfg_1_h_t; + +#define ISM330IS_ISPU_DUMMY_CFG_2_L 0x75U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_dummy_cfg_2 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_dummy_cfg_2 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dummy_cfg_2_l_t; + +#define ISM330IS_ISPU_DUMMY_CFG_2_H 0x76U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_dummy_cfg_2 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_dummy_cfg_2 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dummy_cfg_2_h_t; + +#define ISM330IS_ISPU_DUMMY_CFG_3_L 0x77U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_dummy_cfg_3 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_dummy_cfg_3 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dummy_cfg_3_l_t; + +#define ISM330IS_ISPU_DUMMY_CFG_3_H 0x78U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_dummy_cfg_3 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_dummy_cfg_3 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dummy_cfg_3_h_t; + +#define ISM330IS_ISPU_DUMMY_CFG_4_L 0x79U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_dummy_cfg_4 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_dummy_cfg_4 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dummy_cfg_4_l_t; + +#define ISM330IS_ISPU_DUMMY_CFG_4_H 0x7AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_dummy_cfg_4 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_dummy_cfg_4 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dummy_cfg_4_h_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page sensor_hub + * @{ + * + */ + +#define ISM330IS_SENSOR_HUB_1 0x2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub1 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub1 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_sensor_hub_1_t; + +#define ISM330IS_SENSOR_HUB_2 0x3U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub2 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub2 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_sensor_hub_2_t; + +#define ISM330IS_SENSOR_HUB_3 0x4U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub3 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub3 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_sensor_hub_3_t; + +#define ISM330IS_SENSOR_HUB_4 0x5U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub4 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub4 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_sensor_hub_4_t; + +#define ISM330IS_SENSOR_HUB_5 0x6U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub5 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub5 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_sensor_hub_5_t; + +#define ISM330IS_SENSOR_HUB_6 0x7U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub6 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub6 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_sensor_hub_6_t; + +#define ISM330IS_SENSOR_HUB_7 0x8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub7 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub7 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_sensor_hub_7_t; + +#define ISM330IS_SENSOR_HUB_8 0x9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub8 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub8 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_sensor_hub_8_t; + +#define ISM330IS_SENSOR_HUB_9 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub9 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub9 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_sensor_hub_9_t; + +#define ISM330IS_SENSOR_HUB_10 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub10 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub10 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_sensor_hub_10_t; + +#define ISM330IS_SENSOR_HUB_11 0x0CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub11 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub11 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_sensor_hub_11_t; + +#define ISM330IS_SENSOR_HUB_12 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub12 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub12 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_sensor_hub_12_t; + +#define ISM330IS_SENSOR_HUB_13 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub13 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub13 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_sensor_hub_13_t; + +#define ISM330IS_SENSOR_HUB_14 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub14 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub14 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_sensor_hub_14_t; + +#define ISM330IS_SENSOR_HUB_15 0x10U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub15 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub15 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_sensor_hub_15_t; + +#define ISM330IS_SENSOR_HUB_16 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub16 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub16 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_sensor_hub_16_t; + +#define ISM330IS_SENSOR_HUB_17 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub17 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub17 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_sensor_hub_17_t; + +#define ISM330IS_SENSOR_HUB_18 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub18 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub18 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_sensor_hub_18_t; + +#define ISM330IS_MASTER_CONFIG 0x14U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t aux_sens_on : 2; + uint8_t master_on : 1; + uint8_t shub_pu_en : 1; + uint8_t pass_through_mode : 1; + uint8_t start_config : 1; + uint8_t write_once : 1; + uint8_t rst_master_regs : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t rst_master_regs : 1; + uint8_t write_once : 1; + uint8_t start_config : 1; + uint8_t pass_through_mode : 1; + uint8_t shub_pu_en : 1; + uint8_t master_on : 1; + uint8_t aux_sens_on : 2; +#endif /* DRV_BYTE_ORDER */ +} ism330is_master_config_t; + +#define ISM330IS_SLV0_ADD 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t rw_0 : 1; + uint8_t slave0_add : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave0_add : 7; + uint8_t rw_0 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330is_slv0_add_t; + +#define ISM330IS_SLV0_SUBADD 0x16U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave0_reg : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave0_reg : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_slv0_subadd_t; + +#define ISM330IS_SLAVE0_CONFIG 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave0_numop : 3; + uint8_t not_used0 : 3; + uint8_t shub_odr : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t shub_odr : 2; + uint8_t not_used0 : 3; + uint8_t slave0_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} ism330is_slv0_config_t; + +#define ISM330IS_SLV1_ADD 0x18U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t r_1 : 1; + uint8_t slave1_add : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave1_add : 7; + uint8_t r_1 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330is_slv1_add_t; + +#define ISM330IS_SLV1_SUBADD 0x19U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave1_reg : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave1_reg : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_slv1_subadd_t; + +#define ISM330IS_SLAVE1_CONFIG 0x1AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave1_numop : 3; + uint8_t not_used0 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 5; + uint8_t slave1_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} ism330is_slv1_config_t; + +#define ISM330IS_SLV2_ADD 0x1BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t r_2 : 1; + uint8_t slave2_add : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave2_add : 7; + uint8_t r_2 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330is_slv2_add_t; + +#define ISM330IS_SLV2_SUBADD 0x1CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave2_reg : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave2_reg : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_slv2_subadd_t; + +#define ISM330IS_SLAVE2_CONFIG 0x1DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave2_numop : 3; + uint8_t not_used0 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 5; + uint8_t slave2_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} ism330is_slv2_config_t; + +#define ISM330IS_SLV3_ADD 0x1EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t r_3 : 1; + uint8_t slave3_add : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave3_add : 7; + uint8_t r_3 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330is_slv3_add_t; + +#define ISM330IS_SLV3_SUBADD 0x1FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave3_reg : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave3_reg : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_slv3_subadd_t; + +#define ISM330IS_SLAVE3_CONFIG 0x20U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave3_numop : 3; + uint8_t not_used0 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 5; + uint8_t slave3_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} ism330is_slv3_config_t; + +#define ISM330IS_DATAWRITE_SLV0 0x21U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave0_dataw : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave0_dataw : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_datawrite_slv0_t; + +#define ISM330IS_STATUS_MASTER 0x22U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sens_hub_endop : 1; + uint8_t not_used0 : 2; + uint8_t slave0_nack : 1; + uint8_t slave1_nack : 1; + uint8_t slave2_nack : 1; + uint8_t slave3_nack : 1; + uint8_t wr_once_done : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t wr_once_done : 1; + uint8_t slave3_nack : 1; + uint8_t slave2_nack : 1; + uint8_t slave1_nack : 1; + uint8_t slave0_nack : 1; + uint8_t not_used0 : 2; + uint8_t sens_hub_endop : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330is_status_master_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page ispu + * @{ + * + */ + +#define ISM330IS_ISPU_CONFIG 0x2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_rst_n : 1; + uint8_t clk_dis : 1; + uint8_t not_used0 : 2; + uint8_t latched : 1; + uint8_t not_used1 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 3; + uint8_t latched : 1; + uint8_t not_used0 : 2; + uint8_t clk_dis : 1; + uint8_t ispu_rst_n : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_config_t; + +#define ISM330IS_ISPU_STATUS 0x4U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t boot_end : 1; + uint8_t not_used1 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 5; + uint8_t boot_end : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_status_t; + +#define ISM330IS_ISPU_MEM_SEL 0x8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mem_sel : 1; + uint8_t not_used0 : 5; + uint8_t read_mem_en : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t read_mem_en : 1; + uint8_t not_used0 : 5; + uint8_t mem_sel : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_mem_sel_t; + +#define ISM330IS_ISPU_MEM_ADDR1 0x9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mem_addr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mem_addr : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_mem_addr1_t; + +#define ISM330IS_ISPU_MEM_ADDR0 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mem_addr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mem_addr : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_mem_addr0_t; + +#define ISM330IS_ISPU_MEM_DATA 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mem_data : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mem_data : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_mem_data_t; + +#define ISM330IS_ISPU_IF2S_FLAG_L 0x0CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t if2s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t if2s : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_if2s_flag_l_t; + +#define ISM330IS_ISPU_IF2S_FLAG_H 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t if2s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t if2s : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_if2s_flag_h_t; + +#define ISM330IS_ISPU_S2IF_FLAG_L 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t s2if : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t s2if : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_s2if_flag_l_t; + +#define ISM330IS_ISPU_S2IF_FLAG_H 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t s2if : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t s2if : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_s2if_flag_h_t; + +#define ISM330IS_ISPU_DOUT_00_L 0x10U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout0 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout0 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_00_l_t; + +#define ISM330IS_ISPU_DOUT_00_H 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout0 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout0 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_00_h_t; + +#define ISM330IS_ISPU_DOUT_01_L 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout1 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout1 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_01_l_t; + +#define ISM330IS_ISPU_DOUT_01_H 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout1 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout1 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_01_h_t; + +#define ISM330IS_ISPU_DOUT_02_L 0x14U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout2 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout2 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_02_l_t; + +#define ISM330IS_ISPU_DOUT_02_H 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout2 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout2 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_02_h_t; + +#define ISM330IS_ISPU_DOUT_03_L 0x16U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout3 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout3 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_03_l_t; + +#define ISM330IS_ISPU_DOUT_03_H 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout3 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout3 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_03_h_t; + +#define ISM330IS_ISPU_DOUT_04_L 0x18U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout4 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout4 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_04_l_t; + +#define ISM330IS_ISPU_DOUT_04_H 0x19U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout4 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout4 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_04_h_t; + +#define ISM330IS_ISPU_DOUT_05_L 0x1AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout5 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout5 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_05_l_t; + +#define ISM330IS_ISPU_DOUT_05_H 0x1BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout5 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout5 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_05_h_t; + +#define ISM330IS_ISPU_DOUT_06_L 0x1CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout6 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout6 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_06_l_t; + +#define ISM330IS_ISPU_DOUT_06_H 0x1DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout6 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout6 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_06_h_t; + +#define ISM330IS_ISPU_DOUT_07_L 0x1EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout7 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout7 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_07_l_t; + +#define ISM330IS_ISPU_DOUT_07_H 0x1FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout7 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout7 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_07_h_t; + +#define ISM330IS_ISPU_DOUT_08_L 0x20U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout8 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout8 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_08_l_t; + +#define ISM330IS_ISPU_DOUT_08_H 0x21U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout8 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout8 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_08_h_t; + +#define ISM330IS_ISPU_DOUT_09_L 0x22U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout9 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout9 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_09_l_t; + +#define ISM330IS_ISPU_DOUT_09_H 0x23U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout9 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout9 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_09_h_t; + +#define ISM330IS_ISPU_DOUT_10_L 0x24U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout10 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout10 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_10_l_t; + +#define ISM330IS_ISPU_DOUT_10_H 0x25U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout10 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout10 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_10_h_t; + +#define ISM330IS_ISPU_DOUT_11_L 0x26U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout11 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout11 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_11_l_t; + +#define ISM330IS_ISPU_DOUT_11_H 0x27U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout11 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout11 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_11_h_t; + +#define ISM330IS_ISPU_DOUT_12_L 0x28U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout12 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout12 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_12_l_t; + +#define ISM330IS_ISPU_DOUT_12_H 0x29U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout12 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout12 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_12_h_t; + +#define ISM330IS_ISPU_DOUT_13_L 0x2AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout13 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout13 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_13_l_t; + +#define ISM330IS_ISPU_DOUT_13_H 0x2BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout13 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout13 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_13_h_t; + +#define ISM330IS_ISPU_DOUT_14_L 0x2CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout14 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout14 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_14_l_t; + +#define ISM330IS_ISPU_DOUT_14_H 0x2DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout14 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout14 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_14_h_t; + +#define ISM330IS_ISPU_DOUT_15_L 0x2EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout15 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout15 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_15_l_t; + +#define ISM330IS_ISPU_DOUT_15_H 0x2FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout15 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout15 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_15_h_t; + +#define ISM330IS_ISPU_DOUT_16_L 0x30U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout16 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout16 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_16_l_t; + +#define ISM330IS_ISPU_DOUT_16_H 0x31U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout16 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout16 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_16_h_t; + +#define ISM330IS_ISPU_DOUT_17_L 0x32U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout17 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout17 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_17_l_t; + +#define ISM330IS_ISPU_DOUT_17_H 0x33U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout17 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout17 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_17_h_t; + +#define ISM330IS_ISPU_DOUT_18_L 0x34U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout18 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout18 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_18_l_t; + +#define ISM330IS_ISPU_DOUT_18_H 0x35U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout18 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout18 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_18_h_t; + +#define ISM330IS_ISPU_DOUT_19_L 0x36U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout19 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout19 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_19_l_t; + +#define ISM330IS_ISPU_DOUT_19_H 0x37U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout19 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout19 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_19_h_t; + +#define ISM330IS_ISPU_DOUT_20_L 0x38U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout20 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout20 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_20_l_t; + +#define ISM330IS_ISPU_DOUT_20_H 0x39U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout20 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout20 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_20_h_t; + +#define ISM330IS_ISPU_DOUT_21_L 0x3AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout21 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout21 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_21_l_t; + +#define ISM330IS_ISPU_DOUT_21_H 0x3BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout21 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout21 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_21_h_t; + +#define ISM330IS_ISPU_DOUT_22_L 0x3CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout22 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout22 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_22_l_t; + +#define ISM330IS_ISPU_DOUT_22_H 0x3DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout22 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout22 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_22_h_t; + +#define ISM330IS_ISPU_DOUT_23_L 0x3EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout23 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout23 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_23_l_t; + +#define ISM330IS_ISPU_DOUT_23_H 0x3FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout23 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout23 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_23_h_t; + +#define ISM330IS_ISPU_DOUT_24_L 0x40U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout24 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout24 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_24_l_t; + +#define ISM330IS_ISPU_DOUT_24_H 0x41U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout24 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout24 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_24_h_t; + +#define ISM330IS_ISPU_DOUT_25_L 0x42U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout25 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout25 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_25_l_t; + +#define ISM330IS_ISPU_DOUT_25_H 0x43U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout25 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout25 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_25_h_t; + +#define ISM330IS_ISPU_DOUT_26_L 0x44U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout26 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout26 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_26_l_t; + +#define ISM330IS_ISPU_DOUT_26_H 0x45U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout26 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout26 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_26_h_t; + +#define ISM330IS_ISPU_DOUT_27_L 0x46U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout27 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout27 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_27_l_t; + +#define ISM330IS_ISPU_DOUT_27_H 0x47U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout27 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout27 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_27_h_t; + +#define ISM330IS_ISPU_DOUT_28_L 0x48U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout28 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout28 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_28_l_t; + +#define ISM330IS_ISPU_DOUT_28_H 0x49U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout28 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout28 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_28_h_t; + +#define ISM330IS_ISPU_DOUT_29_L 0x4AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout29 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout29 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_29_l_t; + +#define ISM330IS_ISPU_DOUT_29_H 0x4BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout29 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout29 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_29_h_t; + +#define ISM330IS_ISPU_DOUT_30_L 0x4CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout30 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout30 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_30_l_t; + +#define ISM330IS_ISPU_DOUT_30_H 0x4DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout30 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout30 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_30_h_t; + +#define ISM330IS_ISPU_DOUT_31_L 0x4EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout31 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout31 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_31_l_t; + +#define ISM330IS_ISPU_DOUT_31_H 0x4FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout31 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout31 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_dout_31_h_t; + +#define ISM330IS_ISPU_INT1_CTRL0 0x50U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_int1_ctrl : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_int1_ctrl : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_int1_ctrl0_t; + +#define ISM330IS_ISPU_INT1_CTRL1 0x51U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_int1_ctrl : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_int1_ctrl : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_int1_ctrl1_t; + +#define ISM330IS_ISPU_INT1_CTRL2 0x52U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_int1_ctrl : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_int1_ctrl : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_int1_ctrl2_t; + +#define ISM330IS_ISPU_INT1_CTRL3 0x53U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_int1_ctrl : 6; + uint8_t not_used0 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 2; + uint8_t ispu_int1_ctrl : 6; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_int1_ctrl3_t; + +#define ISM330IS_ISPU_INT2_CTRL0 0x54U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_int2_ctrl : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_int2_ctrl : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_int2_ctrl0_t; + +#define ISM330IS_ISPU_INT2_CTRL1 0x55U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_int2_ctrl : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_int2_ctrl : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_int2_ctrl1_t; + +#define ISM330IS_ISPU_INT2_CTRL2 0x56U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_int2_ctrl : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_int2_ctrl : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_int2_ctrl2_t; + +#define ISM330IS_ISPU_INT2_CTRL3 0x57U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_int2_ctrl : 6; + uint8_t not_used0 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 2; + uint8_t ispu_int2_ctrl : 6; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_int2_ctrl3_t; + +#define ISM330IS_ISPU_INT_STATUS0 0x58U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_int_status : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_int_status : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_int_status0_t; + +#define ISM330IS_ISPU_INT_STATUS1 0x59U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_int_status : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_int_status : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_int_status1_t; + +#define ISM330IS_ISPU_INT_STATUS2 0x5AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_int_status : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_int_status : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_int_status2_t; + +#define ISM330IS_ISPU_INT_STATUS3 0x5BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_int_status : 6; + uint8_t not_used0 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 2; + uint8_t ispu_int_status : 6; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_int_status3_t; + +#define ISM330IS_ISPU_ALGO0 0x70U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_algo : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_algo : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_algo0_t; + +#define ISM330IS_ISPU_ALGO1 0x71U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_algo : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_algo : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_algo1_t; + +#define ISM330IS_ISPU_ALGO2 0x72U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_algo : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_algo : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_algo2_t; + +#define ISM330IS_ISPU_ALGO3 0x73U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_algo : 6; + uint8_t not_used0 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 2; + uint8_t ispu_algo : 6; +#endif /* DRV_BYTE_ORDER */ +} ism330is_ispu_algo3_t; + +/** + * @} + * + */ + +typedef union +{ + ism330is_func_cfg_access_t func_cfg_access; + ism330is_pin_ctrl_t pin_ctrl; + ism330is_drdy_pulsed_reg_t drdy_pulsed_reg; + ism330is_int1_ctrl_t int1_ctrl; + ism330is_int2_ctrl_t int2_ctrl; + ism330is_who_am_i_t who_am_i; + ism330is_ctrl1_xl_t ctrl1_xl; + ism330is_ctrl2_g_t ctrl2_g; + ism330is_ctrl3_c_t ctrl3_c; + ism330is_ctrl4_c_t ctrl4_c; + ism330is_ctrl5_c_t ctrl5_c; + ism330is_ctrl6_c_t ctrl6_c; + ism330is_ctrl7_g_t ctrl7_g; + ism330is_ctrl9_c_t ctrl9_c; + ism330is_ctrl10_c_t ctrl10_c; + ism330is_ispu_int_status0_mainpage_t ispu_int_status0_mainpage; + ism330is_ispu_int_status1_mainpage_t ispu_int_status1_mainpage; + ism330is_ispu_int_status2_mainpage_t ispu_int_status2_mainpage; + ism330is_ispu_int_status3_mainpage_t ispu_int_status3_mainpage; + ism330is_status_reg_t status_reg; + ism330is_out_temp_l_t out_temp_l; + ism330is_out_temp_h_t out_temp_h; + ism330is_outx_l_g_t outx_l_g; + ism330is_outx_h_g_t outx_h_g; + ism330is_outy_l_g_t outy_l_g; + ism330is_outy_h_g_t outy_h_g; + ism330is_outz_l_g_t outz_l_g; + ism330is_outz_h_g_t outz_h_g; + ism330is_outx_l_a_t outx_l_a; + ism330is_outx_h_a_t outx_h_a; + ism330is_outy_l_a_t outy_l_a; + ism330is_outy_h_a_t outy_h_a; + ism330is_outz_l_a_t outz_l_a; + ism330is_outz_h_a_t outz_h_a; + ism330is_status_master_mainpage_t status_master_mainpage; + ism330is_timestamp0_t timestamp0; + ism330is_timestamp1_t timestamp1; + ism330is_timestamp2_t timestamp2; + ism330is_timestamp3_t timestamp3; + ism330is_md1_cfg_t md1_cfg; + ism330is_md2_cfg_t md2_cfg; + ism330is_internal_freq_fine_t internal_freq_fine; + ism330is_ispu_dummy_cfg_1_l_t ispu_dummy_cfg_1_l; + ism330is_ispu_dummy_cfg_1_h_t ispu_dummy_cfg_1_h; + ism330is_ispu_dummy_cfg_2_l_t ispu_dummy_cfg_2_l; + ism330is_ispu_dummy_cfg_2_h_t ispu_dummy_cfg_2_h; + ism330is_ispu_dummy_cfg_3_l_t ispu_dummy_cfg_3_l; + ism330is_ispu_dummy_cfg_3_h_t ispu_dummy_cfg_3_h; + ism330is_ispu_dummy_cfg_4_l_t ispu_dummy_cfg_4_l; + ism330is_ispu_dummy_cfg_4_h_t ispu_dummy_cfg_4_h; + ism330is_sensor_hub_1_t sensor_hub_1; + ism330is_sensor_hub_2_t sensor_hub_2; + ism330is_sensor_hub_3_t sensor_hub_3; + ism330is_sensor_hub_4_t sensor_hub_4; + ism330is_sensor_hub_5_t sensor_hub_5; + ism330is_sensor_hub_6_t sensor_hub_6; + ism330is_sensor_hub_7_t sensor_hub_7; + ism330is_sensor_hub_8_t sensor_hub_8; + ism330is_sensor_hub_9_t sensor_hub_9; + ism330is_sensor_hub_10_t sensor_hub_10; + ism330is_sensor_hub_11_t sensor_hub_11; + ism330is_sensor_hub_12_t sensor_hub_12; + ism330is_sensor_hub_13_t sensor_hub_13; + ism330is_sensor_hub_14_t sensor_hub_14; + ism330is_sensor_hub_15_t sensor_hub_15; + ism330is_sensor_hub_16_t sensor_hub_16; + ism330is_sensor_hub_17_t sensor_hub_17; + ism330is_sensor_hub_18_t sensor_hub_18; + ism330is_master_config_t master_config; + ism330is_slv0_add_t slv0_add; + ism330is_slv0_subadd_t slv0_subadd; + ism330is_slv0_config_t slv0_config; + ism330is_slv1_add_t slv1_add; + ism330is_slv1_subadd_t slv1_subadd; + ism330is_slv1_config_t slv1_config; + ism330is_slv2_add_t slv2_add; + ism330is_slv2_subadd_t slv2_subadd; + ism330is_slv2_config_t slv2_config; + ism330is_slv3_add_t slv3_add; + ism330is_slv3_subadd_t slv3_subadd; + ism330is_slv3_config_t slv3_config; + ism330is_datawrite_slv0_t datawrite_slv0; + ism330is_status_master_t status_master; + ism330is_ispu_config_t ispu_config; + ism330is_ispu_status_t ispu_status; + ism330is_ispu_mem_sel_t ispu_mem_sel; + ism330is_ispu_mem_addr1_t ispu_mem_addr1; + ism330is_ispu_mem_addr0_t ispu_mem_addr0; + ism330is_ispu_mem_data_t ispu_mem_data; + ism330is_ispu_if2s_flag_l_t ispu_if2s_flag_l; + ism330is_ispu_if2s_flag_h_t ispu_if2s_flag_h; + ism330is_ispu_s2if_flag_l_t ispu_s2if_flag_l; + ism330is_ispu_s2if_flag_h_t ispu_s2if_flag_h; + ism330is_ispu_dout_00_l_t ispu_dout_00_l; + ism330is_ispu_dout_00_h_t ispu_dout_00_h; + ism330is_ispu_dout_01_l_t ispu_dout_01_l; + ism330is_ispu_dout_01_h_t ispu_dout_01_h; + ism330is_ispu_dout_02_l_t ispu_dout_02_l; + ism330is_ispu_dout_02_h_t ispu_dout_02_h; + ism330is_ispu_dout_03_l_t ispu_dout_03_l; + ism330is_ispu_dout_03_h_t ispu_dout_03_h; + ism330is_ispu_dout_04_l_t ispu_dout_04_l; + ism330is_ispu_dout_04_h_t ispu_dout_04_h; + ism330is_ispu_dout_05_l_t ispu_dout_05_l; + ism330is_ispu_dout_05_h_t ispu_dout_05_h; + ism330is_ispu_dout_06_l_t ispu_dout_06_l; + ism330is_ispu_dout_06_h_t ispu_dout_06_h; + ism330is_ispu_dout_07_l_t ispu_dout_07_l; + ism330is_ispu_dout_07_h_t ispu_dout_07_h; + ism330is_ispu_dout_08_l_t ispu_dout_08_l; + ism330is_ispu_dout_08_h_t ispu_dout_08_h; + ism330is_ispu_dout_09_l_t ispu_dout_09_l; + ism330is_ispu_dout_09_h_t ispu_dout_09_h; + ism330is_ispu_dout_10_l_t ispu_dout_10_l; + ism330is_ispu_dout_10_h_t ispu_dout_10_h; + ism330is_ispu_dout_11_l_t ispu_dout_11_l; + ism330is_ispu_dout_11_h_t ispu_dout_11_h; + ism330is_ispu_dout_12_l_t ispu_dout_12_l; + ism330is_ispu_dout_12_h_t ispu_dout_12_h; + ism330is_ispu_dout_13_l_t ispu_dout_13_l; + ism330is_ispu_dout_13_h_t ispu_dout_13_h; + ism330is_ispu_dout_14_l_t ispu_dout_14_l; + ism330is_ispu_dout_14_h_t ispu_dout_14_h; + ism330is_ispu_dout_15_l_t ispu_dout_15_l; + ism330is_ispu_dout_15_h_t ispu_dout_15_h; + ism330is_ispu_dout_16_l_t ispu_dout_16_l; + ism330is_ispu_dout_16_h_t ispu_dout_16_h; + ism330is_ispu_dout_17_l_t ispu_dout_17_l; + ism330is_ispu_dout_17_h_t ispu_dout_17_h; + ism330is_ispu_dout_18_l_t ispu_dout_18_l; + ism330is_ispu_dout_18_h_t ispu_dout_18_h; + ism330is_ispu_dout_19_l_t ispu_dout_19_l; + ism330is_ispu_dout_19_h_t ispu_dout_19_h; + ism330is_ispu_dout_20_l_t ispu_dout_20_l; + ism330is_ispu_dout_20_h_t ispu_dout_20_h; + ism330is_ispu_dout_21_l_t ispu_dout_21_l; + ism330is_ispu_dout_21_h_t ispu_dout_21_h; + ism330is_ispu_dout_22_l_t ispu_dout_22_l; + ism330is_ispu_dout_22_h_t ispu_dout_22_h; + ism330is_ispu_dout_23_l_t ispu_dout_23_l; + ism330is_ispu_dout_23_h_t ispu_dout_23_h; + ism330is_ispu_dout_24_l_t ispu_dout_24_l; + ism330is_ispu_dout_24_h_t ispu_dout_24_h; + ism330is_ispu_dout_25_l_t ispu_dout_25_l; + ism330is_ispu_dout_25_h_t ispu_dout_25_h; + ism330is_ispu_dout_26_l_t ispu_dout_26_l; + ism330is_ispu_dout_26_h_t ispu_dout_26_h; + ism330is_ispu_dout_27_l_t ispu_dout_27_l; + ism330is_ispu_dout_27_h_t ispu_dout_27_h; + ism330is_ispu_dout_28_l_t ispu_dout_28_l; + ism330is_ispu_dout_28_h_t ispu_dout_28_h; + ism330is_ispu_dout_29_l_t ispu_dout_29_l; + ism330is_ispu_dout_29_h_t ispu_dout_29_h; + ism330is_ispu_dout_30_l_t ispu_dout_30_l; + ism330is_ispu_dout_30_h_t ispu_dout_30_h; + ism330is_ispu_dout_31_l_t ispu_dout_31_l; + ism330is_ispu_dout_31_h_t ispu_dout_31_h; + ism330is_ispu_int1_ctrl0_t ispu_int1_ctrl0; + ism330is_ispu_int1_ctrl1_t ispu_int1_ctrl1; + ism330is_ispu_int1_ctrl2_t ispu_int1_ctrl2; + ism330is_ispu_int1_ctrl3_t ispu_int1_ctrl3; + ism330is_ispu_int2_ctrl0_t ispu_int2_ctrl0; + ism330is_ispu_int2_ctrl1_t ispu_int2_ctrl1; + ism330is_ispu_int2_ctrl2_t ispu_int2_ctrl2; + ism330is_ispu_int2_ctrl3_t ispu_int2_ctrl3; + ism330is_ispu_int_status0_t ispu_int_status0; + ism330is_ispu_int_status1_t ispu_int_status1; + ism330is_ispu_int_status2_t ispu_int_status2; + ism330is_ispu_int_status3_t ispu_int_status3; + ism330is_ispu_algo0_t ispu_algo0; + ism330is_ispu_algo1_t ispu_algo1; + ism330is_ispu_algo2_t ispu_algo2; + ism330is_ispu_algo3_t ispu_algo3; + bitwise_t bitwise; + uint8_t byte; +} ism330is_reg_t; + +/** + * @} + * + */ + +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + +int32_t ism330is_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); +int32_t ism330is_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); + +float_t ism330is_from_fs2g_to_mg(int16_t lsb); +float_t ism330is_from_fs4g_to_mg(int16_t lsb); +float_t ism330is_from_fs8g_to_mg(int16_t lsb); +float_t ism330is_from_fs16g_to_mg(int16_t lsb); + +float_t ism330is_from_fs125dps_to_mdps(int16_t lsb); +float_t ism330is_from_fs250dps_to_mdps(int16_t lsb); +float_t ism330is_from_fs500dps_to_mdps(int16_t lsb); +float_t ism330is_from_fs1000dps_to_mdps(int16_t lsb); +float_t ism330is_from_fs2000dps_to_mdps(int16_t lsb); + +float_t ism330is_from_lsb_to_celsius(int16_t lsb); + +typedef enum +{ + ISM330IS_MAIN_MEM_BANK = 0x0, + ISM330IS_SENSOR_HUB_MEM_BANK = 0x2, + ISM330IS_ISPU_MEM_BANK = 0x3, +} ism330is_mem_bank_t; +int32_t ism330is_mem_bank_set(stmdev_ctx_t *ctx, ism330is_mem_bank_t val); +int32_t ism330is_mem_bank_get(stmdev_ctx_t *ctx, ism330is_mem_bank_t *val); + +typedef enum +{ + ISM330IS_DRDY_LATCHED = 0x0, + ISM330IS_DRDY_PULSED = 0x1, +} ism330is_data_ready_mode_t; +int32_t ism330is_data_ready_mode_set(stmdev_ctx_t *ctx, + ism330is_data_ready_mode_t val); +int32_t ism330is_data_ready_mode_get(stmdev_ctx_t *ctx, + ism330is_data_ready_mode_t *val); + +int32_t ism330is_device_id_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330is_device_id_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism330is_software_reset(stmdev_ctx_t *ctx); + +int32_t ism330is_boot_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330is_boot_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM330IS_HIGH_PERFOMANCE_MODE_ENABLED = 0x0, + ISM330IS_HIGH_PERFOMANCE_MODE_DISABLED = 0x1, +} ism330is_hm_mode_t; +int32_t ism330is_xl_hm_mode_set(stmdev_ctx_t *ctx, ism330is_hm_mode_t val); +int32_t ism330is_xl_hm_mode_get(stmdev_ctx_t *ctx, ism330is_hm_mode_t *val); +int32_t ism330is_gy_hm_mode_set(stmdev_ctx_t *ctx, ism330is_hm_mode_t val); +int32_t ism330is_gy_hm_mode_get(stmdev_ctx_t *ctx, ism330is_hm_mode_t *val); + +typedef enum +{ + ISM330IS_2g = 0x0, + ISM330IS_16g = 0x1, + ISM330IS_4g = 0x2, + ISM330IS_8g = 0x3, +} ism330is_xl_full_scale_t; +int32_t ism330is_xl_full_scale_set(stmdev_ctx_t *ctx, + ism330is_xl_full_scale_t val); +int32_t ism330is_xl_full_scale_get(stmdev_ctx_t *ctx, + ism330is_xl_full_scale_t *val); + +typedef enum +{ + ISM330IS_XL_ODR_OFF = 0x0, + ISM330IS_XL_ODR_AT_12Hz5_HP = 0x1, + ISM330IS_XL_ODR_AT_26H_HP = 0x2, + ISM330IS_XL_ODR_AT_52Hz_HP = 0x3, + ISM330IS_XL_ODR_AT_104Hz_HP = 0x4, + ISM330IS_XL_ODR_AT_208Hz_HP = 0x5, + ISM330IS_XL_ODR_AT_416Hz_HP = 0x6, + ISM330IS_XL_ODR_AT_833Hz_HP = 0x7, + ISM330IS_XL_ODR_AT_1667Hz_HP = 0x8, + ISM330IS_XL_ODR_AT_3333Hz_HP = 0x9, + ISM330IS_XL_ODR_AT_6667Hz_HP = 0xa, + ISM330IS_XL_ODR_AT_12Hz5_LP = 0x11, + ISM330IS_XL_ODR_AT_26H_LP = 0x12, + ISM330IS_XL_ODR_AT_52Hz_LP = 0x13, + ISM330IS_XL_ODR_AT_104Hz_LP = 0x14, + ISM330IS_XL_ODR_AT_208Hz_LP = 0x15, + ISM330IS_XL_ODR_AT_416Hz_LP = 0x16, + ISM330IS_XL_ODR_AT_833Hz_LP = 0x17, + ISM330IS_XL_ODR_AT_1667Hz_LP = 0x18, + ISM330IS_XL_ODR_AT_3333Hz_LP = 0x19, + ISM330IS_XL_ODR_AT_6667Hz_LP = 0x1a, + ISM330IS_XL_ODR_AT_1Hz6_LP = 0x1b, +} ism330is_xl_data_rate_t; +int32_t ism330is_xl_data_rate_set(stmdev_ctx_t *ctx, + ism330is_xl_data_rate_t val); +int32_t ism330is_xl_data_rate_get(stmdev_ctx_t *ctx, + ism330is_xl_data_rate_t *val); + +typedef enum +{ + ISM330IS_250dps = 0x0, + ISM330IS_500dps = 0x1, + ISM330IS_1000dps = 0x2, + ISM330IS_2000dps = 0x3, + ISM330IS_125dps = 0x10, +} ism330is_gy_full_scale_t; +int32_t ism330is_gy_full_scale_set(stmdev_ctx_t *ctx, + ism330is_gy_full_scale_t val); +int32_t ism330is_gy_full_scale_get(stmdev_ctx_t *ctx, + ism330is_gy_full_scale_t *val); + +typedef enum +{ + ISM330IS_GY_ODR_OFF = 0x0, + ISM330IS_GY_ODR_AT_12Hz5_HP = 0x1, + ISM330IS_GY_ODR_AT_26H_HP = 0x2, + ISM330IS_GY_ODR_AT_52Hz_HP = 0x3, + ISM330IS_GY_ODR_AT_104Hz_HP = 0x4, + ISM330IS_GY_ODR_AT_208Hz_HP = 0x5, + ISM330IS_GY_ODR_AT_416Hz_HP = 0x6, + ISM330IS_GY_ODR_AT_833Hz_HP = 0x7, + ISM330IS_GY_ODR_AT_1667Hz_HP = 0x8, + ISM330IS_GY_ODR_AT_3333Hz_HP = 0x9, + ISM330IS_GY_ODR_AT_6667Hz_HP = 0xa, + ISM330IS_GY_ODR_AT_12Hz5_LP = 0x11, + ISM330IS_GY_ODR_AT_26H_LP = 0x12, + ISM330IS_GY_ODR_AT_52Hz_LP = 0x13, + ISM330IS_GY_ODR_AT_104Hz_LP = 0x14, + ISM330IS_GY_ODR_AT_208Hz_LP = 0x15, + ISM330IS_GY_ODR_AT_416Hz_LP = 0x16, + ISM330IS_GY_ODR_AT_833Hz_LP = 0x17, + ISM330IS_GY_ODR_AT_1667Hz_LP = 0x18, + ISM330IS_GY_ODR_AT_3333Hz_LP = 0x19, + ISM330IS_GY_ODR_AT_6667Hz_LP = 0x1a, +} ism330is_gy_data_rate_t; +int32_t ism330is_gy_data_rate_set(stmdev_ctx_t *ctx, + ism330is_gy_data_rate_t val); +int32_t ism330is_gy_data_rate_get(stmdev_ctx_t *ctx, + ism330is_gy_data_rate_t *val); + +int32_t ism330is_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330is_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism330is_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330is_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM330IS_SLEEP_G_ENABLE = 0x0, + ISM330IS_SLEEP_G_DISABLE = 0x1, +} ism330is_sleep_t; +int32_t ism330is_sleep_set(stmdev_ctx_t *ctx, ism330is_sleep_t val); +int32_t ism330is_sleep_get(stmdev_ctx_t *ctx, ism330is_sleep_t *val); + +typedef enum +{ + ISM330IS_XL_ST_DISABLE = 0x0, + ISM330IS_XL_ST_POSITIVE = 0x1, + ISM330IS_XL_ST_NEGATIVE = 0x2, +} ism330is_xl_self_test_t; +int32_t ism330is_xl_self_test_set(stmdev_ctx_t *ctx, + ism330is_xl_self_test_t val); +int32_t ism330is_xl_self_test_get(stmdev_ctx_t *ctx, + ism330is_xl_self_test_t *val); + +typedef enum +{ + ISM330IS_GY_ST_DISABLE = 0x0, + ISM330IS_GY_ST_POSITIVE = 0x1, + ISM330IS_GY_ST_NEGATIVE = 0x3, +} ism330is_gy_self_test_t; +int32_t ism330is_gy_self_test_set(stmdev_ctx_t *ctx, + ism330is_gy_self_test_t val); +int32_t ism330is_gy_self_test_get(stmdev_ctx_t *ctx, + ism330is_gy_self_test_t *val); + +int32_t ism330is_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330is_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM330IS_SPI_4_WIRE = 0x0, + ISM330IS_SPI_3_WIRE = 0x1, +} ism330is_spi_mode_t; +int32_t ism330is_spi_mode_set(stmdev_ctx_t *ctx, ism330is_spi_mode_t val); +int32_t ism330is_spi_mode_get(stmdev_ctx_t *ctx, ism330is_spi_mode_t *val); + +typedef enum +{ + ISM330IS_I2C_ENABLE = 0x0, + ISM330IS_I2C_DISABLE = 0x1, +} ism330is_ui_i2c_mode_t; +int32_t ism330is_ui_i2c_mode_set(stmdev_ctx_t *ctx, ism330is_ui_i2c_mode_t val); +int32_t ism330is_ui_i2c_mode_get(stmdev_ctx_t *ctx, + ism330is_ui_i2c_mode_t *val); + + +int32_t ism330is_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330is_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism330is_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); + +typedef struct +{ + uint8_t drdy_xl : 1; + uint8_t drdy_gy : 1; + uint8_t boot : 1; + uint8_t sh_endop : 1; + uint8_t ispu : 1; +} ism330is_pin_int1_route_t; +int32_t ism330is_pin_int1_route_set(stmdev_ctx_t *ctx, + ism330is_pin_int1_route_t val); +int32_t ism330is_pin_int1_route_get(stmdev_ctx_t *ctx, + ism330is_pin_int1_route_t *val); + +typedef struct +{ + uint8_t drdy_xl : 1; + uint8_t drdy_gy : 1; + uint8_t drdy_temp : 1; + uint8_t timestamp : 1; + uint8_t ispu_sleep : 1; + uint8_t ispu : 1; +} ism330is_pin_int2_route_t; +int32_t ism330is_pin_int2_route_set(stmdev_ctx_t *ctx, + ism330is_pin_int2_route_t val); +int32_t ism330is_pin_int2_route_get(stmdev_ctx_t *ctx, + ism330is_pin_int2_route_t *val); + +typedef enum +{ + ISM330IS_PUSH_PULL = 0x0, + ISM330IS_OPEN_DRAIN = 0x1, +} ism330is_int_pin_mode_t; +int32_t ism330is_int_pin_mode_set(stmdev_ctx_t *ctx, + ism330is_int_pin_mode_t val); +int32_t ism330is_int_pin_mode_get(stmdev_ctx_t *ctx, + ism330is_int_pin_mode_t *val); + +typedef enum +{ + ISM330IS_ACTIVE_HIGH = 0x0, + ISM330IS_ACTIVE_LOW = 0x1, +} ism330is_pin_polarity_t; +int32_t ism330is_pin_polarity_set(stmdev_ctx_t *ctx, + ism330is_pin_polarity_t val); +int32_t ism330is_pin_polarity_get(stmdev_ctx_t *ctx, + ism330is_pin_polarity_t *val); + +typedef struct +{ + uint8_t drdy_xl : 1; + uint8_t drdy_gy : 1; + uint8_t drdy_temp : 1; + uint8_t sh_endop : 1; + uint8_t sh_slave0_nack : 1; + uint8_t sh_slave1_nack : 1; + uint8_t sh_slave2_nack : 1; + uint8_t sh_slave3_nack : 1; + uint8_t sh_wr_once : 1; + uint32_t ispu : 30; +} ism330is_all_sources_t; +int32_t ism330is_all_sources_get(stmdev_ctx_t *ctx, + ism330is_all_sources_t *val); + +int32_t ism330is_status_reg_get(stmdev_ctx_t *ctx, + ism330is_status_reg_t *val); + +int32_t ism330is_xl_flag_data_ready_get(stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t ism330is_gy_flag_data_ready_get(stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t ism330is_temp_flag_data_ready_get(stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t ism330is_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); + +int32_t ism330is_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val); + +int32_t ism330is_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); + +int32_t ism330is_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330is_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + ism330is_sensor_hub_1_t sh_byte_1; + ism330is_sensor_hub_2_t sh_byte_2; + ism330is_sensor_hub_3_t sh_byte_3; + ism330is_sensor_hub_4_t sh_byte_4; + ism330is_sensor_hub_5_t sh_byte_5; + ism330is_sensor_hub_6_t sh_byte_6; + ism330is_sensor_hub_7_t sh_byte_7; + ism330is_sensor_hub_8_t sh_byte_8; + ism330is_sensor_hub_9_t sh_byte_9; + ism330is_sensor_hub_10_t sh_byte_10; + ism330is_sensor_hub_11_t sh_byte_11; + ism330is_sensor_hub_12_t sh_byte_12; + ism330is_sensor_hub_13_t sh_byte_13; + ism330is_sensor_hub_14_t sh_byte_14; + ism330is_sensor_hub_15_t sh_byte_15; + ism330is_sensor_hub_16_t sh_byte_16; + ism330is_sensor_hub_17_t sh_byte_17; + ism330is_sensor_hub_18_t sh_byte_18; +} ism330is_emb_sh_read_t; +int32_t ism330is_sh_read_data_raw_get(stmdev_ctx_t *ctx, + ism330is_emb_sh_read_t *val, + uint8_t len); + +typedef enum +{ + ISM330IS_SLV_0 = 0x0, + ISM330IS_SLV_0_1 = 0x1, + ISM330IS_SLV_0_1_2 = 0x2, + ISM330IS_SLV_0_1_2_3 = 0x3, +} ism330is_sh_slave_connected_t; +int32_t ism330is_sh_slave_connected_set(stmdev_ctx_t *ctx, + ism330is_sh_slave_connected_t val); +int32_t ism330is_sh_slave_connected_get(stmdev_ctx_t *ctx, + ism330is_sh_slave_connected_t *val); + +int32_t ism330is_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330is_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism330is_sh_master_interface_pull_up_set(stmdev_ctx_t *ctx, + uint8_t val); +int32_t ism330is_sh_master_interface_pull_up_get(stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t ism330is_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330is_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM330IS_SH_TRG_XL_GY_DRDY = 0x0, + ISM330IS_SH_TRIG_INT2 = 0x1, +} ism330is_sh_syncro_mode_t; +int32_t ism330is_sh_syncro_mode_set(stmdev_ctx_t *ctx, + ism330is_sh_syncro_mode_t val); +int32_t ism330is_sh_syncro_mode_get(stmdev_ctx_t *ctx, + ism330is_sh_syncro_mode_t *val); + +typedef enum +{ + ISM330IS_EACH_SH_CYCLE = 0x0, + ISM330IS_ONLY_FIRST_CYCLE = 0x1, +} ism330is_sh_write_mode_t; +int32_t ism330is_sh_write_mode_set(stmdev_ctx_t *ctx, + ism330is_sh_write_mode_t val); +int32_t ism330is_sh_write_mode_get(stmdev_ctx_t *ctx, + ism330is_sh_write_mode_t *val); + +int32_t ism330is_sh_reset_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330is_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t slv0_add; + uint8_t slv0_subadd; + uint8_t slv0_data; +} ism330is_sh_cfg_write_t; +int32_t ism330is_sh_cfg_write(stmdev_ctx_t *ctx, + ism330is_sh_cfg_write_t *val); +typedef enum +{ + ISM330IS_SH_104Hz = 0x0, + ISM330IS_SH_52Hz = 0x1, + ISM330IS_SH_26Hz = 0x2, + ISM330IS_SH_12_5Hz = 0x3, +} ism330is_sh_data_rate_t; +int32_t ism330is_sh_data_rate_set(stmdev_ctx_t *ctx, + ism330is_sh_data_rate_t val); +int32_t ism330is_sh_data_rate_get(stmdev_ctx_t *ctx, + ism330is_sh_data_rate_t *val); + +typedef struct +{ + uint8_t slv_add; + uint8_t slv_subadd; + uint8_t slv_len; +} ism330is_sh_cfg_read_t; +int32_t ism330is_sh_slv0_cfg_read(stmdev_ctx_t *ctx, + ism330is_sh_cfg_read_t *val); +int32_t ism330is_sh_slv1_cfg_read(stmdev_ctx_t *ctx, + ism330is_sh_cfg_read_t *val); +int32_t ism330is_sh_slv2_cfg_read(stmdev_ctx_t *ctx, + ism330is_sh_cfg_read_t *val); +int32_t ism330is_sh_slv3_cfg_read(stmdev_ctx_t *ctx, + ism330is_sh_cfg_read_t *val); + +int32_t ism330is_ispu_reset_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330is_ispu_reset_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM330IS_ISPU_CLK_5MHz = 0x0, + ISM330IS_ISPU_CLK_10MHz = 0x1, +} ism330is_ispu_clock_sel_t; +int32_t ism330is_ispu_clock_set(stmdev_ctx_t *ctx, + ism330is_ispu_clock_sel_t val); +int32_t ism330is_ispu_clock_get(stmdev_ctx_t *ctx, + ism330is_ispu_clock_sel_t *val); + +typedef enum +{ + ISM330IS_ISPU_ODR_OFF = 0x0, + ISM330IS_ISPU_ODR_AT_12Hz5 = 0x1, + ISM330IS_ISPU_ODR_AT_26Hz = 0x2, + ISM330IS_ISPU_ODR_AT_52Hz = 0x3, + ISM330IS_ISPU_ODR_AT_104Hz = 0x4, + ISM330IS_ISPU_ODR_AT_208Hz = 0x5, + ISM330IS_ISPU_ODR_AT_416Hz = 0x6, + ISM330IS_ISPU_ODR_AT_833Hz = 0x7, + ISM330IS_ISPU_ODR_AT_1667Hz = 0x8, + ISM330IS_ISPU_ODR_AT_3333Hz = 0x9, + ISM330IS_ISPU_ODR_AT_6667Hz = 0xa, +} ism330is_ispu_data_rate_t; +int32_t ism330is_ispu_data_rate_set(stmdev_ctx_t *ctx, + ism330is_ispu_data_rate_t val); +int32_t ism330is_ispu_data_rate_get(stmdev_ctx_t *ctx, + ism330is_ispu_data_rate_t *val); + +typedef enum +{ + ISM330IS_ISPU_BDU_OFF = 0x0, + ISM330IS_ISPU_BDU_ON_2B_4B = 0x1, + ISM330IS_ISPU_BDU_ON_2B_2B = 0x2, + ISM330IS_ISPU_BDU_ON_4B_4B = 0x3, +} ism330is_ispu_bdu_t; +int32_t ism330is_ispu_bdu_set(stmdev_ctx_t *ctx, ism330is_ispu_bdu_t val); +int32_t ism330is_ispu_bdu_get(stmdev_ctx_t *ctx, ism330is_ispu_bdu_t *val); + +int32_t ism330is_ia_ispu_get(stmdev_ctx_t *ctx, uint32_t *val); + +int32_t ism330is_ispu_write_dummy_cfg(stmdev_ctx_t *ctx, uint8_t offset, + uint8_t *val, uint8_t len); +int32_t ism330is_ispu_ready_dummy_cfg(stmdev_ctx_t *ctx, uint8_t offset, + uint8_t *val, uint8_t len); + +typedef enum +{ + ISM330IS_ISPU_TURN_ON = 0x0, + ISM330IS_ISPU_TURN_OFF = 0x1, +} ism330is_ispu_boot_latched_t; +int32_t ism330is_ispu_boot_set(stmdev_ctx_t *ctx, + ism330is_ispu_boot_latched_t val); +int32_t ism330is_ispu_boot_get(stmdev_ctx_t *ctx, + ism330is_ispu_boot_latched_t *val); + +typedef enum +{ + ISM330IS_ISPU_INT_PULSED = 0x0, + ISM330IS_ISPU_INT_LATCHED = 0x1, +} ism330is_ispu_int_latched_t; +int32_t ism330is_ispu_int_latched_set(stmdev_ctx_t *ctx, + ism330is_ispu_int_latched_t val); +int32_t ism330is_ispu_int_latched_get(stmdev_ctx_t *ctx, + ism330is_ispu_int_latched_t *val); + +typedef enum +{ + ISM330IS_ISPU_BOOT_IN_PROGRESS = 0x0, + ISM330IS_ISPU_BOOT_ENDED = 0x1, +} ism330is_ispu_boot_end_t; +int32_t ism330is_ispu_get_boot_status(stmdev_ctx_t *ctx, + ism330is_ispu_boot_end_t *val); + +typedef enum +{ + ISM330IS_ISPU_DATA_RAM_MEMORY = 0x0, + ISM330IS_ISPU_PROGRAM_RAM_MEMORY = 0x1, +} ism330is_ispu_memory_type_t; +int32_t ism330is_ispu_read_memory_enable(stmdev_ctx_t *ctx, + ism330is_ispu_memory_type_t val); +int32_t ism330is_ispu_read_memory_disable(stmdev_ctx_t *ctx); + +int32_t ism330is_ispu_write_memory(stmdev_ctx_t *ctx, + ism330is_ispu_memory_type_t mem_sel, + uint16_t mem_addr, uint8_t *mem_data, uint16_t len); +int32_t ism330is_ispu_read_memory(stmdev_ctx_t *ctx, + ism330is_ispu_memory_type_t mem_sel, + uint16_t mem_addr, uint8_t *mem_data, uint16_t len); + +int32_t ism330is_ispu_write_flags(stmdev_ctx_t *ctx, uint16_t data); +int32_t ism330is_ispu_read_flags(stmdev_ctx_t *ctx, uint16_t *data); +int32_t ism330is_ispu_clear_flags(stmdev_ctx_t *ctx); + +int32_t ism330is_ispu_read_data_raw_get(stmdev_ctx_t *ctx, + uint8_t *val, + uint8_t len); + +int32_t ism330is_ispu_int1_ctrl_get(stmdev_ctx_t *ctx, uint32_t *val); +int32_t ism330is_ispu_int1_ctrl_set(stmdev_ctx_t *ctx, uint32_t val); +int32_t ism330is_ispu_int2_ctrl_get(stmdev_ctx_t *ctx, uint32_t *val); +int32_t ism330is_ispu_int2_ctrl_set(stmdev_ctx_t *ctx, uint32_t val); + +int32_t ism330is_ispu_int_status_get(stmdev_ctx_t *ctx, uint32_t *val); + +int32_t ism330is_ispu_algo_get(stmdev_ctx_t *ctx, uint32_t *val); +int32_t ism330is_ispu_algo_set(stmdev_ctx_t *ctx, uint32_t val); +/** + * @} + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /*ISM330IS_DRIVER_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/l20g20is_STdC/driver/l20g20is_reg.c b/sensor/stmemsc/l20g20is_STdC/driver/l20g20is_reg.c index 8a3d75f3a2cf2e7c49e2007e7f171d08fd5da67a..f3598ecf5675e93c771a117aeef2642490690274 100644 --- a/sensor/stmemsc/l20g20is_STdC/driver/l20g20is_reg.c +++ b/sensor/stmemsc/l20g20is_STdC/driver/l20g20is_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t l20g20is_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak l20g20is_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; ret = ctx->read_reg(ctx->handle, reg, data, len); @@ -66,9 +66,9 @@ int32_t l20g20is_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t l20g20is_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak l20g20is_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; ret = ctx->write_reg(ctx->handle, reg, data, len); diff --git a/sensor/stmemsc/l20g20is_STdC/driver/l20g20is_reg.h b/sensor/stmemsc/l20g20is_STdC/driver/l20g20is_reg.h index d18eef6d74edb281d71bac721879f3a54c9b3daa..f0810f7cb809176d7f55036b99fe6e97fbf48cbe 100644 --- a/sensor/stmemsc/l20g20is_STdC/driver/l20g20is_reg.h +++ b/sensor/stmemsc/l20g20is_STdC/driver/l20g20is_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -360,6 +363,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t l20g20is_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.c b/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.c index 19cd5ceb28f15ae1cab8e8f21781caa1f2ec5a76..9194d9b9ef8680a77ed73b1f0903f233fe3d82ce 100644 --- a/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.c +++ b/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t l3gd20h_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak l3gd20h_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; ret = ctx->read_reg(ctx->handle, reg, data, len); @@ -66,9 +66,9 @@ int32_t l3gd20h_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t l3gd20h_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak l3gd20h_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; ret = ctx->write_reg(ctx->handle, reg, data, len); diff --git a/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.h b/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.h index 6172620d079ac7a7eb4423cbbb5c57e97d74f849..ce70da353d8eb562d8a40c675042647693222dfa 100644 --- a/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.h +++ b/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -515,6 +518,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t l3gd20h_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.c b/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.c index 1e8956aabe85d01c855c8f0b0e15fd35020d705b..007f93995b5f9bdd7a9c59e0a7f2da34b4e8d8c9 100644 --- a/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.c +++ b/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis25ba_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lis25ba_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t lis25ba_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis25ba_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lis25ba_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.h b/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.h index b4a4465f95010edd690d6fa160d671ab83ffb911..c48a757e6f859a42746614ae4367f623e972c114 100644 --- a/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.h +++ b/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -294,6 +297,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lis25ba_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.c b/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.c index fc4daae2917951da27d5cc48e7e27d2dc15739f1..e40b907bd9fb404a1d50d89994c246391bf1c41b 100644 --- a/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.c +++ b/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lis2de12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t lis2de12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lis2de12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.h b/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.h index d864071a40a044477079825ce73018d3a3242564..c6206d0bbe26d999a9b84d344543a94ba931f6a9 100644 --- a/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.h +++ b/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -701,6 +704,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lis2de12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.c b/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.c index 5cf3cb57245ae2fdd74e03c47f7ba0354b027600..bd09a4b5d532217be8284027100d1748e1c39a9e 100644 --- a/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.c +++ b/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lis2dh12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t lis2dh12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lis2dh12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.h b/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.h index e5567abc1b2651da92bbc70afbb40eca81882d73..a32d5717d1e747bc43ffd49f5f1f7fa566e98363 100644 --- a/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.h +++ b/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.h @@ -110,12 +110,15 @@ typedef struct */ typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -702,6 +705,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lis2dh12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/lis2dh_STdC/driver/lis2dh_reg.c b/sensor/stmemsc/lis2dh_STdC/driver/lis2dh_reg.c index 190b92c5f1a1044e9633dcb30161b658d4661942..507353a01e0c8ae24646ac53c0f2d67251462afb 100644 --- a/sensor/stmemsc/lis2dh_STdC/driver/lis2dh_reg.c +++ b/sensor/stmemsc/lis2dh_STdC/driver/lis2dh_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lis2dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t lis2dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lis2dh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lis2dh_STdC/driver/lis2dh_reg.h b/sensor/stmemsc/lis2dh_STdC/driver/lis2dh_reg.h index ab6ca37ce019ff0796fb2e575d46ed3a5f7c8912..ead648cdfa3222ba8259e2ddb89852146491ca65 100644 --- a/sensor/stmemsc/lis2dh_STdC/driver/lis2dh_reg.h +++ b/sensor/stmemsc/lis2dh_STdC/driver/lis2dh_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -690,6 +693,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lis2dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.c b/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.c index a49b39bcfb64ce47413c4d43ee99292aa9580b9b..a985af74b49dcebd774b54c92405881f865455e1 100644 --- a/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.c +++ b/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2ds12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lis2ds12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t lis2ds12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2ds12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lis2ds12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.h b/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.h index b95500d69e5646f1ff2cb09f1734c0421394344d..a28e55b26a09e49683b93118ba8e220df593d9b0 100644 --- a/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.h +++ b/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -890,6 +893,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lis2ds12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.c b/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.c index e85c1e9a9bacbd95c393a125eb510a185d331b20..f89f303192d6172aab65e60a02bdb5f5bfc5537a 100644 --- a/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.c +++ b/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lis2dtw12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t lis2dtw12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lis2dtw12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.h b/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.h index 4cf96b71f9362b9763930a942d488797ea10421a..5a51e7a6221732b4aa0fa2504d46970ae28cf8a7 100644 --- a/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.h +++ b/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -651,6 +654,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lis2dtw12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/lis2du12_STdC/driver/lis2du12_reg.c b/sensor/stmemsc/lis2du12_STdC/driver/lis2du12_reg.c new file mode 100644 index 0000000000000000000000000000000000000000..21973735cebf78e70ef547a172431aacce853157 --- /dev/null +++ b/sensor/stmemsc/lis2du12_STdC/driver/lis2du12_reg.c @@ -0,0 +1,1674 @@ +/* + ****************************************************************************** + * @file lis2du12_reg.c + * @author Sensors Software Solution Team + * @brief LIS2DU12 driver file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "lis2du12_reg.h" + +/** + * @defgroup LIS2DU12 + * @brief This file provides a set of functions needed to drive the + * lis2du12 sensor. + * @{ + * + */ + +/** + * @defgroup LIS2DU12_Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +/** + * @brief Read generic device register + * + * @param ctx read / write interface definitions(ptr) + * @param reg register to read + * @param data pointer to buffer that store the data read(ptr) + * @param len number of consecutive register to read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak lis2du12_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data, + uint16_t len) +{ + int32_t ret; + ret = ctx->read_reg(ctx->handle, reg, data, len); + return ret; +} + +/** + * @brief Write generic device register + * + * @param ctx read / write interface definitions(ptr) + * @param reg register to write + * @param data pointer to data to write in register reg(ptr) + * @param len number of consecutive register to write + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak lis2du12_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data, + uint16_t len) +{ + int32_t ret; + ret = ctx->write_reg(ctx->handle, reg, data, len); + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LIS2DU12_Private_functions + * @brief Section collect all the utility functions needed by APIs. + * @{ + * + */ + +static void bytecpy(uint8_t *target, uint8_t *source) +{ + if ( (target != NULL) && (source != NULL) ) { + *target = *source; + } +} + +/** + * @} + * + */ + +/** + * @defgroup LIS2DU12_Sensitivity + * @brief These functions convert raw-data into engineering units. + * @{ + * + */ + +float_t lis2du12_from_fs2g_to_mg(int16_t lsb) +{ + return (float_t)lsb * 0.061f; +} + +float_t lis2du12_from_fs4g_to_mg(int16_t lsb) +{ + return (float_t)lsb * 0.122f; +} + +float_t lis2du12_from_fs8g_to_mg(int16_t lsb) +{ + return (float_t)lsb * 0.244f; +} + +float_t lis2du12_from_fs16g_to_mg(int16_t lsb) +{ + return (float_t)lsb * 0.488f; +} + +float_t lis2du12_from_lsb_to_celsius(int16_t lsb) +{ + return ((float_t)lsb / 355.5f) + 25.0f; +} + +/** + * @} + * + */ + +/** + * @defgroup Basic functions + * @brief This section groups all the functions concerning + * device basic configuration. + * @{ + * + */ + +/** + * @brief Device "Who am I".[get] + * + * @param ctx communication interface handler.(ptr) + * @param val ID values.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_id_get(stmdev_ctx_t *ctx, lis2du12_id_t *val) +{ + uint8_t reg; + int32_t ret; + + ret = lis2du12_read_reg(ctx, LIS2DU12_WHO_AM_I,®, 1); + val->whoami = reg; + + return ret; +} + +/** + * @brief Configures the bus operating mode.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val configures the bus operating mode.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_bus_mode_set(stmdev_ctx_t *ctx, lis2du12_bus_mode_t val) +{ + lis2du12_if_ctrl_t if_ctrl; + lis2du12_ctrl1_t ctrl1; + int32_t ret; + + ret = lis2du12_read_reg(ctx, LIS2DU12_IF_CTRL, (uint8_t*)&if_ctrl, 1); + if (ret == 0) { + if_ctrl.i3c_disable = (uint8_t)val & 0x01U; + if_ctrl.i2c_disable = ((uint8_t)val & 0x02U) >> 1; + ret = lis2du12_write_reg(ctx, LIS2DU12_IF_CTRL, (uint8_t*)&if_ctrl, 1); + } + if (ret == 0) { + ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); + } + if (ret == 0) { + ctrl1.sim = ((uint8_t)val & 0x04U) >> 2; + ret = lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); + } + + return ret; + +} + +/** + * @brief Configures the bus operating mode.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val configures the bus operating mode.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_bus_mode_get(stmdev_ctx_t *ctx, lis2du12_bus_mode_t *val) +{ + lis2du12_if_ctrl_t if_ctrl; + lis2du12_ctrl1_t ctrl1; + int32_t ret; + + ret = lis2du12_read_reg(ctx, LIS2DU12_IF_CTRL, (uint8_t*)&if_ctrl, 1); + if (ret == 0) { + ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); + } + switch ( (ctrl1.sim << 2) | (if_ctrl.i2c_disable) << 1 | + (if_ctrl.i3c_disable) ) { + case LIS2DU12_SEL_BY_HW: + *val = LIS2DU12_SEL_BY_HW; + break; + case LIS2DU12_SPI_3W: + *val = LIS2DU12_SPI_3W; + break; + default: + *val = LIS2DU12_SEL_BY_HW; + break; + } + + return ret; +} + +/** + * @brief Configures the bus operating mode.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val configures the bus operating mode.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_init_set(stmdev_ctx_t *ctx, lis2du12_init_t val) +{ + lis2du12_ctrl1_t ctrl1; + lis2du12_ctrl4_t ctrl4; + int32_t ret; + + ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL4, (uint8_t*)&ctrl4, 1); + switch ( val ) { + case LIS2DU12_BOOT: + ctrl4.boot = PROPERTY_ENABLE; + ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL4, (uint8_t*)&ctrl4, 1); + break; + case LIS2DU12_RESET: + + ctrl1.sw_reset = PROPERTY_ENABLE; + ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); + break; + case LIS2DU12_DRV_RDY: + ctrl4.bdu = PROPERTY_ENABLE; + ctrl1.if_add_inc = PROPERTY_ENABLE; + ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL4, (uint8_t*)&ctrl4, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); + break; + default: + ctrl1.sw_reset = PROPERTY_ENABLE; + ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); + break; + } + + return ret; +} + +/** + * @brief Get the status of the device.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val the status of the device.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_status_get(stmdev_ctx_t *ctx, lis2du12_status_t *val) +{ + lis2du12_status_register_t status_register; + lis2du12_ctrl1_t ctrl1; + lis2du12_ctrl4_t ctrl4; + int32_t ret; + + ret = lis2du12_read_reg(ctx, LIS2DU12_STATUS, + (uint8_t*)&status_register, 1); + if (ret == 0) { + ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); + } + if (ret == 0) { + ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL4, (uint8_t*)&ctrl4, 1); + } + + val->sw_reset = ctrl1.sw_reset; + val->boot = ctrl4.boot; + val->drdy_xl = status_register.drdy; + val->power_down = status_register.pd_status; + + return ret; +} + +/** + * @brief Electrical pin configuration.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val the electrical settings for the configurable pins.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_pin_conf_set(stmdev_ctx_t *ctx, lis2du12_pin_conf_t *val) +{ + lis2du12_if_pu_ctrl_t if_pu_ctrl; + lis2du12_md2_cfg_t md2_cfg; + lis2du12_if_ctrl_t if_ctrl; + lis2du12_ctrl1_t ctrl1; + int32_t ret; + + ret = lis2du12_read_reg(ctx, LIS2DU12_IF_PU_CTRL, (uint8_t*)&if_pu_ctrl, 1); + if (ret == 0) { + ret = lis2du12_read_reg(ctx, LIS2DU12_IF_CTRL, (uint8_t*)&if_ctrl, 1); + } + if (ret == 0) { + ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); + } + if (ret == 0) { + ret = lis2du12_read_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t*)&md2_cfg, 1); + } + + if (ret == 0) { + if_pu_ctrl.sdo_pu_disc = ~val->sdo_pull_up; + if_pu_ctrl.sda_pu_en = val->sda_pull_up; + if_pu_ctrl.cs_pu_disc = ~val->cs_pull_up; + ret = lis2du12_write_reg(ctx, LIS2DU12_IF_PU_CTRL, (uint8_t*)&if_pu_ctrl, 1); + } + if (ret == 0) { + if_ctrl.pd_dis_int1 = val->int1_pull_down; + ret = lis2du12_write_reg(ctx, LIS2DU12_IF_CTRL, (uint8_t*)&if_ctrl, 1); + } + if (ret == 0) { + ctrl1.pp_od = val->int1_int2_push_pull; + ret = lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); + } + if (ret == 0) { + md2_cfg.pd_dis_int2 = val->int2_pull_down; + ret = lis2du12_write_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t*)&md2_cfg, 1); + } + + return ret; +} + +/** + * @brief Electrical pin configuration.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val the electrical settings for the configurable pins.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_pin_conf_get(stmdev_ctx_t *ctx, lis2du12_pin_conf_t *val) +{ + lis2du12_if_pu_ctrl_t if_pu_ctrl; + lis2du12_md2_cfg_t md2_cfg; + lis2du12_if_ctrl_t if_ctrl; + lis2du12_ctrl1_t ctrl1; + int32_t ret; + + ret = lis2du12_read_reg(ctx, LIS2DU12_IF_PU_CTRL, (uint8_t*)&if_pu_ctrl, 1); + if (ret == 0) { + ret = lis2du12_read_reg(ctx, LIS2DU12_IF_CTRL, (uint8_t*)&if_ctrl, 1); + } + if (ret == 0) { + ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); + } + if (ret == 0) { + ret = lis2du12_read_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t*)&md2_cfg, 1); + } + val->sdo_pull_up = ~if_pu_ctrl.sdo_pu_disc; + val->sda_pull_up = if_pu_ctrl.sda_pu_en; + val->cs_pull_up = ~if_pu_ctrl.cs_pu_disc; + val->int1_int2_push_pull = ctrl1.pp_od; + val->int1_pull_down = if_ctrl.pd_dis_int1; + val->int2_pull_down = md2_cfg.pd_dis_int2; + + return ret; +} + +/** + * @brief Get the status of all the interrupt sources.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val the status of all the interrupt sources.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_all_sources_get(stmdev_ctx_t *ctx, + lis2du12_all_sources_t *val) +{ + lis2du12_all_int_src_t all_int_src; + int32_t ret; + + ret = lis2du12_read_reg(ctx, LIS2DU12_ALL_INT_SRC, (uint8_t*)&all_int_src, 1); + if (ret == 0 && all_int_src.int_global == 1U) + { + val->free_fall = all_int_src.ff_ia_all; + val->six_d = all_int_src.d6d_ia_all; + val->wake_up = all_int_src.wu_ia_all; + val->sleep_change = all_int_src.sleep_change_ia_all; + val->single_tap = all_int_src.single_tap_all; + val->double_tap = all_int_src.double_tap_all; + + if (all_int_src.d6d_ia_all == 1U) + { + lis2du12_sixd_src_t sixd_src; + + ret = lis2du12_read_reg(ctx, LIS2DU12_SIXD_SRC, (uint8_t*)&sixd_src, 1); + + val->six_d_xl = sixd_src.xl; + val->six_d_xh = sixd_src.xh; + val->six_d_yl = sixd_src.yl; + val->six_d_yh = sixd_src.yh; + val->six_d_zl = sixd_src.zl; + val->six_d_zh = sixd_src.zh; + } + + if (all_int_src.wu_ia_all == 1U || all_int_src.sleep_change_ia_all == 1U) + { + lis2du12_wake_up_src_t wu_src; + + ret = lis2du12_read_reg(ctx, LIS2DU12_WAKE_UP_SRC, (uint8_t*)&wu_src, 1); + + val->wake_up_z = wu_src.z_wu; + val->wake_up_y = wu_src.y_wu; + val->wake_up_x = wu_src.z_wu; + val->sleep_state = wu_src.sleep_state; + } + + if (all_int_src.single_tap_all == 1U || all_int_src.double_tap_all == 1U) + { + lis2du12_tap_src_t tap_src; + + ret = lis2du12_read_reg(ctx, LIS2DU12_TAP_SRC, (uint8_t*)&tap_src, 1); + + val->tap_z = tap_src.z_tap; + val->tap_y = tap_src.y_tap; + val->tap_x = tap_src.x_tap; + val->tap_sign = tap_src.tap_sign; + } + } + + return ret; +} + +/** + * @brief Sensor conversion parameters selection.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val set the sensor conversion parameters.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_mode_set(stmdev_ctx_t *ctx, lis2du12_md_t *val) +{ + lis2du12_ctrl5_t ctrl5; + int32_t ret; + + ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL5, (uint8_t*)&ctrl5, 1); + + ctrl5.odr = (uint8_t)val->odr; + ctrl5.fs = (uint8_t)val->fs; + ctrl5.bw = (uint8_t)val->bw; + + ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL5, (uint8_t*)&ctrl5, 1); + + return ret; +} + +/** + * @brief Sensor conversion parameters selection.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val get the sensor conversion parameters.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_mode_get(stmdev_ctx_t *ctx, lis2du12_md_t *val) +{ + lis2du12_ctrl5_t ctrl5; + int32_t ret; + + ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL5, (uint8_t*)&ctrl5, 1); + + switch (ctrl5.odr) { + case LIS2DU12_OFF: + val->odr = LIS2DU12_OFF; + break; + case LIS2DU12_1Hz5_ULP: + val->odr = LIS2DU12_1Hz5_ULP; + break; + case LIS2DU12_3Hz_ULP: + val->odr = LIS2DU12_3Hz_ULP; + break; + case LIS2DU12_6Hz_ULP: + val->odr = LIS2DU12_6Hz_ULP; + break; + case LIS2DU12_6Hz: + val->odr = LIS2DU12_6Hz; + break; + case LIS2DU12_12Hz5: + val->odr = LIS2DU12_12Hz5; + break; + case LIS2DU12_25Hz: + val->odr = LIS2DU12_25Hz; + break; + case LIS2DU12_50Hz: + val->odr = LIS2DU12_50Hz; + break; + case LIS2DU12_100Hz: + val->odr = LIS2DU12_100Hz; + break; + case LIS2DU12_200Hz: + val->odr = LIS2DU12_200Hz; + break; + case LIS2DU12_400Hz: + val->odr = LIS2DU12_400Hz; + break; + case LIS2DU12_800Hz: + val->odr = LIS2DU12_800Hz; + break; + case LIS2DU12_TRIG_PIN: + val->odr = LIS2DU12_TRIG_PIN; + break; + case LIS2DU12_TRIG_SW: + val->odr = LIS2DU12_TRIG_SW; + break; + default: + val->odr = LIS2DU12_OFF; + break; + } + + switch (ctrl5.fs) { + case LIS2DU12_2g: + val->fs = LIS2DU12_2g; + break; + case LIS2DU12_4g: + val->fs = LIS2DU12_4g; + break; + case LIS2DU12_8g: + val->fs = LIS2DU12_8g; + break; + case LIS2DU12_16g: + val->fs = LIS2DU12_16g; + break; + default: + val->fs = LIS2DU12_2g; + break; + } + + switch (ctrl5.bw) { + case LIS2DU12_ODR_div_2: + val->bw = LIS2DU12_ODR_div_2; + break; + case LIS2DU12_ODR_div_4: + val->bw = LIS2DU12_ODR_div_4; + break; + case LIS2DU12_ODR_div_8: + val->bw = LIS2DU12_ODR_div_8; + break; + case LIS2DU12_ODR_div_16: + val->bw = LIS2DU12_ODR_div_16; + break; + default: + val->bw = LIS2DU12_ODR_div_2; + break; + } + + return ret; +} + +/** + * @brief Software trigger for One-Shot.[get] + * + * @param ctx communication interface handler.(ptr) + * @param md the sensor conversion parameters.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_trigger_sw(stmdev_ctx_t *ctx, lis2du12_md_t *md) +{ + lis2du12_ctrl4_t ctrl4; + int32_t ret = 0; + + if ( md->odr == LIS2DU12_TRIG_SW ) { + ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL4, (uint8_t*)&ctrl4, 1); + ctrl4.soc = PROPERTY_ENABLE; + ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL4, (uint8_t*)&ctrl4, 1); + } + return ret; +} + +/** + * @brief Software trigger for One-Shot.[get] + * + * @param ctx communication interface handler.(ptr) + * @param md the sensor conversion parameters.(ptr) + * @param data data retrived from the sensor.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_data_get(stmdev_ctx_t *ctx, lis2du12_md_t *md, + lis2du12_data_t *data) +{ + uint8_t buff[8]; + int32_t ret; + uint8_t i; + uint8_t j; + + ret = lis2du12_read_reg(ctx, LIS2DU12_OUTX_L, (uint8_t*)&buff, 8); + + /* acceleration conversion */ + j = 0U; + for (i = 0U; i < 3U; i++) { + data->xl.raw[i] = (int16_t)buff[j+1U]; + data->xl.raw[i] = (data->xl.raw[i] * 256) + (int16_t) buff[j]; + j+=2U; + switch ( md->fs ) { + case LIS2DU12_2g: + data->xl.mg[i] =lis2du12_from_fs2g_to_mg(data->xl.raw[i]); + break; + case LIS2DU12_4g: + data->xl.mg[i] =lis2du12_from_fs4g_to_mg(data->xl.raw[i]); + break; + case LIS2DU12_8g: + data->xl.mg[i] =lis2du12_from_fs8g_to_mg(data->xl.raw[i]); + break; + case LIS2DU12_16g: + data->xl.mg[i] =lis2du12_from_fs16g_to_mg(data->xl.raw[i]); + break; + default: + data->xl.mg[i] = 0.0f; + break; + } + } + + data->heat.raw = (int16_t)buff[j+1U]; + data->heat.raw = (data->heat.raw * 256) + (int16_t) buff[j]; + /* temperature conversion */ + data->heat.deg_c = lis2du12_from_lsb_to_celsius(data->heat.raw); + + return ret; +} + +/** + * @brief Configures the self test.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val self test mode.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_self_test_sign_set(stmdev_ctx_t *ctx, lis2du12_st_t val) +{ + lis2du12_st_sign_t st_sign; + int32_t ret; + + ret = lis2du12_read_reg(ctx, LIS2DU12_ST_SIGN, (uint8_t*)&st_sign, 1); + if (ret == 0) { + st_sign.stsign = (uint8_t) val; + ret = lis2du12_write_reg(ctx, LIS2DU12_ST_SIGN, (uint8_t*)&st_sign, 1); + } + return ret; +} + +/** + * @brief Configures the self test.[start] + * + * @param ctx communication interface handler.(ptr) + * @param val valid values 2 (1st step) or 1 (2nd step) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_self_test_start(stmdev_ctx_t *ctx, uint8_t val) +{ + lis2du12_ctrl3_t ctrl3; + int32_t ret; + + if (val != 1U && val != 2U) { + return -1; + } + + ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL3, (uint8_t*)&ctrl3, 1); + ctrl3.st = (uint8_t) val; + ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL3, (uint8_t*)&ctrl3, 1); + + return ret; +} + +/** + * @brief Configures the self test.[stop] + * + * @param ctx communication interface handler.(ptr) + * @param val valid values 2 (1st step) or 1 (2nd step) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_self_test_stop(stmdev_ctx_t *ctx) +{ + lis2du12_ctrl3_t ctrl3; + int32_t ret; + + ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL3, (uint8_t*)&ctrl3, 1); + ctrl3.st = 0; + ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL3, (uint8_t*)&ctrl3, 1); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup FIFO functions + * @brief This section groups all the functions concerning the + * management of FIFO. + * @{ + * + */ + +/** + * @brief FIFO operation mode selection.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val set the FIFO operation mode.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_fifo_mode_set(stmdev_ctx_t *ctx, lis2du12_fifo_md_t *val) +{ + lis2du12_fifo_ctrl_t fifo_ctrl; + lis2du12_fifo_wtm_t fifo_wtm; + uint8_t reg[2]; + int32_t ret; + + ret = lis2du12_read_reg(ctx, LIS2DU12_FIFO_CTRL, reg, 2); + + bytecpy(( uint8_t*)&fifo_ctrl, ®[0]); + bytecpy(( uint8_t*)&fifo_wtm, ®[1]); + + fifo_ctrl.f_mode = (uint8_t) val->operation; + fifo_ctrl.fifo_depth = (uint8_t) val->store; + + if (val->watermark != 0x00U) { + fifo_ctrl.stop_on_fth = PROPERTY_ENABLE; + } + else { + fifo_ctrl.stop_on_fth = PROPERTY_DISABLE; + } + + fifo_wtm.fth = val->watermark; + + bytecpy(®[0], ( uint8_t*)&fifo_ctrl); + bytecpy(®[1], ( uint8_t*)&fifo_wtm); + + ret += lis2du12_write_reg(ctx, LIS2DU12_FIFO_CTRL, reg, 2); + + return ret; +} + +/** + * @brief FIFO operation mode selection.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val get the FIFO operation mode.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_fifo_mode_get(stmdev_ctx_t *ctx, lis2du12_fifo_md_t *val) +{ + lis2du12_fifo_ctrl_t fifo_ctrl; + lis2du12_fifo_wtm_t fifo_wtm; + uint8_t reg[2]; + int32_t ret; + + ret = lis2du12_read_reg(ctx, LIS2DU12_FIFO_CTRL, reg, 2); + + bytecpy(( uint8_t*)&fifo_ctrl, ®[0]); + bytecpy(( uint8_t*)&fifo_wtm, ®[1]); + + switch (fifo_ctrl.f_mode) + { + case LIS2DU12_BYPASS: + val->operation = LIS2DU12_BYPASS; + break; + case LIS2DU12_FIFO: + val->operation = LIS2DU12_FIFO; + break; + case LIS2DU12_STREAM: + val->operation = LIS2DU12_STREAM; + break; + case LIS2DU12_STREAM_TO_FIFO: + val->operation = LIS2DU12_STREAM_TO_FIFO; + break; + case LIS2DU12_BYPASS_TO_STREAM: + val->operation = LIS2DU12_BYPASS_TO_STREAM; + break; + case LIS2DU12_BYPASS_TO_FIFO: + val->operation = LIS2DU12_BYPASS_TO_FIFO; + break; + default: + val->operation = LIS2DU12_BYPASS; + break; + } + + switch (fifo_ctrl.fifo_depth) + { + case LIS2DU12_16_BIT: + val->store = LIS2DU12_16_BIT; + break; + case LIS2DU12_8_BIT: + val->store = LIS2DU12_8_BIT; + break; + default: + val->store = LIS2DU12_16_BIT; + break; + } + + val->watermark = fifo_wtm.fth; + + return ret; +} + +int32_t lis2du12_fifo_status_get(stmdev_ctx_t *ctx, lis2du12_fifo_status_t *val) +{ + lis2du12_fifo_status1_t fifo_status1; + int32_t ret; + + ret = lis2du12_read_reg(ctx, LIS2DU12_FIFO_STATUS1, (uint8_t *)&fifo_status1, 1); + + val->fifo_fth = fifo_status1.fth; + val->fifo_ovr = fifo_status1.fifo_ovr; + + return ret; +} + +/** + * @brief Get the number of samples stored in FIFO.[get] + * + * @param ctx communication interface handler.(ptr) + * @param md the sensor conversion parameters.(ptr) + * @param val number of samples stored in FIFO.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_fifo_level_get(stmdev_ctx_t *ctx, lis2du12_fifo_md_t *md, + uint8_t *val) +{ + lis2du12_fifo_status2_t fifo_status2; + int32_t ret; + + ret = lis2du12_read_reg(ctx, LIS2DU12_FIFO_STATUS2, + (uint8_t*)&fifo_status2, 1); + + *val = fifo_status2.fss; + + return ret; +} + +/** + * @brief Software trigger for One-Shot.[get] + * + * @param ctx communication interface handler.(ptr) + * @param md the sensor conversion parameters.(ptr) + * @param fmd get the FIFO operation mode.(ptr) + * @param data data retrived from FIFO.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_fifo_data_get(stmdev_ctx_t *ctx, lis2du12_md_t *md, + lis2du12_fifo_md_t *fmd, + lis2du12_fifo_data_t *data) +{ + uint8_t fifo_data[8]; + int8_t i; + int32_t ret; + + ret = lis2du12_read_reg(ctx, LIS2DU12_OUTX_L, fifo_data, 8); + + if (fmd->store == LIS2DU12_8_BIT) { + for (i = 0; i < 3; i++) { + data->xl[0].raw[i] = (int16_t)fifo_data[2*i + 1]; + data->xl[0].raw[i] = data->xl[0].raw[i] * 256 + (int16_t)fifo_data[2*i]; + } + + data->heat.raw = (int16_t)fifo_data[7U]; + data->heat.raw = (data->heat.raw * 256) + (int16_t) fifo_data[6U]; + /* temperature conversion */ + data->heat.deg_c = lis2du12_from_lsb_to_celsius(data->heat.raw); + } else { + for (i = 0; i < 3; i++) { + data->xl[0].raw[i] = (int16_t)fifo_data[i] * 256; + data->xl[1].raw[i] = (int16_t)fifo_data[3 + i] * 256; + } + } + + for (i = 0; i < 3; i++) { + switch ( md->fs ) { + case LIS2DU12_2g: + data->xl[0].mg[i] =lis2du12_from_fs2g_to_mg(data->xl[0].raw[i]); + data->xl[1].mg[i] =lis2du12_from_fs2g_to_mg(data->xl[1].raw[i]); + break; + case LIS2DU12_4g: + data->xl[0].mg[i] =lis2du12_from_fs4g_to_mg(data->xl[0].raw[i]); + data->xl[1].mg[i] =lis2du12_from_fs4g_to_mg(data->xl[1].raw[i]); + break; + case LIS2DU12_8g: + data->xl[0].mg[i] =lis2du12_from_fs8g_to_mg(data->xl[0].raw[i]); + data->xl[1].mg[i] =lis2du12_from_fs8g_to_mg(data->xl[1].raw[i]); + break; + case LIS2DU12_16g: + data->xl[0].mg[i] =lis2du12_from_fs16g_to_mg(data->xl[0].raw[i]); + data->xl[1].mg[i] =lis2du12_from_fs16g_to_mg(data->xl[1].raw[i]); + break; + default: + data->xl[0].mg[i] = 0.0f; + data->xl[1].mg[i] = 0.0f; + break; + } + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Interrupt signals + * @brief This section groups all the functions concerning + * the management of interrupt signals. + * @{ + * + */ + +/** + * @brief Interrupt pins hardware signal configuration.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val the pins hardware signal settings.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_interrupt_mode_set(stmdev_ctx_t *ctx, + lis2du12_int_mode_t *val) +{ + lis2du12_interrupt_cfg_t interrupt_cfg; + lis2du12_ctrl1_t ctrl1; + int32_t ret; + + ret = lis2du12_read_reg(ctx, LIS2DU12_INTERRUPT_CFG, + (uint8_t*)&interrupt_cfg, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); + + interrupt_cfg.int_short_en = (uint8_t)val->base_sig & 0x01U; + interrupt_cfg.lir = ((uint8_t)val->base_sig & 0x02U) >> 1 ; + + interrupt_cfg.h_lactive = val->active_low; + ctrl1.drdy_pulsed = ~val->drdy_latched; + + interrupt_cfg.interrupts_enable = val->enable; + + ret += lis2du12_write_reg(ctx, LIS2DU12_INTERRUPT_CFG, + (uint8_t*)&interrupt_cfg, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); + + return ret; +} + +/** + * @brief Interrupt pins hardware signal configuration.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val the pins hardware signal settings.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_interrupt_mode_get(stmdev_ctx_t *ctx, + lis2du12_int_mode_t *val) +{ + lis2du12_interrupt_cfg_t interrupt_cfg; + lis2du12_ctrl1_t ctrl1; + int32_t ret; + + ret = lis2du12_read_reg(ctx, LIS2DU12_INTERRUPT_CFG, + (uint8_t*)&interrupt_cfg, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); + + val->active_low = interrupt_cfg.h_lactive; + val->drdy_latched = ~ctrl1.drdy_pulsed; + val->enable = interrupt_cfg.interrupts_enable; + + switch ( (interrupt_cfg.lir << 1) | interrupt_cfg.int_short_en ) { + case LIS2DU12_INT_LEVEL: + val->base_sig = LIS2DU12_INT_LEVEL; + break; + case LIS2DU12_INT_LATCHED: + val->base_sig = LIS2DU12_INT_LATCHED; + break; + default: + val->base_sig = LIS2DU12_INT_LEVEL; + break; + } + return ret; +} + +/** + * @brief Route interrupt signals on int1 pin.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val the signals to route on int1 pin.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_pin_int1_route_set(stmdev_ctx_t *ctx, + lis2du12_pin_int_route_t *val) +{ + lis2du12_interrupt_cfg_t interrupt_cfg; + lis2du12_md1_cfg_t md1_cfg; + lis2du12_ctrl2_t ctrl2; + int32_t ret; + + ret = lis2du12_read_reg(ctx, LIS2DU12_INTERRUPT_CFG, + (uint8_t*)&interrupt_cfg, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_MD1_CFG, (uint8_t*)&md1_cfg, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL2, (uint8_t*)&ctrl2, 1); + + ctrl2.int1_boot = val->boot; + ctrl2.int1_drdy = val->drdy_xl; + ctrl2.int1_f_fth = val->fifo_th; + ctrl2.int1_f_ovr = val->fifo_ovr; + ctrl2.int1_f_full = val->fifo_full; + + md1_cfg.int1_double_tap = val->double_tap; + md1_cfg.int1_6d = val->six_d; + md1_cfg.int1_wu = val->wake_up; + md1_cfg.int1_ff = val->free_fall; + md1_cfg.int1_single_tap = val->single_tap; + + if ( val->sleep_state == 1U) { + interrupt_cfg.sleep_status_on_int = PROPERTY_ENABLE; + md1_cfg.int1_sleep_change = PROPERTY_ENABLE; + } + if ( val->sleep_change == 1U) { + interrupt_cfg.sleep_status_on_int = PROPERTY_DISABLE; + md1_cfg.int1_sleep_change = PROPERTY_ENABLE; + } + + ret += lis2du12_write_reg(ctx, LIS2DU12_INTERRUPT_CFG, + (uint8_t*)&interrupt_cfg, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_MD1_CFG, (uint8_t*)&md1_cfg, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL2, (uint8_t*)&ctrl2, 1); + + return ret; +} + +/** + * @brief Route interrupt signals on int1 pin.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val the signals that are routed on int1 pin.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_pin_int1_route_get(stmdev_ctx_t *ctx, + lis2du12_pin_int_route_t *val) +{ + lis2du12_interrupt_cfg_t interrupt_cfg; + lis2du12_md1_cfg_t md1_cfg; + lis2du12_ctrl2_t ctrl2; + int32_t ret; + + ret = lis2du12_read_reg(ctx, LIS2DU12_INTERRUPT_CFG, + (uint8_t*)&interrupt_cfg, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_MD1_CFG, (uint8_t*)&md1_cfg, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL2, (uint8_t*)&ctrl2, 1); + + val->boot = ctrl2.int1_boot; + val->drdy_xl = ctrl2.int1_drdy; + val->fifo_th = ctrl2.int1_f_fth; + val->fifo_ovr = ctrl2.int1_f_ovr; + val->fifo_full = ctrl2.int1_f_full; + + val->double_tap = md1_cfg.int1_double_tap; + val->six_d = md1_cfg.int1_6d; + val->wake_up = md1_cfg.int1_wu; + val->free_fall = md1_cfg.int1_ff; + val->single_tap = md1_cfg.int1_single_tap; + + val->sleep_state = interrupt_cfg.sleep_status_on_int; + + if (val->sleep_state == PROPERTY_DISABLE) { + val->sleep_change = md1_cfg.int1_sleep_change; + } + else { + val->sleep_change = PROPERTY_DISABLE; + } + + return ret; +} + +/** + * @brief Route interrupt signals on int2 pin.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val the signals to route on int2 pin.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_pin_int2_route_set(stmdev_ctx_t *ctx, + lis2du12_pin_int_route_t *val) +{ + lis2du12_interrupt_cfg_t interrupt_cfg; + lis2du12_md2_cfg_t md2_cfg; + lis2du12_ctrl3_t ctrl3; + int32_t ret; + + ret = lis2du12_read_reg(ctx, LIS2DU12_INTERRUPT_CFG, + (uint8_t*)&interrupt_cfg, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t*)&md2_cfg, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL3, (uint8_t*)&ctrl3, 1); + + ctrl3.int2_boot = val->boot; + ctrl3.int2_drdy = val->drdy_xl; + ctrl3.int2_f_fth = val->fifo_th; + ctrl3.int2_f_ovr = val->fifo_ovr; + ctrl3.int2_f_full = val->fifo_full; + + md2_cfg.int2_double_tap = val->double_tap; + md2_cfg.int2_6d = val->six_d; + md2_cfg.int2_wu = val->wake_up; + md2_cfg.int2_ff = val->free_fall; + md2_cfg.int2_single_tap = val->single_tap; + + if ( val->sleep_state == 1U) { + interrupt_cfg.sleep_status_on_int = PROPERTY_ENABLE; + md2_cfg.int2_sleep_change = PROPERTY_ENABLE; + } + if ( val->sleep_change == 1U) { + interrupt_cfg.sleep_status_on_int = PROPERTY_DISABLE; + md2_cfg.int2_sleep_change = PROPERTY_ENABLE; + } + + ret += lis2du12_write_reg(ctx, LIS2DU12_INTERRUPT_CFG, + (uint8_t*)&interrupt_cfg, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t*)&md2_cfg, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL3, (uint8_t*)&ctrl3, 1); + + return ret; +} + +/** + * @brief Route interrupt signals on int2 pin.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val the signals that are routed on int2 pin.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_pin_int2_route_get(stmdev_ctx_t *ctx, + lis2du12_pin_int_route_t *val) +{ + lis2du12_interrupt_cfg_t interrupt_cfg; + lis2du12_md2_cfg_t md2_cfg; + lis2du12_ctrl3_t ctrl3; + int32_t ret; + + ret = lis2du12_read_reg(ctx, LIS2DU12_INTERRUPT_CFG, + (uint8_t*)&interrupt_cfg, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t*)&md2_cfg, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL3, (uint8_t*)&ctrl3, 1); + + val->boot = ctrl3.int2_boot; + val->drdy_xl = ctrl3.int2_drdy; + val->fifo_th = ctrl3.int2_f_fth; + val->fifo_ovr = ctrl3.int2_f_ovr; + val->fifo_full = ctrl3.int2_f_full; + + val->double_tap = md2_cfg.int2_double_tap; + val->six_d = md2_cfg.int2_6d; + val->wake_up = md2_cfg.int2_wu; + val->free_fall = md2_cfg.int2_ff; + val->single_tap = md2_cfg.int2_single_tap; + + val->sleep_state = interrupt_cfg.sleep_status_on_int; + + if (val->sleep_state == PROPERTY_DISABLE) { + val->sleep_change = md2_cfg.int2_sleep_change; + } + else { + val->sleep_change = PROPERTY_DISABLE; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Wakeup functions + * @brief This section groups all the functions concerning + * the wake up functionality. + * @{ + * + */ + +/** + * @brief Configuration of Wake-up and Wake-up to Sleep .[set] + * + * @param ctx communication interface handler.(ptr) + * @param val parameters of configuration.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_wake_up_mode_set(stmdev_ctx_t *ctx, lis2du12_wkup_md_t *val) +{ + lis2du12_interrupt_cfg_t interrupt_cfg; + lis2du12_wake_up_ths_t wake_up_ths; + lis2du12_wake_up_dur_t wake_up_dur; + lis2du12_md1_cfg_t md1_cfg; + lis2du12_ctrl1_t ctrl1; + lis2du12_ctrl4_t ctrl4; + int32_t ret; + + ret = lis2du12_read_reg(ctx, LIS2DU12_INTERRUPT_CFG, + (uint8_t*)&interrupt_cfg, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_WAKE_UP_THS, + (uint8_t*)&wake_up_ths, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_WAKE_UP_DUR, + (uint8_t*)&wake_up_dur, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_MD1_CFG, (uint8_t*)&md1_cfg, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL4, (uint8_t*)&ctrl4, 1); + + ctrl1.wu_z_en = val->z_en; + ctrl1.wu_y_en = val->y_en; + ctrl1.wu_x_en = val->x_en; + + if (val->threshold > 63U) { + interrupt_cfg.wake_ths_w = PROPERTY_ENABLE; + wake_up_ths.wk_ths = val->threshold / 4U; + } + else { + interrupt_cfg.wake_ths_w = PROPERTY_DISABLE; + wake_up_ths.wk_ths = val->threshold; + } + + if (val->duration > 3U) { + md1_cfg.wu_dur_x4 = PROPERTY_ENABLE; + wake_up_dur.wake_dur = val->duration / 4U; + } + else { + md1_cfg.wu_dur_x4 = PROPERTY_DISABLE; + wake_up_dur.wake_dur = val->duration; + } + + wake_up_ths.sleep_on = val->sleep.en; + ctrl4.inact_odr = (uint8_t)val->sleep.odr; + wake_up_dur.sleep_dur = val->sleep.duration; + + ret += lis2du12_write_reg(ctx, LIS2DU12_INTERRUPT_CFG, + (uint8_t*)&interrupt_cfg, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_WAKE_UP_THS, + (uint8_t*)&wake_up_ths, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_WAKE_UP_DUR, + (uint8_t*)&wake_up_dur, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_MD1_CFG, (uint8_t*)&md1_cfg, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); + + return ret; +} + +/** + * @brief Configuration of Wake-up and Wake-up to Sleep.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val retrieve the parameters of configuration.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_wake_up_mode_get(stmdev_ctx_t *ctx, lis2du12_wkup_md_t *val) +{ + lis2du12_interrupt_cfg_t interrupt_cfg; + lis2du12_wake_up_ths_t wake_up_ths; + lis2du12_wake_up_dur_t wake_up_dur; + lis2du12_md1_cfg_t md1_cfg; + lis2du12_ctrl1_t ctrl1; + lis2du12_ctrl4_t ctrl4; + int32_t ret; + + ret = lis2du12_read_reg(ctx, LIS2DU12_INTERRUPT_CFG, + (uint8_t*)&interrupt_cfg, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_WAKE_UP_THS, + (uint8_t*)&wake_up_ths, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_WAKE_UP_DUR, + (uint8_t*)&wake_up_dur, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_MD1_CFG, (uint8_t*)&md1_cfg, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL4, (uint8_t*)&ctrl4, 1); + + val->z_en = ctrl1.wu_z_en; + val->y_en = ctrl1.wu_y_en; + val->x_en = ctrl1.wu_x_en; + + if (interrupt_cfg.wake_ths_w == PROPERTY_ENABLE) { + val->threshold = wake_up_ths.wk_ths * 4U; + } + else { + val->threshold = wake_up_ths.wk_ths; + } + + if (md1_cfg.wu_dur_x4 == PROPERTY_ENABLE) { + val->duration = wake_up_dur.wake_dur * 4U; + } + else { + val->duration = wake_up_dur.wake_dur; + } + + val->sleep.en = wake_up_ths.sleep_on; + val->sleep.duration = wake_up_dur.sleep_dur; + + switch ( ctrl4.inact_odr ) { + case LIS2DU12_DO_NOT_CHANGE: + val->sleep.odr = LIS2DU12_DO_NOT_CHANGE; + break; + case LIS2DU12_SLEEP_AT_6Hz: + val->sleep.odr = LIS2DU12_SLEEP_AT_6Hz; + break; + case LIS2DU12_SLEEP_AT_3Hz: + val->sleep.odr = LIS2DU12_SLEEP_AT_3Hz; + break; + case LIS2DU12_SLEEP_AT_1Hz5: + val->sleep.odr = LIS2DU12_SLEEP_AT_1Hz5; + break; + default: + val->sleep.odr = LIS2DU12_DO_NOT_CHANGE; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Tap functions + * @brief This section groups all the functions concerning + * the single/double tap functionality. + * @{ + * + */ + +/** + * @brief Configuration of Single and Double Tap.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val parameters of configuration.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_tap_mode_set(stmdev_ctx_t *ctx, lis2du12_tap_md_t *val) +{ + lis2du12_wake_up_ths_t wake_up_ths; + lis2du12_tap_ths_x_t tap_ths_x; + lis2du12_tap_ths_y_t tap_ths_y; + lis2du12_tap_ths_z_t tap_ths_z; + lis2du12_int_dur_t int_dur; + int32_t ret; + + ret = lis2du12_read_reg(ctx, LIS2DU12_WAKE_UP_THS, + (uint8_t*)&wake_up_ths, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_X, + (uint8_t*)&tap_ths_x, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_Y, (uint8_t*)&tap_ths_y, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_Z, (uint8_t*)&tap_ths_z, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_INT_DUR, (uint8_t*)&int_dur, 1); + + tap_ths_z.tap_z_en = val->z_en; + tap_ths_z.tap_y_en = val->y_en; + tap_ths_z.tap_x_en = val->x_en; + + tap_ths_x.tap_ths_x = val->threshold.x; + tap_ths_y.tap_ths_y = val->threshold.y; + tap_ths_z.tap_ths_z = val->threshold.z; + + int_dur.shock = val->shock; + int_dur.quiet = val->quiet; + + tap_ths_y.tap_priority = (uint8_t)val->priority; + + wake_up_ths.single_double_tap = val->tap_double.en; + int_dur.latency = val->tap_double.latency; + + ret += lis2du12_write_reg(ctx, LIS2DU12_WAKE_UP_THS, + (uint8_t*)&wake_up_ths, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_TAP_THS_X, (uint8_t*)&tap_ths_x, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_TAP_THS_Y, (uint8_t*)&tap_ths_y, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_TAP_THS_Z, (uint8_t*)&tap_ths_z, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_INT_DUR, (uint8_t*)&int_dur, 1); + + return ret; +} + +/** + * @brief Configuration of Single and Double Tap.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val retrieve the parameters of configuration.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_tap_mode_get(stmdev_ctx_t *ctx, lis2du12_tap_md_t *val) +{ + lis2du12_wake_up_ths_t wake_up_ths; + lis2du12_tap_ths_x_t tap_ths_x; + lis2du12_tap_ths_y_t tap_ths_y; + lis2du12_tap_ths_z_t tap_ths_z; + lis2du12_int_dur_t int_dur; + int32_t ret; + + ret = lis2du12_read_reg(ctx, LIS2DU12_WAKE_UP_THS, + (uint8_t*)&wake_up_ths, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_X, (uint8_t*)&tap_ths_x, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_Y, (uint8_t*)&tap_ths_y, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_Z, (uint8_t*)&tap_ths_z, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_INT_DUR, (uint8_t*)&int_dur, 1); + + val->z_en = tap_ths_z.tap_z_en; + val->y_en = tap_ths_z.tap_y_en; + val->x_en = tap_ths_z.tap_x_en; + + val->threshold.x = tap_ths_x.tap_ths_x; + val->threshold.y = tap_ths_y.tap_ths_y; + val->threshold.z = tap_ths_z.tap_ths_z; + + val->shock = int_dur.shock; + val->quiet = int_dur.quiet; + + switch ( tap_ths_y.tap_priority ) { + case LIS2DU12_XYZ: + val->priority = LIS2DU12_XYZ; + break; + case LIS2DU12_YXZ: + val->priority = LIS2DU12_YXZ; + break; + case LIS2DU12_XZY: + val->priority = LIS2DU12_XZY; + break; + case LIS2DU12_ZYX: + val->priority = LIS2DU12_ZYX; + break; + case LIS2DU12_YZX: + val->priority = LIS2DU12_YZX; + break; + case LIS2DU12_ZXY: + val->priority = LIS2DU12_ZXY; + break; + default: + val->priority = LIS2DU12_XYZ; + break; + } + + val->tap_double.en = wake_up_ths.single_double_tap; + val->tap_double.latency = int_dur.latency; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Free Fall Configuration + * @brief This section groups all the functions concerning + * the free fall functionality. + * @{ + * + */ + +/** + * @brief Configuration Free Fall.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val parameters of configuration.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_free_fall_mode_set(stmdev_ctx_t *ctx, lis2du12_ff_md_t *val) +{ + lis2du12_wake_up_dur_t wake_up_dur; + lis2du12_free_fall_t free_fall; + int32_t ret; + + ret = lis2du12_read_reg(ctx, LIS2DU12_WAKE_UP_DUR, + (uint8_t*)&wake_up_dur, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_FREE_FALL, (uint8_t*)&free_fall, 1); + + wake_up_dur.ff_dur = val->duration & 0x1FU; + free_fall.ff_dur = (val->duration) & 0x20U >> 5; + + free_fall.ff_ths = (uint8_t)val->threshold; + + ret += lis2du12_write_reg(ctx, LIS2DU12_WAKE_UP_DUR, + (uint8_t*)&wake_up_dur, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_FREE_FALL, (uint8_t*)&free_fall, 1); + + return ret; +} + +/** + * @brief Configuration Free Fall.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val retrieve the parameters of configuration.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_free_fall_mode_get(stmdev_ctx_t *ctx, lis2du12_ff_md_t *val) +{ + lis2du12_wake_up_dur_t wake_up_dur; + lis2du12_free_fall_t free_fall; + int32_t ret; + + ret = lis2du12_read_reg(ctx, LIS2DU12_WAKE_UP_DUR, + (uint8_t*)&wake_up_dur, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_FREE_FALL, (uint8_t*)&free_fall, 1); + + val->duration = (free_fall.ff_dur * 32U) + wake_up_dur.ff_dur; + + switch ( free_fall.ff_ths ) { + case LIS2DU12_156mg: + val->threshold = LIS2DU12_156mg; + break; + case LIS2DU12_219mg: + val->threshold = LIS2DU12_219mg; + break; + case LIS2DU12_250mg: + val->threshold = LIS2DU12_250mg; + break; + case LIS2DU12_312mg: + val->threshold = LIS2DU12_312mg; + break; + case LIS2DU12_344mg: + val->threshold = LIS2DU12_344mg; + break; + case LIS2DU12_406mg: + val->threshold = LIS2DU12_406mg; + break; + case LIS2DU12_469mg: + val->threshold = LIS2DU12_469mg; + break; + case LIS2DU12_500mg: + val->threshold = LIS2DU12_500mg; + break; + default: + val->threshold = LIS2DU12_156mg; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Orientation 6D functions + * @brief This section groups all the functions concerning + * the 6/4D orientation functionality. + * @{ + * + */ + +/** + * @brief Configuration of detection 6D or 4D orientation.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val parameters of configuration.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_orientation_mode_set(stmdev_ctx_t *ctx, + lis2du12_orient_md_t *val) +{ + lis2du12_tap_ths_x_t tap_ths_x; + int32_t ret; + + ret = lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_X, (uint8_t*)&tap_ths_x, 1); + + tap_ths_x.d6d_ths = (uint8_t)val->threshold; + tap_ths_x.d4d_en = (uint8_t)val->deg_of_freedom; + + ret += lis2du12_write_reg(ctx, LIS2DU12_TAP_THS_X, (uint8_t*)&tap_ths_x, 1); + + return ret; +} + +/** + * @brief Configuration of detection 6D or 4D orientation.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val retrieve the parameters of configuration.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2du12_orientation_mode_get(stmdev_ctx_t *ctx, + lis2du12_orient_md_t *val) +{ + lis2du12_tap_ths_x_t tap_ths_x; + int32_t ret; + + ret = lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_X, (uint8_t*)&tap_ths_x, 1); + + switch ( tap_ths_x.d6d_ths ) { + case LIS2DU12_DEG_80: + val->threshold = LIS2DU12_DEG_80; + break; + case LIS2DU12_DEG_70: + val->threshold = LIS2DU12_DEG_70; + break; + case LIS2DU12_DEG_60: + val->threshold = LIS2DU12_DEG_60; + break; + case LIS2DU12_DEG_50: + val->threshold = LIS2DU12_DEG_50; + break; + default: + val->threshold = LIS2DU12_DEG_80; + break; + } + + switch ( tap_ths_x.d4d_en ) { + case LIS2DU12_SIX: + val->deg_of_freedom = LIS2DU12_SIX; + break; + case LIS2DU12_FOUR: + val->deg_of_freedom = LIS2DU12_FOUR; + break; + default: + val->deg_of_freedom = LIS2DU12_SIX; + break; + } + return ret; + +} + +/** + * @} + * + */ + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis2du12_STdC/driver/lis2du12_reg.h b/sensor/stmemsc/lis2du12_STdC/driver/lis2du12_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..793630bdd80a4df2bbd7b173bd463207bf1c1097 --- /dev/null +++ b/sensor/stmemsc/lis2du12_STdC/driver/lis2du12_reg.h @@ -0,0 +1,1005 @@ +/* + ****************************************************************************** + * @file lis2du12_reg.h + * @author Sensors Software Solution Team + * @brief This file contains all the functions prototypes for the + * lis2du12_reg.c driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef LIS2DU12_REGS_H +#define LIS2DU12_REGS_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include + +/** @addtogroup LIS2DU12 + * @{ + * + */ + +/** @defgroup Endianness definitions + * @{ + * + */ + +#ifndef DRV_BYTE_ORDER +#ifndef __BYTE_ORDER__ + +#define DRV_LITTLE_ENDIAN 1234 +#define DRV_BIG_ENDIAN 4321 + +/** if _BYTE_ORDER is not defined, choose the endianness of your architecture + * by uncommenting the define which fits your platform endianness + */ +//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN +#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN + +#else /* defined __BYTE_ORDER__ */ + +#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ +#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ +#define DRV_BYTE_ORDER __BYTE_ORDER__ + +#endif /* __BYTE_ORDER__*/ +#endif /* DRV_BYTE_ORDER */ + +/** + * @} + * + */ + +/** @defgroup STMicroelectronics sensors common types + * @{ + * + */ + +#ifndef MEMS_SHARED_TYPES +#define MEMS_SHARED_TYPES + +typedef struct{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} bitwise_t; + +#define PROPERTY_DISABLE (0U) +#define PROPERTY_ENABLE (1U) + +/** @addtogroup Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); +typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); + +typedef struct +{ + /** Component mandatory fields **/ + stmdev_write_ptr write_reg; + stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; + /** Customizable optional pointer **/ + void *handle; +} stmdev_ctx_t; + +/** + * @} + * + */ + +#endif /* MEMS_SHARED_TYPES */ + +#ifndef MEMS_UCF_SHARED_TYPES +#define MEMS_UCF_SHARED_TYPES + +/** @defgroup Generic address-data structure definition + * @brief This structure is useful to load a predefined configuration + * of a sensor. + * You can create a sensor configuration by your own or using + * Unico / Unicleo tools available on STMicroelectronics + * web site. + * + * @{ + * + */ + +typedef struct { + uint8_t address; + uint8_t data; +} ucf_line_t; + +/** + * @} + * + */ + +#endif /* MEMS_UCF_SHARED_TYPES */ + +/** + * @} + * + */ + +/** @defgroup LIS2DU12_Infos + * @{ + * + */ + +/** I2C Device Address 8 bit format if SA0=0 -> 0x if SA0=1 -> 0x **/ +#define LIS2DU12_I2C_ADD_L 0x31U +#define LIS2DU12_I2C_ADD_H 0x33U + +/** Device Identification (Who am I) **/ +#define LIS2DU12_ID 0x45U + +/** + * @} + * + */ + +#define LIS2DU12_IF_PU_CTRL 0x0CU +typedef struct { +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 2; + uint8_t cs_pu_disc : 1; + uint8_t not_used_02 : 3; + uint8_t sda_pu_en : 1; + uint8_t sdo_pu_disc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sdo_pu_disc : 1; + uint8_t sda_pu_en : 1; + uint8_t not_used_02 : 3; + uint8_t cs_pu_disc : 1; + uint8_t not_used_01 : 2; +#endif /* DRV_BYTE_ORDER */ +} lis2du12_if_pu_ctrl_t; + +#define LIS2DU12_IF_CTRL 0x0EU +typedef struct { +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t i2c_disable : 1; + uint8_t i3c_disable : 1; + uint8_t pd_dis_int1 : 1; + uint8_t not_used_01 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 5; + uint8_t pd_dis_int1 : 1; + uint8_t i3c_disable : 1; + uint8_t i2c_disable : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2du12_if_ctrl_t; + +#define LIS2DU12_CTRL1 0x10U +typedef struct { +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wu_z_en : 1; + uint8_t wu_y_en : 1; + uint8_t wu_x_en : 1; + uint8_t drdy_pulsed : 1; + uint8_t if_add_inc : 1; + uint8_t sw_reset : 1; + uint8_t sim : 1; + uint8_t pp_od : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pp_od : 1; + uint8_t sim : 1; + uint8_t sw_reset : 1; + uint8_t if_add_inc : 1; + uint8_t drdy_pulsed : 1; + uint8_t wu_x_en : 1; + uint8_t wu_y_en : 1; + uint8_t wu_z_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2du12_ctrl1_t; + +#define LIS2DU12_CTRL2 0x11U +typedef struct { +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 3; + uint8_t int1_drdy : 1; + uint8_t int1_f_ovr : 1; + uint8_t int1_f_fth : 1; + uint8_t int1_f_full : 1; + uint8_t int1_boot : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_boot : 1; + uint8_t int1_f_full : 1; + uint8_t int1_f_fth : 1; + uint8_t int1_f_ovr : 1; + uint8_t int1_drdy : 1; + uint8_t not_used_01 : 3; +#endif /* DRV_BYTE_ORDER */ +} lis2du12_ctrl2_t; + +#define LIS2DU12_CTRL3 0x12U +typedef struct { +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t st : 2; + uint8_t not_used_01 : 1; + uint8_t int2_drdy : 1; + uint8_t int2_f_ovr : 1; + uint8_t int2_f_fth : 1; + uint8_t int2_f_full : 1; + uint8_t int2_boot : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_boot : 1; + uint8_t int2_f_full : 1; + uint8_t int2_f_fth : 1; + uint8_t int2_f_ovr : 1; + uint8_t int2_drdy : 1; + uint8_t not_used_01 : 1; + uint8_t st : 2; +#endif /* DRV_BYTE_ORDER */ +} lis2du12_ctrl3_t; + +#define LIS2DU12_CTRL4 0x13U +typedef struct { +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t boot : 1; + uint8_t soc : 1; + uint8_t not_used_01 : 3; + uint8_t bdu : 1; + uint8_t inact_odr : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t inact_odr : 2; + uint8_t bdu : 1; + uint8_t not_used_01 : 3; + uint8_t soc : 1; + uint8_t boot : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2du12_ctrl4_t; + +#define LIS2DU12_CTRL5 0x14U +typedef struct { +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs : 2; + uint8_t bw : 2; + uint8_t odr : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t odr : 4; + uint8_t bw : 2; + uint8_t fs : 2; +#endif /* DRV_BYTE_ORDER */ +} lis2du12_ctrl5_t; + +#define LIS2DU12_FIFO_CTRL 0x15U +typedef struct { +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t f_mode : 3; + uint8_t stop_on_fth : 1; + uint8_t not_used_01 : 2; + uint8_t fifo_depth : 1; + uint8_t rounding_xyz : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t rounding_xyz : 1; + uint8_t fifo_depth : 1; + uint8_t not_used_01 : 2; + uint8_t stop_on_fth : 1; + uint8_t f_mode : 3; +#endif /* DRV_BYTE_ORDER */ +} lis2du12_fifo_ctrl_t; + +#define LIS2DU12_FIFO_WTM 0x16U +typedef struct { +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fth : 7; + uint8_t not_used_01 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 1; + uint8_t fth : 7; +#endif /* DRV_BYTE_ORDER */ +} lis2du12_fifo_wtm_t; + +#define LIS2DU12_INTERRUPT_CFG 0x17U +typedef struct { +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t interrupts_enable : 1; + uint8_t lir : 1; + uint8_t h_lactive : 1; + uint8_t sleep_status_on_int : 1; + uint8_t not_used_01 : 1; + uint8_t wake_ths_w : 1; + uint8_t int_short_en : 1; + uint8_t not_used_02 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 1; + uint8_t int_short_en : 1; + uint8_t wake_ths_w : 1; + uint8_t not_used_01 : 1; + uint8_t sleep_status_on_int : 1; + uint8_t h_lactive : 1; + uint8_t lir : 1; + uint8_t interrupts_enable : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2du12_interrupt_cfg_t; + +#define LIS2DU12_TAP_THS_X 0x18U +typedef struct { +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tap_ths_x : 5; + uint8_t d6d_ths : 2; + uint8_t d4d_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t d4d_en : 1; + uint8_t d6d_ths : 2; + uint8_t tap_ths_x : 5; +#endif /* DRV_BYTE_ORDER */ +} lis2du12_tap_ths_x_t; + +#define LIS2DU12_TAP_THS_Y 0x19U +typedef struct { +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tap_ths_y : 5; + uint8_t tap_priority : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tap_priority : 3; + uint8_t tap_ths_y : 5; +#endif /* DRV_BYTE_ORDER */ +} lis2du12_tap_ths_y_t; + +#define LIS2DU12_TAP_THS_Z 0x1AU +typedef struct { +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tap_ths_z : 5; + uint8_t tap_z_en : 1; + uint8_t tap_y_en : 1; + uint8_t tap_x_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tap_x_en : 1; + uint8_t tap_y_en : 1; + uint8_t tap_z_en : 1; + uint8_t tap_ths_z : 5; +#endif /* DRV_BYTE_ORDER */ +} lis2du12_tap_ths_z_t; + +#define LIS2DU12_INT_DUR 0x1BU +typedef struct { +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t shock : 2; + uint8_t quiet : 2; + uint8_t latency : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t latency : 4; + uint8_t quiet : 2; + uint8_t shock : 2; +#endif /* DRV_BYTE_ORDER */ +} lis2du12_int_dur_t; + +#define LIS2DU12_WAKE_UP_THS 0x1CU +typedef struct { +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wk_ths : 6; + uint8_t sleep_on : 1; + uint8_t single_double_tap : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t single_double_tap : 1; + uint8_t sleep_on : 1; + uint8_t wk_ths : 6; +#endif /* DRV_BYTE_ORDER */ +} lis2du12_wake_up_ths_t; + +#define LIS2DU12_WAKE_UP_DUR 0x1DU +typedef struct { +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sleep_dur : 4; + uint8_t not_used_01 : 1; + uint8_t wake_dur : 2; + uint8_t ff_dur : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ff_dur : 1; + uint8_t wake_dur : 2; + uint8_t not_used_01 : 1; + uint8_t sleep_dur : 4; +#endif /* DRV_BYTE_ORDER */ +} lis2du12_wake_up_dur_t; + +#define LIS2DU12_FREE_FALL 0x1EU +typedef struct { +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ff_ths : 3; + uint8_t ff_dur : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ff_dur : 5; + uint8_t ff_ths : 3; +#endif /* DRV_BYTE_ORDER */ +} lis2du12_free_fall_t; + +#define LIS2DU12_MD1_CFG 0x1FU +typedef struct { +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 1; + uint8_t wu_dur_x4 : 1; + uint8_t int1_6d : 1; + uint8_t int1_double_tap : 1; + uint8_t int1_ff : 1; + uint8_t int1_wu : 1; + uint8_t int1_single_tap : 1; + uint8_t int1_sleep_change : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_sleep_change : 1; + uint8_t int1_single_tap : 1; + uint8_t int1_wu : 1; + uint8_t int1_ff : 1; + uint8_t int1_double_tap : 1; + uint8_t int1_6d : 1; + uint8_t wu_dur_x4 : 1; + uint8_t not_used_01 : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2du12_md1_cfg_t; + +#define LIS2DU12_MD2_CFG 0x20U +typedef struct { +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 1; + uint8_t pd_dis_int2 : 1; + uint8_t int2_6d : 1; + uint8_t int2_double_tap : 1; + uint8_t int2_ff : 1; + uint8_t int2_wu : 1; + uint8_t int2_single_tap : 1; + uint8_t int2_sleep_change : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_sleep_change : 1; + uint8_t int2_single_tap : 1; + uint8_t int2_wu : 1; + uint8_t int2_ff : 1; + uint8_t int2_double_tap : 1; + uint8_t int2_6d : 1; + uint8_t pd_dis_int2 : 1; + uint8_t not_used_01 : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2du12_md2_cfg_t; + +#define LIS2DU12_WAKE_UP_SRC 0x21U +typedef struct { +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t z_wu : 1; + uint8_t y_wu : 1; + uint8_t x_wu : 1; + uint8_t wu_ia : 1; + uint8_t sleep_state : 1; + uint8_t ff_ia : 1; + uint8_t sleep_change_ia : 1; + uint8_t not_used_01 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 1; + uint8_t sleep_change_ia : 1; + uint8_t ff_ia : 1; + uint8_t sleep_state : 1; + uint8_t wu_ia : 1; + uint8_t x_wu : 1; + uint8_t y_wu : 1; + uint8_t z_wu : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2du12_wake_up_src_t; + +#define LIS2DU12_TAP_SRC 0x22U +typedef struct { +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t z_tap : 1; + uint8_t y_tap : 1; + uint8_t x_tap : 1; + uint8_t tap_sign : 1; + uint8_t double_tap_ia : 1; + uint8_t single_tap_ia : 1; + uint8_t tap_ia : 1; + uint8_t not_used_01 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 1; + uint8_t tap_ia : 1; + uint8_t single_tap_ia : 1; + uint8_t double_tap_ia : 1; + uint8_t tap_sign : 1; + uint8_t x_tap : 1; + uint8_t y_tap : 1; + uint8_t z_tap : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2du12_tap_src_t; + +#define LIS2DU12_SIXD_SRC 0x23U +typedef struct { +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xl : 1; + uint8_t xh : 1; + uint8_t yl : 1; + uint8_t yh : 1; + uint8_t zl : 1; + uint8_t zh : 1; + uint8_t d6d_ia : 1; + uint8_t not_used_01 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 1; + uint8_t d6d_ia : 1; + uint8_t zh : 1; + uint8_t zl : 1; + uint8_t yh : 1; + uint8_t yl : 1; + uint8_t xh : 1; + uint8_t xl : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2du12_sixd_src_t; + +#define LIS2DU12_ALL_INT_SRC 0x24U +typedef struct { +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ff_ia_all : 1; + uint8_t wu_ia_all : 1; + uint8_t single_tap_all : 1; + uint8_t double_tap_all : 1; + uint8_t d6d_ia_all : 1; + uint8_t sleep_change_ia_all : 1; + uint8_t int_global : 1; + uint8_t not_used_01 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 1; + uint8_t int_global : 1; + uint8_t sleep_change_ia_all : 1; + uint8_t d6d_ia_all : 1; + uint8_t double_tap_all : 1; + uint8_t single_tap_all : 1; + uint8_t wu_ia_all : 1; + uint8_t ff_ia_all : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2du12_all_int_src_t; + +#define LIS2DU12_STATUS 0x25U +typedef struct { +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t drdy : 1; + uint8_t pd_status : 1; + uint8_t not_used_01 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 6; + uint8_t pd_status : 1; + uint8_t drdy : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2du12_status_register_t; + +#define LIS2DU12_FIFO_STATUS1 0x26U +typedef struct { +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 6; + uint8_t fifo_ovr : 1; + uint8_t fth : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fth : 1; + uint8_t fifo_ovr : 1; + uint8_t not_used_01 : 6; +#endif /* DRV_BYTE_ORDER */ +} lis2du12_fifo_status1_t; + +#define LIS2DU12_FIFO_STATUS2 0x27U +typedef struct { + uint8_t fss : 8; +} lis2du12_fifo_status2_t; + +#define LIS2DU12_OUTX_L 0x28U +#define LIS2DU12_OUTX_H 0x29U +#define LIS2DU12_OUTY_L 0x2AU +#define LIS2DU12_OUTY_H 0x2BU +#define LIS2DU12_OUTZ_L 0x2CU +#define LIS2DU12_OUTZ_H 0x2DU +#define LIS2DU12_OUTT_L 0x2EU +#define LIS2DU12_OUTT_H 0x2FU +#define LIS2DU12_TEMP_OUT_L 0x30U +#define LIS2DU12_TEMP_OUT_H 0x31U +#define LIS2DU12_WHO_AM_I 0x43U + +#define LIS2DU12_ST_SIGN 0x58U +typedef struct { +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 5; + uint8_t stsign : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t stsign : 3; + uint8_t not_used_01 : 5; +#endif /* DRV_BYTE_ORDER */ +} lis2du12_st_sign_t; + +/** + * @defgroup LIS2DU12_Register_Union + * @brief This union group all the registers that has a bitfield + * description. + * This union is useful but not need by the driver. + * + * REMOVING this union you are compliant with: + * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " + * + * @{ + * + */ + +typedef union{ + lis2du12_if_pu_ctrl_t if_pu_ctrl; + lis2du12_if_ctrl_t if_ctrl; + lis2du12_ctrl1_t ctrl1; + lis2du12_ctrl2_t ctrl2; + lis2du12_ctrl3_t ctrl3; + lis2du12_ctrl4_t ctrl4; + lis2du12_ctrl5_t ctrl5; + lis2du12_fifo_ctrl_t fifo_ctrl; + lis2du12_fifo_wtm_t fifo_wtm; + lis2du12_interrupt_cfg_t interrupt_cfg; + lis2du12_tap_ths_x_t tap_ths_x; + lis2du12_tap_ths_y_t tap_ths_y; + lis2du12_tap_ths_z_t tap_ths_z; + lis2du12_int_dur_t int_dur; + lis2du12_wake_up_ths_t wake_up_ths; + lis2du12_wake_up_dur_t wake_up_dur; + lis2du12_free_fall_t free_fall; + lis2du12_md1_cfg_t md1_cfg; + lis2du12_md2_cfg_t md2_cfg; + lis2du12_wake_up_src_t wake_up_src; + lis2du12_tap_src_t tap_src; + lis2du12_sixd_src_t sixd_src; + lis2du12_all_int_src_t all_int_src; + lis2du12_status_register_t status_register; + lis2du12_fifo_status1_t fifo_status1; + lis2du12_fifo_status2_t fifo_status2; + bitwise_t bitwise; + uint8_t byte; +} lis2du12_reg_t; + +/** + * @} + * + */ + +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + +int32_t lis2du12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data, + uint16_t len); +int32_t lis2du12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data, + uint16_t len); + +float_t lis2du12_from_fs2g_to_mg(int16_t lsb); +float_t lis2du12_from_fs4g_to_mg(int16_t lsb); +float_t lis2du12_from_fs8g_to_mg(int16_t lsb); +float_t lis2du12_from_fs16g_to_mg(int16_t lsb); +float_t lis2du12_from_lsb_to_celsius(int16_t lsb); + +typedef struct { + uint8_t whoami; +} lis2du12_id_t; +int32_t lis2du12_id_get(stmdev_ctx_t *ctx, lis2du12_id_t *val); + +typedef enum { + LIS2DU12_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */ + LIS2DU12_SPI_4W = 0x03, /* Only SPI: SDO / SDI separated pins */ + LIS2DU12_SPI_3W = 0x07, /* Only SPI: SDO / SDI share the same pin */ + LIS2DU12_I3C_DISABLE = 0x01, /* Select by HW (SPI 3W and I3C disable) */ +} lis2du12_bus_mode_t; +int32_t lis2du12_bus_mode_set(stmdev_ctx_t *ctx, lis2du12_bus_mode_t val); +int32_t lis2du12_bus_mode_get(stmdev_ctx_t *ctx, lis2du12_bus_mode_t *val); + +typedef enum { + LIS2DU12_DRV_RDY = 0x00, /* Initialize the device for driver usage */ + LIS2DU12_BOOT = 0x01, /* Restore calib. param. ( it takes 10ms ) */ + LIS2DU12_RESET = 0x02, /* Reset configuration registers */ +} lis2du12_init_t; +int32_t lis2du12_init_set(stmdev_ctx_t *ctx, lis2du12_init_t val); + +typedef struct { + uint8_t sw_reset : 1; /* Restoring configuration registers */ + uint8_t boot : 1; /* Restoring calibration parameters */ + uint8_t drdy_xl : 1; /* Accelerometer data ready */ + uint8_t power_down : 1; /* Monitors power-down. */ +} lis2du12_status_t; +int32_t lis2du12_status_get(stmdev_ctx_t *ctx, lis2du12_status_t *val); + +typedef struct { + uint8_t sdo_pull_up : 1; /* 1 = pull up enable */ + uint8_t sda_pull_up : 1; /* 1 = pull up enable */ + uint8_t cs_pull_up : 1; /* 1 = pull up enable */ + uint8_t int1_int2_push_pull : 1; /* 1 = push-pull / 0 = open-drain*/ + uint8_t int1_pull_down : 1; /* 1 = pull-down always disabled (0=auto) */ + uint8_t int2_pull_down : 1; /* 1 = pull-down always disabled (0=auto) */ +} lis2du12_pin_conf_t; +int32_t lis2du12_pin_conf_set(stmdev_ctx_t *ctx, lis2du12_pin_conf_t *val); +int32_t lis2du12_pin_conf_get(stmdev_ctx_t *ctx, lis2du12_pin_conf_t *val); + +typedef struct { + uint8_t free_fall : 1; /* free fall event */ + uint8_t wake_up : 1; /* wake up event */ + uint8_t wake_up_z : 1; /* wake up on Z axis event */ + uint8_t wake_up_y : 1; /* wake up on Y axis event */ + uint8_t wake_up_x : 1; /* wake up on X axis event */ + uint8_t single_tap : 1; /* single-tap event */ + uint8_t double_tap : 1; /* double-tap event */ + uint8_t tap_z : 1; /* single-tap on Z axis event */ + uint8_t tap_y : 1; /* single-tap on Y axis event */ + uint8_t tap_x : 1; /* single-tap on X axis event */ + uint8_t tap_sign : 1; /* sign of tap event (0-pos / 1-neg) */ + uint8_t six_d : 1; /* orientation change (6D/4D detection) */ + uint8_t six_d_xl : 1; /* X-axis low 6D/4D event (under threshold) */ + uint8_t six_d_xh : 1; /* X-axis high 6D/4D event (over threshold) */ + uint8_t six_d_yl : 1; /* Y-axis low 6D/4D event (under threshold) */ + uint8_t six_d_yh : 1; /* Y-axis high 6D/4D event (over threshold) */ + uint8_t six_d_zl : 1; /* Z-axis low 6D/4D event (under threshold) */ + uint8_t six_d_zh : 1; /* Z-axis high 6D/4D event (over threshold) */ + uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ + uint8_t sleep_state : 1; /* Act/Inact status flag (0-Act / 1-Inact) */ +} lis2du12_all_sources_t; +int32_t lis2du12_all_sources_get(stmdev_ctx_t *ctx, + lis2du12_all_sources_t *val); + +typedef struct { + enum { + LIS2DU12_OFF = 0x00, /* in power down */ + LIS2DU12_1Hz5_ULP = 0x01, /* @1Hz6 (low power) */ + LIS2DU12_3Hz_ULP = 0x02, /* @1Hz6 (ultra low/Gy, OIS imu off) */ + LIS2DU12_6Hz_ULP = 0x03, /* @12Hz5 (high performance) */ + LIS2DU12_6Hz = 0x04, /* @12Hz5 (low power) */ + LIS2DU12_12Hz5 = 0x05, /* @12Hz5 (ultra low/Gy, OIS imu off) */ + LIS2DU12_25Hz = 0x06, /* @26Hz (high performance) */ + LIS2DU12_50Hz = 0x07, /* @26Hz (low power) */ + LIS2DU12_100Hz = 0x08, /* @26Hz (ultra low/Gy, OIS imu off) */ + LIS2DU12_200Hz = 0x09, /* @52Hz (high performance) */ + LIS2DU12_400Hz = 0x0A, /* @52Hz (low power) */ + LIS2DU12_800Hz = 0x0B, /* @52Hz (ultra low/Gy, OIS imu off) */ + LIS2DU12_TRIG_PIN = 0x0E, /* Single-shot high latency by INT2 */ + LIS2DU12_TRIG_SW = 0x0F, /* Single-shot high latency by IF */ + } odr; + enum { + LIS2DU12_2g = 0, + LIS2DU12_4g = 1, + LIS2DU12_8g = 2, + LIS2DU12_16g = 3, + } fs; + enum { + LIS2DU12_ODR_div_2 = 0, + LIS2DU12_ODR_div_4 = 1, + LIS2DU12_ODR_div_8 = 2, + LIS2DU12_ODR_div_16 = 3, + } bw; +} lis2du12_md_t; +int32_t lis2du12_mode_set(stmdev_ctx_t *ctx, lis2du12_md_t *val); +int32_t lis2du12_mode_get(stmdev_ctx_t *ctx, lis2du12_md_t *val); + +int32_t lis2du12_trigger_sw(stmdev_ctx_t *ctx, lis2du12_md_t *val); + +typedef struct { + struct { + float_t mg[3]; + int16_t raw[3]; + }xl; + struct { + float_t deg_c; + int16_t raw; + }heat; +} lis2du12_data_t; +int32_t lis2du12_data_get(stmdev_ctx_t *ctx, lis2du12_md_t *md, + lis2du12_data_t *data); + +typedef enum { + LIS2DU12_ST_DISABLE = 0, + LIS2DU12_ST_POSITIVE = 6, + LIS2DU12_ST_NEGATIVE = 1, +} lis2du12_st_t; +int32_t lis2du12_self_test_sign_set(stmdev_ctx_t *ctx, lis2du12_st_t val); +int32_t lis2du12_self_test_start(stmdev_ctx_t *ctx, uint8_t val); /* valid values: 1 or 2 */ +int32_t lis2du12_self_test_stop(stmdev_ctx_t *ctx); + +typedef struct { + enum { + LIS2DU12_BYPASS = 0, + LIS2DU12_FIFO = 1, + LIS2DU12_STREAM = 6, + LIS2DU12_STREAM_TO_FIFO = 3, /* Dynamic-Stream, FIFO on Trigger */ + LIS2DU12_BYPASS_TO_STREAM = 4, /* Bypass, Dynamic-Stream on Trigger */ + LIS2DU12_BYPASS_TO_FIFO = 7, /* Bypass, FIFO on Trigger */ + } operation; + enum { + LIS2DU12_8_BIT = 0, + LIS2DU12_16_BIT = 1, + } store; + uint8_t watermark; /* (0 disable) max 127 @16bit, even and max 256 @8bit.*/ +} lis2du12_fifo_md_t; +int32_t lis2du12_fifo_mode_set(stmdev_ctx_t *ctx, lis2du12_fifo_md_t *val); +int32_t lis2du12_fifo_mode_get(stmdev_ctx_t *ctx, lis2du12_fifo_md_t *val); + +typedef struct { + uint8_t fifo_fth : 1; /* 1 = fifo threshold event */ + uint8_t fifo_ovr : 1; /* 1 = fifo overrun event */ +} lis2du12_fifo_status_t; +int32_t lis2du12_fifo_status_get(stmdev_ctx_t *ctx, lis2du12_fifo_status_t *val); + +int32_t lis2du12_fifo_level_get(stmdev_ctx_t *ctx, lis2du12_fifo_md_t *md, + uint8_t *val); + +typedef struct { + struct { + float_t mg[3]; + int16_t raw[3]; + }xl[2]; + struct { + float_t deg_c; + int16_t raw; + }heat; +} lis2du12_fifo_data_t; +int32_t lis2du12_fifo_data_get(stmdev_ctx_t *ctx, lis2du12_md_t *md, + lis2du12_fifo_md_t *fmd, + lis2du12_fifo_data_t *data); + +typedef struct { + uint8_t enable : 1; /* 1 = enabled / 0 = disabled */ + uint8_t active_low : 1; /* 1 = active low / 0 = active high */ + uint8_t drdy_latched : 1; /* drdy returns to 0 after reading data */ + enum { + LIS2DU12_INT_LEVEL = 0, /* active till event condition persist */ + LIS2DU12_INT_LATCHED = 3, /* read ALL_INT_SRC for reset (API all_sources)*/ +} base_sig; /* base functions are: FF, WU(W2S), 4/6D, Tap */ +} lis2du12_int_mode_t; +int32_t lis2du12_interrupt_mode_set(stmdev_ctx_t *ctx, + lis2du12_int_mode_t *val); +int32_t lis2du12_interrupt_mode_get(stmdev_ctx_t *ctx, + lis2du12_int_mode_t *val); + +typedef struct { + uint8_t drdy_xl : 1; /* Accelerometer data ready */ + uint8_t boot : 1; /* Restoring calibration parameters */ + uint8_t fifo_th : 1; /* FIFO threshold reached */ + uint8_t fifo_ovr : 1; /* FIFO overrun */ + uint8_t fifo_full : 1; /* FIFO full */ + uint8_t free_fall : 1; /* free fall event */ + uint8_t six_d : 1; /* orientation change (6D/4D detection) */ + uint8_t single_tap : 1; /* single-tap event */ + uint8_t double_tap : 1; /* double tap event */ + uint8_t wake_up : 1; /* wake up event */ + uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ + uint8_t sleep_state : 1; /* Act/Inact status flag */ +} lis2du12_pin_int_route_t; +int32_t lis2du12_pin_int1_route_set(stmdev_ctx_t *ctx, + lis2du12_pin_int_route_t *val); +int32_t lis2du12_pin_int1_route_get(stmdev_ctx_t *ctx, + lis2du12_pin_int_route_t *val); + +int32_t lis2du12_pin_int2_route_set(stmdev_ctx_t *ctx, + lis2du12_pin_int_route_t *val); +int32_t lis2du12_pin_int2_route_get(stmdev_ctx_t *ctx, + lis2du12_pin_int_route_t *val); + +typedef struct { + uint8_t x_en : 1; /* Detection on X-axis */ + uint8_t y_en : 1; /* Detection on Y-axis */ + uint8_t z_en : 1; /* Detection on Z-axis */ + uint8_t threshold; /* full scale dependent */ + uint8_t duration; /* 1 LSb: 1 ODR_time */ + struct { + uint8_t en : 1; /* Enable sleep detection */ + uint8_t duration; /* 0 is 16 ODR_time, 1 LSB: 512 ODR_time. */ + enum { + LIS2DU12_DO_NOT_CHANGE = 0, + LIS2DU12_SLEEP_AT_6Hz = 1, + LIS2DU12_SLEEP_AT_3Hz = 2, + LIS2DU12_SLEEP_AT_1Hz5 = 3, + } odr; + } sleep; +} lis2du12_wkup_md_t; +int32_t lis2du12_wake_up_mode_set(stmdev_ctx_t *ctx, lis2du12_wkup_md_t *val); +int32_t lis2du12_wake_up_mode_get(stmdev_ctx_t *ctx, lis2du12_wkup_md_t *val); + +typedef struct { + uint8_t x_en : 1; /* Detection on X-axis */ + uint8_t y_en : 1; /* Detection on Y-axis */ + uint8_t z_en : 1; /* Detection on Z-axis */ + struct { + uint8_t x; + uint8_t y; + uint8_t z; + } threshold; + uint8_t shock; /* max shock time. 0 is 4 ODR_time, 1 LSb : 8 ODR_time. */ + uint8_t quiet; /* Time after a tap. 0 is 2 ODR_time, 1 LSB : 4 ODR_time.*/ + enum { + LIS2DU12_XYZ = 0, + LIS2DU12_YXZ = 1, + LIS2DU12_XZY = 2, + LIS2DU12_ZYX = 3, + LIS2DU12_YZX = 5, + LIS2DU12_ZXY = 6, + } priority; + struct { + uint8_t en : 1; /* Double tap detection */ + uint8_t latency; /* Max time gap. 0 is 16 ODR_time, 1 LSB : 32 ODR_time. */ + } tap_double; +} lis2du12_tap_md_t; +int32_t lis2du12_tap_mode_set(stmdev_ctx_t *ctx, lis2du12_tap_md_t *val); +int32_t lis2du12_tap_mode_get(stmdev_ctx_t *ctx, lis2du12_tap_md_t *val); + +typedef struct { + enum { + LIS2DU12_156mg = 0, + LIS2DU12_219mg = 1, + LIS2DU12_250mg = 2, + LIS2DU12_312mg = 3, + LIS2DU12_344mg = 4, + LIS2DU12_406mg = 5, + LIS2DU12_469mg = 6, + LIS2DU12_500mg = 7, + } threshold; + uint8_t duration; /* 1 LSb: 1 ODR_time */ +} lis2du12_ff_md_t; +int32_t lis2du12_free_fall_mode_set(stmdev_ctx_t *ctx, lis2du12_ff_md_t *val); +int32_t lis2du12_free_fall_mode_get(stmdev_ctx_t *ctx, lis2du12_ff_md_t *val); + +typedef struct { + enum { + LIS2DU12_DEG_80 = 0, + LIS2DU12_DEG_70 = 1, + LIS2DU12_DEG_60 = 2, + LIS2DU12_DEG_50 = 3, + } threshold; + enum { + LIS2DU12_SIX = 0, + LIS2DU12_FOUR = 1, + } deg_of_freedom; +} lis2du12_orient_md_t; +int32_t lis2du12_orientation_mode_set(stmdev_ctx_t *ctx, + lis2du12_orient_md_t *val); +int32_t lis2du12_orientation_mode_get(stmdev_ctx_t *ctx, + lis2du12_orient_md_t *val); + +/** + *@} + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /* LIS2DU12_REGS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis2dux12_STdC/driver/lis2dux12_reg.c b/sensor/stmemsc/lis2dux12_STdC/driver/lis2dux12_reg.c new file mode 100644 index 0000000000000000000000000000000000000000..c6a4adcf68887913cec70c39f348f203b5844782 --- /dev/null +++ b/sensor/stmemsc/lis2dux12_STdC/driver/lis2dux12_reg.c @@ -0,0 +1,3556 @@ +/* + ****************************************************************************** + * @file lis2dux12_reg.c + * @author Sensors Software Solution Team + * @brief LIS2DUX12 driver file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2022 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "lis2dux12_reg.h" + +/** + * @defgroup LIS2DUX12 + * @brief This file provides a set of functions needed to drive the + * lis2dux12 sensor. + * @{ + * + */ + +/** + * @defgroup LIS2DUX12_Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +/** + * @brief Read generic device register + * + * @param ctx read / write interface definitions(ptr) + * @param reg register to read + * @param data pointer to buffer that store the data read(ptr) + * @param len number of consecutive register to read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak lis2dux12_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data, + uint16_t len) +{ + int32_t ret; + ret = ctx->read_reg(ctx->handle, reg, data, len); + return ret; +} + +/** + * @brief Write generic device register + * + * @param ctx read / write interface definitions(ptr) + * @param reg register to write + * @param data pointer to data to write in register reg(ptr) + * @param len number of consecutive register to write + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak lis2dux12_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data, + uint16_t len) +{ + int32_t ret; + ret = ctx->write_reg(ctx->handle, reg, data, len); + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LIS2DUX12_Sensitivity + * @brief These functions convert raw-data into engineering units. + * @{ + * + */ + +float_t lis2dux12_from_fs2g_to_mg(int16_t lsb) +{ + return (float_t)lsb * 0.061f; +} + +float_t lis2dux12_from_fs4g_to_mg(int16_t lsb) +{ + return (float_t)lsb * 0.122f; +} + +float_t lis2dux12_from_fs8g_to_mg(int16_t lsb) +{ + return (float_t)lsb * 0.244f; +} + +float_t lis2dux12_from_fs16g_to_mg(int16_t lsb) +{ + return (float_t)lsb * 0.488f; +} + +float_t lis2dux12_from_lsb_to_celsius(int16_t lsb) +{ + return ((float_t)lsb / 355.5f) + 25.0f; +} + +/** + * @} + * + */ + +/** + * @defgroup Common + * @brief Common + * @{/ + * + */ +/** + * @brief Device ID.[get] + * + * @param ctx read / write interface definitions + * @param val Device ID. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_device_id_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_WHO_AM_I, val, 1); + + return ret; +} + +/** + * @brief Configures the bus operating mode.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val configures the bus operating mode.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_init_set(stmdev_ctx_t *ctx, lis2dux12_init_t val) +{ + lis2dux12_ctrl1_t ctrl1; + lis2dux12_ctrl4_t ctrl4; + int32_t ret = 0; + + ret += lis2dux12_read_reg(ctx, LIS2DUX12_CTRL1, (uint8_t*)&ctrl1, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_CTRL4, (uint8_t*)&ctrl4, 1); + switch (val) { + case LIS2DUX12_BOOT: + ctrl4.boot = PROPERTY_ENABLE; + ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL4, (uint8_t*)&ctrl4, 1); + break; + case LIS2DUX12_RESET: + + ctrl1.sw_reset = PROPERTY_ENABLE; + ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL1, (uint8_t*)&ctrl1, 1); + break; + case LIS2DUX12_SENSOR_ONLY_ON: + /* no embedded funcs are used */ + ctrl4.emb_func_en = PROPERTY_DISABLE; + ctrl4.bdu = PROPERTY_ENABLE; + ctrl1.if_add_inc = PROPERTY_ENABLE; + ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL4, (uint8_t*)&ctrl4, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL1, (uint8_t*)&ctrl1, 1); + break; + case LIS2DUX12_SENSOR_EMB_FUNC_ON: + /* complete configuration is used */ + ctrl4.emb_func_en = PROPERTY_ENABLE; + ctrl4.bdu = PROPERTY_ENABLE; + ctrl1.if_add_inc = PROPERTY_ENABLE; + ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL4, (uint8_t*)&ctrl4, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL1, (uint8_t*)&ctrl1, 1); + break; + default: + ctrl1.sw_reset = PROPERTY_ENABLE; + ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL1, (uint8_t*)&ctrl1, 1); + break; + } + return ret; +} + +/** + * @brief Get the status of the device.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val the status of the device.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_status_get(stmdev_ctx_t *ctx, lis2dux12_status_t *val) +{ + lis2dux12_status_register_t status_register; + lis2dux12_ctrl1_t ctrl1; + lis2dux12_ctrl4_t ctrl4; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_STATUS, + (uint8_t*)&status_register, 1); + if (ret == 0) { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL1, (uint8_t*)&ctrl1, 1); + } + if (ret == 0) { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL4, (uint8_t*)&ctrl4, 1); + } + + val->sw_reset = ctrl1.sw_reset; + val->boot = ctrl4.boot; + val->drdy = status_register.drdy; + + return ret; +} + +/** + * @brief Get the status of the embedded funcs.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val the status of the embedded funcs.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_embedded_status_get(stmdev_ctx_t *ctx, lis2dux12_embedded_status_t *val) +{ + lis2dux12_emb_func_status_t status; + int32_t ret; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_STATUS, (uint8_t*)&status, 1); + ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + val->is_step_det = status.is_step_det; + val->is_tilt = status.is_tilt; + val->is_sigmot = status.is_sigmot; + + return ret; +} + +/** + * @brief Enables pulsed data-ready mode (~75 us).[set] + * + * @param ctx read / write interface definitions + * @param val DRDY_LATCHED, DRDY_PULSED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_data_ready_mode_set(stmdev_ctx_t *ctx, lis2dux12_data_ready_mode_t val) +{ + lis2dux12_ctrl1_t ctrl1; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1); + + if (ret == 0) + { + ctrl1.drdy_pulsed = ((uint8_t)val & 0x1U); + ret = lis2dux12_write_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1); + } + + return ret; +} + +/** + * @brief Enables pulsed data-ready mode (~75 us).[get] + * + * @param ctx read / write interface definitions + * @param val DRDY_LATCHED, DRDY_PULSED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_data_ready_mode_get(stmdev_ctx_t *ctx, lis2dux12_data_ready_mode_t *val) +{ + lis2dux12_ctrl1_t ctrl1; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1); + + switch ((ctrl1.drdy_pulsed)) + { + case LIS2DUX12_DRDY_LATCHED: + *val = LIS2DUX12_DRDY_LATCHED; + break; + + case LIS2DUX12_DRDY_PULSED: + *val = LIS2DUX12_DRDY_PULSED; + break; + + default: + *val = LIS2DUX12_DRDY_LATCHED; + break; + } + return ret; +} + +/** + * @brief Sensor mode.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val set the sensor FS and ODR.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_mode_set(stmdev_ctx_t *ctx, lis2dux12_md_t *val) +{ + lis2dux12_ctrl3_t ctrl3; + lis2dux12_ctrl5_t ctrl5; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL5, (uint8_t*)&ctrl5, 1); + + ctrl5.odr = (uint8_t)val->odr & 0xFU; + ctrl5.fs = (uint8_t)val->fs; + ctrl5.bw = (uint8_t)val->bw; + + ret += lis2dux12_read_reg(ctx, LIS2DUX12_CTRL3, (uint8_t*)&ctrl3, 1); + + ctrl3.hp_en = (((uint8_t)val->odr & 0x10U) != 0U) ? 1U : 0U; + + if (ret == 0) { + ret = lis2dux12_write_reg(ctx, LIS2DUX12_CTRL5, (uint8_t*)&ctrl5, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL3, (uint8_t*)&ctrl3, 1); + } + + return ret; +} + +/** + * @brief Sensor mode.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val get the sensor FS and ODR.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_mode_get(stmdev_ctx_t *ctx, lis2dux12_md_t *val) +{ + lis2dux12_ctrl3_t ctrl3; + lis2dux12_ctrl5_t ctrl5; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL5, (uint8_t*)&ctrl5, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_CTRL3, (uint8_t*)&ctrl3, 1); + + switch (ctrl5.odr) { + case LIS2DUX12_OFF: + val->odr = LIS2DUX12_OFF; + break; + case LIS2DUX12_1Hz5_ULP: + val->odr = LIS2DUX12_1Hz5_ULP; + break; + case LIS2DUX12_3Hz_ULP: + val->odr = LIS2DUX12_3Hz_ULP; + break; + case LIS2DUX12_25Hz_ULP: + val->odr = LIS2DUX12_25Hz_ULP; + break; + case LIS2DUX12_6Hz: + val->odr = LIS2DUX12_6Hz; + break; + case LIS2DUX12_12Hz5: + val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUX12_12Hz5_HP : LIS2DUX12_12Hz5; + break; + case LIS2DUX12_25Hz: + val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUX12_25Hz_HP : LIS2DUX12_25Hz; + break; + case LIS2DUX12_50Hz: + val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUX12_50Hz_HP : LIS2DUX12_50Hz; + break; + case LIS2DUX12_100Hz: + val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUX12_100Hz_HP : LIS2DUX12_100Hz; + break; + case LIS2DUX12_200Hz: + val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUX12_200Hz_HP : LIS2DUX12_200Hz; + break; + case LIS2DUX12_400Hz: + val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUX12_400Hz_HP : LIS2DUX12_400Hz; + break; + case LIS2DUX12_800Hz: + val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUX12_800Hz_HP : LIS2DUX12_800Hz; + break; + case LIS2DUX12_TRIG_PIN: + val->odr = LIS2DUX12_TRIG_PIN; + break; + case LIS2DUX12_TRIG_SW: + val->odr = LIS2DUX12_TRIG_SW; + break; + default: + val->odr = LIS2DUX12_OFF; + break; + } + + switch (ctrl5.fs) { + case LIS2DUX12_2g: + val->fs = LIS2DUX12_2g; + break; + case LIS2DUX12_4g: + val->fs = LIS2DUX12_4g; + break; + case LIS2DUX12_8g: + val->fs = LIS2DUX12_8g; + break; + case LIS2DUX12_16g: + val->fs = LIS2DUX12_16g; + break; + default: + val->fs = LIS2DUX12_2g; + break; + } + + switch (ctrl5.bw) { + case LIS2DUX12_ODR_div_2: + val->bw = LIS2DUX12_ODR_div_2; + break; + case LIS2DUX12_ODR_div_4: + val->bw = LIS2DUX12_ODR_div_4; + break; + case LIS2DUX12_ODR_div_8: + val->bw = LIS2DUX12_ODR_div_8; + break; + case LIS2DUX12_ODR_div_16: + val->bw = LIS2DUX12_ODR_div_16; + break; + default: + val->bw = LIS2DUX12_ODR_div_2; + break; + } + + return ret; +} + +/** + * @brief Enter deep power down[set] + * + * @param ctx read / write interface definitions + * @param val Enter deep power down + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_enter_deep_power_down(stmdev_ctx_t *ctx, uint8_t val) +{ + lis2dux12_sleep_t sleep; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_SLEEP, (uint8_t *)&sleep, 1); + + if (ret == 0) + { + sleep.deep_pd = val; + ret = lis2dux12_write_reg(ctx, LIS2DUX12_SLEEP, (uint8_t *)&sleep, 1); + } + + return ret; +} + +/** + * @brief Enter soft power down in SPI case[set] + * + * @param ctx read / write interface definitions + * @param val Enter soft power down in SPI case + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_exit_deep_power_down(stmdev_ctx_t *ctx) +{ + lis2dux12_if_wake_up_t if_wake_up = {0}; + int32_t ret; + + if_wake_up.soft_pd = PROPERTY_ENABLE; + ret = lis2dux12_write_reg(ctx, LIS2DUX12_IF_WAKE_UP, (uint8_t *)&if_wake_up, 1); + + return ret; +} + +/** + * @brief Software trigger for One-Shot.[get] + * + * @param ctx communication interface handler.(ptr) + * @param md the sensor conversion parameters.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_trigger_sw(stmdev_ctx_t *ctx, lis2dux12_md_t *md) +{ + lis2dux12_ctrl4_t ctrl4; + int32_t ret = 0; + + if ( md->odr == LIS2DUX12_TRIG_SW ) { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL4, (uint8_t*)&ctrl4, 1); + ctrl4.soc = PROPERTY_ENABLE; + if (ret == 0) { + ret = lis2dux12_write_reg(ctx, LIS2DUX12_CTRL4, (uint8_t*)&ctrl4, 1); + } + } + return ret; +} + +int32_t lis2dux12_all_sources_get(stmdev_ctx_t *ctx, lis2dux12_all_sources_t *val) +{ + lis2dux12_status_register_t status; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_STATUS, (uint8_t*)&status, 1); + val->drdy = status.drdy; + + if (ret == 0 && status.int_global == 0x1U) + { + lis2dux12_wake_up_src_t wu_src; + lis2dux12_tap_src_t tap_src; + lis2dux12_sixd_src_t sixd_src; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_SIXD_SRC, (uint8_t*)&sixd_src, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_WAKE_UP_SRC, (uint8_t*)&wu_src, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_TAP_SRC, (uint8_t*)&tap_src, 1); + + val->six_d = sixd_src.d6d_ia; + val->six_d_xl = sixd_src.xl; + val->six_d_xh = sixd_src.xh; + val->six_d_yl = sixd_src.yl; + val->six_d_yh = sixd_src.yh; + val->six_d_zl = sixd_src.zl; + val->six_d_zh = sixd_src.zh; + + val->wake_up = wu_src.wu_ia; + val->wake_up_z = wu_src.z_wu; + val->wake_up_y = wu_src.y_wu; + val->wake_up_x = wu_src.x_wu; + val->free_fall = wu_src.ff_ia; + val->sleep_change = wu_src.sleep_change_ia; + val->sleep_state = wu_src.sleep_state; + + val->single_tap = tap_src.single_tap_ia; + val->double_tap = tap_src.double_tap_ia; + val->triple_tap = tap_src.triple_tap_ia; + } + + return ret; +} + +/** + * @brief Accelerometer data.[get] + * + * @param ctx communication interface handler.(ptr) + * @param md the sensor conversion parameters.(ptr) + * @param data data retrived from the sensor.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_xl_data_get(stmdev_ctx_t *ctx, lis2dux12_md_t *md, + lis2dux12_xl_data_t *data) +{ + uint8_t buff[6]; + int32_t ret; + uint8_t i; + uint8_t j; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_OUT_X_L, buff, 6); + + /* acceleration conversion */ + j = 0U; + for (i = 0U; i < 3U; i++) { + data->raw[i] = (int16_t)buff[j+1U]; + data->raw[i] = (data->raw[i] * 256) + (int16_t) buff[j]; + j+=2U; + switch ( md->fs ) { + case LIS2DUX12_2g: + data->mg[i] =lis2dux12_from_fs2g_to_mg(data->raw[i]); + break; + case LIS2DUX12_4g: + data->mg[i] =lis2dux12_from_fs4g_to_mg(data->raw[i]); + break; + case LIS2DUX12_8g: + data->mg[i] =lis2dux12_from_fs8g_to_mg(data->raw[i]); + break; + case LIS2DUX12_16g: + data->mg[i] =lis2dux12_from_fs16g_to_mg(data->raw[i]); + break; + default: + data->mg[i] = 0.0f; + break; + } + } + + return ret; +} + +/** + * @brief OUTT data.[get] + * + * @param ctx communication interface handler.(ptr) + * @param md the sensor conversion parameters.(ptr) + * @param data data retrived from the sensor.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_outt_data_get(stmdev_ctx_t *ctx, lis2dux12_md_t *md, + lis2dux12_outt_data_t *data) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_OUT_T_L, buff, 2); + + data->heat.raw = (int16_t)buff[1U]; + data->heat.raw = (data->heat.raw * 256) + (int16_t) buff[0]; + /* temperature conversion */ + data->heat.deg_c = lis2dux12_from_lsb_to_celsius(data->heat.raw); + + return ret; +} + +/** + * @brief Configures the self test.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val self test mode.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_self_test_sign_set(stmdev_ctx_t *ctx, lis2dux12_xl_self_test_t val) +{ + lis2dux12_ctrl3_t ctrl3; + lis2dux12_wake_up_dur_t wkup_dur; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL3, (uint8_t*)&ctrl3, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_WAKE_UP_DUR, (uint8_t*)&wkup_dur, 1); + + switch (val) { + case LIS2DUX12_XL_ST_POSITIVE: + ctrl3.st_sign_x = 1; + ctrl3.st_sign_y = 1; + wkup_dur.st_sign_z = 0; + break; + + case LIS2DUX12_XL_ST_NEGATIVE: + ctrl3.st_sign_x = 0; + ctrl3.st_sign_y = 0; + wkup_dur.st_sign_z = 1; + break; + + case LIS2DUX12_XL_ST_DISABLE: + default: + ret = -1; + break; + } + + + ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL3, (uint8_t*)&ctrl3, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_WAKE_UP_DUR, (uint8_t*)&wkup_dur, 1); + + return ret; +} + +/** + * @brief Configures the self test.[start] + * + * @param ctx communication interface handler.(ptr) + * @param val valid values 2 (1st step) or 1 (2nd step) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_self_test_start(stmdev_ctx_t *ctx, uint8_t val) +{ + lis2dux12_self_test_t self_test; + int32_t ret; + + if (val != 1U && val != 2U) { + return -1; + } + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_SELF_TEST, (uint8_t*)&self_test, 1); + if (ret == 0) { + self_test.st = (uint8_t) val; + ret = lis2dux12_write_reg(ctx, LIS2DUX12_SELF_TEST, (uint8_t*)&self_test, 1); + } + return ret; +} + +/** + * @brief Configures the self test.[stop] + * + * @param ctx communication interface handler.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_self_test_stop(stmdev_ctx_t *ctx) +{ + lis2dux12_self_test_t self_test; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_SELF_TEST, (uint8_t*)&self_test, 1); + if (ret == 0) { + self_test.st = 0; + ret = lis2dux12_write_reg(ctx, LIS2DUX12_SELF_TEST, (uint8_t*)&self_test, 1); + } + return ret; +} + +/** + * @brief Configures I3C bus.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val configuration params + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_i3c_configure_set(stmdev_ctx_t *ctx, lis2dux12_i3c_cfg_t *val) +{ + lis2dux12_i3c_if_ctrl_t i3c_cfg; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_I3C_IF_CTRL, (uint8_t *)&i3c_cfg, 1); + + if (ret == 0) + { + i3c_cfg.bus_act_sel = (uint8_t)val->bus_act_sel; + i3c_cfg.dis_drstdaa = val->drstdaa_en; + i3c_cfg.asf_on = val->asf_on; + ret = lis2dux12_write_reg(ctx, LIS2DUX12_I3C_IF_CTRL, (uint8_t *)&i3c_cfg, 1); + } + + return ret; +} + +/** + * @brief Configures I3C bus.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val configuration params + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */int32_t lis2dux12_i3c_configure_get(stmdev_ctx_t *ctx, lis2dux12_i3c_cfg_t *val) +{ + lis2dux12_i3c_if_ctrl_t i3c_cfg; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_I3C_IF_CTRL, (uint8_t *)&i3c_cfg, 1); + + val->drstdaa_en = i3c_cfg.dis_drstdaa; + val->asf_on = i3c_cfg.asf_on; + + switch (val->bus_act_sel) { + case LIS2DUX12_I3C_BUS_AVAIL_TIME_20US: + val->bus_act_sel = LIS2DUX12_I3C_BUS_AVAIL_TIME_20US; + break; + + case LIS2DUX12_I3C_BUS_AVAIL_TIME_50US: + val->bus_act_sel = LIS2DUX12_I3C_BUS_AVAIL_TIME_50US; + break; + + case LIS2DUX12_I3C_BUS_AVAIL_TIME_1MS: + val->bus_act_sel = LIS2DUX12_I3C_BUS_AVAIL_TIME_1MS; + break; + + case LIS2DUX12_I3C_BUS_AVAIL_TIME_25MS: + default: + val->bus_act_sel = LIS2DUX12_I3C_BUS_AVAIL_TIME_25MS; + break; + } + + return ret; +} + +/** + * @brief Change memory bank.[set] + * + * @param ctx read / write interface definitions + * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, SENSOR_HUB_MEM_BANK, STRED_MEM_BANK, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_mem_bank_set(stmdev_ctx_t *ctx, lis2dux12_mem_bank_t val) +{ + lis2dux12_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + if (ret == 0) + { + func_cfg_access.emb_func_reg_access = ((uint8_t)val & 0x1U); + ret = lis2dux12_write_reg(ctx, LIS2DUX12_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Change memory bank.[get] + * + * @param ctx read / write interface definitions + * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, SENSOR_HUB_MEM_BANK, STRED_MEM_BANK, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_mem_bank_get(stmdev_ctx_t *ctx, lis2dux12_mem_bank_t *val) +{ + lis2dux12_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + switch ((func_cfg_access.emb_func_reg_access)) + { + case LIS2DUX12_MAIN_MEM_BANK: + *val = LIS2DUX12_MAIN_MEM_BANK; + break; + + case LIS2DUX12_EMBED_FUNC_MEM_BANK: + *val = LIS2DUX12_EMBED_FUNC_MEM_BANK; + break; + + default: + *val = LIS2DUX12_MAIN_MEM_BANK; + break; + } + return ret; +} + +/** + * @brief Write buffer in a page. + * + * @param ctx read / write interface definitions + * @param address Address of page register to be written (page number in 8-bit + * msb, register address in 8-bit lsb). + * @param buf Pointer to data buffer. + * @param len Buffer len. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len) +{ + lis2dux12_page_address_t page_address; + lis2dux12_page_sel_t page_sel; + lis2dux12_page_rw_t page_rw; + uint8_t msb; + uint8_t lsb; + int32_t ret; + uint8_t i ; + + msb = ((uint8_t)(address >> 8) & 0x0FU); + lsb = (uint8_t)address & 0xFFU; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_ENABLE; + ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1); + + ret += lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1); + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1); + + page_address.page_addr = lsb; + ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_ADDRESS, (uint8_t *)&page_address, 1); + + for (i = 0; ((i < len) && (ret == 0)); i++) + { + ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_VALUE, &buf[i], 1); + lsb++; + + /* Check if page wrap */ + if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) + { + msb++; + ret += lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1); + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1); + } + } + + page_sel.page_sel = 0; + page_sel.not_used0 = 1;// Default value + ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1); + + ret += lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1); + } + + ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Read buffer in a page. + * + * @param ctx read / write interface definitions + * @param address Address of page register to be read (page number in 8-bit + * msb, register address in 8-bit lsb). + * @param buf Pointer to data buffer. + * @param len Buffer len. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len) +{ + lis2dux12_page_address_t page_address; + lis2dux12_page_sel_t page_sel; + lis2dux12_page_rw_t page_rw; + uint8_t msb; + uint8_t lsb; + int32_t ret; + uint8_t i ; + + msb = ((uint8_t)(address >> 8) & 0x0FU); + lsb = (uint8_t)address & 0xFFU; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_ENABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1); + + ret += lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1); + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1); + + page_address.page_addr = lsb; + ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_ADDRESS, (uint8_t *)&page_address, 1); + + for (i = 0; ((i < len) && (ret == 0)); i++) + { + ret += lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_VALUE, &buf[i], 1); + lsb++; + + /* Check if page wrap */ + if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) + { + msb++; + ret += lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1); + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1); + } + } + + page_sel.page_sel = 0; + page_sel.not_used0 = 1;// Default value + ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1); + + ret += lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1); + } + + ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Interrupt PINs + * @brief Interrupt PINs + * @{/ + * + */ + +/** + * @brief Electrical pin configuration.[set] + * + * @param ctx read / write interface definitions + * @param val the electrical settings for the configurable pins.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_pin_conf_set(stmdev_ctx_t *ctx, lis2dux12_pin_conf_t *val) +{ + lis2dux12_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + + if (ret == 0) + { + pin_ctrl.cs_pu_dis = ~val->cs_pull_up; + pin_ctrl.pd_dis_int1 = ~val->int1_pull_down; + pin_ctrl.pd_dis_int2 = ~val->int2_pull_down; + pin_ctrl.sda_pu_en = val->sda_pull_up; + pin_ctrl.sdo_pu_en = val->sdo_pull_up; + pin_ctrl.pp_od = ~val->int1_int2_push_pull; + + ret = lis2dux12_write_reg(ctx, LIS2DUX12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + + return ret; +} + +/** + * @brief Electrical pin configuration.[get] + * + * @param ctx read / write interface definitions + * @param val the electrical settings for the configurable pins.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_pin_conf_get(stmdev_ctx_t *ctx, lis2dux12_pin_conf_t *val) +{ + lis2dux12_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + + val->cs_pull_up = ~pin_ctrl.cs_pu_dis; + val->int1_pull_down = ~pin_ctrl.pd_dis_int1; + val->int2_pull_down = ~pin_ctrl.pd_dis_int2; + val->sda_pull_up = pin_ctrl.sda_pu_en; + val->sdo_pull_up = pin_ctrl.sdo_pu_en; + val->int1_int2_push_pull = ~pin_ctrl.pp_od; + + return ret; +} + +/** + * @brief Interrupt activation level.[set] + * + * @param ctx read / write interface definitions + * @param val ACTIVE_HIGH, ACTIVE_LOW, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_int_pin_polarity_set(stmdev_ctx_t *ctx, lis2dux12_int_pin_polarity_t val) +{ + lis2dux12_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + + if (ret == 0) + { + pin_ctrl.h_lactive = (uint8_t)val; + ret = lis2dux12_write_reg(ctx, LIS2DUX12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + + return ret; +} + +/** + * @brief Interrupt activation level.[get] + * + * @param ctx read / write interface definitions + * @param val ACTIVE_HIGH, ACTIVE_LOW, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_int_pin_polarity_get(stmdev_ctx_t *ctx, lis2dux12_int_pin_polarity_t *val) +{ + lis2dux12_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + + switch ((pin_ctrl.h_lactive)) + { + case LIS2DUX12_ACTIVE_HIGH: + *val = LIS2DUX12_ACTIVE_HIGH; + break; + + case LIS2DUX12_ACTIVE_LOW: + *val = LIS2DUX12_ACTIVE_LOW; + break; + + default: + *val = LIS2DUX12_ACTIVE_HIGH; + break; + } + return ret; +} + +/** + * @brief SPI mode.[set] + * + * @param ctx read / write interface definitions + * @param val SPI_4_WIRE, SPI_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_spi_mode_set(stmdev_ctx_t *ctx, lis2dux12_spi_mode val) +{ + lis2dux12_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + + if (ret == 0) + { + pin_ctrl.sim = (uint8_t)val; + ret = lis2dux12_write_reg(ctx, LIS2DUX12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + + return ret; +} + +/** + * @brief SPI mode.[get] + * + * @param ctx read / write interface definitions + * @param val SPI_4_WIRE, SPI_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_spi_mode_get(stmdev_ctx_t *ctx, lis2dux12_spi_mode *val) +{ + lis2dux12_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + + switch ((pin_ctrl.h_lactive)) + { + case LIS2DUX12_SPI_4_WIRE: + *val = LIS2DUX12_SPI_4_WIRE; + break; + + case LIS2DUX12_SPI_3_WIRE: + *val = LIS2DUX12_SPI_3_WIRE; + break; + + default: + *val = LIS2DUX12_SPI_4_WIRE; + break; + } + return ret; +} + +/** + * @brief routes interrupt signals on INT 1 pin.[set] + * + * @param ctx read / write interface definitions + * @param val routes interrupt signals on INT 1 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_pin_int1_route_set(stmdev_ctx_t *ctx, lis2dux12_pin_int_route_t *val) +{ + lis2dux12_ctrl1_t ctrl1; + lis2dux12_ctrl2_t ctrl2; + lis2dux12_md1_cfg_t md1_cfg; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1); + + if (ret == 0) + { + ctrl1.int1_on_res = val->int_on_res; + + ret = lis2dux12_write_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1); + } + + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL2, (uint8_t *)&ctrl2, 1); + + if (ret == 0) + { + ctrl2.int1_drdy = val->drdy; + ctrl2.int1_fifo_ovr = val->fifo_ovr; + ctrl2.int1_fifo_th = val->fifo_th; + ctrl2.int1_fifo_full = val->fifo_full; + ctrl2.int1_boot = val->boot; + + ret = lis2dux12_write_reg(ctx, LIS2DUX12_CTRL2, (uint8_t *)&ctrl2, 1); + } + } + + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_MD1_CFG, (uint8_t *)&md1_cfg, 1); + + if (ret == 0) + { + md1_cfg.int1_ff = val->free_fall; + md1_cfg.int1_6d = val->six_d; + md1_cfg.int1_tap = val->tap; + md1_cfg.int1_wu = val->wake_up; + md1_cfg.int1_sleep_change = val->sleep_change; + md1_cfg.int1_emb_func = val->emb_function; + md1_cfg.int1_timestamp = val->timestamp; + + ret = lis2dux12_write_reg(ctx, LIS2DUX12_MD1_CFG, (uint8_t *)&md1_cfg, 1); + } + } + + return ret; +} + +/** + * @brief routes interrupt signals on INT 1 pin.[get] + * + * @param ctx read / write interface definitions + * @param val Get interrupt signals routing on INT 1 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_pin_int1_route_get(stmdev_ctx_t *ctx, lis2dux12_pin_int_route_t *val) +{ + lis2dux12_ctrl1_t ctrl1; + lis2dux12_ctrl2_t ctrl2; + lis2dux12_md1_cfg_t md1_cfg; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_CTRL2, (uint8_t *)&ctrl2, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_MD1_CFG, (uint8_t *)&md1_cfg, 1); + + if (ret == 0) + { + val->int_on_res = ctrl1.int1_on_res; + val->drdy = ctrl2.int1_drdy; + val->fifo_ovr = ctrl2.int1_fifo_ovr; + val->fifo_th = ctrl2.int1_fifo_th; + val->fifo_full = ctrl2.int1_fifo_full; + val->boot = ctrl2.int1_boot; + val->free_fall = md1_cfg.int1_ff; + val->six_d = md1_cfg.int1_6d; + val->tap = md1_cfg.int1_tap; + val->wake_up = md1_cfg.int1_wu; + val->sleep_change = md1_cfg.int1_sleep_change; + val->emb_function = md1_cfg.int1_emb_func; + val->timestamp = md1_cfg.int1_timestamp; + } + + return ret; +} + +/** + * @brief routes embedded func interrupt signals on INT 1 pin.[set] + * + * @param ctx read / write interface definitions + * @param val routes embedded func interrupt signals on INT 1 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_emb_pin_int1_route_set(stmdev_ctx_t *ctx, + lis2dux12_emb_pin_int_route_t *val) +{ + lis2dux12_emb_func_int1_t emb_func_int1; + lis2dux12_md1_cfg_t md1_cfg; + int32_t ret; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + } + + if (ret == 0) + { + emb_func_int1.int1_tilt = val->tilt; + emb_func_int1.int1_sig_mot = val->sig_mot; + emb_func_int1.int1_step_det = val->step_det; + emb_func_int1.int1_fsm_lc = val->fsm_lc; + + ret = lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + } + ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + ret += lis2dux12_read_reg(ctx, LIS2DUX12_MD1_CFG, (uint8_t *)&md1_cfg, 1); + if (ret == 0) + { + md1_cfg.int1_emb_func = 1; + ret = lis2dux12_write_reg(ctx, LIS2DUX12_MD1_CFG, (uint8_t *)&md1_cfg, 1); + } + + return ret; +} + +/** + * @brief routes embedded func interrupt signals on INT 1 pin.[get] + * + * @param ctx read / write interface definitions + * @param val routes embedded func interrupt signals on INT 1 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_emb_pin_int1_route_get(stmdev_ctx_t *ctx, + lis2dux12_emb_pin_int_route_t *val) +{ + lis2dux12_emb_func_int1_t emb_func_int1; + int32_t ret; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + } + + if (ret == 0) + { + val->tilt = emb_func_int1.int1_tilt; + val->sig_mot = emb_func_int1.int1_sig_mot; + val->step_det = emb_func_int1.int1_step_det; + val->fsm_lc = emb_func_int1.int1_fsm_lc; + } + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief routes interrupt signals on INT 2 pin.[set] + * + * @param ctx read / write interface definitions + * @param val routes interrupt signals on INT 2 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_pin_int2_route_set(stmdev_ctx_t *ctx, lis2dux12_pin_int_route_t *val) +{ + lis2dux12_ctrl3_t ctrl3; + lis2dux12_md2_cfg_t md2_cfg; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL2, (uint8_t *)&ctrl3, 1); + + if (ret == 0) + { + ctrl3.int2_drdy = val->drdy; + ctrl3.int2_fifo_ovr = val->fifo_ovr; + ctrl3.int2_fifo_th = val->fifo_th; + ctrl3.int2_fifo_full = val->fifo_full; + ctrl3.int2_boot = val->boot; + + ret = lis2dux12_write_reg(ctx, LIS2DUX12_CTRL3, (uint8_t *)&ctrl3, 1); + } + + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_MD2_CFG, (uint8_t *)&md2_cfg, 1); + + if (ret == 0) + { + md2_cfg.int2_ff = val->free_fall; + md2_cfg.int2_6d = val->six_d; + md2_cfg.int2_tap = val->tap; + md2_cfg.int2_wu = val->wake_up; + md2_cfg.int2_sleep_change = val->sleep_change; + md2_cfg.int2_emb_func = val->emb_function; + md2_cfg.int2_timestamp = val->timestamp; + + ret = lis2dux12_write_reg(ctx, LIS2DUX12_MD2_CFG, (uint8_t *)&md2_cfg, 1); + } + } + + return ret; +} + +/** + * @brief routes interrupt signals on INT 2 pin.[get] + * + * @param ctx read / write interface definitions + * @param val Get interrupt signals routing on INT 2 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_pin_int2_route_get(stmdev_ctx_t *ctx, lis2dux12_pin_int_route_t *val) +{ + lis2dux12_ctrl3_t ctrl3; + lis2dux12_md2_cfg_t md2_cfg; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL2, (uint8_t *)&ctrl3, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_MD1_CFG, (uint8_t *)&md2_cfg, 1); + + if (ret == 0) + { + val->drdy = ctrl3.int2_drdy; + val->fifo_ovr = ctrl3.int2_fifo_ovr; + val->fifo_th = ctrl3.int2_fifo_th; + val->fifo_full = ctrl3.int2_fifo_full; + val->boot = ctrl3.int2_boot; + val->free_fall = md2_cfg.int2_ff; + val->six_d = md2_cfg.int2_6d; + val->tap = md2_cfg.int2_tap; + val->wake_up = md2_cfg.int2_wu; + val->sleep_change = md2_cfg.int2_sleep_change; + val->emb_function = md2_cfg.int2_emb_func; + val->timestamp = md2_cfg.int2_timestamp; + } + + return ret; +} + +/** + * @brief routes embedded func interrupt signals on INT 2 pin.[set] + * + * @param ctx read / write interface definitions + * @param val routes embedded func interrupt signals on INT 2 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_emb_pin_int2_route_set(stmdev_ctx_t *ctx, + lis2dux12_emb_pin_int_route_t *val) +{ + lis2dux12_emb_func_int2_t emb_func_int2; + lis2dux12_md2_cfg_t md2_cfg; + int32_t ret; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + } + + if (ret == 0) + { + emb_func_int2.int2_tilt = val->tilt; + emb_func_int2.int2_sig_mot = val->sig_mot; + emb_func_int2.int2_step_det = val->step_det; + emb_func_int2.int2_fsm_lc = val->fsm_lc; + + ret = lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + } + ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + ret += lis2dux12_read_reg(ctx, LIS2DUX12_MD2_CFG, (uint8_t *)&md2_cfg, 1); + if (ret == 0) + { + md2_cfg.int2_emb_func = 1; + ret = lis2dux12_write_reg(ctx, LIS2DUX12_MD2_CFG, (uint8_t *)&md2_cfg, 1); + } + + return ret; +} + +/** + * @brief routes embedded func interrupt signals on INT 2 pin.[get] + * + * @param ctx read / write interface definitions + * @param val routes embedded func interrupt signals on INT 2 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_emb_pin_int2_route_get(stmdev_ctx_t *ctx, + lis2dux12_emb_pin_int_route_t *val) +{ + lis2dux12_emb_func_int2_t emb_func_int2; + int32_t ret; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + } + + if (ret == 0) + { + val->tilt = emb_func_int2.int2_tilt; + val->sig_mot = emb_func_int2.int2_sig_mot; + val->step_det = emb_func_int2.int2_step_det; + val->fsm_lc = emb_func_int2.int2_fsm_lc; + } + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Interrupt configuration mode.[set] + * + * @param ctx read / write interface definitions + * @param val INT_DISABLED, INT_LEVEL, INT_LATCHED + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_int_config_set(stmdev_ctx_t *ctx, lis2dux12_int_config_t *val) +{ + lis2dux12_interrupt_cfg_t interrupt_cfg; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1); + + if (ret == 0) + { + switch (val->int_cfg) + { + case LIS2DUX12_INT_DISABLED: + interrupt_cfg.interrupts_enable = 0; + break; + + case LIS2DUX12_INT_LEVEL: + interrupt_cfg.interrupts_enable = 1; + interrupt_cfg.lir = 0; + break; + + case LIS2DUX12_INT_LATCHED: + default: + interrupt_cfg.interrupts_enable = 1; + interrupt_cfg.lir = 1; + break; + } + + interrupt_cfg.dis_rst_lir_all_int = val->dis_rst_lir_all_int; + interrupt_cfg.sleep_status_on_int = val->sleep_status_on_int; + + ret = lis2dux12_write_reg(ctx, LIS2DUX12_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1); + } + + return ret; +} + +/** + * @brief Interrupt configuration mode.[get] + * + * @param ctx read / write interface definitions + * @param val INT_DISABLED, INT_LEVEL, INT_LATCHED + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_int_config_get(stmdev_ctx_t *ctx, lis2dux12_int_config_t *val) +{ + lis2dux12_interrupt_cfg_t interrupt_cfg; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1); + + if (ret == 0) + { + val->dis_rst_lir_all_int = interrupt_cfg.dis_rst_lir_all_int; + val->sleep_status_on_int = interrupt_cfg.sleep_status_on_int; + + if (interrupt_cfg.interrupts_enable == 0U) + { + val->int_cfg = LIS2DUX12_INT_DISABLED; + } + else if (interrupt_cfg.lir == 0U) + { + val->int_cfg = LIS2DUX12_INT_LEVEL; + } + else + { + val->int_cfg = LIS2DUX12_INT_LATCHED; + } + } + + return ret; +} + +/** + * @brief Embedded Interrupt configuration mode.[set] + * + * @param ctx read / write interface definitions + * @param val INT_PULSED, INT_LATCHED + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_embedded_int_config_set(stmdev_ctx_t *ctx, lis2dux12_embedded_int_config_t val) +{ + lis2dux12_page_rw_t page_rw; + int32_t ret; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1); + + switch (val) + { + case LIS2DUX12_EMBEDDED_INT_LEVEL: + page_rw.emb_func_lir = 0; + break; + + case LIS2DUX12_EMBEDDED_INT_LATCHED: + default: + page_rw.emb_func_lir = 1; + break; + } + + ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1); + } + + ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Interrupt configuration mode.[get] + * + * @param ctx read / write interface definitions + * @param val INT_DISABLED, INT_PULSED, INT_LATCHED + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_embedded_int_config_get(stmdev_ctx_t *ctx, lis2dux12_embedded_int_config_t *val) +{ + lis2dux12_page_rw_t page_rw; + int32_t ret; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1); + + if (page_rw.emb_func_lir == 0U) { + *val = LIS2DUX12_EMBEDDED_INT_LEVEL; + } else { + *val = LIS2DUX12_EMBEDDED_INT_LATCHED; + } + } + + ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup FIFO + * @brief FIFO + * @{/ + * + */ + +/** + * @brief FIFO mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val BYPASS_MODE, FIFO_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_fifo_mode_set(stmdev_ctx_t *ctx, lis2dux12_fifo_mode_t val) +{ + lis2dux12_ctrl4_t ctrl4; + lis2dux12_fifo_ctrl_t fifo_ctrl; + lis2dux12_fifo_wtm_t fifo_wtm; + lis2dux12_fifo_batch_dec_t fifo_batch; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); + + if (ret == 0) + { + /* set FIFO mode */ + if (val.operation != LIS2DUX12_FIFO_OFF) + { + ctrl4.fifo_en = 1; + fifo_ctrl.fifo_mode = ((uint8_t)val.operation & 0x7U); + } + else { + ctrl4.fifo_en = 0; + } + + /* set fifo depth (1X/2X) */ + fifo_ctrl.fifo_depth = (uint8_t)val.store; + + /* Set xl_only_fifo */ + fifo_wtm.xl_only_fifo = val.xl_only; + + /* set batching info */ + if (val.batch.dec_ts != LIS2DUX12_DEC_TS_OFF) + { + fifo_batch.dec_ts_batch = (uint8_t)val.batch.dec_ts; + fifo_batch.bdr_xl = (uint8_t)val.batch.bdr_xl; + } + + fifo_ctrl.cfg_chg_en = val.cfg_change_in_fifo; + + /* set watermark */ + if (val.watermark > 0U) { + fifo_ctrl.stop_on_fth = 1; + fifo_wtm.fth = val.watermark; + } + + ret += lis2dux12_write_reg(ctx, LIS2DUX12_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1); + } + + return ret; +} + +/** + * @brief FIFO mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val BYPASS_MODE, FIFO_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_fifo_mode_get(stmdev_ctx_t *ctx, lis2dux12_fifo_mode_t *val) +{ + lis2dux12_ctrl4_t ctrl4; + lis2dux12_fifo_ctrl_t fifo_ctrl; + lis2dux12_fifo_wtm_t fifo_wtm; + lis2dux12_fifo_batch_dec_t fifo_batch; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); + + if (ret == 0) + { + /* get FIFO mode */ + if (ctrl4.fifo_en == 0U) { + val->operation = LIS2DUX12_FIFO_OFF; + } + else { + val->operation = (enum operation)fifo_ctrl.fifo_mode; + } + val->cfg_change_in_fifo = fifo_ctrl.cfg_chg_en; + + /* get fifo depth (1X/2X) */ + val->store = (enum store)fifo_ctrl.fifo_depth; + + /* Get xl_only_fifo */ + val->xl_only = fifo_wtm.xl_only_fifo; + + /* get batching info */ + val->batch.dec_ts = (enum dec_ts)fifo_batch.dec_ts_batch; + val->batch.bdr_xl = (enum bdr_xl)fifo_batch.bdr_xl; + + /* get watermark */ + val->watermark = fifo_wtm.fth; + } + + return ret; +} + +/** + * @brief Number of unread sensor data (TAG + 6 bytes) stored in FIFO.[get] + * + * @param ctx read / write interface definitions + * @param val Number of unread sensor data (TAG + 6 bytes) stored in FIFO. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_STATUS2, &buff, 1); + + *val = buff; + + return ret; +} + +int32_t lis2dux12_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lis2dux12_fifo_status1_t fifo_status1; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_STATUS1, (uint8_t *)&fifo_status1, 1); + + *val = fifo_status1.fifo_wtm_ia; + + return ret; +} + +int32_t lis2dux12_fifo_sensor_tag_get(stmdev_ctx_t *ctx, lis2dux12_fifo_sensor_tag_t *val) +{ + lis2dux12_fifo_data_out_tag_t fifo_tag; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_DATA_OUT_TAG, (uint8_t *)&fifo_tag, 1); + + *val = (lis2dux12_fifo_sensor_tag_t) fifo_tag.tag_sensor; + + return ret; +} + +int32_t lis2dux12_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_DATA_OUT_X_L, buff, 6); + + return ret; +} + +int32_t lis2dux12_fifo_data_get(stmdev_ctx_t *ctx, lis2dux12_md_t *md, + lis2dux12_fifo_mode_t *fmd, + lis2dux12_fifo_data_t *data) +{ + lis2dux12_fifo_data_out_tag_t fifo_tag; + uint8_t fifo_raw[6]; + int32_t ret, i; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_DATA_OUT_TAG, (uint8_t *)&fifo_tag, 1); + data->tag = fifo_tag.tag_sensor; + + switch (fifo_tag.tag_sensor) { + case LIS2DUX12_XL_ONLY_2X_TAG: + /* A FIFO sample consists of 2X 8-bits 3-axis XL at ODR/2 */ + ret = lis2dux12_fifo_out_raw_get(ctx, fifo_raw); + for (i = 0; i < 3; i++) { + data->xl[0].raw[i] = (int16_t)fifo_raw[i] * 256; + data->xl[1].raw[i] = (int16_t)fifo_raw[3 + i] * 256; + } + break; + case LIS2DUX12_XL_TEMP_TAG: + ret = lis2dux12_fifo_out_raw_get(ctx, fifo_raw); + if (fmd->xl_only == 0x0U) { + /* A FIFO sample consists of 12-bits 3-axis XL + T at ODR*/ + data->xl[0].raw[0] = (int16_t)fifo_raw[0]; + data->xl[0].raw[0] = (data->xl[0].raw[0] + (int16_t)fifo_raw[1] * 256) * 16; + data->xl[0].raw[1] = (int16_t)fifo_raw[1] / 16; + data->xl[0].raw[1] = (data->xl[0].raw[1] + ((int16_t)fifo_raw[2] * 16)) * 16; + data->xl[0].raw[2] = (int16_t)fifo_raw[3]; + data->xl[0].raw[2] = data->xl[0].raw[2] + ((int16_t)fifo_raw[4] * 256) * 16; + data->heat.raw = (int16_t)fifo_raw[4] / 16; + data->heat.raw = (data->heat.raw + ((int16_t)fifo_raw[5] * 16)) * 16; + data->heat.deg_c = lis2dux12_from_lsb_to_celsius(data->heat.raw); + } else { + /* A FIFO sample consists of 16-bits 3-axis XL at ODR */ + data->xl[0].raw[0] = (int16_t)fifo_raw[0] + (int16_t)fifo_raw[1] * 256; + data->xl[0].raw[1] = (int16_t)fifo_raw[1] + (int16_t)fifo_raw[3] * 256; + data->xl[0].raw[2] = (int16_t)fifo_raw[2] + (int16_t)fifo_raw[5] * 256; + } + break; + case LIS2DUX12_TIMESTAMP_TAG: + ret = lis2dux12_fifo_out_raw_get(ctx, fifo_raw); + + data->cfg_chg.cfg_change = fifo_raw[0] >> 7; + data->cfg_chg.odr = (fifo_raw[0] >> 3) & 0xFU; + data->cfg_chg.bw = (fifo_raw[0] >> 1) & 0x3U; + data->cfg_chg.lp_hp = fifo_raw[0] & 0x1U; + data->cfg_chg.fs = (fifo_raw[1] >> 5) & 0x3U; + data->cfg_chg.dec_ts = (fifo_raw[1] >> 3) & 0x3U; + data->cfg_chg.odr_xl_batch = fifo_raw[1] & 0x7U; + + data->cfg_chg.timestamp = fifo_raw[5]; + data->cfg_chg.timestamp = (data->cfg_chg.timestamp * 256U) + fifo_raw[4]; + data->cfg_chg.timestamp = (data->cfg_chg.timestamp * 256U) + fifo_raw[3]; + data->cfg_chg.timestamp = (data->cfg_chg.timestamp * 256U) + fifo_raw[2]; + break; + + case LIS2DUX12_STEP_COUNTER_TAG: + ret = lis2dux12_fifo_out_raw_get(ctx, fifo_raw); + + data->pedo.steps = fifo_raw[1]; + data->pedo.steps = (data->pedo.steps * 256U) + fifo_raw[0]; + + data->pedo.timestamp = fifo_raw[5]; + data->pedo.timestamp = (data->pedo.timestamp * 256U) + fifo_raw[4]; + data->pedo.timestamp = (data->pedo.timestamp * 256U) + fifo_raw[3]; + data->pedo.timestamp = (data->pedo.timestamp * 256U) + fifo_raw[2]; + + break; + + case LIS2DUX12_FIFO_EMPTY: + default: + break; + } + + for (i = 0; i < 3; i++) { + switch ( md->fs ) { + case LIS2DUX12_2g: + data->xl[0].mg[i] =lis2dux12_from_fs2g_to_mg(data->xl[0].raw[i]); + data->xl[1].mg[i] =lis2dux12_from_fs2g_to_mg(data->xl[1].raw[i]); + break; + case LIS2DUX12_4g: + data->xl[0].mg[i] =lis2dux12_from_fs4g_to_mg(data->xl[0].raw[i]); + data->xl[1].mg[i] =lis2dux12_from_fs4g_to_mg(data->xl[1].raw[i]); + break; + case LIS2DUX12_8g: + data->xl[0].mg[i] =lis2dux12_from_fs8g_to_mg(data->xl[0].raw[i]); + data->xl[1].mg[i] =lis2dux12_from_fs8g_to_mg(data->xl[1].raw[i]); + break; + case LIS2DUX12_16g: + data->xl[0].mg[i] =lis2dux12_from_fs16g_to_mg(data->xl[0].raw[i]); + data->xl[1].mg[i] =lis2dux12_from_fs16g_to_mg(data->xl[1].raw[i]); + break; + default: + data->xl[0].mg[i] = 0.0f; + data->xl[1].mg[i] = 0.0f; + break; + } + } + + return ret; +} + +/** + * @defgroup Step Counter (Pedometer) + * @brief Step Counter (Pedometer) + * @{/ + * + */ +/** + * @brief Step counter mode[set] + * + * @param ctx read / write interface definitions + * @param val Step counter mode + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_stpcnt_mode_set(stmdev_ctx_t *ctx, lis2dux12_stpcnt_mode_t val) +{ + lis2dux12_emb_func_en_a_t emb_func_en_a; + lis2dux12_emb_func_en_b_t emb_func_en_b; + lis2dux12_emb_func_fifo_en_t emb_func_fifo_en; + lis2dux12_pedo_cmd_reg_t pedo_cmd_reg; + int32_t ret; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_FIFO_EN, (uint8_t *)&emb_func_fifo_en, 1); + + if ((val.false_step_rej == PROPERTY_ENABLE) && ((emb_func_en_a.mlc_before_fsm_en & emb_func_en_b.mlc_en) == PROPERTY_DISABLE)) + { + emb_func_en_a.mlc_before_fsm_en = PROPERTY_ENABLE; + } + + emb_func_fifo_en.step_counter_fifo_en = val.step_counter_in_fifo; + ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_FIFO_EN, (uint8_t *)&emb_func_fifo_en, 1); + + emb_func_en_a.pedo_en = val.step_counter_enable; + ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + + ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + ret += lis2dux12_ln_pg_read(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + + if (ret == 0) + { + pedo_cmd_reg.fp_rejection_en = val.false_step_rej; + ret += lis2dux12_ln_pg_write(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + + return ret; +} + +/** + * @brief Step counter mode[get] + * + * @param ctx read / write interface definitions + * @param val Step counter mode + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_stpcnt_mode_get(stmdev_ctx_t *ctx, lis2dux12_stpcnt_mode_t *val) +{ + lis2dux12_emb_func_en_a_t emb_func_en_a; + lis2dux12_pedo_cmd_reg_t pedo_cmd_reg; + int32_t ret; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + ret += lis2dux12_ln_pg_read(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + val->false_step_rej = pedo_cmd_reg.fp_rejection_en; + val->step_counter_enable = emb_func_en_a.pedo_en; + + return ret; +} + +/** + * @brief Step counter output, number of detected steps.[get] + * + * @param ctx read / write interface definitions + * @param val Step counter output, number of detected steps. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_STEP_COUNTER_L, &buff[0], 2); + ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief Reset step counter.[set] + * + * @param ctx read / write interface definitions + * @param val Reset step counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_stpcnt_rst_step_set(stmdev_ctx_t *ctx) +{ + lis2dux12_emb_func_src_t emb_func_src; + int32_t ret; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + emb_func_src.pedo_rst_step = 1; + ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } + + ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Pedometer debounce configuration.[set] + * + * @param ctx read / write interface definitions + * @param val Pedometer debounce configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_stpcnt_debounce_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lis2dux12_pedo_deb_steps_conf_t pedo_deb_steps_conf; + int32_t ret; + + pedo_deb_steps_conf.deb_step = val; + ret = lis2dux12_ln_pg_write(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); + + return ret; +} + +/** + * @brief Pedometer debounce configuration.[get] + * + * @param ctx read / write interface definitions + * @param val Pedometer debounce configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_stpcnt_debounce_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lis2dux12_pedo_deb_steps_conf_t pedo_deb_steps_conf; + int32_t ret; + + ret = lis2dux12_ln_pg_read(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); + *val = pedo_deb_steps_conf.deb_step; + + return ret; +} + +/** + * @brief Time period register for step detection on delta time.[set] + * + * @param ctx read / write interface definitions + * @param val Time period register for step detection on delta time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + + ret = lis2dux12_ln_pg_write(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_SC_DELTAT_L, (uint8_t *)buff, 2); + + return ret; +} + +/** + * @brief Time period register for step detection on delta time.[get] + * + * @param ctx read / write interface definitions + * @param val Time period register for step detection on delta time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_stpcnt_period_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lis2dux12_ln_pg_read(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_SC_DELTAT_L, (uint8_t *)buff, 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Tilt + * @brief Tilt + * @{/ + * + */ +/** + * @brief Tilt calculation.[set] + * + * @param ctx read / write interface definitions + * @param val Tilt calculation. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_tilt_mode_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lis2dux12_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + emb_func_en_a.tilt_en = val; + ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + + ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Tilt calculation.[get] + * + * @param ctx read / write interface definitions + * @param val Tilt calculation. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_tilt_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lis2dux12_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + *val = emb_func_en_a.tilt_en; + } + + ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Significant motion detection + * @brief Significant motion detection + * @{/ + * + */ +/** + * @brief Enables significant motion detection function.[set] + * + * @param ctx read / write interface definitions + * @param val Enables significant motion detection function. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_sigmot_mode_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lis2dux12_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + emb_func_en_a.sign_motion_en = val; + ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + + ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enables significant motion detection function.[get] + * + * @param ctx read / write interface definitions + * @param val Enables significant motion detection function. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_sigmot_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lis2dux12_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + *val = emb_func_en_a.sign_motion_en; + } + + ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + + +/** + * @defgroup Free Fall + * @brief Free Fall + * @{/ + * + */ +/** + * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[set] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_ff_duration_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lis2dux12_wake_up_dur_t wake_up_dur; + lis2dux12_free_fall_t free_fall; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + + if (ret == 0) + { + wake_up_dur.ff_dur = (val >> 5) & 0x1U; + ret = lis2dux12_write_reg(ctx, LIS2DUX12_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + } + + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_FREE_FALL, (uint8_t *)&free_fall, 1); + free_fall.ff_dur = val & 0x1FU; + ret += lis2dux12_write_reg(ctx, LIS2DUX12_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + return ret; +} + +/** + * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[get] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_ff_duration_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lis2dux12_wake_up_dur_t wake_up_dur; + lis2dux12_free_fall_t free_fall; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + *val = (wake_up_dur.ff_dur << 5) | free_fall.ff_dur; + + return ret; +} + +/** + * @brief Free fall threshold setting.[set] + * + * @param ctx read / write interface definitions + * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_ff_thresholds_set(stmdev_ctx_t *ctx, lis2dux12_ff_thresholds_t val) +{ + lis2dux12_free_fall_t free_fall; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_FREE_FALL, (uint8_t *)&free_fall, 1); + free_fall.ff_ths = ((uint8_t)val & 0x7U); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_FREE_FALL, (uint8_t *)&free_fall, 1); + + return ret; +} + +/** + * @brief Free fall threshold setting.[get] + * + * @param ctx read / write interface definitions + * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_ff_thresholds_get(stmdev_ctx_t *ctx, lis2dux12_ff_thresholds_t *val) +{ + lis2dux12_free_fall_t free_fall; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_FREE_FALL, (uint8_t *)&free_fall, 1); + + switch (free_fall.ff_ths) + { + case LIS2DUX12_156_mg: + *val = LIS2DUX12_156_mg; + break; + + case LIS2DUX12_219_mg: + *val = LIS2DUX12_219_mg; + break; + + case LIS2DUX12_250_mg: + *val = LIS2DUX12_250_mg; + break; + + case LIS2DUX12_312_mg: + *val = LIS2DUX12_312_mg; + break; + + case LIS2DUX12_344_mg: + *val = LIS2DUX12_344_mg; + break; + + case LIS2DUX12_406_mg: + *val = LIS2DUX12_406_mg; + break; + + case LIS2DUX12_469_mg: + *val = LIS2DUX12_469_mg; + break; + + case LIS2DUX12_500_mg: + *val = LIS2DUX12_500_mg; + break; + + default: + *val = LIS2DUX12_156_mg; + break; + } + return ret; +} + +/** + * @} + * + */ + + +/** + * @defgroup Orientation 6D (and 4D) + * @brief Orientation 6D (and 4D) + * @{/ + * + */ +/** + * @brief configuration for 4D/6D function.[set] + * + * @param ctx read / write interface definitions + * @param val 4D/6D, DEG_80, DEG_70, DEG_60, DEG_50, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_sixd_config_set(stmdev_ctx_t *ctx, lis2dux12_sixd_config_t val) +{ + lis2dux12_sixd_t sixd; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_SIXD, (uint8_t *)&sixd, 1); + + if (ret == 0) + { + sixd.d4d_en = ((uint8_t)val.mode); + sixd.d6d_ths = ((uint8_t)val.threshold); + ret = lis2dux12_write_reg(ctx, LIS2DUX12_SIXD, (uint8_t *)&sixd, 1); + } + + return ret; +} + +/** + * @brief configuration for 4D/6D function.[get] + * + * @param ctx read / write interface definitions + * @param val 4D/6D, DEG_80, DEG_70, DEG_60, DEG_50, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_sixd_config_get(stmdev_ctx_t *ctx, lis2dux12_sixd_config_t *val) +{ + lis2dux12_sixd_t sixd; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_SIXD, (uint8_t *)&sixd, 1); + + val->mode = (enum mode)sixd.d4d_en; + + switch ((sixd.d6d_ths)) + { + case LIS2DUX12_DEG_80: + val->threshold = LIS2DUX12_DEG_80; + break; + + case LIS2DUX12_DEG_70: + val->threshold = LIS2DUX12_DEG_70; + break; + + case LIS2DUX12_DEG_60: + val->threshold = LIS2DUX12_DEG_60; + break; + + case LIS2DUX12_DEG_50: + val->threshold = LIS2DUX12_DEG_50; + break; + + default: + val->threshold = LIS2DUX12_DEG_80; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup wakeup configuration + * @brief wakeup configuration + * @{/ + * + */ + +/** + * @brief configuration for wakeup function.[set] + * + * @param ctx read / write interface definitions + * @param val threshold, duration, ... + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_wakeup_config_set(stmdev_ctx_t *ctx, lis2dux12_wakeup_config_t val) +{ + lis2dux12_wake_up_ths_t wup_ths; + lis2dux12_wake_up_dur_t wup_dur; + lis2dux12_wake_up_dur_ext_t wup_dur_ext; + lis2dux12_interrupt_cfg_t int_cfg; + lis2dux12_ctrl1_t ctrl1; + lis2dux12_ctrl4_t ctrl4; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_WAKE_UP_THS, (uint8_t *)&wup_ths, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_WAKE_UP_DUR, (uint8_t *)&wup_dur, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_WAKE_UP_DUR_EXT, (uint8_t *)&wup_dur_ext, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1); + + if (ret == 0) + { + wup_dur.wake_dur = (uint8_t)val.wake_dur & 0x3U; + wup_dur_ext.wu_dur_extended = (uint8_t)val.wake_dur >> 2; + wup_dur.sleep_dur = val.sleep_dur; + + int_cfg.wake_ths_w = val.wake_ths_weight; + wup_ths.wk_ths = val.wake_ths; + wup_ths.sleep_on = (uint8_t)val.wake_enable; + ctrl4.inact_odr = (uint8_t)val.inact_odr; + + if (val.wake_enable == LIS2DUX12_SLEEP_ON) { + ctrl1.wu_x_en = 1; + ctrl1.wu_y_en = 1; + ctrl1.wu_z_en = 1; + } else { + ctrl1.wu_x_en = 0; + ctrl1.wu_y_en = 0; + ctrl1.wu_z_en = 0; + } + + ret += lis2dux12_write_reg(ctx, LIS2DUX12_WAKE_UP_THS, (uint8_t *)&wup_ths, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_WAKE_UP_DUR, (uint8_t *)&wup_dur, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_WAKE_UP_DUR_EXT, (uint8_t *)&wup_dur_ext, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1); + } + + return ret; +} + +/** + * @brief configuration for wakeup function.[get] + * + * @param ctx read / write interface definitions + * @param val threshold, duration, ... + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_wakeup_config_get(stmdev_ctx_t *ctx, lis2dux12_wakeup_config_t *val) +{ + lis2dux12_wake_up_ths_t wup_ths; + lis2dux12_wake_up_dur_t wup_dur; + lis2dux12_wake_up_dur_ext_t wup_dur_ext; + lis2dux12_interrupt_cfg_t int_cfg; + lis2dux12_ctrl4_t ctrl4; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_WAKE_UP_THS, (uint8_t *)&wup_ths, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_WAKE_UP_DUR, (uint8_t *)&wup_dur, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_WAKE_UP_DUR_EXT, (uint8_t *)&wup_dur_ext, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1); + + if (ret == 0) + { + switch(wup_dur.wake_dur) { + case 0x0: + val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ? + LIS2DUX12_3_ODR : LIS2DUX12_0_ODR; + break; + + case 0x1: + val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ? + LIS2DUX12_7_ODR : LIS2DUX12_1_ODR; + break; + + case 0x2: + val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ? + LIS2DUX12_11_ODR : LIS2DUX12_2_ODR; + break; + + case 0x3: + default: + val->wake_dur = LIS2DUX12_15_ODR; + break; + } + + val->sleep_dur = wup_dur.sleep_dur; + + val->wake_ths_weight = int_cfg.wake_ths_w; + val->wake_ths = wup_ths.wk_ths; + val->wake_enable = (enum wake_enable)wup_ths.sleep_on; + val->inact_odr = (enum inact_odr)ctrl4.inact_odr; + } + + return ret; +} + +/** + * @} + * + */ + +int32_t lis2dux12_tap_config_set(stmdev_ctx_t *ctx, lis2dux12_tap_config_t val) +{ + lis2dux12_tap_cfg0_t tap_cfg0; + lis2dux12_tap_cfg1_t tap_cfg1; + lis2dux12_tap_cfg2_t tap_cfg2; + lis2dux12_tap_cfg3_t tap_cfg3; + lis2dux12_tap_cfg4_t tap_cfg4; + lis2dux12_tap_cfg5_t tap_cfg5; + lis2dux12_tap_cfg6_t tap_cfg6; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_TAP_CFG3, (uint8_t *)&tap_cfg3, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_TAP_CFG4, (uint8_t *)&tap_cfg4, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_TAP_CFG5, (uint8_t *)&tap_cfg5, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_TAP_CFG6, (uint8_t *)&tap_cfg6, 1); + + if (ret == 0) + { + tap_cfg0.axis = (uint8_t)val.axis; + tap_cfg0.invert_t = val.inverted_peak_time; + tap_cfg1.pre_still_ths = val.pre_still_ths; + tap_cfg3.post_still_ths = val.post_still_ths; + tap_cfg1.post_still_t = val.post_still_time & 0xFU; + tap_cfg2.post_still_t = val.post_still_time >> 4; + tap_cfg2.wait_t = val.shock_wait_time; + tap_cfg3.latency_t = val.latency; + tap_cfg4.wait_end_latency = val.wait_end_latency; + tap_cfg4.peak_ths = val.peak_ths; + tap_cfg5.rebound_t = val.rebound; + tap_cfg5.single_tap_en = val.single_tap_on; + tap_cfg5.double_tap_en = val.double_tap_on; + tap_cfg5.triple_tap_en = val.triple_tap_on; + tap_cfg6.pre_still_st = val.pre_still_start; + tap_cfg6.pre_still_n = val.pre_still_n; + + ret += lis2dux12_write_reg(ctx, LIS2DUX12_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_TAP_CFG3, (uint8_t *)&tap_cfg3, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_TAP_CFG4, (uint8_t *)&tap_cfg4, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_TAP_CFG5, (uint8_t *)&tap_cfg5, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_TAP_CFG6, (uint8_t *)&tap_cfg6, 1); + } + + return ret; +} + +int32_t lis2dux12_tap_config_get(stmdev_ctx_t *ctx, lis2dux12_tap_config_t *val) +{ + lis2dux12_tap_cfg0_t tap_cfg0; + lis2dux12_tap_cfg1_t tap_cfg1; + lis2dux12_tap_cfg2_t tap_cfg2; + lis2dux12_tap_cfg3_t tap_cfg3; + lis2dux12_tap_cfg4_t tap_cfg4; + lis2dux12_tap_cfg5_t tap_cfg5; + lis2dux12_tap_cfg6_t tap_cfg6; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_TAP_CFG3, (uint8_t *)&tap_cfg3, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_TAP_CFG4, (uint8_t *)&tap_cfg4, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_TAP_CFG5, (uint8_t *)&tap_cfg5, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_TAP_CFG6, (uint8_t *)&tap_cfg6, 1); + + if (ret == 0) + { + val->axis = (enum axis)tap_cfg0.axis; + val->inverted_peak_time = tap_cfg0.invert_t; + val->pre_still_ths = tap_cfg1.pre_still_ths; + val->post_still_ths = tap_cfg3.post_still_ths; + val->post_still_time = (tap_cfg2.post_still_t << 4) | tap_cfg1.post_still_t; + val->shock_wait_time = tap_cfg2.wait_t; + val->latency = tap_cfg3.latency_t; + val->wait_end_latency = tap_cfg4.wait_end_latency; + val->peak_ths = tap_cfg4.peak_ths; + val->rebound = tap_cfg5.rebound_t; + val->single_tap_on = tap_cfg5.single_tap_en; + val->double_tap_on = tap_cfg5.double_tap_en; + val->triple_tap_on = tap_cfg5.triple_tap_en; + val->pre_still_start = tap_cfg6.pre_still_st; + val->pre_still_n = tap_cfg6.pre_still_n; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup lis2dux12_Timestamp + * @brief This section groups all the functions that manage the + * timestamp generation. + * @{ + * + */ + +/** + * @brief Enables timestamp counter.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of timestamp_en in reg INTERRUPT_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2dux12_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lis2dux12_interrupt_cfg_t int_cfg; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1); + + if (ret == 0) + { + int_cfg.timestamp_en = (uint8_t)val; + ret = lis2dux12_write_reg(ctx, LIS2DUX12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1); + } + + return ret; +} + +/** + * @brief Enables timestamp counter.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of timestamp_en in reg INTERRUPT_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2dux12_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lis2dux12_interrupt_cfg_t int_cfg; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1); + *val = int_cfg.timestamp_en; + + return ret; +} + +/** + * @brief Timestamp first data output register (r). + * The value is expressed as a 32-bit word and the bit resolution + * is 10 us.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2dux12_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) +{ + uint8_t buff[4]; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_TIMESTAMP0, buff, 4); + *val = buff[3]; + *val = (*val * 256U) + buff[2]; + *val = (*val * 256U) + buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LIS2DUX12_finite_state_machine + * @brief This section groups all the functions that manage the + * state_machine. + * @{ + * + */ + +/** + * @brief Interrupt status bit for FSM long counter timeout interrupt + * event.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of is_fsm_lc in reg EMB_FUNC_STATUS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2dux12_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, + uint8_t *val) +{ + lis2dux12_emb_func_status_t emb_func_status; + int32_t ret; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_STATUS, + (uint8_t *)&emb_func_status, 1); + + *val = emb_func_status.is_fsm_lc; + } + + ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Embedded final state machine functions mode.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fsm_en in reg EMB_FUNC_EN_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2dux12_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val) +{ + int32_t ret; + + lis2dux12_emb_func_en_b_t emb_func_en_b; + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + + emb_func_en_b.fsm_en = (uint8_t)val; + + ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + } + + ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Embedded final state machine functions mode.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of fsm_en in reg EMB_FUNC_EN_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2dux12_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + int32_t ret; + + lis2dux12_emb_func_en_b_t emb_func_en_b; + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + + *val = emb_func_en_b.fsm_en; + + ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + } + + ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Embedded final state machine functions mode.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2dux12_fsm_enable_set(stmdev_ctx_t *ctx, + lis2dux12_emb_fsm_enable_t *val) +{ + lis2dux12_emb_func_en_b_t emb_func_en_b; + int32_t ret; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2dux12_write_reg(ctx, LIS2DUX12_FSM_ENABLE, + (uint8_t *)&val->fsm_enable, 1); + } + + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + + if ((val->fsm_enable.fsm1_en | + val->fsm_enable.fsm2_en | + val->fsm_enable.fsm3_en | + val->fsm_enable.fsm4_en | + val->fsm_enable.fsm5_en | + val->fsm_enable.fsm6_en | + val->fsm_enable.fsm7_en | + val->fsm_enable.fsm8_en) != PROPERTY_DISABLE) + { + emb_func_en_b.fsm_en = PROPERTY_ENABLE; + } + else + { + emb_func_en_b.fsm_en = PROPERTY_DISABLE; + } + + ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + } + + ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Embedded final state machine functions mode.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2dux12_fsm_enable_get(stmdev_ctx_t *ctx, + lis2dux12_emb_fsm_enable_t *val) +{ + int32_t ret; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_FSM_ENABLE, + (uint8_t *)&val->fsm_enable, 1); + } + + ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief FSM long counter status register. Long counter value is an + * unsigned integer value (16-bit format).[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2dux12_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = lis2dux12_write_reg(ctx, LIS2DUX12_FSM_LONG_COUNTER_L, buff, 2); + } + + ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief FSM long counter status register. Long counter value is an + * unsigned integer value (16-bit format).[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2dux12_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_FSM_LONG_COUNTER_L, buff, 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } + + ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief FSM status.[get] + * + * @param ctx read / write interface definitions + * @param val register FSM_STATUS_MAINPAGE + * + */ +int32_t lis2dux12_fsm_status_get(stmdev_ctx_t *ctx, + lis2dux12_fsm_status_mainpage_t *val) +{ + return lis2dux12_read_reg(ctx, LIS2DUX12_FSM_STATUS_MAINPAGE, + (uint8_t *) val, 1); +} + +/** + * @brief FSM output registers.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Structure of registers from FSM_OUTS1 to FSM_OUTS16 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2dux12_fsm_out_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + int32_t ret; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_FSM_OUTS1, val, 8); + } + + ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Finite State Machine ODR configuration.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2dux12_fsm_data_rate_set(stmdev_ctx_t *ctx, + lis2dux12_fsm_val_odr_t val) +{ + lis2dux12_fsm_odr_t fsm_odr_reg; + int32_t ret; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_FSM_ODR, + (uint8_t *)&fsm_odr_reg, 1); + + fsm_odr_reg.fsm_odr = (uint8_t)val; + ret += lis2dux12_write_reg(ctx, LIS2DUX12_FSM_ODR, + (uint8_t *)&fsm_odr_reg, 1); + } + + ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Finite State Machine ODR configuration.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2dux12_fsm_data_rate_get(stmdev_ctx_t *ctx, + lis2dux12_fsm_val_odr_t *val) +{ + lis2dux12_fsm_odr_t fsm_odr_reg; + int32_t ret; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_FSM_ODR, + (uint8_t *)&fsm_odr_reg, 1); + } + + ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + switch (fsm_odr_reg.fsm_odr) + { + case LIS2DUX12_ODR_FSM_12Hz5: + *val = LIS2DUX12_ODR_FSM_12Hz5; + break; + + case LIS2DUX12_ODR_FSM_25Hz: + *val = LIS2DUX12_ODR_FSM_25Hz; + break; + + case LIS2DUX12_ODR_FSM_50Hz: + *val = LIS2DUX12_ODR_FSM_50Hz; + break; + + case LIS2DUX12_ODR_FSM_100Hz: + *val = LIS2DUX12_ODR_FSM_100Hz; + break; + + case LIS2DUX12_ODR_FSM_200Hz: + *val = LIS2DUX12_ODR_FSM_200Hz; + break; + + case LIS2DUX12_ODR_FSM_400Hz: + *val = LIS2DUX12_ODR_FSM_400Hz; + break; + + case LIS2DUX12_ODR_FSM_800Hz: + *val = LIS2DUX12_ODR_FSM_800Hz; + break; + + default: + *val = LIS2DUX12_ODR_FSM_12Hz5; + break; + } + + return ret; +} + +/** + * @brief FSM initialization request.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fsm_init in reg FSM_INIT + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2dux12_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lis2dux12_emb_func_init_b_t emb_func_init_b; + int32_t ret; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_INIT_B, + (uint8_t *)&emb_func_init_b, 1); + + emb_func_init_b.fsm_init = (uint8_t)val; + + ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_INIT_B, + (uint8_t *)&emb_func_init_b, 1); + } + + ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief FSM initialization request.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fsm_init in reg FSM_INIT + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2dux12_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lis2dux12_emb_func_init_b_t emb_func_init_b; + int32_t ret; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_INIT_B, + (uint8_t *)&emb_func_init_b, 1); + + *val = emb_func_init_b.fsm_init; + } + + ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief FSM long counter timeout register (r/w). The long counter + * timeout value is an unsigned integer value (16-bit format). + * When the long counter value reached this value, the FSM + * generates an interrupt.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2dux12_long_cnt_int_value_set(stmdev_ctx_t *ctx, + uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = lis2dux12_ln_pg_write(ctx, LIS2DUX12_FSM_LC_TIMEOUT_L, buff, 2); + + return ret; +} + +/** + * @brief FSM long counter timeout register (r/w). The long counter + * timeout value is an unsigned integer value (16-bit format). + * When the long counter value reached this value, the FSM generates + * an interrupt.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2dux12_long_cnt_int_value_get(stmdev_ctx_t *ctx, + uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lis2dux12_ln_pg_read(ctx, LIS2DUX12_FSM_LC_TIMEOUT_L, buff, 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief FSM number of programs register.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2dux12_fsm_number_of_programs_set(stmdev_ctx_t *ctx, + uint8_t *buff) +{ + int32_t ret; + + ret = lis2dux12_ln_pg_write(ctx, LIS2DUX12_FSM_PROGRAMS, buff, 2); + + return ret; +} + +/** + * @brief FSM number of programs register.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2dux12_fsm_number_of_programs_get(stmdev_ctx_t *ctx, + uint8_t *buff) +{ + int32_t ret; + + ret = lis2dux12_ln_pg_read(ctx, LIS2DUX12_FSM_PROGRAMS, buff, 2); + + return ret; +} + +/** + * @brief FSM start address register (r/w). First available address is + * 0x033C.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2dux12_fsm_start_address_set(stmdev_ctx_t *ctx, + uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = lis2dux12_ln_pg_write(ctx, LIS2DUX12_FSM_START_ADD_L, buff, 2); + + return ret; +} + +/** + * @brief FSM start address register (r/w). First available address + * is 0x033C.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2dux12_fsm_start_address_get(stmdev_ctx_t *ctx, + uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lis2dux12_ln_pg_read(ctx, LIS2DUX12_FSM_START_ADD_L, buff, 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @addtogroup Machine Learning Core + * @brief This section group all the functions concerning the + * usage of Machine Learning Core + * @{ + * + */ + +/** + * @brief Enable Machine Learning Core.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of mlc_en in + * reg EMB_FUNC_EN_B and mlc_before_fsm_en + * in EMB_FUNC_INIT_A + * + */ +int32_t lis2dux12_mlc_set(stmdev_ctx_t *ctx, lis2dux12_mlc_mode_t val) +{ + lis2dux12_emb_func_en_a_t emb_en_a; + lis2dux12_emb_func_en_b_t emb_en_b; + int32_t ret; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + + switch(val) + { + case LIS2DUX12_MLC_OFF: + emb_en_a.mlc_before_fsm_en = 0; + emb_en_b.mlc_en = 0; + break; + case LIS2DUX12_MLC_ON: + emb_en_a.mlc_before_fsm_en = 0; + emb_en_b.mlc_en = 1; + break; + case LIS2DUX12_MLC_ON_BEFORE_FSM: + emb_en_a.mlc_before_fsm_en = 1; + emb_en_b.mlc_en = 0; + break; + default: + break; + } + + ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + } + + ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable Machine Learning Core.[get] + * + * @param ctx read / write interface definitions + * @param val get the values of mlc_en in + * reg EMB_FUNC_EN_B and mlc_before_fsm_en + * in EMB_FUNC_INIT_A + * + */ +int32_t lis2dux12_mlc_get(stmdev_ctx_t *ctx, lis2dux12_mlc_mode_t *val) +{ + lis2dux12_emb_func_en_a_t emb_en_a; + lis2dux12_emb_func_en_b_t emb_en_b; + int32_t ret; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + + if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U) + { + *val = LIS2DUX12_MLC_OFF; + } + else if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 1U) + { + *val = LIS2DUX12_MLC_ON; + } + else if (emb_en_a.mlc_before_fsm_en == 1U) + { + *val = LIS2DUX12_MLC_ON_BEFORE_FSM; + } + else + { + /* Do nothing */ + } + } + + ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Machine Learning Core status register[get] + * + * @param ctx read / write interface definitions + * @param val register MLC_STATUS_MAINPAGE + * + */ +int32_t lis2dux12_mlc_status_get(stmdev_ctx_t *ctx, + lis2dux12_mlc_status_mainpage_t *val) +{ + return lis2dux12_read_reg(ctx, LIS2DUX12_MLC_STATUS_MAINPAGE, + (uint8_t *) val, 1); +} + +/** + * @brief prgsens_out: [get] Output value of all MLCx decision trees. + * + * @param ctx_t *ctx: read / write interface definitions + * @param uint8_t * : buffer that stores data read + * + */ +int32_t lis2dux12_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_MLC1_SRC, buff, 4); + } + + ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Machine Learning Core data rate selection.[set] + * + * @param ctx read / write interface definitions + * @param val get the values of mlc_odr in + * reg EMB_FUNC_ODR_CFG_C + * + */ +int32_t lis2dux12_mlc_data_rate_set(stmdev_ctx_t *ctx, + lis2dux12_mlc_odr_val_t val) +{ + lis2dux12_mlc_odr_t reg; + int32_t ret; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_MLC_ODR, (uint8_t *)®, 1); + reg.mlc_odr = (uint8_t)val; + ret += lis2dux12_write_reg(ctx, LIS2DUX12_MLC_ODR, (uint8_t *)®, 1); + } + + if (ret == 0) + { + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief Machine Learning Core data rate selection.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of mlc_odr in + * reg EMB_FUNC_ODR_CFG_C + * + */ +int32_t lis2dux12_mlc_data_rate_get(stmdev_ctx_t *ctx, + lis2dux12_mlc_odr_val_t *val) +{ + lis2dux12_mlc_odr_t reg; + int32_t ret; + + ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_MLC_ODR, (uint8_t *)®, 1); + + switch (reg.mlc_odr) + { + case LIS2DUX12_ODR_PRGS_12Hz5: + *val = LIS2DUX12_ODR_PRGS_12Hz5; + break; + + case LIS2DUX12_ODR_PRGS_25Hz: + *val = LIS2DUX12_ODR_PRGS_25Hz; + break; + + case LIS2DUX12_ODR_PRGS_50Hz: + *val = LIS2DUX12_ODR_PRGS_50Hz; + break; + + case LIS2DUX12_ODR_PRGS_100Hz: + *val = LIS2DUX12_ODR_PRGS_100Hz; + break; + + case LIS2DUX12_ODR_PRGS_200Hz: + *val = LIS2DUX12_ODR_PRGS_200Hz; + break; + + default: + *val = LIS2DUX12_ODR_PRGS_12Hz5; + break; + } + } + + ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis2dux12_STdC/driver/lis2dux12_reg.h b/sensor/stmemsc/lis2dux12_STdC/driver/lis2dux12_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..be29b23ee4691a20d7faa4fbb881a4efae3c5372 --- /dev/null +++ b/sensor/stmemsc/lis2dux12_STdC/driver/lis2dux12_reg.h @@ -0,0 +1,2597 @@ +/* + ****************************************************************************** + * @file lis2dux12_reg.h + * @author Sensors Software Solution Team + * @brief This file contains all the functions prototypes for the + * lis2dux12_reg.c driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2022 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef LIS2DUX12_REGS_H +#define LIS2DUX12_REGS_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include + +/** @addtogroup LIS2DUX12 + * @{ + * + */ + +/** @defgroup Endianness definitions + * @{ + * + */ + +#ifndef DRV_BYTE_ORDER +#ifndef __BYTE_ORDER__ + +#define DRV_LITTLE_ENDIAN 1234 +#define DRV_BIG_ENDIAN 4321 + +/** if _BYTE_ORDER is not defined, choose the endianness of your architecture + * by uncommenting the define which fits your platform endianness + */ +//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN +#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN + +#else /* defined __BYTE_ORDER__ */ + +#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ +#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ +#define DRV_BYTE_ORDER __BYTE_ORDER__ + +#endif /* __BYTE_ORDER__*/ +#endif /* DRV_BYTE_ORDER */ + +/** + * @} + * + */ + +/** @defgroup STMicroelectronics sensors common types + * @{ + * + */ + +#ifndef MEMS_SHARED_TYPES +#define MEMS_SHARED_TYPES + +typedef struct{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} bitwise_t; + +#define PROPERTY_DISABLE (0U) +#define PROPERTY_ENABLE (1U) + +/** @addtogroup Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); +typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); + +typedef struct +{ + /** Component mandatory fields **/ + stmdev_write_ptr write_reg; + stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; + /** Customizable optional pointer **/ + void *handle; +} stmdev_ctx_t; + +/** + * @} + * + */ + +#endif /* MEMS_SHARED_TYPES */ + +#ifndef MEMS_UCF_SHARED_TYPES +#define MEMS_UCF_SHARED_TYPES + +/** @defgroup Generic address-data structure definition + * @brief This structure is useful to load a predefined configuration + * of a sensor. + * You can create a sensor configuration by your own or using + * Unico / Unicleo tools available on STMicroelectronics + * web site. + * + * @{ + * + */ + +typedef struct { + uint8_t address; + uint8_t data; +} ucf_line_t; + +/** + * @} + * + */ + +#endif /* MEMS_UCF_SHARED_TYPES */ + +/** + * @} + * + */ + +/** @defgroup LIS2DUX12_Infos + * @{ + * + */ + +/** I2C Device Address 8 bit format if SA0=0 -> 0x if SA0=1 -> 0x **/ +#define LIS2DUX12_I2C_ADD_L 0x31U +#define LIS2DUX12_I2C_ADD_H 0x33U + +/** Device Identification (Who am I) **/ +#define LIS2DUX12_ID 0x47U + +/** + * @} + * + */ + +#define LIS2DUX12_PIN_CTRL 0x0CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sim : 1; + uint8_t pp_od : 1; + uint8_t cs_pu_dis : 1; + uint8_t h_lactive : 1; + uint8_t pd_dis_int1 : 1; + uint8_t pd_dis_int2 : 1; + uint8_t sda_pu_en : 1; + uint8_t sdo_pu_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sdo_pu_en : 1; + uint8_t sda_pu_en : 1; + uint8_t pd_dis_int2 : 1; + uint8_t pd_dis_int1 : 1; + uint8_t h_lactive : 1; + uint8_t cs_pu_dis : 1; + uint8_t pp_od : 1; + uint8_t sim : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_pin_ctrl_t; + +#define LIS2DUX12_WAKE_UP_DUR_EXT 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 4; + uint8_t wu_dur_extended : 1; + uint8_t not_used1 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 3; + uint8_t wu_dur_extended : 1; + uint8_t not_used0 : 4; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_wake_up_dur_ext_t; + +#define LIS2DUX12_WHO_AM_I 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t id : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t id : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_who_am_i_t; + +#define LIS2DUX12_CTRL1 0x10U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wu_z_en : 1; + uint8_t wu_y_en : 1; + uint8_t wu_x_en : 1; + uint8_t drdy_pulsed : 1; + uint8_t if_add_inc : 1; + uint8_t sw_reset : 1; + uint8_t int1_on_res : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t int1_on_res : 1; + uint8_t sw_reset : 1; + uint8_t if_add_inc : 1; + uint8_t drdy_pulsed : 1; + uint8_t wu_x_en : 1; + uint8_t wu_y_en : 1; + uint8_t wu_z_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_ctrl1_t; + +#define LIS2DUX12_CTRL2 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t int1_drdy : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_fifo_th : 1; + uint8_t int1_fifo_full : 1; + uint8_t int1_boot : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_boot : 1; + uint8_t int1_fifo_full : 1; + uint8_t int1_fifo_th : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_drdy : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_ctrl2_t; + +#define LIS2DUX12_CTRL3 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t st_sign_x : 1; + uint8_t st_sign_y : 1; + uint8_t hp_en : 1; + uint8_t int2_drdy : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_fifo_th : 1; + uint8_t int2_fifo_full : 1; + uint8_t int2_boot : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_boot : 1; + uint8_t int2_fifo_full : 1; + uint8_t int2_fifo_th : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_drdy : 1; + uint8_t hp_en : 1; + uint8_t st_sign_y : 1; + uint8_t st_sign_x : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_ctrl3_t; + +#define LIS2DUX12_CTRL4 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t boot : 1; + uint8_t soc : 1; + uint8_t not_used0 : 1; + uint8_t fifo_en : 1; + uint8_t emb_func_en : 1; + uint8_t bdu : 1; + uint8_t inact_odr : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t inact_odr : 2; + uint8_t bdu : 1; + uint8_t emb_func_en : 1; + uint8_t fifo_en : 1; + uint8_t not_used0 : 1; + uint8_t soc : 1; + uint8_t boot : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_ctrl4_t; + +#define LIS2DUX12_CTRL5 0x14U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs : 2; + uint8_t bw : 2; + uint8_t odr : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t odr : 4; + uint8_t bw : 2; + uint8_t fs : 2; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_ctrl5_t; + +#define LIS2DUX12_FIFO_CTRL 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_mode : 3; + uint8_t stop_on_fth : 1; + uint8_t not_used0 : 2; + uint8_t fifo_depth : 1; + uint8_t cfg_chg_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t cfg_chg_en : 1; + uint8_t fifo_depth : 1; + uint8_t not_used0 : 2; + uint8_t stop_on_fth : 1; + uint8_t fifo_mode : 3; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fifo_ctrl_t; + +#define LIS2DUX12_FIFO_WTM 0x16U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fth : 7; + uint8_t xl_only_fifo : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t xl_only_fifo : 1; + uint8_t fth : 7; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fifo_wtm_t; + +#define LIS2DUX12_INTERRUPT_CFG 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t interrupts_enable : 1; + uint8_t lir : 1; + uint8_t dis_rst_lir_all_int : 1; + uint8_t sleep_status_on_int : 1; + uint8_t not_used0 : 1; + uint8_t wake_ths_w : 1; + uint8_t not_used1 : 1; + uint8_t timestamp_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp_en : 1; + uint8_t not_used1 : 1; + uint8_t wake_ths_w : 1; + uint8_t not_used0 : 1; + uint8_t sleep_status_on_int : 1; + uint8_t dis_rst_lir_all_int : 1; + uint8_t lir : 1; + uint8_t interrupts_enable : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_interrupt_cfg_t; + +#define LIS2DUX12_SIXD 0x18U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 5; + uint8_t d6d_ths : 2; + uint8_t d4d_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t d4d_en : 1; + uint8_t d6d_ths : 2; + uint8_t not_used0 : 5; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_sixd_t; + +#define LIS2DUX12_WAKE_UP_THS 0x1CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wk_ths : 6; + uint8_t sleep_on : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t sleep_on : 1; + uint8_t wk_ths : 6; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_wake_up_ths_t; + +#define LIS2DUX12_WAKE_UP_DUR 0x1DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sleep_dur : 4; + uint8_t st_sign_z : 1; + uint8_t wake_dur : 2; + uint8_t ff_dur : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ff_dur : 1; + uint8_t wake_dur : 2; + uint8_t st_sign_z : 1; + uint8_t sleep_dur : 4; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_wake_up_dur_t; + +#define LIS2DUX12_FREE_FALL 0x1EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ff_ths : 3; + uint8_t ff_dur : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ff_dur : 5; + uint8_t ff_ths : 3; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_free_fall_t; + +#define LIS2DUX12_MD1_CFG 0x1FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_emb_func : 1; + uint8_t int1_timestamp : 1; + uint8_t int1_6d : 1; + uint8_t int1_tap : 1; + uint8_t int1_ff : 1; + uint8_t int1_wu : 1; + uint8_t not_used0 : 1; + uint8_t int1_sleep_change : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_sleep_change : 1; + uint8_t not_used0 : 1; + uint8_t int1_wu : 1; + uint8_t int1_ff : 1; + uint8_t int1_tap : 1; + uint8_t int1_6d : 1; + uint8_t int1_timestamp : 1; + uint8_t int1_emb_func : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_md1_cfg_t; + +#define LIS2DUX12_MD2_CFG 0x20U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_emb_func : 1; + uint8_t int2_timestamp : 1; + uint8_t int2_6d : 1; + uint8_t int2_tap : 1; + uint8_t int2_ff : 1; + uint8_t int2_wu : 1; + uint8_t not_used0 : 1; + uint8_t int2_sleep_change : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_sleep_change : 1; + uint8_t not_used0 : 1; + uint8_t int2_wu : 1; + uint8_t int2_ff : 1; + uint8_t int2_tap : 1; + uint8_t int2_6d : 1; + uint8_t int2_timestamp : 1; + uint8_t int2_emb_func : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_md2_cfg_t; + +#define LIS2DUX12_WAKE_UP_SRC 0x21U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t z_wu : 1; + uint8_t y_wu : 1; + uint8_t x_wu : 1; + uint8_t wu_ia : 1; + uint8_t sleep_state : 1; + uint8_t ff_ia : 1; + uint8_t sleep_change_ia : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t sleep_change_ia : 1; + uint8_t ff_ia : 1; + uint8_t sleep_state : 1; + uint8_t wu_ia : 1; + uint8_t x_wu : 1; + uint8_t y_wu : 1; + uint8_t z_wu : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_wake_up_src_t; + +#define LIS2DUX12_TAP_SRC 0x22U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 4; + uint8_t triple_tap_ia : 1; + uint8_t double_tap_ia : 1; + uint8_t single_tap_ia : 1; + uint8_t tap_ia : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tap_ia : 1; + uint8_t single_tap_ia : 1; + uint8_t double_tap_ia : 1; + uint8_t triple_tap_ia : 1; + uint8_t not_used0 : 4; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_tap_src_t; + +#define LIS2DUX12_SIXD_SRC 0x23U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xl : 1; + uint8_t xh : 1; + uint8_t yl : 1; + uint8_t yh : 1; + uint8_t zl : 1; + uint8_t zh : 1; + uint8_t d6d_ia : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t d6d_ia : 1; + uint8_t zh : 1; + uint8_t zl : 1; + uint8_t yh : 1; + uint8_t yl : 1; + uint8_t xh : 1; + uint8_t xl : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_sixd_src_t; + +#define LIS2DUX12_ALL_INT_SRC 0x24U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ff_ia_all : 1; + uint8_t wu_ia_all : 1; + uint8_t single_tap_all : 1; + uint8_t double_tap_all : 1; + uint8_t triple_tap_all : 1; + uint8_t d6d_ia_all : 1; + uint8_t sleep_change_ia_all : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t sleep_change_ia_all : 1; + uint8_t d6d_ia_all : 1; + uint8_t triple_tap_all : 1; + uint8_t double_tap_all : 1; + uint8_t single_tap_all : 1; + uint8_t wu_ia_all : 1; + uint8_t ff_ia_all : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_all_int_src_t; + +#define LIS2DUX12_STATUS 0x25U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t drdy : 1; + uint8_t not_used0 : 4; + uint8_t int_global : 1; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t int_global : 1; + uint8_t not_used0 : 4; + uint8_t drdy : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_status_register_t; + +#define LIS2DUX12_FIFO_STATUS1 0x26U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 6; + uint8_t fifo_ovr_ia : 1; + uint8_t fifo_wtm_ia : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_wtm_ia : 1; + uint8_t fifo_ovr_ia : 1; + uint8_t not_used0 : 6; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fifo_status1_t; + +#define LIS2DUX12_FIFO_STATUS2 0x27U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fss : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fss : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fifo_status2_t; + +#define LIS2DUX12_OUT_X_L 0x28U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_out_x_l_t; + +#define LIS2DUX12_OUT_X_H 0x29U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_out_x_h_t; + +#define LIS2DUX12_OUT_Y_L 0x2AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_out_y_l_t; + +#define LIS2DUX12_OUT_Y_H 0x2BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_out_y_h_t; + +#define LIS2DUX12_OUT_Z_L 0x2CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_out_z_l_t; + +#define LIS2DUX12_OUT_Z_H 0x2DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_out_z_h_t; + +#define LIS2DUX12_OUT_T_L 0x2EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outt : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outt : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_out_t_l_t; + +#define LIS2DUX12_OUT_T_H 0x2FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outt : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outt : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_out_t_h_t; + +#define LIS2DUX12_SELF_TEST 0x32U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 4; + uint8_t st : 2; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t st : 2; + uint8_t not_used0 : 4; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_self_test_t; + +#define LIS2DUX12_I3C_IF_CTRL 0x33U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bus_act_sel : 2; + uint8_t not_used0 : 3; + uint8_t asf_on : 1; + uint8_t dis_drstdaa : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t dis_drstdaa : 1; + uint8_t asf_on : 1; + uint8_t not_used0 : 3; + uint8_t bus_act_sel : 2; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_i3c_if_ctrl_t; + +#define LIS2DUX12_EMB_FUNC_STATUS_MAINPAGE 0x34U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t is_step_det : 1; + uint8_t is_tilt : 1; + uint8_t is_sigmot : 1; + uint8_t not_used1 : 1; + uint8_t is_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t is_sigmot : 1; + uint8_t is_tilt : 1; + uint8_t is_step_det : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_emb_func_status_mainpage_t; + +#define LIS2DUX12_FSM_STATUS_MAINPAGE 0x35U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm1 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm8 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fsm_status_mainpage_t; + +#define LIS2DUX12_MLC_STATUS_MAINPAGE 0x36U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_mlc1 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc4 : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t is_mlc4 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_mlc_status_mainpage_t; + +#define LIS2DUX12_SLEEP 0x3DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t deep_pd : 1; + uint8_t not_used0 : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 7; + uint8_t deep_pd : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_sleep_t; + +#define LIS2DUX12_IF_WAKE_UP 0x3EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t soft_pd : 1; + uint8_t not_used0 : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 7; + uint8_t soft_pd : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_if_wake_up_t; + +#define LIS2DUX12_FUNC_CFG_ACCESS 0x3FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_wr_ctrl_en : 1; + uint8_t not_used0 : 6; + uint8_t emb_func_reg_access : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t emb_func_reg_access : 1; + uint8_t not_used0 : 6; + uint8_t fsm_wr_ctrl_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_func_cfg_access_t; + +#define LIS2DUX12_FIFO_DATA_OUT_TAG 0x40U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t tag_sensor : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tag_sensor : 5; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fifo_data_out_tag_t; + +#define LIS2DUX12_FIFO_DATA_OUT_X_L 0x41U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fifo_data_out_x_l_t; + +#define LIS2DUX12_FIFO_DATA_OUT_X_H 0x42U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fifo_data_out_x_h_t; + +#define LIS2DUX12_FIFO_DATA_OUT_Y_L 0x43U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fifo_data_out_y_l_t; + +#define LIS2DUX12_FIFO_DATA_OUT_Y_H 0x44U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fifo_data_out_y_h_t; + +#define LIS2DUX12_FIFO_DATA_OUT_Z_L 0x45U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fifo_data_out_z_l_t; + +#define LIS2DUX12_FIFO_DATA_OUT_Z_H 0x46U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fifo_data_out_z_h_t; + +#define LIS2DUX12_FIFO_BATCH_DEC 0x47U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bdr_xl : 3; + uint8_t dec_ts_batch : 2; + uint8_t not_used0 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 3; + uint8_t dec_ts_batch : 2; + uint8_t bdr_xl : 3; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fifo_batch_dec_t; + +#define LIS2DUX12_TAP_CFG0 0x6FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t invert_t : 5; + uint8_t axis : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t axis : 2; + uint8_t invert_t : 5; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_tap_cfg0_t; + +#define LIS2DUX12_TAP_CFG1 0x70U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t post_still_t : 4; + uint8_t pre_still_ths : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pre_still_ths : 4; + uint8_t post_still_t : 4; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_tap_cfg1_t; + +#define LIS2DUX12_TAP_CFG2 0x71U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wait_t : 6; + uint8_t post_still_t : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t post_still_t : 2; + uint8_t wait_t : 6; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_tap_cfg2_t; + +#define LIS2DUX12_TAP_CFG3 0x72U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t latency_t : 4; + uint8_t post_still_ths : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t post_still_ths : 4; + uint8_t latency_t : 4; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_tap_cfg3_t; + +#define LIS2DUX12_TAP_CFG4 0x73U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t peak_ths : 6; + uint8_t not_used0 : 1; + uint8_t wait_end_latency : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t wait_end_latency : 1; + uint8_t not_used0 : 1; + uint8_t peak_ths : 6; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_tap_cfg4_t; + +#define LIS2DUX12_TAP_CFG5 0x74U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t rebound_t : 5; + uint8_t single_tap_en : 1; + uint8_t double_tap_en : 1; + uint8_t triple_tap_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t triple_tap_en : 1; + uint8_t double_tap_en : 1; + uint8_t single_tap_en : 1; + uint8_t rebound_t : 5; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_tap_cfg5_t; + +#define LIS2DUX12_TAP_CFG6 0x75U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t pre_still_n : 4; + uint8_t pre_still_st : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pre_still_st : 4; + uint8_t pre_still_n : 4; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_tap_cfg6_t; + +#define LIS2DUX12_TIMESTAMP0 0x7AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_timestamp0_t; + +#define LIS2DUX12_TIMESTAMP1 0x7BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_timestamp1_t; + +#define LIS2DUX12_TIMESTAMP2 0x7CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_timestamp2_t; + +#define LIS2DUX12_TIMESTAMP3 0x7DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_timestamp3_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page embedded + * @{ + * + */ + +#define LIS2DUX12_PAGE_SEL 0x2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 4; + uint8_t page_sel : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_sel : 4; + uint8_t not_used0 : 4; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_page_sel_t; + +#define LIS2DUX12_EMB_FUNC_EN_A 0x4U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t pedo_en : 1; + uint8_t tilt_en : 1; + uint8_t sign_motion_en : 1; + uint8_t not_used1 : 1; + uint8_t mlc_before_fsm_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_before_fsm_en : 1; + uint8_t not_used1 : 1; + uint8_t sign_motion_en : 1; + uint8_t tilt_en : 1; + uint8_t pedo_en : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_emb_func_en_a_t; + +#define LIS2DUX12_EMB_FUNC_EN_B 0x5U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_en : 1; + uint8_t not_used0 : 3; + uint8_t mlc_en : 1; + uint8_t not_used1 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 3; + uint8_t mlc_en : 1; + uint8_t not_used0 : 3; + uint8_t fsm_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_emb_func_en_b_t; + +#define LIS2DUX12_EMB_FUNC_EXEC_STATUS 0x7U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t emb_func_endop : 1; + uint8_t emb_func_exec_ovr : 1; + uint8_t not_used0 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 6; + uint8_t emb_func_exec_ovr : 1; + uint8_t emb_func_endop : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_emb_func_exec_status_t; + +#define LIS2DUX12_PAGE_ADDRESS 0x8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t page_addr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_addr : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_page_address_t; + +#define LIS2DUX12_PAGE_VALUE 0x9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t page_value : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_value : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_page_value_t; + +#define LIS2DUX12_EMB_FUNC_INT1 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t int1_step_det : 1; + uint8_t int1_tilt : 1; + uint8_t int1_sig_mot : 1; + uint8_t not_used1 : 1; + uint8_t int1_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t int1_sig_mot : 1; + uint8_t int1_tilt : 1; + uint8_t int1_step_det : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_emb_func_int1_t; + +#define LIS2DUX12_FSM_INT1 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_fsm1 : 1; + uint8_t int1_fsm2 : 1; + uint8_t int1_fsm3 : 1; + uint8_t int1_fsm4 : 1; + uint8_t int1_fsm5 : 1; + uint8_t int1_fsm6 : 1; + uint8_t int1_fsm7 : 1; + uint8_t int1_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_fsm8 : 1; + uint8_t int1_fsm7 : 1; + uint8_t int1_fsm6 : 1; + uint8_t int1_fsm5 : 1; + uint8_t int1_fsm4 : 1; + uint8_t int1_fsm3 : 1; + uint8_t int1_fsm2 : 1; + uint8_t int1_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fsm_int1_t; + +#define LIS2DUX12_MLC_INT1 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_mlc1 : 1; + uint8_t int1_mlc2 : 1; + uint8_t int1_mlc3 : 1; + uint8_t int1_mlc4 : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t int1_mlc4 : 1; + uint8_t int1_mlc3 : 1; + uint8_t int1_mlc2 : 1; + uint8_t int1_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_mlc_int1_t; + +#define LIS2DUX12_EMB_FUNC_INT2 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t int2_step_det : 1; + uint8_t int2_tilt : 1; + uint8_t int2_sig_mot : 1; + uint8_t not_used1 : 1; + uint8_t int2_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t int2_sig_mot : 1; + uint8_t int2_tilt : 1; + uint8_t int2_step_det : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_emb_func_int2_t; + +#define LIS2DUX12_FSM_INT2 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_fsm1 : 1; + uint8_t int2_fsm2 : 1; + uint8_t int2_fsm3 : 1; + uint8_t int2_fsm4 : 1; + uint8_t int2_fsm5 : 1; + uint8_t int2_fsm6 : 1; + uint8_t int2_fsm7 : 1; + uint8_t int2_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_fsm8 : 1; + uint8_t int2_fsm7 : 1; + uint8_t int2_fsm6 : 1; + uint8_t int2_fsm5 : 1; + uint8_t int2_fsm4 : 1; + uint8_t int2_fsm3 : 1; + uint8_t int2_fsm2 : 1; + uint8_t int2_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fsm_int2_t; + +#define LIS2DUX12_MLC_INT2 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_mlc1 : 1; + uint8_t int2_mlc2 : 1; + uint8_t int2_mlc3 : 1; + uint8_t int2_mlc4 : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t int2_mlc4 : 1; + uint8_t int2_mlc3 : 1; + uint8_t int2_mlc2 : 1; + uint8_t int2_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_mlc_int2_t; + +#define LIS2DUX12_EMB_FUNC_STATUS 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t is_step_det : 1; + uint8_t is_tilt : 1; + uint8_t is_sigmot : 1; + uint8_t not_used1 : 1; + uint8_t is_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t is_sigmot : 1; + uint8_t is_tilt : 1; + uint8_t is_step_det : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_emb_func_status_t; + +#define LIS2DUX12_FSM_STATUS 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm1 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm8 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fsm_status_t; + +#define LIS2DUX12_MLC_STATUS 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_mlc1 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc4 : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t is_mlc4 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_mlc_status_t; + +#define LIS2DUX12_PAGE_RW 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 5; + uint8_t page_read : 1; + uint8_t page_write : 1; + uint8_t emb_func_lir : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t emb_func_lir : 1; + uint8_t page_write : 1; + uint8_t page_read : 1; + uint8_t not_used0 : 5; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_page_rw_t; + +#define LIS2DUX12_EMB_FUNC_FIFO_EN 0x18U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t step_counter_fifo_en : 1; + uint8_t mlc_fifo_en : 1; + uint8_t mlc_filter_feature_fifo_en : 1; + uint8_t fsm_fifo_en : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t fsm_fifo_en : 1; + uint8_t mlc_filter_feature_fifo_en : 1; + uint8_t mlc_fifo_en : 1; + uint8_t step_counter_fifo_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_emb_func_fifo_en_t; + +#define LIS2DUX12_FSM_ENABLE 0x1AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm1_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm8_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm8_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm1_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fsm_enable_t; + +#define LIS2DUX12_FSM_LONG_COUNTER_L 0x1CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fsm_long_counter_l_t; + +#define LIS2DUX12_FSM_LONG_COUNTER_H 0x1DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fsm_long_counter_h_t; + +#define LIS2DUX12_INT_ACK_MASK 0x1FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t iack_mask0 : 1; + uint8_t iack_mask1 : 1; + uint8_t iack_mask2 : 1; + uint8_t iack_mask3 : 1; + uint8_t iack_mask4 : 1; + uint8_t iack_mask5 : 1; + uint8_t iack_mask6 : 1; + uint8_t iack_mask7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t iack_mask7 : 1; + uint8_t iack_mask6 : 1; + uint8_t iack_mask5 : 1; + uint8_t iack_mask4 : 1; + uint8_t iack_mask3 : 1; + uint8_t iack_mask2 : 1; + uint8_t iack_mask1 : 1; + uint8_t iack_mask0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_int_ack_mask_t; + +#define LIS2DUX12_FSM_OUTS1 0x20U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fsm_outs1_t; + +#define LIS2DUX12_FSM_OUTS2 0x21U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fsm_outs2_t; + +#define LIS2DUX12_FSM_OUTS3 0x22U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fsm_outs3_t; + +#define LIS2DUX12_FSM_OUTS4 0x23U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fsm_outs4_t; + +#define LIS2DUX12_FSM_OUTS5 0x24U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fsm_outs5_t; + +#define LIS2DUX12_FSM_OUTS6 0x25U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fsm_outs6_t; + +#define LIS2DUX12_FSM_OUTS7 0x26U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fsm_outs7_t; + +#define LIS2DUX12_FSM_OUTS8 0x27U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fsm_outs8_t; + +#define LIS2DUX12_STEP_COUNTER_L 0x28U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t step : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t step : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_step_counter_l_t; + +#define LIS2DUX12_STEP_COUNTER_H 0x29U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t step : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t step : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_step_counter_h_t; + +#define LIS2DUX12_EMB_FUNC_SRC 0x2AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t stepcounter_bit_set : 1; + uint8_t step_overflow : 1; + uint8_t step_count_delta_ia : 1; + uint8_t step_detected : 1; + uint8_t not_used1 : 1; + uint8_t pedo_rst_step : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pedo_rst_step : 1; + uint8_t not_used1 : 1; + uint8_t step_detected : 1; + uint8_t step_count_delta_ia : 1; + uint8_t step_overflow : 1; + uint8_t stepcounter_bit_set : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_emb_func_src_t; + +#define LIS2DUX12_EMB_FUNC_INIT_A 0x2CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t step_det_init : 1; + uint8_t tilt_init : 1; + uint8_t sig_mot_init : 1; + uint8_t not_used1 : 1; + uint8_t mlc_before_fsm_init : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_before_fsm_init : 1; + uint8_t not_used1 : 1; + uint8_t sig_mot_init : 1; + uint8_t tilt_init : 1; + uint8_t step_det_init : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_emb_func_init_a_t; + +#define LIS2DUX12_EMB_FUNC_INIT_B 0x2DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_init : 1; + uint8_t not_used0 : 3; + uint8_t mlc_init : 1; + uint8_t not_used1 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 3; + uint8_t mlc_init : 1; + uint8_t not_used0 : 3; + uint8_t fsm_init : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_emb_func_init_b_t; + +#define LIS2DUX12_MLC1_SRC 0x34U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc1_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc1_src : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_mlc1_src_t; + +#define LIS2DUX12_MLC2_SRC 0x35U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc2_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc2_src : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_mlc2_src_t; + +#define LIS2DUX12_MLC3_SRC 0x36U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc3_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc3_src : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_mlc3_src_t; + +#define LIS2DUX12_MLC4_SRC 0x37U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc4_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc4_src : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_mlc4_src_t; + +#define LIS2DUX12_FSM_ODR 0x39U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t fsm_odr : 3; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t fsm_odr : 3; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fsm_odr_t; + +#define LIS2DUX12_MLC_ODR 0x3AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 4; + uint8_t mlc_odr : 3; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t mlc_odr : 3; + uint8_t not_used0 : 4; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_mlc_odr_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page pg0_emb_adv + * @{ + * + */ +#define LIS2DUX12_EMB_ADV_PG_0 0x000U + +#define LIS2DUX12_FSM_LC_TIMEOUT_L 0x54U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc_timeout : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc_timeout : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fsm_lc_timeout_l_t; + +#define LIS2DUX12_FSM_LC_TIMEOUT_H 0x55U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc_timeout : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc_timeout : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fsm_lc_timeout_h_t; + +#define LIS2DUX12_FSM_PROGRAMS 0x56U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_n_prog : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_n_prog : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fsm_programs_t; + +#define LIS2DUX12_FSM_START_ADD_L 0x58U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_start : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_start : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fsm_start_add_l_t; + +#define LIS2DUX12_FSM_START_ADD_H 0x59U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_start : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_start : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_fsm_start_add_h_t; + +#define LIS2DUX12_PEDO_CMD_REG 0x5DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t fp_rejection_en : 1; + uint8_t carry_count_en : 1; + uint8_t not_used1 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 4; + uint8_t carry_count_en : 1; + uint8_t fp_rejection_en : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_pedo_cmd_reg_t; + +#define LIS2DUX12_PEDO_DEB_STEPS_CONF 0x5EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t deb_step : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t deb_step : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_pedo_deb_steps_conf_t; + +#define LIS2DUX12_PEDO_SC_DELTAT_L 0xAAU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t pd_sc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pd_sc : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_pedo_sc_deltat_l_t; + +#define LIS2DUX12_PEDO_SC_DELTAT_H 0xABU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t pd_sc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pd_sc : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_pedo_sc_deltat_h_t; + +#define LIS2DUX12_T_SENSITIVITY_L 0xB6U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t t_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t t_s : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_t_sensitivity_l_t; + +#define LIS2DUX12_T_SENSITIVITY_H 0xB7U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t t_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t t_s : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_t_sensitivity_h_t; + +/** + * @} + * + */ + +typedef union +{ + lis2dux12_pin_ctrl_t pin_ctrl; + lis2dux12_wake_up_dur_ext_t wake_up_dur_ext; + lis2dux12_who_am_i_t who_am_i; + lis2dux12_ctrl1_t ctrl1; + lis2dux12_ctrl2_t ctrl2; + lis2dux12_ctrl3_t ctrl3; + lis2dux12_ctrl4_t ctrl4; + lis2dux12_ctrl5_t ctrl5; + lis2dux12_fifo_ctrl_t fifo_ctrl; + lis2dux12_fifo_wtm_t fifo_wtm; + lis2dux12_interrupt_cfg_t interrupt_cfg; + lis2dux12_sixd_t sixd; + lis2dux12_wake_up_ths_t wake_up_ths; + lis2dux12_wake_up_dur_t wake_up_dur; + lis2dux12_free_fall_t free_fall; + lis2dux12_md1_cfg_t md1_cfg; + lis2dux12_md2_cfg_t md2_cfg; + lis2dux12_wake_up_src_t wake_up_src; + lis2dux12_tap_src_t tap_src; + lis2dux12_sixd_src_t sixd_src; + lis2dux12_all_int_src_t all_int_src; + lis2dux12_status_register_t status; + lis2dux12_fifo_status1_t fifo_status1; + lis2dux12_fifo_status2_t fifo_status2; + lis2dux12_out_x_l_t out_x_l; + lis2dux12_out_x_h_t out_x_h; + lis2dux12_out_y_l_t out_y_l; + lis2dux12_out_y_h_t out_y_h; + lis2dux12_out_z_l_t out_z_l; + lis2dux12_out_z_h_t out_z_h; + lis2dux12_out_t_l_t out_t_l; + lis2dux12_out_t_h_t out_t_h; + lis2dux12_self_test_t self_test; + lis2dux12_i3c_if_ctrl_t i3c_if_ctrl; + lis2dux12_emb_func_status_mainpage_t emb_func_status_mainpage; + lis2dux12_fsm_status_mainpage_t fsm_status_mainpage; + lis2dux12_mlc_status_mainpage_t mlc_status_mainpage; + lis2dux12_sleep_t sleep; + lis2dux12_if_wake_up_t if_wake_up; + lis2dux12_func_cfg_access_t func_cfg_access; + lis2dux12_fifo_data_out_tag_t fifo_data_out_tag; + lis2dux12_fifo_data_out_x_l_t fifo_data_out_x_l; + lis2dux12_fifo_data_out_x_h_t fifo_data_out_x_h; + lis2dux12_fifo_data_out_y_l_t fifo_data_out_y_l; + lis2dux12_fifo_data_out_y_h_t fifo_data_out_y_h; + lis2dux12_fifo_data_out_z_l_t fifo_data_out_z_l; + lis2dux12_fifo_data_out_z_h_t fifo_data_out_z_h; + lis2dux12_fifo_batch_dec_t fifo_batch_dec; + lis2dux12_tap_cfg0_t tap_cfg0; + lis2dux12_tap_cfg1_t tap_cfg1; + lis2dux12_tap_cfg2_t tap_cfg2; + lis2dux12_tap_cfg3_t tap_cfg3; + lis2dux12_tap_cfg4_t tap_cfg4; + lis2dux12_tap_cfg5_t tap_cfg5; + lis2dux12_tap_cfg6_t tap_cfg6; + lis2dux12_timestamp0_t timestamp0; + lis2dux12_timestamp1_t timestamp1; + lis2dux12_timestamp2_t timestamp2; + lis2dux12_timestamp3_t timestamp3; + lis2dux12_page_sel_t page_sel; + lis2dux12_emb_func_en_a_t emb_func_en_a; + lis2dux12_emb_func_en_b_t emb_func_en_b; + lis2dux12_emb_func_exec_status_t emb_func_exec_status; + lis2dux12_page_address_t page_address; + lis2dux12_page_value_t page_value; + lis2dux12_emb_func_int1_t emb_func_int1; + lis2dux12_fsm_int1_t fsm_int1; + lis2dux12_mlc_int1_t mlc_int1; + lis2dux12_emb_func_int2_t emb_func_int2; + lis2dux12_fsm_int2_t fsm_int2; + lis2dux12_mlc_int2_t mlc_int2; + lis2dux12_emb_func_status_t emb_func_status; + lis2dux12_fsm_status_t fsm_status; + lis2dux12_mlc_status_t mlc_status; + lis2dux12_page_rw_t page_rw; + lis2dux12_emb_func_fifo_en_t emb_func_fifo_en; + lis2dux12_fsm_enable_t fsm_enable; + lis2dux12_fsm_long_counter_l_t fsm_long_counter_l; + lis2dux12_fsm_long_counter_h_t fsm_long_counter_h; + lis2dux12_int_ack_mask_t int_ack_mask; + lis2dux12_fsm_outs1_t fsm_outs1; + lis2dux12_fsm_outs2_t fsm_outs2; + lis2dux12_fsm_outs3_t fsm_outs3; + lis2dux12_fsm_outs4_t fsm_outs4; + lis2dux12_fsm_outs5_t fsm_outs5; + lis2dux12_fsm_outs6_t fsm_outs6; + lis2dux12_fsm_outs7_t fsm_outs7; + lis2dux12_fsm_outs8_t fsm_outs8; + lis2dux12_step_counter_l_t step_counter_l; + lis2dux12_step_counter_h_t step_counter_h; + lis2dux12_emb_func_src_t emb_func_src; + lis2dux12_emb_func_init_a_t emb_func_init_a; + lis2dux12_emb_func_init_b_t emb_func_init_b; + lis2dux12_mlc1_src_t mlc1_src; + lis2dux12_mlc2_src_t mlc2_src; + lis2dux12_mlc3_src_t mlc3_src; + lis2dux12_mlc4_src_t mlc4_src; + lis2dux12_fsm_odr_t fsm_odr; + lis2dux12_mlc_odr_t mlc_odr; + lis2dux12_fsm_lc_timeout_l_t fsm_lc_timeout_l; + lis2dux12_fsm_lc_timeout_h_t fsm_lc_timeout_h; + lis2dux12_fsm_programs_t fsm_programs; + lis2dux12_fsm_start_add_l_t fsm_start_add_l; + lis2dux12_fsm_start_add_h_t fsm_start_add_h; + lis2dux12_pedo_cmd_reg_t pedo_cmd_reg; + lis2dux12_pedo_deb_steps_conf_t pedo_deb_steps_conf; + lis2dux12_pedo_sc_deltat_l_t pedo_sc_deltat_l; + lis2dux12_pedo_sc_deltat_h_t pedo_sc_deltat_h; + lis2dux12_t_sensitivity_l_t t_sensitivity_l; + lis2dux12_t_sensitivity_h_t t_sensitivity_h; + bitwise_t bitwise; + uint8_t byte; +} lis2dux12_reg_t; + +/** + * @} + * + */ + +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + +int32_t lis2dux12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); +int32_t lis2dux12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); + +float_t lis2dux12_from_fs2g_to_mg(int16_t lsb); +float_t lis2dux12_from_fs4g_to_mg(int16_t lsb); +float_t lis2dux12_from_fs8g_to_mg(int16_t lsb); +float_t lis2dux12_from_fs16g_to_mg(int16_t lsb); +float_t lis2dux12_from_lsb_to_celsius(int16_t lsb); + +int32_t lis2dux12_device_id_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { + LIS2DUX12_SENSOR_ONLY_ON = 0x00, /* Initialize the driver for sensor usage */ + LIS2DUX12_BOOT = 0x01, /* Restore calib. param. (it takes 10ms) */ + LIS2DUX12_RESET = 0x02, /* Reset configuration registers */ + LIS2DUX12_SENSOR_EMB_FUNC_ON = 0x03, /* Initialize the driver for sensor and/or + embedded functions usage (it takes 10ms) */ +} lis2dux12_init_t; +int32_t lis2dux12_init_set(stmdev_ctx_t *ctx, lis2dux12_init_t val); + +typedef struct { + uint8_t sw_reset : 1; /* Restoring configuration registers */ + uint8_t boot : 1; /* Restoring calibration parameters */ + uint8_t drdy : 1; /* Accelerometer data ready */ + uint8_t power_down : 1; /* Monitors power-down. */ +} lis2dux12_status_t; +int32_t lis2dux12_status_get(stmdev_ctx_t *ctx, lis2dux12_status_t *val); + +typedef struct { + uint8_t is_step_det : 1; /* Step detected */ + uint8_t is_tilt : 1; /* Tilt detected */ + uint8_t is_sigmot : 1; /* Significant motion detected */ +} lis2dux12_embedded_status_t; +int32_t lis2dux12_embedded_status_get(stmdev_ctx_t *ctx, lis2dux12_embedded_status_t *val); + +typedef enum +{ + LIS2DUX12_DRDY_LATCHED = 0x0, + LIS2DUX12_DRDY_PULSED = 0x1, +} lis2dux12_data_ready_mode_t; +int32_t lis2dux12_data_ready_mode_set(stmdev_ctx_t *ctx, lis2dux12_data_ready_mode_t val); +int32_t lis2dux12_data_ready_mode_get(stmdev_ctx_t *ctx, lis2dux12_data_ready_mode_t *val); + +typedef struct { + enum { + LIS2DUX12_OFF = 0x00, /* in power down */ + LIS2DUX12_1Hz5_ULP = 0x01, /* @1Hz6 (low power) */ + LIS2DUX12_3Hz_ULP = 0x02, /* @3Hz (ultra low) */ + LIS2DUX12_25Hz_ULP = 0x03, /* @25Hz (ultra low) */ + LIS2DUX12_6Hz = 0x04, /* @6Hz (low power) */ + LIS2DUX12_12Hz5 = 0x05, /* @12Hz5 (low power) */ + LIS2DUX12_25Hz = 0x06, /* @25Hz (low power ) */ + LIS2DUX12_50Hz = 0x07, /* @50Hz (low power) */ + LIS2DUX12_100Hz = 0x08, /* @100Hz (low power) */ + LIS2DUX12_200Hz = 0x09, /* @200Hz (low power) */ + LIS2DUX12_400Hz = 0x0A, /* @400Hz (low power) */ + LIS2DUX12_800Hz = 0x0B, /* @800Hz (low power) */ + LIS2DUX12_TRIG_PIN = 0x0E, /* Single-shot high latency by INT2 */ + LIS2DUX12_TRIG_SW = 0x0F, /* Single-shot high latency by IF */ + LIS2DUX12_6Hz_HP = 0x14, /* @6Hz (high performance) */ + LIS2DUX12_12Hz5_HP = 0x15, /* @12Hz5 (high performance) */ + LIS2DUX12_25Hz_HP = 0x16, /* @25Hz (high performance ) */ + LIS2DUX12_50Hz_HP = 0x17, /* @50Hz (high performance) */ + LIS2DUX12_100Hz_HP = 0x18, /* @100Hz (high performance) */ + LIS2DUX12_200Hz_HP = 0x19, /* @200Hz (high performance) */ + LIS2DUX12_400Hz_HP = 0x1A, /* @400Hz (high performance) */ + LIS2DUX12_800Hz_HP = 0x1B, /* @800Hz (high performance) */ + } odr; + enum { + LIS2DUX12_2g = 0, + LIS2DUX12_4g = 1, + LIS2DUX12_8g = 2, + LIS2DUX12_16g = 3, + } fs; + enum { + LIS2DUX12_ODR_div_2 = 0, + LIS2DUX12_ODR_div_4 = 1, + LIS2DUX12_ODR_div_8 = 2, + LIS2DUX12_ODR_div_16 = 3, + } bw; +} lis2dux12_md_t; +int32_t lis2dux12_mode_set(stmdev_ctx_t *ctx, lis2dux12_md_t *val); +int32_t lis2dux12_mode_get(stmdev_ctx_t *ctx, lis2dux12_md_t *val); + +int32_t lis2dux12_trigger_sw(stmdev_ctx_t *ctx, lis2dux12_md_t *md); + +typedef struct +{ + uint8_t drdy : 1; + uint8_t timestamp : 1; + uint8_t free_fall : 1; + uint8_t wake_up : 1; + uint8_t wake_up_z : 1; + uint8_t wake_up_y : 1; + uint8_t wake_up_x : 1; + uint8_t single_tap : 1; + uint8_t double_tap : 1; + uint8_t triple_tap : 1; + uint8_t six_d : 1; + uint8_t six_d_xl : 1; + uint8_t six_d_xh : 1; + uint8_t six_d_yl : 1; + uint8_t six_d_yh : 1; + uint8_t six_d_zl : 1; + uint8_t six_d_zh : 1; + uint8_t sleep_change : 1; + uint8_t sleep_state : 1; + uint8_t tilt : 1; + uint8_t fifo_bdr : 1; + uint8_t fifo_full : 1; + uint8_t fifo_ovr : 1; + uint8_t fifo_th : 1; +} lis2dux12_all_sources_t; +int32_t lis2dux12_all_sources_get(stmdev_ctx_t *ctx, lis2dux12_all_sources_t *val); + +typedef struct { + float_t mg[3]; + int16_t raw[3]; +} lis2dux12_xl_data_t; +int32_t lis2dux12_xl_data_get(stmdev_ctx_t *ctx, lis2dux12_md_t *md, + lis2dux12_xl_data_t *data); + +typedef struct { + struct { + float_t deg_c; + int16_t raw; + }heat; +} lis2dux12_outt_data_t; +int32_t lis2dux12_outt_data_get(stmdev_ctx_t *ctx, lis2dux12_md_t *md, + lis2dux12_outt_data_t *data); + +typedef enum +{ + LIS2DUX12_XL_ST_DISABLE = 0x0, + LIS2DUX12_XL_ST_POSITIVE = 0x1, + LIS2DUX12_XL_ST_NEGATIVE = 0x2, +} lis2dux12_xl_self_test_t; +int32_t lis2dux12_self_test_sign_set(stmdev_ctx_t *ctx, lis2dux12_xl_self_test_t val); +int32_t lis2dux12_self_test_start(stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dux12_self_test_stop(stmdev_ctx_t *ctx); + +int32_t lis2dux12_enter_deep_power_down(stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dux12_exit_deep_power_down(stmdev_ctx_t *ctx); + +typedef struct { + enum { + LIS2DUX12_I3C_BUS_AVAIL_TIME_20US = 0x0, + LIS2DUX12_I3C_BUS_AVAIL_TIME_50US = 0x1, + LIS2DUX12_I3C_BUS_AVAIL_TIME_1MS = 0x2, + LIS2DUX12_I3C_BUS_AVAIL_TIME_25MS = 0x3, + } bus_act_sel; + uint8_t asf_on : 1; + uint8_t drstdaa_en : 1; +} lis2dux12_i3c_cfg_t; +int32_t lis2dux12_i3c_configure_set(stmdev_ctx_t *ctx, lis2dux12_i3c_cfg_t *val); +int32_t lis2dux12_i3c_configure_get(stmdev_ctx_t *ctx, lis2dux12_i3c_cfg_t *val); + +typedef enum +{ + LIS2DUX12_MAIN_MEM_BANK = 0x0, + LIS2DUX12_EMBED_FUNC_MEM_BANK = 0x1, +} lis2dux12_mem_bank_t; +int32_t lis2dux12_mem_bank_set(stmdev_ctx_t *ctx, lis2dux12_mem_bank_t val); +int32_t lis2dux12_mem_bank_get(stmdev_ctx_t *ctx, lis2dux12_mem_bank_t *val); + +int32_t lis2dux12_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); +int32_t lis2dux12_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); + +typedef struct { + uint8_t sdo_pull_up : 1; /* 1 = pull up enable */ + uint8_t sda_pull_up : 1; /* 1 = pull up enable */ + uint8_t cs_pull_up : 1; /* 1 = pull up enable */ + uint8_t int1_int2_push_pull : 1; /* 1 = push-pull / 0 = open-drain*/ + uint8_t int1_pull_down : 1; /* 1 = pull-down always disabled (0=auto) */ + uint8_t int2_pull_down : 1; /* 1 = pull-down always disabled (0=auto) */ +} lis2dux12_pin_conf_t; +int32_t lis2dux12_pin_conf_set(stmdev_ctx_t *ctx, lis2dux12_pin_conf_t *val); +int32_t lis2dux12_pin_conf_get(stmdev_ctx_t *ctx, lis2dux12_pin_conf_t *val); + +typedef enum +{ + LIS2DUX12_ACTIVE_HIGH = 0x0, + LIS2DUX12_ACTIVE_LOW = 0x1, +} lis2dux12_int_pin_polarity_t; +int32_t lis2dux12_int_pin_polarity_set(stmdev_ctx_t *ctx, lis2dux12_int_pin_polarity_t val); +int32_t lis2dux12_int_pin_polarity_get(stmdev_ctx_t *ctx, lis2dux12_int_pin_polarity_t *val); + +typedef enum +{ + LIS2DUX12_SPI_4_WIRE = 0x0, /* SPI 4 wires */ + LIS2DUX12_SPI_3_WIRE = 0x1, /* SPI 3 wires */ +} lis2dux12_spi_mode; +int32_t lis2dux12_spi_mode_set(stmdev_ctx_t *ctx, lis2dux12_spi_mode val); +int32_t lis2dux12_spi_mode_get(stmdev_ctx_t *ctx, lis2dux12_spi_mode *val); + +typedef struct { + uint8_t int_on_res : 1; /* Interrupt on RES pin */ + uint8_t drdy : 1; /* Accelerometer data ready */ + uint8_t boot : 1; /* Restoring calibration parameters */ + uint8_t fifo_th : 1; /* FIFO threshold reached */ + uint8_t fifo_ovr : 1; /* FIFO overrun */ + uint8_t fifo_full : 1; /* FIFO full */ + uint8_t free_fall : 1; /* free fall event */ + uint8_t six_d : 1; /* orientation change (6D/4D detection) */ + uint8_t tap : 1; /* all tap event */ + uint8_t wake_up : 1; /* wake up event */ + uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ + uint8_t emb_function : 1; /* Embedded Function */ + uint8_t timestamp : 1; /* Timestamp */ +} lis2dux12_pin_int_route_t; +int32_t lis2dux12_pin_int1_route_set(stmdev_ctx_t *ctx, + lis2dux12_pin_int_route_t *val); +int32_t lis2dux12_pin_int1_route_get(stmdev_ctx_t *ctx, + lis2dux12_pin_int_route_t *val); +int32_t lis2dux12_pin_int2_route_set(stmdev_ctx_t *ctx, + lis2dux12_pin_int_route_t *val); +int32_t lis2dux12_pin_int2_route_get(stmdev_ctx_t *ctx, + lis2dux12_pin_int_route_t *val); + +typedef struct { + uint8_t step_det : 1; /* route step detection event on INT pad */ + uint8_t tilt : 1; /* route tilt event on INT pad */ + uint8_t sig_mot : 1; /* route significant motion event on INT pad */ + uint8_t fsm_lc : 1; /* route FSM long counter event on INT pad */ +} lis2dux12_emb_pin_int_route_t; +int32_t lis2dux12_emb_pin_int1_route_set(stmdev_ctx_t *ctx, + lis2dux12_emb_pin_int_route_t *val); +int32_t lis2dux12_emb_pin_int1_route_get(stmdev_ctx_t *ctx, + lis2dux12_emb_pin_int_route_t *val); +int32_t lis2dux12_emb_pin_int2_route_set(stmdev_ctx_t *ctx, + lis2dux12_emb_pin_int_route_t *val); +int32_t lis2dux12_emb_pin_int2_route_get(stmdev_ctx_t *ctx, + lis2dux12_emb_pin_int_route_t *val); + +typedef struct { + enum int_cfg + { + LIS2DUX12_INT_DISABLED = 0x0, + LIS2DUX12_INT_LEVEL = 0x1, + LIS2DUX12_INT_LATCHED = 0x2, + } int_cfg; + uint8_t sleep_status_on_int : 1; /* route sleep_status on interrupt */ + uint8_t dis_rst_lir_all_int : 1; /* disable LIR reset when reading ALL_INT_SRC */ +} lis2dux12_int_config_t; +int32_t lis2dux12_int_config_set(stmdev_ctx_t *ctx, lis2dux12_int_config_t *val); +int32_t lis2dux12_int_config_get(stmdev_ctx_t *ctx, lis2dux12_int_config_t *val); + +typedef enum +{ + LIS2DUX12_EMBEDDED_INT_LEVEL = 0x0, + LIS2DUX12_EMBEDDED_INT_LATCHED = 0x1, +} lis2dux12_embedded_int_config_t; +int32_t lis2dux12_embedded_int_config_set(stmdev_ctx_t *ctx, lis2dux12_embedded_int_config_t val); +int32_t lis2dux12_embedded_int_config_get(stmdev_ctx_t *ctx, lis2dux12_embedded_int_config_t *val); + +typedef struct { + enum operation + { + LIS2DUX12_BYPASS_MODE = 0x0, + LIS2DUX12_FIFO_MODE = 0x1, + LIS2DUX12_STREAM_TO_FIFO_MODE = 0x3, + LIS2DUX12_BYPASS_TO_STREAM_MODE = 0x4, + LIS2DUX12_STREAM_MODE = 0x6, + LIS2DUX12_BYPASS_TO_FIFO_MODE = 0x7, + LIS2DUX12_FIFO_OFF = 0x8, + } operation; + enum store { + LIS2DUX12_FIFO_1X = 0, + LIS2DUX12_FIFO_2X = 1, + } store; + uint8_t xl_only : 1; /* when set to 1, only XL samples (16-bit) are stored in FIFO */ + uint8_t watermark : 7; /* (0 disable) max 127 @16bit, even and max 256 @8bit.*/ + uint8_t cfg_change_in_fifo : 1; + struct { + enum dec_ts + { + LIS2DUX12_DEC_TS_OFF = 0x0, + LIS2DUX12_DEC_TS_1 = 0x1, + LIS2DUX12_DEC_TS_8 = 0x2, + LIS2DUX12_DEC_TS_32 = 0x3, + } dec_ts; /* decimation for timestamp batching*/ + enum bdr_xl + { + LIS2DUX12_BDR_XL_ODR = 0x0, + LIS2DUX12_BDR_XL_ODR_DIV_2 = 0x1, + LIS2DUX12_BDR_XL_ODR_DIV_4 = 0x2, + LIS2DUX12_BDR_XL_ODR_DIV_8 = 0x3, + LIS2DUX12_BDR_XL_ODR_DIV_16 = 0x4, + LIS2DUX12_BDR_XL_ODR_DIV_32 = 0x5, + LIS2DUX12_BDR_XL_ODR_DIV_64 = 0x6, + LIS2DUX12_BDR_XL_ODR_OFF = 0x7, + } bdr_xl; /* accelerometer batch data rate*/ + } batch; +} lis2dux12_fifo_mode_t; +int32_t lis2dux12_fifo_mode_set(stmdev_ctx_t *ctx, lis2dux12_fifo_mode_t val); +int32_t lis2dux12_fifo_mode_get(stmdev_ctx_t *ctx, lis2dux12_fifo_mode_t *val); + +int32_t lis2dux12_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lis2dux12_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LIS2DUX12_FIFO_EMPTY = 0x0, + LIS2DUX12_XL_TEMP_TAG = 0x2, + LIS2DUX12_XL_ONLY_2X_TAG = 0x3, + LIS2DUX12_TIMESTAMP_TAG = 0x4, + LIS2DUX12_STEP_COUNTER_TAG = 0x12, + LIS2DUX12_MLC_RESULT_TAG = 0x1A, + LIS2DUX12_MLC_FILTER_TAG = 0x1B, + LIS2DUX12_MLC_FEATURE = 0x1C, + LIS2DUX12_FSM_RESULT_TAG = 0x1D, +} lis2dux12_fifo_sensor_tag_t; +int32_t lis2dux12_fifo_sensor_tag_get(stmdev_ctx_t *ctx, + lis2dux12_fifo_sensor_tag_t *val); + +int32_t lis2dux12_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff); + +typedef struct { + uint8_t tag; + struct { + float_t mg[3]; + int16_t raw[3]; + }xl[2]; + struct heat { + float_t deg_c; + int16_t raw; + } heat; + struct pedo { + uint32_t steps; + uint32_t timestamp; + } pedo; + struct cfg_chg { + uint8_t cfg_change : 1; /* 1 if ODR/BDR configuration is changed */ + uint8_t odr : 4; /* ODR */ + uint8_t bw : 2; /* BW */ + uint8_t lp_hp : 1; /* Power (LP == 0/HP == 1) */ + uint8_t fs : 2; /* FS */ + uint8_t dec_ts : 2; /* Timestamp decimator value */ + uint8_t odr_xl_batch : 1; /* Accelerometer ODR is batched */ + uint32_t timestamp; + } cfg_chg; +} lis2dux12_fifo_data_t; +int32_t lis2dux12_fifo_data_get(stmdev_ctx_t *ctx, lis2dux12_md_t *md, + lis2dux12_fifo_mode_t *fmd, + lis2dux12_fifo_data_t *data); + + +typedef struct +{ + uint8_t false_step_rej : 1; + uint8_t step_counter_enable : 1; + uint8_t step_counter_in_fifo : 1; +} lis2dux12_stpcnt_mode_t; +int32_t lis2dux12_stpcnt_mode_set(stmdev_ctx_t *ctx, lis2dux12_stpcnt_mode_t val); +int32_t lis2dux12_stpcnt_mode_get(stmdev_ctx_t *ctx, lis2dux12_stpcnt_mode_t *val); + +int32_t lis2dux12_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val); + +int32_t lis2dux12_stpcnt_rst_step_set(stmdev_ctx_t *ctx); + +int32_t lis2dux12_stpcnt_debounce_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dux12_stpcnt_debounce_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lis2dux12_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val); +int32_t lis2dux12_stpcnt_period_get(stmdev_ctx_t *ctx, uint16_t *val); + +int32_t lis2dux12_tilt_mode_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dux12_tilt_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dux12_sigmot_mode_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dux12_sigmot_mode_get(stmdev_ctx_t *ctx, uint8_t *val); + + +int32_t lis2dux12_ff_duration_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dux12_ff_duration_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LIS2DUX12_156_mg = 0x0, + LIS2DUX12_219_mg = 0x1, + LIS2DUX12_250_mg = 0x2, + LIS2DUX12_312_mg = 0x3, + LIS2DUX12_344_mg = 0x4, + LIS2DUX12_406_mg = 0x5, + LIS2DUX12_469_mg = 0x6, + LIS2DUX12_500_mg = 0x7, +} lis2dux12_ff_thresholds_t; +int32_t lis2dux12_ff_thresholds_set(stmdev_ctx_t *ctx, lis2dux12_ff_thresholds_t val); +int32_t lis2dux12_ff_thresholds_get(stmdev_ctx_t *ctx, lis2dux12_ff_thresholds_t *val); + +typedef struct { + enum threshold + { + LIS2DUX12_DEG_80 = 0x0, + LIS2DUX12_DEG_70 = 0x1, + LIS2DUX12_DEG_60 = 0x2, + LIS2DUX12_DEG_50 = 0x3, + } threshold; + enum mode + { + LIS2DUX12_6D = 0x0, + LIS2DUX12_4D = 0x1, + } mode; +} lis2dux12_sixd_config_t; + +int32_t lis2dux12_sixd_config_set(stmdev_ctx_t *ctx, lis2dux12_sixd_config_t val); +int32_t lis2dux12_sixd_config_get(stmdev_ctx_t *ctx, lis2dux12_sixd_config_t *val); + +typedef struct { + enum wake_dur + { + LIS2DUX12_0_ODR = 0x000, /* 0 ODR time */ + LIS2DUX12_1_ODR = 0x001, /* 1 ODR time */ + LIS2DUX12_2_ODR = 0x002, /* 2 ODR time */ + LIS2DUX12_3_ODR = 0x100, /* 3 ODR time */ + LIS2DUX12_7_ODR = 0x101, /* 7 ODR time */ + LIS2DUX12_11_ODR = 0x102, /* 11 ODR time */ + LIS2DUX12_15_ODR = 0x103, /* 15 ODR time */ + } wake_dur; + uint8_t sleep_dur : 4; /* 1 LSB == 512 ODR time */ + uint8_t wake_ths : 7; /* wakeup threshold */ + uint8_t wake_ths_weight : 1; /* 0: 1LSB = FS_XL/2^6, 1: 1LSB = FS_XL/2^8 */ + enum wake_enable + { + LIS2DUX12_SLEEP_OFF = 0, + LIS2DUX12_SLEEP_ON = 1, + } wake_enable; + enum inact_odr + { + LIS2DUX12_ODR_NO_CHANGE = 0, /* no odr change during inactivity state */ + LIS2DUX12_ODR_1_6_HZ = 1, /* set odr to 1.6Hz during inactivity state */ + LIS2DUX12_ODR_3_HZ = 1, /* set odr to 3Hz during inactivity state */ + LIS2DUX12_ODR_25_HZ = 1, /* set odr to 25Hz during inactivity state */ + } inact_odr; +} lis2dux12_wakeup_config_t; + +int32_t lis2dux12_wakeup_config_set(stmdev_ctx_t *ctx, lis2dux12_wakeup_config_t val); +int32_t lis2dux12_wakeup_config_get(stmdev_ctx_t *ctx, lis2dux12_wakeup_config_t *val); + +typedef struct { + enum axis + { + LIS2DUX12_TAP_NONE = 0x0, /* No axis */ + LIS2DUX12_TAP_ON_X = 0x1, /* Detect tap on X axis */ + LIS2DUX12_TAP_ON_Y = 0x2, /* Detect tap on Y axis */ + LIS2DUX12_TAP_ON_Z = 0x3, /* Detect tap on Z axis */ + } axis; + uint8_t inverted_peak_time : 5; /* 1 LSB == 1 sample */ + uint8_t pre_still_ths : 4; /* 1 LSB == 62.5 mg */ + uint8_t post_still_ths : 4; /* 1 LSB == 62.5 mg */ + uint8_t post_still_time : 6; /* samples num during stationary condition */ + uint8_t shock_wait_time : 6; /* samples num during shock condition */ + uint8_t latency : 4; /* samples max num between taps */ + uint8_t wait_end_latency : 1; /* wait end of latency time to generate tap events */ + uint8_t peak_ths : 6; /* 1 LSB == 62.5 mg */ + uint8_t rebound : 5; /* samples num during rebound condition */ + uint8_t pre_still_start : 4; /* pre still start */ + uint8_t pre_still_n : 4; /* pre still n */ + uint8_t single_tap_on : 1; /* enable single tap */ + uint8_t double_tap_on : 1; /* enable double tap */ + uint8_t triple_tap_on : 1; /* enable triple tap */ +} lis2dux12_tap_config_t; + +int32_t lis2dux12_tap_config_set(stmdev_ctx_t *ctx, lis2dux12_tap_config_t val); +int32_t lis2dux12_tap_config_get(stmdev_ctx_t *ctx, lis2dux12_tap_config_t *val); + +int32_t lis2dux12_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dux12_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lis2dux12_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); + +int32_t lis2dux12_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t lis2dux12_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dux12_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + lis2dux12_fsm_enable_t fsm_enable; +} lis2dux12_emb_fsm_enable_t; +int32_t lis2dux12_fsm_enable_set(stmdev_ctx_t *ctx, + lis2dux12_emb_fsm_enable_t *val); +int32_t lis2dux12_fsm_enable_get(stmdev_ctx_t *ctx, + lis2dux12_emb_fsm_enable_t *val); + +int32_t lis2dux12_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val); +int32_t lis2dux12_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val); + +int32_t lis2dux12_fsm_status_get(stmdev_ctx_t *ctx, + lis2dux12_fsm_status_mainpage_t *val); +int32_t lis2dux12_fsm_out_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LIS2DUX12_ODR_FSM_12Hz5 = 0, + LIS2DUX12_ODR_FSM_25Hz = 1, + LIS2DUX12_ODR_FSM_50Hz = 2, + LIS2DUX12_ODR_FSM_100Hz = 3, + LIS2DUX12_ODR_FSM_200Hz = 4, + LIS2DUX12_ODR_FSM_400Hz = 5, + LIS2DUX12_ODR_FSM_800Hz = 6, +} lis2dux12_fsm_val_odr_t; +int32_t lis2dux12_fsm_data_rate_set(stmdev_ctx_t *ctx, + lis2dux12_fsm_val_odr_t val); +int32_t lis2dux12_fsm_data_rate_get(stmdev_ctx_t *ctx, + lis2dux12_fsm_val_odr_t *val); + +int32_t lis2dux12_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dux12_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lis2dux12_long_cnt_int_value_set(stmdev_ctx_t *ctx, + uint16_t val); +int32_t lis2dux12_long_cnt_int_value_get(stmdev_ctx_t *ctx, + uint16_t *val); + +int32_t lis2dux12_fsm_number_of_programs_set(stmdev_ctx_t *ctx, + uint8_t *buff); +int32_t lis2dux12_fsm_number_of_programs_get(stmdev_ctx_t *ctx, + uint8_t *buff); + +int32_t lis2dux12_fsm_start_address_set(stmdev_ctx_t *ctx, + uint16_t val); +int32_t lis2dux12_fsm_start_address_get(stmdev_ctx_t *ctx, + uint16_t *val); + +typedef enum +{ + LIS2DUX12_MLC_OFF = 0, + LIS2DUX12_MLC_ON = 1, + LIS2DUX12_MLC_ON_BEFORE_FSM = 2, +} lis2dux12_mlc_mode_t; +int32_t lis2dux12_mlc_set(stmdev_ctx_t *ctx, lis2dux12_mlc_mode_t val); +int32_t lis2dux12_mlc_get(stmdev_ctx_t *ctx, lis2dux12_mlc_mode_t *val); + +int32_t lis2dux12_mlc_status_get(stmdev_ctx_t *ctx, + lis2dux12_mlc_status_mainpage_t *val); + +int32_t lis2dux12_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff); + +typedef enum +{ + LIS2DUX12_ODR_PRGS_12Hz5 = 0, + LIS2DUX12_ODR_PRGS_25Hz = 1, + LIS2DUX12_ODR_PRGS_50Hz = 2, + LIS2DUX12_ODR_PRGS_100Hz = 3, + LIS2DUX12_ODR_PRGS_200Hz = 4, +} lis2dux12_mlc_odr_val_t; +int32_t lis2dux12_mlc_data_rate_set(stmdev_ctx_t *ctx, + lis2dux12_mlc_odr_val_t val); +int32_t lis2dux12_mlc_data_rate_get(stmdev_ctx_t *ctx, + lis2dux12_mlc_odr_val_t *val); + +#ifdef __cplusplus +} +#endif + +#endif /* LIS2DUX12_REGS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis2duxs12_STdC/driver/lis2duxs12_reg.c b/sensor/stmemsc/lis2duxs12_STdC/driver/lis2duxs12_reg.c new file mode 100644 index 0000000000000000000000000000000000000000..3c4fb0aa116aca247d930096216ade72762cdb33 --- /dev/null +++ b/sensor/stmemsc/lis2duxs12_STdC/driver/lis2duxs12_reg.c @@ -0,0 +1,3688 @@ +/* + ****************************************************************************** + * @file lis2duxs12_reg.c + * @author Sensors Software Solution Team + * @brief LIS2DUXS12 driver file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2022 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "lis2duxs12_reg.h" + +/** + * @defgroup LIS2DUXS12 + * @brief This file provides a set of functions needed to drive the + * lis2duxs12 sensor. + * @{ + * + */ + +/** + * @defgroup LIS2DUXS12_Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +/** + * @brief Read generic device register + * + * @param ctx read / write interface definitions(ptr) + * @param reg register to read + * @param data pointer to buffer that store the data read(ptr) + * @param len number of consecutive register to read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak lis2duxs12_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data, + uint16_t len) +{ + int32_t ret; + ret = ctx->read_reg(ctx->handle, reg, data, len); + return ret; +} + +/** + * @brief Write generic device register + * + * @param ctx read / write interface definitions(ptr) + * @param reg register to write + * @param data pointer to data to write in register reg(ptr) + * @param len number of consecutive register to write + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak lis2duxs12_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data, + uint16_t len) +{ + int32_t ret; + ret = ctx->write_reg(ctx->handle, reg, data, len); + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LIS2DUXS12_Sensitivity + * @brief These functions convert raw-data into engineering units. + * @{ + * + */ + +float_t lis2duxs12_from_fs2g_to_mg(int16_t lsb) +{ + return (float_t)lsb * 0.061f; +} + +float_t lis2duxs12_from_fs4g_to_mg(int16_t lsb) +{ + return (float_t)lsb * 0.122f; +} + +float_t lis2duxs12_from_fs8g_to_mg(int16_t lsb) +{ + return (float_t)lsb * 0.244f; +} + +float_t lis2duxs12_from_fs16g_to_mg(int16_t lsb) +{ + return (float_t)lsb * 0.488f; +} + +float_t lis2duxs12_from_lsb_to_celsius(int16_t lsb) +{ + return ((float_t)lsb / 355.5f) + 25.0f; +} + +/** + * @} + * + */ + +/** + * @defgroup Common + * @brief Common + * @{/ + * + */ +/** + * @brief Device ID.[get] + * + * @param ctx read / write interface definitions + * @param val Device ID. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_device_id_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_WHO_AM_I, val, 1); + + return ret; +} + +/** + * @brief Configures the bus operating mode.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val configures the bus operating mode.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_init_set(stmdev_ctx_t *ctx, lis2duxs12_init_t val) +{ + lis2duxs12_ctrl1_t ctrl1; + lis2duxs12_ctrl4_t ctrl4; + int32_t ret = 0; + + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t*)&ctrl1, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t*)&ctrl4, 1); + switch (val) { + case LIS2DUXS12_BOOT: + ctrl4.boot = PROPERTY_ENABLE; + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t*)&ctrl4, 1); + break; + case LIS2DUXS12_RESET: + + ctrl1.sw_reset = PROPERTY_ENABLE; + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t*)&ctrl1, 1); + break; + case LIS2DUXS12_SENSOR_ONLY_ON: + /* no embedded funcs are used */ + ctrl4.emb_func_en = PROPERTY_DISABLE; + ctrl4.bdu = PROPERTY_ENABLE; + ctrl1.if_add_inc = PROPERTY_ENABLE; + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t*)&ctrl4, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t*)&ctrl1, 1); + break; + case LIS2DUXS12_SENSOR_EMB_FUNC_ON: + /* complete configuration is used */ + ctrl4.emb_func_en = PROPERTY_ENABLE; + ctrl4.bdu = PROPERTY_ENABLE; + ctrl1.if_add_inc = PROPERTY_ENABLE; + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t*)&ctrl4, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t*)&ctrl1, 1); + break; + default: + ctrl1.sw_reset = PROPERTY_ENABLE; + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t*)&ctrl1, 1); + break; + } + return ret; +} + +/** + * @brief Get the status of the device.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val the status of the device.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_status_get(stmdev_ctx_t *ctx, lis2duxs12_status_t *val) +{ + lis2duxs12_status_register_t status_register; + lis2duxs12_ctrl1_t ctrl1; + lis2duxs12_ctrl4_t ctrl4; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_STATUS, + (uint8_t*)&status_register, 1); + if (ret == 0) { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t*)&ctrl1, 1); + } + if (ret == 0) { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t*)&ctrl4, 1); + } + + val->sw_reset = ctrl1.sw_reset; + val->boot = ctrl4.boot; + val->drdy = status_register.drdy; + + return ret; +} + +/** + * @brief Get the status of the embedded funcs.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val the status of the embedded funcs.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_embedded_status_get(stmdev_ctx_t *ctx, lis2duxs12_embedded_status_t *val) +{ + lis2duxs12_emb_func_status_t status; + int32_t ret; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_STATUS, (uint8_t*)&status, 1); + ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + val->is_step_det = status.is_step_det; + val->is_tilt = status.is_tilt; + val->is_sigmot = status.is_sigmot; + + return ret; +} + +/** + * @brief Enables pulsed data-ready mode (~75 us).[set] + * + * @param ctx read / write interface definitions + * @param val DRDY_LATCHED, DRDY_PULSED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_data_ready_mode_set(stmdev_ctx_t *ctx, lis2duxs12_data_ready_mode_t val) +{ + lis2duxs12_ctrl1_t ctrl1; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1); + + if (ret == 0) + { + ctrl1.drdy_pulsed = ((uint8_t)val & 0x1U); + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1); + } + + return ret; +} + +/** + * @brief Enables pulsed data-ready mode (~75 us).[get] + * + * @param ctx read / write interface definitions + * @param val DRDY_LATCHED, DRDY_PULSED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_data_ready_mode_get(stmdev_ctx_t *ctx, lis2duxs12_data_ready_mode_t *val) +{ + lis2duxs12_ctrl1_t ctrl1; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1); + + switch ((ctrl1.drdy_pulsed)) + { + case LIS2DUXS12_DRDY_LATCHED: + *val = LIS2DUXS12_DRDY_LATCHED; + break; + + case LIS2DUXS12_DRDY_PULSED: + *val = LIS2DUXS12_DRDY_PULSED; + break; + + default: + *val = LIS2DUXS12_DRDY_LATCHED; + break; + } + return ret; +} + +/** + * @brief Sensor mode.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val set the sensor FS and ODR.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_mode_set(stmdev_ctx_t *ctx, lis2duxs12_md_t *val) +{ + lis2duxs12_ctrl3_t ctrl3; + lis2duxs12_ctrl5_t ctrl5; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL5, (uint8_t*)&ctrl5, 1); + + ctrl5.odr = (uint8_t)val->odr & 0xFU; + ctrl5.fs = (uint8_t)val->fs; + ctrl5.bw = (uint8_t)val->bw; + + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t*)&ctrl3, 1); + + ctrl3.hp_en = (((uint8_t)val->odr & 0x10U) != 0U) ? 1U : 0U; + + if (ret == 0) { + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL5, (uint8_t*)&ctrl5, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t*)&ctrl3, 1); + } + + return ret; +} + +/** + * @brief Sensor mode.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val get the sensor FS and ODR.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_mode_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *val) +{ + lis2duxs12_ctrl3_t ctrl3; + lis2duxs12_ctrl5_t ctrl5; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL5, (uint8_t*)&ctrl5, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t*)&ctrl3, 1); + + switch (ctrl5.odr) { + case LIS2DUXS12_OFF: + val->odr = LIS2DUXS12_OFF; + break; + case LIS2DUXS12_1Hz5_ULP: + val->odr = LIS2DUXS12_1Hz5_ULP; + break; + case LIS2DUXS12_3Hz_ULP: + val->odr = LIS2DUXS12_3Hz_ULP; + break; + case LIS2DUXS12_25Hz_ULP: + val->odr = LIS2DUXS12_25Hz_ULP; + break; + case LIS2DUXS12_6Hz: + val->odr = LIS2DUXS12_6Hz; + break; + case LIS2DUXS12_12Hz5: + val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_12Hz5_HP : LIS2DUXS12_12Hz5; + break; + case LIS2DUXS12_25Hz: + val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_25Hz_HP : LIS2DUXS12_25Hz; + break; + case LIS2DUXS12_50Hz: + val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_50Hz_HP : LIS2DUXS12_50Hz; + break; + case LIS2DUXS12_100Hz: + val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_100Hz_HP : LIS2DUXS12_100Hz; + break; + case LIS2DUXS12_200Hz: + val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_200Hz_HP : LIS2DUXS12_200Hz; + break; + case LIS2DUXS12_400Hz: + val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_400Hz_HP : LIS2DUXS12_400Hz; + break; + case LIS2DUXS12_800Hz: + val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_800Hz_HP : LIS2DUXS12_800Hz; + break; + case LIS2DUXS12_TRIG_PIN: + val->odr = LIS2DUXS12_TRIG_PIN; + break; + case LIS2DUXS12_TRIG_SW: + val->odr = LIS2DUXS12_TRIG_SW; + break; + default: + val->odr = LIS2DUXS12_OFF; + break; + } + + switch (ctrl5.fs) { + case LIS2DUXS12_2g: + val->fs = LIS2DUXS12_2g; + break; + case LIS2DUXS12_4g: + val->fs = LIS2DUXS12_4g; + break; + case LIS2DUXS12_8g: + val->fs = LIS2DUXS12_8g; + break; + case LIS2DUXS12_16g: + val->fs = LIS2DUXS12_16g; + break; + default: + val->fs = LIS2DUXS12_2g; + break; + } + + switch (ctrl5.bw) { + case LIS2DUXS12_ODR_div_2: + val->bw = LIS2DUXS12_ODR_div_2; + break; + case LIS2DUXS12_ODR_div_4: + val->bw = LIS2DUXS12_ODR_div_4; + break; + case LIS2DUXS12_ODR_div_8: + val->bw = LIS2DUXS12_ODR_div_8; + break; + case LIS2DUXS12_ODR_div_16: + val->bw = LIS2DUXS12_ODR_div_16; + break; + default: + val->bw = LIS2DUXS12_ODR_div_2; + break; + } + + return ret; +} + +/** + * @brief Enter deep power down[set] + * + * @param ctx read / write interface definitions + * @param val Enter deep power down + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_enter_deep_power_down(stmdev_ctx_t *ctx, uint8_t val) +{ + lis2duxs12_sleep_t sleep; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SLEEP, (uint8_t *)&sleep, 1); + + if (ret == 0) + { + sleep.deep_pd = val; + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_SLEEP, (uint8_t *)&sleep, 1); + } + + return ret; +} + +/** + * @brief Enter soft power down in SPI case[set] + * + * @param ctx read / write interface definitions + * @param val Enter soft power down in SPI case + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_exit_deep_power_down(stmdev_ctx_t *ctx) +{ + lis2duxs12_if_wake_up_t if_wake_up = {0}; + int32_t ret; + + if_wake_up.soft_pd = PROPERTY_ENABLE; + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_IF_WAKE_UP, (uint8_t *)&if_wake_up, 1); + + return ret; +} + +/** + * @brief Software trigger for One-Shot.[get] + * + * @param ctx communication interface handler.(ptr) + * @param md the sensor conversion parameters.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_trigger_sw(stmdev_ctx_t *ctx, lis2duxs12_md_t *md) +{ + lis2duxs12_ctrl4_t ctrl4; + int32_t ret = 0; + + if ( md->odr == LIS2DUXS12_TRIG_SW ) { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t*)&ctrl4, 1); + ctrl4.soc = PROPERTY_ENABLE; + if (ret == 0) { + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t*)&ctrl4, 1); + } + } + return ret; +} + +int32_t lis2duxs12_all_sources_get(stmdev_ctx_t *ctx, lis2duxs12_all_sources_t *val) +{ + lis2duxs12_status_register_t status; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_STATUS, (uint8_t*)&status, 1); + val->drdy = status.drdy; + + if (ret == 0 && status.int_global == 0x1U) + { + lis2duxs12_wake_up_src_t wu_src; + lis2duxs12_tap_src_t tap_src; + lis2duxs12_sixd_src_t sixd_src; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SIXD_SRC, (uint8_t*)&sixd_src, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_SRC, (uint8_t*)&wu_src, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_SRC, (uint8_t*)&tap_src, 1); + + val->six_d = sixd_src.d6d_ia; + val->six_d_xl = sixd_src.xl; + val->six_d_xh = sixd_src.xh; + val->six_d_yl = sixd_src.yl; + val->six_d_yh = sixd_src.yh; + val->six_d_zl = sixd_src.zl; + val->six_d_zh = sixd_src.zh; + + val->wake_up = wu_src.wu_ia; + val->wake_up_z = wu_src.z_wu; + val->wake_up_y = wu_src.y_wu; + val->wake_up_x = wu_src.x_wu; + val->free_fall = wu_src.ff_ia; + val->sleep_change = wu_src.sleep_change_ia; + val->sleep_state = wu_src.sleep_state; + + val->single_tap = tap_src.single_tap_ia; + val->double_tap = tap_src.double_tap_ia; + val->triple_tap = tap_src.triple_tap_ia; + } + + return ret; +} + +/** + * @brief Accelerometer data.[get] + * + * @param ctx communication interface handler.(ptr) + * @param md the sensor conversion parameters.(ptr) + * @param data data retrived from the sensor.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_xl_data_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *md, + lis2duxs12_xl_data_t *data) +{ + uint8_t buff[6]; + int32_t ret; + uint8_t i; + uint8_t j; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_OUT_X_L, buff, 6); + + /* acceleration conversion */ + j = 0U; + for (i = 0U; i < 3U; i++) { + data->raw[i] = (int16_t)buff[j+1U]; + data->raw[i] = (data->raw[i] * 256) + (int16_t) buff[j]; + j+=2U; + switch ( md->fs ) { + case LIS2DUXS12_2g: + data->mg[i] =lis2duxs12_from_fs2g_to_mg(data->raw[i]); + break; + case LIS2DUXS12_4g: + data->mg[i] =lis2duxs12_from_fs4g_to_mg(data->raw[i]); + break; + case LIS2DUXS12_8g: + data->mg[i] =lis2duxs12_from_fs8g_to_mg(data->raw[i]); + break; + case LIS2DUXS12_16g: + data->mg[i] =lis2duxs12_from_fs16g_to_mg(data->raw[i]); + break; + default: + data->mg[i] = 0.0f; + break; + } + } + + return ret; +} + +/** + * @brief OUTT data.[get] + * + * @param ctx communication interface handler.(ptr) + * @param md the sensor conversion parameters.(ptr) + * @param data data retrived from the sensor.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_outt_data_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *md, + lis2duxs12_outt_data_t *data) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_OUT_T_AH_QVAR_L, buff, 2); + + data->heat.raw = (int16_t)buff[1U]; + data->heat.raw = (data->heat.raw * 256) + (int16_t) buff[0]; + /* temperature conversion */ + data->heat.deg_c = lis2duxs12_from_lsb_to_celsius(data->heat.raw); + + return ret; +} + +/** + * @brief AH_QVAR data.[get] + * + * @param ctx communication interface handler.(ptr) + * @param md the sensor conversion parameters.(ptr) + * @param data data retrived from the sensor.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_ah_qvar_data_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *md, + lis2duxs12_ah_qvar_data_t *data) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_OUT_T_AH_QVAR_L, buff, 2); + + data->ah_qvar = (int16_t)buff[1U]; + data->ah_qvar = (data->ah_qvar * 256) + (int16_t) buff[0]; + + return ret; +} + +/** + * @brief Configures the self test.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val self test mode.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_self_test_sign_set(stmdev_ctx_t *ctx, lis2duxs12_xl_self_test_t val) +{ + lis2duxs12_ctrl3_t ctrl3; + lis2duxs12_wake_up_dur_t wkup_dur; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t*)&ctrl3, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t*)&wkup_dur, 1); + + switch (val) { + case LIS2DUXS12_XL_ST_POSITIVE: + ctrl3.st_sign_x = 1; + ctrl3.st_sign_y = 1; + wkup_dur.st_sign_z = 0; + break; + + case LIS2DUXS12_XL_ST_NEGATIVE: + ctrl3.st_sign_x = 0; + ctrl3.st_sign_y = 0; + wkup_dur.st_sign_z = 1; + break; + + case LIS2DUXS12_XL_ST_DISABLE: + default: + ret = -1; + break; + } + + + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t*)&ctrl3, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t*)&wkup_dur, 1); + + return ret; +} + +/** + * @brief Configures the self test.[start] + * + * @param ctx communication interface handler.(ptr) + * @param val valid values 2 (1st step) or 1 (2nd step) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_self_test_start(stmdev_ctx_t *ctx, uint8_t val) +{ + lis2duxs12_self_test_t self_test; + int32_t ret; + + if (val != 1U && val != 2U) { + return -1; + } + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t*)&self_test, 1); + if (ret == 0) { + self_test.st = (uint8_t) val; + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t*)&self_test, 1); + } + return ret; +} + +/** + * @brief Configures the self test.[stop] + * + * @param ctx communication interface handler.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_self_test_stop(stmdev_ctx_t *ctx) +{ + lis2duxs12_self_test_t self_test; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t*)&self_test, 1); + if (ret == 0) { + self_test.st = 0; + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t*)&self_test, 1); + } + return ret; +} + +/** + * @brief Configures I3C bus.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val configuration params + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_i3c_configure_set(stmdev_ctx_t *ctx, lis2duxs12_i3c_cfg_t *val) +{ + lis2duxs12_i3c_if_ctrl_t i3c_cfg; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_I3C_IF_CTRL, (uint8_t *)&i3c_cfg, 1); + + if (ret == 0) + { + i3c_cfg.bus_act_sel = (uint8_t)val->bus_act_sel; + i3c_cfg.dis_drstdaa = val->drstdaa_en; + i3c_cfg.asf_on = val->asf_on; + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_I3C_IF_CTRL, (uint8_t *)&i3c_cfg, 1); + } + + return ret; +} + +/** + * @brief Configures I3C bus.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val configuration params + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */int32_t lis2duxs12_i3c_configure_get(stmdev_ctx_t *ctx, lis2duxs12_i3c_cfg_t *val) +{ + lis2duxs12_i3c_if_ctrl_t i3c_cfg; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_I3C_IF_CTRL, (uint8_t *)&i3c_cfg, 1); + + val->drstdaa_en = i3c_cfg.dis_drstdaa; + val->asf_on = i3c_cfg.asf_on; + + switch (val->bus_act_sel) { + case LIS2DUXS12_I3C_BUS_AVAIL_TIME_20US: + val->bus_act_sel = LIS2DUXS12_I3C_BUS_AVAIL_TIME_20US; + break; + + case LIS2DUXS12_I3C_BUS_AVAIL_TIME_50US: + val->bus_act_sel = LIS2DUXS12_I3C_BUS_AVAIL_TIME_50US; + break; + + case LIS2DUXS12_I3C_BUS_AVAIL_TIME_1MS: + val->bus_act_sel = LIS2DUXS12_I3C_BUS_AVAIL_TIME_1MS; + break; + + case LIS2DUXS12_I3C_BUS_AVAIL_TIME_25MS: + default: + val->bus_act_sel = LIS2DUXS12_I3C_BUS_AVAIL_TIME_25MS; + break; + } + + return ret; +} + +/** + * @brief Change memory bank.[set] + * + * @param ctx read / write interface definitions + * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, SENSOR_HUB_MEM_BANK, STRED_MEM_BANK, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_mem_bank_set(stmdev_ctx_t *ctx, lis2duxs12_mem_bank_t val) +{ + lis2duxs12_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + if (ret == 0) + { + func_cfg_access.emb_func_reg_access = ((uint8_t)val & 0x1U); + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Change memory bank.[get] + * + * @param ctx read / write interface definitions + * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, SENSOR_HUB_MEM_BANK, STRED_MEM_BANK, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_mem_bank_get(stmdev_ctx_t *ctx, lis2duxs12_mem_bank_t *val) +{ + lis2duxs12_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + switch ((func_cfg_access.emb_func_reg_access)) + { + case LIS2DUXS12_MAIN_MEM_BANK: + *val = LIS2DUXS12_MAIN_MEM_BANK; + break; + + case LIS2DUXS12_EMBED_FUNC_MEM_BANK: + *val = LIS2DUXS12_EMBED_FUNC_MEM_BANK; + break; + + default: + *val = LIS2DUXS12_MAIN_MEM_BANK; + break; + } + return ret; +} + +/** + * @brief Write buffer in a page. + * + * @param ctx read / write interface definitions + * @param address Address of page register to be written (page number in 8-bit + * msb, register address in 8-bit lsb). + * @param buf Pointer to data buffer. + * @param len Buffer len. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len) +{ + lis2duxs12_page_address_t page_address; + lis2duxs12_page_sel_t page_sel; + lis2duxs12_page_rw_t page_rw; + uint8_t msb; + uint8_t lsb; + int32_t ret; + uint8_t i ; + + msb = ((uint8_t)(address >> 8) & 0x0FU); + lsb = (uint8_t)address & 0xFFU; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_ENABLE; + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1); + + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1); + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1); + + page_address.page_addr = lsb; + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_ADDRESS, (uint8_t *)&page_address, 1); + + for (i = 0; ((i < len) && (ret == 0)); i++) + { + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_VALUE, &buf[i], 1); + lsb++; + + /* Check if page wrap */ + if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) + { + msb++; + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1); + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1); + } + } + + page_sel.page_sel = 0; + page_sel.not_used0 = 1;// Default value + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1); + + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1); + } + + ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Read buffer in a page. + * + * @param ctx read / write interface definitions + * @param address Address of page register to be read (page number in 8-bit + * msb, register address in 8-bit lsb). + * @param buf Pointer to data buffer. + * @param len Buffer len. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len) +{ + lis2duxs12_page_address_t page_address; + lis2duxs12_page_sel_t page_sel; + lis2duxs12_page_rw_t page_rw; + uint8_t msb; + uint8_t lsb; + int32_t ret; + uint8_t i ; + + msb = ((uint8_t)(address >> 8) & 0x0FU); + lsb = (uint8_t)address & 0xFFU; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_ENABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1); + + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1); + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1); + + page_address.page_addr = lsb; + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_ADDRESS, (uint8_t *)&page_address, 1); + + for (i = 0; ((i < len) && (ret == 0)); i++) + { + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_VALUE, &buf[i], 1); + lsb++; + + /* Check if page wrap */ + if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) + { + msb++; + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1); + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1); + } + } + + page_sel.page_sel = 0; + page_sel.not_used0 = 1;// Default value + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1); + + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1); + } + + ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Interrupt PINs + * @brief Interrupt PINs + * @{/ + * + */ + +/** + * @brief Electrical pin configuration.[set] + * + * @param ctx read / write interface definitions + * @param val the electrical settings for the configurable pins.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_pin_conf_set(stmdev_ctx_t *ctx, lis2duxs12_pin_conf_t *val) +{ + lis2duxs12_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + + if (ret == 0) + { + pin_ctrl.cs_pu_dis = ~val->cs_pull_up; + pin_ctrl.pd_dis_int1 = ~val->int1_pull_down; + pin_ctrl.pd_dis_int2 = ~val->int2_pull_down; + pin_ctrl.sda_pu_en = val->sda_pull_up; + pin_ctrl.sdo_pu_en = val->sdo_pull_up; + pin_ctrl.pp_od = ~val->int1_int2_push_pull; + + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + + return ret; +} + +/** + * @brief Electrical pin configuration.[get] + * + * @param ctx read / write interface definitions + * @param val the electrical settings for the configurable pins.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_pin_conf_get(stmdev_ctx_t *ctx, lis2duxs12_pin_conf_t *val) +{ + lis2duxs12_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + + val->cs_pull_up = ~pin_ctrl.cs_pu_dis; + val->int1_pull_down = ~pin_ctrl.pd_dis_int1; + val->int2_pull_down = ~pin_ctrl.pd_dis_int2; + val->sda_pull_up = pin_ctrl.sda_pu_en; + val->sdo_pull_up = pin_ctrl.sdo_pu_en; + val->int1_int2_push_pull = ~pin_ctrl.pp_od; + + return ret; +} + +/** + * @brief Interrupt activation level.[set] + * + * @param ctx read / write interface definitions + * @param val ACTIVE_HIGH, ACTIVE_LOW, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_int_pin_polarity_set(stmdev_ctx_t *ctx, lis2duxs12_int_pin_polarity_t val) +{ + lis2duxs12_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + + if (ret == 0) + { + pin_ctrl.h_lactive = (uint8_t)val; + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + + return ret; +} + +/** + * @brief Interrupt activation level.[get] + * + * @param ctx read / write interface definitions + * @param val ACTIVE_HIGH, ACTIVE_LOW, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_int_pin_polarity_get(stmdev_ctx_t *ctx, lis2duxs12_int_pin_polarity_t *val) +{ + lis2duxs12_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + + switch ((pin_ctrl.h_lactive)) + { + case LIS2DUXS12_ACTIVE_HIGH: + *val = LIS2DUXS12_ACTIVE_HIGH; + break; + + case LIS2DUXS12_ACTIVE_LOW: + *val = LIS2DUXS12_ACTIVE_LOW; + break; + + default: + *val = LIS2DUXS12_ACTIVE_HIGH; + break; + } + return ret; +} + +/** + * @brief SPI mode.[set] + * + * @param ctx read / write interface definitions + * @param val SPI_4_WIRE, SPI_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_spi_mode_set(stmdev_ctx_t *ctx, lis2duxs12_spi_mode val) +{ + lis2duxs12_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + + if (ret == 0) + { + pin_ctrl.sim = (uint8_t)val; + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + + return ret; +} + +/** + * @brief SPI mode.[get] + * + * @param ctx read / write interface definitions + * @param val SPI_4_WIRE, SPI_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_spi_mode_get(stmdev_ctx_t *ctx, lis2duxs12_spi_mode *val) +{ + lis2duxs12_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + + switch ((pin_ctrl.h_lactive)) + { + case LIS2DUXS12_SPI_4_WIRE: + *val = LIS2DUXS12_SPI_4_WIRE; + break; + + case LIS2DUXS12_SPI_3_WIRE: + *val = LIS2DUXS12_SPI_3_WIRE; + break; + + default: + *val = LIS2DUXS12_SPI_4_WIRE; + break; + } + return ret; +} + +/** + * @brief routes interrupt signals on INT 1 pin.[set] + * + * @param ctx read / write interface definitions + * @param val routes interrupt signals on INT 1 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_pin_int1_route_set(stmdev_ctx_t *ctx, lis2duxs12_pin_int_route_t *val) +{ + lis2duxs12_ctrl1_t ctrl1; + lis2duxs12_ctrl2_t ctrl2; + lis2duxs12_md1_cfg_t md1_cfg; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1); + + if (ret == 0) + { + ctrl1.int1_on_res = val->int_on_res; + + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1); + } + + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL2, (uint8_t *)&ctrl2, 1); + + if (ret == 0) + { + ctrl2.int1_drdy = val->drdy; + ctrl2.int1_fifo_ovr = val->fifo_ovr; + ctrl2.int1_fifo_th = val->fifo_th; + ctrl2.int1_fifo_full = val->fifo_full; + ctrl2.int1_boot = val->boot; + + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL2, (uint8_t *)&ctrl2, 1); + } + } + + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_MD1_CFG, (uint8_t *)&md1_cfg, 1); + + if (ret == 0) + { + md1_cfg.int1_ff = val->free_fall; + md1_cfg.int1_6d = val->six_d; + md1_cfg.int1_tap = val->tap; + md1_cfg.int1_wu = val->wake_up; + md1_cfg.int1_sleep_change = val->sleep_change; + md1_cfg.int1_emb_func = val->emb_function; + md1_cfg.int1_timestamp = val->timestamp; + + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_MD1_CFG, (uint8_t *)&md1_cfg, 1); + } + } + + return ret; +} + +/** + * @brief routes interrupt signals on INT 1 pin.[get] + * + * @param ctx read / write interface definitions + * @param val Get interrupt signals routing on INT 1 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_pin_int1_route_get(stmdev_ctx_t *ctx, lis2duxs12_pin_int_route_t *val) +{ + lis2duxs12_ctrl1_t ctrl1; + lis2duxs12_ctrl2_t ctrl2; + lis2duxs12_md1_cfg_t md1_cfg; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL2, (uint8_t *)&ctrl2, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_MD1_CFG, (uint8_t *)&md1_cfg, 1); + + if (ret == 0) + { + val->int_on_res = ctrl1.int1_on_res; + val->drdy = ctrl2.int1_drdy; + val->fifo_ovr = ctrl2.int1_fifo_ovr; + val->fifo_th = ctrl2.int1_fifo_th; + val->fifo_full = ctrl2.int1_fifo_full; + val->boot = ctrl2.int1_boot; + val->free_fall = md1_cfg.int1_ff; + val->six_d = md1_cfg.int1_6d; + val->tap = md1_cfg.int1_tap; + val->wake_up = md1_cfg.int1_wu; + val->sleep_change = md1_cfg.int1_sleep_change; + val->emb_function = md1_cfg.int1_emb_func; + val->timestamp = md1_cfg.int1_timestamp; + } + + return ret; +} + +/** + * @brief routes embedded func interrupt signals on INT 1 pin.[set] + * + * @param ctx read / write interface definitions + * @param val routes embedded func interrupt signals on INT 1 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_emb_pin_int1_route_set(stmdev_ctx_t *ctx, + lis2duxs12_emb_pin_int_route_t *val) +{ + lis2duxs12_emb_func_int1_t emb_func_int1; + lis2duxs12_md1_cfg_t md1_cfg; + int32_t ret; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + } + + if (ret == 0) + { + emb_func_int1.int1_tilt = val->tilt; + emb_func_int1.int1_sig_mot = val->sig_mot; + emb_func_int1.int1_step_det = val->step_det; + emb_func_int1.int1_fsm_lc = val->fsm_lc; + + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + } + ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_MD1_CFG, (uint8_t *)&md1_cfg, 1); + if (ret == 0) + { + md1_cfg.int1_emb_func = 1; + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_MD1_CFG, (uint8_t *)&md1_cfg, 1); + } + + return ret; +} + +/** + * @brief routes embedded func interrupt signals on INT 1 pin.[get] + * + * @param ctx read / write interface definitions + * @param val routes embedded func interrupt signals on INT 1 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_emb_pin_int1_route_get(stmdev_ctx_t *ctx, + lis2duxs12_emb_pin_int_route_t *val) +{ + lis2duxs12_emb_func_int1_t emb_func_int1; + int32_t ret; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + } + + if (ret == 0) + { + val->tilt = emb_func_int1.int1_tilt; + val->sig_mot = emb_func_int1.int1_sig_mot; + val->step_det = emb_func_int1.int1_step_det; + val->fsm_lc = emb_func_int1.int1_fsm_lc; + } + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief routes interrupt signals on INT 2 pin.[set] + * + * @param ctx read / write interface definitions + * @param val routes interrupt signals on INT 2 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_pin_int2_route_set(stmdev_ctx_t *ctx, lis2duxs12_pin_int_route_t *val) +{ + lis2duxs12_ctrl3_t ctrl3; + lis2duxs12_md2_cfg_t md2_cfg; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL2, (uint8_t *)&ctrl3, 1); + + if (ret == 0) + { + ctrl3.int2_drdy = val->drdy; + ctrl3.int2_fifo_ovr = val->fifo_ovr; + ctrl3.int2_fifo_th = val->fifo_th; + ctrl3.int2_fifo_full = val->fifo_full; + ctrl3.int2_boot = val->boot; + + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t *)&ctrl3, 1); + } + + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_MD2_CFG, (uint8_t *)&md2_cfg, 1); + + if (ret == 0) + { + md2_cfg.int2_ff = val->free_fall; + md2_cfg.int2_6d = val->six_d; + md2_cfg.int2_tap = val->tap; + md2_cfg.int2_wu = val->wake_up; + md2_cfg.int2_sleep_change = val->sleep_change; + md2_cfg.int2_emb_func = val->emb_function; + md2_cfg.int2_timestamp = val->timestamp; + + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_MD2_CFG, (uint8_t *)&md2_cfg, 1); + } + } + + return ret; +} + +/** + * @brief routes interrupt signals on INT 2 pin.[get] + * + * @param ctx read / write interface definitions + * @param val Get interrupt signals routing on INT 2 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_pin_int2_route_get(stmdev_ctx_t *ctx, lis2duxs12_pin_int_route_t *val) +{ + lis2duxs12_ctrl3_t ctrl3; + lis2duxs12_md2_cfg_t md2_cfg; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL2, (uint8_t *)&ctrl3, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_MD1_CFG, (uint8_t *)&md2_cfg, 1); + + if (ret == 0) + { + val->drdy = ctrl3.int2_drdy; + val->fifo_ovr = ctrl3.int2_fifo_ovr; + val->fifo_th = ctrl3.int2_fifo_th; + val->fifo_full = ctrl3.int2_fifo_full; + val->boot = ctrl3.int2_boot; + val->free_fall = md2_cfg.int2_ff; + val->six_d = md2_cfg.int2_6d; + val->tap = md2_cfg.int2_tap; + val->wake_up = md2_cfg.int2_wu; + val->sleep_change = md2_cfg.int2_sleep_change; + val->emb_function = md2_cfg.int2_emb_func; + val->timestamp = md2_cfg.int2_timestamp; + } + + return ret; +} + +/** + * @brief routes embedded func interrupt signals on INT 2 pin.[set] + * + * @param ctx read / write interface definitions + * @param val routes embedded func interrupt signals on INT 2 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_emb_pin_int2_route_set(stmdev_ctx_t *ctx, + lis2duxs12_emb_pin_int_route_t *val) +{ + lis2duxs12_emb_func_int2_t emb_func_int2; + lis2duxs12_md2_cfg_t md2_cfg; + int32_t ret; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + } + + if (ret == 0) + { + emb_func_int2.int2_tilt = val->tilt; + emb_func_int2.int2_sig_mot = val->sig_mot; + emb_func_int2.int2_step_det = val->step_det; + emb_func_int2.int2_fsm_lc = val->fsm_lc; + + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + } + ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_MD2_CFG, (uint8_t *)&md2_cfg, 1); + if (ret == 0) + { + md2_cfg.int2_emb_func = 1; + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_MD2_CFG, (uint8_t *)&md2_cfg, 1); + } + + return ret; +} + +/** + * @brief routes embedded func interrupt signals on INT 2 pin.[get] + * + * @param ctx read / write interface definitions + * @param val routes embedded func interrupt signals on INT 2 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_emb_pin_int2_route_get(stmdev_ctx_t *ctx, + lis2duxs12_emb_pin_int_route_t *val) +{ + lis2duxs12_emb_func_int2_t emb_func_int2; + int32_t ret; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + } + + if (ret == 0) + { + val->tilt = emb_func_int2.int2_tilt; + val->sig_mot = emb_func_int2.int2_sig_mot; + val->step_det = emb_func_int2.int2_step_det; + val->fsm_lc = emb_func_int2.int2_fsm_lc; + } + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Interrupt configuration mode.[set] + * + * @param ctx read / write interface definitions + * @param val INT_DISABLED, INT_LEVEL, INT_LATCHED + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_int_config_set(stmdev_ctx_t *ctx, lis2duxs12_int_config_t *val) +{ + lis2duxs12_interrupt_cfg_t interrupt_cfg; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1); + + if (ret == 0) + { + switch (val->int_cfg) + { + case LIS2DUXS12_INT_DISABLED: + interrupt_cfg.interrupts_enable = 0; + break; + + case LIS2DUXS12_INT_LEVEL: + interrupt_cfg.interrupts_enable = 1; + interrupt_cfg.lir = 0; + break; + + case LIS2DUXS12_INT_LATCHED: + default: + interrupt_cfg.interrupts_enable = 1; + interrupt_cfg.lir = 1; + break; + } + + interrupt_cfg.dis_rst_lir_all_int = val->dis_rst_lir_all_int; + interrupt_cfg.sleep_status_on_int = val->sleep_status_on_int; + + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1); + } + + return ret; +} + +/** + * @brief Interrupt configuration mode.[get] + * + * @param ctx read / write interface definitions + * @param val INT_DISABLED, INT_LEVEL, INT_LATCHED + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_int_config_get(stmdev_ctx_t *ctx, lis2duxs12_int_config_t *val) +{ + lis2duxs12_interrupt_cfg_t interrupt_cfg; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1); + + if (ret == 0) + { + val->dis_rst_lir_all_int = interrupt_cfg.dis_rst_lir_all_int; + val->sleep_status_on_int = interrupt_cfg.sleep_status_on_int; + + if (interrupt_cfg.interrupts_enable == 0U) + { + val->int_cfg = LIS2DUXS12_INT_DISABLED; + } + else if (interrupt_cfg.lir == 0U) + { + val->int_cfg = LIS2DUXS12_INT_LEVEL; + } + else + { + val->int_cfg = LIS2DUXS12_INT_LATCHED; + } + } + + return ret; +} + +/** + * @brief Embedded Interrupt configuration mode.[set] + * + * @param ctx read / write interface definitions + * @param val INT_PULSED, INT_LATCHED + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_embedded_int_config_set(stmdev_ctx_t *ctx, lis2duxs12_embedded_int_config_t val) +{ + lis2duxs12_page_rw_t page_rw; + int32_t ret; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1); + + switch (val) + { + case LIS2DUXS12_EMBEDDED_INT_LEVEL: + page_rw.emb_func_lir = 0; + break; + + case LIS2DUXS12_EMBEDDED_INT_LATCHED: + default: + page_rw.emb_func_lir = 1; + break; + } + + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1); + } + + ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Interrupt configuration mode.[get] + * + * @param ctx read / write interface definitions + * @param val INT_DISABLED, INT_PULSED, INT_LATCHED + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_embedded_int_config_get(stmdev_ctx_t *ctx, lis2duxs12_embedded_int_config_t *val) +{ + lis2duxs12_page_rw_t page_rw; + int32_t ret; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1); + + if (page_rw.emb_func_lir == 0U) { + *val = LIS2DUXS12_EMBEDDED_INT_LEVEL; + } else { + *val = LIS2DUXS12_EMBEDDED_INT_LATCHED; + } + } + + ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup FIFO + * @brief FIFO + * @{/ + * + */ + +/** + * @brief FIFO mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val BYPASS_MODE, FIFO_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_fifo_mode_set(stmdev_ctx_t *ctx, lis2duxs12_fifo_mode_t val) +{ + lis2duxs12_ctrl4_t ctrl4; + lis2duxs12_fifo_ctrl_t fifo_ctrl; + lis2duxs12_fifo_wtm_t fifo_wtm; + lis2duxs12_fifo_batch_dec_t fifo_batch; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); + + if (ret == 0) + { + /* set FIFO mode */ + if (val.operation != LIS2DUXS12_FIFO_OFF) + { + ctrl4.fifo_en = 1; + fifo_ctrl.fifo_mode = ((uint8_t)val.operation & 0x7U); + } + else { + ctrl4.fifo_en = 0; + } + + /* set fifo depth (1X/2X) */ + fifo_ctrl.fifo_depth = (uint8_t)val.store; + + /* Set xl_only_fifo */ + fifo_wtm.xl_only_fifo = val.xl_only; + + /* set batching info */ + if (val.batch.dec_ts != LIS2DUXS12_DEC_TS_OFF) + { + fifo_batch.dec_ts_batch = (uint8_t)val.batch.dec_ts; + fifo_batch.bdr_xl = (uint8_t)val.batch.bdr_xl; + } + + fifo_ctrl.cfg_chg_en = val.cfg_change_in_fifo; + + /* set watermark */ + if (val.watermark > 0U) { + fifo_ctrl.stop_on_fth = 1; + fifo_wtm.fth = val.watermark; + } + + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1); + } + + return ret; +} + +/** + * @brief FIFO mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val BYPASS_MODE, FIFO_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_fifo_mode_get(stmdev_ctx_t *ctx, lis2duxs12_fifo_mode_t *val) +{ + lis2duxs12_ctrl4_t ctrl4; + lis2duxs12_fifo_ctrl_t fifo_ctrl; + lis2duxs12_fifo_wtm_t fifo_wtm; + lis2duxs12_fifo_batch_dec_t fifo_batch; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); + + if (ret == 0) + { + /* get FIFO mode */ + if (ctrl4.fifo_en == 0U) { + val->operation = LIS2DUXS12_FIFO_OFF; + } + else { + val->operation = (enum operation)fifo_ctrl.fifo_mode; + } + val->cfg_change_in_fifo = fifo_ctrl.cfg_chg_en; + + /* get fifo depth (1X/2X) */ + val->store = (enum store)fifo_ctrl.fifo_depth; + + /* Get xl_only_fifo */ + val->xl_only = fifo_wtm.xl_only_fifo; + + /* get batching info */ + val->batch.dec_ts = (enum dec_ts)fifo_batch.dec_ts_batch; + val->batch.bdr_xl = (enum bdr_xl)fifo_batch.bdr_xl; + + /* get watermark */ + val->watermark = fifo_wtm.fth; + } + + return ret; +} + +/** + * @brief Number of unread sensor data (TAG + 6 bytes) stored in FIFO.[get] + * + * @param ctx read / write interface definitions + * @param val Number of unread sensor data (TAG + 6 bytes) stored in FIFO. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_STATUS2, &buff, 1); + + *val = buff; + + return ret; +} + +int32_t lis2duxs12_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lis2duxs12_fifo_status1_t fifo_status1; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_STATUS1, (uint8_t *)&fifo_status1, 1); + + *val = fifo_status1.fifo_wtm_ia; + + return ret; +} + +int32_t lis2duxs12_fifo_sensor_tag_get(stmdev_ctx_t *ctx, lis2duxs12_fifo_sensor_tag_t *val) +{ + lis2duxs12_fifo_data_out_tag_t fifo_tag; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_DATA_OUT_TAG, (uint8_t *)&fifo_tag, 1); + + *val = (lis2duxs12_fifo_sensor_tag_t) fifo_tag.tag_sensor; + + return ret; +} + +int32_t lis2duxs12_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_DATA_OUT_X_L, buff, 6); + + return ret; +} + +int32_t lis2duxs12_fifo_data_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *md, + lis2duxs12_fifo_mode_t *fmd, + lis2duxs12_fifo_data_t *data) +{ + lis2duxs12_fifo_data_out_tag_t fifo_tag; + uint8_t fifo_raw[6]; + int32_t ret, i; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_DATA_OUT_TAG, (uint8_t *)&fifo_tag, 1); + data->tag = fifo_tag.tag_sensor; + + switch (fifo_tag.tag_sensor) { + case LIS2DUXS12_XL_ONLY_2X_TAG: + case LIS2DUXS12_XL_ONLY_2X_TAG_2ND: + /* A FIFO sample consists of 2X 8-bits 3-axis XL at ODR/2 */ + ret = lis2duxs12_fifo_out_raw_get(ctx, fifo_raw); + for (i = 0; i < 3; i++) { + data->xl[0].raw[i] = (int16_t)fifo_raw[i] * 256; + data->xl[1].raw[i] = (int16_t)fifo_raw[3 + i] * 256; + } + break; + case LIS2DUXS12_XL_AND_QVAR: + case LIS2DUXS12_XL_TEMP_TAG: + ret = lis2duxs12_fifo_out_raw_get(ctx, fifo_raw); + if (fmd->xl_only == 0x0U) { + /* A FIFO sample consists of 12-bits 3-axis XL + T at ODR*/ + data->xl[0].raw[0] = (int16_t)fifo_raw[0]; + data->xl[0].raw[0] = (data->xl[0].raw[0] + (int16_t)fifo_raw[1] * 256) * 16; + data->xl[0].raw[1] = (int16_t)fifo_raw[1] / 16; + data->xl[0].raw[1] = (data->xl[0].raw[1] + ((int16_t)fifo_raw[2] * 16)) * 16; + data->xl[0].raw[2] = (int16_t)fifo_raw[3]; + data->xl[0].raw[2] = data->xl[0].raw[2] + ((int16_t)fifo_raw[4] * 256) * 16; + data->heat.raw = (int16_t)fifo_raw[4] / 16; + data->heat.raw = (data->heat.raw + ((int16_t)fifo_raw[5] * 16)) * 16; + if (fifo_tag.tag_sensor == (uint8_t)LIS2DUXS12_XL_TEMP_TAG) { + data->heat.deg_c = lis2duxs12_from_lsb_to_celsius(data->heat.raw); + } else { + data->ah_qvar = data->heat.raw; + } + } else { + /* A FIFO sample consists of 16-bits 3-axis XL at ODR */ + data->xl[0].raw[0] = (int16_t)fifo_raw[0] + (int16_t)fifo_raw[1] * 256; + data->xl[0].raw[1] = (int16_t)fifo_raw[1] + (int16_t)fifo_raw[3] * 256; + data->xl[0].raw[2] = (int16_t)fifo_raw[2] + (int16_t)fifo_raw[5] * 256; + } + break; + case LIS2DUXS12_TIMESTAMP_TAG: + ret = lis2duxs12_fifo_out_raw_get(ctx, fifo_raw); + + data->cfg_chg.cfg_change = fifo_raw[0] >> 7; + data->cfg_chg.odr = (fifo_raw[0] >> 3) & 0xFU; + data->cfg_chg.bw = (fifo_raw[0] >> 1) & 0x3U; + data->cfg_chg.lp_hp = fifo_raw[0] & 0x1U; + data->cfg_chg.qvar_en = fifo_raw[1] >> 7; + data->cfg_chg.fs = (fifo_raw[1] >> 5) & 0x3U; + data->cfg_chg.dec_ts = (fifo_raw[1] >> 3) & 0x3U; + data->cfg_chg.odr_xl_batch = fifo_raw[1] & 0x7U; + + data->cfg_chg.timestamp = fifo_raw[5]; + data->cfg_chg.timestamp = (data->cfg_chg.timestamp * 256U) + fifo_raw[4]; + data->cfg_chg.timestamp = (data->cfg_chg.timestamp * 256U) + fifo_raw[3]; + data->cfg_chg.timestamp = (data->cfg_chg.timestamp * 256U) + fifo_raw[2]; + break; + + case LIS2DUXS12_STEP_COUNTER_TAG: + ret = lis2duxs12_fifo_out_raw_get(ctx, fifo_raw); + + data->pedo.steps = fifo_raw[1]; + data->pedo.steps = (data->pedo.steps * 256U) + fifo_raw[0]; + + data->pedo.timestamp = fifo_raw[5]; + data->pedo.timestamp = (data->pedo.timestamp * 256U) + fifo_raw[4]; + data->pedo.timestamp = (data->pedo.timestamp * 256U) + fifo_raw[3]; + data->pedo.timestamp = (data->pedo.timestamp * 256U) + fifo_raw[2]; + + break; + + case LIS2DUXS12_FIFO_EMPTY: + default: + break; + } + + for (i = 0; i < 3; i++) { + switch ( md->fs ) { + case LIS2DUXS12_2g: + data->xl[0].mg[i] =lis2duxs12_from_fs2g_to_mg(data->xl[0].raw[i]); + data->xl[1].mg[i] =lis2duxs12_from_fs2g_to_mg(data->xl[1].raw[i]); + break; + case LIS2DUXS12_4g: + data->xl[0].mg[i] =lis2duxs12_from_fs4g_to_mg(data->xl[0].raw[i]); + data->xl[1].mg[i] =lis2duxs12_from_fs4g_to_mg(data->xl[1].raw[i]); + break; + case LIS2DUXS12_8g: + data->xl[0].mg[i] =lis2duxs12_from_fs8g_to_mg(data->xl[0].raw[i]); + data->xl[1].mg[i] =lis2duxs12_from_fs8g_to_mg(data->xl[1].raw[i]); + break; + case LIS2DUXS12_16g: + data->xl[0].mg[i] =lis2duxs12_from_fs16g_to_mg(data->xl[0].raw[i]); + data->xl[1].mg[i] =lis2duxs12_from_fs16g_to_mg(data->xl[1].raw[i]); + break; + default: + data->xl[0].mg[i] = 0.0f; + data->xl[1].mg[i] = 0.0f; + break; + } + } + + return ret; +} + +/** + * @brief Enables AH_QVAR chain.[set] + * + * @param ctx read / write interface definitions + * @param val Enables and configures AH_QVAR chain. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_ah_qvar_mode_set(stmdev_ctx_t *ctx, + lis2duxs12_ah_qvar_mode_t val) +{ + lis2duxs12_ah_qvar_cfg_t ah_qvar_cfg; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_AH_QVAR_CFG, (uint8_t *)&ah_qvar_cfg, 1); + if (ret == 0) + { + ah_qvar_cfg.ah_qvar_gain = (uint8_t)val.ah_qvar_gain; + ah_qvar_cfg.ah_qvar_c_zin = (uint8_t)val.ah_qvar_zin; + ah_qvar_cfg.ah_qvar_notch_cutoff = (uint8_t)val.ah_qvar_notch; + ah_qvar_cfg.ah_qvar_notch_en = val.ah_qvar_notch_en; + ah_qvar_cfg.ah_qvar_en = val.ah_qvar_en; + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_AH_QVAR_CFG, (uint8_t *)&ah_qvar_cfg, 1); + } + + return ret; +} + +/** + * @brief Enables AH_QVAR chain.[get] + * + * @param ctx read / write interface definitions + * @param val Enables and configures AH_QVAR chain. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_ah_qvar_mode_get(stmdev_ctx_t *ctx, + lis2duxs12_ah_qvar_mode_t *val) +{ + lis2duxs12_ah_qvar_cfg_t ah_qvar_cfg; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_AH_QVAR_CFG, (uint8_t *)&ah_qvar_cfg, 1); + + switch (ah_qvar_cfg.ah_qvar_gain) + { + case LIS2DUXS12_GAIN_0_5: + val->ah_qvar_gain = LIS2DUXS12_GAIN_0_5; + break; + + case LIS2DUXS12_GAIN_1: + val->ah_qvar_gain = LIS2DUXS12_GAIN_1; + break; + + case LIS2DUXS12_GAIN_2: + val->ah_qvar_gain = LIS2DUXS12_GAIN_2; + break; + + case LIS2DUXS12_GAIN_4: + default: + val->ah_qvar_gain = LIS2DUXS12_GAIN_4; + break; + } + + switch (ah_qvar_cfg.ah_qvar_c_zin) + { + case LIS2DUXS12_520MOhm: + val->ah_qvar_zin = LIS2DUXS12_520MOhm; + break; + + case LIS2DUXS12_175MOhm: + val->ah_qvar_zin = LIS2DUXS12_175MOhm; + break; + + case LIS2DUXS12_310MOhm: + val->ah_qvar_zin = LIS2DUXS12_310MOhm; + break; + + case LIS2DUXS12_75MOhm: + default: + val->ah_qvar_zin = LIS2DUXS12_75MOhm; + break; + } + + switch (ah_qvar_cfg.ah_qvar_notch_cutoff) + { + case LIS2DUXS12_NOTCH_50HZ: + val->ah_qvar_notch = LIS2DUXS12_NOTCH_50HZ; + break; + + case LIS2DUXS12_NOTCH_60HZ: + default: + val->ah_qvar_notch = LIS2DUXS12_NOTCH_60HZ; + break; + } + + val->ah_qvar_notch_en = ah_qvar_cfg.ah_qvar_notch_en; + val->ah_qvar_en = ah_qvar_cfg.ah_qvar_en; + + return ret; +} + +/** + * @defgroup Step Counter (Pedometer) + * @brief Step Counter (Pedometer) + * @{/ + * + */ +/** + * @brief Step counter mode[set] + * + * @param ctx read / write interface definitions + * @param val Step counter mode + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_stpcnt_mode_set(stmdev_ctx_t *ctx, lis2duxs12_stpcnt_mode_t val) +{ + lis2duxs12_emb_func_en_a_t emb_func_en_a; + lis2duxs12_emb_func_en_b_t emb_func_en_b; + lis2duxs12_emb_func_fifo_en_t emb_func_fifo_en; + lis2duxs12_pedo_cmd_reg_t pedo_cmd_reg; + int32_t ret; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_FIFO_EN, (uint8_t *)&emb_func_fifo_en, 1); + + if ((val.false_step_rej == PROPERTY_ENABLE) && ((emb_func_en_a.mlc_before_fsm_en & emb_func_en_b.mlc_en) == PROPERTY_DISABLE)) + { + emb_func_en_a.mlc_before_fsm_en = PROPERTY_ENABLE; + } + + emb_func_fifo_en.step_counter_fifo_en = val.step_counter_in_fifo; + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_FIFO_EN, (uint8_t *)&emb_func_fifo_en, 1); + + emb_func_en_a.pedo_en = val.step_counter_enable; + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + + ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + ret += lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + + if (ret == 0) + { + pedo_cmd_reg.fp_rejection_en = val.false_step_rej; + ret += lis2duxs12_ln_pg_write(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + + return ret; +} + +/** + * @brief Step counter mode[get] + * + * @param ctx read / write interface definitions + * @param val Step counter mode + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_stpcnt_mode_get(stmdev_ctx_t *ctx, lis2duxs12_stpcnt_mode_t *val) +{ + lis2duxs12_emb_func_en_a_t emb_func_en_a; + lis2duxs12_pedo_cmd_reg_t pedo_cmd_reg; + int32_t ret; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + ret += lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + val->false_step_rej = pedo_cmd_reg.fp_rejection_en; + val->step_counter_enable = emb_func_en_a.pedo_en; + + return ret; +} + +/** + * @brief Step counter output, number of detected steps.[get] + * + * @param ctx read / write interface definitions + * @param val Step counter output, number of detected steps. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_STEP_COUNTER_L, &buff[0], 2); + ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief Reset step counter.[set] + * + * @param ctx read / write interface definitions + * @param val Reset step counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_stpcnt_rst_step_set(stmdev_ctx_t *ctx) +{ + lis2duxs12_emb_func_src_t emb_func_src; + int32_t ret; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + emb_func_src.pedo_rst_step = 1; + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } + + ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Pedometer debounce configuration.[set] + * + * @param ctx read / write interface definitions + * @param val Pedometer debounce configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_stpcnt_debounce_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lis2duxs12_pedo_deb_steps_conf_t pedo_deb_steps_conf; + int32_t ret; + + pedo_deb_steps_conf.deb_step = val; + ret = lis2duxs12_ln_pg_write(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); + + return ret; +} + +/** + * @brief Pedometer debounce configuration.[get] + * + * @param ctx read / write interface definitions + * @param val Pedometer debounce configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_stpcnt_debounce_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lis2duxs12_pedo_deb_steps_conf_t pedo_deb_steps_conf; + int32_t ret; + + ret = lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); + *val = pedo_deb_steps_conf.deb_step; + + return ret; +} + +/** + * @brief Time period register for step detection on delta time.[set] + * + * @param ctx read / write interface definitions + * @param val Time period register for step detection on delta time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + + ret = lis2duxs12_ln_pg_write(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_SC_DELTAT_L, (uint8_t *)buff, 2); + + return ret; +} + +/** + * @brief Time period register for step detection on delta time.[get] + * + * @param ctx read / write interface definitions + * @param val Time period register for step detection on delta time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_stpcnt_period_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_SC_DELTAT_L, (uint8_t *)buff, 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Tilt + * @brief Tilt + * @{/ + * + */ +/** + * @brief Tilt calculation.[set] + * + * @param ctx read / write interface definitions + * @param val Tilt calculation. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_tilt_mode_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lis2duxs12_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + emb_func_en_a.tilt_en = val; + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + + ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Tilt calculation.[get] + * + * @param ctx read / write interface definitions + * @param val Tilt calculation. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_tilt_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lis2duxs12_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + *val = emb_func_en_a.tilt_en; + } + + ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Significant motion detection + * @brief Significant motion detection + * @{/ + * + */ +/** + * @brief Enables significant motion detection function.[set] + * + * @param ctx read / write interface definitions + * @param val Enables significant motion detection function. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_sigmot_mode_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lis2duxs12_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + emb_func_en_a.sign_motion_en = val; + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + + ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enables significant motion detection function.[get] + * + * @param ctx read / write interface definitions + * @param val Enables significant motion detection function. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_sigmot_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lis2duxs12_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + *val = emb_func_en_a.sign_motion_en; + } + + ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + + +/** + * @defgroup Free Fall + * @brief Free Fall + * @{/ + * + */ +/** + * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[set] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_ff_duration_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lis2duxs12_wake_up_dur_t wake_up_dur; + lis2duxs12_free_fall_t free_fall; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + + if (ret == 0) + { + wake_up_dur.ff_dur = (val >> 5) & 0x1U; + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + } + + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FREE_FALL, (uint8_t *)&free_fall, 1); + free_fall.ff_dur = val & 0x1FU; + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + return ret; +} + +/** + * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[get] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_ff_duration_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lis2duxs12_wake_up_dur_t wake_up_dur; + lis2duxs12_free_fall_t free_fall; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + *val = (wake_up_dur.ff_dur << 5) | free_fall.ff_dur; + + return ret; +} + +/** + * @brief Free fall threshold setting.[set] + * + * @param ctx read / write interface definitions + * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_ff_thresholds_set(stmdev_ctx_t *ctx, lis2duxs12_ff_thresholds_t val) +{ + lis2duxs12_free_fall_t free_fall; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FREE_FALL, (uint8_t *)&free_fall, 1); + free_fall.ff_ths = ((uint8_t)val & 0x7U); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FREE_FALL, (uint8_t *)&free_fall, 1); + + return ret; +} + +/** + * @brief Free fall threshold setting.[get] + * + * @param ctx read / write interface definitions + * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_ff_thresholds_get(stmdev_ctx_t *ctx, lis2duxs12_ff_thresholds_t *val) +{ + lis2duxs12_free_fall_t free_fall; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FREE_FALL, (uint8_t *)&free_fall, 1); + + switch (free_fall.ff_ths) + { + case LIS2DUXS12_156_mg: + *val = LIS2DUXS12_156_mg; + break; + + case LIS2DUXS12_219_mg: + *val = LIS2DUXS12_219_mg; + break; + + case LIS2DUXS12_250_mg: + *val = LIS2DUXS12_250_mg; + break; + + case LIS2DUXS12_312_mg: + *val = LIS2DUXS12_312_mg; + break; + + case LIS2DUXS12_344_mg: + *val = LIS2DUXS12_344_mg; + break; + + case LIS2DUXS12_406_mg: + *val = LIS2DUXS12_406_mg; + break; + + case LIS2DUXS12_469_mg: + *val = LIS2DUXS12_469_mg; + break; + + case LIS2DUXS12_500_mg: + *val = LIS2DUXS12_500_mg; + break; + + default: + *val = LIS2DUXS12_156_mg; + break; + } + return ret; +} + +/** + * @} + * + */ + + +/** + * @defgroup Orientation 6D (and 4D) + * @brief Orientation 6D (and 4D) + * @{/ + * + */ +/** + * @brief configuration for 4D/6D function.[set] + * + * @param ctx read / write interface definitions + * @param val 4D/6D, DEG_80, DEG_70, DEG_60, DEG_50, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_sixd_config_set(stmdev_ctx_t *ctx, lis2duxs12_sixd_config_t val) +{ + lis2duxs12_sixd_t sixd; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SIXD, (uint8_t *)&sixd, 1); + + if (ret == 0) + { + sixd.d4d_en = ((uint8_t)val.mode); + sixd.d6d_ths = ((uint8_t)val.threshold); + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_SIXD, (uint8_t *)&sixd, 1); + } + + return ret; +} + +/** + * @brief configuration for 4D/6D function.[get] + * + * @param ctx read / write interface definitions + * @param val 4D/6D, DEG_80, DEG_70, DEG_60, DEG_50, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_sixd_config_get(stmdev_ctx_t *ctx, lis2duxs12_sixd_config_t *val) +{ + lis2duxs12_sixd_t sixd; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SIXD, (uint8_t *)&sixd, 1); + + val->mode = (enum mode)sixd.d4d_en; + + switch ((sixd.d6d_ths)) + { + case LIS2DUXS12_DEG_80: + val->threshold = LIS2DUXS12_DEG_80; + break; + + case LIS2DUXS12_DEG_70: + val->threshold = LIS2DUXS12_DEG_70; + break; + + case LIS2DUXS12_DEG_60: + val->threshold = LIS2DUXS12_DEG_60; + break; + + case LIS2DUXS12_DEG_50: + val->threshold = LIS2DUXS12_DEG_50; + break; + + default: + val->threshold = LIS2DUXS12_DEG_80; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup wakeup configuration + * @brief wakeup configuration + * @{/ + * + */ + +/** + * @brief configuration for wakeup function.[set] + * + * @param ctx read / write interface definitions + * @param val threshold, duration, ... + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_wakeup_config_set(stmdev_ctx_t *ctx, lis2duxs12_wakeup_config_t val) +{ + lis2duxs12_wake_up_ths_t wup_ths; + lis2duxs12_wake_up_dur_t wup_dur; + lis2duxs12_wake_up_dur_ext_t wup_dur_ext; + lis2duxs12_interrupt_cfg_t int_cfg; + lis2duxs12_ctrl1_t ctrl1; + lis2duxs12_ctrl4_t ctrl4; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_THS, (uint8_t *)&wup_ths, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t *)&wup_dur, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_DUR_EXT, (uint8_t *)&wup_dur_ext, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1); + + if (ret == 0) + { + wup_dur.wake_dur = (uint8_t)val.wake_dur & 0x3U; + wup_dur_ext.wu_dur_extended = (uint8_t)val.wake_dur >> 2; + wup_dur.sleep_dur = val.sleep_dur; + + int_cfg.wake_ths_w = val.wake_ths_weight; + wup_ths.wk_ths = val.wake_ths; + wup_ths.sleep_on = (uint8_t)val.wake_enable; + ctrl4.inact_odr = (uint8_t)val.inact_odr; + + if (val.wake_enable == LIS2DUXS12_SLEEP_ON) { + ctrl1.wu_x_en = 1; + ctrl1.wu_y_en = 1; + ctrl1.wu_z_en = 1; + } else { + ctrl1.wu_x_en = 0; + ctrl1.wu_y_en = 0; + ctrl1.wu_z_en = 0; + } + + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_WAKE_UP_THS, (uint8_t *)&wup_ths, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t *)&wup_dur, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_WAKE_UP_DUR_EXT, (uint8_t *)&wup_dur_ext, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1); + } + + return ret; +} + +/** + * @brief configuration for wakeup function.[get] + * + * @param ctx read / write interface definitions + * @param val threshold, duration, ... + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_wakeup_config_get(stmdev_ctx_t *ctx, lis2duxs12_wakeup_config_t *val) +{ + lis2duxs12_wake_up_ths_t wup_ths; + lis2duxs12_wake_up_dur_t wup_dur; + lis2duxs12_wake_up_dur_ext_t wup_dur_ext; + lis2duxs12_interrupt_cfg_t int_cfg; + lis2duxs12_ctrl4_t ctrl4; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_THS, (uint8_t *)&wup_ths, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t *)&wup_dur, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_DUR_EXT, (uint8_t *)&wup_dur_ext, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1); + + if (ret == 0) + { + switch(wup_dur.wake_dur) { + case 0x0: + val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ? + LIS2DUXS12_3_ODR : LIS2DUXS12_0_ODR; + break; + + case 0x1: + val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ? + LIS2DUXS12_7_ODR : LIS2DUXS12_1_ODR; + break; + + case 0x2: + val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ? + LIS2DUXS12_11_ODR : LIS2DUXS12_2_ODR; + break; + + case 0x3: + default: + val->wake_dur = LIS2DUXS12_15_ODR; + break; + } + + val->sleep_dur = wup_dur.sleep_dur; + + val->wake_ths_weight = int_cfg.wake_ths_w; + val->wake_ths = wup_ths.wk_ths; + val->wake_enable = (enum wake_enable)wup_ths.sleep_on; + val->inact_odr = (enum inact_odr)ctrl4.inact_odr; + } + + return ret; +} + +/** + * @} + * + */ + +int32_t lis2duxs12_tap_config_set(stmdev_ctx_t *ctx, lis2duxs12_tap_config_t val) +{ + lis2duxs12_tap_cfg0_t tap_cfg0; + lis2duxs12_tap_cfg1_t tap_cfg1; + lis2duxs12_tap_cfg2_t tap_cfg2; + lis2duxs12_tap_cfg3_t tap_cfg3; + lis2duxs12_tap_cfg4_t tap_cfg4; + lis2duxs12_tap_cfg5_t tap_cfg5; + lis2duxs12_tap_cfg6_t tap_cfg6; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG3, (uint8_t *)&tap_cfg3, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG4, (uint8_t *)&tap_cfg4, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG5, (uint8_t *)&tap_cfg5, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG6, (uint8_t *)&tap_cfg6, 1); + + if (ret == 0) + { + tap_cfg0.axis = (uint8_t)val.axis; + tap_cfg0.invert_t = val.inverted_peak_time; + tap_cfg1.pre_still_ths = val.pre_still_ths; + tap_cfg3.post_still_ths = val.post_still_ths; + tap_cfg1.post_still_t = val.post_still_time & 0xFU; + tap_cfg2.post_still_t = val.post_still_time >> 4; + tap_cfg2.wait_t = val.shock_wait_time; + tap_cfg3.latency_t = val.latency; + tap_cfg4.wait_end_latency = val.wait_end_latency; + tap_cfg4.peak_ths = val.peak_ths; + tap_cfg5.rebound_t = val.rebound; + tap_cfg5.single_tap_en = val.single_tap_on; + tap_cfg5.double_tap_en = val.double_tap_on; + tap_cfg5.triple_tap_en = val.triple_tap_on; + tap_cfg6.pre_still_st = val.pre_still_start; + tap_cfg6.pre_still_n = val.pre_still_n; + + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_TAP_CFG3, (uint8_t *)&tap_cfg3, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_TAP_CFG4, (uint8_t *)&tap_cfg4, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_TAP_CFG5, (uint8_t *)&tap_cfg5, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_TAP_CFG6, (uint8_t *)&tap_cfg6, 1); + } + + return ret; +} + +int32_t lis2duxs12_tap_config_get(stmdev_ctx_t *ctx, lis2duxs12_tap_config_t *val) +{ + lis2duxs12_tap_cfg0_t tap_cfg0; + lis2duxs12_tap_cfg1_t tap_cfg1; + lis2duxs12_tap_cfg2_t tap_cfg2; + lis2duxs12_tap_cfg3_t tap_cfg3; + lis2duxs12_tap_cfg4_t tap_cfg4; + lis2duxs12_tap_cfg5_t tap_cfg5; + lis2duxs12_tap_cfg6_t tap_cfg6; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG3, (uint8_t *)&tap_cfg3, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG4, (uint8_t *)&tap_cfg4, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG5, (uint8_t *)&tap_cfg5, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG6, (uint8_t *)&tap_cfg6, 1); + + if (ret == 0) + { + val->axis = (enum axis)tap_cfg0.axis; + val->inverted_peak_time = tap_cfg0.invert_t; + val->pre_still_ths = tap_cfg1.pre_still_ths; + val->post_still_ths = tap_cfg3.post_still_ths; + val->post_still_time = (tap_cfg2.post_still_t << 4) | tap_cfg1.post_still_t; + val->shock_wait_time = tap_cfg2.wait_t; + val->latency = tap_cfg3.latency_t; + val->wait_end_latency = tap_cfg4.wait_end_latency; + val->peak_ths = tap_cfg4.peak_ths; + val->rebound = tap_cfg5.rebound_t; + val->single_tap_on = tap_cfg5.single_tap_en; + val->double_tap_on = tap_cfg5.double_tap_en; + val->triple_tap_on = tap_cfg5.triple_tap_en; + val->pre_still_start = tap_cfg6.pre_still_st; + val->pre_still_n = tap_cfg6.pre_still_n; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup lis2duxs12_Timestamp + * @brief This section groups all the functions that manage the + * timestamp generation. + * @{ + * + */ + +/** + * @brief Enables timestamp counter.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of timestamp_en in reg INTERRUPT_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2duxs12_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lis2duxs12_interrupt_cfg_t int_cfg; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1); + + if (ret == 0) + { + int_cfg.timestamp_en = (uint8_t)val; + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1); + } + + return ret; +} + +/** + * @brief Enables timestamp counter.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of timestamp_en in reg INTERRUPT_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2duxs12_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lis2duxs12_interrupt_cfg_t int_cfg; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1); + *val = int_cfg.timestamp_en; + + return ret; +} + +/** + * @brief Timestamp first data output register (r). + * The value is expressed as a 32-bit word and the bit resolution + * is 10 us.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2duxs12_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) +{ + uint8_t buff[4]; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_TIMESTAMP0, buff, 4); + *val = buff[3]; + *val = (*val * 256U) + buff[2]; + *val = (*val * 256U) + buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LIS2DUXS12_finite_state_machine + * @brief This section groups all the functions that manage the + * state_machine. + * @{ + * + */ + +/** + * @brief Interrupt status bit for FSM long counter timeout interrupt + * event.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of is_fsm_lc in reg EMB_FUNC_STATUS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2duxs12_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, + uint8_t *val) +{ + lis2duxs12_emb_func_status_t emb_func_status; + int32_t ret; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_STATUS, + (uint8_t *)&emb_func_status, 1); + + *val = emb_func_status.is_fsm_lc; + } + + ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Embedded final state machine functions mode.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fsm_en in reg EMB_FUNC_EN_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2duxs12_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val) +{ + int32_t ret; + + lis2duxs12_emb_func_en_b_t emb_func_en_b; + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + + emb_func_en_b.fsm_en = (uint8_t)val; + + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + } + + ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Embedded final state machine functions mode.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of fsm_en in reg EMB_FUNC_EN_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2duxs12_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + int32_t ret; + + lis2duxs12_emb_func_en_b_t emb_func_en_b; + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + + *val = emb_func_en_b.fsm_en; + + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + } + + ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Embedded final state machine functions mode.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2duxs12_fsm_enable_set(stmdev_ctx_t *ctx, + lis2duxs12_emb_fsm_enable_t *val) +{ + lis2duxs12_emb_func_en_b_t emb_func_en_b; + int32_t ret; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_FSM_ENABLE, + (uint8_t *)&val->fsm_enable, 1); + } + + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + + if ((val->fsm_enable.fsm1_en | + val->fsm_enable.fsm2_en | + val->fsm_enable.fsm3_en | + val->fsm_enable.fsm4_en | + val->fsm_enable.fsm5_en | + val->fsm_enable.fsm6_en | + val->fsm_enable.fsm7_en | + val->fsm_enable.fsm8_en) != PROPERTY_DISABLE) + { + emb_func_en_b.fsm_en = PROPERTY_ENABLE; + } + else + { + emb_func_en_b.fsm_en = PROPERTY_DISABLE; + } + + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + } + + ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Embedded final state machine functions mode.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2duxs12_fsm_enable_get(stmdev_ctx_t *ctx, + lis2duxs12_emb_fsm_enable_t *val) +{ + int32_t ret; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FSM_ENABLE, + (uint8_t *)&val->fsm_enable, 1); + } + + ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief FSM long counter status register. Long counter value is an + * unsigned integer value (16-bit format).[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2duxs12_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_FSM_LONG_COUNTER_L, buff, 2); + } + + ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief FSM long counter status register. Long counter value is an + * unsigned integer value (16-bit format).[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2duxs12_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FSM_LONG_COUNTER_L, buff, 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } + + ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief FSM status.[get] + * + * @param ctx read / write interface definitions + * @param val register FSM_STATUS_MAINPAGE + * + */ +int32_t lis2duxs12_fsm_status_get(stmdev_ctx_t *ctx, + lis2duxs12_fsm_status_mainpage_t *val) +{ + return lis2duxs12_read_reg(ctx, LIS2DUXS12_FSM_STATUS_MAINPAGE, + (uint8_t *) val, 1); +} + +/** + * @brief FSM output registers.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Structure of registers from FSM_OUTS1 to FSM_OUTS16 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2duxs12_fsm_out_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + int32_t ret; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FSM_OUTS1, val, 8); + } + + ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Finite State Machine ODR configuration.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2duxs12_fsm_data_rate_set(stmdev_ctx_t *ctx, + lis2duxs12_fsm_val_odr_t val) +{ + lis2duxs12_fsm_odr_t fsm_odr_reg; + int32_t ret; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FSM_ODR, + (uint8_t *)&fsm_odr_reg, 1); + + fsm_odr_reg.fsm_odr = (uint8_t)val; + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FSM_ODR, + (uint8_t *)&fsm_odr_reg, 1); + } + + ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Finite State Machine ODR configuration.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2duxs12_fsm_data_rate_get(stmdev_ctx_t *ctx, + lis2duxs12_fsm_val_odr_t *val) +{ + lis2duxs12_fsm_odr_t fsm_odr_reg; + int32_t ret; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FSM_ODR, + (uint8_t *)&fsm_odr_reg, 1); + } + + ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + switch (fsm_odr_reg.fsm_odr) + { + case LIS2DUXS12_ODR_FSM_12Hz5: + *val = LIS2DUXS12_ODR_FSM_12Hz5; + break; + + case LIS2DUXS12_ODR_FSM_25Hz: + *val = LIS2DUXS12_ODR_FSM_25Hz; + break; + + case LIS2DUXS12_ODR_FSM_50Hz: + *val = LIS2DUXS12_ODR_FSM_50Hz; + break; + + case LIS2DUXS12_ODR_FSM_100Hz: + *val = LIS2DUXS12_ODR_FSM_100Hz; + break; + + case LIS2DUXS12_ODR_FSM_200Hz: + *val = LIS2DUXS12_ODR_FSM_200Hz; + break; + + case LIS2DUXS12_ODR_FSM_400Hz: + *val = LIS2DUXS12_ODR_FSM_400Hz; + break; + + case LIS2DUXS12_ODR_FSM_800Hz: + *val = LIS2DUXS12_ODR_FSM_800Hz; + break; + + default: + *val = LIS2DUXS12_ODR_FSM_12Hz5; + break; + } + + return ret; +} + +/** + * @brief FSM initialization request.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fsm_init in reg FSM_INIT + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2duxs12_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lis2duxs12_emb_func_init_b_t emb_func_init_b; + int32_t ret; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_INIT_B, + (uint8_t *)&emb_func_init_b, 1); + + emb_func_init_b.fsm_init = (uint8_t)val; + + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_INIT_B, + (uint8_t *)&emb_func_init_b, 1); + } + + ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief FSM initialization request.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fsm_init in reg FSM_INIT + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2duxs12_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lis2duxs12_emb_func_init_b_t emb_func_init_b; + int32_t ret; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_INIT_B, + (uint8_t *)&emb_func_init_b, 1); + + *val = emb_func_init_b.fsm_init; + } + + ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief FSM long counter timeout register (r/w). The long counter + * timeout value is an unsigned integer value (16-bit format). + * When the long counter value reached this value, the FSM + * generates an interrupt.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2duxs12_long_cnt_int_value_set(stmdev_ctx_t *ctx, + uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = lis2duxs12_ln_pg_write(ctx, LIS2DUXS12_FSM_LC_TIMEOUT_L, buff, 2); + + return ret; +} + +/** + * @brief FSM long counter timeout register (r/w). The long counter + * timeout value is an unsigned integer value (16-bit format). + * When the long counter value reached this value, the FSM generates + * an interrupt.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2duxs12_long_cnt_int_value_get(stmdev_ctx_t *ctx, + uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_FSM_LC_TIMEOUT_L, buff, 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief FSM number of programs register.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2duxs12_fsm_number_of_programs_set(stmdev_ctx_t *ctx, + uint8_t *buff) +{ + int32_t ret; + + ret = lis2duxs12_ln_pg_write(ctx, LIS2DUXS12_FSM_PROGRAMS, buff, 2); + + return ret; +} + +/** + * @brief FSM number of programs register.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2duxs12_fsm_number_of_programs_get(stmdev_ctx_t *ctx, + uint8_t *buff) +{ + int32_t ret; + + ret = lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_FSM_PROGRAMS, buff, 2); + + return ret; +} + +/** + * @brief FSM start address register (r/w). First available address is + * 0x033C.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2duxs12_fsm_start_address_set(stmdev_ctx_t *ctx, + uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = lis2duxs12_ln_pg_write(ctx, LIS2DUXS12_FSM_START_ADD_L, buff, 2); + + return ret; +} + +/** + * @brief FSM start address register (r/w). First available address + * is 0x033C.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lis2duxs12_fsm_start_address_get(stmdev_ctx_t *ctx, + uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_FSM_START_ADD_L, buff, 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @addtogroup Machine Learning Core + * @brief This section group all the functions concerning the + * usage of Machine Learning Core + * @{ + * + */ + +/** + * @brief Enable Machine Learning Core.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of mlc_en in + * reg EMB_FUNC_EN_B and mlc_before_fsm_en + * in EMB_FUNC_INIT_A + * + */ +int32_t lis2duxs12_mlc_set(stmdev_ctx_t *ctx, lis2duxs12_mlc_mode_t val) +{ + lis2duxs12_emb_func_en_a_t emb_en_a; + lis2duxs12_emb_func_en_b_t emb_en_b; + int32_t ret; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + + switch(val) + { + case LIS2DUXS12_MLC_OFF: + emb_en_a.mlc_before_fsm_en = 0; + emb_en_b.mlc_en = 0; + break; + case LIS2DUXS12_MLC_ON: + emb_en_a.mlc_before_fsm_en = 0; + emb_en_b.mlc_en = 1; + break; + case LIS2DUXS12_MLC_ON_BEFORE_FSM: + emb_en_a.mlc_before_fsm_en = 1; + emb_en_b.mlc_en = 0; + break; + default: + break; + } + + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + } + + ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable Machine Learning Core.[get] + * + * @param ctx read / write interface definitions + * @param val get the values of mlc_en in + * reg EMB_FUNC_EN_B and mlc_before_fsm_en + * in EMB_FUNC_INIT_A + * + */ +int32_t lis2duxs12_mlc_get(stmdev_ctx_t *ctx, lis2duxs12_mlc_mode_t *val) +{ + lis2duxs12_emb_func_en_a_t emb_en_a; + lis2duxs12_emb_func_en_b_t emb_en_b; + int32_t ret; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + + if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U) + { + *val = LIS2DUXS12_MLC_OFF; + } + else if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 1U) + { + *val = LIS2DUXS12_MLC_ON; + } + else if (emb_en_a.mlc_before_fsm_en == 1U) + { + *val = LIS2DUXS12_MLC_ON_BEFORE_FSM; + } + else + { + /* Do nothing */ + } + } + + ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Machine Learning Core status register[get] + * + * @param ctx read / write interface definitions + * @param val register MLC_STATUS_MAINPAGE + * + */ +int32_t lis2duxs12_mlc_status_get(stmdev_ctx_t *ctx, + lis2duxs12_mlc_status_mainpage_t *val) +{ + return lis2duxs12_read_reg(ctx, LIS2DUXS12_MLC_STATUS_MAINPAGE, + (uint8_t *) val, 1); +} + +/** + * @brief prgsens_out: [get] Output value of all MLCx decision trees. + * + * @param ctx_t *ctx: read / write interface definitions + * @param uint8_t * : buffer that stores data read + * + */ +int32_t lis2duxs12_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_MLC1_SRC, buff, 4); + } + + ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Machine Learning Core data rate selection.[set] + * + * @param ctx read / write interface definitions + * @param val get the values of mlc_odr in + * reg EMB_FUNC_ODR_CFG_C + * + */ +int32_t lis2duxs12_mlc_data_rate_set(stmdev_ctx_t *ctx, + lis2duxs12_mlc_odr_val_t val) +{ + lis2duxs12_mlc_odr_t reg; + int32_t ret; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_MLC_ODR, (uint8_t *)®, 1); + reg.mlc_odr = (uint8_t)val; + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_MLC_ODR, (uint8_t *)®, 1); + } + + if (ret == 0) + { + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief Machine Learning Core data rate selection.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of mlc_odr in + * reg EMB_FUNC_ODR_CFG_C + * + */ +int32_t lis2duxs12_mlc_data_rate_get(stmdev_ctx_t *ctx, + lis2duxs12_mlc_odr_val_t *val) +{ + lis2duxs12_mlc_odr_t reg; + int32_t ret; + + ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_MLC_ODR, (uint8_t *)®, 1); + + switch (reg.mlc_odr) + { + case LIS2DUXS12_ODR_PRGS_12Hz5: + *val = LIS2DUXS12_ODR_PRGS_12Hz5; + break; + + case LIS2DUXS12_ODR_PRGS_25Hz: + *val = LIS2DUXS12_ODR_PRGS_25Hz; + break; + + case LIS2DUXS12_ODR_PRGS_50Hz: + *val = LIS2DUXS12_ODR_PRGS_50Hz; + break; + + case LIS2DUXS12_ODR_PRGS_100Hz: + *val = LIS2DUXS12_ODR_PRGS_100Hz; + break; + + case LIS2DUXS12_ODR_PRGS_200Hz: + *val = LIS2DUXS12_ODR_PRGS_200Hz; + break; + + default: + *val = LIS2DUXS12_ODR_PRGS_12Hz5; + break; + } + } + + ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis2duxs12_STdC/driver/lis2duxs12_reg.h b/sensor/stmemsc/lis2duxs12_STdC/driver/lis2duxs12_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..71772d5e51a733630f10f4bf1423c77bf65710e5 --- /dev/null +++ b/sensor/stmemsc/lis2duxs12_STdC/driver/lis2duxs12_reg.h @@ -0,0 +1,2653 @@ +/* + ****************************************************************************** + * @file lis2duxs12_reg.h + * @author Sensors Software Solution Team + * @brief This file contains all the functions prototypes for the + * lis2duxs12_reg.c driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2022 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef LIS2DUXS12_REGS_H +#define LIS2DUXS12_REGS_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include + +/** @addtogroup LIS2DUXS12 + * @{ + * + */ + +/** @defgroup Endianness definitions + * @{ + * + */ + +#ifndef DRV_BYTE_ORDER +#ifndef __BYTE_ORDER__ + +#define DRV_LITTLE_ENDIAN 1234 +#define DRV_BIG_ENDIAN 4321 + +/** if _BYTE_ORDER is not defined, choose the endianness of your architecture + * by uncommenting the define which fits your platform endianness + */ +//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN +#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN + +#else /* defined __BYTE_ORDER__ */ + +#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ +#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ +#define DRV_BYTE_ORDER __BYTE_ORDER__ + +#endif /* __BYTE_ORDER__*/ +#endif /* DRV_BYTE_ORDER */ + +/** + * @} + * + */ + +/** @defgroup STMicroelectronics sensors common types + * @{ + * + */ + +#ifndef MEMS_SHARED_TYPES +#define MEMS_SHARED_TYPES + +typedef struct{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} bitwise_t; + +#define PROPERTY_DISABLE (0U) +#define PROPERTY_ENABLE (1U) + +/** @addtogroup Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); +typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); + +typedef struct +{ + /** Component mandatory fields **/ + stmdev_write_ptr write_reg; + stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; + /** Customizable optional pointer **/ + void *handle; +} stmdev_ctx_t; + +/** + * @} + * + */ + +#endif /* MEMS_SHARED_TYPES */ + +#ifndef MEMS_UCF_SHARED_TYPES +#define MEMS_UCF_SHARED_TYPES + +/** @defgroup Generic address-data structure definition + * @brief This structure is useful to load a predefined configuration + * of a sensor. + * You can create a sensor configuration by your own or using + * Unico / Unicleo tools available on STMicroelectronics + * web site. + * + * @{ + * + */ + +typedef struct { + uint8_t address; + uint8_t data; +} ucf_line_t; + +/** + * @} + * + */ + +#endif /* MEMS_UCF_SHARED_TYPES */ + +/** + * @} + * + */ + +/** @defgroup LIS2DUXS12_Infos + * @{ + * + */ + +/** I2C Device Address 8 bit format if SA0=0 -> 0x if SA0=1 -> 0x **/ +#define LIS2DUXS12_I2C_ADD_L 0x31U +#define LIS2DUXS12_I2C_ADD_H 0x33U + +/** Device Identification (Who am I) **/ +#define LIS2DUXS12_ID 0x47U + +/** + * @} + * + */ + +#define LIS2DUXS12_PIN_CTRL 0x0CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sim : 1; + uint8_t pp_od : 1; + uint8_t cs_pu_dis : 1; + uint8_t h_lactive : 1; + uint8_t pd_dis_int1 : 1; + uint8_t pd_dis_int2 : 1; + uint8_t sda_pu_en : 1; + uint8_t sdo_pu_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sdo_pu_en : 1; + uint8_t sda_pu_en : 1; + uint8_t pd_dis_int2 : 1; + uint8_t pd_dis_int1 : 1; + uint8_t h_lactive : 1; + uint8_t cs_pu_dis : 1; + uint8_t pp_od : 1; + uint8_t sim : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_pin_ctrl_t; + +#define LIS2DUXS12_WAKE_UP_DUR_EXT 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 4; + uint8_t wu_dur_extended : 1; + uint8_t not_used1 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 3; + uint8_t wu_dur_extended : 1; + uint8_t not_used0 : 4; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_wake_up_dur_ext_t; + +#define LIS2DUXS12_WHO_AM_I 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t id : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t id : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_who_am_i_t; + +#define LIS2DUXS12_CTRL1 0x10U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wu_z_en : 1; + uint8_t wu_y_en : 1; + uint8_t wu_x_en : 1; + uint8_t drdy_pulsed : 1; + uint8_t if_add_inc : 1; + uint8_t sw_reset : 1; + uint8_t int1_on_res : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t int1_on_res : 1; + uint8_t sw_reset : 1; + uint8_t if_add_inc : 1; + uint8_t drdy_pulsed : 1; + uint8_t wu_x_en : 1; + uint8_t wu_y_en : 1; + uint8_t wu_z_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_ctrl1_t; + +#define LIS2DUXS12_CTRL2 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t int1_drdy : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_fifo_th : 1; + uint8_t int1_fifo_full : 1; + uint8_t int1_boot : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_boot : 1; + uint8_t int1_fifo_full : 1; + uint8_t int1_fifo_th : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_drdy : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_ctrl2_t; + +#define LIS2DUXS12_CTRL3 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t st_sign_x : 1; + uint8_t st_sign_y : 1; + uint8_t hp_en : 1; + uint8_t int2_drdy : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_fifo_th : 1; + uint8_t int2_fifo_full : 1; + uint8_t int2_boot : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_boot : 1; + uint8_t int2_fifo_full : 1; + uint8_t int2_fifo_th : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_drdy : 1; + uint8_t hp_en : 1; + uint8_t st_sign_y : 1; + uint8_t st_sign_x : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_ctrl3_t; + +#define LIS2DUXS12_CTRL4 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t boot : 1; + uint8_t soc : 1; + uint8_t not_used0 : 1; + uint8_t fifo_en : 1; + uint8_t emb_func_en : 1; + uint8_t bdu : 1; + uint8_t inact_odr : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t inact_odr : 2; + uint8_t bdu : 1; + uint8_t emb_func_en : 1; + uint8_t fifo_en : 1; + uint8_t not_used0 : 1; + uint8_t soc : 1; + uint8_t boot : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_ctrl4_t; + +#define LIS2DUXS12_CTRL5 0x14U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs : 2; + uint8_t bw : 2; + uint8_t odr : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t odr : 4; + uint8_t bw : 2; + uint8_t fs : 2; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_ctrl5_t; + +#define LIS2DUXS12_FIFO_CTRL 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_mode : 3; + uint8_t stop_on_fth : 1; + uint8_t not_used0 : 2; + uint8_t fifo_depth : 1; + uint8_t cfg_chg_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t cfg_chg_en : 1; + uint8_t fifo_depth : 1; + uint8_t not_used0 : 2; + uint8_t stop_on_fth : 1; + uint8_t fifo_mode : 3; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fifo_ctrl_t; + +#define LIS2DUXS12_FIFO_WTM 0x16U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fth : 7; + uint8_t xl_only_fifo : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t xl_only_fifo : 1; + uint8_t fth : 7; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fifo_wtm_t; + +#define LIS2DUXS12_INTERRUPT_CFG 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t interrupts_enable : 1; + uint8_t lir : 1; + uint8_t dis_rst_lir_all_int : 1; + uint8_t sleep_status_on_int : 1; + uint8_t not_used0 : 1; + uint8_t wake_ths_w : 1; + uint8_t not_used1 : 1; + uint8_t timestamp_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp_en : 1; + uint8_t not_used1 : 1; + uint8_t wake_ths_w : 1; + uint8_t not_used0 : 1; + uint8_t sleep_status_on_int : 1; + uint8_t dis_rst_lir_all_int : 1; + uint8_t lir : 1; + uint8_t interrupts_enable : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_interrupt_cfg_t; + +#define LIS2DUXS12_SIXD 0x18U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 5; + uint8_t d6d_ths : 2; + uint8_t d4d_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t d4d_en : 1; + uint8_t d6d_ths : 2; + uint8_t not_used0 : 5; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_sixd_t; + +#define LIS2DUXS12_WAKE_UP_THS 0x1CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wk_ths : 6; + uint8_t sleep_on : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t sleep_on : 1; + uint8_t wk_ths : 6; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_wake_up_ths_t; + +#define LIS2DUXS12_WAKE_UP_DUR 0x1DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sleep_dur : 4; + uint8_t st_sign_z : 1; + uint8_t wake_dur : 2; + uint8_t ff_dur : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ff_dur : 1; + uint8_t wake_dur : 2; + uint8_t st_sign_z : 1; + uint8_t sleep_dur : 4; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_wake_up_dur_t; + +#define LIS2DUXS12_FREE_FALL 0x1EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ff_ths : 3; + uint8_t ff_dur : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ff_dur : 5; + uint8_t ff_ths : 3; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_free_fall_t; + +#define LIS2DUXS12_MD1_CFG 0x1FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_emb_func : 1; + uint8_t int1_timestamp : 1; + uint8_t int1_6d : 1; + uint8_t int1_tap : 1; + uint8_t int1_ff : 1; + uint8_t int1_wu : 1; + uint8_t not_used0 : 1; + uint8_t int1_sleep_change : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_sleep_change : 1; + uint8_t not_used0 : 1; + uint8_t int1_wu : 1; + uint8_t int1_ff : 1; + uint8_t int1_tap : 1; + uint8_t int1_6d : 1; + uint8_t int1_timestamp : 1; + uint8_t int1_emb_func : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_md1_cfg_t; + +#define LIS2DUXS12_MD2_CFG 0x20U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_emb_func : 1; + uint8_t int2_timestamp : 1; + uint8_t int2_6d : 1; + uint8_t int2_tap : 1; + uint8_t int2_ff : 1; + uint8_t int2_wu : 1; + uint8_t not_used0 : 1; + uint8_t int2_sleep_change : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_sleep_change : 1; + uint8_t not_used0 : 1; + uint8_t int2_wu : 1; + uint8_t int2_ff : 1; + uint8_t int2_tap : 1; + uint8_t int2_6d : 1; + uint8_t int2_timestamp : 1; + uint8_t int2_emb_func : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_md2_cfg_t; + +#define LIS2DUXS12_WAKE_UP_SRC 0x21U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t z_wu : 1; + uint8_t y_wu : 1; + uint8_t x_wu : 1; + uint8_t wu_ia : 1; + uint8_t sleep_state : 1; + uint8_t ff_ia : 1; + uint8_t sleep_change_ia : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t sleep_change_ia : 1; + uint8_t ff_ia : 1; + uint8_t sleep_state : 1; + uint8_t wu_ia : 1; + uint8_t x_wu : 1; + uint8_t y_wu : 1; + uint8_t z_wu : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_wake_up_src_t; + +#define LIS2DUXS12_TAP_SRC 0x22U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 4; + uint8_t triple_tap_ia : 1; + uint8_t double_tap_ia : 1; + uint8_t single_tap_ia : 1; + uint8_t tap_ia : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tap_ia : 1; + uint8_t single_tap_ia : 1; + uint8_t double_tap_ia : 1; + uint8_t triple_tap_ia : 1; + uint8_t not_used0 : 4; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_tap_src_t; + +#define LIS2DUXS12_SIXD_SRC 0x23U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xl : 1; + uint8_t xh : 1; + uint8_t yl : 1; + uint8_t yh : 1; + uint8_t zl : 1; + uint8_t zh : 1; + uint8_t d6d_ia : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t d6d_ia : 1; + uint8_t zh : 1; + uint8_t zl : 1; + uint8_t yh : 1; + uint8_t yl : 1; + uint8_t xh : 1; + uint8_t xl : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_sixd_src_t; + +#define LIS2DUXS12_ALL_INT_SRC 0x24U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ff_ia_all : 1; + uint8_t wu_ia_all : 1; + uint8_t single_tap_all : 1; + uint8_t double_tap_all : 1; + uint8_t triple_tap_all : 1; + uint8_t d6d_ia_all : 1; + uint8_t sleep_change_ia_all : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t sleep_change_ia_all : 1; + uint8_t d6d_ia_all : 1; + uint8_t triple_tap_all : 1; + uint8_t double_tap_all : 1; + uint8_t single_tap_all : 1; + uint8_t wu_ia_all : 1; + uint8_t ff_ia_all : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_all_int_src_t; + +#define LIS2DUXS12_STATUS 0x25U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t drdy : 1; + uint8_t not_used0 : 4; + uint8_t int_global : 1; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t int_global : 1; + uint8_t not_used0 : 4; + uint8_t drdy : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_status_register_t; + +#define LIS2DUXS12_FIFO_STATUS1 0x26U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 6; + uint8_t fifo_ovr_ia : 1; + uint8_t fifo_wtm_ia : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_wtm_ia : 1; + uint8_t fifo_ovr_ia : 1; + uint8_t not_used0 : 6; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fifo_status1_t; + +#define LIS2DUXS12_FIFO_STATUS2 0x27U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fss : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fss : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fifo_status2_t; + +#define LIS2DUXS12_OUT_X_L 0x28U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_out_x_l_t; + +#define LIS2DUXS12_OUT_X_H 0x29U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_out_x_h_t; + +#define LIS2DUXS12_OUT_Y_L 0x2AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_out_y_l_t; + +#define LIS2DUXS12_OUT_Y_H 0x2BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_out_y_h_t; + +#define LIS2DUXS12_OUT_Z_L 0x2CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_out_z_l_t; + +#define LIS2DUXS12_OUT_Z_H 0x2DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_out_z_h_t; + +#define LIS2DUXS12_OUT_T_AH_QVAR_L 0x2EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outt : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outt : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_out_t_ah_qvar_l_t; + +#define LIS2DUXS12_OUT_T_AH_QVAR_H 0x2FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outt : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outt : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_out_t_ah_qvar_h_t; + +#define LIS2DUXS12_AH_QVAR_CFG 0x31U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t ah_qvar_gain : 2; + uint8_t ah_qvar_c_zin : 2; + uint8_t ah_qvar_notch_cutoff : 1; + uint8_t ah_qvar_notch_en : 1; + uint8_t ah_qvar_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ah_qvar_en : 1; + uint8_t ah_qvar_notch_en : 1; + uint8_t ah_qvar_notch_cutoff : 1; + uint8_t ah_qvar_c_zin : 2; + uint8_t ah_qvar_gain : 2; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_ah_qvar_cfg_t; + +#define LIS2DUXS12_SELF_TEST 0x32U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 4; + uint8_t st : 2; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t st : 2; + uint8_t not_used0 : 4; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_self_test_t; + +#define LIS2DUXS12_I3C_IF_CTRL 0x33U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bus_act_sel : 2; + uint8_t not_used0 : 3; + uint8_t asf_on : 1; + uint8_t dis_drstdaa : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t dis_drstdaa : 1; + uint8_t asf_on : 1; + uint8_t not_used0 : 3; + uint8_t bus_act_sel : 2; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_i3c_if_ctrl_t; + +#define LIS2DUXS12_EMB_FUNC_STATUS_MAINPAGE 0x34U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t is_step_det : 1; + uint8_t is_tilt : 1; + uint8_t is_sigmot : 1; + uint8_t not_used1 : 1; + uint8_t is_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t is_sigmot : 1; + uint8_t is_tilt : 1; + uint8_t is_step_det : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_emb_func_status_mainpage_t; + +#define LIS2DUXS12_FSM_STATUS_MAINPAGE 0x35U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm1 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm8 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fsm_status_mainpage_t; + +#define LIS2DUXS12_MLC_STATUS_MAINPAGE 0x36U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_mlc1 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc4 : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t is_mlc4 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_mlc_status_mainpage_t; + +#define LIS2DUXS12_SLEEP 0x3DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t deep_pd : 1; + uint8_t not_used0 : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 7; + uint8_t deep_pd : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_sleep_t; + +#define LIS2DUXS12_IF_WAKE_UP 0x3EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t soft_pd : 1; + uint8_t not_used0 : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 7; + uint8_t soft_pd : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_if_wake_up_t; + +#define LIS2DUXS12_FUNC_CFG_ACCESS 0x3FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_wr_ctrl_en : 1; + uint8_t not_used0 : 6; + uint8_t emb_func_reg_access : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t emb_func_reg_access : 1; + uint8_t not_used0 : 6; + uint8_t fsm_wr_ctrl_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_func_cfg_access_t; + +#define LIS2DUXS12_FIFO_DATA_OUT_TAG 0x40U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t tag_sensor : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tag_sensor : 5; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fifo_data_out_tag_t; + +#define LIS2DUXS12_FIFO_DATA_OUT_X_L 0x41U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fifo_data_out_x_l_t; + +#define LIS2DUXS12_FIFO_DATA_OUT_X_H 0x42U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fifo_data_out_x_h_t; + +#define LIS2DUXS12_FIFO_DATA_OUT_Y_L 0x43U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fifo_data_out_y_l_t; + +#define LIS2DUXS12_FIFO_DATA_OUT_Y_H 0x44U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fifo_data_out_y_h_t; + +#define LIS2DUXS12_FIFO_DATA_OUT_Z_L 0x45U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fifo_data_out_z_l_t; + +#define LIS2DUXS12_FIFO_DATA_OUT_Z_H 0x46U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fifo_data_out_z_h_t; + +#define LIS2DUXS12_FIFO_BATCH_DEC 0x47U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bdr_xl : 3; + uint8_t dec_ts_batch : 2; + uint8_t not_used0 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 3; + uint8_t dec_ts_batch : 2; + uint8_t bdr_xl : 3; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fifo_batch_dec_t; + +#define LIS2DUXS12_TAP_CFG0 0x6FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t invert_t : 5; + uint8_t axis : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t axis : 2; + uint8_t invert_t : 5; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_tap_cfg0_t; + +#define LIS2DUXS12_TAP_CFG1 0x70U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t post_still_t : 4; + uint8_t pre_still_ths : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pre_still_ths : 4; + uint8_t post_still_t : 4; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_tap_cfg1_t; + +#define LIS2DUXS12_TAP_CFG2 0x71U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wait_t : 6; + uint8_t post_still_t : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t post_still_t : 2; + uint8_t wait_t : 6; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_tap_cfg2_t; + +#define LIS2DUXS12_TAP_CFG3 0x72U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t latency_t : 4; + uint8_t post_still_ths : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t post_still_ths : 4; + uint8_t latency_t : 4; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_tap_cfg3_t; + +#define LIS2DUXS12_TAP_CFG4 0x73U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t peak_ths : 6; + uint8_t not_used0 : 1; + uint8_t wait_end_latency : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t wait_end_latency : 1; + uint8_t not_used0 : 1; + uint8_t peak_ths : 6; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_tap_cfg4_t; + +#define LIS2DUXS12_TAP_CFG5 0x74U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t rebound_t : 5; + uint8_t single_tap_en : 1; + uint8_t double_tap_en : 1; + uint8_t triple_tap_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t triple_tap_en : 1; + uint8_t double_tap_en : 1; + uint8_t single_tap_en : 1; + uint8_t rebound_t : 5; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_tap_cfg5_t; + +#define LIS2DUXS12_TAP_CFG6 0x75U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t pre_still_n : 4; + uint8_t pre_still_st : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pre_still_st : 4; + uint8_t pre_still_n : 4; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_tap_cfg6_t; + +#define LIS2DUXS12_TIMESTAMP0 0x7AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_timestamp0_t; + +#define LIS2DUXS12_TIMESTAMP1 0x7BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_timestamp1_t; + +#define LIS2DUXS12_TIMESTAMP2 0x7CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_timestamp2_t; + +#define LIS2DUXS12_TIMESTAMP3 0x7DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_timestamp3_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page embedded + * @{ + * + */ + +#define LIS2DUXS12_PAGE_SEL 0x2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 4; + uint8_t page_sel : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_sel : 4; + uint8_t not_used0 : 4; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_page_sel_t; + +#define LIS2DUXS12_EMB_FUNC_EN_A 0x4U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t pedo_en : 1; + uint8_t tilt_en : 1; + uint8_t sign_motion_en : 1; + uint8_t not_used1 : 1; + uint8_t mlc_before_fsm_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_before_fsm_en : 1; + uint8_t not_used1 : 1; + uint8_t sign_motion_en : 1; + uint8_t tilt_en : 1; + uint8_t pedo_en : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_emb_func_en_a_t; + +#define LIS2DUXS12_EMB_FUNC_EN_B 0x5U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_en : 1; + uint8_t not_used0 : 3; + uint8_t mlc_en : 1; + uint8_t not_used1 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 3; + uint8_t mlc_en : 1; + uint8_t not_used0 : 3; + uint8_t fsm_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_emb_func_en_b_t; + +#define LIS2DUXS12_EMB_FUNC_EXEC_STATUS 0x7U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t emb_func_endop : 1; + uint8_t emb_func_exec_ovr : 1; + uint8_t not_used0 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 6; + uint8_t emb_func_exec_ovr : 1; + uint8_t emb_func_endop : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_emb_func_exec_status_t; + +#define LIS2DUXS12_PAGE_ADDRESS 0x8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t page_addr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_addr : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_page_address_t; + +#define LIS2DUXS12_PAGE_VALUE 0x9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t page_value : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_value : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_page_value_t; + +#define LIS2DUXS12_EMB_FUNC_INT1 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t int1_step_det : 1; + uint8_t int1_tilt : 1; + uint8_t int1_sig_mot : 1; + uint8_t not_used1 : 1; + uint8_t int1_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t int1_sig_mot : 1; + uint8_t int1_tilt : 1; + uint8_t int1_step_det : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_emb_func_int1_t; + +#define LIS2DUXS12_FSM_INT1 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_fsm1 : 1; + uint8_t int1_fsm2 : 1; + uint8_t int1_fsm3 : 1; + uint8_t int1_fsm4 : 1; + uint8_t int1_fsm5 : 1; + uint8_t int1_fsm6 : 1; + uint8_t int1_fsm7 : 1; + uint8_t int1_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_fsm8 : 1; + uint8_t int1_fsm7 : 1; + uint8_t int1_fsm6 : 1; + uint8_t int1_fsm5 : 1; + uint8_t int1_fsm4 : 1; + uint8_t int1_fsm3 : 1; + uint8_t int1_fsm2 : 1; + uint8_t int1_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fsm_int1_t; + +#define LIS2DUXS12_MLC_INT1 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_mlc1 : 1; + uint8_t int1_mlc2 : 1; + uint8_t int1_mlc3 : 1; + uint8_t int1_mlc4 : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t int1_mlc4 : 1; + uint8_t int1_mlc3 : 1; + uint8_t int1_mlc2 : 1; + uint8_t int1_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_mlc_int1_t; + +#define LIS2DUXS12_EMB_FUNC_INT2 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t int2_step_det : 1; + uint8_t int2_tilt : 1; + uint8_t int2_sig_mot : 1; + uint8_t not_used1 : 1; + uint8_t int2_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t int2_sig_mot : 1; + uint8_t int2_tilt : 1; + uint8_t int2_step_det : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_emb_func_int2_t; + +#define LIS2DUXS12_FSM_INT2 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_fsm1 : 1; + uint8_t int2_fsm2 : 1; + uint8_t int2_fsm3 : 1; + uint8_t int2_fsm4 : 1; + uint8_t int2_fsm5 : 1; + uint8_t int2_fsm6 : 1; + uint8_t int2_fsm7 : 1; + uint8_t int2_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_fsm8 : 1; + uint8_t int2_fsm7 : 1; + uint8_t int2_fsm6 : 1; + uint8_t int2_fsm5 : 1; + uint8_t int2_fsm4 : 1; + uint8_t int2_fsm3 : 1; + uint8_t int2_fsm2 : 1; + uint8_t int2_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fsm_int2_t; + +#define LIS2DUXS12_MLC_INT2 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_mlc1 : 1; + uint8_t int2_mlc2 : 1; + uint8_t int2_mlc3 : 1; + uint8_t int2_mlc4 : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t int2_mlc4 : 1; + uint8_t int2_mlc3 : 1; + uint8_t int2_mlc2 : 1; + uint8_t int2_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_mlc_int2_t; + +#define LIS2DUXS12_EMB_FUNC_STATUS 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t is_step_det : 1; + uint8_t is_tilt : 1; + uint8_t is_sigmot : 1; + uint8_t not_used1 : 1; + uint8_t is_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t is_sigmot : 1; + uint8_t is_tilt : 1; + uint8_t is_step_det : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_emb_func_status_t; + +#define LIS2DUXS12_FSM_STATUS 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm1 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm8 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fsm_status_t; + +#define LIS2DUXS12_MLC_STATUS 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_mlc1 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc4 : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t is_mlc4 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_mlc_status_t; + +#define LIS2DUXS12_PAGE_RW 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 5; + uint8_t page_read : 1; + uint8_t page_write : 1; + uint8_t emb_func_lir : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t emb_func_lir : 1; + uint8_t page_write : 1; + uint8_t page_read : 1; + uint8_t not_used0 : 5; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_page_rw_t; + +#define LIS2DUXS12_EMB_FUNC_FIFO_EN 0x18U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t step_counter_fifo_en : 1; + uint8_t mlc_fifo_en : 1; + uint8_t mlc_filter_feature_fifo_en : 1; + uint8_t fsm_fifo_en : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t fsm_fifo_en : 1; + uint8_t mlc_filter_feature_fifo_en : 1; + uint8_t mlc_fifo_en : 1; + uint8_t step_counter_fifo_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_emb_func_fifo_en_t; + +#define LIS2DUXS12_FSM_ENABLE 0x1AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm1_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm8_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm8_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm1_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fsm_enable_t; + +#define LIS2DUXS12_FSM_LONG_COUNTER_L 0x1CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fsm_long_counter_l_t; + +#define LIS2DUXS12_FSM_LONG_COUNTER_H 0x1DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fsm_long_counter_h_t; + +#define LIS2DUXS12_INT_ACK_MASK 0x1FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t iack_mask0 : 1; + uint8_t iack_mask1 : 1; + uint8_t iack_mask2 : 1; + uint8_t iack_mask3 : 1; + uint8_t iack_mask4 : 1; + uint8_t iack_mask5 : 1; + uint8_t iack_mask6 : 1; + uint8_t iack_mask7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t iack_mask7 : 1; + uint8_t iack_mask6 : 1; + uint8_t iack_mask5 : 1; + uint8_t iack_mask4 : 1; + uint8_t iack_mask3 : 1; + uint8_t iack_mask2 : 1; + uint8_t iack_mask1 : 1; + uint8_t iack_mask0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_int_ack_mask_t; + +#define LIS2DUXS12_FSM_OUTS1 0x20U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fsm_outs1_t; + +#define LIS2DUXS12_FSM_OUTS2 0x21U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fsm_outs2_t; + +#define LIS2DUXS12_FSM_OUTS3 0x22U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fsm_outs3_t; + +#define LIS2DUXS12_FSM_OUTS4 0x23U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fsm_outs4_t; + +#define LIS2DUXS12_FSM_OUTS5 0x24U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fsm_outs5_t; + +#define LIS2DUXS12_FSM_OUTS6 0x25U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fsm_outs6_t; + +#define LIS2DUXS12_FSM_OUTS7 0x26U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fsm_outs7_t; + +#define LIS2DUXS12_FSM_OUTS8 0x27U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fsm_outs8_t; + +#define LIS2DUXS12_STEP_COUNTER_L 0x28U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t step : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t step : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_step_counter_l_t; + +#define LIS2DUXS12_STEP_COUNTER_H 0x29U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t step : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t step : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_step_counter_h_t; + +#define LIS2DUXS12_EMB_FUNC_SRC 0x2AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t stepcounter_bit_set : 1; + uint8_t step_overflow : 1; + uint8_t step_count_delta_ia : 1; + uint8_t step_detected : 1; + uint8_t not_used1 : 1; + uint8_t pedo_rst_step : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pedo_rst_step : 1; + uint8_t not_used1 : 1; + uint8_t step_detected : 1; + uint8_t step_count_delta_ia : 1; + uint8_t step_overflow : 1; + uint8_t stepcounter_bit_set : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_emb_func_src_t; + +#define LIS2DUXS12_EMB_FUNC_INIT_A 0x2CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t step_det_init : 1; + uint8_t tilt_init : 1; + uint8_t sig_mot_init : 1; + uint8_t not_used1 : 1; + uint8_t mlc_before_fsm_init : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_before_fsm_init : 1; + uint8_t not_used1 : 1; + uint8_t sig_mot_init : 1; + uint8_t tilt_init : 1; + uint8_t step_det_init : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_emb_func_init_a_t; + +#define LIS2DUXS12_EMB_FUNC_INIT_B 0x2DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_init : 1; + uint8_t not_used0 : 3; + uint8_t mlc_init : 1; + uint8_t not_used1 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 3; + uint8_t mlc_init : 1; + uint8_t not_used0 : 3; + uint8_t fsm_init : 1; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_emb_func_init_b_t; + +#define LIS2DUXS12_MLC1_SRC 0x34U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc1_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc1_src : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_mlc1_src_t; + +#define LIS2DUXS12_MLC2_SRC 0x35U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc2_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc2_src : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_mlc2_src_t; + +#define LIS2DUXS12_MLC3_SRC 0x36U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc3_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc3_src : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_mlc3_src_t; + +#define LIS2DUXS12_MLC4_SRC 0x37U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc4_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc4_src : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_mlc4_src_t; + +#define LIS2DUXS12_FSM_ODR 0x39U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t fsm_odr : 3; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t fsm_odr : 3; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fsm_odr_t; + +#define LIS2DUXS12_MLC_ODR 0x3AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 4; + uint8_t mlc_odr : 3; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t mlc_odr : 3; + uint8_t not_used0 : 4; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_mlc_odr_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page pg0_emb_adv + * @{ + * + */ +#define LIS2DUXS12_EMB_ADV_PG_0 0x000U + +#define LIS2DUXS12_FSM_LC_TIMEOUT_L 0x54U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc_timeout : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc_timeout : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fsm_lc_timeout_l_t; + +#define LIS2DUXS12_FSM_LC_TIMEOUT_H 0x55U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc_timeout : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc_timeout : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fsm_lc_timeout_h_t; + +#define LIS2DUXS12_FSM_PROGRAMS 0x56U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_n_prog : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_n_prog : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fsm_programs_t; + +#define LIS2DUXS12_FSM_START_ADD_L 0x58U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_start : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_start : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fsm_start_add_l_t; + +#define LIS2DUXS12_FSM_START_ADD_H 0x59U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_start : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_start : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_fsm_start_add_h_t; + +#define LIS2DUXS12_PEDO_CMD_REG 0x5DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t fp_rejection_en : 1; + uint8_t carry_count_en : 1; + uint8_t not_used1 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 4; + uint8_t carry_count_en : 1; + uint8_t fp_rejection_en : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_pedo_cmd_reg_t; + +#define LIS2DUXS12_PEDO_DEB_STEPS_CONF 0x5EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t deb_step : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t deb_step : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_pedo_deb_steps_conf_t; + +#define LIS2DUXS12_PEDO_SC_DELTAT_L 0xAAU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t pd_sc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pd_sc : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_pedo_sc_deltat_l_t; + +#define LIS2DUXS12_PEDO_SC_DELTAT_H 0xABU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t pd_sc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pd_sc : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_pedo_sc_deltat_h_t; + +#define LIS2DUXS12_T_AH_QVAR_SENSITIVITY_L 0xB6U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t t_ah_qvar_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t t_ah_qvar_s : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_t_ah_qvar_sensitivity_l_t; + +#define LIS2DUXS12_T_AH_QVAR_SENSITIVITY_H 0xB7U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t t_ah_qvar_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t t_ah_qvar_s : 8; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_t_ah_qvar_sensitivity_h_t; + +/** + * @} + * + */ + +typedef union +{ + lis2duxs12_pin_ctrl_t pin_ctrl; + lis2duxs12_wake_up_dur_ext_t wake_up_dur_ext; + lis2duxs12_who_am_i_t who_am_i; + lis2duxs12_ctrl1_t ctrl1; + lis2duxs12_ctrl2_t ctrl2; + lis2duxs12_ctrl3_t ctrl3; + lis2duxs12_ctrl4_t ctrl4; + lis2duxs12_ctrl5_t ctrl5; + lis2duxs12_fifo_ctrl_t fifo_ctrl; + lis2duxs12_fifo_wtm_t fifo_wtm; + lis2duxs12_interrupt_cfg_t interrupt_cfg; + lis2duxs12_sixd_t sixd; + lis2duxs12_wake_up_ths_t wake_up_ths; + lis2duxs12_wake_up_dur_t wake_up_dur; + lis2duxs12_free_fall_t free_fall; + lis2duxs12_md1_cfg_t md1_cfg; + lis2duxs12_md2_cfg_t md2_cfg; + lis2duxs12_wake_up_src_t wake_up_src; + lis2duxs12_tap_src_t tap_src; + lis2duxs12_sixd_src_t sixd_src; + lis2duxs12_all_int_src_t all_int_src; + lis2duxs12_status_register_t status; + lis2duxs12_fifo_status1_t fifo_status1; + lis2duxs12_fifo_status2_t fifo_status2; + lis2duxs12_out_x_l_t out_x_l; + lis2duxs12_out_x_h_t out_x_h; + lis2duxs12_out_y_l_t out_y_l; + lis2duxs12_out_y_h_t out_y_h; + lis2duxs12_out_z_l_t out_z_l; + lis2duxs12_out_z_h_t out_z_h; + lis2duxs12_out_t_ah_qvar_l_t out_t_ah_qvar_l; + lis2duxs12_out_t_ah_qvar_h_t out_t_ah_qvar_h; + lis2duxs12_ah_qvar_cfg_t ah_qvar_cfg; + lis2duxs12_self_test_t self_test; + lis2duxs12_i3c_if_ctrl_t i3c_if_ctrl; + lis2duxs12_emb_func_status_mainpage_t emb_func_status_mainpage; + lis2duxs12_fsm_status_mainpage_t fsm_status_mainpage; + lis2duxs12_mlc_status_mainpage_t mlc_status_mainpage; + lis2duxs12_sleep_t sleep; + lis2duxs12_if_wake_up_t if_wake_up; + lis2duxs12_func_cfg_access_t func_cfg_access; + lis2duxs12_fifo_data_out_tag_t fifo_data_out_tag; + lis2duxs12_fifo_data_out_x_l_t fifo_data_out_x_l; + lis2duxs12_fifo_data_out_x_h_t fifo_data_out_x_h; + lis2duxs12_fifo_data_out_y_l_t fifo_data_out_y_l; + lis2duxs12_fifo_data_out_y_h_t fifo_data_out_y_h; + lis2duxs12_fifo_data_out_z_l_t fifo_data_out_z_l; + lis2duxs12_fifo_data_out_z_h_t fifo_data_out_z_h; + lis2duxs12_fifo_batch_dec_t fifo_batch_dec; + lis2duxs12_tap_cfg0_t tap_cfg0; + lis2duxs12_tap_cfg1_t tap_cfg1; + lis2duxs12_tap_cfg2_t tap_cfg2; + lis2duxs12_tap_cfg3_t tap_cfg3; + lis2duxs12_tap_cfg4_t tap_cfg4; + lis2duxs12_tap_cfg5_t tap_cfg5; + lis2duxs12_tap_cfg6_t tap_cfg6; + lis2duxs12_timestamp0_t timestamp0; + lis2duxs12_timestamp1_t timestamp1; + lis2duxs12_timestamp2_t timestamp2; + lis2duxs12_timestamp3_t timestamp3; + lis2duxs12_page_sel_t page_sel; + lis2duxs12_emb_func_en_a_t emb_func_en_a; + lis2duxs12_emb_func_en_b_t emb_func_en_b; + lis2duxs12_emb_func_exec_status_t emb_func_exec_status; + lis2duxs12_page_address_t page_address; + lis2duxs12_page_value_t page_value; + lis2duxs12_emb_func_int1_t emb_func_int1; + lis2duxs12_fsm_int1_t fsm_int1; + lis2duxs12_mlc_int1_t mlc_int1; + lis2duxs12_emb_func_int2_t emb_func_int2; + lis2duxs12_fsm_int2_t fsm_int2; + lis2duxs12_mlc_int2_t mlc_int2; + lis2duxs12_emb_func_status_t emb_func_status; + lis2duxs12_fsm_status_t fsm_status; + lis2duxs12_mlc_status_t mlc_status; + lis2duxs12_page_rw_t page_rw; + lis2duxs12_emb_func_fifo_en_t emb_func_fifo_en; + lis2duxs12_fsm_enable_t fsm_enable; + lis2duxs12_fsm_long_counter_l_t fsm_long_counter_l; + lis2duxs12_fsm_long_counter_h_t fsm_long_counter_h; + lis2duxs12_int_ack_mask_t int_ack_mask; + lis2duxs12_fsm_outs1_t fsm_outs1; + lis2duxs12_fsm_outs2_t fsm_outs2; + lis2duxs12_fsm_outs3_t fsm_outs3; + lis2duxs12_fsm_outs4_t fsm_outs4; + lis2duxs12_fsm_outs5_t fsm_outs5; + lis2duxs12_fsm_outs6_t fsm_outs6; + lis2duxs12_fsm_outs7_t fsm_outs7; + lis2duxs12_fsm_outs8_t fsm_outs8; + lis2duxs12_step_counter_l_t step_counter_l; + lis2duxs12_step_counter_h_t step_counter_h; + lis2duxs12_emb_func_src_t emb_func_src; + lis2duxs12_emb_func_init_a_t emb_func_init_a; + lis2duxs12_emb_func_init_b_t emb_func_init_b; + lis2duxs12_mlc1_src_t mlc1_src; + lis2duxs12_mlc2_src_t mlc2_src; + lis2duxs12_mlc3_src_t mlc3_src; + lis2duxs12_mlc4_src_t mlc4_src; + lis2duxs12_fsm_odr_t fsm_odr; + lis2duxs12_mlc_odr_t mlc_odr; + lis2duxs12_fsm_lc_timeout_l_t fsm_lc_timeout_l; + lis2duxs12_fsm_lc_timeout_h_t fsm_lc_timeout_h; + lis2duxs12_fsm_programs_t fsm_programs; + lis2duxs12_fsm_start_add_l_t fsm_start_add_l; + lis2duxs12_fsm_start_add_h_t fsm_start_add_h; + lis2duxs12_pedo_cmd_reg_t pedo_cmd_reg; + lis2duxs12_pedo_deb_steps_conf_t pedo_deb_steps_conf; + lis2duxs12_pedo_sc_deltat_l_t pedo_sc_deltat_l; + lis2duxs12_pedo_sc_deltat_h_t pedo_sc_deltat_h; + lis2duxs12_t_ah_qvar_sensitivity_l_t t_ah_qvar_sensitivity_l; + lis2duxs12_t_ah_qvar_sensitivity_h_t t_ah_qvar_sensitivity_h; + bitwise_t bitwise; + uint8_t byte; +} lis2duxs12_reg_t; + +/** + * @} + * + */ + +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + +int32_t lis2duxs12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); +int32_t lis2duxs12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); + +float_t lis2duxs12_from_fs2g_to_mg(int16_t lsb); +float_t lis2duxs12_from_fs4g_to_mg(int16_t lsb); +float_t lis2duxs12_from_fs8g_to_mg(int16_t lsb); +float_t lis2duxs12_from_fs16g_to_mg(int16_t lsb); +float_t lis2duxs12_from_lsb_to_celsius(int16_t lsb); + +int32_t lis2duxs12_device_id_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { + LIS2DUXS12_SENSOR_ONLY_ON = 0x00, /* Initialize the driver for sensor usage */ + LIS2DUXS12_BOOT = 0x01, /* Restore calib. param. (it takes 10ms) */ + LIS2DUXS12_RESET = 0x02, /* Reset configuration registers */ + LIS2DUXS12_SENSOR_EMB_FUNC_ON = 0x03, /* Initialize the driver for sensor and/or + embedded functions usage (it takes 10ms) */ +} lis2duxs12_init_t; +int32_t lis2duxs12_init_set(stmdev_ctx_t *ctx, lis2duxs12_init_t val); + +typedef struct { + uint8_t sw_reset : 1; /* Restoring configuration registers */ + uint8_t boot : 1; /* Restoring calibration parameters */ + uint8_t drdy : 1; /* Accelerometer data ready */ + uint8_t power_down : 1; /* Monitors power-down. */ +} lis2duxs12_status_t; +int32_t lis2duxs12_status_get(stmdev_ctx_t *ctx, lis2duxs12_status_t *val); + +typedef struct { + uint8_t is_step_det : 1; /* Step detected */ + uint8_t is_tilt : 1; /* Tilt detected */ + uint8_t is_sigmot : 1; /* Significant motion detected */ +} lis2duxs12_embedded_status_t; +int32_t lis2duxs12_embedded_status_get(stmdev_ctx_t *ctx, lis2duxs12_embedded_status_t *val); + +typedef enum +{ + LIS2DUXS12_DRDY_LATCHED = 0x0, + LIS2DUXS12_DRDY_PULSED = 0x1, +} lis2duxs12_data_ready_mode_t; +int32_t lis2duxs12_data_ready_mode_set(stmdev_ctx_t *ctx, lis2duxs12_data_ready_mode_t val); +int32_t lis2duxs12_data_ready_mode_get(stmdev_ctx_t *ctx, lis2duxs12_data_ready_mode_t *val); + +typedef struct { + enum { + LIS2DUXS12_OFF = 0x00, /* in power down */ + LIS2DUXS12_1Hz5_ULP = 0x01, /* @1Hz6 (low power) */ + LIS2DUXS12_3Hz_ULP = 0x02, /* @3Hz (ultra low) */ + LIS2DUXS12_25Hz_ULP = 0x03, /* @25Hz (ultra low) */ + LIS2DUXS12_6Hz = 0x04, /* @6Hz (low power) */ + LIS2DUXS12_12Hz5 = 0x05, /* @12Hz5 (low power) */ + LIS2DUXS12_25Hz = 0x06, /* @25Hz (low power ) */ + LIS2DUXS12_50Hz = 0x07, /* @50Hz (low power) */ + LIS2DUXS12_100Hz = 0x08, /* @100Hz (low power) */ + LIS2DUXS12_200Hz = 0x09, /* @200Hz (low power) */ + LIS2DUXS12_400Hz = 0x0A, /* @400Hz (low power) */ + LIS2DUXS12_800Hz = 0x0B, /* @800Hz (low power) */ + LIS2DUXS12_TRIG_PIN = 0x0E, /* Single-shot high latency by INT2 */ + LIS2DUXS12_TRIG_SW = 0x0F, /* Single-shot high latency by IF */ + LIS2DUXS12_6Hz_HP = 0x14, /* @6Hz (high performance) */ + LIS2DUXS12_12Hz5_HP = 0x15, /* @12Hz5 (high performance) */ + LIS2DUXS12_25Hz_HP = 0x16, /* @25Hz (high performance ) */ + LIS2DUXS12_50Hz_HP = 0x17, /* @50Hz (high performance) */ + LIS2DUXS12_100Hz_HP = 0x18, /* @100Hz (high performance) */ + LIS2DUXS12_200Hz_HP = 0x19, /* @200Hz (high performance) */ + LIS2DUXS12_400Hz_HP = 0x1A, /* @400Hz (high performance) */ + LIS2DUXS12_800Hz_HP = 0x1B, /* @800Hz (high performance) */ + } odr; + enum { + LIS2DUXS12_2g = 0, + LIS2DUXS12_4g = 1, + LIS2DUXS12_8g = 2, + LIS2DUXS12_16g = 3, + } fs; + enum { + LIS2DUXS12_ODR_div_2 = 0, + LIS2DUXS12_ODR_div_4 = 1, + LIS2DUXS12_ODR_div_8 = 2, + LIS2DUXS12_ODR_div_16 = 3, + } bw; +} lis2duxs12_md_t; +int32_t lis2duxs12_mode_set(stmdev_ctx_t *ctx, lis2duxs12_md_t *val); +int32_t lis2duxs12_mode_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *val); + +int32_t lis2duxs12_trigger_sw(stmdev_ctx_t *ctx, lis2duxs12_md_t *md); + +typedef struct +{ + uint8_t drdy : 1; + uint8_t timestamp : 1; + uint8_t free_fall : 1; + uint8_t wake_up : 1; + uint8_t wake_up_z : 1; + uint8_t wake_up_y : 1; + uint8_t wake_up_x : 1; + uint8_t single_tap : 1; + uint8_t double_tap : 1; + uint8_t triple_tap : 1; + uint8_t six_d : 1; + uint8_t six_d_xl : 1; + uint8_t six_d_xh : 1; + uint8_t six_d_yl : 1; + uint8_t six_d_yh : 1; + uint8_t six_d_zl : 1; + uint8_t six_d_zh : 1; + uint8_t sleep_change : 1; + uint8_t sleep_state : 1; + uint8_t tilt : 1; + uint8_t fifo_bdr : 1; + uint8_t fifo_full : 1; + uint8_t fifo_ovr : 1; + uint8_t fifo_th : 1; +} lis2duxs12_all_sources_t; +int32_t lis2duxs12_all_sources_get(stmdev_ctx_t *ctx, lis2duxs12_all_sources_t *val); + +typedef struct { + float_t mg[3]; + int16_t raw[3]; +} lis2duxs12_xl_data_t; +int32_t lis2duxs12_xl_data_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *md, + lis2duxs12_xl_data_t *data); + +typedef struct { + struct { + float_t deg_c; + int16_t raw; + }heat; +} lis2duxs12_outt_data_t; +int32_t lis2duxs12_outt_data_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *md, + lis2duxs12_outt_data_t *data); + +typedef struct { + int16_t ah_qvar; +} lis2duxs12_ah_qvar_data_t; +int32_t lis2duxs12_ah_qvar_data_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *md, + lis2duxs12_ah_qvar_data_t *data); + +typedef enum +{ + LIS2DUXS12_XL_ST_DISABLE = 0x0, + LIS2DUXS12_XL_ST_POSITIVE = 0x1, + LIS2DUXS12_XL_ST_NEGATIVE = 0x2, +} lis2duxs12_xl_self_test_t; +int32_t lis2duxs12_self_test_sign_set(stmdev_ctx_t *ctx, lis2duxs12_xl_self_test_t val); +int32_t lis2duxs12_self_test_start(stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2duxs12_self_test_stop(stmdev_ctx_t *ctx); + +int32_t lis2duxs12_enter_deep_power_down(stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2duxs12_exit_deep_power_down(stmdev_ctx_t *ctx); + +typedef struct { + enum { + LIS2DUXS12_I3C_BUS_AVAIL_TIME_20US = 0x0, + LIS2DUXS12_I3C_BUS_AVAIL_TIME_50US = 0x1, + LIS2DUXS12_I3C_BUS_AVAIL_TIME_1MS = 0x2, + LIS2DUXS12_I3C_BUS_AVAIL_TIME_25MS = 0x3, + } bus_act_sel; + uint8_t asf_on : 1; + uint8_t drstdaa_en : 1; +} lis2duxs12_i3c_cfg_t; +int32_t lis2duxs12_i3c_configure_set(stmdev_ctx_t *ctx, lis2duxs12_i3c_cfg_t *val); +int32_t lis2duxs12_i3c_configure_get(stmdev_ctx_t *ctx, lis2duxs12_i3c_cfg_t *val); + +typedef enum +{ + LIS2DUXS12_MAIN_MEM_BANK = 0x0, + LIS2DUXS12_EMBED_FUNC_MEM_BANK = 0x1, +} lis2duxs12_mem_bank_t; +int32_t lis2duxs12_mem_bank_set(stmdev_ctx_t *ctx, lis2duxs12_mem_bank_t val); +int32_t lis2duxs12_mem_bank_get(stmdev_ctx_t *ctx, lis2duxs12_mem_bank_t *val); + +int32_t lis2duxs12_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); +int32_t lis2duxs12_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); + +typedef struct { + uint8_t sdo_pull_up : 1; /* 1 = pull up enable */ + uint8_t sda_pull_up : 1; /* 1 = pull up enable */ + uint8_t cs_pull_up : 1; /* 1 = pull up enable */ + uint8_t int1_int2_push_pull : 1; /* 1 = push-pull / 0 = open-drain*/ + uint8_t int1_pull_down : 1; /* 1 = pull-down always disabled (0=auto) */ + uint8_t int2_pull_down : 1; /* 1 = pull-down always disabled (0=auto) */ +} lis2duxs12_pin_conf_t; +int32_t lis2duxs12_pin_conf_set(stmdev_ctx_t *ctx, lis2duxs12_pin_conf_t *val); +int32_t lis2duxs12_pin_conf_get(stmdev_ctx_t *ctx, lis2duxs12_pin_conf_t *val); + +typedef enum +{ + LIS2DUXS12_ACTIVE_HIGH = 0x0, + LIS2DUXS12_ACTIVE_LOW = 0x1, +} lis2duxs12_int_pin_polarity_t; +int32_t lis2duxs12_int_pin_polarity_set(stmdev_ctx_t *ctx, lis2duxs12_int_pin_polarity_t val); +int32_t lis2duxs12_int_pin_polarity_get(stmdev_ctx_t *ctx, lis2duxs12_int_pin_polarity_t *val); + +typedef enum +{ + LIS2DUXS12_SPI_4_WIRE = 0x0, /* SPI 4 wires */ + LIS2DUXS12_SPI_3_WIRE = 0x1, /* SPI 3 wires */ +} lis2duxs12_spi_mode; +int32_t lis2duxs12_spi_mode_set(stmdev_ctx_t *ctx, lis2duxs12_spi_mode val); +int32_t lis2duxs12_spi_mode_get(stmdev_ctx_t *ctx, lis2duxs12_spi_mode *val); + +typedef struct { + uint8_t int_on_res : 1; /* Interrupt on RES pin */ + uint8_t drdy : 1; /* Accelerometer data ready */ + uint8_t boot : 1; /* Restoring calibration parameters */ + uint8_t fifo_th : 1; /* FIFO threshold reached */ + uint8_t fifo_ovr : 1; /* FIFO overrun */ + uint8_t fifo_full : 1; /* FIFO full */ + uint8_t free_fall : 1; /* free fall event */ + uint8_t six_d : 1; /* orientation change (6D/4D detection) */ + uint8_t tap : 1; /* all tap event */ + uint8_t wake_up : 1; /* wake up event */ + uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ + uint8_t emb_function : 1; /* Embedded Function */ + uint8_t timestamp : 1; /* Timestamp */ +} lis2duxs12_pin_int_route_t; +int32_t lis2duxs12_pin_int1_route_set(stmdev_ctx_t *ctx, + lis2duxs12_pin_int_route_t *val); +int32_t lis2duxs12_pin_int1_route_get(stmdev_ctx_t *ctx, + lis2duxs12_pin_int_route_t *val); +int32_t lis2duxs12_pin_int2_route_set(stmdev_ctx_t *ctx, + lis2duxs12_pin_int_route_t *val); +int32_t lis2duxs12_pin_int2_route_get(stmdev_ctx_t *ctx, + lis2duxs12_pin_int_route_t *val); + +typedef struct { + uint8_t step_det : 1; /* route step detection event on INT pad */ + uint8_t tilt : 1; /* route tilt event on INT pad */ + uint8_t sig_mot : 1; /* route significant motion event on INT pad */ + uint8_t fsm_lc : 1; /* route FSM long counter event on INT pad */ +} lis2duxs12_emb_pin_int_route_t; +int32_t lis2duxs12_emb_pin_int1_route_set(stmdev_ctx_t *ctx, + lis2duxs12_emb_pin_int_route_t *val); +int32_t lis2duxs12_emb_pin_int1_route_get(stmdev_ctx_t *ctx, + lis2duxs12_emb_pin_int_route_t *val); +int32_t lis2duxs12_emb_pin_int2_route_set(stmdev_ctx_t *ctx, + lis2duxs12_emb_pin_int_route_t *val); +int32_t lis2duxs12_emb_pin_int2_route_get(stmdev_ctx_t *ctx, + lis2duxs12_emb_pin_int_route_t *val); + +typedef struct { + enum int_cfg + { + LIS2DUXS12_INT_DISABLED = 0x0, + LIS2DUXS12_INT_LEVEL = 0x1, + LIS2DUXS12_INT_LATCHED = 0x2, + } int_cfg; + uint8_t sleep_status_on_int : 1; /* route sleep_status on interrupt */ + uint8_t dis_rst_lir_all_int : 1; /* disable LIR reset when reading ALL_INT_SRC */ +} lis2duxs12_int_config_t; +int32_t lis2duxs12_int_config_set(stmdev_ctx_t *ctx, lis2duxs12_int_config_t *val); +int32_t lis2duxs12_int_config_get(stmdev_ctx_t *ctx, lis2duxs12_int_config_t *val); + +typedef enum +{ + LIS2DUXS12_EMBEDDED_INT_LEVEL = 0x0, + LIS2DUXS12_EMBEDDED_INT_LATCHED = 0x1, +} lis2duxs12_embedded_int_config_t; +int32_t lis2duxs12_embedded_int_config_set(stmdev_ctx_t *ctx, lis2duxs12_embedded_int_config_t val); +int32_t lis2duxs12_embedded_int_config_get(stmdev_ctx_t *ctx, lis2duxs12_embedded_int_config_t *val); + +typedef struct { + enum operation + { + LIS2DUXS12_BYPASS_MODE = 0x0, + LIS2DUXS12_FIFO_MODE = 0x1, + LIS2DUXS12_STREAM_TO_FIFO_MODE = 0x3, + LIS2DUXS12_BYPASS_TO_STREAM_MODE = 0x4, + LIS2DUXS12_STREAM_MODE = 0x6, + LIS2DUXS12_BYPASS_TO_FIFO_MODE = 0x7, + LIS2DUXS12_FIFO_OFF = 0x8, + } operation; + enum store { + LIS2DUXS12_FIFO_1X = 0, + LIS2DUXS12_FIFO_2X = 1, + } store; + uint8_t xl_only : 1; /* when set to 1, only XL samples (16-bit) are stored in FIFO */ + uint8_t watermark : 7; /* (0 disable) max 127 @16bit, even and max 256 @8bit.*/ + uint8_t cfg_change_in_fifo : 1; + struct { + enum dec_ts + { + LIS2DUXS12_DEC_TS_OFF = 0x0, + LIS2DUXS12_DEC_TS_1 = 0x1, + LIS2DUXS12_DEC_TS_8 = 0x2, + LIS2DUXS12_DEC_TS_32 = 0x3, + } dec_ts; /* decimation for timestamp batching*/ + enum bdr_xl + { + LIS2DUXS12_BDR_XL_ODR = 0x0, + LIS2DUXS12_BDR_XL_ODR_DIV_2 = 0x1, + LIS2DUXS12_BDR_XL_ODR_DIV_4 = 0x2, + LIS2DUXS12_BDR_XL_ODR_DIV_8 = 0x3, + LIS2DUXS12_BDR_XL_ODR_DIV_16 = 0x4, + LIS2DUXS12_BDR_XL_ODR_DIV_32 = 0x5, + LIS2DUXS12_BDR_XL_ODR_DIV_64 = 0x6, + LIS2DUXS12_BDR_XL_ODR_OFF = 0x7, + } bdr_xl; /* accelerometer batch data rate*/ + } batch; +} lis2duxs12_fifo_mode_t; +int32_t lis2duxs12_fifo_mode_set(stmdev_ctx_t *ctx, lis2duxs12_fifo_mode_t val); +int32_t lis2duxs12_fifo_mode_get(stmdev_ctx_t *ctx, lis2duxs12_fifo_mode_t *val); + +int32_t lis2duxs12_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lis2duxs12_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LIS2DUXS12_FIFO_EMPTY = 0x0, + LIS2DUXS12_XL_TEMP_TAG = 0x2, + LIS2DUXS12_XL_ONLY_2X_TAG = 0x3, + LIS2DUXS12_TIMESTAMP_TAG = 0x4, + LIS2DUXS12_STEP_COUNTER_TAG = 0x12, + LIS2DUXS12_MLC_RESULT_TAG = 0x1A, + LIS2DUXS12_MLC_FILTER_TAG = 0x1B, + LIS2DUXS12_MLC_FEATURE = 0x1C, + LIS2DUXS12_FSM_RESULT_TAG = 0x1D, + LIS2DUXS12_XL_ONLY_2X_TAG_2ND = 0x1E, + LIS2DUXS12_XL_AND_QVAR = 0x1F, +} lis2duxs12_fifo_sensor_tag_t; +int32_t lis2duxs12_fifo_sensor_tag_get(stmdev_ctx_t *ctx, + lis2duxs12_fifo_sensor_tag_t *val); + +int32_t lis2duxs12_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff); + +typedef struct { + uint8_t tag; + struct { + float_t mg[3]; + int16_t raw[3]; + }xl[2]; + int16_t ah_qvar; + struct { + float_t deg_c; + int16_t raw; + }heat; + struct pedo { + uint32_t steps; + uint32_t timestamp; + } pedo; + struct cfg_chg { + uint8_t cfg_change : 1; /* 1 if ODR/BDR configuration is changed */ + uint8_t odr : 4; /* ODR */ + uint8_t bw : 2; /* BW */ + uint8_t lp_hp : 1; /* Power (LP == 0/HP == 1) */ + uint8_t qvar_en : 1; /* QVAR is enabled */ + uint8_t fs : 2; /* FS */ + uint8_t dec_ts : 2; /* Timestamp decimator value */ + uint8_t odr_xl_batch : 1; /* Accelerometer ODR is batched */ + uint32_t timestamp; + } cfg_chg; +} lis2duxs12_fifo_data_t; +int32_t lis2duxs12_fifo_data_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *md, + lis2duxs12_fifo_mode_t *fmd, + lis2duxs12_fifo_data_t *data); + +typedef struct +{ + uint8_t ah_qvar_en : 1; + uint8_t ah_qvar_notch_en : 1; + enum { + LIS2DUXS12_NOTCH_50HZ = 0x0, + LIS2DUXS12_NOTCH_60HZ = 0x1, + } ah_qvar_notch; + enum { + LIS2DUXS12_520MOhm = 0x0, + LIS2DUXS12_175MOhm = 0x1, + LIS2DUXS12_310MOhm = 0x2, + LIS2DUXS12_75MOhm = 0x3, + } ah_qvar_zin; + enum { + LIS2DUXS12_GAIN_0_5 = 0x0, + LIS2DUXS12_GAIN_1 = 0x1, + LIS2DUXS12_GAIN_2 = 0x2, + LIS2DUXS12_GAIN_4 = 0x3, + } ah_qvar_gain; +} lis2duxs12_ah_qvar_mode_t; +int32_t lis2duxs12_ah_qvar_mode_set(stmdev_ctx_t *ctx, + lis2duxs12_ah_qvar_mode_t val); +int32_t lis2duxs12_ah_qvar_mode_get(stmdev_ctx_t *ctx, + lis2duxs12_ah_qvar_mode_t *val); + +typedef struct +{ + uint8_t false_step_rej : 1; + uint8_t step_counter_enable : 1; + uint8_t step_counter_in_fifo : 1; +} lis2duxs12_stpcnt_mode_t; +int32_t lis2duxs12_stpcnt_mode_set(stmdev_ctx_t *ctx, lis2duxs12_stpcnt_mode_t val); +int32_t lis2duxs12_stpcnt_mode_get(stmdev_ctx_t *ctx, lis2duxs12_stpcnt_mode_t *val); + +int32_t lis2duxs12_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val); + +int32_t lis2duxs12_stpcnt_rst_step_set(stmdev_ctx_t *ctx); + +int32_t lis2duxs12_stpcnt_debounce_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2duxs12_stpcnt_debounce_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lis2duxs12_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val); +int32_t lis2duxs12_stpcnt_period_get(stmdev_ctx_t *ctx, uint16_t *val); + +int32_t lis2duxs12_tilt_mode_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2duxs12_tilt_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2duxs12_sigmot_mode_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2duxs12_sigmot_mode_get(stmdev_ctx_t *ctx, uint8_t *val); + + +int32_t lis2duxs12_ff_duration_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2duxs12_ff_duration_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LIS2DUXS12_156_mg = 0x0, + LIS2DUXS12_219_mg = 0x1, + LIS2DUXS12_250_mg = 0x2, + LIS2DUXS12_312_mg = 0x3, + LIS2DUXS12_344_mg = 0x4, + LIS2DUXS12_406_mg = 0x5, + LIS2DUXS12_469_mg = 0x6, + LIS2DUXS12_500_mg = 0x7, +} lis2duxs12_ff_thresholds_t; +int32_t lis2duxs12_ff_thresholds_set(stmdev_ctx_t *ctx, lis2duxs12_ff_thresholds_t val); +int32_t lis2duxs12_ff_thresholds_get(stmdev_ctx_t *ctx, lis2duxs12_ff_thresholds_t *val); + +typedef struct { + enum threshold + { + LIS2DUXS12_DEG_80 = 0x0, + LIS2DUXS12_DEG_70 = 0x1, + LIS2DUXS12_DEG_60 = 0x2, + LIS2DUXS12_DEG_50 = 0x3, + } threshold; + enum mode + { + LIS2DUXS12_6D = 0x0, + LIS2DUXS12_4D = 0x1, + } mode; +} lis2duxs12_sixd_config_t; + +int32_t lis2duxs12_sixd_config_set(stmdev_ctx_t *ctx, lis2duxs12_sixd_config_t val); +int32_t lis2duxs12_sixd_config_get(stmdev_ctx_t *ctx, lis2duxs12_sixd_config_t *val); + +typedef struct { + enum wake_dur + { + LIS2DUXS12_0_ODR = 0x000, /* 0 ODR time */ + LIS2DUXS12_1_ODR = 0x001, /* 1 ODR time */ + LIS2DUXS12_2_ODR = 0x002, /* 2 ODR time */ + LIS2DUXS12_3_ODR = 0x100, /* 3 ODR time */ + LIS2DUXS12_7_ODR = 0x101, /* 7 ODR time */ + LIS2DUXS12_11_ODR = 0x102, /* 11 ODR time */ + LIS2DUXS12_15_ODR = 0x103, /* 15 ODR time */ + } wake_dur; + uint8_t sleep_dur : 4; /* 1 LSB == 512 ODR time */ + uint8_t wake_ths : 7; /* wakeup threshold */ + uint8_t wake_ths_weight : 1; /* 0: 1LSB = FS_XL/2^6, 1: 1LSB = FS_XL/2^8 */ + enum wake_enable + { + LIS2DUXS12_SLEEP_OFF = 0, + LIS2DUXS12_SLEEP_ON = 1, + } wake_enable; + enum inact_odr + { + LIS2DUXS12_ODR_NO_CHANGE = 0, /* no odr change during inactivity state */ + LIS2DUXS12_ODR_1_6_HZ = 1, /* set odr to 1.6Hz during inactivity state */ + LIS2DUXS12_ODR_3_HZ = 1, /* set odr to 3Hz during inactivity state */ + LIS2DUXS12_ODR_25_HZ = 1, /* set odr to 25Hz during inactivity state */ + } inact_odr; +} lis2duxs12_wakeup_config_t; + +int32_t lis2duxs12_wakeup_config_set(stmdev_ctx_t *ctx, lis2duxs12_wakeup_config_t val); +int32_t lis2duxs12_wakeup_config_get(stmdev_ctx_t *ctx, lis2duxs12_wakeup_config_t *val); + +typedef struct { + enum axis + { + LIS2DUXS12_TAP_NONE = 0x0, /* No axis */ + LIS2DUXS12_TAP_ON_X = 0x1, /* Detect tap on X axis */ + LIS2DUXS12_TAP_ON_Y = 0x2, /* Detect tap on Y axis */ + LIS2DUXS12_TAP_ON_Z = 0x3, /* Detect tap on Z axis */ + } axis; + uint8_t inverted_peak_time : 5; /* 1 LSB == 1 sample */ + uint8_t pre_still_ths : 4; /* 1 LSB == 62.5 mg */ + uint8_t post_still_ths : 4; /* 1 LSB == 62.5 mg */ + uint8_t post_still_time : 6; /* samples num during stationary condition */ + uint8_t shock_wait_time : 6; /* samples num during shock condition */ + uint8_t latency : 4; /* samples max num between taps */ + uint8_t wait_end_latency : 1; /* wait end of latency time to generate tap events */ + uint8_t peak_ths : 6; /* 1 LSB == 62.5 mg */ + uint8_t rebound : 5; /* samples num during rebound condition */ + uint8_t pre_still_start : 4; /* pre still start */ + uint8_t pre_still_n : 4; /* pre still n */ + uint8_t single_tap_on : 1; /* enable single tap */ + uint8_t double_tap_on : 1; /* enable double tap */ + uint8_t triple_tap_on : 1; /* enable triple tap */ +} lis2duxs12_tap_config_t; + +int32_t lis2duxs12_tap_config_set(stmdev_ctx_t *ctx, lis2duxs12_tap_config_t val); +int32_t lis2duxs12_tap_config_get(stmdev_ctx_t *ctx, lis2duxs12_tap_config_t *val); + +int32_t lis2duxs12_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2duxs12_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lis2duxs12_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); + +int32_t lis2duxs12_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t lis2duxs12_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2duxs12_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + lis2duxs12_fsm_enable_t fsm_enable; +} lis2duxs12_emb_fsm_enable_t; +int32_t lis2duxs12_fsm_enable_set(stmdev_ctx_t *ctx, + lis2duxs12_emb_fsm_enable_t *val); +int32_t lis2duxs12_fsm_enable_get(stmdev_ctx_t *ctx, + lis2duxs12_emb_fsm_enable_t *val); + +int32_t lis2duxs12_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val); +int32_t lis2duxs12_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val); + +int32_t lis2duxs12_fsm_status_get(stmdev_ctx_t *ctx, + lis2duxs12_fsm_status_mainpage_t *val); +int32_t lis2duxs12_fsm_out_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LIS2DUXS12_ODR_FSM_12Hz5 = 0, + LIS2DUXS12_ODR_FSM_25Hz = 1, + LIS2DUXS12_ODR_FSM_50Hz = 2, + LIS2DUXS12_ODR_FSM_100Hz = 3, + LIS2DUXS12_ODR_FSM_200Hz = 4, + LIS2DUXS12_ODR_FSM_400Hz = 5, + LIS2DUXS12_ODR_FSM_800Hz = 6, +} lis2duxs12_fsm_val_odr_t; +int32_t lis2duxs12_fsm_data_rate_set(stmdev_ctx_t *ctx, + lis2duxs12_fsm_val_odr_t val); +int32_t lis2duxs12_fsm_data_rate_get(stmdev_ctx_t *ctx, + lis2duxs12_fsm_val_odr_t *val); + +int32_t lis2duxs12_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2duxs12_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lis2duxs12_long_cnt_int_value_set(stmdev_ctx_t *ctx, + uint16_t val); +int32_t lis2duxs12_long_cnt_int_value_get(stmdev_ctx_t *ctx, + uint16_t *val); + +int32_t lis2duxs12_fsm_number_of_programs_set(stmdev_ctx_t *ctx, + uint8_t *buff); +int32_t lis2duxs12_fsm_number_of_programs_get(stmdev_ctx_t *ctx, + uint8_t *buff); + +int32_t lis2duxs12_fsm_start_address_set(stmdev_ctx_t *ctx, + uint16_t val); +int32_t lis2duxs12_fsm_start_address_get(stmdev_ctx_t *ctx, + uint16_t *val); + +typedef enum +{ + LIS2DUXS12_MLC_OFF = 0, + LIS2DUXS12_MLC_ON = 1, + LIS2DUXS12_MLC_ON_BEFORE_FSM = 2, +} lis2duxs12_mlc_mode_t; +int32_t lis2duxs12_mlc_set(stmdev_ctx_t *ctx, lis2duxs12_mlc_mode_t val); +int32_t lis2duxs12_mlc_get(stmdev_ctx_t *ctx, lis2duxs12_mlc_mode_t *val); + +int32_t lis2duxs12_mlc_status_get(stmdev_ctx_t *ctx, + lis2duxs12_mlc_status_mainpage_t *val); + +int32_t lis2duxs12_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff); + +typedef enum +{ + LIS2DUXS12_ODR_PRGS_12Hz5 = 0, + LIS2DUXS12_ODR_PRGS_25Hz = 1, + LIS2DUXS12_ODR_PRGS_50Hz = 2, + LIS2DUXS12_ODR_PRGS_100Hz = 3, + LIS2DUXS12_ODR_PRGS_200Hz = 4, +} lis2duxs12_mlc_odr_val_t; +int32_t lis2duxs12_mlc_data_rate_set(stmdev_ctx_t *ctx, + lis2duxs12_mlc_odr_val_t val); +int32_t lis2duxs12_mlc_data_rate_get(stmdev_ctx_t *ctx, + lis2duxs12_mlc_odr_val_t *val); + +#ifdef __cplusplus +} +#endif + +#endif /* LIS2DUXS12_REGS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.c b/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.c index dbbc03088c1e3c3b92d1649cf87197a331e78186..fa651dd66d4fdbba80d32daeaec0ad7421eea209 100644 --- a/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.c +++ b/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lis2dw12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t lis2dw12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lis2dw12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.h b/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.h index 21e2185574580d635027837248166e65921d2dcf..ef1d637cf3dc81dab48f8685ea3ba8529fd553af 100644 --- a/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.h +++ b/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -653,6 +656,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lis2dw12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.c b/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.c index 081caf097fad2ccbe496d4caa29a2e2620323122..4d04ce5069c0e3da82503d5f1c96c0978cf5fa77 100644 --- a/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.c +++ b/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.c @@ -45,9 +45,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2hh12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lis2hh12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -66,9 +66,9 @@ int32_t lis2hh12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2hh12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lis2hh12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.h b/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.h index f7cf214a15bf1831367ee82813e46d68d6a8e8a7..9b35afcf7664b45efd04517a712bcbabb696855c 100644 --- a/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.h +++ b/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -569,6 +572,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lis2hh12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.c b/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.c index 02ebd616d6c9bbe82ed73b2520149d7c849aa4d1..6fcd19efe038620597c2f5653cf4e11bc2c66c8d 100644 --- a/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.c +++ b/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lis2mdl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t lis2mdl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lis2mdl_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.h b/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.h index c50307dcdb7e23f89f9f062aa2f3994fe2ceacda..2d298fae860ffe3fc51db3c3bcd7e583a7902867 100644 --- a/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.h +++ b/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -355,6 +358,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lis2mdl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.c b/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.c index cd4e5aa74cb0e8a3739fd28d575d444aef9bcf2c..e0f791cc3e0cd37b5aa3be16622d5776ba155f40 100644 --- a/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.c +++ b/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lis331dlh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t lis331dlh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lis331dlh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.h b/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.h index 18d4e6516fa86e689efc1e655a717dd3000b7d1a..ed1fab2d260eea0729830d36582a2bd78571868b 100644 --- a/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.h +++ b/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -481,6 +484,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lis331dlh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.c b/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.c index 8a64723cf747499ece1784482913339a1a50b979..cce50368583b6c4d0ee79a253b9fe45101e247e8 100644 --- a/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.c +++ b/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.c @@ -46,8 +46,8 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, - uint16_t len) +int32_t __weak lis3de_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, + uint16_t len) { int32_t ret; @@ -66,9 +66,9 @@ int32_t lis3de_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lis3de_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.h b/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.h index 8966d95819e7458ad98ec6e6e3470abf6af4ba54..938d9bbe836a111cd987eb160ee88dc73802afdd 100644 --- a/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.h +++ b/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -700,6 +703,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lis3de_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); int32_t lis3de_write_reg(stmdev_ctx_t *ctx, uint8_t reg, diff --git a/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.c b/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.c index c2a6ce9140bcddc6d5ae49778d5decfc0d23ac62..47d2526be8364b894d885e337b98605fdafc624b 100644 --- a/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.c +++ b/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.c @@ -46,8 +46,8 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, - uint16_t len) +int32_t __weak lis3dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, + uint16_t len) { int32_t ret; @@ -66,9 +66,9 @@ int32_t lis3dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lis3dh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.h b/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.h index f8b35575e976a4fb05593c8886dcfe2a69282514..cb8d478dbbf439c5ecbd1f06a180f7afaf8ef993 100644 --- a/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.h +++ b/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -715,6 +718,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lis3dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); int32_t lis3dh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, diff --git a/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.c b/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.c index 85427b5636ca90e3715bceeaa775ba297e2e2bed..9fc7aab4652b497a8606905c8964030891f8af00 100644 --- a/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.c +++ b/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dhh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lis3dhh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t lis3dhh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dhh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lis3dhh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.h b/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.h index ef9efa4876f08773d50dda1bcdcbd831931b63fd..543b6033ed4fd1de7522db4f0182732edd9cc60a 100644 --- a/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.h +++ b/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -357,6 +360,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lis3dhh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/lis3dsh_STdC/driver/lis3dsh_reg.c b/sensor/stmemsc/lis3dsh_STdC/driver/lis3dsh_reg.c index 9bd96a671798c0cd85b822a2631dc8f427a78f6c..c8a9720739883a2fc49cb78aa1b16216d3d07aa9 100644 --- a/sensor/stmemsc/lis3dsh_STdC/driver/lis3dsh_reg.c +++ b/sensor/stmemsc/lis3dsh_STdC/driver/lis3dsh_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dsh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lis3dsh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t lis3dsh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dsh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lis3dsh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lis3dsh_STdC/driver/lis3dsh_reg.h b/sensor/stmemsc/lis3dsh_STdC/driver/lis3dsh_reg.h index 56e1ae913416f3ed990bcee45a5c9b06522ecf3f..0aa1e384b0d7910568034f459f965543372ff1db 100644 --- a/sensor/stmemsc/lis3dsh_STdC/driver/lis3dsh_reg.h +++ b/sensor/stmemsc/lis3dsh_STdC/driver/lis3dsh_reg.h @@ -116,12 +116,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -721,6 +724,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lis3dsh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.c b/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.c index 9344a8b2388203d3e98d7daa05e6193777a0e838..14024fd82e61423da65e9ff98ed85209d7cc44cf 100644 --- a/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.c +++ b/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lis3mdl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t lis3mdl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lis3mdl_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.h b/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.h index 621a209ecc3bedc7cf4ef0754c406f9e960f13d4..f76934af09730374c8bfa63e925e22d0f17ed851 100644 --- a/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.h +++ b/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -372,6 +375,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lis3mdl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/lps22ch_STdC/driver/lps22ch_reg.c b/sensor/stmemsc/lps22ch_STdC/driver/lps22ch_reg.c index ece25095ffecaa22bf0601d932f9554223910fcf..23a1a9760f693d18046ec85f24292240f982be1d 100644 --- a/sensor/stmemsc/lps22ch_STdC/driver/lps22ch_reg.c +++ b/sensor/stmemsc/lps22ch_STdC/driver/lps22ch_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lps22ch_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t lps22ch_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lps22ch_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lps22ch_STdC/driver/lps22ch_reg.h b/sensor/stmemsc/lps22ch_STdC/driver/lps22ch_reg.h index 07ebdb322b705439e6901f558bdb4d9bd75bcaee..aa876c62488f6283e0b6dbbae4b996d2641bfeda 100644 --- a/sensor/stmemsc/lps22ch_STdC/driver/lps22ch_reg.h +++ b/sensor/stmemsc/lps22ch_STdC/driver/lps22ch_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -433,6 +436,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lps22ch_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/lps22df_STdC/driver/lps22df_reg.c b/sensor/stmemsc/lps22df_STdC/driver/lps22df_reg.c index 1bac1389a74264eed0ef84f132aedb503eea9cb2..c9a2336408c03d45ebd06b2f86ca64c58865053b 100644 --- a/sensor/stmemsc/lps22df_STdC/driver/lps22df_reg.c +++ b/sensor/stmemsc/lps22df_STdC/driver/lps22df_reg.c @@ -46,8 +46,8 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22df_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, - uint16_t len) +int32_t __weak lps22df_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, + uint16_t len) { int32_t ret; @@ -65,8 +65,8 @@ int32_t lps22df_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22df_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, - uint16_t len) +int32_t __weak lps22df_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lps22df_STdC/driver/lps22df_reg.h b/sensor/stmemsc/lps22df_STdC/driver/lps22df_reg.h index 0122b90893b93f80456fe44dea3b328886ee281f..696e09e17a655c7cf881bdf121417aaa864402ff 100644 --- a/sensor/stmemsc/lps22df_STdC/driver/lps22df_reg.h +++ b/sensor/stmemsc/lps22df_STdC/driver/lps22df_reg.h @@ -109,14 +109,17 @@ typedef struct * */ -typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -487,6 +490,19 @@ typedef union uint8_t byte; } lis2du12_reg_t; +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lps22df_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); int32_t lps22df_write_reg(stmdev_ctx_t *ctx, uint8_t reg, diff --git a/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.c b/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.c index 842a88ee772df88f7e89ccf6f1788f5412a501cd..eaef600ebc21e0a51cfcb9362a101981e7740f98 100644 --- a/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.c +++ b/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.c @@ -45,9 +45,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hb_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lps22hb_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -66,9 +66,9 @@ int32_t lps22hb_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hb_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lps22hb_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.h b/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.h index 4a7f08ab4c77c4cc9b61c201f49abfa660da8662..b100480aaf04f40613cf5c29d01a7de9d6bb9afd 100644 --- a/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.h +++ b/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -393,6 +396,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lps22hb_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.c b/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.c index 97c8a1cc8e6474f1a4dd55bc78383a5621d86c11..c9cb90d3a038dbc8c5c4f1cadede0502a79b9253 100644 --- a/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.c +++ b/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lps22hh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t lps22hh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lps22hh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -459,7 +459,7 @@ int32_t lps22hh_data_rate_get(stmdev_ctx_t *ctx, lps22hh_odr_t *val) /** * @brief The Reference pressure value is a 16-bit data - * expressed as 2’s complement. The value is used + * expressed as 2's complement. The value is used * when AUTOZERO or AUTORIFP function is enabled.[set] * * @param ctx read / write interface definitions @@ -481,7 +481,7 @@ int32_t lps22hh_pressure_ref_set(stmdev_ctx_t *ctx, int16_t val) /** * @brief The Reference pressure value is a 16-bit - * data expressed as 2’s complement. + * data expressed as 2's complement. * The value is used when AUTOZERO or AUTORIFP * function is enabled.[get] * @@ -663,9 +663,9 @@ int32_t lps22hh_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff) uint8_t reg[3]; ret = lps22hh_read_reg(ctx, LPS22HH_PRESS_OUT_XL, reg, 3); *buff = reg[2]; - *buff = (*buff * 256) + reg[1]; - *buff = (*buff * 256) + reg[0]; - *buff *= 256; + *buff = (*buff * 256U) + reg[1]; + *buff = (*buff * 256U) + reg[0]; + *buff *= 256U; return ret; } @@ -681,11 +681,11 @@ int32_t lps22hh_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff) int32_t lps22hh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff) { int32_t ret; - uint8_t reg[2]; + ret = lps22hh_read_reg(ctx, LPS22HH_TEMP_OUT_L, reg, 2); - *buff = reg[1]; - *buff = (*buff * 256) + reg[0]; + *buff = (int16_t)reg[1]; + *buff = (*buff * 256) + (int16_t)reg[0]; return ret; } @@ -706,9 +706,9 @@ int32_t lps22hh_fifo_pressure_raw_get(stmdev_ctx_t *ctx, uint8_t reg[3]; ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_DATA_OUT_PRESS_XL, reg, 3); *buff = reg[2]; - *buff = (*buff * 256) + reg[1]; - *buff = (*buff * 256) + reg[0]; - *buff *= 256; + *buff = (*buff * 256U) + reg[1]; + *buff = (*buff * 256U) + reg[0]; + *buff *= 256U; return ret; } @@ -728,8 +728,8 @@ int32_t lps22hh_fifo_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t reg[2]; ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_DATA_OUT_TEMP_L, reg, 2); - *buff = reg[1]; - *buff = (*buff * 256) + reg[0]; + *buff = (int16_t)reg[1]; + *buff = (*buff * 256) + (int16_t)reg[0]; return ret; } @@ -1474,37 +1474,52 @@ int32_t lps22hh_pin_polarity_get(stmdev_ctx_t *ctx, } /** - * @brief Select the signal that need to route on int pad.[set] + * @brief Route interrupt signals on int1 pin.[set] * - * @param ctx read / write interface definitions - * @param val registers CTRL_REG3 - * @retval interface status (MANDATORY: return 0 -> no Error) + * @param ctx communication interface handler.(ptr) + * @param val the signals to route on int1 pin.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) * */ int32_t lps22hh_pin_int_route_set(stmdev_ctx_t *ctx, - lps22hh_ctrl_reg3_t *val) + lps22hh_pin_int_route_t *val) { + lps22hh_ctrl_reg3_t ctrl_reg3; int32_t ret; - ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t *) val, 1); + ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret == 0) + { + ctrl_reg3.drdy = val->drdy_pres; + ctrl_reg3.int_f_wtm = val->fifo_th; + ctrl_reg3.int_f_ovr = val->fifo_ovr; + ctrl_reg3.int_f_full = val->fifo_full; + ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + } return ret; } /** - * @brief Select the signal that need to route on int pad.[get] + * @brief Route interrupt signals on int1 pin.[get] * - * @param ctx read / write interface definitions - * @param val registers CTRL_REG3 - * @retval interface status (MANDATORY: return 0 -> no Error) + * @param ctx communication interface handler.(ptr) + * @param val the signals that are routed on int1 pin.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) * */ int32_t lps22hh_pin_int_route_get(stmdev_ctx_t *ctx, - lps22hh_ctrl_reg3_t *val) + lps22hh_pin_int_route_t *val) { + lps22hh_ctrl_reg3_t ctrl_reg3; int32_t ret; - ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t *) val, 1); + ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + + val->drdy_pres = ctrl_reg3.drdy; + val->fifo_th = ctrl_reg3.int_f_wtm; + val->fifo_ovr = ctrl_reg3.int_f_ovr; + val->fifo_full = ctrl_reg3.int_f_full; return ret; } @@ -1838,15 +1853,15 @@ int32_t lps22hh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) * @brief FIFO stored data level.[get] * * @param ctx read / write interface definitions - * @param buff buffer that stores data read + * @param num buffer that stores data read * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lps22hh_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *num) { int32_t ret; - ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS1, buff, 1); + ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS1, num, 1); return ret; } @@ -1926,137 +1941,6 @@ int32_t lps22hh_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) return ret; } -/** - * @brief FIFO overrun interrupt on INT_DRDY pin.[set] - * - * @param stmdev_ctx_t *ctx: read / write interface definitions - * @param uint8_t val: change the values of f_ovr in reg CTRL_REG3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lps22hh_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps22hh_ctrl_reg3_t reg; - int32_t ret; - - ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t *)®, 1); - - if (ret == 0) - { - reg.int_f_ovr = val; - ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t *)®, 1); - } - - return ret; -} - -/** - * @brief FIFO overrun interrupt on INT_DRDY pin.[get] - * - * @param stmdev_ctx_t *ctx: read / write interface definitions - * @param uint8_t: change the values of f_ovr in reg CTRL_REG3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lps22hh_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps22hh_ctrl_reg3_t reg; - int32_t ret; - - ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t *)®, 1); - *val = reg.int_f_ovr; - - return ret; -} - -/** - * @brief FIFO watermark status on INT_DRDY pin.[set] - * - * @param stmdev_ctx_t *ctx: read / write interface definitions - * @param uint8_t val: change the values of f_fth in reg CTRL_REG3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lps22hh_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, - uint8_t val) -{ - lps22hh_ctrl_reg3_t reg; - int32_t ret; - - ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t *)®, 1); - - if (ret == 0) - { - reg.int_f_wtm = val; - ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t *)®, 1); - } - - return ret; -} - -/** - * @brief FIFO watermark status on INT_DRDY pin.[get] - * - * @param lps22hb_ctx_t *ctx: read / write interface definitions - * @param uint8_t: change the values of f_fth in reg CTRL_REG3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lps22hh_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, - uint8_t *val) -{ - lps22hh_ctrl_reg3_t reg; - int32_t ret; - - ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t *)®, 1); - *val = reg.int_f_wtm; - - return ret; -} - -/** - * @brief FIFO full flag on INT_DRDY pin.[set] - * - * @param stmdev_ctx_t *ctx: read / write interface definitions - * @param uint8_t val: change the values of f_fss5 in reg CTRL_REG3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lps22hh_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps22hh_ctrl_reg3_t reg; - int32_t ret; - - ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t *)®, 1); - - if (ret == 0) - { - reg.int_f_full = val; - ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t *)®, 1); - } - - return ret; -} - -/** - * @brief FIFO full flag on INT_DRDY pin.[get] - * - * @param stmdev_ctx_t *ctx: read / write interface definitions - * @param uint8_t: change the values of f_fss5 in reg CTRL_REG3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lps22hh_fifo_full_on_int_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps22hh_ctrl_reg3_t reg; - int32_t ret; - - ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t *)®, 1); - *val = reg.int_f_full; - - return ret; -} - /** * @} * diff --git a/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.h b/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.h index dfc2a9a5f094e9021195f66439305754da54abef..7cf084687140de5bafc04576dd8ff872559c4cf5 100644 --- a/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.h +++ b/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.h @@ -50,7 +50,7 @@ extern "C" { /** if _BYTE_ORDER is not defined, choose the endianness of your architecture * by uncommenting the define which fits your platform endianness */ -//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN +/* #define DRV_BYTE_ORDER DRV_BIG_ENDIAN */ #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN #else /* defined __BYTE_ORDER__ */ @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -433,12 +436,24 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ int32_t lps22hh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len); + uint8_t *data, + uint16_t len); int32_t lps22hh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len); + uint8_t *data, + uint16_t len); float_t lps22hh_from_lsb_to_hpa(uint32_t lsb); @@ -606,10 +621,17 @@ int32_t lps22hh_pin_polarity_set(stmdev_ctx_t *ctx, int32_t lps22hh_pin_polarity_get(stmdev_ctx_t *ctx, lps22hh_int_h_l_t *val); +typedef struct +{ + uint8_t drdy_pres : 1; /* Pressure data ready */ + uint8_t fifo_th : 1; /* FIFO threshold reached */ + uint8_t fifo_ovr : 1; /* FIFO overrun */ + uint8_t fifo_full : 1; /* FIFO full */ +} lps22hh_pin_int_route_t; int32_t lps22hh_pin_int_route_set(stmdev_ctx_t *ctx, - lps22hh_ctrl_reg3_t *val); + lps22hh_pin_int_route_t *val); int32_t lps22hh_pin_int_route_get(stmdev_ctx_t *ctx, - lps22hh_ctrl_reg3_t *val); + lps22hh_pin_int_route_t *val); typedef enum { @@ -647,7 +669,7 @@ int32_t lps22hh_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val); int32_t lps22hh_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); int32_t lps22hh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hh_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lps22hh_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *num); int32_t lps22hh_fifo_src_get(stmdev_ctx_t *ctx, lps22hh_fifo_status2_t *val); @@ -658,17 +680,6 @@ int32_t lps22hh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); int32_t lps22hh_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hh_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22hh_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps22hh_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, - uint8_t val); -int32_t lps22hh_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, - uint8_t *val); - -int32_t lps22hh_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22hh_fifo_full_on_int_get(stmdev_ctx_t *ctx, uint8_t *val); - /** * @} * diff --git a/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.c b/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.c index de9f8b854d62c909efa190aeb50bdb72a6741de9..fbe6925f0ff1888a7330b64daa6005b34500843c 100644 --- a/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.c +++ b/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.c @@ -45,9 +45,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps25hb_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lps25hb_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -66,9 +66,9 @@ int32_t lps25hb_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps25hb_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lps25hb_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.h b/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.h index 2cd69cd010fe0d1e81dc40eccce37070fcab6d05..d21bcdd7736cc19cd1b56e7c052feb633a96b9c8 100644 --- a/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.h +++ b/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.h @@ -112,12 +112,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -393,6 +396,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lps25hb_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/lps27hhtw_STdC/driver/lps27hhtw_reg.c b/sensor/stmemsc/lps27hhtw_STdC/driver/lps27hhtw_reg.c index d3ee18bc4da489970b1b3ed3c797387317db31bc..ed3291d6e0bf24aaa33cc172ae8632bb7228bfe0 100644 --- a/sensor/stmemsc/lps27hhtw_STdC/driver/lps27hhtw_reg.c +++ b/sensor/stmemsc/lps27hhtw_STdC/driver/lps27hhtw_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lps27hhtw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t lps27hhtw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lps27hhtw_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lps27hhtw_STdC/driver/lps27hhtw_reg.h b/sensor/stmemsc/lps27hhtw_STdC/driver/lps27hhtw_reg.h index 0cfab74b6aa01aebfb839c3b534a926c2a23ea40..b4106a942d550b6c0ee28e608c29a02cd3425570 100644 --- a/sensor/stmemsc/lps27hhtw_STdC/driver/lps27hhtw_reg.h +++ b/sensor/stmemsc/lps27hhtw_STdC/driver/lps27hhtw_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -435,6 +438,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lps27hhtw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.c b/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.c index f171bd47601dffed42745cd0203247cb4e438643..74694618238531c0cfd7b3ba33f3af6241b83219 100644 --- a/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.c +++ b/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lps27hhw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t lps27hhw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lps27hhw_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.h b/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.h index 1433d820c737a681e0158e2e7b77013a872e1804..0f40f6410303d1de0d02126c46ebd457811f3a5a 100644 --- a/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.h +++ b/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -435,6 +438,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lps27hhw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/lps28dfw_STdC/driver/lps28dfw_reg.c b/sensor/stmemsc/lps28dfw_STdC/driver/lps28dfw_reg.c index 249197068da774f2090fd3da51736b2be4bde688..67031c6069c23ce68790e01609eb7c9ed32ce35c 100644 --- a/sensor/stmemsc/lps28dfw_STdC/driver/lps28dfw_reg.c +++ b/sensor/stmemsc/lps28dfw_STdC/driver/lps28dfw_reg.c @@ -46,8 +46,8 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps28dfw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, - uint16_t len) +int32_t __weak lps28dfw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, + uint16_t len) { int32_t ret; ret = ctx->read_reg(ctx->handle, reg, data, len); @@ -64,8 +64,8 @@ int32_t lps28dfw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps28dfw_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, - uint16_t len) +int32_t __weak lps28dfw_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, + uint16_t len) { int32_t ret; ret = ctx->write_reg(ctx->handle, reg, data, len); @@ -1045,7 +1045,7 @@ int32_t lps28dfw_int_on_threshold_mode_set(stmdev_ctx_t *ctx, bytecpy(®[1], (uint8_t *)&ths_p_l); bytecpy(®[2], (uint8_t *)&ths_p_h); - ret = lps28dfw_read_reg(ctx, LPS28DFW_INTERRUPT_CFG, reg, 3); + ret = lps28dfw_write_reg(ctx, LPS28DFW_INTERRUPT_CFG, reg, 3); } return ret; } @@ -1118,7 +1118,7 @@ int32_t lps28dfw_reference_mode_set(stmdev_ctx_t *ctx, lps28dfw_ref_md_t *val) interrupt_cfg.reset_az = ((uint8_t)val->apply_ref & 0x02U) >> 1; interrupt_cfg.reset_arp = ((uint8_t)val->apply_ref & 0x02U) >> 1; - ret = lps28dfw_read_reg(ctx, LPS28DFW_INTERRUPT_CFG, + ret = lps28dfw_write_reg(ctx, LPS28DFW_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1); } return ret; diff --git a/sensor/stmemsc/lps28dfw_STdC/driver/lps28dfw_reg.h b/sensor/stmemsc/lps28dfw_STdC/driver/lps28dfw_reg.h index b5ddb372250db0cf1c1a32edb0a15d4234cfd3f3..f38348a9202999026c5ff5232ec8f0fa1f7cf530 100644 --- a/sensor/stmemsc/lps28dfw_STdC/driver/lps28dfw_reg.h +++ b/sensor/stmemsc/lps28dfw_STdC/driver/lps28dfw_reg.h @@ -109,14 +109,17 @@ typedef struct * */ -typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -483,6 +486,19 @@ typedef union uint8_t byte; } lps28dfw_reg_t; +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lps28dfw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); int32_t lps28dfw_write_reg(stmdev_ctx_t *ctx, uint8_t reg, diff --git a/sensor/stmemsc/lps33hw_STdC/driver/lps33hw_reg.c b/sensor/stmemsc/lps33hw_STdC/driver/lps33hw_reg.c index 4f135bbcc27d02674c1914bbbbe20e7f76606c43..820dab4adce95aacf705d550110c0a23624a8bd1 100644 --- a/sensor/stmemsc/lps33hw_STdC/driver/lps33hw_reg.c +++ b/sensor/stmemsc/lps33hw_STdC/driver/lps33hw_reg.c @@ -45,9 +45,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps33hw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lps33hw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -66,9 +66,9 @@ int32_t lps33hw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps33hw_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lps33hw_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lps33hw_STdC/driver/lps33hw_reg.h b/sensor/stmemsc/lps33hw_STdC/driver/lps33hw_reg.h index 993ff9a0962de7c3000e0d8eef418f1c4421f346..3d0d6dcab0c5e9d1046a1d77a262f5cfb2f8a013 100644 --- a/sensor/stmemsc/lps33hw_STdC/driver/lps33hw_reg.h +++ b/sensor/stmemsc/lps33hw_STdC/driver/lps33hw_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -390,6 +393,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lps33hw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.c b/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.c index cf2af66f840aa5050164ff7c4e5fcbf49a4245c3..42310a9bec7d25d0123b09c5f9607d27f82b6018 100644 --- a/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.c +++ b/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.c @@ -45,8 +45,8 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps33k_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, - uint16_t len) +int32_t __weak lps33k_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, + uint16_t len) { int32_t ret; @@ -65,9 +65,9 @@ int32_t lps33k_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps33k_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lps33k_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.h b/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.h index c569658fb57024f54ddb4cd6410ba2c818c35ac8..656a2693b8e0a8355a1deb18a60e4f72c41dc11b 100644 --- a/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.h +++ b/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -288,6 +291,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lps33k_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); int32_t lps33k_write_reg(stmdev_ctx_t *ctx, uint8_t reg, diff --git a/sensor/stmemsc/lps33w_STdC/driver/lps33w_reg.c b/sensor/stmemsc/lps33w_STdC/driver/lps33w_reg.c index 400e6a623e9bbebcd18ee027885699414b06ffc2..5b9ca046996105bda0510b6481c1a242d93961f0 100644 --- a/sensor/stmemsc/lps33w_STdC/driver/lps33w_reg.c +++ b/sensor/stmemsc/lps33w_STdC/driver/lps33w_reg.c @@ -45,8 +45,8 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps33w_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, - uint16_t len) +int32_t __weak lps33w_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, + uint16_t len) { int32_t ret; @@ -65,9 +65,9 @@ int32_t lps33w_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps33w_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lps33w_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lps33w_STdC/driver/lps33w_reg.h b/sensor/stmemsc/lps33w_STdC/driver/lps33w_reg.h index 7801b5d1e55d200831078d6599f0ad35ee7915bd..42cc4024e083c52d12303980a7e4ffc9a18cbccd 100644 --- a/sensor/stmemsc/lps33w_STdC/driver/lps33w_reg.h +++ b/sensor/stmemsc/lps33w_STdC/driver/lps33w_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -390,6 +393,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lps33w_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); int32_t lps33w_write_reg(stmdev_ctx_t *ctx, uint8_t reg, diff --git a/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.c b/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.c index cf484e5f03cdd3d6fb85d51b9f961c9f84b92321..7b1c46246d93e95c3e4737fae0b3db1279bda778 100644 --- a/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.c +++ b/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm303agr_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lsm303agr_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t lsm303agr_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm303agr_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lsm303agr_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.h b/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.h index d4669b47c1e8205bf2b60b2351631b66ed1392c1..e4b5fddfec8cac2c1e3f89a7432a6b38f2fc5926 100644 --- a/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.h +++ b/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -848,6 +851,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lsm303agr_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.c b/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.c index ac00398214b12b650eb4a16a72cd5c743db21bc1..18e668f8ffc03eb3c878f8960a001de1b8ee95be 100644 --- a/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.c +++ b/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm303ah_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lsm303ah_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t lsm303ah_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm303ah_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lsm303ah_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.h b/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.h index 9f48086dd0dca5b8029f5e8eff76ac94ad4905e0..970fc4bc5efe23e4b56ace7cd136831f26665942 100644 --- a/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.h +++ b/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -845,6 +848,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lsm303ah_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/lsm6ds3_STdC/driver/lsm6ds3_reg.c b/sensor/stmemsc/lsm6ds3_STdC/driver/lsm6ds3_reg.c index e5c5923c0ebae3402794e4aed5b025e12d83e7a1..148b0acce023b4f62975f6fb9f1c3915199af13b 100644 --- a/sensor/stmemsc/lsm6ds3_STdC/driver/lsm6ds3_reg.c +++ b/sensor/stmemsc/lsm6ds3_STdC/driver/lsm6ds3_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6ds3_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lsm6ds3_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t lsm6ds3_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6ds3_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lsm6ds3_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lsm6ds3_STdC/driver/lsm6ds3_reg.h b/sensor/stmemsc/lsm6ds3_STdC/driver/lsm6ds3_reg.h index 62538de38b71bfe84b99478b5a137bda33dd89c1..56a89a169d59ea37f01fd74f71f76261a490bb31 100644 --- a/sensor/stmemsc/lsm6ds3_STdC/driver/lsm6ds3_reg.h +++ b/sensor/stmemsc/lsm6ds3_STdC/driver/lsm6ds3_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -1585,6 +1588,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lsm6ds3_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/lsm6ds3tr-c_STdC/driver/lsm6ds3tr-c_reg.c b/sensor/stmemsc/lsm6ds3tr-c_STdC/driver/lsm6ds3tr-c_reg.c index 1c00c01f715359e69c28ad55dcdd6c1b3a94eb57..0da47e1009d9585663c713936f0024afa6c14b47 100644 --- a/sensor/stmemsc/lsm6ds3tr-c_STdC/driver/lsm6ds3tr-c_reg.c +++ b/sensor/stmemsc/lsm6ds3tr-c_STdC/driver/lsm6ds3tr-c_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6ds3tr_c_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lsm6ds3tr_c_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t lsm6ds3tr_c_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6ds3tr_c_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lsm6ds3tr_c_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lsm6ds3tr-c_STdC/driver/lsm6ds3tr-c_reg.h b/sensor/stmemsc/lsm6ds3tr-c_STdC/driver/lsm6ds3tr-c_reg.h index d483dca1af015e3b69f247231d558a6f446975fb..f8e71842c2d8795d3fd653fbb03090a1ff9dd37c 100644 --- a/sensor/stmemsc/lsm6ds3tr-c_STdC/driver/lsm6ds3tr-c_reg.h +++ b/sensor/stmemsc/lsm6ds3tr-c_STdC/driver/lsm6ds3tr-c_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -1697,6 +1700,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lsm6ds3tr_c_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.c b/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.c index 92a588b679bf911463a566c5d6d8eb978e1177b4..f44360d402e923d9d1bdd98d6f2555bc76c02e38 100644 --- a/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.c +++ b/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lsm6dsl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t lsm6dsl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsl_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lsm6dsl_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.h b/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.h index 69c241db162575660aa568f549c755296e334752..b9addf3d7a7831b19e198d98cbe03db9bd1bbdc2 100644 --- a/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.h +++ b/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -1696,6 +1699,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lsm6dsl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.c b/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.c index 3645b0f6cfe8673c71002d80b682e0d72e1996cf..1bfbe5f4a50f7627aafdfb5025eb3834b54b760c 100644 --- a/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.c +++ b/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsm_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lsm6dsm_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t lsm6dsm_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsm_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lsm6dsm_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.h b/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.h index 0834624c3150ba9a3b6ffbdf83d8a67342283c55..3ea21ee9087c4789c5aacba9840e765d5cd0aff2 100644 --- a/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.h +++ b/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.h @@ -112,12 +112,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -1788,6 +1791,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lsm6dsm_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/lsm6dso16is_STdC/driver/lsm6dso16is_reg.c b/sensor/stmemsc/lsm6dso16is_STdC/driver/lsm6dso16is_reg.c new file mode 100644 index 0000000000000000000000000000000000000000..6a41e69bdd44edb7002483dc735ecac825c99c6f --- /dev/null +++ b/sensor/stmemsc/lsm6dso16is_STdC/driver/lsm6dso16is_reg.c @@ -0,0 +1,3787 @@ +/** + ****************************************************************************** + * @file lsm6dso16is_reg.c + * @author Sensors Software Solution Team + * @brief LSM6DSO16IS driver file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2022 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "lsm6dso16is_reg.h" + +/** + * @defgroup LSM6DSO16IS + * @brief This file provides a set of functions needed to drive the + * lsm6dso16is enhanced inertial module. + * @{ + * + */ + +/** + * @defgroup Interfaces functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +/** + * @brief Read generic device register + * + * @param ctx communication interface handler.(ptr) + * @param reg first register address to read. + * @param data buffer for data read.(ptr) + * @param len number of consecutive register to read. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak lsm6dso16is_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) +{ + int32_t ret; + + ret = ctx->read_reg(ctx->handle, reg, data, len); + + return ret; +} + +/** + * @brief Write generic device register + * + * @param ctx communication interface handler.(ptr) + * @param reg first register address to write. + * @param data the buffer contains data to be written.(ptr) + * @param len number of consecutive register to write. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak lsm6dso16is_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) +{ + int32_t ret; + + ret = ctx->write_reg(ctx->handle, reg, data, len); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSO16IS_Sensitivity + * @brief These functions convert raw-data into engineering units. + * @{ + * + */ + +float_t lsm6dso16is_from_fs2g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 0.061f); +} + +float_t lsm6dso16is_from_fs4g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 0.122f); +} + +float_t lsm6dso16is_from_fs8g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 0.244f); +} + +float_t lsm6dso16is_from_fs16g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 0.488f); +} + +float_t lsm6dso16is_from_fs125dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 4.375f); +} + +float_t lsm6dso16is_from_fs250dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 8.75f); +} + +float_t lsm6dso16is_from_fs500dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 17.50f); +} + +float_t lsm6dso16is_from_fs1000dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 35.0f); +} + +float_t lsm6dso16is_from_fs2000dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 70.0f); +} + +float_t lsm6dso16is_from_lsb_to_celsius(int16_t lsb) +{ + return (((float_t)lsb / 256.0f) + 25.0f); +} + +/** + * @defgroup Common + * @brief Common + * @{/ + * + */ + +/** + * @brief Difference in percentage of the effective ODR (and timestamp rate) + * with respect to the typical.[set] + * Step: 0.15%. 8-bit format, 2's complement. + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dso16is_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dso16is_internal_freq_fine_t internal_freq_fine; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_INTERNAL_FREQ_FINE, + (uint8_t *)&internal_freq_fine, 1); + + if (ret == 0) + { + internal_freq_fine.freq_fine = (uint8_t)val; + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_INTERNAL_FREQ_FINE, + (uint8_t *)&internal_freq_fine, 1); + } + + return ret; +} + +/** + * @brief Difference in percentage of the effective ODR (and timestamp rate) + * with respect to the typical.[get] + * Step: 0.15%. 8-bit format, 2's complement. + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dso16is_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dso16is_internal_freq_fine_t internal_freq_fine; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_INTERNAL_FREQ_FINE, + (uint8_t *)&internal_freq_fine, 1); + *val = internal_freq_fine.freq_fine; + + return ret; +} + +/** + * @brief Change memory bank.[set] + * + * @param ctx read / write interface definitions + * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, SENSOR_HUB_MEM_BANK, ISPU_MEM_BANK, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_mem_bank_set(stmdev_ctx_t *ctx, lsm6dso16is_mem_bank_t val) +{ + lsm6dso16is_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + if (ret == 0) + { + func_cfg_access.shub_reg_access = (val == LSM6DSO16IS_SENSOR_HUB_MEM_BANK) ? 0x1U : 0x0U; + func_cfg_access.ispu_reg_access = (val == LSM6DSO16IS_ISPU_MEM_BANK) ? 0x1U : 0x0U; + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Change memory bank.[get] + * + * @param ctx read / write interface definitions + * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, SENSOR_HUB_MEM_BANK, ISPU_MEM_BANK, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_mem_bank_get(stmdev_ctx_t *ctx, lsm6dso16is_mem_bank_t *val) +{ + lsm6dso16is_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + if (func_cfg_access.shub_reg_access == 1U) + { + *val = LSM6DSO16IS_SENSOR_HUB_MEM_BANK; + } + else if (func_cfg_access.ispu_reg_access == 1U) + { + *val = LSM6DSO16IS_ISPU_MEM_BANK; + } + else + { + *val = LSM6DSO16IS_MAIN_MEM_BANK; + } + + return ret; +} + +/** + * @brief Enables pulsed data-ready mode (~75 us).[set] + * + * @param ctx read / write interface definitions + * @param val DRDY_LATCHED, DRDY_PULSED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_data_ready_mode_set(stmdev_ctx_t *ctx, + lsm6dso16is_data_ready_mode_t val) +{ + lsm6dso16is_drdy_pulsed_reg_t drdy_pulsed_reg; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_DRDY_PULSED_REG, (uint8_t *)&drdy_pulsed_reg, 1); + + if (ret == 0) + { + drdy_pulsed_reg.drdy_pulsed = ((uint8_t)val & 0x1U); + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_DRDY_PULSED_REG, (uint8_t *)&drdy_pulsed_reg, 1); + } + + return ret; +} + +/** + * @brief Enables pulsed data-ready mode (~75 us).[get] + * + * @param ctx read / write interface definitions + * @param val DRDY_LATCHED, DRDY_PULSED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_data_ready_mode_get(stmdev_ctx_t *ctx, + lsm6dso16is_data_ready_mode_t *val) +{ + lsm6dso16is_drdy_pulsed_reg_t drdy_pulsed_reg; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_DRDY_PULSED_REG, (uint8_t *)&drdy_pulsed_reg, 1); + + switch ((drdy_pulsed_reg.drdy_pulsed)) + { + case LSM6DSO16IS_DRDY_LATCHED: + *val = LSM6DSO16IS_DRDY_LATCHED; + break; + + case LSM6DSO16IS_DRDY_PULSED: + *val = LSM6DSO16IS_DRDY_PULSED; + break; + + default: + *val = LSM6DSO16IS_DRDY_LATCHED; + break; + } + return ret; +} + +/** + * @brief Device ID.[get] + * + * @param ctx read / write interface definitions + * @param val Device ID. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_device_id_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_WHO_AM_I, (uint8_t *)val, 1); + + return ret; +} + +/** + * @brief Software reset. Restore the default values in user registers.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dso16is_software_reset(stmdev_ctx_t *ctx) +{ + lsm6dso16is_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret == 0) + { + ret += lsm6dso16is_xl_data_rate_set(ctx, LSM6DSO16IS_XL_ODR_OFF); + ret += lsm6dso16is_gy_data_rate_set(ctx, LSM6DSO16IS_GY_ODR_OFF); + + ctrl3_c.sw_reset = PROPERTY_ENABLE; + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + do { + ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } while (ret == 0 && ctrl3_c.sw_reset == PROPERTY_ENABLE); + } + + return ret; +} + +/** + * @brief Reboot memory content. Reload the calibration parameters.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of boot in reg CTRL_REG1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dso16is_boot_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dso16is_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret == 0) + { + ctrl3_c.boot = val; + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + + return ret; +} + +/** + * @brief Reboot memory content. Reload the calibration parameters.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of boot in reg CTRL_REG1.(ptr) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dso16is_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dso16is_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + *val = ctrl3_c.boot; + + return ret; +} + +/** + * @brief Enable disable high-performance mode[set] + * + * @param ctx read / write interface definitions + * @param val HIGH_PERFOMANCE_MODE_ENABLED, HIGH_PERFOMANCE_MODE_DISABLED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_xl_hm_mode_set(stmdev_ctx_t *ctx, lsm6dso16is_hm_mode_t val) +{ + lsm6dso16is_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + + if (ret == 0) + { + ctrl6_c.xl_hm_mode = ((uint8_t)val & 0x1U); + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + } + + return ret; +} + +/** + * @brief Enable disable high-performance mode[get] + * + * @param ctx read / write interface definitions + * @param val HIGH_PERFOMANCE_MODE_ENABLED, HIGH_PERFOMANCE_MODE_DISABLED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_xl_hm_mode_get(stmdev_ctx_t *ctx, + lsm6dso16is_hm_mode_t *val) +{ + lsm6dso16is_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + + switch ((ctrl6_c.xl_hm_mode)) + { + case LSM6DSO16IS_HIGH_PERFOMANCE_MODE_ENABLED: + *val = LSM6DSO16IS_HIGH_PERFOMANCE_MODE_ENABLED; + break; + + case LSM6DSO16IS_HIGH_PERFOMANCE_MODE_DISABLED: + *val = LSM6DSO16IS_HIGH_PERFOMANCE_MODE_DISABLED; + break; + + default: + *val = LSM6DSO16IS_HIGH_PERFOMANCE_MODE_ENABLED; + break; + } + return ret; +} + +/** + * @brief Accelerometer full-scale selection.[set] + * + * @param ctx read / write interface definitions + * @param val 2g, 4g, 8g, 16g, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_xl_full_scale_set(stmdev_ctx_t *ctx, + lsm6dso16is_xl_full_scale_t val) +{ + lsm6dso16is_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + + if (ret == 0) + { + ctrl1_xl.fs_xl = ((uint8_t)val & 0x3U); + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + } + + return ret; +} + +/** + * @brief Accelerometer full-scale selection.[get] + * + * @param ctx read / write interface definitions + * @param val 2g, 4g, 8g, 16g, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_xl_full_scale_get(stmdev_ctx_t *ctx, + lsm6dso16is_xl_full_scale_t *val) +{ + lsm6dso16is_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + + switch ((ctrl1_xl.fs_xl)) + { + case LSM6DSO16IS_2g: + *val = LSM6DSO16IS_2g; + break; + + case LSM6DSO16IS_4g: + *val = LSM6DSO16IS_4g; + break; + + case LSM6DSO16IS_8g: + *val = LSM6DSO16IS_8g; + break; + + case LSM6DSO16IS_16g: + *val = LSM6DSO16IS_16g; + break; + + default: + *val = LSM6DSO16IS_2g; + break; + } + return ret; +} + +/** + * @brief Accelerometer output data rate (ODR) selection.[set] + * + * @param ctx read / write interface definitions + * @param val XL_ODR_OFF, XL_ODR_AT_1Hz875, XL_ODR_AT_7Hz5, XL_ODR_AT_15Hz, XL_ODR_AT_30Hz, XL_ODR_AT_60Hz, XL_ODR_AT_120Hz, XL_ODR_AT_240Hz, XL_ODR_AT_480Hz, XL_ODR_AT_960Hz, XL_ODR_AT_1920Hz, XL_ODR_AT_3840Hz, XL_ODR_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_xl_data_rate_set(stmdev_ctx_t *ctx, + lsm6dso16is_xl_data_rate_t val) +{ + lsm6dso16is_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + + if (ret == 0) + { + if (((uint8_t)val & 0x10U) == 0x10U) + { + ret += lsm6dso16is_xl_hm_mode_set(ctx, + LSM6DSO16IS_HIGH_PERFOMANCE_MODE_DISABLED); + } + else + { + ret += lsm6dso16is_xl_hm_mode_set(ctx, + LSM6DSO16IS_HIGH_PERFOMANCE_MODE_ENABLED); + } + + ctrl1_xl.odr_xl = ((uint8_t)val & 0xfU); + ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, + 1); + } + + return ret; +} + +/** + * @brief Accelerometer output data rate (ODR) selection.[get] + * + * @param ctx read / write interface definitions + * @param val XL_ODR_OFF, XL_ODR_AT_1Hz875, XL_ODR_AT_7Hz5, XL_ODR_AT_15Hz, XL_ODR_AT_30Hz, XL_ODR_AT_60Hz, XL_ODR_AT_120Hz, XL_ODR_AT_240Hz, XL_ODR_AT_480Hz, XL_ODR_AT_960Hz, XL_ODR_AT_1920Hz, XL_ODR_AT_3840Hz, XL_ODR_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_xl_data_rate_get(stmdev_ctx_t *ctx, + lsm6dso16is_xl_data_rate_t *val) +{ + lsm6dso16is_ctrl1_xl_t ctrl1_xl; + lsm6dso16is_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret == 0) + { + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + } + + switch ((ctrl6_c.xl_hm_mode << 4) | (ctrl1_xl.odr_xl)) + { + case LSM6DSO16IS_XL_ODR_OFF: + *val = LSM6DSO16IS_XL_ODR_OFF; + break; + + case LSM6DSO16IS_XL_ODR_AT_12Hz5_HP: + *val = LSM6DSO16IS_XL_ODR_AT_12Hz5_HP; + break; + + case LSM6DSO16IS_XL_ODR_AT_26H_HP: + *val = LSM6DSO16IS_XL_ODR_AT_26H_HP; + break; + + case LSM6DSO16IS_XL_ODR_AT_52Hz_HP: + *val = LSM6DSO16IS_XL_ODR_AT_52Hz_HP; + break; + + case LSM6DSO16IS_XL_ODR_AT_104Hz_HP: + *val = LSM6DSO16IS_XL_ODR_AT_104Hz_HP; + break; + + case LSM6DSO16IS_XL_ODR_AT_208Hz_HP: + *val = LSM6DSO16IS_XL_ODR_AT_208Hz_HP; + break; + + case LSM6DSO16IS_XL_ODR_AT_416Hz_HP: + *val = LSM6DSO16IS_XL_ODR_AT_416Hz_HP; + break; + + case LSM6DSO16IS_XL_ODR_AT_833Hz_HP: + *val = LSM6DSO16IS_XL_ODR_AT_833Hz_HP; + break; + + case LSM6DSO16IS_XL_ODR_AT_1667Hz_HP: + *val = LSM6DSO16IS_XL_ODR_AT_1667Hz_HP; + break; + + case LSM6DSO16IS_XL_ODR_AT_3333Hz_HP: + *val = LSM6DSO16IS_XL_ODR_AT_3333Hz_HP; + break; + + case LSM6DSO16IS_XL_ODR_AT_6667Hz_HP: + *val = LSM6DSO16IS_XL_ODR_AT_6667Hz_HP; + break; + + case LSM6DSO16IS_XL_ODR_AT_12Hz5_LP: + *val = LSM6DSO16IS_XL_ODR_AT_12Hz5_LP; + break; + + case LSM6DSO16IS_XL_ODR_AT_26H_LP: + *val = LSM6DSO16IS_XL_ODR_AT_26H_LP; + break; + + case LSM6DSO16IS_XL_ODR_AT_52Hz_LP: + *val = LSM6DSO16IS_XL_ODR_AT_52Hz_LP; + break; + + case LSM6DSO16IS_XL_ODR_AT_104Hz_LP: + *val = LSM6DSO16IS_XL_ODR_AT_104Hz_LP; + break; + + case LSM6DSO16IS_XL_ODR_AT_208Hz_LP: + *val = LSM6DSO16IS_XL_ODR_AT_208Hz_LP; + break; + + case LSM6DSO16IS_XL_ODR_AT_416Hz_LP: + *val = LSM6DSO16IS_XL_ODR_AT_416Hz_LP; + break; + + case LSM6DSO16IS_XL_ODR_AT_833Hz_LP: + *val = LSM6DSO16IS_XL_ODR_AT_833Hz_LP; + break; + + case LSM6DSO16IS_XL_ODR_AT_1667Hz_LP: + *val = LSM6DSO16IS_XL_ODR_AT_1667Hz_LP; + break; + + case LSM6DSO16IS_XL_ODR_AT_3333Hz_LP: + *val = LSM6DSO16IS_XL_ODR_AT_3333Hz_LP; + break; + + case LSM6DSO16IS_XL_ODR_AT_6667Hz_LP: + *val = LSM6DSO16IS_XL_ODR_AT_6667Hz_LP; + break; + + case LSM6DSO16IS_XL_ODR_AT_1Hz6_LP: + *val = LSM6DSO16IS_XL_ODR_AT_1Hz6_LP; + break; + + default: + *val = LSM6DSO16IS_XL_ODR_OFF; + break; + } + return ret; +} + +/** + * @brief Enable disable high-performance mode[set] + * + * @param ctx read / write interface definitions + * @param val HIGH_PERFOMANCE_MODE_ENABLED, HIGH_PERFOMANCE_MODE_DISABLED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_gy_hm_mode_set(stmdev_ctx_t *ctx, lsm6dso16is_hm_mode_t val) +{ + lsm6dso16is_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + + if (ret == 0) + { + ctrl7_g.g_hm_mode = ((uint8_t)val & 0x1U); + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + } + + return ret; +} + +/** + * @brief Enable disable high-performance mode[get] + * + * @param ctx read / write interface definitions + * @param val HIGH_PERFOMANCE_MODE_ENABLED, HIGH_PERFOMANCE_MODE_DISABLED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_gy_hm_mode_get(stmdev_ctx_t *ctx, + lsm6dso16is_hm_mode_t *val) +{ + lsm6dso16is_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + + switch ((ctrl7_g.g_hm_mode)) + { + case LSM6DSO16IS_HIGH_PERFOMANCE_MODE_ENABLED: + *val = LSM6DSO16IS_HIGH_PERFOMANCE_MODE_ENABLED; + break; + + case LSM6DSO16IS_HIGH_PERFOMANCE_MODE_DISABLED: + *val = LSM6DSO16IS_HIGH_PERFOMANCE_MODE_DISABLED; + break; + + default: + *val = LSM6DSO16IS_HIGH_PERFOMANCE_MODE_ENABLED; + break; + } + return ret; +} + +/** + * @brief Gyroscope full-scale selection[set] + * + * @param ctx read / write interface definitions + * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_gy_full_scale_set(stmdev_ctx_t *ctx, + lsm6dso16is_gy_full_scale_t val) +{ + lsm6dso16is_ctrl2_g_t ctrl2_g; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + + if (ret == 0) + { + ctrl2_g.fs_g = ((uint8_t)val & 0x3U); + ctrl2_g.fs_125 = ((uint8_t)val >> 4); + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + } + + return ret; +} + +/** + * @brief Gyroscope full-scale selection[get] + * + * @param ctx read / write interface definitions + * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_gy_full_scale_get(stmdev_ctx_t *ctx, + lsm6dso16is_gy_full_scale_t *val) +{ + lsm6dso16is_ctrl2_g_t ctrl2_g; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + + switch ((ctrl2_g.fs_125 << 4) | (ctrl2_g.fs_g)) + { + case LSM6DSO16IS_125dps: + *val = LSM6DSO16IS_125dps; + break; + + case LSM6DSO16IS_250dps: + *val = LSM6DSO16IS_250dps; + break; + + case LSM6DSO16IS_500dps: + *val = LSM6DSO16IS_500dps; + break; + + case LSM6DSO16IS_1000dps: + *val = LSM6DSO16IS_1000dps; + break; + + case LSM6DSO16IS_2000dps: + *val = LSM6DSO16IS_2000dps; + break; + + default: + *val = LSM6DSO16IS_125dps; + break; + } + return ret; +} + +/** + * @brief Gyroscope output data rate (ODR) selection.[set] + * + * @param ctx read / write interface definitions + * @param val GY_ODR_OFF, GY_ODR_AT_7Hz5, GY_ODR_AT_15Hz, GY_ODR_AT_30Hz, GY_ODR_AT_60Hz, GY_ODR_AT_120Hz, GY_ODR_AT_240Hz, GY_ODR_AT_480Hz, GY_ODR_AT_960Hz, GY_ODR_AT_1920Hz, GY_ODR_AT_3840Hz, GY_ODR_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_gy_data_rate_set(stmdev_ctx_t *ctx, + lsm6dso16is_gy_data_rate_t val) +{ + lsm6dso16is_ctrl2_g_t ctrl2_g; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + + if (ret == 0) + { + if (((uint8_t)val & 0x10U) == 0x10U) + { + ret += lsm6dso16is_gy_hm_mode_set(ctx, + LSM6DSO16IS_HIGH_PERFOMANCE_MODE_DISABLED); + } + else + { + ret += lsm6dso16is_gy_hm_mode_set(ctx, + LSM6DSO16IS_HIGH_PERFOMANCE_MODE_ENABLED); + } + + ctrl2_g.odr_g = ((uint8_t)val & 0xfU); + ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + } + + return ret; +} + +/** + * @brief Gyroscope output data rate (ODR) selection.[get] + * + * @param ctx read / write interface definitions + * @param val GY_ODR_OFF, GY_ODR_AT_7Hz5, GY_ODR_AT_15Hz, GY_ODR_AT_30Hz, GY_ODR_AT_60Hz, GY_ODR_AT_120Hz, GY_ODR_AT_240Hz, GY_ODR_AT_480Hz, GY_ODR_AT_960Hz, GY_ODR_AT_1920Hz, GY_ODR_AT_3840Hz, GY_ODR_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_gy_data_rate_get(stmdev_ctx_t *ctx, + lsm6dso16is_gy_data_rate_t *val) +{ + lsm6dso16is_ctrl2_g_t ctrl2_g; + lsm6dso16is_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + if (ret == 0) + { + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + } + + switch ((ctrl7_g.g_hm_mode << 4) | (ctrl2_g.odr_g)) + { + case LSM6DSO16IS_GY_ODR_OFF: + *val = LSM6DSO16IS_GY_ODR_OFF; + break; + + case LSM6DSO16IS_GY_ODR_AT_12Hz5_HP: + *val = LSM6DSO16IS_GY_ODR_AT_12Hz5_HP; + break; + + case LSM6DSO16IS_GY_ODR_AT_26H_HP: + *val = LSM6DSO16IS_GY_ODR_AT_26H_HP; + break; + + case LSM6DSO16IS_GY_ODR_AT_52Hz_HP: + *val = LSM6DSO16IS_GY_ODR_AT_52Hz_HP; + break; + + case LSM6DSO16IS_GY_ODR_AT_104Hz_HP: + *val = LSM6DSO16IS_GY_ODR_AT_104Hz_HP; + break; + + case LSM6DSO16IS_GY_ODR_AT_208Hz_HP: + *val = LSM6DSO16IS_GY_ODR_AT_208Hz_HP; + break; + + case LSM6DSO16IS_GY_ODR_AT_416Hz_HP: + *val = LSM6DSO16IS_GY_ODR_AT_416Hz_HP; + break; + + case LSM6DSO16IS_GY_ODR_AT_833Hz_HP: + *val = LSM6DSO16IS_GY_ODR_AT_833Hz_HP; + break; + + case LSM6DSO16IS_GY_ODR_AT_1667Hz_HP: + *val = LSM6DSO16IS_GY_ODR_AT_1667Hz_HP; + break; + + case LSM6DSO16IS_GY_ODR_AT_3333Hz_HP: + *val = LSM6DSO16IS_GY_ODR_AT_3333Hz_HP; + break; + + case LSM6DSO16IS_GY_ODR_AT_6667Hz_HP: + *val = LSM6DSO16IS_GY_ODR_AT_6667Hz_HP; + break; + + case LSM6DSO16IS_GY_ODR_AT_12Hz5_LP: + *val = LSM6DSO16IS_GY_ODR_AT_12Hz5_LP; + break; + + case LSM6DSO16IS_GY_ODR_AT_26H_LP: + *val = LSM6DSO16IS_GY_ODR_AT_26H_LP; + break; + + case LSM6DSO16IS_GY_ODR_AT_52Hz_LP: + *val = LSM6DSO16IS_GY_ODR_AT_52Hz_LP; + break; + + case LSM6DSO16IS_GY_ODR_AT_104Hz_LP: + *val = LSM6DSO16IS_GY_ODR_AT_104Hz_LP; + break; + + case LSM6DSO16IS_GY_ODR_AT_208Hz_LP: + *val = LSM6DSO16IS_GY_ODR_AT_208Hz_LP; + break; + + case LSM6DSO16IS_GY_ODR_AT_416Hz_LP: + *val = LSM6DSO16IS_GY_ODR_AT_416Hz_LP; + break; + + case LSM6DSO16IS_GY_ODR_AT_833Hz_LP: + *val = LSM6DSO16IS_GY_ODR_AT_833Hz_LP; + break; + + case LSM6DSO16IS_GY_ODR_AT_1667Hz_LP: + *val = LSM6DSO16IS_GY_ODR_AT_1667Hz_LP; + break; + + case LSM6DSO16IS_GY_ODR_AT_3333Hz_LP: + *val = LSM6DSO16IS_GY_ODR_AT_3333Hz_LP; + break; + + case LSM6DSO16IS_GY_ODR_AT_6667Hz_LP: + *val = LSM6DSO16IS_GY_ODR_AT_6667Hz_LP; + break; + + default: + *val = LSM6DSO16IS_GY_ODR_OFF; + break; + } + + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[set] + * + * @param ctx read / write interface definitions + * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dso16is_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret == 0) + { + ctrl3_c.if_inc = val; + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[get] + * + * @param ctx read / write interface definitions + * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dso16is_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + *val = ctrl3_c.if_inc; + + return ret; +} + +/** + * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [set] + * + * @param ctx read / write interface definitions + * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dso16is_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret == 0) + { + ctrl3_c.bdu = val; + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + + return ret; +} + +/** + * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [get] + * + * @param ctx read / write interface definitions + * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dso16is_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + *val = ctrl3_c.bdu; + + return ret; +} + +/** + * @brief Enables gyroscope sleep mode[set] + * + * @param ctx read / write interface definitions + * @param val SLEEP_G_ENABLE, SLEEP_G_DISABLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_sleep_set(stmdev_ctx_t *ctx, lsm6dso16is_sleep_t val) +{ + lsm6dso16is_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + + if (ret == 0) + { + ctrl4_c.sleep_g = ((uint8_t)val & 0x1U); + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + } + + return ret; +} + +/** + * @brief Enables gyroscope sleep mode[get] + * + * @param ctx read / write interface definitions + * @param val SLEEP_G_ENABLE, SLEEP_G_DISABLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_sleep_get(stmdev_ctx_t *ctx, lsm6dso16is_sleep_t *val) +{ + lsm6dso16is_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + + switch ((ctrl4_c.sleep_g)) + { + case LSM6DSO16IS_SLEEP_G_ENABLE: + *val = LSM6DSO16IS_SLEEP_G_ENABLE; + break; + + case LSM6DSO16IS_SLEEP_G_DISABLE: + *val = LSM6DSO16IS_SLEEP_G_DISABLE; + break; + + default: + *val = LSM6DSO16IS_SLEEP_G_ENABLE; + break; + } + return ret; +} + +/** + * @brief Accelerometer self-test selection.[set] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_xl_self_test_set(stmdev_ctx_t *ctx, + lsm6dso16is_xl_self_test_t val) +{ + lsm6dso16is_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + + if (ret == 0) + { + ctrl5_c.st_xl = ((uint8_t)val & 0x3U); + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + } + + return ret; +} + +/** + * @brief Accelerometer self-test selection.[get] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_xl_self_test_get(stmdev_ctx_t *ctx, + lsm6dso16is_xl_self_test_t *val) +{ + lsm6dso16is_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + + switch ((ctrl5_c.st_xl)) + { + case LSM6DSO16IS_XL_ST_DISABLE: + *val = LSM6DSO16IS_XL_ST_DISABLE; + break; + + case LSM6DSO16IS_XL_ST_POSITIVE: + *val = LSM6DSO16IS_XL_ST_POSITIVE; + break; + + case LSM6DSO16IS_XL_ST_NEGATIVE: + *val = LSM6DSO16IS_XL_ST_NEGATIVE; + break; + + default: + *val = LSM6DSO16IS_XL_ST_DISABLE; + break; + } + return ret; +} + +/** + * @brief Gyroscope self-test selection.[set] + * + * @param ctx read / write interface definitions + * @param val GY_ST_DISABLE, GY_ST_POSITIVE, GY_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_gy_self_test_set(stmdev_ctx_t *ctx, + lsm6dso16is_gy_self_test_t val) +{ + lsm6dso16is_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + + if (ret == 0) + { + ctrl5_c.st_g = ((uint8_t)val & 0x3U); + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + } + + return ret; +} + +/** + * @brief Gyroscope self-test selection.[get] + * + * @param ctx read / write interface definitions + * @param val GY_ST_DISABLE, GY_ST_POSITIVE, GY_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_gy_self_test_get(stmdev_ctx_t *ctx, + lsm6dso16is_gy_self_test_t *val) +{ + lsm6dso16is_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + + switch ((ctrl5_c.st_g)) + { + case LSM6DSO16IS_GY_ST_DISABLE: + *val = LSM6DSO16IS_GY_ST_DISABLE; + break; + + case LSM6DSO16IS_GY_ST_POSITIVE: + *val = LSM6DSO16IS_GY_ST_POSITIVE; + break; + + case LSM6DSO16IS_GY_ST_NEGATIVE: + *val = LSM6DSO16IS_GY_ST_NEGATIVE; + break; + + default: + *val = LSM6DSO16IS_GY_ST_DISABLE; + break; + } + return ret; +} + +/** + * @defgroup Serial Interfaces + * @brief Serial Interfaces + * @{/ + * + */ +/** + * @brief Enables pull-up on SDO pin of UI (User Interface).[set] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDO pin of UI (User Interface). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dso16is_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + + if (ret == 0) + { + pin_ctrl.sdo_pu_en = val; + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + + return ret; +} + +/** + * @brief Enables pull-up on SDO pin of UI (User Interface).[get] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDO pin of UI (User Interface). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dso16is_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + + *val = pin_ctrl.sdo_pu_en; + + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val SPI_4_WIRE, SPI_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_spi_mode_set(stmdev_ctx_t *ctx, lsm6dso16is_spi_mode_t val) +{ + lsm6dso16is_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret == 0) + { + ctrl3_c.sim = ((uint8_t)val & 0x1U); + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val SPI_4_WIRE, SPI_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_spi_mode_get(stmdev_ctx_t *ctx, lsm6dso16is_spi_mode_t *val) +{ + lsm6dso16is_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + switch ((ctrl3_c.sim)) + { + case LSM6DSO16IS_SPI_4_WIRE: + *val = LSM6DSO16IS_SPI_4_WIRE; + break; + + case LSM6DSO16IS_SPI_3_WIRE: + *val = LSM6DSO16IS_SPI_3_WIRE; + break; + + default: + *val = LSM6DSO16IS_SPI_4_WIRE; + break; + } + return ret; +} + +/** + * @brief Disables I2C on UI (User Interface).[set] + * + * @param ctx read / write interface definitions + * @param val I2C_ENABLE, I2C_DISABLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_ui_i2c_mode_set(stmdev_ctx_t *ctx, + lsm6dso16is_ui_i2c_mode_t val) +{ + lsm6dso16is_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + + if (ret == 0) + { + ctrl4_c.i2c_disable = ((uint8_t)val & 0x1U); + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + } + + return ret; +} + +/** + * @brief Disables I2C on UI (User Interface).[get] + * + * @param ctx read / write interface definitions + * @param val I2C_ENABLE, I2C_DISABLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_ui_i2c_mode_get(stmdev_ctx_t *ctx, + lsm6dso16is_ui_i2c_mode_t *val) +{ + lsm6dso16is_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + + switch ((ctrl4_c.i2c_disable)) + { + case LSM6DSO16IS_I2C_ENABLE: + *val = LSM6DSO16IS_I2C_ENABLE; + break; + + case LSM6DSO16IS_I2C_DISABLE: + *val = LSM6DSO16IS_I2C_DISABLE; + break; + + default: + *val = LSM6DSO16IS_I2C_ENABLE; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Timestamp + * @brief Timestamp + * @{/ + * + */ +/** + * @brief Enables timestamp counter.[set] + * + * @param ctx read / write interface definitions + * @param val Enables timestamp counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dso16is_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + if (ret == 0) + { + ctrl10_c.timestamp_en = val; + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + } + + return ret; +} + +/** + * @brief Enables timestamp counter.[get] + * + * @param ctx read / write interface definitions + * @param val Enables timestamp counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dso16is_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + *val = ctrl10_c.timestamp_en; + + return ret; +} + +/** + * @brief Timestamp data output.[get] + * + * @param ctx read / write interface definitions + * @param val Timestamp data output. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) +{ + uint8_t buff[4]; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_TIMESTAMP0, &buff[0], 4); + + *val = (uint32_t)buff[3]; + *val = (*val * 256U) + (uint32_t)buff[2]; + *val = (*val * 256U) + (uint32_t)buff[1]; + *val = (*val * 256U) + (uint32_t)buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @brief Get the status of all the interrupt sources.[get] + * + * @param ctx read / write interface definitions + * @param val Get the status of all the interrupt sources. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_all_sources_get(stmdev_ctx_t *ctx, + lsm6dso16is_all_sources_t *val) +{ + lsm6dso16is_status_reg_t status_reg; + lsm6dso16is_status_master_mainpage_t status_sh; + uint32_t status_ispu; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret == 0) + { + val->drdy_xl = status_reg.xlda; + val->drdy_gy = status_reg.gda; + val->drdy_temp = status_reg.tda; + } + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_STATUS_MASTER_MAINPAGE, (uint8_t *)&status_sh, 1); + if (ret == 0) + { + val->sh_endop = status_sh.sens_hub_endop; + val->sh_slave0_nack = status_sh.sens_hub_endop; + val->sh_slave1_nack = status_sh.sens_hub_endop; + val->sh_slave2_nack = status_sh.sens_hub_endop; + val->sh_slave3_nack = status_sh.sens_hub_endop; + val->sh_wr_once = status_sh.sens_hub_endop; + } + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_INT_STATUS0_MAINPAGE, (uint8_t *)&status_ispu, 4); + if (ret == 0) + { + val->ispu = status_ispu; + } + + return ret; +} + +/** + * @brief The STATUS_REG register is read by the primary interface.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get register STATUS_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dso16is_status_reg_get(stmdev_ctx_t *ctx, + lsm6dso16is_status_reg_t *val) +{ + int32_t ret; + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_STATUS_REG, (uint8_t *) val, 1); + + return ret; +} + +/** + * @brief Accelerometer new data available.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of xlda in reg STATUS_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dso16is_xl_flag_data_ready_get(stmdev_ctx_t *ctx, + uint8_t *val) +{ + lsm6dso16is_status_reg_t status_reg; + int32_t ret; + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_STATUS_REG, + (uint8_t *)&status_reg, 1); + *val = status_reg.xlda; + + return ret; +} + +/** + * @brief Gyroscope new data available.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of gda in reg STATUS_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dso16is_gy_flag_data_ready_get(stmdev_ctx_t *ctx, + uint8_t *val) +{ + lsm6dso16is_status_reg_t status_reg; + int32_t ret; + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_STATUS_REG, + (uint8_t *)&status_reg, 1); + *val = status_reg.gda; + + return ret; +} + +/** + * @brief Temperature new data available.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of tda in reg STATUS_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dso16is_temp_flag_data_ready_get(stmdev_ctx_t *ctx, + uint8_t *val) +{ + lsm6dso16is_status_reg_t status_reg; + int32_t ret; + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_STATUS_REG, + (uint8_t *)&status_reg, 1); + *val = status_reg.tda; + + return ret; +} + +/** + * @brief Temperature data output register[get] + * + * @param ctx read / write interface definitions + * @param val Temperature data output register + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_OUT_TEMP_L, &buff[0], 2); + *val = (int16_t)buff[1]; + *val = (*val * 256) + (int16_t)buff[0]; + + return ret; +} + +/** + * @brief Angular rate sensor.[get] + * + * @param ctx read / write interface definitions + * @param val Angular rate sensor. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_OUTX_L_G, buff, 6); + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Linear acceleration sensor.[get] + * + * @param ctx read / write interface definitions + * @param val Linear acceleration sensor. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_OUTX_L_A, buff, 6); + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Interrupt PINs + * @brief Interrupt PINs + * @{/ + * + */ +/** + * @brief It routes interrupt signals on INT 1 pin.[set] + * + * @param ctx read / write interface definitions + * @param val It routes interrupt signals on INT 1 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_pin_int1_route_set(stmdev_ctx_t *ctx, + lsm6dso16is_pin_int1_route_t val) +{ + lsm6dso16is_int1_ctrl_t int1_ctrl; + lsm6dso16is_md1_cfg_t md1_cfg; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + if (ret == 0) + { + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MD1_CFG, (uint8_t *)&md1_cfg, 1); + } + + if (ret == 0) + { + int1_ctrl.int1_drdy_xl = val.drdy_xl; + int1_ctrl.int1_drdy_g = val.drdy_gy; + int1_ctrl.int1_boot = val.boot; + ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_INT1_CTRL, (uint8_t *)&int1_ctrl, + 1); + + md1_cfg.int1_shub = val.sh_endop; + md1_cfg.int1_ispu = val.ispu; + ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MD1_CFG, (uint8_t *)&md1_cfg, 1); + } + + return ret; +} + +/** + * @brief It routes interrupt signals on INT 1 pin.[get] + * + * @param ctx read / write interface definitions + * @param val It routes interrupt signals on INT 1 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_pin_int1_route_get(stmdev_ctx_t *ctx, + lsm6dso16is_pin_int1_route_t *val) +{ + lsm6dso16is_int1_ctrl_t int1_ctrl; + lsm6dso16is_md1_cfg_t md1_cfg; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + if (ret == 0) + { + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MD1_CFG, (uint8_t *)&md1_cfg, 1); + } + + if (ret == 0) + { + val->drdy_xl = int1_ctrl.int1_drdy_xl; + val->drdy_gy = int1_ctrl.int1_drdy_g; + val->boot = int1_ctrl.int1_boot; + val->sh_endop = md1_cfg.int1_shub; + val->ispu = md1_cfg.int1_ispu; + } + + return ret; +} + +/** + * @brief It routes interrupt signals on INT 2 pin.[set] + * + * @param ctx read / write interface definitions + * @param val It routes interrupt signals on INT 2 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_pin_int2_route_set(stmdev_ctx_t *ctx, + lsm6dso16is_pin_int2_route_t val) +{ + lsm6dso16is_int2_ctrl_t int2_ctrl; + lsm6dso16is_md2_cfg_t md2_cfg; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + if (ret == 0) + { + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MD2_CFG, (uint8_t *)&md2_cfg, 1); + } + + if (ret == 0) + { + int2_ctrl.int2_drdy_xl = val.drdy_xl; + int2_ctrl.int2_drdy_g = val.drdy_gy; + int2_ctrl.int2_drdy_temp = val.drdy_temp; + int2_ctrl.int2_sleep_ispu = val.ispu_sleep; + ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_INT2_CTRL, (uint8_t *)&int2_ctrl, + 1); + + md2_cfg.int2_ispu = val.ispu; + md2_cfg.int2_timestamp = val.timestamp; + ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MD2_CFG, (uint8_t *)&md2_cfg, 1); + } + + return ret; +} + +/** + * @brief It routes interrupt signals on INT 2 pin.[get] + * + * @param ctx read / write interface definitions + * @param val It routes interrupt signals on INT 2 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_pin_int2_route_get(stmdev_ctx_t *ctx, + lsm6dso16is_pin_int2_route_t *val) +{ + lsm6dso16is_int2_ctrl_t int2_ctrl; + lsm6dso16is_md2_cfg_t md2_cfg; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + if (ret == 0) + { + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MD2_CFG, (uint8_t *)&md2_cfg, 1); + } + + if (ret == 0) + { + val->drdy_xl = int2_ctrl.int2_drdy_xl; + val->drdy_gy = int2_ctrl.int2_drdy_g; + val->drdy_temp = int2_ctrl.int2_drdy_temp; + val->ispu_sleep = int2_ctrl.int2_sleep_ispu; + val->ispu = md2_cfg.int2_ispu; + val->timestamp = md2_cfg.int2_timestamp; + } + + return ret; +} + +/** + * @brief Push-pull/open-drain selection on INT1 and INT2 pins.[set] + * + * @param ctx read / write interface definitions + * @param val PUSH_PULL, OPEN_DRAIN, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_int_pin_mode_set(stmdev_ctx_t *ctx, + lsm6dso16is_int_pin_mode_t val) +{ + lsm6dso16is_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret == 0) + { + ctrl3_c.pp_od = ((uint8_t)val & 0x1U); + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + + return ret; +} + +/** + * @brief Push-pull/open-drain selection on INT1 and INT2 pins.[get] + * + * @param ctx read / write interface definitions + * @param val PUSH_PULL, OPEN_DRAIN, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_int_pin_mode_get(stmdev_ctx_t *ctx, + lsm6dso16is_int_pin_mode_t *val) +{ + lsm6dso16is_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + switch ((ctrl3_c.pp_od)) + { + case LSM6DSO16IS_PUSH_PULL: + *val = LSM6DSO16IS_PUSH_PULL; + break; + + case LSM6DSO16IS_OPEN_DRAIN: + *val = LSM6DSO16IS_OPEN_DRAIN; + break; + + default: + *val = LSM6DSO16IS_PUSH_PULL; + break; + } + return ret; +} + +/** + * @brief Interrupt activation level.[set] + * + * @param ctx read / write interface definitions + * @param val ACTIVE_HIGH, ACTIVE_LOW, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_pin_polarity_set(stmdev_ctx_t *ctx, + lsm6dso16is_pin_polarity_t val) +{ + lsm6dso16is_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret == 0) + { + ctrl3_c.h_lactive = ((uint8_t)val & 0x1U); + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + + return ret; +} + +/** + * @brief Interrupt activation level.[get] + * + * @param ctx read / write interface definitions + * @param val ACTIVE_HIGH, ACTIVE_LOW, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_pin_polarity_get(stmdev_ctx_t *ctx, + lsm6dso16is_pin_polarity_t *val) +{ + lsm6dso16is_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + switch ((ctrl3_c.h_lactive)) + { + case LSM6DSO16IS_ACTIVE_HIGH: + *val = LSM6DSO16IS_ACTIVE_HIGH; + break; + + case LSM6DSO16IS_ACTIVE_LOW: + *val = LSM6DSO16IS_ACTIVE_LOW; + break; + + default: + *val = LSM6DSO16IS_ACTIVE_HIGH; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Sensor hub + * @brief This section groups all the functions that manage the + * sensor hub. + * @{ + * + */ + +/** + * @brief Sensor hub output registers.[get] + * + * @param ctx read / write interface definitions + * @param val Sensor hub output registers. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_sh_read_data_raw_get(stmdev_ctx_t *ctx, + lsm6dso16is_emb_sh_read_t *val, + uint8_t len) +{ + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_SENSOR_HUB_1, (uint8_t *) val, + len); + } + if (ret == 0) + { + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + } + + + return ret; +} + +/** + * @brief Number of external sensors to be read by the sensor hub.[set] + * + * @param ctx read / write interface definitions + * @param val SLV_0, SLV_0_1, SLV_0_1_2, SLV_0_1_2_3, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_sh_slave_connected_set(stmdev_ctx_t *ctx, + lsm6dso16is_sh_slave_connected_t val) +{ + lsm6dso16is_master_config_t master_config; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + master_config.aux_sens_on = (uint8_t)val & 0x3U; + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief Number of external sensors to be read by the sensor hub.[get] + * + * @param ctx read / write interface definitions + * @param val SLV_0, SLV_0_1, SLV_0_1_2, SLV_0_1_2_3, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_sh_slave_connected_get(stmdev_ctx_t *ctx, + lsm6dso16is_sh_slave_connected_t *val) +{ + lsm6dso16is_master_config_t master_config; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + } + + switch (master_config.aux_sens_on) + { + case LSM6DSO16IS_SLV_0: + *val = LSM6DSO16IS_SLV_0; + break; + + case LSM6DSO16IS_SLV_0_1: + *val = LSM6DSO16IS_SLV_0_1; + break; + + case LSM6DSO16IS_SLV_0_1_2: + *val = LSM6DSO16IS_SLV_0_1_2; + break; + + case LSM6DSO16IS_SLV_0_1_2_3: + *val = LSM6DSO16IS_SLV_0_1_2_3; + break; + + default: + *val = LSM6DSO16IS_SLV_0; + break; + } + return ret; +} + +/** + * @brief Sensor hub I2C master enable.[set] + * + * @param ctx read / write interface definitions + * @param val Sensor hub I2C master enable. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dso16is_master_config_t master_config; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + master_config.master_on = val; + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief Sensor hub I2C master enable.[get] + * + * @param ctx read / write interface definitions + * @param val Sensor hub I2C master enable. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dso16is_master_config_t master_config; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + *val = master_config.master_on; + + if (ret == 0) + { + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief Sensor Hub master I2C pull-up enable.[set] + * + * @param ctx read / write interface definitions + * @param val Sensor Hub master I2C pull-up enable. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_sh_master_interface_pull_up_set(stmdev_ctx_t *ctx, + uint8_t val) +{ + lsm6dso16is_master_config_t master_config; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + master_config.shub_pu_en = val; + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief Sensor Hub master I2C pull-up enable.[get] + * + * @param ctx read / write interface definitions + * @param val Sensor Hub master I2C pull-up enable. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_sh_master_interface_pull_up_get(stmdev_ctx_t *ctx, + uint8_t *val) +{ + lsm6dso16is_master_config_t master_config; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + *val = master_config.shub_pu_en; + + if (ret == 0) + { + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief I2C interface pass-through.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of pass_through_mode in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dso16is_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dso16is_master_config_t master_config; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); + + if (ret == 0) + { + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + master_config.pass_through_mode = (uint8_t)val; + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief I2C interface pass-through.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of pass_through_mode in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dso16is_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dso16is_master_config_t master_config; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); + + if (ret == 0) + { + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + *val = master_config.pass_through_mode; + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief Sensor hub trigger signal selection.[set] + * + * @param ctx read / write interface definitions + * @param val SH_TRG_XL_GY_DRDY, SH_TRIG_INT2, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_sh_syncro_mode_set(stmdev_ctx_t *ctx, + lsm6dso16is_sh_syncro_mode_t val) +{ + lsm6dso16is_master_config_t master_config; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + master_config.start_config = (uint8_t)val & 0x01U; + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief Sensor hub trigger signal selection.[get] + * + * @param ctx read / write interface definitions + * @param val SH_TRG_XL_GY_DRDY, SH_TRIG_INT2, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_sh_syncro_mode_get(stmdev_ctx_t *ctx, + lsm6dso16is_sh_syncro_mode_t *val) +{ + lsm6dso16is_master_config_t master_config; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + } + + switch (master_config.start_config) + { + case LSM6DSO16IS_SH_TRG_XL_GY_DRDY: + *val = LSM6DSO16IS_SH_TRG_XL_GY_DRDY; + break; + + case LSM6DSO16IS_SH_TRIG_INT2: + *val = LSM6DSO16IS_SH_TRIG_INT2; + break; + + default: + *val = LSM6DSO16IS_SH_TRG_XL_GY_DRDY; + break; + } + return ret; +} + +/** + * @brief Slave 0 write operation is performed only at the first sensor hub cycle.[set] + * + * @param ctx read / write interface definitions + * @param val EACH_SH_CYCLE, ONLY_FIRST_CYCLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_sh_write_mode_set(stmdev_ctx_t *ctx, + lsm6dso16is_sh_write_mode_t val) +{ + lsm6dso16is_master_config_t master_config; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + master_config.write_once = (uint8_t)val & 0x01U; + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief Slave 0 write operation is performed only at the first sensor hub cycle.[get] + * + * @param ctx read / write interface definitions + * @param val EACH_SH_CYCLE, ONLY_FIRST_CYCLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_sh_write_mode_get(stmdev_ctx_t *ctx, + lsm6dso16is_sh_write_mode_t *val) +{ + lsm6dso16is_master_config_t master_config; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + } + + + switch (master_config.write_once) + { + case LSM6DSO16IS_EACH_SH_CYCLE: + *val = LSM6DSO16IS_EACH_SH_CYCLE; + break; + + case LSM6DSO16IS_ONLY_FIRST_CYCLE: + *val = LSM6DSO16IS_ONLY_FIRST_CYCLE; + break; + + default: + *val = LSM6DSO16IS_EACH_SH_CYCLE; + break; + } + return ret; +} + +/** + * @brief Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.[set] + * + * @param ctx read / write interface definitions + * @param val Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_sh_reset_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dso16is_master_config_t master_config; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + master_config.rst_master_regs = val; + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.[get] + * + * @param ctx read / write interface definitions + * @param val Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dso16is_master_config_t master_config; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + *val = master_config.rst_master_regs; + + if (ret == 0) + { + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief Configure slave 0 for perform a write.[set] + * + * @param ctx read / write interface definitions + * @param val a structure that contain + * - uint8_t slv1_add; 8 bit i2c device address + * - uint8_t slv1_subadd; 8 bit register device address + * - uint8_t slv1_data; 8 bit data to write + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_sh_cfg_write(stmdev_ctx_t *ctx, + lsm6dso16is_sh_cfg_write_t *val) +{ + lsm6dso16is_slv0_add_t reg; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + reg.slave0_add = val->slv0_add; + reg.rw_0 = 0; + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV0_ADD, (uint8_t *)®, 1); + } + + if (ret == 0) + { + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV0_SUBADD, + &(val->slv0_subadd), 1); + } + + if (ret == 0) + { + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_DATAWRITE_SLV0, + &(val->slv0_data), 1); + } + + if (ret == 0) + { + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief Rate at which the master communicates.[set] + * + * @param ctx read / write interface definitions + * @param val SH_12_5Hz, SH_26Hz, SH_52Hz, SH_104Hz + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_sh_data_rate_set(stmdev_ctx_t *ctx, + lsm6dso16is_sh_data_rate_t val) +{ + lsm6dso16is_slv0_config_t slv0_config; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_SLAVE0_CONFIG, (uint8_t *)&slv0_config, 1); + } + + if (ret == 0) + { + slv0_config.shub_odr = (uint8_t)val & 0x07U; + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLAVE0_CONFIG, (uint8_t *)&slv0_config, 1); + } + if (ret == 0) + { + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief Rate at which the master communicates.[get] + * + * @param ctx read / write interface definitions + * @param val SH_12_5Hz, SH_26Hz, SH_52Hz, SH_104Hz + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_sh_data_rate_get(stmdev_ctx_t *ctx, + lsm6dso16is_sh_data_rate_t *val) +{ + lsm6dso16is_slv0_config_t slv0_config; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_SLAVE0_CONFIG, (uint8_t *)&slv0_config, 1); + } + if (ret == 0) + { + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + } + + switch (slv0_config.shub_odr) + { + case LSM6DSO16IS_SH_12_5Hz: + *val = LSM6DSO16IS_SH_12_5Hz; + break; + + case LSM6DSO16IS_SH_26Hz: + *val = LSM6DSO16IS_SH_26Hz; + break; + + case LSM6DSO16IS_SH_52Hz: + *val = LSM6DSO16IS_SH_52Hz; + break; + + case LSM6DSO16IS_SH_104Hz: + *val = LSM6DSO16IS_SH_104Hz; + break; + + default: + *val = LSM6DSO16IS_SH_12_5Hz; + break; + } + return ret; +} + +/** + * @brief Configure slave 0 for perform a read.[set] + * + * @param ctx read / write interface definitions + * @param val Structure that contain + * - uint8_t slv1_add; 8 bit i2c device address + * - uint8_t slv1_subadd; 8 bit register device address + * - uint8_t slv1_len; num of bit to read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_sh_slv0_cfg_read(stmdev_ctx_t *ctx, + lsm6dso16is_sh_cfg_read_t *val) +{ + lsm6dso16is_slv0_add_t slv0_add; + lsm6dso16is_slv0_config_t slv0_config; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); + + if (ret == 0) + { + slv0_add.slave0_add = val->slv_add; + slv0_add.rw_0 = 1; + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV0_ADD, (uint8_t *)&slv0_add, 1); + } + + if (ret == 0) + { + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV0_SUBADD, + &(val->slv_subadd), 1); + } + + if (ret == 0) + { + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_SLAVE0_CONFIG, + (uint8_t *)&slv0_config, 1); + } + + if (ret == 0) + { + slv0_config.slave0_numop = val->slv_len; + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLAVE0_CONFIG, + (uint8_t *)&slv0_config, 1); + } + + if (ret == 0) + { + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief Configure slave 0 for perform a write/read.[set] + * + * @param ctx read / write interface definitions + * @param val Structure that contain + * - uint8_t slv1_add; 8 bit i2c device address + * - uint8_t slv1_subadd; 8 bit register device address + * - uint8_t slv1_len; num of bit to read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_sh_slv1_cfg_read(stmdev_ctx_t *ctx, + lsm6dso16is_sh_cfg_read_t *val) +{ + lsm6dso16is_slv1_add_t slv1_add; + lsm6dso16is_slv1_config_t slv1_config; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); + + if (ret == 0) + { + slv1_add.slave1_add = val->slv_add; + slv1_add.r_1 = 1; + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV1_ADD, (uint8_t *)&slv1_add, 1); + } + + if (ret == 0) + { + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV1_SUBADD, + &(val->slv_subadd), 1); + } + + if (ret == 0) + { + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_SLAVE1_CONFIG, + (uint8_t *)&slv1_config, 1); + } + + if (ret == 0) + { + slv1_config.slave1_numop = val->slv_len; + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLAVE1_CONFIG, + (uint8_t *)&slv1_config, 1); + } + + if (ret == 0) + { + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief Configure slave 0 for perform a write/read.[set] + * + * @param ctx read / write interface definitions + * @param val Structure that contain + * - uint8_t slv2_add; 8 bit i2c device address + * - uint8_t slv2_subadd; 8 bit register device address + * - uint8_t slv2_len; num of bit to read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_sh_slv2_cfg_read(stmdev_ctx_t *ctx, + lsm6dso16is_sh_cfg_read_t *val) +{ + lsm6dso16is_slv2_add_t slv2_add; + lsm6dso16is_slv2_config_t slv2_config; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); + + if (ret == 0) + { + slv2_add.slave2_add = val->slv_add; + slv2_add.r_2 = 1; + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV2_ADD, (uint8_t *)&slv2_add, 1); + } + + if (ret == 0) + { + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV2_SUBADD, + &(val->slv_subadd), 1); + } + + if (ret == 0) + { + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_SLAVE2_CONFIG, + (uint8_t *)&slv2_config, 1); + } + + if (ret == 0) + { + slv2_config.slave2_numop = val->slv_len; + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLAVE2_CONFIG, + (uint8_t *)&slv2_config, 1); + } + + if (ret == 0) + { + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief Configure slave 0 for perform a write/read.[set] + * + * @param ctx read / write interface definitions + * @param val Structure that contain + * - uint8_t slv3_add; 8 bit i2c device address + * - uint8_t slv3_subadd; 8 bit register device address + * - uint8_t slv3_len; num of bit to read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_sh_slv3_cfg_read(stmdev_ctx_t *ctx, + lsm6dso16is_sh_cfg_read_t *val) +{ + lsm6dso16is_slv3_add_t slv3_add; + lsm6dso16is_slv3_config_t slv3_config; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); + + if (ret == 0) + { + slv3_add.slave3_add = val->slv_add; + slv3_add.r_3 = 1; + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV3_ADD, (uint8_t *)&slv3_add, 1); + } + + if (ret == 0) + { + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV3_SUBADD, + &(val->slv_subadd), 1); + } + + if (ret == 0) + { + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_SLAVE3_CONFIG, + (uint8_t *)&slv3_config, 1); + } + + if (ret == 0) + { + slv3_config.slave3_numop = val->slv_len; + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLAVE3_CONFIG, + (uint8_t *)&slv3_config, 1); + } + + if (ret == 0) + { + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ispu + * @brief ispu + * @{/ + * + */ +/** + * @brief Software reset of ISPU core.[set] + * + * @param ctx read / write interface definitions + * @param val Software reset of ISPU core. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_ispu_reset_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dso16is_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + if (ret == 0) + { + func_cfg_access.sw_reset_ispu = val; + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Software reset of ISPU core.[get] + * + * @param ctx read / write interface definitions + * @param val Software reset of ISPU core. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_ispu_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dso16is_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + *val = func_cfg_access.sw_reset_ispu; + + + return ret; +} + +int32_t lsm6dso16is_ispu_clock_set(stmdev_ctx_t *ctx, + lsm6dso16is_ispu_clock_sel_t val) +{ + lsm6dso16is_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + if (ret == 0) + { + ctrl10_c.ispu_clk_sel = (uint8_t)val; + ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL10_C, (uint8_t *)&ctrl10_c, + 1); + } + + return ret; +} + +int32_t lsm6dso16is_ispu_clock_get(stmdev_ctx_t *ctx, + lsm6dso16is_ispu_clock_sel_t *val) +{ + lsm6dso16is_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + switch (ctrl10_c.ispu_clk_sel) + { + default: + case 0: + *val = LSM6DSO16IS_ISPU_CLK_5MHz; + break; + case 1: + *val = LSM6DSO16IS_ISPU_CLK_10MHz; + break; + } + + return ret; +} + +/** + * @brief ISPU irq rate selection.[set] + * + * @param ctx read / write interface definitions + * @param val ISPU_ODR_OFF, ISPU_ODR_AT_12Hz5, ISPU_ODR_AT_26Hz, ISPU_ODR_AT_52Hz, + * ISPU_ODR_AT_104Hz, ISPU_ODR_AT_208Hz, ISPU_ODR_AT_417Hz, ISPU_ODR_AT_833Hz, + * ISPU_ODR_AT_1667Hz, ISPU_ODR_AT_3333Hz, ISPU_ODR_AT_6667Hz + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_ispu_data_rate_set(stmdev_ctx_t *ctx, + lsm6dso16is_ispu_data_rate_t val) +{ + lsm6dso16is_ctrl9_c_t ctrl9_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1); + + if (ret == 0) + { + ctrl9_c.ispu_rate = ((uint8_t)val & 0xfU); + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1); + } + + return ret; +} + +/** + * @brief ISPU irq rate selection.[get] + * + * @param ctx read / write interface definitions + * @param val ISPU_ODR_OFF, ISPU_ODR_AT_12Hz5, ISPU_ODR_AT_26Hz, ISPU_ODR_AT_52Hz, + * ISPU_ODR_AT_104Hz, ISPU_ODR_AT_208Hz, ISPU_ODR_AT_417Hz, ISPU_ODR_AT_833Hz, + * ISPU_ODR_AT_1667Hz, ISPU_ODR_AT_3333Hz, ISPU_ODR_AT_6667Hz + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_ispu_data_rate_get(stmdev_ctx_t *ctx, + lsm6dso16is_ispu_data_rate_t *val) +{ + lsm6dso16is_ctrl9_c_t ctrl9_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1); + + switch ((ctrl9_c.ispu_rate)) + { + case LSM6DSO16IS_ISPU_ODR_OFF: + *val = LSM6DSO16IS_ISPU_ODR_OFF; + break; + + case LSM6DSO16IS_ISPU_ODR_AT_12Hz5: + *val = LSM6DSO16IS_ISPU_ODR_AT_12Hz5; + break; + + case LSM6DSO16IS_ISPU_ODR_AT_26Hz: + *val = LSM6DSO16IS_ISPU_ODR_AT_26Hz; + break; + + case LSM6DSO16IS_ISPU_ODR_AT_52Hz: + *val = LSM6DSO16IS_ISPU_ODR_AT_52Hz; + break; + + case LSM6DSO16IS_ISPU_ODR_AT_104Hz: + *val = LSM6DSO16IS_ISPU_ODR_AT_104Hz; + break; + + case LSM6DSO16IS_ISPU_ODR_AT_208Hz: + *val = LSM6DSO16IS_ISPU_ODR_AT_208Hz; + break; + + case LSM6DSO16IS_ISPU_ODR_AT_416Hz: + *val = LSM6DSO16IS_ISPU_ODR_AT_416Hz; + break; + + case LSM6DSO16IS_ISPU_ODR_AT_833Hz: + *val = LSM6DSO16IS_ISPU_ODR_AT_833Hz; + break; + + case LSM6DSO16IS_ISPU_ODR_AT_1667Hz: + *val = LSM6DSO16IS_ISPU_ODR_AT_1667Hz; + break; + + case LSM6DSO16IS_ISPU_ODR_AT_3333Hz: + *val = LSM6DSO16IS_ISPU_ODR_AT_3333Hz; + break; + + case LSM6DSO16IS_ISPU_ODR_AT_6667Hz: + *val = LSM6DSO16IS_ISPU_ODR_AT_6667Hz; + break; + + default: + *val = LSM6DSO16IS_ISPU_ODR_OFF; + break; + } + return ret; +} + +/** + * @brief ISPU bdu selection.[set] + * + * @param ctx read / write interface definitions + * @param val ISPU_BDU_OFF, ISPU_BDU_ON_2B_4B, ISPU_BDU_ON_2B_2B, ISPU_BDU_ON_4B_4B, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_ispu_bdu_set(stmdev_ctx_t *ctx, lsm6dso16is_ispu_bdu_t val) +{ + lsm6dso16is_ctrl9_c_t ctrl9_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1); + + if (ret == 0) + { + ctrl9_c.ispu_bdu = ((uint8_t)val & 0x3U); + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1); + } + + return ret; +} + +/** + * @brief ISPU bdu selection.[get] + * + * @param ctx read / write interface definitions + * @param val ISPU_BDU_OFF, ISPU_BDU_ON_2B_4B, ISPU_BDU_ON_2B_2B, ISPU_BDU_ON_4B_4B, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_ispu_bdu_get(stmdev_ctx_t *ctx, lsm6dso16is_ispu_bdu_t *val) +{ + lsm6dso16is_ctrl9_c_t ctrl9_c; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1); + + switch ((ctrl9_c.ispu_rate)) + { + case LSM6DSO16IS_ISPU_BDU_OFF: + *val = LSM6DSO16IS_ISPU_BDU_OFF; + break; + + case LSM6DSO16IS_ISPU_BDU_ON_2B_4B: + *val = LSM6DSO16IS_ISPU_BDU_ON_2B_4B; + break; + + case LSM6DSO16IS_ISPU_BDU_ON_2B_2B: + *val = LSM6DSO16IS_ISPU_BDU_ON_2B_2B; + break; + + case LSM6DSO16IS_ISPU_BDU_ON_4B_4B: + *val = LSM6DSO16IS_ISPU_BDU_ON_4B_4B; + break; + + default: + *val = LSM6DSO16IS_ISPU_BDU_OFF; + break; + } + return ret; +} + +/** + * @brief Generic Interrupt Flags from ISPU.[get] + * + * @param ctx read / write interface definitions + * @param val Generic Interrupt Flags from ISPU. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_ia_ispu_get(stmdev_ctx_t *ctx, uint32_t *val) +{ + uint8_t buff[4]; + int32_t ret; + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_INT_STATUS0_MAINPAGE, &buff[0], 4); + + *val = (uint32_t)buff[3]; + *val = (*val * 256U) + (uint32_t)buff[2]; + *val = (*val * 256U) + (uint32_t)buff[1]; + *val = (*val * 256U) + (uint32_t)buff[0]; + + return ret; +} + +/** + * @brief General purpose input configuration register for ISPU[set] + * + * @param ctx read / write interface definitions + * @param offset offset from ISPU_DUMMY_CFG_1 register + * @param val General purpose input configuration register for ISPU + * @param len number of bytes to write + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_ispu_write_dummy_cfg(stmdev_ctx_t *ctx, uint8_t offset, + uint8_t *val, uint8_t len) +{ + int32_t ret; + + /* check if we are writing outside of the range */ + if (LSM6DSO16IS_ISPU_DUMMY_CFG_1_L + offset + len > + LSM6DSO16IS_ISPU_DUMMY_CFG_4_H) + { + return -1; + } + + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_DUMMY_CFG_1_L + offset, val, len); + + return ret; +} + +/** + * @brief General purpose input configuration register for ISPU[set] + * + * @param ctx read / write interface definitions + * @param offset offset from ISPU_DUMMY_CFG_1 register + * @param val General purpose input configuration register for ISPU + * @param len number of bytes to write + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_ispu_ready_dummy_cfg(stmdev_ctx_t *ctx, uint8_t offset, + uint8_t *val, uint8_t len) +{ + int32_t ret; + + /* check if we are reading outside of the range */ + if (LSM6DSO16IS_ISPU_DUMMY_CFG_1_L + offset + len > + LSM6DSO16IS_ISPU_DUMMY_CFG_4_H) + { + return -1; + } + + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_DUMMY_CFG_1_L + offset, val, len); + + return ret; +} + +/** + * @brief Boot ISPU core[set] + * + * @param ctx read / write interface definitions + * @param val Boot ISPU core + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_ispu_boot_set(stmdev_ctx_t *ctx, + lsm6dso16is_ispu_boot_latched_t val) +{ + lsm6dso16is_ispu_config_t ispu_config; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK); + + if (ret == 0) + { + ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, + (uint8_t *)&ispu_config, 1); + } + + if (ret == 0) + { + ispu_config.ispu_rst_n = (uint8_t)val; + ispu_config.clk_dis = (uint8_t)val; + ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, + (uint8_t *)&ispu_config, + 1); + } + + ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Boot ISPU core[get] + * + * @param ctx read / write interface definitions + * @param val Boot ISPU core + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_ispu_boot_get(stmdev_ctx_t *ctx, + lsm6dso16is_ispu_boot_latched_t *val) +{ + lsm6dso16is_ispu_config_t ispu_config; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK); + + if (ret == 0) + { + ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, + (uint8_t *)&ispu_config, 1); + } + + *val = LSM6DSO16IS_ISPU_TURN_OFF; + if (ispu_config.ispu_rst_n == 1U || ispu_config.clk_dis == 1U) + { + *val = LSM6DSO16IS_ISPU_TURN_ON; + } + + ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enables latched ISPU interrupt.[set] + * + * @param ctx read / write interface definitions + * @param val ISPU_INT_PULSED, ISPU_INT_LATCHED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_ispu_int_latched_set(stmdev_ctx_t *ctx, + lsm6dso16is_ispu_int_latched_t val) +{ + lsm6dso16is_ispu_config_t ispu_config; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK); + + if (ret == 0) + { + ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, + (uint8_t *)&ispu_config, 1); + } + + if (ret == 0) + { + ispu_config.latched = ((uint8_t)val & 0x1U); + ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, + (uint8_t *)&ispu_config, + 1); + } + + ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enables latched ISPU interrupt.[get] + * + * @param ctx read / write interface definitions + * @param val ISPU_INT_PULSED, ISPU_INT_LATCHED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_ispu_int_latched_get(stmdev_ctx_t *ctx, + lsm6dso16is_ispu_int_latched_t *val) +{ + lsm6dso16is_ispu_config_t ispu_config; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK); + + if (ret == 0) + { + ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, + (uint8_t *)&ispu_config, 1); + } + + ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + + switch ((ispu_config.latched)) + { + case LSM6DSO16IS_ISPU_INT_PULSED: + *val = LSM6DSO16IS_ISPU_INT_PULSED; + break; + + case LSM6DSO16IS_ISPU_INT_LATCHED: + *val = LSM6DSO16IS_ISPU_INT_LATCHED; + break; + + default: + *val = LSM6DSO16IS_ISPU_INT_PULSED; + break; + } + return ret; +} + +/** + * @brief returns ISPU boot status + * + * @param ctx read / write interface definitions + * @param val LSM6DSO16IS_ISPU_BOOT_IN_PROGRESS, LSM6DSO16IS_ISPU_BOOT_ENDED + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_ispu_get_boot_status(stmdev_ctx_t *ctx, + lsm6dso16is_ispu_boot_end_t *val) +{ + lsm6dso16is_ispu_status_t ispu_boot_status; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK); + if (ret == 0) + { + ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_STATUS, + (uint8_t *)&ispu_boot_status, 1); + *val = (lsm6dso16is_ispu_boot_end_t)ispu_boot_status.boot_end; + ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + } + + return ret; +} + +static int32_t lsm6dso16is_ispu_sel_memory_addr(stmdev_ctx_t *ctx, uint16_t mem_addr) +{ + uint8_t mem_addr_l, mem_addr_h; + int32_t ret = 0; + + mem_addr_l = (uint8_t)(mem_addr & 0xFFU); + mem_addr_h = (uint8_t)(mem_addr / 256U); + ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_MEM_ADDR1, + (uint8_t *)&mem_addr_h, 1); + ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_MEM_ADDR0, + (uint8_t *)&mem_addr_l, 1); + + return ret; +} + +/** + * @brief ISPU write memory + * + * @param ctx read / write interface definitions + * @param mem_sel LSM6DSO16IS_ISPU_DATA_RAM_MEMORY, LSM6DSO16IS_ISPU_PROGRAM_RAM_MEMORY + * @param mem_addr memory address + * @param mem_data memory data + * @param len data length + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_ispu_write_memory(stmdev_ctx_t *ctx, + lsm6dso16is_ispu_memory_type_t mem_sel, + uint16_t mem_addr, uint8_t *mem_data, uint16_t len) +{ + lsm6dso16is_ispu_mem_sel_t ispu_mem_sel; + int32_t ret; + uint16_t i; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK); + if (ret == 0) + { + /* select memory to be written */ + ispu_mem_sel.read_mem_en = 0; + ispu_mem_sel.mem_sel = (uint8_t)mem_sel; + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_MEM_SEL, (uint8_t *)&ispu_mem_sel, 1); + + if (mem_sel == LSM6DSO16IS_ISPU_PROGRAM_RAM_MEMORY) + { + uint16_t addr_s[4] = {0U, 0U, 0U, 0U}; + uint16_t len_s[4] = {0U, 0U, 0U, 0U}; + uint8_t j = 0; + uint16_t k; + + addr_s[0] = mem_addr; + for (i = 0, k = 0; i < len; i++, k++) + { + if ((mem_addr + i == 0x2000U) || (mem_addr + i == 0x4000U) || (mem_addr + i == 0x6000U)) + { + len_s[j++] = k; + addr_s[j] = mem_addr + i; + k = 0; + } + } + len_s[j++] = k; + + for (i = 0, k = 0; i < j; k+=len_s[i], i++) + { + ret += lsm6dso16is_ispu_sel_memory_addr(ctx, addr_s[i]); + ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_MEM_DATA, &mem_data[k], len_s[i]); + } + } else { + /* select memory address */ + ret += lsm6dso16is_ispu_sel_memory_addr(ctx, mem_addr); + ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_MEM_DATA, &mem_data[0], len); + } + } + + ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief ISPU read memory + * + * @param ctx read / write interface definitions + * @param mem_sel LSM6DSO16IS_ISPU_DATA_RAM_MEMORY, LSM6DSO16IS_ISPU_PROGRAM_RAM_MEMORY + * @param mem_addr memory address + * @param mem_data memory data + * @param len data length + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_ispu_read_memory(stmdev_ctx_t *ctx, + lsm6dso16is_ispu_memory_type_t mem_sel, + uint16_t mem_addr, uint8_t *mem_data, uint16_t len) +{ + lsm6dso16is_ispu_mem_sel_t ispu_mem_sel; + int32_t ret; + uint8_t dummy; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK); + if (ret == 0) + { + /* select memory to be read */ + ispu_mem_sel.read_mem_en = 1; + ispu_mem_sel.mem_sel = (uint8_t)mem_sel; + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_MEM_SEL, (uint8_t *)&ispu_mem_sel, 1); + + /* select memory address */ + ret += lsm6dso16is_ispu_sel_memory_addr(ctx, mem_addr); + ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_MEM_DATA, &dummy, 1); + + ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_MEM_DATA, &mem_data[0], len); + } + + ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief ISPU write flags (IF2S) + * + * @param ctx read / write interface definitions + * @param data ISPU flags + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_ispu_write_flags(stmdev_ctx_t *ctx, uint16_t data) +{ + lsm6dso16is_ispu_if2s_flag_l_t flag_l; + lsm6dso16is_ispu_if2s_flag_h_t flag_h; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK); + if (ret == 0) + { + /* write the flags */ + flag_h.if2s = (uint8_t)(data / 256U); + ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_IF2S_FLAG_H, + (uint8_t *)&flag_h, + 1); + flag_l.if2s = (uint8_t)(data & 0xffU); + ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_IF2S_FLAG_L, + (uint8_t *)&flag_l, + 1); + } + + ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief ISPU read flags (S2IF) + * + * @param ctx read / write interface definitions + * @param data ISPU flags + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_ispu_read_flags(stmdev_ctx_t *ctx, uint16_t *data) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK); + if (ret == 0) + { + /* read the flags */ + ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_S2IF_FLAG_L, buff, 2); + data[0] = (uint16_t)buff[1]; + data[0] = (data[0] * 256U) + (uint16_t)buff[0]; + } + + ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief ISPU clear flags (S2IF) + * + * @param ctx read / write interface definitions + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_ispu_clear_flags(stmdev_ctx_t *ctx) +{ + uint8_t data = 1; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK); + + if (ret == 0) + { + ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_S2IF_FLAG_H, &data, 1); + ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + } + + return ret; +} + +/** + * @brief ISPU DOUT registers.[get] + * + * @param ctx read / write interface definitions + * @param val ISPU DOUT output registers. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_ispu_read_data_raw_get(stmdev_ctx_t *ctx, + uint8_t *val, + uint8_t len) +{ + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK); + if (ret == 0) + { + ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_DOUT_00_L, (uint8_t *) val, + len); + } + + ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief ISPU int1_ctrl.[get] + * + * @param ctx read / write interface definitions + * @param val ISPU int1_ctrl register value + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_ispu_int1_ctrl_get(stmdev_ctx_t *ctx, uint32_t *val) +{ + uint8_t buff[4]; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK); + if (ret == 0) + { + /* read int1_ctrl reg */ + ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_INT1_CTRL0, &buff[0], 4); + + *val = (uint32_t)buff[3]; + *val = (*val * 256U) + (uint32_t)buff[2]; + *val = (*val * 256U) + (uint32_t)buff[1]; + *val = (*val * 256U) + (uint32_t)buff[0]; + } + + ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief ISPU int1_ctrl.[set] + * + * @param ctx read / write interface definitions + * @param val ISPU int1_ctrl register value + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_ispu_int1_ctrl_set(stmdev_ctx_t *ctx, uint32_t val) +{ + lsm6dso16is_ispu_int1_ctrl0_t int1_ctrl0; + lsm6dso16is_ispu_int1_ctrl1_t int1_ctrl1; + lsm6dso16is_ispu_int1_ctrl2_t int1_ctrl2; + lsm6dso16is_ispu_int1_ctrl3_t int1_ctrl3; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK); + if (ret == 0) + { + /* write the int1_ctrl reg */ + int1_ctrl3.ispu_int1_ctrl = (uint8_t)((val >> 24) & 0xffU); + ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_INT1_CTRL3, + (uint8_t *)&int1_ctrl3, + 1); + + int1_ctrl2.ispu_int1_ctrl = (uint8_t)((val >> 16) & 0xffU); + ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_INT1_CTRL2, + (uint8_t *)&int1_ctrl2, + 1); + + int1_ctrl1.ispu_int1_ctrl = (uint8_t)((val >> 8) & 0xffU); + ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_INT1_CTRL1, + (uint8_t *)&int1_ctrl1, + 1); + + int1_ctrl0.ispu_int1_ctrl = (uint8_t)(val & 0xffU); + ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_INT1_CTRL0, + (uint8_t *)&int1_ctrl0, + 1); + } + + ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief ISPU int2_ctrl.[get] + * + * @param ctx read / write interface definitions + * @param val ISPU int2_ctrl register value + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_ispu_int2_ctrl_get(stmdev_ctx_t *ctx, uint32_t *val) +{ + uint8_t buff[4]; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK); + if (ret == 0) + { + /* read int2_ctrl reg */ + ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_INT2_CTRL0, &buff[0], 4); + + *val = (uint32_t)buff[3]; + *val = (*val * 256U) + (uint32_t)buff[2]; + *val = (*val * 256U) + (uint32_t)buff[1]; + *val = (*val * 256U) + (uint32_t)buff[0]; + } + + ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief ISPU int2_ctrl.[set] + * + * @param ctx read / write interface definitions + * @param val ISPU int2_ctrl register value + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_ispu_int2_ctrl_set(stmdev_ctx_t *ctx, uint32_t val) +{ + lsm6dso16is_ispu_int2_ctrl0_t int2_ctrl0; + lsm6dso16is_ispu_int2_ctrl1_t int2_ctrl1; + lsm6dso16is_ispu_int2_ctrl2_t int2_ctrl2; + lsm6dso16is_ispu_int2_ctrl3_t int2_ctrl3; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK); + if (ret == 0) + { + /* write the int2_ctrl reg */ + int2_ctrl3.ispu_int2_ctrl = (uint8_t)((val >> 24) & 0xffU); + ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_INT2_CTRL3, + (uint8_t *)&int2_ctrl3, + 1); + + int2_ctrl2.ispu_int2_ctrl = (uint8_t)((val >> 16) & 0xffU); + ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_INT2_CTRL2, + (uint8_t *)&int2_ctrl2, + 1); + + int2_ctrl1.ispu_int2_ctrl = (uint8_t)((val >> 8) & 0xffU); + ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_INT2_CTRL1, + (uint8_t *)&int2_ctrl1, + 1); + + int2_ctrl0.ispu_int2_ctrl = (uint8_t)(val & 0xffU); + ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_INT2_CTRL0, + (uint8_t *)&int2_ctrl0, + 1); + } + + ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief ISPU int_status.[get] + * + * @param ctx read / write interface definitions + * @param val ISPU int2_status register value + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_ispu_int_status_get(stmdev_ctx_t *ctx, uint32_t *val) +{ + uint8_t buff[4]; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK); + if (ret == 0) + { + /* read int2_ctrl reg */ + ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_INT_STATUS0, &buff[0], 4); + + *val = (uint32_t)buff[3]; + *val = (*val * 256U) + (uint32_t)buff[2]; + *val = (*val * 256U) + (uint32_t)buff[1]; + *val = (*val * 256U) + (uint32_t)buff[0]; + } + + ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief ISPU algo.[get] + * + * @param ctx read / write interface definitions + * @param val ISPU algo register value + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_ispu_algo_get(stmdev_ctx_t *ctx, uint32_t *val) +{ + uint8_t buff[4]; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK); + if (ret == 0) + { + /* read int2_ctrl reg */ + ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_ALGO0, &buff[0], 4); + + *val = (uint32_t)buff[3]; + *val = (*val * 256U) + (uint32_t)buff[2]; + *val = (*val * 256U) + (uint32_t)buff[1]; + *val = (*val * 256U) + (uint32_t)buff[0]; + } + + ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief ISPU algo.[set] + * + * @param ctx read / write interface definitions + * @param val ISPU algo register value + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dso16is_ispu_algo_set(stmdev_ctx_t *ctx, uint32_t val) +{ + lsm6dso16is_ispu_algo0_t algo0; + lsm6dso16is_ispu_algo1_t algo1; + lsm6dso16is_ispu_algo2_t algo2; + lsm6dso16is_ispu_algo3_t algo3; + int32_t ret; + + ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK); + if (ret == 0) + { + /* write the algo reg */ + algo3.ispu_algo = (uint8_t)((val >> 24) & 0xffU); + ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_ALGO3, (uint8_t *)&algo3, 1); + + algo2.ispu_algo = (uint8_t)((val >> 16) & 0xffU); + ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_ALGO2, (uint8_t *)&algo2, 1); + + algo1.ispu_algo = (uint8_t)((val >> 8) & 0xffU); + ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_ALGO1, (uint8_t *)&algo1, 1); + + algo0.ispu_algo = (uint8_t)(val & 0xffU); + ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_ALGO0, (uint8_t *)&algo0, 1); + } + + ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ diff --git a/sensor/stmemsc/lsm6dso16is_STdC/driver/lsm6dso16is_reg.h b/sensor/stmemsc/lsm6dso16is_STdC/driver/lsm6dso16is_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..018fa8f4be85b4ffadea8318ae7b29bd1d607972 --- /dev/null +++ b/sensor/stmemsc/lsm6dso16is_STdC/driver/lsm6dso16is_reg.h @@ -0,0 +1,2840 @@ +/** + ****************************************************************************** + * @file lsm6dso16is_reg.h + * @author Sensors Software Solution Team + * @brief This file contains all the functions prototypes for the + * lsm6dso16is_reg.c driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2022 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef LSM6DSO16IS_REGS_H +#define LSM6DSO16IS_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include + +/** @addtogroup LSM6DSO16IS + * @{ + * + */ + +/** @defgroup Endianness definitions + * @{ + * + */ + +#ifndef DRV_BYTE_ORDER +#ifndef __BYTE_ORDER__ + +#define DRV_LITTLE_ENDIAN 1234 +#define DRV_BIG_ENDIAN 4321 + +/** if _BYTE_ORDER is not defined, choose the endianness of your architecture + * by uncommenting the define which fits your platform endianness + */ +//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN +#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN + +#else /* defined __BYTE_ORDER__ */ + +#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ +#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ +#define DRV_BYTE_ORDER __BYTE_ORDER__ + +#endif /* __BYTE_ORDER__*/ +#endif /* DRV_BYTE_ORDER */ + +/** + * @} + * + */ + +/** @defgroup STMicroelectronics sensors common types + * @{ + * + */ + +#ifndef MEMS_SHARED_TYPES +#define MEMS_SHARED_TYPES + +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} bitwise_t; + +#define PROPERTY_DISABLE (0U) +#define PROPERTY_ENABLE (1U) + +/** @addtogroup Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); +typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); + +typedef struct +{ + /** Component mandatory fields **/ + stmdev_write_ptr write_reg; + stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; + /** Customizable optional pointer **/ + void *handle; +} stmdev_ctx_t; + +/** + * @} + * + */ + +#endif /* MEMS_SHARED_TYPES */ + +#ifndef MEMS_UCF_SHARED_TYPES +#define MEMS_UCF_SHARED_TYPES + +/** @defgroup Generic address-data structure definition + * @brief This structure is useful to load a predefined configuration + * of a sensor. + * You can create a sensor configuration by your own or using + * Unico / Unicleo tools available on STMicroelectronics + * web site. + * + * @{ + * + */ + +typedef struct +{ + uint8_t address; + uint8_t data; +} ucf_line_t; + +/** + * @} + * + */ + +#endif /* MEMS_UCF_SHARED_TYPES */ + +/** + * @} + * + */ + +/** @defgroup LSM6DSO16IS_Infos + * @{ + * + */ + +/** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ +#define LSM6DSO16IS_I2C_ADD_L 0xD5U +#define LSM6DSO16IS_I2C_ADD_H 0xD7U + +/** Device Identification (Who am I) **/ +#define LSM6DSO16IS_ID 0x22U + +/** + * @} + * + */ + +/** @defgroup bitfields page main + * @{ + * + */ + +#define LSM6DSO16IS_FUNC_CFG_ACCESS 0x1U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t sw_reset_ispu : 1; + uint8_t not_used1 : 4; + uint8_t shub_reg_access : 1; + uint8_t ispu_reg_access : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_reg_access : 1; + uint8_t shub_reg_access : 1; + uint8_t not_used1 : 4; + uint8_t sw_reset_ispu : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_func_cfg_access_t; + +#define LSM6DSO16IS_PIN_CTRL 0x2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 6; + uint8_t sdo_pu_en : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t sdo_pu_en : 1; + uint8_t not_used0 : 6; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_pin_ctrl_t; + +#define LSM6DSO16IS_DRDY_PULSED_REG 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 7; + uint8_t drdy_pulsed : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t drdy_pulsed : 1; + uint8_t not_used0 : 7; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_drdy_pulsed_reg_t; + +#define LSM6DSO16IS_INT1_CTRL 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_drdy_xl : 1; + uint8_t int1_drdy_g : 1; + uint8_t int1_boot : 1; + uint8_t not_used0 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 5; + uint8_t int1_boot : 1; + uint8_t int1_drdy_g : 1; + uint8_t int1_drdy_xl : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_int1_ctrl_t; + +#define LSM6DSO16IS_INT2_CTRL 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_drdy_xl : 1; + uint8_t int2_drdy_g : 1; + uint8_t int2_drdy_temp : 1; + uint8_t not_used0 : 4; + uint8_t int2_sleep_ispu : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_sleep_ispu : 1; + uint8_t not_used0 : 4; + uint8_t int2_drdy_temp : 1; + uint8_t int2_drdy_g : 1; + uint8_t int2_drdy_xl : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_int2_ctrl_t; + +#define LSM6DSO16IS_WHO_AM_I 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t id : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t id : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_who_am_i_t; + +#define LSM6DSO16IS_CTRL1_XL 0x10U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t fs_xl : 2; + uint8_t odr_xl : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t odr_xl : 4; + uint8_t fs_xl : 2; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ctrl1_xl_t; + +#define LSM6DSO16IS_CTRL2_G 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t fs_125 : 1; + uint8_t fs_g : 2; + uint8_t odr_g : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t odr_g : 4; + uint8_t fs_g : 2; + uint8_t fs_125 : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ctrl2_g_t; + +#define LSM6DSO16IS_CTRL3_C 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sw_reset : 1; + uint8_t not_used0 : 1; + uint8_t if_inc : 1; + uint8_t sim : 1; + uint8_t pp_od : 1; + uint8_t h_lactive : 1; + uint8_t bdu : 1; + uint8_t boot : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t boot : 1; + uint8_t bdu : 1; + uint8_t h_lactive : 1; + uint8_t pp_od : 1; + uint8_t sim : 1; + uint8_t if_inc : 1; + uint8_t not_used0 : 1; + uint8_t sw_reset : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ctrl3_c_t; + +#define LSM6DSO16IS_CTRL4_C 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t i2c_disable : 1; + uint8_t not_used1 : 2; + uint8_t int2_on_int1 : 1; + uint8_t sleep_g : 1; + uint8_t not_used2 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used2 : 1; + uint8_t sleep_g : 1; + uint8_t int2_on_int1 : 1; + uint8_t not_used1 : 2; + uint8_t i2c_disable : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ctrl4_c_t; + +#define LSM6DSO16IS_CTRL5_C 0x14U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t st_xl : 2; + uint8_t st_g : 2; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t st_g : 2; + uint8_t st_xl : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ctrl5_c_t; + +#define LSM6DSO16IS_CTRL6_C 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 4; + uint8_t xl_hm_mode : 1; + uint8_t not_used1 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 3; + uint8_t xl_hm_mode : 1; + uint8_t not_used0 : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ctrl6_c_t; + +#define LSM6DSO16IS_CTRL7_G 0x16U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 7; + uint8_t g_hm_mode : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t g_hm_mode : 1; + uint8_t not_used0 : 7; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ctrl7_g_t; + +#define LSM6DSO16IS_CTRL9_C 0x18U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_bdu : 2; + uint8_t not_used0 : 2; + uint8_t ispu_rate : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_rate : 4; + uint8_t not_used0 : 2; + uint8_t ispu_bdu : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ctrl9_c_t; + +#define LSM6DSO16IS_CTRL10_C 0x19U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t ispu_clk_sel : 1; + uint8_t not_used1 : 2; + uint8_t timestamp_en : 1; + uint8_t not_used2 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used2 : 2; + uint8_t timestamp_en : 1; + uint8_t not_used1 : 2; + uint8_t ispu_clk_sel : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ctrl10_c_t; + +#define LSM6DSO16IS_ISPU_INT_STATUS0_MAINPAGE 0x1AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ia_ispu : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ia_ispu : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_int_status0_mainpage_t; + +#define LSM6DSO16IS_ISPU_INT_STATUS1_MAINPAGE 0x1BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ia_ispu : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ia_ispu : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_int_status1_mainpage_t; + +#define LSM6DSO16IS_ISPU_INT_STATUS2_MAINPAGE 0x1CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ia_ispu : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ia_ispu : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_int_status2_mainpage_t; + +#define LSM6DSO16IS_ISPU_INT_STATUS3_MAINPAGE 0x1DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ia_ispu : 6; + uint8_t not_used0 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 2; + uint8_t ia_ispu : 6; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_int_status3_mainpage_t; + +#define LSM6DSO16IS_STATUS_REG 0x1EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xlda : 1; + uint8_t gda : 1; + uint8_t tda : 1; + uint8_t not_used0 : 4; + uint8_t timestamp_endcount : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp_endcount : 1; + uint8_t not_used0 : 4; + uint8_t tda : 1; + uint8_t gda : 1; + uint8_t xlda : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_status_reg_t; + +#define LSM6DSO16IS_OUT_TEMP_L 0x20U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t temp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t temp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_out_temp_l_t; + +#define LSM6DSO16IS_OUT_TEMP_H 0x21U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t temp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t temp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_out_temp_h_t; + +#define LSM6DSO16IS_OUTX_L_G 0x22U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_outx_l_g_t; + +#define LSM6DSO16IS_OUTX_H_G 0x23U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_outx_h_g_t; + +#define LSM6DSO16IS_OUTY_L_G 0x24U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_outy_l_g_t; + +#define LSM6DSO16IS_OUTY_H_G 0x25U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_outy_h_g_t; + +#define LSM6DSO16IS_OUTZ_L_G 0x26U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_outz_l_g_t; + +#define LSM6DSO16IS_OUTZ_H_G 0x27U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_outz_h_g_t; + +#define LSM6DSO16IS_OUTX_L_A 0x28U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_outx_l_a_t; + +#define LSM6DSO16IS_OUTX_H_A 0x29U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_outx_h_a_t; + +#define LSM6DSO16IS_OUTY_L_A 0x2AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_outy_l_a_t; + +#define LSM6DSO16IS_OUTY_H_A 0x2BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_outy_h_a_t; + +#define LSM6DSO16IS_OUTZ_L_A 0x2CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_outz_l_a_t; + +#define LSM6DSO16IS_OUTZ_H_A 0x2DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_outz_h_a_t; + +#define LSM6DSO16IS_STATUS_MASTER_MAINPAGE 0x39U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sens_hub_endop : 1; + uint8_t not_used0 : 2; + uint8_t slave0_nack : 1; + uint8_t slave1_nack : 1; + uint8_t slave2_nack : 1; + uint8_t slave3_nack : 1; + uint8_t wr_once_done : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t wr_once_done : 1; + uint8_t slave3_nack : 1; + uint8_t slave2_nack : 1; + uint8_t slave1_nack : 1; + uint8_t slave0_nack : 1; + uint8_t not_used0 : 2; + uint8_t sens_hub_endop : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_status_master_mainpage_t; + +#define LSM6DSO16IS_TIMESTAMP0 0x40U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_timestamp0_t; + +#define LSM6DSO16IS_TIMESTAMP1 0x41U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_timestamp1_t; + +#define LSM6DSO16IS_TIMESTAMP2 0x42U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_timestamp2_t; + +#define LSM6DSO16IS_TIMESTAMP3 0x43U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_timestamp3_t; + +#define LSM6DSO16IS_MD1_CFG 0x5EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_shub : 1; + uint8_t int1_ispu : 1; + uint8_t not_used0 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 6; + uint8_t int1_ispu : 1; + uint8_t int1_shub : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_md1_cfg_t; + +#define LSM6DSO16IS_MD2_CFG 0x5FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_timestamp : 1; + uint8_t int2_ispu : 1; + uint8_t not_used0 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 6; + uint8_t int2_ispu : 1; + uint8_t int2_timestamp : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_md2_cfg_t; + +#define LSM6DSO16IS_INTERNAL_FREQ_FINE 0x63U +typedef struct +{ + uint8_t freq_fine : 8; +} lsm6dso16is_internal_freq_fine_t; + +#define LSM6DSO16IS_ISPU_DUMMY_CFG_1_L 0x73U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_dummy_cfg_1 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_dummy_cfg_1 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dummy_cfg_1_l_t; + +#define LSM6DSO16IS_ISPU_DUMMY_CFG_1_H 0x74U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_dummy_cfg_1 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_dummy_cfg_1 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dummy_cfg_1_h_t; + +#define LSM6DSO16IS_ISPU_DUMMY_CFG_2_L 0x75U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_dummy_cfg_2 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_dummy_cfg_2 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dummy_cfg_2_l_t; + +#define LSM6DSO16IS_ISPU_DUMMY_CFG_2_H 0x76U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_dummy_cfg_2 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_dummy_cfg_2 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dummy_cfg_2_h_t; + +#define LSM6DSO16IS_ISPU_DUMMY_CFG_3_L 0x77U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_dummy_cfg_3 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_dummy_cfg_3 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dummy_cfg_3_l_t; + +#define LSM6DSO16IS_ISPU_DUMMY_CFG_3_H 0x78U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_dummy_cfg_3 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_dummy_cfg_3 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dummy_cfg_3_h_t; + +#define LSM6DSO16IS_ISPU_DUMMY_CFG_4_L 0x79U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_dummy_cfg_4 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_dummy_cfg_4 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dummy_cfg_4_l_t; + +#define LSM6DSO16IS_ISPU_DUMMY_CFG_4_H 0x7AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_dummy_cfg_4 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_dummy_cfg_4 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dummy_cfg_4_h_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page sensor_hub + * @{ + * + */ + +#define LSM6DSO16IS_SENSOR_HUB_1 0x2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub1 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub1 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_sensor_hub_1_t; + +#define LSM6DSO16IS_SENSOR_HUB_2 0x3U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub2 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub2 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_sensor_hub_2_t; + +#define LSM6DSO16IS_SENSOR_HUB_3 0x4U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub3 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub3 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_sensor_hub_3_t; + +#define LSM6DSO16IS_SENSOR_HUB_4 0x5U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub4 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub4 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_sensor_hub_4_t; + +#define LSM6DSO16IS_SENSOR_HUB_5 0x6U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub5 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub5 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_sensor_hub_5_t; + +#define LSM6DSO16IS_SENSOR_HUB_6 0x7U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub6 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub6 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_sensor_hub_6_t; + +#define LSM6DSO16IS_SENSOR_HUB_7 0x8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub7 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub7 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_sensor_hub_7_t; + +#define LSM6DSO16IS_SENSOR_HUB_8 0x9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub8 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub8 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_sensor_hub_8_t; + +#define LSM6DSO16IS_SENSOR_HUB_9 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub9 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub9 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_sensor_hub_9_t; + +#define LSM6DSO16IS_SENSOR_HUB_10 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub10 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub10 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_sensor_hub_10_t; + +#define LSM6DSO16IS_SENSOR_HUB_11 0x0CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub11 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub11 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_sensor_hub_11_t; + +#define LSM6DSO16IS_SENSOR_HUB_12 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub12 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub12 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_sensor_hub_12_t; + +#define LSM6DSO16IS_SENSOR_HUB_13 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub13 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub13 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_sensor_hub_13_t; + +#define LSM6DSO16IS_SENSOR_HUB_14 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub14 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub14 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_sensor_hub_14_t; + +#define LSM6DSO16IS_SENSOR_HUB_15 0x10U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub15 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub15 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_sensor_hub_15_t; + +#define LSM6DSO16IS_SENSOR_HUB_16 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub16 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub16 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_sensor_hub_16_t; + +#define LSM6DSO16IS_SENSOR_HUB_17 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub17 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub17 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_sensor_hub_17_t; + +#define LSM6DSO16IS_SENSOR_HUB_18 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub18 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub18 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_sensor_hub_18_t; + +#define LSM6DSO16IS_MASTER_CONFIG 0x14U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t aux_sens_on : 2; + uint8_t master_on : 1; + uint8_t shub_pu_en : 1; + uint8_t pass_through_mode : 1; + uint8_t start_config : 1; + uint8_t write_once : 1; + uint8_t rst_master_regs : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t rst_master_regs : 1; + uint8_t write_once : 1; + uint8_t start_config : 1; + uint8_t pass_through_mode : 1; + uint8_t shub_pu_en : 1; + uint8_t master_on : 1; + uint8_t aux_sens_on : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_master_config_t; + +#define LSM6DSO16IS_SLV0_ADD 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t rw_0 : 1; + uint8_t slave0_add : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave0_add : 7; + uint8_t rw_0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_slv0_add_t; + +#define LSM6DSO16IS_SLV0_SUBADD 0x16U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave0_reg : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave0_reg : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_slv0_subadd_t; + +#define LSM6DSO16IS_SLAVE0_CONFIG 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave0_numop : 3; + uint8_t not_used0 : 3; + uint8_t shub_odr : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t shub_odr : 2; + uint8_t not_used0 : 3; + uint8_t slave0_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_slv0_config_t; + +#define LSM6DSO16IS_SLV1_ADD 0x18U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t r_1 : 1; + uint8_t slave1_add : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave1_add : 7; + uint8_t r_1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_slv1_add_t; + +#define LSM6DSO16IS_SLV1_SUBADD 0x19U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave1_reg : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave1_reg : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_slv1_subadd_t; + +#define LSM6DSO16IS_SLAVE1_CONFIG 0x1AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave1_numop : 3; + uint8_t not_used0 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 5; + uint8_t slave1_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_slv1_config_t; + +#define LSM6DSO16IS_SLV2_ADD 0x1BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t r_2 : 1; + uint8_t slave2_add : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave2_add : 7; + uint8_t r_2 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_slv2_add_t; + +#define LSM6DSO16IS_SLV2_SUBADD 0x1CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave2_reg : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave2_reg : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_slv2_subadd_t; + +#define LSM6DSO16IS_SLAVE2_CONFIG 0x1DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave2_numop : 3; + uint8_t not_used0 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 5; + uint8_t slave2_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_slv2_config_t; + +#define LSM6DSO16IS_SLV3_ADD 0x1EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t r_3 : 1; + uint8_t slave3_add : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave3_add : 7; + uint8_t r_3 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_slv3_add_t; + +#define LSM6DSO16IS_SLV3_SUBADD 0x1FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave3_reg : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave3_reg : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_slv3_subadd_t; + +#define LSM6DSO16IS_SLAVE3_CONFIG 0x20U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave3_numop : 3; + uint8_t not_used0 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 5; + uint8_t slave3_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_slv3_config_t; + +#define LSM6DSO16IS_DATAWRITE_SLV0 0x21U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave0_dataw : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave0_dataw : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_datawrite_slv0_t; + +#define LSM6DSO16IS_STATUS_MASTER 0x22U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sens_hub_endop : 1; + uint8_t not_used0 : 2; + uint8_t slave0_nack : 1; + uint8_t slave1_nack : 1; + uint8_t slave2_nack : 1; + uint8_t slave3_nack : 1; + uint8_t wr_once_done : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t wr_once_done : 1; + uint8_t slave3_nack : 1; + uint8_t slave2_nack : 1; + uint8_t slave1_nack : 1; + uint8_t slave0_nack : 1; + uint8_t not_used0 : 2; + uint8_t sens_hub_endop : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_status_master_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page ispu + * @{ + * + */ + +#define LSM6DSO16IS_ISPU_CONFIG 0x2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_rst_n : 1; + uint8_t clk_dis : 1; + uint8_t not_used0 : 2; + uint8_t latched : 1; + uint8_t not_used1 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 3; + uint8_t latched : 1; + uint8_t not_used0 : 2; + uint8_t clk_dis : 1; + uint8_t ispu_rst_n : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_config_t; + +#define LSM6DSO16IS_ISPU_STATUS 0x4U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t boot_end : 1; + uint8_t not_used1 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 5; + uint8_t boot_end : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_status_t; + +#define LSM6DSO16IS_ISPU_MEM_SEL 0x8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mem_sel : 1; + uint8_t not_used0 : 5; + uint8_t read_mem_en : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t read_mem_en : 1; + uint8_t not_used0 : 5; + uint8_t mem_sel : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_mem_sel_t; + +#define LSM6DSO16IS_ISPU_MEM_ADDR1 0x9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mem_addr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mem_addr : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_mem_addr1_t; + +#define LSM6DSO16IS_ISPU_MEM_ADDR0 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mem_addr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mem_addr : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_mem_addr0_t; + +#define LSM6DSO16IS_ISPU_MEM_DATA 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mem_data : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mem_data : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_mem_data_t; + +#define LSM6DSO16IS_ISPU_IF2S_FLAG_L 0x0CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t if2s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t if2s : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_if2s_flag_l_t; + +#define LSM6DSO16IS_ISPU_IF2S_FLAG_H 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t if2s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t if2s : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_if2s_flag_h_t; + +#define LSM6DSO16IS_ISPU_S2IF_FLAG_L 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t s2if : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t s2if : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_s2if_flag_l_t; + +#define LSM6DSO16IS_ISPU_S2IF_FLAG_H 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t s2if : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t s2if : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_s2if_flag_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_00_L 0x10U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout0 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout0 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_00_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_00_H 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout0 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout0 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_00_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_01_L 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout1 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout1 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_01_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_01_H 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout1 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout1 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_01_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_02_L 0x14U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout2 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout2 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_02_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_02_H 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout2 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout2 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_02_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_03_L 0x16U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout3 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout3 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_03_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_03_H 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout3 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout3 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_03_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_04_L 0x18U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout4 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout4 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_04_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_04_H 0x19U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout4 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout4 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_04_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_05_L 0x1AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout5 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout5 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_05_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_05_H 0x1BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout5 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout5 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_05_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_06_L 0x1CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout6 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout6 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_06_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_06_H 0x1DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout6 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout6 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_06_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_07_L 0x1EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout7 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout7 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_07_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_07_H 0x1FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout7 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout7 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_07_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_08_L 0x20U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout8 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout8 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_08_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_08_H 0x21U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout8 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout8 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_08_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_09_L 0x22U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout9 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout9 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_09_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_09_H 0x23U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout9 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout9 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_09_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_10_L 0x24U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout10 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout10 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_10_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_10_H 0x25U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout10 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout10 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_10_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_11_L 0x26U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout11 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout11 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_11_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_11_H 0x27U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout11 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout11 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_11_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_12_L 0x28U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout12 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout12 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_12_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_12_H 0x29U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout12 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout12 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_12_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_13_L 0x2AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout13 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout13 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_13_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_13_H 0x2BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout13 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout13 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_13_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_14_L 0x2CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout14 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout14 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_14_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_14_H 0x2DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout14 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout14 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_14_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_15_L 0x2EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout15 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout15 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_15_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_15_H 0x2FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout15 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout15 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_15_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_16_L 0x30U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout16 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout16 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_16_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_16_H 0x31U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout16 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout16 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_16_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_17_L 0x32U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout17 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout17 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_17_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_17_H 0x33U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout17 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout17 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_17_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_18_L 0x34U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout18 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout18 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_18_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_18_H 0x35U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout18 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout18 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_18_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_19_L 0x36U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout19 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout19 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_19_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_19_H 0x37U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout19 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout19 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_19_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_20_L 0x38U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout20 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout20 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_20_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_20_H 0x39U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout20 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout20 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_20_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_21_L 0x3AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout21 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout21 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_21_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_21_H 0x3BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout21 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout21 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_21_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_22_L 0x3CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout22 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout22 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_22_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_22_H 0x3DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout22 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout22 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_22_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_23_L 0x3EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout23 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout23 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_23_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_23_H 0x3FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout23 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout23 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_23_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_24_L 0x40U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout24 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout24 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_24_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_24_H 0x41U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout24 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout24 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_24_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_25_L 0x42U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout25 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout25 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_25_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_25_H 0x43U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout25 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout25 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_25_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_26_L 0x44U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout26 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout26 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_26_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_26_H 0x45U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout26 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout26 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_26_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_27_L 0x46U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout27 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout27 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_27_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_27_H 0x47U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout27 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout27 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_27_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_28_L 0x48U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout28 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout28 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_28_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_28_H 0x49U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout28 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout28 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_28_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_29_L 0x4AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout29 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout29 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_29_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_29_H 0x4BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout29 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout29 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_29_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_30_L 0x4CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout30 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout30 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_30_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_30_H 0x4DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout30 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout30 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_30_h_t; + +#define LSM6DSO16IS_ISPU_DOUT_31_L 0x4EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout31 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout31 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_31_l_t; + +#define LSM6DSO16IS_ISPU_DOUT_31_H 0x4FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t dout31 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dout31 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_dout_31_h_t; + +#define LSM6DSO16IS_ISPU_INT1_CTRL0 0x50U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_int1_ctrl : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_int1_ctrl : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_int1_ctrl0_t; + +#define LSM6DSO16IS_ISPU_INT1_CTRL1 0x51U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_int1_ctrl : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_int1_ctrl : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_int1_ctrl1_t; + +#define LSM6DSO16IS_ISPU_INT1_CTRL2 0x52U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_int1_ctrl : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_int1_ctrl : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_int1_ctrl2_t; + +#define LSM6DSO16IS_ISPU_INT1_CTRL3 0x53U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_int1_ctrl : 6; + uint8_t not_used0 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 2; + uint8_t ispu_int1_ctrl : 6; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_int1_ctrl3_t; + +#define LSM6DSO16IS_ISPU_INT2_CTRL0 0x54U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_int2_ctrl : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_int2_ctrl : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_int2_ctrl0_t; + +#define LSM6DSO16IS_ISPU_INT2_CTRL1 0x55U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_int2_ctrl : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_int2_ctrl : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_int2_ctrl1_t; + +#define LSM6DSO16IS_ISPU_INT2_CTRL2 0x56U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_int2_ctrl : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_int2_ctrl : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_int2_ctrl2_t; + +#define LSM6DSO16IS_ISPU_INT2_CTRL3 0x57U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_int2_ctrl : 6; + uint8_t not_used0 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 2; + uint8_t ispu_int2_ctrl : 6; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_int2_ctrl3_t; + +#define LSM6DSO16IS_ISPU_INT_STATUS0 0x58U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_int_status : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_int_status : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_int_status0_t; + +#define LSM6DSO16IS_ISPU_INT_STATUS1 0x59U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_int_status : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_int_status : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_int_status1_t; + +#define LSM6DSO16IS_ISPU_INT_STATUS2 0x5AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_int_status : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_int_status : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_int_status2_t; + +#define LSM6DSO16IS_ISPU_INT_STATUS3 0x5BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_int_status : 6; + uint8_t not_used0 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 2; + uint8_t ispu_int_status : 6; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_int_status3_t; + +#define LSM6DSO16IS_ISPU_ALGO0 0x70U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_algo : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_algo : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_algo0_t; + +#define LSM6DSO16IS_ISPU_ALGO1 0x71U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_algo : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_algo : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_algo1_t; + +#define LSM6DSO16IS_ISPU_ALGO2 0x72U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_algo : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ispu_algo : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_algo2_t; + +#define LSM6DSO16IS_ISPU_ALGO3 0x73U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ispu_algo : 6; + uint8_t not_used0 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 2; + uint8_t ispu_algo : 6; +#endif /* DRV_BYTE_ORDER */ +} lsm6dso16is_ispu_algo3_t; + +/** + * @} + * + */ + +typedef union +{ + lsm6dso16is_func_cfg_access_t func_cfg_access; + lsm6dso16is_pin_ctrl_t pin_ctrl; + lsm6dso16is_drdy_pulsed_reg_t drdy_pulsed_reg; + lsm6dso16is_int1_ctrl_t int1_ctrl; + lsm6dso16is_int2_ctrl_t int2_ctrl; + lsm6dso16is_who_am_i_t who_am_i; + lsm6dso16is_ctrl1_xl_t ctrl1_xl; + lsm6dso16is_ctrl2_g_t ctrl2_g; + lsm6dso16is_ctrl3_c_t ctrl3_c; + lsm6dso16is_ctrl4_c_t ctrl4_c; + lsm6dso16is_ctrl5_c_t ctrl5_c; + lsm6dso16is_ctrl6_c_t ctrl6_c; + lsm6dso16is_ctrl7_g_t ctrl7_g; + lsm6dso16is_ctrl9_c_t ctrl9_c; + lsm6dso16is_ctrl10_c_t ctrl10_c; + lsm6dso16is_ispu_int_status0_mainpage_t ispu_int_status0_mainpage; + lsm6dso16is_ispu_int_status1_mainpage_t ispu_int_status1_mainpage; + lsm6dso16is_ispu_int_status2_mainpage_t ispu_int_status2_mainpage; + lsm6dso16is_ispu_int_status3_mainpage_t ispu_int_status3_mainpage; + lsm6dso16is_status_reg_t status_reg; + lsm6dso16is_out_temp_l_t out_temp_l; + lsm6dso16is_out_temp_h_t out_temp_h; + lsm6dso16is_outx_l_g_t outx_l_g; + lsm6dso16is_outx_h_g_t outx_h_g; + lsm6dso16is_outy_l_g_t outy_l_g; + lsm6dso16is_outy_h_g_t outy_h_g; + lsm6dso16is_outz_l_g_t outz_l_g; + lsm6dso16is_outz_h_g_t outz_h_g; + lsm6dso16is_outx_l_a_t outx_l_a; + lsm6dso16is_outx_h_a_t outx_h_a; + lsm6dso16is_outy_l_a_t outy_l_a; + lsm6dso16is_outy_h_a_t outy_h_a; + lsm6dso16is_outz_l_a_t outz_l_a; + lsm6dso16is_outz_h_a_t outz_h_a; + lsm6dso16is_status_master_mainpage_t status_master_mainpage; + lsm6dso16is_timestamp0_t timestamp0; + lsm6dso16is_timestamp1_t timestamp1; + lsm6dso16is_timestamp2_t timestamp2; + lsm6dso16is_timestamp3_t timestamp3; + lsm6dso16is_md1_cfg_t md1_cfg; + lsm6dso16is_md2_cfg_t md2_cfg; + lsm6dso16is_internal_freq_fine_t internal_freq_fine; + lsm6dso16is_ispu_dummy_cfg_1_l_t ispu_dummy_cfg_1_l; + lsm6dso16is_ispu_dummy_cfg_1_h_t ispu_dummy_cfg_1_h; + lsm6dso16is_ispu_dummy_cfg_2_l_t ispu_dummy_cfg_2_l; + lsm6dso16is_ispu_dummy_cfg_2_h_t ispu_dummy_cfg_2_h; + lsm6dso16is_ispu_dummy_cfg_3_l_t ispu_dummy_cfg_3_l; + lsm6dso16is_ispu_dummy_cfg_3_h_t ispu_dummy_cfg_3_h; + lsm6dso16is_ispu_dummy_cfg_4_l_t ispu_dummy_cfg_4_l; + lsm6dso16is_ispu_dummy_cfg_4_h_t ispu_dummy_cfg_4_h; + lsm6dso16is_sensor_hub_1_t sensor_hub_1; + lsm6dso16is_sensor_hub_2_t sensor_hub_2; + lsm6dso16is_sensor_hub_3_t sensor_hub_3; + lsm6dso16is_sensor_hub_4_t sensor_hub_4; + lsm6dso16is_sensor_hub_5_t sensor_hub_5; + lsm6dso16is_sensor_hub_6_t sensor_hub_6; + lsm6dso16is_sensor_hub_7_t sensor_hub_7; + lsm6dso16is_sensor_hub_8_t sensor_hub_8; + lsm6dso16is_sensor_hub_9_t sensor_hub_9; + lsm6dso16is_sensor_hub_10_t sensor_hub_10; + lsm6dso16is_sensor_hub_11_t sensor_hub_11; + lsm6dso16is_sensor_hub_12_t sensor_hub_12; + lsm6dso16is_sensor_hub_13_t sensor_hub_13; + lsm6dso16is_sensor_hub_14_t sensor_hub_14; + lsm6dso16is_sensor_hub_15_t sensor_hub_15; + lsm6dso16is_sensor_hub_16_t sensor_hub_16; + lsm6dso16is_sensor_hub_17_t sensor_hub_17; + lsm6dso16is_sensor_hub_18_t sensor_hub_18; + lsm6dso16is_master_config_t master_config; + lsm6dso16is_slv0_add_t slv0_add; + lsm6dso16is_slv0_subadd_t slv0_subadd; + lsm6dso16is_slv0_config_t slv0_config; + lsm6dso16is_slv1_add_t slv1_add; + lsm6dso16is_slv1_subadd_t slv1_subadd; + lsm6dso16is_slv1_config_t slv1_config; + lsm6dso16is_slv2_add_t slv2_add; + lsm6dso16is_slv2_subadd_t slv2_subadd; + lsm6dso16is_slv2_config_t slv2_config; + lsm6dso16is_slv3_add_t slv3_add; + lsm6dso16is_slv3_subadd_t slv3_subadd; + lsm6dso16is_slv3_config_t slv3_config; + lsm6dso16is_datawrite_slv0_t datawrite_slv0; + lsm6dso16is_status_master_t status_master; + lsm6dso16is_ispu_config_t ispu_config; + lsm6dso16is_ispu_status_t ispu_status; + lsm6dso16is_ispu_mem_sel_t ispu_mem_sel; + lsm6dso16is_ispu_mem_addr1_t ispu_mem_addr1; + lsm6dso16is_ispu_mem_addr0_t ispu_mem_addr0; + lsm6dso16is_ispu_mem_data_t ispu_mem_data; + lsm6dso16is_ispu_if2s_flag_l_t ispu_if2s_flag_l; + lsm6dso16is_ispu_if2s_flag_h_t ispu_if2s_flag_h; + lsm6dso16is_ispu_s2if_flag_l_t ispu_s2if_flag_l; + lsm6dso16is_ispu_s2if_flag_h_t ispu_s2if_flag_h; + lsm6dso16is_ispu_dout_00_l_t ispu_dout_00_l; + lsm6dso16is_ispu_dout_00_h_t ispu_dout_00_h; + lsm6dso16is_ispu_dout_01_l_t ispu_dout_01_l; + lsm6dso16is_ispu_dout_01_h_t ispu_dout_01_h; + lsm6dso16is_ispu_dout_02_l_t ispu_dout_02_l; + lsm6dso16is_ispu_dout_02_h_t ispu_dout_02_h; + lsm6dso16is_ispu_dout_03_l_t ispu_dout_03_l; + lsm6dso16is_ispu_dout_03_h_t ispu_dout_03_h; + lsm6dso16is_ispu_dout_04_l_t ispu_dout_04_l; + lsm6dso16is_ispu_dout_04_h_t ispu_dout_04_h; + lsm6dso16is_ispu_dout_05_l_t ispu_dout_05_l; + lsm6dso16is_ispu_dout_05_h_t ispu_dout_05_h; + lsm6dso16is_ispu_dout_06_l_t ispu_dout_06_l; + lsm6dso16is_ispu_dout_06_h_t ispu_dout_06_h; + lsm6dso16is_ispu_dout_07_l_t ispu_dout_07_l; + lsm6dso16is_ispu_dout_07_h_t ispu_dout_07_h; + lsm6dso16is_ispu_dout_08_l_t ispu_dout_08_l; + lsm6dso16is_ispu_dout_08_h_t ispu_dout_08_h; + lsm6dso16is_ispu_dout_09_l_t ispu_dout_09_l; + lsm6dso16is_ispu_dout_09_h_t ispu_dout_09_h; + lsm6dso16is_ispu_dout_10_l_t ispu_dout_10_l; + lsm6dso16is_ispu_dout_10_h_t ispu_dout_10_h; + lsm6dso16is_ispu_dout_11_l_t ispu_dout_11_l; + lsm6dso16is_ispu_dout_11_h_t ispu_dout_11_h; + lsm6dso16is_ispu_dout_12_l_t ispu_dout_12_l; + lsm6dso16is_ispu_dout_12_h_t ispu_dout_12_h; + lsm6dso16is_ispu_dout_13_l_t ispu_dout_13_l; + lsm6dso16is_ispu_dout_13_h_t ispu_dout_13_h; + lsm6dso16is_ispu_dout_14_l_t ispu_dout_14_l; + lsm6dso16is_ispu_dout_14_h_t ispu_dout_14_h; + lsm6dso16is_ispu_dout_15_l_t ispu_dout_15_l; + lsm6dso16is_ispu_dout_15_h_t ispu_dout_15_h; + lsm6dso16is_ispu_dout_16_l_t ispu_dout_16_l; + lsm6dso16is_ispu_dout_16_h_t ispu_dout_16_h; + lsm6dso16is_ispu_dout_17_l_t ispu_dout_17_l; + lsm6dso16is_ispu_dout_17_h_t ispu_dout_17_h; + lsm6dso16is_ispu_dout_18_l_t ispu_dout_18_l; + lsm6dso16is_ispu_dout_18_h_t ispu_dout_18_h; + lsm6dso16is_ispu_dout_19_l_t ispu_dout_19_l; + lsm6dso16is_ispu_dout_19_h_t ispu_dout_19_h; + lsm6dso16is_ispu_dout_20_l_t ispu_dout_20_l; + lsm6dso16is_ispu_dout_20_h_t ispu_dout_20_h; + lsm6dso16is_ispu_dout_21_l_t ispu_dout_21_l; + lsm6dso16is_ispu_dout_21_h_t ispu_dout_21_h; + lsm6dso16is_ispu_dout_22_l_t ispu_dout_22_l; + lsm6dso16is_ispu_dout_22_h_t ispu_dout_22_h; + lsm6dso16is_ispu_dout_23_l_t ispu_dout_23_l; + lsm6dso16is_ispu_dout_23_h_t ispu_dout_23_h; + lsm6dso16is_ispu_dout_24_l_t ispu_dout_24_l; + lsm6dso16is_ispu_dout_24_h_t ispu_dout_24_h; + lsm6dso16is_ispu_dout_25_l_t ispu_dout_25_l; + lsm6dso16is_ispu_dout_25_h_t ispu_dout_25_h; + lsm6dso16is_ispu_dout_26_l_t ispu_dout_26_l; + lsm6dso16is_ispu_dout_26_h_t ispu_dout_26_h; + lsm6dso16is_ispu_dout_27_l_t ispu_dout_27_l; + lsm6dso16is_ispu_dout_27_h_t ispu_dout_27_h; + lsm6dso16is_ispu_dout_28_l_t ispu_dout_28_l; + lsm6dso16is_ispu_dout_28_h_t ispu_dout_28_h; + lsm6dso16is_ispu_dout_29_l_t ispu_dout_29_l; + lsm6dso16is_ispu_dout_29_h_t ispu_dout_29_h; + lsm6dso16is_ispu_dout_30_l_t ispu_dout_30_l; + lsm6dso16is_ispu_dout_30_h_t ispu_dout_30_h; + lsm6dso16is_ispu_dout_31_l_t ispu_dout_31_l; + lsm6dso16is_ispu_dout_31_h_t ispu_dout_31_h; + lsm6dso16is_ispu_int1_ctrl0_t ispu_int1_ctrl0; + lsm6dso16is_ispu_int1_ctrl1_t ispu_int1_ctrl1; + lsm6dso16is_ispu_int1_ctrl2_t ispu_int1_ctrl2; + lsm6dso16is_ispu_int1_ctrl3_t ispu_int1_ctrl3; + lsm6dso16is_ispu_int2_ctrl0_t ispu_int2_ctrl0; + lsm6dso16is_ispu_int2_ctrl1_t ispu_int2_ctrl1; + lsm6dso16is_ispu_int2_ctrl2_t ispu_int2_ctrl2; + lsm6dso16is_ispu_int2_ctrl3_t ispu_int2_ctrl3; + lsm6dso16is_ispu_int_status0_t ispu_int_status0; + lsm6dso16is_ispu_int_status1_t ispu_int_status1; + lsm6dso16is_ispu_int_status2_t ispu_int_status2; + lsm6dso16is_ispu_int_status3_t ispu_int_status3; + lsm6dso16is_ispu_algo0_t ispu_algo0; + lsm6dso16is_ispu_algo1_t ispu_algo1; + lsm6dso16is_ispu_algo2_t ispu_algo2; + lsm6dso16is_ispu_algo3_t ispu_algo3; + bitwise_t bitwise; + uint8_t byte; +} lsm6dso16is_reg_t; + +/** + * @} + * + */ + +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + +int32_t lsm6dso16is_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); +int32_t lsm6dso16is_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); + +float_t lsm6dso16is_from_fs2g_to_mg(int16_t lsb); +float_t lsm6dso16is_from_fs4g_to_mg(int16_t lsb); +float_t lsm6dso16is_from_fs8g_to_mg(int16_t lsb); +float_t lsm6dso16is_from_fs16g_to_mg(int16_t lsb); + +float_t lsm6dso16is_from_fs125dps_to_mdps(int16_t lsb); +float_t lsm6dso16is_from_fs250dps_to_mdps(int16_t lsb); +float_t lsm6dso16is_from_fs500dps_to_mdps(int16_t lsb); +float_t lsm6dso16is_from_fs1000dps_to_mdps(int16_t lsb); +float_t lsm6dso16is_from_fs2000dps_to_mdps(int16_t lsb); + +float_t lsm6dso16is_from_lsb_to_celsius(int16_t lsb); + +typedef enum +{ + LSM6DSO16IS_MAIN_MEM_BANK = 0x0, + LSM6DSO16IS_SENSOR_HUB_MEM_BANK = 0x2, + LSM6DSO16IS_ISPU_MEM_BANK = 0x3, +} lsm6dso16is_mem_bank_t; +int32_t lsm6dso16is_mem_bank_set(stmdev_ctx_t *ctx, lsm6dso16is_mem_bank_t val); +int32_t lsm6dso16is_mem_bank_get(stmdev_ctx_t *ctx, + lsm6dso16is_mem_bank_t *val); + +typedef enum +{ + LSM6DSO16IS_DRDY_LATCHED = 0x0, + LSM6DSO16IS_DRDY_PULSED = 0x1, +} lsm6dso16is_data_ready_mode_t; +int32_t lsm6dso16is_data_ready_mode_set(stmdev_ctx_t *ctx, + lsm6dso16is_data_ready_mode_t val); +int32_t lsm6dso16is_data_ready_mode_get(stmdev_ctx_t *ctx, + lsm6dso16is_data_ready_mode_t *val); + +int32_t lsm6dso16is_device_id_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso16is_device_id_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dso16is_software_reset(stmdev_ctx_t *ctx); + +int32_t lsm6dso16is_boot_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso16is_boot_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSO16IS_HIGH_PERFOMANCE_MODE_ENABLED = 0x0, + LSM6DSO16IS_HIGH_PERFOMANCE_MODE_DISABLED = 0x1, +} lsm6dso16is_hm_mode_t; +int32_t lsm6dso16is_xl_hm_mode_set(stmdev_ctx_t *ctx, + lsm6dso16is_hm_mode_t val); +int32_t lsm6dso16is_xl_hm_mode_get(stmdev_ctx_t *ctx, + lsm6dso16is_hm_mode_t *val); +int32_t lsm6dso16is_gy_hm_mode_set(stmdev_ctx_t *ctx, + lsm6dso16is_hm_mode_t val); +int32_t lsm6dso16is_gy_hm_mode_get(stmdev_ctx_t *ctx, + lsm6dso16is_hm_mode_t *val); + +typedef enum +{ + LSM6DSO16IS_2g = 0x0, + LSM6DSO16IS_16g = 0x1, + LSM6DSO16IS_4g = 0x2, + LSM6DSO16IS_8g = 0x3, +} lsm6dso16is_xl_full_scale_t; +int32_t lsm6dso16is_xl_full_scale_set(stmdev_ctx_t *ctx, + lsm6dso16is_xl_full_scale_t val); +int32_t lsm6dso16is_xl_full_scale_get(stmdev_ctx_t *ctx, + lsm6dso16is_xl_full_scale_t *val); + +typedef enum +{ + LSM6DSO16IS_XL_ODR_OFF = 0x0, + LSM6DSO16IS_XL_ODR_AT_12Hz5_HP = 0x1, + LSM6DSO16IS_XL_ODR_AT_26H_HP = 0x2, + LSM6DSO16IS_XL_ODR_AT_52Hz_HP = 0x3, + LSM6DSO16IS_XL_ODR_AT_104Hz_HP = 0x4, + LSM6DSO16IS_XL_ODR_AT_208Hz_HP = 0x5, + LSM6DSO16IS_XL_ODR_AT_416Hz_HP = 0x6, + LSM6DSO16IS_XL_ODR_AT_833Hz_HP = 0x7, + LSM6DSO16IS_XL_ODR_AT_1667Hz_HP = 0x8, + LSM6DSO16IS_XL_ODR_AT_3333Hz_HP = 0x9, + LSM6DSO16IS_XL_ODR_AT_6667Hz_HP = 0xa, + LSM6DSO16IS_XL_ODR_AT_12Hz5_LP = 0x11, + LSM6DSO16IS_XL_ODR_AT_26H_LP = 0x12, + LSM6DSO16IS_XL_ODR_AT_52Hz_LP = 0x13, + LSM6DSO16IS_XL_ODR_AT_104Hz_LP = 0x14, + LSM6DSO16IS_XL_ODR_AT_208Hz_LP = 0x15, + LSM6DSO16IS_XL_ODR_AT_416Hz_LP = 0x16, + LSM6DSO16IS_XL_ODR_AT_833Hz_LP = 0x17, + LSM6DSO16IS_XL_ODR_AT_1667Hz_LP = 0x18, + LSM6DSO16IS_XL_ODR_AT_3333Hz_LP = 0x19, + LSM6DSO16IS_XL_ODR_AT_6667Hz_LP = 0x1a, + LSM6DSO16IS_XL_ODR_AT_1Hz6_LP = 0x1b, +} lsm6dso16is_xl_data_rate_t; +int32_t lsm6dso16is_xl_data_rate_set(stmdev_ctx_t *ctx, + lsm6dso16is_xl_data_rate_t val); +int32_t lsm6dso16is_xl_data_rate_get(stmdev_ctx_t *ctx, + lsm6dso16is_xl_data_rate_t *val); + +typedef enum +{ + LSM6DSO16IS_250dps = 0x0, + LSM6DSO16IS_500dps = 0x1, + LSM6DSO16IS_1000dps = 0x2, + LSM6DSO16IS_2000dps = 0x3, + LSM6DSO16IS_125dps = 0x10, +} lsm6dso16is_gy_full_scale_t; +int32_t lsm6dso16is_gy_full_scale_set(stmdev_ctx_t *ctx, + lsm6dso16is_gy_full_scale_t val); +int32_t lsm6dso16is_gy_full_scale_get(stmdev_ctx_t *ctx, + lsm6dso16is_gy_full_scale_t *val); + +typedef enum +{ + LSM6DSO16IS_GY_ODR_OFF = 0x0, + LSM6DSO16IS_GY_ODR_AT_12Hz5_HP = 0x1, + LSM6DSO16IS_GY_ODR_AT_26H_HP = 0x2, + LSM6DSO16IS_GY_ODR_AT_52Hz_HP = 0x3, + LSM6DSO16IS_GY_ODR_AT_104Hz_HP = 0x4, + LSM6DSO16IS_GY_ODR_AT_208Hz_HP = 0x5, + LSM6DSO16IS_GY_ODR_AT_416Hz_HP = 0x6, + LSM6DSO16IS_GY_ODR_AT_833Hz_HP = 0x7, + LSM6DSO16IS_GY_ODR_AT_1667Hz_HP = 0x8, + LSM6DSO16IS_GY_ODR_AT_3333Hz_HP = 0x9, + LSM6DSO16IS_GY_ODR_AT_6667Hz_HP = 0xa, + LSM6DSO16IS_GY_ODR_AT_12Hz5_LP = 0x11, + LSM6DSO16IS_GY_ODR_AT_26H_LP = 0x12, + LSM6DSO16IS_GY_ODR_AT_52Hz_LP = 0x13, + LSM6DSO16IS_GY_ODR_AT_104Hz_LP = 0x14, + LSM6DSO16IS_GY_ODR_AT_208Hz_LP = 0x15, + LSM6DSO16IS_GY_ODR_AT_416Hz_LP = 0x16, + LSM6DSO16IS_GY_ODR_AT_833Hz_LP = 0x17, + LSM6DSO16IS_GY_ODR_AT_1667Hz_LP = 0x18, + LSM6DSO16IS_GY_ODR_AT_3333Hz_LP = 0x19, + LSM6DSO16IS_GY_ODR_AT_6667Hz_LP = 0x1a, +} lsm6dso16is_gy_data_rate_t; +int32_t lsm6dso16is_gy_data_rate_set(stmdev_ctx_t *ctx, + lsm6dso16is_gy_data_rate_t val); +int32_t lsm6dso16is_gy_data_rate_get(stmdev_ctx_t *ctx, + lsm6dso16is_gy_data_rate_t *val); + +int32_t lsm6dso16is_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso16is_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dso16is_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso16is_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSO16IS_SLEEP_G_ENABLE = 0x0, + LSM6DSO16IS_SLEEP_G_DISABLE = 0x1, +} lsm6dso16is_sleep_t; +int32_t lsm6dso16is_sleep_set(stmdev_ctx_t *ctx, lsm6dso16is_sleep_t val); +int32_t lsm6dso16is_sleep_get(stmdev_ctx_t *ctx, lsm6dso16is_sleep_t *val); + +typedef enum +{ + LSM6DSO16IS_XL_ST_DISABLE = 0x0, + LSM6DSO16IS_XL_ST_POSITIVE = 0x1, + LSM6DSO16IS_XL_ST_NEGATIVE = 0x2, +} lsm6dso16is_xl_self_test_t; +int32_t lsm6dso16is_xl_self_test_set(stmdev_ctx_t *ctx, + lsm6dso16is_xl_self_test_t val); +int32_t lsm6dso16is_xl_self_test_get(stmdev_ctx_t *ctx, + lsm6dso16is_xl_self_test_t *val); + +typedef enum +{ + LSM6DSO16IS_GY_ST_DISABLE = 0x0, + LSM6DSO16IS_GY_ST_POSITIVE = 0x1, + LSM6DSO16IS_GY_ST_NEGATIVE = 0x3, +} lsm6dso16is_gy_self_test_t; +int32_t lsm6dso16is_gy_self_test_set(stmdev_ctx_t *ctx, + lsm6dso16is_gy_self_test_t val); +int32_t lsm6dso16is_gy_self_test_get(stmdev_ctx_t *ctx, + lsm6dso16is_gy_self_test_t *val); + +int32_t lsm6dso16is_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso16is_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSO16IS_SPI_4_WIRE = 0x0, + LSM6DSO16IS_SPI_3_WIRE = 0x1, +} lsm6dso16is_spi_mode_t; +int32_t lsm6dso16is_spi_mode_set(stmdev_ctx_t *ctx, lsm6dso16is_spi_mode_t val); +int32_t lsm6dso16is_spi_mode_get(stmdev_ctx_t *ctx, + lsm6dso16is_spi_mode_t *val); + +typedef enum +{ + LSM6DSO16IS_I2C_ENABLE = 0x0, + LSM6DSO16IS_I2C_DISABLE = 0x1, +} lsm6dso16is_ui_i2c_mode_t; +int32_t lsm6dso16is_ui_i2c_mode_set(stmdev_ctx_t *ctx, + lsm6dso16is_ui_i2c_mode_t val); +int32_t lsm6dso16is_ui_i2c_mode_get(stmdev_ctx_t *ctx, + lsm6dso16is_ui_i2c_mode_t *val); + + +int32_t lsm6dso16is_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso16is_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dso16is_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); + +typedef struct +{ + uint8_t drdy_xl : 1; + uint8_t drdy_gy : 1; + uint8_t boot : 1; + uint8_t sh_endop : 1; + uint8_t ispu : 1; +} lsm6dso16is_pin_int1_route_t; +int32_t lsm6dso16is_pin_int1_route_set(stmdev_ctx_t *ctx, + lsm6dso16is_pin_int1_route_t val); +int32_t lsm6dso16is_pin_int1_route_get(stmdev_ctx_t *ctx, + lsm6dso16is_pin_int1_route_t *val); + +typedef struct +{ + uint8_t drdy_xl : 1; + uint8_t drdy_gy : 1; + uint8_t drdy_temp : 1; + uint8_t timestamp : 1; + uint8_t ispu_sleep : 1; + uint8_t ispu : 1; +} lsm6dso16is_pin_int2_route_t; +int32_t lsm6dso16is_pin_int2_route_set(stmdev_ctx_t *ctx, + lsm6dso16is_pin_int2_route_t val); +int32_t lsm6dso16is_pin_int2_route_get(stmdev_ctx_t *ctx, + lsm6dso16is_pin_int2_route_t *val); + +typedef enum +{ + LSM6DSO16IS_PUSH_PULL = 0x0, + LSM6DSO16IS_OPEN_DRAIN = 0x1, +} lsm6dso16is_int_pin_mode_t; +int32_t lsm6dso16is_int_pin_mode_set(stmdev_ctx_t *ctx, + lsm6dso16is_int_pin_mode_t val); +int32_t lsm6dso16is_int_pin_mode_get(stmdev_ctx_t *ctx, + lsm6dso16is_int_pin_mode_t *val); + +typedef enum +{ + LSM6DSO16IS_ACTIVE_HIGH = 0x0, + LSM6DSO16IS_ACTIVE_LOW = 0x1, +} lsm6dso16is_pin_polarity_t; +int32_t lsm6dso16is_pin_polarity_set(stmdev_ctx_t *ctx, + lsm6dso16is_pin_polarity_t val); +int32_t lsm6dso16is_pin_polarity_get(stmdev_ctx_t *ctx, + lsm6dso16is_pin_polarity_t *val); + +typedef struct +{ + uint8_t drdy_xl : 1; + uint8_t drdy_gy : 1; + uint8_t drdy_temp : 1; + uint8_t sh_endop : 1; + uint8_t sh_slave0_nack : 1; + uint8_t sh_slave1_nack : 1; + uint8_t sh_slave2_nack : 1; + uint8_t sh_slave3_nack : 1; + uint8_t sh_wr_once : 1; + uint32_t ispu : 30; +} lsm6dso16is_all_sources_t; +int32_t lsm6dso16is_all_sources_get(stmdev_ctx_t *ctx, + lsm6dso16is_all_sources_t *val); + +int32_t lsm6dso16is_status_reg_get(stmdev_ctx_t *ctx, + lsm6dso16is_status_reg_t *val); + +int32_t lsm6dso16is_xl_flag_data_ready_get(stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t lsm6dso16is_gy_flag_data_ready_get(stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t lsm6dso16is_temp_flag_data_ready_get(stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t lsm6dso16is_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); + +int32_t lsm6dso16is_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val); + +int32_t lsm6dso16is_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); + +int32_t lsm6dso16is_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso16is_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + lsm6dso16is_sensor_hub_1_t sh_byte_1; + lsm6dso16is_sensor_hub_2_t sh_byte_2; + lsm6dso16is_sensor_hub_3_t sh_byte_3; + lsm6dso16is_sensor_hub_4_t sh_byte_4; + lsm6dso16is_sensor_hub_5_t sh_byte_5; + lsm6dso16is_sensor_hub_6_t sh_byte_6; + lsm6dso16is_sensor_hub_7_t sh_byte_7; + lsm6dso16is_sensor_hub_8_t sh_byte_8; + lsm6dso16is_sensor_hub_9_t sh_byte_9; + lsm6dso16is_sensor_hub_10_t sh_byte_10; + lsm6dso16is_sensor_hub_11_t sh_byte_11; + lsm6dso16is_sensor_hub_12_t sh_byte_12; + lsm6dso16is_sensor_hub_13_t sh_byte_13; + lsm6dso16is_sensor_hub_14_t sh_byte_14; + lsm6dso16is_sensor_hub_15_t sh_byte_15; + lsm6dso16is_sensor_hub_16_t sh_byte_16; + lsm6dso16is_sensor_hub_17_t sh_byte_17; + lsm6dso16is_sensor_hub_18_t sh_byte_18; +} lsm6dso16is_emb_sh_read_t; +int32_t lsm6dso16is_sh_read_data_raw_get(stmdev_ctx_t *ctx, + lsm6dso16is_emb_sh_read_t *val, + uint8_t len); + +typedef enum +{ + LSM6DSO16IS_SLV_0 = 0x0, + LSM6DSO16IS_SLV_0_1 = 0x1, + LSM6DSO16IS_SLV_0_1_2 = 0x2, + LSM6DSO16IS_SLV_0_1_2_3 = 0x3, +} lsm6dso16is_sh_slave_connected_t; +int32_t lsm6dso16is_sh_slave_connected_set(stmdev_ctx_t *ctx, + lsm6dso16is_sh_slave_connected_t val); +int32_t lsm6dso16is_sh_slave_connected_get(stmdev_ctx_t *ctx, + lsm6dso16is_sh_slave_connected_t *val); + +int32_t lsm6dso16is_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso16is_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dso16is_sh_master_interface_pull_up_set(stmdev_ctx_t *ctx, + uint8_t val); +int32_t lsm6dso16is_sh_master_interface_pull_up_get(stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t lsm6dso16is_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso16is_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSO16IS_SH_TRG_XL_GY_DRDY = 0x0, + LSM6DSO16IS_SH_TRIG_INT2 = 0x1, +} lsm6dso16is_sh_syncro_mode_t; +int32_t lsm6dso16is_sh_syncro_mode_set(stmdev_ctx_t *ctx, + lsm6dso16is_sh_syncro_mode_t val); +int32_t lsm6dso16is_sh_syncro_mode_get(stmdev_ctx_t *ctx, + lsm6dso16is_sh_syncro_mode_t *val); + +typedef enum +{ + LSM6DSO16IS_EACH_SH_CYCLE = 0x0, + LSM6DSO16IS_ONLY_FIRST_CYCLE = 0x1, +} lsm6dso16is_sh_write_mode_t; +int32_t lsm6dso16is_sh_write_mode_set(stmdev_ctx_t *ctx, + lsm6dso16is_sh_write_mode_t val); +int32_t lsm6dso16is_sh_write_mode_get(stmdev_ctx_t *ctx, + lsm6dso16is_sh_write_mode_t *val); + +int32_t lsm6dso16is_sh_reset_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso16is_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t slv0_add; + uint8_t slv0_subadd; + uint8_t slv0_data; +} lsm6dso16is_sh_cfg_write_t; +int32_t lsm6dso16is_sh_cfg_write(stmdev_ctx_t *ctx, + lsm6dso16is_sh_cfg_write_t *val); +typedef enum +{ + LSM6DSO16IS_SH_104Hz = 0x0, + LSM6DSO16IS_SH_52Hz = 0x1, + LSM6DSO16IS_SH_26Hz = 0x2, + LSM6DSO16IS_SH_12_5Hz = 0x3, +} lsm6dso16is_sh_data_rate_t; +int32_t lsm6dso16is_sh_data_rate_set(stmdev_ctx_t *ctx, + lsm6dso16is_sh_data_rate_t val); +int32_t lsm6dso16is_sh_data_rate_get(stmdev_ctx_t *ctx, + lsm6dso16is_sh_data_rate_t *val); + +typedef struct +{ + uint8_t slv_add; + uint8_t slv_subadd; + uint8_t slv_len; +} lsm6dso16is_sh_cfg_read_t; +int32_t lsm6dso16is_sh_slv0_cfg_read(stmdev_ctx_t *ctx, + lsm6dso16is_sh_cfg_read_t *val); +int32_t lsm6dso16is_sh_slv1_cfg_read(stmdev_ctx_t *ctx, + lsm6dso16is_sh_cfg_read_t *val); +int32_t lsm6dso16is_sh_slv2_cfg_read(stmdev_ctx_t *ctx, + lsm6dso16is_sh_cfg_read_t *val); +int32_t lsm6dso16is_sh_slv3_cfg_read(stmdev_ctx_t *ctx, + lsm6dso16is_sh_cfg_read_t *val); + +int32_t lsm6dso16is_ispu_reset_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso16is_ispu_reset_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSO16IS_ISPU_CLK_5MHz = 0x0, + LSM6DSO16IS_ISPU_CLK_10MHz = 0x1, +} lsm6dso16is_ispu_clock_sel_t; +int32_t lsm6dso16is_ispu_clock_set(stmdev_ctx_t *ctx, + lsm6dso16is_ispu_clock_sel_t val); +int32_t lsm6dso16is_ispu_clock_get(stmdev_ctx_t *ctx, + lsm6dso16is_ispu_clock_sel_t *val); + +typedef enum +{ + LSM6DSO16IS_ISPU_ODR_OFF = 0x0, + LSM6DSO16IS_ISPU_ODR_AT_12Hz5 = 0x1, + LSM6DSO16IS_ISPU_ODR_AT_26Hz = 0x2, + LSM6DSO16IS_ISPU_ODR_AT_52Hz = 0x3, + LSM6DSO16IS_ISPU_ODR_AT_104Hz = 0x4, + LSM6DSO16IS_ISPU_ODR_AT_208Hz = 0x5, + LSM6DSO16IS_ISPU_ODR_AT_416Hz = 0x6, + LSM6DSO16IS_ISPU_ODR_AT_833Hz = 0x7, + LSM6DSO16IS_ISPU_ODR_AT_1667Hz = 0x8, + LSM6DSO16IS_ISPU_ODR_AT_3333Hz = 0x9, + LSM6DSO16IS_ISPU_ODR_AT_6667Hz = 0xa, +} lsm6dso16is_ispu_data_rate_t; +int32_t lsm6dso16is_ispu_data_rate_set(stmdev_ctx_t *ctx, + lsm6dso16is_ispu_data_rate_t val); +int32_t lsm6dso16is_ispu_data_rate_get(stmdev_ctx_t *ctx, + lsm6dso16is_ispu_data_rate_t *val); + +typedef enum +{ + LSM6DSO16IS_ISPU_BDU_OFF = 0x0, + LSM6DSO16IS_ISPU_BDU_ON_2B_4B = 0x1, + LSM6DSO16IS_ISPU_BDU_ON_2B_2B = 0x2, + LSM6DSO16IS_ISPU_BDU_ON_4B_4B = 0x3, +} lsm6dso16is_ispu_bdu_t; +int32_t lsm6dso16is_ispu_bdu_set(stmdev_ctx_t *ctx, lsm6dso16is_ispu_bdu_t val); +int32_t lsm6dso16is_ispu_bdu_get(stmdev_ctx_t *ctx, + lsm6dso16is_ispu_bdu_t *val); + +int32_t lsm6dso16is_ia_ispu_get(stmdev_ctx_t *ctx, uint32_t *val); + +int32_t lsm6dso16is_ispu_write_dummy_cfg(stmdev_ctx_t *ctx, uint8_t offset, + uint8_t *val, uint8_t len); +int32_t lsm6dso16is_ispu_ready_dummy_cfg(stmdev_ctx_t *ctx, uint8_t offset, + uint8_t *val, uint8_t len); + +typedef enum +{ + LSM6DSO16IS_ISPU_TURN_ON = 0x0, + LSM6DSO16IS_ISPU_TURN_OFF = 0x1, +} lsm6dso16is_ispu_boot_latched_t; +int32_t lsm6dso16is_ispu_boot_set(stmdev_ctx_t *ctx, + lsm6dso16is_ispu_boot_latched_t val); +int32_t lsm6dso16is_ispu_boot_get(stmdev_ctx_t *ctx, + lsm6dso16is_ispu_boot_latched_t *val); + +typedef enum +{ + LSM6DSO16IS_ISPU_INT_PULSED = 0x0, + LSM6DSO16IS_ISPU_INT_LATCHED = 0x1, +} lsm6dso16is_ispu_int_latched_t; +int32_t lsm6dso16is_ispu_int_latched_set(stmdev_ctx_t *ctx, + lsm6dso16is_ispu_int_latched_t val); +int32_t lsm6dso16is_ispu_int_latched_get(stmdev_ctx_t *ctx, + lsm6dso16is_ispu_int_latched_t *val); + +typedef enum +{ + LSM6DSO16IS_ISPU_BOOT_IN_PROGRESS = 0x0, + LSM6DSO16IS_ISPU_BOOT_ENDED = 0x1, +} lsm6dso16is_ispu_boot_end_t; +int32_t lsm6dso16is_ispu_get_boot_status(stmdev_ctx_t *ctx, + lsm6dso16is_ispu_boot_end_t *val); + +typedef enum +{ + LSM6DSO16IS_ISPU_DATA_RAM_MEMORY = 0x0, + LSM6DSO16IS_ISPU_PROGRAM_RAM_MEMORY = 0x1, +} lsm6dso16is_ispu_memory_type_t; +int32_t lsm6dso16is_ispu_read_memory_enable(stmdev_ctx_t *ctx, + lsm6dso16is_ispu_memory_type_t val); +int32_t lsm6dso16is_ispu_read_memory_disable(stmdev_ctx_t *ctx); + +int32_t lsm6dso16is_ispu_write_memory(stmdev_ctx_t *ctx, + lsm6dso16is_ispu_memory_type_t mem_sel, + uint16_t mem_addr, uint8_t *mem_data, uint16_t len); +int32_t lsm6dso16is_ispu_read_memory(stmdev_ctx_t *ctx, + lsm6dso16is_ispu_memory_type_t mem_sel, + uint16_t mem_addr, uint8_t *mem_data, uint16_t len); + +int32_t lsm6dso16is_ispu_write_flags(stmdev_ctx_t *ctx, uint16_t data); +int32_t lsm6dso16is_ispu_read_flags(stmdev_ctx_t *ctx, uint16_t *data); +int32_t lsm6dso16is_ispu_clear_flags(stmdev_ctx_t *ctx); + +int32_t lsm6dso16is_ispu_read_data_raw_get(stmdev_ctx_t *ctx, + uint8_t *val, + uint8_t len); + +int32_t lsm6dso16is_ispu_int1_ctrl_get(stmdev_ctx_t *ctx, uint32_t *val); +int32_t lsm6dso16is_ispu_int1_ctrl_set(stmdev_ctx_t *ctx, uint32_t val); +int32_t lsm6dso16is_ispu_int2_ctrl_get(stmdev_ctx_t *ctx, uint32_t *val); +int32_t lsm6dso16is_ispu_int2_ctrl_set(stmdev_ctx_t *ctx, uint32_t val); + +int32_t lsm6dso16is_ispu_int_status_get(stmdev_ctx_t *ctx, uint32_t *val); + +int32_t lsm6dso16is_ispu_algo_get(stmdev_ctx_t *ctx, uint32_t *val); +int32_t lsm6dso16is_ispu_algo_set(stmdev_ctx_t *ctx, uint32_t val); +/** + * @} + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /*LSM6DSO16IS_DRIVER_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.c b/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.c index ad213008f0a5ca141436f152a92c88d6ea92e1ed..e7d294f1044ca8072acf6c99ead19ea50f68a91c 100644 --- a/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.c +++ b/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lsm6dso32_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t lsm6dso32_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lsm6dso32_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.h b/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.h index 58bd04595f9c250be20634bbef2ab00d70a940f3..f878a9da8717ef10663aa1b3952486d6af099fba 100644 --- a/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.h +++ b/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -2622,6 +2625,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lsm6dso32_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/lsm6dso32x_STdC/driver/lsm6dso32x_reg.c b/sensor/stmemsc/lsm6dso32x_STdC/driver/lsm6dso32x_reg.c index 1243b39144ca84e109def8490f48483290c67610..2f586b4d07f87bde6ebda3d6ad937432915ab4f5 100644 --- a/sensor/stmemsc/lsm6dso32x_STdC/driver/lsm6dso32x_reg.c +++ b/sensor/stmemsc/lsm6dso32x_STdC/driver/lsm6dso32x_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lsm6dso32x_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t lsm6dso32x_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lsm6dso32x_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lsm6dso32x_STdC/driver/lsm6dso32x_reg.h b/sensor/stmemsc/lsm6dso32x_STdC/driver/lsm6dso32x_reg.h index dee58bd41a10d05c937e65911ff2621cf3afe976..5fec672d9500f2ed5241efa3aa3a2517c9aefa50 100644 --- a/sensor/stmemsc/lsm6dso32x_STdC/driver/lsm6dso32x_reg.h +++ b/sensor/stmemsc/lsm6dso32x_STdC/driver/lsm6dso32x_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -2740,6 +2743,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lsm6dso32x_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); int32_t lsm6dso32x_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, diff --git a/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.c b/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.c index 974b2135dc5d8726be1763e36235e74e530685ac..ae0432e418c65a60412734c4aadcfbd96f5c717e 100644 --- a/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.c +++ b/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.c @@ -47,9 +47,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lsm6dso_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -68,9 +68,9 @@ int32_t lsm6dso_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lsm6dso_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -780,7 +780,7 @@ int32_t lsm6dso_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @brief Block data update.[get] * * @param ctx read / write interface definitions - * @param val change the values of bdu in reg CTRL3_C + * @param val Get the values of bdu in reg CTRL3_C * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -1019,7 +1019,7 @@ int32_t lsm6dso_status_reg_get(stmdev_ctx_t *ctx, * @brief Accelerometer new data available.[get] * * @param ctx read / write interface definitions - * @param val change the values of xlda in reg STATUS_REG + * @param val Get the values of xlda in reg STATUS_REG * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -1039,7 +1039,7 @@ int32_t lsm6dso_xl_flag_data_ready_get(stmdev_ctx_t *ctx, * @brief Gyroscope new data available.[get] * * @param ctx read / write interface definitions - * @param val change the values of gda in reg STATUS_REG + * @param val Get the values of gda in reg STATUS_REG * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -1059,7 +1059,7 @@ int32_t lsm6dso_gy_flag_data_ready_get(stmdev_ctx_t *ctx, * @brief Temperature new data available.[get] * * @param ctx read / write interface definitions - * @param val change the values of tda in reg STATUS_REG + * @param val Get the values of tda in reg STATUS_REG * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -1077,7 +1077,7 @@ int32_t lsm6dso_temp_flag_data_ready_get(stmdev_ctx_t *ctx, /** * @brief Accelerometer X-axis user offset correction expressed in - * two’s complement, weight depends on USR_OFF_W in CTRL6_C (15h). + * two's complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * * @param ctx read / write interface definitions @@ -1095,7 +1095,7 @@ int32_t lsm6dso_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -1114,7 +1114,7 @@ int32_t lsm6dso_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * @@ -1133,7 +1133,7 @@ int32_t lsm6dso_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -1152,7 +1152,7 @@ int32_t lsm6dso_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Z-axis user offset correction expressed in two’s + * @brief Accelerometer Z-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * @@ -1171,7 +1171,7 @@ int32_t lsm6dso_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Z-axis user offset correction expressed in two’s + * @brief Accelerometer Z-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -1286,7 +1286,7 @@ int32_t lsm6dso_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) * @brief Enables timestamp counter.[get] * * @param ctx read / write interface definitions - * @param val change the values of timestamp_en in reg CTRL10_C + * @param val Get the values of timestamp_en in reg CTRL10_C * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -1304,7 +1304,7 @@ int32_t lsm6dso_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) /** * @brief Timestamp first data output register (r). * The value is expressed as a 32-bit word and the bit - * resolution is 25 μs.[get] + * resolution is 25 us.[get] * * @param ctx read / write interface definitions * @param buff buffer that stores data read @@ -1407,7 +1407,7 @@ int32_t lsm6dso_rounding_mode_get(stmdev_ctx_t *ctx, /** * @brief Temperature data output register (r). - * L and H registers together express a 16-bit word in two’s + * L and H registers together express a 16-bit word in two's * complement.[get] * * @param ctx read / write interface definitions @@ -1429,7 +1429,7 @@ int32_t lsm6dso_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) /** * @brief Angular rate sensor. The value is expressed as a 16-bit - * word in two’s complement.[get] + * word in two's complement.[get] * * @param ctx read / write interface definitions * @param buff buffer that stores data read @@ -1454,7 +1454,7 @@ int32_t lsm6dso_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) /** * @brief Linear acceleration output register. - * The value is expressed as a 16-bit word in two’s complement.[get] + * The value is expressed as a 16-bit word in two's complement.[get] * * @param ctx read / write interface definitions * @param buff buffer that stores data read @@ -1604,7 +1604,7 @@ int32_t lsm6dso_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) * Step: 0.15%. 8-bit format, 2's complement.[get] * * @param ctx read / write interface definitions - * @param val change the values of freq_fine in reg INTERNAL_FREQ_FINE + * @param val Get the values of freq_fine in reg INTERNAL_FREQ_FINE * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -2043,7 +2043,7 @@ int32_t lsm6dso_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @brief Software reset. Restore the default values in user registers.[get] * * @param ctx read / write interface definitions - * @param val change the values of sw_reset in reg CTRL3_C + * @param val Get the values of sw_reset in reg CTRL3_C * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -2088,7 +2088,7 @@ int32_t lsm6dso_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * access with a serial interface.[get] * * @param ctx read / write interface definitions - * @param val change the values of if_inc in reg CTRL3_C + * @param val Get the values of if_inc in reg CTRL3_C * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -2131,7 +2131,7 @@ int32_t lsm6dso_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @brief Reboot memory content. Reload the calibration parameters.[get] * * @param ctx read / write interface definitions - * @param val change the values of boot in reg CTRL3_C + * @param val Get the values of boot in reg CTRL3_C * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -2313,7 +2313,7 @@ int32_t lsm6dso_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val) * @brief Accelerometer output from LPF2 filtering stage selection.[get] * * @param ctx read / write interface definitions - * @param val change the values of lpf2_xl_en in reg CTRL1_XL + * @param val Get the values of lpf2_xl_en in reg CTRL1_XL * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -2360,7 +2360,7 @@ int32_t lsm6dso_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val) * in CTRL6_C (15h).[get] * * @param ctx read / write interface definitions - * @param val change the values of lpf1_sel_g in reg CTRL4_C + * @param val Get the values of lpf1_sel_g in reg CTRL4_C * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -2406,7 +2406,7 @@ int32_t lsm6dso_filter_settling_mask_set(stmdev_ctx_t *ctx, * (XL and Gyro independently masked).[get] * * @param ctx read / write interface definitions - * @param val change the values of drdy_mask in reg CTRL4_C + * @param val Get the values of drdy_mask in reg CTRL4_C * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -2533,7 +2533,7 @@ int32_t lsm6dso_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val) * @brief Low pass filter 2 on 6D function selection.[get] * * @param ctx read / write interface definitions - * @param val change the values of low_pass_on_6d in reg CTRL8_XL + * @param val Get the values of low_pass_on_6d in reg CTRL8_XL * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -2731,7 +2731,7 @@ int32_t lsm6dso_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) * Active only during device exit from power-down mode.[get] * * @param ctx read / write interface definitions - * @param val change the values of fastsettl_mode_xl in reg CTRL8_XL + * @param val Get the values of fastsettl_mode_xl in reg CTRL8_XL * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -2812,7 +2812,7 @@ int32_t lsm6dso_xl_hp_path_internal_get(stmdev_ctx_t *ctx, * enabled only if the gyro is in HP mode.[set] * * @param ctx read / write interface definitions - * @param val Get the values of hp_en_g and hp_en_g + * @param val change the values of hp_en_g and hp_en_g * in reg CTRL7_G * @retval interface status (MANDATORY: return 0 -> no Error) * @@ -3110,7 +3110,7 @@ int32_t lsm6dso_aux_status_reg_get(stmdev_ctx_t *ctx, * @brief aux_xl_flag_data_ready: [get] AUX accelerometer data available * * @param ctx read / write interface definitions - * @param val change the values of xlda in reg STATUS_SPIAUX + * @param val Get the values of xlda in reg STATUS_SPIAUX * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -3130,7 +3130,7 @@ int32_t lsm6dso_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, * @brief aux_gy_flag_data_ready: [get] AUX gyroscope data available. * * @param ctx read / write interface definitions - * @param val change the values of gda in reg STATUS_SPIAUX + * @param val Get the values of gda in reg STATUS_SPIAUX * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -3150,7 +3150,7 @@ int32_t lsm6dso_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, * @brief High when the gyroscope output is in the settling phase.[get] * * @param ctx read / write interface definitions - * @param val change the values of gyro_settling in reg STATUS_SPIAUX + * @param val Get the values of gyro_settling in reg STATUS_SPIAUX * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -3403,7 +3403,7 @@ int32_t lsm6dso_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val) * This setting has priority over all other INT2 settings.[get] * * @param ctx read / write interface definitions - * @param val change the values of int2_drdy_ois in reg INT_OIS + * @param val Get the values of int2_drdy_ois in reg INT_OIS * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -4284,7 +4284,7 @@ int32_t lsm6dso_i3c_disable_set(stmdev_ctx_t *ctx, * @brief I3C Enable/Disable communication protocol.[get] * * @param ctx read / write interface definitions - * @param val change the values of i3c_disable in + * @param val Get the values of i3c_disable in * reg CTRL9_XL * @retval interface status (MANDATORY: return 0 -> no Error) * @@ -4549,7 +4549,7 @@ int32_t lsm6dso_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @brief All interrupt signals become available on INT1 pin.[get] * * @param ctx read / write interface definitions - * @param val change the values of int2_on_int1 in reg CTRL4_C + * @param val Get the values of int2_on_int1 in reg CTRL4_C * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -4793,7 +4793,7 @@ int32_t lsm6dso_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * WAKE_UP_DUR.[get] * * @param ctx read / write interface definitions - * @param val change the values of wk_ths in reg WAKE_UP_THS + * @param val Get the values of wk_ths in reg WAKE_UP_THS * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -4839,7 +4839,7 @@ int32_t lsm6dso_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, * 1LSb = 1 / ODR * * @param ctx read / write interface definitions - * @param val change the values of usr_off_on_wu in reg WAKE_UP_THS + * @param val Get the values of usr_off_on_wu in reg WAKE_UP_THS * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -4885,7 +4885,7 @@ int32_t lsm6dso_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) * 1LSb = 1 / ODR * * @param ctx read / write interface definitions - * @param val change the values of wake_dur in reg WAKE_UP_DUR + * @param val Get the values of wake_dur in reg WAKE_UP_DUR * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -4941,7 +4941,7 @@ int32_t lsm6dso_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @brief Enables gyroscope Sleep mode.[get] * * @param ctx read / write interface definitions - * @param val change the values of sleep_g in reg CTRL4_C + * @param val Get the values of sleep_g in reg CTRL4_C * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -5118,7 +5118,7 @@ int32_t lsm6dso_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) * 1 LSb = 512 / ODR * * @param ctx read / write interface definitions - * @param val change the values of sleep_dur in reg WAKE_UP_DUR + * @param val Get the values of sleep_dur in reg WAKE_UP_DUR * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -5174,7 +5174,7 @@ int32_t lsm6dso_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val) * @brief Enable Z direction in tap recognition.[get] * * @param ctx read / write interface definitions - * @param val change the values of tap_z_en in reg TAP_CFG0 + * @param val Get the values of tap_z_en in reg TAP_CFG0 * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -5218,7 +5218,7 @@ int32_t lsm6dso_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val) * @brief Enable Y direction in tap recognition.[get] * * @param ctx read / write interface definitions - * @param val change the values of tap_y_en in reg TAP_CFG0 + * @param val Get the values of tap_y_en in reg TAP_CFG0 * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -5262,7 +5262,7 @@ int32_t lsm6dso_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val) * @brief Enable X direction in tap recognition.[get] * * @param ctx read / write interface definitions - * @param val change the values of tap_x_en in reg TAP_CFG0 + * @param val Get the values of tap_x_en in reg TAP_CFG0 * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -5306,7 +5306,7 @@ int32_t lsm6dso_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) * @brief X-axis tap recognition threshold.[get] * * @param ctx read / write interface definitions - * @param val change the values of tap_ths_x in reg TAP_CFG1 + * @param val Get the values of tap_ths_x in reg TAP_CFG1 * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -5426,7 +5426,7 @@ int32_t lsm6dso_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val) * @brief Y-axis tap recognition threshold.[get] * * @param ctx read / write interface definitions - * @param val change the values of tap_ths_y in reg TAP_CFG2 + * @param val Get the values of tap_ths_y in reg TAP_CFG2 * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -5469,7 +5469,7 @@ int32_t lsm6dso_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val) * @brief Z-axis recognition threshold.[get] * * @param ctx read / write interface definitions - * @param val change the values of tap_ths_z in reg TAP_THS_6D + * @param val Get the values of tap_ths_z in reg TAP_THS_6D * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -5522,7 +5522,7 @@ int32_t lsm6dso_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) * value, 1LSB corresponds to 8*ODR_XL time.[get] * * @param ctx read / write interface definitions - * @param val change the values of shock in reg INT_DUR2 + * @param val Get the values of shock in reg INT_DUR2 * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -5577,7 +5577,7 @@ int32_t lsm6dso_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) * value, 1LSB corresponds to 4*ODR_XL time.[get] * * @param ctx read / write interface definitions - * @param val change the values of quiet in reg INT_DUR2 + * @param val Get the values of quiet in reg INT_DUR2 * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -5634,7 +5634,7 @@ int32_t lsm6dso_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) * 1LSB corresponds to 32*ODR_XL time.[get] * * @param ctx read / write interface definitions - * @param val change the values of dur in reg INT_DUR2 + * @param val Get the values of dur in reg INT_DUR2 * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -5816,7 +5816,7 @@ int32_t lsm6dso_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @brief 4D orientation detection enable.[get] * * @param ctx read / write interface definitions - * @param val change the values of d4d_en in reg TAP_THS_6D + * @param val Get the values of d4d_en in reg TAP_THS_6D * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -5970,7 +5970,7 @@ int32_t lsm6dso_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) * 1LSb = 1 / ODR * * @param ctx read / write interface definitions - * @param val change the values of ff_dur in reg FREE_FALL + * @param val Get the values of ff_dur in reg FREE_FALL * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -6042,7 +6042,7 @@ int32_t lsm6dso_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) * @brief FIFO watermark level selection.[get] * * @param ctx read / write interface definitions - * @param val change the values of wtm in reg FIFO_CTRL1 + * @param val Get the values of wtm in reg FIFO_CTRL1 * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -6105,7 +6105,7 @@ int32_t lsm6dso_compression_algo_init_set(stmdev_ctx_t *ctx, * @brief FIFO compression feature initialization request [get]. * * @param ctx read / write interface definitions - * @param val change the values of FIFO_COMPR_INIT in + * @param val Get the values of FIFO_COMPR_INIT in * reg EMB_FUNC_INIT_B * @retval interface status (MANDATORY: return 0 -> no Error) * @@ -6237,7 +6237,7 @@ int32_t lsm6dso_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get] * * @param ctx read / write interface definitions - * @param val change the values of odrchg_en in reg FIFO_CTRL2 + * @param val Get the values of odrchg_en in reg FIFO_CTRL2 * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -6283,7 +6283,7 @@ int32_t lsm6dso_compression_algo_real_time_set(stmdev_ctx_t *ctx, * @brief Enables/Disables compression algorithm runtime. [get] * * @param ctx read / write interface definitions - * @param val change the values of fifo_compr_rt_en in reg FIFO_CTRL2 + * @param val Get the values of fifo_compr_rt_en in reg FIFO_CTRL2 * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -6329,7 +6329,7 @@ int32_t lsm6dso_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) * threshold level.[get] * * @param ctx read / write interface definitions - * @param val change the values of stop_on_wtm in reg FIFO_CTRL2 + * @param val Get the values of stop_on_wtm in reg FIFO_CTRL2 * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -6827,7 +6827,7 @@ int32_t lsm6dso_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, /** * @brief Resets the internal counter of batching vents for a single sensor. - * This bit is automatically reset to zero if it was set to ‘1’.[set] + * This bit is automatically reset to zero if it was set to '1'.[set] * * @param ctx read / write interface definitions * @param val change the values of rst_counter_bdr in @@ -6854,10 +6854,10 @@ int32_t lsm6dso_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val) /** * @brief Resets the internal counter of batching events for a single sensor. - * This bit is automatically reset to zero if it was set to ‘1’.[get] + * This bit is automatically reset to zero if it was set to '1'.[get] * * @param ctx read / write interface definitions - * @param val change the values of rst_counter_bdr in + * @param val Get the values of rst_counter_bdr in * reg COUNTER_BDR_REG1 * @retval interface status (MANDATORY: return 0 -> no Error) * @@ -6913,7 +6913,7 @@ int32_t lsm6dso_batch_counter_threshold_set(stmdev_ctx_t *ctx, * @brief Batch data rate counter.[get] * * @param ctx read / write interface definitions - * @param val change the values of cnt_bdr_th in + * @param val Get the values of cnt_bdr_th in * reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1. * @retval interface status (MANDATORY: return 0 -> no Error) * @@ -6943,7 +6943,7 @@ int32_t lsm6dso_batch_counter_threshold_get(stmdev_ctx_t *ctx, * @brief Number of unread sensor data(TAG + 6 bytes) stored in FIFO.[get] * * @param ctx read / write interface definitions - * @param val change the values of diff_fifo in reg FIFO_STATUS1 + * @param val Get the values of diff_fifo in reg FIFO_STATUS1 * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -6989,7 +6989,7 @@ int32_t lsm6dso_fifo_status_get(stmdev_ctx_t *ctx, * @brief Smart FIFO full status.[get] * * @param ctx read / write interface definitions - * @param val change the values of fifo_full_ia in reg FIFO_STATUS2 + * @param val Get the values of fifo_full_ia in reg FIFO_STATUS2 * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -7008,7 +7008,7 @@ int32_t lsm6dso_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @brief FIFO overrun status.[get] * * @param ctx read / write interface definitions - * @param val change the values of fifo_over_run_latched in + * @param val Get the values of fifo_over_run_latched in * reg FIFO_STATUS2 * @retval interface status (MANDATORY: return 0 -> no Error) * @@ -7028,7 +7028,7 @@ int32_t lsm6dso_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @brief FIFO watermark status.[get] * * @param ctx read / write interface definitions - * @param val change the values of fifo_wtm_ia in reg FIFO_STATUS2 + * @param val Get the values of fifo_wtm_ia in reg FIFO_STATUS2 * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -7047,7 +7047,7 @@ int32_t lsm6dso_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @brief Identifies the sensor in FIFO_DATA_OUT.[get] * * @param ctx read / write interface definitions - * @param val change the values of tag_sensor in reg FIFO_DATA_OUT_TAG + * @param val Get the values of tag_sensor in reg FIFO_DATA_OUT_TAG * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -7074,6 +7074,10 @@ int32_t lsm6dso_fifo_sensor_tag_get(stmdev_ctx_t *ctx, *val = LSM6DSO_TEMPERATURE_TAG; break; + case LSM6DSO_TIMESTAMP_TAG: + *val = LSM6DSO_TIMESTAMP_TAG; + break; + case LSM6DSO_CFG_CHANGE_TAG: *val = LSM6DSO_CFG_CHANGE_TAG; break; @@ -7126,8 +7130,8 @@ int32_t lsm6dso_fifo_sensor_tag_get(stmdev_ctx_t *ctx, *val = LSM6DSO_SENSORHUB_SLAVE3_TAG; break; - case LSM6DSO_STEP_CPUNTER_TAG: - *val = LSM6DSO_STEP_CPUNTER_TAG; + case LSM6DSO_STEP_COUNTER_TAG: + *val = LSM6DSO_STEP_COUNTER_TAG; break; case LSM6DSO_GAME_ROTATION_TAG: @@ -7196,7 +7200,7 @@ int32_t lsm6dso_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val) * @brief Enable FIFO batching of pedometer embedded function values.[get] * * @param ctx read / write interface definitions - * @param val change the values of pedo_fifo_en in + * @param val Get the values of pedo_fifo_en in * reg LSM6DSO_EMB_FUNC_FIFO_CFG * @retval interface status (MANDATORY: return 0 -> no Error) * @@ -7262,7 +7266,7 @@ int32_t lsm6dso_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val) * @brief Enable FIFO batching data of first slave.[get] * * @param ctx read / write interface definitions - * @param val change the values of batch_ext_sens_0_en in + * @param val Get the values of batch_ext_sens_0_en in * reg SLV0_CONFIG * @retval interface status (MANDATORY: return 0 -> no Error) * @@ -7327,7 +7331,7 @@ int32_t lsm6dso_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val) * @brief Enable FIFO batching data of second slave.[get] * * @param ctx read / write interface definitions - * @param val change the values of batch_ext_sens_1_en in + * @param val Get the values of batch_ext_sens_1_en in * reg SLV1_CONFIG * @retval interface status (MANDATORY: return 0 -> no Error) * @@ -7392,7 +7396,7 @@ int32_t lsm6dso_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val) * @brief Enable FIFO batching data of third slave.[get] * * @param ctx read / write interface definitions - * @param val change the values of batch_ext_sens_2_en in + * @param val Get the values of batch_ext_sens_2_en in * reg SLV2_CONFIG * @retval interface status (MANDATORY: return 0 -> no Error) * @@ -7457,7 +7461,7 @@ int32_t lsm6dso_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val) * @brief Enable FIFO batching data of fourth slave.[get] * * @param ctx read / write interface definitions - * @param val change the values of batch_ext_sens_3_en in + * @param val Get the values of batch_ext_sens_3_en in * reg SLV3_CONFIG * @retval interface status (MANDATORY: return 0 -> no Error) * @@ -7717,7 +7721,7 @@ int32_t lsm6dso_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) * @brief DEN value stored in LSB of X-axis.[get] * * @param ctx read / write interface definitions - * @param val change the values of den_z in reg CTRL9_XL + * @param val Get the values of den_z in reg CTRL9_XL * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -7760,7 +7764,7 @@ int32_t lsm6dso_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) * @brief DEN value stored in LSB of Y-axis.[get] * * @param ctx read / write interface definitions - * @param val change the values of den_y in reg CTRL9_XL + * @param val Get the values of den_y in reg CTRL9_XL * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -7803,7 +7807,7 @@ int32_t lsm6dso_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val) * @brief DEN value stored in LSB of Z-axis.[get] * * @param ctx read / write interface definitions - * @param val change the values of den_x in reg CTRL9_XL + * @param val Get the values of den_x in reg CTRL9_XL * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -7902,7 +7906,7 @@ int32_t lsm6dso_pedo_sens_get(stmdev_ctx_t *ctx, * @brief Interrupt status bit for step detection.[get] * * @param ctx read / write interface definitions - * @param val change the values of is_step_det in reg EMB_FUNC_STATUS + * @param val Get the values of is_step_det in reg EMB_FUNC_STATUS * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -8100,7 +8104,7 @@ int32_t lsm6dso_pedo_int_mode_get(stmdev_ctx_t *ctx, * @brief Interrupt status bit for significant motion detection.[get] * * @param ctx read / write interface definitions - * @param val change the values of is_sigmot in reg EMB_FUNC_STATUS + * @param val Get the values of is_sigmot in reg EMB_FUNC_STATUS * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -8143,7 +8147,7 @@ int32_t lsm6dso_motion_flag_data_ready_get(stmdev_ctx_t *ctx, * @brief Interrupt status bit for tilt detection.[get] * * @param ctx read / write interface definitions - * @param val change the values of is_tilt in reg EMB_FUNC_STATUS + * @param val Get the values of is_tilt in reg EMB_FUNC_STATUS * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -8826,7 +8830,7 @@ int32_t lsm6dso_mag_x_orient_get(stmdev_ctx_t *ctx, * timeout interrupt event.[get] * * @param ctx read / write interface definitions - * @param val change the values of is_fsm_lc in reg EMB_FUNC_STATUS + * @param val Get the values of is_fsm_lc in reg EMB_FUNC_STATUS * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -9225,7 +9229,7 @@ int32_t lsm6dso_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val) * @brief FSM initialization request.[get] * * @param ctx read / write interface definitions - * @param val change the values of fsm_init in reg FSM_INIT + * @param val Get the values of fsm_init in reg FSM_INIT * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -9571,7 +9575,7 @@ int32_t lsm6dso_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) * @brief Sensor hub I2C master enable.[get] * * @param ctx read / write interface definitions - * @param val change the values of master_on in reg MASTER_CONFIG + * @param val Get the values of master_on in reg MASTER_CONFIG * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -9714,7 +9718,7 @@ int32_t lsm6dso_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) * @brief I2C interface pass-through.[get] * * @param ctx read / write interface definitions - * @param val change the values of pass_through_mode in + * @param val Get the values of pass_through_mode in * reg MASTER_CONFIG * @retval interface status (MANDATORY: return 0 -> no Error) * @@ -9943,7 +9947,7 @@ int32_t lsm6dso_sh_reset_set(stmdev_ctx_t *ctx) * @brief Reset Master logic and output registers.[get] * * @param ctx read / write interface definitions - * @param val change the values of rst_master_regs in reg MASTER_CONFIG + * @param val Get the values of rst_master_regs in reg MASTER_CONFIG * @retval interface status (MANDATORY: return 0 -> no Error) * */ @@ -10919,14 +10923,13 @@ int32_t lsm6dso_interrupt_mode_get(stmdev_ctx_t *ctx, if (ret == 0) { - ctrl3_c.h_lactive = val->active_low; + val->active_low = ctrl3_c.h_lactive; ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *) &tap_cfg0, 1); } if (ret == 0) { - tap_cfg0.lir = val->base_latched; - tap_cfg0.int_clr_on_read = val->base_latched | val->emb_latched; + val->base_latched = (tap_cfg0.lir & tap_cfg0.int_clr_on_read); ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); } @@ -10937,8 +10940,7 @@ int32_t lsm6dso_interrupt_mode_get(stmdev_ctx_t *ctx, if (ret == 0) { - page_rw.emb_func_lir = val->emb_latched; - ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1); + val->emb_latched = (page_rw.emb_func_lir & tap_cfg0.int_clr_on_read); } if (ret == 0) diff --git a/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.h b/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.h index df811d692dc4842306a2566f4495b9ff323333e5..078c8f13e7abc9697e542e8bc2c4459e33dfb048 100644 --- a/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.h +++ b/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.h @@ -50,7 +50,7 @@ extern "C" { /** if _BYTE_ORDER is not defined, choose the endianness of your architecture * by uncommenting the define which fits your platform endianness */ -//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN +/* #define DRV_BYTE_ORDER DRV_BIG_ENDIAN */ #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN #else /* defined __BYTE_ORDER__ */ @@ -111,16 +111,38 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ +int32_t lsm6dso_read_reg(stmdev_ctx_t* ctx, uint8_t reg, + uint8_t* data, + uint16_t len); +int32_t lsm6dso_write_reg(stmdev_ctx_t* ctx, uint8_t reg, + uint8_t* data, + uint16_t len); + /** * @} * @@ -2718,13 +2740,6 @@ typedef union * */ -int32_t lsm6dso_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len); -int32_t lsm6dso_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len); - float_t lsm6dso_from_fs2_to_mg(int16_t lsb); float_t lsm6dso_from_fs4_to_mg(int16_t lsb); float_t lsm6dso_from_fs8_to_mg(int16_t lsb); @@ -2743,7 +2758,7 @@ float_t lsm6dso_from_lsb_to_nsec(int16_t lsb); typedef enum { LSM6DSO_2g = 0, - LSM6DSO_16g = 1, /* if XL_FS_MODE = ‘1’ -> LSM6DSO_2g */ + LSM6DSO_16g = 1, /* if XL_FS_MODE = '1' -> LSM6DSO_2g */ LSM6DSO_4g = 2, LSM6DSO_8g = 3, } lsm6dso_fs_xl_t; @@ -3595,7 +3610,7 @@ typedef enum LSM6DSO_SENSORHUB_SLAVE1_TAG, LSM6DSO_SENSORHUB_SLAVE2_TAG, LSM6DSO_SENSORHUB_SLAVE3_TAG, - LSM6DSO_STEP_CPUNTER_TAG, + LSM6DSO_STEP_COUNTER_TAG, LSM6DSO_GAME_ROTATION_TAG, LSM6DSO_GEOMAG_ROTATION_TAG, LSM6DSO_ROTATION_TAG, @@ -3964,8 +3979,8 @@ typedef enum LSM6DSO_SPI_4W = 0x06, /* Only SPI: SDO / SDI separated pins */ LSM6DSO_SPI_3W = 0x07, /* Only SPI: SDO / SDI share the same pin */ LSM6DSO_I2C = 0x04, /* Only I2C */ - LSM6DSO_I3C_T_50us = 0x02, /* I3C: available time equal to 50 μs */ - LSM6DSO_I3C_T_2us = 0x12, /* I3C: available time equal to 2 μs */ + LSM6DSO_I3C_T_50us = 0x02, /* I3C: available time equal to 50 us */ + LSM6DSO_I3C_T_2us = 0x12, /* I3C: available time equal to 2 us */ LSM6DSO_I3C_T_1ms = 0x22, /* I3C: available time equal to 1 ms */ LSM6DSO_I3C_T_25ms = 0x32, /* I3C: available time equal to 25 ms */ } lsm6dso_ui_bus_md_t; diff --git a/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.c b/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.c index 105707d7e0e0bde79ac713103c873e6657dadf0d..d44356334375ae73dd85e105b585f212ad732ada 100644 --- a/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.c +++ b/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lsm6dsox_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t lsm6dsox_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lsm6dsox_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -11911,14 +11911,13 @@ int32_t lsm6dsox_interrupt_mode_get(stmdev_ctx_t *ctx, if (ret == 0) { - ctrl3_c.h_lactive = val->active_low; + val->active_low = ctrl3_c.h_lactive; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *) &tap_cfg0, 1); } if (ret == 0) { - tap_cfg0.lir = val->base_latched; - tap_cfg0.int_clr_on_read = val->base_latched | val->emb_latched; + val->base_latched = (tap_cfg0.lir & tap_cfg0.int_clr_on_read); ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); } @@ -11929,8 +11928,7 @@ int32_t lsm6dsox_interrupt_mode_get(stmdev_ctx_t *ctx, if (ret == 0) { - page_rw.emb_func_lir = val->emb_latched; - ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); + val->emb_latched = (page_rw.emb_func_lir & tap_cfg0.int_clr_on_read); } if (ret == 0) diff --git a/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.h b/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.h index f4e3668aa8651ee8a22c6a2ccbf459050278217e..145b6bb46335b3622cf514fd60050ad9ebfe7ae8 100644 --- a/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.h +++ b/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -3006,6 +3009,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lsm6dsox_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.c b/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.c index 352d2bf3bba602ed1b67bf9f75e119a99b314f52..706e883cd18e73a78db374ae4e6e511a0e542e44 100644 --- a/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.c +++ b/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsr_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lsm6dsr_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t lsm6dsr_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsr_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lsm6dsr_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.h b/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.h index 4816043d4d8ea9dd71386fdfed598f2ce8263b69..1321ee9442c9a924e8110b15258b826677f85385 100644 --- a/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.h +++ b/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -2777,6 +2780,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lsm6dsr_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.c b/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.c index 6ec561fd411d6b8b44bdde9819a2ba1cd8754347..d4357d65b1e545988f85ffa1a160e45318a690d2 100644 --- a/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.c +++ b/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsrx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lsm6dsrx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t lsm6dsrx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsrx_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lsm6dsrx_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.h b/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.h index 85b763015760e88403fce6d8d5077dba9d639f1f..1a734795959eed5c78c6f53e2ce5433d0a0e0894 100644 --- a/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.h +++ b/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -2885,6 +2888,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lsm6dsrx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/lsm6dsv16bx_STdC/driver/lsm6dsv16bx_reg.c b/sensor/stmemsc/lsm6dsv16bx_STdC/driver/lsm6dsv16bx_reg.c new file mode 100644 index 0000000000000000000000000000000000000000..974eb477d421e884222a98ca5cd75498f1bbf736 --- /dev/null +++ b/sensor/stmemsc/lsm6dsv16bx_STdC/driver/lsm6dsv16bx_reg.c @@ -0,0 +1,8433 @@ +/** + ****************************************************************************** + * @file lsm6dsv16bx_reg.c + * @author Sensors Software Solution Team + * @brief LSM6DSV16BX driver file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2022 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "lsm6dsv16bx_reg.h" + +/** + * @defgroup LSM6DSV16BX + * @brief This file provides a set of functions needed to drive the + * lsm6dsv16bx enhanced inertial module. + * @{ + * + */ + +/** + * @defgroup Interfaces functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +/** + * @brief Read generic device register + * + * @param ctx communication interface handler.(ptr) + * @param reg first register address to read. + * @param data buffer for data read.(ptr) + * @param len number of consecutive register to read. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak lsm6dsv16bx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) +{ + int32_t ret; + + ret = ctx->read_reg(ctx->handle, reg, data, len); + + return ret; +} + +/** + * @brief Write generic device register + * + * @param ctx communication interface handler.(ptr) + * @param reg first register address to write. + * @param data the buffer contains data to be written.(ptr) + * @param len number of consecutive register to write. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak lsm6dsv16bx_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) +{ + int32_t ret; + + ret = ctx->write_reg(ctx->handle, reg, data, len); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Private functions + * @brief Section collect all the utility functions needed by APIs. + * @{ + * + */ + +static void bytecpy(uint8_t *target, uint8_t *source) +{ + if ((target != NULL) && (source != NULL)) + { + *target = *source; + } +} + +/** + * @} + * + */ + +/** + * @defgroup Sensitivity + * @brief These functions convert raw-data into engineering units. + * @{ + * + */ +float_t lsm6dsv16bx_from_sflp_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.061f; +} + +float_t lsm6dsv16bx_from_fs2_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.061f; +} + +float_t lsm6dsv16bx_from_fs4_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.122f; +} + +float_t lsm6dsv16bx_from_fs8_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.244f; +} + +float_t lsm6dsv16bx_from_fs16_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.488f; +} + +float_t lsm6dsv16bx_from_fs125_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 4.375f; +} + +float_t lsm6dsv16bx_from_fs250_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 8.750f; +} + +float_t lsm6dsv16bx_from_fs500_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 17.50f; +} + +float_t lsm6dsv16bx_from_fs1000_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 35.0f; +} + +float_t lsm6dsv16bx_from_fs2000_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 70.0f; +} + +float_t lsm6dsv16bx_from_fs4000_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 140.0f; +} + +float_t lsm6dsv16bx_from_lsb_to_celsius(int16_t lsb) +{ + return (((float_t)lsb / 256.0f) + 25.0f); +} + +uint64_t lsm6dsv16bx_from_lsb_to_nsec(uint32_t lsb) +{ + return ((uint64_t)lsb * 21750); +} + +/** + * @} + * + */ + +/** + * @defgroup Common + * @brief This section groups common useful functions. + * + */ + +/** + * @brief Reset of the device.[set] + * + * @param ctx read / write interface definitions + * @param val Reset of the device. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_reset_set(stmdev_ctx_t *ctx, lsm6dsv16bx_reset_t val) +{ + lsm6dsv16bx_func_cfg_access_t func_cfg_access; + lsm6dsv16bx_ctrl3_t ctrl3; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + ctrl3.boot = ((uint8_t)val & 0x04U) >> 2; + ctrl3.sw_reset = ((uint8_t)val & 0x02U) >> 1; + func_cfg_access.sw_por = (uint8_t)val & 0x01U; + + if (ret == 0) + { + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1); + } + if (ret == 0) + { + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Global reset of the device.[get] + * + * @param ctx read / write interface definitions + * @param val Global reset of the device. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_reset_get(stmdev_ctx_t *ctx, lsm6dsv16bx_reset_t *val) +{ + lsm6dsv16bx_func_cfg_access_t func_cfg_access; + lsm6dsv16bx_ctrl3_t ctrl3; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + switch ((ctrl3.sw_reset << 2) + (ctrl3.boot << 1) + func_cfg_access.sw_por) + { + case LSM6DSV16BX_READY: + *val = LSM6DSV16BX_READY; + break; + + case LSM6DSV16BX_GLOBAL_RST: + *val = LSM6DSV16BX_GLOBAL_RST; + break; + + case LSM6DSV16BX_RESTORE_CAL_PARAM: + *val = LSM6DSV16BX_RESTORE_CAL_PARAM; + break; + + case LSM6DSV16BX_RESTORE_CTRL_REGS: + *val = LSM6DSV16BX_RESTORE_CTRL_REGS; + break; + + default: + *val = LSM6DSV16BX_GLOBAL_RST; + break; + } + return ret; +} + +/** + * @brief Change memory bank.[set] + * + * @param ctx read / write interface definitions + * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_mem_bank_set(stmdev_ctx_t *ctx, lsm6dsv16bx_mem_bank_t val) +{ + lsm6dsv16bx_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret == 0) + { + func_cfg_access.emb_func_reg_access = (uint8_t)val & 0x01U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Change memory bank.[get] + * + * @param ctx read / write interface definitions + * @param val MAIN_MEM_BANK, SENSOR_HUB_MEM_BANK, EMBED_FUNC_MEM_BANK, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_mem_bank_get(stmdev_ctx_t *ctx, lsm6dsv16bx_mem_bank_t *val) +{ + lsm6dsv16bx_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + switch (func_cfg_access.emb_func_reg_access) + { + case LSM6DSV16BX_MAIN_MEM_BANK: + *val = LSM6DSV16BX_MAIN_MEM_BANK; + break; + + case LSM6DSV16BX_EMBED_FUNC_MEM_BANK: + *val = LSM6DSV16BX_EMBED_FUNC_MEM_BANK; + break; + + default: + *val = LSM6DSV16BX_MAIN_MEM_BANK; + break; + } + return ret; +} + +/** + * @brief Device ID.[get] + * + * @param ctx read / write interface definitions + * @param val Device ID. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_device_id_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16bx_who_am_i_t who_am_i; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WHO_AM_I, (uint8_t *)&who_am_i, 1); + *val = who_am_i.id; + + return ret; +} + +/** + * @brief Accelerometer output data rate (ODR) selection.[set] + * + * @param ctx read / write interface definitions + * @param val XL_ODR_OFF, XL_ODR_AT_1Hz875, XL_ODR_AT_7Hz5, XL_ODR_AT_15Hz, XL_ODR_AT_30Hz, XL_ODR_AT_60Hz, XL_ODR_AT_120Hz, XL_ODR_AT_240Hz, XL_ODR_AT_480Hz, XL_ODR_AT_960Hz, XL_ODR_AT_1920Hz, XL_ODR_AT_3840Hz, XL_ODR_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_xl_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_xl_data_rate_t val) +{ + lsm6dsv16bx_ctrl1_t ctrl1; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret == 0) + { + ctrl1.odr_xl = (uint8_t)val & 0xFU; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL1, (uint8_t *)&ctrl1, 1); + } + + return ret; +} + +/** + * @brief Accelerometer output data rate (ODR) selection.[get] + * + * @param ctx read / write interface definitions + * @param val XL_ODR_OFF, XL_ODR_AT_1Hz875, XL_ODR_AT_7Hz5, XL_ODR_AT_15Hz, XL_ODR_AT_30Hz, XL_ODR_AT_60Hz, XL_ODR_AT_120Hz, XL_ODR_AT_240Hz, XL_ODR_AT_480Hz, XL_ODR_AT_960Hz, XL_ODR_AT_1920Hz, XL_ODR_AT_3840Hz, XL_ODR_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_xl_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_xl_data_rate_t *val) +{ + lsm6dsv16bx_ctrl1_t ctrl1; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL1, (uint8_t *)&ctrl1, 1); + + switch (ctrl1.odr_xl) + { + case LSM6DSV16BX_XL_ODR_OFF: + *val = LSM6DSV16BX_XL_ODR_OFF; + break; + + case LSM6DSV16BX_XL_ODR_AT_1Hz875: + *val = LSM6DSV16BX_XL_ODR_AT_1Hz875; + break; + + case LSM6DSV16BX_XL_ODR_AT_7Hz5: + *val = LSM6DSV16BX_XL_ODR_AT_7Hz5; + break; + + case LSM6DSV16BX_XL_ODR_AT_15Hz: + *val = LSM6DSV16BX_XL_ODR_AT_15Hz; + break; + + case LSM6DSV16BX_XL_ODR_AT_30Hz: + *val = LSM6DSV16BX_XL_ODR_AT_30Hz; + break; + + case LSM6DSV16BX_XL_ODR_AT_60Hz: + *val = LSM6DSV16BX_XL_ODR_AT_60Hz; + break; + + case LSM6DSV16BX_XL_ODR_AT_120Hz: + *val = LSM6DSV16BX_XL_ODR_AT_120Hz; + break; + + case LSM6DSV16BX_XL_ODR_AT_240Hz: + *val = LSM6DSV16BX_XL_ODR_AT_240Hz; + break; + + case LSM6DSV16BX_XL_ODR_AT_480Hz: + *val = LSM6DSV16BX_XL_ODR_AT_480Hz; + break; + + case LSM6DSV16BX_XL_ODR_AT_960Hz: + *val = LSM6DSV16BX_XL_ODR_AT_960Hz; + break; + + case LSM6DSV16BX_XL_ODR_AT_1920Hz: + *val = LSM6DSV16BX_XL_ODR_AT_1920Hz; + break; + + case LSM6DSV16BX_XL_ODR_AT_3840Hz: + *val = LSM6DSV16BX_XL_ODR_AT_3840Hz; + break; + + case LSM6DSV16BX_XL_ODR_AT_7680Hz: + *val = LSM6DSV16BX_XL_ODR_AT_7680Hz; + break; + + default: + *val = LSM6DSV16BX_XL_ODR_OFF; + break; + } + return ret; +} + +/** + * @brief Accelerometer operating mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val XL_HIGH_PERFORMANCE_MD, XL_HIGH_ACCURANCY_ODR_MD, XL_LOW_POWER_2_AVG_MD, XL_LOW_POWER_4_AVG_MD, XL_LOW_POWER_8_AVG_MD, XL_NORMAL_MD, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_xl_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_xl_mode_t val) +{ + lsm6dsv16bx_ctrl1_t ctrl1; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL1, (uint8_t *)&ctrl1, 1); + + if (ret == 0) + { + ctrl1.op_mode_xl = (uint8_t)val & 0x07U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL1, (uint8_t *)&ctrl1, 1); + } + + return ret; +} + +/** + * @brief Accelerometer operating mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val XL_HIGH_PERFORMANCE_MD, XL_HIGH_ACCURANCY_ODR_MD, XL_LOW_POWER_2_AVG_MD, XL_LOW_POWER_4_AVG_MD, XL_LOW_POWER_8_AVG_MD, XL_NORMAL_MD, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_xl_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_xl_mode_t *val) +{ + lsm6dsv16bx_ctrl1_t ctrl1; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL1, (uint8_t *)&ctrl1, 1); + + switch (ctrl1.op_mode_xl) + { + case LSM6DSV16BX_XL_HIGH_PERFORMANCE_MD: + *val = LSM6DSV16BX_XL_HIGH_PERFORMANCE_MD; + break; + + case LSM6DSV16BX_XL_HIGH_ACCURANCY_ODR_MD: + *val = LSM6DSV16BX_XL_HIGH_ACCURANCY_ODR_MD; + break; + + case LSM6DSV16BX_XL_LOW_POWER_2_AVG_MD: + *val = LSM6DSV16BX_XL_LOW_POWER_2_AVG_MD; + break; + + case LSM6DSV16BX_XL_LOW_POWER_4_AVG_MD: + *val = LSM6DSV16BX_XL_LOW_POWER_4_AVG_MD; + break; + + case LSM6DSV16BX_XL_LOW_POWER_8_AVG_MD: + *val = LSM6DSV16BX_XL_LOW_POWER_8_AVG_MD; + break; + + case LSM6DSV16BX_XL_NORMAL_MD: + *val = LSM6DSV16BX_XL_NORMAL_MD; + break; + + default: + *val = LSM6DSV16BX_XL_HIGH_PERFORMANCE_MD; + break; + } + return ret; +} + +/** + * @brief Gyroscope output data rate (ODR) selection.[set] + * + * @param ctx read / write interface definitions + * @param val GY_ODR_OFF, GY_ODR_AT_7Hz5, GY_ODR_AT_15Hz, GY_ODR_AT_30Hz, GY_ODR_AT_60Hz, GY_ODR_AT_120Hz, GY_ODR_AT_240Hz, GY_ODR_AT_480Hz, GY_ODR_AT_960Hz, GY_ODR_AT_1920Hz, GY_ODR_AT_3840Hz, GY_ODR_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_gy_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_gy_data_rate_t val) +{ + lsm6dsv16bx_ctrl2_t ctrl2; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL2, (uint8_t *)&ctrl2, 1); + + if (ret == 0) + { + ctrl2.odr_g = (uint8_t)val & 0xFU; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL2, (uint8_t *)&ctrl2, 1); + } + + return ret; +} + +/** + * @brief Gyroscope output data rate (ODR) selection.[get] + * + * @param ctx read / write interface definitions + * @param val GY_ODR_OFF, GY_ODR_AT_7Hz5, GY_ODR_AT_15Hz, GY_ODR_AT_30Hz, GY_ODR_AT_60Hz, GY_ODR_AT_120Hz, GY_ODR_AT_240Hz, GY_ODR_AT_480Hz, GY_ODR_AT_960Hz, GY_ODR_AT_1920Hz, GY_ODR_AT_3840Hz, GY_ODR_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_gy_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_gy_data_rate_t *val) +{ + lsm6dsv16bx_ctrl2_t ctrl2; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL2, (uint8_t *)&ctrl2, 1); + + switch (ctrl2.odr_g) + { + case LSM6DSV16BX_GY_ODR_OFF: + *val = LSM6DSV16BX_GY_ODR_OFF; + break; + + case LSM6DSV16BX_GY_ODR_AT_7Hz5: + *val = LSM6DSV16BX_GY_ODR_AT_7Hz5; + break; + + case LSM6DSV16BX_GY_ODR_AT_15Hz: + *val = LSM6DSV16BX_GY_ODR_AT_15Hz; + break; + + case LSM6DSV16BX_GY_ODR_AT_30Hz: + *val = LSM6DSV16BX_GY_ODR_AT_30Hz; + break; + + case LSM6DSV16BX_GY_ODR_AT_60Hz: + *val = LSM6DSV16BX_GY_ODR_AT_60Hz; + break; + + case LSM6DSV16BX_GY_ODR_AT_120Hz: + *val = LSM6DSV16BX_GY_ODR_AT_120Hz; + break; + + case LSM6DSV16BX_GY_ODR_AT_240Hz: + *val = LSM6DSV16BX_GY_ODR_AT_240Hz; + break; + + case LSM6DSV16BX_GY_ODR_AT_480Hz: + *val = LSM6DSV16BX_GY_ODR_AT_480Hz; + break; + + case LSM6DSV16BX_GY_ODR_AT_960Hz: + *val = LSM6DSV16BX_GY_ODR_AT_960Hz; + break; + + case LSM6DSV16BX_GY_ODR_AT_1920Hz: + *val = LSM6DSV16BX_GY_ODR_AT_1920Hz; + break; + + case LSM6DSV16BX_GY_ODR_AT_3840Hz: + *val = LSM6DSV16BX_GY_ODR_AT_3840Hz; + break; + + case LSM6DSV16BX_GY_ODR_AT_7680Hz: + *val = LSM6DSV16BX_GY_ODR_AT_7680Hz; + break; + + default: + *val = LSM6DSV16BX_GY_ODR_OFF; + break; + } + return ret; +} + +/** + * @brief Gyroscope operating mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val GY_HIGH_PERFORMANCE_MD, GY_HIGH_ACCURANCY_ODR_MD, GY_SLEEP_MD, GY_LOW_POWER_MD, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_gy_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_gy_mode_t val) +{ + lsm6dsv16bx_ctrl2_t ctrl2; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret == 0) + { + ctrl2.op_mode_g = (uint8_t)val & 0x07U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL2, (uint8_t *)&ctrl2, 1); + } + + return ret; +} + +/** + * @brief Gyroscope operating mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val GY_HIGH_PERFORMANCE_MD, GY_HIGH_ACCURANCY_ODR_MD, GY_SLEEP_MD, GY_LOW_POWER_MD, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_gy_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_gy_mode_t *val) +{ + lsm6dsv16bx_ctrl2_t ctrl2; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL2, (uint8_t *)&ctrl2, 1); + switch (ctrl2.op_mode_g) + { + case LSM6DSV16BX_GY_HIGH_PERFORMANCE_MD: + *val = LSM6DSV16BX_GY_HIGH_PERFORMANCE_MD; + break; + + case LSM6DSV16BX_GY_HIGH_ACCURANCY_ODR_MD: + *val = LSM6DSV16BX_GY_HIGH_ACCURANCY_ODR_MD; + break; + + case LSM6DSV16BX_GY_SLEEP_MD: + *val = LSM6DSV16BX_GY_SLEEP_MD; + break; + + case LSM6DSV16BX_GY_LOW_POWER_MD: + *val = LSM6DSV16BX_GY_LOW_POWER_MD; + break; + + default: + *val = LSM6DSV16BX_GY_HIGH_PERFORMANCE_MD; + break; + } + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[set] + * + * @param ctx read / write interface definitions + * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16bx_ctrl3_t ctrl3; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret == 0) + { + ctrl3.if_inc = val; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1); + } + + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[get] + * + * @param ctx read / write interface definitions + * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16bx_ctrl3_t ctrl3; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1); + *val = ctrl3.if_inc; + + + return ret; +} + +/** + * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [set] + * + * @param ctx read / write interface definitions + * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16bx_ctrl3_t ctrl3; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1); + + if (ret == 0) + { + ctrl3.bdu = val; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1); + } + + return ret; +} + +/** + * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [get] + * + * @param ctx read / write interface definitions + * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16bx_ctrl3_t ctrl3; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1); + *val = ctrl3.bdu; + + return ret; +} + +/** + * @brief Enables pulsed data-ready mode (~75 us).[set] + * + * @param ctx read / write interface definitions + * @param val DRDY_LATCHED, DRDY_PULSED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_data_ready_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_data_ready_mode_t val) +{ + lsm6dsv16bx_ctrl4_t ctrl4; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1); + + if (ret == 0) + { + ctrl4.drdy_pulsed = (uint8_t)val & 0x1U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1); + } + + return ret; +} + +/** + * @brief Enables pulsed data-ready mode (~75 us).[get] + * + * @param ctx read / write interface definitions + * @param val DRDY_LATCHED, DRDY_PULSED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_data_ready_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_data_ready_mode_t *val) +{ + lsm6dsv16bx_ctrl4_t ctrl4; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1); + + switch (ctrl4.drdy_pulsed) + { + case LSM6DSV16BX_DRDY_LATCHED: + *val = LSM6DSV16BX_DRDY_LATCHED; + break; + + case LSM6DSV16BX_DRDY_PULSED: + *val = LSM6DSV16BX_DRDY_PULSED; + break; + + default: + *val = LSM6DSV16BX_DRDY_LATCHED; + break; + } + return ret; +} + +/** + * @brief Gyroscope full-scale selection[set] + * + * @param ctx read / write interface definitions + * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_gy_full_scale_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_gy_full_scale_t val) +{ + lsm6dsv16bx_ctrl6_t ctrl6; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL6, (uint8_t *)&ctrl6, 1); + + if (ret == 0) + { + ctrl6.fs_g = (uint8_t)val & 0xFU; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL6, (uint8_t *)&ctrl6, 1); + } + + return ret; +} + +/** + * @brief Gyroscope full-scale selection[get] + * + * @param ctx read / write interface definitions + * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_gy_full_scale_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_gy_full_scale_t *val) +{ + lsm6dsv16bx_ctrl6_t ctrl6; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL6, (uint8_t *)&ctrl6, 1); + + switch (ctrl6.fs_g) + { + case LSM6DSV16BX_125dps: + *val = LSM6DSV16BX_125dps; + break; + + case LSM6DSV16BX_250dps: + *val = LSM6DSV16BX_250dps; + break; + + case LSM6DSV16BX_500dps: + *val = LSM6DSV16BX_500dps; + break; + + case LSM6DSV16BX_1000dps: + *val = LSM6DSV16BX_1000dps; + break; + + case LSM6DSV16BX_2000dps: + *val = LSM6DSV16BX_2000dps; + break; + + case LSM6DSV16BX_4000dps: + *val = LSM6DSV16BX_4000dps; + break; + + default: + *val = LSM6DSV16BX_125dps; + break; + } + return ret; +} + +/** + * @brief Accelerometer full-scale selection.[set] + * + * @param ctx read / write interface definitions + * @param val 2g, 4g, 8g, 16g, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_xl_full_scale_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_xl_full_scale_t val) +{ + lsm6dsv16bx_ctrl8_t ctrl8; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1); + + if (ret == 0) + { + ctrl8.fs_xl = (uint8_t)val & 0x3U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1); + } + + return ret; +} + +/** + * @brief Accelerometer full-scale selection.[get] + * + * @param ctx read / write interface definitions + * @param val 2g, 4g, 8g, 16g, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_xl_full_scale_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_xl_full_scale_t *val) +{ + lsm6dsv16bx_ctrl8_t ctrl8; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1); + + switch (ctrl8.fs_xl) + { + case LSM6DSV16BX_2g: + *val = LSM6DSV16BX_2g; + break; + + case LSM6DSV16BX_4g: + *val = LSM6DSV16BX_4g; + break; + + case LSM6DSV16BX_8g: + *val = LSM6DSV16BX_8g; + break; + + case LSM6DSV16BX_16g: + *val = LSM6DSV16BX_16g; + break; + + default: + *val = LSM6DSV16BX_2g; + break; + } + return ret; +} + +/** + * @brief It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.[set] + * + * @param ctx read / write interface definitions + * @param val It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_xl_dual_channel_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16bx_ctrl8_t ctrl8; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1); + + if (ret == 0) + { + ctrl8.xl_dualc_en = val; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1); + } + + return ret; +} + +/** + * @brief It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.[get] + * + * @param ctx read / write interface definitions + * @param val It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_xl_dual_channel_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16bx_ctrl8_t ctrl8; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1); + *val = ctrl8.xl_dualc_en; + + return ret; +} + +/** + * @brief Accelerometer self-test selection.[set] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_xl_self_test_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_xl_self_test_t val) +{ + lsm6dsv16bx_ctrl10_t ctrl10; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1); + + if (ret == 0) + { + ctrl10.st_xl = (uint8_t)val & 0x3U; + ctrl10.xl_st_offset = ((uint8_t)val & 0x04U) >> 2; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1); + } + + return ret; +} + +/** + * @brief Accelerometer self-test selection.[get] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_xl_self_test_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_xl_self_test_t *val) +{ + lsm6dsv16bx_ctrl10_t ctrl10; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1); + + //switch (ctrl10.xl_st_offset) + switch (ctrl10.st_xl) + { + case LSM6DSV16BX_XL_ST_DISABLE: + *val = LSM6DSV16BX_XL_ST_DISABLE; + break; + + case LSM6DSV16BX_XL_ST_POSITIVE: + *val = LSM6DSV16BX_XL_ST_POSITIVE; + break; + + case LSM6DSV16BX_XL_ST_NEGATIVE: + *val = LSM6DSV16BX_XL_ST_NEGATIVE; + break; + + default: + *val = LSM6DSV16BX_XL_ST_DISABLE; + break; + } + return ret; +} + +/** + * @brief Gyroscope self-test selection.[set] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_gy_self_test_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_gy_self_test_t val) +{ + lsm6dsv16bx_ctrl10_t ctrl10; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1); + + if (ret == 0) + { + ctrl10.st_g = (uint8_t)val & 0x3U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1); + } + + return ret; +} + +/** + * @brief Gyroscope self-test selection.[get] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_gy_self_test_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_gy_self_test_t *val) +{ + lsm6dsv16bx_ctrl10_t ctrl10; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1); + + switch (ctrl10.st_g) + { + case LSM6DSV16BX_GY_ST_DISABLE: + *val = LSM6DSV16BX_GY_ST_DISABLE; + break; + + case LSM6DSV16BX_GY_ST_POSITIVE: + *val = LSM6DSV16BX_GY_ST_POSITIVE; + break; + + case LSM6DSV16BX_GY_ST_NEGATIVE: + *val = LSM6DSV16BX_GY_ST_NEGATIVE; + break; + + default: + *val = LSM6DSV16BX_GY_ST_DISABLE; + break; + } + return ret; +} + +/** + * @brief Get the status of all the interrupt sources.[get] + * + * @param ctx read / write interface definitions + * @param val Get the status of all the interrupt sources. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_all_sources_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_all_sources_t *val) +{ + lsm6dsv16bx_emb_func_status_mainpage_t emb_func_status_mainpage; + lsm6dsv16bx_emb_func_exec_status_t emb_func_exec_status; + lsm6dsv16bx_fsm_status_mainpage_t fsm_status_mainpage; + lsm6dsv16bx_mlc_status_mainpage_t mlc_status_mainpage; + lsm6dsv16bx_functions_enable_t functions_enable; + lsm6dsv16bx_emb_func_src_t emb_func_src; + lsm6dsv16bx_fifo_status2_t fifo_status2; + lsm6dsv16bx_all_int_src_t all_int_src; + lsm6dsv16bx_wake_up_src_t wake_up_src; + lsm6dsv16bx_status_reg_t status_reg; + lsm6dsv16bx_d6d_src_t d6d_src; + lsm6dsv16bx_tap_src_t tap_src; + uint8_t buff[7]; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret == 0) + { + functions_enable.dis_rst_lir_all_int = PROPERTY_ENABLE; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_STATUS1, (uint8_t *)&buff, 4); + } + bytecpy((uint8_t *)&fifo_status2, &buff[1]); + bytecpy((uint8_t *)&all_int_src, &buff[2]); + bytecpy((uint8_t *)&status_reg, &buff[3]); + + val->fifo_ovr = fifo_status2.fifo_ovr_ia; + val->fifo_bdr = fifo_status2.counter_bdr_ia; + val->fifo_full = fifo_status2.fifo_full_ia; + val->fifo_th = fifo_status2.fifo_wtm_ia; + + val->free_fall = all_int_src.ff_ia; + val->wake_up = all_int_src.wu_ia; + val->six_d = all_int_src.d6d_ia; + + val->drdy_xl = status_reg.xlda; + val->drdy_gy = status_reg.gda; + val->drdy_temp = status_reg.tda; + val->drdy_ah_qvar = status_reg.ah_qvarda; + val->timestamp = status_reg.timestamp_endcount; + + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + if (ret == 0) + { + functions_enable.dis_rst_lir_all_int = PROPERTY_DISABLE; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_SRC, (uint8_t *)&buff, 7); + } + + if (ret == 0) + { + bytecpy((uint8_t *)&wake_up_src, &buff[0]); + bytecpy((uint8_t *)&tap_src, &buff[1]); + bytecpy((uint8_t *)&d6d_src, &buff[2]); + bytecpy((uint8_t *)&emb_func_status_mainpage, &buff[4]); + bytecpy((uint8_t *)&fsm_status_mainpage, &buff[5]); + bytecpy((uint8_t *)&mlc_status_mainpage, &buff[6]); + + val->sleep_change = wake_up_src.sleep_change_ia; + val->wake_up_x = wake_up_src.x_wu; + val->wake_up_y = wake_up_src.y_wu; + val->wake_up_z = wake_up_src.z_wu; + val->sleep_state = wake_up_src.sleep_state; + + val->tap_x = tap_src.x_tap; + val->tap_y = tap_src.y_tap; + val->tap_z = tap_src.z_tap; + val->tap_sign = tap_src.tap_sign; + val->double_tap = tap_src.double_tap; + val->single_tap = tap_src.single_tap; + + val->six_d_zl = d6d_src.zl; + val->six_d_zh = d6d_src.zh; + val->six_d_yl = d6d_src.yl; + val->six_d_yh = d6d_src.yh; + val->six_d_xl = d6d_src.xl; + val->six_d_xh = d6d_src.xh; + + val->step_detector = emb_func_status_mainpage.is_step_det; + val->tilt = emb_func_status_mainpage.is_tilt; + val->sig_mot = emb_func_status_mainpage.is_sigmot; + val->fsm_lc = emb_func_status_mainpage.is_fsm_lc; + + val->fsm1 = fsm_status_mainpage.is_fsm1; + val->fsm2 = fsm_status_mainpage.is_fsm2; + val->fsm3 = fsm_status_mainpage.is_fsm3; + val->fsm4 = fsm_status_mainpage.is_fsm4; + val->fsm5 = fsm_status_mainpage.is_fsm5; + val->fsm6 = fsm_status_mainpage.is_fsm6; + val->fsm7 = fsm_status_mainpage.is_fsm7; + val->fsm8 = fsm_status_mainpage.is_fsm8; + + val->mlc1 = mlc_status_mainpage.is_mlc1; + val->mlc2 = mlc_status_mainpage.is_mlc2; + val->mlc3 = mlc_status_mainpage.is_mlc3; + val->mlc4 = mlc_status_mainpage.is_mlc4; + } + + + if (ret == 0) + { + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status, 1); + } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + val->emb_func_stand_by = emb_func_exec_status.emb_func_endop; + val->emb_func_time_exceed = emb_func_exec_status.emb_func_exec_ovr; + val->step_count_inc = emb_func_src.stepcounter_bit_set; + val->step_count_overflow = emb_func_src.step_overflow; + val->step_on_delta_time = emb_func_src.step_count_delta_ia; + + val->step_detector = emb_func_src.step_detected; + + return ret; +} + +int32_t lsm6dsv16bx_flag_data_ready_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_data_ready_t *val) +{ + lsm6dsv16bx_status_reg_t status; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_STATUS_REG, (uint8_t *)&status, 1); + val->drdy_xl = status.xlda; + val->drdy_gy = status.gda; + val->drdy_temp = status.tda; + + return ret; +} + +/** + * @brief Temperature data output register[get] + * + * @param ctx read / write interface definitions + * @param val Temperature data output register + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_OUT_TEMP_L, &buff[0], 2); + *val = (int16_t)buff[1]; + *val = (*val * 256) + (int16_t)buff[0]; + + return ret; +} + +/** + * @brief Angular rate sensor.[get] + * + * @param ctx read / write interface definitions + * @param val Angular rate sensor. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_OUTX_L_G, &buff[0], 6); + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Linear acceleration sensor.[get] + * + * @param ctx read / write interface definitions + * @param val Linear acceleration sensor. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_OUTZ_L_A, &buff[0], 6); + val[2] = (int16_t)buff[1]; + val[2] = (val[2] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[0] = (int16_t)buff[5]; + val[0] = (val[0] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Linear acceleration sensor for Dual channel mode.[get] + * + * @param ctx read / write interface definitions + * @param val Linear acceleration sensor or Dual channel mode. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_dual_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_UI_OUTZ_L_A_OIS_DUALC, &buff[0], 6); + val[2] = (int16_t)buff[1]; + val[2] = (val[2] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[0] = (int16_t)buff[5]; + val[0] = (val[0] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Qvar data output register.[get] + * + * @param ctx read / write interface definitions + * @param val Qvar data output register. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_ah_qvar_raw_get(stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_AH_QVAR_OUT_L, &buff[0], 2); + *val = (int16_t)buff[1]; + *val = (*val * 256) + (int16_t)buff[0]; + + return ret; +} + +/** + * @brief Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement.[get] + * + * @param ctx read / write interface definitions + * @param val Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_odr_cal_reg_get(stmdev_ctx_t *ctx, int8_t *val) +{ + lsm6dsv16bx_internal_freq_t internal_freq; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INTERNAL_FREQ, (uint8_t *)&internal_freq, 1); + *val = (int8_t)internal_freq.freq_fine; + + return ret; +} + +/** + * @brief Enable accelerometer axis.[set] + * + * @param ctx read / write interface definitions + * @param val Enable accelerometer axis. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_xl_axis_set(stmdev_ctx_t *ctx, lsm6dsv16bx_xl_axis_t val) +{ + lsm6dsv16bx_tdm_cfg1_t tdm_cfg1; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1); + if (ret == 0) + { + tdm_cfg1.tdm_xl_z_en = val.z; + tdm_cfg1.tdm_xl_y_en = val.y; + tdm_cfg1.tdm_xl_x_en = val.x; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1); + } + + return ret; +} + +/** + * @brief Enable accelerometer axis.[get] + * + * @param ctx read / write interface definitions + * @param val Enable accelerometer axis. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_xl_axis_get(stmdev_ctx_t *ctx, lsm6dsv16bx_xl_axis_t *val) +{ + lsm6dsv16bx_tdm_cfg1_t tdm_cfg1; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1); + val->x = tdm_cfg1.tdm_xl_x_en; + val->y = tdm_cfg1.tdm_xl_y_en; + val->z = tdm_cfg1.tdm_xl_z_en; + + return ret; +} + +/** + * @brief Write buffer in a page.[set] + * + * @param ctx read / write interface definitions + * @param val Write buffer in a page. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, + uint8_t *buf, uint8_t len) +{ + lsm6dsv16bx_page_address_t page_address; + lsm6dsv16bx_page_sel_t page_sel; + lsm6dsv16bx_page_rw_t page_rw; + uint8_t msb; + uint8_t lsb; + int32_t ret; + uint8_t i ; + + msb = ((uint8_t)(address >> 8) & 0x0FU); + lsb = (uint8_t)address & 0xFFU; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + + /* set page write */ + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_ENABLE; + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); + + /* select page */ + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, 1); + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + + /* set page addr */ + page_address.page_addr = lsb; + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + + for (i = 0; ((i < len) && (ret == 0)); i++) + { + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_VALUE, &buf[i], 1); + lsb++; + + /* Check if page wrap */ + if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) + { + msb++; + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, 1); + + if (ret == 0) + { + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + } + } + } + + page_sel.page_sel = 0; + page_sel.not_used0 = 1;// Default value + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + + /* unset page write */ + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Read buffer in a page.[set] + * + * @param ctx read / write interface definitions + * @param val Write buffer in a page. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, + uint8_t *buf, uint8_t len) +{ + lsm6dsv16bx_page_address_t page_address; + lsm6dsv16bx_page_sel_t page_sel; + lsm6dsv16bx_page_rw_t page_rw; + uint8_t msb; + uint8_t lsb; + int32_t ret; + uint8_t i ; + + msb = ((uint8_t)(address >> 8) & 0x0FU); + lsb = (uint8_t)address & 0xFFU; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + + /* set page write */ + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_ENABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); + + /* select page */ + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, 1); + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + + /* set page addr */ + page_address.page_addr = lsb; + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + + for (i = 0; ((i < len) && (ret == 0)); i++) + { + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_VALUE, &buf[i], 1); + lsb++; + + /* Check if page wrap */ + if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) + { + msb++; + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, 1); + + if (ret == 0) + { + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + } + } + } + + page_sel.page_sel = 0; + page_sel.not_used0 = 1;// Default value + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + + /* unset page write */ + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Timestamp + * @brief This section groups all the functions that manage the + * timestamp generation. + * @{ + * + */ + +/** + * @brief Enables timestamp counter.[set] + * + * @param ctx read / write interface definitions + * @param val Enables timestamp counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16bx_functions_enable_t functions_enable; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret == 0) + { + functions_enable.timestamp_en = val; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + return ret; +} + +/** + * @brief Enables timestamp counter.[get] + * + * @param ctx read / write interface definitions + * @param val Enables timestamp counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16bx_functions_enable_t functions_enable; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + *val = functions_enable.timestamp_en; + + return ret; +} + +/** + * @brief Timestamp data output.[get] + * + * @param ctx read / write interface definitions + * @param val Timestamp data output. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) +{ + uint8_t buff[4]; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TIMESTAMP0, &buff[0], 4); + *val = buff[3]; + *val = (*val * 256U) + buff[2]; + *val = (*val * 256U) + buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Filters + * @brief This section group all the functions concerning the + * filters configuration + * @{ + * + */ + +/** + * @brief Protocol anti-spike filters.[set] + * + * @param ctx read / write interface definitions + * @param val AUTO, ALWAYS_ACTIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_filt_anti_spike_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_anti_spike_t val) +{ + lsm6dsv16bx_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1); + + if (ret == 0) + { + if_cfg.asf_ctrl = (uint8_t)val & 0x01U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Protocol anti-spike filters.[get] + * + * @param ctx read / write interface definitions + * @param val AUTO, ALWAYS_ACTIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_filt_anti_spike_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_anti_spike_t *val) +{ + lsm6dsv16bx_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1); + switch (if_cfg.asf_ctrl) + { + case LSM6DSV16BX_AUTO: + *val = LSM6DSV16BX_AUTO; + break; + + case LSM6DSV16BX_ALWAYS_ACTIVE: + *val = LSM6DSV16BX_ALWAYS_ACTIVE; + break; + + default: + *val = LSM6DSV16BX_AUTO; + break; + } + return ret; +} + +/** + * @brief It masks DRDY and Interrupts RQ until filter settling ends.[set] + * + * @param ctx read / write interface definitions + * @param val It masks DRDY and Interrupts RQ until filter settling ends. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_filt_settling_mask_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_settling_mask_t val) +{ + lsm6dsv16bx_emb_func_cfg_t emb_func_cfg; + lsm6dsv16bx_tdm_cfg2_t tdm_cfg2; + lsm6dsv16bx_ctrl4_t ctrl4; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1); + + if (ret == 0) + { + ctrl4.drdy_mask = val.drdy; + + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + } + + if (ret == 0) + { + emb_func_cfg.emb_func_irq_mask_xl_settl = val.irq_xl; + emb_func_cfg.emb_func_irq_mask_g_settl = val.irq_g; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1); + } + + if (ret == 0) + { + tdm_cfg2.tdm_data_mask = val.tdm_excep_code; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1); + } + + return ret; +} + +/** + * @brief It masks DRDY and Interrupts RQ until filter settling ends.[get] + * + * @param ctx read / write interface definitions + * @param val It masks DRDY and Interrupts RQ until filter settling ends. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_filt_settling_mask_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_settling_mask_t *val) +{ + lsm6dsv16bx_emb_func_cfg_t emb_func_cfg; + lsm6dsv16bx_tdm_cfg2_t tdm_cfg2; + lsm6dsv16bx_ctrl4_t ctrl4; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1); + } + + val->drdy = ctrl4.drdy_mask; + val->irq_xl = emb_func_cfg.emb_func_irq_mask_xl_settl; + val->irq_g = emb_func_cfg.emb_func_irq_mask_g_settl; + val->tdm_excep_code = tdm_cfg2.tdm_data_mask; + + return ret; +} + +/** + * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[set] + * + * @param ctx read / write interface definitions + * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_filt_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_gy_lp1_bandwidth_t val) +{ + lsm6dsv16bx_ctrl6_t ctrl6; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL6, (uint8_t *)&ctrl6, 1); + if (ret == 0) + { + ctrl6.lpf1_g_bw = (uint8_t)val & 0x7U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL6, (uint8_t *)&ctrl6, 1); + } + + return ret; +} + +/** + * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[get] + * + * @param ctx read / write interface definitions + * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_filt_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_gy_lp1_bandwidth_t *val) +{ + lsm6dsv16bx_ctrl6_t ctrl6; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL6, (uint8_t *)&ctrl6, 1); + + switch (ctrl6.lpf1_g_bw) + { + case LSM6DSV16BX_GY_ULTRA_LIGHT: + *val = LSM6DSV16BX_GY_ULTRA_LIGHT; + break; + + case LSM6DSV16BX_GY_VERY_LIGHT: + *val = LSM6DSV16BX_GY_VERY_LIGHT; + break; + + case LSM6DSV16BX_GY_LIGHT: + *val = LSM6DSV16BX_GY_LIGHT; + break; + + case LSM6DSV16BX_GY_MEDIUM: + *val = LSM6DSV16BX_GY_MEDIUM; + break; + + case LSM6DSV16BX_GY_STRONG: + *val = LSM6DSV16BX_GY_STRONG; + break; + + case LSM6DSV16BX_GY_VERY_STRONG: + *val = LSM6DSV16BX_GY_VERY_STRONG; + break; + + case LSM6DSV16BX_GY_AGGRESSIVE: + *val = LSM6DSV16BX_GY_AGGRESSIVE; + break; + + case LSM6DSV16BX_GY_XTREME: + *val = LSM6DSV16BX_GY_XTREME; + break; + + default: + *val = LSM6DSV16BX_GY_ULTRA_LIGHT; + break; + } + return ret; +} + +/** + * @brief It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW.[set] + * + * @param ctx read / write interface definitions + * @param val It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_filt_gy_lp1_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16bx_ctrl7_t ctrl7; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1); + + if (ret == 0) + { + ctrl7.lpf1_g_en = val; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1); + } + + return ret; +} + +/** + * @brief It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW.[get] + * + * @param ctx read / write interface definitions + * @param val It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_filt_gy_lp1_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16bx_ctrl7_t ctrl7; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1); + *val = ctrl7.lpf1_g_en; + + return ret; +} + +/** + * @brief Qvar filter configuration.[set] + * + * @param ctx read / write interface definitions + * @param val Qvar filter configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_filt_ah_qvar_conf_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_ah_qvar_conf_t val) +{ + lsm6dsv16bx_ctrl9_t ctrl9; + lsm6dsv16bx_ctrl8_t ctrl8; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); + } + + ctrl8.ah_qvar_hpf = val.hpf; + ctrl9.ah_qvar_lpf = val.lpf; + + if (ret == 0) + { + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1); + } + if (ret == 0) + { + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Qvar filter configuration.[get] + * + * @param ctx read / write interface definitions + * @param val Qvar filter configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_filt_ah_qvar_conf_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_ah_qvar_conf_t *val) +{ + lsm6dsv16bx_ctrl8_t ctrl8; + lsm6dsv16bx_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); + } + + val->lpf = ctrl9.ah_qvar_lpf; + val->hpf = ctrl8.ah_qvar_hpf; + + return ret; +} + +/** + * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[set] + * + * @param ctx read / write interface definitions + * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_filt_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_xl_lp2_bandwidth_t val) +{ + lsm6dsv16bx_ctrl8_t ctrl8; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret == 0) + { + ctrl8.hp_lpf2_xl_bw = (uint8_t)val & 0x7U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1); + } + + return ret; +} + +/** + * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[get] + * + * @param ctx read / write interface definitions + * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_filt_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_xl_lp2_bandwidth_t *val) +{ + lsm6dsv16bx_ctrl8_t ctrl8; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1); + switch (ctrl8.hp_lpf2_xl_bw) + { + case LSM6DSV16BX_XL_ULTRA_LIGHT: + *val = LSM6DSV16BX_XL_ULTRA_LIGHT; + break; + + case LSM6DSV16BX_XL_VERY_LIGHT: + *val = LSM6DSV16BX_XL_VERY_LIGHT; + break; + + case LSM6DSV16BX_XL_LIGHT: + *val = LSM6DSV16BX_XL_LIGHT; + break; + + case LSM6DSV16BX_XL_MEDIUM: + *val = LSM6DSV16BX_XL_MEDIUM; + break; + + case LSM6DSV16BX_XL_STRONG: + *val = LSM6DSV16BX_XL_STRONG; + break; + + case LSM6DSV16BX_XL_VERY_STRONG: + *val = LSM6DSV16BX_XL_VERY_STRONG; + break; + + case LSM6DSV16BX_XL_AGGRESSIVE: + *val = LSM6DSV16BX_XL_AGGRESSIVE; + break; + + case LSM6DSV16BX_XL_XTREME: + *val = LSM6DSV16BX_XL_XTREME; + break; + + default: + *val = LSM6DSV16BX_XL_ULTRA_LIGHT; + break; + } + return ret; +} + +/** + * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[set] + * + * @param ctx read / write interface definitions + * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_filt_xl_lp2_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16bx_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.lpf2_xl_en = val; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[get] + * + * @param ctx read / write interface definitions + * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_filt_xl_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16bx_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); + *val = ctrl9.lpf2_xl_en; + + return ret; +} + +/** + * @brief Accelerometer slope filter / high-pass filter selection.[set] + * + * @param ctx read / write interface definitions + * @param val Accelerometer slope filter / high-pass filter selection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_filt_xl_hp_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16bx_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.hp_slope_xl_en = val; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Accelerometer slope filter / high-pass filter selection.[get] + * + * @param ctx read / write interface definitions + * @param val Accelerometer slope filter / high-pass filter selection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_filt_xl_hp_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16bx_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); + *val = ctrl9.hp_slope_xl_en; + + return ret; +} + +/** + * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[set] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_filt_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16bx_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.xl_fastsettl_mode = val; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[get] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_filt_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16bx_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); + *val = ctrl9.xl_fastsettl_mode; + + return ret; +} + +/** + * @brief Accelerometer high-pass filter mode.[set] + * + * @param ctx read / write interface definitions + * @param val HP_MD_NORMAL, HP_MD_REFERENCE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_filt_xl_hp_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_xl_hp_mode_t val) +{ + lsm6dsv16bx_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.hp_ref_mode_xl = (uint8_t)val & 0x01U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Accelerometer high-pass filter mode.[get] + * + * @param ctx read / write interface definitions + * @param val HP_MD_NORMAL, HP_MD_REFERENCE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_filt_xl_hp_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_xl_hp_mode_t *val) +{ + lsm6dsv16bx_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); + switch (ctrl9.hp_ref_mode_xl) + { + case LSM6DSV16BX_HP_MD_NORMAL: + *val = LSM6DSV16BX_HP_MD_NORMAL; + break; + + case LSM6DSV16BX_HP_MD_REFERENCE: + *val = LSM6DSV16BX_HP_MD_REFERENCE; + break; + + default: + *val = LSM6DSV16BX_HP_MD_NORMAL; + break; + } + return ret; +} + +/** + * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[set] + * + * @param ctx read / write interface definitions + * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_filt_wkup_act_feed_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_wkup_act_feed_t val) +{ + lsm6dsv16bx_wake_up_ths_t wake_up_ths; + lsm6dsv16bx_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + } + + tap_cfg0.slope_fds = (uint8_t)val & 0x01U; + wake_up_ths.usr_off_on_wu = ((uint8_t)val & 0x02U) >> 1; + + if (ret == 0) + { + + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + if (ret == 0) + { + + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + } + + return ret; +} + +/** + * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[get] + * + * @param ctx read / write interface definitions + * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_filt_wkup_act_feed_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_wkup_act_feed_t *val) +{ + lsm6dsv16bx_wake_up_ths_t wake_up_ths; + lsm6dsv16bx_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + switch ((wake_up_ths.usr_off_on_wu << 1) + tap_cfg0.slope_fds) + { + case LSM6DSV16BX_WK_FEED_SLOPE: + *val = LSM6DSV16BX_WK_FEED_SLOPE; + break; + + case LSM6DSV16BX_WK_FEED_HIGH_PASS: + *val = LSM6DSV16BX_WK_FEED_HIGH_PASS; + break; + + case LSM6DSV16BX_WK_FEED_LP_WITH_OFFSET: + *val = LSM6DSV16BX_WK_FEED_LP_WITH_OFFSET; + break; + + default: + *val = LSM6DSV16BX_WK_FEED_SLOPE; + break; + } + return ret; +} + +/** + * @brief Mask hw function triggers when xl is settling.[set] + * + * @param ctx read / write interface definitions + * @param val 0 or 1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_mask_trigger_xl_settl_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16bx_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + + if (ret == 0) + { + tap_cfg0.hw_func_mask_xl_settl = val & 0x01U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + return ret; +} + +/** + * @brief Mask hw function triggers when xl is settling.[get] + * + * @param ctx read / write interface definitions + * @param val 0 or 1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_mask_trigger_xl_settl_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16bx_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + *val = tap_cfg0.hw_func_mask_xl_settl; + + return ret; +} + + +/** + * @brief LPF2 filter on 6D (sixd) function selection.[set] + * + * @param ctx read / write interface definitions + * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_filt_sixd_feed_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_sixd_feed_t val) +{ + lsm6dsv16bx_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret == 0) + { + tap_cfg0.low_pass_on_6d = (uint8_t)val & 0x01U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + return ret; +} + +/** + * @brief LPF2 filter on 6D (sixd) function selection.[get] + * + * @param ctx read / write interface definitions + * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_filt_sixd_feed_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_sixd_feed_t *val) +{ + lsm6dsv16bx_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + switch (tap_cfg0.low_pass_on_6d) + { + case LSM6DSV16BX_SIXD_FEED_ODR_DIV_2: + *val = LSM6DSV16BX_SIXD_FEED_ODR_DIV_2; + break; + + case LSM6DSV16BX_SIXD_FEED_LOW_PASS: + *val = LSM6DSV16BX_SIXD_FEED_LOW_PASS; + break; + + default: + *val = LSM6DSV16BX_SIXD_FEED_ODR_DIV_2; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Serial interfaces + * @brief This section groups all the functions concerning + * serial interfaces management (not auxiliary) + * @{ + * + */ + +/** + * @brief Enables pull-up on SDO pin of UI (User Interface).[set] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDO pin of UI (User Interface). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16bx_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret == 0) + { + pin_ctrl.sdo_pu_en = val; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + + return ret; +} + +/** + * @brief Enables pull-up on SDO pin of UI (User Interface).[get] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDO pin of UI (User Interface). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16bx_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + *val = pin_ctrl.sdo_pu_en; + + return ret; +} + +/** + * @brief Disables I2C and I3C on UI (User Interface).[set] + * + * @param ctx read / write interface definitions + * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_ui_i2c_i3c_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_ui_i2c_i3c_mode_t val) +{ + lsm6dsv16bx_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.i2c_i3c_disable = (uint8_t)val & 0x01U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Disables I2C and I3C on UI (User Interface).[get] + * + * @param ctx read / write interface definitions + * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_ui_i2c_i3c_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_ui_i2c_i3c_mode_t *val) +{ + lsm6dsv16bx_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1); + switch (if_cfg.i2c_i3c_disable) + { + case LSM6DSV16BX_I2C_I3C_ENABLE: + *val = LSM6DSV16BX_I2C_I3C_ENABLE; + break; + + case LSM6DSV16BX_I2C_I3C_DISABLE: + *val = LSM6DSV16BX_I2C_I3C_DISABLE; + break; + + default: + *val = LSM6DSV16BX_I2C_I3C_ENABLE; + break; + } + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val SPI_4_WIRE, SPI_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_spi_mode_t val) +{ + lsm6dsv16bx_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.sim = (uint8_t)val & 0x01U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val SPI_4_WIRE, SPI_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_spi_mode_t *val) +{ + lsm6dsv16bx_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1); + switch (if_cfg.sim) + { + case LSM6DSV16BX_SPI_4_WIRE: + *val = LSM6DSV16BX_SPI_4_WIRE; + break; + + case LSM6DSV16BX_SPI_3_WIRE: + *val = LSM6DSV16BX_SPI_3_WIRE; + break; + + default: + *val = LSM6DSV16BX_SPI_4_WIRE; + break; + } + return ret; +} + +/** + * @brief Enables pull-up on SDA pin.[set] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDA pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_ui_sda_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16bx_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.sda_pu_en = (uint8_t)val & 0x01U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Enables pull-up on SDA pin.[get] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDA pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_ui_sda_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16bx_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1); + *val = if_cfg.sda_pu_en; + + return ret; +} + +/** + * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[set] + * + * @param ctx read / write interface definitions + * @param val IBI_2us, IBI_50us, IBI_1ms, IBI_25ms, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_i3c_ibi_time_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_i3c_ibi_time_t val) +{ + lsm6dsv16bx_ctrl5_t ctrl5; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret == 0) + { + ctrl5.bus_act_sel = (uint8_t)val & 0x03U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL5, (uint8_t *)&ctrl5, 1); + } + + return ret; +} + +/** + * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[get] + * + * @param ctx read / write interface definitions + * @param val IBI_2us, IBI_50us, IBI_1ms, IBI_25ms, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_i3c_ibi_time_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_i3c_ibi_time_t *val) +{ + lsm6dsv16bx_ctrl5_t ctrl5; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL5, (uint8_t *)&ctrl5, 1); + switch (ctrl5.bus_act_sel) + { + case LSM6DSV16BX_IBI_2us: + *val = LSM6DSV16BX_IBI_2us; + break; + + case LSM6DSV16BX_IBI_50us: + *val = LSM6DSV16BX_IBI_50us; + break; + + case LSM6DSV16BX_IBI_1ms: + *val = LSM6DSV16BX_IBI_1ms; + break; + + case LSM6DSV16BX_IBI_25ms: + *val = LSM6DSV16BX_IBI_25ms; + break; + + default: + *val = LSM6DSV16BX_IBI_2us; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Interrupt pins + * @brief This section groups all the functions that manage interrupt pins + * @{ + * + */ + +/** + * @brief Push-pull/open-drain selection on INT1 and INT2 pins.[set] + * + * @param ctx read / write interface definitions + * @param val PUSH_PULL, OPEN_DRAIN, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_int_pin_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_int_pin_mode_t val) +{ + lsm6dsv16bx_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.pp_od = (uint8_t)val & 0x01U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Push-pull/open-drain selection on INT1 and INT2 pins.[get] + * + * @param ctx read / write interface definitions + * @param val PUSH_PULL, OPEN_DRAIN, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_int_pin_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_int_pin_mode_t *val) +{ + lsm6dsv16bx_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1); + switch (if_cfg.pp_od) + { + case LSM6DSV16BX_PUSH_PULL: + *val = LSM6DSV16BX_PUSH_PULL; + break; + + case LSM6DSV16BX_OPEN_DRAIN: + *val = LSM6DSV16BX_OPEN_DRAIN; + break; + + default: + *val = LSM6DSV16BX_PUSH_PULL; + break; + } + return ret; +} + +/** + * @brief Interrupt activation level.[set] + * + * @param ctx read / write interface definitions + * @param val ACTIVE_HIGH, ACTIVE_LOW, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_pin_polarity_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_pin_polarity_t val) +{ + lsm6dsv16bx_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.h_lactive = (uint8_t)val & 0x01U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Interrupt activation level.[get] + * + * @param ctx read / write interface definitions + * @param val ACTIVE_HIGH, ACTIVE_LOW, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_pin_polarity_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_pin_polarity_t *val) +{ + lsm6dsv16bx_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1); + switch (if_cfg.h_lactive) + { + case LSM6DSV16BX_ACTIVE_HIGH: + *val = LSM6DSV16BX_ACTIVE_HIGH; + break; + + case LSM6DSV16BX_ACTIVE_LOW: + *val = LSM6DSV16BX_ACTIVE_LOW; + break; + + default: + *val = LSM6DSV16BX_ACTIVE_HIGH; + break; + } + return ret; +} + +/** + * @brief It routes interrupt signals on INT 1 pin.[set] + * + * @param ctx read / write interface definitions + * @param val It routes interrupt signals on INT 1 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_pin_int1_route_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_pin_int1_route_t val) +{ + lsm6dsv16bx_functions_enable_t functions_enable; + lsm6dsv16bx_pin_int2_route_t pin_int2_route; + lsm6dsv16bx_inactivity_dur_t inactivity_dur; + lsm6dsv16bx_emb_func_int1_t emb_func_int1; + lsm6dsv16bx_pedo_cmd_reg_t pedo_cmd_reg; + lsm6dsv16bx_int2_ctrl_t int2_ctrl; + lsm6dsv16bx_int1_ctrl_t int1_ctrl; + lsm6dsv16bx_fsm_int1_t fsm_int1; + lsm6dsv16bx_mlc_int1_t mlc_int1; + lsm6dsv16bx_md1_cfg_t md1_cfg; + lsm6dsv16bx_md2_cfg_t md2_cfg; + lsm6dsv16bx_ctrl4_t ctrl4; + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_INT1, (uint8_t *)&fsm_int1, 1); + } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MLC_INT1, (uint8_t *)&mlc_int1, 1); + } + + if (ret == 0) + { + emb_func_int1.int1_step_detector = val.step_detector; + emb_func_int1.int1_tilt = val.tilt; + emb_func_int1.int1_sig_mot = val.sig_mot; + emb_func_int1.int1_fsm_lc = val.fsm_lc; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + } + if (ret == 0) + { + fsm_int1.int1_fsm1 = val.fsm1; + fsm_int1.int1_fsm2 = val.fsm2; + fsm_int1.int1_fsm3 = val.fsm3; + fsm_int1.int1_fsm4 = val.fsm4; + fsm_int1.int1_fsm5 = val.fsm5; + fsm_int1.int1_fsm6 = val.fsm6; + fsm_int1.int1_fsm7 = val.fsm7; + fsm_int1.int1_fsm8 = val.fsm8; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FSM_INT1, (uint8_t *)&fsm_int1, 1); + } + if (ret == 0) + { + mlc_int1.int1_mlc1 = val.mlc1; + mlc_int1.int1_mlc2 = val.mlc2; + mlc_int1.int1_mlc3 = val.mlc3; + mlc_int1.int1_mlc4 = val.mlc4; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_MLC_INT1, (uint8_t *)&mlc_int1, 1); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1); + } + if (ret == 0) + { + if ((val.emb_func_stand_by | val.timestamp) != PROPERTY_DISABLE) + { + ctrl4.int2_on_int1 = PROPERTY_ENABLE; + } + else + { + ctrl4.int2_on_int1 = PROPERTY_DISABLE; + } + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + } + + if (ret == 0) + { + int2_ctrl.int2_emb_func_endop = val.emb_func_stand_by; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + } + + + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MD2_CFG, (uint8_t *)&md2_cfg, 1); + } + + if (ret == 0) + { + md2_cfg.int2_timestamp = val.timestamp; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_MD2_CFG, (uint8_t *)&md2_cfg, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + if (ret == 0) + { + inactivity_dur.sleep_status_on_int = val.sleep_status; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + } + + if (ret == 0) + { + int1_ctrl.int1_drdy_xl = val.drdy_xl; + int1_ctrl.int1_drdy_g = val.drdy_gy; + int1_ctrl.int1_fifo_th = val.fifo_th; + int1_ctrl.int1_fifo_ovr = val.fifo_ovr; + int1_ctrl.int1_fifo_full = val.fifo_full; + int1_ctrl.int1_cnt_bdr = val.fifo_bdr; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MD1_CFG, (uint8_t *)&md1_cfg, 1); + } + + if (ret == 0) + { + if ((emb_func_int1.int1_fsm_lc + | emb_func_int1.int1_sig_mot + | emb_func_int1.int1_step_detector + | emb_func_int1.int1_tilt + | fsm_int1.int1_fsm1 + | fsm_int1.int1_fsm2 + | fsm_int1.int1_fsm3 + | fsm_int1.int1_fsm4 + | fsm_int1.int1_fsm5 + | fsm_int1.int1_fsm6 + | fsm_int1.int1_fsm7 + | fsm_int1.int1_fsm8 + | mlc_int1.int1_mlc1 + | mlc_int1.int1_mlc2 + | mlc_int1.int1_mlc3 + | mlc_int1.int1_mlc4) != PROPERTY_DISABLE) + { + md1_cfg.int1_emb_func = PROPERTY_ENABLE; + } + else + { + md1_cfg.int1_emb_func = PROPERTY_DISABLE; + } + md1_cfg.int1_6d = val.six_d; + md1_cfg.int1_double_tap = val.double_tap; + md1_cfg.int1_ff = val.free_fall; + md1_cfg.int1_wu = val.wake_up; + md1_cfg.int1_single_tap = val.single_tap; + if ((val.sleep_status | val.sleep_change) != PROPERTY_DISABLE) + { + md1_cfg.int1_sleep_change = PROPERTY_ENABLE; + } + else + { + md1_cfg.int1_sleep_change = PROPERTY_DISABLE; + } + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_MD1_CFG, (uint8_t *)&md1_cfg, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + + if (ret == 0) + { + pedo_cmd_reg.carry_count_en = val.step_count_overflow; + ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + + + if (ret == 0) + { + ret = lsm6dsv16bx_pin_int2_route_get(ctx, &pin_int2_route); + } + + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + if (ret == 0) + { + if ((pin_int2_route.six_d + | pin_int2_route.double_tap + | pin_int2_route.free_fall + | pin_int2_route.wake_up + | pin_int2_route.single_tap + | pin_int2_route.sleep_status + | pin_int2_route.sleep_change + | val.six_d + | val.double_tap + | val.free_fall + | val.wake_up + | val.single_tap + | val.sleep_status + | val.sleep_change) != PROPERTY_DISABLE) + { + functions_enable.interrupts_enable = PROPERTY_ENABLE; + } + + else + { + functions_enable.interrupts_enable = PROPERTY_DISABLE; + } + + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + return ret; +} + +/** + * @brief It routes interrupt signals on INT 1 pin.[get] + * + * @param ctx read / write interface definitions + * @param val It routes interrupt signals on INT 1 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_pin_int1_route_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_pin_int1_route_t *val) +{ + lsm6dsv16bx_inactivity_dur_t inactivity_dur; + lsm6dsv16bx_emb_func_int1_t emb_func_int1; + lsm6dsv16bx_pedo_cmd_reg_t pedo_cmd_reg; + lsm6dsv16bx_int1_ctrl_t int1_ctrl; + lsm6dsv16bx_int2_ctrl_t int2_ctrl; + lsm6dsv16bx_fsm_int1_t fsm_int1; + lsm6dsv16bx_mlc_int1_t mlc_int1; + lsm6dsv16bx_md1_cfg_t md1_cfg; + lsm6dsv16bx_md2_cfg_t md2_cfg; + lsm6dsv16bx_ctrl4_t ctrl4; + int32_t ret; + + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1); + if (ctrl4.int2_on_int1 == PROPERTY_ENABLE) + { + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop; + } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MD2_CFG, (uint8_t *)&md2_cfg, 1); + val->timestamp = md2_cfg.int2_timestamp; + } + } + + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + val->sleep_status = inactivity_dur.sleep_status_on_int; + } + + + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + val->drdy_xl = int1_ctrl.int1_drdy_xl; + val->drdy_gy = int1_ctrl.int1_drdy_g; + val->fifo_th = int1_ctrl.int1_fifo_th; + val->fifo_ovr = int1_ctrl.int1_fifo_ovr; + val->fifo_full = int1_ctrl.int1_fifo_full; + val->fifo_bdr = int1_ctrl.int1_cnt_bdr; + } + + + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MD1_CFG, (uint8_t *)&md1_cfg, 1); + val->six_d = md1_cfg.int1_6d; + val->double_tap = md1_cfg.int1_double_tap; + val->free_fall = md1_cfg.int1_ff; + val->wake_up = md1_cfg.int1_wu; + val->single_tap = md1_cfg.int1_single_tap; + val->sleep_change = md1_cfg.int1_sleep_change; + } + + if (ret == 0) + { + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + val->step_detector = emb_func_int1.int1_step_detector; + val->tilt = emb_func_int1.int1_tilt; + val->sig_mot = emb_func_int1.int1_sig_mot; + val->fsm_lc = emb_func_int1.int1_fsm_lc; + } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_INT1, (uint8_t *)&fsm_int1, 1); + val->fsm1 = fsm_int1.int1_fsm1; + val->fsm2 = fsm_int1.int1_fsm2; + val->fsm3 = fsm_int1.int1_fsm3; + val->fsm4 = fsm_int1.int1_fsm4; + val->fsm5 = fsm_int1.int1_fsm5; + val->fsm6 = fsm_int1.int1_fsm6; + val->fsm7 = fsm_int1.int1_fsm7; + val->fsm8 = fsm_int1.int1_fsm8; + } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MLC_INT1, (uint8_t *)&mlc_int1, 1); + val->mlc1 = mlc_int1.int1_mlc1; + val->mlc2 = mlc_int1.int1_mlc2; + val->mlc3 = mlc_int1.int1_mlc3; + val->mlc4 = mlc_int1.int1_mlc4; + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + if (ret == 0) + { + ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + val->step_count_overflow = pedo_cmd_reg.carry_count_en; + } + + return ret; +} + + +/** + * @brief It routes interrupt signals on INT 2 pin.[set] + * + * @param ctx read / write interface definitions + * @param val It routes interrupt signals on INT 2 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_pin_int2_route_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_pin_int2_route_t val) +{ + lsm6dsv16bx_functions_enable_t functions_enable; + lsm6dsv16bx_pin_int1_route_t pin_int1_route; + lsm6dsv16bx_inactivity_dur_t inactivity_dur; + lsm6dsv16bx_emb_func_int2_t emb_func_int2; + lsm6dsv16bx_pedo_cmd_reg_t pedo_cmd_reg; + lsm6dsv16bx_int2_ctrl_t int2_ctrl; + lsm6dsv16bx_fsm_int2_t fsm_int2; + lsm6dsv16bx_mlc_int2_t mlc_int2; + lsm6dsv16bx_md2_cfg_t md2_cfg; + lsm6dsv16bx_ctrl4_t ctrl4; + int32_t ret; + + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_INT2, (uint8_t *)&fsm_int2, 1); + } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MLC_INT2, (uint8_t *)&mlc_int2, 1); + } + + if (ret == 0) + { + emb_func_int2.int2_step_detector = val.step_detector; + emb_func_int2.int2_tilt = val.tilt; + emb_func_int2.int2_sig_mot = val.sig_mot; + emb_func_int2.int2_fsm_lc = val.fsm_lc; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + } + if (ret == 0) + { + fsm_int2.int2_fsm1 = val.fsm1; + fsm_int2.int2_fsm2 = val.fsm2; + fsm_int2.int2_fsm3 = val.fsm3; + fsm_int2.int2_fsm4 = val.fsm4; + fsm_int2.int2_fsm5 = val.fsm5; + fsm_int2.int2_fsm6 = val.fsm6; + fsm_int2.int2_fsm7 = val.fsm7; + fsm_int2.int2_fsm8 = val.fsm8; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FSM_INT2, (uint8_t *)&fsm_int2, 1); + } + if (ret == 0) + { + mlc_int2.int2_mlc1 = val.mlc1; + mlc_int2.int2_mlc2 = val.mlc2; + mlc_int2.int2_mlc3 = val.mlc3; + mlc_int2.int2_mlc4 = val.mlc4; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_MLC_INT2, (uint8_t *)&mlc_int2, 1); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1); + } + if (ret == 0) + { + if ((val.emb_func_stand_by | val.timestamp) != PROPERTY_DISABLE) + { + ctrl4.int2_on_int1 = PROPERTY_DISABLE; + } + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + if (ret == 0) + { + inactivity_dur.sleep_status_on_int = val.sleep_status; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + } + + if (ret == 0) + { + int2_ctrl.int2_drdy_xl = val.drdy_xl; + int2_ctrl.int2_drdy_g = val.drdy_gy; + int2_ctrl.int2_fifo_th = val.fifo_th; + int2_ctrl.int2_fifo_ovr = val.fifo_ovr; + int2_ctrl.int2_fifo_full = val.fifo_full; + int2_ctrl.int2_cnt_bdr = val.fifo_bdr; + int2_ctrl.int2_emb_func_endop = val.emb_func_stand_by; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MD2_CFG, (uint8_t *)&md2_cfg, 1); + } + + if (ret == 0) + { + if ((emb_func_int2.int2_fsm_lc + | emb_func_int2.int2_sig_mot + | emb_func_int2.int2_step_detector + | emb_func_int2.int2_tilt + | fsm_int2.int2_fsm1 + | fsm_int2.int2_fsm2 + | fsm_int2.int2_fsm3 + | fsm_int2.int2_fsm4 + | fsm_int2.int2_fsm5 + | fsm_int2.int2_fsm6 + | fsm_int2.int2_fsm7 + | fsm_int2.int2_fsm8 + | mlc_int2.int2_mlc1 + | mlc_int2.int2_mlc2 + | mlc_int2.int2_mlc3 + | mlc_int2.int2_mlc4) != PROPERTY_DISABLE) + { + md2_cfg.int2_emb_func = PROPERTY_ENABLE; + } + else + { + md2_cfg.int2_emb_func = PROPERTY_DISABLE; + } + md2_cfg.int2_6d = val.six_d; + md2_cfg.int2_double_tap = val.double_tap; + md2_cfg.int2_ff = val.free_fall; + md2_cfg.int2_wu = val.wake_up; + md2_cfg.int2_single_tap = val.single_tap; + md2_cfg.int2_timestamp = val.timestamp; + if ((val.sleep_status | val.sleep_change) != PROPERTY_DISABLE) + { + md2_cfg.int2_sleep_change = PROPERTY_ENABLE; + } + else + { + md2_cfg.int2_sleep_change = PROPERTY_DISABLE; + } + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_MD2_CFG, (uint8_t *)&md2_cfg, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + + if (ret == 0) + { + pedo_cmd_reg.carry_count_en = val.step_count_overflow; + ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + + + if (ret == 0) + { + ret = lsm6dsv16bx_pin_int1_route_get(ctx, &pin_int1_route); + } + + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + if (ret == 0) + { + if ((pin_int1_route.six_d + | pin_int1_route.double_tap + | pin_int1_route.free_fall + | pin_int1_route.wake_up + | pin_int1_route.single_tap + | pin_int1_route.sleep_status + | pin_int1_route.sleep_change + | val.six_d + | val.double_tap + | val.free_fall + | val.wake_up + | val.single_tap + | val.sleep_status + | val.sleep_change) != PROPERTY_DISABLE) + { + functions_enable.interrupts_enable = PROPERTY_ENABLE; + } + + else + { + functions_enable.interrupts_enable = PROPERTY_DISABLE; + } + + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + return ret; +} + +/** + * @brief It routes interrupt signals on INT 2 pin.[get] + * + * @param ctx read / write interface definitions + * @param val It routes interrupt signals on INT 2 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_pin_int2_route_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_pin_int2_route_t *val) +{ + lsm6dsv16bx_inactivity_dur_t inactivity_dur; + lsm6dsv16bx_emb_func_int2_t emb_func_int2; + lsm6dsv16bx_pedo_cmd_reg_t pedo_cmd_reg; + lsm6dsv16bx_int2_ctrl_t int2_ctrl; + lsm6dsv16bx_fsm_int2_t fsm_int2; + lsm6dsv16bx_mlc_int2_t mlc_int2; + lsm6dsv16bx_md2_cfg_t md2_cfg; + lsm6dsv16bx_ctrl4_t ctrl4; + int32_t ret; + + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1); + if (ctrl4.int2_on_int1 == PROPERTY_DISABLE) + { + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop; + } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MD2_CFG, (uint8_t *)&md2_cfg, 1); + val->timestamp = md2_cfg.int2_timestamp; + } + } + + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + val->sleep_status = inactivity_dur.sleep_status_on_int; + } + + + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + val->drdy_xl = int2_ctrl.int2_drdy_xl; + val->drdy_gy = int2_ctrl.int2_drdy_g; + val->fifo_th = int2_ctrl.int2_fifo_th; + val->fifo_ovr = int2_ctrl.int2_fifo_ovr; + val->fifo_full = int2_ctrl.int2_fifo_full; + val->fifo_bdr = int2_ctrl.int2_cnt_bdr; + } + + + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MD2_CFG, (uint8_t *)&md2_cfg, 1); + val->six_d = md2_cfg.int2_6d; + val->double_tap = md2_cfg.int2_double_tap; + val->free_fall = md2_cfg.int2_ff; + val->wake_up = md2_cfg.int2_wu; + val->single_tap = md2_cfg.int2_single_tap; + val->sleep_change = md2_cfg.int2_sleep_change; + } + + if (ret == 0) + { + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + val->step_detector = emb_func_int2.int2_step_detector; + val->tilt = emb_func_int2.int2_tilt; + val->sig_mot = emb_func_int2.int2_sig_mot; + val->fsm_lc = emb_func_int2.int2_fsm_lc; + } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_INT2, (uint8_t *)&fsm_int2, 1); + val->fsm1 = fsm_int2.int2_fsm1; + val->fsm2 = fsm_int2.int2_fsm2; + val->fsm3 = fsm_int2.int2_fsm3; + val->fsm4 = fsm_int2.int2_fsm4; + val->fsm5 = fsm_int2.int2_fsm5; + val->fsm6 = fsm_int2.int2_fsm6; + val->fsm7 = fsm_int2.int2_fsm7; + val->fsm8 = fsm_int2.int2_fsm8; + } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MLC_INT2, (uint8_t *)&mlc_int2, 1); + val->mlc1 = mlc_int2.int2_mlc1; + val->mlc2 = mlc_int2.int2_mlc2; + val->mlc3 = mlc_int2.int2_mlc3; + val->mlc4 = mlc_int2.int2_mlc4; + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + if (ret == 0) + { + ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + val->step_count_overflow = pedo_cmd_reg.carry_count_en; + } + + return ret; +} + +/** + * @brief Enables INT pin when I3C is enabled.[set] + * + * @param ctx read / write interface definitions + * @param val Enables INT pin when I3C is enabled. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_pin_int_en_when_i2c_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16bx_ctrl5_t ctrl5; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret == 0) + { + ctrl5.int_en_i3c = val; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL5, (uint8_t *)&ctrl5, 1); + } + + return ret; +} + +/** + * @brief Enables INT pin when I3C is enabled.[get] + * + * @param ctx read / write interface definitions + * @param val Enables INT pin when I3C is enabled. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_pin_int_en_when_i2c_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16bx_ctrl5_t ctrl5; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL5, (uint8_t *)&ctrl5, 1); + *val = ctrl5.int_en_i3c; + + return ret; +} + +/** + * @brief Interrupt notification mode.[set] + * + * @param ctx read / write interface definitions + * @param val ALL_INT_PULSED, BASE_LATCHED_EMB_PULSED, BASE_PULSED_EMB_LATCHED, ALL_INT_LATCHED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_int_notification_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_int_notification_t val) +{ + lsm6dsv16bx_tap_cfg0_t tap_cfg0; + lsm6dsv16bx_page_rw_t page_rw; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret == 0) + { + tap_cfg0.lir = (uint8_t)val & 0x01U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); + } + + if (ret == 0) + { + page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Interrupt notification mode.[get] + * + * @param ctx read / write interface definitions + * @param val ALL_INT_PULSED, BASE_LATCHED_EMB_PULSED, BASE_PULSED_EMB_LATCHED, ALL_INT_LATCHED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_int_notification_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_int_notification_t *val) +{ + lsm6dsv16bx_tap_cfg0_t tap_cfg0; + lsm6dsv16bx_page_rw_t page_rw; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret == 0) + { + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + switch ((page_rw.emb_func_lir << 1) + tap_cfg0.lir) + { + case LSM6DSV16BX_ALL_INT_PULSED: + *val = LSM6DSV16BX_ALL_INT_PULSED; + break; + + case LSM6DSV16BX_BASE_LATCHED_EMB_PULSED: + *val = LSM6DSV16BX_BASE_LATCHED_EMB_PULSED; + break; + + case LSM6DSV16BX_BASE_PULSED_EMB_LATCHED: + *val = LSM6DSV16BX_BASE_PULSED_EMB_LATCHED; + break; + + case LSM6DSV16BX_ALL_INT_LATCHED: + *val = LSM6DSV16BX_ALL_INT_LATCHED; + break; + + default: + *val = LSM6DSV16BX_ALL_INT_PULSED; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Wake Up event and Activity / Inactivity detection + * @brief This section groups all the functions that manage the Wake Up + * event generation. + * @{ + * + */ + +/** + * @brief Enable activity/inactivity (sleep) function.[set] + * + * @param ctx read / write interface definitions + * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_act_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_act_mode_t val) +{ + lsm6dsv16bx_functions_enable_t functions_enable; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret == 0) + { + functions_enable.inact_en = (uint8_t)val & 0x03U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + return ret; +} + +/** + * @brief Enable activity/inactivity (sleep) function.[get] + * + * @param ctx read / write interface definitions + * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_act_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_act_mode_t *val) +{ + lsm6dsv16bx_functions_enable_t functions_enable; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + switch (functions_enable.inact_en) + { + case LSM6DSV16BX_XL_AND_GY_NOT_AFFECTED: + *val = LSM6DSV16BX_XL_AND_GY_NOT_AFFECTED; + break; + + case LSM6DSV16BX_XL_LOW_POWER_GY_NOT_AFFECTED: + *val = LSM6DSV16BX_XL_LOW_POWER_GY_NOT_AFFECTED; + break; + + case LSM6DSV16BX_XL_LOW_POWER_GY_SLEEP: + *val = LSM6DSV16BX_XL_LOW_POWER_GY_SLEEP; + break; + + case LSM6DSV16BX_XL_LOW_POWER_GY_POWER_DOWN: + *val = LSM6DSV16BX_XL_LOW_POWER_GY_POWER_DOWN; + break; + + default: + *val = LSM6DSV16BX_XL_AND_GY_NOT_AFFECTED; + break; + } + return ret; +} + +/** + * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[set] + * + * @param ctx read / write interface definitions + * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_act_from_sleep_to_act_dur_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_act_from_sleep_to_act_dur_t val) +{ + lsm6dsv16bx_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret == 0) + { + inactivity_dur.inact_dur = (uint8_t)val & 0x3U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + return ret; +} + +/** + * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[get] + * + * @param ctx read / write interface definitions + * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_act_from_sleep_to_act_dur_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_act_from_sleep_to_act_dur_t *val) +{ + lsm6dsv16bx_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + switch (inactivity_dur.inact_dur) + { + case LSM6DSV16BX_SLEEP_TO_ACT_AT_1ST_SAMPLE: + *val = LSM6DSV16BX_SLEEP_TO_ACT_AT_1ST_SAMPLE; + break; + + case LSM6DSV16BX_SLEEP_TO_ACT_AT_2ND_SAMPLE: + *val = LSM6DSV16BX_SLEEP_TO_ACT_AT_2ND_SAMPLE; + break; + + case LSM6DSV16BX_SLEEP_TO_ACT_AT_3RD_SAMPLE: + *val = LSM6DSV16BX_SLEEP_TO_ACT_AT_3RD_SAMPLE; + break; + + case LSM6DSV16BX_SLEEP_TO_ACT_AT_4th_SAMPLE: + *val = LSM6DSV16BX_SLEEP_TO_ACT_AT_4th_SAMPLE; + break; + + default: + *val = LSM6DSV16BX_SLEEP_TO_ACT_AT_1ST_SAMPLE; + break; + } + return ret; +} + +/** + * @brief Selects the accelerometer data rate during Inactivity.[set] + * + * @param ctx read / write interface definitions + * @param val 1Hz875, 15Hz, 30Hz, 60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_act_sleep_xl_odr_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_act_sleep_xl_odr_t val) +{ + lsm6dsv16bx_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret == 0) + { + inactivity_dur.xl_inact_odr = (uint8_t)val & 0x03U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + return ret; +} + +/** + * @brief Selects the accelerometer data rate during Inactivity.[get] + * + * @param ctx read / write interface definitions + * @param val 1Hz875, 15Hz, 30Hz, 60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_act_sleep_xl_odr_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_act_sleep_xl_odr_t *val) +{ + lsm6dsv16bx_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + switch (inactivity_dur.xl_inact_odr) + { + case LSM6DSV16BX_1Hz875: + *val = LSM6DSV16BX_1Hz875; + break; + + case LSM6DSV16BX_15Hz: + *val = LSM6DSV16BX_15Hz; + break; + + case LSM6DSV16BX_30Hz: + *val = LSM6DSV16BX_30Hz; + break; + + case LSM6DSV16BX_60Hz: + *val = LSM6DSV16BX_60Hz; + break; + + default: + *val = LSM6DSV16BX_1Hz875; + break; + } + return ret; +} + +/** + * @brief Wakeup and activity/inactivity threshold.[set] + * + * @param ctx read / write interface definitions + * @param val Wakeup and activity/inactivity threshold. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_act_thresholds_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_act_thresholds_t val) +{ + lsm6dsv16bx_inactivity_ths_t inactivity_ths; + lsm6dsv16bx_inactivity_dur_t inactivity_dur; + lsm6dsv16bx_wake_up_ths_t wake_up_ths; + int32_t ret; + float_t tmp; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + } + + if ((val.wk_ths_mg < (uint32_t)(7.8125f * 63.0f)) + && (val.inact_ths_mg < (uint32_t)(7.8125f * 63.0f))) + { + inactivity_dur.wu_inact_ths_w = 0; + + tmp = (float_t)val.inact_ths_mg / 7.8125f; + inactivity_ths.inact_ths = (uint8_t)tmp; + + tmp = (float_t)val.wk_ths_mg / 7.8125f; + wake_up_ths.wk_ths = (uint8_t)tmp; + } + else if ((val.wk_ths_mg < (uint32_t)(15.625f * 63.0f)) + && (val.inact_ths_mg < (uint32_t)(15.625f * 63.0f))) + { + inactivity_dur.wu_inact_ths_w = 1; + + tmp = (float_t)val.inact_ths_mg / 15.625f; + inactivity_ths.inact_ths = (uint8_t)tmp; + + tmp = (float_t)val.wk_ths_mg / 15.625f; + wake_up_ths.wk_ths = (uint8_t)tmp; + } + else if ((val.wk_ths_mg < (uint32_t)(31.25f * 63.0f)) + && (val.inact_ths_mg < (uint32_t)(31.25f * 63.0f))) + { + inactivity_dur.wu_inact_ths_w = 2; + + tmp = (float_t)val.inact_ths_mg / 31.25f; + inactivity_ths.inact_ths = (uint8_t)tmp; + + tmp = (float_t)val.wk_ths_mg / 31.25f; + wake_up_ths.wk_ths = (uint8_t)tmp; + } + else if ((val.wk_ths_mg < (uint32_t)(62.5f * 63.0f)) + && (val.inact_ths_mg < (uint32_t)(62.5f * 63.0f))) + { + inactivity_dur.wu_inact_ths_w = 3; + + tmp = (float_t)val.inact_ths_mg / 62.5f; + inactivity_ths.inact_ths = (uint8_t)tmp; + + tmp = (float_t)val.wk_ths_mg / 62.5f; + wake_up_ths.wk_ths = (uint8_t)tmp; + } + else if ((val.wk_ths_mg < (uint32_t)(125.0f * 63.0f)) + && (val.inact_ths_mg < (uint32_t)(125.0f * 63.0f))) + { + inactivity_dur.wu_inact_ths_w = 4; + + tmp = (float_t)val.inact_ths_mg / 125.0f; + inactivity_ths.inact_ths = (uint8_t)tmp; + + tmp = (float_t)val.wk_ths_mg / 125.0f; + wake_up_ths.wk_ths = (uint8_t)tmp; + } + else if ((val.wk_ths_mg < (uint32_t)(250.0f * 63.0f)) + && (val.inact_ths_mg < (uint32_t)(250.0f * 63.0f))) + { + inactivity_dur.wu_inact_ths_w = 5; + + tmp = (float_t)val.inact_ths_mg / 250.0f; + inactivity_ths.inact_ths = (uint8_t)tmp; + + tmp = (float_t)val.wk_ths_mg / 250.0f; + wake_up_ths.wk_ths = (uint8_t)tmp; + } + else // out of limit + { + inactivity_dur.wu_inact_ths_w = 5; + inactivity_ths.inact_ths = 0x3FU; + wake_up_ths.wk_ths = 0x3FU; + } + + if (ret == 0) + { + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + if (ret == 0) + { + + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); + } + if (ret == 0) + { + + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + } + + return ret; +} + +/** + * @brief Wakeup and activity/inactivity threshold.[get] + * + * @param ctx read / write interface definitions + * @param val Wakeup and activity/inactivity threshold. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_act_thresholds_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_act_thresholds_t *val) +{ + lsm6dsv16bx_inactivity_dur_t inactivity_dur; + lsm6dsv16bx_inactivity_ths_t inactivity_ths; + lsm6dsv16bx_wake_up_ths_t wake_up_ths; + int32_t ret; + float_t tmp; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); + } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + } + + switch (inactivity_dur.wu_inact_ths_w) + { + case 0: + tmp = (float_t)wake_up_ths.wk_ths * 7.8125f; + val->wk_ths_mg = (uint32_t)tmp; + + tmp = (float_t)inactivity_ths.inact_ths * 7.8125f; + val->inact_ths_mg = (uint32_t)tmp; + break; + + case 1: + tmp = (float_t)wake_up_ths.wk_ths * 15.625f; + val->wk_ths_mg = (uint32_t)tmp; + + tmp = (float_t)inactivity_ths.inact_ths * 15.625f; + val->inact_ths_mg = (uint32_t)tmp; + break; + + case 2: + tmp = (float_t)wake_up_ths.wk_ths * 31.25f; + val->wk_ths_mg = (uint32_t)tmp; + + tmp = (float_t)inactivity_ths.inact_ths * 31.25f; + val->inact_ths_mg = (uint32_t)tmp; + break; + + case 3: + tmp = (float_t)wake_up_ths.wk_ths * 62.5f; + val->wk_ths_mg = (uint32_t)tmp; + + tmp = (float_t)inactivity_ths.inact_ths * 62.5f; + val->inact_ths_mg = (uint32_t)tmp; + break; + + case 4: + tmp = (float_t)wake_up_ths.wk_ths * 125.0f; + val->wk_ths_mg = (uint32_t)tmp; + + tmp = (float_t)inactivity_ths.inact_ths * 125.0f; + val->inact_ths_mg = (uint32_t)tmp; + break; + + default: + tmp = (float_t)wake_up_ths.wk_ths * 250.0f; + val->wk_ths_mg = (uint32_t)tmp; + + tmp = (float_t)inactivity_ths.inact_ths * 250.0f; + val->inact_ths_mg = (uint32_t)tmp; + break; + } + + return ret; +} + +/** + * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [set] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_act_wkup_time_windows_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_act_wkup_time_windows_t val) +{ + lsm6dsv16bx_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + wake_up_dur.wake_dur = val.shock; + wake_up_dur.sleep_dur = val.quiet; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + } + + return ret; +} + +/** + * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [get] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_act_wkup_time_windows_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_act_wkup_time_windows_t *val) +{ + lsm6dsv16bx_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + val->shock = wake_up_dur.wake_dur; + val->quiet = wake_up_dur.sleep_dur; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Tap Generator + * @brief This section groups all the functions that manage the + * tap and double tap event generation. + * @{ + * + */ + +/** + * @brief Enable axis for Tap - Double Tap detection.[set] + * + * @param ctx read / write interface definitions + * @param val Enable axis for Tap - Double Tap detection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_tap_detection_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_tap_detection_t val) +{ + lsm6dsv16bx_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret == 0) + { + tap_cfg0.tap_x_en = val.tap_x_en; + tap_cfg0.tap_y_en = val.tap_y_en; + tap_cfg0.tap_z_en = val.tap_z_en; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + return ret; +} + +/** + * @brief Enable axis for Tap - Double Tap detection.[get] + * + * @param ctx read / write interface definitions + * @param val Enable axis for Tap - Double Tap detection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_tap_detection_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_tap_detection_t *val) +{ + lsm6dsv16bx_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + val->tap_x_en = tap_cfg0.tap_x_en; + val->tap_y_en = tap_cfg0.tap_y_en; + val->tap_z_en = tap_cfg0.tap_z_en; + + return ret; +} + +/** + * @brief axis Tap - Double Tap recognition thresholds.[set] + * + * @param ctx read / write interface definitions + * @param val axis Tap - Double Tap recognition thresholds. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_tap_thresholds_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_tap_thresholds_t val) +{ + lsm6dsv16bx_tap_ths_6d_t tap_ths_6d; + lsm6dsv16bx_tap_cfg2_t tap_cfg2; + lsm6dsv16bx_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + } + + tap_cfg1.tap_ths_z = val.z; + tap_cfg2.tap_ths_y = val.y; + tap_ths_6d.tap_ths_x = val.x; + + if (ret == 0) + { + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + } + if (ret == 0) + { + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + } + if (ret == 0) + { + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + } + + return ret; +} + +/** + * @brief axis Tap - Double Tap recognition thresholds.[get] + * + * @param ctx read / write interface definitions + * @param val axis Tap - Double Tap recognition thresholds. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_tap_thresholds_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_tap_thresholds_t *val) +{ + lsm6dsv16bx_tap_ths_6d_t tap_ths_6d; + lsm6dsv16bx_tap_cfg2_t tap_cfg2; + lsm6dsv16bx_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + } + + val->z = tap_cfg1.tap_ths_z; + val->y = tap_cfg2.tap_ths_y; + val->x = tap_ths_6d.tap_ths_x; + + return ret; +} + +/** + * @brief Selection of axis priority for TAP detection.[set] + * + * @param ctx read / write interface definitions + * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY , + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_tap_axis_priority_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_tap_axis_priority_t val) +{ + lsm6dsv16bx_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret == 0) + { + tap_cfg1.tap_priority = (uint8_t)val & 0x07U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + } + + return ret; +} + +/** + * @brief Selection of axis priority for TAP detection.[get] + * + * @param ctx read / write interface definitions + * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY , + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_tap_axis_priority_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_tap_axis_priority_t *val) +{ + lsm6dsv16bx_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + switch (tap_cfg1.tap_priority) + { + case LSM6DSV16BX_XYZ : + *val = LSM6DSV16BX_XYZ ; + break; + + case LSM6DSV16BX_YXZ : + *val = LSM6DSV16BX_YXZ ; + break; + + case LSM6DSV16BX_XZY: + *val = LSM6DSV16BX_XZY; + break; + + case LSM6DSV16BX_ZYX : + *val = LSM6DSV16BX_ZYX ; + break; + + case LSM6DSV16BX_YZX : + *val = LSM6DSV16BX_YZX ; + break; + + case LSM6DSV16BX_ZXY : + *val = LSM6DSV16BX_ZXY ; + break; + + default: + *val = LSM6DSV16BX_XYZ ; + break; + } + return ret; +} + + +/** + * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[set] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_tap_time_windows_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_tap_time_windows_t val) +{ + lsm6dsv16bx_tap_dur_t tap_dur; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_DUR, (uint8_t *)&tap_dur, 1); + if (ret == 0) + { + tap_dur.shock = val.shock; + tap_dur.quiet = val.quiet; + tap_dur.dur = val.tap_gap; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_DUR, (uint8_t *)&tap_dur, 1); + } + + return ret; +} + +/** + * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[get] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_tap_time_windows_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_tap_time_windows_t *val) +{ + lsm6dsv16bx_tap_dur_t tap_dur; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_DUR, (uint8_t *)&tap_dur, 1); + val->shock = tap_dur.shock; + val->quiet = tap_dur.quiet; + val->tap_gap = tap_dur.dur; + + return ret; +} + +/** + * @brief Single/double-tap event enable.[set] + * + * @param ctx read / write interface definitions + * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_tap_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_tap_mode_t val) +{ + lsm6dsv16bx_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret == 0) + { + wake_up_ths.single_double_tap = (uint8_t)val & 0x01U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + } + + return ret; +} + +/** + * @brief Single/double-tap event enable.[get] + * + * @param ctx read / write interface definitions + * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_tap_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_tap_mode_t *val) +{ + lsm6dsv16bx_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + switch (wake_up_ths.single_double_tap) + { + case LSM6DSV16BX_ONLY_SINGLE: + *val = LSM6DSV16BX_ONLY_SINGLE; + break; + + case LSM6DSV16BX_BOTH_SINGLE_DOUBLE: + *val = LSM6DSV16BX_BOTH_SINGLE_DOUBLE; + break; + + default: + *val = LSM6DSV16BX_ONLY_SINGLE; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Six position detection (6D) + * @brief This section groups all the functions concerning six position + * detection (6D). + * @{ + * + */ + +/** + * @brief Threshold for 4D/6D function.[set] + * + * @param ctx read / write interface definitions + * @param val DEG_80, DEG_70, DEG_60, DEG_50, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_6d_threshold_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_6d_threshold_t val) +{ + lsm6dsv16bx_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret == 0) + { + tap_ths_6d.sixd_ths = (uint8_t)val & 0x03U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + } + + return ret; +} + +/** + * @brief Threshold for 4D/6D function.[get] + * + * @param ctx read / write interface definitions + * @param val DEG_80, DEG_70, DEG_60, DEG_50, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_6d_threshold_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_6d_threshold_t *val) +{ + lsm6dsv16bx_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + switch (tap_ths_6d.sixd_ths) + { + case LSM6DSV16BX_DEG_80: + *val = LSM6DSV16BX_DEG_80; + break; + + case LSM6DSV16BX_DEG_70: + *val = LSM6DSV16BX_DEG_70; + break; + + case LSM6DSV16BX_DEG_60: + *val = LSM6DSV16BX_DEG_60; + break; + + case LSM6DSV16BX_DEG_50: + *val = LSM6DSV16BX_DEG_50; + break; + + default: + *val = LSM6DSV16BX_DEG_80; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Free fall + * @brief This section group all the functions concerning the free + * fall detection. + * @{ + * + */ + +/** + * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[set] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_ff_time_windows_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16bx_wake_up_dur_t wake_up_dur; + lsm6dsv16bx_free_fall_t free_fall; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + if (ret == 0) + { + free_fall.ff_dur = (uint8_t)val & 0x1FU; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + return ret; +} + +/** + * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[get] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_ff_time_windows_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16bx_wake_up_dur_t wake_up_dur; + lsm6dsv16bx_free_fall_t free_fall; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; + + return ret; +} + +/** + * @brief Free fall threshold setting.[set] + * + * @param ctx read / write interface definitions + * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_ff_thresholds_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_ff_thresholds_t val) +{ + lsm6dsv16bx_free_fall_t free_fall; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret == 0) + { + free_fall.ff_ths = (uint8_t)val & 0x7U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + return ret; +} + +/** + * @brief Free fall threshold setting.[get] + * + * @param ctx read / write interface definitions + * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_ff_thresholds_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_ff_thresholds_t *val) +{ + lsm6dsv16bx_free_fall_t free_fall; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FREE_FALL, (uint8_t *)&free_fall, 1); + + switch (free_fall.ff_ths) + { + case LSM6DSV16BX_156_mg: + *val = LSM6DSV16BX_156_mg; + break; + + case LSM6DSV16BX_219_mg: + *val = LSM6DSV16BX_219_mg; + break; + + case LSM6DSV16BX_250_mg: + *val = LSM6DSV16BX_250_mg; + break; + + case LSM6DSV16BX_312_mg: + *val = LSM6DSV16BX_312_mg; + break; + + case LSM6DSV16BX_344_mg: + *val = LSM6DSV16BX_344_mg; + break; + + case LSM6DSV16BX_406_mg: + *val = LSM6DSV16BX_406_mg; + break; + + case LSM6DSV16BX_469_mg: + *val = LSM6DSV16BX_469_mg; + break; + + case LSM6DSV16BX_500_mg: + *val = LSM6DSV16BX_500_mg; + break; + + default: + *val = LSM6DSV16BX_156_mg; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup FIFO + * @brief This section group all the functions concerning the fifo usage + * @{ + * + */ + +/** + * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[set] + * + * @param ctx read / write interface definitions + * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16bx_fifo_ctrl1_t fifo_ctrl1; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + + if (ret == 0) + { + fifo_ctrl1.wtm = val; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + } + + return ret; +} + +/** + * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[get] + * + * @param ctx read / write interface definitions + * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16bx_fifo_ctrl1_t fifo_ctrl1; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + *val = fifo_ctrl1.wtm; + + return ret; +} + +/** + * @brief When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.[set] + * + * @param ctx read / write interface definitions + * @param val When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_xl_dual_fsm_batch_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.xl_dualc_batch_from_fsm = val; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.[get] + * + * @param ctx read / write interface definitions + * @param val When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_xl_dual_fsm_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + *val = fifo_ctrl2.xl_dualc_batch_from_fsm; + + return ret; +} + +/** + * @brief It configures the compression algorithm to write non-compressed data at each rate.[set] + * + * @param ctx read / write interface definitions + * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_compress_algo_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_compress_algo_t val) +{ + lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.uncompr_rate = (uint8_t)val & 0x03U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief It configures the compression algorithm to write non-compressed data at each rate.[get] + * + * @param ctx read / write interface definitions + * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_compress_algo_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_compress_algo_t *val) +{ + lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + + switch (fifo_ctrl2.uncompr_rate) + { + case LSM6DSV16BX_CMP_DISABLE: + *val = LSM6DSV16BX_CMP_DISABLE; + break; + + case LSM6DSV16BX_CMP_8_TO_1: + *val = LSM6DSV16BX_CMP_8_TO_1; + break; + + case LSM6DSV16BX_CMP_16_TO_1: + *val = LSM6DSV16BX_CMP_16_TO_1; + break; + + case LSM6DSV16BX_CMP_32_TO_1: + *val = LSM6DSV16BX_CMP_32_TO_1; + break; + + default: + *val = LSM6DSV16BX_CMP_DISABLE; + break; + } + return ret; +} + +/** + * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set] + * + * @param ctx read / write interface definitions + * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, + uint8_t val) +{ + lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.odr_chg_en = val; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get] + * + * @param ctx read / write interface definitions + * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, + uint8_t *val) +{ + lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + *val = fifo_ctrl2.odr_chg_en; + + return ret; +} + +/** + * @brief Enables/Disables compression algorithm runtime.[set] + * + * @param ctx read / write interface definitions + * @param val Enables/Disables compression algorithm runtime. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_compress_algo_real_time_set(stmdev_ctx_t *ctx, + uint8_t val) +{ + lsm6dsv16bx_emb_func_en_b_t emb_func_en_b; + lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2; + + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.fifo_compr_rt_en = val; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + emb_func_en_b.fifo_compr_en = val; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enables/Disables compression algorithm runtime.[get] + * + * @param ctx read / write interface definitions + * @param val Enables/Disables compression algorithm runtime. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_compress_algo_real_time_get(stmdev_ctx_t *ctx, + uint8_t *val) +{ + lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + + *val = fifo_ctrl2.fifo_compr_rt_en; + + return ret; +} + +/** + * @brief Sensing chain FIFO stop values memorization at threshold level.[set] + * + * @param ctx read / write interface definitions + * @param val Sensing chain FIFO stop values memorization at threshold level. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.stop_on_wtm = val; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief Sensing chain FIFO stop values memorization at threshold level.[get] + * + * @param ctx read / write interface definitions + * @param val Sensing chain FIFO stop values memorization at threshold level. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + *val = fifo_ctrl2.stop_on_wtm; + + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[set] + * + * @param ctx read / write interface definitions + * @param val XL_NOT_BATCHED, XL_BATCHED_AT_1Hz875, XL_BATCHED_AT_7Hz5, XL_BATCHED_AT_15Hz, XL_BATCHED_AT_30Hz, XL_BATCHED_AT_60Hz, XL_BATCHED_AT_120Hz, XL_BATCHED_AT_240Hz, XL_BATCHED_AT_480Hz, XL_BATCHED_AT_960Hz, XL_BATCHED_AT_1920Hz, XL_BATCHED_AT_3840Hz, XL_BATCHED_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_xl_batch_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_xl_batch_t val) +{ + lsm6dsv16bx_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret == 0) + { + fifo_ctrl3.bdr_xl = (uint8_t)val & 0xFU; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + } + + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[get] + * + * @param ctx read / write interface definitions + * @param val XL_NOT_BATCHED, XL_BATCHED_AT_1Hz875, XL_BATCHED_AT_7Hz5, XL_BATCHED_AT_15Hz, XL_BATCHED_AT_30Hz, XL_BATCHED_AT_60Hz, XL_BATCHED_AT_120Hz, XL_BATCHED_AT_240Hz, XL_BATCHED_AT_480Hz, XL_BATCHED_AT_960Hz, XL_BATCHED_AT_1920Hz, XL_BATCHED_AT_3840Hz, XL_BATCHED_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_xl_batch_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_xl_batch_t *val) +{ + lsm6dsv16bx_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + switch (fifo_ctrl3.bdr_xl) + { + case LSM6DSV16BX_XL_NOT_BATCHED: + *val = LSM6DSV16BX_XL_NOT_BATCHED; + break; + + case LSM6DSV16BX_XL_BATCHED_AT_1Hz875: + *val = LSM6DSV16BX_XL_BATCHED_AT_1Hz875; + break; + + case LSM6DSV16BX_XL_BATCHED_AT_7Hz5: + *val = LSM6DSV16BX_XL_BATCHED_AT_7Hz5; + break; + + case LSM6DSV16BX_XL_BATCHED_AT_15Hz: + *val = LSM6DSV16BX_XL_BATCHED_AT_15Hz; + break; + + case LSM6DSV16BX_XL_BATCHED_AT_30Hz: + *val = LSM6DSV16BX_XL_BATCHED_AT_30Hz; + break; + + case LSM6DSV16BX_XL_BATCHED_AT_60Hz: + *val = LSM6DSV16BX_XL_BATCHED_AT_60Hz; + break; + + case LSM6DSV16BX_XL_BATCHED_AT_120Hz: + *val = LSM6DSV16BX_XL_BATCHED_AT_120Hz; + break; + + case LSM6DSV16BX_XL_BATCHED_AT_240Hz: + *val = LSM6DSV16BX_XL_BATCHED_AT_240Hz; + break; + + case LSM6DSV16BX_XL_BATCHED_AT_480Hz: + *val = LSM6DSV16BX_XL_BATCHED_AT_480Hz; + break; + + case LSM6DSV16BX_XL_BATCHED_AT_960Hz: + *val = LSM6DSV16BX_XL_BATCHED_AT_960Hz; + break; + + case LSM6DSV16BX_XL_BATCHED_AT_1920Hz: + *val = LSM6DSV16BX_XL_BATCHED_AT_1920Hz; + break; + + case LSM6DSV16BX_XL_BATCHED_AT_3840Hz: + *val = LSM6DSV16BX_XL_BATCHED_AT_3840Hz; + break; + + case LSM6DSV16BX_XL_BATCHED_AT_7680Hz: + *val = LSM6DSV16BX_XL_BATCHED_AT_7680Hz; + break; + + default: + *val = LSM6DSV16BX_XL_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[set] + * + * @param ctx read / write interface definitions + * @param val XL_NOT_BATCHED, XL_BATCHED_AT_1Hz875, XL_BATCHED_AT_7Hz5, XL_BATCHED_AT_15Hz, XL_BATCHED_AT_30Hz, XL_BATCHED_AT_60Hz, XL_BATCHED_AT_120Hz, XL_BATCHED_AT_240Hz, XL_BATCHED_AT_480Hz, XL_BATCHED_AT_960Hz, XL_BATCHED_AT_1920Hz, XL_BATCHED_AT_3840Hz, XL_BATCHED_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_gy_batch_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_gy_batch_t val) +{ + lsm6dsv16bx_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret == 0) + { + fifo_ctrl3.bdr_gy = (uint8_t)val & 0xFU; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + } + + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[get] + * + * @param ctx read / write interface definitions + * @param val XL_NOT_BATCHED, XL_BATCHED_AT_1Hz875, XL_BATCHED_AT_7Hz5, XL_BATCHED_AT_15Hz, XL_BATCHED_AT_30Hz, XL_BATCHED_AT_60Hz, XL_BATCHED_AT_120Hz, XL_BATCHED_AT_240Hz, XL_BATCHED_AT_480Hz, XL_BATCHED_AT_960Hz, XL_BATCHED_AT_1920Hz, XL_BATCHED_AT_3840Hz, XL_BATCHED_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_gy_batch_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_gy_batch_t *val) +{ + lsm6dsv16bx_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + switch (fifo_ctrl3.bdr_gy) + { + case LSM6DSV16BX_GY_NOT_BATCHED: + *val = LSM6DSV16BX_GY_NOT_BATCHED; + break; + + case LSM6DSV16BX_GY_BATCHED_AT_1Hz875: + *val = LSM6DSV16BX_GY_BATCHED_AT_1Hz875; + break; + + case LSM6DSV16BX_GY_BATCHED_AT_7Hz5: + *val = LSM6DSV16BX_GY_BATCHED_AT_7Hz5; + break; + + case LSM6DSV16BX_GY_BATCHED_AT_15Hz: + *val = LSM6DSV16BX_GY_BATCHED_AT_15Hz; + break; + + case LSM6DSV16BX_GY_BATCHED_AT_30Hz: + *val = LSM6DSV16BX_GY_BATCHED_AT_30Hz; + break; + + case LSM6DSV16BX_GY_BATCHED_AT_60Hz: + *val = LSM6DSV16BX_GY_BATCHED_AT_60Hz; + break; + + case LSM6DSV16BX_GY_BATCHED_AT_120Hz: + *val = LSM6DSV16BX_GY_BATCHED_AT_120Hz; + break; + + case LSM6DSV16BX_GY_BATCHED_AT_240Hz: + *val = LSM6DSV16BX_GY_BATCHED_AT_240Hz; + break; + + case LSM6DSV16BX_GY_BATCHED_AT_480Hz: + *val = LSM6DSV16BX_GY_BATCHED_AT_480Hz; + break; + + case LSM6DSV16BX_GY_BATCHED_AT_960Hz: + *val = LSM6DSV16BX_GY_BATCHED_AT_960Hz; + break; + + case LSM6DSV16BX_GY_BATCHED_AT_1920Hz: + *val = LSM6DSV16BX_GY_BATCHED_AT_1920Hz; + break; + + case LSM6DSV16BX_GY_BATCHED_AT_3840Hz: + *val = LSM6DSV16BX_GY_BATCHED_AT_3840Hz; + break; + + case LSM6DSV16BX_GY_BATCHED_AT_7680Hz: + *val = LSM6DSV16BX_GY_BATCHED_AT_7680Hz; + break; + + default: + *val = LSM6DSV16BX_GY_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief FIFO mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val BYPASS_MODE, FIFO_MODE, STREAM_WTM_TO_FULL_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_mode_t val) +{ + lsm6dsv16bx_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.fifo_mode = (uint8_t)val & 0x07U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief FIFO mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val BYPASS_MODE, FIFO_MODE, STREAM_WTM_TO_FULL_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_mode_t *val) +{ + lsm6dsv16bx_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + switch (fifo_ctrl4.fifo_mode) + { + case LSM6DSV16BX_BYPASS_MODE: + *val = LSM6DSV16BX_BYPASS_MODE; + break; + + case LSM6DSV16BX_FIFO_MODE: + *val = LSM6DSV16BX_FIFO_MODE; + break; + + case LSM6DSV16BX_STREAM_WTM_TO_FULL_MODE: + *val = LSM6DSV16BX_STREAM_WTM_TO_FULL_MODE; + break; + + case LSM6DSV16BX_STREAM_TO_FIFO_MODE: + *val = LSM6DSV16BX_STREAM_TO_FIFO_MODE; + break; + + case LSM6DSV16BX_BYPASS_TO_STREAM_MODE: + *val = LSM6DSV16BX_BYPASS_TO_STREAM_MODE; + break; + + case LSM6DSV16BX_STREAM_MODE: + *val = LSM6DSV16BX_STREAM_MODE; + break; + + case LSM6DSV16BX_BYPASS_TO_FIFO_MODE: + *val = LSM6DSV16BX_BYPASS_TO_FIFO_MODE; + break; + + default: + *val = LSM6DSV16BX_BYPASS_MODE; + break; + } + return ret; +} + +/** + * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[set] + * + * @param ctx read / write interface definitions + * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_temp_batch_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_temp_batch_t val) +{ + lsm6dsv16bx_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.odr_t_batch = (uint8_t)val & 0x03U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[get] + * + * @param ctx read / write interface definitions + * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_temp_batch_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_temp_batch_t *val) +{ + lsm6dsv16bx_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + switch (fifo_ctrl4.odr_t_batch) + { + case LSM6DSV16BX_TEMP_NOT_BATCHED: + *val = LSM6DSV16BX_TEMP_NOT_BATCHED; + break; + + case LSM6DSV16BX_TEMP_BATCHED_AT_1Hz875: + *val = LSM6DSV16BX_TEMP_BATCHED_AT_1Hz875; + break; + + case LSM6DSV16BX_TEMP_BATCHED_AT_15Hz: + *val = LSM6DSV16BX_TEMP_BATCHED_AT_15Hz; + break; + + case LSM6DSV16BX_TEMP_BATCHED_AT_60Hz: + *val = LSM6DSV16BX_TEMP_BATCHED_AT_60Hz; + break; + + default: + *val = LSM6DSV16BX_TEMP_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[set] + * + * @param ctx read / write interface definitions + * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_timestamp_batch_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_timestamp_batch_t val) +{ + lsm6dsv16bx_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.dec_ts_batch = (uint8_t)val & 0x3U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[get] + * + * @param ctx read / write interface definitions + * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_timestamp_batch_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_timestamp_batch_t *val) +{ + lsm6dsv16bx_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + switch (fifo_ctrl4.dec_ts_batch) + { + case LSM6DSV16BX_TMSTMP_NOT_BATCHED: + *val = LSM6DSV16BX_TMSTMP_NOT_BATCHED; + break; + + case LSM6DSV16BX_TMSTMP_DEC_1: + *val = LSM6DSV16BX_TMSTMP_DEC_1; + break; + + case LSM6DSV16BX_TMSTMP_DEC_8: + *val = LSM6DSV16BX_TMSTMP_DEC_8; + break; + + case LSM6DSV16BX_TMSTMP_DEC_32: + *val = LSM6DSV16BX_TMSTMP_DEC_32; + break; + + default: + *val = LSM6DSV16BX_TMSTMP_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[set] + * + * @param ctx read / write interface definitions + * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_batch_counter_threshold_set(stmdev_ctx_t *ctx, + uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[get] + * + * @param ctx read / write interface definitions + * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_batch_counter_threshold_get(stmdev_ctx_t *ctx, + uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, &buff[0], 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief Enables AH_QVAR batching in FIFO.[set] + * + * @param ctx read / write interface definitions + * @param val Enables AH_QVAR batching in FIFO. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_batch_ah_qvar_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16bx_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret == 0) + { + counter_bdr_reg1.ah_qvar_batch_en = val; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + } + + return ret; +} + +/** + * @brief Enables AH_QVAR batching in FIFO.[get] + * + * @param ctx read / write interface definitions + * @param val Enables AH_QVAR batching in FIFO. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_batch_ah_qvar_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16bx_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + *val = counter_bdr_reg1.ah_qvar_batch_en; + + return ret; +} + +/** + * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope and EIS gyroscope.[set] + * + * @param ctx read / write interface definitions + * @param val XL_BATCH_EVENT, GY_BATCH_EVENT, GY_EIS_BATCH_EVENT, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_batch_cnt_event_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_batch_cnt_event_t val) +{ + lsm6dsv16bx_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + + if (ret == 0) + { + counter_bdr_reg1.trig_counter_bdr = (uint8_t)val & 0x03U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + } + + return ret; +} + +/** + * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope and EIS gyroscope.[get] + * + * @param ctx read / write interface definitions + * @param val XL_BATCH_EVENT, GY_BATCH_EVENT, GY_EIS_BATCH_EVENT, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_batch_cnt_event_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_batch_cnt_event_t *val) +{ + lsm6dsv16bx_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + switch (counter_bdr_reg1.trig_counter_bdr) + { + case LSM6DSV16BX_XL_BATCH_EVENT: + *val = LSM6DSV16BX_XL_BATCH_EVENT; + break; + + case LSM6DSV16BX_GY_BATCH_EVENT: + *val = LSM6DSV16BX_GY_BATCH_EVENT; + break; + + case LSM6DSV16BX_GY_EIS_BATCH_EVENT: + *val = LSM6DSV16BX_GY_EIS_BATCH_EVENT; + break; + + default: + *val = LSM6DSV16BX_XL_BATCH_EVENT; + break; + } + return ret; +} + +/** + * @brief Batching in FIFO buffer of SFLP.[set] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of SFLP values. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_sflp_batch_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_sflp_raw_t val) +{ + lsm6dsv16bx_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + emb_func_fifo_en_a.sflp_game_fifo_en = val.game_rotation; + emb_func_fifo_en_a.sflp_gravity_fifo_en = val.gravity; + emb_func_fifo_en_a.sflp_gbias_fifo_en = val.gbias; + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_A, + (uint8_t *)&emb_func_fifo_en_a, 1); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Batching in FIFO buffer of SFLP.[get] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of SFLP values. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_sflp_batch_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_sflp_raw_t *val) +{ + lsm6dsv16bx_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + + val->game_rotation = emb_func_fifo_en_a.sflp_game_fifo_en; + val->gravity = emb_func_fifo_en_a.sflp_gravity_fifo_en; + val->gbias = emb_func_fifo_en_a.sflp_gbias_fifo_en; + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Status of FIFO.[get] + * + * @param ctx read / write interface definitions + * @param val Status of FIFO (level and flags). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_status_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_status_t *val) +{ + uint8_t buff[2]; + lsm6dsv16bx_fifo_status2_t status; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_STATUS1, (uint8_t *)&buff[0], 2); + bytecpy((uint8_t *)&status, &buff[1]); + + val->fifo_bdr = status.counter_bdr_ia; + val->fifo_ovr = status.fifo_ovr_ia; + val->fifo_full = status.fifo_full_ia; + val->fifo_th = status.fifo_wtm_ia; + + val->fifo_level = (uint16_t)buff[1] & 0x01U; + val->fifo_level = (val->fifo_level * 256U) + buff[0]; + + return ret; +} + +/** + * @brief FIFO data output[get] + * + * @param ctx read / write interface definitions + * @param val FIFO_EMPTY, GY_NC_TAG, XL_NC_TAG, TIMESTAMP_TAG, + TEMPERATURE_TAG, CFG_CHANGE_TAG, XL_NC_T_2_TAG, + XL_NC_T_1_TAG, XL_2XC_TAG, XL_3XC_TAG, GY_NC_T_2_TAG, + GY_NC_T_1_TAG, GY_2XC_TAG, GY_3XC_TAG, STEP_COUNTER_TAG, + SFLP_GAME_ROTATION_VECTOR_TAG, SFLP_GYROSCOPE_BIAS_TAG, + SFLP_GRAVITY_VECTOR_TAG, MLC_RESULT_TAG, + MLC_FILTER, MLC_FEATURE, XL_DUAL_CORE, AH_QVAR, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_out_raw_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_out_raw_t *val) +{ + lsm6dsv16bx_fifo_data_out_tag_t fifo_data_out_tag; + uint8_t buff[7]; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_DATA_OUT_TAG, buff, 7); + bytecpy((uint8_t *)&fifo_data_out_tag, &buff[0]); + + switch (fifo_data_out_tag.tag_sensor) + { + case LSM6DSV16BX_FIFO_EMPTY: + val->tag = LSM6DSV16BX_FIFO_EMPTY; + break; + + case LSM6DSV16BX_GY_NC_TAG: + val->tag = LSM6DSV16BX_GY_NC_TAG; + break; + + case LSM6DSV16BX_XL_NC_TAG: + val->tag = LSM6DSV16BX_XL_NC_TAG; + break; + + case LSM6DSV16BX_TIMESTAMP_TAG: + val->tag = LSM6DSV16BX_TIMESTAMP_TAG; + break; + + case LSM6DSV16BX_TEMPERATURE_TAG: + val->tag = LSM6DSV16BX_TEMPERATURE_TAG; + break; + + case LSM6DSV16BX_CFG_CHANGE_TAG: + val->tag = LSM6DSV16BX_CFG_CHANGE_TAG; + break; + + case LSM6DSV16BX_XL_NC_T_2_TAG: + val->tag = LSM6DSV16BX_XL_NC_T_2_TAG; + break; + + case LSM6DSV16BX_XL_NC_T_1_TAG: + val->tag = LSM6DSV16BX_XL_NC_T_1_TAG; + break; + + case LSM6DSV16BX_XL_2XC_TAG: + val->tag = LSM6DSV16BX_XL_2XC_TAG; + break; + + case LSM6DSV16BX_XL_3XC_TAG: + val->tag = LSM6DSV16BX_XL_3XC_TAG; + break; + + case LSM6DSV16BX_GY_NC_T_2_TAG: + val->tag = LSM6DSV16BX_GY_NC_T_2_TAG; + break; + + case LSM6DSV16BX_GY_NC_T_1_TAG: + val->tag = LSM6DSV16BX_GY_NC_T_1_TAG; + break; + + case LSM6DSV16BX_GY_2XC_TAG: + val->tag = LSM6DSV16BX_GY_2XC_TAG; + break; + + case LSM6DSV16BX_GY_3XC_TAG: + val->tag = LSM6DSV16BX_GY_3XC_TAG; + break; + + case LSM6DSV16BX_STEP_COUNTER_TAG: + val->tag = LSM6DSV16BX_STEP_COUNTER_TAG; + break; + + case LSM6DSV16BX_MLC_RESULT_TAG: + val->tag = LSM6DSV16BX_MLC_RESULT_TAG; + break; + + case LSM6DSV16BX_SFLP_GAME_ROTATION_VECTOR_TAG: + val->tag = LSM6DSV16BX_SFLP_GAME_ROTATION_VECTOR_TAG; + break; + + case LSM6DSV16BX_SFLP_GYROSCOPE_BIAS_TAG: + val->tag = LSM6DSV16BX_SFLP_GYROSCOPE_BIAS_TAG; + break; + + case LSM6DSV16BX_SFLP_GRAVITY_VECTOR_TAG: + val->tag = LSM6DSV16BX_SFLP_GRAVITY_VECTOR_TAG; + break; + + case LSM6DSV16BX_MLC_FILTER: + val->tag = LSM6DSV16BX_MLC_FILTER; + break; + + case LSM6DSV16BX_MLC_FEATURE: + val->tag = LSM6DSV16BX_MLC_FEATURE; + break; + + case LSM6DSV16BX_XL_DUAL_CORE: + val->tag = LSM6DSV16BX_XL_DUAL_CORE; + break; + + case LSM6DSV16BX_AH_QVAR: + val->tag = LSM6DSV16BX_AH_QVAR; + break; + + default: + val->tag = LSM6DSV16BX_FIFO_EMPTY; + break; + } + + val->cnt = fifo_data_out_tag.tag_cnt; + + val->data[0] = buff[1]; + val->data[1] = buff[2]; + val->data[2] = buff[3]; + val->data[3] = buff[4]; + val->data[4] = buff[5]; + val->data[5] = buff[6]; + + return ret; +} + +/** + * @brief Batching in FIFO buffer of step counter value.[set] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of step counter value. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_stpcnt_batch_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16bx_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + + if (ret == 0) + { + emb_func_fifo_en_a.step_counter_fifo_en = val; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Batching in FIFO buffer of step counter value.[get] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of step counter value. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_stpcnt_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16bx_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + + *val = emb_func_fifo_en_a.step_counter_fifo_en; + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + + return ret; +} + +/** + * @brief Batching in FIFO buffer of machine learning core results.[set] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of machine learning core results. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_mlc_batch_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16bx_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + + if (ret == 0) + { + emb_func_fifo_en_a.mlc_fifo_en = val; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Batching in FIFO buffer of machine learning core results.[get] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of machine learning core results. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_mlc_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16bx_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + + *val = emb_func_fifo_en_a.mlc_fifo_en; + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enables batching in FIFO buffer of machine learning core filters and features.[set] + * + * @param ctx read / write interface definitions + * @param val Enables batching in FIFO buffer of machine learning core filters and features. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_mlc_filt_batch_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16bx_emb_func_fifo_en_b_t emb_func_fifo_en_b; + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); + } + + if (ret == 0) + { + emb_func_fifo_en_b.mlc_filter_feature_fifo_en = val; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enables batching in FIFO buffer of machine learning core filters and features.[get] + * + * @param ctx read / write interface definitions + * @param val Enables batching in FIFO buffer of machine learning core filters and features. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fifo_mlc_filt_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16bx_emb_func_fifo_en_b_t emb_func_fifo_en_b; + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); + } + + *val = emb_func_fifo_en_b.mlc_filter_feature_fifo_en; + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Step Counter + * @brief This section groups all the functions that manage pedometer. + * @{ + * + */ + +/** + * @brief Step counter mode[set] + * + * @param ctx read / write interface definitions + * @param val false_step_rej, step_counter, step_detector, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_stpcnt_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_stpcnt_mode_t val) +{ + lsm6dsv16bx_emb_func_en_a_t emb_func_en_a; + lsm6dsv16bx_emb_func_en_b_t emb_func_en_b; + lsm6dsv16bx_pedo_cmd_reg_t pedo_cmd_reg; + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + if ((val.false_step_rej == PROPERTY_ENABLE) + && ((emb_func_en_a.mlc_before_fsm_en & emb_func_en_b.mlc_en) == + PROPERTY_DISABLE)) + { + emb_func_en_a.mlc_before_fsm_en = PROPERTY_ENABLE; + } + if (ret == 0) + { + emb_func_en_a.pedo_en = val.step_counter_enable; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + if (ret == 0) + { + ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + if (ret == 0) + { + pedo_cmd_reg.fp_rejection_en = val.false_step_rej; + ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + + return ret; +} + +/** + * @brief Step counter mode[get] + * + * @param ctx read / write interface definitions + * @param val false_step_rej, step_counter, step_detector, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_stpcnt_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_stpcnt_mode_t *val) +{ + lsm6dsv16bx_emb_func_en_a_t emb_func_en_a; + lsm6dsv16bx_pedo_cmd_reg_t pedo_cmd_reg; + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + if (ret == 0) + { + ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + val->false_step_rej = pedo_cmd_reg.fp_rejection_en; + val->step_counter_enable = emb_func_en_a.pedo_en; + + return ret; +} + +/** + * @brief Step counter output, number of detected steps.[get] + * + * @param ctx read / write interface definitions + * @param val Step counter output, number of detected steps. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_STEP_COUNTER_L, &buff[0], 2); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief Reset step counter.[set] + * + * @param ctx read / write interface definitions + * @param val Reset step counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_stpcnt_rst_step_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16bx_emb_func_src_t emb_func_src; + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } + + if (ret == 0) + { + emb_func_src.pedo_rst_step = val; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Reset step counter.[get] + * + * @param ctx read / write interface definitions + * @param val Reset step counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_stpcnt_rst_step_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16bx_emb_func_src_t emb_func_src; + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } + + *val = emb_func_src.pedo_rst_step; + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Pedometer debounce configuration.[set] + * + * @param ctx read / write interface definitions + * @param val Pedometer debounce configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_stpcnt_debounce_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16bx_pedo_deb_steps_conf_t pedo_deb_steps_conf; + int32_t ret; + + ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); + if (ret == 0) + { + pedo_deb_steps_conf.deb_step = val; + ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); + } + + return ret; +} + +/** + * @brief Pedometer debounce configuration.[get] + * + * @param ctx read / write interface definitions + * @param val Pedometer debounce configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_stpcnt_debounce_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16bx_pedo_deb_steps_conf_t pedo_deb_steps_conf; + int32_t ret; + + ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); + *val = pedo_deb_steps_conf.deb_step; + + return ret; +} + +/** + * @brief Time period register for step detection on delta time.[set] + * + * @param ctx read / write interface definitions + * @param val Time period register for step detection on delta time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + + ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_PEDO_SC_DELTAT_L, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief Time period register for step detection on delta time.[get] + * + * @param ctx read / write interface definitions + * @param val Time period register for step detection on delta time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_stpcnt_period_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_SC_DELTAT_L, &buff[0], 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Significant motion + * @brief This section groups all the functions that manage the + * significant motion detection. + * @{ + * + */ + +/** + * @brief Enables significant motion detection function.[set] + * + * @param ctx read / write interface definitions + * @param val Enables significant motion detection function. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_sigmot_mode_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16bx_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + if (ret == 0) + { + emb_func_en_a.sign_motion_en = val; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + + return ret; +} + +/** + * @brief Enables significant motion detection function.[get] + * + * @param ctx read / write interface definitions + * @param val Enables significant motion detection function. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_sigmot_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16bx_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + *val = emb_func_en_a.sign_motion_en; + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Tilt detection + * @brief This section groups all the functions that manage the tilt + * event detection. + * @{ + * + */ + +/** + * @brief Tilt calculation.[set] + * + * @param ctx read / write interface definitions + * @param val Tilt calculation. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_tilt_mode_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16bx_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + if (ret == 0) + { + emb_func_en_a.tilt_en = val; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Tilt calculation.[get] + * + * @param ctx read / write interface definitions + * @param val Tilt calculation. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_tilt_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16bx_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + *val = emb_func_en_a.tilt_en; + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Sensor Fusion Low Power (SFLP) + * @brief This section groups all the functions that manage pedometer. + * @{ + * + */ + +/** + * @brief Enable SFLP Game Rotation Vector (6x).[set] + * + * @param ctx read / write interface definitions + * @param val Enable/Disable game rotation value (0/1). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_sflp_game_rotation_set(stmdev_ctx_t *ctx, uint16_t val) +{ + lsm6dsv16bx_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + emb_func_en_a.sflp_game_en = val; + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, + (uint8_t *)&emb_func_en_a, 1); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable SFLP Game Rotation Vector (6x).[get] + * + * @param ctx read / write interface definitions + * @param val Enable/Disable game rotation value (0/1). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_sflp_game_rotation_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + lsm6dsv16bx_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + *val = emb_func_en_a.sflp_game_en; + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief SFLP Data Rate (ODR) configuration.[set] + * + * @param ctx read / write interface definitions + * @param val SFLP_15Hz, SFLP_30Hz, SFLP_60Hz, SFLP_120Hz, SFLP_240Hz, SFLP_480Hz + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_sflp_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_sflp_data_rate_t val) +{ + lsm6dsv16bx_sflp_odr_t sflp_odr; + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + sflp_odr.sflp_game_odr = (uint8_t)val & 0x07U; + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_SFLP_ODR, (uint8_t *)&sflp_odr, + 1); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief SFLP Data Rate (ODR) configuration.[get] + * + * @param ctx read / write interface definitions + * @param val SFLP_15Hz, SFLP_30Hz, SFLP_60Hz, SFLP_120Hz, SFLP_240Hz, SFLP_480Hz + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_sflp_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_sflp_data_rate_t *val) +{ + lsm6dsv16bx_sflp_odr_t sflp_odr; + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + switch (sflp_odr.sflp_game_odr) + { + case LSM6DSV16BX_SFLP_15Hz: + *val = LSM6DSV16BX_SFLP_15Hz; + break; + + case LSM6DSV16BX_SFLP_30Hz: + *val = LSM6DSV16BX_SFLP_30Hz; + break; + + case LSM6DSV16BX_SFLP_60Hz: + *val = LSM6DSV16BX_SFLP_60Hz; + break; + + case LSM6DSV16BX_SFLP_120Hz: + *val = LSM6DSV16BX_SFLP_120Hz; + break; + + case LSM6DSV16BX_SFLP_240Hz: + *val = LSM6DSV16BX_SFLP_240Hz; + break; + + case LSM6DSV16BX_SFLP_480Hz: + *val = LSM6DSV16BX_SFLP_480Hz; + break; + + default: + *val = LSM6DSV16BX_SFLP_15Hz; + break; + } + return ret; +} + +/* + * Original conversion routines taken from: https://github.com/numpy/numpy + * + * uint16_t npy_floatbits_to_halfbits(uint32_t f); + * uint16_t npy_float_to_half(float_t f); + * + * Released under BSD-3-Clause License + */ +static uint16_t npy_floatbits_to_halfbits(uint32_t f) +{ + uint32_t f_exp, f_sig; + uint16_t h_sgn, h_exp, h_sig; + + h_sgn = (uint16_t)((f & 0x80000000u) >> 16); + f_exp = (f & 0x7f800000u); + + /* Exponent overflow/NaN converts to signed inf/NaN */ + if (f_exp >= 0x47800000u) + { + if (f_exp == 0x7f800000u) + { + /* Inf or NaN */ + f_sig = (f & 0x007fffffu); + if (f_sig != 0) + { + /* NaN - propagate the flag in the significand... */ + uint16_t ret = (uint16_t)(0x7c00u + (f_sig >> 13)); + /* ...but make sure it stays a NaN */ + if (ret == 0x7c00u) + { + ret++; + } + return h_sgn + ret; + } + else + { + /* signed inf */ + return (uint16_t)(h_sgn + 0x7c00u); + } + } + else + { + /* overflow to signed inf */ +#if NPY_HALF_GENERATE_OVERFLOW + npy_set_floatstatus_overflow(); +#endif + return (uint16_t)(h_sgn + 0x7c00u); + } + } + + /* Exponent underflow converts to a subnormal half or signed zero */ + if (f_exp <= 0x38000000u) + { + /* + * Signed zeros, subnormal floats, and floats with small + * exponents all convert to signed zero half-floats. + */ + if (f_exp < 0x33000000u) + { +#if NPY_HALF_GENERATE_UNDERFLOW + /* If f != 0, it underflowed to 0 */ + if ((f & 0x7fffffff) != 0) + { + npy_set_floatstatus_underflow(); + } +#endif + return h_sgn; + } + /* Make the subnormal significand */ + f_exp >>= 23; + f_sig = (0x00800000u + (f & 0x007fffffu)); +#if NPY_HALF_GENERATE_UNDERFLOW + /* If it's not exactly represented, it underflowed */ + if ((f_sig & (((uint32_t)1 << (126 - f_exp)) - 1)) != 0) + { + npy_set_floatstatus_underflow(); + } +#endif + /* + * Usually the significand is shifted by 13. For subnormals an + * additional shift needs to occur. This shift is one for the largest + * exponent giving a subnormal `f_exp = 0x38000000 >> 23 = 112`, which + * offsets the new first bit. At most the shift can be 1+10 bits. + */ + f_sig >>= (113 - f_exp); + /* Handle rounding by adding 1 to the bit beyond half precision */ +#if NPY_HALF_ROUND_TIES_TO_EVEN + /* + * If the last bit in the half significand is 0 (already even), and + * the remaining bit pattern is 1000...0, then we do not add one + * to the bit after the half significand. However, the (113 - f_exp) + * shift can lose up to 11 bits, so the || checks them in the original. + * In all other cases, we can just add one. + */ + if (((f_sig & 0x00003fffu) != 0x00001000u) || (f & 0x000007ffu)) + { + f_sig += 0x00001000u; + } +#else + f_sig += 0x00001000u; +#endif + h_sig = (uint16_t)(f_sig >> 13); + /* + * If the rounding causes a bit to spill into h_exp, it will + * increment h_exp from zero to one and h_sig will be zero. + * This is the correct result. + */ + return (uint16_t)(h_sgn + h_sig); + } + + /* Regular case with no overflow or underflow */ + h_exp = (uint16_t)((f_exp - 0x38000000u) >> 13); + /* Handle rounding by adding 1 to the bit beyond half precision */ + f_sig = (f & 0x007fffffu); +#if NPY_HALF_ROUND_TIES_TO_EVEN + /* + * If the last bit in the half significand is 0 (already even), and + * the remaining bit pattern is 1000...0, then we do not add one + * to the bit after the half significand. In all other cases, we do. + */ + if ((f_sig & 0x00003fffu) != 0x00001000u) + { + f_sig += 0x00001000u; + } +#else + f_sig += 0x00001000u; +#endif + h_sig = (uint16_t)(f_sig >> 13); + /* + * If the rounding causes a bit to spill into h_exp, it will + * increment h_exp by one and h_sig will be zero. This is the + * correct result. h_exp may increment to 15, at greatest, in + * which case the result overflows to a signed inf. + */ +#if NPY_HALF_GENERATE_OVERFLOW + h_sig += h_exp; + if (h_sig == 0x7c00u) + { + npy_set_floatstatus_overflow(); + } + return h_sgn + h_sig; +#else + return h_sgn + h_exp + h_sig; +#endif +} + +static uint16_t npy_float_to_half(float_t f) +{ + union + { + float_t f; + uint32_t fbits; + } conv; + conv.f = f; + return npy_floatbits_to_halfbits(conv.fbits); +} + +/** + * @brief SFLP GBIAS value. The register value is expressed as half-precision + * floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent + * bits; F: 10 fraction bits).[set] + * + * @param ctx read / write interface definitions + * @param val GBIAS x/y/z val. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_sflp_game_gbias_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_sflp_gbias_t *val) +{ + lsm6dsv16bx_sflp_data_rate_t sflp_odr; + lsm6dsv16bx_emb_func_exec_status_t emb_func_sts; + lsm6dsv16bx_data_ready_t drdy; + lsm6dsv16bx_xl_full_scale_t xl_fs; + lsm6dsv16bx_ctrl10_t ctrl10; + uint8_t master_config; + uint8_t emb_func_en_saved[2]; + uint8_t conf_saved[2]; + uint8_t reg_zero[2] = {0x0, 0x0}; + uint16_t gbias_hf[3]; + float_t k = 0.005f; + int16_t xl_data[3]; + int32_t data_tmp; + uint8_t *data_ptr = (uint8_t *)&data_tmp; + uint8_t i, j; + int32_t ret; + + ret = lsm6dsv16bx_sflp_data_rate_get(ctx, &sflp_odr); + if (ret != 0) + { + return ret; + } + + /* Calculate k factor */ + switch (sflp_odr) + { + case LSM6DSV16BX_SFLP_15Hz: + k = 0.04f; + break; + case LSM6DSV16BX_SFLP_30Hz: + k = 0.02f; + break; + case LSM6DSV16BX_SFLP_60Hz: + k = 0.01f; + break; + case LSM6DSV16BX_SFLP_120Hz: + k = 0.005f; + break; + case LSM6DSV16BX_SFLP_240Hz: + k = 0.0025f; + break; + case LSM6DSV16BX_SFLP_480Hz: + k = 0.00125f; + break; + } + + /* compute gbias as half precision float in order to be put in embedded advanced feature register */ + gbias_hf[0] = npy_float_to_half(val->gbias_x * (3.14159265358979323846f / 180.0f) / k); + gbias_hf[1] = npy_float_to_half(val->gbias_y * (3.14159265358979323846f / 180.0f) / k); + gbias_hf[2] = npy_float_to_half(val->gbias_z * (3.14159265358979323846f / 180.0f) / k); + + /* Save sensor configuration and set high-performance mode (if the sensor is in power-down mode, turn it on) */ + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL1, conf_saved, 2); + ret += lsm6dsv16bx_xl_mode_set(ctx, LSM6DSV16BX_XL_HIGH_PERFORMANCE_MD); + ret += lsm6dsv16bx_gy_mode_set(ctx, LSM6DSV16BX_GY_HIGH_PERFORMANCE_MD); + if ((conf_saved[0] & 0x0FU) == LSM6DSV16BX_XL_ODR_OFF) + { + ret += lsm6dsv16bx_xl_data_rate_set(ctx, LSM6DSV16BX_XL_ODR_AT_120Hz); + } + + /* disable algos */ + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, emb_func_en_saved, + 2); + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, reg_zero, 2); + do + { + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EXEC_STATUS, + (uint8_t *)&emb_func_sts, 1); + } while (emb_func_sts.emb_func_endop != 1); + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + // enable gbias setting + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1); + ctrl10.emb_func_debug = 1; + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1); + + /* enable algos */ + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + emb_func_en_saved[0] |= 0x02; /* force SFLP GAME en */ + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, emb_func_en_saved, + 2); + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + ret += lsm6dsv16bx_xl_full_scale_get(ctx, &xl_fs); + + /* Read XL data */ + do + { + ret += lsm6dsv16bx_flag_data_ready_get(ctx, &drdy); + } while (drdy.drdy_xl != 1); + ret += lsm6dsv16bx_acceleration_raw_get(ctx, xl_data); + + /* force sflp initialization */ + master_config = 0x40; + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, &master_config, + 1); + for (i = 0; i < 3; i++) + { + j = 0; + data_tmp = (int32_t)xl_data[i]; + data_tmp <<= xl_fs; // shift based on current fs + ret += lsm6dsv16bx_write_reg(ctx, 0x02 + 3 * i, &data_ptr[j++], 1); + ret += lsm6dsv16bx_write_reg(ctx, 0x03 + 3 * i, &data_ptr[j++], 1); + ret += lsm6dsv16bx_write_reg(ctx, 0x04 + 3 * i, &data_ptr[j], 1); + } + for (i = 0; i < 3; i++) + { + j = 0; + data_tmp = 0; + ret += lsm6dsv16bx_write_reg(ctx, 0x0B + 3 * i, &data_ptr[j++], 1); + ret += lsm6dsv16bx_write_reg(ctx, 0x0C + 3 * i, &data_ptr[j++], 1); + ret += lsm6dsv16bx_write_reg(ctx, 0x0D + 3 * i, &data_ptr[j], 1); + } + master_config = 0x00; + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, &master_config, + 1); + + // wait end_op (and at least 30 us) + ctx->mdelay(1); + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + do + { + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EXEC_STATUS, + (uint8_t *)&emb_func_sts, 1); + } while (emb_func_sts.emb_func_endop != 1); + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + /* write gbias in embedded advanced features registers */ + ret += lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_SFLP_GAME_GBIASX_L, + (uint8_t *)gbias_hf, 6); + + /* reload previous sensor configuration */ + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL1, conf_saved, 2); + + // disable gbias setting + ctrl10.emb_func_debug = 0; + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1); + + return ret; +} + +/** + * @brief SFLP initial configuration [set] + * + * @param ctx read / write interface definitions + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_sflp_configure(stmdev_ctx_t *ctx) +{ + uint8_t val = 0x50; + int32_t ret; + + ret = lsm6dsv16bx_ln_pg_write(ctx, 0xD2, &val, 1); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Finite State Machine (FSM) + * @brief This section groups all the functions that manage the + * state_machine. + * @{ + * + */ + +/** + * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[set] + * + * @param ctx read / write interface definitions + * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fsm_permission_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_fsm_permission_t val) +{ + lsm6dsv16bx_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret == 0) + { + func_cfg_access.fsm_wr_ctrl_en = (uint8_t)val & 0x01U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Return the status of the CTRL registers permission (standard interface vs FSM).[get] + * + * @param ctx read / write interface definitions + * @param val 0: all FSM regs are under std_if control, 1: some regs are under FSM control. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fsm_permission_status_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_fsm_permission_status_t *val) +{ + lsm6dsv16bx_ctrl_status_t status; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL_STATUS, (uint8_t *)&status, 1); + *val = (status.fsm_wr_ctrl_status == 0) ? LSM6DSV16BX_STD_IF_CONTROL : LSM6DSV16BX_FSM_CONTROL; + + return ret; +} + +/** + * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[get] + * + * @param ctx read / write interface definitions + * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fsm_permission_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_fsm_permission_t *val) +{ + lsm6dsv16bx_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + switch (func_cfg_access.fsm_wr_ctrl_en) + { + case LSM6DSV16BX_PROTECT_CTRL_REGS: + *val = LSM6DSV16BX_PROTECT_CTRL_REGS; + break; + + case LSM6DSV16BX_WRITE_CTRL_REG: + *val = LSM6DSV16BX_WRITE_CTRL_REG; + break; + + default: + *val = LSM6DSV16BX_PROTECT_CTRL_REGS; + break; + } + return ret; +} + +/** + * @brief Get the FSM permission status + * + * @param ctx read / write interface definitions + * @param val 0: All reg writable from std if - 1: some regs are under FSM control. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fsm_permission_status(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16bx_ctrl_status_t ctrl_status; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL_STATUS, (uint8_t *)&ctrl_status, 1); + + *val = ctrl_status.fsm_wr_ctrl_status; + + return ret; +} + +/** + * @brief Enable Finite State Machine (FSM) feature.[set] + * + * @param ctx read / write interface definitions + * @param val Enable Finite State Machine (FSM) feature. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fsm_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_mode_t val) +{ + lsm6dsv16bx_emb_func_en_b_t emb_func_en_b; + lsm6dsv16bx_fsm_enable_t fsm_enable; + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); + } + if ((val.fsm1_en | val.fsm2_en | val.fsm1_en | val.fsm1_en + | val.fsm1_en | val.fsm2_en | val.fsm1_en | val.fsm1_en) == PROPERTY_ENABLE) + { + emb_func_en_b.fsm_en = PROPERTY_ENABLE; + } + else + { + emb_func_en_b.fsm_en = PROPERTY_DISABLE; + } + if (ret == 0) + { + fsm_enable.fsm1_en = val.fsm1_en; + fsm_enable.fsm2_en = val.fsm2_en; + fsm_enable.fsm3_en = val.fsm3_en; + fsm_enable.fsm4_en = val.fsm4_en; + fsm_enable.fsm5_en = val.fsm5_en; + fsm_enable.fsm6_en = val.fsm6_en; + fsm_enable.fsm7_en = val.fsm7_en; + fsm_enable.fsm8_en = val.fsm8_en; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); + } + if (ret == 0) + { + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable Finite State Machine (FSM) feature.[get] + * + * @param ctx read / write interface definitions + * @param val Enable Finite State Machine (FSM) feature. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fsm_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_mode_t *val) +{ + lsm6dsv16bx_fsm_enable_t fsm_enable; + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + val->fsm1_en = fsm_enable.fsm1_en; + val->fsm2_en = fsm_enable.fsm2_en; + val->fsm3_en = fsm_enable.fsm3_en; + val->fsm4_en = fsm_enable.fsm4_en; + val->fsm5_en = fsm_enable.fsm5_en; + val->fsm6_en = fsm_enable.fsm6_en; + val->fsm7_en = fsm_enable.fsm7_en; + val->fsm8_en = fsm_enable.fsm8_en; + + return ret; +} + +/** + * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[set] + * + * @param ctx read / write interface definitions + * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fsm_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FSM_LONG_COUNTER_L, (uint8_t *)&buff[0], 2); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[get] + * + * @param ctx read / write interface definitions + * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fsm_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_LONG_COUNTER_L, &buff[0], 2); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief FSM output registers[get] + * + * @param ctx read / write interface definitions + * @param val FSM output registers + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fsm_out_get(stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_out_t *val) +{ + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_OUTS1, (uint8_t *)val, 8); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Finite State Machine Output Data Rate (ODR) configuration.[set] + * + * @param ctx read / write interface definitions + * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fsm_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_fsm_data_rate_t val) +{ + lsm6dsv16bx_fsm_odr_t fsm_odr; + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_ODR, (uint8_t *)&fsm_odr, 1); + } + + if (ret == 0) + { + fsm_odr.fsm_odr = (uint8_t)val & 0x07U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FSM_ODR, (uint8_t *)&fsm_odr, 1); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Finite State Machine Output Data Rate (ODR) configuration.[get] + * + * @param ctx read / write interface definitions + * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fsm_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_fsm_data_rate_t *val) +{ + lsm6dsv16bx_fsm_odr_t fsm_odr; + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_ODR, (uint8_t *)&fsm_odr, 1); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + switch (fsm_odr.fsm_odr) + { + case LSM6DSV16BX_FSM_15Hz: + *val = LSM6DSV16BX_FSM_15Hz; + break; + + case LSM6DSV16BX_FSM_30Hz: + *val = LSM6DSV16BX_FSM_30Hz; + break; + + case LSM6DSV16BX_FSM_60Hz: + *val = LSM6DSV16BX_FSM_60Hz; + break; + + case LSM6DSV16BX_FSM_120Hz: + *val = LSM6DSV16BX_FSM_120Hz; + break; + + case LSM6DSV16BX_FSM_240Hz: + *val = LSM6DSV16BX_FSM_240Hz; + break; + + case LSM6DSV16BX_FSM_480Hz: + *val = LSM6DSV16BX_FSM_480Hz; + break; + + case LSM6DSV16BX_FSM_960Hz: + *val = LSM6DSV16BX_FSM_960Hz; + break; + + default: + *val = LSM6DSV16BX_FSM_15Hz; + break; + } + return ret; +} + +/** + * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[set] + * + * @param ctx read / write interface definitions + * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fsm_long_cnt_timeout_set(stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_FSM_LC_TIMEOUT_L, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[get] + * + * @param ctx read / write interface definitions + * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fsm_long_cnt_timeout_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_FSM_LC_TIMEOUT_L, &buff[0], 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief FSM number of programs.[set] + * + * @param ctx read / write interface definitions + * @param val FSM number of programs. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16bx_fsm_programs_t fsm_programs; + int32_t ret; + + ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); + if (ret == 0) + { + fsm_programs.fsm_n_prog = val; + ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); + } + + return ret; +} + +/** + * @brief FSM number of programs.[get] + * + * @param ctx read / write interface definitions + * @param val FSM number of programs. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16bx_fsm_programs_t fsm_programs; + int32_t ret; + + ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); + *val = fsm_programs.fsm_n_prog; + + + return ret; +} + +/** + * @brief FSM start address. First available address is 0x35C.[set] + * + * @param ctx read / write interface definitions + * @param val FSM start address. First available address is 0x35C. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_FSM_START_ADD_L, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief FSM start address. First available address is 0x35C.[get] + * + * @param ctx read / write interface definitions + * @param val FSM start address. First available address is 0x35C. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_FSM_START_ADD_L, &buff[0], 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @addtogroup Machine Learning Core + * @brief This section group all the functions concerning the + * usage of Machine Learning Core + * @{ + * + */ + +/** + * @brief It enables Machine Learning Core feature (MLC). When the Machine Learning Core is enabled the Finite State Machine (FSM) programs are executed before executing the MLC algorithms.[set] + * + * @param ctx read / write interface definitions + * @param val MLC_OFF, MLC_ON, MLC_BEFORE_FSM, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_mlc_set(stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_mode_t val) +{ + lsm6dsv16bx_emb_func_en_b_t emb_en_b; + lsm6dsv16bx_emb_func_en_a_t emb_en_a; + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + + switch(val) + { + case LSM6DSV16BX_MLC_OFF: + emb_en_a.mlc_before_fsm_en = 0; + emb_en_b.mlc_en = 0; + break; + case LSM6DSV16BX_MLC_ON: + emb_en_a.mlc_before_fsm_en = 0; + emb_en_b.mlc_en = 1; + break; + case LSM6DSV16BX_MLC_ON_BEFORE_FSM: + emb_en_a.mlc_before_fsm_en = 1; + emb_en_b.mlc_en = 0; + break; + default: + break; + } + + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief It enables Machine Learning Core feature (MLC). When the Machine Learning Core is enabled the Finite State Machine (FSM) programs are executed before executing the MLC algorithms.[get] + * + * @param ctx read / write interface definitions + * @param val MLC_OFF, MLC_ON, MLC_BEFORE_FSM, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_mlc_get(stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_mode_t *val) +{ + lsm6dsv16bx_emb_func_en_b_t emb_en_b; + lsm6dsv16bx_emb_func_en_a_t emb_en_a; + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + + if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U) + { + *val = LSM6DSV16BX_MLC_OFF; + } + else if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 1U) + { + *val = LSM6DSV16BX_MLC_ON; + } + else if (emb_en_a.mlc_before_fsm_en == 1U) + { + *val = LSM6DSV16BX_MLC_ON_BEFORE_FSM; + } + else + { + /* Do nothing */ + } + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Machine Learning Core Output Data Rate (ODR) configuration.[set] + * + * @param ctx read / write interface definitions + * @param val MLC_15Hz, MLC_30Hz, MLC_60Hz, MLC_120Hz, MLC_240Hz, MLC_480Hz, MLC_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_mlc_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_mlc_data_rate_t val) +{ + lsm6dsv16bx_mlc_odr_t mlc_odr; + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MLC_ODR, (uint8_t *)&mlc_odr, 1); + } + + if (ret == 0) + { + mlc_odr.mlc_odr = (uint8_t)val & 0x07U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_MLC_ODR, (uint8_t *)&mlc_odr, 1); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Machine Learning Core Output Data Rate (ODR) configuration.[get] + * + * @param ctx read / write interface definitions + * @param val MLC_15Hz, MLC_30Hz, MLC_60Hz, MLC_120Hz, MLC_240Hz, MLC_480Hz, MLC_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_mlc_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_mlc_data_rate_t *val) +{ + lsm6dsv16bx_mlc_odr_t mlc_odr; + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MLC_ODR, (uint8_t *)&mlc_odr, 1); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + + switch (mlc_odr.mlc_odr) + { + case LSM6DSV16BX_MLC_15Hz: + *val = LSM6DSV16BX_MLC_15Hz; + break; + + case LSM6DSV16BX_MLC_30Hz: + *val = LSM6DSV16BX_MLC_30Hz; + break; + + case LSM6DSV16BX_MLC_60Hz: + *val = LSM6DSV16BX_MLC_60Hz; + break; + + case LSM6DSV16BX_MLC_120Hz: + *val = LSM6DSV16BX_MLC_120Hz; + break; + + case LSM6DSV16BX_MLC_240Hz: + *val = LSM6DSV16BX_MLC_240Hz; + break; + + case LSM6DSV16BX_MLC_480Hz: + *val = LSM6DSV16BX_MLC_480Hz; + break; + + case LSM6DSV16BX_MLC_960Hz: + *val = LSM6DSV16BX_MLC_960Hz; + break; + + default: + *val = LSM6DSV16BX_MLC_15Hz; + break; + } + return ret; +} + +/** + * @brief Output value of all MLC decision trees.[get] + * + * @param ctx read / write interface definitions + * @param val Output value of all MLC decision trees. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_mlc_out_get(stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_out_t *val) +{ + int32_t ret; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MLC1_SRC, (uint8_t *)&val, 4); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + return ret; +} + +/** + * @brief Qvar sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the Qvar sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set] + * + * @param ctx read / write interface definitions + * @param val Qvar sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the Qvar sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_mlc_qvar_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_MLC_QVAR_SENSITIVITY_L, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief Qvar sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the Qvar sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get] + * + * @param ctx read / write interface definitions + * @param val Qvar sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the Qvar sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_mlc_qvar_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_MLC_QVAR_SENSITIVITY_L, &buff[0], 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @addtogroup Accelerometer user offset correction + * @brief This section group all the functions concerning the + * usage of Accelerometer user offset correction + * @{ + * + */ + +/** + * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[set] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_xl_offset_on_out_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16bx_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.usr_off_on_out = val; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[get] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_xl_offset_on_out_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16bx_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); + *val = ctrl9.usr_off_on_out; + + return ret; +} + +/** + * @brief Accelerometer user offset correction values in mg.[set] + * + * @param ctx read / write interface definitions + * @param val Accelerometer user offset correction values in mg. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_xl_offset_mg_set(stmdev_ctx_t *ctx, + lsm6dsv16bxxl_offset_mg_t val) +{ + lsm6dsv16bx_z_ofs_usr_t z_ofs_usr; + lsm6dsv16bx_y_ofs_usr_t y_ofs_usr; + lsm6dsv16bx_x_ofs_usr_t x_ofs_usr; + lsm6dsv16bx_ctrl9_t ctrl9; + int32_t ret; + float_t tmp; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + } + + + if ((val.x_mg < (0.0078125f * 127.0f)) && (val.x_mg > (0.0078125f * -127.0f)) && + (val.y_mg < (0.0078125f * 127.0f)) && (val.y_mg > (0.0078125f * -127.0f)) && + (val.z_mg < (0.0078125f * 127.0f)) && (val.z_mg > (0.0078125f * -127.0f))) + { + ctrl9.usr_off_w = 0; + + tmp = val.z_mg / 0.0078125f; + z_ofs_usr.z_ofs_usr = (uint8_t)tmp; + + tmp = val.y_mg / 0.0078125f; + y_ofs_usr.y_ofs_usr = (uint8_t)tmp; + + tmp = val.x_mg / 0.0078125f; + x_ofs_usr.x_ofs_usr = (uint8_t)tmp; + } + else if ((val.x_mg < (0.125f * 127.0f)) && (val.x_mg > (0.125f * -127.0f)) && + (val.y_mg < (0.125f * 127.0f)) && (val.y_mg > (0.125f * -127.0f)) && + (val.z_mg < (0.125f * 127.0f)) && (val.z_mg > (0.125f * -127.0f))) + { + ctrl9.usr_off_w = 1; + + tmp = val.z_mg / 0.125f; + z_ofs_usr.z_ofs_usr = (uint8_t)tmp; + + tmp = val.y_mg / 0.125f; + y_ofs_usr.y_ofs_usr = (uint8_t)tmp; + + tmp = val.x_mg / 0.125f; + x_ofs_usr.x_ofs_usr = (uint8_t)tmp; + } + else // out of limit + { + ctrl9.usr_off_w = 1; + z_ofs_usr.z_ofs_usr = 0xFFU; + y_ofs_usr.y_ofs_usr = 0xFFU; + x_ofs_usr.x_ofs_usr = 0xFFU; + } + + if (ret == 0) + { + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + } + if (ret == 0) + { + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + } + if (ret == 0) + { + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + } + if (ret == 0) + { + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); + } + return ret; +} + +/** + * @brief Accelerometer user offset correction values in mg.[get] + * + * @param ctx read / write interface definitions + * @param val Accelerometer user offset correction values in mg. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_xl_offset_mg_get(stmdev_ctx_t *ctx, + lsm6dsv16bxxl_offset_mg_t *val) +{ + lsm6dsv16bx_z_ofs_usr_t z_ofs_usr; + lsm6dsv16bx_y_ofs_usr_t y_ofs_usr; + lsm6dsv16bx_x_ofs_usr_t x_ofs_usr; + lsm6dsv16bx_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + } + + if (ctrl9.usr_off_w == PROPERTY_DISABLE) + { + val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.0078125f); + val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.0078125f); + val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.0078125f); + } + else + { + val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.125f); + val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.125f); + val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.125f); + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @addtogroup AH_QVAR + * @brief This section group all the functions concerning the + * usage of AH_QVAR + * @{ + * + */ + +/** + * @brief Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/Qvar1 and SCx/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode.[set] + * + * @param ctx read / write interface definitions + * @param val Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/Qvar1 and SCx/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_ah_qvar_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_ah_qvar_mode_t val) +{ + lsm6dsv16bx_ctrl10_t ctrl10; + lsm6dsv16bx_ctrl7_t ctrl7; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1); + } + + if (ret == 0) + { + if ((val.ah_qvar1_en | val.ah_qvar2_en) == PROPERTY_ENABLE) + { + ctrl7.ah_qvar_en = PROPERTY_ENABLE; + } + else + { + ctrl7.ah_qvar_en = PROPERTY_DISABLE; + } + ctrl7.ah_qvar1_en = val.ah_qvar1_en; + ctrl7.ah_qvar2_en = val.ah_qvar2_en; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1); + } + if (ret == 0) + { + ctrl10.ah_qvar_sw = val.swaps; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1); + } + return ret; +} + +/** + * @brief Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/Qvar1 and SCx/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode.[get] + * + * @param ctx read / write interface definitions + * @param val Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/Qvar1 and SCx/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_ah_qvar_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_ah_qvar_mode_t *val) +{ + lsm6dsv16bx_ctrl10_t ctrl10; + lsm6dsv16bx_ctrl7_t ctrl7; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1); + } + + val->ah_qvar1_en = ctrl7.ah_qvar1_en; + val->ah_qvar2_en = ctrl7.ah_qvar2_en; + val->swaps = ctrl10.ah_qvar_sw; + + return ret; +} + +/** + * @brief Configures the equivalent input impedance of the AH_QVAR buffers.[set] + * + * @param ctx read / write interface definitions + * @param val 2400MOhm, 730MOhm, 300MOhm, 255MOhm, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_ah_qvar_zin_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_ah_qvar_zin_t val) +{ + lsm6dsv16bx_ctrl7_t ctrl7; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret == 0) + { + ctrl7.ah_qvar_c_zin = (uint8_t)val & 0x03U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1); + } + + return ret; +} + +/** + * @brief Configures the equivalent input impedance of the AH_QVAR buffers.[get] + * + * @param ctx read / write interface definitions + * @param val 2400MOhm, 730MOhm, 300MOhm, 255MOhm, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_ah_qvar_zin_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_ah_qvar_zin_t *val) +{ + lsm6dsv16bx_ctrl7_t ctrl7; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1); + switch (ctrl7.ah_qvar_c_zin) + { + case LSM6DSV16BX_2400MOhm: + *val = LSM6DSV16BX_2400MOhm; + break; + + case LSM6DSV16BX_730MOhm: + *val = LSM6DSV16BX_730MOhm; + break; + + case LSM6DSV16BX_300MOhm: + *val = LSM6DSV16BX_300MOhm; + break; + + case LSM6DSV16BX_255MOhm: + *val = LSM6DSV16BX_255MOhm; + break; + + default: + *val = LSM6DSV16BX_2400MOhm; + break; + } + return ret; +} + +/** + * @brief Qvar sensor sensitivity value register for the Finite State Machine. This register corresponds to the conversion value of the Qvar sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set] + * + * @param ctx read / write interface definitions + * @param val Qvar sensor sensitivity value register for the Finite State Machine. This register corresponds to the conversion value of the Qvar sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fsm_qvar_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_FSM_QVAR_SENSITIVITY_L, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief Qvar sensor sensitivity value register for the Finite State Machine. This register corresponds to the conversion value of the Qvar sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get] + * + * @param ctx read / write interface definitions + * @param val Qvar sensor sensitivity value register for the Finite State Machine. This register corresponds to the conversion value of the Qvar sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_fsm_qvar_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_FSM_QVAR_SENSITIVITY_L, &buff[0], 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @addtogroup SenseWire (I3C) + * @brief This section group all the functions concerning the + * usage of SenseWire (I3C) + * @{ + * + */ + +/** + * @brief Selects the action the device will perform after "Reset whole chip" I3C pattern.[set] + * + * @param ctx read / write interface definitions + * @param val SW_RST_DYN_ADDRESS_RST, GLOBAL_RST_, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_i3c_reset_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_i3c_reset_mode_t val) +{ + lsm6dsv16bx_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret == 0) + { + pin_ctrl.ibhr_por_en = (uint8_t)val & 0x01U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + + return ret; +} + +/** + * @brief Selects the action the device will perform after "Reset whole chip" I3C pattern.[get] + * + * @param ctx read / write interface definitions + * @param val SW_RST_DYN_ADDRESS_RST, GLOBAL_RST_, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_i3c_reset_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_i3c_reset_mode_t *val) +{ + lsm6dsv16bx_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + switch (pin_ctrl.ibhr_por_en) + { + case LSM6DSV16BX_SW_RST_DYN_ADDRESS_RST: + *val = LSM6DSV16BX_SW_RST_DYN_ADDRESS_RST; + break; + + case LSM6DSV16BX_I3C_GLOBAL_RST: + *val = LSM6DSV16BX_I3C_GLOBAL_RST; + break; + + default: + *val = LSM6DSV16BX_SW_RST_DYN_ADDRESS_RST; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @addtogroup Time-Division Multiplexing (TDM) + * @brief This section group all the functions concerning the + * usage of Time-Division Multiplexing (TDM) + * @{ + * + */ + +/** + * @brief Disables pull-up on WCLK pin.[set] + * + * @param ctx read / write interface definitions + * @param val Disables pull-up on WCLK pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_tdm_dis_wclk_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16bx_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret == 0) + { + pin_ctrl.tdm_wclk_pu_dis = val; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + + return ret; +} + +/** + * @brief Disables pull-up on WCLK pin.[get] + * + * @param ctx read / write interface definitions + * @param val Disables pull-up on WCLK pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_tdm_dis_wclk_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16bx_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + *val = pin_ctrl.tdm_wclk_pu_dis; + + return ret; +} + +/** + * @brief Enables pull-up on TDMout pin.[set] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on TDMout pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_tdm_tdmout_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16bx_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.tdm_out_pu_en = val; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Enables pull-up on TDMout pin.[get] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on TDMout pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_tdm_tdmout_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16bx_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1); + *val = if_cfg.tdm_out_pu_en; + + return ret; +} + +/** + * @brief WCLK and BCLK frequencies.[set] + * + * @param ctx read / write interface definitions + * @param val WCLK_8kHZ_1024kHz, WCLK_16kHZ_2048kHz, WCLK_8kHZ_2048kHz, WCLK_16kHZ_1024kHz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_tdm_wclk_bclk_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_tdm_wclk_bclk_t val) +{ + lsm6dsv16bx_tdm_cfg0_t tdm_cfg0; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + if (ret == 0) + { + tdm_cfg0.tdm_wclk_bclk_sel = ((uint8_t)val & 0x4U) >> 2; + tdm_cfg0.tdm_wclk = (uint8_t)val & 0x3U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + } + + return ret; +} + +/** + * @brief WCLK and BCLK frequencies.[get] + * + * @param ctx read / write interface definitions + * @param val WCLK_8kHZ_1024kHz, WCLK_16kHZ_2048kHz, WCLK_8kHZ_2048kHz, WCLK_16kHZ_1024kHz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_tdm_wclk_bclk_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_tdm_wclk_bclk_t *val) +{ + lsm6dsv16bx_tdm_cfg0_t tdm_cfg0; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + switch ((tdm_cfg0.tdm_wclk_bclk_sel << 2) + tdm_cfg0.tdm_wclk) + { + case LSM6DSV16BX_WCLK_16kHZ_BCLK_2048kHz: + *val = LSM6DSV16BX_WCLK_16kHZ_BCLK_2048kHz; + break; + + case LSM6DSV16BX_WCLK_8kHZ_BCLK_2048kHz: + *val = LSM6DSV16BX_WCLK_8kHZ_BCLK_2048kHz; + break; + + default: + *val = LSM6DSV16BX_WCLK_8kHZ_BCLK_2048kHz; + break; + } + return ret; +} + +/** + * @brief Selection of TDM slot for transmission.[set] + * + * @param ctx read / write interface definitions + * @param val SLOT_012, SLOT_456, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_tdm_slot_set(stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_slot_t val) +{ + lsm6dsv16bx_tdm_cfg0_t tdm_cfg0; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + if (ret == 0) + { + tdm_cfg0.tdm_slot_sel = (uint8_t)val & 0x01U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + } + + return ret; +} + +/** + * @brief Selection of TDM slot for transmission.[get] + * + * @param ctx read / write interface definitions + * @param val SLOT_012, SLOT_456, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_tdm_slot_get(stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_slot_t *val) +{ + lsm6dsv16bx_tdm_cfg0_t tdm_cfg0; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + switch (tdm_cfg0.tdm_slot_sel) + { + case LSM6DSV16BX_SLOT_012: + *val = LSM6DSV16BX_SLOT_012; + break; + + case LSM6DSV16BX_SLOT_456: + *val = LSM6DSV16BX_SLOT_456; + break; + + default: + *val = LSM6DSV16BX_SLOT_012; + break; + } + return ret; +} + +/** + * @brief BCLK edge selection for TDM interface.[set] + * + * @param ctx read / write interface definitions + * @param val BCLK_RISING, BCLK_FALLING, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_tdm_bclk_edge_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_tdm_bclk_edge_t val) +{ + lsm6dsv16bx_tdm_cfg0_t tdm_cfg0; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + if (ret == 0) + { + tdm_cfg0.tdm_bclk_edge_sel = (uint8_t)val & 0x01U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + } + + return ret; +} + +/** + * @brief BCLK edge selection for TDM interface.[get] + * + * @param ctx read / write interface definitions + * @param val BCLK_RISING, BCLK_FALLING, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_tdm_bclk_edge_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_tdm_bclk_edge_t *val) +{ + lsm6dsv16bx_tdm_cfg0_t tdm_cfg0; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + switch (tdm_cfg0.tdm_bclk_edge_sel) + { + case LSM6DSV16BX_BCLK_RISING: + *val = LSM6DSV16BX_BCLK_RISING; + break; + + case LSM6DSV16BX_BCLK_FALLING: + *val = LSM6DSV16BX_BCLK_FALLING; + break; + + default: + *val = LSM6DSV16BX_BCLK_RISING; + break; + } + return ret; +} + +/** + * @brief Enables TDM delayed configuration.[set] + * + * @param ctx read / write interface definitions + * @param val Enables TDM delayed configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_tdm_delayed_conf_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16bx_tdm_cfg0_t tdm_cfg0; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + if (ret == 0) + { + tdm_cfg0.tdm_delayed_cfg = val; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + } + + return ret; +} + +/** + * @brief Enables TDM delayed configuration.[get] + * + * @param ctx read / write interface definitions + * @param val Enables TDM delayed configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_tdm_delayed_conf_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16bx_tdm_cfg0_t tdm_cfg0; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + *val = tdm_cfg0.tdm_delayed_cfg; + + return ret; +} + + +/** + * @brief Selects order of transmission of TDM axes.[set] + * + * @param ctx read / write interface definitions + * @param val TDM_ORDER_ZYX, TDM_ORDER_XZY, TDM_ORDER_XYZ, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_tdm_axis_order_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_tdm_axis_order_t val) +{ + lsm6dsv16bx_tdm_cfg1_t tdm_cfg1; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1); + if (ret == 0) + { + tdm_cfg1.tdm_axes_ord_sel = (uint8_t)val & 0x03U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1); + } + + return ret; +} + +/** + * @brief Selects order of transmission of TDM axes.[get] + * + * @param ctx read / write interface definitions + * @param val TDM_ORDER_ZYX, TDM_ORDER_XZY, TDM_ORDER_XYZ, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_tdm_axis_order_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_tdm_axis_order_t *val) +{ + lsm6dsv16bx_tdm_cfg1_t tdm_cfg1; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1); + switch (tdm_cfg1.tdm_axes_ord_sel) + { + case LSM6DSV16BX_TDM_ORDER_ZYX: + *val = LSM6DSV16BX_TDM_ORDER_ZYX; + break; + + case LSM6DSV16BX_TDM_ORDER_XZY: + *val = LSM6DSV16BX_TDM_ORDER_XZY; + break; + + case LSM6DSV16BX_TDM_ORDER_XYZ: + *val = LSM6DSV16BX_TDM_ORDER_XYZ; + break; + + default: + *val = LSM6DSV16BX_TDM_ORDER_ZYX; + break; + } + return ret; +} + +/** + * @brief TDM channel accelerometer full-scale selection.[set] + * + * @param ctx read / write interface definitions + * @param val TDM_2g, TDM_4g, TDM_8g, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_tdm_xl_full_scale_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_tdm_xl_full_scale_t val) +{ + lsm6dsv16bx_tdm_cfg2_t tdm_cfg2; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1); + if (ret == 0) + { + tdm_cfg2.tdm_fs_xl = (uint8_t)val & 0x3U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1); + } + + return ret; +} + +/** + * @brief TDM channel accelerometer full-scale selection.[get] + * + * @param ctx read / write interface definitions + * @param val TDM_2g, TDM_4g, TDM_8g, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16bx_tdm_xl_full_scale_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_tdm_xl_full_scale_t *val) +{ + lsm6dsv16bx_tdm_cfg2_t tdm_cfg2; + int32_t ret; + + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1); + switch (tdm_cfg2.tdm_fs_xl) + { + case LSM6DSV16BX_TDM_2g: + *val = LSM6DSV16BX_TDM_2g; + break; + + case LSM6DSV16BX_TDM_4g: + *val = LSM6DSV16BX_TDM_4g; + break; + + case LSM6DSV16BX_TDM_8g: + *val = LSM6DSV16BX_TDM_8g; + break; + + default: + *val = LSM6DSV16BX_TDM_2g; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @} + * + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dsv16bx_STdC/driver/lsm6dsv16bx_reg.h b/sensor/stmemsc/lsm6dsv16bx_STdC/driver/lsm6dsv16bx_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..ea2ccda3f255300bd0d8a16e271be6155d317dbc --- /dev/null +++ b/sensor/stmemsc/lsm6dsv16bx_STdC/driver/lsm6dsv16bx_reg.h @@ -0,0 +1,3801 @@ +/** + ****************************************************************************** + * @file lsm6dsv16bx_reg.h + * @author Sensors Software Solution Team + * @brief This file contains all the functions prototypes for the + * lsm6dsv16bx_reg.c driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2022 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef LSM6DSV16BX_REGS_H +#define LSM6DSV16BX_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include + +/** @addtogroup LSM6DSV16BX + * @{ + * + */ + +/** @defgroup Endianness definitions + * @{ + * + */ + +#ifndef DRV_BYTE_ORDER +#ifndef __BYTE_ORDER__ + +#define DRV_LITTLE_ENDIAN 1234 +#define DRV_BIG_ENDIAN 4321 + +/** if _BYTE_ORDER is not defined, choose the endianness of your architecture + * by uncommenting the define which fits your platform endianness + */ +//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN +#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN + +#else /* defined __BYTE_ORDER__ */ + +#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ +#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ +#define DRV_BYTE_ORDER __BYTE_ORDER__ + +#endif /* __BYTE_ORDER__*/ +#endif /* DRV_BYTE_ORDER */ + +/** + * @} + * + */ + +/** @defgroup STMicroelectronics sensors common types + * @{ + * + */ + +#ifndef MEMS_SHARED_TYPES +#define MEMS_SHARED_TYPES + +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} bitwise_t; + +#define PROPERTY_DISABLE (0U) +#define PROPERTY_ENABLE (1U) + +/** @addtogroup Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); +typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); + +typedef struct +{ + /** Component mandatory fields **/ + stmdev_write_ptr write_reg; + stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; + /** Customizable optional pointer **/ + void *handle; +} stmdev_ctx_t; + +/** + * @} + * + */ + +#endif /* MEMS_SHARED_TYPES */ + +#ifndef MEMS_UCF_SHARED_TYPES +#define MEMS_UCF_SHARED_TYPES + +/** @defgroup Generic address-data structure definition + * @brief This structure is useful to load a predefined configuration + * of a sensor. + * You can create a sensor configuration by your own or using + * Unico / Unicleo tools available on STMicroelectronics + * web site. + * + * @{ + * + */ + +typedef struct +{ + uint8_t address; + uint8_t data; +} ucf_line_t; + +/** + * @} + * + */ + +#endif /* MEMS_UCF_SHARED_TYPES */ + +/** + * @} + * + */ + +/** @defgroup LSM6DSV16BX_Infos + * @{ + * + */ + +/** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ +#define LSM6DSV16BX_I2C_ADD_L 0xD5U +#define LSM6DSV16BX_I2C_ADD_H 0xD7U + +/** Device Identification (Who am I) **/ +#define LSM6DSV16BX_ID 0x71U + +/** + * @} + * + */ + +/** @defgroup bitfields page main + * @{ + * + */ + +#define LSM6DSV16BX_FUNC_CFG_ACCESS 0x1U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t sw_por : 1; + uint8_t fsm_wr_ctrl_en : 1; + uint8_t not_used1 : 3; + uint8_t emb_func_reg_access : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t emb_func_reg_access : 1; + uint8_t not_used1 : 3; + uint8_t fsm_wr_ctrl_en : 1; + uint8_t sw_por : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_func_cfg_access_t; + +#define LSM6DSV16BX_PIN_CTRL 0x2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 5; + uint8_t ibhr_por_en : 1; + uint8_t sdo_pu_en : 1; + uint8_t tdm_wclk_pu_dis : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tdm_wclk_pu_dis : 1; + uint8_t sdo_pu_en : 1; + uint8_t ibhr_por_en : 1; + uint8_t not_used0 : 5; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_pin_ctrl_t; + +#define LSM6DSV16BX_IF_CFG 0x3U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t i2c_i3c_disable : 1; + uint8_t not_used0 : 1; + uint8_t sim : 1; + uint8_t pp_od : 1; + uint8_t h_lactive : 1; + uint8_t asf_ctrl : 1; + uint8_t tdm_out_pu_en : 1; + uint8_t sda_pu_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sda_pu_en : 1; + uint8_t tdm_out_pu_en : 1; + uint8_t asf_ctrl : 1; + uint8_t h_lactive : 1; + uint8_t pp_od : 1; + uint8_t sim : 1; + uint8_t not_used0 : 1; + uint8_t i2c_i3c_disable : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_if_cfg_t; + +#define LSM6DSV16BX_FIFO_CTRL1 0x7U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wtm : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t wtm : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fifo_ctrl1_t; + +#define LSM6DSV16BX_FIFO_CTRL2 0x8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xl_dualc_batch_from_fsm : 1; + uint8_t uncompr_rate : 2; + uint8_t not_used0 : 1; + uint8_t odr_chg_en : 1; + uint8_t not_used1 : 1; + uint8_t fifo_compr_rt_en : 1; + uint8_t stop_on_wtm : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t stop_on_wtm : 1; + uint8_t fifo_compr_rt_en : 1; + uint8_t not_used1 : 1; + uint8_t odr_chg_en : 1; + uint8_t not_used0 : 1; + uint8_t uncompr_rate : 2; + uint8_t xl_dualc_batch_from_fsm : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fifo_ctrl2_t; + +#define LSM6DSV16BX_FIFO_CTRL3 0x9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bdr_xl : 4; + uint8_t bdr_gy : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bdr_gy : 4; + uint8_t bdr_xl : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fifo_ctrl3_t; + +#define LSM6DSV16BX_FIFO_CTRL4 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_mode : 3; + uint8_t not_used0 : 1; + uint8_t odr_t_batch : 2; + uint8_t dec_ts_batch : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dec_ts_batch : 2; + uint8_t odr_t_batch : 2; + uint8_t not_used0 : 1; + uint8_t fifo_mode : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fifo_ctrl4_t; + +#define LSM6DSV16BX_COUNTER_BDR_REG1 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t cnt_bdr_th : 2; + uint8_t ah_qvar_batch_en : 1; + uint8_t not_used0 : 2; + uint8_t trig_counter_bdr : 2; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t trig_counter_bdr : 2; + uint8_t not_used0 : 2; + uint8_t ah_qvar_batch_en : 1; + uint8_t cnt_bdr_th : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_counter_bdr_reg1_t; + +#define LSM6DSV16BX_COUNTER_BDR_REG2 0x0CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t cnt_bdr_th : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t cnt_bdr_th : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_counter_bdr_reg2_t; + +#define LSM6DSV16BX_INT1_CTRL 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_drdy_xl : 1; + uint8_t int1_drdy_g : 1; + uint8_t not_used0 : 1; + uint8_t int1_fifo_th : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_fifo_full : 1; + uint8_t int1_cnt_bdr : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t int1_cnt_bdr : 1; + uint8_t int1_fifo_full : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_fifo_th : 1; + uint8_t not_used0 : 1; + uint8_t int1_drdy_g : 1; + uint8_t int1_drdy_xl : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_int1_ctrl_t; + +#define LSM6DSV16BX_INT2_CTRL 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_drdy_xl : 1; + uint8_t int2_drdy_g : 1; + uint8_t not_used0 : 1; + uint8_t int2_fifo_th : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_fifo_full : 1; + uint8_t int2_cnt_bdr : 1; + uint8_t int2_emb_func_endop : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_emb_func_endop : 1; + uint8_t int2_cnt_bdr : 1; + uint8_t int2_fifo_full : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_fifo_th : 1; + uint8_t not_used0 : 1; + uint8_t int2_drdy_g : 1; + uint8_t int2_drdy_xl : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_int2_ctrl_t; + +#define LSM6DSV16BX_WHO_AM_I 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t id : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t id : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_who_am_i_t; + +#define LSM6DSV16BX_CTRL1 0x10U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t odr_xl : 4; + uint8_t op_mode_xl : 3; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t op_mode_xl : 3; + uint8_t odr_xl : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_ctrl1_t; + +#define LSM6DSV16BX_CTRL2 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t odr_g : 4; + uint8_t op_mode_g : 3; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t op_mode_g : 3; + uint8_t odr_g : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_ctrl2_t; + +#define LSM6DSV16BX_CTRL3 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sw_reset : 1; + uint8_t not_used0 : 1; + uint8_t if_inc : 1; + uint8_t not_used1 : 3; + uint8_t bdu : 1; + uint8_t boot : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t boot : 1; + uint8_t bdu : 1; + uint8_t not_used1 : 3; + uint8_t if_inc : 1; + uint8_t not_used0 : 1; + uint8_t sw_reset : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_ctrl3_t; + +#define LSM6DSV16BX_CTRL4 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used1 : 1; + uint8_t drdy_pulsed : 1; + uint8_t int2_drdy_temp : 1; + uint8_t drdy_mask : 1; + uint8_t int2_on_int1 : 1; + uint8_t not_used0 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 3; + uint8_t int2_on_int1 : 1; + uint8_t drdy_mask : 1; + uint8_t int2_drdy_temp : 1; + uint8_t drdy_pulsed : 1; + uint8_t not_used1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_ctrl4_t; + +#define LSM6DSV16BX_CTRL5 0x14U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int_en_i3c : 1; + uint8_t bus_act_sel : 2; + uint8_t not_used0 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 5; + uint8_t bus_act_sel : 2; + uint8_t int_en_i3c : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_ctrl5_t; + +#define LSM6DSV16BX_CTRL6 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_g : 4; + uint8_t lpf1_g_bw : 3; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t lpf1_g_bw : 3; + uint8_t fs_g : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_ctrl6_t; + +#define LSM6DSV16BX_CTRL7 0x16U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t lpf1_g_en : 1; + uint8_t not_used0 : 1; + uint8_t ah_qvar2_en : 1; + uint8_t ah_qvar1_en : 1; + uint8_t ah_qvar_c_zin : 2; + uint8_t int2_drdy_ah_qvar : 1; + uint8_t ah_qvar_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ah_qvar_en : 1; + uint8_t int2_drdy_ah_qvar : 1; + uint8_t ah_qvar_c_zin : 2; + uint8_t ah_qvar1_en : 1; + uint8_t ah_qvar2_en : 1; + uint8_t not_used0 : 1; + uint8_t lpf1_g_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_ctrl7_t; + +#define LSM6DSV16BX_CTRL8 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_xl : 2; + uint8_t not_used0 : 1; + uint8_t xl_dualc_en : 1; + uint8_t ah_qvar_hpf : 1; + uint8_t hp_lpf2_xl_bw : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t hp_lpf2_xl_bw : 3; + uint8_t ah_qvar_hpf : 1; + uint8_t xl_dualc_en : 1; + uint8_t not_used0 : 1; + uint8_t fs_xl : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_ctrl8_t; + +#define LSM6DSV16BX_CTRL9 0x18U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t usr_off_on_out : 1; + uint8_t usr_off_w : 1; + uint8_t not_used0 : 1; + uint8_t lpf2_xl_en : 1; + uint8_t hp_slope_xl_en : 1; + uint8_t xl_fastsettl_mode : 1; + uint8_t hp_ref_mode_xl : 1; + uint8_t ah_qvar_lpf : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ah_qvar_lpf : 1; + uint8_t hp_ref_mode_xl : 1; + uint8_t xl_fastsettl_mode : 1; + uint8_t hp_slope_xl_en : 1; + uint8_t lpf2_xl_en : 1; + uint8_t not_used0 : 1; + uint8_t usr_off_w : 1; + uint8_t usr_off_on_out : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_ctrl9_t; + +#define LSM6DSV16BX_CTRL10 0x19U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t st_xl : 2; + uint8_t st_g : 2; + uint8_t xl_st_offset : 1; + uint8_t ah_qvar_sw : 1; + uint8_t emb_func_debug : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t emb_func_debug : 1; + uint8_t ah_qvar_sw : 1; + uint8_t xl_st_offset : 1; + uint8_t st_g : 2; + uint8_t st_xl : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_ctrl10_t; + +#define LSM6DSV16BX_CTRL_STATUS 0x1AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t fsm_wr_ctrl_status : 1; + uint8_t not_used1 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 5; + uint8_t fsm_wr_ctrl_status : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_ctrl_status_t; + +#define LSM6DSV16BX_FIFO_STATUS1 0x1BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t diff_fifo : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t diff_fifo : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fifo_status1_t; + +#define LSM6DSV16BX_FIFO_STATUS2 0x1CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t diff_fifo : 1; + uint8_t not_used0 : 2; + uint8_t fifo_ovr_latched : 1; + uint8_t counter_bdr_ia : 1; + uint8_t fifo_full_ia : 1; + uint8_t fifo_ovr_ia : 1; + uint8_t fifo_wtm_ia : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_wtm_ia : 1; + uint8_t fifo_ovr_ia : 1; + uint8_t fifo_full_ia : 1; + uint8_t counter_bdr_ia : 1; + uint8_t fifo_ovr_latched : 1; + uint8_t not_used0 : 2; + uint8_t diff_fifo : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fifo_status2_t; + +#define LSM6DSV16BX_ALL_INT_SRC 0x1DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ff_ia : 1; + uint8_t wu_ia : 1; + uint8_t tap_ia : 1; + uint8_t not_used0 : 1; + uint8_t d6d_ia : 1; + uint8_t sleep_change_ia : 1; + uint8_t not_used1 : 1; + uint8_t emb_func_ia : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t emb_func_ia : 1; + uint8_t not_used1 : 1; + uint8_t sleep_change_ia : 1; + uint8_t d6d_ia : 1; + uint8_t not_used0 : 1; + uint8_t tap_ia : 1; + uint8_t wu_ia : 1; + uint8_t ff_ia : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_all_int_src_t; + +#define LSM6DSV16BX_STATUS_REG 0x1EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xlda : 1; + uint8_t gda : 1; + uint8_t tda : 1; + uint8_t ah_qvarda : 1; + uint8_t not_used0 : 3; + uint8_t timestamp_endcount : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp_endcount : 1; + uint8_t not_used0 : 3; + uint8_t ah_qvarda : 1; + uint8_t tda : 1; + uint8_t gda : 1; + uint8_t xlda : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_status_reg_t; + +#define LSM6DSV16BX_OUT_TEMP_L 0x20U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t temp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t temp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_out_temp_l_t; + +#define LSM6DSV16BX_OUT_TEMP_H 0x21U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t temp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t temp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_out_temp_h_t; + +#define LSM6DSV16BX_OUTX_L_G 0x22U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_outx_l_g_t; + +#define LSM6DSV16BX_OUTX_H_G 0x23U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_outx_h_g_t; + +#define LSM6DSV16BX_OUTY_L_G 0x24U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_outy_l_g_t; + +#define LSM6DSV16BX_OUTY_H_G 0x25U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_outy_h_g_t; + +#define LSM6DSV16BX_OUTZ_L_G 0x26U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_outz_l_g_t; + +#define LSM6DSV16BX_OUTZ_H_G 0x27U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_outz_h_g_t; + +#define LSM6DSV16BX_OUTZ_L_A 0x28U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_outz_l_a_t; + +#define LSM6DSV16BX_OUTZ_H_A 0x29U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_outz_h_a_t; + +#define LSM6DSV16BX_OUTY_L_A 0x2AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_outy_l_a_t; + +#define LSM6DSV16BX_OUTY_H_A 0x2BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_outy_h_a_t; + +#define LSM6DSV16BX_OUTX_L_A 0x2CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_outx_l_a_t; + +#define LSM6DSV16BX_OUTX_H_A 0x2DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_outx_h_a_t; + +#define LSM6DSV16BX_UI_OUTZ_L_A_OIS_DUALC 0x34U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outz_a_ois_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outz_a_ois_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_ui_outz_l_a_ois_dualc_t; + +#define LSM6DSV16BX_UI_OUTZ_H_A_OIS_DUALC 0x35U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outz_a_ois_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outz_a_ois_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_ui_outz_h_a_ois_dualc_t; + +#define LSM6DSV16BX_UI_OUTY_L_A_OIS_DUALC 0x36U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outy_a_ois_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outy_a_ois_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_ui_outy_l_a_ois_dualc_t; + +#define LSM6DSV16BX_UI_OUTY_H_A_OIS_DUALC 0x37U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outy_a_ois_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outy_a_ois_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_ui_outy_h_a_ois_dualc_t; + +#define LSM6DSV16BX_UI_OUTX_L_A_OIS_DUALC 0x38U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outx_a_ois_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outx_a_ois_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_ui_outx_l_a_ois_dualc_t; + +#define LSM6DSV16BX_UI_OUTX_H_A_OIS_DUALC 0x39U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outx_a_ois_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outx_a_ois_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_ui_outx_h_a_ois_dualc_t; + +#define LSM6DSV16BX_AH_QVAR_OUT_L 0x3AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ah_qvar : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ah_qvar : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_ah_qvar_out_l_t; + +#define LSM6DSV16BX_AH_QVAR_OUT_H 0x3BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ah_qvar : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ah_qvar : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_ah_qvar_out_h_t; + +#define LSM6DSV16BX_TIMESTAMP0 0x40U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_timestamp0_t; + +#define LSM6DSV16BX_TIMESTAMP1 0x41U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_timestamp1_t; + +#define LSM6DSV16BX_TIMESTAMP2 0x42U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_timestamp2_t; + +#define LSM6DSV16BX_TIMESTAMP3 0x43U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_timestamp3_t; + +#define LSM6DSV16BX_WAKE_UP_SRC 0x45U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t x_wu : 1; + uint8_t y_wu : 1; + uint8_t z_wu : 1; + uint8_t wu_ia : 1; + uint8_t sleep_state : 1; + uint8_t ff_ia : 1; + uint8_t sleep_change_ia : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t sleep_change_ia : 1; + uint8_t ff_ia : 1; + uint8_t sleep_state : 1; + uint8_t wu_ia : 1; + uint8_t z_wu : 1; + uint8_t y_wu : 1; + uint8_t x_wu : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_wake_up_src_t; + +#define LSM6DSV16BX_TAP_SRC 0x46U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t x_tap : 1; + uint8_t y_tap : 1; + uint8_t z_tap : 1; + uint8_t tap_sign : 1; + uint8_t not_used0 : 1; + uint8_t double_tap : 1; + uint8_t single_tap : 1; + uint8_t tap_ia : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tap_ia : 1; + uint8_t single_tap : 1; + uint8_t double_tap : 1; + uint8_t not_used0 : 1; + uint8_t tap_sign : 1; + uint8_t z_tap : 1; + uint8_t y_tap : 1; + uint8_t x_tap : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_tap_src_t; + +#define LSM6DSV16BX_D6D_SRC 0x47U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t zl : 1; + uint8_t zh : 1; + uint8_t yl : 1; + uint8_t yh : 1; + uint8_t xl : 1; + uint8_t xh : 1; + uint8_t d6d_ia : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t d6d_ia : 1; + uint8_t xh : 1; + uint8_t xl : 1; + uint8_t yh : 1; + uint8_t yl : 1; + uint8_t zh : 1; + uint8_t zl : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_d6d_src_t; + +#define LSM6DSV16BX_EMB_FUNC_STATUS_MAINPAGE 0x49U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t is_step_det : 1; + uint8_t is_tilt : 1; + uint8_t is_sigmot : 1; + uint8_t not_used1 : 1; + uint8_t is_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t is_sigmot : 1; + uint8_t is_tilt : 1; + uint8_t is_step_det : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_emb_func_status_mainpage_t; + +#define LSM6DSV16BX_FSM_STATUS_MAINPAGE 0x4AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm1 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm8 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fsm_status_mainpage_t; + +#define LSM6DSV16BX_MLC_STATUS_MAINPAGE 0x4BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_mlc1 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc4 : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t is_mlc4 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_mlc_status_mainpage_t; + +#define LSM6DSV16BX_INTERNAL_FREQ 0x4FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t freq_fine : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t freq_fine : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_internal_freq_t; + +#define LSM6DSV16BX_FUNCTIONS_ENABLE 0x50U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t inact_en : 2; + uint8_t not_used0 : 1; + uint8_t dis_rst_lir_all_int : 1; + uint8_t not_used1 : 2; + uint8_t timestamp_en : 1; + uint8_t interrupts_enable : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t interrupts_enable : 1; + uint8_t timestamp_en : 1; + uint8_t not_used1 : 2; + uint8_t dis_rst_lir_all_int : 1; + uint8_t not_used0 : 1; + uint8_t inact_en : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_functions_enable_t; + +#define LSM6DSV16BX_INACTIVITY_DUR 0x54U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t inact_dur : 2; + uint8_t xl_inact_odr : 2; + uint8_t wu_inact_ths_w : 3; + uint8_t sleep_status_on_int : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sleep_status_on_int : 1; + uint8_t wu_inact_ths_w : 3; + uint8_t xl_inact_odr : 2; + uint8_t inact_dur : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_inactivity_dur_t; + +#define LSM6DSV16BX_INACTIVITY_THS 0x55U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t inact_ths : 6; + uint8_t not_used0 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 2; + uint8_t inact_ths : 6; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_inactivity_ths_t; + +#define LSM6DSV16BX_TAP_CFG0 0x56U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t lir : 1; + uint8_t tap_x_en : 1; + uint8_t tap_y_en : 1; + uint8_t tap_z_en : 1; + uint8_t slope_fds : 1; + uint8_t hw_func_mask_xl_settl : 1; + uint8_t low_pass_on_6d : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t low_pass_on_6d : 1; + uint8_t hw_func_mask_xl_settl : 1; + uint8_t slope_fds : 1; + uint8_t tap_z_en : 1; + uint8_t tap_y_en : 1; + uint8_t tap_x_en : 1; + uint8_t lir : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_tap_cfg0_t; + +#define LSM6DSV16BX_TAP_CFG1 0x57U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tap_ths_z : 5; + uint8_t tap_priority : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tap_priority : 3; + uint8_t tap_ths_z : 5; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_tap_cfg1_t; + +#define LSM6DSV16BX_TAP_CFG2 0x58U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tap_ths_y : 5; + uint8_t not_used0 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 3; + uint8_t tap_ths_y : 5; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_tap_cfg2_t; + +#define LSM6DSV16BX_TAP_THS_6D 0x59U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tap_ths_x : 5; + uint8_t sixd_ths : 2; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t sixd_ths : 2; + uint8_t tap_ths_x : 5; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_tap_ths_6d_t; + +#define LSM6DSV16BX_TAP_DUR 0x5AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t shock : 2; + uint8_t quiet : 2; + uint8_t dur : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dur : 4; + uint8_t quiet : 2; + uint8_t shock : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_tap_dur_t; + +#define LSM6DSV16BX_WAKE_UP_THS 0x5BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wk_ths : 6; + uint8_t usr_off_on_wu : 1; + uint8_t single_double_tap : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t single_double_tap : 1; + uint8_t usr_off_on_wu : 1; + uint8_t wk_ths : 6; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_wake_up_ths_t; + +#define LSM6DSV16BX_WAKE_UP_DUR 0x5CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sleep_dur : 4; + uint8_t not_used0 : 1; + uint8_t wake_dur : 2; + uint8_t ff_dur : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ff_dur : 1; + uint8_t wake_dur : 2; + uint8_t not_used0 : 1; + uint8_t sleep_dur : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_wake_up_dur_t; + +#define LSM6DSV16BX_FREE_FALL 0x5DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ff_ths : 3; + uint8_t ff_dur : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ff_dur : 5; + uint8_t ff_ths : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_free_fall_t; + +#define LSM6DSV16BX_MD1_CFG 0x5EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t int1_emb_func : 1; + uint8_t int1_6d : 1; + uint8_t int1_double_tap : 1; + uint8_t int1_ff : 1; + uint8_t int1_wu : 1; + uint8_t int1_single_tap : 1; + uint8_t int1_sleep_change : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_sleep_change : 1; + uint8_t int1_single_tap : 1; + uint8_t int1_wu : 1; + uint8_t int1_ff : 1; + uint8_t int1_double_tap : 1; + uint8_t int1_6d : 1; + uint8_t int1_emb_func : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_md1_cfg_t; + +#define LSM6DSV16BX_MD2_CFG 0x5FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_timestamp : 1; + uint8_t int2_emb_func : 1; + uint8_t int2_6d : 1; + uint8_t int2_double_tap : 1; + uint8_t int2_ff : 1; + uint8_t int2_wu : 1; + uint8_t int2_single_tap : 1; + uint8_t int2_sleep_change : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_sleep_change : 1; + uint8_t int2_single_tap : 1; + uint8_t int2_wu : 1; + uint8_t int2_ff : 1; + uint8_t int2_double_tap : 1; + uint8_t int2_6d : 1; + uint8_t int2_emb_func : 1; + uint8_t int2_timestamp : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_md2_cfg_t; + +#define LSM6DSV16BX_EMB_FUNC_CFG 0x63U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t emb_func_disable : 1; + uint8_t emb_func_irq_mask_xl_settl : 1; + uint8_t emb_func_irq_mask_g_settl : 1; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t emb_func_irq_mask_g_settl : 1; + uint8_t emb_func_irq_mask_xl_settl : 1; + uint8_t emb_func_disable : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_emb_func_cfg_t; + +#define LSM6DSV16BX_TDM_CFG0 0x6CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tdm_wclk_bclk_sel : 1; + uint8_t tdm_wclk : 2; + uint8_t not_used0 : 1; + uint8_t tdm_slot_sel : 1; + uint8_t tdm_bclk_edge_sel : 1; + uint8_t tdm_delayed_cfg : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t tdm_delayed_cfg : 1; + uint8_t tdm_bclk_edge_sel : 1; + uint8_t tdm_slot_sel : 1; + uint8_t not_used0 : 1; + uint8_t tdm_wclk : 2; + uint8_t tdm_wclk_bclk_sel : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_tdm_cfg0_t; + +#define LSM6DSV16BX_TDM_CFG1 0x6DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t tdm_axes_ord_sel : 2; + uint8_t tdm_xl_z_en : 1; + uint8_t tdm_xl_y_en : 1; + uint8_t tdm_xl_x_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tdm_xl_x_en : 1; + uint8_t tdm_xl_y_en : 1; + uint8_t tdm_xl_z_en : 1; + uint8_t tdm_axes_ord_sel : 2; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_tdm_cfg1_t; + +#define LSM6DSV16BX_TDM_CFG2 0x6EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tdm_fs_xl : 2; + uint8_t not_used0 : 1; + uint8_t tdm_data_mask : 1; + uint8_t not_used1 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 4; + uint8_t tdm_data_mask : 1; + uint8_t not_used0 : 1; + uint8_t tdm_fs_xl : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_tdm_cfg2_t; + +#define LSM6DSV16BX_UI_INT_OIS 0x6FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 4; + uint8_t st_ois_clampdis : 1; + uint8_t not_used1 : 1; + uint8_t drdy_mask_ois : 1; + uint8_t int2_drdy_ois : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_drdy_ois : 1; + uint8_t drdy_mask_ois : 1; + uint8_t not_used1 : 1; + uint8_t st_ois_clampdis : 1; + uint8_t not_used0 : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_ui_int_ois_t; + +#define LSM6DSV16BX_Z_OFS_USR 0x73U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t z_ofs_usr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t z_ofs_usr : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_z_ofs_usr_t; + +#define LSM6DSV16BX_Y_OFS_USR 0x74U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t y_ofs_usr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t y_ofs_usr : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_y_ofs_usr_t; + +#define LSM6DSV16BX_X_OFS_USR 0x75U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t x_ofs_usr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t x_ofs_usr : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_x_ofs_usr_t; + +#define LSM6DSV16BX_FIFO_DATA_OUT_TAG 0x78U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t tag_cnt : 2; + uint8_t tag_sensor : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tag_sensor : 5; + uint8_t tag_cnt : 2; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fifo_data_out_tag_t; + +#define LSM6DSV16BX_FIFO_DATA_OUT_BYTE_0 0x79U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fifo_data_out_byte_0_t; + +#define LSM6DSV16BX_FIFO_DATA_OUT_BYTE_1 0x7AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fifo_data_out_byte_1_t; + +#define LSM6DSV16BX_FIFO_DATA_OUT_BYTE_2 0x7BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fifo_data_out_byte_2_t; + +#define LSM6DSV16BX_FIFO_DATA_OUT_BYTE_3 0x7CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fifo_data_out_byte_3_t; + +#define LSM6DSV16BX_FIFO_DATA_OUT_BYTE_4 0x7DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fifo_data_out_byte_4_t; + +#define LSM6DSV16BX_FIFO_DATA_OUT_BYTE_5 0x7EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fifo_data_out_byte_5_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page embedded + * @{ + * + */ + +#define LSM6DSV16BX_PAGE_SEL 0x2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 4; + uint8_t page_sel : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_sel : 4; + uint8_t not_used0 : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_page_sel_t; + +#define LSM6DSV16BX_EMB_FUNC_EN_A 0x4U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used2 : 1; + uint8_t sflp_game_en : 1; + uint8_t not_used0 : 1; + uint8_t pedo_en : 1; + uint8_t tilt_en : 1; + uint8_t sign_motion_en : 1; + uint8_t not_used1 : 1; + uint8_t mlc_before_fsm_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_before_fsm_en : 1; + uint8_t not_used1 : 1; + uint8_t sign_motion_en : 1; + uint8_t tilt_en : 1; + uint8_t pedo_en : 1; + uint8_t not_used0 : 1; + uint8_t sflp_game_en : 1; + uint8_t not_used2 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_emb_func_en_a_t; + +#define LSM6DSV16BX_EMB_FUNC_EN_B 0x5U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_en : 1; + uint8_t not_used0 : 2; + uint8_t fifo_compr_en : 1; + uint8_t mlc_en : 1; + uint8_t not_used1 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 3; + uint8_t mlc_en : 1; + uint8_t fifo_compr_en : 1; + uint8_t not_used0 : 2; + uint8_t fsm_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_emb_func_en_b_t; + +#define LSM6DSV16BX_EMB_FUNC_EXEC_STATUS 0x7U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t emb_func_endop : 1; + uint8_t emb_func_exec_ovr : 1; + uint8_t not_used0 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 6; + uint8_t emb_func_exec_ovr : 1; + uint8_t emb_func_endop : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_emb_func_exec_status_t; + +#define LSM6DSV16BX_PAGE_ADDRESS 0x8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t page_addr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_addr : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_page_address_t; + +#define LSM6DSV16BX_PAGE_VALUE 0x9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t page_value : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_value : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_page_value_t; + +#define LSM6DSV16BX_EMB_FUNC_INT1 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t int1_step_detector : 1; + uint8_t int1_tilt : 1; + uint8_t int1_sig_mot : 1; + uint8_t not_used1 : 1; + uint8_t int1_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t int1_sig_mot : 1; + uint8_t int1_tilt : 1; + uint8_t int1_step_detector : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_emb_func_int1_t; + +#define LSM6DSV16BX_FSM_INT1 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_fsm1 : 1; + uint8_t int1_fsm2 : 1; + uint8_t int1_fsm3 : 1; + uint8_t int1_fsm4 : 1; + uint8_t int1_fsm5 : 1; + uint8_t int1_fsm6 : 1; + uint8_t int1_fsm7 : 1; + uint8_t int1_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_fsm8 : 1; + uint8_t int1_fsm7 : 1; + uint8_t int1_fsm6 : 1; + uint8_t int1_fsm5 : 1; + uint8_t int1_fsm4 : 1; + uint8_t int1_fsm3 : 1; + uint8_t int1_fsm2 : 1; + uint8_t int1_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fsm_int1_t; + +#define LSM6DSV16BX_MLC_INT1 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_mlc1 : 1; + uint8_t int1_mlc2 : 1; + uint8_t int1_mlc3 : 1; + uint8_t int1_mlc4 : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t int1_mlc4 : 1; + uint8_t int1_mlc3 : 1; + uint8_t int1_mlc2 : 1; + uint8_t int1_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_mlc_int1_t; + +#define LSM6DSV16BX_EMB_FUNC_INT2 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t int2_step_detector : 1; + uint8_t int2_tilt : 1; + uint8_t int2_sig_mot : 1; + uint8_t not_used1 : 1; + uint8_t int2_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t int2_sig_mot : 1; + uint8_t int2_tilt : 1; + uint8_t int2_step_detector : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_emb_func_int2_t; + +#define LSM6DSV16BX_FSM_INT2 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_fsm1 : 1; + uint8_t int2_fsm2 : 1; + uint8_t int2_fsm3 : 1; + uint8_t int2_fsm4 : 1; + uint8_t int2_fsm5 : 1; + uint8_t int2_fsm6 : 1; + uint8_t int2_fsm7 : 1; + uint8_t int2_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_fsm8 : 1; + uint8_t int2_fsm7 : 1; + uint8_t int2_fsm6 : 1; + uint8_t int2_fsm5 : 1; + uint8_t int2_fsm4 : 1; + uint8_t int2_fsm3 : 1; + uint8_t int2_fsm2 : 1; + uint8_t int2_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fsm_int2_t; + +#define LSM6DSV16BX_MLC_INT2 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_mlc1 : 1; + uint8_t int2_mlc2 : 1; + uint8_t int2_mlc3 : 1; + uint8_t int2_mlc4 : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t int2_mlc4 : 1; + uint8_t int2_mlc3 : 1; + uint8_t int2_mlc2 : 1; + uint8_t int2_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_mlc_int2_t; + +#define LSM6DSV16BX_EMB_FUNC_STATUS 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t is_step_det : 1; + uint8_t is_tilt : 1; + uint8_t is_sigmot : 1; + uint8_t not_used1 : 1; + uint8_t is_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t is_sigmot : 1; + uint8_t is_tilt : 1; + uint8_t is_step_det : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_emb_func_status_t; + +#define LSM6DSV16BX_FSM_STATUS 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm1 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm8 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fsm_status_t; + +#define LSM6DSV16BX_MLC_STATUS 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_mlc1 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc4 : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t is_mlc4 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_mlc_status_t; + +#define LSM6DSV16BX_PAGE_RW 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 5; + uint8_t page_read : 1; + uint8_t page_write : 1; + uint8_t emb_func_lir : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t emb_func_lir : 1; + uint8_t page_write : 1; + uint8_t page_read : 1; + uint8_t not_used0 : 5; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_page_rw_t; + +#define LSM6DSV16BX_EMB_FUNC_FIFO_EN_A 0x44U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t sflp_game_fifo_en : 1; + uint8_t not_used1 : 2; + uint8_t sflp_gravity_fifo_en : 1; + uint8_t sflp_gbias_fifo_en : 1; + uint8_t step_counter_fifo_en : 1; + uint8_t mlc_fifo_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_fifo_en : 1; + uint8_t step_counter_fifo_en : 1; + uint8_t sflp_gbias_fifo_en : 1; + uint8_t sflp_gravity_fifo_en : 1; + uint8_t not_used1 : 2; + uint8_t sflp_game_fifo_en : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_emb_func_fifo_en_a_t; + +#define LSM6DSV16BX_EMB_FUNC_FIFO_EN_B 0x45U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t mlc_filter_feature_fifo_en : 1; + uint8_t not_used1 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 6; + uint8_t mlc_filter_feature_fifo_en : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_emb_func_fifo_en_b_t; + +#define LSM6DSV16BX_FSM_ENABLE 0x46U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm1_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm8_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm8_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm1_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fsm_enable_t; + +#define LSM6DSV16BX_FSM_LONG_COUNTER_L 0x48U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fsm_long_counter_l_t; + +#define LSM6DSV16BX_FSM_LONG_COUNTER_H 0x49U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fsm_long_counter_h_t; + +#define LSM6DSV16BX_INT_ACK_MASK 0x4BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t iack_mask : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t iack_mask : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_int_ack_mask_t; + +#define LSM6DSV16BX_FSM_OUTS1 0x4CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm1_n_v : 1; + uint8_t fsm1_p_v : 1; + uint8_t fsm1_n_3 : 1; + uint8_t fsm1_p_3 : 1; + uint8_t fsm1_n_2 : 1; + uint8_t fsm1_p_2 : 1; + uint8_t fsm1_n_1 : 1; + uint8_t fsm1_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm1_p_1 : 1; + uint8_t fsm1_n_1 : 1; + uint8_t fsm1_p_2 : 1; + uint8_t fsm1_n_2 : 1; + uint8_t fsm1_p_3 : 1; + uint8_t fsm1_n_3 : 1; + uint8_t fsm1_p_v : 1; + uint8_t fsm1_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fsm_outs1_t; + +#define LSM6DSV16BX_FSM_OUTS2 0x4DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm2_n_v : 1; + uint8_t fsm2_p_v : 1; + uint8_t fsm2_n_3 : 1; + uint8_t fsm2_p_3 : 1; + uint8_t fsm2_n_2 : 1; + uint8_t fsm2_p_2 : 1; + uint8_t fsm2_n_1 : 1; + uint8_t fsm2_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm2_p_1 : 1; + uint8_t fsm2_n_1 : 1; + uint8_t fsm2_p_2 : 1; + uint8_t fsm2_n_2 : 1; + uint8_t fsm2_p_3 : 1; + uint8_t fsm2_n_3 : 1; + uint8_t fsm2_p_v : 1; + uint8_t fsm2_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fsm_outs2_t; + +#define LSM6DSV16BX_FSM_OUTS3 0x4EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm3_n_v : 1; + uint8_t fsm3_p_v : 1; + uint8_t fsm3_n_3 : 1; + uint8_t fsm3_p_3 : 1; + uint8_t fsm3_n_2 : 1; + uint8_t fsm3_p_2 : 1; + uint8_t fsm3_n_1 : 1; + uint8_t fsm3_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm3_p_1 : 1; + uint8_t fsm3_n_1 : 1; + uint8_t fsm3_p_2 : 1; + uint8_t fsm3_n_2 : 1; + uint8_t fsm3_p_3 : 1; + uint8_t fsm3_n_3 : 1; + uint8_t fsm3_p_v : 1; + uint8_t fsm3_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fsm_outs3_t; + +#define LSM6DSV16BX_FSM_OUTS4 0x4FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm4_n_v : 1; + uint8_t fsm4_p_v : 1; + uint8_t fsm4_n_3 : 1; + uint8_t fsm4_p_3 : 1; + uint8_t fsm4_n_2 : 1; + uint8_t fsm4_p_2 : 1; + uint8_t fsm4_n_1 : 1; + uint8_t fsm4_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm4_p_1 : 1; + uint8_t fsm4_n_1 : 1; + uint8_t fsm4_p_2 : 1; + uint8_t fsm4_n_2 : 1; + uint8_t fsm4_p_3 : 1; + uint8_t fsm4_n_3 : 1; + uint8_t fsm4_p_v : 1; + uint8_t fsm4_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fsm_outs4_t; + +#define LSM6DSV16BX_FSM_OUTS5 0x50U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm5_n_v : 1; + uint8_t fsm5_p_v : 1; + uint8_t fsm5_n_3 : 1; + uint8_t fsm5_p_3 : 1; + uint8_t fsm5_n_2 : 1; + uint8_t fsm5_p_2 : 1; + uint8_t fsm5_n_1 : 1; + uint8_t fsm5_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm5_p_1 : 1; + uint8_t fsm5_n_1 : 1; + uint8_t fsm5_p_2 : 1; + uint8_t fsm5_n_2 : 1; + uint8_t fsm5_p_3 : 1; + uint8_t fsm5_n_3 : 1; + uint8_t fsm5_p_v : 1; + uint8_t fsm5_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fsm_outs5_t; + +#define LSM6DSV16BX_FSM_OUTS6 0x51U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm6_n_v : 1; + uint8_t fsm6_p_v : 1; + uint8_t fsm6_n_3 : 1; + uint8_t fsm6_p_3 : 1; + uint8_t fsm6_n_2 : 1; + uint8_t fsm6_p_2 : 1; + uint8_t fsm6_n_1 : 1; + uint8_t fsm6_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm6_p_1 : 1; + uint8_t fsm6_n_1 : 1; + uint8_t fsm6_p_2 : 1; + uint8_t fsm6_n_2 : 1; + uint8_t fsm6_p_3 : 1; + uint8_t fsm6_n_3 : 1; + uint8_t fsm6_p_v : 1; + uint8_t fsm6_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fsm_outs6_t; + +#define LSM6DSV16BX_FSM_OUTS7 0x52U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm7_n_v : 1; + uint8_t fsm7_p_v : 1; + uint8_t fsm7_n_3 : 1; + uint8_t fsm7_p_3 : 1; + uint8_t fsm7_n_2 : 1; + uint8_t fsm7_p_2 : 1; + uint8_t fsm7_n_1 : 1; + uint8_t fsm7_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm7_p_1 : 1; + uint8_t fsm7_n_1 : 1; + uint8_t fsm7_p_2 : 1; + uint8_t fsm7_n_2 : 1; + uint8_t fsm7_p_3 : 1; + uint8_t fsm7_n_3 : 1; + uint8_t fsm7_p_v : 1; + uint8_t fsm7_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fsm_outs7_t; + +#define LSM6DSV16BX_FSM_OUTS8 0x53U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm8_n_v : 1; + uint8_t fsm8_p_v : 1; + uint8_t fsm8_n_3 : 1; + uint8_t fsm8_p_3 : 1; + uint8_t fsm8_n_2 : 1; + uint8_t fsm8_p_2 : 1; + uint8_t fsm8_n_1 : 1; + uint8_t fsm8_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm8_p_1 : 1; + uint8_t fsm8_n_1 : 1; + uint8_t fsm8_p_2 : 1; + uint8_t fsm8_n_2 : 1; + uint8_t fsm8_p_3 : 1; + uint8_t fsm8_n_3 : 1; + uint8_t fsm8_p_v : 1; + uint8_t fsm8_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fsm_outs8_t; + +#define LSM6DSV16BX_SFLP_ODR 0x5EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t sflp_game_odr : 3; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t sflp_game_odr : 3; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_sflp_odr_t; + +#define LSM6DSV16BX_FSM_ODR 0x5FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t fsm_odr : 3; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t fsm_odr : 3; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fsm_odr_t; + +#define LSM6DSV16BX_MLC_ODR 0x60U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 4; + uint8_t mlc_odr : 3; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t mlc_odr : 3; + uint8_t not_used0 : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_mlc_odr_t; + +#define LSM6DSV16BX_STEP_COUNTER_L 0x62U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t step : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t step : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_step_counter_l_t; + +#define LSM6DSV16BX_STEP_COUNTER_H 0x63U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t step : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t step : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_step_counter_h_t; + +#define LSM6DSV16BX_EMB_FUNC_SRC 0x64U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t stepcounter_bit_set : 1; + uint8_t step_overflow : 1; + uint8_t step_count_delta_ia : 1; + uint8_t step_detected : 1; + uint8_t not_used1 : 1; + uint8_t pedo_rst_step : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pedo_rst_step : 1; + uint8_t not_used1 : 1; + uint8_t step_detected : 1; + uint8_t step_count_delta_ia : 1; + uint8_t step_overflow : 1; + uint8_t stepcounter_bit_set : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_emb_func_src_t; + +#define LSM6DSV16BX_EMB_FUNC_INIT_A 0x66U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t sflp_game_init : 1; + uint8_t not_used2 : 1; + uint8_t step_det_init : 1; + uint8_t tilt_init : 1; + uint8_t sig_mot_init : 1; + uint8_t not_used1 : 1; + uint8_t mlc_before_fsm_init : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_before_fsm_init : 1; + uint8_t not_used1 : 1; + uint8_t sig_mot_init : 1; + uint8_t tilt_init : 1; + uint8_t step_det_init : 1; + uint8_t not_used2 : 1; + uint8_t sflp_game_init : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_emb_func_init_a_t; + +#define LSM6DSV16BX_EMB_FUNC_INIT_B 0x67U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_init : 1; + uint8_t not_used0 : 2; + uint8_t fifo_compr_init : 1; + uint8_t mlc_init : 1; + uint8_t not_used1 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 3; + uint8_t mlc_init : 1; + uint8_t fifo_compr_init : 1; + uint8_t not_used0 : 2; + uint8_t fsm_init : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_emb_func_init_b_t; + +#define LSM6DSV16BX_MLC1_SRC 0x70U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc1_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc1_src : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_mlc1_src_t; + +#define LSM6DSV16BX_MLC2_SRC 0x71U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc2_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc2_src : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_mlc2_src_t; + +#define LSM6DSV16BX_MLC3_SRC 0x72U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc3_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc3_src : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_mlc3_src_t; + +#define LSM6DSV16BX_MLC4_SRC 0x73U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc4_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc4_src : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_mlc4_src_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page pg0_emb_adv + * @{ + * + */ +#define LSM6DSV16BX_EMB_ADV_PG_0 0x000 + +#define LSM6DSV16BX_SFLP_GAME_GBIASX_L 0x6EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasx : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_sflp_game_gbiasx_l_t; + +#define LSM6DSV16BX_SFLP_GAME_GBIASX_H 0x6FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasx : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_sflp_game_gbiasx_h_t; + +#define LSM6DSV16BX_SFLP_GAME_GBIASY_L 0x70U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasy : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_sflp_game_gbiasy_l_t; + +#define LSM6DSV16BX_SFLP_GAME_GBIASY_H 0x71U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasy : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_sflp_game_gbiasy_h_t; + +#define LSM6DSV16BX_SFLP_GAME_GBIASZ_L 0x72U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_sflp_game_gbiasz_l_t; + +#define LSM6DSV16BX_SFLP_GAME_GBIASZ_H 0x73U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_sflp_game_gbiasz_h_t; + +#define LSM6DSV16BX_FSM_QVAR_SENSITIVITY_L 0xBAU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_qvar_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_qvar_s : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fsm_qvar_sensitivity_l_t; + +#define LSM6DSV16BX_FSM_QVAR_SENSITIVITY_H 0xBBU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_qvar_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_qvar_s : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fsm_qvar_sensitivity_h_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page pg1_emb_adv + * @{ + * + */ + +#define LSM6DSV16BX_EMB_ADV_PG_1 0x001 + +#define LSM6DSV16BX_FSM_LC_TIMEOUT_L 0x17AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc_timeout : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc_timeout : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fsm_lc_timeout_l_t; + +#define LSM6DSV16BX_FSM_LC_TIMEOUT_H 0x17BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc_timeout : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc_timeout : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fsm_lc_timeout_h_t; + +#define LSM6DSV16BX_FSM_PROGRAMS 0x17CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_n_prog : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_n_prog : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fsm_programs_t; + +#define LSM6DSV16BX_FSM_START_ADD_L 0x17EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_start : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_start : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fsm_start_add_l_t; + +#define LSM6DSV16BX_FSM_START_ADD_H 0x17FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_start : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_start : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_fsm_start_add_h_t; + +#define LSM6DSV16BX_PEDO_CMD_REG 0x183U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t fp_rejection_en : 1; + uint8_t carry_count_en : 1; + uint8_t not_used1 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 4; + uint8_t carry_count_en : 1; + uint8_t fp_rejection_en : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_pedo_cmd_reg_t; + +#define LSM6DSV16BX_PEDO_DEB_STEPS_CONF 0x184U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t deb_step : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t deb_step : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_pedo_deb_steps_conf_t; + +#define LSM6DSV16BX_PEDO_SC_DELTAT_L 0x1D0U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t pd_sc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pd_sc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_pedo_sc_deltat_l_t; + +#define LSM6DSV16BX_PEDO_SC_DELTAT_H 0x1D1U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t pd_sc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pd_sc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_pedo_sc_deltat_h_t; + +#define LSM6DSV16BX_MLC_QVAR_SENSITIVITY_L 0x1E8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc_qvar_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_qvar_s : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_mlc_qvar_sensitivity_l_t; + +#define LSM6DSV16BX_MLC_QVAR_SENSITIVITY_H 0x1E9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc_qvar_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_qvar_s : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16bx_mlc_qvar_sensitivity_h_t; + +/** + * @} + * + */ + +#define LSM6DSV16BX_START_FSM_ADD 0x035CU + +/** + * @defgroup LSM6DSV16BX_Register_Union + * @brief These unions group all the registers having a bit-field + * description. + * These unions are useful but it's not needed by the driver. + * + * REMOVING this unions you are compliant with: + * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " + * + * @{ + * + */ +typedef union +{ + lsm6dsv16bx_func_cfg_access_t func_cfg_access; + lsm6dsv16bx_pin_ctrl_t pin_ctrl; + lsm6dsv16bx_if_cfg_t if_cfg; + lsm6dsv16bx_fifo_ctrl1_t fifo_ctrl1; + lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2; + lsm6dsv16bx_fifo_ctrl3_t fifo_ctrl3; + lsm6dsv16bx_fifo_ctrl4_t fifo_ctrl4; + lsm6dsv16bx_counter_bdr_reg1_t counter_bdr_reg1; + lsm6dsv16bx_counter_bdr_reg2_t counter_bdr_reg2; + lsm6dsv16bx_int1_ctrl_t int1_ctrl; + lsm6dsv16bx_int2_ctrl_t int2_ctrl; + lsm6dsv16bx_who_am_i_t who_am_i; + lsm6dsv16bx_ctrl1_t ctrl1; + lsm6dsv16bx_ctrl2_t ctrl2; + lsm6dsv16bx_ctrl3_t ctrl3; + lsm6dsv16bx_ctrl4_t ctrl4; + lsm6dsv16bx_ctrl5_t ctrl5; + lsm6dsv16bx_ctrl6_t ctrl6; + lsm6dsv16bx_ctrl7_t ctrl7; + lsm6dsv16bx_ctrl8_t ctrl8; + lsm6dsv16bx_ctrl9_t ctrl9; + lsm6dsv16bx_ctrl10_t ctrl10; + lsm6dsv16bx_fifo_status1_t fifo_status1; + lsm6dsv16bx_fifo_status2_t fifo_status2; + lsm6dsv16bx_all_int_src_t all_int_src; + lsm6dsv16bx_status_reg_t status_reg; + lsm6dsv16bx_out_temp_l_t out_temp_l; + lsm6dsv16bx_out_temp_h_t out_temp_h; + lsm6dsv16bx_outx_l_g_t outx_l_g; + lsm6dsv16bx_outx_h_g_t outx_h_g; + lsm6dsv16bx_outy_l_g_t outy_l_g; + lsm6dsv16bx_outy_h_g_t outy_h_g; + lsm6dsv16bx_outz_l_g_t outz_l_g; + lsm6dsv16bx_outz_h_g_t outz_h_g; + lsm6dsv16bx_outz_l_a_t outz_l_a; + lsm6dsv16bx_outz_h_a_t outz_h_a; + lsm6dsv16bx_outy_l_a_t outy_l_a; + lsm6dsv16bx_outy_h_a_t outy_h_a; + lsm6dsv16bx_outx_l_a_t outx_l_a; + lsm6dsv16bx_outx_h_a_t outx_h_a; + lsm6dsv16bx_ui_outz_l_a_ois_dualc_t ui_outz_l_a_ois_dualc; + lsm6dsv16bx_ui_outz_h_a_ois_dualc_t ui_outz_h_a_ois_dualc; + lsm6dsv16bx_ui_outy_l_a_ois_dualc_t ui_outy_l_a_ois_dualc; + lsm6dsv16bx_ui_outy_h_a_ois_dualc_t ui_outy_h_a_ois_dualc; + lsm6dsv16bx_ui_outx_l_a_ois_dualc_t ui_outx_l_a_ois_dualc; + lsm6dsv16bx_ui_outx_h_a_ois_dualc_t ui_outx_h_a_ois_dualc; + lsm6dsv16bx_ah_qvar_out_l_t ah_qvar_out_l; + lsm6dsv16bx_ah_qvar_out_h_t ah_qvar_out_h; + lsm6dsv16bx_timestamp0_t timestamp0; + lsm6dsv16bx_timestamp1_t timestamp1; + lsm6dsv16bx_timestamp2_t timestamp2; + lsm6dsv16bx_timestamp3_t timestamp3; + lsm6dsv16bx_wake_up_src_t wake_up_src; + lsm6dsv16bx_tap_src_t tap_src; + lsm6dsv16bx_d6d_src_t d6d_src; + lsm6dsv16bx_emb_func_status_mainpage_t emb_func_status_mainpage; + lsm6dsv16bx_fsm_status_mainpage_t fsm_status_mainpage; + lsm6dsv16bx_mlc_status_mainpage_t mlc_status_mainpage; + lsm6dsv16bx_internal_freq_t internal_freq; + lsm6dsv16bx_functions_enable_t functions_enable; + lsm6dsv16bx_inactivity_dur_t inactivity_dur; + lsm6dsv16bx_inactivity_ths_t inactivity_ths; + lsm6dsv16bx_tap_cfg0_t tap_cfg0; + lsm6dsv16bx_tap_cfg1_t tap_cfg1; + lsm6dsv16bx_tap_cfg2_t tap_cfg2; + lsm6dsv16bx_tap_ths_6d_t tap_ths_6d; + lsm6dsv16bx_tap_dur_t int_dur2; + lsm6dsv16bx_wake_up_ths_t wake_up_ths; + lsm6dsv16bx_wake_up_dur_t wake_up_dur; + lsm6dsv16bx_free_fall_t free_fall; + lsm6dsv16bx_md1_cfg_t md1_cfg; + lsm6dsv16bx_md2_cfg_t md2_cfg; + lsm6dsv16bx_emb_func_cfg_t emb_func_cfg; + lsm6dsv16bx_tdm_cfg0_t tdm_cfg0; + lsm6dsv16bx_tdm_cfg1_t tdm_cfg1; + lsm6dsv16bx_tdm_cfg2_t tdm_cfg2; + lsm6dsv16bx_ui_int_ois_t ui_int_ois; + lsm6dsv16bx_z_ofs_usr_t z_ofs_usr; + lsm6dsv16bx_y_ofs_usr_t y_ofs_usr; + lsm6dsv16bx_x_ofs_usr_t x_ofs_usr; + lsm6dsv16bx_fifo_data_out_tag_t fifo_data_out_tag; + lsm6dsv16bx_fifo_data_out_byte_0_t fifo_data_out_byte_0; + lsm6dsv16bx_fifo_data_out_byte_1_t fifo_data_out_byte_1; + lsm6dsv16bx_fifo_data_out_byte_2_t fifo_data_out_byte_2; + lsm6dsv16bx_fifo_data_out_byte_3_t fifo_data_out_byte_3; + lsm6dsv16bx_fifo_data_out_byte_4_t fifo_data_out_byte_4; + lsm6dsv16bx_fifo_data_out_byte_5_t fifo_data_out_byte_5; + lsm6dsv16bx_page_sel_t page_sel; + lsm6dsv16bx_emb_func_en_a_t emb_func_en_a; + lsm6dsv16bx_emb_func_en_b_t emb_func_en_b; + lsm6dsv16bx_emb_func_exec_status_t emb_func_exec_status; + lsm6dsv16bx_page_address_t page_address; + lsm6dsv16bx_page_value_t page_value; + lsm6dsv16bx_emb_func_int1_t emb_func_int1; + lsm6dsv16bx_fsm_int1_t fsm_int1; + lsm6dsv16bx_mlc_int1_t mlc_int1; + lsm6dsv16bx_emb_func_int2_t emb_func_int2; + lsm6dsv16bx_fsm_int2_t fsm_int2; + lsm6dsv16bx_mlc_int2_t mlc_int2; + lsm6dsv16bx_emb_func_status_t emb_func_status; + lsm6dsv16bx_fsm_status_t fsm_status; + lsm6dsv16bx_mlc_status_t mlc_status; + lsm6dsv16bx_page_rw_t page_rw; + lsm6dsv16bx_emb_func_fifo_en_a_t emb_func_fifo_en_a; + lsm6dsv16bx_emb_func_fifo_en_b_t emb_func_fifo_en_b; + lsm6dsv16bx_fsm_enable_t fsm_enable; + lsm6dsv16bx_fsm_long_counter_l_t fsm_long_counter_l; + lsm6dsv16bx_fsm_long_counter_h_t fsm_long_counter_h; + lsm6dsv16bx_fsm_outs1_t fsm_outs1; + lsm6dsv16bx_fsm_outs2_t fsm_outs2; + lsm6dsv16bx_fsm_outs3_t fsm_outs3; + lsm6dsv16bx_fsm_outs4_t fsm_outs4; + lsm6dsv16bx_fsm_outs5_t fsm_outs5; + lsm6dsv16bx_fsm_outs6_t fsm_outs6; + lsm6dsv16bx_fsm_outs7_t fsm_outs7; + lsm6dsv16bx_fsm_outs8_t fsm_outs8; + lsm6dsv16bx_fsm_odr_t fsm_odr; + lsm6dsv16bx_mlc_odr_t mlc_odr; + lsm6dsv16bx_step_counter_l_t step_counter_l; + lsm6dsv16bx_step_counter_h_t step_counter_h; + lsm6dsv16bx_emb_func_src_t emb_func_src; + lsm6dsv16bx_emb_func_init_a_t emb_func_init_a; + lsm6dsv16bx_emb_func_init_b_t emb_func_init_b; + lsm6dsv16bx_mlc1_src_t mlc1_src; + lsm6dsv16bx_mlc2_src_t mlc2_src; + lsm6dsv16bx_mlc3_src_t mlc3_src; + lsm6dsv16bx_mlc4_src_t mlc4_src; + lsm6dsv16bx_fsm_qvar_sensitivity_l_t fsm_qvar_sensitivity_l; + lsm6dsv16bx_fsm_qvar_sensitivity_h_t fsm_qvar_sensitivity_h; + lsm6dsv16bx_fsm_lc_timeout_l_t fsm_lc_timeout_l; + lsm6dsv16bx_fsm_lc_timeout_h_t fsm_lc_timeout_h; + lsm6dsv16bx_fsm_programs_t fsm_programs; + lsm6dsv16bx_fsm_start_add_l_t fsm_start_add_l; + lsm6dsv16bx_fsm_start_add_h_t fsm_start_add_h; + lsm6dsv16bx_pedo_cmd_reg_t pedo_cmd_reg; + lsm6dsv16bx_pedo_deb_steps_conf_t pedo_deb_steps_conf; + lsm6dsv16bx_pedo_sc_deltat_l_t pedo_sc_deltat_l; + lsm6dsv16bx_pedo_sc_deltat_h_t pedo_sc_deltat_h; + lsm6dsv16bx_mlc_qvar_sensitivity_l_t mlc_qvar_sensitivity_l; + lsm6dsv16bx_mlc_qvar_sensitivity_h_t mlc_qvar_sensitivity_h; + bitwise_t bitwise; + uint8_t byte; +} lsm6dsv16bx_reg_t; + + +/** + * @} + * + */ + +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + +int32_t lsm6dsv16bx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); +int32_t lsm6dsv16bx_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); + +float_t lsm6dsv16bx_from_sflp_to_mg(int16_t lsb); +float_t lsm6dsv16bx_from_fs2_to_mg(int16_t lsb); +float_t lsm6dsv16bx_from_fs4_to_mg(int16_t lsb); +float_t lsm6dsv16bx_from_fs8_to_mg(int16_t lsb); +float_t lsm6dsv16bx_from_fs16_to_mg(int16_t lsb); + +float_t lsm6dsv16bx_from_fs125_to_mdps(int16_t lsb); +float_t lsm6dsv16bx_from_fs500_to_mdps(int16_t lsb); +float_t lsm6dsv16bx_from_fs250_to_mdps(int16_t lsb); +float_t lsm6dsv16bx_from_fs1000_to_mdps(int16_t lsb); +float_t lsm6dsv16bx_from_fs2000_to_mdps(int16_t lsb); +float_t lsm6dsv16bx_from_fs4000_to_mdps(int16_t lsb); + +float_t lsm6dsv16bx_from_lsb_to_celsius(int16_t lsb); + +uint64_t lsm6dsv16bx_from_lsb_to_nsec(uint32_t lsb); + +typedef enum +{ + LSM6DSV16BX_READY = 0x0, + LSM6DSV16BX_GLOBAL_RST = 0x1, + LSM6DSV16BX_RESTORE_CAL_PARAM = 0x2, + LSM6DSV16BX_RESTORE_CTRL_REGS = 0x4, +} lsm6dsv16bx_reset_t; +int32_t lsm6dsv16bx_reset_set(stmdev_ctx_t *ctx, lsm6dsv16bx_reset_t val); +int32_t lsm6dsv16bx_reset_get(stmdev_ctx_t *ctx, lsm6dsv16bx_reset_t *val); + +typedef enum +{ + LSM6DSV16BX_MAIN_MEM_BANK = 0x0, + LSM6DSV16BX_EMBED_FUNC_MEM_BANK = 0x1, +} lsm6dsv16bx_mem_bank_t; +int32_t lsm6dsv16bx_mem_bank_set(stmdev_ctx_t *ctx, lsm6dsv16bx_mem_bank_t val); +int32_t lsm6dsv16bx_mem_bank_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_mem_bank_t *val); + +int32_t lsm6dsv16bx_device_id_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16BX_XL_ODR_OFF = 0x0, + LSM6DSV16BX_XL_ODR_AT_1Hz875 = 0x1, + LSM6DSV16BX_XL_ODR_AT_7Hz5 = 0x2, + LSM6DSV16BX_XL_ODR_AT_15Hz = 0x3, + LSM6DSV16BX_XL_ODR_AT_30Hz = 0x4, + LSM6DSV16BX_XL_ODR_AT_60Hz = 0x5, + LSM6DSV16BX_XL_ODR_AT_120Hz = 0x6, + LSM6DSV16BX_XL_ODR_AT_240Hz = 0x7, + LSM6DSV16BX_XL_ODR_AT_480Hz = 0x8, + LSM6DSV16BX_XL_ODR_AT_960Hz = 0x9, + LSM6DSV16BX_XL_ODR_AT_1920Hz = 0xA, + LSM6DSV16BX_XL_ODR_AT_3840Hz = 0xB, + LSM6DSV16BX_XL_ODR_AT_7680Hz = 0xC, +} lsm6dsv16bx_xl_data_rate_t; +int32_t lsm6dsv16bx_xl_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_xl_data_rate_t val); +int32_t lsm6dsv16bx_xl_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_xl_data_rate_t *val); + +typedef enum +{ + LSM6DSV16BX_XL_HIGH_PERFORMANCE_MD = 0x0, + LSM6DSV16BX_XL_HIGH_ACCURANCY_ODR_MD = 0x1, + LSM6DSV16BX_XL_LOW_POWER_2_AVG_MD = 0x4, + LSM6DSV16BX_XL_LOW_POWER_4_AVG_MD = 0x5, + LSM6DSV16BX_XL_LOW_POWER_8_AVG_MD = 0x6, + LSM6DSV16BX_XL_NORMAL_MD = 0x7, +} lsm6dsv16bx_xl_mode_t; +int32_t lsm6dsv16bx_xl_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_xl_mode_t val); +int32_t lsm6dsv16bx_xl_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_xl_mode_t *val); + +typedef enum +{ + LSM6DSV16BX_GY_ODR_OFF = 0x0, + LSM6DSV16BX_GY_ODR_AT_7Hz5 = 0x2, + LSM6DSV16BX_GY_ODR_AT_15Hz = 0x3, + LSM6DSV16BX_GY_ODR_AT_30Hz = 0x4, + LSM6DSV16BX_GY_ODR_AT_60Hz = 0x5, + LSM6DSV16BX_GY_ODR_AT_120Hz = 0x6, + LSM6DSV16BX_GY_ODR_AT_240Hz = 0x7, + LSM6DSV16BX_GY_ODR_AT_480Hz = 0x8, + LSM6DSV16BX_GY_ODR_AT_960Hz = 0x9, + LSM6DSV16BX_GY_ODR_AT_1920Hz = 0xa, + LSM6DSV16BX_GY_ODR_AT_3840Hz = 0xb, + LSM6DSV16BX_GY_ODR_AT_7680Hz = 0xc, +} lsm6dsv16bx_gy_data_rate_t; +int32_t lsm6dsv16bx_gy_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_gy_data_rate_t val); +int32_t lsm6dsv16bx_gy_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_gy_data_rate_t *val); + +typedef enum +{ + LSM6DSV16BX_GY_HIGH_PERFORMANCE_MD = 0x0, + LSM6DSV16BX_GY_HIGH_ACCURANCY_ODR_MD = 0x1, + LSM6DSV16BX_GY_SLEEP_MD = 0x4, + LSM6DSV16BX_GY_LOW_POWER_MD = 0x5, +} lsm6dsv16bx_gy_mode_t; +int32_t lsm6dsv16bx_gy_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_gy_mode_t val); +int32_t lsm6dsv16bx_gy_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_gy_mode_t *val); + +int32_t lsm6dsv16bx_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16bx_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16BX_DRDY_LATCHED = 0x0, + LSM6DSV16BX_DRDY_PULSED = 0x1, +} lsm6dsv16bx_data_ready_mode_t; +int32_t lsm6dsv16bx_data_ready_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_data_ready_mode_t val); +int32_t lsm6dsv16bx_data_ready_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_data_ready_mode_t *val); + +typedef enum +{ + LSM6DSV16BX_125dps = 0x0, + LSM6DSV16BX_250dps = 0x1, + LSM6DSV16BX_500dps = 0x2, + LSM6DSV16BX_1000dps = 0x3, + LSM6DSV16BX_2000dps = 0x4, + LSM6DSV16BX_4000dps = 0x5, +} lsm6dsv16bx_gy_full_scale_t; +int32_t lsm6dsv16bx_gy_full_scale_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_gy_full_scale_t val); +int32_t lsm6dsv16bx_gy_full_scale_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_gy_full_scale_t *val); + +typedef enum +{ + LSM6DSV16BX_2g = 0x0, + LSM6DSV16BX_4g = 0x1, + LSM6DSV16BX_8g = 0x2, + LSM6DSV16BX_16g = 0x3, +} lsm6dsv16bx_xl_full_scale_t; +int32_t lsm6dsv16bx_xl_full_scale_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_xl_full_scale_t val); +int32_t lsm6dsv16bx_xl_full_scale_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_xl_full_scale_t *val); + +int32_t lsm6dsv16bx_xl_dual_channel_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_xl_dual_channel_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16BX_XL_ST_DISABLE = 0x0, + LSM6DSV16BX_XL_ST_POSITIVE = 0x1, + LSM6DSV16BX_XL_ST_NEGATIVE = 0x2, + LSM6DSV16BX_XL_ST_OFFSET_POS = 0x5, + LSM6DSV16BX_XL_ST_OFFSET_NEG = 0x6, +} lsm6dsv16bx_xl_self_test_t; +int32_t lsm6dsv16bx_xl_self_test_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_xl_self_test_t val); +int32_t lsm6dsv16bx_xl_self_test_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_xl_self_test_t *val); + +typedef enum +{ + LSM6DSV16BX_GY_ST_DISABLE = 0x0, + LSM6DSV16BX_GY_ST_POSITIVE = 0x1, + LSM6DSV16BX_GY_ST_NEGATIVE = 0x2, +} lsm6dsv16bx_gy_self_test_t; +int32_t lsm6dsv16bx_gy_self_test_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_gy_self_test_t val); +int32_t lsm6dsv16bx_gy_self_test_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_gy_self_test_t *val); + +typedef struct +{ + uint8_t drdy_xl : 1; + uint8_t drdy_gy : 1; + uint8_t drdy_temp : 1; + uint8_t drdy_ah_qvar : 1; + uint8_t gy_settling : 1; + uint8_t den_flag : 1; + uint8_t timestamp : 1; + uint8_t free_fall : 1; + uint8_t wake_up : 1; + uint8_t wake_up_z : 1; + uint8_t wake_up_y : 1; + uint8_t wake_up_x : 1; + uint8_t single_tap : 1; + uint8_t double_tap : 1; + uint8_t tap_z : 1; + uint8_t tap_y : 1; + uint8_t tap_x : 1; + uint8_t tap_sign : 1; + uint8_t six_d : 1; + uint8_t six_d_xl : 1; + uint8_t six_d_xh : 1; + uint8_t six_d_yl : 1; + uint8_t six_d_yh : 1; + uint8_t six_d_zl : 1; + uint8_t six_d_zh : 1; + uint8_t sleep_change : 1; + uint8_t sleep_state : 1; + uint8_t step_detector : 1; + uint8_t step_count_inc : 1; + uint8_t step_count_overflow : 1; + uint8_t step_on_delta_time : 1; + uint8_t emb_func_stand_by : 1; + uint8_t emb_func_time_exceed: 1; + uint8_t tilt : 1; + uint8_t sig_mot : 1; + uint8_t fsm_lc : 1; + uint8_t fsm1 : 1; + uint8_t fsm2 : 1; + uint8_t fsm3 : 1; + uint8_t fsm4 : 1; + uint8_t fsm5 : 1; + uint8_t fsm6 : 1; + uint8_t fsm7 : 1; + uint8_t fsm8 : 1; + uint8_t mlc1 : 1; + uint8_t mlc2 : 1; + uint8_t mlc3 : 1; + uint8_t mlc4 : 1; + uint8_t fifo_bdr : 1; + uint8_t fifo_full : 1; + uint8_t fifo_ovr : 1; + uint8_t fifo_th : 1; +} lsm6dsv16bx_all_sources_t; +int32_t lsm6dsv16bx_all_sources_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_all_sources_t *val); + +typedef struct +{ + uint8_t drdy_xl : 1; + uint8_t drdy_gy : 1; + uint8_t drdy_temp : 1; +} lsm6dsv16bx_data_ready_t; +int32_t lsm6dsv16bx_flag_data_ready_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_data_ready_t *val); + +int32_t lsm6dsv16bx_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); + +int32_t lsm6dsv16bx_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val); + +int32_t lsm6dsv16bx_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); + +int32_t lsm6dsv16bx_dual_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); + +int32_t lsm6dsv16bx_ois_dual_acceleration_raw_get(stmdev_ctx_t *ctx, + int16_t *val); + +int32_t lsm6dsv16bx_ah_qvar_raw_get(stmdev_ctx_t *ctx, int16_t *val); + +int32_t lsm6dsv16bx_odr_cal_reg_get(stmdev_ctx_t *ctx, int8_t *val); + +typedef struct +{ + uint8_t x : 1; + uint8_t y : 1; + uint8_t z : 1; +} lsm6dsv16bx_xl_axis_t; +int32_t lsm6dsv16bx_xl_axis_set(stmdev_ctx_t *ctx, lsm6dsv16bx_xl_axis_t val); +int32_t lsm6dsv16bx_xl_axis_get(stmdev_ctx_t *ctx, lsm6dsv16bx_xl_axis_t *val); + +int32_t lsm6dsv16bx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, + uint8_t *buf, uint8_t len); +int32_t lsm6dsv16bx_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, + uint8_t *buf, uint8_t len); + +int32_t lsm6dsv16bx_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16bx_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); + +typedef enum +{ + LSM6DSV16BX_AUTO = 0x0, + LSM6DSV16BX_ALWAYS_ACTIVE = 0x1, +} lsm6dsv16bx_filt_anti_spike_t; +int32_t lsm6dsv16bx_filt_anti_spike_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_anti_spike_t val); +int32_t lsm6dsv16bx_filt_anti_spike_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_anti_spike_t *val); + +typedef struct +{ + uint8_t drdy : 1; + uint8_t irq_xl : 1; + uint8_t irq_g : 1; + uint8_t tdm_excep_code : 1; +} lsm6dsv16bx_filt_settling_mask_t; +int32_t lsm6dsv16bx_filt_settling_mask_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_settling_mask_t val); +int32_t lsm6dsv16bx_filt_settling_mask_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_settling_mask_t *val); + +typedef enum +{ + LSM6DSV16BX_GY_ULTRA_LIGHT = 0x0, + LSM6DSV16BX_GY_VERY_LIGHT = 0x1, + LSM6DSV16BX_GY_LIGHT = 0x2, + LSM6DSV16BX_GY_MEDIUM = 0x3, + LSM6DSV16BX_GY_STRONG = 0x4, + LSM6DSV16BX_GY_VERY_STRONG = 0x5, + LSM6DSV16BX_GY_AGGRESSIVE = 0x6, + LSM6DSV16BX_GY_XTREME = 0x7, +} lsm6dsv16bx_filt_gy_lp1_bandwidth_t; +int32_t lsm6dsv16bx_filt_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_gy_lp1_bandwidth_t val); +int32_t lsm6dsv16bx_filt_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_gy_lp1_bandwidth_t *val); + +int32_t lsm6dsv16bx_filt_gy_lp1_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_filt_gy_lp1_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t hpf : 1; + uint8_t lpf : 1; +} lsm6dsv16bx_filt_ah_qvar_conf_t; +int32_t lsm6dsv16bx_filt_ah_qvar_conf_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_ah_qvar_conf_t val); +int32_t lsm6dsv16bx_filt_ah_qvar_conf_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_ah_qvar_conf_t *val); + +typedef enum +{ + LSM6DSV16BX_XL_ULTRA_LIGHT = 0x0, + LSM6DSV16BX_XL_VERY_LIGHT = 0x1, + LSM6DSV16BX_XL_LIGHT = 0x2, + LSM6DSV16BX_XL_MEDIUM = 0x3, + LSM6DSV16BX_XL_STRONG = 0x4, + LSM6DSV16BX_XL_VERY_STRONG = 0x5, + LSM6DSV16BX_XL_AGGRESSIVE = 0x6, + LSM6DSV16BX_XL_XTREME = 0x7, +} lsm6dsv16bx_filt_xl_lp2_bandwidth_t; +int32_t lsm6dsv16bx_filt_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_xl_lp2_bandwidth_t val); +int32_t lsm6dsv16bx_filt_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_xl_lp2_bandwidth_t *val); + +int32_t lsm6dsv16bx_filt_xl_lp2_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_filt_xl_lp2_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16bx_filt_xl_hp_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_filt_xl_hp_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16bx_filt_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_filt_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16BX_HP_MD_NORMAL = 0x0, + LSM6DSV16BX_HP_MD_REFERENCE = 0x1, +} lsm6dsv16bx_filt_xl_hp_mode_t; +int32_t lsm6dsv16bx_filt_xl_hp_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_xl_hp_mode_t val); +int32_t lsm6dsv16bx_filt_xl_hp_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_xl_hp_mode_t *val); + +typedef enum +{ + LSM6DSV16BX_WK_FEED_SLOPE = 0x0, + LSM6DSV16BX_WK_FEED_HIGH_PASS = 0x1, + LSM6DSV16BX_WK_FEED_LP_WITH_OFFSET = 0x2, +} lsm6dsv16bx_filt_wkup_act_feed_t; +int32_t lsm6dsv16bx_filt_wkup_act_feed_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_wkup_act_feed_t val); +int32_t lsm6dsv16bx_filt_wkup_act_feed_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_wkup_act_feed_t *val); + +int32_t lsm6dsv16bx_mask_trigger_xl_settl_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_mask_trigger_xl_settl_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16BX_SIXD_FEED_ODR_DIV_2 = 0x0, + LSM6DSV16BX_SIXD_FEED_LOW_PASS = 0x1, +} lsm6dsv16bx_filt_sixd_feed_t; +int32_t lsm6dsv16bx_filt_sixd_feed_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_sixd_feed_t val); +int32_t lsm6dsv16bx_filt_sixd_feed_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_filt_sixd_feed_t *val); + +int32_t lsm6dsv16bx_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16BX_I2C_I3C_ENABLE = 0x0, + LSM6DSV16BX_I2C_I3C_DISABLE = 0x1, +} lsm6dsv16bx_ui_i2c_i3c_mode_t; +int32_t lsm6dsv16bx_ui_i2c_i3c_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_ui_i2c_i3c_mode_t val); +int32_t lsm6dsv16bx_ui_i2c_i3c_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_ui_i2c_i3c_mode_t *val); + +typedef enum +{ + LSM6DSV16BX_SPI_4_WIRE = 0x0, + LSM6DSV16BX_SPI_3_WIRE = 0x1, +} lsm6dsv16bx_spi_mode_t; +int32_t lsm6dsv16bx_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_spi_mode_t val); +int32_t lsm6dsv16bx_spi_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_spi_mode_t *val); + +int32_t lsm6dsv16bx_ui_sda_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_ui_sda_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16BX_IBI_2us = 0x0, + LSM6DSV16BX_IBI_50us = 0x1, + LSM6DSV16BX_IBI_1ms = 0x2, + LSM6DSV16BX_IBI_25ms = 0x3, +} lsm6dsv16bx_i3c_ibi_time_t; +int32_t lsm6dsv16bx_i3c_ibi_time_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_i3c_ibi_time_t val); +int32_t lsm6dsv16bx_i3c_ibi_time_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_i3c_ibi_time_t *val); + +typedef enum +{ + LSM6DSV16BX_PUSH_PULL = 0x0, + LSM6DSV16BX_OPEN_DRAIN = 0x1, +} lsm6dsv16bx_int_pin_mode_t; +int32_t lsm6dsv16bx_int_pin_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_int_pin_mode_t val); +int32_t lsm6dsv16bx_int_pin_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_int_pin_mode_t *val); + +typedef enum +{ + LSM6DSV16BX_ACTIVE_HIGH = 0x0, + LSM6DSV16BX_ACTIVE_LOW = 0x1, +} lsm6dsv16bx_pin_polarity_t; +int32_t lsm6dsv16bx_pin_polarity_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_pin_polarity_t val); +int32_t lsm6dsv16bx_pin_polarity_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_pin_polarity_t *val); + +typedef struct +{ + uint8_t boot : 1; + uint8_t drdy_ois : 1; + uint8_t drdy_xl : 1; + uint8_t drdy_gy : 1; + uint8_t drdy_temp : 1; + uint8_t fifo_th : 1; + uint8_t fifo_ovr : 1; + uint8_t fifo_full : 1; + uint8_t fifo_bdr : 1; + uint8_t den_flag : 1; + uint8_t timestamp : 1; // impact on int2 signals + uint8_t six_d : 1; + uint8_t double_tap : 1; + uint8_t free_fall : 1; + uint8_t wake_up : 1; + uint8_t single_tap : 1; + uint8_t sleep_change : 1; + uint8_t sleep_status : 1; + uint8_t step_detector : 1; + uint8_t step_count_overflow : 1; + uint8_t tilt : 1; + uint8_t sig_mot : 1; + uint8_t emb_func_stand_by : 1; // impact on int2 signals + uint8_t fsm_lc : 1; + uint8_t fsm1 : 1; + uint8_t fsm2 : 1; + uint8_t fsm3 : 1; + uint8_t fsm4 : 1; + uint8_t fsm5 : 1; + uint8_t fsm6 : 1; + uint8_t fsm7 : 1; + uint8_t fsm8 : 1; + uint8_t mlc1 : 1; + uint8_t mlc2 : 1; + uint8_t mlc3 : 1; + uint8_t mlc4 : 1; +} lsm6dsv16bx_pin_int1_route_t; +int32_t lsm6dsv16bx_pin_int1_route_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_pin_int1_route_t val); +int32_t lsm6dsv16bx_pin_int1_route_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_pin_int1_route_t *val); + +typedef struct +{ + uint8_t boot : 1; + uint8_t drdy_ois : 1; + uint8_t drdy_xl : 1; + uint8_t drdy_gy : 1; + uint8_t drdy_temp : 1; + uint8_t fifo_th : 1; + uint8_t fifo_ovr : 1; + uint8_t fifo_full : 1; + uint8_t fifo_bdr : 1; + uint8_t den_flag : 1; + uint8_t timestamp : 1; // impact on int2 signals + uint8_t six_d : 1; + uint8_t double_tap : 1; + uint8_t free_fall : 1; + uint8_t wake_up : 1; + uint8_t single_tap : 1; + uint8_t sleep_change : 1; + uint8_t sleep_status : 1; + uint8_t step_detector : 1; + uint8_t step_count_overflow : 1; + uint8_t tilt : 1; + uint8_t sig_mot : 1; + uint8_t emb_func_stand_by : 1; // impact on int2 signals + uint8_t fsm_lc : 1; + uint8_t fsm1 : 1; + uint8_t fsm2 : 1; + uint8_t fsm3 : 1; + uint8_t fsm4 : 1; + uint8_t fsm5 : 1; + uint8_t fsm6 : 1; + uint8_t fsm7 : 1; + uint8_t fsm8 : 1; + uint8_t mlc1 : 1; + uint8_t mlc2 : 1; + uint8_t mlc3 : 1; + uint8_t mlc4 : 1; +} lsm6dsv16bx_pin_int2_route_t; +int32_t lsm6dsv16bx_pin_int2_route_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_pin_int2_route_t val); +int32_t lsm6dsv16bx_pin_int2_route_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_pin_int2_route_t *val); + +int32_t lsm6dsv16bx_pin_int_en_when_i2c_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_pin_int_en_when_i2c_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16BX_ALL_INT_PULSED = 0x0, + LSM6DSV16BX_BASE_LATCHED_EMB_PULSED = 0x1, + LSM6DSV16BX_BASE_PULSED_EMB_LATCHED = 0x2, + LSM6DSV16BX_ALL_INT_LATCHED = 0x3, +} lsm6dsv16bx_int_notification_t; +int32_t lsm6dsv16bx_int_notification_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_int_notification_t val); +int32_t lsm6dsv16bx_int_notification_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_int_notification_t *val); + +typedef enum +{ + LSM6DSV16BX_XL_AND_GY_NOT_AFFECTED = 0x0, + LSM6DSV16BX_XL_LOW_POWER_GY_NOT_AFFECTED = 0x1, + LSM6DSV16BX_XL_LOW_POWER_GY_SLEEP = 0x2, + LSM6DSV16BX_XL_LOW_POWER_GY_POWER_DOWN = 0x3, +} lsm6dsv16bx_act_mode_t; +int32_t lsm6dsv16bx_act_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_act_mode_t val); +int32_t lsm6dsv16bx_act_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_act_mode_t *val); + +typedef enum +{ + LSM6DSV16BX_SLEEP_TO_ACT_AT_1ST_SAMPLE = 0x0, + LSM6DSV16BX_SLEEP_TO_ACT_AT_2ND_SAMPLE = 0x1, + LSM6DSV16BX_SLEEP_TO_ACT_AT_3RD_SAMPLE = 0x2, + LSM6DSV16BX_SLEEP_TO_ACT_AT_4th_SAMPLE = 0x3, +} lsm6dsv16bx_act_from_sleep_to_act_dur_t; +int32_t lsm6dsv16bx_act_from_sleep_to_act_dur_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_act_from_sleep_to_act_dur_t val); +int32_t lsm6dsv16bx_act_from_sleep_to_act_dur_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_act_from_sleep_to_act_dur_t *val); + +typedef enum +{ + LSM6DSV16BX_1Hz875 = 0x0, + LSM6DSV16BX_15Hz = 0x1, + LSM6DSV16BX_30Hz = 0x2, + LSM6DSV16BX_60Hz = 0x3, +} lsm6dsv16bx_act_sleep_xl_odr_t; +int32_t lsm6dsv16bx_act_sleep_xl_odr_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_act_sleep_xl_odr_t val); +int32_t lsm6dsv16bx_act_sleep_xl_odr_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_act_sleep_xl_odr_t *val); + +typedef struct +{ + uint32_t wk_ths_mg; + uint32_t inact_ths_mg; +} lsm6dsv16bx_act_thresholds_t; +int32_t lsm6dsv16bx_act_thresholds_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_act_thresholds_t val); +int32_t lsm6dsv16bx_act_thresholds_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_act_thresholds_t *val); + +typedef struct +{ + uint8_t shock : 2; + uint8_t quiet : 4; +} lsm6dsv16bx_act_wkup_time_windows_t; +int32_t lsm6dsv16bx_act_wkup_time_windows_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_act_wkup_time_windows_t val); +int32_t lsm6dsv16bx_act_wkup_time_windows_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_act_wkup_time_windows_t *val); + +typedef struct +{ + uint8_t tap_x_en : 1; + uint8_t tap_y_en : 1; + uint8_t tap_z_en : 1; +} lsm6dsv16bx_tap_detection_t; +int32_t lsm6dsv16bx_tap_detection_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_tap_detection_t val); +int32_t lsm6dsv16bx_tap_detection_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_tap_detection_t *val); + +typedef struct +{ + uint8_t x : 1; + uint8_t y : 1; + uint8_t z : 1; +} lsm6dsv16bx_tap_thresholds_t; +int32_t lsm6dsv16bx_tap_thresholds_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_tap_thresholds_t val); +int32_t lsm6dsv16bx_tap_thresholds_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_tap_thresholds_t *val); + + +typedef enum +{ + LSM6DSV16BX_XYZ = 0x3, + LSM6DSV16BX_YXZ = 0x5, + LSM6DSV16BX_XZY = 0x6, + LSM6DSV16BX_ZYX = 0x0, + LSM6DSV16BX_YZX = 0x1, + LSM6DSV16BX_ZXY = 0x2, +} lsm6dsv16bx_tap_axis_priority_t; +int32_t lsm6dsv16bx_tap_axis_priority_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_tap_axis_priority_t val); +int32_t lsm6dsv16bx_tap_axis_priority_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_tap_axis_priority_t *val); + +typedef struct +{ + uint8_t shock : 1; + uint8_t quiet : 1; + uint8_t tap_gap : 1; +} lsm6dsv16bx_tap_time_windows_t; +int32_t lsm6dsv16bx_tap_time_windows_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_tap_time_windows_t val); +int32_t lsm6dsv16bx_tap_time_windows_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_tap_time_windows_t *val); + +typedef enum +{ + LSM6DSV16BX_ONLY_SINGLE = 0x0, + LSM6DSV16BX_BOTH_SINGLE_DOUBLE = 0x1, +} lsm6dsv16bx_tap_mode_t; +int32_t lsm6dsv16bx_tap_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_tap_mode_t val); +int32_t lsm6dsv16bx_tap_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_tap_mode_t *val); + +typedef enum +{ + LSM6DSV16BX_DEG_80 = 0x0, + LSM6DSV16BX_DEG_70 = 0x1, + LSM6DSV16BX_DEG_60 = 0x2, + LSM6DSV16BX_DEG_50 = 0x3, +} lsm6dsv16bx_6d_threshold_t; +int32_t lsm6dsv16bx_6d_threshold_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_6d_threshold_t val); +int32_t lsm6dsv16bx_6d_threshold_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_6d_threshold_t *val); + +int32_t lsm6dsv16bx_ff_time_windows_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_ff_time_windows_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16BX_156_mg = 0x0, + LSM6DSV16BX_219_mg = 0x1, + LSM6DSV16BX_250_mg = 0x2, + LSM6DSV16BX_312_mg = 0x3, + LSM6DSV16BX_344_mg = 0x4, + LSM6DSV16BX_406_mg = 0x5, + LSM6DSV16BX_469_mg = 0x6, + LSM6DSV16BX_500_mg = 0x7, +} lsm6dsv16bx_ff_thresholds_t; +int32_t lsm6dsv16bx_ff_thresholds_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_ff_thresholds_t val); +int32_t lsm6dsv16bx_ff_thresholds_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_ff_thresholds_t *val); + +int32_t lsm6dsv16bx_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16bx_fifo_xl_dual_fsm_batch_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_fifo_xl_dual_fsm_batch_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16BX_CMP_DISABLE = 0x0, + LSM6DSV16BX_CMP_8_TO_1 = 0x1, + LSM6DSV16BX_CMP_16_TO_1 = 0x2, + LSM6DSV16BX_CMP_32_TO_1 = 0x3, +} lsm6dsv16bx_fifo_compress_algo_t; +int32_t lsm6dsv16bx_fifo_compress_algo_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_compress_algo_t val); +int32_t lsm6dsv16bx_fifo_compress_algo_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_compress_algo_t *val); + +int32_t lsm6dsv16bx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, + uint8_t val); +int32_t lsm6dsv16bx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t lsm6dsv16bx_fifo_compress_algo_real_time_set(stmdev_ctx_t *ctx, + uint8_t val); +int32_t lsm6dsv16bx_fifo_compress_algo_real_time_get(stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t lsm6dsv16bx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16BX_XL_NOT_BATCHED = 0x0, + LSM6DSV16BX_XL_BATCHED_AT_1Hz875 = 0x1, + LSM6DSV16BX_XL_BATCHED_AT_7Hz5 = 0x2, + LSM6DSV16BX_XL_BATCHED_AT_15Hz = 0x3, + LSM6DSV16BX_XL_BATCHED_AT_30Hz = 0x4, + LSM6DSV16BX_XL_BATCHED_AT_60Hz = 0x5, + LSM6DSV16BX_XL_BATCHED_AT_120Hz = 0x6, + LSM6DSV16BX_XL_BATCHED_AT_240Hz = 0x7, + LSM6DSV16BX_XL_BATCHED_AT_480Hz = 0x8, + LSM6DSV16BX_XL_BATCHED_AT_960Hz = 0x9, + LSM6DSV16BX_XL_BATCHED_AT_1920Hz = 0xA, + LSM6DSV16BX_XL_BATCHED_AT_3840Hz = 0xB, + LSM6DSV16BX_XL_BATCHED_AT_7680Hz = 0xC, +} lsm6dsv16bx_fifo_xl_batch_t; +int32_t lsm6dsv16bx_fifo_xl_batch_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_xl_batch_t val); +int32_t lsm6dsv16bx_fifo_xl_batch_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_xl_batch_t *val); + +typedef enum +{ + LSM6DSV16BX_GY_NOT_BATCHED = 0x0, + LSM6DSV16BX_GY_BATCHED_AT_1Hz875 = 0x1, + LSM6DSV16BX_GY_BATCHED_AT_7Hz5 = 0x2, + LSM6DSV16BX_GY_BATCHED_AT_15Hz = 0x3, + LSM6DSV16BX_GY_BATCHED_AT_30Hz = 0x4, + LSM6DSV16BX_GY_BATCHED_AT_60Hz = 0x5, + LSM6DSV16BX_GY_BATCHED_AT_120Hz = 0x6, + LSM6DSV16BX_GY_BATCHED_AT_240Hz = 0x7, + LSM6DSV16BX_GY_BATCHED_AT_480Hz = 0x8, + LSM6DSV16BX_GY_BATCHED_AT_960Hz = 0x9, + LSM6DSV16BX_GY_BATCHED_AT_1920Hz = 0xa, + LSM6DSV16BX_GY_BATCHED_AT_3840Hz = 0xb, + LSM6DSV16BX_GY_BATCHED_AT_7680Hz = 0xc, +} lsm6dsv16bx_fifo_gy_batch_t; +int32_t lsm6dsv16bx_fifo_gy_batch_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_gy_batch_t val); +int32_t lsm6dsv16bx_fifo_gy_batch_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_gy_batch_t *val); + +typedef enum +{ + LSM6DSV16BX_BYPASS_MODE = 0x0, + LSM6DSV16BX_FIFO_MODE = 0x1, + LSM6DSV16BX_STREAM_WTM_TO_FULL_MODE = 0x2, + LSM6DSV16BX_STREAM_TO_FIFO_MODE = 0x3, + LSM6DSV16BX_BYPASS_TO_STREAM_MODE = 0x4, + LSM6DSV16BX_STREAM_MODE = 0x6, + LSM6DSV16BX_BYPASS_TO_FIFO_MODE = 0x7, +} lsm6dsv16bx_fifo_mode_t; +int32_t lsm6dsv16bx_fifo_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_mode_t val); +int32_t lsm6dsv16bx_fifo_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_mode_t *val); + +typedef enum +{ + LSM6DSV16BX_TEMP_NOT_BATCHED = 0x0, + LSM6DSV16BX_TEMP_BATCHED_AT_1Hz875 = 0x1, + LSM6DSV16BX_TEMP_BATCHED_AT_15Hz = 0x2, + LSM6DSV16BX_TEMP_BATCHED_AT_60Hz = 0x3, +} lsm6dsv16bx_fifo_temp_batch_t; +int32_t lsm6dsv16bx_fifo_temp_batch_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_temp_batch_t val); +int32_t lsm6dsv16bx_fifo_temp_batch_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_temp_batch_t *val); + +typedef enum +{ + LSM6DSV16BX_TMSTMP_NOT_BATCHED = 0x0, + LSM6DSV16BX_TMSTMP_DEC_1 = 0x1, + LSM6DSV16BX_TMSTMP_DEC_8 = 0x2, + LSM6DSV16BX_TMSTMP_DEC_32 = 0x3, +} lsm6dsv16bx_fifo_timestamp_batch_t; +int32_t lsm6dsv16bx_fifo_timestamp_batch_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_timestamp_batch_t val); +int32_t lsm6dsv16bx_fifo_timestamp_batch_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_timestamp_batch_t *val); + +int32_t lsm6dsv16bx_fifo_batch_counter_threshold_set(stmdev_ctx_t *ctx, + uint16_t val); +int32_t lsm6dsv16bx_fifo_batch_counter_threshold_get(stmdev_ctx_t *ctx, + uint16_t *val); + +int32_t lsm6dsv16bx_fifo_batch_ah_qvar_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_fifo_batch_ah_qvar_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16BX_XL_BATCH_EVENT = 0x0, + LSM6DSV16BX_GY_BATCH_EVENT = 0x1, + LSM6DSV16BX_GY_EIS_BATCH_EVENT = 0x2, +} lsm6dsv16bx_fifo_batch_cnt_event_t; +int32_t lsm6dsv16bx_fifo_batch_cnt_event_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_batch_cnt_event_t val); +int32_t lsm6dsv16bx_fifo_batch_cnt_event_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_batch_cnt_event_t *val); + +typedef struct +{ + uint8_t game_rotation : 1; + uint8_t gravity : 1; + uint8_t gbias : 1; +} lsm6dsv16bx_fifo_sflp_raw_t; +int32_t lsm6dsv16bx_fifo_sflp_batch_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_sflp_raw_t val); +int32_t lsm6dsv16bx_fifo_sflp_batch_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_sflp_raw_t *val); + +typedef struct +{ + uint16_t fifo_level : 9; + uint8_t fifo_bdr : 1; + uint8_t fifo_full : 1; + uint8_t fifo_ovr : 1; + uint8_t fifo_th : 1; +} lsm6dsv16bx_fifo_status_t; + +int32_t lsm6dsv16bx_fifo_status_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_status_t *val); + +typedef struct +{ + enum + { + LSM6DSV16BX_FIFO_EMPTY = 0x0, + LSM6DSV16BX_GY_NC_TAG = 0x1, + LSM6DSV16BX_XL_NC_TAG = 0x2, + LSM6DSV16BX_TEMPERATURE_TAG = 0x3, + LSM6DSV16BX_TIMESTAMP_TAG = 0x4, + LSM6DSV16BX_CFG_CHANGE_TAG = 0x5, + LSM6DSV16BX_XL_NC_T_2_TAG = 0x6, + LSM6DSV16BX_XL_NC_T_1_TAG = 0x7, + LSM6DSV16BX_XL_2XC_TAG = 0x8, + LSM6DSV16BX_XL_3XC_TAG = 0x9, + LSM6DSV16BX_GY_NC_T_2_TAG = 0xA, + LSM6DSV16BX_GY_NC_T_1_TAG = 0xB, + LSM6DSV16BX_GY_2XC_TAG = 0xC, + LSM6DSV16BX_GY_3XC_TAG = 0xD, + LSM6DSV16BX_STEP_COUNTER_TAG = 0x12, + LSM6DSV16BX_SFLP_GAME_ROTATION_VECTOR_TAG = 0x13, + LSM6DSV16BX_SFLP_GYROSCOPE_BIAS_TAG = 0x16, + LSM6DSV16BX_SFLP_GRAVITY_VECTOR_TAG = 0x17, + LSM6DSV16BX_MLC_RESULT_TAG = 0x1A, + LSM6DSV16BX_MLC_FILTER = 0x1B, + LSM6DSV16BX_MLC_FEATURE = 0x1C, + LSM6DSV16BX_XL_DUAL_CORE = 0x1D, + LSM6DSV16BX_AH_QVAR = 0x1F, + } tag; + uint8_t cnt; + uint8_t data[6]; +} lsm6dsv16bx_fifo_out_raw_t; +int32_t lsm6dsv16bx_fifo_out_raw_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_fifo_out_raw_t *val); + +int32_t lsm6dsv16bx_fifo_stpcnt_batch_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_fifo_stpcnt_batch_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16bx_fifo_mlc_batch_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_fifo_mlc_batch_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16bx_fifo_mlc_filt_batch_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_fifo_mlc_filt_batch_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t step_counter_enable : 1; + uint8_t false_step_rej : 1; +} lsm6dsv16bx_stpcnt_mode_t; +int32_t lsm6dsv16bx_stpcnt_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_stpcnt_mode_t val); +int32_t lsm6dsv16bx_stpcnt_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_stpcnt_mode_t *val); + +int32_t lsm6dsv16bx_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val); + +int32_t lsm6dsv16bx_stpcnt_rst_step_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_stpcnt_rst_step_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16bx_stpcnt_debounce_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_stpcnt_debounce_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16bx_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv16bx_stpcnt_period_get(stmdev_ctx_t *ctx, uint16_t *val); + +int32_t lsm6dsv16bx_sigmot_mode_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_sigmot_mode_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16bx_tilt_mode_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_tilt_mode_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16bx_sflp_game_rotation_set(stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv16bx_sflp_game_rotation_get(stmdev_ctx_t *ctx, uint16_t *val); + +typedef struct +{ + float_t gbias_x; /* dps */ + float_t gbias_y; /* dps */ + float_t gbias_z; /* dps */ +} lsm6dsv16bx_sflp_gbias_t; +int32_t lsm6dsv16bx_sflp_game_gbias_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_sflp_gbias_t *val); + +int32_t lsm6dsv16bx_sflp_configure(stmdev_ctx_t *ctx); + +typedef enum +{ + LSM6DSV16BX_SFLP_15Hz = 0x0, + LSM6DSV16BX_SFLP_30Hz = 0x1, + LSM6DSV16BX_SFLP_60Hz = 0x2, + LSM6DSV16BX_SFLP_120Hz = 0x3, + LSM6DSV16BX_SFLP_240Hz = 0x4, + LSM6DSV16BX_SFLP_480Hz = 0x5, +} lsm6dsv16bx_sflp_data_rate_t; +int32_t lsm6dsv16bx_sflp_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_sflp_data_rate_t val); +int32_t lsm6dsv16bx_sflp_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_sflp_data_rate_t *val); + +typedef enum +{ + LSM6DSV16BX_PROTECT_CTRL_REGS = 0x0, + LSM6DSV16BX_WRITE_CTRL_REG = 0x1, +} lsm6dsv16bx_fsm_permission_t; +int32_t lsm6dsv16bx_fsm_permission_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_fsm_permission_t val); +int32_t lsm6dsv16bx_fsm_permission_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_fsm_permission_t *val); +int32_t lsm6dsv16bx_fsm_permission_status(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16BX_STD_IF_CONTROL = 0x0, + LSM6DSV16BX_FSM_CONTROL = 0x1, +} lsm6dsv16bx_fsm_permission_status_t; +int32_t lsm6dsv16bx_fsm_permission_status_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_fsm_permission_status_t *val); + +typedef struct +{ + uint8_t fsm1_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm8_en : 1; +} lsm6dsv16bx_fsm_mode_t; +int32_t lsm6dsv16bx_fsm_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_mode_t val); +int32_t lsm6dsv16bx_fsm_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_fsm_mode_t *val); + +int32_t lsm6dsv16bx_fsm_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv16bx_fsm_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val); + +typedef struct +{ + uint8_t fsm_outs1; + uint8_t fsm_outs2; + uint8_t fsm_outs3; + uint8_t fsm_outs4; + uint8_t fsm_outs5; + uint8_t fsm_outs6; + uint8_t fsm_outs7; + uint8_t fsm_outs8; +} lsm6dsv16bx_fsm_out_t; +int32_t lsm6dsv16bx_fsm_out_get(stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_out_t *val); + +typedef enum +{ + LSM6DSV16BX_FSM_15Hz = 0x0, + LSM6DSV16BX_FSM_30Hz = 0x1, + LSM6DSV16BX_FSM_60Hz = 0x2, + LSM6DSV16BX_FSM_120Hz = 0x3, + LSM6DSV16BX_FSM_240Hz = 0x4, + LSM6DSV16BX_FSM_480Hz = 0x5, + LSM6DSV16BX_FSM_960Hz = 0x6, +} lsm6dsv16bx_fsm_data_rate_t; +int32_t lsm6dsv16bx_fsm_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_fsm_data_rate_t val); +int32_t lsm6dsv16bx_fsm_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_fsm_data_rate_t *val); + +int32_t lsm6dsv16bx_fsm_long_cnt_timeout_set(stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv16bx_fsm_long_cnt_timeout_get(stmdev_ctx_t *ctx, uint16_t *val); + +int32_t lsm6dsv16bx_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16bx_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv16bx_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val); + +typedef enum +{ + LSM6DSV16BX_MLC_OFF = 0x0, + LSM6DSV16BX_MLC_ON = 0x1, + LSM6DSV16BX_MLC_ON_BEFORE_FSM = 0x2, +} lsm6dsv16bx_mlc_mode_t; +int32_t lsm6dsv16bx_mlc_set(stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_mode_t val); +int32_t lsm6dsv16bx_mlc_get(stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_mode_t *val); + +typedef enum +{ + LSM6DSV16BX_MLC_15Hz = 0x0, + LSM6DSV16BX_MLC_30Hz = 0x1, + LSM6DSV16BX_MLC_60Hz = 0x2, + LSM6DSV16BX_MLC_120Hz = 0x3, + LSM6DSV16BX_MLC_240Hz = 0x4, + LSM6DSV16BX_MLC_480Hz = 0x5, + LSM6DSV16BX_MLC_960Hz = 0x6, +} lsm6dsv16bx_mlc_data_rate_t; +int32_t lsm6dsv16bx_mlc_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_mlc_data_rate_t val); +int32_t lsm6dsv16bx_mlc_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_mlc_data_rate_t *val); + +typedef struct +{ + uint8_t mlc1_src; + uint8_t mlc2_src; + uint8_t mlc3_src; + uint8_t mlc4_src; +} lsm6dsv16bx_mlc_out_t; +int32_t lsm6dsv16bx_mlc_out_get(stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_out_t *val); + +int32_t lsm6dsv16bx_mlc_qvar_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv16bx_mlc_qvar_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val); + +int32_t lsm6dsv16bx_xl_offset_on_out_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_xl_offset_on_out_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + float_t z_mg; + float_t y_mg; + float_t x_mg; +} lsm6dsv16bxxl_offset_mg_t; +int32_t lsm6dsv16bx_xl_offset_mg_set(stmdev_ctx_t *ctx, + lsm6dsv16bxxl_offset_mg_t val); +int32_t lsm6dsv16bx_xl_offset_mg_get(stmdev_ctx_t *ctx, + lsm6dsv16bxxl_offset_mg_t *val); + +typedef struct +{ + uint8_t ah_qvar1_en : 1; + uint8_t ah_qvar2_en : 1; + uint8_t swaps : 1; +} lsm6dsv16bx_ah_qvar_mode_t; +int32_t lsm6dsv16bx_ah_qvar_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_ah_qvar_mode_t val); +int32_t lsm6dsv16bx_ah_qvar_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_ah_qvar_mode_t *val); + +typedef enum +{ + LSM6DSV16BX_2400MOhm = 0x0, + LSM6DSV16BX_730MOhm = 0x1, + LSM6DSV16BX_300MOhm = 0x2, + LSM6DSV16BX_255MOhm = 0x3, +} lsm6dsv16bx_ah_qvar_zin_t; +int32_t lsm6dsv16bx_ah_qvar_zin_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_ah_qvar_zin_t val); +int32_t lsm6dsv16bx_ah_qvar_zin_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_ah_qvar_zin_t *val); + +int32_t lsm6dsv16bx_fsm_qvar_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv16bx_fsm_qvar_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val); + +typedef enum +{ + LSM6DSV16BX_SW_RST_DYN_ADDRESS_RST = 0x0, + LSM6DSV16BX_I3C_GLOBAL_RST = 0x1, +} lsm6dsv16bx_i3c_reset_mode_t; +int32_t lsm6dsv16bx_i3c_reset_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_i3c_reset_mode_t val); +int32_t lsm6dsv16bx_i3c_reset_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_i3c_reset_mode_t *val); + +int32_t lsm6dsv16bx_tdm_dis_wclk_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_tdm_dis_wclk_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16bx_tdm_tdmout_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_tdm_tdmout_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16BX_WCLK_16kHZ_BCLK_2048kHz = 0x1, + LSM6DSV16BX_WCLK_8kHZ_BCLK_2048kHz = 0x4, +} lsm6dsv16bx_tdm_wclk_bclk_t; +int32_t lsm6dsv16bx_tdm_wclk_bclk_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_tdm_wclk_bclk_t val); +int32_t lsm6dsv16bx_tdm_wclk_bclk_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_tdm_wclk_bclk_t *val); + +typedef enum +{ + LSM6DSV16BX_SLOT_012 = 0x0, + LSM6DSV16BX_SLOT_456 = 0x1, +} lsm6dsv16bx_tdm_slot_t; +int32_t lsm6dsv16bx_tdm_slot_set(stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_slot_t val); +int32_t lsm6dsv16bx_tdm_slot_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_tdm_slot_t *val); + +typedef enum +{ + LSM6DSV16BX_BCLK_RISING = 0x0, + LSM6DSV16BX_BCLK_FALLING = 0x1, +} lsm6dsv16bx_tdm_bclk_edge_t; +int32_t lsm6dsv16bx_tdm_bclk_edge_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_tdm_bclk_edge_t val); +int32_t lsm6dsv16bx_tdm_bclk_edge_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_tdm_bclk_edge_t *val); + +int32_t lsm6dsv16bx_tdm_delayed_conf_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_tdm_delayed_conf_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16BX_TDM_ORDER_ZYX = 0x0, + LSM6DSV16BX_TDM_ORDER_XZY = 0x1, + LSM6DSV16BX_TDM_ORDER_XYZ = 0x2, +} lsm6dsv16bx_tdm_axis_order_t; +int32_t lsm6dsv16bx_tdm_axis_order_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_tdm_axis_order_t val); +int32_t lsm6dsv16bx_tdm_axis_order_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_tdm_axis_order_t *val); + +typedef enum +{ + LSM6DSV16BX_TDM_2g = 0x0, + LSM6DSV16BX_TDM_4g = 0x1, + LSM6DSV16BX_TDM_8g = 0x2, +} lsm6dsv16bx_tdm_xl_full_scale_t; +int32_t lsm6dsv16bx_tdm_xl_full_scale_set(stmdev_ctx_t *ctx, + lsm6dsv16bx_tdm_xl_full_scale_t val); +int32_t lsm6dsv16bx_tdm_xl_full_scale_get(stmdev_ctx_t *ctx, + lsm6dsv16bx_tdm_xl_full_scale_t *val); + +/** + * @} + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /*LSM6DSV16BX_DRIVER_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dsv16x_STdC/driver/lsm6dsv16x_reg.c b/sensor/stmemsc/lsm6dsv16x_STdC/driver/lsm6dsv16x_reg.c new file mode 100644 index 0000000000000000000000000000000000000000..a84610f9137610f82b8c53481264fe894d9cb980 --- /dev/null +++ b/sensor/stmemsc/lsm6dsv16x_STdC/driver/lsm6dsv16x_reg.c @@ -0,0 +1,10128 @@ +/** + ****************************************************************************** + * @file lsm6dsv16x_reg.c + * @author Sensors Software Solution Team + * @brief LSM6DSV16X driver file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2022 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "lsm6dsv16x_reg.h" + +/** + * @defgroup LSM6DSV16X + * @brief This file provides a set of functions needed to drive the + * lsm6dsv16x enhanced inertial module. + * @{ + * + */ + +/** + * @defgroup Interfaces functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +/** + * @brief Read generic device register + * + * @param ctx communication interface handler.(ptr) + * @param reg first register address to read. + * @param data buffer for data read.(ptr) + * @param len number of consecutive register to read. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak lsm6dsv16x_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) +{ + int32_t ret; + + ret = ctx->read_reg(ctx->handle, reg, data, len); + + return ret; +} + +/** + * @brief Write generic device register + * + * @param ctx communication interface handler.(ptr) + * @param reg first register address to write. + * @param data the buffer contains data to be written.(ptr) + * @param len number of consecutive register to write. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak lsm6dsv16x_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) +{ + int32_t ret; + + ret = ctx->write_reg(ctx->handle, reg, data, len); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Private functions + * @brief Section collect all the utility functions needed by APIs. + * @{ + * + */ + +static void bytecpy(uint8_t *target, uint8_t *source) +{ + if ((target != NULL) && (source != NULL)) + { + *target = *source; + } +} + +/** + * @} + * + */ + +/** + * @defgroup Sensitivity + * @brief These functions convert raw-data into engineering units. + * @{ + * + */ +float_t lsm6dsv16x_from_sflp_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.061f; +} + +float_t lsm6dsv16x_from_fs2_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.061f; +} + +float_t lsm6dsv16x_from_fs4_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.122f; +} + +float_t lsm6dsv16x_from_fs8_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.244f; +} + +float_t lsm6dsv16x_from_fs16_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.488f; +} + +float_t lsm6dsv16x_from_fs125_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 4.375f; +} + +float_t lsm6dsv16x_from_fs250_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 8.750f; +} + +float_t lsm6dsv16x_from_fs500_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 17.50f; +} + +float_t lsm6dsv16x_from_fs1000_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 35.0f; +} + +float_t lsm6dsv16x_from_fs2000_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 70.0f; +} + +float_t lsm6dsv16x_from_fs4000_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 140.0f; +} + +float_t lsm6dsv16x_from_lsb_to_celsius(int16_t lsb) +{ + return (((float_t)lsb / 256.0f) + 25.0f); +} + +float_t lsm6dsv16x_from_lsb_to_nsec(uint32_t lsb) +{ + return ((float_t)lsb * 21750.0f); +} + +/** + * @} + * + */ + +/** + * @defgroup Accelerometer user offset correction + * @brief This section groups all the functions concerning the + * usage of Accelerometer user offset correction + * @{ + * + */ + +/** + * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[set] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_xl_offset_on_out_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.usr_off_on_out = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[get] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_xl_offset_on_out_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1); + *val = ctrl9.usr_off_on_out; + + return ret; +} + +/** + * @brief Accelerometer user offset correction values in mg.[set] + * + * @param ctx read / write interface definitions + * @param val Accelerometer user offset correction values in mg. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_xl_offset_mg_set(stmdev_ctx_t *ctx, + lsm6dsv16x_xl_offset_mg_t val) +{ + lsm6dsv16x_z_ofs_usr_t z_ofs_usr; + lsm6dsv16x_y_ofs_usr_t y_ofs_usr; + lsm6dsv16x_x_ofs_usr_t x_ofs_usr; + lsm6dsv16x_ctrl9_t ctrl9; + int32_t ret; + float_t tmp; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + } + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + } + + + if ((val.x_mg < (0.0078125f * 127.0f)) && (val.x_mg > (0.0078125f * -127.0f)) && + (val.y_mg < (0.0078125f * 127.0f)) && (val.y_mg > (0.0078125f * -127.0f)) && + (val.z_mg < (0.0078125f * 127.0f)) && (val.z_mg > (0.0078125f * -127.0f))) + { + ctrl9.usr_off_w = 0; + + tmp = val.z_mg / 0.0078125f; + z_ofs_usr.z_ofs_usr = (uint8_t)tmp; + + tmp = val.y_mg / 0.0078125f; + y_ofs_usr.y_ofs_usr = (uint8_t)tmp; + + tmp = val.x_mg / 0.0078125f; + x_ofs_usr.x_ofs_usr = (uint8_t)tmp; + } + else if ((val.x_mg < (0.125f * 127.0f)) && (val.x_mg > (0.125f * -127.0f)) && + (val.y_mg < (0.125f * 127.0f)) && (val.y_mg > (0.125f * -127.0f)) && + (val.z_mg < (0.125f * 127.0f)) && (val.z_mg > (0.125f * -127.0f))) + { + ctrl9.usr_off_w = 1; + + tmp = val.z_mg / 0.125f; + z_ofs_usr.z_ofs_usr = (uint8_t)tmp; + + tmp = val.y_mg / 0.125f; + y_ofs_usr.y_ofs_usr = (uint8_t)tmp; + + tmp = val.x_mg / 0.125f; + x_ofs_usr.x_ofs_usr = (uint8_t)tmp; + } + else // out of limit + { + ctrl9.usr_off_w = 1; + z_ofs_usr.z_ofs_usr = 0xFFU; + y_ofs_usr.y_ofs_usr = 0xFFU; + x_ofs_usr.x_ofs_usr = 0xFFU; + } + + if (ret == 0) + { + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + } + if (ret == 0) + { + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + } + if (ret == 0) + { + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + } + if (ret == 0) + { + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1); + } + return ret; +} + +/** + * @brief Accelerometer user offset correction values in mg.[get] + * + * @param ctx read / write interface definitions + * @param val Accelerometer user offset correction values in mg. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_xl_offset_mg_get(stmdev_ctx_t *ctx, + lsm6dsv16x_xl_offset_mg_t *val) +{ + lsm6dsv16x_z_ofs_usr_t z_ofs_usr; + lsm6dsv16x_y_ofs_usr_t y_ofs_usr; + lsm6dsv16x_x_ofs_usr_t x_ofs_usr; + lsm6dsv16x_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + } + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + } + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + } + + if (ctrl9.usr_off_w == PROPERTY_DISABLE) + { + val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.0078125f); + val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.0078125f); + val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.0078125f); + } + else + { + val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.125f); + val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.125f); + val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.125f); + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @brief Reset of the device.[set] + * + * @param ctx read / write interface definitions + * @param val Reset of the device. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_reset_set(stmdev_ctx_t *ctx, lsm6dsv16x_reset_t val) +{ + lsm6dsv16x_func_cfg_access_t func_cfg_access; + lsm6dsv16x_ctrl3_t ctrl3; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + ctrl3.boot = ((uint8_t)val & 0x04U) >> 2; + ctrl3.sw_reset = ((uint8_t)val & 0x02U) >> 1; + func_cfg_access.sw_por = (uint8_t)val & 0x01U; + + if (ret == 0) + { + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL3, (uint8_t *)&ctrl3, 1); + } + if (ret == 0) + { + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Global reset of the device.[get] + * + * @param ctx read / write interface definitions + * @param val Global reset of the device. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_reset_get(stmdev_ctx_t *ctx, lsm6dsv16x_reset_t *val) +{ + lsm6dsv16x_func_cfg_access_t func_cfg_access; + lsm6dsv16x_ctrl3_t ctrl3; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + switch ((ctrl3.sw_reset << 2) + (ctrl3.boot << 1) + func_cfg_access.sw_por) + { + case LSM6DSV16X_READY: + *val = LSM6DSV16X_READY; + break; + + case LSM6DSV16X_GLOBAL_RST: + *val = LSM6DSV16X_GLOBAL_RST; + break; + + case LSM6DSV16X_RESTORE_CAL_PARAM: + *val = LSM6DSV16X_RESTORE_CAL_PARAM; + break; + + case LSM6DSV16X_RESTORE_CTRL_REGS: + *val = LSM6DSV16X_RESTORE_CTRL_REGS; + break; + + default: + *val = LSM6DSV16X_GLOBAL_RST; + break; + } + return ret; +} + +/** + * @brief Change memory bank.[set] + * + * @param ctx read / write interface definitions + * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_mem_bank_set(stmdev_ctx_t *ctx, lsm6dsv16x_mem_bank_t val) +{ + lsm6dsv16x_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + if (ret == 0) + { + func_cfg_access.shub_reg_access = ((uint8_t)val & 0x02U) >> 1; + func_cfg_access.emb_func_reg_access = (uint8_t)val & 0x01U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Change memory bank.[get] + * + * @param ctx read / write interface definitions + * @param val MAIN_MEM_BANK, SENSOR_HUB_MEM_BANK, EMBED_FUNC_MEM_BANK, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_mem_bank_get(stmdev_ctx_t *ctx, lsm6dsv16x_mem_bank_t *val) +{ + lsm6dsv16x_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + switch ((func_cfg_access.shub_reg_access << 1) + func_cfg_access.emb_func_reg_access) + { + case LSM6DSV16X_MAIN_MEM_BANK: + *val = LSM6DSV16X_MAIN_MEM_BANK; + break; + + case LSM6DSV16X_EMBED_FUNC_MEM_BANK: + *val = LSM6DSV16X_EMBED_FUNC_MEM_BANK; + break; + + case LSM6DSV16X_SENSOR_HUB_MEM_BANK: + *val = LSM6DSV16X_SENSOR_HUB_MEM_BANK; + break; + + default: + *val = LSM6DSV16X_MAIN_MEM_BANK; + break; + } + return ret; +} + +/** + * @brief Device ID.[get] THis function works also for OIS + * (WHO_AM_I and SPI2_WHO_AM_I have same address) + * + * @param ctx read / write interface definitions + * @param val Device ID. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_device_id_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WHO_AM_I, val, 1); + + return ret; +} + +/** + * @brief Accelerometer output data rate (ODR) selection.[set] + * + * @param ctx read / write interface definitions + * @param val lsm6dsv16x_data_rate_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_xl_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv16x_data_rate_t val) +{ + lsm6dsv16x_ctrl1_t ctrl1; + lsm6dsv16x_haodr_cfg_t haodr; + uint8_t sel; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret == 0) + { + ctrl1.odr_xl = (uint8_t)val & 0x0Fu; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL1, (uint8_t *)&ctrl1, 1); + } + + sel = ((uint8_t)val >> 4) & 0xFU; + if (sel != 0U) + { + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_HAODR_CFG, (uint8_t *)&haodr, 1); + haodr.haodr_sel = sel; + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_HAODR_CFG, (uint8_t *)&haodr, 1); + } + + return ret; +} + +/** + * @brief Accelerometer output data rate (ODR) selection.[get] + * + * @param ctx read / write interface definitions + * @param val lsm6dsv16x_data_rate_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_xl_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv16x_data_rate_t *val) +{ + lsm6dsv16x_ctrl1_t ctrl1; + lsm6dsv16x_haodr_cfg_t haodr; + uint8_t sel; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL1, (uint8_t *)&ctrl1, 1); + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_HAODR_CFG, (uint8_t *)&haodr, 1); + sel = haodr.haodr_sel; + + switch (ctrl1.odr_xl) + { + case LSM6DSV16X_ODR_OFF: + *val = LSM6DSV16X_ODR_OFF; + break; + + case LSM6DSV16X_ODR_AT_1Hz875: + *val = LSM6DSV16X_ODR_AT_1Hz875; + break; + + case LSM6DSV16X_ODR_AT_7Hz5: + *val = LSM6DSV16X_ODR_AT_7Hz5; + break; + + case LSM6DSV16X_ODR_AT_15Hz: + switch (sel) { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_15Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_15Hz625; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_12Hz5; + break; + } + break; + + case LSM6DSV16X_ODR_AT_30Hz: + switch (sel) { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_30Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_31Hz25; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_25Hz; + break; + } + break; + + case LSM6DSV16X_ODR_AT_60Hz: + switch (sel) { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_60Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_62Hz5; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_50Hz; + break; + } + break; + + case LSM6DSV16X_ODR_AT_120Hz: + switch (sel) { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_120Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_125Hz; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_100Hz; + break; + } + break; + + case LSM6DSV16X_ODR_AT_240Hz: + switch (sel) { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_240Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_250Hz; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_200Hz; + break; + } + break; + + case LSM6DSV16X_ODR_AT_480Hz: + switch (sel) { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_480Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_500Hz; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_400Hz; + break; + } + break; + + case LSM6DSV16X_ODR_AT_960Hz: + switch (sel) { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_960Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_1000Hz; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_800Hz; + break; + } + break; + + case LSM6DSV16X_ODR_AT_1920Hz: + switch (sel) { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_1920Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_2000Hz; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_1600Hz; + break; + } + break; + + case LSM6DSV16X_ODR_AT_3840Hz: + switch (sel) { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_3840Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_4000Hz; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_3200Hz; + break; + } + break; + + case LSM6DSV16X_ODR_AT_7680Hz: + switch (sel) { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_7680Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_8000Hz; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_6400Hz; + break; + } + break; + + default: + *val = LSM6DSV16X_ODR_OFF; + break; + } + return ret; +} + +/** + * @brief Accelerometer operating mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val XL_HIGH_PERFORMANCE_MD, XL_HIGH_ACCURACY_ODR_MD, XL_LOW_POWER_2_AVG_MD, XL_LOW_POWER_4_AVG_MD, XL_LOW_POWER_8_AVG_MD, XL_NORMAL_MD, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_xl_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_xl_mode_t val) +{ + lsm6dsv16x_ctrl1_t ctrl1; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL1, (uint8_t *)&ctrl1, 1); + + if (ret == 0) + { + ctrl1.op_mode_xl = (uint8_t)val & 0x07U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL1, (uint8_t *)&ctrl1, 1); + } + + return ret; +} + +/** + * @brief Accelerometer operating mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val XL_HIGH_PERFORMANCE_MD, XL_HIGH_ACCURACY_ODR_MD, XL_LOW_POWER_2_AVG_MD, XL_LOW_POWER_4_AVG_MD, XL_LOW_POWER_8_AVG_MD, XL_NORMAL_MD, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_xl_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_xl_mode_t *val) +{ + lsm6dsv16x_ctrl1_t ctrl1; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL1, (uint8_t *)&ctrl1, 1); + + switch (ctrl1.op_mode_xl) + { + case LSM6DSV16X_XL_HIGH_PERFORMANCE_MD: + *val = LSM6DSV16X_XL_HIGH_PERFORMANCE_MD; + break; + + case LSM6DSV16X_XL_HIGH_ACCURACY_ODR_MD: + *val = LSM6DSV16X_XL_HIGH_ACCURACY_ODR_MD; + break; + + case LSM6DSV16X_XL_ODR_TRIGGERED_MD: + *val = LSM6DSV16X_XL_ODR_TRIGGERED_MD; + break; + + case LSM6DSV16X_XL_LOW_POWER_2_AVG_MD: + *val = LSM6DSV16X_XL_LOW_POWER_2_AVG_MD; + break; + + case LSM6DSV16X_XL_LOW_POWER_4_AVG_MD: + *val = LSM6DSV16X_XL_LOW_POWER_4_AVG_MD; + break; + + case LSM6DSV16X_XL_LOW_POWER_8_AVG_MD: + *val = LSM6DSV16X_XL_LOW_POWER_8_AVG_MD; + break; + + case LSM6DSV16X_XL_NORMAL_MD: + *val = LSM6DSV16X_XL_NORMAL_MD; + break; + + default: + *val = LSM6DSV16X_XL_HIGH_PERFORMANCE_MD; + break; + } + return ret; +} + +/** + * @brief Gyroscope output data rate (ODR) selection.[set] + * + * @param ctx read / write interface definitions + * @param val lsm6dsv16x_data_rate_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_gy_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv16x_data_rate_t val) +{ + lsm6dsv16x_ctrl2_t ctrl2; + lsm6dsv16x_haodr_cfg_t haodr; + uint8_t sel; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL2, (uint8_t *)&ctrl2, 1); + + if (ret == 0) + { + ctrl2.odr_g = (uint8_t)val & 0x0Fu; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL2, (uint8_t *)&ctrl2, 1); + } + + sel = ((uint8_t)val >> 4) & 0xFU; + if (sel != 0U) + { + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_HAODR_CFG, (uint8_t *)&haodr, 1); + haodr.haodr_sel = sel; + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_HAODR_CFG, (uint8_t *)&haodr, 1); + } + + return ret; +} + +/** + * @brief Gyroscope output data rate (ODR) selection.[get] + * + * @param ctx read / write interface definitions + * @param val lsm6dsv16x_data_rate_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_gy_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv16x_data_rate_t *val) +{ + lsm6dsv16x_ctrl2_t ctrl2; + lsm6dsv16x_haodr_cfg_t haodr; + uint8_t sel; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL2, (uint8_t *)&ctrl2, 1); + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_HAODR_CFG, (uint8_t *)&haodr, 1); + sel = haodr.haodr_sel; + + switch (ctrl2.odr_g) + { + case LSM6DSV16X_ODR_OFF: + *val = LSM6DSV16X_ODR_OFF; + break; + + case LSM6DSV16X_ODR_AT_1Hz875: + *val = LSM6DSV16X_ODR_AT_1Hz875; + break; + + case LSM6DSV16X_ODR_AT_7Hz5: + *val = LSM6DSV16X_ODR_AT_7Hz5; + break; + + case LSM6DSV16X_ODR_AT_15Hz: + switch (sel) { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_15Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_15Hz625; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_12Hz5; + break; + } + break; + + case LSM6DSV16X_ODR_AT_30Hz: + switch (sel) { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_30Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_31Hz25; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_25Hz; + break; + } + break; + + case LSM6DSV16X_ODR_AT_60Hz: + switch (sel) { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_60Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_62Hz5; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_50Hz; + break; + } + break; + + case LSM6DSV16X_ODR_AT_120Hz: + switch (sel) { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_120Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_125Hz; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_100Hz; + break; + } + break; + + case LSM6DSV16X_ODR_AT_240Hz: + switch (sel) { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_240Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_250Hz; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_200Hz; + break; + } + break; + + case LSM6DSV16X_ODR_AT_480Hz: + switch (sel) { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_480Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_500Hz; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_400Hz; + break; + } + break; + + case LSM6DSV16X_ODR_AT_960Hz: + switch (sel) { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_960Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_1000Hz; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_800Hz; + break; + } + break; + + case LSM6DSV16X_ODR_AT_1920Hz: + switch (sel) { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_1920Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_2000Hz; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_1600Hz; + break; + } + break; + + case LSM6DSV16X_ODR_AT_3840Hz: + switch (sel) { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_3840Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_4000Hz; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_3200Hz; + break; + } + break; + + case LSM6DSV16X_ODR_AT_7680Hz: + switch (sel) { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_7680Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_8000Hz; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_6400Hz; + break; + } + break; + + default: + *val = LSM6DSV16X_ODR_OFF; + break; + } + return ret; +} + +/** + * @brief Gyroscope operating mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val GY_HIGH_PERFORMANCE_MD, GY_HIGH_ACCURACY_ODR_MD, GY_SLEEP_MD, GY_LOW_POWER_MD, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_gy_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_gy_mode_t val) +{ + lsm6dsv16x_ctrl2_t ctrl2; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret == 0) + { + ctrl2.op_mode_g = (uint8_t)val & 0x07U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL2, (uint8_t *)&ctrl2, 1); + } + + return ret; +} + +/** + * @brief Gyroscope operating mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val GY_HIGH_PERFORMANCE_MD, GY_HIGH_ACCURACY_ODR_MD, GY_SLEEP_MD, GY_LOW_POWER_MD, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_gy_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_gy_mode_t *val) +{ + lsm6dsv16x_ctrl2_t ctrl2; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL2, (uint8_t *)&ctrl2, 1); + switch (ctrl2.op_mode_g) + { + case LSM6DSV16X_GY_HIGH_PERFORMANCE_MD: + *val = LSM6DSV16X_GY_HIGH_PERFORMANCE_MD; + break; + + case LSM6DSV16X_GY_HIGH_ACCURACY_ODR_MD: + *val = LSM6DSV16X_GY_HIGH_ACCURACY_ODR_MD; + break; + + case LSM6DSV16X_GY_SLEEP_MD: + *val = LSM6DSV16X_GY_SLEEP_MD; + break; + + case LSM6DSV16X_GY_LOW_POWER_MD: + *val = LSM6DSV16X_GY_LOW_POWER_MD; + break; + + default: + *val = LSM6DSV16X_GY_HIGH_PERFORMANCE_MD; + break; + } + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[set] + * + * @param ctx read / write interface definitions + * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_ctrl3_t ctrl3; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret == 0) + { + ctrl3.if_inc = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL3, (uint8_t *)&ctrl3, 1); + } + + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[get] + * + * @param ctx read / write interface definitions + * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_ctrl3_t ctrl3; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL3, (uint8_t *)&ctrl3, 1); + *val = ctrl3.if_inc; + + + return ret; +} + +/** + * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [set] + * + * @param ctx read / write interface definitions + * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_ctrl3_t ctrl3; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL3, (uint8_t *)&ctrl3, 1); + + if (ret == 0) + { + ctrl3.bdu = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL3, (uint8_t *)&ctrl3, 1); + } + + return ret; +} + +/** + * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [get] + * + * @param ctx read / write interface definitions + * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_ctrl3_t ctrl3; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL3, (uint8_t *)&ctrl3, 1); + *val = ctrl3.bdu; + + return ret; +} + +/** + * @brief Configure ODR trigger. [set] + * + * @param ctx read / write interface definitions + * @param val number of data in the reference period. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_odr_trig_cfg_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_odr_trig_cfg_t odr_trig; + int32_t ret; + + if (val >= 1U && val <= 3U) { + return -1; + } + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_ODR_TRIG_CFG, (uint8_t *)&odr_trig, 1); + + if (ret == 0) + { + odr_trig.odr_trig_nodr = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_ODR_TRIG_CFG, (uint8_t *)&odr_trig, 1); + } + + return ret; +} + +/** + * @brief Configure ODR trigger. [get] + * + * @param ctx read / write interface definitions + * @param val number of data in the reference period. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_odr_trig_cfg_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_odr_trig_cfg_t odr_trig; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_ODR_TRIG_CFG, (uint8_t *)&odr_trig, 1); + *val = odr_trig.odr_trig_nodr; + + return ret; +} + +/** + * @brief Enables pulsed data-ready mode (~75 us).[set] + * + * @param ctx read / write interface definitions + * @param val DRDY_LATCHED, DRDY_PULSED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_data_ready_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16x_data_ready_mode_t val) +{ + lsm6dsv16x_ctrl4_t ctrl4; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1); + + if (ret == 0) + { + ctrl4.drdy_pulsed = (uint8_t)val & 0x1U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1); + } + + return ret; +} + +/** + * @brief Enables pulsed data-ready mode (~75 us).[get] + * + * @param ctx read / write interface definitions + * @param val DRDY_LATCHED, DRDY_PULSED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_data_ready_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16x_data_ready_mode_t *val) +{ + lsm6dsv16x_ctrl4_t ctrl4; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1); + + switch (ctrl4.drdy_pulsed) + { + case LSM6DSV16X_DRDY_LATCHED: + *val = LSM6DSV16X_DRDY_LATCHED; + break; + + case LSM6DSV16X_DRDY_PULSED: + *val = LSM6DSV16X_DRDY_PULSED; + break; + + default: + *val = LSM6DSV16X_DRDY_LATCHED; + break; + } + return ret; +} + +/** + * @brief Enables interrupt.[set] + * + * @param ctx read / write interface definitions + * @param val enable/disable, latched/pulsed + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_interrupt_enable_set(stmdev_ctx_t *ctx, + lsm6dsv16x_interrupt_mode_t val) +{ + lsm6dsv16x_tap_cfg0_t cfg; + lsm6dsv16x_functions_enable_t func; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&func, 1); + + if (ret == 0) + { + func.interrupts_enable = val.enable; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&func, 1); + } + + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&cfg, 1); + + if (ret == 0) + { + cfg.lir = val.lir; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&cfg, 1); + } + + return ret; +} + +/** + * @brief Enables latched interrupt mode.[get] + * + * @param ctx read / write interface definitions + * @param val enable/disable, latched/pulsed + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_interrupt_enable_get(stmdev_ctx_t *ctx, + lsm6dsv16x_interrupt_mode_t *val) +{ + lsm6dsv16x_tap_cfg0_t cfg; + lsm6dsv16x_functions_enable_t func; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&func, 1); + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&cfg, 1); + + val->enable = func.interrupts_enable; + val->lir = cfg.lir; + + return ret; +} + +/** + * @brief Gyroscope full-scale selection[set] + * + * @param ctx read / write interface definitions + * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_gy_full_scale_set(stmdev_ctx_t *ctx, + lsm6dsv16x_gy_full_scale_t val) +{ + lsm6dsv16x_ctrl6_t ctrl6; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL6, (uint8_t *)&ctrl6, 1); + + if (ret == 0) + { + ctrl6.fs_g = (uint8_t)val & 0xfu; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL6, (uint8_t *)&ctrl6, 1); + } + + return ret; +} + +/** + * @brief Gyroscope full-scale selection[get] + * + * @param ctx read / write interface definitions + * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_gy_full_scale_get(stmdev_ctx_t *ctx, + lsm6dsv16x_gy_full_scale_t *val) +{ + lsm6dsv16x_ctrl6_t ctrl6; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL6, (uint8_t *)&ctrl6, 1); + + switch (ctrl6.fs_g) + { + case LSM6DSV16X_125dps: + *val = LSM6DSV16X_125dps; + break; + + case LSM6DSV16X_250dps: + *val = LSM6DSV16X_250dps; + break; + + case LSM6DSV16X_500dps: + *val = LSM6DSV16X_500dps; + break; + + case LSM6DSV16X_1000dps: + *val = LSM6DSV16X_1000dps; + break; + + case LSM6DSV16X_2000dps: + *val = LSM6DSV16X_2000dps; + break; + + case LSM6DSV16X_4000dps: + *val = LSM6DSV16X_4000dps; + break; + + default: + *val = LSM6DSV16X_125dps; + break; + } + return ret; +} + +/** + * @brief Accelerometer full-scale selection.[set] + * + * @param ctx read / write interface definitions + * @param val 2g, 4g, 8g, 16g, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_xl_full_scale_set(stmdev_ctx_t *ctx, + lsm6dsv16x_xl_full_scale_t val) +{ + lsm6dsv16x_ctrl8_t ctrl8; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL8, (uint8_t *)&ctrl8, 1); + + if (ret == 0) + { + ctrl8.fs_xl = (uint8_t)val & 0x3U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL8, (uint8_t *)&ctrl8, 1); + } + + return ret; +} + +/** + * @brief Accelerometer full-scale selection.[get] + * + * @param ctx read / write interface definitions + * @param val 2g, 4g, 8g, 16g, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_xl_full_scale_get(stmdev_ctx_t *ctx, + lsm6dsv16x_xl_full_scale_t *val) +{ + lsm6dsv16x_ctrl8_t ctrl8; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL8, (uint8_t *)&ctrl8, 1); + + switch (ctrl8.fs_xl) + { + case LSM6DSV16X_2g: + *val = LSM6DSV16X_2g; + break; + + case LSM6DSV16X_4g: + *val = LSM6DSV16X_4g; + break; + + case LSM6DSV16X_8g: + *val = LSM6DSV16X_8g; + break; + + case LSM6DSV16X_16g: + *val = LSM6DSV16X_16g; + break; + + default: + *val = LSM6DSV16X_2g; + break; + } + return ret; +} + +/** + * @brief It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.[set] + * + * @param ctx read / write interface definitions + * @param val It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_xl_dual_channel_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_ctrl8_t ctrl8; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL8, (uint8_t *)&ctrl8, 1); + + if (ret == 0) + { + ctrl8.xl_dualc_en = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL8, (uint8_t *)&ctrl8, 1); + } + + return ret; +} + +/** + * @brief It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.[get] + * + * @param ctx read / write interface definitions + * @param val It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_xl_dual_channel_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_ctrl8_t ctrl8; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL8, (uint8_t *)&ctrl8, 1); + *val = ctrl8.xl_dualc_en; + + return ret; +} + +/** + * @brief Accelerometer self-test selection.[set] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_xl_self_test_set(stmdev_ctx_t *ctx, + lsm6dsv16x_xl_self_test_t val) +{ + lsm6dsv16x_ctrl10_t ctrl10; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1); + + if (ret == 0) + { + ctrl10.st_xl = (uint8_t)val & 0x3U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1); + } + + return ret; +} + +/** + * @brief Accelerometer self-test selection.[get] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_xl_self_test_get(stmdev_ctx_t *ctx, + lsm6dsv16x_xl_self_test_t *val) +{ + lsm6dsv16x_ctrl10_t ctrl10; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1); + + switch (ctrl10.st_xl) + { + case LSM6DSV16X_XL_ST_DISABLE: + *val = LSM6DSV16X_XL_ST_DISABLE; + break; + + case LSM6DSV16X_XL_ST_POSITIVE: + *val = LSM6DSV16X_XL_ST_POSITIVE; + break; + + case LSM6DSV16X_XL_ST_NEGATIVE: + *val = LSM6DSV16X_XL_ST_NEGATIVE; + break; + + default: + *val = LSM6DSV16X_XL_ST_DISABLE; + break; + } + return ret; +} + +/** + * @brief Gyroscope self-test selection.[set] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_gy_self_test_set(stmdev_ctx_t *ctx, + lsm6dsv16x_gy_self_test_t val) +{ + lsm6dsv16x_ctrl10_t ctrl10; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1); + + if (ret == 0) + { + ctrl10.st_g = (uint8_t)val & 0x3U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1); + } + + return ret; +} + +/** + * @brief Gyroscope self-test selection.[get] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_gy_self_test_get(stmdev_ctx_t *ctx, + lsm6dsv16x_gy_self_test_t *val) +{ + lsm6dsv16x_ctrl10_t ctrl10; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1); + + switch (ctrl10.st_g) + { + case LSM6DSV16X_GY_ST_DISABLE: + *val = LSM6DSV16X_GY_ST_DISABLE; + break; + + case LSM6DSV16X_GY_ST_POSITIVE: + *val = LSM6DSV16X_GY_ST_POSITIVE; + break; + + case LSM6DSV16X_GY_ST_NEGATIVE: + *val = LSM6DSV16X_GY_ST_NEGATIVE; + break; + + default: + *val = LSM6DSV16X_GY_ST_DISABLE; + break; + } + return ret; +} + +/** + * @brief SPI2 Accelerometer self-test selection.[set] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ois_xl_self_test_set(stmdev_ctx_t *ctx, + lsm6dsv16x_ois_xl_self_test_t val) +{ + lsm6dsv16x_spi2_int_ois_t spi2_int_ois; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); + + if (ret == 0) + { + spi2_int_ois.st_xl_ois = ((uint8_t)val & 0x3U); + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); + } + + return ret; +} + +/** + * @brief SPI2 Accelerometer self-test selection.[get] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ois_xl_self_test_get(stmdev_ctx_t *ctx, + lsm6dsv16x_ois_xl_self_test_t *val) +{ + lsm6dsv16x_spi2_int_ois_t spi2_int_ois; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); + + switch (spi2_int_ois.st_xl_ois) + { + case LSM6DSV16X_OIS_XL_ST_DISABLE: + *val = LSM6DSV16X_OIS_XL_ST_DISABLE; + break; + + case LSM6DSV16X_OIS_XL_ST_POSITIVE: + *val = LSM6DSV16X_OIS_XL_ST_POSITIVE; + break; + + case LSM6DSV16X_OIS_XL_ST_NEGATIVE: + *val = LSM6DSV16X_OIS_XL_ST_NEGATIVE; + break; + + default: + *val = LSM6DSV16X_OIS_XL_ST_DISABLE; + break; + } + return ret; +} + +/** + * @brief SPI2 Accelerometer self-test selection.[set] + * + * @param ctx read / write interface definitions + * @param val GY_ST_DISABLE, GY_ST_POSITIVE, GY_ST_NEGATIVE, LSM6DSV16X_OIS_GY_ST_CLAMP_POS, LSM6DSV16X_OIS_GY_ST_CLAMP_NEG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ois_gy_self_test_set(stmdev_ctx_t *ctx, + lsm6dsv16x_ois_gy_self_test_t val) +{ + lsm6dsv16x_spi2_int_ois_t spi2_int_ois; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); + + if (ret == 0) + { + spi2_int_ois.st_g_ois = ((uint8_t)val & 0x3U); + spi2_int_ois.st_ois_clampdis = ((uint8_t)val & 0x04U) >> 2; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); + } + + return ret; +} + +/** + * @brief SPI2 Accelerometer self-test selection.[get] + * + * @param ctx read / write interface definitions + * @param val GY_ST_DISABLE, GY_ST_POSITIVE, GY_ST_NEGATIVE, LSM6DSV16X_OIS_GY_ST_CLAMP_POS, LSM6DSV16X_OIS_GY_ST_CLAMP_NEG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ois_gy_self_test_get(stmdev_ctx_t *ctx, + lsm6dsv16x_ois_gy_self_test_t *val) +{ + lsm6dsv16x_spi2_int_ois_t spi2_int_ois; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); + + switch (spi2_int_ois.st_g_ois) + { + case LSM6DSV16X_OIS_GY_ST_DISABLE: + *val = LSM6DSV16X_OIS_GY_ST_DISABLE; + break; + + case LSM6DSV16X_OIS_GY_ST_POSITIVE: + *val = (spi2_int_ois.st_ois_clampdis == 1U) ? LSM6DSV16X_OIS_GY_ST_CLAMP_POS : LSM6DSV16X_OIS_GY_ST_POSITIVE; + break; + + case LSM6DSV16X_OIS_GY_ST_NEGATIVE: + *val = (spi2_int_ois.st_ois_clampdis == 1U) ? LSM6DSV16X_OIS_GY_ST_CLAMP_NEG : LSM6DSV16X_OIS_GY_ST_NEGATIVE; + break; + + default: + *val = LSM6DSV16X_OIS_GY_ST_DISABLE; + break; + } + return ret; +} + +/** + * @defgroup interrupt_pins + * @brief This section groups all the functions that manage + * interrupt pins + * @{ + * + */ + +/** + * @brief Select the signal that need to route on int1 pad[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val the signals to route on int1 pin. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsv16x_pin_int1_route_set(stmdev_ctx_t *ctx, + lsm6dsv16x_pin_int_route_t *val) +{ + lsm6dsv16x_int1_ctrl_t int1_ctrl; + lsm6dsv16x_md1_cfg_t md1_cfg; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + + int1_ctrl.int1_drdy_xl = val->drdy_xl; + int1_ctrl.int1_drdy_g = val->drdy_g; + int1_ctrl.int1_fifo_th = val->fifo_th; + int1_ctrl.int1_fifo_ovr = val->fifo_ovr; + int1_ctrl.int1_fifo_full = val->fifo_full; + int1_ctrl.int1_cnt_bdr = val->cnt_bdr; + + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_INT1_CTRL, (uint8_t *)&int1_ctrl, + 1); + + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MD1_CFG, (uint8_t *)&md1_cfg, 1); + + md1_cfg.int1_shub = val->shub; + md1_cfg.int1_emb_func = val->emb_func; + md1_cfg.int1_6d = val->sixd; + md1_cfg.int1_single_tap = val->single_tap; + md1_cfg.int1_double_tap = val->double_tap; + md1_cfg.int1_wu = val->wakeup; + md1_cfg.int1_ff = val->freefall; + md1_cfg.int1_sleep_change = val->sleep_change; + + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MD1_CFG, (uint8_t *)&md1_cfg, 1); + + return ret; +} + +/** + * @brief Select the signal that need to route on int1 pad.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val the signals that are routed on int1 pin.(ptr) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsv16x_pin_int1_route_get(stmdev_ctx_t *ctx, + lsm6dsv16x_pin_int_route_t *val) +{ + lsm6dsv16x_int1_ctrl_t int1_ctrl; + lsm6dsv16x_md1_cfg_t md1_cfg; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + + val->drdy_xl = int1_ctrl.int1_drdy_xl; + val->drdy_g = int1_ctrl.int1_drdy_g; + val->fifo_th = int1_ctrl.int1_fifo_th; + val->fifo_ovr = int1_ctrl.int1_fifo_ovr; + val->fifo_full = int1_ctrl.int1_fifo_full; + val->cnt_bdr = int1_ctrl.int1_cnt_bdr; + + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MD1_CFG, (uint8_t *)&md1_cfg, 1); + + val->shub = md1_cfg.int1_shub; + val->emb_func = md1_cfg.int1_emb_func; + val->sixd = md1_cfg.int1_6d; + val->single_tap = md1_cfg.int1_single_tap; + val->double_tap = md1_cfg.int1_double_tap; + val->wakeup = md1_cfg.int1_wu; + val->freefall = md1_cfg.int1_ff; + val->sleep_change = md1_cfg.int1_sleep_change; + + return ret; +} + +/** + * @brief Select the signal that need to route on int2 pad[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val the signals to route on int1 pin. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsv16x_pin_int2_route_set(stmdev_ctx_t *ctx, + lsm6dsv16x_pin_int_route_t *val) +{ + lsm6dsv16x_int2_ctrl_t int2_ctrl; + lsm6dsv16x_md2_cfg_t md2_cfg; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + + int2_ctrl.int2_drdy_xl = val->drdy_xl; + int2_ctrl.int2_drdy_g = val->drdy_g; + int2_ctrl.int2_fifo_th = val->fifo_th; + int2_ctrl.int2_fifo_ovr = val->fifo_ovr; + int2_ctrl.int2_fifo_full = val->fifo_full; + int2_ctrl.int2_cnt_bdr = val->cnt_bdr; + int2_ctrl.int2_drdy_g_eis = val->drdy_g_eis; + int2_ctrl.int2_emb_func_endop = val->emb_func_endop; + + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_INT2_CTRL, (uint8_t *)&int2_ctrl, + 1); + + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MD2_CFG, (uint8_t *)&md2_cfg, 1); + + md2_cfg.int2_timestamp = val->timestamp; + md2_cfg.int2_emb_func = val->emb_func; + md2_cfg.int2_6d = val->sixd; + md2_cfg.int2_single_tap = val->single_tap; + md2_cfg.int2_double_tap = val->double_tap; + md2_cfg.int2_wu = val->wakeup; + md2_cfg.int2_ff = val->freefall; + md2_cfg.int2_sleep_change = val->sleep_change; + + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MD2_CFG, (uint8_t *)&md2_cfg, 1); + + return ret; +} + +/** + * @brief Select the signal that need to route on int2 pad.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val the signals that are routed on int1 pin.(ptr) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsv16x_pin_int2_route_get(stmdev_ctx_t *ctx, + lsm6dsv16x_pin_int_route_t *val) +{ + lsm6dsv16x_int2_ctrl_t int2_ctrl; + lsm6dsv16x_md2_cfg_t md2_cfg; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + + val->drdy_xl = int2_ctrl.int2_drdy_xl; + val->drdy_g = int2_ctrl.int2_drdy_g; + val->fifo_th = int2_ctrl.int2_fifo_th; + val->fifo_ovr = int2_ctrl.int2_fifo_ovr; + val->fifo_full = int2_ctrl.int2_fifo_full; + val->cnt_bdr = int2_ctrl.int2_cnt_bdr; + val->drdy_g_eis = int2_ctrl.int2_drdy_g_eis; + val->emb_func_endop = int2_ctrl.int2_emb_func_endop; + + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MD2_CFG, (uint8_t *)&md2_cfg, 1); + + val->timestamp = md2_cfg.int2_timestamp; + val->emb_func = md2_cfg.int2_emb_func; + val->sixd = md2_cfg.int2_6d; + val->single_tap = md2_cfg.int2_single_tap; + val->double_tap = md2_cfg.int2_double_tap; + val->wakeup = md2_cfg.int2_wu; + val->freefall = md2_cfg.int2_ff; + val->sleep_change = md2_cfg.int2_sleep_change; + + return ret; +} + +/** + * @} + * + */ + +/** + * @brief Get the status of all the interrupt sources.[get] + * + * @param ctx read / write interface definitions + * @param val Get the status of all the interrupt sources. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_all_sources_get(stmdev_ctx_t *ctx, + lsm6dsv16x_all_sources_t *val) +{ + lsm6dsv16x_emb_func_status_mainpage_t emb_func_status_mainpage; + lsm6dsv16x_emb_func_exec_status_t emb_func_exec_status; + lsm6dsv16x_fsm_status_mainpage_t fsm_status_mainpage; + lsm6dsv16x_mlc_status_mainpage_t mlc_status_mainpage; + lsm6dsv16x_functions_enable_t functions_enable; + lsm6dsv16x_emb_func_src_t emb_func_src; + lsm6dsv16x_fifo_status2_t fifo_status2; + lsm6dsv16x_all_int_src_t all_int_src; + lsm6dsv16x_wake_up_src_t wake_up_src; + lsm6dsv16x_status_reg_t status_reg; + lsm6dsv16x_d6d_src_t d6d_src; + lsm6dsv16x_tap_src_t tap_src; + lsm6dsv16x_ui_status_reg_ois_t status_reg_ois; + lsm6dsv16x_status_master_t status_shub; + uint8_t buff[8]; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret == 0) + { + functions_enable.dis_rst_lir_all_int = PROPERTY_ENABLE; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_STATUS1, (uint8_t *)&buff, 4); + } + bytecpy((uint8_t *)&fifo_status2, &buff[1]); + bytecpy((uint8_t *)&all_int_src, &buff[2]); + bytecpy((uint8_t *)&status_reg, &buff[3]); + + val->fifo_ovr = fifo_status2.fifo_ovr_ia; + val->fifo_bdr = fifo_status2.counter_bdr_ia; + val->fifo_full = fifo_status2.fifo_full_ia; + val->fifo_th = fifo_status2.fifo_wtm_ia; + + val->free_fall = all_int_src.ff_ia; + val->wake_up = all_int_src.wu_ia; + val->six_d = all_int_src.d6d_ia; + + val->drdy_xl = status_reg.xlda; + val->drdy_gy = status_reg.gda; + val->drdy_temp = status_reg.tda; + val->drdy_ah_qvar = status_reg.ah_qvarda; + val->drdy_eis = status_reg.gda_eis; + val->drdy_ois = status_reg.ois_drdy; + val->timestamp = status_reg.timestamp_endcount; + + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + if (ret == 0) + { + functions_enable.dis_rst_lir_all_int = PROPERTY_DISABLE; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_STATUS_REG_OIS, (uint8_t *)&buff, 8); + } + + bytecpy((uint8_t *)&status_reg_ois, &buff[0]); + bytecpy((uint8_t *)&wake_up_src, &buff[1]); + bytecpy((uint8_t *)&tap_src, &buff[2]); + bytecpy((uint8_t *)&d6d_src, &buff[3]); + bytecpy((uint8_t *)&emb_func_status_mainpage, &buff[5]); + bytecpy((uint8_t *)&fsm_status_mainpage, &buff[6]); + bytecpy((uint8_t *)&mlc_status_mainpage, &buff[7]); + + val->gy_settling = status_reg_ois.gyro_settling; + val->sleep_change = wake_up_src.sleep_change_ia; + val->wake_up_x = wake_up_src.x_wu; + val->wake_up_y = wake_up_src.y_wu; + val->wake_up_z = wake_up_src.z_wu; + val->sleep_state = wake_up_src.sleep_state; + + val->tap_x = tap_src.x_tap; + val->tap_y = tap_src.y_tap; + val->tap_z = tap_src.z_tap; + val->tap_sign = tap_src.tap_sign; + val->double_tap = tap_src.double_tap; + val->single_tap = tap_src.single_tap; + + val->six_d_zl = d6d_src.zl; + val->six_d_zh = d6d_src.zh; + val->six_d_yl = d6d_src.yl; + val->six_d_yh = d6d_src.yh; + val->six_d_xl = d6d_src.xl; + val->six_d_xh = d6d_src.xh; + + val->step_detector = emb_func_status_mainpage.is_step_det; + val->tilt = emb_func_status_mainpage.is_tilt; + val->sig_mot = emb_func_status_mainpage.is_sigmot; + val->fsm_lc = emb_func_status_mainpage.is_fsm_lc; + + val->fsm1 = fsm_status_mainpage.is_fsm1; + val->fsm2 = fsm_status_mainpage.is_fsm2; + val->fsm3 = fsm_status_mainpage.is_fsm3; + val->fsm4 = fsm_status_mainpage.is_fsm4; + val->fsm5 = fsm_status_mainpage.is_fsm5; + val->fsm6 = fsm_status_mainpage.is_fsm6; + val->fsm7 = fsm_status_mainpage.is_fsm7; + val->fsm8 = fsm_status_mainpage.is_fsm8; + + val->mlc1 = mlc_status_mainpage.is_mlc1; + val->mlc2 = mlc_status_mainpage.is_mlc2; + val->mlc3 = mlc_status_mainpage.is_mlc3; + val->mlc4 = mlc_status_mainpage.is_mlc4; + + + if (ret == 0) + { + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + } + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status, 1); + } + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + val->emb_func_stand_by = emb_func_exec_status.emb_func_endop; + val->emb_func_time_exceed = emb_func_exec_status.emb_func_exec_ovr; + val->step_count_inc = emb_func_src.stepcounter_bit_set; + val->step_count_overflow = emb_func_src.step_overflow; + val->step_on_delta_time = emb_func_src.step_count_delta_ia; + + val->step_detector = emb_func_src.step_detected; + + /* sensor hub */ + if (ret == 0) + { + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); + } + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_STATUS_MASTER, (uint8_t *)&status_shub, 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + val->sh_endop = status_shub.sens_hub_endop; + val->sh_wr_once = status_shub.wr_once_done; + val->sh_slave3_nack = status_shub.slave3_nack; + val->sh_slave2_nack = status_shub.slave2_nack; + val->sh_slave1_nack = status_shub.slave1_nack; + val->sh_slave0_nack = status_shub.slave0_nack; + + return ret; +} + +int32_t lsm6dsv16x_flag_data_ready_get(stmdev_ctx_t *ctx, + lsm6dsv16x_data_ready_t *val) +{ + lsm6dsv16x_status_reg_t status; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_STATUS_REG, (uint8_t *)&status, 1); + val->drdy_xl = status.xlda; + val->drdy_gy = status.gda; + val->drdy_temp = status.tda; + + return ret; +} + +/** + * @brief Mask status bit reset[set] + * + * @param ctx read / write interface definitions + * @param val Mask to prevent status bit being reset + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_int_ack_mask_set(stmdev_ctx_t *ctx, uint8_t val) +{ + int32_t ret; + + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_INT_ACK_MASK, &val, 1); + + return ret; +} + +/** + * @brief Mask status bit reset[get] + * + * @param ctx read / write interface definitions + * @param val Mask to prevent status bit being reset + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_int_ack_mask_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INT_ACK_MASK, val, 1); + + return ret; +} + +/** + * @brief Temperature data output register[get] + * + * @param ctx read / write interface definitions + * @param val Temperature data output register + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_OUT_TEMP_L, &buff[0], 2); + *val = (int16_t)buff[1]; + *val = (*val * 256) + (int16_t)buff[0]; + + return ret; +} + +/** + * @brief Angular rate sensor.[get] + * + * @param ctx read / write interface definitions + * @param val Angular rate sensor. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_OUTX_L_G, &buff[0], 6); + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Angular rate sensor.[get] + * + * @param ctx read / write interface definitions + * @param val OIS Angular rate sensor (thru SPI2). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ois_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SPI2_OUTX_L_G_OIS, &buff[0], 6); + val[0] = (int16_t)buff[1]; + val[0] = (*val * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (*val * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (*val * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Angular rate sensor for OIS gyro or the EIS gyro channel.[get] + * + * @param ctx read / write interface definitions + * @param val Angular rate sensor for OIS gyro or the EIS gyro channel. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ois_eis_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_OUTX_L_G_OIS_EIS, &buff[0], 6); + val[0] = (int16_t)buff[1]; + val[0] = (*val * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (*val * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (*val * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Linear acceleration sensor.[get] + * + * @param ctx read / write interface definitions + * @param val Linear acceleration sensor. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_OUTX_L_A, &buff[0], 6); + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Linear acceleration sensor for Dual channel mode.[get] + * + * @param ctx read / write interface definitions + * @param val Linear acceleration sensor or Dual channel mode. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_dual_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_OUTX_L_A_OIS_DUALC, &buff[0], 6); + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief ah_qvar data output register.[get] + * + * @param ctx read / write interface definitions + * @param val ah_qvar data output register. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ah_qvar_raw_get(stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_AH_QVAR_OUT_L, &buff[0], 2); + *val = (int16_t)buff[1]; + *val = (*val * 256) + (int16_t)buff[0]; + + return ret; +} + +/** + * @brief Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement.[get] + * + * @param ctx read / write interface definitions + * @param val Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_odr_cal_reg_get(stmdev_ctx_t *ctx, int8_t *val) +{ + lsm6dsv16x_internal_freq_t internal_freq; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INTERNAL_FREQ, (uint8_t *)&internal_freq, 1); + *val = (int8_t)internal_freq.freq_fine; + + return ret; +} + +/** + * @brief Write buffer in a page.[set] + * + * @param ctx read / write interface definitions + * @param val Write buffer in a page. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, + uint8_t *buf, uint8_t len) +{ + lsm6dsv16x_page_address_t page_address; + lsm6dsv16x_page_sel_t page_sel; + lsm6dsv16x_page_rw_t page_rw; + uint8_t msb; + uint8_t lsb; + int32_t ret; + uint8_t i ; + + msb = ((uint8_t)(address >> 8) & 0x0FU); + lsb = (uint8_t)address & 0xFFU; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + + /* set page write */ + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_ENABLE; + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1); + + /* select page */ + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1); + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1); + + /* set page addr */ + page_address.page_addr = lsb; + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + + for (i = 0; ((i < len) && (ret == 0)); i++) + { + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_VALUE, &buf[i], 1); + lsb++; + + /* Check if page wrap */ + if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) + { + msb++; + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1); + + if (ret == 0) + { + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1); + } + } + } + + page_sel.page_sel = 0; + page_sel.not_used0 = 1;// Default value + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1); + + /* unset page write */ + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1); + + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @defgroup Common + * @brief This section groups common useful functions. + * @{/ + * + */ + +/** + * @brief Read buffer in a page.[set] + * + * @param ctx read / write interface definitions + * @param val Write buffer in a page. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, + uint8_t len) +{ + lsm6dsv16x_page_address_t page_address; + lsm6dsv16x_page_sel_t page_sel; + lsm6dsv16x_page_rw_t page_rw; + uint8_t msb; + uint8_t lsb; + int32_t ret; + uint8_t i ; + + msb = ((uint8_t)(address >> 8) & 0x0FU); + lsb = (uint8_t)address & 0xFFU; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + + /* set page write */ + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_ENABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1); + + /* select page */ + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1); + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1); + + /* set page addr */ + page_address.page_addr = lsb; + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + + for (i = 0; ((i < len) && (ret == 0)); i++) + { + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_VALUE, &buf[i], 1); + lsb++; + + /* Check if page wrap */ + if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) + { + msb++; + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1); + + if (ret == 0) + { + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1); + } + } + } + + page_sel.page_sel = 0; + page_sel.not_used0 = 1;// Default value + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1); + + /* unset page write */ + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1); + + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable debug mode for embedded functions [set] + * + * @param ctx read / write interface definitions + * @param val 0, 1 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_emb_function_dbg_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_ctrl10_t ctrl10; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1); + + if (ret == 0) + { + ctrl10.emb_func_debug = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1); + } + + return ret; +} + +/** + * @brief Enable debug mode for embedded functions [get] + * + * @param ctx read / write interface definitions + * @param val 0, 1 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_emb_function_dbg_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_ctrl10_t ctrl10; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1); + + if (ret == 0) + { + *val = ctrl10.emb_func_debug; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Data ENable (DEN) + * @brief This section groups all the functions concerning + * DEN functionality. + * @{ + * + */ + +/** + * @brief It changes the polarity of INT2 pin input trigger for data enable (DEN) or embedded functions.[set] + * + * @param ctx read / write interface definitions + * @param val DEN_ACT_LOW, DEN_ACT_HIGH, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_den_polarity_set(stmdev_ctx_t *ctx, + lsm6dsv16x_den_polarity_t val) +{ + lsm6dsv16x_ctrl4_t ctrl4; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1); + + if (ret == 0) + { + ctrl4.int2_in_lh = (uint8_t)val & 0x1U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1); + } + + return ret; +} + +/** + * @brief It changes the polarity of INT2 pin input trigger for data enable (DEN) or embedded functions.[get] + * + * @param ctx read / write interface definitions + * @param val DEN_ACT_LOW, DEN_ACT_HIGH, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_den_polarity_get(stmdev_ctx_t *ctx, + lsm6dsv16x_den_polarity_t *val) +{ + lsm6dsv16x_ctrl4_t ctrl4; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1); + switch (ctrl4.int2_in_lh) + { + case LSM6DSV16X_DEN_ACT_LOW: + *val = LSM6DSV16X_DEN_ACT_LOW; + break; + + case LSM6DSV16X_DEN_ACT_HIGH: + *val = LSM6DSV16X_DEN_ACT_HIGH; + break; + + default: + *val = LSM6DSV16X_DEN_ACT_LOW; + break; + } + return ret; +} + +/** + * @brief Data ENable (DEN) configuration.[set] + * + * @param ctx read / write interface definitions + * @param val Data ENable (DEN) configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_den_conf_set(stmdev_ctx_t *ctx, lsm6dsv16x_den_conf_t val) +{ + lsm6dsv16x_den_t den; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_DEN, (uint8_t *)&den, 1); + if (ret == 0) + { + den.den_z = val.den_z; + den.den_y = val.den_y; + den.den_x = val.den_x; + + den.lvl2_en = (uint8_t)val.mode & 0x1U; + den.lvl1_en = ((uint8_t)val.mode & 0x2U) >> 1; + + if (val.stamp_in_gy_data == PROPERTY_ENABLE && val.stamp_in_xl_data == PROPERTY_ENABLE) + { + den.den_xl_g = PROPERTY_DISABLE; + den.den_xl_en = PROPERTY_ENABLE; + } + else if (val.stamp_in_gy_data == PROPERTY_ENABLE && val.stamp_in_xl_data == PROPERTY_DISABLE) + { + den.den_xl_g = PROPERTY_DISABLE; + den.den_xl_en = PROPERTY_DISABLE; + } + else if (val.stamp_in_gy_data == PROPERTY_DISABLE && val.stamp_in_xl_data == PROPERTY_ENABLE) + { + den.den_xl_g = PROPERTY_ENABLE; + den.den_xl_en = PROPERTY_DISABLE; + } + else + { + den.den_xl_g = PROPERTY_DISABLE; + den.den_xl_en = PROPERTY_DISABLE; + den.den_z = PROPERTY_DISABLE; + den.den_y = PROPERTY_DISABLE; + den.den_x = PROPERTY_DISABLE; + den.lvl2_en = PROPERTY_DISABLE; + den.lvl1_en = PROPERTY_DISABLE; + } + + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_DEN, (uint8_t *)&den, 1); + } + + return ret; +} + + +/** + * @brief Data ENable (DEN) configuration.[get] + * + * @param ctx read / write interface definitions + * @param val Data ENable (DEN) configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_den_conf_get(stmdev_ctx_t *ctx, lsm6dsv16x_den_conf_t *val) +{ + lsm6dsv16x_den_t den; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_DEN, (uint8_t *)&den, 1); + + val->den_z = den.den_z; + val->den_y = den.den_y; + val->den_x = den.den_x; + + if ((den.den_z | den.den_z | den.den_z) == PROPERTY_ENABLE) + { + if (den.den_xl_g == PROPERTY_DISABLE && den.den_xl_en == PROPERTY_ENABLE) + { + val->stamp_in_gy_data = PROPERTY_ENABLE; + val->stamp_in_xl_data = PROPERTY_ENABLE; + } + else if (den.den_xl_g == PROPERTY_DISABLE && den.den_xl_en == PROPERTY_DISABLE) + { + val->stamp_in_gy_data = PROPERTY_ENABLE; + val->stamp_in_xl_data = PROPERTY_DISABLE; + } + else // ( (den.den_xl_g & !den.den_xl_en) == PROPERTY_ENABLE ) + { + val->stamp_in_gy_data = PROPERTY_DISABLE; + val->stamp_in_xl_data = PROPERTY_ENABLE; + } + } + else + { + val->stamp_in_gy_data = PROPERTY_DISABLE; + val->stamp_in_xl_data = PROPERTY_DISABLE; + } + + switch ((den.lvl1_en << 1) + den.lvl2_en) + { + case LEVEL_TRIGGER: + val->mode = LEVEL_TRIGGER; + break; + + case LEVEL_LATCHED: + val->mode = LEVEL_LATCHED; + break; + + default: + val->mode = DEN_NOT_DEFINED; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Electronic Image Stabilization (EIS) + * @brief Electronic Image Stabilization (EIS) + * @{/ + * + */ + +/** + * @brief Gyroscope full-scale selection for EIS channel. WARNING: 4000dps will be available only if also User Interface chain is set to 4000dps[set] + * + * @param ctx read / write interface definitions + * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_eis_gy_full_scale_set(stmdev_ctx_t *ctx, + lsm6dsv16x_eis_gy_full_scale_t val) +{ + lsm6dsv16x_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + + if (ret == 0) + { + ctrl_eis.fs_g_eis = (uint8_t)val & 0x7U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + } + + return ret; +} + +/** + * @brief Gyroscope full-scale selection for EIS channel. WARNING: 4000dps will be available only if also User Interface chain is set to 4000dps[get] + * + * @param ctx read / write interface definitions + * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_eis_gy_full_scale_get(stmdev_ctx_t *ctx, + lsm6dsv16x_eis_gy_full_scale_t *val) +{ + lsm6dsv16x_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + + switch (ctrl_eis.fs_g_eis) + { + case LSM6DSV16X_EIS_125dps: + *val = LSM6DSV16X_EIS_125dps; + break; + + case LSM6DSV16X_EIS_250dps: + *val = LSM6DSV16X_EIS_250dps; + break; + + case LSM6DSV16X_EIS_500dps: + *val = LSM6DSV16X_EIS_500dps; + break; + + case LSM6DSV16X_EIS_1000dps: + *val = LSM6DSV16X_EIS_1000dps; + break; + + case LSM6DSV16X_EIS_2000dps: + *val = LSM6DSV16X_EIS_2000dps; + break; + + default: + *val = LSM6DSV16X_EIS_125dps; + break; + } + return ret; +} + +/** + * @brief Enables routing of gyroscope EIS outputs on SPI2 (OIS interface). The gyroscope data on SPI2 (OIS interface) cannot be read from User Interface (UI).[set] + * + * @param ctx read / write interface definitions + * @param val Enables routing of gyroscope EIS outputs on SPI2 (OIS interface). The gyroscope data on SPI2 (OIS interface) cannot be read from User Interface (UI). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_eis_gy_on_spi2_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + + if (ret == 0) + { + ctrl_eis.g_eis_on_g_ois_out_reg = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + } + + return ret; +} + +/** + * @brief Enables routing of gyroscope EIS outputs on SPI2 (OIS interface). The gyroscope data on SPI2 (OIS interface) cannot be read from User Interface (UI).[get] + * + * @param ctx read / write interface definitions + * @param val Enables routing of gyroscope EIS outputs on SPI2 (OIS interface). The gyroscope data on SPI2 (OIS interface) cannot be read from User Interface (UI). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_eis_gy_on_spi2_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + *val = ctrl_eis.g_eis_on_g_ois_out_reg; + + return ret; +} + +/** + * @brief Enables and selects the ODR of the gyroscope EIS channel.[set] + * + * @param ctx read / write interface definitions + * @param val EIS_1920Hz, EIS_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_gy_eis_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv16x_gy_eis_data_rate_t val) +{ + lsm6dsv16x_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + + if (ret == 0) + { + ctrl_eis.odr_g_eis = (uint8_t)val & 0x03U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + } + + return ret; +} + +/** + * @brief Enables and selects the ODR of the gyroscope EIS channel.[get] + * + * @param ctx read / write interface definitions + * @param val EIS_1920Hz, EIS_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_gy_eis_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv16x_gy_eis_data_rate_t *val) +{ + lsm6dsv16x_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + + switch (ctrl_eis.odr_g_eis) + { + case LSM6DSV16X_EIS_ODR_OFF: + *val = LSM6DSV16X_EIS_ODR_OFF; + break; + + case LSM6DSV16X_EIS_1920Hz: + *val = LSM6DSV16X_EIS_1920Hz; + break; + + case LSM6DSV16X_EIS_960Hz: + *val = LSM6DSV16X_EIS_960Hz; + break; + + default: + *val = LSM6DSV16X_EIS_1920Hz; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup FIFO + * @brief This section group all the functions concerning the FIFO usage + * @{ + * + */ + +/** + * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[set] + * + * @param ctx read / write interface definitions + * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_fifo_ctrl1_t fifo_ctrl1; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + + if (ret == 0) + { + fifo_ctrl1.wtm = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + } + + return ret; +} + +/** + * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[get] + * + * @param ctx read / write interface definitions + * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_fifo_ctrl1_t fifo_ctrl1; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + *val = fifo_ctrl1.wtm; + + return ret; +} + +/** + * @brief When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.[set] + * + * @param ctx read / write interface definitions + * @param val When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_xl_dual_fsm_batch_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.xl_dualc_batch_from_fsm = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.[get] + * + * @param ctx read / write interface definitions + * @param val When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_xl_dual_fsm_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + *val = fifo_ctrl2.xl_dualc_batch_from_fsm; + + + return ret; +} + +/** + * @brief It configures the compression algorithm to write non-compressed data at each rate.[set] + * + * @param ctx read / write interface definitions + * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_compress_algo_set(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_compress_algo_t val) +{ + lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.uncompr_rate = (uint8_t)val & 0x03U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief It configures the compression algorithm to write non-compressed data at each rate.[get] + * + * @param ctx read / write interface definitions + * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_compress_algo_get(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_compress_algo_t *val) +{ + lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + switch (fifo_ctrl2.uncompr_rate) + { + case LSM6DSV16X_CMP_DISABLE: + *val = LSM6DSV16X_CMP_DISABLE; + break; + + case LSM6DSV16X_CMP_8_TO_1: + *val = LSM6DSV16X_CMP_8_TO_1; + break; + + case LSM6DSV16X_CMP_16_TO_1: + *val = LSM6DSV16X_CMP_16_TO_1; + break; + + case LSM6DSV16X_CMP_32_TO_1: + *val = LSM6DSV16X_CMP_32_TO_1; + break; + + default: + *val = LSM6DSV16X_CMP_DISABLE; + break; + } + return ret; +} + +/** + * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set] + * + * @param ctx read / write interface definitions + * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.odr_chg_en = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get] + * + * @param ctx read / write interface definitions + * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, + uint8_t *val) +{ + lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + *val = fifo_ctrl2.odr_chg_en; + + return ret; +} + +/** + * @brief Enables/Disables compression algorithm runtime.[set] + * + * @param ctx read / write interface definitions + * @param val Enables/Disables compression algorithm runtime. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_compress_algo_real_time_set(stmdev_ctx_t *ctx, + uint8_t val) +{ + lsm6dsv16x_emb_func_en_b_t emb_func_en_b; + lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2; + + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.fifo_compr_rt_en = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + } + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + emb_func_en_b.fifo_compr_en = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enables/Disables compression algorithm runtime.[get] + * + * @param ctx read / write interface definitions + * @param val Enables/Disables compression algorithm runtime. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_compress_algo_real_time_get(stmdev_ctx_t *ctx, + uint8_t *val) +{ + lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + + *val = fifo_ctrl2.fifo_compr_rt_en; + + return ret; +} + +/** + * @brief Sensing chain FIFO stop values memorization at threshold level.[set] + * + * @param ctx read / write interface definitions + * @param val Sensing chain FIFO stop values memorization at threshold level. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.stop_on_wtm = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief Sensing chain FIFO stop values memorization at threshold level.[get] + * + * @param ctx read / write interface definitions + * @param val Sensing chain FIFO stop values memorization at threshold level. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + *val = fifo_ctrl2.stop_on_wtm; + + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[set] + * + * @param ctx read / write interface definitions + * @param val XL_NOT_BATCHED, XL_BATCHED_AT_1Hz875, XL_BATCHED_AT_7Hz5, XL_BATCHED_AT_15Hz, XL_BATCHED_AT_30Hz, XL_BATCHED_AT_60Hz, XL_BATCHED_AT_120Hz, XL_BATCHED_AT_240Hz, XL_BATCHED_AT_480Hz, XL_BATCHED_AT_960Hz, XL_BATCHED_AT_1920Hz, XL_BATCHED_AT_3840Hz, XL_BATCHED_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_xl_batch_set(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_xl_batch_t val) +{ + lsm6dsv16x_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret == 0) + { + fifo_ctrl3.bdr_xl = (uint8_t)val & 0xFu; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + } + + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[get] + * + * @param ctx read / write interface definitions + * @param val XL_NOT_BATCHED, XL_BATCHED_AT_1Hz875, XL_BATCHED_AT_7Hz5, XL_BATCHED_AT_15Hz, XL_BATCHED_AT_30Hz, XL_BATCHED_AT_60Hz, XL_BATCHED_AT_120Hz, XL_BATCHED_AT_240Hz, XL_BATCHED_AT_480Hz, XL_BATCHED_AT_960Hz, XL_BATCHED_AT_1920Hz, XL_BATCHED_AT_3840Hz, XL_BATCHED_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_xl_batch_get(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_xl_batch_t *val) +{ + lsm6dsv16x_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + switch (fifo_ctrl3.bdr_xl) + { + case LSM6DSV16X_XL_NOT_BATCHED: + *val = LSM6DSV16X_XL_NOT_BATCHED; + break; + + case LSM6DSV16X_XL_BATCHED_AT_1Hz875: + *val = LSM6DSV16X_XL_BATCHED_AT_1Hz875; + break; + + case LSM6DSV16X_XL_BATCHED_AT_7Hz5: + *val = LSM6DSV16X_XL_BATCHED_AT_7Hz5; + break; + + case LSM6DSV16X_XL_BATCHED_AT_15Hz: + *val = LSM6DSV16X_XL_BATCHED_AT_15Hz; + break; + + case LSM6DSV16X_XL_BATCHED_AT_30Hz: + *val = LSM6DSV16X_XL_BATCHED_AT_30Hz; + break; + + case LSM6DSV16X_XL_BATCHED_AT_60Hz: + *val = LSM6DSV16X_XL_BATCHED_AT_60Hz; + break; + + case LSM6DSV16X_XL_BATCHED_AT_120Hz: + *val = LSM6DSV16X_XL_BATCHED_AT_120Hz; + break; + + case LSM6DSV16X_XL_BATCHED_AT_240Hz: + *val = LSM6DSV16X_XL_BATCHED_AT_240Hz; + break; + + case LSM6DSV16X_XL_BATCHED_AT_480Hz: + *val = LSM6DSV16X_XL_BATCHED_AT_480Hz; + break; + + case LSM6DSV16X_XL_BATCHED_AT_960Hz: + *val = LSM6DSV16X_XL_BATCHED_AT_960Hz; + break; + + case LSM6DSV16X_XL_BATCHED_AT_1920Hz: + *val = LSM6DSV16X_XL_BATCHED_AT_1920Hz; + break; + + case LSM6DSV16X_XL_BATCHED_AT_3840Hz: + *val = LSM6DSV16X_XL_BATCHED_AT_3840Hz; + break; + + case LSM6DSV16X_XL_BATCHED_AT_7680Hz: + *val = LSM6DSV16X_XL_BATCHED_AT_7680Hz; + break; + + default: + *val = LSM6DSV16X_XL_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[set] + * + * @param ctx read / write interface definitions + * @param val GY_NOT_BATCHED, GY_BATCHED_AT_1Hz875, GY_BATCHED_AT_7Hz5, GY_BATCHED_AT_15Hz, GY_BATCHED_AT_30Hz, GY_BATCHED_AT_60Hz, GY_BATCHED_AT_120Hz, GY_BATCHED_AT_240Hz, GY_BATCHED_AT_480Hz, GY_BATCHED_AT_960Hz, GY_BATCHED_AT_1920Hz, GY_BATCHED_AT_3840Hz, GY_BATCHED_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_gy_batch_set(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_gy_batch_t val) +{ + lsm6dsv16x_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret == 0) + { + fifo_ctrl3.bdr_gy = (uint8_t)val & 0x0Fu; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + } + + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[get] + * + * @param ctx read / write interface definitions + * @param val GY_NOT_BATCHED, GY_BATCHED_AT_1Hz875, GY_BATCHED_AT_7Hz5, GY_BATCHED_AT_15Hz, GY_BATCHED_AT_30Hz, GY_BATCHED_AT_60Hz, GY_BATCHED_AT_120Hz, GY_BATCHED_AT_240Hz, GY_BATCHED_AT_480Hz, GY_BATCHED_AT_960Hz, GY_BATCHED_AT_1920Hz, GY_BATCHED_AT_3840Hz, GY_BATCHED_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_gy_batch_get(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_gy_batch_t *val) +{ + lsm6dsv16x_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + switch (fifo_ctrl3.bdr_gy) + { + case LSM6DSV16X_GY_NOT_BATCHED: + *val = LSM6DSV16X_GY_NOT_BATCHED; + break; + + case LSM6DSV16X_GY_BATCHED_AT_1Hz875: + *val = LSM6DSV16X_GY_BATCHED_AT_1Hz875; + break; + + case LSM6DSV16X_GY_BATCHED_AT_7Hz5: + *val = LSM6DSV16X_GY_BATCHED_AT_7Hz5; + break; + + case LSM6DSV16X_GY_BATCHED_AT_15Hz: + *val = LSM6DSV16X_GY_BATCHED_AT_15Hz; + break; + + case LSM6DSV16X_GY_BATCHED_AT_30Hz: + *val = LSM6DSV16X_GY_BATCHED_AT_30Hz; + break; + + case LSM6DSV16X_GY_BATCHED_AT_60Hz: + *val = LSM6DSV16X_GY_BATCHED_AT_60Hz; + break; + + case LSM6DSV16X_GY_BATCHED_AT_120Hz: + *val = LSM6DSV16X_GY_BATCHED_AT_120Hz; + break; + + case LSM6DSV16X_GY_BATCHED_AT_240Hz: + *val = LSM6DSV16X_GY_BATCHED_AT_240Hz; + break; + + case LSM6DSV16X_GY_BATCHED_AT_480Hz: + *val = LSM6DSV16X_GY_BATCHED_AT_480Hz; + break; + + case LSM6DSV16X_GY_BATCHED_AT_960Hz: + *val = LSM6DSV16X_GY_BATCHED_AT_960Hz; + break; + + case LSM6DSV16X_GY_BATCHED_AT_1920Hz: + *val = LSM6DSV16X_GY_BATCHED_AT_1920Hz; + break; + + case LSM6DSV16X_GY_BATCHED_AT_3840Hz: + *val = LSM6DSV16X_GY_BATCHED_AT_3840Hz; + break; + + case LSM6DSV16X_GY_BATCHED_AT_7680Hz: + *val = LSM6DSV16X_GY_BATCHED_AT_7680Hz; + break; + + default: + *val = LSM6DSV16X_GY_NOT_BATCHED; + break; + } + return ret; +} + + +/** + * @brief FIFO mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val BYPASS_MODE, FIFO_MODE, STREAM_WTM_TO_FULL_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_fifo_mode_t val) +{ + lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.fifo_mode = (uint8_t)val & 0x07U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief FIFO mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val BYPASS_MODE, FIFO_MODE, STREAM_WTM_TO_FULL_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_fifo_mode_t *val) +{ + lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + switch (fifo_ctrl4.fifo_mode) + { + case LSM6DSV16X_BYPASS_MODE: + *val = LSM6DSV16X_BYPASS_MODE; + break; + + case LSM6DSV16X_FIFO_MODE: + *val = LSM6DSV16X_FIFO_MODE; + break; + + case LSM6DSV16X_STREAM_WTM_TO_FULL_MODE: + *val = LSM6DSV16X_STREAM_WTM_TO_FULL_MODE; + break; + + case LSM6DSV16X_STREAM_TO_FIFO_MODE: + *val = LSM6DSV16X_STREAM_TO_FIFO_MODE; + break; + + case LSM6DSV16X_BYPASS_TO_STREAM_MODE: + *val = LSM6DSV16X_BYPASS_TO_STREAM_MODE; + break; + + case LSM6DSV16X_STREAM_MODE: + *val = LSM6DSV16X_STREAM_MODE; + break; + + case LSM6DSV16X_BYPASS_TO_FIFO_MODE: + *val = LSM6DSV16X_BYPASS_TO_FIFO_MODE; + break; + + default: + *val = LSM6DSV16X_BYPASS_MODE; + break; + } + return ret; +} + +/** + * @brief Enables FIFO batching of EIS gyroscope output values.[set] + * + * @param ctx read / write interface definitions + * @param val Enables FIFO batching of EIS gyroscope output values. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_gy_eis_batch_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.g_eis_fifo_en = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief Enables FIFO batching of EIS gyroscope output values.[get] + * + * @param ctx read / write interface definitions + * @param val Enables FIFO batching of EIS gyroscope output values. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_gy_eis_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + *val = fifo_ctrl4.g_eis_fifo_en; + + return ret; +} + +/** + * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[set] + * + * @param ctx read / write interface definitions + * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_temp_batch_set(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_temp_batch_t val) +{ + lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.odr_t_batch = (uint8_t)val & 0x03U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[get] + * + * @param ctx read / write interface definitions + * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_temp_batch_get(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_temp_batch_t *val) +{ + lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + switch (fifo_ctrl4.odr_t_batch) + { + case LSM6DSV16X_TEMP_NOT_BATCHED: + *val = LSM6DSV16X_TEMP_NOT_BATCHED; + break; + + case LSM6DSV16X_TEMP_BATCHED_AT_1Hz875: + *val = LSM6DSV16X_TEMP_BATCHED_AT_1Hz875; + break; + + case LSM6DSV16X_TEMP_BATCHED_AT_15Hz: + *val = LSM6DSV16X_TEMP_BATCHED_AT_15Hz; + break; + + case LSM6DSV16X_TEMP_BATCHED_AT_60Hz: + *val = LSM6DSV16X_TEMP_BATCHED_AT_60Hz; + break; + + default: + *val = LSM6DSV16X_TEMP_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[set] + * + * @param ctx read / write interface definitions + * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_timestamp_batch_set(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_timestamp_batch_t val) +{ + lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.dec_ts_batch = (uint8_t)val & 0x03U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[get] + * + * @param ctx read / write interface definitions + * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_timestamp_batch_get(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_timestamp_batch_t *val) +{ + lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + switch (fifo_ctrl4.dec_ts_batch) + { + case LSM6DSV16X_TMSTMP_NOT_BATCHED: + *val = LSM6DSV16X_TMSTMP_NOT_BATCHED; + break; + + case LSM6DSV16X_TMSTMP_DEC_1: + *val = LSM6DSV16X_TMSTMP_DEC_1; + break; + + case LSM6DSV16X_TMSTMP_DEC_8: + *val = LSM6DSV16X_TMSTMP_DEC_8; + break; + + case LSM6DSV16X_TMSTMP_DEC_32: + *val = LSM6DSV16X_TMSTMP_DEC_32; + break; + + default: + *val = LSM6DSV16X_TMSTMP_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[set] + * + * @param ctx read / write interface definitions + * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_batch_counter_threshold_set(stmdev_ctx_t *ctx, + uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_COUNTER_BDR_REG1, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[get] + * + * @param ctx read / write interface definitions + * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_batch_counter_threshold_get(stmdev_ctx_t *ctx, + uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_COUNTER_BDR_REG1, &buff[0], 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope and EIS gyroscope.[set] + * + * @param ctx read / write interface definitions + * @param val XL_BATCH_EVENT, GY_BATCH_EVENT, GY_EIS_BATCH_EVENT, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_batch_cnt_event_set(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_batch_cnt_event_t val) +{ + lsm6dsv16x_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret == 0) + { + counter_bdr_reg1.trig_counter_bdr = (uint8_t)val & 0x03U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + } + + return ret; +} + +/** + * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope and EIS gyroscope.[get] + * + * @param ctx read / write interface definitions + * @param val XL_BATCH_EVENT, GY_BATCH_EVENT, GY_EIS_BATCH_EVENT, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_batch_cnt_event_get(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_batch_cnt_event_t *val) +{ + lsm6dsv16x_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + switch (counter_bdr_reg1.trig_counter_bdr) + { + case LSM6DSV16X_XL_BATCH_EVENT: + *val = LSM6DSV16X_XL_BATCH_EVENT; + break; + + case LSM6DSV16X_GY_BATCH_EVENT: + *val = LSM6DSV16X_GY_BATCH_EVENT; + break; + + case LSM6DSV16X_GY_EIS_BATCH_EVENT: + *val = LSM6DSV16X_GY_EIS_BATCH_EVENT; + break; + + default: + *val = LSM6DSV16X_XL_BATCH_EVENT; + break; + } + return ret; +} + +int32_t lsm6dsv16x_fifo_status_get(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_status_t *val) +{ + uint8_t buff[2]; + lsm6dsv16x_fifo_status2_t status; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_STATUS1, (uint8_t *)&buff[0], 2); + bytecpy((uint8_t *)&status, &buff[1]); + + val->fifo_bdr = status.counter_bdr_ia; + val->fifo_ovr = status.fifo_ovr_ia; + val->fifo_full = status.fifo_full_ia; + val->fifo_th = status.fifo_wtm_ia; + + val->fifo_level = (uint16_t)buff[1] & 0x01U; + val->fifo_level = (val->fifo_level * 256U) + buff[0]; + + return ret; +} + + +/** + * @brief FIFO data output[get] + * + * @param ctx read / write interface definitions + * @param val FIFO_EMPTY, GY_NC_TAG, XL_NC_TAG, TIMESTAMP_TAG, + TEMPERATURE_TAG, CFG_CHANGE_TAG, XL_NC_T_2_TAG, + XL_NC_T_1_TAG, XL_2XC_TAG, XL_3XC_TAG, GY_NC_T_2_TAG, + GY_NC_T_1_TAG, GY_2XC_TAG, GY_3XC_TAG, SENSORHUB_SLAVE0_TAG, + SENSORHUB_SLAVE1_TAG, SENSORHUB_SLAVE2_TAG, SENSORHUB_SLAVE3_TAG, + STEP_COUNTER_TAG, SFLP_GAME_ROTATION_VECTOR_TAG, SFLP_GYROSCOPE_BIAS_TAG, + SFLP_GRAVITY_VECTOR_TAG, SENSORHUB_NACK_TAG, MLC_RESULT_TAG, + MLC_FILTER, MLC_FEATURE, XL_DUAL_CORE, GY_ENHANCED_EIS, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_out_raw_get(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_out_raw_t *val) +{ + lsm6dsv16x_fifo_data_out_tag_t fifo_data_out_tag; + uint8_t buff[7]; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_DATA_OUT_TAG, buff, 7); + bytecpy((uint8_t *)&fifo_data_out_tag, &buff[0]); + + switch (fifo_data_out_tag.tag_sensor) + { + case LSM6DSV16X_FIFO_EMPTY: + val->tag = LSM6DSV16X_FIFO_EMPTY; + break; + + case LSM6DSV16X_GY_NC_TAG: + val->tag = LSM6DSV16X_GY_NC_TAG; + break; + + case LSM6DSV16X_XL_NC_TAG: + val->tag = LSM6DSV16X_XL_NC_TAG; + break; + + case LSM6DSV16X_TIMESTAMP_TAG: + val->tag = LSM6DSV16X_TIMESTAMP_TAG; + break; + + case LSM6DSV16X_TEMPERATURE_TAG: + val->tag = LSM6DSV16X_TEMPERATURE_TAG; + break; + + case LSM6DSV16X_CFG_CHANGE_TAG: + val->tag = LSM6DSV16X_CFG_CHANGE_TAG; + break; + + case LSM6DSV16X_XL_NC_T_2_TAG: + val->tag = LSM6DSV16X_XL_NC_T_2_TAG; + break; + + case LSM6DSV16X_XL_NC_T_1_TAG: + val->tag = LSM6DSV16X_XL_NC_T_1_TAG; + break; + + case LSM6DSV16X_XL_2XC_TAG: + val->tag = LSM6DSV16X_XL_2XC_TAG; + break; + + case LSM6DSV16X_XL_3XC_TAG: + val->tag = LSM6DSV16X_XL_3XC_TAG; + break; + + case LSM6DSV16X_GY_NC_T_2_TAG: + val->tag = LSM6DSV16X_GY_NC_T_2_TAG; + break; + + case LSM6DSV16X_GY_NC_T_1_TAG: + val->tag = LSM6DSV16X_GY_NC_T_1_TAG; + break; + + case LSM6DSV16X_GY_2XC_TAG: + val->tag = LSM6DSV16X_GY_2XC_TAG; + break; + + case LSM6DSV16X_GY_3XC_TAG: + val->tag = LSM6DSV16X_GY_3XC_TAG; + break; + + case LSM6DSV16X_SENSORHUB_SLAVE0_TAG: + val->tag = LSM6DSV16X_SENSORHUB_SLAVE0_TAG; + break; + + case LSM6DSV16X_SENSORHUB_SLAVE1_TAG: + val->tag = LSM6DSV16X_SENSORHUB_SLAVE1_TAG; + break; + + case LSM6DSV16X_SENSORHUB_SLAVE2_TAG: + val->tag = LSM6DSV16X_SENSORHUB_SLAVE2_TAG; + break; + + case LSM6DSV16X_SENSORHUB_SLAVE3_TAG: + val->tag = LSM6DSV16X_SENSORHUB_SLAVE3_TAG; + break; + + case LSM6DSV16X_STEP_COUNTER_TAG: + val->tag = LSM6DSV16X_STEP_COUNTER_TAG; + break; + + case LSM6DSV16X_SFLP_GAME_ROTATION_VECTOR_TAG: + val->tag = LSM6DSV16X_SFLP_GAME_ROTATION_VECTOR_TAG; + break; + + case LSM6DSV16X_SFLP_GYROSCOPE_BIAS_TAG: + val->tag = LSM6DSV16X_SFLP_GYROSCOPE_BIAS_TAG; + break; + + case LSM6DSV16X_SFLP_GRAVITY_VECTOR_TAG: + val->tag = LSM6DSV16X_SFLP_GRAVITY_VECTOR_TAG; + break; + + case LSM6DSV16X_SENSORHUB_NACK_TAG: + val->tag = LSM6DSV16X_SENSORHUB_NACK_TAG; + break; + + case LSM6DSV16X_MLC_RESULT_TAG: + val->tag = LSM6DSV16X_MLC_RESULT_TAG; + break; + + case LSM6DSV16X_MLC_FILTER: + val->tag = LSM6DSV16X_MLC_FILTER; + break; + + case LSM6DSV16X_MLC_FEATURE: + val->tag = LSM6DSV16X_MLC_FEATURE; + break; + + case LSM6DSV16X_XL_DUAL_CORE: + val->tag = LSM6DSV16X_XL_DUAL_CORE; + break; + + case LSM6DSV16X_GY_ENHANCED_EIS: + val->tag = LSM6DSV16X_GY_ENHANCED_EIS; + break; + + default: + val->tag = LSM6DSV16X_FIFO_EMPTY; + break; + } + + val->cnt = fifo_data_out_tag.tag_cnt; + + val->data[0] = buff[1]; + val->data[1] = buff[2]; + val->data[2] = buff[3]; + val->data[3] = buff[4]; + val->data[4] = buff[5]; + val->data[5] = buff[6]; + + return ret; +} + +/** + * @brief Batching in FIFO buffer of step counter value.[set] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of step counter value. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_stpcnt_batch_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + + if (ret == 0) + { + emb_func_fifo_en_a.step_counter_fifo_en = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Batching in FIFO buffer of step counter value.[get] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of step counter value. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_stpcnt_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + + *val = emb_func_fifo_en_a.step_counter_fifo_en; + + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Batching in FIFO buffer of machine learning core results.[set] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of machine learning core results. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_mlc_batch_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + + if (ret == 0) + { + emb_func_fifo_en_a.mlc_fifo_en = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Batching in FIFO buffer of machine learning core results.[get] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of machine learning core results. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_mlc_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + + *val = emb_func_fifo_en_a.mlc_fifo_en; + + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enables batching in FIFO buffer of machine learning core filters and features.[set] + * + * @param ctx read / write interface definitions + * @param val Enables batching in FIFO buffer of machine learning core filters and features. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_mlc_filt_batch_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_emb_func_fifo_en_b_t emb_func_fifo_en_b; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); + } + + if (ret == 0) + { + emb_func_fifo_en_b.mlc_filter_feature_fifo_en = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enables batching in FIFO buffer of machine learning core filters and features.[get] + * + * @param ctx read / write interface definitions + * @param val Enables batching in FIFO buffer of machine learning core filters and features. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_mlc_filt_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_emb_func_fifo_en_b_t emb_func_fifo_en_b; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); + } + + *val = emb_func_fifo_en_b.mlc_filter_feature_fifo_en; + + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable FIFO data batching of first slave.[set] + * + * @param ctx read / write interface definitions + * @param val Enable FIFO data batching of first slave. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_batch_sh_slave_0_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_slv0_config_t slv0_config; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); + } + + if (ret == 0) + { + slv0_config.batch_ext_sens_0_en = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable FIFO data batching of first slave.[get] + * + * @param ctx read / write interface definitions + * @param val Enable FIFO data batching of first slave. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_batch_sh_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_slv0_config_t slv0_config; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); + } + + *val = slv0_config.batch_ext_sens_0_en; + + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable FIFO data batching of second slave.[set] + * + * @param ctx read / write interface definitions + * @param val Enable FIFO data batching of second slave. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_batch_sh_slave_1_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_slv1_config_t slv1_config; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV1_CONFIG, (uint8_t *)&slv1_config, 1); + } + + if (ret == 0) + { + slv1_config.batch_ext_sens_1_en = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV1_CONFIG, (uint8_t *)&slv1_config, 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable FIFO data batching of second slave.[get] + * + * @param ctx read / write interface definitions + * @param val Enable FIFO data batching of second slave. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_batch_sh_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_slv1_config_t slv1_config; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV1_CONFIG, (uint8_t *)&slv1_config, 1); + } + + *val = slv1_config.batch_ext_sens_1_en; + + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable FIFO data batching of third slave.[set] + * + * @param ctx read / write interface definitions + * @param val Enable FIFO data batching of third slave. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_batch_sh_slave_2_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_slv2_config_t slv2_config; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV2_CONFIG, (uint8_t *)&slv2_config, 1); + } + + if (ret == 0) + { + slv2_config.batch_ext_sens_2_en = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV2_CONFIG, (uint8_t *)&slv2_config, 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable FIFO data batching of third slave.[get] + * + * @param ctx read / write interface definitions + * @param val Enable FIFO data batching of third slave. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_batch_sh_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_slv2_config_t slv2_config; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV2_CONFIG, (uint8_t *)&slv2_config, 1); + } + + *val = slv2_config.batch_ext_sens_2_en; + + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable FIFO data batching of fourth slave.[set] + * + * @param ctx read / write interface definitions + * @param val Enable FIFO data batching of fourth slave. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_batch_sh_slave_3_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_slv3_config_t slv3_config; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV3_CONFIG, (uint8_t *)&slv3_config, 1); + } + + if (ret == 0) + { + slv3_config.batch_ext_sens_3_en = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV3_CONFIG, (uint8_t *)&slv3_config, 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable FIFO data batching of fourth slave.[get] + * + * @param ctx read / write interface definitions + * @param val Enable FIFO data batching of fourth slave. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_batch_sh_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_slv3_config_t slv3_config; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV3_CONFIG, (uint8_t *)&slv3_config, 1); + } + + *val = slv3_config.batch_ext_sens_3_en; + + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Batching in FIFO buffer of SFLP.[set] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of SFLP values. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_sflp_batch_set(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_sflp_raw_t val) +{ + lsm6dsv16x_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + emb_func_fifo_en_a.sflp_game_fifo_en = val.game_rotation; + emb_func_fifo_en_a.sflp_gravity_fifo_en = val.gravity; + emb_func_fifo_en_a.sflp_gbias_fifo_en = val.gbias; + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_A, + (uint8_t *)&emb_func_fifo_en_a, 1); + } + + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Batching in FIFO buffer of SFLP.[get] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of SFLP values. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fifo_sflp_batch_get(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_sflp_raw_t *val) +{ + lsm6dsv16x_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + + val->game_rotation = emb_func_fifo_en_a.sflp_game_fifo_en; + val->gravity = emb_func_fifo_en_a.sflp_gravity_fifo_en; + val->gbias = emb_func_fifo_en_a.sflp_gbias_fifo_en; + } + + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Filters + * @brief This section group all the functions concerning the + * filters configuration + * @{ + * + */ + +/** + * @brief Protocol anti-spike filters.[set] + * + * @param ctx read / write interface definitions + * @param val AUTO, ALWAYS_ACTIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_filt_anti_spike_set(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_anti_spike_t val) +{ + lsm6dsv16x_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1); + + if (ret == 0) + { + if_cfg.asf_ctrl = (uint8_t)val & 0x01U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Protocol anti-spike filters.[get] + * + * @param ctx read / write interface definitions + * @param val AUTO, ALWAYS_ACTIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_filt_anti_spike_get(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_anti_spike_t *val) +{ + lsm6dsv16x_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1); + switch (if_cfg.asf_ctrl) + { + case LSM6DSV16X_AUTO: + *val = LSM6DSV16X_AUTO; + break; + + case LSM6DSV16X_ALWAYS_ACTIVE: + *val = LSM6DSV16X_ALWAYS_ACTIVE; + break; + + default: + *val = LSM6DSV16X_AUTO; + break; + } + return ret; +} + +/** + * @brief It masks DRDY and Interrupts RQ until filter settling ends.[set] + * + * @param ctx read / write interface definitions + * @param val It masks DRDY and Interrupts RQ until filter settling ends. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_filt_settling_mask_set(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_settling_mask_t val) +{ + lsm6dsv16x_emb_func_cfg_t emb_func_cfg; + lsm6dsv16x_ui_int_ois_t ui_int_ois; + lsm6dsv16x_ctrl4_t ctrl4; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1); + + if (ret == 0) + { + ctrl4.drdy_mask = val.drdy; + + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + } + + if (ret == 0) + { + emb_func_cfg.emb_func_irq_mask_xl_settl = val.irq_xl; + emb_func_cfg.emb_func_irq_mask_g_settl = val.irq_g; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1); + } + + if (ret == 0) + { + ui_int_ois.drdy_mask_ois = val.ois_drdy; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1); + } + + return ret; +} + +/** + * @brief It masks DRDY and Interrupts RQ until filter settling ends.[get] + * + * @param ctx read / write interface definitions + * @param val It masks DRDY and Interrupts RQ until filter settling ends. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_filt_settling_mask_get(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_settling_mask_t *val) +{ + lsm6dsv16x_emb_func_cfg_t emb_func_cfg; + lsm6dsv16x_ui_int_ois_t ui_int_ois; + lsm6dsv16x_ctrl4_t ctrl4; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + } + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1); + } + + val->irq_xl = emb_func_cfg.emb_func_irq_mask_xl_settl; + val->irq_g = emb_func_cfg.emb_func_irq_mask_g_settl; + val->drdy = ctrl4.drdy_mask; + + return ret; +} + +/** + * @brief It masks DRDY and Interrupts RQ until filter settling ends.[set] + * + * @param ctx read / write interface definitions + * @param val It masks DRDY and Interrupts RQ until filter settling ends from OIS interface. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_filt_ois_settling_mask_set(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_ois_settling_mask_t val) +{ + lsm6dsv16x_spi2_int_ois_t spi2_int_ois; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); + + if (ret == 0) + { + spi2_int_ois.drdy_mask_ois = val.ois_drdy; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); + } + + return ret; +} + +/** + * @brief It masks DRDY and Interrupts RQ until filter settling ends.[get] + * + * @param ctx read / write interface definitions + * @param val It masks DRDY and Interrupts RQ until filter settling ends. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_filt_ois_settling_mask_get(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_ois_settling_mask_t *val) +{ + + lsm6dsv16x_spi2_int_ois_t spi2_int_ois; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); + val->ois_drdy = spi2_int_ois.drdy_mask_ois; + + return ret; +} + +/** + * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[set] + * + * @param ctx read / write interface definitions + * @param val GY_ULTRA_LIGHT, GY_VERY_LIGHT, GY_LIGHT, GY_MEDIUM, GY_STRONG, GY_VERY_STRONG, GY_AGGRESSIVE, GY_XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_filt_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_gy_lp1_bandwidth_t val) +{ + lsm6dsv16x_ctrl6_t ctrl6; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL6, (uint8_t *)&ctrl6, 1); + if (ret == 0) + { + ctrl6.lpf1_g_bw = (uint8_t)val & 0x0Fu; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL6, (uint8_t *)&ctrl6, 1); + } + + return ret; +} + +/** + * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[get] + * + * @param ctx read / write interface definitions + * @param val GY_ULTRA_LIGHT, GY_VERY_LIGHT, GY_LIGHT, GY_MEDIUM, GY_STRONG, GY_VERY_STRONG, GY_AGGRESSIVE, GY_XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_filt_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_gy_lp1_bandwidth_t *val) +{ + lsm6dsv16x_ctrl6_t ctrl6; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL6, (uint8_t *)&ctrl6, 1); + switch (ctrl6.lpf1_g_bw) + { + case LSM6DSV16X_GY_ULTRA_LIGHT: + *val = LSM6DSV16X_GY_ULTRA_LIGHT; + break; + + case LSM6DSV16X_GY_VERY_LIGHT: + *val = LSM6DSV16X_GY_VERY_LIGHT; + break; + + case LSM6DSV16X_GY_LIGHT: + *val = LSM6DSV16X_GY_LIGHT; + break; + + case LSM6DSV16X_GY_MEDIUM: + *val = LSM6DSV16X_GY_MEDIUM; + break; + + case LSM6DSV16X_GY_STRONG: + *val = LSM6DSV16X_GY_STRONG; + break; + + case LSM6DSV16X_GY_VERY_STRONG: + *val = LSM6DSV16X_GY_VERY_STRONG; + break; + + case LSM6DSV16X_GY_AGGRESSIVE: + *val = LSM6DSV16X_GY_AGGRESSIVE; + break; + + case LSM6DSV16X_GY_XTREME: + *val = LSM6DSV16X_GY_XTREME; + break; + + default: + *val = LSM6DSV16X_GY_ULTRA_LIGHT; + break; + } + return ret; +} + +/** + * @brief It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW.[set] + * + * @param ctx read / write interface definitions + * @param val It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_filt_gy_lp1_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_ctrl7_t ctrl7; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret == 0) + { + ctrl7.lpf1_g_en = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL7, (uint8_t *)&ctrl7, 1); + } + + return ret; +} + + +/** + * @brief It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW.[get] + * + * @param ctx read / write interface definitions + * @param val It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_filt_gy_lp1_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_ctrl7_t ctrl7; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL7, (uint8_t *)&ctrl7, 1); + *val = ctrl7.lpf1_g_en; + + return ret; +} + +/** + * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[set] + * + * @param ctx read / write interface definitions + * @param val XL_ULTRA_LIGHT, XL_VERY_LIGHT, XL_LIGHT, XL_MEDIUM, XL_STRONG, XL_VERY_STRONG, XL_AGGRESSIVE, XL_XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_filt_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_xl_lp2_bandwidth_t val) +{ + lsm6dsv16x_ctrl8_t ctrl8; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret == 0) + { + ctrl8.hp_lpf2_xl_bw = (uint8_t)val & 0x07U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL8, (uint8_t *)&ctrl8, 1); + } + + return ret; +} + +/** + * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[get] + * + * @param ctx read / write interface definitions + * @param val XL_ULTRA_LIGHT, XL_VERY_LIGHT, XL_LIGHT, XL_MEDIUM, XL_STRONG, XL_VERY_STRONG, XL_AGGRESSIVE, XL_XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_filt_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_xl_lp2_bandwidth_t *val) +{ + lsm6dsv16x_ctrl8_t ctrl8; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL8, (uint8_t *)&ctrl8, 1); + switch (ctrl8.hp_lpf2_xl_bw) + { + case LSM6DSV16X_XL_ULTRA_LIGHT: + *val = LSM6DSV16X_XL_ULTRA_LIGHT; + break; + + case LSM6DSV16X_XL_VERY_LIGHT: + *val = LSM6DSV16X_XL_VERY_LIGHT; + break; + + case LSM6DSV16X_XL_LIGHT: + *val = LSM6DSV16X_XL_LIGHT; + break; + + case LSM6DSV16X_XL_MEDIUM: + *val = LSM6DSV16X_XL_MEDIUM; + break; + + case LSM6DSV16X_XL_STRONG: + *val = LSM6DSV16X_XL_STRONG; + break; + + case LSM6DSV16X_XL_VERY_STRONG: + *val = LSM6DSV16X_XL_VERY_STRONG; + break; + + case LSM6DSV16X_XL_AGGRESSIVE: + *val = LSM6DSV16X_XL_AGGRESSIVE; + break; + + case LSM6DSV16X_XL_XTREME: + *val = LSM6DSV16X_XL_XTREME; + break; + + default: + *val = LSM6DSV16X_XL_ULTRA_LIGHT; + break; + } + return ret; +} + +/** + * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[set] + * + * @param ctx read / write interface definitions + * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_filt_xl_lp2_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.lpf2_xl_en = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[get] + * + * @param ctx read / write interface definitions + * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_filt_xl_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1); + *val = ctrl9.lpf2_xl_en; + + return ret; +} + +/** + * @brief Accelerometer slope filter / high-pass filter selection.[set] + * + * @param ctx read / write interface definitions + * @param val Accelerometer slope filter / high-pass filter selection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_filt_xl_hp_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.hp_slope_xl_en = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Accelerometer slope filter / high-pass filter selection.[get] + * + * @param ctx read / write interface definitions + * @param val Accelerometer slope filter / high-pass filter selection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_filt_xl_hp_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1); + *val = ctrl9.hp_slope_xl_en; + + return ret; +} + +/** + * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[set] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_filt_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.xl_fastsettl_mode = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[get] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_filt_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1); + *val = ctrl9.xl_fastsettl_mode; + + return ret; +} + +/** + * @brief Accelerometer high-pass filter mode.[set] + * + * @param ctx read / write interface definitions + * @param val HP_MD_NORMAL, HP_MD_REFERENCE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_filt_xl_hp_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_xl_hp_mode_t val) +{ + lsm6dsv16x_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.hp_ref_mode_xl = (uint8_t)val & 0x01U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Accelerometer high-pass filter mode.[get] + * + * @param ctx read / write interface definitions + * @param val HP_MD_NORMAL, HP_MD_REFERENCE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_filt_xl_hp_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_xl_hp_mode_t *val) +{ + lsm6dsv16x_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1); + switch (ctrl9.hp_ref_mode_xl) + { + case LSM6DSV16X_HP_MD_NORMAL: + *val = LSM6DSV16X_HP_MD_NORMAL; + break; + + case LSM6DSV16X_HP_MD_REFERENCE: + *val = LSM6DSV16X_HP_MD_REFERENCE; + break; + + default: + *val = LSM6DSV16X_HP_MD_NORMAL; + break; + } + return ret; +} + +/** + * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[set] + * + * @param ctx read / write interface definitions + * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS, WK_FEED_LP_WITH_OFFSET, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_filt_wkup_act_feed_set(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_wkup_act_feed_t val) +{ + lsm6dsv16x_wake_up_ths_t wake_up_ths; + lsm6dsv16x_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + if (ret == 0) + { + tap_cfg0.slope_fds = (uint8_t)val & 0x01U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + if (ret == 0) + { + wake_up_ths.usr_off_on_wu = ((uint8_t)val & 0x02U) >> 1; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + } + + return ret; +} + +/** + * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[get] + * + * @param ctx read / write interface definitions + * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS, WK_FEED_LP_WITH_OFFSET, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_filt_wkup_act_feed_get(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_wkup_act_feed_t *val) +{ + lsm6dsv16x_wake_up_ths_t wake_up_ths; + lsm6dsv16x_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + switch ((wake_up_ths.usr_off_on_wu << 1) + tap_cfg0.slope_fds) + { + case LSM6DSV16X_WK_FEED_SLOPE: + *val = LSM6DSV16X_WK_FEED_SLOPE; + break; + + case LSM6DSV16X_WK_FEED_HIGH_PASS: + *val = LSM6DSV16X_WK_FEED_HIGH_PASS; + break; + + case LSM6DSV16X_WK_FEED_LP_WITH_OFFSET: + *val = LSM6DSV16X_WK_FEED_LP_WITH_OFFSET; + break; + + default: + *val = LSM6DSV16X_WK_FEED_SLOPE; + break; + } + return ret; +} + +/** + * @brief Mask hw function triggers when xl is settling.[set] + * + * @param ctx read / write interface definitions + * @param val 0 or 1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_mask_trigger_xl_settl_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + + if (ret == 0) + { + tap_cfg0.hw_func_mask_xl_settl = val & 0x01U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + return ret; +} + +/** + * @brief Mask hw function triggers when xl is settling.[get] + * + * @param ctx read / write interface definitions + * @param val 0 or 1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_mask_trigger_xl_settl_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + *val = tap_cfg0.hw_func_mask_xl_settl; + + return ret; +} + +/** + * @brief LPF2 filter on 6D (sixd) function selection.[set] + * + * @param ctx read / write interface definitions + * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_filt_sixd_feed_set(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_sixd_feed_t val) +{ + lsm6dsv16x_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + + if (ret == 0) + { + tap_cfg0.low_pass_on_6d = (uint8_t)val & 0x01U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + return ret; +} + +/** + * @brief LPF2 filter on 6D (sixd) function selection.[get] + * + * @param ctx read / write interface definitions + * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_filt_sixd_feed_get(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_sixd_feed_t *val) +{ + lsm6dsv16x_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + + switch (tap_cfg0.low_pass_on_6d) + { + case LSM6DSV16X_SIXD_FEED_ODR_DIV_2: + *val = LSM6DSV16X_SIXD_FEED_ODR_DIV_2; + break; + + case LSM6DSV16X_SIXD_FEED_LOW_PASS: + *val = LSM6DSV16X_SIXD_FEED_LOW_PASS; + break; + + default: + *val = LSM6DSV16X_SIXD_FEED_ODR_DIV_2; + break; + } + return ret; +} + +/** + * @brief Gyroscope digital LPF_EIS filter bandwidth selection.[set] + * + * @param ctx read / write interface definitions + * @param val EIS_LP_NORMAL, EIS_LP_LIGHT, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_filt_gy_eis_lp_bandwidth_set(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_gy_eis_lp_bandwidth_t val) +{ + lsm6dsv16x_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + + if (ret == 0) + { + ctrl_eis.lpf_g_eis_bw = (uint8_t)val & 0x01U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + } + + return ret; +} + +/** + * @brief Gyroscope digital LPF_EIS filter bandwidth selection.[get] + * + * @param ctx read / write interface definitions + * @param val EIS_LP_NORMAL, EIS_LP_LIGHT, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_filt_gy_eis_lp_bandwidth_get(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_gy_eis_lp_bandwidth_t *val) +{ + lsm6dsv16x_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + + switch (ctrl_eis.lpf_g_eis_bw) + { + case LSM6DSV16X_EIS_LP_NORMAL: + *val = LSM6DSV16X_EIS_LP_NORMAL; + break; + + case LSM6DSV16X_EIS_LP_LIGHT: + *val = LSM6DSV16X_EIS_LP_LIGHT; + break; + + default: + *val = LSM6DSV16X_EIS_LP_NORMAL; + break; + } + return ret; +} + +/** + * @brief Gyroscope OIS digital LPF1 filter bandwidth selection. This function works also on OIS interface (SPI2_CTRL2_OIS = UI_CTRL2_OIS).[set] + * + * @param ctx read / write interface definitions + * @param val OIS_GY_LP_NORMAL, OIS_GY_LP_STRONG, OIS_GY_LP_AGGRESSIVE, OIS_GY_LP_LIGHT, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_filt_gy_ois_lp_bandwidth_set(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_gy_ois_lp_bandwidth_t val) +{ + lsm6dsv16x_ui_ctrl2_ois_t ui_ctrl2_ois; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1); + + if (ret == 0) + { + ui_ctrl2_ois.lpf1_g_ois_bw = (uint8_t)val & 0x03U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1); + } + + return ret; +} + +/** + * @brief Gyroscope OIS digital LPF1 filter bandwidth selection. This function works also on OIS interface (SPI2_CTRL2_OIS = UI_CTRL2_OIS).[get] + * + * @param ctx read / write interface definitions + * @param val OIS_GY_LP_NORMAL, OIS_GY_LP_STRONG, OIS_GY_LP_AGGRESSIVE, OIS_GY_LP_LIGHT, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_filt_gy_ois_lp_bandwidth_get(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_gy_ois_lp_bandwidth_t *val) +{ + + lsm6dsv16x_ui_ctrl2_ois_t ui_ctrl2_ois; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1); + + switch (ui_ctrl2_ois.lpf1_g_ois_bw) + { + case LSM6DSV16X_OIS_GY_LP_NORMAL: + *val = LSM6DSV16X_OIS_GY_LP_NORMAL; + break; + + case LSM6DSV16X_OIS_GY_LP_STRONG: + *val = LSM6DSV16X_OIS_GY_LP_STRONG; + break; + + case LSM6DSV16X_OIS_GY_LP_AGGRESSIVE: + *val = LSM6DSV16X_OIS_GY_LP_AGGRESSIVE; + break; + + case LSM6DSV16X_OIS_GY_LP_LIGHT: + *val = LSM6DSV16X_OIS_GY_LP_LIGHT; + break; + + default: + *val = LSM6DSV16X_OIS_GY_LP_NORMAL; + break; + } + return ret; +} + +/** + * @brief Selects accelerometer OIS channel bandwidth. This function works also on OIS interface (SPI2_CTRL3_OIS = UI_CTRL3_OIS).[set] + * + * @param ctx read / write interface definitions + * @param val OIS_XL_LP_ULTRA_LIGHT, OIS_XL_LP_VERY_LIGHT, OIS_XL_LP_LIGHT, OIS_XL_LP_NORMAL, OIS_XL_LP_STRONG, OIS_XL_LP_VERY_STRONG, OIS_XL_LP_AGGRESSIVE, OIS_XL_LP_XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_filt_xl_ois_lp_bandwidth_set(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_xl_ois_lp_bandwidth_t val) +{ + lsm6dsv16x_ui_ctrl3_ois_t ui_ctrl3_ois; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1); + + if (ret == 0) + { + ui_ctrl3_ois.lpf_xl_ois_bw = (uint8_t)val & 0x07U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1); + } + + return ret; +} + +/** + * @brief Selects accelerometer OIS channel bandwidth. This function works also on OIS interface (SPI2_CTRL3_OIS = UI_CTRL3_OIS).[get] + * + * @param ctx read / write interface definitions + * @param val OIS_XL_LP_ULTRA_LIGHT, OIS_XL_LP_VERY_LIGHT, OIS_XL_LP_LIGHT, OIS_XL_LP_NORMAL, OIS_XL_LP_STRONG, OIS_XL_LP_VERY_STRONG, OIS_XL_LP_AGGRESSIVE, OIS_XL_LP_XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_filt_xl_ois_lp_bandwidth_get(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_xl_ois_lp_bandwidth_t *val) +{ + lsm6dsv16x_ui_ctrl3_ois_t ui_ctrl3_ois; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1); + + switch (ui_ctrl3_ois.lpf_xl_ois_bw) + { + case LSM6DSV16X_OIS_XL_LP_ULTRA_LIGHT: + *val = LSM6DSV16X_OIS_XL_LP_ULTRA_LIGHT; + break; + + case LSM6DSV16X_OIS_XL_LP_VERY_LIGHT: + *val = LSM6DSV16X_OIS_XL_LP_VERY_LIGHT; + break; + + case LSM6DSV16X_OIS_XL_LP_LIGHT: + *val = LSM6DSV16X_OIS_XL_LP_LIGHT; + break; + + case LSM6DSV16X_OIS_XL_LP_NORMAL: + *val = LSM6DSV16X_OIS_XL_LP_NORMAL; + break; + + case LSM6DSV16X_OIS_XL_LP_STRONG: + *val = LSM6DSV16X_OIS_XL_LP_STRONG; + break; + + case LSM6DSV16X_OIS_XL_LP_VERY_STRONG: + *val = LSM6DSV16X_OIS_XL_LP_VERY_STRONG; + break; + + case LSM6DSV16X_OIS_XL_LP_AGGRESSIVE: + *val = LSM6DSV16X_OIS_XL_LP_AGGRESSIVE; + break; + + case LSM6DSV16X_OIS_XL_LP_XTREME: + *val = LSM6DSV16X_OIS_XL_LP_XTREME; + break; + + default: + *val = LSM6DSV16X_OIS_XL_LP_ULTRA_LIGHT; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Finite State Machine (FSM) + * @brief This section groups all the functions that manage the + * state_machine. + * @{ + * + */ + +/** + * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[set] + * + * @param ctx read / write interface definitions + * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fsm_permission_set(stmdev_ctx_t *ctx, + lsm6dsv16x_fsm_permission_t val) +{ + lsm6dsv16x_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + if (ret == 0) + { + func_cfg_access.fsm_wr_ctrl_en = (uint8_t)val & 0x01U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[get] + * + * @param ctx read / write interface definitions + * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fsm_permission_get(stmdev_ctx_t *ctx, + lsm6dsv16x_fsm_permission_t *val) +{ + lsm6dsv16x_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + switch (func_cfg_access.fsm_wr_ctrl_en) + { + case LSM6DSV16X_PROTECT_CTRL_REGS: + *val = LSM6DSV16X_PROTECT_CTRL_REGS; + break; + + case LSM6DSV16X_WRITE_CTRL_REG: + *val = LSM6DSV16X_WRITE_CTRL_REG; + break; + + default: + *val = LSM6DSV16X_PROTECT_CTRL_REGS; + break; + } + return ret; +} + +/** + * @brief Get the FSM permission status + * + * @param ctx read / write interface definitions + * @param val 0: All reg writable from std if - 1: some regs are under FSM control. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fsm_permission_status(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_ctrl_status_t ctrl_status; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL_STATUS, (uint8_t *)&ctrl_status, 1); + + *val = ctrl_status.fsm_wr_ctrl_status; + + return ret; +} + +/** + * @brief Enable Finite State Machine (FSM) feature.[set] + * + * @param ctx read / write interface definitions + * @param val Enable Finite State Machine (FSM) feature. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fsm_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_fsm_mode_t val) +{ + lsm6dsv16x_emb_func_en_b_t emb_func_en_b; + lsm6dsv16x_fsm_enable_t fsm_enable; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); + } + if ((val.fsm1_en | val.fsm2_en | val.fsm1_en | val.fsm1_en + | val.fsm1_en | val.fsm2_en | val.fsm1_en | val.fsm1_en) == PROPERTY_ENABLE) + { + emb_func_en_b.fsm_en = PROPERTY_ENABLE; + } + else + { + emb_func_en_b.fsm_en = PROPERTY_DISABLE; + } + if (ret == 0) + { + fsm_enable.fsm1_en = val.fsm1_en; + fsm_enable.fsm2_en = val.fsm2_en; + fsm_enable.fsm3_en = val.fsm3_en; + fsm_enable.fsm4_en = val.fsm4_en; + fsm_enable.fsm5_en = val.fsm5_en; + fsm_enable.fsm6_en = val.fsm6_en; + fsm_enable.fsm7_en = val.fsm7_en; + fsm_enable.fsm8_en = val.fsm8_en; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); + } + if (ret == 0) + { + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable Finite State Machine (FSM) feature.[get] + * + * @param ctx read / write interface definitions + * @param val Enable Finite State Machine (FSM) feature. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fsm_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_fsm_mode_t *val) +{ + lsm6dsv16x_fsm_enable_t fsm_enable; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + val->fsm1_en = fsm_enable.fsm1_en; + val->fsm2_en = fsm_enable.fsm2_en; + val->fsm3_en = fsm_enable.fsm3_en; + val->fsm4_en = fsm_enable.fsm4_en; + val->fsm5_en = fsm_enable.fsm5_en; + val->fsm6_en = fsm_enable.fsm6_en; + val->fsm7_en = fsm_enable.fsm7_en; + val->fsm8_en = fsm_enable.fsm8_en; + + return ret; +} + +/** + * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[set] + * + * @param ctx read / write interface definitions + * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fsm_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FSM_LONG_COUNTER_L, (uint8_t *)&buff[0], 2); + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[get] + * + * @param ctx read / write interface definitions + * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fsm_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FSM_LONG_COUNTER_L, &buff[0], 2); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief FSM output registers[get] + * + * @param ctx read / write interface definitions + * @param val FSM output registers + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fsm_out_get(stmdev_ctx_t *ctx, lsm6dsv16x_fsm_out_t *val) +{ + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FSM_OUTS1, (uint8_t *)val, 8); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Finite State Machine Output Data Rate (ODR) configuration.[set] + * + * @param ctx read / write interface definitions + * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fsm_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv16x_fsm_data_rate_t val) +{ + lsm6dsv16x_fsm_odr_t fsm_odr; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FSM_ODR, (uint8_t *)&fsm_odr, 1); + } + + if (ret == 0) + { + fsm_odr.fsm_odr = (uint8_t)val & 0x07U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FSM_ODR, (uint8_t *)&fsm_odr, 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Finite State Machine Output Data Rate (ODR) configuration.[get] + * + * @param ctx read / write interface definitions + * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fsm_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv16x_fsm_data_rate_t *val) +{ + lsm6dsv16x_fsm_odr_t fsm_odr; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FSM_ODR, (uint8_t *)&fsm_odr, 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + + switch (fsm_odr.fsm_odr) + { + case LSM6DSV16X_FSM_15Hz: + *val = LSM6DSV16X_FSM_15Hz; + break; + + case LSM6DSV16X_FSM_30Hz: + *val = LSM6DSV16X_FSM_30Hz; + break; + + case LSM6DSV16X_FSM_60Hz: + *val = LSM6DSV16X_FSM_60Hz; + break; + + case LSM6DSV16X_FSM_120Hz: + *val = LSM6DSV16X_FSM_120Hz; + break; + + case LSM6DSV16X_FSM_240Hz: + *val = LSM6DSV16X_FSM_240Hz; + break; + + case LSM6DSV16X_FSM_480Hz: + *val = LSM6DSV16X_FSM_480Hz; + break; + + case LSM6DSV16X_FSM_960Hz: + *val = LSM6DSV16X_FSM_960Hz; + break; + + default: + *val = LSM6DSV16X_FSM_15Hz; + break; + } + return ret; +} + +/* + * Original conversion routines taken from: https://github.com/numpy/numpy + * + * uint16_t npy_floatbits_to_halfbits(uint32_t f); + * uint16_t npy_float_to_half(float_t f); + * + * Released under BSD-3-Clause License + */ +static uint16_t npy_floatbits_to_halfbits(uint32_t f) +{ + uint32_t f_exp, f_sig; + uint16_t h_sgn, h_exp, h_sig; + + h_sgn = (uint16_t)((f & 0x80000000u) >> 16); + f_exp = (f & 0x7f800000u); + + /* Exponent overflow/NaN converts to signed inf/NaN */ + if (f_exp >= 0x47800000u) + { + if (f_exp == 0x7f800000u) + { + /* Inf or NaN */ + f_sig = (f & 0x007fffffu); + if (f_sig != 0U) + { + /* NaN - propagate the flag in the significand... */ + uint16_t ret = (uint16_t)(0x7c00u + (f_sig >> 13)); + /* ...but make sure it stays a NaN */ + if (ret == 0x7c00u) + { + ret++; + } + return h_sgn + ret; + } + else + { + /* signed inf */ + return (uint16_t)(h_sgn + 0x7c00u); + } + } + else + { + /* overflow to signed inf */ +#if NPY_HALF_GENERATE_OVERFLOW + npy_set_floatstatus_overflow(); +#endif + return (uint16_t)(h_sgn + 0x7c00u); + } + } + + /* Exponent underflow converts to a subnormal half or signed zero */ + if (f_exp <= 0x38000000u) + { + /* + * Signed zeros, subnormal floats, and floats with small + * exponents all convert to signed zero half-floats. + */ + if (f_exp < 0x33000000u) + { +#if NPY_HALF_GENERATE_UNDERFLOW + /* If f != 0, it underflowed to 0 */ + if ((f & 0x7fffffff) != 0) + { + npy_set_floatstatus_underflow(); + } +#endif + return h_sgn; + } + /* Make the subnormal significand */ + f_exp >>= 23; + f_sig = (0x00800000u + (f & 0x007fffffu)); +#if NPY_HALF_GENERATE_UNDERFLOW + /* If it's not exactly represented, it underflowed */ + if ((f_sig & (((uint32_t)1 << (126 - f_exp)) - 1)) != 0) + { + npy_set_floatstatus_underflow(); + } +#endif + /* + * Usually the significand is shifted by 13. For subnormals an + * additional shift needs to occur. This shift is one for the largest + * exponent giving a subnormal `f_exp = 0x38000000 >> 23 = 112`, which + * offsets the new first bit. At most the shift can be 1+10 bits. + */ + f_sig >>= (113U - f_exp); + /* Handle rounding by adding 1 to the bit beyond half precision */ +#if NPY_HALF_ROUND_TIES_TO_EVEN + /* + * If the last bit in the half significand is 0 (already even), and + * the remaining bit pattern is 1000...0, then we do not add one + * to the bit after the half significand. However, the (113 - f_exp) + * shift can lose up to 11 bits, so the || checks them in the original. + * In all other cases, we can just add one. + */ + if (((f_sig & 0x00003fffu) != 0x00001000u) || (f & 0x000007ffu)) + { + f_sig += 0x00001000u; + } +#else + f_sig += 0x00001000u; +#endif + h_sig = (uint16_t)(f_sig >> 13); + /* + * If the rounding causes a bit to spill into h_exp, it will + * increment h_exp from zero to one and h_sig will be zero. + * This is the correct result. + */ + return (uint16_t)(h_sgn + h_sig); + } + + /* Regular case with no overflow or underflow */ + h_exp = (uint16_t)((f_exp - 0x38000000u) >> 13); + /* Handle rounding by adding 1 to the bit beyond half precision */ + f_sig = (f & 0x007fffffu); +#if NPY_HALF_ROUND_TIES_TO_EVEN + /* + * If the last bit in the half significand is 0 (already even), and + * the remaining bit pattern is 1000...0, then we do not add one + * to the bit after the half significand. In all other cases, we do. + */ + if ((f_sig & 0x00003fffu) != 0x00001000u) + { + f_sig += 0x00001000u; + } +#else + f_sig += 0x00001000u; +#endif + h_sig = (uint16_t)(f_sig >> 13); + /* + * If the rounding causes a bit to spill into h_exp, it will + * increment h_exp by one and h_sig will be zero. This is the + * correct result. h_exp may increment to 15, at greatest, in + * which case the result overflows to a signed inf. + */ +#if NPY_HALF_GENERATE_OVERFLOW + h_sig += h_exp; + if (h_sig == 0x7c00u) + { + npy_set_floatstatus_overflow(); + } + return h_sgn + h_sig; +#else + return h_sgn + h_exp + h_sig; +#endif +} + +static uint16_t npy_float_to_half(float_t f) +{ + union + { + float_t f; + uint32_t fbits; + } conv; + conv.f = f; + return npy_floatbits_to_halfbits(conv.fbits); +} + +/** + * @brief SFLP GBIAS value. The register value is expressed as half-precision + * floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent + * bits; F: 10 fraction bits).[set] + * + * @param ctx read / write interface definitions + * @param val GBIAS x/y/z val. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_sflp_game_gbias_set(stmdev_ctx_t *ctx, + lsm6dsv16x_sflp_gbias_t *val) +{ + lsm6dsv16x_sflp_data_rate_t sflp_odr; + lsm6dsv16x_emb_func_exec_status_t emb_func_sts; + lsm6dsv16x_data_ready_t drdy; + lsm6dsv16x_xl_full_scale_t xl_fs; + lsm6dsv16x_ctrl10_t ctrl10; + uint8_t master_config; + uint8_t emb_func_en_saved[2]; + uint8_t conf_saved[2]; + uint8_t reg_zero[2] = {0x0, 0x0}; + uint16_t gbias_hf[3]; + float_t k = 0.005f; + int16_t xl_data[3]; + int32_t data_tmp; + uint8_t *data_ptr = (uint8_t *)&data_tmp; + uint8_t i, j; + int32_t ret; + + ret = lsm6dsv16x_sflp_data_rate_get(ctx, &sflp_odr); + if (ret != 0) + { + return ret; + } + + /* Calculate k factor */ + switch (sflp_odr) + { + default: + case LSM6DSV16X_SFLP_15Hz: + k = 0.04f; + break; + case LSM6DSV16X_SFLP_30Hz: + k = 0.02f; + break; + case LSM6DSV16X_SFLP_60Hz: + k = 0.01f; + break; + case LSM6DSV16X_SFLP_120Hz: + k = 0.005f; + break; + case LSM6DSV16X_SFLP_240Hz: + k = 0.0025f; + break; + case LSM6DSV16X_SFLP_480Hz: + k = 0.00125f; + break; + } + + /* compute gbias as half precision float in order to be put in embedded advanced feature register */ + gbias_hf[0] = npy_float_to_half(val->gbias_x * (3.14159265358979323846f / 180.0f) / k); + gbias_hf[1] = npy_float_to_half(val->gbias_y * (3.14159265358979323846f / 180.0f) / k); + gbias_hf[2] = npy_float_to_half(val->gbias_z * (3.14159265358979323846f / 180.0f) / k); + + /* Save sensor configuration and set high-performance mode (if the sensor is in power-down mode, turn it on) */ + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL1, conf_saved, 2); + ret += lsm6dsv16x_xl_mode_set(ctx, LSM6DSV16X_XL_HIGH_PERFORMANCE_MD); + ret += lsm6dsv16x_gy_mode_set(ctx, LSM6DSV16X_GY_HIGH_PERFORMANCE_MD); + if (((uint8_t)conf_saved[0] & 0x0FU) == (uint8_t)LSM6DSV16X_ODR_OFF) + { + ret += lsm6dsv16x_xl_data_rate_set(ctx, LSM6DSV16X_ODR_AT_120Hz); + } + + /* Make sure to turn the sensor-hub master off */ + ret += lsm6dsv16x_sh_master_get(ctx, &master_config); + ret += lsm6dsv16x_sh_master_set(ctx, 0); + + /* disable algos */ + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, emb_func_en_saved, 2); + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, reg_zero, 2); + do + { + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EXEC_STATUS, + (uint8_t *)&emb_func_sts, 1); + } while (emb_func_sts.emb_func_endop != 1U); + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + // enable gbias setting + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1); + ctrl10.emb_func_debug = 1; + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1); + + /* enable algos */ + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + emb_func_en_saved[0] |= 0x02U; /* force SFLP GAME en */ + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, emb_func_en_saved, + 2); + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + ret += lsm6dsv16x_xl_full_scale_get(ctx, &xl_fs); + + /* Read XL data */ + do + { + ret += lsm6dsv16x_flag_data_ready_get(ctx, &drdy); + } while (drdy.drdy_xl != 1U); + ret += lsm6dsv16x_acceleration_raw_get(ctx, xl_data); + + /* force sflp initialization */ + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); + for (i = 0; i < 3U; i++) + { + j = 0; + data_tmp = (int32_t)xl_data[i]; + data_tmp <<= xl_fs; // shift based on current fs + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SENSOR_HUB_1 + 3U * i, + &data_ptr[j++], 1); + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SENSOR_HUB_2 + 3U * i, + &data_ptr[j++], 1); + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SENSOR_HUB_3 + 3U * i, &data_ptr[j], + 1); + } + for (i = 0; i < 3U; i++) + { + j = 0; + data_tmp = 0; + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SENSOR_HUB_10 + 3U * i, + &data_ptr[j++], 1); + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SENSOR_HUB_11 + 3U * i, + &data_ptr[j++], 1); + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SENSOR_HUB_12 + 3U * i, &data_ptr[j], + 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + // wait end_op (and at least 30 us) + ctx->mdelay(1); + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + do + { + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EXEC_STATUS, + (uint8_t *)&emb_func_sts, 1); + } while (emb_func_sts.emb_func_endop != 1U); + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + /* write gbias in embedded advanced features registers */ + ret += lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_SFLP_GAME_GBIASX_L, + (uint8_t *)gbias_hf, 6); + + /* reload previous sensor configuration */ + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL1, conf_saved, 2); + + // disable gbias setting + ctrl10.emb_func_debug = 0; + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1); + + /* reload previous master configuration */ + ret += lsm6dsv16x_sh_master_set(ctx, master_config); + + return ret; +} + +/** + * @brief External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB).[set] + * + * @param ctx read / write interface definitions + * @param val External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fsm_ext_sens_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_FSM_EXT_SENSITIVITY_L, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB).[get] + * + * @param ctx read / write interface definitions + * @param val External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fsm_ext_sens_sensitivity_get(stmdev_ctx_t *ctx, + uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_FSM_EXT_SENSITIVITY_L, &buff[0], 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set] + * + * @param ctx read / write interface definitions + * @param val External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fsm_ext_sens_offset_set(stmdev_ctx_t *ctx, + lsm6dsv16x_xl_fsm_ext_sens_offset_t val) +{ + uint8_t buff[6]; + int32_t ret; + + buff[1] = (uint8_t)(val.x / 256U); + buff[0] = (uint8_t)(val.x - (buff[1] * 256U)); + buff[3] = (uint8_t)(val.y / 256U); + buff[2] = (uint8_t)(val.y - (buff[3] * 256U)); + buff[5] = (uint8_t)(val.z / 256U); + buff[4] = (uint8_t)(val.z - (buff[5] * 256U)); + ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_FSM_EXT_OFFX_L, (uint8_t *)&buff[0], 6); + + return ret; +} + +/** + * @brief External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get] + * + * @param ctx read / write interface definitions + * @param val External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fsm_ext_sens_offset_get(stmdev_ctx_t *ctx, + lsm6dsv16x_xl_fsm_ext_sens_offset_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_FSM_EXT_OFFX_L, &buff[0], 6); + + val->x = buff[1]; + val->x = (val->x * 256U) + buff[0]; + val->y = buff[3]; + val->y = (val->y * 256U) + buff[2]; + val->z = buff[5]; + val->z = (val->z * 256U) + buff[4]; + + return ret; +} + +/** + * @brief External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set] + * + * @param ctx read / write interface definitions + * @param val External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fsm_ext_sens_matrix_set(stmdev_ctx_t *ctx, + lsm6dsv16x_xl_fsm_ext_sens_matrix_t val) +{ + uint8_t buff[12]; + int32_t ret; + + buff[1] = (uint8_t)(val.xx / 256U); + buff[0] = (uint8_t)(val.xx - (buff[1] * 256U)); + buff[3] = (uint8_t)(val.xy / 256U); + buff[2] = (uint8_t)(val.xy - (buff[3] * 256U)); + buff[5] = (uint8_t)(val.xz / 256U); + buff[4] = (uint8_t)(val.xz - (buff[5] * 256U)); + buff[7] = (uint8_t)(val.yy / 256U); + buff[6] = (uint8_t)(val.yy - (buff[7] * 256U)); + buff[9] = (uint8_t)(val.yz / 256U); + buff[8] = (uint8_t)(val.yz - (buff[9] * 256U)); + buff[11] = (uint8_t)(val.zz / 256U); + buff[10] = (uint8_t)(val.zz - (buff[11] * 256U)); + ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_FSM_EXT_MATRIX_XX_L, (uint8_t *)&buff[0], 12); + + return ret; +} + +/** + * @brief External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get] + * + * @param ctx read / write interface definitions + * @param val External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fsm_ext_sens_matrix_get(stmdev_ctx_t *ctx, + lsm6dsv16x_xl_fsm_ext_sens_matrix_t *val) +{ + uint8_t buff[12]; + int32_t ret; + + ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_FSM_EXT_MATRIX_XX_L, &buff[0], 12); + + val->xx = buff[1]; + val->xx = (val->xx * 256U) + buff[0]; + val->xy = buff[3]; + val->xy = (val->xy * 256U) + buff[2]; + val->xz = buff[5]; + val->xz = (val->xz * 256U) + buff[4]; + val->yy = buff[7]; + val->yy = (val->yy * 256U) + buff[6]; + val->yz = buff[9]; + val->yz = (val->yz * 256U) + buff[8]; + val->zz = buff[11]; + val->zz = (val->zz * 256U) + buff[10]; + + return ret; +} + +/** + * @brief External sensor z-axis coordinates rotation.[set] + * + * @param ctx read / write interface definitions + * @param val Z_EQ_Y, Z_EQ_MIN_Y, Z_EQ_X, Z_EQ_MIN_X, Z_EQ_MIN_Z, Z_EQ_Z, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fsm_ext_sens_z_orient_set(stmdev_ctx_t *ctx, + lsm6dsv16x_fsm_ext_sens_z_orient_t val) +{ + lsm6dsv16x_ext_cfg_a_t ext_cfg_a; + int32_t ret; + + ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); + if (ret == 0) + { + ext_cfg_a.ext_z_axis = (uint8_t)val & 0x07U; + ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); + } + + return ret; +} + +/** + * @brief External sensor z-axis coordinates rotation.[get] + * + * @param ctx read / write interface definitions + * @param val Z_EQ_Y, Z_EQ_MIN_Y, Z_EQ_X, Z_EQ_MIN_X, Z_EQ_MIN_Z, Z_EQ_Z, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fsm_ext_sens_z_orient_get(stmdev_ctx_t *ctx, + lsm6dsv16x_fsm_ext_sens_z_orient_t *val) +{ + lsm6dsv16x_ext_cfg_a_t ext_cfg_a; + int32_t ret; + + ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); + switch (ext_cfg_a.ext_z_axis) + { + case LSM6DSV16X_Z_EQ_Y: + *val = LSM6DSV16X_Z_EQ_Y; + break; + + case LSM6DSV16X_Z_EQ_MIN_Y: + *val = LSM6DSV16X_Z_EQ_MIN_Y; + break; + + case LSM6DSV16X_Z_EQ_X: + *val = LSM6DSV16X_Z_EQ_X; + break; + + case LSM6DSV16X_Z_EQ_MIN_X: + *val = LSM6DSV16X_Z_EQ_MIN_X; + break; + + case LSM6DSV16X_Z_EQ_MIN_Z: + *val = LSM6DSV16X_Z_EQ_MIN_Z; + break; + + case LSM6DSV16X_Z_EQ_Z: + *val = LSM6DSV16X_Z_EQ_Z; + break; + + default: + *val = LSM6DSV16X_Z_EQ_Y; + break; + } + return ret; +} + +/** + * @brief External sensor Y-axis coordinates rotation.[set] + * + * @param ctx read / write interface definitions + * @param val Y_EQ_Y, Y_EQ_MIN_Y, Y_EQ_X, Y_EQ_MIN_X, Y_EQ_MIN_Z, Y_EQ_Z, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fsm_ext_sens_y_orient_set(stmdev_ctx_t *ctx, + lsm6dsv16x_fsm_ext_sens_y_orient_t val) +{ + lsm6dsv16x_ext_cfg_a_t ext_cfg_a; + int32_t ret; + + ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); + if (ret == 0) + { + ext_cfg_a.ext_y_axis = (uint8_t)val & 0x7U; + ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); + } + + return ret; +} + +/** + * @brief External sensor Y-axis coordinates rotation.[get] + * + * @param ctx read / write interface definitions + * @param val Y_EQ_Y, Y_EQ_MIN_Y, Y_EQ_X, Y_EQ_MIN_X, Y_EQ_MIN_Z, Y_EQ_Z, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fsm_ext_sens_y_orient_get(stmdev_ctx_t *ctx, + lsm6dsv16x_fsm_ext_sens_y_orient_t *val) +{ + lsm6dsv16x_ext_cfg_a_t ext_cfg_a; + int32_t ret; + + ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); + switch (ext_cfg_a.ext_y_axis) + { + case LSM6DSV16X_Y_EQ_Y: + *val = LSM6DSV16X_Y_EQ_Y; + break; + + case LSM6DSV16X_Y_EQ_MIN_Y: + *val = LSM6DSV16X_Y_EQ_MIN_Y; + break; + + case LSM6DSV16X_Y_EQ_X: + *val = LSM6DSV16X_Y_EQ_X; + break; + + case LSM6DSV16X_Y_EQ_MIN_X: + *val = LSM6DSV16X_Y_EQ_MIN_X; + break; + + case LSM6DSV16X_Y_EQ_MIN_Z: + *val = LSM6DSV16X_Y_EQ_MIN_Z; + break; + + case LSM6DSV16X_Y_EQ_Z: + *val = LSM6DSV16X_Y_EQ_Z; + break; + + default: + *val = LSM6DSV16X_Y_EQ_Y; + break; + } + return ret; +} + +/** + * @brief External sensor X-axis coordinates rotation.[set] + * + * @param ctx read / write interface definitions + * @param val X_EQ_Y, X_EQ_MIN_Y, X_EQ_X, X_EQ_MIN_X, X_EQ_MIN_Z, X_EQ_Z, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fsm_ext_sens_x_orient_set(stmdev_ctx_t *ctx, + lsm6dsv16x_fsm_ext_sens_x_orient_t val) +{ + lsm6dsv16x_ext_cfg_b_t ext_cfg_b; + int32_t ret; + + ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EXT_CFG_B, (uint8_t *)&ext_cfg_b, 1); + if (ret == 0) + { + ext_cfg_b.ext_x_axis = (uint8_t)val & 0x7U; + ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EXT_CFG_B, (uint8_t *)&ext_cfg_b, 1); + } + + return ret; +} + +/** + * @brief External sensor X-axis coordinates rotation.[get] + * + * @param ctx read / write interface definitions + * @param val X_EQ_Y, X_EQ_MIN_Y, X_EQ_X, X_EQ_MIN_X, X_EQ_MIN_Z, X_EQ_Z, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fsm_ext_sens_x_orient_get(stmdev_ctx_t *ctx, + lsm6dsv16x_fsm_ext_sens_x_orient_t *val) +{ + lsm6dsv16x_ext_cfg_b_t ext_cfg_b; + int32_t ret; + + ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EXT_CFG_B, (uint8_t *)&ext_cfg_b, 1); + switch (ext_cfg_b.ext_x_axis) + { + case LSM6DSV16X_X_EQ_Y: + *val = LSM6DSV16X_X_EQ_Y; + break; + + case LSM6DSV16X_X_EQ_MIN_Y: + *val = LSM6DSV16X_X_EQ_MIN_Y; + break; + + case LSM6DSV16X_X_EQ_X: + *val = LSM6DSV16X_X_EQ_X; + break; + + case LSM6DSV16X_X_EQ_MIN_X: + *val = LSM6DSV16X_X_EQ_MIN_X; + break; + + case LSM6DSV16X_X_EQ_MIN_Z: + *val = LSM6DSV16X_X_EQ_MIN_Z; + break; + + case LSM6DSV16X_X_EQ_Z: + *val = LSM6DSV16X_X_EQ_Z; + break; + + default: + *val = LSM6DSV16X_X_EQ_Y; + break; + } + return ret; +} + +/** + * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[set] + * + * @param ctx read / write interface definitions + * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fsm_long_cnt_timeout_set(stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_LC_TIMEOUT_L, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[get] + * + * @param ctx read / write interface definitions + * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fsm_long_cnt_timeout_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_LC_TIMEOUT_L, &buff[0], 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief FSM number of programs.[set] + * + * @param ctx read / write interface definitions + * @param val FSM number of programs. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_fsm_programs_t fsm_programs; + int32_t ret; + + ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); + if (ret == 0) + { + fsm_programs.fsm_n_prog = val; + ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); + } + + return ret; +} + +/** + * @brief FSM number of programs.[get] + * + * @param ctx read / write interface definitions + * @param val FSM number of programs. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_fsm_programs_t fsm_programs; + int32_t ret; + + ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); + *val = fsm_programs.fsm_n_prog; + + return ret; +} + +/** + * @brief FSM start address. First available address is 0x35C.[set] + * + * @param ctx read / write interface definitions + * @param val FSM start address. First available address is 0x35C. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_START_ADD_L, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief FSM start address. First available address is 0x35C.[get] + * + * @param ctx read / write interface definitions + * @param val FSM start address. First available address is 0x35C. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_START_ADD_L, &buff[0], 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Free fall + * @brief This section group all the functions concerning the free + * fall detection. + * @{ + * + */ + +/** + * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[set] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ff_time_windows_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_wake_up_dur_t wake_up_dur; + lsm6dsv16x_free_fall_t free_fall; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + } + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + if (ret == 0) + { + free_fall.ff_dur = (uint8_t)val & 0x1FU; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + return ret; +} + +/** + * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[get] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ff_time_windows_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_wake_up_dur_t wake_up_dur; + lsm6dsv16x_free_fall_t free_fall; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; + + return ret; +} + +/** + * @brief Free fall threshold setting.[set] + * + * @param ctx read / write interface definitions + * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ff_thresholds_set(stmdev_ctx_t *ctx, + lsm6dsv16x_ff_thresholds_t val) +{ + lsm6dsv16x_free_fall_t free_fall; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret == 0) + { + free_fall.ff_ths = (uint8_t)val & 0x7U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + return ret; +} + +/** + * @brief Free fall threshold setting.[get] + * + * @param ctx read / write interface definitions + * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ff_thresholds_get(stmdev_ctx_t *ctx, + lsm6dsv16x_ff_thresholds_t *val) +{ + lsm6dsv16x_free_fall_t free_fall; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FREE_FALL, (uint8_t *)&free_fall, 1); + switch (free_fall.ff_ths) + { + case LSM6DSV16X_156_mg: + *val = LSM6DSV16X_156_mg; + break; + + case LSM6DSV16X_219_mg: + *val = LSM6DSV16X_219_mg; + break; + + case LSM6DSV16X_250_mg: + *val = LSM6DSV16X_250_mg; + break; + + case LSM6DSV16X_312_mg: + *val = LSM6DSV16X_312_mg; + break; + + case LSM6DSV16X_344_mg: + *val = LSM6DSV16X_344_mg; + break; + + case LSM6DSV16X_406_mg: + *val = LSM6DSV16X_406_mg; + break; + + case LSM6DSV16X_469_mg: + *val = LSM6DSV16X_469_mg; + break; + + case LSM6DSV16X_500_mg: + *val = LSM6DSV16X_500_mg; + break; + + default: + *val = LSM6DSV16X_156_mg; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Machine Learning Core (MLC) + * @brief This section group all the functions concerning the + * usage of Machine Learning Core + * @{ + * + */ + +/** + * @brief It enables Machine Learning Core feature (MLC). When the Machine Learning Core is enabled the Finite State Machine (FSM) programs are executed before executing the MLC algorithms.[set] + * + * @param ctx read / write interface definitions + * @param val MLC_OFF, MLC_ON, MLC_BEFORE_FSM, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_mlc_set(stmdev_ctx_t *ctx, lsm6dsv16x_mlc_mode_t val) +{ + lsm6dsv16x_emb_func_en_b_t emb_en_b; + lsm6dsv16x_emb_func_en_a_t emb_en_a; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + + switch(val) + { + case LSM6DSV16X_MLC_OFF: + emb_en_a.mlc_before_fsm_en = 0; + emb_en_b.mlc_en = 0; + break; + case LSM6DSV16X_MLC_ON: + emb_en_a.mlc_before_fsm_en = 0; + emb_en_b.mlc_en = 1; + break; + case LSM6DSV16X_MLC_ON_BEFORE_FSM: + emb_en_a.mlc_before_fsm_en = 1; + emb_en_b.mlc_en = 0; + break; + default: + break; + } + + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + } + + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief It enables Machine Learning Core feature (MLC). When the Machine Learning Core is enabled the Finite State Machine (FSM) programs are executed before executing the MLC algorithms.[get] + * + * @param ctx read / write interface definitions + * @param val MLC_OFF, MLC_ON, MLC_BEFORE_FSM, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_mlc_get(stmdev_ctx_t *ctx, lsm6dsv16x_mlc_mode_t *val) +{ + lsm6dsv16x_emb_func_en_b_t emb_en_b; + lsm6dsv16x_emb_func_en_a_t emb_en_a; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + + if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U) + { + *val = LSM6DSV16X_MLC_OFF; + } + else if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 1U) + { + *val = LSM6DSV16X_MLC_ON; + } + else if (emb_en_a.mlc_before_fsm_en == 1U) + { + *val = LSM6DSV16X_MLC_ON_BEFORE_FSM; + } + else + { + /* Do nothing */ + } + } + + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Machine Learning Core Output Data Rate (ODR) configuration.[set] + * + * @param ctx read / write interface definitions + * @param val MLC_15Hz, MLC_30Hz, MLC_60Hz, MLC_120Hz, MLC_240Hz, MLC_480Hz, MLC_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_mlc_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv16x_mlc_data_rate_t val) +{ + lsm6dsv16x_mlc_odr_t mlc_odr; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MLC_ODR, (uint8_t *)&mlc_odr, 1); + } + + if (ret == 0) + { + mlc_odr.mlc_odr = (uint8_t)val & 0x07U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MLC_ODR, (uint8_t *)&mlc_odr, 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Machine Learning Core Output Data Rate (ODR) configuration.[get] + * + * @param ctx read / write interface definitions + * @param val MLC_15Hz, MLC_30Hz, MLC_60Hz, MLC_120Hz, MLC_240Hz, MLC_480Hz, MLC_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_mlc_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv16x_mlc_data_rate_t *val) +{ + lsm6dsv16x_mlc_odr_t mlc_odr; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MLC_ODR, (uint8_t *)&mlc_odr, 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + switch (mlc_odr.mlc_odr) + { + case LSM6DSV16X_MLC_15Hz: + *val = LSM6DSV16X_MLC_15Hz; + break; + + case LSM6DSV16X_MLC_30Hz: + *val = LSM6DSV16X_MLC_30Hz; + break; + + case LSM6DSV16X_MLC_60Hz: + *val = LSM6DSV16X_MLC_60Hz; + break; + + case LSM6DSV16X_MLC_120Hz: + *val = LSM6DSV16X_MLC_120Hz; + break; + + case LSM6DSV16X_MLC_240Hz: + *val = LSM6DSV16X_MLC_240Hz; + break; + + case LSM6DSV16X_MLC_480Hz: + *val = LSM6DSV16X_MLC_480Hz; + break; + + case LSM6DSV16X_MLC_960Hz: + *val = LSM6DSV16X_MLC_960Hz; + break; + + default: + *val = LSM6DSV16X_MLC_15Hz; + break; + } + return ret; +} + +/** + * @brief Output value of all MLC decision trees.[get] + * + * @param ctx read / write interface definitions + * @param val Output value of all MLC decision trees. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_mlc_out_get(stmdev_ctx_t *ctx, lsm6dsv16x_mlc_out_t *val) +{ + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MLC1_SRC, (uint8_t *)val, 4); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + return ret; +} + +/** + * @brief External sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).Default value is 0x3C00 (when using an external magnetometer this value corresponds to 1 gauss/LSB).[set] + * + * @param ctx read / write interface definitions + * @param val External sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).Default value is 0x3C00 (when using an external magnetometer this value corresponds to 1 gauss/LSB). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_mlc_ext_sens_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + + ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_MLC_EXT_SENSITIVITY_L, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief External sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).Default value is 0x3C00 (when using an external magnetometer this value corresponds to 1 gauss/LSB).[get] + * + * @param ctx read / write interface definitions + * @param val External sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).Default value is 0x3C00 (when using an external magnetometer this value corresponds to 1 gauss/LSB). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_mlc_ext_sens_sensitivity_get(stmdev_ctx_t *ctx, + uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_MLC_EXT_SENSITIVITY_L, &buff[0], 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Optical Image Stabilization (OIS) + * @brief This section groups all the functions concerning + * Optical Image Stabilization (OIS). + * @{ + * + */ + +/** + * @brief Enable the full control of OIS configurations from the UI (User Interface).[set] + * + * @param ctx read / write interface definitions + * @param val OIS_CTRL_FROM_OIS, OIS_CTRL_FROM_UI, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ois_ctrl_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16x_ois_ctrl_mode_t val) +{ + lsm6dsv16x_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret == 0) + { + func_cfg_access.ois_ctrl_from_ui = (uint8_t)val & 0x1U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Enable the full control of OIS configurations from the UI (User Interface).[get] + * + * @param ctx read / write interface definitions + * @param val OIS_CTRL_FROM_OIS, OIS_CTRL_FROM_UI, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ois_ctrl_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16x_ois_ctrl_mode_t *val) +{ + lsm6dsv16x_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + switch (func_cfg_access.ois_ctrl_from_ui) + { + case LSM6DSV16X_OIS_CTRL_FROM_OIS: + *val = LSM6DSV16X_OIS_CTRL_FROM_OIS; + break; + + case LSM6DSV16X_OIS_CTRL_FROM_UI: + *val = LSM6DSV16X_OIS_CTRL_FROM_UI; + break; + + default: + *val = LSM6DSV16X_OIS_CTRL_FROM_OIS; + break; + } + return ret; +} + +/** + * @brief Resets the control registers of OIS from the UI (User Interface)[set] + * + * @param ctx read / write interface definitions + * @param val Resets the control registers of OIS from the UI (User Interface) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ois_reset_set(stmdev_ctx_t *ctx, int8_t val) +{ + lsm6dsv16x_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret == 0) + { + func_cfg_access.spi2_reset = (uint8_t)val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Resets the control registers of OIS from the UI (User Interface)[get] + * + * @param ctx read / write interface definitions + * @param val Resets the control registers of OIS from the UI (User Interface) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ois_reset_get(stmdev_ctx_t *ctx, int8_t *val) +{ + lsm6dsv16x_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + *val = (int8_t)func_cfg_access.spi2_reset; + + return ret; +} + +/** + * @brief Enable/disable pull up on OIS interface.[set] + * + * @param ctx read / write interface definitions + * @param val Enable/disable pull up on OIS interface. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ois_interface_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret == 0) + { + pin_ctrl.ois_pu_dis = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + + return ret; +} + +/** + * @brief Enable/disable pull up on OIS interface.[get] + * + * @param ctx read / write interface definitions + * @param val Enable/disable pull up on OIS interface. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ois_interface_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + *val = pin_ctrl.ois_pu_dis; + + return ret; +} + +/** + * @brief Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.[set] + * + * @param ctx read / write interface definitions + * @param val Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ois_handshake_from_ui_set(stmdev_ctx_t *ctx, + lsm6dsv16x_ois_handshake_t val) +{ + lsm6dsv16x_ui_handshake_ctrl_t ui_handshake_ctrl; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_HANDSHAKE_CTRL, (uint8_t *)&ui_handshake_ctrl, 1); + if (ret == 0) + { + ui_handshake_ctrl.ui_shared_ack = val.ack; + ui_handshake_ctrl.ui_shared_req = val.req; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_UI_HANDSHAKE_CTRL, (uint8_t *)&ui_handshake_ctrl, 1); + } + + return ret; +} + +/** + * @brief Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.[get] + * + * @param ctx read / write interface definitions + * @param val Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ois_handshake_from_ui_get(stmdev_ctx_t *ctx, + lsm6dsv16x_ois_handshake_t *val) +{ + lsm6dsv16x_ui_handshake_ctrl_t ui_handshake_ctrl; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_HANDSHAKE_CTRL, (uint8_t *)&ui_handshake_ctrl, 1); + val->ack = ui_handshake_ctrl.ui_shared_ack; + val->req = ui_handshake_ctrl.ui_shared_req; + + return ret; +} + +/** + * @brief Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.[set] + * + * @param ctx read / write interface definitions + * @param val Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ois_handshake_from_ois_set(stmdev_ctx_t *ctx, + lsm6dsv16x_ois_handshake_t val) +{ + lsm6dsv16x_spi2_handshake_ctrl_t spi2_handshake_ctrl; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SPI2_HANDSHAKE_CTRL, (uint8_t *)&spi2_handshake_ctrl, 1); + if (ret == 0) + { + spi2_handshake_ctrl.spi2_shared_ack = val.ack; + spi2_handshake_ctrl.spi2_shared_req = val.req; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SPI2_HANDSHAKE_CTRL, (uint8_t *)&spi2_handshake_ctrl, 1); + } + + return ret; +} + +/** + * @brief Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.[get] + * + * @param ctx read / write interface definitions + * @param val Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ois_handshake_from_ois_get(stmdev_ctx_t *ctx, + lsm6dsv16x_ois_handshake_t *val) +{ + lsm6dsv16x_spi2_handshake_ctrl_t spi2_handshake_ctrl; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SPI2_HANDSHAKE_CTRL, (uint8_t *)&spi2_handshake_ctrl, 1); + val->ack = spi2_handshake_ctrl.spi2_shared_ack; + val->req = spi2_handshake_ctrl.spi2_shared_req; + + return ret; +} + +/** + * @brief User interface (UI) / SPI2 (OIS) shared registers[set] + * + * @param ctx read / write interface definitions + * @param val User interface (UI) / SPI2 (OIS) shared registers + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ois_shared_set(stmdev_ctx_t *ctx, uint8_t val[6]) +{ + int32_t ret; + + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_UI_SPI2_SHARED_0, val, 6); + + return ret; +} + +/** + * @brief User interface (UI) / SPI2 (OIS) shared registers[get] + * + * @param ctx read / write interface definitions + * @param val User interface (UI) / SPI2 (OIS) shared registers + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ois_shared_get(stmdev_ctx_t *ctx, uint8_t val[6]) +{ + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_SPI2_SHARED_0, val, 6); + + return ret; +} + +/** + * @brief In User Interface (UI) full control mode, enables SPI2 (OIS Interface) for reading OIS data. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[set] + * + * @param ctx read / write interface definitions + * @param val In User Interface (UI) full control mode, enables SPI2 (OIS Interface) for reading OIS data. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ois_on_spi2_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_ui_ctrl1_ois_t ui_ctrl1_ois; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + if (ret == 0) + { + ui_ctrl1_ois.spi2_read_en = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + } + + return ret; +} + +/** + * @brief In User Interface (UI) full control mode, enables SPI2 (OIS Interface) for reading OIS data. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[get] + * + * @param ctx read / write interface definitions + * @param val In User Interface (UI) full control mode, enables SPI2 (OIS Interface) for reading OIS data. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ois_on_spi2_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_ui_ctrl1_ois_t ui_ctrl1_ois; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + *val = ui_ctrl1_ois.spi2_read_en; + + return ret; +} + +/** + * @brief Enables gyroscope/accelerometer OIS chain. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[set] + * + * @param ctx read / write interface definitions + * @param val Enables gyroscope/accelerometer OIS chain. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ois_chain_set(stmdev_ctx_t *ctx, lsm6dsv16x_ois_chain_t val) +{ + lsm6dsv16x_ui_ctrl1_ois_t ui_ctrl1_ois; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + if (ret == 0) + { + ui_ctrl1_ois.ois_g_en = val.gy; + ui_ctrl1_ois.ois_xl_en = val.xl; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + } + + return ret; +} + +/** + * @brief Enables gyroscope/accelerometer OIS chain.[get] + * + * @param ctx read / write interface definitions + * @param val Enables gyroscope/accelerometer OIS chain. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ois_chain_get(stmdev_ctx_t *ctx, lsm6dsv16x_ois_chain_t *val) +{ + lsm6dsv16x_ui_ctrl1_ois_t ui_ctrl1_ois; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + val->gy = ui_ctrl1_ois.ois_g_en; + val->xl = ui_ctrl1_ois.ois_xl_en; + + return ret; +} + +/** + * @brief Gyroscope OIS full-scale selection[set] + * + * @param ctx read / write interface definitions + * @param val OIS_125dps, OIS_250dps, OIS_500dps, OIS_1000dps, OIS_2000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ois_gy_full_scale_set(stmdev_ctx_t *ctx, + lsm6dsv16x_ois_gy_full_scale_t val) +{ + lsm6dsv16x_ui_ctrl2_ois_t ui_ctrl2_ois; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1); + if (ret == 0) + { + ui_ctrl2_ois.fs_g_ois = (uint8_t)val & 0x03U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1); + } + + return ret; +} + +/** + * @brief Gyroscope OIS full-scale selection[get] + * + * @param ctx read / write interface definitions + * @param val OIS_125dps, OIS_250dps, OIS_500dps, OIS_1000dps, OIS_2000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ois_gy_full_scale_get(stmdev_ctx_t *ctx, + lsm6dsv16x_ois_gy_full_scale_t *val) +{ + lsm6dsv16x_ui_ctrl2_ois_t ui_ctrl2_ois; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1); + switch (ui_ctrl2_ois.fs_g_ois) + { + case LSM6DSV16X_OIS_125dps: + *val = LSM6DSV16X_OIS_125dps; + break; + + case LSM6DSV16X_OIS_250dps: + *val = LSM6DSV16X_OIS_250dps; + break; + + case LSM6DSV16X_OIS_500dps: + *val = LSM6DSV16X_OIS_500dps; + break; + + case LSM6DSV16X_OIS_1000dps: + *val = LSM6DSV16X_OIS_1000dps; + break; + + case LSM6DSV16X_OIS_2000dps: + *val = LSM6DSV16X_OIS_2000dps; + break; + + default: + *val = LSM6DSV16X_OIS_125dps; + break; + } + return ret; +} + +/** + * @brief Selects accelerometer OIS channel full-scale.[set] + * + * @param ctx read / write interface definitions + * @param val OIS_2g, OIS_4g, OIS_8g, OIS_16g, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ois_xl_full_scale_set(stmdev_ctx_t *ctx, + lsm6dsv16x_ois_xl_full_scale_t val) +{ + lsm6dsv16x_ui_ctrl3_ois_t ui_ctrl3_ois; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1); + if (ret == 0) + { + ui_ctrl3_ois.fs_xl_ois = (uint8_t)val & 0x3U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1); + } + + return ret; +} + +/** + * @brief Selects accelerometer OIS channel full-scale.[get] + * + * @param ctx read / write interface definitions + * @param val OIS_2g, OIS_4g, OIS_8g, OIS_16g, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ois_xl_full_scale_get(stmdev_ctx_t *ctx, + lsm6dsv16x_ois_xl_full_scale_t *val) +{ + lsm6dsv16x_ui_ctrl3_ois_t ui_ctrl3_ois; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1); + switch (ui_ctrl3_ois.fs_xl_ois) + { + case LSM6DSV16X_OIS_2g: + *val = LSM6DSV16X_OIS_2g; + break; + + case LSM6DSV16X_OIS_4g: + *val = LSM6DSV16X_OIS_4g; + break; + + case LSM6DSV16X_OIS_8g: + *val = LSM6DSV16X_OIS_8g; + break; + + case LSM6DSV16X_OIS_16g: + *val = LSM6DSV16X_OIS_16g; + break; + + default: + *val = LSM6DSV16X_OIS_2g; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Orientation 6D (and 4D) + * @brief This section groups all the functions concerning six position + * detection (6D). + * @{ + * + */ + +/** + * @brief Threshold for 4D/6D function.[set] + * + * @param ctx read / write interface definitions + * @param val DEG_80, DEG_70, DEG_60, DEG_50, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_6d_threshold_set(stmdev_ctx_t *ctx, + lsm6dsv16x_6d_threshold_t val) +{ + lsm6dsv16x_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret == 0) + { + tap_ths_6d.sixd_ths = (uint8_t)val & 0x03U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + } + + return ret; +} + +/** + * @brief Threshold for 4D/6D function.[get] + * + * @param ctx read / write interface definitions + * @param val DEG_80, DEG_70, DEG_60, DEG_50, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_6d_threshold_get(stmdev_ctx_t *ctx, + lsm6dsv16x_6d_threshold_t *val) +{ + lsm6dsv16x_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + switch (tap_ths_6d.sixd_ths) + { + case LSM6DSV16X_DEG_80: + *val = LSM6DSV16X_DEG_80; + break; + + case LSM6DSV16X_DEG_70: + *val = LSM6DSV16X_DEG_70; + break; + + case LSM6DSV16X_DEG_60: + *val = LSM6DSV16X_DEG_60; + break; + + case LSM6DSV16X_DEG_50: + *val = LSM6DSV16X_DEG_50; + break; + + default: + *val = LSM6DSV16X_DEG_80; + break; + } + return ret; +} + +/** + * @brief 4D orientation detection enable. Z-axis position detection is disabled.[set] + * + * @param ctx read / write interface definitions + * @param val 4D orientation detection enable. Z-axis position detection is disabled. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret == 0) + { + tap_ths_6d.d4d_en = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + } + + return ret; +} + +/** + * @brief 4D orientation detection enable. Z-axis position detection is disabled.[get] + * + * @param ctx read / write interface definitions + * @param val 4D orientation detection enable. Z-axis position detection is disabled. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + *val = tap_ths_6d.d4d_en; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup AH_QVAR + * @brief This section group all the functions concerning the + * usage of AH_QVAR + * @{ + * + */ + +/** + * @brief Configures the equivalent input impedance of the AH_QVAR buffers.[set] + * + * @param ctx read / write interface definitions + * @param val 2400MOhm, 730MOhm, 300MOhm, 255MOhm, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ah_qvar_zin_set(stmdev_ctx_t *ctx, + lsm6dsv16x_ah_qvar_zin_t val) +{ + lsm6dsv16x_ctrl7_t ctrl7; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret == 0) + { + ctrl7.ah_qvar_c_zin = (uint8_t)val & 0x03U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL7, (uint8_t *)&ctrl7, 1); + } + + return ret; +} + +/** + * @brief Configures the equivalent input impedance of the AH_QVAR buffers.[get] + * + * @param ctx read / write interface definitions + * @param val 2400MOhm, 730MOhm, 300MOhm, 255MOhm, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ah_qvar_zin_get(stmdev_ctx_t *ctx, + lsm6dsv16x_ah_qvar_zin_t *val) +{ + lsm6dsv16x_ctrl7_t ctrl7; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL7, (uint8_t *)&ctrl7, 1); + switch (ctrl7.ah_qvar_c_zin) + { + case LSM6DSV16X_2400MOhm: + *val = LSM6DSV16X_2400MOhm; + break; + + case LSM6DSV16X_730MOhm: + *val = LSM6DSV16X_730MOhm; + break; + + case LSM6DSV16X_300MOhm: + *val = LSM6DSV16X_300MOhm; + break; + + case LSM6DSV16X_255MOhm: + *val = LSM6DSV16X_255MOhm; + break; + + default: + *val = LSM6DSV16X_2400MOhm; + break; + } + return ret; +} + +/** + * @brief Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/AH1/Qvar1 and SCx/AH2/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode.[set] + * + * @param ctx read / write interface definitions + * @param val Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/AH1/Qvar1 and SCx/AH2/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ah_qvar_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16x_ah_qvar_mode_t val) +{ + lsm6dsv16x_ctrl7_t ctrl7; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret == 0) + { + ctrl7.ah_qvar_en = val.ah_qvar_en; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL7, (uint8_t *)&ctrl7, 1); + } + + return ret; +} + +/** + * @brief Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/AH1/Qvar1 and SCx/AH2/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode.[get] + * + * @param ctx read / write interface definitions + * @param val Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/AH1/Qvar1 and SCx/AH2/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ah_qvar_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16x_ah_qvar_mode_t *val) +{ + lsm6dsv16x_ctrl7_t ctrl7; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL7, (uint8_t *)&ctrl7, 1); + val->ah_qvar_en = ctrl7.ah_qvar_en; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup SenseWire (I3C) + * @brief This section group all the functions concerning the + * usage of SenseWire (I3C) + * @{ + * + */ + +/** + * @brief Selects the action the device will perform after "Reset whole chip" I3C pattern.[set] + * + * @param ctx read / write interface definitions + * @param val SW_RST_DYN_ADDRESS_RST, GLOBAL_RST, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_i3c_reset_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16x_i3c_reset_mode_t val) +{ + lsm6dsv16x_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret == 0) + { + pin_ctrl.ibhr_por_en = (uint8_t)val & 0x01U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + + return ret; +} + +/** + * @brief Selects the action the device will perform after "Reset whole chip" I3C pattern.[get] + * + * @param ctx read / write interface definitions + * @param val SW_RST_DYN_ADDRESS_RST, I3C_GLOBAL_RST, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_i3c_reset_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16x_i3c_reset_mode_t *val) +{ + lsm6dsv16x_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + switch (pin_ctrl.ibhr_por_en) + { + case LSM6DSV16X_SW_RST_DYN_ADDRESS_RST: + *val = LSM6DSV16X_SW_RST_DYN_ADDRESS_RST; + break; + + case LSM6DSV16X_I3C_GLOBAL_RST: + *val = LSM6DSV16X_I3C_GLOBAL_RST; + break; + + default: + *val = LSM6DSV16X_SW_RST_DYN_ADDRESS_RST; + break; + } + return ret; +} + +/** + * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[set] + * + * @param ctx read / write interface definitions + * @param val IBI_2us, IBI_50us, IBI_1ms, IBI_25ms, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_i3c_ibi_time_set(stmdev_ctx_t *ctx, + lsm6dsv16x_i3c_ibi_time_t val) +{ + lsm6dsv16x_ctrl5_t ctrl5; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret == 0) + { + ctrl5.bus_act_sel = (uint8_t)val & 0x03U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL5, (uint8_t *)&ctrl5, 1); + } + + return ret; +} + +/** + * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[get] + * + * @param ctx read / write interface definitions + * @param val IBI_2us, IBI_50us, IBI_1ms, IBI_25ms, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_i3c_ibi_time_get(stmdev_ctx_t *ctx, + lsm6dsv16x_i3c_ibi_time_t *val) +{ + lsm6dsv16x_ctrl5_t ctrl5; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL5, (uint8_t *)&ctrl5, 1); + switch (ctrl5.bus_act_sel) + { + case LSM6DSV16X_IBI_2us: + *val = LSM6DSV16X_IBI_2us; + break; + + case LSM6DSV16X_IBI_50us: + *val = LSM6DSV16X_IBI_50us; + break; + + case LSM6DSV16X_IBI_1ms: + *val = LSM6DSV16X_IBI_1ms; + break; + + case LSM6DSV16X_IBI_25ms: + *val = LSM6DSV16X_IBI_25ms; + break; + + default: + *val = LSM6DSV16X_IBI_2us; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Sensor hub + * @brief This section groups all the functions that manage the + * sensor hub. + * @{ + * + */ + +/** + * @brief Sensor Hub master I2C pull-up enable.[set] + * + * @param ctx read / write interface definitions + * @param val Sensor Hub master I2C pull-up enable. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_sh_master_interface_pull_up_set(stmdev_ctx_t *ctx, + uint8_t val) +{ + lsm6dsv16x_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.shub_pu_en = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Sensor Hub master I2C pull-up enable.[get] + * + * @param ctx read / write interface definitions + * @param val Sensor Hub master I2C pull-up enable. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_sh_master_interface_pull_up_get(stmdev_ctx_t *ctx, + uint8_t *val) +{ + lsm6dsv16x_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1); + *val = if_cfg.shub_pu_en; + + return ret; +} + +/** + * @brief Sensor hub output registers.[get] + * + * @param ctx read / write interface definitions + * @param val Sensor hub output registers. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_sh_read_data_raw_get(stmdev_ctx_t *ctx, + lsm6dsv16x_emb_sh_read_t *val, + uint8_t len) +{ + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SENSOR_HUB_1, (uint8_t *) val, + len); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + + return ret; +} + +/** + * @brief Number of external sensors to be read by the sensor hub.[set] + * + * @param ctx read / write interface definitions + * @param val SLV_0, SLV_0_1, SLV_0_1_2, SLV_0_1_2_3, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_sh_slave_connected_set(stmdev_ctx_t *ctx, + lsm6dsv16x_sh_slave_connected_t val) +{ + lsm6dsv16x_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + master_config.aux_sens_on = (uint8_t)val & 0x3U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Number of external sensors to be read by the sensor hub.[get] + * + * @param ctx read / write interface definitions + * @param val SLV_0, SLV_0_1, SLV_0_1_2, SLV_0_1_2_3, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_sh_slave_connected_get(stmdev_ctx_t *ctx, + lsm6dsv16x_sh_slave_connected_t *val) +{ + lsm6dsv16x_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + switch (master_config.aux_sens_on) + { + case LSM6DSV16X_SLV_0: + *val = LSM6DSV16X_SLV_0; + break; + + case LSM6DSV16X_SLV_0_1: + *val = LSM6DSV16X_SLV_0_1; + break; + + case LSM6DSV16X_SLV_0_1_2: + *val = LSM6DSV16X_SLV_0_1_2; + break; + + case LSM6DSV16X_SLV_0_1_2_3: + *val = LSM6DSV16X_SLV_0_1_2_3; + break; + + default: + *val = LSM6DSV16X_SLV_0; + break; + } + return ret; +} + +/** + * @brief Sensor hub I2C master enable.[set] + * + * @param ctx read / write interface definitions + * @param val Sensor hub I2C master enable. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + master_config.master_on = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Sensor hub I2C master enable.[get] + * + * @param ctx read / write interface definitions + * @param val Sensor hub I2C master enable. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + *val = master_config.master_on; + + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief I2C interface pass-through.[set] + * + * @param ctx read / write interface definitions + * @param val I2C interface pass-through. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + master_config.pass_through_mode = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief I2C interface pass-through.[get] + * + * @param ctx read / write interface definitions + * @param val I2C interface pass-through. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + *val = master_config.pass_through_mode; + + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Sensor hub trigger signal selection.[set] + * + * @param ctx read / write interface definitions + * @param val SH_TRG_XL_GY_DRDY, SH_TRIG_INT2, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_sh_syncro_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16x_sh_syncro_mode_t val) +{ + lsm6dsv16x_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + master_config.start_config = (uint8_t)val & 0x01U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Sensor hub trigger signal selection.[get] + * + * @param ctx read / write interface definitions + * @param val SH_TRG_XL_GY_DRDY, SH_TRIG_INT2, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_sh_syncro_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16x_sh_syncro_mode_t *val) +{ + lsm6dsv16x_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + switch (master_config.start_config) + { + case LSM6DSV16X_SH_TRG_XL_GY_DRDY: + *val = LSM6DSV16X_SH_TRG_XL_GY_DRDY; + break; + + case LSM6DSV16X_SH_TRIG_INT2: + *val = LSM6DSV16X_SH_TRIG_INT2; + break; + + default: + *val = LSM6DSV16X_SH_TRG_XL_GY_DRDY; + break; + } + return ret; +} + +/** + * @brief Slave 0 write operation is performed only at the first sensor hub cycle.[set] + * + * @param ctx read / write interface definitions + * @param val EACH_SH_CYCLE, ONLY_FIRST_CYCLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_sh_write_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16x_sh_write_mode_t val) +{ + lsm6dsv16x_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + master_config.write_once = (uint8_t)val & 0x01U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Slave 0 write operation is performed only at the first sensor hub cycle.[get] + * + * @param ctx read / write interface definitions + * @param val EACH_SH_CYCLE, ONLY_FIRST_CYCLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_sh_write_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16x_sh_write_mode_t *val) +{ + lsm6dsv16x_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + + switch (master_config.write_once) + { + case LSM6DSV16X_EACH_SH_CYCLE: + *val = LSM6DSV16X_EACH_SH_CYCLE; + break; + + case LSM6DSV16X_ONLY_FIRST_CYCLE: + *val = LSM6DSV16X_ONLY_FIRST_CYCLE; + break; + + default: + *val = LSM6DSV16X_EACH_SH_CYCLE; + break; + } + return ret; +} + +/** + * @brief Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.[set] + * + * @param ctx read / write interface definitions + * @param val Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_sh_reset_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + master_config.rst_master_regs = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.[get] + * + * @param ctx read / write interface definitions + * @param val Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + *val = master_config.rst_master_regs; + + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Configure slave 0 for perform a write.[set] + * + * @param ctx read / write interface definitions + * @param val a structure that contain + * - uint8_t slv1_add; 8 bit i2c device address + * - uint8_t slv1_subadd; 8 bit register device address + * - uint8_t slv1_data; 8 bit data to write + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_sh_cfg_write(stmdev_ctx_t *ctx, + lsm6dsv16x_sh_cfg_write_t *val) +{ + lsm6dsv16x_slv0_add_t reg; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + reg.slave0_add = val->slv0_add; + reg.rw_0 = 0; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_ADD, (uint8_t *)®, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_SUBADD, + &(val->slv0_subadd), 1); + } + + if (ret == 0) + { + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_DATAWRITE_SLV0, + &(val->slv0_data), 1); + } + + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Rate at which the master communicates.[set] + * + * @param ctx read / write interface definitions + * @param val SH_15Hz, SH_30Hz, SH_60Hz, SH_120Hz, SH_240Hz, SH_480Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_sh_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv16x_sh_data_rate_t val) +{ + lsm6dsv16x_slv0_config_t slv0_config; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); + } + + if (ret == 0) + { + slv0_config.shub_odr = (uint8_t)val & 0x07U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Rate at which the master communicates.[get] + * + * @param ctx read / write interface definitions + * @param val SH_15Hz, SH_30Hz, SH_60Hz, SH_120Hz, SH_240Hz, SH_480Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_sh_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv16x_sh_data_rate_t *val) +{ + lsm6dsv16x_slv0_config_t slv0_config; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + switch (slv0_config.shub_odr) + { + case LSM6DSV16X_SH_15Hz: + *val = LSM6DSV16X_SH_15Hz; + break; + + case LSM6DSV16X_SH_30Hz: + *val = LSM6DSV16X_SH_30Hz; + break; + + case LSM6DSV16X_SH_60Hz: + *val = LSM6DSV16X_SH_60Hz; + break; + + case LSM6DSV16X_SH_120Hz: + *val = LSM6DSV16X_SH_120Hz; + break; + + case LSM6DSV16X_SH_240Hz: + *val = LSM6DSV16X_SH_240Hz; + break; + + case LSM6DSV16X_SH_480Hz: + *val = LSM6DSV16X_SH_480Hz; + break; + + default: + *val = LSM6DSV16X_SH_15Hz; + break; + } + return ret; +} + +/** + * @brief Configure slave 0 for perform a read.[set] + * + * @param ctx read / write interface definitions + * @param val Structure that contain + * - uint8_t slv1_add; 8 bit i2c device address + * - uint8_t slv1_subadd; 8 bit register device address + * - uint8_t slv1_len; num of bit to read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_sh_slv0_cfg_read(stmdev_ctx_t *ctx, + lsm6dsv16x_sh_cfg_read_t *val) +{ + lsm6dsv16x_slv0_add_t slv0_add; + lsm6dsv16x_slv0_config_t slv0_config; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); + + if (ret == 0) + { + slv0_add.slave0_add = val->slv_add; + slv0_add.rw_0 = 1; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_ADD, (uint8_t *)&slv0_add, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_SUBADD, + &(val->slv_subadd), 1); + } + + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV0_CONFIG, + (uint8_t *)&slv0_config, 1); + } + + if (ret == 0) + { + slv0_config.slave0_numop = val->slv_len; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_CONFIG, + (uint8_t *)&slv0_config, 1); + } + + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Configure slave 0 for perform a write/read.[set] + * + * @param ctx read / write interface definitions + * @param val Structure that contain + * - uint8_t slv1_add; 8 bit i2c device address + * - uint8_t slv1_subadd; 8 bit register device address + * - uint8_t slv1_len; num of bit to read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_sh_slv1_cfg_read(stmdev_ctx_t *ctx, + lsm6dsv16x_sh_cfg_read_t *val) +{ + lsm6dsv16x_slv1_add_t slv1_add; + lsm6dsv16x_slv1_config_t slv1_config; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); + + if (ret == 0) + { + slv1_add.slave1_add = val->slv_add; + slv1_add.r_1 = 1; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV1_ADD, (uint8_t *)&slv1_add, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV1_SUBADD, + &(val->slv_subadd), 1); + } + + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV1_CONFIG, + (uint8_t *)&slv1_config, 1); + } + + if (ret == 0) + { + slv1_config.slave1_numop = val->slv_len; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV1_CONFIG, + (uint8_t *)&slv1_config, 1); + } + + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Configure slave 0 for perform a write/read.[set] + * + * @param ctx read / write interface definitions + * @param val Structure that contain + * - uint8_t slv2_add; 8 bit i2c device address + * - uint8_t slv2_subadd; 8 bit register device address + * - uint8_t slv2_len; num of bit to read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_sh_slv2_cfg_read(stmdev_ctx_t *ctx, + lsm6dsv16x_sh_cfg_read_t *val) +{ + lsm6dsv16x_slv2_add_t slv2_add; + lsm6dsv16x_slv2_config_t slv2_config; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); + + if (ret == 0) + { + slv2_add.slave2_add = val->slv_add; + slv2_add.r_2 = 1; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV2_ADD, (uint8_t *)&slv2_add, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV2_SUBADD, + &(val->slv_subadd), 1); + } + + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV2_CONFIG, + (uint8_t *)&slv2_config, 1); + } + + if (ret == 0) + { + slv2_config.slave2_numop = val->slv_len; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV2_CONFIG, + (uint8_t *)&slv2_config, 1); + } + + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Configure slave 0 for perform a write/read.[set] + * + * @param ctx read / write interface definitions + * @param val Structure that contain + * - uint8_t slv3_add; 8 bit i2c device address + * - uint8_t slv3_subadd; 8 bit register device address + * - uint8_t slv3_len; num of bit to read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_sh_slv3_cfg_read(stmdev_ctx_t *ctx, + lsm6dsv16x_sh_cfg_read_t *val) +{ + lsm6dsv16x_slv3_add_t slv3_add; + lsm6dsv16x_slv3_config_t slv3_config; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); + + if (ret == 0) + { + slv3_add.slave3_add = val->slv_add; + slv3_add.r_3 = 1; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV3_ADD, (uint8_t *)&slv3_add, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV3_SUBADD, + &(val->slv_subadd), 1); + } + + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV3_CONFIG, + (uint8_t *)&slv3_config, 1); + } + + if (ret == 0) + { + slv3_config.slave3_numop = val->slv_len; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV3_CONFIG, + (uint8_t *)&slv3_config, 1); + } + + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Serial interfaces + * @brief This section groups all the functions concerning + * serial interfaces management (not auxiliary) + * @{ + * + */ + +/** + * @brief Enables pull-up on SDO pin of UI (User Interface).[set] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDO pin of UI (User Interface). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret == 0) + { + pin_ctrl.sdo_pu_en = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + + return ret; +} + +/** + * @brief Enables pull-up on SDO pin of UI (User Interface).[get] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDO pin of UI (User Interface). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + *val = pin_ctrl.sdo_pu_en; + + return ret; +} + +/** + * @brief Disables I2C and I3C on UI (User Interface).[set] + * + * @param ctx read / write interface definitions + * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ui_i2c_i3c_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16x_ui_i2c_i3c_mode_t val) +{ + lsm6dsv16x_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.i2c_i3c_disable = (uint8_t)val & 0x1U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Disables I2C and I3C on UI (User Interface).[get] + * + * @param ctx read / write interface definitions + * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ui_i2c_i3c_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16x_ui_i2c_i3c_mode_t *val) +{ + lsm6dsv16x_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1); + switch (if_cfg.i2c_i3c_disable) + { + case LSM6DSV16X_I2C_I3C_ENABLE: + *val = LSM6DSV16X_I2C_I3C_ENABLE; + break; + + case LSM6DSV16X_I2C_I3C_DISABLE: + *val = LSM6DSV16X_I2C_I3C_DISABLE; + break; + + default: + *val = LSM6DSV16X_I2C_I3C_ENABLE; + break; + } + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val SPI_4_WIRE, SPI_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_spi_mode_t val) +{ + lsm6dsv16x_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.sim = (uint8_t)val & 0x01U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val SPI_4_WIRE, SPI_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_spi_mode_t *val) +{ + lsm6dsv16x_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1); + switch (if_cfg.sim) + { + case LSM6DSV16X_SPI_4_WIRE: + *val = LSM6DSV16X_SPI_4_WIRE; + break; + + case LSM6DSV16X_SPI_3_WIRE: + *val = LSM6DSV16X_SPI_3_WIRE; + break; + + default: + *val = LSM6DSV16X_SPI_4_WIRE; + break; + } + return ret; +} + +/** + * @brief Enables pull-up on SDA pin.[set] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDA pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ui_sda_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.sda_pu_en = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Enables pull-up on SDA pin.[get] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDA pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_ui_sda_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1); + *val = if_cfg.sda_pu_en; + + return ret; +} + +/** + * @brief SPI2 (OIS Inteface) Serial Interface Mode selection. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[set] + * + * @param ctx read / write interface definitions + * @param val SPI2_4_WIRE, SPI2_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_spi2_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_spi2_mode_t val) +{ + lsm6dsv16x_ui_ctrl1_ois_t ui_ctrl1_ois; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + if (ret == 0) + { + ui_ctrl1_ois.sim_ois = (uint8_t)val & 0x01U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + } + + return ret; +} + +/** + * @brief SPI2 (OIS Inteface) Serial Interface Mode selection. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[get] + * + * @param ctx read / write interface definitions + * @param val SPI2_4_WIRE, SPI2_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_spi2_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_spi2_mode_t *val) +{ + lsm6dsv16x_ui_ctrl1_ois_t ui_ctrl1_ois; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + switch (ui_ctrl1_ois.sim_ois) + { + case LSM6DSV16X_SPI2_4_WIRE: + *val = LSM6DSV16X_SPI2_4_WIRE; + break; + + case LSM6DSV16X_SPI2_3_WIRE: + *val = LSM6DSV16X_SPI2_3_WIRE; + break; + + default: + *val = LSM6DSV16X_SPI2_4_WIRE; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Significant motion detection + * @brief This section groups all the functions that manage the + * significant motion detection. + * @{ + * + */ + + +/** + * @brief Enables significant motion detection function.[set] + * + * @param ctx read / write interface definitions + * @param val Enables significant motion detection function. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_sigmot_mode_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + if (ret == 0) + { + emb_func_en_a.sign_motion_en = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enables significant motion detection function.[get] + * + * @param ctx read / write interface definitions + * @param val Enables significant motion detection function. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_sigmot_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + *val = emb_func_en_a.sign_motion_en; + + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Step Counter (Pedometer) + * @brief This section groups all the functions that manage pedometer. + * @{ + * + */ + +/** + * @brief Step counter mode[set] + * + * @param ctx read / write interface definitions + * @param val Step counter mode + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_stpcnt_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16x_stpcnt_mode_t val) +{ + lsm6dsv16x_emb_func_en_a_t emb_func_en_a; + lsm6dsv16x_emb_func_en_b_t emb_func_en_b; + lsm6dsv16x_pedo_cmd_reg_t pedo_cmd_reg; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + if ((val.false_step_rej == PROPERTY_ENABLE) + && ((emb_func_en_a.mlc_before_fsm_en & emb_func_en_b.mlc_en) == + PROPERTY_DISABLE)) + { + emb_func_en_a.mlc_before_fsm_en = PROPERTY_ENABLE; + } + if (ret == 0) + { + emb_func_en_a.pedo_en = val.step_counter_enable; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + if (ret == 0) + { + ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + if (ret == 0) + { + pedo_cmd_reg.fp_rejection_en = val.false_step_rej; + ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + + return ret; +} + +/** + * @brief Step counter mode[get] + * + * @param ctx read / write interface definitions + * @param val false_step_rej, step_counter, step_detector, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_stpcnt_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16x_stpcnt_mode_t *val) +{ + lsm6dsv16x_emb_func_en_a_t emb_func_en_a; + lsm6dsv16x_pedo_cmd_reg_t pedo_cmd_reg; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + if (ret == 0) + { + ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + val->false_step_rej = pedo_cmd_reg.fp_rejection_en; + val->step_counter_enable = emb_func_en_a.pedo_en; + + return ret; +} + +/** + * @brief Step counter output, number of detected steps.[get] + * + * @param ctx read / write interface definitions + * @param val Step counter output, number of detected steps. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_STEP_COUNTER_L, &buff[0], 2); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief Reset step counter.[set] + * + * @param ctx read / write interface definitions + * @param val Reset step counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_stpcnt_rst_step_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_emb_func_src_t emb_func_src; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } + + if (ret == 0) + { + emb_func_src.pedo_rst_step = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Reset step counter.[get] + * + * @param ctx read / write interface definitions + * @param val Reset step counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_stpcnt_rst_step_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_emb_func_src_t emb_func_src; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } + + *val = emb_func_src.pedo_rst_step; + + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Pedometer debounce configuration.[set] + * + * @param ctx read / write interface definitions + * @param val Pedometer debounce configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_stpcnt_debounce_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_pedo_deb_steps_conf_t pedo_deb_steps_conf; + int32_t ret; + + ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); + if (ret == 0) + { + pedo_deb_steps_conf.deb_step = val; + ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); + } + + return ret; +} + +/** + * @brief Pedometer debounce configuration.[get] + * + * @param ctx read / write interface definitions + * @param val Pedometer debounce configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_stpcnt_debounce_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_pedo_deb_steps_conf_t pedo_deb_steps_conf; + int32_t ret; + + ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); + *val = pedo_deb_steps_conf.deb_step; + + return ret; +} + +/** + * @brief Time period register for step detection on delta time.[set] + * + * @param ctx read / write interface definitions + * @param val Time period register for step detection on delta time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_SC_DELTAT_L, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief Time period register for step detection on delta time.[get] + * + * @param ctx read / write interface definitions + * @param val Time period register for step detection on delta time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_stpcnt_period_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_SC_DELTAT_L, &buff[0], 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Sensor Fusion Low Power (SFLP) + * @brief This section groups all the functions that manage pedometer. + * @{ + * + */ + +/** + * @brief Enable SFLP Game Rotation Vector (6x).[set] + * + * @param ctx read / write interface definitions + * @param val Enable/Disable game rotation value (0/1). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_sflp_game_rotation_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + emb_func_en_a.sflp_game_en = val; + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, + (uint8_t *)&emb_func_en_a, 1); + } + + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable SFLP Game Rotation Vector (6x).[get] + * + * @param ctx read / write interface definitions + * @param val Enable/Disable game rotation value (0/1). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_sflp_game_rotation_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + *val = emb_func_en_a.sflp_game_en; + } + + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief SFLP Data Rate (ODR) configuration.[set] + * + * @param ctx read / write interface definitions + * @param val SFLP_15Hz, SFLP_30Hz, SFLP_60Hz, SFLP_120Hz, SFLP_240Hz, SFLP_480Hz + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_sflp_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv16x_sflp_data_rate_t val) +{ + lsm6dsv16x_sflp_odr_t sflp_odr; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + sflp_odr.sflp_game_odr = (uint8_t)val & 0x07U; + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + } + + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief SFLP Data Rate (ODR) configuration.[get] + * + * @param ctx read / write interface definitions + * @param val SFLP_15Hz, SFLP_30Hz, SFLP_60Hz, SFLP_120Hz, SFLP_240Hz, SFLP_480Hz + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_sflp_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv16x_sflp_data_rate_t *val) +{ + lsm6dsv16x_sflp_odr_t sflp_odr; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + switch (sflp_odr.sflp_game_odr) + { + case LSM6DSV16X_SFLP_15Hz: + *val = LSM6DSV16X_SFLP_15Hz; + break; + + case LSM6DSV16X_SFLP_30Hz: + *val = LSM6DSV16X_SFLP_30Hz; + break; + + case LSM6DSV16X_SFLP_60Hz: + *val = LSM6DSV16X_SFLP_60Hz; + break; + + case LSM6DSV16X_SFLP_120Hz: + *val = LSM6DSV16X_SFLP_120Hz; + break; + + case LSM6DSV16X_SFLP_240Hz: + *val = LSM6DSV16X_SFLP_240Hz; + break; + + case LSM6DSV16X_SFLP_480Hz: + *val = LSM6DSV16X_SFLP_480Hz; + break; + + default: + *val = LSM6DSV16X_SFLP_15Hz; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Tap - Double Tap + * @brief This section groups all the functions that manage the + * tap and double tap event generation. + * @{ + * + */ + +/** + * @brief Enable axis for Tap - Double Tap detection.[set] + * + * @param ctx read / write interface definitions + * @param val Enable axis for Tap - Double Tap detection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_tap_detection_set(stmdev_ctx_t *ctx, + lsm6dsv16x_tap_detection_t val) +{ + lsm6dsv16x_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret == 0) + { + tap_cfg0.tap_x_en = val.tap_x_en; + tap_cfg0.tap_y_en = val.tap_y_en; + tap_cfg0.tap_z_en = val.tap_z_en; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + return ret; +} + +/** + * @brief Enable axis for Tap - Double Tap detection.[get] + * + * @param ctx read / write interface definitions + * @param val Enable axis for Tap - Double Tap detection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_tap_detection_get(stmdev_ctx_t *ctx, + lsm6dsv16x_tap_detection_t *val) +{ + lsm6dsv16x_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + val->tap_x_en = tap_cfg0.tap_x_en; + val->tap_y_en = tap_cfg0.tap_y_en; + val->tap_z_en = tap_cfg0.tap_z_en; + + return ret; +} + +/** + * @brief axis Tap - Double Tap recognition thresholds.[set] + * + * @param ctx read / write interface definitions + * @param val axis Tap - Double Tap recognition thresholds. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_tap_thresholds_set(stmdev_ctx_t *ctx, + lsm6dsv16x_tap_thresholds_t val) +{ + lsm6dsv16x_tap_ths_6d_t tap_ths_6d; + lsm6dsv16x_tap_cfg2_t tap_cfg2; + lsm6dsv16x_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + } + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + } + + tap_cfg1.tap_ths_x = val.x; + tap_cfg2.tap_ths_y = val.y; + tap_ths_6d.tap_ths_z = val.z; + + if (ret == 0) + { + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + } + if (ret == 0) + { + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + } + if (ret == 0) + { + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + } + + return ret; +} + +/** + * @brief axis Tap - Double Tap recognition thresholds.[get] + * + * @param ctx read / write interface definitions + * @param val axis Tap - Double Tap recognition thresholds. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_tap_thresholds_get(stmdev_ctx_t *ctx, + lsm6dsv16x_tap_thresholds_t *val) +{ + lsm6dsv16x_tap_ths_6d_t tap_ths_6d; + lsm6dsv16x_tap_cfg2_t tap_cfg2; + lsm6dsv16x_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + } + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + } + + val->x = tap_cfg1.tap_ths_x; + val->y = tap_cfg2.tap_ths_y; + val->z = tap_ths_6d.tap_ths_z; + + return ret; +} + +/** + * @brief Selection of axis priority for TAP detection.[set] + * + * @param ctx read / write interface definitions + * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY , + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_tap_axis_priority_set(stmdev_ctx_t *ctx, + lsm6dsv16x_tap_axis_priority_t val) +{ + lsm6dsv16x_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret == 0) + { + tap_cfg1.tap_priority = (uint8_t)val & 0x7U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + } + + return ret; +} + +/** + * @brief Selection of axis priority for TAP detection.[get] + * + * @param ctx read / write interface definitions + * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY , + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_tap_axis_priority_get(stmdev_ctx_t *ctx, + lsm6dsv16x_tap_axis_priority_t *val) +{ + lsm6dsv16x_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + switch (tap_cfg1.tap_priority) + { + case LSM6DSV16X_XYZ : + *val = LSM6DSV16X_XYZ ; + break; + + case LSM6DSV16X_YXZ : + *val = LSM6DSV16X_YXZ ; + break; + + case LSM6DSV16X_XZY: + *val = LSM6DSV16X_XZY; + break; + + case LSM6DSV16X_ZYX : + *val = LSM6DSV16X_ZYX ; + break; + + case LSM6DSV16X_YZX : + *val = LSM6DSV16X_YZX ; + break; + + case LSM6DSV16X_ZXY : + *val = LSM6DSV16X_ZXY ; + break; + + default: + *val = LSM6DSV16X_XYZ ; + break; + } + return ret; +} + +/** + * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[set] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_tap_time_windows_set(stmdev_ctx_t *ctx, + lsm6dsv16x_tap_time_windows_t val) +{ + lsm6dsv16x_tap_dur_t tap_dur; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_DUR, (uint8_t *)&tap_dur, 1); + if (ret == 0) + { + tap_dur.shock = val.shock; + tap_dur.quiet = val.quiet; + tap_dur.dur = val.tap_gap; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_DUR, (uint8_t *)&tap_dur, 1); + } + + return ret; +} + +/** + * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[get] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_tap_time_windows_get(stmdev_ctx_t *ctx, + lsm6dsv16x_tap_time_windows_t *val) +{ + lsm6dsv16x_tap_dur_t tap_dur; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_DUR, (uint8_t *)&tap_dur, 1); + val->shock = tap_dur.shock; + val->quiet = tap_dur.quiet; + val->tap_gap = tap_dur.dur; + + return ret; +} + +/** + * @brief Single/double-tap event enable.[set] + * + * @param ctx read / write interface definitions + * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_tap_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_tap_mode_t val) +{ + lsm6dsv16x_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret == 0) + { + wake_up_ths.single_double_tap = (uint8_t)val & 0x01U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + } + + return ret; +} + +/** + * @brief Single/double-tap event enable.[get] + * + * @param ctx read / write interface definitions + * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_tap_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_tap_mode_t *val) +{ + lsm6dsv16x_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + switch (wake_up_ths.single_double_tap) + { + case LSM6DSV16X_ONLY_SINGLE: + *val = LSM6DSV16X_ONLY_SINGLE; + break; + + case LSM6DSV16X_BOTH_SINGLE_DOUBLE: + *val = LSM6DSV16X_BOTH_SINGLE_DOUBLE; + break; + + default: + *val = LSM6DSV16X_ONLY_SINGLE; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Tilt detection + * @brief This section groups all the functions that manage the tilt + * event detection. + * @{ + * + */ + +/** + * @brief Tilt calculation.[set] + * + * @param ctx read / write interface definitions + * @param val Tilt calculation. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_tilt_mode_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + if (ret == 0) + { + emb_func_en_a.tilt_en = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Tilt calculation.[get] + * + * @param ctx read / write interface definitions + * @param val Tilt calculation. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_tilt_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + *val = emb_func_en_a.tilt_en; + + ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Timestamp + * @brief This section groups all the functions that manage the + * timestamp generation. + * @{ + * + */ + +/** + * @brief Timestamp data output.[get] + * + * @param ctx read / write interface definitions + * @param val Timestamp data output. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) +{ + uint8_t buff[4]; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TIMESTAMP0, &buff[0], 4); + *val = buff[3]; + *val = (*val * 256U) + buff[2]; + *val = (*val * 256U) + buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief Enables timestamp counter.[set] + * + * @param ctx read / write interface definitions + * @param val Enables timestamp counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_functions_enable_t functions_enable; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret == 0) + { + functions_enable.timestamp_en = val; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + return ret; +} + +/** + * @brief Enables timestamp counter.[get] + * + * @param ctx read / write interface definitions + * @param val Enables timestamp counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_functions_enable_t functions_enable; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + *val = functions_enable.timestamp_en; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Wake Up - Activity - Inactivity (Sleep) + * @brief This section groups all the functions that manage the Wake Up + * event generation. + * @{ + * + */ + +/** + * @brief Enable activity/inactivity (sleep) function.[set] + * + * @param ctx read / write interface definitions + * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_act_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_act_mode_t val) +{ + lsm6dsv16x_functions_enable_t functions_enable; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret == 0) + { + functions_enable.inact_en = (uint8_t)val & 0x3U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + return ret; +} + +/** + * @brief Enable activity/inactivity (sleep) function.[get] + * + * @param ctx read / write interface definitions + * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_act_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_act_mode_t *val) +{ + lsm6dsv16x_functions_enable_t functions_enable; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + switch (functions_enable.inact_en) + { + case LSM6DSV16X_XL_AND_GY_NOT_AFFECTED: + *val = LSM6DSV16X_XL_AND_GY_NOT_AFFECTED; + break; + + case LSM6DSV16X_XL_LOW_POWER_GY_NOT_AFFECTED: + *val = LSM6DSV16X_XL_LOW_POWER_GY_NOT_AFFECTED; + break; + + case LSM6DSV16X_XL_LOW_POWER_GY_SLEEP: + *val = LSM6DSV16X_XL_LOW_POWER_GY_SLEEP; + break; + + case LSM6DSV16X_XL_LOW_POWER_GY_POWER_DOWN: + *val = LSM6DSV16X_XL_LOW_POWER_GY_POWER_DOWN; + break; + + default: + *val = LSM6DSV16X_XL_AND_GY_NOT_AFFECTED; + break; + } + return ret; +} + +/** + * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[set] + * + * @param ctx read / write interface definitions + * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_act_from_sleep_to_act_dur_set(stmdev_ctx_t *ctx, + lsm6dsv16x_act_from_sleep_to_act_dur_t val) +{ + lsm6dsv16x_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret == 0) + { + inactivity_dur.inact_dur = (uint8_t)val & 0x3U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + return ret; +} + +/** + * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[get] + * + * @param ctx read / write interface definitions + * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_act_from_sleep_to_act_dur_get(stmdev_ctx_t *ctx, + lsm6dsv16x_act_from_sleep_to_act_dur_t *val) +{ + lsm6dsv16x_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + switch (inactivity_dur.inact_dur) + { + case LSM6DSV16X_SLEEP_TO_ACT_AT_1ST_SAMPLE: + *val = LSM6DSV16X_SLEEP_TO_ACT_AT_1ST_SAMPLE; + break; + + case LSM6DSV16X_SLEEP_TO_ACT_AT_2ND_SAMPLE: + *val = LSM6DSV16X_SLEEP_TO_ACT_AT_2ND_SAMPLE; + break; + + case LSM6DSV16X_SLEEP_TO_ACT_AT_3RD_SAMPLE: + *val = LSM6DSV16X_SLEEP_TO_ACT_AT_3RD_SAMPLE; + break; + + case LSM6DSV16X_SLEEP_TO_ACT_AT_4th_SAMPLE: + *val = LSM6DSV16X_SLEEP_TO_ACT_AT_4th_SAMPLE; + break; + + default: + *val = LSM6DSV16X_SLEEP_TO_ACT_AT_1ST_SAMPLE; + break; + } + return ret; +} + +/** + * @brief Selects the accelerometer data rate during Inactivity.[set] + * + * @param ctx read / write interface definitions + * @param val 1Hz875, 15Hz, 30Hz, 60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_act_sleep_xl_odr_set(stmdev_ctx_t *ctx, + lsm6dsv16x_act_sleep_xl_odr_t val) +{ + lsm6dsv16x_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret == 0) + { + inactivity_dur.xl_inact_odr = (uint8_t)val & 0x03U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + return ret; +} + +/** + * @brief Selects the accelerometer data rate during Inactivity.[get] + * + * @param ctx read / write interface definitions + * @param val 1Hz875, 15Hz, 30Hz, 60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_act_sleep_xl_odr_get(stmdev_ctx_t *ctx, + lsm6dsv16x_act_sleep_xl_odr_t *val) +{ + lsm6dsv16x_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + switch (inactivity_dur.xl_inact_odr) + { + case LSM6DSV16X_1Hz875: + *val = LSM6DSV16X_1Hz875; + break; + + case LSM6DSV16X_15Hz: + *val = LSM6DSV16X_15Hz; + break; + + case LSM6DSV16X_30Hz: + *val = LSM6DSV16X_30Hz; + break; + + case LSM6DSV16X_60Hz: + *val = LSM6DSV16X_60Hz; + break; + + default: + *val = LSM6DSV16X_1Hz875; + break; + } + return ret; +} + +/** + * @brief Wakeup and activity/inactivity threshold.[set] + * + * @param ctx read / write interface definitions + * @param val Wakeup and activity/inactivity threshold. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_act_thresholds_set(stmdev_ctx_t *ctx, + lsm6dsv16x_act_thresholds_t *val) +{ + lsm6dsv16x_inactivity_ths_t inactivity_ths; + lsm6dsv16x_inactivity_dur_t inactivity_dur; + lsm6dsv16x_wake_up_ths_t wake_up_ths; + lsm6dsv16x_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + + inactivity_dur.wu_inact_ths_w = val->inactivity_cfg.wu_inact_ths_w; + inactivity_dur.xl_inact_odr = val->inactivity_cfg.xl_inact_odr; + inactivity_dur.inact_dur = val->inactivity_cfg.inact_dur; + + inactivity_ths.inact_ths = val->inactivity_ths; + wake_up_ths.wk_ths = val->threshold; + wake_up_dur.wake_dur = val->duration; + + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + + return ret; +} + +/** + * @brief Wakeup and activity/inactivity threshold.[get] + * + * @param ctx read / write interface definitions + * @param val Wakeup and activity/inactivity threshold. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_act_thresholds_get(stmdev_ctx_t *ctx, + lsm6dsv16x_act_thresholds_t *val) +{ + lsm6dsv16x_inactivity_dur_t inactivity_dur; + lsm6dsv16x_inactivity_ths_t inactivity_ths; + lsm6dsv16x_wake_up_ths_t wake_up_ths; + lsm6dsv16x_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + + val->inactivity_cfg.wu_inact_ths_w = inactivity_dur.wu_inact_ths_w; + val->inactivity_cfg.xl_inact_odr = inactivity_dur.xl_inact_odr; + val->inactivity_cfg.inact_dur = inactivity_dur.inact_dur; + + val->inactivity_ths = inactivity_ths.inact_ths; + val->threshold = wake_up_ths.wk_ths; + val->duration = wake_up_dur.wake_dur; + + return ret; +} + +/** + * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [set] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_act_wkup_time_windows_set(stmdev_ctx_t *ctx, + lsm6dsv16x_act_wkup_time_windows_t val) +{ + lsm6dsv16x_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + wake_up_dur.wake_dur = val.shock; + wake_up_dur.sleep_dur = val.quiet; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + } + + return ret; +} + +/** + * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [get] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_act_wkup_time_windows_get(stmdev_ctx_t *ctx, + lsm6dsv16x_act_wkup_time_windows_t *val) +{ + lsm6dsv16x_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + val->shock = wake_up_dur.wake_dur; + val->quiet = wake_up_dur.sleep_dur; + + return ret; +} + +/** + * @} + * + */ diff --git a/sensor/stmemsc/lsm6dsv16x_STdC/driver/lsm6dsv16x_reg.h b/sensor/stmemsc/lsm6dsv16x_STdC/driver/lsm6dsv16x_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..3a8d3865672861a22c0492d81199ecfcb6be5d7b --- /dev/null +++ b/sensor/stmemsc/lsm6dsv16x_STdC/driver/lsm6dsv16x_reg.h @@ -0,0 +1,5302 @@ +/** + ****************************************************************************** + * @file lsm6dsv16x_reg.h + * @author Sensors Software Solution Team + * @brief This file contains all the functions prototypes for the + * lsm6dsv16x_reg.c driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2022 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef LSM6DSV16X_REGS_H +#define LSM6DSV16X_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include + +/** @addtogroup LSM6DSV16X + * @{ + * + */ + +/** @defgroup Endianness definitions + * @{ + * + */ + +#ifndef DRV_BYTE_ORDER +#ifndef __BYTE_ORDER__ + +#define DRV_LITTLE_ENDIAN 1234 +#define DRV_BIG_ENDIAN 4321 + +/** if _BYTE_ORDER is not defined, choose the endianness of your architecture + * by uncommenting the define which fits your platform endianness + */ +//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN +#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN + +#else /* defined __BYTE_ORDER__ */ + +#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ +#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ +#define DRV_BYTE_ORDER __BYTE_ORDER__ + +#endif /* __BYTE_ORDER__*/ +#endif /* DRV_BYTE_ORDER */ + +/** + * @} + * + */ + +/** @defgroup STMicroelectronics sensors common types + * @{ + * + */ + +#ifndef MEMS_SHARED_TYPES +#define MEMS_SHARED_TYPES + +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} bitwise_t; + +#define PROPERTY_DISABLE (0U) +#define PROPERTY_ENABLE (1U) + +/** @addtogroup Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); +typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); + +typedef struct +{ + /** Component mandatory fields **/ + stmdev_write_ptr write_reg; + stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; + /** Customizable optional pointer **/ + void *handle; +} stmdev_ctx_t; + +/** + * @} + * + */ + +#endif /* MEMS_SHARED_TYPES */ + +#ifndef MEMS_UCF_SHARED_TYPES +#define MEMS_UCF_SHARED_TYPES + +/** @defgroup Generic address-data structure definition + * @brief This structure is useful to load a predefined configuration + * of a sensor. + * You can create a sensor configuration by your own or using + * Unico / Unicleo tools available on STMicroelectronics + * web site. + * + * @{ + * + */ + +typedef struct +{ + uint8_t address; + uint8_t data; +} ucf_line_t; + +/** + * @} + * + */ + +#endif /* MEMS_UCF_SHARED_TYPES */ + +/** + * @} + * + */ + +/** @defgroup LSM6DSV16X_Infos + * @{ + * + */ + +/** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ +#define LSM6DSV16X_I2C_ADD_L 0xD5U +#define LSM6DSV16X_I2C_ADD_H 0xD7U + +/** Device Identification (Who am I) **/ +#define LSM6DSV16X_ID 0x70U + +/** + * @} + * + */ + +/** @defgroup bitfields page main + * @{ + * + */ + +#define LSM6DSV16X_FUNC_CFG_ACCESS 0x1U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ois_ctrl_from_ui : 1; + uint8_t spi2_reset : 1; + uint8_t sw_por : 1; + uint8_t fsm_wr_ctrl_en : 1; + uint8_t not_used0 : 2; + uint8_t shub_reg_access : 1; + uint8_t emb_func_reg_access : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t emb_func_reg_access : 1; + uint8_t shub_reg_access : 1; + uint8_t not_used0 : 2; + uint8_t fsm_wr_ctrl_en : 1; + uint8_t sw_por : 1; + uint8_t spi2_reset : 1; + uint8_t ois_ctrl_from_ui : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_func_cfg_access_t; + +#define LSM6DSV16X_PIN_CTRL 0x2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 5; + uint8_t ibhr_por_en : 1; + uint8_t sdo_pu_en : 1; + uint8_t ois_pu_dis : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ois_pu_dis : 1; + uint8_t sdo_pu_en : 1; + uint8_t ibhr_por_en : 1; + uint8_t not_used0 : 5; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_pin_ctrl_t; + +#define LSM6DSV16X_IF_CFG 0x3U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t i2c_i3c_disable : 1; + uint8_t not_used0 : 1; + uint8_t sim : 1; + uint8_t pp_od : 1; + uint8_t h_lactive : 1; + uint8_t asf_ctrl : 1; + uint8_t shub_pu_en : 1; + uint8_t sda_pu_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sda_pu_en : 1; + uint8_t shub_pu_en : 1; + uint8_t asf_ctrl : 1; + uint8_t h_lactive : 1; + uint8_t pp_od : 1; + uint8_t sim : 1; + uint8_t not_used0 : 1; + uint8_t i2c_i3c_disable : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_if_cfg_t; + +#define LSM6DSV16X_ODR_TRIG_CFG 0x6U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t odr_trig_nodr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t odr_trig_nodr : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_odr_trig_cfg_t; + +#define LSM6DSV16X_FIFO_CTRL1 0x7U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wtm : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t wtm : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fifo_ctrl1_t; + +#define LSM6DSV16X_FIFO_CTRL2 0x8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xl_dualc_batch_from_fsm : 1; + uint8_t uncompr_rate : 2; + uint8_t not_used0 : 1; + uint8_t odr_chg_en : 1; + uint8_t not_used1 : 1; + uint8_t fifo_compr_rt_en : 1; + uint8_t stop_on_wtm : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t stop_on_wtm : 1; + uint8_t fifo_compr_rt_en : 1; + uint8_t not_used1 : 1; + uint8_t odr_chg_en : 1; + uint8_t not_used0 : 1; + uint8_t uncompr_rate : 2; + uint8_t xl_dualc_batch_from_fsm : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fifo_ctrl2_t; + +#define LSM6DSV16X_FIFO_CTRL3 0x9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bdr_xl : 4; + uint8_t bdr_gy : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bdr_gy : 4; + uint8_t bdr_xl : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fifo_ctrl3_t; + +#define LSM6DSV16X_FIFO_CTRL4 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_mode : 3; + uint8_t g_eis_fifo_en : 1; + uint8_t odr_t_batch : 2; + uint8_t dec_ts_batch : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dec_ts_batch : 2; + uint8_t odr_t_batch : 2; + uint8_t g_eis_fifo_en : 1; + uint8_t fifo_mode : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fifo_ctrl4_t; + +#define LSM6DSV16X_COUNTER_BDR_REG1 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t cnt_bdr_th : 2; + uint8_t not_used0 : 3; + uint8_t trig_counter_bdr : 2; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t trig_counter_bdr : 2; + uint8_t not_used0 : 3; + uint8_t cnt_bdr_th : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_counter_bdr_reg1_t; + +#define LSM6DSV16X_COUNTER_BDR_REG2 0x0CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t cnt_bdr_th : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t cnt_bdr_th : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_counter_bdr_reg2_t; + +#define LSM6DSV16X_INT1_CTRL 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_drdy_xl : 1; + uint8_t int1_drdy_g : 1; + uint8_t not_used0 : 1; + uint8_t int1_fifo_th : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_fifo_full : 1; + uint8_t int1_cnt_bdr : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t int1_cnt_bdr : 1; + uint8_t int1_fifo_full : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_fifo_th : 1; + uint8_t not_used0 : 1; + uint8_t int1_drdy_g : 1; + uint8_t int1_drdy_xl : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_int1_ctrl_t; + +#define LSM6DSV16X_INT2_CTRL 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_drdy_xl : 1; + uint8_t int2_drdy_g : 1; + uint8_t int2_drdy_g_eis : 1; + uint8_t int2_fifo_th : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_fifo_full : 1; + uint8_t int2_cnt_bdr : 1; + uint8_t int2_emb_func_endop : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_emb_func_endop : 1; + uint8_t int2_cnt_bdr : 1; + uint8_t int2_fifo_full : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_fifo_th : 1; + uint8_t int2_drdy_g_eis : 1; + uint8_t int2_drdy_g : 1; + uint8_t int2_drdy_xl : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_int2_ctrl_t; + +#define LSM6DSV16X_WHO_AM_I 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t id : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t id : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_who_am_i_t; + +#define LSM6DSV16X_CTRL1 0x10U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t odr_xl : 4; + uint8_t op_mode_xl : 3; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t op_mode_xl : 3; + uint8_t odr_xl : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ctrl1_t; + +#define LSM6DSV16X_CTRL2 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t odr_g : 4; + uint8_t op_mode_g : 3; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t op_mode_g : 3; + uint8_t odr_g : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ctrl2_t; + +#define LSM6DSV16X_CTRL3 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sw_reset : 1; + uint8_t not_used0 : 1; + uint8_t if_inc : 1; + uint8_t not_used1 : 3; + uint8_t bdu : 1; + uint8_t boot : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t boot : 1; + uint8_t bdu : 1; + uint8_t not_used1 : 3; + uint8_t if_inc : 1; + uint8_t not_used0 : 1; + uint8_t sw_reset : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ctrl3_t; + +#define LSM6DSV16X_CTRL4 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_in_lh : 1; + uint8_t drdy_pulsed : 1; + uint8_t int2_drdy_temp : 1; + uint8_t drdy_mask : 1; + uint8_t int2_on_int1 : 1; + uint8_t not_used0 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 3; + uint8_t int2_on_int1 : 1; + uint8_t drdy_mask : 1; + uint8_t int2_drdy_temp : 1; + uint8_t drdy_pulsed : 1; + uint8_t int2_in_lh : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ctrl4_t; + +#define LSM6DSV16X_CTRL5 0x14U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int_en_i3c : 1; + uint8_t bus_act_sel : 2; + uint8_t not_used0 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 5; + uint8_t bus_act_sel : 2; + uint8_t int_en_i3c : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ctrl5_t; + +#define LSM6DSV16X_CTRL6 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_g : 4; + uint8_t lpf1_g_bw : 3; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t lpf1_g_bw : 3; + uint8_t fs_g : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ctrl6_t; + +#define LSM6DSV16X_CTRL7 0x16U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t lpf1_g_en : 1; + uint8_t not_used0 : 3; + uint8_t ah_qvar_c_zin : 2; + uint8_t int2_drdy_ah_qvar : 1; + uint8_t ah_qvar_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ah_qvar_en : 1; + uint8_t int2_drdy_ah_qvar : 1; + uint8_t ah_qvar_c_zin : 2; + uint8_t not_used0 : 3; + uint8_t lpf1_g_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ctrl7_t; + +#define LSM6DSV16X_CTRL8 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_xl : 2; + uint8_t not_used0 : 1; + uint8_t xl_dualc_en : 1; + uint8_t not_used1 : 1; + uint8_t hp_lpf2_xl_bw : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t hp_lpf2_xl_bw : 3; + uint8_t not_used1 : 1; + uint8_t xl_dualc_en : 1; + uint8_t not_used0 : 1; + uint8_t fs_xl : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ctrl8_t; + +#define LSM6DSV16X_CTRL9 0x18U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t usr_off_on_out : 1; + uint8_t usr_off_w : 1; + uint8_t not_used0 : 1; + uint8_t lpf2_xl_en : 1; + uint8_t hp_slope_xl_en : 1; + uint8_t xl_fastsettl_mode : 1; + uint8_t hp_ref_mode_xl : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t hp_ref_mode_xl : 1; + uint8_t xl_fastsettl_mode : 1; + uint8_t hp_slope_xl_en : 1; + uint8_t lpf2_xl_en : 1; + uint8_t not_used0 : 1; + uint8_t usr_off_w : 1; + uint8_t usr_off_on_out : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ctrl9_t; + +#define LSM6DSV16X_CTRL10 0x19U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t st_xl : 2; + uint8_t st_g : 2; + uint8_t not_used0 : 2; + uint8_t emb_func_debug : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t emb_func_debug : 1; + uint8_t not_used0 : 2; + uint8_t st_g : 2; + uint8_t st_xl : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ctrl10_t; + +#define LSM6DSV16X_CTRL_STATUS 0x1AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t fsm_wr_ctrl_status : 1; + uint8_t not_used1 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 5; + uint8_t fsm_wr_ctrl_status : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ctrl_status_t; + +#define LSM6DSV16X_FIFO_STATUS1 0x1BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t diff_fifo : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t diff_fifo : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fifo_status1_t; + +#define LSM6DSV16X_FIFO_STATUS2 0x1CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t diff_fifo : 1; + uint8_t not_used0 : 2; + uint8_t fifo_ovr_latched : 1; + uint8_t counter_bdr_ia : 1; + uint8_t fifo_full_ia : 1; + uint8_t fifo_ovr_ia : 1; + uint8_t fifo_wtm_ia : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_wtm_ia : 1; + uint8_t fifo_ovr_ia : 1; + uint8_t fifo_full_ia : 1; + uint8_t counter_bdr_ia : 1; + uint8_t fifo_ovr_latched : 1; + uint8_t not_used0 : 2; + uint8_t diff_fifo : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fifo_status2_t; + +#define LSM6DSV16X_ALL_INT_SRC 0x1DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ff_ia : 1; + uint8_t wu_ia : 1; + uint8_t tap_ia : 1; + uint8_t not_used0 : 1; + uint8_t d6d_ia : 1; + uint8_t sleep_change_ia : 1; + uint8_t shub_ia : 1; + uint8_t emb_func_ia : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t emb_func_ia : 1; + uint8_t shub_ia : 1; + uint8_t sleep_change_ia : 1; + uint8_t d6d_ia : 1; + uint8_t not_used0 : 1; + uint8_t tap_ia : 1; + uint8_t wu_ia : 1; + uint8_t ff_ia : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_all_int_src_t; + +#define LSM6DSV16X_STATUS_REG 0x1EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xlda : 1; + uint8_t gda : 1; + uint8_t tda : 1; + uint8_t ah_qvarda : 1; + uint8_t gda_eis : 1; + uint8_t ois_drdy : 1; + uint8_t not_used0 : 1; + uint8_t timestamp_endcount : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp_endcount : 1; + uint8_t not_used0 : 1; + uint8_t ois_drdy : 1; + uint8_t gda_eis : 1; + uint8_t ah_qvarda : 1; + uint8_t tda : 1; + uint8_t gda : 1; + uint8_t xlda : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_status_reg_t; + +#define LSM6DSV16X_OUT_TEMP_L 0x20U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t temp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t temp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_out_temp_l_t; + +#define LSM6DSV16X_OUT_TEMP_H 0x21U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t temp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t temp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_out_temp_h_t; + +#define LSM6DSV16X_OUTX_L_G 0x22U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_outx_l_g_t; + +#define LSM6DSV16X_OUTX_H_G 0x23U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_outx_h_g_t; + +#define LSM6DSV16X_OUTY_L_G 0x24U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_outy_l_g_t; + +#define LSM6DSV16X_OUTY_H_G 0x25U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_outy_h_g_t; + +#define LSM6DSV16X_OUTZ_L_G 0x26U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_outz_l_g_t; + +#define LSM6DSV16X_OUTZ_H_G 0x27U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_outz_h_g_t; + +#define LSM6DSV16X_OUTX_L_A 0x28U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_outx_l_a_t; + +#define LSM6DSV16X_OUTX_H_A 0x29U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_outx_h_a_t; + +#define LSM6DSV16X_OUTY_L_A 0x2AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_outy_l_a_t; + +#define LSM6DSV16X_OUTY_H_A 0x2BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_outy_h_a_t; + +#define LSM6DSV16X_OUTZ_L_A 0x2CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_outz_l_a_t; + +#define LSM6DSV16X_OUTZ_H_A 0x2DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_outz_h_a_t; + +#define LSM6DSV16X_UI_OUTX_L_G_OIS_EIS 0x2EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outx_g_ois_eis : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outx_g_ois_eis : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ui_outx_l_g_ois_eis_t; + +#define LSM6DSV16X_UI_OUTX_H_G_OIS_EIS 0x2FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outx_g_ois_eis : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outx_g_ois_eis : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ui_outx_h_g_ois_eis_t; + +#define LSM6DSV16X_UI_OUTY_L_G_OIS_EIS 0x30U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outy_g_ois_eis : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outy_g_ois_eis : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ui_outy_l_g_ois_eis_t; + +#define LSM6DSV16X_UI_OUTY_H_G_OIS_EIS 0x31U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outy_g_ois_eis : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outy_g_ois_eis : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ui_outy_h_g_ois_eis_t; + +#define LSM6DSV16X_UI_OUTZ_L_G_OIS_EIS 0x32U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outz_g_ois_eis : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outz_g_ois_eis : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ui_outz_l_g_ois_eis_t; + +#define LSM6DSV16X_UI_OUTZ_H_G_OIS_EIS 0x33U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outz_g_ois_eis : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outz_g_ois_eis : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ui_outz_h_g_ois_eis_t; + +#define LSM6DSV16X_UI_OUTX_L_A_OIS_DUALC 0x34U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outx_a_ois_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outx_a_ois_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ui_outx_l_a_ois_dualc_t; + +#define LSM6DSV16X_UI_OUTX_H_A_OIS_DUALC 0x35U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outx_a_ois_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outx_a_ois_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ui_outx_h_a_ois_dualc_t; + +#define LSM6DSV16X_UI_OUTY_L_A_OIS_DUALC 0x36U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outy_a_ois_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outy_a_ois_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ui_outy_l_a_ois_dualc_t; + +#define LSM6DSV16X_UI_OUTY_H_A_OIS_DUALC 0x37U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outy_a_ois_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outy_a_ois_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ui_outy_h_a_ois_dualc_t; + +#define LSM6DSV16X_UI_OUTZ_L_A_OIS_DUALC 0x38U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outz_a_ois_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outz_a_ois_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ui_outz_l_a_ois_dualc_t; + +#define LSM6DSV16X_UI_OUTZ_H_A_OIS_DUALC 0x39U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outz_a_ois_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outz_a_ois_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ui_outz_h_a_ois_dualc_t; + +#define LSM6DSV16X_AH_QVAR_OUT_L 0x3AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ah_qvar : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ah_qvar : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ah_qvar_out_l_t; + +#define LSM6DSV16X_AH_QVAR_OUT_H 0x3BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ah_qvar : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ah_qvar : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ah_qvar_out_h_t; + +#define LSM6DSV16X_TIMESTAMP0 0x40U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_timestamp0_t; + +#define LSM6DSV16X_TIMESTAMP1 0x41U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_timestamp1_t; + +#define LSM6DSV16X_TIMESTAMP2 0x42U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_timestamp2_t; + +#define LSM6DSV16X_TIMESTAMP3 0x43U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_timestamp3_t; + +#define LSM6DSV16X_UI_STATUS_REG_OIS 0x44U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xlda_ois : 1; + uint8_t gda_ois : 1; + uint8_t gyro_settling : 1; + uint8_t not_used0 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 5; + uint8_t gyro_settling : 1; + uint8_t gda_ois : 1; + uint8_t xlda_ois : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ui_status_reg_ois_t; + +#define LSM6DSV16X_WAKE_UP_SRC 0x45U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t z_wu : 1; + uint8_t y_wu : 1; + uint8_t x_wu : 1; + uint8_t wu_ia : 1; + uint8_t sleep_state : 1; + uint8_t ff_ia : 1; + uint8_t sleep_change_ia : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t sleep_change_ia : 1; + uint8_t ff_ia : 1; + uint8_t sleep_state : 1; + uint8_t wu_ia : 1; + uint8_t x_wu : 1; + uint8_t y_wu : 1; + uint8_t z_wu : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_wake_up_src_t; + +#define LSM6DSV16X_TAP_SRC 0x46U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t z_tap : 1; + uint8_t y_tap : 1; + uint8_t x_tap : 1; + uint8_t tap_sign : 1; + uint8_t double_tap : 1; + uint8_t single_tap : 1; + uint8_t tap_ia : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t tap_ia : 1; + uint8_t single_tap : 1; + uint8_t double_tap : 1; + uint8_t tap_sign : 1; + uint8_t x_tap : 1; + uint8_t y_tap : 1; + uint8_t z_tap : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_tap_src_t; + +#define LSM6DSV16X_D6D_SRC 0x47U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xl : 1; + uint8_t xh : 1; + uint8_t yl : 1; + uint8_t yh : 1; + uint8_t zl : 1; + uint8_t zh : 1; + uint8_t d6d_ia : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t d6d_ia : 1; + uint8_t zh : 1; + uint8_t zl : 1; + uint8_t yh : 1; + uint8_t yl : 1; + uint8_t xh : 1; + uint8_t xl : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_d6d_src_t; + +#define LSM6DSV16X_STATUS_MASTER_MAINPAGE 0x48U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sens_hub_endop : 1; + uint8_t not_used0 : 2; + uint8_t slave0_nack : 1; + uint8_t slave1_nack : 1; + uint8_t slave2_nack : 1; + uint8_t slave3_nack : 1; + uint8_t wr_once_done : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t wr_once_done : 1; + uint8_t slave3_nack : 1; + uint8_t slave2_nack : 1; + uint8_t slave1_nack : 1; + uint8_t slave0_nack : 1; + uint8_t not_used0 : 2; + uint8_t sens_hub_endop : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_status_master_mainpage_t; + +#define LSM6DSV16X_EMB_FUNC_STATUS_MAINPAGE 0x49U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t is_step_det : 1; + uint8_t is_tilt : 1; + uint8_t is_sigmot : 1; + uint8_t not_used1 : 1; + uint8_t is_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t is_sigmot : 1; + uint8_t is_tilt : 1; + uint8_t is_step_det : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_emb_func_status_mainpage_t; + +#define LSM6DSV16X_FSM_STATUS_MAINPAGE 0x4AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm1 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm8 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_status_mainpage_t; + +#define LSM6DSV16X_MLC_STATUS_MAINPAGE 0x4BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_mlc1 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc4 : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t is_mlc4 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_mlc_status_mainpage_t; + +#define LSM6DSV16X_INTERNAL_FREQ 0x4FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t freq_fine : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t freq_fine : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_internal_freq_t; + +#define LSM6DSV16X_FUNCTIONS_ENABLE 0x50U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t inact_en : 2; + uint8_t not_used0 : 1; + uint8_t dis_rst_lir_all_int : 1; + uint8_t not_used1 : 2; + uint8_t timestamp_en : 1; + uint8_t interrupts_enable : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t interrupts_enable : 1; + uint8_t timestamp_en : 1; + uint8_t not_used1 : 2; + uint8_t dis_rst_lir_all_int : 1; + uint8_t not_used0 : 1; + uint8_t inact_en : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_functions_enable_t; + +#define LSM6DSV16X_DEN 0x51U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t den_xl_g : 1; + uint8_t den_z : 1; + uint8_t den_y : 1; + uint8_t den_x : 1; + uint8_t den_xl_en : 1; + uint8_t lvl2_en : 1; + uint8_t lvl1_en : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t lvl1_en : 1; + uint8_t lvl2_en : 1; + uint8_t den_xl_en : 1; + uint8_t den_x : 1; + uint8_t den_y : 1; + uint8_t den_z : 1; + uint8_t den_xl_g : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_den_t; + +#define LSM6DSV16X_INACTIVITY_DUR 0x54U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t inact_dur : 2; + uint8_t xl_inact_odr : 2; + uint8_t wu_inact_ths_w : 3; + uint8_t sleep_status_on_int : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sleep_status_on_int : 1; + uint8_t wu_inact_ths_w : 3; + uint8_t xl_inact_odr : 2; + uint8_t inact_dur : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_inactivity_dur_t; + +#define LSM6DSV16X_INACTIVITY_THS 0x55U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t inact_ths : 6; + uint8_t not_used0 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 2; + uint8_t inact_ths : 6; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_inactivity_ths_t; + +#define LSM6DSV16X_TAP_CFG0 0x56U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t lir : 1; + uint8_t tap_z_en : 1; + uint8_t tap_y_en : 1; + uint8_t tap_x_en : 1; + uint8_t slope_fds : 1; + uint8_t hw_func_mask_xl_settl : 1; + uint8_t low_pass_on_6d : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t low_pass_on_6d : 1; + uint8_t hw_func_mask_xl_settl : 1; + uint8_t slope_fds : 1; + uint8_t tap_x_en : 1; + uint8_t tap_y_en : 1; + uint8_t tap_z_en : 1; + uint8_t lir : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_tap_cfg0_t; + +#define LSM6DSV16X_TAP_CFG1 0x57U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tap_ths_x : 5; + uint8_t tap_priority : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tap_priority : 3; + uint8_t tap_ths_x : 5; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_tap_cfg1_t; + +#define LSM6DSV16X_TAP_CFG2 0x58U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tap_ths_y : 5; + uint8_t not_used0 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 3; + uint8_t tap_ths_y : 5; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_tap_cfg2_t; + +#define LSM6DSV16X_TAP_THS_6D 0x59U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tap_ths_z : 5; + uint8_t sixd_ths : 2; + uint8_t d4d_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t d4d_en : 1; + uint8_t sixd_ths : 2; + uint8_t tap_ths_z : 5; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_tap_ths_6d_t; + +#define LSM6DSV16X_TAP_DUR 0x5AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t shock : 2; + uint8_t quiet : 2; + uint8_t dur : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dur : 4; + uint8_t quiet : 2; + uint8_t shock : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_tap_dur_t; + +#define LSM6DSV16X_WAKE_UP_THS 0x5BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wk_ths : 6; + uint8_t usr_off_on_wu : 1; + uint8_t single_double_tap : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t single_double_tap : 1; + uint8_t usr_off_on_wu : 1; + uint8_t wk_ths : 6; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_wake_up_ths_t; + +#define LSM6DSV16X_WAKE_UP_DUR 0x5CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sleep_dur : 4; + uint8_t not_used0 : 1; + uint8_t wake_dur : 2; + uint8_t ff_dur : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ff_dur : 1; + uint8_t wake_dur : 2; + uint8_t not_used0 : 1; + uint8_t sleep_dur : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_wake_up_dur_t; + +#define LSM6DSV16X_FREE_FALL 0x5DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ff_ths : 3; + uint8_t ff_dur : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ff_dur : 5; + uint8_t ff_ths : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_free_fall_t; + +#define LSM6DSV16X_MD1_CFG 0x5EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_shub : 1; + uint8_t int1_emb_func : 1; + uint8_t int1_6d : 1; + uint8_t int1_double_tap : 1; + uint8_t int1_ff : 1; + uint8_t int1_wu : 1; + uint8_t int1_single_tap : 1; + uint8_t int1_sleep_change : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_sleep_change : 1; + uint8_t int1_single_tap : 1; + uint8_t int1_wu : 1; + uint8_t int1_ff : 1; + uint8_t int1_double_tap : 1; + uint8_t int1_6d : 1; + uint8_t int1_emb_func : 1; + uint8_t int1_shub : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_md1_cfg_t; + +#define LSM6DSV16X_MD2_CFG 0x5FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_timestamp : 1; + uint8_t int2_emb_func : 1; + uint8_t int2_6d : 1; + uint8_t int2_double_tap : 1; + uint8_t int2_ff : 1; + uint8_t int2_wu : 1; + uint8_t int2_single_tap : 1; + uint8_t int2_sleep_change : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_sleep_change : 1; + uint8_t int2_single_tap : 1; + uint8_t int2_wu : 1; + uint8_t int2_ff : 1; + uint8_t int2_double_tap : 1; + uint8_t int2_6d : 1; + uint8_t int2_emb_func : 1; + uint8_t int2_timestamp : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_md2_cfg_t; + +#define LSM6DSV16X_HAODR_CFG 0x62U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t haodr_sel : 2; + uint8_t not_used0 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 6; + uint8_t haodr_sel : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_haodr_cfg_t; + +#define LSM6DSV16X_EMB_FUNC_CFG 0x63U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t emb_func_disable : 1; + uint8_t emb_func_irq_mask_xl_settl : 1; + uint8_t emb_func_irq_mask_g_settl : 1; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t emb_func_irq_mask_g_settl : 1; + uint8_t emb_func_irq_mask_xl_settl : 1; + uint8_t emb_func_disable : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_emb_func_cfg_t; + +#define LSM6DSV16X_UI_HANDSHAKE_CTRL 0x64U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_shared_req : 1; + uint8_t ui_shared_ack : 1; + uint8_t not_used0 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 6; + uint8_t ui_shared_ack : 1; + uint8_t ui_shared_req : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ui_handshake_ctrl_t; + +#define LSM6DSV16X_UI_SPI2_SHARED_0 0x65U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_spi2_shared : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_spi2_shared : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ui_spi2_shared_0_t; + +#define LSM6DSV16X_UI_SPI2_SHARED_1 0x66U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_spi2_shared : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_spi2_shared : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ui_spi2_shared_1_t; + +#define LSM6DSV16X_UI_SPI2_SHARED_2 0x67U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_spi2_shared : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_spi2_shared : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ui_spi2_shared_2_t; + +#define LSM6DSV16X_UI_SPI2_SHARED_3 0x68U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_spi2_shared : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_spi2_shared : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ui_spi2_shared_3_t; + +#define LSM6DSV16X_UI_SPI2_SHARED_4 0x69U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_spi2_shared : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_spi2_shared : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ui_spi2_shared_4_t; + +#define LSM6DSV16X_UI_SPI2_SHARED_5 0x6AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_spi2_shared : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_spi2_shared : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ui_spi2_shared_5_t; + +#define LSM6DSV16X_CTRL_EIS 0x6BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_g_eis : 3; + uint8_t g_eis_on_g_ois_out_reg : 1; + uint8_t lpf_g_eis_bw : 1; + uint8_t not_used0 : 1; + uint8_t odr_g_eis : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t odr_g_eis : 2; + uint8_t not_used0 : 1; + uint8_t lpf_g_eis_bw : 1; + uint8_t g_eis_on_g_ois_out_reg : 1; + uint8_t fs_g_eis : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ctrl_eis_t; + +#define LSM6DSV16X_UI_INT_OIS 0x6FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 4; + uint8_t st_ois_clampdis : 1; + uint8_t not_used1 : 1; + uint8_t drdy_mask_ois : 1; + uint8_t int2_drdy_ois : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_drdy_ois : 1; + uint8_t drdy_mask_ois : 1; + uint8_t not_used1 : 1; + uint8_t st_ois_clampdis : 1; + uint8_t not_used0 : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ui_int_ois_t; + +#define LSM6DSV16X_UI_CTRL1_OIS 0x70U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_read_en : 1; + uint8_t ois_g_en : 1; + uint8_t ois_xl_en : 1; + uint8_t not_used0 : 2; + uint8_t sim_ois : 1; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t sim_ois : 1; + uint8_t not_used0 : 2; + uint8_t ois_xl_en : 1; + uint8_t ois_g_en : 1; + uint8_t spi2_read_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ui_ctrl1_ois_t; + +#define LSM6DSV16X_UI_CTRL2_OIS 0x71U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_g_ois : 3; + uint8_t lpf1_g_ois_bw : 2; + uint8_t not_used0 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 3; + uint8_t lpf1_g_ois_bw : 2; + uint8_t fs_g_ois : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ui_ctrl2_ois_t; + +#define LSM6DSV16X_UI_CTRL3_OIS 0x72U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_xl_ois : 2; + uint8_t not_used0 : 1; + uint8_t lpf_xl_ois_bw : 3; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t lpf_xl_ois_bw : 3; + uint8_t not_used0 : 1; + uint8_t fs_xl_ois : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ui_ctrl3_ois_t; + +#define LSM6DSV16X_X_OFS_USR 0x73U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t x_ofs_usr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t x_ofs_usr : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_x_ofs_usr_t; + +#define LSM6DSV16X_Y_OFS_USR 0x74U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t y_ofs_usr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t y_ofs_usr : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_y_ofs_usr_t; + +#define LSM6DSV16X_Z_OFS_USR 0x75U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t z_ofs_usr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t z_ofs_usr : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_z_ofs_usr_t; + +#define LSM6DSV16X_FIFO_DATA_OUT_TAG 0x78U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t tag_cnt : 2; + uint8_t tag_sensor : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tag_sensor : 5; + uint8_t tag_cnt : 2; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fifo_data_out_tag_t; + +#define LSM6DSV16X_FIFO_DATA_OUT_X_L 0x79U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fifo_data_out_x_l_t; + +#define LSM6DSV16X_FIFO_DATA_OUT_X_H 0x7AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fifo_data_out_x_h_t; + +#define LSM6DSV16X_FIFO_DATA_OUT_Y_L 0x7BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fifo_data_out_y_l_t; + +#define LSM6DSV16X_FIFO_DATA_OUT_Y_H 0x7CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fifo_data_out_y_h_t; + +#define LSM6DSV16X_FIFO_DATA_OUT_Z_L 0x7DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fifo_data_out_z_l_t; + +#define LSM6DSV16X_FIFO_DATA_OUT_Z_H 0x7EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fifo_data_out_z_h_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page spi2 + * @{ + * + */ + +#define LSM6DSV16X_SPI2_WHO_AM_I 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t id : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t id : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_spi2_who_am_i_t; + +#define LSM6DSV16X_SPI2_STATUS_REG_OIS 0x1EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xlda : 1; + uint8_t gda : 1; + uint8_t gyro_settling : 1; + uint8_t not_used0 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 5; + uint8_t gyro_settling : 1; + uint8_t gda : 1; + uint8_t xlda : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_spi2_status_reg_ois_t; + +#define LSM6DSV16X_SPI2_OUT_TEMP_L 0x20U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t temp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t temp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_spi2_out_temp_l_t; + +#define LSM6DSV16X_SPI2_OUT_TEMP_H 0x21U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t temp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t temp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_spi2_out_temp_h_t; + +#define LSM6DSV16X_SPI2_OUTX_L_G_OIS 0x22U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outx_g_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outx_g_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_spi2_outx_l_g_ois_t; + +#define LSM6DSV16X_SPI2_OUTX_H_G_OIS 0x23U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outx_g_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outx_g_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_spi2_outx_h_g_ois_t; + +#define LSM6DSV16X_SPI2_OUTY_L_G_OIS 0x24U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outy_g_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outy_g_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_spi2_outy_l_g_ois_t; + +#define LSM6DSV16X_SPI2_OUTY_H_G_OIS 0x25U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outy_g_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outy_g_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_spi2_outy_h_g_ois_t; + +#define LSM6DSV16X_SPI2_OUTZ_L_G_OIS 0x26U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outz_g_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outz_g_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_spi2_outz_l_g_ois_t; + +#define LSM6DSV16X_SPI2_OUTZ_H_G_OIS 0x27U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outz_g_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outz_g_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_spi2_outz_h_g_ois_t; + +#define LSM6DSV16X_SPI2_OUTX_L_A_OIS 0x28U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outx_a_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outx_a_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_spi2_outx_l_a_ois_t; + +#define LSM6DSV16X_SPI2_OUTX_H_A_OIS 0x29U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outx_a_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outx_a_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_spi2_outx_h_a_ois_t; + +#define LSM6DSV16X_SPI2_OUTY_L_A_OIS 0x2AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outy_a_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outy_a_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_spi2_outy_l_a_ois_t; + +#define LSM6DSV16X_SPI2_OUTY_H_A_OIS 0x2BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outy_a_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outy_a_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_spi2_outy_h_a_ois_t; + +#define LSM6DSV16X_SPI2_OUTZ_L_A_OIS 0x2CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outz_a_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outz_a_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_spi2_outz_l_a_ois_t; + +#define LSM6DSV16X_SPI2_OUTZ_H_A_OIS 0x2DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outz_a_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outz_a_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_spi2_outz_h_a_ois_t; + +#define LSM6DSV16X_SPI2_HANDSHAKE_CTRL 0x6EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_shared_ack : 1; + uint8_t spi2_shared_req : 1; + uint8_t not_used0 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 6; + uint8_t spi2_shared_req : 1; + uint8_t spi2_shared_ack : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_spi2_handshake_ctrl_t; + +#define LSM6DSV16X_SPI2_INT_OIS 0x6FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t st_xl_ois : 2; + uint8_t st_g_ois : 2; + uint8_t st_ois_clampdis : 1; + uint8_t not_used0 : 1; + uint8_t drdy_mask_ois : 1; + uint8_t int2_drdy_ois : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_drdy_ois : 1; + uint8_t drdy_mask_ois : 1; + uint8_t not_used0 : 1; + uint8_t st_ois_clampdis : 1; + uint8_t st_g_ois : 2; + uint8_t st_xl_ois : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_spi2_int_ois_t; + +#define LSM6DSV16X_SPI2_CTRL1_OIS 0x70U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_read_en : 1; + uint8_t ois_g_en : 1; + uint8_t ois_xl_en : 1; + uint8_t not_used0 : 2; + uint8_t sim_ois : 1; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t sim_ois : 1; + uint8_t not_used0 : 2; + uint8_t ois_xl_en : 1; + uint8_t ois_g_en : 1; + uint8_t spi2_read_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_spi2_ctrl1_ois_t; + +#define LSM6DSV16X_SPI2_CTRL2_OIS 0x71U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_g_ois : 3; + uint8_t lpf1_g_ois_bw : 2; + uint8_t not_used0 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 3; + uint8_t lpf1_g_ois_bw : 2; + uint8_t fs_g_ois : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_spi2_ctrl2_ois_t; + +#define LSM6DSV16X_SPI2_CTRL3_OIS 0x72U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_xl_ois : 2; + uint8_t not_used0 : 1; + uint8_t lpf_xl_ois_bw : 3; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t lpf_xl_ois_bw : 3; + uint8_t not_used0 : 1; + uint8_t fs_xl_ois : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_spi2_ctrl3_ois_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page embedded + * @{ + * + */ + +#define LSM6DSV16X_PAGE_SEL 0x2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 4; + uint8_t page_sel : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_sel : 4; + uint8_t not_used0 : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_page_sel_t; + +#define LSM6DSV16X_EMB_FUNC_EN_A 0x4U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t sflp_game_en : 1; + uint8_t not_used2 : 1; + uint8_t pedo_en : 1; + uint8_t tilt_en : 1; + uint8_t sign_motion_en : 1; + uint8_t not_used1 : 1; + uint8_t mlc_before_fsm_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_before_fsm_en : 1; + uint8_t not_used1 : 1; + uint8_t sign_motion_en : 1; + uint8_t tilt_en : 1; + uint8_t pedo_en : 1; + uint8_t not_used2 : 1; + uint8_t sflp_game_en : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_emb_func_en_a_t; + +#define LSM6DSV16X_EMB_FUNC_EN_B 0x5U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_en : 1; + uint8_t not_used0 : 2; + uint8_t fifo_compr_en : 1; + uint8_t mlc_en : 1; + uint8_t not_used1 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 3; + uint8_t mlc_en : 1; + uint8_t fifo_compr_en : 1; + uint8_t not_used0 : 2; + uint8_t fsm_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_emb_func_en_b_t; + +#define LSM6DSV16X_EMB_FUNC_EXEC_STATUS 0x7U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t emb_func_endop : 1; + uint8_t emb_func_exec_ovr : 1; + uint8_t not_used0 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 6; + uint8_t emb_func_exec_ovr : 1; + uint8_t emb_func_endop : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_emb_func_exec_status_t; + +#define LSM6DSV16X_PAGE_ADDRESS 0x8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t page_addr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_addr : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_page_address_t; + +#define LSM6DSV16X_PAGE_VALUE 0x9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t page_value : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_value : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_page_value_t; + +#define LSM6DSV16X_EMB_FUNC_INT1 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t int1_step_detector : 1; + uint8_t int1_tilt : 1; + uint8_t int1_sig_mot : 1; + uint8_t not_used1 : 1; + uint8_t int1_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t int1_sig_mot : 1; + uint8_t int1_tilt : 1; + uint8_t int1_step_detector : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_emb_func_int1_t; + +#define LSM6DSV16X_FSM_INT1 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_fsm1 : 1; + uint8_t int1_fsm2 : 1; + uint8_t int1_fsm3 : 1; + uint8_t int1_fsm4 : 1; + uint8_t int1_fsm5 : 1; + uint8_t int1_fsm6 : 1; + uint8_t int1_fsm7 : 1; + uint8_t int1_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_fsm8 : 1; + uint8_t int1_fsm7 : 1; + uint8_t int1_fsm6 : 1; + uint8_t int1_fsm5 : 1; + uint8_t int1_fsm4 : 1; + uint8_t int1_fsm3 : 1; + uint8_t int1_fsm2 : 1; + uint8_t int1_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_int1_t; + +#define LSM6DSV16X_MLC_INT1 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_mlc1 : 1; + uint8_t int1_mlc2 : 1; + uint8_t int1_mlc3 : 1; + uint8_t int1_mlc4 : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t int1_mlc4 : 1; + uint8_t int1_mlc3 : 1; + uint8_t int1_mlc2 : 1; + uint8_t int1_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_mlc_int1_t; + +#define LSM6DSV16X_EMB_FUNC_INT2 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t int2_step_detector : 1; + uint8_t int2_tilt : 1; + uint8_t int2_sig_mot : 1; + uint8_t not_used1 : 1; + uint8_t int2_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t int2_sig_mot : 1; + uint8_t int2_tilt : 1; + uint8_t int2_step_detector : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_emb_func_int2_t; + +#define LSM6DSV16X_FSM_INT2 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_fsm1 : 1; + uint8_t int2_fsm2 : 1; + uint8_t int2_fsm3 : 1; + uint8_t int2_fsm4 : 1; + uint8_t int2_fsm5 : 1; + uint8_t int2_fsm6 : 1; + uint8_t int2_fsm7 : 1; + uint8_t int2_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_fsm8 : 1; + uint8_t int2_fsm7 : 1; + uint8_t int2_fsm6 : 1; + uint8_t int2_fsm5 : 1; + uint8_t int2_fsm4 : 1; + uint8_t int2_fsm3 : 1; + uint8_t int2_fsm2 : 1; + uint8_t int2_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_int2_t; + +#define LSM6DSV16X_MLC_INT2 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_mlc1 : 1; + uint8_t int2_mlc2 : 1; + uint8_t int2_mlc3 : 1; + uint8_t int2_mlc4 : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t int2_mlc4 : 1; + uint8_t int2_mlc3 : 1; + uint8_t int2_mlc2 : 1; + uint8_t int2_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_mlc_int2_t; + +#define LSM6DSV16X_EMB_FUNC_STATUS 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t is_step_det : 1; + uint8_t is_tilt : 1; + uint8_t is_sigmot : 1; + uint8_t not_used1 : 1; + uint8_t is_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t is_sigmot : 1; + uint8_t is_tilt : 1; + uint8_t is_step_det : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_emb_func_status_t; + +#define LSM6DSV16X_FSM_STATUS 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm1 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm8 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_status_t; + +#define LSM6DSV16X_MLC_STATUS 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_mlc1 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc4 : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t is_mlc4 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_mlc_status_t; + +#define LSM6DSV16X_PAGE_RW 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 5; + uint8_t page_read : 1; + uint8_t page_write : 1; + uint8_t emb_func_lir : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t emb_func_lir : 1; + uint8_t page_write : 1; + uint8_t page_read : 1; + uint8_t not_used0 : 5; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_page_rw_t; + +#define LSM6DSV16X_EMB_FUNC_FIFO_EN_A 0x44U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t sflp_game_fifo_en : 1; + uint8_t not_used1 : 2; + uint8_t sflp_gravity_fifo_en : 1; + uint8_t sflp_gbias_fifo_en : 1; + uint8_t step_counter_fifo_en : 1; + uint8_t mlc_fifo_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_fifo_en : 1; + uint8_t step_counter_fifo_en : 1; + uint8_t sflp_gbias_fifo_en : 1; + uint8_t sflp_gravity_fifo_en : 1; + uint8_t not_used1 : 2; + uint8_t sflp_game_fifo_en : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_emb_func_fifo_en_a_t; + +#define LSM6DSV16X_EMB_FUNC_FIFO_EN_B 0x45U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t mlc_filter_feature_fifo_en : 1; + uint8_t not_used1 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 6; + uint8_t mlc_filter_feature_fifo_en : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_emb_func_fifo_en_b_t; + +#define LSM6DSV16X_FSM_ENABLE 0x46U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm1_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm8_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm8_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm1_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_enable_t; + +#define LSM6DSV16X_FSM_LONG_COUNTER_L 0x48U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_long_counter_l_t; + +#define LSM6DSV16X_FSM_LONG_COUNTER_H 0x49U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_long_counter_h_t; + +#define LSM6DSV16X_INT_ACK_MASK 0x4BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t iack_mask : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t iack_mask : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_int_ack_mask_t; + +#define LSM6DSV16X_FSM_OUTS1 0x4CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm1_n_v : 1; + uint8_t fsm1_p_v : 1; + uint8_t fsm1_n_z : 1; + uint8_t fsm1_p_z : 1; + uint8_t fsm1_n_y : 1; + uint8_t fsm1_p_y : 1; + uint8_t fsm1_n_x : 1; + uint8_t fsm1_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm1_p_x : 1; + uint8_t fsm1_n_x : 1; + uint8_t fsm1_p_y : 1; + uint8_t fsm1_n_y : 1; + uint8_t fsm1_p_z : 1; + uint8_t fsm1_n_z : 1; + uint8_t fsm1_p_v : 1; + uint8_t fsm1_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_outs1_t; + +#define LSM6DSV16X_FSM_OUTS2 0x4DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm2_n_v : 1; + uint8_t fsm2_p_v : 1; + uint8_t fsm2_n_z : 1; + uint8_t fsm2_p_z : 1; + uint8_t fsm2_n_y : 1; + uint8_t fsm2_p_y : 1; + uint8_t fsm2_n_x : 1; + uint8_t fsm2_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm2_p_x : 1; + uint8_t fsm2_n_x : 1; + uint8_t fsm2_p_y : 1; + uint8_t fsm2_n_y : 1; + uint8_t fsm2_p_z : 1; + uint8_t fsm2_n_z : 1; + uint8_t fsm2_p_v : 1; + uint8_t fsm2_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_outs2_t; + +#define LSM6DSV16X_FSM_OUTS3 0x4EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm3_n_v : 1; + uint8_t fsm3_p_v : 1; + uint8_t fsm3_n_z : 1; + uint8_t fsm3_p_z : 1; + uint8_t fsm3_n_y : 1; + uint8_t fsm3_p_y : 1; + uint8_t fsm3_n_x : 1; + uint8_t fsm3_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm3_p_x : 1; + uint8_t fsm3_n_x : 1; + uint8_t fsm3_p_y : 1; + uint8_t fsm3_n_y : 1; + uint8_t fsm3_p_z : 1; + uint8_t fsm3_n_z : 1; + uint8_t fsm3_p_v : 1; + uint8_t fsm3_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_outs3_t; + +#define LSM6DSV16X_FSM_OUTS4 0x4FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm4_n_v : 1; + uint8_t fsm4_p_v : 1; + uint8_t fsm4_n_z : 1; + uint8_t fsm4_p_z : 1; + uint8_t fsm4_n_y : 1; + uint8_t fsm4_p_y : 1; + uint8_t fsm4_n_x : 1; + uint8_t fsm4_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm4_p_x : 1; + uint8_t fsm4_n_x : 1; + uint8_t fsm4_p_y : 1; + uint8_t fsm4_n_y : 1; + uint8_t fsm4_p_z : 1; + uint8_t fsm4_n_z : 1; + uint8_t fsm4_p_v : 1; + uint8_t fsm4_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_outs4_t; + +#define LSM6DSV16X_FSM_OUTS5 0x50U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm5_n_v : 1; + uint8_t fsm5_p_v : 1; + uint8_t fsm5_n_z : 1; + uint8_t fsm5_p_z : 1; + uint8_t fsm5_n_y : 1; + uint8_t fsm5_p_y : 1; + uint8_t fsm5_n_x : 1; + uint8_t fsm5_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm5_p_x : 1; + uint8_t fsm5_n_x : 1; + uint8_t fsm5_p_y : 1; + uint8_t fsm5_n_y : 1; + uint8_t fsm5_p_z : 1; + uint8_t fsm5_n_z : 1; + uint8_t fsm5_p_v : 1; + uint8_t fsm5_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_outs5_t; + +#define LSM6DSV16X_FSM_OUTS6 0x51U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm6_n_v : 1; + uint8_t fsm6_p_v : 1; + uint8_t fsm6_n_z : 1; + uint8_t fsm6_p_z : 1; + uint8_t fsm6_n_y : 1; + uint8_t fsm6_p_y : 1; + uint8_t fsm6_n_x : 1; + uint8_t fsm6_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm6_p_x : 1; + uint8_t fsm6_n_x : 1; + uint8_t fsm6_p_y : 1; + uint8_t fsm6_n_y : 1; + uint8_t fsm6_p_z : 1; + uint8_t fsm6_n_z : 1; + uint8_t fsm6_p_v : 1; + uint8_t fsm6_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_outs6_t; + +#define LSM6DSV16X_FSM_OUTS7 0x52U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm7_n_v : 1; + uint8_t fsm7_p_v : 1; + uint8_t fsm7_n_z : 1; + uint8_t fsm7_p_z : 1; + uint8_t fsm7_n_y : 1; + uint8_t fsm7_p_y : 1; + uint8_t fsm7_n_x : 1; + uint8_t fsm7_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm7_p_x : 1; + uint8_t fsm7_n_x : 1; + uint8_t fsm7_p_y : 1; + uint8_t fsm7_n_y : 1; + uint8_t fsm7_p_z : 1; + uint8_t fsm7_n_z : 1; + uint8_t fsm7_p_v : 1; + uint8_t fsm7_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_outs7_t; + +#define LSM6DSV16X_FSM_OUTS8 0x53U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm8_n_v : 1; + uint8_t fsm8_p_v : 1; + uint8_t fsm8_n_z : 1; + uint8_t fsm8_p_z : 1; + uint8_t fsm8_n_y : 1; + uint8_t fsm8_p_y : 1; + uint8_t fsm8_n_x : 1; + uint8_t fsm8_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm8_p_x : 1; + uint8_t fsm8_n_x : 1; + uint8_t fsm8_p_y : 1; + uint8_t fsm8_n_y : 1; + uint8_t fsm8_p_z : 1; + uint8_t fsm8_n_z : 1; + uint8_t fsm8_p_v : 1; + uint8_t fsm8_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_outs8_t; + +#define LSM6DSV16X_SFLP_ODR 0x5EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t sflp_game_odr : 3; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t sflp_game_odr : 3; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_sflp_odr_t; + +#define LSM6DSV16X_FSM_ODR 0x5FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t fsm_odr : 3; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t fsm_odr : 3; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_odr_t; + +#define LSM6DSV16X_MLC_ODR 0x60U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 4; + uint8_t mlc_odr : 3; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t mlc_odr : 3; + uint8_t not_used0 : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_mlc_odr_t; + +#define LSM6DSV16X_STEP_COUNTER_L 0x62U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t step : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t step : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_step_counter_l_t; + +#define LSM6DSV16X_STEP_COUNTER_H 0x63U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t step : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t step : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_step_counter_h_t; + +#define LSM6DSV16X_EMB_FUNC_SRC 0x64U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t stepcounter_bit_set : 1; + uint8_t step_overflow : 1; + uint8_t step_count_delta_ia : 1; + uint8_t step_detected : 1; + uint8_t not_used1 : 1; + uint8_t pedo_rst_step : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pedo_rst_step : 1; + uint8_t not_used1 : 1; + uint8_t step_detected : 1; + uint8_t step_count_delta_ia : 1; + uint8_t step_overflow : 1; + uint8_t stepcounter_bit_set : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_emb_func_src_t; + +#define LSM6DSV16X_EMB_FUNC_INIT_A 0x66U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t sflp_game_init : 1; + uint8_t not_used2 : 1; + uint8_t step_det_init : 1; + uint8_t tilt_init : 1; + uint8_t sig_mot_init : 1; + uint8_t not_used1 : 1; + uint8_t mlc_before_fsm_init : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_before_fsm_init : 1; + uint8_t not_used1 : 1; + uint8_t sig_mot_init : 1; + uint8_t tilt_init : 1; + uint8_t step_det_init : 1; + uint8_t not_used2 : 1; + uint8_t sflp_game_init : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_emb_func_init_a_t; + +#define LSM6DSV16X_EMB_FUNC_INIT_B 0x67U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_init : 1; + uint8_t not_used0 : 2; + uint8_t fifo_compr_init : 1; + uint8_t mlc_init : 1; + uint8_t not_used1 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 3; + uint8_t mlc_init : 1; + uint8_t fifo_compr_init : 1; + uint8_t not_used0 : 2; + uint8_t fsm_init : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_emb_func_init_b_t; + +#define LSM6DSV16X_MLC1_SRC 0x70U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc1_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc1_src : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_mlc1_src_t; + +#define LSM6DSV16X_MLC2_SRC 0x71U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc2_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc2_src : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_mlc2_src_t; + +#define LSM6DSV16X_MLC3_SRC 0x72U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc3_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc3_src : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_mlc3_src_t; + +#define LSM6DSV16X_MLC4_SRC 0x73U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc4_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc4_src : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_mlc4_src_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page pg0_emb_adv + * @{ + * + */ +#define LSM6DSV16X_EMB_ADV_PG_0 0x000U + +#define LSM6DSV16X_SFLP_GAME_GBIASX_L 0x6EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasx : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_sflp_game_gbiasx_l_t; + +#define LSM6DSV16X_SFLP_GAME_GBIASX_H 0x6FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasx : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_sflp_game_gbiasx_h_t; + +#define LSM6DSV16X_SFLP_GAME_GBIASY_L 0x70U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasy : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_sflp_game_gbiasy_l_t; + +#define LSM6DSV16X_SFLP_GAME_GBIASY_H 0x71U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasy : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_sflp_game_gbiasy_h_t; + +#define LSM6DSV16X_SFLP_GAME_GBIASZ_L 0x72U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_sflp_game_gbiasz_l_t; + +#define LSM6DSV16X_SFLP_GAME_GBIASZ_H 0x73U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_sflp_game_gbiasz_h_t; + +#define LSM6DSV16X_FSM_EXT_SENSITIVITY_L 0xBAU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_s : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_ext_sensitivity_l_t; + +#define LSM6DSV16X_FSM_EXT_SENSITIVITY_H 0xBBU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_s : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_ext_sensitivity_h_t; + +#define LSM6DSV16X_FSM_EXT_OFFX_L 0xC0U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_offx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_offx : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_ext_offx_l_t; + +#define LSM6DSV16X_FSM_EXT_OFFX_H 0xC1U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_offx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_offx : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_ext_offx_h_t; + +#define LSM6DSV16X_FSM_EXT_OFFY_L 0xC2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_offy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_offy : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_ext_offy_l_t; + +#define LSM6DSV16X_FSM_EXT_OFFY_H 0xC3U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_offy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_offy : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_ext_offy_h_t; + +#define LSM6DSV16X_FSM_EXT_OFFZ_L 0xC4U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_offz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_offz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_ext_offz_l_t; + +#define LSM6DSV16X_FSM_EXT_OFFZ_H 0xC5U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_offz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_offz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_ext_offz_h_t; + +#define LSM6DSV16X_FSM_EXT_MATRIX_XX_L 0xC6U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_xx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_xx : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_ext_matrix_xx_l_t; + +#define LSM6DSV16X_FSM_EXT_MATRIX_XX_H 0xC7U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_xx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_xx : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_ext_matrix_xx_h_t; + +#define LSM6DSV16X_FSM_EXT_MATRIX_XY_L 0xC8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_xy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_xy : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_ext_matrix_xy_l_t; + +#define LSM6DSV16X_FSM_EXT_MATRIX_XY_H 0xC9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_xy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_xy : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_ext_matrix_xy_h_t; + +#define LSM6DSV16X_FSM_EXT_MATRIX_XZ_L 0xCAU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_xz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_xz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_ext_matrix_xz_l_t; + +#define LSM6DSV16X_FSM_EXT_MATRIX_XZ_H 0xCBU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_xz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_xz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_ext_matrix_xz_h_t; + +#define LSM6DSV16X_FSM_EXT_MATRIX_YY_L 0xCCU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_yy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_yy : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_ext_matrix_yy_l_t; + +#define LSM6DSV16X_FSM_EXT_MATRIX_YY_H 0xCDU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_yy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_yy : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_ext_matrix_yy_h_t; + +#define LSM6DSV16X_FSM_EXT_MATRIX_YZ_L 0xCEU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_yz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_yz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_ext_matrix_yz_l_t; + +#define LSM6DSV16X_FSM_EXT_MATRIX_YZ_H 0xCFU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_yz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_yz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_ext_matrix_yz_h_t; + +#define LSM6DSV16X_FSM_EXT_MATRIX_ZZ_L 0xD0U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_zz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_zz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_ext_matrix_zz_l_t; + +#define LSM6DSV16X_FSM_EXT_MATRIX_ZZ_H 0xD1U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_zz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_zz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_ext_matrix_zz_h_t; + +#define LSM6DSV16X_EXT_CFG_A 0xD4U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ext_z_axis : 3; + uint8_t not_used0 : 1; + uint8_t ext_y_axis : 3; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t ext_y_axis : 3; + uint8_t not_used0 : 1; + uint8_t ext_z_axis : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ext_cfg_a_t; + +#define LSM6DSV16X_EXT_CFG_B 0xD5U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ext_x_axis : 3; + uint8_t not_used0 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 5; + uint8_t ext_x_axis : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ext_cfg_b_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page pg1_emb_adv + * @{ + * + */ +#define LSM6DSV16X_EMB_ADV_PG_1 0x100U + +#define LSM6DSV16X_FSM_LC_TIMEOUT_L 0x7AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc_timeout : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc_timeout : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_lc_timeout_l_t; + +#define LSM6DSV16X_FSM_LC_TIMEOUT_H 0x7BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc_timeout : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc_timeout : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_lc_timeout_h_t; + +#define LSM6DSV16X_FSM_PROGRAMS 0x7CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_n_prog : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_n_prog : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_programs_t; + +#define LSM6DSV16X_FSM_START_ADD_L 0x7EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_start : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_start : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_start_add_l_t; + +#define LSM6DSV16X_FSM_START_ADD_H 0x7FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_start : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_start : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_fsm_start_add_h_t; + +#define LSM6DSV16X_PEDO_CMD_REG 0x83U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t fp_rejection_en : 1; + uint8_t carry_count_en : 1; + uint8_t not_used1 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 4; + uint8_t carry_count_en : 1; + uint8_t fp_rejection_en : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_pedo_cmd_reg_t; + +#define LSM6DSV16X_PEDO_DEB_STEPS_CONF 0x84U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t deb_step : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t deb_step : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_pedo_deb_steps_conf_t; + +#define LSM6DSV16X_PEDO_SC_DELTAT_L 0xD0U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t pd_sc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pd_sc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_pedo_sc_deltat_l_t; + +#define LSM6DSV16X_PEDO_SC_DELTAT_H 0xD1U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t pd_sc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pd_sc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_pedo_sc_deltat_h_t; + +#define LSM6DSV16X_MLC_EXT_SENSITIVITY_L 0xE8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc_ext_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_ext_s : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_mlc_ext_sensitivity_l_t; + +#define LSM6DSV16X_MLC_EXT_SENSITIVITY_H 0xE9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc_ext_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_ext_s : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_mlc_ext_sensitivity_h_t; + +/** @defgroup bitfields page pg2_emb_adv + * @{ + * + */ +#define LSM6DSV16X_EMB_ADV_PG_2 0x200U + +#define LSM6DSV16X_EXT_FORMAT 0x00 +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t ext_format_sel : 1; + uint8_t not_used1 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 5; + uint8_t ext_format_sel : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ext_format_t; + +#define LSM6DSV16X_EXT_3BYTE_SENSITIVITY_L 0x02U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ext_3byte_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ext_3byte_s : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ext_3byte_sensitivity_l_t; + +#define LSM6DSV16X_EXT_3BYTE_SENSITIVITY_H 0x03U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ext_3byte_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ext_3byte_s : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ext_3byte_sensitivity_h_t; + +#define LSM6DSV16X_EXT_3BYTE_OFFSET_XL 0x06U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ext_3byte_off : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ext_3byte_off : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ext_3byte_offset_xl_t; + +#define LSM6DSV16X_EXT_3BYTE_OFFSET_L 0x07U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ext_3byte_off : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ext_3byte_off : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ext_3byte_offset_l_t; + +#define LSM6DSV16X_EXT_3BYTE_OFFSET_H 0x08U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ext_3byte_off : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ext_3byte_off : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_ext_3byte_offset_h_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page sensor_hub + * @{ + * + */ + +#define LSM6DSV16X_SENSOR_HUB_1 0x2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub1 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub1 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_sensor_hub_1_t; + +#define LSM6DSV16X_SENSOR_HUB_2 0x3U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub2 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub2 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_sensor_hub_2_t; + +#define LSM6DSV16X_SENSOR_HUB_3 0x4U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub3 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub3 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_sensor_hub_3_t; + +#define LSM6DSV16X_SENSOR_HUB_4 0x5U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub4 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub4 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_sensor_hub_4_t; + +#define LSM6DSV16X_SENSOR_HUB_5 0x6U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub5 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub5 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_sensor_hub_5_t; + +#define LSM6DSV16X_SENSOR_HUB_6 0x7U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub6 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub6 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_sensor_hub_6_t; + +#define LSM6DSV16X_SENSOR_HUB_7 0x8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub7 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub7 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_sensor_hub_7_t; + +#define LSM6DSV16X_SENSOR_HUB_8 0x9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub8 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub8 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_sensor_hub_8_t; + +#define LSM6DSV16X_SENSOR_HUB_9 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub9 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub9 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_sensor_hub_9_t; + +#define LSM6DSV16X_SENSOR_HUB_10 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub10 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub10 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_sensor_hub_10_t; + +#define LSM6DSV16X_SENSOR_HUB_11 0x0CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub11 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub11 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_sensor_hub_11_t; + +#define LSM6DSV16X_SENSOR_HUB_12 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub12 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub12 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_sensor_hub_12_t; + +#define LSM6DSV16X_SENSOR_HUB_13 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub13 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub13 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_sensor_hub_13_t; + +#define LSM6DSV16X_SENSOR_HUB_14 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub14 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub14 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_sensor_hub_14_t; + +#define LSM6DSV16X_SENSOR_HUB_15 0x10U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub15 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub15 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_sensor_hub_15_t; + +#define LSM6DSV16X_SENSOR_HUB_16 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub16 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub16 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_sensor_hub_16_t; + +#define LSM6DSV16X_SENSOR_HUB_17 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub17 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub17 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_sensor_hub_17_t; + +#define LSM6DSV16X_SENSOR_HUB_18 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub18 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub18 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_sensor_hub_18_t; + +#define LSM6DSV16X_MASTER_CONFIG 0x14U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t aux_sens_on : 2; + uint8_t master_on : 1; + uint8_t not_used0 : 1; + uint8_t pass_through_mode : 1; + uint8_t start_config : 1; + uint8_t write_once : 1; + uint8_t rst_master_regs : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t rst_master_regs : 1; + uint8_t write_once : 1; + uint8_t start_config : 1; + uint8_t pass_through_mode : 1; + uint8_t not_used0 : 1; + uint8_t master_on : 1; + uint8_t aux_sens_on : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_master_config_t; + +#define LSM6DSV16X_SLV0_ADD 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t rw_0 : 1; + uint8_t slave0_add : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave0_add : 7; + uint8_t rw_0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_slv0_add_t; + +#define LSM6DSV16X_SLV0_SUBADD 0x16U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave0_reg : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave0_reg : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_slv0_subadd_t; + +#define LSM6DSV16X_SLV0_CONFIG 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave0_numop : 3; + uint8_t batch_ext_sens_0_en : 1; + uint8_t not_used0 : 1; + uint8_t shub_odr : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t shub_odr : 3; + uint8_t not_used0 : 1; + uint8_t batch_ext_sens_0_en : 1; + uint8_t slave0_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_slv0_config_t; + +#define LSM6DSV16X_SLV1_ADD 0x18U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t r_1 : 1; + uint8_t slave1_add : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave1_add : 7; + uint8_t r_1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_slv1_add_t; + +#define LSM6DSV16X_SLV1_SUBADD 0x19U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave1_reg : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave1_reg : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_slv1_subadd_t; + +#define LSM6DSV16X_SLV1_CONFIG 0x1AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave1_numop : 3; + uint8_t batch_ext_sens_1_en : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t batch_ext_sens_1_en : 1; + uint8_t slave1_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_slv1_config_t; + +#define LSM6DSV16X_SLV2_ADD 0x1BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t r_2 : 1; + uint8_t slave2_add : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave2_add : 7; + uint8_t r_2 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_slv2_add_t; + +#define LSM6DSV16X_SLV2_SUBADD 0x1CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave2_reg : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave2_reg : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_slv2_subadd_t; + +#define LSM6DSV16X_SLV2_CONFIG 0x1DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave2_numop : 3; + uint8_t batch_ext_sens_2_en : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t batch_ext_sens_2_en : 1; + uint8_t slave2_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_slv2_config_t; + +#define LSM6DSV16X_SLV3_ADD 0x1EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t r_3 : 1; + uint8_t slave3_add : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave3_add : 7; + uint8_t r_3 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_slv3_add_t; + +#define LSM6DSV16X_SLV3_SUBADD 0x1FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave3_reg : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave3_reg : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_slv3_subadd_t; + +#define LSM6DSV16X_SLV3_CONFIG 0x20U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave3_numop : 3; + uint8_t batch_ext_sens_3_en : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t batch_ext_sens_3_en : 1; + uint8_t slave3_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_slv3_config_t; + +#define LSM6DSV16X_DATAWRITE_SLV0 0x21U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave0_dataw : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave0_dataw : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_datawrite_slv0_t; + +#define LSM6DSV16X_STATUS_MASTER 0x22U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sens_hub_endop : 1; + uint8_t not_used0 : 2; + uint8_t slave0_nack : 1; + uint8_t slave1_nack : 1; + uint8_t slave2_nack : 1; + uint8_t slave3_nack : 1; + uint8_t wr_once_done : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t wr_once_done : 1; + uint8_t slave3_nack : 1; + uint8_t slave2_nack : 1; + uint8_t slave1_nack : 1; + uint8_t slave0_nack : 1; + uint8_t not_used0 : 2; + uint8_t sens_hub_endop : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16x_status_master_t; + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSO_Register_Union + * @brief This union group all the registers having a bit-field + * description. + * This union is useful but it's not needed by the driver. + * + * REMOVING this union you are compliant with: + * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " + * + * @{ + * + */ +typedef union +{ + lsm6dsv16x_func_cfg_access_t func_cfg_access; + lsm6dsv16x_pin_ctrl_t pin_ctrl; + lsm6dsv16x_if_cfg_t if_cfg; + lsm6dsv16x_odr_trig_cfg_t odr_trig_cfg; + lsm6dsv16x_fifo_ctrl1_t fifo_ctrl1; + lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2; + lsm6dsv16x_fifo_ctrl3_t fifo_ctrl3; + lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4; + lsm6dsv16x_counter_bdr_reg1_t counter_bdr_reg1; + lsm6dsv16x_counter_bdr_reg2_t counter_bdr_reg2; + lsm6dsv16x_int1_ctrl_t int1_ctrl; + lsm6dsv16x_int2_ctrl_t int2_ctrl; + lsm6dsv16x_who_am_i_t who_am_i; + lsm6dsv16x_ctrl1_t ctrl1; + lsm6dsv16x_ctrl2_t ctrl2; + lsm6dsv16x_ctrl3_t ctrl3; + lsm6dsv16x_ctrl4_t ctrl4; + lsm6dsv16x_ctrl5_t ctrl5; + lsm6dsv16x_ctrl6_t ctrl6; + lsm6dsv16x_ctrl7_t ctrl7; + lsm6dsv16x_ctrl8_t ctrl8; + lsm6dsv16x_ctrl9_t ctrl9; + lsm6dsv16x_ctrl10_t ctrl10; + lsm6dsv16x_ctrl_status_t ctrl_status; + lsm6dsv16x_fifo_status1_t fifo_status1; + lsm6dsv16x_fifo_status2_t fifo_status2; + lsm6dsv16x_all_int_src_t all_int_src; + lsm6dsv16x_status_reg_t status_reg; + lsm6dsv16x_out_temp_l_t out_temp_l; + lsm6dsv16x_out_temp_h_t out_temp_h; + lsm6dsv16x_outx_l_g_t outx_l_g; + lsm6dsv16x_outx_h_g_t outx_h_g; + lsm6dsv16x_outy_l_g_t outy_l_g; + lsm6dsv16x_outy_h_g_t outy_h_g; + lsm6dsv16x_outz_l_g_t outz_l_g; + lsm6dsv16x_outz_h_g_t outz_h_g; + lsm6dsv16x_outx_l_a_t outx_l_a; + lsm6dsv16x_outx_h_a_t outx_h_a; + lsm6dsv16x_outy_l_a_t outy_l_a; + lsm6dsv16x_outy_h_a_t outy_h_a; + lsm6dsv16x_outz_l_a_t outz_l_a; + lsm6dsv16x_outz_h_a_t outz_h_a; + lsm6dsv16x_ui_outx_l_g_ois_eis_t ui_outx_l_g_ois_eis; + lsm6dsv16x_ui_outx_h_g_ois_eis_t ui_outx_h_g_ois_eis; + lsm6dsv16x_ui_outy_l_g_ois_eis_t ui_outy_l_g_ois_eis; + lsm6dsv16x_ui_outy_h_g_ois_eis_t ui_outy_h_g_ois_eis; + lsm6dsv16x_ui_outz_l_g_ois_eis_t ui_outz_l_g_ois_eis; + lsm6dsv16x_ui_outz_h_g_ois_eis_t ui_outz_h_g_ois_eis; + lsm6dsv16x_ui_outx_l_a_ois_dualc_t ui_outx_l_a_ois_dualc; + lsm6dsv16x_ui_outx_h_a_ois_dualc_t ui_outx_h_a_ois_dualc; + lsm6dsv16x_ui_outy_l_a_ois_dualc_t ui_outy_l_a_ois_dualc; + lsm6dsv16x_ui_outy_h_a_ois_dualc_t ui_outy_h_a_ois_dualc; + lsm6dsv16x_ui_outz_l_a_ois_dualc_t ui_outz_l_a_ois_dualc; + lsm6dsv16x_ui_outz_h_a_ois_dualc_t ui_outz_h_a_ois_dualc; + lsm6dsv16x_ah_qvar_out_l_t ah_qvar_out_l; + lsm6dsv16x_ah_qvar_out_h_t ah_qvar_out_h; + lsm6dsv16x_timestamp0_t timestamp0; + lsm6dsv16x_timestamp1_t timestamp1; + lsm6dsv16x_timestamp2_t timestamp2; + lsm6dsv16x_timestamp3_t timestamp3; + lsm6dsv16x_ui_status_reg_ois_t ui_status_reg_ois; + lsm6dsv16x_wake_up_src_t wake_up_src; + lsm6dsv16x_tap_src_t tap_src; + lsm6dsv16x_d6d_src_t d6d_src; + lsm6dsv16x_status_master_mainpage_t status_master_mainpage; + lsm6dsv16x_emb_func_status_mainpage_t emb_func_status_mainpage; + lsm6dsv16x_fsm_status_mainpage_t fsm_status_mainpage; + lsm6dsv16x_mlc_status_mainpage_t mlc_status_mainpage; + lsm6dsv16x_internal_freq_t internal_freq; + lsm6dsv16x_functions_enable_t functions_enable; + lsm6dsv16x_den_t den; + lsm6dsv16x_inactivity_dur_t inactivity_dur; + lsm6dsv16x_inactivity_ths_t inactivity_ths; + lsm6dsv16x_tap_cfg0_t tap_cfg0; + lsm6dsv16x_tap_cfg1_t tap_cfg1; + lsm6dsv16x_tap_cfg2_t tap_cfg2; + lsm6dsv16x_tap_ths_6d_t tap_ths_6d; + lsm6dsv16x_tap_dur_t tap_dur; + lsm6dsv16x_wake_up_ths_t wake_up_ths; + lsm6dsv16x_wake_up_dur_t wake_up_dur; + lsm6dsv16x_free_fall_t free_fall; + lsm6dsv16x_md1_cfg_t md1_cfg; + lsm6dsv16x_md2_cfg_t md2_cfg; + lsm6dsv16x_emb_func_cfg_t emb_func_cfg; + lsm6dsv16x_ui_handshake_ctrl_t ui_handshake_ctrl; + lsm6dsv16x_ui_spi2_shared_0_t ui_spi2_shared_0; + lsm6dsv16x_ui_spi2_shared_1_t ui_spi2_shared_1; + lsm6dsv16x_ui_spi2_shared_2_t ui_spi2_shared_2; + lsm6dsv16x_ui_spi2_shared_3_t ui_spi2_shared_3; + lsm6dsv16x_ui_spi2_shared_4_t ui_spi2_shared_4; + lsm6dsv16x_ui_spi2_shared_5_t ui_spi2_shared_5; + lsm6dsv16x_ctrl_eis_t ctrl_eis; + lsm6dsv16x_ui_int_ois_t ui_int_ois; + lsm6dsv16x_ui_ctrl1_ois_t ui_ctrl1_ois; + lsm6dsv16x_ui_ctrl2_ois_t ui_ctrl2_ois; + lsm6dsv16x_ui_ctrl3_ois_t ui_ctrl3_ois; + lsm6dsv16x_x_ofs_usr_t x_ofs_usr; + lsm6dsv16x_y_ofs_usr_t y_ofs_usr; + lsm6dsv16x_z_ofs_usr_t z_ofs_usr; + lsm6dsv16x_fifo_data_out_tag_t fifo_data_out_tag; + lsm6dsv16x_fifo_data_out_x_l_t fifo_data_out_x_l; + lsm6dsv16x_fifo_data_out_x_h_t fifo_data_out_x_h; + lsm6dsv16x_fifo_data_out_y_l_t fifo_data_out_y_l; + lsm6dsv16x_fifo_data_out_y_h_t fifo_data_out_y_h; + lsm6dsv16x_fifo_data_out_z_l_t fifo_data_out_z_l; + lsm6dsv16x_fifo_data_out_z_h_t fifo_data_out_z_h; + lsm6dsv16x_spi2_who_am_i_t spi2_who_am_i; + lsm6dsv16x_spi2_status_reg_ois_t spi2_status_reg_ois; + lsm6dsv16x_spi2_out_temp_l_t spi2_out_temp_l; + lsm6dsv16x_spi2_out_temp_h_t spi2_out_temp_h; + lsm6dsv16x_spi2_outx_l_g_ois_t spi2_outx_l_g_ois; + lsm6dsv16x_spi2_outx_h_g_ois_t spi2_outx_h_g_ois; + lsm6dsv16x_spi2_outy_l_g_ois_t spi2_outy_l_g_ois; + lsm6dsv16x_spi2_outy_h_g_ois_t spi2_outy_h_g_ois; + lsm6dsv16x_spi2_outz_l_g_ois_t spi2_outz_l_g_ois; + lsm6dsv16x_spi2_outz_h_g_ois_t spi2_outz_h_g_ois; + lsm6dsv16x_spi2_outx_l_a_ois_t spi2_outx_l_a_ois; + lsm6dsv16x_spi2_outx_h_a_ois_t spi2_outx_h_a_ois; + lsm6dsv16x_spi2_outy_l_a_ois_t spi2_outy_l_a_ois; + lsm6dsv16x_spi2_outy_h_a_ois_t spi2_outy_h_a_ois; + lsm6dsv16x_spi2_outz_l_a_ois_t spi2_outz_l_a_ois; + lsm6dsv16x_spi2_outz_h_a_ois_t spi2_outz_h_a_ois; + lsm6dsv16x_spi2_handshake_ctrl_t spi2_handshake_ctrl; + lsm6dsv16x_spi2_int_ois_t spi2_int_ois; + lsm6dsv16x_spi2_ctrl1_ois_t spi2_ctrl1_ois; + lsm6dsv16x_spi2_ctrl2_ois_t spi2_ctrl2_ois; + lsm6dsv16x_spi2_ctrl3_ois_t spi2_ctrl3_ois; + lsm6dsv16x_page_sel_t page_sel; + lsm6dsv16x_emb_func_en_a_t emb_func_en_a; + lsm6dsv16x_emb_func_en_b_t emb_func_en_b; + lsm6dsv16x_emb_func_exec_status_t emb_func_exec_status; + lsm6dsv16x_page_address_t page_address; + lsm6dsv16x_page_value_t page_value; + lsm6dsv16x_emb_func_int1_t emb_func_int1; + lsm6dsv16x_fsm_int1_t fsm_int1; + lsm6dsv16x_mlc_int1_t mlc_int1; + lsm6dsv16x_emb_func_int2_t emb_func_int2; + lsm6dsv16x_fsm_int2_t fsm_int2; + lsm6dsv16x_mlc_int2_t mlc_int2; + lsm6dsv16x_emb_func_status_t emb_func_status; + lsm6dsv16x_fsm_status_t fsm_status; + lsm6dsv16x_mlc_status_t mlc_status; + lsm6dsv16x_page_rw_t page_rw; + lsm6dsv16x_emb_func_fifo_en_a_t emb_func_fifo_en_a; + lsm6dsv16x_emb_func_fifo_en_b_t emb_func_fifo_en_b; + lsm6dsv16x_fsm_enable_t fsm_enable; + lsm6dsv16x_fsm_long_counter_l_t fsm_long_counter_l; + lsm6dsv16x_fsm_long_counter_h_t fsm_long_counter_h; + lsm6dsv16x_int_ack_mask_t int_ack_mask; + lsm6dsv16x_fsm_outs1_t fsm_outs1; + lsm6dsv16x_fsm_outs2_t fsm_outs2; + lsm6dsv16x_fsm_outs3_t fsm_outs3; + lsm6dsv16x_fsm_outs4_t fsm_outs4; + lsm6dsv16x_fsm_outs5_t fsm_outs5; + lsm6dsv16x_fsm_outs6_t fsm_outs6; + lsm6dsv16x_fsm_outs7_t fsm_outs7; + lsm6dsv16x_fsm_outs8_t fsm_outs8; + lsm6dsv16x_fsm_odr_t fsm_odr; + lsm6dsv16x_mlc_odr_t mlc_odr; + lsm6dsv16x_step_counter_l_t step_counter_l; + lsm6dsv16x_step_counter_h_t step_counter_h; + lsm6dsv16x_emb_func_src_t emb_func_src; + lsm6dsv16x_emb_func_init_a_t emb_func_init_a; + lsm6dsv16x_emb_func_init_b_t emb_func_init_b; + lsm6dsv16x_mlc1_src_t mlc1_src; + lsm6dsv16x_mlc2_src_t mlc2_src; + lsm6dsv16x_mlc3_src_t mlc3_src; + lsm6dsv16x_mlc4_src_t mlc4_src; + lsm6dsv16x_fsm_ext_sensitivity_l_t fsm_ext_sensitivity_l; + lsm6dsv16x_fsm_ext_sensitivity_h_t fsm_ext_sensitivity_h; + lsm6dsv16x_fsm_ext_offx_l_t fsm_ext_offx_l; + lsm6dsv16x_fsm_ext_offx_h_t fsm_ext_offx_h; + lsm6dsv16x_fsm_ext_offy_l_t fsm_ext_offy_l; + lsm6dsv16x_fsm_ext_offy_h_t fsm_ext_offy_h; + lsm6dsv16x_fsm_ext_offz_l_t fsm_ext_offz_l; + lsm6dsv16x_fsm_ext_offz_h_t fsm_ext_offz_h; + lsm6dsv16x_fsm_ext_matrix_xx_l_t fsm_ext_matrix_xx_l; + lsm6dsv16x_fsm_ext_matrix_xx_h_t fsm_ext_matrix_xx_h; + lsm6dsv16x_fsm_ext_matrix_xy_l_t fsm_ext_matrix_xy_l; + lsm6dsv16x_fsm_ext_matrix_xy_h_t fsm_ext_matrix_xy_h; + lsm6dsv16x_fsm_ext_matrix_xz_l_t fsm_ext_matrix_xz_l; + lsm6dsv16x_fsm_ext_matrix_xz_h_t fsm_ext_matrix_xz_h; + lsm6dsv16x_fsm_ext_matrix_yy_l_t fsm_ext_matrix_yy_l; + lsm6dsv16x_fsm_ext_matrix_yy_h_t fsm_ext_matrix_yy_h; + lsm6dsv16x_fsm_ext_matrix_yz_l_t fsm_ext_matrix_yz_l; + lsm6dsv16x_fsm_ext_matrix_yz_h_t fsm_ext_matrix_yz_h; + lsm6dsv16x_fsm_ext_matrix_zz_l_t fsm_ext_matrix_zz_l; + lsm6dsv16x_fsm_ext_matrix_zz_h_t fsm_ext_matrix_zz_h; + lsm6dsv16x_ext_cfg_a_t ext_cfg_a; + lsm6dsv16x_ext_cfg_b_t ext_cfg_b; + lsm6dsv16x_fsm_lc_timeout_l_t fsm_lc_timeout_l; + lsm6dsv16x_fsm_lc_timeout_h_t fsm_lc_timeout_h; + lsm6dsv16x_fsm_programs_t fsm_programs; + lsm6dsv16x_fsm_start_add_l_t fsm_start_add_l; + lsm6dsv16x_fsm_start_add_h_t fsm_start_add_h; + lsm6dsv16x_pedo_cmd_reg_t pedo_cmd_reg; + lsm6dsv16x_pedo_deb_steps_conf_t pedo_deb_steps_conf; + lsm6dsv16x_pedo_sc_deltat_l_t pedo_sc_deltat_l; + lsm6dsv16x_pedo_sc_deltat_h_t pedo_sc_deltat_h; + lsm6dsv16x_mlc_ext_sensitivity_l_t mlc_ext_sensitivity_l; + lsm6dsv16x_mlc_ext_sensitivity_h_t mlc_ext_sensitivity_h; + lsm6dsv16x_sensor_hub_1_t sensor_hub_1; + lsm6dsv16x_sensor_hub_2_t sensor_hub_2; + lsm6dsv16x_sensor_hub_3_t sensor_hub_3; + lsm6dsv16x_sensor_hub_4_t sensor_hub_4; + lsm6dsv16x_sensor_hub_5_t sensor_hub_5; + lsm6dsv16x_sensor_hub_6_t sensor_hub_6; + lsm6dsv16x_sensor_hub_7_t sensor_hub_7; + lsm6dsv16x_sensor_hub_8_t sensor_hub_8; + lsm6dsv16x_sensor_hub_9_t sensor_hub_9; + lsm6dsv16x_sensor_hub_10_t sensor_hub_10; + lsm6dsv16x_sensor_hub_11_t sensor_hub_11; + lsm6dsv16x_sensor_hub_12_t sensor_hub_12; + lsm6dsv16x_sensor_hub_13_t sensor_hub_13; + lsm6dsv16x_sensor_hub_14_t sensor_hub_14; + lsm6dsv16x_sensor_hub_15_t sensor_hub_15; + lsm6dsv16x_sensor_hub_16_t sensor_hub_16; + lsm6dsv16x_sensor_hub_17_t sensor_hub_17; + lsm6dsv16x_sensor_hub_18_t sensor_hub_18; + lsm6dsv16x_master_config_t master_config; + lsm6dsv16x_slv0_add_t slv0_add; + lsm6dsv16x_slv0_subadd_t slv0_subadd; + lsm6dsv16x_slv0_config_t slv0_config; + lsm6dsv16x_slv1_add_t slv1_add; + lsm6dsv16x_slv1_subadd_t slv1_subadd; + lsm6dsv16x_slv1_config_t slv1_config; + lsm6dsv16x_slv2_add_t slv2_add; + lsm6dsv16x_slv2_subadd_t slv2_subadd; + lsm6dsv16x_slv2_config_t slv2_config; + lsm6dsv16x_slv3_add_t slv3_add; + lsm6dsv16x_slv3_subadd_t slv3_subadd; + lsm6dsv16x_slv3_config_t slv3_config; + lsm6dsv16x_datawrite_slv0_t datawrite_slv0; + lsm6dsv16x_status_master_t status_master; + bitwise_t bitwise; + uint8_t byte; +} lsm6dsv16x_reg_t; + +/** + * @} + * + */ + +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + +int32_t lsm6dsv16x_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); +int32_t lsm6dsv16x_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); + +float_t lsm6dsv16x_from_sflp_to_mg(int16_t lsb); +float_t lsm6dsv16x_from_fs2_to_mg(int16_t lsb); +float_t lsm6dsv16x_from_fs4_to_mg(int16_t lsb); +float_t lsm6dsv16x_from_fs8_to_mg(int16_t lsb); +float_t lsm6dsv16x_from_fs16_to_mg(int16_t lsb); + +float_t lsm6dsv16x_from_fs125_to_mdps(int16_t lsb); +float_t lsm6dsv16x_from_fs500_to_mdps(int16_t lsb); +float_t lsm6dsv16x_from_fs250_to_mdps(int16_t lsb); +float_t lsm6dsv16x_from_fs1000_to_mdps(int16_t lsb); +float_t lsm6dsv16x_from_fs2000_to_mdps(int16_t lsb); +float_t lsm6dsv16x_from_fs4000_to_mdps(int16_t lsb); + +float_t lsm6dsv16x_from_lsb_to_celsius(int16_t lsb); + +float_t lsm6dsv16x_from_lsb_to_nsec(uint32_t lsb); + +int32_t lsm6dsv16x_xl_offset_on_out_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_xl_offset_on_out_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + float_t z_mg; + float_t y_mg; + float_t x_mg; +} lsm6dsv16x_xl_offset_mg_t; +int32_t lsm6dsv16x_xl_offset_mg_set(stmdev_ctx_t *ctx, + lsm6dsv16x_xl_offset_mg_t val); +int32_t lsm6dsv16x_xl_offset_mg_get(stmdev_ctx_t *ctx, + lsm6dsv16x_xl_offset_mg_t *val); + +typedef enum +{ + LSM6DSV16X_READY = 0x0, + LSM6DSV16X_GLOBAL_RST = 0x1, + LSM6DSV16X_RESTORE_CAL_PARAM = 0x2, + LSM6DSV16X_RESTORE_CTRL_REGS = 0x4, +} lsm6dsv16x_reset_t; +int32_t lsm6dsv16x_reset_set(stmdev_ctx_t *ctx, lsm6dsv16x_reset_t val); +int32_t lsm6dsv16x_reset_get(stmdev_ctx_t *ctx, lsm6dsv16x_reset_t *val); + +typedef enum +{ + LSM6DSV16X_MAIN_MEM_BANK = 0x0, + LSM6DSV16X_EMBED_FUNC_MEM_BANK = 0x1, + LSM6DSV16X_SENSOR_HUB_MEM_BANK = 0x2, +} lsm6dsv16x_mem_bank_t; +int32_t lsm6dsv16x_mem_bank_set(stmdev_ctx_t *ctx, lsm6dsv16x_mem_bank_t val); +int32_t lsm6dsv16x_mem_bank_get(stmdev_ctx_t *ctx, lsm6dsv16x_mem_bank_t *val); + +int32_t lsm6dsv16x_device_id_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16X_ODR_OFF = 0x0, + LSM6DSV16X_ODR_AT_1Hz875 = 0x1, + LSM6DSV16X_ODR_AT_7Hz5 = 0x2, + LSM6DSV16X_ODR_AT_15Hz = 0x3, + LSM6DSV16X_ODR_AT_30Hz = 0x4, + LSM6DSV16X_ODR_AT_60Hz = 0x5, + LSM6DSV16X_ODR_AT_120Hz = 0x6, + LSM6DSV16X_ODR_AT_240Hz = 0x7, + LSM6DSV16X_ODR_AT_480Hz = 0x8, + LSM6DSV16X_ODR_AT_960Hz = 0x9, + LSM6DSV16X_ODR_AT_1920Hz = 0xA, + LSM6DSV16X_ODR_AT_3840Hz = 0xB, + LSM6DSV16X_ODR_AT_7680Hz = 0xC, + LSM6DSV16X_ODR_HA01_AT_15Hz625 = 0x13, + LSM6DSV16X_ODR_HA01_AT_31Hz25 = 0x14, + LSM6DSV16X_ODR_HA01_AT_62Hz5 = 0x15, + LSM6DSV16X_ODR_HA01_AT_125Hz = 0x16, + LSM6DSV16X_ODR_HA01_AT_250Hz = 0x17, + LSM6DSV16X_ODR_HA01_AT_500Hz = 0x18, + LSM6DSV16X_ODR_HA01_AT_1000Hz = 0x19, + LSM6DSV16X_ODR_HA01_AT_2000Hz = 0x1A, + LSM6DSV16X_ODR_HA01_AT_4000Hz = 0x1B, + LSM6DSV16X_ODR_HA01_AT_8000Hz = 0x1C, + LSM6DSV16X_ODR_HA02_AT_12Hz5 = 0x23, + LSM6DSV16X_ODR_HA02_AT_25Hz = 0x24, + LSM6DSV16X_ODR_HA02_AT_50Hz = 0x25, + LSM6DSV16X_ODR_HA02_AT_100Hz = 0x26, + LSM6DSV16X_ODR_HA02_AT_200Hz = 0x27, + LSM6DSV16X_ODR_HA02_AT_400Hz = 0x28, + LSM6DSV16X_ODR_HA02_AT_800Hz = 0x29, + LSM6DSV16X_ODR_HA02_AT_1600Hz = 0x2A, + LSM6DSV16X_ODR_HA02_AT_3200Hz = 0x2B, + LSM6DSV16X_ODR_HA02_AT_6400Hz = 0x2C, +} lsm6dsv16x_data_rate_t; +int32_t lsm6dsv16x_xl_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv16x_data_rate_t val); +int32_t lsm6dsv16x_xl_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv16x_data_rate_t *val); +int32_t lsm6dsv16x_gy_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv16x_data_rate_t val); +int32_t lsm6dsv16x_gy_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv16x_data_rate_t *val); + + +typedef enum +{ + LSM6DSV16X_XL_HIGH_PERFORMANCE_MD = 0x0, + LSM6DSV16X_XL_HIGH_ACCURACY_ODR_MD = 0x1, + LSM6DSV16X_XL_ODR_TRIGGERED_MD = 0x3, + LSM6DSV16X_XL_LOW_POWER_2_AVG_MD = 0x4, + LSM6DSV16X_XL_LOW_POWER_4_AVG_MD = 0x5, + LSM6DSV16X_XL_LOW_POWER_8_AVG_MD = 0x6, + LSM6DSV16X_XL_NORMAL_MD = 0x7, +} lsm6dsv16x_xl_mode_t; +int32_t lsm6dsv16x_xl_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_xl_mode_t val); +int32_t lsm6dsv16x_xl_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_xl_mode_t *val); + +typedef enum +{ + LSM6DSV16X_GY_HIGH_PERFORMANCE_MD = 0x0, + LSM6DSV16X_GY_HIGH_ACCURACY_ODR_MD = 0x1, + LSM6DSV16X_GY_SLEEP_MD = 0x4, + LSM6DSV16X_GY_LOW_POWER_MD = 0x5, +} lsm6dsv16x_gy_mode_t; +int32_t lsm6dsv16x_gy_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_gy_mode_t val); +int32_t lsm6dsv16x_gy_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_gy_mode_t *val); + +int32_t lsm6dsv16x_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16x_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16x_odr_trig_cfg_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_odr_trig_cfg_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16X_DRDY_LATCHED = 0x0, + LSM6DSV16X_DRDY_PULSED = 0x1, +} lsm6dsv16x_data_ready_mode_t; +int32_t lsm6dsv16x_data_ready_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16x_data_ready_mode_t val); +int32_t lsm6dsv16x_data_ready_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16x_data_ready_mode_t *val); + +typedef struct +{ + uint8_t enable : 1; /* interrupt enable */ + uint8_t lir : 1; /* interrupt pulsed or latched */ +} lsm6dsv16x_interrupt_mode_t; +int32_t lsm6dsv16x_interrupt_enable_set(stmdev_ctx_t *ctx, + lsm6dsv16x_interrupt_mode_t val); +int32_t lsm6dsv16x_interrupt_enable_get(stmdev_ctx_t *ctx, + lsm6dsv16x_interrupt_mode_t *val); + +typedef enum +{ + LSM6DSV16X_125dps = 0x0, + LSM6DSV16X_250dps = 0x1, + LSM6DSV16X_500dps = 0x2, + LSM6DSV16X_1000dps = 0x3, + LSM6DSV16X_2000dps = 0x4, + LSM6DSV16X_4000dps = 0x5, +} lsm6dsv16x_gy_full_scale_t; +int32_t lsm6dsv16x_gy_full_scale_set(stmdev_ctx_t *ctx, + lsm6dsv16x_gy_full_scale_t val); +int32_t lsm6dsv16x_gy_full_scale_get(stmdev_ctx_t *ctx, + lsm6dsv16x_gy_full_scale_t *val); + +typedef enum +{ + LSM6DSV16X_2g = 0x0, + LSM6DSV16X_4g = 0x1, + LSM6DSV16X_8g = 0x2, + LSM6DSV16X_16g = 0x3, +} lsm6dsv16x_xl_full_scale_t; +int32_t lsm6dsv16x_xl_full_scale_set(stmdev_ctx_t *ctx, + lsm6dsv16x_xl_full_scale_t val); +int32_t lsm6dsv16x_xl_full_scale_get(stmdev_ctx_t *ctx, + lsm6dsv16x_xl_full_scale_t *val); + +int32_t lsm6dsv16x_xl_dual_channel_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_xl_dual_channel_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16X_XL_ST_DISABLE = 0x0, + LSM6DSV16X_XL_ST_POSITIVE = 0x1, + LSM6DSV16X_XL_ST_NEGATIVE = 0x2, +} lsm6dsv16x_xl_self_test_t; +int32_t lsm6dsv16x_xl_self_test_set(stmdev_ctx_t *ctx, + lsm6dsv16x_xl_self_test_t val); +int32_t lsm6dsv16x_xl_self_test_get(stmdev_ctx_t *ctx, + lsm6dsv16x_xl_self_test_t *val); + +typedef enum +{ + LSM6DSV16X_OIS_XL_ST_DISABLE = 0x0, + LSM6DSV16X_OIS_XL_ST_POSITIVE = 0x1, + LSM6DSV16X_OIS_XL_ST_NEGATIVE = 0x2, +} lsm6dsv16x_ois_xl_self_test_t; +int32_t lsm6dsv16x_ois_xl_self_test_set(stmdev_ctx_t *ctx, + lsm6dsv16x_ois_xl_self_test_t val); +int32_t lsm6dsv16x_ois_xl_self_test_get(stmdev_ctx_t *ctx, + lsm6dsv16x_ois_xl_self_test_t *val); + +typedef enum +{ + LSM6DSV16X_GY_ST_DISABLE = 0x0, + LSM6DSV16X_GY_ST_POSITIVE = 0x1, + LSM6DSV16X_GY_ST_NEGATIVE = 0x2, + +} lsm6dsv16x_gy_self_test_t; +int32_t lsm6dsv16x_gy_self_test_set(stmdev_ctx_t *ctx, + lsm6dsv16x_gy_self_test_t val); +int32_t lsm6dsv16x_gy_self_test_get(stmdev_ctx_t *ctx, + lsm6dsv16x_gy_self_test_t *val); + +typedef enum +{ + LSM6DSV16X_OIS_GY_ST_DISABLE = 0x0, + LSM6DSV16X_OIS_GY_ST_POSITIVE = 0x1, + LSM6DSV16X_OIS_GY_ST_NEGATIVE = 0x2, + LSM6DSV16X_OIS_GY_ST_CLAMP_POS = 0x5, + LSM6DSV16X_OIS_GY_ST_CLAMP_NEG = 0x6, + +} lsm6dsv16x_ois_gy_self_test_t; +int32_t lsm6dsv16x_ois_gy_self_test_set(stmdev_ctx_t *ctx, + lsm6dsv16x_ois_gy_self_test_t val); +int32_t lsm6dsv16x_ois_gy_self_test_get(stmdev_ctx_t *ctx, + lsm6dsv16x_ois_gy_self_test_t *val); + +typedef struct +{ + uint8_t drdy_xl : 1; + uint8_t drdy_gy : 1; + uint8_t drdy_temp : 1; + uint8_t drdy_ah_qvar : 1; + uint8_t drdy_eis : 1; + uint8_t drdy_ois : 1; + uint8_t gy_settling : 1; + uint8_t timestamp : 1; + uint8_t free_fall : 1; + uint8_t wake_up : 1; + uint8_t wake_up_z : 1; + uint8_t wake_up_y : 1; + uint8_t wake_up_x : 1; + uint8_t single_tap : 1; + uint8_t double_tap : 1; + uint8_t tap_z : 1; + uint8_t tap_y : 1; + uint8_t tap_x : 1; + uint8_t tap_sign : 1; + uint8_t six_d : 1; + uint8_t six_d_xl : 1; + uint8_t six_d_xh : 1; + uint8_t six_d_yl : 1; + uint8_t six_d_yh : 1; + uint8_t six_d_zl : 1; + uint8_t six_d_zh : 1; + uint8_t sleep_change : 1; + uint8_t sleep_state : 1; + uint8_t step_detector : 1; + uint8_t step_count_inc : 1; + uint8_t step_count_overflow : 1; + uint8_t step_on_delta_time : 1; + uint8_t emb_func_stand_by : 1; + uint8_t emb_func_time_exceed : 1; + uint8_t tilt : 1; + uint8_t sig_mot : 1; + uint8_t fsm_lc : 1; + uint8_t fsm1 : 1; + uint8_t fsm2 : 1; + uint8_t fsm3 : 1; + uint8_t fsm4 : 1; + uint8_t fsm5 : 1; + uint8_t fsm6 : 1; + uint8_t fsm7 : 1; + uint8_t fsm8 : 1; + uint8_t mlc1 : 1; + uint8_t mlc2 : 1; + uint8_t mlc3 : 1; + uint8_t mlc4 : 1; + uint8_t sh_endop : 1; + uint8_t sh_slave0_nack : 1; + uint8_t sh_slave1_nack : 1; + uint8_t sh_slave2_nack : 1; + uint8_t sh_slave3_nack : 1; + uint8_t sh_wr_once : 1; + uint8_t fifo_bdr : 1; + uint8_t fifo_full : 1; + uint8_t fifo_ovr : 1; + uint8_t fifo_th : 1; +} lsm6dsv16x_all_sources_t; +int32_t lsm6dsv16x_all_sources_get(stmdev_ctx_t *ctx, + lsm6dsv16x_all_sources_t *val); + +typedef struct +{ + uint8_t drdy_xl : 1; + uint8_t drdy_g : 1; + uint8_t drdy_g_eis : 1; + uint8_t fifo_th : 1; + uint8_t fifo_ovr : 1; + uint8_t fifo_full : 1; + uint8_t cnt_bdr : 1; + uint8_t emb_func_endop : 1; + uint8_t timestamp : 1; + uint8_t shub : 1; + uint8_t emb_func : 1; + uint8_t sixd : 1; + uint8_t single_tap : 1; + uint8_t double_tap : 1; + uint8_t wakeup : 1; + uint8_t freefall : 1; + uint8_t sleep_change : 1; +} lsm6dsv16x_pin_int_route_t; +int32_t lsm6dsv16x_pin_int1_route_set(stmdev_ctx_t *ctx, + lsm6dsv16x_pin_int_route_t *val); +int32_t lsm6dsv16x_pin_int1_route_get(stmdev_ctx_t *ctx, + lsm6dsv16x_pin_int_route_t *val); +int32_t lsm6dsv16x_pin_int2_route_set(stmdev_ctx_t *ctx, + lsm6dsv16x_pin_int_route_t *val); +int32_t lsm6dsv16x_pin_int2_route_get(stmdev_ctx_t *ctx, + lsm6dsv16x_pin_int_route_t *val); + +typedef struct +{ + uint8_t drdy_xl : 1; + uint8_t drdy_gy : 1; + uint8_t drdy_temp : 1; +} lsm6dsv16x_data_ready_t; +int32_t lsm6dsv16x_flag_data_ready_get(stmdev_ctx_t *ctx, + lsm6dsv16x_data_ready_t *val); + +int32_t lsm6dsv16x_int_ack_mask_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_int_ack_mask_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16x_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); + +int32_t lsm6dsv16x_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val); + +int32_t lsm6dsv16x_ois_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val); + +int32_t lsm6dsv16x_ois_eis_angular_rate_raw_get(stmdev_ctx_t *ctx, + int16_t *val); + +int32_t lsm6dsv16x_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); + +int32_t lsm6dsv16x_dual_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); + +int32_t lsm6dsv16x_ois_dual_acceleration_raw_get(stmdev_ctx_t *ctx, + int16_t *val); + +int32_t lsm6dsv16x_ah_qvar_raw_get(stmdev_ctx_t *ctx, int16_t *val); + +int32_t lsm6dsv16x_odr_cal_reg_get(stmdev_ctx_t *ctx, int8_t *val); + +int32_t lsm6dsv16x_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, + uint8_t *buf, uint8_t len); +int32_t lsm6dsv16x_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, + uint8_t len); + +int32_t lsm6dsv16x_emb_function_dbg_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_emb_function_dbg_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16X_DEN_ACT_LOW = 0x0, + LSM6DSV16X_DEN_ACT_HIGH = 0x1, +} lsm6dsv16x_den_polarity_t; +int32_t lsm6dsv16x_den_polarity_set(stmdev_ctx_t *ctx, + lsm6dsv16x_den_polarity_t val); +int32_t lsm6dsv16x_den_polarity_get(stmdev_ctx_t *ctx, + lsm6dsv16x_den_polarity_t *val); + +typedef struct +{ + uint8_t stamp_in_gy_data : 1; + uint8_t stamp_in_xl_data : 1; + uint8_t den_x : 1; + uint8_t den_y : 1; + uint8_t den_z : 1; + enum + { + DEN_NOT_DEFINED = 0x00, + LEVEL_TRIGGER = 0x02, + LEVEL_LATCHED = 0x03, + } mode; +} lsm6dsv16x_den_conf_t; +int32_t lsm6dsv16x_den_conf_set(stmdev_ctx_t *ctx, lsm6dsv16x_den_conf_t val); +int32_t lsm6dsv16x_den_conf_get(stmdev_ctx_t *ctx, lsm6dsv16x_den_conf_t *val); + +typedef enum +{ + LSM6DSV16X_EIS_125dps = 0x0, + LSM6DSV16X_EIS_250dps = 0x1, + LSM6DSV16X_EIS_500dps = 0x2, + LSM6DSV16X_EIS_1000dps = 0x3, + LSM6DSV16X_EIS_2000dps = 0x4, +} lsm6dsv16x_eis_gy_full_scale_t; +int32_t lsm6dsv16x_eis_gy_full_scale_set(stmdev_ctx_t *ctx, + lsm6dsv16x_eis_gy_full_scale_t val); +int32_t lsm6dsv16x_eis_gy_full_scale_get(stmdev_ctx_t *ctx, + lsm6dsv16x_eis_gy_full_scale_t *val); + +int32_t lsm6dsv16x_eis_gy_on_spi2_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_eis_gy_on_spi2_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16X_EIS_ODR_OFF = 0x0, + LSM6DSV16X_EIS_1920Hz = 0x1, + LSM6DSV16X_EIS_960Hz = 0x2, +} lsm6dsv16x_gy_eis_data_rate_t; +int32_t lsm6dsv16x_gy_eis_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv16x_gy_eis_data_rate_t val); +int32_t lsm6dsv16x_gy_eis_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv16x_gy_eis_data_rate_t *val); + +int32_t lsm6dsv16x_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16x_fifo_xl_dual_fsm_batch_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_fifo_xl_dual_fsm_batch_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16X_CMP_DISABLE = 0x0, + LSM6DSV16X_CMP_8_TO_1 = 0x1, + LSM6DSV16X_CMP_16_TO_1 = 0x2, + LSM6DSV16X_CMP_32_TO_1 = 0x3, +} lsm6dsv16x_fifo_compress_algo_t; +int32_t lsm6dsv16x_fifo_compress_algo_set(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_compress_algo_t val); +int32_t lsm6dsv16x_fifo_compress_algo_get(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_compress_algo_t *val); + +int32_t lsm6dsv16x_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, + uint8_t val); +int32_t lsm6dsv16x_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t lsm6dsv16x_fifo_compress_algo_real_time_set(stmdev_ctx_t *ctx, + uint8_t val); +int32_t lsm6dsv16x_fifo_compress_algo_real_time_get(stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t lsm6dsv16x_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16X_XL_NOT_BATCHED = 0x0, + LSM6DSV16X_XL_BATCHED_AT_1Hz875 = 0x1, + LSM6DSV16X_XL_BATCHED_AT_7Hz5 = 0x2, + LSM6DSV16X_XL_BATCHED_AT_15Hz = 0x3, + LSM6DSV16X_XL_BATCHED_AT_30Hz = 0x4, + LSM6DSV16X_XL_BATCHED_AT_60Hz = 0x5, + LSM6DSV16X_XL_BATCHED_AT_120Hz = 0x6, + LSM6DSV16X_XL_BATCHED_AT_240Hz = 0x7, + LSM6DSV16X_XL_BATCHED_AT_480Hz = 0x8, + LSM6DSV16X_XL_BATCHED_AT_960Hz = 0x9, + LSM6DSV16X_XL_BATCHED_AT_1920Hz = 0xa, + LSM6DSV16X_XL_BATCHED_AT_3840Hz = 0xb, + LSM6DSV16X_XL_BATCHED_AT_7680Hz = 0xc, +} lsm6dsv16x_fifo_xl_batch_t; +int32_t lsm6dsv16x_fifo_xl_batch_set(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_xl_batch_t val); +int32_t lsm6dsv16x_fifo_xl_batch_get(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_xl_batch_t *val); + +typedef enum +{ + LSM6DSV16X_GY_NOT_BATCHED = 0x0, + LSM6DSV16X_GY_BATCHED_AT_1Hz875 = 0x1, + LSM6DSV16X_GY_BATCHED_AT_7Hz5 = 0x2, + LSM6DSV16X_GY_BATCHED_AT_15Hz = 0x3, + LSM6DSV16X_GY_BATCHED_AT_30Hz = 0x4, + LSM6DSV16X_GY_BATCHED_AT_60Hz = 0x5, + LSM6DSV16X_GY_BATCHED_AT_120Hz = 0x6, + LSM6DSV16X_GY_BATCHED_AT_240Hz = 0x7, + LSM6DSV16X_GY_BATCHED_AT_480Hz = 0x8, + LSM6DSV16X_GY_BATCHED_AT_960Hz = 0x9, + LSM6DSV16X_GY_BATCHED_AT_1920Hz = 0xa, + LSM6DSV16X_GY_BATCHED_AT_3840Hz = 0xb, + LSM6DSV16X_GY_BATCHED_AT_7680Hz = 0xc, +} lsm6dsv16x_fifo_gy_batch_t; +int32_t lsm6dsv16x_fifo_gy_batch_set(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_gy_batch_t val); +int32_t lsm6dsv16x_fifo_gy_batch_get(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_gy_batch_t *val); + +typedef enum +{ + LSM6DSV16X_BYPASS_MODE = 0x0, + LSM6DSV16X_FIFO_MODE = 0x1, + LSM6DSV16X_STREAM_WTM_TO_FULL_MODE = 0x2, + LSM6DSV16X_STREAM_TO_FIFO_MODE = 0x3, + LSM6DSV16X_BYPASS_TO_STREAM_MODE = 0x4, + LSM6DSV16X_STREAM_MODE = 0x6, + LSM6DSV16X_BYPASS_TO_FIFO_MODE = 0x7, +} lsm6dsv16x_fifo_mode_t; +int32_t lsm6dsv16x_fifo_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_fifo_mode_t val); +int32_t lsm6dsv16x_fifo_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_mode_t *val); + +int32_t lsm6dsv16x_fifo_gy_eis_batch_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_fifo_gy_eis_batch_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16X_TEMP_NOT_BATCHED = 0x0, + LSM6DSV16X_TEMP_BATCHED_AT_1Hz875 = 0x1, + LSM6DSV16X_TEMP_BATCHED_AT_15Hz = 0x2, + LSM6DSV16X_TEMP_BATCHED_AT_60Hz = 0x3, +} lsm6dsv16x_fifo_temp_batch_t; +int32_t lsm6dsv16x_fifo_temp_batch_set(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_temp_batch_t val); +int32_t lsm6dsv16x_fifo_temp_batch_get(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_temp_batch_t *val); + +typedef enum +{ + LSM6DSV16X_TMSTMP_NOT_BATCHED = 0x0, + LSM6DSV16X_TMSTMP_DEC_1 = 0x1, + LSM6DSV16X_TMSTMP_DEC_8 = 0x2, + LSM6DSV16X_TMSTMP_DEC_32 = 0x3, +} lsm6dsv16x_fifo_timestamp_batch_t; +int32_t lsm6dsv16x_fifo_timestamp_batch_set(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_timestamp_batch_t val); +int32_t lsm6dsv16x_fifo_timestamp_batch_get(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_timestamp_batch_t *val); + +int32_t lsm6dsv16x_fifo_batch_counter_threshold_set(stmdev_ctx_t *ctx, + uint16_t val); +int32_t lsm6dsv16x_fifo_batch_counter_threshold_get(stmdev_ctx_t *ctx, + uint16_t *val); + +typedef enum +{ + LSM6DSV16X_XL_BATCH_EVENT = 0x0, + LSM6DSV16X_GY_BATCH_EVENT = 0x1, + LSM6DSV16X_GY_EIS_BATCH_EVENT = 0x2, +} lsm6dsv16x_fifo_batch_cnt_event_t; +int32_t lsm6dsv16x_fifo_batch_cnt_event_set(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_batch_cnt_event_t val); +int32_t lsm6dsv16x_fifo_batch_cnt_event_get(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_batch_cnt_event_t *val); + +typedef struct +{ + uint16_t fifo_level : 9; + uint8_t fifo_bdr : 1; + uint8_t fifo_full : 1; + uint8_t fifo_ovr : 1; + uint8_t fifo_th : 1; +} lsm6dsv16x_fifo_status_t; + +int32_t lsm6dsv16x_fifo_status_get(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_status_t *val); + +typedef struct +{ + enum + { + LSM6DSV16X_FIFO_EMPTY = 0x0, + LSM6DSV16X_GY_NC_TAG = 0x1, + LSM6DSV16X_XL_NC_TAG = 0x2, + LSM6DSV16X_TEMPERATURE_TAG = 0x3, + LSM6DSV16X_TIMESTAMP_TAG = 0x4, + LSM6DSV16X_CFG_CHANGE_TAG = 0x5, + LSM6DSV16X_XL_NC_T_2_TAG = 0x6, + LSM6DSV16X_XL_NC_T_1_TAG = 0x7, + LSM6DSV16X_XL_2XC_TAG = 0x8, + LSM6DSV16X_XL_3XC_TAG = 0x9, + LSM6DSV16X_GY_NC_T_2_TAG = 0xA, + LSM6DSV16X_GY_NC_T_1_TAG = 0xB, + LSM6DSV16X_GY_2XC_TAG = 0xC, + LSM6DSV16X_GY_3XC_TAG = 0xD, + LSM6DSV16X_SENSORHUB_SLAVE0_TAG = 0xE, + LSM6DSV16X_SENSORHUB_SLAVE1_TAG = 0xF, + LSM6DSV16X_SENSORHUB_SLAVE2_TAG = 0x10, + LSM6DSV16X_SENSORHUB_SLAVE3_TAG = 0x11, + LSM6DSV16X_STEP_COUNTER_TAG = 0x12, + LSM6DSV16X_SFLP_GAME_ROTATION_VECTOR_TAG = 0x13, + LSM6DSV16X_SFLP_GYROSCOPE_BIAS_TAG = 0x16, + LSM6DSV16X_SFLP_GRAVITY_VECTOR_TAG = 0x17, + LSM6DSV16X_SENSORHUB_NACK_TAG = 0x19, + LSM6DSV16X_MLC_RESULT_TAG = 0x1A, + LSM6DSV16X_MLC_FILTER = 0x1B, + LSM6DSV16X_MLC_FEATURE = 0x1C, + LSM6DSV16X_XL_DUAL_CORE = 0x1D, + LSM6DSV16X_GY_ENHANCED_EIS = 0x1E, + } tag; + uint8_t cnt; + uint8_t data[6]; +} lsm6dsv16x_fifo_out_raw_t; +int32_t lsm6dsv16x_fifo_out_raw_get(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_out_raw_t *val); + +int32_t lsm6dsv16x_fifo_stpcnt_batch_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_fifo_stpcnt_batch_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16x_fifo_mlc_batch_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_fifo_mlc_batch_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16x_fifo_mlc_filt_batch_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_fifo_mlc_filt_batch_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16x_fifo_batch_sh_slave_0_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_fifo_batch_sh_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16x_fifo_batch_sh_slave_1_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_fifo_batch_sh_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16x_fifo_batch_sh_slave_2_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_fifo_batch_sh_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16x_fifo_batch_sh_slave_3_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_fifo_batch_sh_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t game_rotation : 1; + uint8_t gravity : 1; + uint8_t gbias : 1; +} lsm6dsv16x_fifo_sflp_raw_t; +int32_t lsm6dsv16x_fifo_sflp_batch_set(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_sflp_raw_t val); +int32_t lsm6dsv16x_fifo_sflp_batch_get(stmdev_ctx_t *ctx, + lsm6dsv16x_fifo_sflp_raw_t *val); + +typedef enum +{ + LSM6DSV16X_AUTO = 0x0, + LSM6DSV16X_ALWAYS_ACTIVE = 0x1, +} lsm6dsv16x_filt_anti_spike_t; +int32_t lsm6dsv16x_filt_anti_spike_set(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_anti_spike_t val); +int32_t lsm6dsv16x_filt_anti_spike_get(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_anti_spike_t *val); + +typedef struct +{ + uint8_t drdy : 1; + uint8_t ois_drdy : 1; + uint8_t irq_xl : 1; + uint8_t irq_g : 1; +} lsm6dsv16x_filt_settling_mask_t; +int32_t lsm6dsv16x_filt_settling_mask_set(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_settling_mask_t val); +int32_t lsm6dsv16x_filt_settling_mask_get(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_settling_mask_t *val); + +typedef struct +{ + uint8_t ois_drdy : 1; +} lsm6dsv16x_filt_ois_settling_mask_t; +int32_t lsm6dsv16x_filt_ois_settling_mask_set(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_ois_settling_mask_t val); +int32_t lsm6dsv16x_filt_ois_settling_mask_get(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_ois_settling_mask_t *val); + +typedef enum +{ + LSM6DSV16X_GY_ULTRA_LIGHT = 0x0, + LSM6DSV16X_GY_VERY_LIGHT = 0x1, + LSM6DSV16X_GY_LIGHT = 0x2, + LSM6DSV16X_GY_MEDIUM = 0x3, + LSM6DSV16X_GY_STRONG = 0x4, + LSM6DSV16X_GY_VERY_STRONG = 0x5, + LSM6DSV16X_GY_AGGRESSIVE = 0x6, + LSM6DSV16X_GY_XTREME = 0x7, +} lsm6dsv16x_filt_gy_lp1_bandwidth_t; +int32_t lsm6dsv16x_filt_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_gy_lp1_bandwidth_t val); +int32_t lsm6dsv16x_filt_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_gy_lp1_bandwidth_t *val); + +int32_t lsm6dsv16x_filt_gy_lp1_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_filt_gy_lp1_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16X_XL_ULTRA_LIGHT = 0x0, + LSM6DSV16X_XL_VERY_LIGHT = 0x1, + LSM6DSV16X_XL_LIGHT = 0x2, + LSM6DSV16X_XL_MEDIUM = 0x3, + LSM6DSV16X_XL_STRONG = 0x4, + LSM6DSV16X_XL_VERY_STRONG = 0x5, + LSM6DSV16X_XL_AGGRESSIVE = 0x6, + LSM6DSV16X_XL_XTREME = 0x7, +} lsm6dsv16x_filt_xl_lp2_bandwidth_t; +int32_t lsm6dsv16x_filt_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_xl_lp2_bandwidth_t val); +int32_t lsm6dsv16x_filt_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_xl_lp2_bandwidth_t *val); + +int32_t lsm6dsv16x_filt_xl_lp2_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_filt_xl_lp2_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16x_filt_xl_hp_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_filt_xl_hp_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16x_filt_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_filt_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16X_HP_MD_NORMAL = 0x0, + LSM6DSV16X_HP_MD_REFERENCE = 0x1, +} lsm6dsv16x_filt_xl_hp_mode_t; +int32_t lsm6dsv16x_filt_xl_hp_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_xl_hp_mode_t val); +int32_t lsm6dsv16x_filt_xl_hp_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_xl_hp_mode_t *val); + +typedef enum +{ + LSM6DSV16X_WK_FEED_SLOPE = 0x0, + LSM6DSV16X_WK_FEED_HIGH_PASS = 0x1, + LSM6DSV16X_WK_FEED_LP_WITH_OFFSET = 0x2, +} lsm6dsv16x_filt_wkup_act_feed_t; +int32_t lsm6dsv16x_filt_wkup_act_feed_set(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_wkup_act_feed_t val); +int32_t lsm6dsv16x_filt_wkup_act_feed_get(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_wkup_act_feed_t *val); + +int32_t lsm6dsv16x_mask_trigger_xl_settl_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_mask_trigger_xl_settl_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16X_SIXD_FEED_ODR_DIV_2 = 0x0, + LSM6DSV16X_SIXD_FEED_LOW_PASS = 0x1, +} lsm6dsv16x_filt_sixd_feed_t; +int32_t lsm6dsv16x_filt_sixd_feed_set(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_sixd_feed_t val); +int32_t lsm6dsv16x_filt_sixd_feed_get(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_sixd_feed_t *val); + +typedef enum +{ + LSM6DSV16X_EIS_LP_NORMAL = 0x0, + LSM6DSV16X_EIS_LP_LIGHT = 0x1, +} lsm6dsv16x_filt_gy_eis_lp_bandwidth_t; +int32_t lsm6dsv16x_filt_gy_eis_lp_bandwidth_set(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_gy_eis_lp_bandwidth_t val); +int32_t lsm6dsv16x_filt_gy_eis_lp_bandwidth_get(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_gy_eis_lp_bandwidth_t *val); + +typedef enum +{ + LSM6DSV16X_OIS_GY_LP_NORMAL = 0x0, + LSM6DSV16X_OIS_GY_LP_STRONG = 0x1, + LSM6DSV16X_OIS_GY_LP_AGGRESSIVE = 0x2, + LSM6DSV16X_OIS_GY_LP_LIGHT = 0x3, +} lsm6dsv16x_filt_gy_ois_lp_bandwidth_t; +int32_t lsm6dsv16x_filt_gy_ois_lp_bandwidth_set(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_gy_ois_lp_bandwidth_t val); +int32_t lsm6dsv16x_filt_gy_ois_lp_bandwidth_get(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_gy_ois_lp_bandwidth_t *val); + +typedef enum +{ + LSM6DSV16X_OIS_XL_LP_ULTRA_LIGHT = 0x0, + LSM6DSV16X_OIS_XL_LP_VERY_LIGHT = 0x1, + LSM6DSV16X_OIS_XL_LP_LIGHT = 0x2, + LSM6DSV16X_OIS_XL_LP_NORMAL = 0x3, + LSM6DSV16X_OIS_XL_LP_STRONG = 0x4, + LSM6DSV16X_OIS_XL_LP_VERY_STRONG = 0x5, + LSM6DSV16X_OIS_XL_LP_AGGRESSIVE = 0x6, + LSM6DSV16X_OIS_XL_LP_XTREME = 0x7, +} lsm6dsv16x_filt_xl_ois_lp_bandwidth_t; +int32_t lsm6dsv16x_filt_xl_ois_lp_bandwidth_set(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_xl_ois_lp_bandwidth_t val); +int32_t lsm6dsv16x_filt_xl_ois_lp_bandwidth_get(stmdev_ctx_t *ctx, + lsm6dsv16x_filt_xl_ois_lp_bandwidth_t *val); + +typedef enum +{ + LSM6DSV16X_PROTECT_CTRL_REGS = 0x0, + LSM6DSV16X_WRITE_CTRL_REG = 0x1, +} lsm6dsv16x_fsm_permission_t; +int32_t lsm6dsv16x_fsm_permission_set(stmdev_ctx_t *ctx, + lsm6dsv16x_fsm_permission_t val); +int32_t lsm6dsv16x_fsm_permission_get(stmdev_ctx_t *ctx, + lsm6dsv16x_fsm_permission_t *val); +int32_t lsm6dsv16x_fsm_permission_status(stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t fsm1_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm8_en : 1; +} lsm6dsv16x_fsm_mode_t; +int32_t lsm6dsv16x_fsm_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_fsm_mode_t val); +int32_t lsm6dsv16x_fsm_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_fsm_mode_t *val); + +int32_t lsm6dsv16x_fsm_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv16x_fsm_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val); + + +typedef struct +{ + uint8_t fsm_outs1; + uint8_t fsm_outs2; + uint8_t fsm_outs3; + uint8_t fsm_outs4; + uint8_t fsm_outs5; + uint8_t fsm_outs6; + uint8_t fsm_outs7; + uint8_t fsm_outs8; +} lsm6dsv16x_fsm_out_t; +int32_t lsm6dsv16x_fsm_out_get(stmdev_ctx_t *ctx, lsm6dsv16x_fsm_out_t *val); + +typedef enum +{ + LSM6DSV16X_FSM_15Hz = 0x0, + LSM6DSV16X_FSM_30Hz = 0x1, + LSM6DSV16X_FSM_60Hz = 0x2, + LSM6DSV16X_FSM_120Hz = 0x3, + LSM6DSV16X_FSM_240Hz = 0x4, + LSM6DSV16X_FSM_480Hz = 0x5, + LSM6DSV16X_FSM_960Hz = 0x6, +} lsm6dsv16x_fsm_data_rate_t; +int32_t lsm6dsv16x_fsm_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv16x_fsm_data_rate_t val); +int32_t lsm6dsv16x_fsm_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv16x_fsm_data_rate_t *val); + +int32_t lsm6dsv16x_fsm_ext_sens_sensitivity_set(stmdev_ctx_t *ctx, + uint16_t val); +int32_t lsm6dsv16x_fsm_ext_sens_sensitivity_get(stmdev_ctx_t *ctx, + uint16_t *val); + +typedef struct +{ + uint16_t z; + uint16_t y; + uint16_t x; +} lsm6dsv16x_xl_fsm_ext_sens_offset_t; +int32_t lsm6dsv16x_fsm_ext_sens_offset_set(stmdev_ctx_t *ctx, + lsm6dsv16x_xl_fsm_ext_sens_offset_t val); +int32_t lsm6dsv16x_fsm_ext_sens_offset_get(stmdev_ctx_t *ctx, + lsm6dsv16x_xl_fsm_ext_sens_offset_t *val); + +typedef struct +{ + uint16_t xx; + uint16_t xy; + uint16_t xz; + uint16_t yy; + uint16_t yz; + uint16_t zz; +} lsm6dsv16x_xl_fsm_ext_sens_matrix_t; +int32_t lsm6dsv16x_fsm_ext_sens_matrix_set(stmdev_ctx_t *ctx, + lsm6dsv16x_xl_fsm_ext_sens_matrix_t val); +int32_t lsm6dsv16x_fsm_ext_sens_matrix_get(stmdev_ctx_t *ctx, + lsm6dsv16x_xl_fsm_ext_sens_matrix_t *val); + +typedef enum +{ + LSM6DSV16X_Z_EQ_Y = 0x0, + LSM6DSV16X_Z_EQ_MIN_Y = 0x1, + LSM6DSV16X_Z_EQ_X = 0x2, + LSM6DSV16X_Z_EQ_MIN_X = 0x3, + LSM6DSV16X_Z_EQ_MIN_Z = 0x4, + LSM6DSV16X_Z_EQ_Z = 0x5, +} lsm6dsv16x_fsm_ext_sens_z_orient_t; +int32_t lsm6dsv16x_fsm_ext_sens_z_orient_set(stmdev_ctx_t *ctx, + lsm6dsv16x_fsm_ext_sens_z_orient_t val); +int32_t lsm6dsv16x_fsm_ext_sens_z_orient_get(stmdev_ctx_t *ctx, + lsm6dsv16x_fsm_ext_sens_z_orient_t *val); + +typedef enum +{ + LSM6DSV16X_Y_EQ_Y = 0x0, + LSM6DSV16X_Y_EQ_MIN_Y = 0x1, + LSM6DSV16X_Y_EQ_X = 0x2, + LSM6DSV16X_Y_EQ_MIN_X = 0x3, + LSM6DSV16X_Y_EQ_MIN_Z = 0x4, + LSM6DSV16X_Y_EQ_Z = 0x5, +} lsm6dsv16x_fsm_ext_sens_y_orient_t; +int32_t lsm6dsv16x_fsm_ext_sens_y_orient_set(stmdev_ctx_t *ctx, + lsm6dsv16x_fsm_ext_sens_y_orient_t val); +int32_t lsm6dsv16x_fsm_ext_sens_y_orient_get(stmdev_ctx_t *ctx, + lsm6dsv16x_fsm_ext_sens_y_orient_t *val); + +typedef enum +{ + LSM6DSV16X_X_EQ_Y = 0x0, + LSM6DSV16X_X_EQ_MIN_Y = 0x1, + LSM6DSV16X_X_EQ_X = 0x2, + LSM6DSV16X_X_EQ_MIN_X = 0x3, + LSM6DSV16X_X_EQ_MIN_Z = 0x4, + LSM6DSV16X_X_EQ_Z = 0x5, +} lsm6dsv16x_fsm_ext_sens_x_orient_t; +int32_t lsm6dsv16x_fsm_ext_sens_x_orient_set(stmdev_ctx_t *ctx, + lsm6dsv16x_fsm_ext_sens_x_orient_t val); +int32_t lsm6dsv16x_fsm_ext_sens_x_orient_get(stmdev_ctx_t *ctx, + lsm6dsv16x_fsm_ext_sens_x_orient_t *val); + +int32_t lsm6dsv16x_fsm_long_cnt_timeout_set(stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv16x_fsm_long_cnt_timeout_get(stmdev_ctx_t *ctx, uint16_t *val); + +int32_t lsm6dsv16x_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16x_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv16x_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val); + +int32_t lsm6dsv16x_ff_time_windows_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_ff_time_windows_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16X_156_mg = 0x0, + LSM6DSV16X_219_mg = 0x1, + LSM6DSV16X_250_mg = 0x2, + LSM6DSV16X_312_mg = 0x3, + LSM6DSV16X_344_mg = 0x4, + LSM6DSV16X_406_mg = 0x5, + LSM6DSV16X_469_mg = 0x6, + LSM6DSV16X_500_mg = 0x7, +} lsm6dsv16x_ff_thresholds_t; +int32_t lsm6dsv16x_ff_thresholds_set(stmdev_ctx_t *ctx, + lsm6dsv16x_ff_thresholds_t val); +int32_t lsm6dsv16x_ff_thresholds_get(stmdev_ctx_t *ctx, + lsm6dsv16x_ff_thresholds_t *val); + +typedef enum +{ + LSM6DSV16X_MLC_OFF = 0x0, + LSM6DSV16X_MLC_ON = 0x1, + LSM6DSV16X_MLC_ON_BEFORE_FSM = 0x2, +} lsm6dsv16x_mlc_mode_t; +int32_t lsm6dsv16x_mlc_set(stmdev_ctx_t *ctx, lsm6dsv16x_mlc_mode_t val); +int32_t lsm6dsv16x_mlc_get(stmdev_ctx_t *ctx, lsm6dsv16x_mlc_mode_t *val); + +typedef enum +{ + LSM6DSV16X_MLC_15Hz = 0x0, + LSM6DSV16X_MLC_30Hz = 0x1, + LSM6DSV16X_MLC_60Hz = 0x2, + LSM6DSV16X_MLC_120Hz = 0x3, + LSM6DSV16X_MLC_240Hz = 0x4, + LSM6DSV16X_MLC_480Hz = 0x5, + LSM6DSV16X_MLC_960Hz = 0x6, +} lsm6dsv16x_mlc_data_rate_t; +int32_t lsm6dsv16x_mlc_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv16x_mlc_data_rate_t val); +int32_t lsm6dsv16x_mlc_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv16x_mlc_data_rate_t *val); + +typedef struct +{ + uint8_t mlc1_src; + uint8_t mlc2_src; + uint8_t mlc3_src; + uint8_t mlc4_src; +} lsm6dsv16x_mlc_out_t; +int32_t lsm6dsv16x_mlc_out_get(stmdev_ctx_t *ctx, lsm6dsv16x_mlc_out_t *val); + +int32_t lsm6dsv16x_mlc_ext_sens_sensitivity_set(stmdev_ctx_t *ctx, + uint16_t val); +int32_t lsm6dsv16x_mlc_ext_sens_sensitivity_get(stmdev_ctx_t *ctx, + uint16_t *val); + +typedef enum +{ + LSM6DSV16X_OIS_CTRL_FROM_OIS = 0x0, + LSM6DSV16X_OIS_CTRL_FROM_UI = 0x1, +} lsm6dsv16x_ois_ctrl_mode_t; +int32_t lsm6dsv16x_ois_ctrl_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16x_ois_ctrl_mode_t val); +int32_t lsm6dsv16x_ois_ctrl_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16x_ois_ctrl_mode_t *val); + +int32_t lsm6dsv16x_ois_reset_set(stmdev_ctx_t *ctx, int8_t val); +int32_t lsm6dsv16x_ois_reset_get(stmdev_ctx_t *ctx, int8_t *val); + +int32_t lsm6dsv16x_ois_interface_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_ois_interface_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t ack : 1; + uint8_t req : 1; +} lsm6dsv16x_ois_handshake_t; +int32_t lsm6dsv16x_ois_handshake_from_ui_set(stmdev_ctx_t *ctx, + lsm6dsv16x_ois_handshake_t val); +int32_t lsm6dsv16x_ois_handshake_from_ui_get(stmdev_ctx_t *ctx, + lsm6dsv16x_ois_handshake_t *val); +int32_t lsm6dsv16x_ois_handshake_from_ois_set(stmdev_ctx_t *ctx, + lsm6dsv16x_ois_handshake_t val); +int32_t lsm6dsv16x_ois_handshake_from_ois_get(stmdev_ctx_t *ctx, + lsm6dsv16x_ois_handshake_t *val); + +int32_t lsm6dsv16x_ois_shared_set(stmdev_ctx_t *ctx, uint8_t val[6]); +int32_t lsm6dsv16x_ois_shared_get(stmdev_ctx_t *ctx, uint8_t val[6]); + +int32_t lsm6dsv16x_ois_on_spi2_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_ois_on_spi2_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t gy : 1; + uint8_t xl : 1; +} lsm6dsv16x_ois_chain_t; +int32_t lsm6dsv16x_ois_chain_set(stmdev_ctx_t *ctx, lsm6dsv16x_ois_chain_t val); +int32_t lsm6dsv16x_ois_chain_get(stmdev_ctx_t *ctx, + lsm6dsv16x_ois_chain_t *val); + +typedef enum +{ + LSM6DSV16X_OIS_125dps = 0x0, + LSM6DSV16X_OIS_250dps = 0x1, + LSM6DSV16X_OIS_500dps = 0x2, + LSM6DSV16X_OIS_1000dps = 0x3, + LSM6DSV16X_OIS_2000dps = 0x4, +} lsm6dsv16x_ois_gy_full_scale_t; +int32_t lsm6dsv16x_ois_gy_full_scale_set(stmdev_ctx_t *ctx, + lsm6dsv16x_ois_gy_full_scale_t val); +int32_t lsm6dsv16x_ois_gy_full_scale_get(stmdev_ctx_t *ctx, + lsm6dsv16x_ois_gy_full_scale_t *val); + +typedef enum +{ + LSM6DSV16X_OIS_2g = 0x0, + LSM6DSV16X_OIS_4g = 0x1, + LSM6DSV16X_OIS_8g = 0x2, + LSM6DSV16X_OIS_16g = 0x3, +} lsm6dsv16x_ois_xl_full_scale_t; +int32_t lsm6dsv16x_ois_xl_full_scale_set(stmdev_ctx_t *ctx, + lsm6dsv16x_ois_xl_full_scale_t val); +int32_t lsm6dsv16x_ois_xl_full_scale_get(stmdev_ctx_t *ctx, + lsm6dsv16x_ois_xl_full_scale_t *val); + +typedef enum +{ + LSM6DSV16X_DEG_80 = 0x0, + LSM6DSV16X_DEG_70 = 0x1, + LSM6DSV16X_DEG_60 = 0x2, + LSM6DSV16X_DEG_50 = 0x3, +} lsm6dsv16x_6d_threshold_t; +int32_t lsm6dsv16x_6d_threshold_set(stmdev_ctx_t *ctx, + lsm6dsv16x_6d_threshold_t val); +int32_t lsm6dsv16x_6d_threshold_get(stmdev_ctx_t *ctx, + lsm6dsv16x_6d_threshold_t *val); + +int32_t lsm6dsv16x_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16X_2400MOhm = 0x0, + LSM6DSV16X_730MOhm = 0x1, + LSM6DSV16X_300MOhm = 0x2, + LSM6DSV16X_255MOhm = 0x3, +} lsm6dsv16x_ah_qvar_zin_t; +int32_t lsm6dsv16x_ah_qvar_zin_set(stmdev_ctx_t *ctx, + lsm6dsv16x_ah_qvar_zin_t val); +int32_t lsm6dsv16x_ah_qvar_zin_get(stmdev_ctx_t *ctx, + lsm6dsv16x_ah_qvar_zin_t *val); + +typedef struct +{ + uint8_t ah_qvar_en : 1; +} lsm6dsv16x_ah_qvar_mode_t; +int32_t lsm6dsv16x_ah_qvar_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16x_ah_qvar_mode_t val); +int32_t lsm6dsv16x_ah_qvar_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16x_ah_qvar_mode_t *val); + +typedef enum +{ + LSM6DSV16X_SW_RST_DYN_ADDRESS_RST = 0x0, + LSM6DSV16X_I3C_GLOBAL_RST = 0x1, +} lsm6dsv16x_i3c_reset_mode_t; +int32_t lsm6dsv16x_i3c_reset_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16x_i3c_reset_mode_t val); +int32_t lsm6dsv16x_i3c_reset_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16x_i3c_reset_mode_t *val); + +typedef enum +{ + LSM6DSV16X_IBI_2us = 0x0, + LSM6DSV16X_IBI_50us = 0x1, + LSM6DSV16X_IBI_1ms = 0x2, + LSM6DSV16X_IBI_25ms = 0x3, +} lsm6dsv16x_i3c_ibi_time_t; +int32_t lsm6dsv16x_i3c_ibi_time_set(stmdev_ctx_t *ctx, + lsm6dsv16x_i3c_ibi_time_t val); +int32_t lsm6dsv16x_i3c_ibi_time_get(stmdev_ctx_t *ctx, + lsm6dsv16x_i3c_ibi_time_t *val); + +int32_t lsm6dsv16x_sh_master_interface_pull_up_set(stmdev_ctx_t *ctx, + uint8_t val); +int32_t lsm6dsv16x_sh_master_interface_pull_up_get(stmdev_ctx_t *ctx, + uint8_t *val); + +typedef struct +{ + lsm6dsv16x_sensor_hub_1_t sh_byte_1; + lsm6dsv16x_sensor_hub_2_t sh_byte_2; + lsm6dsv16x_sensor_hub_3_t sh_byte_3; + lsm6dsv16x_sensor_hub_4_t sh_byte_4; + lsm6dsv16x_sensor_hub_5_t sh_byte_5; + lsm6dsv16x_sensor_hub_6_t sh_byte_6; + lsm6dsv16x_sensor_hub_7_t sh_byte_7; + lsm6dsv16x_sensor_hub_8_t sh_byte_8; + lsm6dsv16x_sensor_hub_9_t sh_byte_9; + lsm6dsv16x_sensor_hub_10_t sh_byte_10; + lsm6dsv16x_sensor_hub_11_t sh_byte_11; + lsm6dsv16x_sensor_hub_12_t sh_byte_12; + lsm6dsv16x_sensor_hub_13_t sh_byte_13; + lsm6dsv16x_sensor_hub_14_t sh_byte_14; + lsm6dsv16x_sensor_hub_15_t sh_byte_15; + lsm6dsv16x_sensor_hub_16_t sh_byte_16; + lsm6dsv16x_sensor_hub_17_t sh_byte_17; + lsm6dsv16x_sensor_hub_18_t sh_byte_18; +} lsm6dsv16x_emb_sh_read_t; +int32_t lsm6dsv16x_sh_read_data_raw_get(stmdev_ctx_t *ctx, + lsm6dsv16x_emb_sh_read_t *val, + uint8_t len); + +typedef enum +{ + LSM6DSV16X_SLV_0 = 0x0, + LSM6DSV16X_SLV_0_1 = 0x1, + LSM6DSV16X_SLV_0_1_2 = 0x2, + LSM6DSV16X_SLV_0_1_2_3 = 0x3, +} lsm6dsv16x_sh_slave_connected_t; +int32_t lsm6dsv16x_sh_slave_connected_set(stmdev_ctx_t *ctx, + lsm6dsv16x_sh_slave_connected_t val); +int32_t lsm6dsv16x_sh_slave_connected_get(stmdev_ctx_t *ctx, + lsm6dsv16x_sh_slave_connected_t *val); + +int32_t lsm6dsv16x_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16x_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16X_SH_TRG_XL_GY_DRDY = 0x0, + LSM6DSV16X_SH_TRIG_INT2 = 0x1, +} lsm6dsv16x_sh_syncro_mode_t; +int32_t lsm6dsv16x_sh_syncro_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16x_sh_syncro_mode_t val); +int32_t lsm6dsv16x_sh_syncro_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16x_sh_syncro_mode_t *val); + +typedef enum +{ + LSM6DSV16X_EACH_SH_CYCLE = 0x0, + LSM6DSV16X_ONLY_FIRST_CYCLE = 0x1, +} lsm6dsv16x_sh_write_mode_t; +int32_t lsm6dsv16x_sh_write_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16x_sh_write_mode_t val); +int32_t lsm6dsv16x_sh_write_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16x_sh_write_mode_t *val); + +int32_t lsm6dsv16x_sh_reset_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t slv0_add; + uint8_t slv0_subadd; + uint8_t slv0_data; +} lsm6dsv16x_sh_cfg_write_t; +int32_t lsm6dsv16x_sh_cfg_write(stmdev_ctx_t *ctx, + lsm6dsv16x_sh_cfg_write_t *val); +typedef enum +{ + LSM6DSV16X_SH_15Hz = 0x1, + LSM6DSV16X_SH_30Hz = 0x2, + LSM6DSV16X_SH_60Hz = 0x3, + LSM6DSV16X_SH_120Hz = 0x4, + LSM6DSV16X_SH_240Hz = 0x5, + LSM6DSV16X_SH_480Hz = 0x6, +} lsm6dsv16x_sh_data_rate_t; +int32_t lsm6dsv16x_sh_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv16x_sh_data_rate_t val); +int32_t lsm6dsv16x_sh_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv16x_sh_data_rate_t *val); + +typedef struct +{ + uint8_t slv_add; + uint8_t slv_subadd; + uint8_t slv_len; +} lsm6dsv16x_sh_cfg_read_t; +int32_t lsm6dsv16x_sh_slv0_cfg_read(stmdev_ctx_t *ctx, + lsm6dsv16x_sh_cfg_read_t *val); +int32_t lsm6dsv16x_sh_slv1_cfg_read(stmdev_ctx_t *ctx, + lsm6dsv16x_sh_cfg_read_t *val); +int32_t lsm6dsv16x_sh_slv2_cfg_read(stmdev_ctx_t *ctx, + lsm6dsv16x_sh_cfg_read_t *val); +int32_t lsm6dsv16x_sh_slv3_cfg_read(stmdev_ctx_t *ctx, + lsm6dsv16x_sh_cfg_read_t *val); + + +int32_t lsm6dsv16x_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16X_I2C_I3C_ENABLE = 0x0, + LSM6DSV16X_I2C_I3C_DISABLE = 0x1, +} lsm6dsv16x_ui_i2c_i3c_mode_t; +int32_t lsm6dsv16x_ui_i2c_i3c_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16x_ui_i2c_i3c_mode_t val); +int32_t lsm6dsv16x_ui_i2c_i3c_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16x_ui_i2c_i3c_mode_t *val); + +typedef enum +{ + LSM6DSV16X_SPI_4_WIRE = 0x0, + LSM6DSV16X_SPI_3_WIRE = 0x1, +} lsm6dsv16x_spi_mode_t; +int32_t lsm6dsv16x_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_spi_mode_t val); +int32_t lsm6dsv16x_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_spi_mode_t *val); + +int32_t lsm6dsv16x_ui_sda_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_ui_sda_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16X_SPI2_4_WIRE = 0x0, + LSM6DSV16X_SPI2_3_WIRE = 0x1, +} lsm6dsv16x_spi2_mode_t; +int32_t lsm6dsv16x_spi2_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_spi2_mode_t val); +int32_t lsm6dsv16x_spi2_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16x_spi2_mode_t *val); + +int32_t lsm6dsv16x_sigmot_mode_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_sigmot_mode_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t step_counter_enable : 1; + uint8_t false_step_rej : 1; +} lsm6dsv16x_stpcnt_mode_t; +int32_t lsm6dsv16x_stpcnt_mode_set(stmdev_ctx_t *ctx, + lsm6dsv16x_stpcnt_mode_t val); +int32_t lsm6dsv16x_stpcnt_mode_get(stmdev_ctx_t *ctx, + lsm6dsv16x_stpcnt_mode_t *val); + +int32_t lsm6dsv16x_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val); + +int32_t lsm6dsv16x_stpcnt_rst_step_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_stpcnt_rst_step_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16x_stpcnt_debounce_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_stpcnt_debounce_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16x_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv16x_stpcnt_period_get(stmdev_ctx_t *ctx, uint16_t *val); + +int32_t lsm6dsv16x_sflp_game_rotation_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_sflp_game_rotation_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + float_t gbias_x; /* dps */ + float_t gbias_y; /* dps */ + float_t gbias_z; /* dps */ +} lsm6dsv16x_sflp_gbias_t; +int32_t lsm6dsv16x_sflp_game_gbias_set(stmdev_ctx_t *ctx, + lsm6dsv16x_sflp_gbias_t *val); + +typedef enum +{ + LSM6DSV16X_SFLP_15Hz = 0x0, + LSM6DSV16X_SFLP_30Hz = 0x1, + LSM6DSV16X_SFLP_60Hz = 0x2, + LSM6DSV16X_SFLP_120Hz = 0x3, + LSM6DSV16X_SFLP_240Hz = 0x4, + LSM6DSV16X_SFLP_480Hz = 0x5, +} lsm6dsv16x_sflp_data_rate_t; +int32_t lsm6dsv16x_sflp_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv16x_sflp_data_rate_t val); +int32_t lsm6dsv16x_sflp_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv16x_sflp_data_rate_t *val); + +typedef struct +{ + uint8_t tap_x_en : 1; + uint8_t tap_y_en : 1; + uint8_t tap_z_en : 1; +} lsm6dsv16x_tap_detection_t; +int32_t lsm6dsv16x_tap_detection_set(stmdev_ctx_t *ctx, + lsm6dsv16x_tap_detection_t val); +int32_t lsm6dsv16x_tap_detection_get(stmdev_ctx_t *ctx, + lsm6dsv16x_tap_detection_t *val); + +typedef struct +{ + uint8_t x : 5; + uint8_t y : 5; + uint8_t z : 5; +} lsm6dsv16x_tap_thresholds_t; +int32_t lsm6dsv16x_tap_thresholds_set(stmdev_ctx_t *ctx, + lsm6dsv16x_tap_thresholds_t val); +int32_t lsm6dsv16x_tap_thresholds_get(stmdev_ctx_t *ctx, + lsm6dsv16x_tap_thresholds_t *val); + +typedef enum +{ + LSM6DSV16X_XYZ = 0x0, + LSM6DSV16X_YXZ = 0x1, + LSM6DSV16X_XZY = 0x2, + LSM6DSV16X_ZYX = 0x3, + LSM6DSV16X_YZX = 0x5, + LSM6DSV16X_ZXY = 0x6, +} lsm6dsv16x_tap_axis_priority_t; +int32_t lsm6dsv16x_tap_axis_priority_set(stmdev_ctx_t *ctx, + lsm6dsv16x_tap_axis_priority_t val); +int32_t lsm6dsv16x_tap_axis_priority_get(stmdev_ctx_t *ctx, + lsm6dsv16x_tap_axis_priority_t *val); + +typedef struct +{ + uint8_t shock : 2; + uint8_t quiet : 2; + uint8_t tap_gap : 4; +} lsm6dsv16x_tap_time_windows_t; +int32_t lsm6dsv16x_tap_time_windows_set(stmdev_ctx_t *ctx, + lsm6dsv16x_tap_time_windows_t val); +int32_t lsm6dsv16x_tap_time_windows_get(stmdev_ctx_t *ctx, + lsm6dsv16x_tap_time_windows_t *val); + +typedef enum +{ + LSM6DSV16X_ONLY_SINGLE = 0x0, + LSM6DSV16X_BOTH_SINGLE_DOUBLE = 0x1, +} lsm6dsv16x_tap_mode_t; +int32_t lsm6dsv16x_tap_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_tap_mode_t val); +int32_t lsm6dsv16x_tap_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_tap_mode_t *val); + +int32_t lsm6dsv16x_tilt_mode_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_tilt_mode_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16x_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); + +int32_t lsm6dsv16x_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16X_XL_AND_GY_NOT_AFFECTED = 0x0, + LSM6DSV16X_XL_LOW_POWER_GY_NOT_AFFECTED = 0x1, + LSM6DSV16X_XL_LOW_POWER_GY_SLEEP = 0x2, + LSM6DSV16X_XL_LOW_POWER_GY_POWER_DOWN = 0x3, +} lsm6dsv16x_act_mode_t; +int32_t lsm6dsv16x_act_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_act_mode_t val); +int32_t lsm6dsv16x_act_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_act_mode_t *val); + +typedef enum +{ + LSM6DSV16X_SLEEP_TO_ACT_AT_1ST_SAMPLE = 0x0, + LSM6DSV16X_SLEEP_TO_ACT_AT_2ND_SAMPLE = 0x1, + LSM6DSV16X_SLEEP_TO_ACT_AT_3RD_SAMPLE = 0x2, + LSM6DSV16X_SLEEP_TO_ACT_AT_4th_SAMPLE = 0x3, +} lsm6dsv16x_act_from_sleep_to_act_dur_t; +int32_t lsm6dsv16x_act_from_sleep_to_act_dur_set(stmdev_ctx_t *ctx, + lsm6dsv16x_act_from_sleep_to_act_dur_t val); +int32_t lsm6dsv16x_act_from_sleep_to_act_dur_get(stmdev_ctx_t *ctx, + lsm6dsv16x_act_from_sleep_to_act_dur_t *val); + +typedef enum +{ + LSM6DSV16X_1Hz875 = 0x0, + LSM6DSV16X_15Hz = 0x1, + LSM6DSV16X_30Hz = 0x2, + LSM6DSV16X_60Hz = 0x3, +} lsm6dsv16x_act_sleep_xl_odr_t; +int32_t lsm6dsv16x_act_sleep_xl_odr_set(stmdev_ctx_t *ctx, + lsm6dsv16x_act_sleep_xl_odr_t val); +int32_t lsm6dsv16x_act_sleep_xl_odr_get(stmdev_ctx_t *ctx, + lsm6dsv16x_act_sleep_xl_odr_t *val); + +typedef struct +{ + lsm6dsv16x_inactivity_dur_t inactivity_cfg; + uint8_t inactivity_ths; + uint8_t threshold; + uint8_t duration; +} lsm6dsv16x_act_thresholds_t; +int32_t lsm6dsv16x_act_thresholds_set(stmdev_ctx_t *ctx, + lsm6dsv16x_act_thresholds_t *val); +int32_t lsm6dsv16x_act_thresholds_get(stmdev_ctx_t *ctx, + lsm6dsv16x_act_thresholds_t *val); + +typedef struct +{ + uint8_t shock : 2; + uint8_t quiet : 4; +} lsm6dsv16x_act_wkup_time_windows_t; +int32_t lsm6dsv16x_act_wkup_time_windows_set(stmdev_ctx_t *ctx, + lsm6dsv16x_act_wkup_time_windows_t val); +int32_t lsm6dsv16x_act_wkup_time_windows_get(stmdev_ctx_t *ctx, + lsm6dsv16x_act_wkup_time_windows_t *val); + +/** + * @} + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /*LSM6DSV16X_DRIVER_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dsv_STdC/driver/lsm6dsv_reg.c b/sensor/stmemsc/lsm6dsv_STdC/driver/lsm6dsv_reg.c new file mode 100644 index 0000000000000000000000000000000000000000..ef185095ad32e56d790902e154fb5a11fe36d981 --- /dev/null +++ b/sensor/stmemsc/lsm6dsv_STdC/driver/lsm6dsv_reg.c @@ -0,0 +1,8726 @@ +/** + ****************************************************************************** + * @file lsm6dsv_reg.c + * @author Sensors Software Solution Team + * @brief LSM6DSV driver file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2022 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "lsm6dsv_reg.h" + +/** + * @defgroup LSM6DSV + * @brief This file provides a set of functions needed to drive the + * lsm6dsv enhanced inertial module. + * @{ + * + */ + +/** + * @defgroup Interfaces functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +/** + * @brief Read generic device register + * + * @param ctx communication interface handler.(ptr) + * @param reg first register address to read. + * @param data buffer for data read.(ptr) + * @param len number of consecutive register to read. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak lsm6dsv_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) +{ + int32_t ret; + + ret = ctx->read_reg(ctx->handle, reg, data, len); + + return ret; +} + +/** + * @brief Write generic device register + * + * @param ctx communication interface handler.(ptr) + * @param reg first register address to write. + * @param data the buffer contains data to be written.(ptr) + * @param len number of consecutive register to write. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak lsm6dsv_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) +{ + int32_t ret; + + ret = ctx->write_reg(ctx->handle, reg, data, len); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Private functions + * @brief Section collect all the utility functions needed by APIs. + * @{ + * + */ + +static void bytecpy(uint8_t *target, uint8_t *source) +{ + if ((target != NULL) && (source != NULL)) + { + *target = *source; + } +} + +/** + * @} + * + */ + +/** + * @defgroup Sensitivity + * @brief These functions convert raw-data into engineering units. + * @{ + * + */ +float_t lsm6dsv_from_fs2_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.061f; +} + +float_t lsm6dsv_from_fs4_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.122f; +} + +float_t lsm6dsv_from_fs8_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.244f; +} + +float_t lsm6dsv_from_fs16_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.488f; +} + +float_t lsm6dsv_from_fs125_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 4.375f; +} + +float_t lsm6dsv_from_fs250_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 8.750f; +} + +float_t lsm6dsv_from_fs500_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 17.50f; +} + +float_t lsm6dsv_from_fs1000_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 35.0f; +} + +float_t lsm6dsv_from_fs2000_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 70.0f; +} + +float_t lsm6dsv_from_fs4000_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 140.0f; +} + +float_t lsm6dsv_from_lsb_to_celsius(int16_t lsb) +{ + return (((float_t)lsb / 256.0f) + 25.0f); +} + +float_t lsm6dsv_from_lsb_to_nsec(uint32_t lsb) +{ + return ((float_t)lsb * 21750.0f); +} + +/** + * @} + * + */ + +/** + * @defgroup Accelerometer user offset correction + * @brief This section groups all the functions concerning the + * usage of Accelerometer user offset correction + * @{ + * + */ + +/** + * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[set] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_xl_offset_on_out_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.usr_off_on_out = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[get] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_xl_offset_on_out_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1); + *val = ctrl9.usr_off_on_out; + + return ret; +} + +/** + * @brief Accelerometer user offset correction values in mg.[set] + * + * @param ctx read / write interface definitions + * @param val Accelerometer user offset correction values in mg. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_xl_offset_mg_set(stmdev_ctx_t *ctx, + lsm6dsv_xl_offset_mg_t val) +{ + lsm6dsv_z_ofs_usr_t z_ofs_usr; + lsm6dsv_y_ofs_usr_t y_ofs_usr; + lsm6dsv_x_ofs_usr_t x_ofs_usr; + lsm6dsv_ctrl9_t ctrl9; + int32_t ret; + float_t tmp; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + } + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + } + + + if ((val.x_mg < (0.0078125f * 127.0f)) && (val.x_mg > (0.0078125f * -127.0f)) && + (val.y_mg < (0.0078125f * 127.0f)) && (val.y_mg > (0.0078125f * -127.0f)) && + (val.z_mg < (0.0078125f * 127.0f)) && (val.z_mg > (0.0078125f * -127.0f))) + { + ctrl9.usr_off_w = 0; + + tmp = val.z_mg / 0.0078125f; + z_ofs_usr.z_ofs_usr = (uint8_t)tmp; + + tmp = val.y_mg / 0.0078125f; + y_ofs_usr.y_ofs_usr = (uint8_t)tmp; + + tmp = val.x_mg / 0.0078125f; + x_ofs_usr.x_ofs_usr = (uint8_t)tmp; + } + else if ((val.x_mg < (0.125f * 127.0f)) && (val.x_mg > (0.125f * -127.0f)) && + (val.y_mg < (0.125f * 127.0f)) && (val.y_mg > (0.125f * -127.0f)) && + (val.z_mg < (0.125f * 127.0f)) && (val.z_mg > (0.125f * -127.0f))) + { + ctrl9.usr_off_w = 1; + + tmp = val.z_mg / 0.125f; + z_ofs_usr.z_ofs_usr = (uint8_t)tmp; + + tmp = val.y_mg / 0.125f; + y_ofs_usr.y_ofs_usr = (uint8_t)tmp; + + tmp = val.x_mg / 0.125f; + x_ofs_usr.x_ofs_usr = (uint8_t)tmp; + } + else // out of limit + { + ctrl9.usr_off_w = 1; + z_ofs_usr.z_ofs_usr = 0xFFU; + y_ofs_usr.y_ofs_usr = 0xFFU; + x_ofs_usr.x_ofs_usr = 0xFFU; + } + + if (ret == 0) + { + ret = lsm6dsv_write_reg(ctx, LSM6DSV_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + } + if (ret == 0) + { + ret = lsm6dsv_write_reg(ctx, LSM6DSV_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + } + if (ret == 0) + { + ret = lsm6dsv_write_reg(ctx, LSM6DSV_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + } + if (ret == 0) + { + ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1); + } + return ret; +} + +/** + * @brief Accelerometer user offset correction values in mg.[get] + * + * @param ctx read / write interface definitions + * @param val Accelerometer user offset correction values in mg. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_xl_offset_mg_get(stmdev_ctx_t *ctx, + lsm6dsv_xl_offset_mg_t *val) +{ + lsm6dsv_z_ofs_usr_t z_ofs_usr; + lsm6dsv_y_ofs_usr_t y_ofs_usr; + lsm6dsv_x_ofs_usr_t x_ofs_usr; + lsm6dsv_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + } + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + } + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + } + + if (ctrl9.usr_off_w == PROPERTY_DISABLE) + { + val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.0078125f); + val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.0078125f); + val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.0078125f); + } + else + { + val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.125f); + val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.125f); + val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.125f); + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @brief Reset of the device.[set] + * + * @param ctx read / write interface definitions + * @param val Reset of the device. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_reset_set(stmdev_ctx_t *ctx, lsm6dsv_reset_t val) +{ + lsm6dsv_func_cfg_access_t func_cfg_access; + lsm6dsv_ctrl3_t ctrl3; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + ctrl3.boot = ((uint8_t)val & 0x04U) >> 2; + ctrl3.sw_reset = ((uint8_t)val & 0x02U) >> 1; + func_cfg_access.sw_por = (uint8_t)val & 0x01U; + + if (ret == 0) + { + ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL3, (uint8_t *)&ctrl3, 1); + } + if (ret == 0) + { + ret = lsm6dsv_write_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Global reset of the device.[get] + * + * @param ctx read / write interface definitions + * @param val Global reset of the device. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_reset_get(stmdev_ctx_t *ctx, lsm6dsv_reset_t *val) +{ + lsm6dsv_func_cfg_access_t func_cfg_access; + lsm6dsv_ctrl3_t ctrl3; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + switch ((ctrl3.sw_reset << 2) + (ctrl3.boot << 1) + func_cfg_access.sw_por) + { + case LSM6DSV_READY: + *val = LSM6DSV_READY; + break; + + case LSM6DSV_GLOBAL_RST: + *val = LSM6DSV_GLOBAL_RST; + break; + + case LSM6DSV_RESTORE_CAL_PARAM: + *val = LSM6DSV_RESTORE_CAL_PARAM; + break; + + case LSM6DSV_RESTORE_CTRL_REGS: + *val = LSM6DSV_RESTORE_CTRL_REGS; + break; + + default: + *val = LSM6DSV_GLOBAL_RST; + break; + } + return ret; +} + +/** + * @brief Change memory bank.[set] + * + * @param ctx read / write interface definitions + * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_mem_bank_set(stmdev_ctx_t *ctx, lsm6dsv_mem_bank_t val) +{ + lsm6dsv_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + if (ret == 0) + { + func_cfg_access.shub_reg_access = ((uint8_t)val & 0x02U) >> 1; + func_cfg_access.emb_func_reg_access = (uint8_t)val & 0x01U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Change memory bank.[get] + * + * @param ctx read / write interface definitions + * @param val MAIN_MEM_BANK, SENSOR_HUB_MEM_BANK, EMBED_FUNC_MEM_BANK, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_mem_bank_get(stmdev_ctx_t *ctx, lsm6dsv_mem_bank_t *val) +{ + lsm6dsv_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + switch ((func_cfg_access.shub_reg_access << 1) + func_cfg_access.emb_func_reg_access) + { + case LSM6DSV_MAIN_MEM_BANK: + *val = LSM6DSV_MAIN_MEM_BANK; + break; + + case LSM6DSV_EMBED_FUNC_MEM_BANK: + *val = LSM6DSV_EMBED_FUNC_MEM_BANK; + break; + + case LSM6DSV_SENSOR_HUB_MEM_BANK: + *val = LSM6DSV_SENSOR_HUB_MEM_BANK; + break; + + default: + *val = LSM6DSV_MAIN_MEM_BANK; + break; + } + return ret; +} + +/** + * @brief Device ID.[get] THis function works also for OIS + * (WHO_AM_I and SPI2_WHO_AM_I have same address) + * + * @param ctx read / write interface definitions + * @param val Device ID. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_device_id_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_WHO_AM_I, val, 1); + + return ret; +} + +/** + * @brief Accelerometer output data rate (ODR) selection.[set] + * + * @param ctx read / write interface definitions + * @param val lsm6dsv_data_rate_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_xl_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv_data_rate_t val) +{ + lsm6dsv_ctrl1_t ctrl1; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret == 0) + { + ctrl1.odr_xl = (uint8_t)val & 0x0Fu; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL1, (uint8_t *)&ctrl1, 1); + } + + return ret; +} + +/** + * @brief Accelerometer output data rate (ODR) selection.[get] + * + * @param ctx read / write interface definitions + * @param val lsm6dsv_data_rate_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_xl_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv_data_rate_t *val) +{ + lsm6dsv_ctrl1_t ctrl1; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL1, (uint8_t *)&ctrl1, 1); + + switch (ctrl1.odr_xl) + { + case LSM6DSV_ODR_OFF: + *val = LSM6DSV_ODR_OFF; + break; + + case LSM6DSV_ODR_AT_1Hz875: + *val = LSM6DSV_ODR_AT_1Hz875; + break; + + case LSM6DSV_ODR_AT_7Hz5: + *val = LSM6DSV_ODR_AT_7Hz5; + break; + + case LSM6DSV_ODR_AT_15Hz: + *val = LSM6DSV_ODR_AT_15Hz; + break; + + case LSM6DSV_ODR_AT_30Hz: + *val = LSM6DSV_ODR_AT_30Hz; + break; + + case LSM6DSV_ODR_AT_60Hz: + *val = LSM6DSV_ODR_AT_60Hz; + break; + + case LSM6DSV_ODR_AT_120Hz: + *val = LSM6DSV_ODR_AT_120Hz; + break; + + case LSM6DSV_ODR_AT_240Hz: + *val = LSM6DSV_ODR_AT_240Hz; + break; + + case LSM6DSV_ODR_AT_480Hz: + *val = LSM6DSV_ODR_AT_480Hz; + break; + + case LSM6DSV_ODR_AT_960Hz: + *val = LSM6DSV_ODR_AT_960Hz; + break; + + case LSM6DSV_ODR_AT_1920Hz: + *val = LSM6DSV_ODR_AT_1920Hz; + break; + + case LSM6DSV_ODR_AT_3840Hz: + *val = LSM6DSV_ODR_AT_3840Hz; + break; + + case LSM6DSV_ODR_AT_7680Hz: + *val = LSM6DSV_ODR_AT_7680Hz; + break; + + default: + *val = LSM6DSV_ODR_OFF; + break; + } + return ret; +} + +/** + * @brief Accelerometer operating mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val XL_HIGH_PERFORMANCE_MD, XL_LOW_POWER_2_AVG_MD, XL_LOW_POWER_4_AVG_MD, XL_LOW_POWER_8_AVG_MD, XL_NORMAL_MD, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_xl_mode_set(stmdev_ctx_t *ctx, lsm6dsv_xl_mode_t val) +{ + lsm6dsv_ctrl1_t ctrl1; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL1, (uint8_t *)&ctrl1, 1); + + if (ret == 0) + { + ctrl1.op_mode_xl = (uint8_t)val & 0x07U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL1, (uint8_t *)&ctrl1, 1); + } + + return ret; +} + +/** + * @brief Accelerometer operating mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val XL_HIGH_PERFORMANCE_MD, XL_LOW_POWER_2_AVG_MD, XL_LOW_POWER_4_AVG_MD, XL_LOW_POWER_8_AVG_MD, XL_NORMAL_MD, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_xl_mode_get(stmdev_ctx_t *ctx, lsm6dsv_xl_mode_t *val) +{ + lsm6dsv_ctrl1_t ctrl1; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL1, (uint8_t *)&ctrl1, 1); + + switch (ctrl1.op_mode_xl) + { + case LSM6DSV_XL_HIGH_PERFORMANCE_MD: + *val = LSM6DSV_XL_HIGH_PERFORMANCE_MD; + break; + + case LSM6DSV_XL_LOW_POWER_2_AVG_MD: + *val = LSM6DSV_XL_LOW_POWER_2_AVG_MD; + break; + + case LSM6DSV_XL_LOW_POWER_4_AVG_MD: + *val = LSM6DSV_XL_LOW_POWER_4_AVG_MD; + break; + + case LSM6DSV_XL_LOW_POWER_8_AVG_MD: + *val = LSM6DSV_XL_LOW_POWER_8_AVG_MD; + break; + + case LSM6DSV_XL_NORMAL_MD: + *val = LSM6DSV_XL_NORMAL_MD; + break; + + default: + *val = LSM6DSV_XL_HIGH_PERFORMANCE_MD; + break; + } + return ret; +} + +/** + * @brief Gyroscope output data rate (ODR) selection.[set] + * + * @param ctx read / write interface definitions + * @param val lsm6dsv_data_rate_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_gy_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv_data_rate_t val) +{ + lsm6dsv_ctrl2_t ctrl2; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL2, (uint8_t *)&ctrl2, 1); + + if (ret == 0) + { + ctrl2.odr_g = (uint8_t)val & 0x0Fu; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL2, (uint8_t *)&ctrl2, 1); + } + + return ret; +} + +/** + * @brief Gyroscope output data rate (ODR) selection.[get] + * + * @param ctx read / write interface definitions + * @param val lsm6dsv_data_rate_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_gy_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv_data_rate_t *val) +{ + lsm6dsv_ctrl2_t ctrl2; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL2, (uint8_t *)&ctrl2, 1); + + switch (ctrl2.odr_g) + { + case LSM6DSV_ODR_OFF: + *val = LSM6DSV_ODR_OFF; + break; + + case LSM6DSV_ODR_AT_1Hz875: + *val = LSM6DSV_ODR_AT_1Hz875; + break; + + case LSM6DSV_ODR_AT_7Hz5: + *val = LSM6DSV_ODR_AT_7Hz5; + break; + + case LSM6DSV_ODR_AT_15Hz: + *val = LSM6DSV_ODR_AT_15Hz; + break; + + case LSM6DSV_ODR_AT_30Hz: + *val = LSM6DSV_ODR_AT_30Hz; + break; + + case LSM6DSV_ODR_AT_60Hz: + *val = LSM6DSV_ODR_AT_60Hz; + break; + + case LSM6DSV_ODR_AT_120Hz: + *val = LSM6DSV_ODR_AT_120Hz; + break; + + case LSM6DSV_ODR_AT_240Hz: + *val = LSM6DSV_ODR_AT_240Hz; + break; + + case LSM6DSV_ODR_AT_480Hz: + *val = LSM6DSV_ODR_AT_480Hz; + break; + + case LSM6DSV_ODR_AT_960Hz: + *val = LSM6DSV_ODR_AT_960Hz; + break; + + case LSM6DSV_ODR_AT_1920Hz: + *val = LSM6DSV_ODR_AT_1920Hz; + break; + + case LSM6DSV_ODR_AT_3840Hz: + *val = LSM6DSV_ODR_AT_3840Hz; + break; + + case LSM6DSV_ODR_AT_7680Hz: + *val = LSM6DSV_ODR_AT_7680Hz; + break; + + default: + *val = LSM6DSV_ODR_OFF; + break; + } + return ret; +} + +/** + * @brief Gyroscope operating mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val GY_HIGH_PERFORMANCE_MD, GY_SLEEP_MD, GY_LOW_POWER_MD, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_gy_mode_set(stmdev_ctx_t *ctx, lsm6dsv_gy_mode_t val) +{ + lsm6dsv_ctrl2_t ctrl2; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret == 0) + { + ctrl2.op_mode_g = (uint8_t)val & 0x07U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL2, (uint8_t *)&ctrl2, 1); + } + + return ret; +} + +/** + * @brief Gyroscope operating mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val GY_HIGH_PERFORMANCE_MD, GY_SLEEP_MD, GY_LOW_POWER_MD, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_gy_mode_get(stmdev_ctx_t *ctx, lsm6dsv_gy_mode_t *val) +{ + lsm6dsv_ctrl2_t ctrl2; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL2, (uint8_t *)&ctrl2, 1); + switch (ctrl2.op_mode_g) + { + case LSM6DSV_GY_HIGH_PERFORMANCE_MD: + *val = LSM6DSV_GY_HIGH_PERFORMANCE_MD; + break; + + case LSM6DSV_GY_HIGH_ACCURACY_ODR_MD: + *val = LSM6DSV_GY_HIGH_ACCURACY_ODR_MD; + break; + + case LSM6DSV_GY_SLEEP_MD: + *val = LSM6DSV_GY_SLEEP_MD; + break; + + case LSM6DSV_GY_LOW_POWER_MD: + *val = LSM6DSV_GY_LOW_POWER_MD; + break; + + default: + *val = LSM6DSV_GY_HIGH_PERFORMANCE_MD; + break; + } + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[set] + * + * @param ctx read / write interface definitions + * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_ctrl3_t ctrl3; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret == 0) + { + ctrl3.if_inc = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL3, (uint8_t *)&ctrl3, 1); + } + + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[get] + * + * @param ctx read / write interface definitions + * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_ctrl3_t ctrl3; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL3, (uint8_t *)&ctrl3, 1); + *val = ctrl3.if_inc; + + + return ret; +} + +/** + * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [set] + * + * @param ctx read / write interface definitions + * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_ctrl3_t ctrl3; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL3, (uint8_t *)&ctrl3, 1); + + if (ret == 0) + { + ctrl3.bdu = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL3, (uint8_t *)&ctrl3, 1); + } + + return ret; +} + +/** + * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [get] + * + * @param ctx read / write interface definitions + * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_ctrl3_t ctrl3; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL3, (uint8_t *)&ctrl3, 1); + *val = ctrl3.bdu; + + return ret; +} + +/** + * @brief Enables pulsed data-ready mode (~75 us).[set] + * + * @param ctx read / write interface definitions + * @param val DRDY_LATCHED, DRDY_PULSED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_data_ready_mode_set(stmdev_ctx_t *ctx, + lsm6dsv_data_ready_mode_t val) +{ + lsm6dsv_ctrl4_t ctrl4; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1); + + if (ret == 0) + { + ctrl4.drdy_pulsed = (uint8_t)val & 0x1U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1); + } + + return ret; +} + +/** + * @brief Enables pulsed data-ready mode (~75 us).[get] + * + * @param ctx read / write interface definitions + * @param val DRDY_LATCHED, DRDY_PULSED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_data_ready_mode_get(stmdev_ctx_t *ctx, + lsm6dsv_data_ready_mode_t *val) +{ + lsm6dsv_ctrl4_t ctrl4; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1); + + switch (ctrl4.drdy_pulsed) + { + case LSM6DSV_DRDY_LATCHED: + *val = LSM6DSV_DRDY_LATCHED; + break; + + case LSM6DSV_DRDY_PULSED: + *val = LSM6DSV_DRDY_PULSED; + break; + + default: + *val = LSM6DSV_DRDY_LATCHED; + break; + } + return ret; +} + +/** + * @brief Enables interrupt.[set] + * + * @param ctx read / write interface definitions + * @param val enable/disable, latched/pulsed + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_interrupt_enable_set(stmdev_ctx_t *ctx, + lsm6dsv_interrupt_mode_t val) +{ + lsm6dsv_tap_cfg0_t cfg; + lsm6dsv_functions_enable_t func; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&func, 1); + + if (ret == 0) + { + func.interrupts_enable = val.enable; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&func, 1); + } + + ret += lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&cfg, 1); + + if (ret == 0) + { + cfg.lir = val.lir; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&cfg, 1); + } + + return ret; +} + +/** + * @brief Enables latched interrupt mode.[get] + * + * @param ctx read / write interface definitions + * @param val enable/disable, latched/pulsed + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_interrupt_enable_get(stmdev_ctx_t *ctx, + lsm6dsv_interrupt_mode_t *val) +{ + lsm6dsv_tap_cfg0_t cfg; + lsm6dsv_functions_enable_t func; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&func, 1); + ret += lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&cfg, 1); + + val->enable = func.interrupts_enable; + val->lir = cfg.lir; + + return ret; +} + +/** + * @brief Gyroscope full-scale selection[set] + * + * @param ctx read / write interface definitions + * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_gy_full_scale_set(stmdev_ctx_t *ctx, + lsm6dsv_gy_full_scale_t val) +{ + lsm6dsv_ctrl6_t ctrl6; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL6, (uint8_t *)&ctrl6, 1); + + if (ret == 0) + { + ctrl6.fs_g = (uint8_t)val & 0xfu; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL6, (uint8_t *)&ctrl6, 1); + } + + return ret; +} + +/** + * @brief Gyroscope full-scale selection[get] + * + * @param ctx read / write interface definitions + * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_gy_full_scale_get(stmdev_ctx_t *ctx, + lsm6dsv_gy_full_scale_t *val) +{ + lsm6dsv_ctrl6_t ctrl6; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL6, (uint8_t *)&ctrl6, 1); + + switch (ctrl6.fs_g) + { + case LSM6DSV_125dps: + *val = LSM6DSV_125dps; + break; + + case LSM6DSV_250dps: + *val = LSM6DSV_250dps; + break; + + case LSM6DSV_500dps: + *val = LSM6DSV_500dps; + break; + + case LSM6DSV_1000dps: + *val = LSM6DSV_1000dps; + break; + + case LSM6DSV_2000dps: + *val = LSM6DSV_2000dps; + break; + + case LSM6DSV_4000dps: + *val = LSM6DSV_4000dps; + break; + + default: + *val = LSM6DSV_125dps; + break; + } + return ret; +} + +/** + * @brief Accelerometer full-scale selection.[set] + * + * @param ctx read / write interface definitions + * @param val 2g, 4g, 8g, 16g, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_xl_full_scale_set(stmdev_ctx_t *ctx, + lsm6dsv_xl_full_scale_t val) +{ + lsm6dsv_ctrl8_t ctrl8; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL8, (uint8_t *)&ctrl8, 1); + + if (ret == 0) + { + ctrl8.fs_xl = (uint8_t)val & 0x3U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL8, (uint8_t *)&ctrl8, 1); + } + + return ret; +} + +/** + * @brief Accelerometer full-scale selection.[get] + * + * @param ctx read / write interface definitions + * @param val 2g, 4g, 8g, 16g, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_xl_full_scale_get(stmdev_ctx_t *ctx, + lsm6dsv_xl_full_scale_t *val) +{ + lsm6dsv_ctrl8_t ctrl8; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL8, (uint8_t *)&ctrl8, 1); + + switch (ctrl8.fs_xl) + { + case LSM6DSV_2g: + *val = LSM6DSV_2g; + break; + + case LSM6DSV_4g: + *val = LSM6DSV_4g; + break; + + case LSM6DSV_8g: + *val = LSM6DSV_8g; + break; + + case LSM6DSV_16g: + *val = LSM6DSV_16g; + break; + + default: + *val = LSM6DSV_2g; + break; + } + return ret; +} + +/** + * @brief It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.[set] + * + * @param ctx read / write interface definitions + * @param val It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_xl_dual_channel_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_ctrl8_t ctrl8; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL8, (uint8_t *)&ctrl8, 1); + + if (ret == 0) + { + ctrl8.xl_dualc_en = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL8, (uint8_t *)&ctrl8, 1); + } + + return ret; +} + +/** + * @brief It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.[get] + * + * @param ctx read / write interface definitions + * @param val It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_xl_dual_channel_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_ctrl8_t ctrl8; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL8, (uint8_t *)&ctrl8, 1); + *val = ctrl8.xl_dualc_en; + + return ret; +} + +/** + * @brief Accelerometer self-test selection.[set] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_xl_self_test_set(stmdev_ctx_t *ctx, lsm6dsv_xl_self_test_t val) +{ + lsm6dsv_ctrl10_t ctrl10; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL10, (uint8_t *)&ctrl10, 1); + + if (ret == 0) + { + ctrl10.st_xl = (uint8_t)val & 0x3U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL10, (uint8_t *)&ctrl10, 1); + } + + return ret; +} + +/** + * @brief Accelerometer self-test selection.[get] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_xl_self_test_get(stmdev_ctx_t *ctx, lsm6dsv_xl_self_test_t *val) +{ + lsm6dsv_ctrl10_t ctrl10; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL10, (uint8_t *)&ctrl10, 1); + + switch (ctrl10.st_xl) + { + case LSM6DSV_XL_ST_DISABLE: + *val = LSM6DSV_XL_ST_DISABLE; + break; + + case LSM6DSV_XL_ST_POSITIVE: + *val = LSM6DSV_XL_ST_POSITIVE; + break; + + case LSM6DSV_XL_ST_NEGATIVE: + *val = LSM6DSV_XL_ST_NEGATIVE; + break; + + default: + *val = LSM6DSV_XL_ST_DISABLE; + break; + } + return ret; +} + +/** + * @brief Gyroscope self-test selection.[set] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_gy_self_test_set(stmdev_ctx_t *ctx, lsm6dsv_gy_self_test_t val) +{ + lsm6dsv_ctrl10_t ctrl10; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL10, (uint8_t *)&ctrl10, 1); + + if (ret == 0) + { + ctrl10.st_g = (uint8_t)val & 0x3U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL10, (uint8_t *)&ctrl10, 1); + } + + return ret; +} + +/** + * @brief Gyroscope self-test selection.[get] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_gy_self_test_get(stmdev_ctx_t *ctx, lsm6dsv_gy_self_test_t *val) +{ + lsm6dsv_ctrl10_t ctrl10; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL10, (uint8_t *)&ctrl10, 1); + + switch (ctrl10.st_g) + { + case LSM6DSV_GY_ST_DISABLE: + *val = LSM6DSV_GY_ST_DISABLE; + break; + + case LSM6DSV_GY_ST_POSITIVE: + *val = LSM6DSV_GY_ST_POSITIVE; + break; + + case LSM6DSV_GY_ST_NEGATIVE: + *val = LSM6DSV_GY_ST_NEGATIVE; + break; + + default: + *val = LSM6DSV_GY_ST_DISABLE; + break; + } + return ret; +} + +/** + * @brief SPI2 Accelerometer self-test selection.[set] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ois_xl_self_test_set(stmdev_ctx_t *ctx, + lsm6dsv_ois_xl_self_test_t val) +{ + lsm6dsv_spi2_int_ois_t spi2_int_ois; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); + + if (ret == 0) + { + spi2_int_ois.st_xl_ois = ((uint8_t)val & 0x3U); + ret = lsm6dsv_write_reg(ctx, LSM6DSV_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); + } + + return ret; +} + +/** + * @brief SPI2 Accelerometer self-test selection.[get] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ois_xl_self_test_get(stmdev_ctx_t *ctx, + lsm6dsv_ois_xl_self_test_t *val) +{ + lsm6dsv_spi2_int_ois_t spi2_int_ois; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); + + switch (spi2_int_ois.st_xl_ois) + { + case LSM6DSV_OIS_XL_ST_DISABLE: + *val = LSM6DSV_OIS_XL_ST_DISABLE; + break; + + case LSM6DSV_OIS_XL_ST_POSITIVE: + *val = LSM6DSV_OIS_XL_ST_POSITIVE; + break; + + case LSM6DSV_OIS_XL_ST_NEGATIVE: + *val = LSM6DSV_OIS_XL_ST_NEGATIVE; + break; + + default: + *val = LSM6DSV_OIS_XL_ST_DISABLE; + break; + } + return ret; +} + +/** + * @brief SPI2 Accelerometer self-test selection.[set] + * + * @param ctx read / write interface definitions + * @param val GY_ST_DISABLE, GY_ST_POSITIVE, GY_ST_NEGATIVE, LSM6DSV_OIS_GY_ST_CLAMP_POS, LSM6DSV_OIS_GY_ST_CLAMP_NEG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ois_gy_self_test_set(stmdev_ctx_t *ctx, + lsm6dsv_ois_gy_self_test_t val) +{ + lsm6dsv_spi2_int_ois_t spi2_int_ois; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); + + if (ret == 0) + { + spi2_int_ois.st_g_ois = ((uint8_t)val & 0x3U); + spi2_int_ois.st_ois_clampdis = ((uint8_t)val & 0x04U) >> 2; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); + } + + return ret; +} + +/** + * @brief SPI2 Accelerometer self-test selection.[get] + * + * @param ctx read / write interface definitions + * @param val GY_ST_DISABLE, GY_ST_POSITIVE, GY_ST_NEGATIVE, LSM6DSV_OIS_GY_ST_CLAMP_POS, LSM6DSV_OIS_GY_ST_CLAMP_NEG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ois_gy_self_test_get(stmdev_ctx_t *ctx, + lsm6dsv_ois_gy_self_test_t *val) +{ + lsm6dsv_spi2_int_ois_t spi2_int_ois; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); + + switch (spi2_int_ois.st_g_ois) + { + case LSM6DSV_OIS_GY_ST_DISABLE: + *val = LSM6DSV_OIS_GY_ST_DISABLE; + break; + + case LSM6DSV_OIS_GY_ST_POSITIVE: + *val = (spi2_int_ois.st_ois_clampdis == 1U) ? LSM6DSV_OIS_GY_ST_CLAMP_POS : LSM6DSV_OIS_GY_ST_POSITIVE; + break; + + case LSM6DSV_OIS_GY_ST_NEGATIVE: + *val = (spi2_int_ois.st_ois_clampdis == 1U) ? LSM6DSV_OIS_GY_ST_CLAMP_NEG : LSM6DSV_OIS_GY_ST_NEGATIVE; + break; + + default: + *val = LSM6DSV_OIS_GY_ST_DISABLE; + break; + } + return ret; +} + +/** + * @defgroup interrupt_pins + * @brief This section groups all the functions that manage + * interrupt pins + * @{ + * + */ + +/** + * @brief Select the signal that need to route on int1 pad[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val the signals to route on int1 pin. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsv_pin_int1_route_set(stmdev_ctx_t *ctx, + lsm6dsv_pin_int_route_t *val) +{ + lsm6dsv_int1_ctrl_t int1_ctrl; + lsm6dsv_md1_cfg_t md1_cfg; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + + int1_ctrl.int1_drdy_xl = val->drdy_xl; + int1_ctrl.int1_drdy_g = val->drdy_g; + int1_ctrl.int1_fifo_th = val->fifo_th; + int1_ctrl.int1_fifo_ovr = val->fifo_ovr; + int1_ctrl.int1_fifo_full = val->fifo_full; + int1_ctrl.int1_cnt_bdr = val->cnt_bdr; + + ret += lsm6dsv_write_reg(ctx, LSM6DSV_INT1_CTRL, (uint8_t *)&int1_ctrl, + 1); + + ret += lsm6dsv_read_reg(ctx, LSM6DSV_MD1_CFG, (uint8_t *)&md1_cfg, 1); + + md1_cfg.int1_shub = val->shub; + md1_cfg.int1_emb_func = val->emb_func; + md1_cfg.int1_6d = val->sixd; + md1_cfg.int1_single_tap = val->single_tap; + md1_cfg.int1_double_tap = val->double_tap; + md1_cfg.int1_wu = val->wakeup; + md1_cfg.int1_ff = val->freefall; + md1_cfg.int1_sleep_change = val->sleep_change; + + ret += lsm6dsv_write_reg(ctx, LSM6DSV_MD1_CFG, (uint8_t *)&md1_cfg, 1); + + return ret; +} + +/** + * @brief Select the signal that need to route on int1 pad.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val the signals that are routed on int1 pin.(ptr) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsv_pin_int1_route_get(stmdev_ctx_t *ctx, + lsm6dsv_pin_int_route_t *val) +{ + lsm6dsv_int1_ctrl_t int1_ctrl; + lsm6dsv_md1_cfg_t md1_cfg; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + + val->drdy_xl = int1_ctrl.int1_drdy_xl; + val->drdy_g = int1_ctrl.int1_drdy_g; + val->fifo_th = int1_ctrl.int1_fifo_th; + val->fifo_ovr = int1_ctrl.int1_fifo_ovr; + val->fifo_full = int1_ctrl.int1_fifo_full; + val->cnt_bdr = int1_ctrl.int1_cnt_bdr; + + ret += lsm6dsv_read_reg(ctx, LSM6DSV_MD1_CFG, (uint8_t *)&md1_cfg, 1); + + val->shub = md1_cfg.int1_shub; + val->emb_func = md1_cfg.int1_emb_func; + val->sixd = md1_cfg.int1_6d; + val->single_tap = md1_cfg.int1_single_tap; + val->double_tap = md1_cfg.int1_double_tap; + val->wakeup = md1_cfg.int1_wu; + val->freefall = md1_cfg.int1_ff; + val->sleep_change = md1_cfg.int1_sleep_change; + + return ret; +} + +/** + * @brief Select the signal that need to route on int2 pad[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val the signals to route on int1 pin. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsv_pin_int2_route_set(stmdev_ctx_t *ctx, + lsm6dsv_pin_int_route_t *val) +{ + lsm6dsv_int2_ctrl_t int2_ctrl; + lsm6dsv_md2_cfg_t md2_cfg; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + + int2_ctrl.int2_drdy_xl = val->drdy_xl; + int2_ctrl.int2_drdy_g = val->drdy_g; + int2_ctrl.int2_fifo_th = val->fifo_th; + int2_ctrl.int2_fifo_ovr = val->fifo_ovr; + int2_ctrl.int2_fifo_full = val->fifo_full; + int2_ctrl.int2_cnt_bdr = val->cnt_bdr; + int2_ctrl.int2_drdy_g_eis = val->drdy_g_eis; + int2_ctrl.int2_emb_func_endop = val->emb_func_endop; + + ret += lsm6dsv_write_reg(ctx, LSM6DSV_INT2_CTRL, (uint8_t *)&int2_ctrl, + 1); + + ret += lsm6dsv_read_reg(ctx, LSM6DSV_MD2_CFG, (uint8_t *)&md2_cfg, 1); + + md2_cfg.int2_timestamp = val->timestamp; + md2_cfg.int2_emb_func = val->emb_func; + md2_cfg.int2_6d = val->sixd; + md2_cfg.int2_single_tap = val->single_tap; + md2_cfg.int2_double_tap = val->double_tap; + md2_cfg.int2_wu = val->wakeup; + md2_cfg.int2_ff = val->freefall; + md2_cfg.int2_sleep_change = val->sleep_change; + + ret += lsm6dsv_write_reg(ctx, LSM6DSV_MD2_CFG, (uint8_t *)&md2_cfg, 1); + + return ret; +} + +/** + * @brief Select the signal that need to route on int2 pad.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val the signals that are routed on int1 pin.(ptr) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsv_pin_int2_route_get(stmdev_ctx_t *ctx, + lsm6dsv_pin_int_route_t *val) +{ + lsm6dsv_int2_ctrl_t int2_ctrl; + lsm6dsv_md2_cfg_t md2_cfg; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + + val->drdy_xl = int2_ctrl.int2_drdy_xl; + val->drdy_g = int2_ctrl.int2_drdy_g; + val->fifo_th = int2_ctrl.int2_fifo_th; + val->fifo_ovr = int2_ctrl.int2_fifo_ovr; + val->fifo_full = int2_ctrl.int2_fifo_full; + val->cnt_bdr = int2_ctrl.int2_cnt_bdr; + val->drdy_g_eis = int2_ctrl.int2_drdy_g_eis; + val->emb_func_endop = int2_ctrl.int2_emb_func_endop; + + ret += lsm6dsv_read_reg(ctx, LSM6DSV_MD2_CFG, (uint8_t *)&md2_cfg, 1); + + val->timestamp = md2_cfg.int2_timestamp; + val->emb_func = md2_cfg.int2_emb_func; + val->sixd = md2_cfg.int2_6d; + val->single_tap = md2_cfg.int2_single_tap; + val->double_tap = md2_cfg.int2_double_tap; + val->wakeup = md2_cfg.int2_wu; + val->freefall = md2_cfg.int2_ff; + val->sleep_change = md2_cfg.int2_sleep_change; + + return ret; +} + +/** + * @} + * + */ + +/** + * @brief Get the status of all the interrupt sources.[get] + * + * @param ctx read / write interface definitions + * @param val Get the status of all the interrupt sources. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_all_sources_get(stmdev_ctx_t *ctx, lsm6dsv_all_sources_t *val) +{ + lsm6dsv_emb_func_status_mainpage_t emb_func_status_mainpage; + lsm6dsv_emb_func_exec_status_t emb_func_exec_status; + lsm6dsv_fsm_status_mainpage_t fsm_status_mainpage; + lsm6dsv_functions_enable_t functions_enable; + lsm6dsv_emb_func_src_t emb_func_src; + lsm6dsv_fifo_status2_t fifo_status2; + lsm6dsv_all_int_src_t all_int_src; + lsm6dsv_wake_up_src_t wake_up_src; + lsm6dsv_status_reg_t status_reg; + lsm6dsv_d6d_src_t d6d_src; + lsm6dsv_tap_src_t tap_src; + lsm6dsv_ui_status_reg_ois_t status_reg_ois; + lsm6dsv_status_master_t status_shub; + uint8_t buff[7]; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret == 0) + { + functions_enable.dis_rst_lir_all_int = PROPERTY_ENABLE; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_STATUS1, (uint8_t *)&buff, 4); + } + bytecpy((uint8_t *)&fifo_status2, &buff[1]); + bytecpy((uint8_t *)&all_int_src, &buff[2]); + bytecpy((uint8_t *)&status_reg, &buff[3]); + + val->fifo_ovr = fifo_status2.fifo_ovr_ia; + val->fifo_bdr = fifo_status2.counter_bdr_ia; + val->fifo_full = fifo_status2.fifo_full_ia; + val->fifo_th = fifo_status2.fifo_wtm_ia; + + val->free_fall = all_int_src.ff_ia; + val->wake_up = all_int_src.wu_ia; + val->six_d = all_int_src.d6d_ia; + + val->drdy_xl = status_reg.xlda; + val->drdy_gy = status_reg.gda; + val->drdy_temp = status_reg.tda; + val->drdy_eis = status_reg.gda_eis; + val->drdy_ois = status_reg.ois_drdy; + val->timestamp = status_reg.timestamp_endcount; + + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + if (ret == 0) + { + functions_enable.dis_rst_lir_all_int = PROPERTY_DISABLE; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_STATUS_REG_OIS, (uint8_t *)&buff, 7); + } + + bytecpy((uint8_t *)&status_reg_ois, &buff[0]); + bytecpy((uint8_t *)&wake_up_src, &buff[1]); + bytecpy((uint8_t *)&tap_src, &buff[2]); + bytecpy((uint8_t *)&d6d_src, &buff[3]); + bytecpy((uint8_t *)&emb_func_status_mainpage, &buff[4]); + bytecpy((uint8_t *)&fsm_status_mainpage, &buff[5]); + + val->gy_settling = status_reg_ois.gyro_settling; + val->sleep_change = wake_up_src.sleep_change_ia; + val->wake_up_x = wake_up_src.x_wu; + val->wake_up_y = wake_up_src.y_wu; + val->wake_up_z = wake_up_src.z_wu; + val->sleep_state = wake_up_src.sleep_state; + + val->tap_x = tap_src.x_tap; + val->tap_y = tap_src.y_tap; + val->tap_z = tap_src.z_tap; + val->tap_sign = tap_src.tap_sign; + val->double_tap = tap_src.double_tap; + val->single_tap = tap_src.single_tap; + + val->six_d_zl = d6d_src.zl; + val->six_d_zh = d6d_src.zh; + val->six_d_yl = d6d_src.yl; + val->six_d_yh = d6d_src.yh; + val->six_d_xl = d6d_src.xl; + val->six_d_xh = d6d_src.xh; + + val->step_detector = emb_func_status_mainpage.is_step_det; + val->tilt = emb_func_status_mainpage.is_tilt; + val->sig_mot = emb_func_status_mainpage.is_sigmot; + val->fsm_lc = emb_func_status_mainpage.is_fsm_lc; + + val->fsm1 = fsm_status_mainpage.is_fsm1; + val->fsm2 = fsm_status_mainpage.is_fsm2; + val->fsm3 = fsm_status_mainpage.is_fsm3; + val->fsm4 = fsm_status_mainpage.is_fsm4; + val->fsm5 = fsm_status_mainpage.is_fsm5; + val->fsm6 = fsm_status_mainpage.is_fsm6; + val->fsm7 = fsm_status_mainpage.is_fsm7; + val->fsm8 = fsm_status_mainpage.is_fsm8; + + + if (ret == 0) + { + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); + } + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status, 1); + } + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + val->emb_func_stand_by = emb_func_exec_status.emb_func_endop; + val->emb_func_time_exceed = emb_func_exec_status.emb_func_exec_ovr; + val->step_count_inc = emb_func_src.stepcounter_bit_set; + val->step_count_overflow = emb_func_src.step_overflow; + val->step_on_delta_time = emb_func_src.step_count_delta_ia; + + val->step_detector = emb_func_src.step_detected; + + /* sensor hub */ + if (ret == 0) + { + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + } + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_STATUS_MASTER, (uint8_t *)&status_shub, 1); + } + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + val->sh_endop = status_shub.sens_hub_endop; + val->sh_wr_once = status_shub.wr_once_done; + val->sh_slave3_nack = status_shub.slave3_nack; + val->sh_slave2_nack = status_shub.slave2_nack; + val->sh_slave1_nack = status_shub.slave1_nack; + val->sh_slave0_nack = status_shub.slave0_nack; + + return ret; +} + +int32_t lsm6dsv_flag_data_ready_get(stmdev_ctx_t *ctx, + lsm6dsv_data_ready_t *val) +{ + lsm6dsv_status_reg_t status; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_STATUS_REG, (uint8_t *)&status, 1); + val->drdy_xl = status.xlda; + val->drdy_gy = status.gda; + val->drdy_temp = status.tda; + + return ret; +} + +/** + * @brief Mask status bit reset[set] + * + * @param ctx read / write interface definitions + * @param val Mask to prevent status bit being reset + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_int_ack_mask_set(stmdev_ctx_t *ctx, uint8_t val) +{ + int32_t ret; + + ret = lsm6dsv_write_reg(ctx, LSM6DSV_INT_ACK_MASK, &val, 1); + + return ret; +} + +/** + * @brief Mask status bit reset[get] + * + * @param ctx read / write interface definitions + * @param val Mask to prevent status bit being reset + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_int_ack_mask_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_INT_ACK_MASK, val, 1); + + return ret; +} + +/** + * @brief Temperature data output register[get] + * + * @param ctx read / write interface definitions + * @param val Temperature data output register + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_OUT_TEMP_L, &buff[0], 2); + *val = (int16_t)buff[1]; + *val = (*val * 256) + (int16_t)buff[0]; + + return ret; +} + +/** + * @brief Angular rate sensor.[get] + * + * @param ctx read / write interface definitions + * @param val Angular rate sensor. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_OUTX_L_G, &buff[0], 6); + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Angular rate sensor.[get] + * + * @param ctx read / write interface definitions + * @param val OIS Angular rate sensor (thru SPI2). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ois_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_SPI2_OUTX_L_G_OIS, &buff[0], 6); + val[0] = (int16_t)buff[1]; + val[0] = (*val * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (*val * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (*val * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Angular rate sensor for OIS gyro or the EIS gyro channel.[get] + * + * @param ctx read / write interface definitions + * @param val Angular rate sensor for OIS gyro or the EIS gyro channel. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ois_eis_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_OUTX_L_G_OIS_EIS, &buff[0], 6); + val[0] = (int16_t)buff[1]; + val[0] = (*val * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (*val * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (*val * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Linear acceleration sensor.[get] + * + * @param ctx read / write interface definitions + * @param val Linear acceleration sensor. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_OUTX_L_A, &buff[0], 6); + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Linear acceleration sensor for Dual channel mode.[get] + * + * @param ctx read / write interface definitions + * @param val Linear acceleration sensor or Dual channel mode. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_dual_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_OUTX_L_A_OIS_DUALC, &buff[0], 6); + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement.[get] + * + * @param ctx read / write interface definitions + * @param val Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_odr_cal_reg_get(stmdev_ctx_t *ctx, int8_t *val) +{ + lsm6dsv_internal_freq_t internal_freq; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_INTERNAL_FREQ, (uint8_t *)&internal_freq, 1); + *val = (int8_t)internal_freq.freq_fine; + + return ret; +} + +/** + * @brief Write buffer in a page.[set] + * + * @param ctx read / write interface definitions + * @param val Write buffer in a page. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, + uint8_t *buf, uint8_t len) +{ + lsm6dsv_page_address_t page_address; + lsm6dsv_page_sel_t page_sel; + lsm6dsv_page_rw_t page_rw; + uint8_t msb; + uint8_t lsb; + int32_t ret; + uint8_t i ; + + msb = ((uint8_t)(address >> 8) & 0x0FU); + lsb = (uint8_t)address & 0xFFU; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); + + /* set page write */ + ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_ENABLE; + ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1); + + /* select page */ + ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1); + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1); + + /* set page addr */ + page_address.page_addr = lsb; + ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + + for (i = 0; ((i < len) && (ret == 0)); i++) + { + ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_VALUE, &buf[i], 1); + lsb++; + + /* Check if page wrap */ + if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) + { + msb++; + ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1); + + if (ret == 0) + { + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1); + } + } + } + + page_sel.page_sel = 0; + page_sel.not_used0 = 1;// Default value + ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1); + + /* unset page write */ + ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1); + + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @defgroup Common + * @brief This section groups common useful functions. + * @{/ + * + */ + +/** + * @brief Read buffer in a page.[set] + * + * @param ctx read / write interface definitions + * @param val Write buffer in a page. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, + uint8_t len) +{ + lsm6dsv_page_address_t page_address; + lsm6dsv_page_sel_t page_sel; + lsm6dsv_page_rw_t page_rw; + uint8_t msb; + uint8_t lsb; + int32_t ret; + uint8_t i ; + + msb = ((uint8_t)(address >> 8) & 0x0FU); + lsb = (uint8_t)address & 0xFFU; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); + + /* set page write */ + ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_ENABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1); + + /* select page */ + ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1); + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1); + + /* set page addr */ + page_address.page_addr = lsb; + ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + + for (i = 0; ((i < len) && (ret == 0)); i++) + { + ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_VALUE, &buf[i], 1); + lsb++; + + /* Check if page wrap */ + if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) + { + msb++; + ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1); + + if (ret == 0) + { + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1); + } + } + } + + page_sel.page_sel = 0; + page_sel.not_used0 = 1;// Default value + ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1); + + /* unset page write */ + ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1); + + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable debug mode for embedded functions [set] + * + * @param ctx read / write interface definitions + * @param val 0, 1 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_emb_function_dbg_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_ctrl10_t ctrl10; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL10, (uint8_t *)&ctrl10, 1); + + if (ret == 0) + { + ctrl10.emb_func_debug = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL10, (uint8_t *)&ctrl10, 1); + } + + return ret; +} + +/** + * @brief Enable debug mode for embedded functions [get] + * + * @param ctx read / write interface definitions + * @param val 0, 1 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_emb_function_dbg_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_ctrl10_t ctrl10; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL10, (uint8_t *)&ctrl10, 1); + + if (ret == 0) + { + *val = ctrl10.emb_func_debug; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Data ENable (DEN) + * @brief This section groups all the functions concerning + * DEN functionality. + * @{ + * + */ + +/** + * @brief It changes the polarity of INT2 pin input trigger for data enable (DEN) or embedded functions.[set] + * + * @param ctx read / write interface definitions + * @param val DEN_ACT_LOW, DEN_ACT_HIGH, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_den_polarity_set(stmdev_ctx_t *ctx, lsm6dsv_den_polarity_t val) +{ + lsm6dsv_ctrl4_t ctrl4; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1); + + if (ret == 0) + { + ctrl4.int2_in_lh = (uint8_t)val & 0x1U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1); + } + + return ret; +} + +/** + * @brief It changes the polarity of INT2 pin input trigger for data enable (DEN) or embedded functions.[get] + * + * @param ctx read / write interface definitions + * @param val DEN_ACT_LOW, DEN_ACT_HIGH, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_den_polarity_get(stmdev_ctx_t *ctx, lsm6dsv_den_polarity_t *val) +{ + lsm6dsv_ctrl4_t ctrl4; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1); + switch (ctrl4.int2_in_lh) + { + case LSM6DSV_DEN_ACT_LOW: + *val = LSM6DSV_DEN_ACT_LOW; + break; + + case LSM6DSV_DEN_ACT_HIGH: + *val = LSM6DSV_DEN_ACT_HIGH; + break; + + default: + *val = LSM6DSV_DEN_ACT_LOW; + break; + } + return ret; +} + +/** + * @brief Data ENable (DEN) configuration.[set] + * + * @param ctx read / write interface definitions + * @param val Data ENable (DEN) configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_den_conf_set(stmdev_ctx_t *ctx, lsm6dsv_den_conf_t val) +{ + lsm6dsv_den_t den; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_DEN, (uint8_t *)&den, 1); + if (ret == 0) + { + den.den_z = val.den_z; + den.den_y = val.den_y; + den.den_x = val.den_x; + + den.lvl2_en = (uint8_t)val.mode & 0x1U; + den.lvl1_en = ((uint8_t)val.mode & 0x2U) >> 1; + + if (val.stamp_in_gy_data == PROPERTY_ENABLE && val.stamp_in_xl_data == PROPERTY_ENABLE) + { + den.den_xl_g = PROPERTY_DISABLE; + den.den_xl_en = PROPERTY_ENABLE; + } + else if (val.stamp_in_gy_data == PROPERTY_ENABLE && val.stamp_in_xl_data == PROPERTY_DISABLE) + { + den.den_xl_g = PROPERTY_DISABLE; + den.den_xl_en = PROPERTY_DISABLE; + } + else if (val.stamp_in_gy_data == PROPERTY_DISABLE && val.stamp_in_xl_data == PROPERTY_ENABLE) + { + den.den_xl_g = PROPERTY_ENABLE; + den.den_xl_en = PROPERTY_DISABLE; + } + else + { + den.den_xl_g = PROPERTY_DISABLE; + den.den_xl_en = PROPERTY_DISABLE; + den.den_z = PROPERTY_DISABLE; + den.den_y = PROPERTY_DISABLE; + den.den_x = PROPERTY_DISABLE; + den.lvl2_en = PROPERTY_DISABLE; + den.lvl1_en = PROPERTY_DISABLE; + } + + ret = lsm6dsv_write_reg(ctx, LSM6DSV_DEN, (uint8_t *)&den, 1); + } + + return ret; +} + + +/** + * @brief Data ENable (DEN) configuration.[get] + * + * @param ctx read / write interface definitions + * @param val Data ENable (DEN) configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_den_conf_get(stmdev_ctx_t *ctx, lsm6dsv_den_conf_t *val) +{ + lsm6dsv_den_t den; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_DEN, (uint8_t *)&den, 1); + + val->den_z = den.den_z; + val->den_y = den.den_y; + val->den_x = den.den_x; + + if ((den.den_z | den.den_z | den.den_z) == PROPERTY_ENABLE) + { + if (den.den_xl_g == PROPERTY_DISABLE && den.den_xl_en == PROPERTY_ENABLE) + { + val->stamp_in_gy_data = PROPERTY_ENABLE; + val->stamp_in_xl_data = PROPERTY_ENABLE; + } + else if (den.den_xl_g == PROPERTY_DISABLE && den.den_xl_en == PROPERTY_DISABLE) + { + val->stamp_in_gy_data = PROPERTY_ENABLE; + val->stamp_in_xl_data = PROPERTY_DISABLE; + } + else // ( (den.den_xl_g & !den.den_xl_en) == PROPERTY_ENABLE ) + { + val->stamp_in_gy_data = PROPERTY_DISABLE; + val->stamp_in_xl_data = PROPERTY_ENABLE; + } + } + else + { + val->stamp_in_gy_data = PROPERTY_DISABLE; + val->stamp_in_xl_data = PROPERTY_DISABLE; + } + + switch ((den.lvl1_en << 1) + den.lvl2_en) + { + case LEVEL_TRIGGER: + val->mode = LEVEL_TRIGGER; + break; + + case LEVEL_LATCHED: + val->mode = LEVEL_LATCHED; + break; + + default: + val->mode = DEN_NOT_DEFINED; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Electronic Image Stabilization (EIS) + * @brief Electronic Image Stabilization (EIS) + * @{/ + * + */ + +/** + * @brief Gyroscope full-scale selection for EIS channel. WARNING: 4000dps will be available only if also User Interface chain is set to 4000dps[set] + * + * @param ctx read / write interface definitions + * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_eis_gy_full_scale_set(stmdev_ctx_t *ctx, + lsm6dsv_eis_gy_full_scale_t val) +{ + lsm6dsv_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + + if (ret == 0) + { + ctrl_eis.fs_g_eis = (uint8_t)val & 0x7U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + } + + return ret; +} + +/** + * @brief Gyroscope full-scale selection for EIS channel. WARNING: 4000dps will be available only if also User Interface chain is set to 4000dps[get] + * + * @param ctx read / write interface definitions + * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_eis_gy_full_scale_get(stmdev_ctx_t *ctx, + lsm6dsv_eis_gy_full_scale_t *val) +{ + lsm6dsv_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + + switch (ctrl_eis.fs_g_eis) + { + case LSM6DSV_EIS_125dps: + *val = LSM6DSV_EIS_125dps; + break; + + case LSM6DSV_EIS_250dps: + *val = LSM6DSV_EIS_250dps; + break; + + case LSM6DSV_EIS_500dps: + *val = LSM6DSV_EIS_500dps; + break; + + case LSM6DSV_EIS_1000dps: + *val = LSM6DSV_EIS_1000dps; + break; + + case LSM6DSV_EIS_2000dps: + *val = LSM6DSV_EIS_2000dps; + break; + + default: + *val = LSM6DSV_EIS_125dps; + break; + } + return ret; +} + +/** + * @brief Enables routing of gyroscope EIS outputs on SPI2 (OIS interface). The gyroscope data on SPI2 (OIS interface) cannot be read from User Interface (UI).[set] + * + * @param ctx read / write interface definitions + * @param val Enables routing of gyroscope EIS outputs on SPI2 (OIS interface). The gyroscope data on SPI2 (OIS interface) cannot be read from User Interface (UI). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_eis_gy_on_spi2_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + + if (ret == 0) + { + ctrl_eis.g_eis_on_g_ois_out_reg = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + } + + return ret; +} + +/** + * @brief Enables routing of gyroscope EIS outputs on SPI2 (OIS interface). The gyroscope data on SPI2 (OIS interface) cannot be read from User Interface (UI).[get] + * + * @param ctx read / write interface definitions + * @param val Enables routing of gyroscope EIS outputs on SPI2 (OIS interface). The gyroscope data on SPI2 (OIS interface) cannot be read from User Interface (UI). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_eis_gy_on_spi2_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + *val = ctrl_eis.g_eis_on_g_ois_out_reg; + + return ret; +} + +/** + * @brief Enables and selects the ODR of the gyroscope EIS channel.[set] + * + * @param ctx read / write interface definitions + * @param val EIS_1920Hz, EIS_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_gy_eis_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv_gy_eis_data_rate_t val) +{ + lsm6dsv_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + + if (ret == 0) + { + ctrl_eis.odr_g_eis = (uint8_t)val & 0x03U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + } + + return ret; +} + +/** + * @brief Enables and selects the ODR of the gyroscope EIS channel.[get] + * + * @param ctx read / write interface definitions + * @param val EIS_1920Hz, EIS_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_gy_eis_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv_gy_eis_data_rate_t *val) +{ + lsm6dsv_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + + switch (ctrl_eis.odr_g_eis) + { + case LSM6DSV_EIS_ODR_OFF: + *val = LSM6DSV_EIS_ODR_OFF; + break; + + case LSM6DSV_EIS_1920Hz: + *val = LSM6DSV_EIS_1920Hz; + break; + + case LSM6DSV_EIS_960Hz: + *val = LSM6DSV_EIS_960Hz; + break; + + default: + *val = LSM6DSV_EIS_1920Hz; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup FIFO + * @brief This section group all the functions concerning the FIFO usage + * @{ + * + */ + +/** + * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[set] + * + * @param ctx read / write interface definitions + * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_fifo_ctrl1_t fifo_ctrl1; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + + if (ret == 0) + { + fifo_ctrl1.wtm = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + } + + return ret; +} + +/** + * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[get] + * + * @param ctx read / write interface definitions + * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_fifo_ctrl1_t fifo_ctrl1; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + *val = fifo_ctrl1.wtm; + + return ret; +} + +/** + * @brief When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.[set] + * + * @param ctx read / write interface definitions + * @param val When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_xl_dual_fsm_batch_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.xl_dualc_batch_from_fsm = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.[get] + * + * @param ctx read / write interface definitions + * @param val When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_xl_dual_fsm_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + *val = fifo_ctrl2.xl_dualc_batch_from_fsm; + + + return ret; +} + +/** + * @brief It configures the compression algorithm to write non-compressed data at each rate.[set] + * + * @param ctx read / write interface definitions + * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_compress_algo_set(stmdev_ctx_t *ctx, + lsm6dsv_fifo_compress_algo_t val) +{ + lsm6dsv_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.uncompr_rate = (uint8_t)val & 0x03U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief It configures the compression algorithm to write non-compressed data at each rate.[get] + * + * @param ctx read / write interface definitions + * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_compress_algo_get(stmdev_ctx_t *ctx, + lsm6dsv_fifo_compress_algo_t *val) +{ + lsm6dsv_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + switch (fifo_ctrl2.uncompr_rate) + { + case LSM6DSV_CMP_DISABLE: + *val = LSM6DSV_CMP_DISABLE; + break; + + case LSM6DSV_CMP_8_TO_1: + *val = LSM6DSV_CMP_8_TO_1; + break; + + case LSM6DSV_CMP_16_TO_1: + *val = LSM6DSV_CMP_16_TO_1; + break; + + case LSM6DSV_CMP_32_TO_1: + *val = LSM6DSV_CMP_32_TO_1; + break; + + default: + *val = LSM6DSV_CMP_DISABLE; + break; + } + return ret; +} + +/** + * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set] + * + * @param ctx read / write interface definitions + * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.odr_chg_en = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get] + * + * @param ctx read / write interface definitions + * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + *val = fifo_ctrl2.odr_chg_en; + + return ret; +} + +/** + * @brief Enables/Disables compression algorithm runtime.[set] + * + * @param ctx read / write interface definitions + * @param val Enables/Disables compression algorithm runtime. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_compress_algo_real_time_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_emb_func_en_b_t emb_func_en_b; + lsm6dsv_fifo_ctrl2_t fifo_ctrl2; + + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.fifo_compr_rt_en = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + if (ret == 0) + { + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); + } + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + emb_func_en_b.fifo_compr_en = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enables/Disables compression algorithm runtime.[get] + * + * @param ctx read / write interface definitions + * @param val Enables/Disables compression algorithm runtime. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_compress_algo_real_time_get(stmdev_ctx_t *ctx, + uint8_t *val) +{ + lsm6dsv_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + + *val = fifo_ctrl2.fifo_compr_rt_en; + + return ret; +} + +/** + * @brief Sensing chain FIFO stop values memorization at threshold level.[set] + * + * @param ctx read / write interface definitions + * @param val Sensing chain FIFO stop values memorization at threshold level. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.stop_on_wtm = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief Sensing chain FIFO stop values memorization at threshold level.[get] + * + * @param ctx read / write interface definitions + * @param val Sensing chain FIFO stop values memorization at threshold level. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + *val = fifo_ctrl2.stop_on_wtm; + + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[set] + * + * @param ctx read / write interface definitions + * @param val XL_NOT_BATCHED, XL_BATCHED_AT_1Hz875, XL_BATCHED_AT_7Hz5, XL_BATCHED_AT_15Hz, XL_BATCHED_AT_30Hz, XL_BATCHED_AT_60Hz, XL_BATCHED_AT_120Hz, XL_BATCHED_AT_240Hz, XL_BATCHED_AT_480Hz, XL_BATCHED_AT_960Hz, XL_BATCHED_AT_1920Hz, XL_BATCHED_AT_3840Hz, XL_BATCHED_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_xl_batch_set(stmdev_ctx_t *ctx, + lsm6dsv_fifo_xl_batch_t val) +{ + lsm6dsv_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret == 0) + { + fifo_ctrl3.bdr_xl = (uint8_t)val & 0xFu; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + } + + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[get] + * + * @param ctx read / write interface definitions + * @param val XL_NOT_BATCHED, XL_BATCHED_AT_1Hz875, XL_BATCHED_AT_7Hz5, XL_BATCHED_AT_15Hz, XL_BATCHED_AT_30Hz, XL_BATCHED_AT_60Hz, XL_BATCHED_AT_120Hz, XL_BATCHED_AT_240Hz, XL_BATCHED_AT_480Hz, XL_BATCHED_AT_960Hz, XL_BATCHED_AT_1920Hz, XL_BATCHED_AT_3840Hz, XL_BATCHED_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_xl_batch_get(stmdev_ctx_t *ctx, + lsm6dsv_fifo_xl_batch_t *val) +{ + lsm6dsv_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + switch (fifo_ctrl3.bdr_xl) + { + case LSM6DSV_XL_NOT_BATCHED: + *val = LSM6DSV_XL_NOT_BATCHED; + break; + + case LSM6DSV_XL_BATCHED_AT_1Hz875: + *val = LSM6DSV_XL_BATCHED_AT_1Hz875; + break; + + case LSM6DSV_XL_BATCHED_AT_7Hz5: + *val = LSM6DSV_XL_BATCHED_AT_7Hz5; + break; + + case LSM6DSV_XL_BATCHED_AT_15Hz: + *val = LSM6DSV_XL_BATCHED_AT_15Hz; + break; + + case LSM6DSV_XL_BATCHED_AT_30Hz: + *val = LSM6DSV_XL_BATCHED_AT_30Hz; + break; + + case LSM6DSV_XL_BATCHED_AT_60Hz: + *val = LSM6DSV_XL_BATCHED_AT_60Hz; + break; + + case LSM6DSV_XL_BATCHED_AT_120Hz: + *val = LSM6DSV_XL_BATCHED_AT_120Hz; + break; + + case LSM6DSV_XL_BATCHED_AT_240Hz: + *val = LSM6DSV_XL_BATCHED_AT_240Hz; + break; + + case LSM6DSV_XL_BATCHED_AT_480Hz: + *val = LSM6DSV_XL_BATCHED_AT_480Hz; + break; + + case LSM6DSV_XL_BATCHED_AT_960Hz: + *val = LSM6DSV_XL_BATCHED_AT_960Hz; + break; + + case LSM6DSV_XL_BATCHED_AT_1920Hz: + *val = LSM6DSV_XL_BATCHED_AT_1920Hz; + break; + + case LSM6DSV_XL_BATCHED_AT_3840Hz: + *val = LSM6DSV_XL_BATCHED_AT_3840Hz; + break; + + case LSM6DSV_XL_BATCHED_AT_7680Hz: + *val = LSM6DSV_XL_BATCHED_AT_7680Hz; + break; + + default: + *val = LSM6DSV_XL_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[set] + * + * @param ctx read / write interface definitions + * @param val GY_NOT_BATCHED, GY_BATCHED_AT_1Hz875, GY_BATCHED_AT_7Hz5, GY_BATCHED_AT_15Hz, GY_BATCHED_AT_30Hz, GY_BATCHED_AT_60Hz, GY_BATCHED_AT_120Hz, GY_BATCHED_AT_240Hz, GY_BATCHED_AT_480Hz, GY_BATCHED_AT_960Hz, GY_BATCHED_AT_1920Hz, GY_BATCHED_AT_3840Hz, GY_BATCHED_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_gy_batch_set(stmdev_ctx_t *ctx, + lsm6dsv_fifo_gy_batch_t val) +{ + lsm6dsv_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret == 0) + { + fifo_ctrl3.bdr_gy = (uint8_t)val & 0x0Fu; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + } + + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[get] + * + * @param ctx read / write interface definitions + * @param val GY_NOT_BATCHED, GY_BATCHED_AT_1Hz875, GY_BATCHED_AT_7Hz5, GY_BATCHED_AT_15Hz, GY_BATCHED_AT_30Hz, GY_BATCHED_AT_60Hz, GY_BATCHED_AT_120Hz, GY_BATCHED_AT_240Hz, GY_BATCHED_AT_480Hz, GY_BATCHED_AT_960Hz, GY_BATCHED_AT_1920Hz, GY_BATCHED_AT_3840Hz, GY_BATCHED_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_gy_batch_get(stmdev_ctx_t *ctx, + lsm6dsv_fifo_gy_batch_t *val) +{ + lsm6dsv_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + switch (fifo_ctrl3.bdr_gy) + { + case LSM6DSV_GY_NOT_BATCHED: + *val = LSM6DSV_GY_NOT_BATCHED; + break; + + case LSM6DSV_GY_BATCHED_AT_1Hz875: + *val = LSM6DSV_GY_BATCHED_AT_1Hz875; + break; + + case LSM6DSV_GY_BATCHED_AT_7Hz5: + *val = LSM6DSV_GY_BATCHED_AT_7Hz5; + break; + + case LSM6DSV_GY_BATCHED_AT_15Hz: + *val = LSM6DSV_GY_BATCHED_AT_15Hz; + break; + + case LSM6DSV_GY_BATCHED_AT_30Hz: + *val = LSM6DSV_GY_BATCHED_AT_30Hz; + break; + + case LSM6DSV_GY_BATCHED_AT_60Hz: + *val = LSM6DSV_GY_BATCHED_AT_60Hz; + break; + + case LSM6DSV_GY_BATCHED_AT_120Hz: + *val = LSM6DSV_GY_BATCHED_AT_120Hz; + break; + + case LSM6DSV_GY_BATCHED_AT_240Hz: + *val = LSM6DSV_GY_BATCHED_AT_240Hz; + break; + + case LSM6DSV_GY_BATCHED_AT_480Hz: + *val = LSM6DSV_GY_BATCHED_AT_480Hz; + break; + + case LSM6DSV_GY_BATCHED_AT_960Hz: + *val = LSM6DSV_GY_BATCHED_AT_960Hz; + break; + + case LSM6DSV_GY_BATCHED_AT_1920Hz: + *val = LSM6DSV_GY_BATCHED_AT_1920Hz; + break; + + case LSM6DSV_GY_BATCHED_AT_3840Hz: + *val = LSM6DSV_GY_BATCHED_AT_3840Hz; + break; + + case LSM6DSV_GY_BATCHED_AT_7680Hz: + *val = LSM6DSV_GY_BATCHED_AT_7680Hz; + break; + + default: + *val = LSM6DSV_GY_NOT_BATCHED; + break; + } + return ret; +} + + +/** + * @brief FIFO mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val BYPASS_MODE, FIFO_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_mode_set(stmdev_ctx_t *ctx, lsm6dsv_fifo_mode_t val) +{ + lsm6dsv_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.fifo_mode = (uint8_t)val & 0x07U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief FIFO mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val BYPASS_MODE, FIFO_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_mode_get(stmdev_ctx_t *ctx, lsm6dsv_fifo_mode_t *val) +{ + lsm6dsv_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + switch (fifo_ctrl4.fifo_mode) + { + case LSM6DSV_BYPASS_MODE: + *val = LSM6DSV_BYPASS_MODE; + break; + + case LSM6DSV_FIFO_MODE: + *val = LSM6DSV_FIFO_MODE; + break; + + case LSM6DSV_STREAM_WTM_TO_FULL_MODE: + *val = LSM6DSV_STREAM_WTM_TO_FULL_MODE; + break; + + case LSM6DSV_STREAM_TO_FIFO_MODE: + *val = LSM6DSV_STREAM_TO_FIFO_MODE; + break; + + case LSM6DSV_BYPASS_TO_STREAM_MODE: + *val = LSM6DSV_BYPASS_TO_STREAM_MODE; + break; + + case LSM6DSV_STREAM_MODE: + *val = LSM6DSV_STREAM_MODE; + break; + + case LSM6DSV_BYPASS_TO_FIFO_MODE: + *val = LSM6DSV_BYPASS_TO_FIFO_MODE; + break; + + default: + *val = LSM6DSV_BYPASS_MODE; + break; + } + return ret; +} + +/** + * @brief Enables FIFO batching of EIS gyroscope output values.[set] + * + * @param ctx read / write interface definitions + * @param val Enables FIFO batching of EIS gyroscope output values. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_gy_eis_batch_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.g_eis_fifo_en = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief Enables FIFO batching of EIS gyroscope output values.[get] + * + * @param ctx read / write interface definitions + * @param val Enables FIFO batching of EIS gyroscope output values. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_gy_eis_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + *val = fifo_ctrl4.g_eis_fifo_en; + + return ret; +} + +/** + * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[set] + * + * @param ctx read / write interface definitions + * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_temp_batch_set(stmdev_ctx_t *ctx, + lsm6dsv_fifo_temp_batch_t val) +{ + lsm6dsv_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.odr_t_batch = (uint8_t)val & 0x03U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[get] + * + * @param ctx read / write interface definitions + * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_temp_batch_get(stmdev_ctx_t *ctx, + lsm6dsv_fifo_temp_batch_t *val) +{ + lsm6dsv_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + switch (fifo_ctrl4.odr_t_batch) + { + case LSM6DSV_TEMP_NOT_BATCHED: + *val = LSM6DSV_TEMP_NOT_BATCHED; + break; + + case LSM6DSV_TEMP_BATCHED_AT_1Hz875: + *val = LSM6DSV_TEMP_BATCHED_AT_1Hz875; + break; + + case LSM6DSV_TEMP_BATCHED_AT_15Hz: + *val = LSM6DSV_TEMP_BATCHED_AT_15Hz; + break; + + case LSM6DSV_TEMP_BATCHED_AT_60Hz: + *val = LSM6DSV_TEMP_BATCHED_AT_60Hz; + break; + + default: + *val = LSM6DSV_TEMP_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[set] + * + * @param ctx read / write interface definitions + * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_timestamp_batch_set(stmdev_ctx_t *ctx, + lsm6dsv_fifo_timestamp_batch_t val) +{ + lsm6dsv_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.dec_ts_batch = (uint8_t)val & 0x03U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[get] + * + * @param ctx read / write interface definitions + * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_timestamp_batch_get(stmdev_ctx_t *ctx, + lsm6dsv_fifo_timestamp_batch_t *val) +{ + lsm6dsv_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + switch (fifo_ctrl4.dec_ts_batch) + { + case LSM6DSV_TMSTMP_NOT_BATCHED: + *val = LSM6DSV_TMSTMP_NOT_BATCHED; + break; + + case LSM6DSV_TMSTMP_DEC_1: + *val = LSM6DSV_TMSTMP_DEC_1; + break; + + case LSM6DSV_TMSTMP_DEC_8: + *val = LSM6DSV_TMSTMP_DEC_8; + break; + + case LSM6DSV_TMSTMP_DEC_32: + *val = LSM6DSV_TMSTMP_DEC_32; + break; + + default: + *val = LSM6DSV_TMSTMP_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[set] + * + * @param ctx read / write interface definitions + * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_batch_counter_threshold_set(stmdev_ctx_t *ctx, + uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = lsm6dsv_write_reg(ctx, LSM6DSV_COUNTER_BDR_REG1, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[get] + * + * @param ctx read / write interface definitions + * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_batch_counter_threshold_get(stmdev_ctx_t *ctx, + uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_COUNTER_BDR_REG1, &buff[0], 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope and EIS gyroscope.[set] + * + * @param ctx read / write interface definitions + * @param val XL_BATCH_EVENT, GY_BATCH_EVENT, GY_EIS_BATCH_EVENT, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_batch_cnt_event_set(stmdev_ctx_t *ctx, + lsm6dsv_fifo_batch_cnt_event_t val) +{ + lsm6dsv_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret == 0) + { + counter_bdr_reg1.trig_counter_bdr = (uint8_t)val & 0x03U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + } + + return ret; +} + +/** + * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope and EIS gyroscope.[get] + * + * @param ctx read / write interface definitions + * @param val XL_BATCH_EVENT, GY_BATCH_EVENT, GY_EIS_BATCH_EVENT, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_batch_cnt_event_get(stmdev_ctx_t *ctx, + lsm6dsv_fifo_batch_cnt_event_t *val) +{ + lsm6dsv_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + switch (counter_bdr_reg1.trig_counter_bdr) + { + case LSM6DSV_XL_BATCH_EVENT: + *val = LSM6DSV_XL_BATCH_EVENT; + break; + + case LSM6DSV_GY_BATCH_EVENT: + *val = LSM6DSV_GY_BATCH_EVENT; + break; + + case LSM6DSV_GY_EIS_BATCH_EVENT: + *val = LSM6DSV_GY_EIS_BATCH_EVENT; + break; + + default: + *val = LSM6DSV_XL_BATCH_EVENT; + break; + } + return ret; +} + +int32_t lsm6dsv_fifo_status_get(stmdev_ctx_t *ctx, + lsm6dsv_fifo_status_t *val) +{ + uint8_t buff[2]; + lsm6dsv_fifo_status2_t status; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_STATUS1, (uint8_t *)&buff[0], 2); + bytecpy((uint8_t *)&status, &buff[1]); + + val->fifo_bdr = status.counter_bdr_ia; + val->fifo_ovr = status.fifo_ovr_ia; + val->fifo_full = status.fifo_full_ia; + val->fifo_th = status.fifo_wtm_ia; + + val->fifo_level = (uint16_t)buff[1] & 0x01U; + val->fifo_level = (val->fifo_level * 256U) + buff[0]; + + return ret; +} + +/** + * @brief FIFO data output[get] + * + * @param ctx read / write interface definitions + * @param val FIFO_EMPTY, GY_NC_TAG, XL_NC_TAG, TIMESTAMP_TAG, TEMPERATURE_TAG, CFG_CHANGE_TAG, XL_NC_T_2_TAG, XL_NC_T_1_TAG, XL_2XC_TAG, XL_3XC_TAG, GY_NC_T_2_TAG, GY_NC_T_1_TAG, GY_2XC_TAG, GY_3XC_TAG, SENSORHUB_SLAVE0_TAG, SENSORHUB_SLAVE1_TAG, SENSORHUB_SLAVE2_TAG, SENSORHUB_SLAVE3_TAG, STEP_CPUNTER_TAG, SENSORHUB_NACK_TAG, MLC_RESULT_TAG, MLC_FILTER, MLC_FEATURE, XL_DUAL_CORE, AH, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_out_raw_get(stmdev_ctx_t *ctx, + lsm6dsv_fifo_out_raw_t *val) +{ + lsm6dsv_fifo_data_out_tag_t fifo_data_out_tag; + uint8_t buff[7]; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_DATA_OUT_TAG, buff, 7); + bytecpy((uint8_t *)&fifo_data_out_tag, &buff[0]); + + switch (fifo_data_out_tag.tag_sensor) + { + case LSM6DSV_FIFO_EMPTY: + val->tag = LSM6DSV_FIFO_EMPTY; + break; + + case LSM6DSV_GY_NC_TAG: + val->tag = LSM6DSV_GY_NC_TAG; + break; + + case LSM6DSV_XL_NC_TAG: + val->tag = LSM6DSV_XL_NC_TAG; + break; + + case LSM6DSV_TIMESTAMP_TAG: + val->tag = LSM6DSV_TIMESTAMP_TAG; + break; + + case LSM6DSV_TEMPERATURE_TAG: + val->tag = LSM6DSV_TEMPERATURE_TAG; + break; + + case LSM6DSV_CFG_CHANGE_TAG: + val->tag = LSM6DSV_CFG_CHANGE_TAG; + break; + + case LSM6DSV_XL_NC_T_2_TAG: + val->tag = LSM6DSV_XL_NC_T_2_TAG; + break; + + case LSM6DSV_XL_NC_T_1_TAG: + val->tag = LSM6DSV_XL_NC_T_1_TAG; + break; + + case LSM6DSV_XL_2XC_TAG: + val->tag = LSM6DSV_XL_2XC_TAG; + break; + + case LSM6DSV_XL_3XC_TAG: + val->tag = LSM6DSV_XL_3XC_TAG; + break; + + case LSM6DSV_GY_NC_T_2_TAG: + val->tag = LSM6DSV_GY_NC_T_2_TAG; + break; + + case LSM6DSV_GY_NC_T_1_TAG: + val->tag = LSM6DSV_GY_NC_T_1_TAG; + break; + + case LSM6DSV_GY_2XC_TAG: + val->tag = LSM6DSV_GY_2XC_TAG; + break; + + case LSM6DSV_GY_3XC_TAG: + val->tag = LSM6DSV_GY_3XC_TAG; + break; + + case LSM6DSV_SENSORHUB_SLAVE0_TAG: + val->tag = LSM6DSV_SENSORHUB_SLAVE0_TAG; + break; + + case LSM6DSV_SENSORHUB_SLAVE1_TAG: + val->tag = LSM6DSV_SENSORHUB_SLAVE1_TAG; + break; + + case LSM6DSV_SENSORHUB_SLAVE2_TAG: + val->tag = LSM6DSV_SENSORHUB_SLAVE2_TAG; + break; + + case LSM6DSV_SENSORHUB_SLAVE3_TAG: + val->tag = LSM6DSV_SENSORHUB_SLAVE3_TAG; + break; + + case LSM6DSV_STEP_COUNTER_TAG: + val->tag = LSM6DSV_STEP_COUNTER_TAG; + break; + + case LSM6DSV_SENSORHUB_NACK_TAG: + val->tag = LSM6DSV_SENSORHUB_NACK_TAG; + break; + + case LSM6DSV_XL_DUAL_CORE: + val->tag = LSM6DSV_XL_DUAL_CORE; + break; + + case LSM6DSV_GY_ENHANCED_EIS: + val->tag = LSM6DSV_GY_ENHANCED_EIS; + break; + + default: + val->tag = LSM6DSV_FIFO_EMPTY; + break; + } + + val->cnt = fifo_data_out_tag.tag_cnt; + + val->data[0] = buff[1]; + val->data[1] = buff[2]; + val->data[2] = buff[3]; + val->data[3] = buff[4]; + val->data[4] = buff[5]; + val->data[5] = buff[6]; + + return ret; +} + +/** + * @brief Batching in FIFO buffer of step counter value.[set] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of step counter value. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_stpcnt_batch_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + + if (ret == 0) + { + emb_func_fifo_en_a.step_counter_fifo_en = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Batching in FIFO buffer of step counter value.[get] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of step counter value. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_stpcnt_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + + *val = emb_func_fifo_en_a.step_counter_fifo_en; + + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable FIFO data batching of first slave.[set] + * + * @param ctx read / write interface definitions + * @param val Enable FIFO data batching of first slave. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_batch_sh_slave_0_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_slv0_config_t slv0_config; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); + } + + if (ret == 0) + { + slv0_config.batch_ext_sens_0_en = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); + } + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable FIFO data batching of first slave.[get] + * + * @param ctx read / write interface definitions + * @param val Enable FIFO data batching of first slave. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_batch_sh_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_slv0_config_t slv0_config; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); + } + + *val = slv0_config.batch_ext_sens_0_en; + + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable FIFO data batching of second slave.[set] + * + * @param ctx read / write interface definitions + * @param val Enable FIFO data batching of second slave. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_batch_sh_slave_1_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_slv1_config_t slv1_config; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_SLV1_CONFIG, (uint8_t *)&slv1_config, 1); + } + + if (ret == 0) + { + slv1_config.batch_ext_sens_1_en = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV1_CONFIG, (uint8_t *)&slv1_config, 1); + } + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable FIFO data batching of second slave.[get] + * + * @param ctx read / write interface definitions + * @param val Enable FIFO data batching of second slave. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_batch_sh_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_slv1_config_t slv1_config; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_SLV1_CONFIG, (uint8_t *)&slv1_config, 1); + } + + *val = slv1_config.batch_ext_sens_1_en; + + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable FIFO data batching of third slave.[set] + * + * @param ctx read / write interface definitions + * @param val Enable FIFO data batching of third slave. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_batch_sh_slave_2_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_slv2_config_t slv2_config; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_SLV2_CONFIG, (uint8_t *)&slv2_config, 1); + } + + if (ret == 0) + { + slv2_config.batch_ext_sens_2_en = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV2_CONFIG, (uint8_t *)&slv2_config, 1); + } + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable FIFO data batching of third slave.[get] + * + * @param ctx read / write interface definitions + * @param val Enable FIFO data batching of third slave. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_batch_sh_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_slv2_config_t slv2_config; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_SLV2_CONFIG, (uint8_t *)&slv2_config, 1); + } + + *val = slv2_config.batch_ext_sens_2_en; + + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable FIFO data batching of fourth slave.[set] + * + * @param ctx read / write interface definitions + * @param val Enable FIFO data batching of fourth slave. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_batch_sh_slave_3_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_slv3_config_t slv3_config; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_SLV3_CONFIG, (uint8_t *)&slv3_config, 1); + } + + if (ret == 0) + { + slv3_config.batch_ext_sens_3_en = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV3_CONFIG, (uint8_t *)&slv3_config, 1); + } + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable FIFO data batching of fourth slave.[get] + * + * @param ctx read / write interface definitions + * @param val Enable FIFO data batching of fourth slave. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fifo_batch_sh_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_slv3_config_t slv3_config; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_SLV3_CONFIG, (uint8_t *)&slv3_config, 1); + } + + *val = slv3_config.batch_ext_sens_3_en; + + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Filters + * @brief This section group all the functions concerning the + * filters configuration + * @{ + * + */ + +/** + * @brief Protocol anti-spike filters.[set] + * + * @param ctx read / write interface definitions + * @param val AUTO, ALWAYS_ACTIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_filt_anti_spike_set(stmdev_ctx_t *ctx, + lsm6dsv_filt_anti_spike_t val) +{ + lsm6dsv_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1); + + if (ret == 0) + { + if_cfg.asf_ctrl = (uint8_t)val & 0x01U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Protocol anti-spike filters.[get] + * + * @param ctx read / write interface definitions + * @param val AUTO, ALWAYS_ACTIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_filt_anti_spike_get(stmdev_ctx_t *ctx, + lsm6dsv_filt_anti_spike_t *val) +{ + lsm6dsv_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1); + switch (if_cfg.asf_ctrl) + { + case LSM6DSV_AUTO: + *val = LSM6DSV_AUTO; + break; + + case LSM6DSV_ALWAYS_ACTIVE: + *val = LSM6DSV_ALWAYS_ACTIVE; + break; + + default: + *val = LSM6DSV_AUTO; + break; + } + return ret; +} + +/** + * @brief It masks DRDY and Interrupts RQ until filter settling ends.[set] + * + * @param ctx read / write interface definitions + * @param val It masks DRDY and Interrupts RQ until filter settling ends. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_filt_settling_mask_set(stmdev_ctx_t *ctx, + lsm6dsv_filt_settling_mask_t val) +{ + lsm6dsv_emb_func_cfg_t emb_func_cfg; + lsm6dsv_ui_int_ois_t ui_int_ois; + lsm6dsv_ctrl4_t ctrl4; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1); + + if (ret == 0) + { + ctrl4.drdy_mask = val.drdy; + + ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1); + } + + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + } + + if (ret == 0) + { + emb_func_cfg.emb_func_irq_mask_xl_settl = val.irq_xl; + emb_func_cfg.emb_func_irq_mask_g_settl = val.irq_g; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + } + + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1); + } + + if (ret == 0) + { + ui_int_ois.drdy_mask_ois = val.ois_drdy; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1); + } + + return ret; +} + +/** + * @brief It masks DRDY and Interrupts RQ until filter settling ends.[get] + * + * @param ctx read / write interface definitions + * @param val It masks DRDY and Interrupts RQ until filter settling ends. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_filt_settling_mask_get(stmdev_ctx_t *ctx, + lsm6dsv_filt_settling_mask_t *val) +{ + lsm6dsv_emb_func_cfg_t emb_func_cfg; + lsm6dsv_ui_int_ois_t ui_int_ois; + lsm6dsv_ctrl4_t ctrl4; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + } + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1); + } + + val->irq_xl = emb_func_cfg.emb_func_irq_mask_xl_settl; + val->irq_g = emb_func_cfg.emb_func_irq_mask_g_settl; + val->drdy = ctrl4.drdy_mask; + + return ret; +} + +/** + * @brief It masks DRDY and Interrupts RQ until filter settling ends.[set] + * + * @param ctx read / write interface definitions + * @param val It masks DRDY and Interrupts RQ until filter settling ends from OIS interface. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_filt_ois_settling_mask_set(stmdev_ctx_t *ctx, + lsm6dsv_filt_ois_settling_mask_t val) +{ + lsm6dsv_spi2_int_ois_t spi2_int_ois; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); + + if (ret == 0) + { + spi2_int_ois.drdy_mask_ois = val.ois_drdy; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); + } + + return ret; +} + +/** + * @brief It masks DRDY and Interrupts RQ until filter settling ends.[get] + * + * @param ctx read / write interface definitions + * @param val It masks DRDY and Interrupts RQ until filter settling ends. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_filt_ois_settling_mask_get(stmdev_ctx_t *ctx, + lsm6dsv_filt_ois_settling_mask_t *val) +{ + + lsm6dsv_spi2_int_ois_t spi2_int_ois; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); + val->ois_drdy = spi2_int_ois.drdy_mask_ois; + + return ret; +} + +/** + * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[set] + * + * @param ctx read / write interface definitions + * @param val GY_ULTRA_LIGHT, GY_VERY_LIGHT, GY_LIGHT, GY_MEDIUM, GY_STRONG, GY_VERY_STRONG, GY_AGGRESSIVE, GY_XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_filt_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, + lsm6dsv_filt_gy_lp1_bandwidth_t val) +{ + lsm6dsv_ctrl6_t ctrl6; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL6, (uint8_t *)&ctrl6, 1); + if (ret == 0) + { + ctrl6.lpf1_g_bw = (uint8_t)val & 0x0Fu; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL6, (uint8_t *)&ctrl6, 1); + } + + return ret; +} + +/** + * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[get] + * + * @param ctx read / write interface definitions + * @param val GY_ULTRA_LIGHT, GY_VERY_LIGHT, GY_LIGHT, GY_MEDIUM, GY_STRONG, GY_VERY_STRONG, GY_AGGRESSIVE, GY_XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_filt_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, + lsm6dsv_filt_gy_lp1_bandwidth_t *val) +{ + lsm6dsv_ctrl6_t ctrl6; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL6, (uint8_t *)&ctrl6, 1); + switch (ctrl6.lpf1_g_bw) + { + case LSM6DSV_GY_ULTRA_LIGHT: + *val = LSM6DSV_GY_ULTRA_LIGHT; + break; + + case LSM6DSV_GY_VERY_LIGHT: + *val = LSM6DSV_GY_VERY_LIGHT; + break; + + case LSM6DSV_GY_LIGHT: + *val = LSM6DSV_GY_LIGHT; + break; + + case LSM6DSV_GY_MEDIUM: + *val = LSM6DSV_GY_MEDIUM; + break; + + case LSM6DSV_GY_STRONG: + *val = LSM6DSV_GY_STRONG; + break; + + case LSM6DSV_GY_VERY_STRONG: + *val = LSM6DSV_GY_VERY_STRONG; + break; + + case LSM6DSV_GY_AGGRESSIVE: + *val = LSM6DSV_GY_AGGRESSIVE; + break; + + case LSM6DSV_GY_XTREME: + *val = LSM6DSV_GY_XTREME; + break; + + default: + *val = LSM6DSV_GY_ULTRA_LIGHT; + break; + } + return ret; +} + +/** + * @brief It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW.[set] + * + * @param ctx read / write interface definitions + * @param val It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_filt_gy_lp1_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_ctrl7_t ctrl7; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret == 0) + { + ctrl7.lpf1_g_en = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL7, (uint8_t *)&ctrl7, 1); + } + + return ret; +} + + +/** + * @brief It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW.[get] + * + * @param ctx read / write interface definitions + * @param val It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_filt_gy_lp1_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_ctrl7_t ctrl7; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL7, (uint8_t *)&ctrl7, 1); + *val = ctrl7.lpf1_g_en; + + return ret; +} + +/** + * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[set] + * + * @param ctx read / write interface definitions + * @param val XL_ULTRA_LIGHT, XL_VERY_LIGHT, XL_LIGHT, XL_MEDIUM, XL_STRONG, XL_VERY_STRONG, XL_AGGRESSIVE, XL_XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_filt_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, + lsm6dsv_filt_xl_lp2_bandwidth_t val) +{ + lsm6dsv_ctrl8_t ctrl8; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret == 0) + { + ctrl8.hp_lpf2_xl_bw = (uint8_t)val & 0x07U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL8, (uint8_t *)&ctrl8, 1); + } + + return ret; +} + +/** + * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[get] + * + * @param ctx read / write interface definitions + * @param val XL_ULTRA_LIGHT, XL_VERY_LIGHT, XL_LIGHT, XL_MEDIUM, XL_STRONG, XL_VERY_STRONG, XL_AGGRESSIVE, XL_XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_filt_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, + lsm6dsv_filt_xl_lp2_bandwidth_t *val) +{ + lsm6dsv_ctrl8_t ctrl8; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL8, (uint8_t *)&ctrl8, 1); + switch (ctrl8.hp_lpf2_xl_bw) + { + case LSM6DSV_XL_ULTRA_LIGHT: + *val = LSM6DSV_XL_ULTRA_LIGHT; + break; + + case LSM6DSV_XL_VERY_LIGHT: + *val = LSM6DSV_XL_VERY_LIGHT; + break; + + case LSM6DSV_XL_LIGHT: + *val = LSM6DSV_XL_LIGHT; + break; + + case LSM6DSV_XL_MEDIUM: + *val = LSM6DSV_XL_MEDIUM; + break; + + case LSM6DSV_XL_STRONG: + *val = LSM6DSV_XL_STRONG; + break; + + case LSM6DSV_XL_VERY_STRONG: + *val = LSM6DSV_XL_VERY_STRONG; + break; + + case LSM6DSV_XL_AGGRESSIVE: + *val = LSM6DSV_XL_AGGRESSIVE; + break; + + case LSM6DSV_XL_XTREME: + *val = LSM6DSV_XL_XTREME; + break; + + default: + *val = LSM6DSV_XL_ULTRA_LIGHT; + break; + } + return ret; +} + +/** + * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[set] + * + * @param ctx read / write interface definitions + * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_filt_xl_lp2_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.lpf2_xl_en = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[get] + * + * @param ctx read / write interface definitions + * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_filt_xl_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1); + *val = ctrl9.lpf2_xl_en; + + return ret; +} + +/** + * @brief Accelerometer slope filter / high-pass filter selection.[set] + * + * @param ctx read / write interface definitions + * @param val Accelerometer slope filter / high-pass filter selection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_filt_xl_hp_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.hp_slope_xl_en = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Accelerometer slope filter / high-pass filter selection.[get] + * + * @param ctx read / write interface definitions + * @param val Accelerometer slope filter / high-pass filter selection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_filt_xl_hp_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1); + *val = ctrl9.hp_slope_xl_en; + + return ret; +} + +/** + * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[set] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_filt_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.xl_fastsettl_mode = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[get] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_filt_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1); + *val = ctrl9.xl_fastsettl_mode; + + return ret; +} + +/** + * @brief Accelerometer high-pass filter mode.[set] + * + * @param ctx read / write interface definitions + * @param val HP_MD_NORMAL, HP_MD_REFERENCE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_filt_xl_hp_mode_set(stmdev_ctx_t *ctx, + lsm6dsv_filt_xl_hp_mode_t val) +{ + lsm6dsv_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.hp_ref_mode_xl = (uint8_t)val & 0x01U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Accelerometer high-pass filter mode.[get] + * + * @param ctx read / write interface definitions + * @param val HP_MD_NORMAL, HP_MD_REFERENCE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_filt_xl_hp_mode_get(stmdev_ctx_t *ctx, + lsm6dsv_filt_xl_hp_mode_t *val) +{ + lsm6dsv_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1); + switch (ctrl9.hp_ref_mode_xl) + { + case LSM6DSV_HP_MD_NORMAL: + *val = LSM6DSV_HP_MD_NORMAL; + break; + + case LSM6DSV_HP_MD_REFERENCE: + *val = LSM6DSV_HP_MD_REFERENCE; + break; + + default: + *val = LSM6DSV_HP_MD_NORMAL; + break; + } + return ret; +} + +/** + * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[set] + * + * @param ctx read / write interface definitions + * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS, WK_FEED_LP_WITH_OFFSET, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_filt_wkup_act_feed_set(stmdev_ctx_t *ctx, + lsm6dsv_filt_wkup_act_feed_t val) +{ + lsm6dsv_wake_up_ths_t wake_up_ths; + lsm6dsv_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + if (ret == 0) + { + tap_cfg0.slope_fds = (uint8_t)val & 0x01U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + if (ret == 0) + { + wake_up_ths.usr_off_on_wu = ((uint8_t)val & 0x02U) >> 1; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + } + + return ret; +} + +/** + * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[get] + * + * @param ctx read / write interface definitions + * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS, WK_FEED_LP_WITH_OFFSET, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_filt_wkup_act_feed_get(stmdev_ctx_t *ctx, + lsm6dsv_filt_wkup_act_feed_t *val) +{ + lsm6dsv_wake_up_ths_t wake_up_ths; + lsm6dsv_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + switch ((wake_up_ths.usr_off_on_wu << 1) + tap_cfg0.slope_fds) + { + case LSM6DSV_WK_FEED_SLOPE: + *val = LSM6DSV_WK_FEED_SLOPE; + break; + + case LSM6DSV_WK_FEED_HIGH_PASS: + *val = LSM6DSV_WK_FEED_HIGH_PASS; + break; + + case LSM6DSV_WK_FEED_LP_WITH_OFFSET: + *val = LSM6DSV_WK_FEED_LP_WITH_OFFSET; + break; + + default: + *val = LSM6DSV_WK_FEED_SLOPE; + break; + } + return ret; +} + +/** + * @brief Mask hw function triggers when xl is settling.[set] + * + * @param ctx read / write interface definitions + * @param val 0 or 1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_mask_trigger_xl_settl_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + + if (ret == 0) + { + tap_cfg0.hw_func_mask_xl_settl = val & 0x01U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + return ret; +} + +/** + * @brief Mask hw function triggers when xl is settling.[get] + * + * @param ctx read / write interface definitions + * @param val 0 or 1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_mask_trigger_xl_settl_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + *val = tap_cfg0.hw_func_mask_xl_settl; + + return ret; +} + +/** + * @brief LPF2 filter on 6D (sixd) function selection.[set] + * + * @param ctx read / write interface definitions + * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_filt_sixd_feed_set(stmdev_ctx_t *ctx, + lsm6dsv_filt_sixd_feed_t val) +{ + lsm6dsv_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + + if (ret == 0) + { + tap_cfg0.low_pass_on_6d = (uint8_t)val & 0x01U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + return ret; +} + +/** + * @brief LPF2 filter on 6D (sixd) function selection.[get] + * + * @param ctx read / write interface definitions + * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_filt_sixd_feed_get(stmdev_ctx_t *ctx, + lsm6dsv_filt_sixd_feed_t *val) +{ + lsm6dsv_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + + switch (tap_cfg0.low_pass_on_6d) + { + case LSM6DSV_SIXD_FEED_ODR_DIV_2: + *val = LSM6DSV_SIXD_FEED_ODR_DIV_2; + break; + + case LSM6DSV_SIXD_FEED_LOW_PASS: + *val = LSM6DSV_SIXD_FEED_LOW_PASS; + break; + + default: + *val = LSM6DSV_SIXD_FEED_ODR_DIV_2; + break; + } + return ret; +} + +/** + * @brief Gyroscope digital LPF_EIS filter bandwidth selection.[set] + * + * @param ctx read / write interface definitions + * @param val EIS_LP_NORMAL, EIS_LP_LIGHT, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_filt_gy_eis_lp_bandwidth_set(stmdev_ctx_t *ctx, + lsm6dsv_filt_gy_eis_lp_bandwidth_t val) +{ + lsm6dsv_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + + if (ret == 0) + { + ctrl_eis.lpf_g_eis_bw = (uint8_t)val & 0x01U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + } + + return ret; +} + +/** + * @brief Gyroscope digital LPF_EIS filter bandwidth selection.[get] + * + * @param ctx read / write interface definitions + * @param val EIS_LP_NORMAL, EIS_LP_LIGHT, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_filt_gy_eis_lp_bandwidth_get(stmdev_ctx_t *ctx, + lsm6dsv_filt_gy_eis_lp_bandwidth_t *val) +{ + lsm6dsv_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + + switch (ctrl_eis.lpf_g_eis_bw) + { + case LSM6DSV_EIS_LP_NORMAL: + *val = LSM6DSV_EIS_LP_NORMAL; + break; + + case LSM6DSV_EIS_LP_LIGHT: + *val = LSM6DSV_EIS_LP_LIGHT; + break; + + default: + *val = LSM6DSV_EIS_LP_NORMAL; + break; + } + return ret; +} + +/** + * @brief Gyroscope OIS digital LPF1 filter bandwidth selection. This function works also on OIS interface (SPI2_CTRL2_OIS = UI_CTRL2_OIS).[set] + * + * @param ctx read / write interface definitions + * @param val OIS_GY_LP_NORMAL, OIS_GY_LP_STRONG, OIS_GY_LP_AGGRESSIVE, OIS_GY_LP_LIGHT, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_filt_gy_ois_lp_bandwidth_set(stmdev_ctx_t *ctx, + lsm6dsv_filt_gy_ois_lp_bandwidth_t val) +{ + lsm6dsv_ui_ctrl2_ois_t ui_ctrl2_ois; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1); + + if (ret == 0) + { + ui_ctrl2_ois.lpf1_g_ois_bw = (uint8_t)val & 0x03U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1); + } + + return ret; +} + +/** + * @brief Gyroscope OIS digital LPF1 filter bandwidth selection. This function works also on OIS interface (SPI2_CTRL2_OIS = UI_CTRL2_OIS).[get] + * + * @param ctx read / write interface definitions + * @param val OIS_GY_LP_NORMAL, OIS_GY_LP_STRONG, OIS_GY_LP_AGGRESSIVE, OIS_GY_LP_LIGHT, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_filt_gy_ois_lp_bandwidth_get(stmdev_ctx_t *ctx, + lsm6dsv_filt_gy_ois_lp_bandwidth_t *val) +{ + + lsm6dsv_ui_ctrl2_ois_t ui_ctrl2_ois; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1); + + switch (ui_ctrl2_ois.lpf1_g_ois_bw) + { + case LSM6DSV_OIS_GY_LP_NORMAL: + *val = LSM6DSV_OIS_GY_LP_NORMAL; + break; + + case LSM6DSV_OIS_GY_LP_STRONG: + *val = LSM6DSV_OIS_GY_LP_STRONG; + break; + + case LSM6DSV_OIS_GY_LP_AGGRESSIVE: + *val = LSM6DSV_OIS_GY_LP_AGGRESSIVE; + break; + + case LSM6DSV_OIS_GY_LP_LIGHT: + *val = LSM6DSV_OIS_GY_LP_LIGHT; + break; + + default: + *val = LSM6DSV_OIS_GY_LP_NORMAL; + break; + } + return ret; +} + +/** + * @brief Selects accelerometer OIS channel bandwidth. This function works also on OIS interface (SPI2_CTRL3_OIS = UI_CTRL3_OIS).[set] + * + * @param ctx read / write interface definitions + * @param val OIS_XL_LP_ULTRA_LIGHT, OIS_XL_LP_VERY_LIGHT, OIS_XL_LP_LIGHT, OIS_XL_LP_NORMAL, OIS_XL_LP_STRONG, OIS_XL_LP_VERY_STRONG, OIS_XL_LP_AGGRESSIVE, OIS_XL_LP_XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_filt_xl_ois_lp_bandwidth_set(stmdev_ctx_t *ctx, + lsm6dsv_filt_xl_ois_lp_bandwidth_t val) +{ + lsm6dsv_ui_ctrl3_ois_t ui_ctrl3_ois; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1); + + if (ret == 0) + { + ui_ctrl3_ois.lpf_xl_ois_bw = (uint8_t)val & 0x07U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1); + } + + return ret; +} + +/** + * @brief Selects accelerometer OIS channel bandwidth. This function works also on OIS interface (SPI2_CTRL3_OIS = UI_CTRL3_OIS).[get] + * + * @param ctx read / write interface definitions + * @param val OIS_XL_LP_ULTRA_LIGHT, OIS_XL_LP_VERY_LIGHT, OIS_XL_LP_LIGHT, OIS_XL_LP_NORMAL, OIS_XL_LP_STRONG, OIS_XL_LP_VERY_STRONG, OIS_XL_LP_AGGRESSIVE, OIS_XL_LP_XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_filt_xl_ois_lp_bandwidth_get(stmdev_ctx_t *ctx, + lsm6dsv_filt_xl_ois_lp_bandwidth_t *val) +{ + lsm6dsv_ui_ctrl3_ois_t ui_ctrl3_ois; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1); + + switch (ui_ctrl3_ois.lpf_xl_ois_bw) + { + case LSM6DSV_OIS_XL_LP_ULTRA_LIGHT: + *val = LSM6DSV_OIS_XL_LP_ULTRA_LIGHT; + break; + + case LSM6DSV_OIS_XL_LP_VERY_LIGHT: + *val = LSM6DSV_OIS_XL_LP_VERY_LIGHT; + break; + + case LSM6DSV_OIS_XL_LP_LIGHT: + *val = LSM6DSV_OIS_XL_LP_LIGHT; + break; + + case LSM6DSV_OIS_XL_LP_NORMAL: + *val = LSM6DSV_OIS_XL_LP_NORMAL; + break; + + case LSM6DSV_OIS_XL_LP_STRONG: + *val = LSM6DSV_OIS_XL_LP_STRONG; + break; + + case LSM6DSV_OIS_XL_LP_VERY_STRONG: + *val = LSM6DSV_OIS_XL_LP_VERY_STRONG; + break; + + case LSM6DSV_OIS_XL_LP_AGGRESSIVE: + *val = LSM6DSV_OIS_XL_LP_AGGRESSIVE; + break; + + case LSM6DSV_OIS_XL_LP_XTREME: + *val = LSM6DSV_OIS_XL_LP_XTREME; + break; + + default: + *val = LSM6DSV_OIS_XL_LP_ULTRA_LIGHT; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Finite State Machine (FSM) + * @brief This section groups all the functions that manage the + * state_machine. + * @{ + * + */ + +/** + * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[set] + * + * @param ctx read / write interface definitions + * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fsm_permission_set(stmdev_ctx_t *ctx, + lsm6dsv_fsm_permission_t val) +{ + lsm6dsv_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + if (ret == 0) + { + func_cfg_access.fsm_wr_ctrl_en = (uint8_t)val & 0x01U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[get] + * + * @param ctx read / write interface definitions + * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fsm_permission_get(stmdev_ctx_t *ctx, + lsm6dsv_fsm_permission_t *val) +{ + lsm6dsv_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + switch (func_cfg_access.fsm_wr_ctrl_en) + { + case LSM6DSV_PROTECT_CTRL_REGS: + *val = LSM6DSV_PROTECT_CTRL_REGS; + break; + + case LSM6DSV_WRITE_CTRL_REG: + *val = LSM6DSV_WRITE_CTRL_REG; + break; + + default: + *val = LSM6DSV_PROTECT_CTRL_REGS; + break; + } + return ret; +} + +/** + * @brief Get the FSM permission status + * + * @param ctx read / write interface definitions + * @param val 0: All reg writable from std if - 1: some regs are under FSM control. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fsm_permission_status(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_ctrl_status_t ctrl_status; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL_STATUS, (uint8_t *)&ctrl_status, 1); + + *val = ctrl_status.fsm_wr_ctrl_status; + + return ret; +} + +/** + * @brief Enable Finite State Machine (FSM) feature.[set] + * + * @param ctx read / write interface definitions + * @param val Enable Finite State Machine (FSM) feature. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fsm_mode_set(stmdev_ctx_t *ctx, lsm6dsv_fsm_mode_t val) +{ + lsm6dsv_emb_func_en_b_t emb_func_en_b; + lsm6dsv_fsm_enable_t fsm_enable; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); + } + if ((val.fsm1_en | val.fsm2_en | val.fsm1_en | val.fsm1_en + | val.fsm1_en | val.fsm2_en | val.fsm1_en | val.fsm1_en) == PROPERTY_ENABLE) + { + emb_func_en_b.fsm_en = PROPERTY_ENABLE; + } + else + { + emb_func_en_b.fsm_en = PROPERTY_DISABLE; + } + if (ret == 0) + { + fsm_enable.fsm1_en = val.fsm1_en; + fsm_enable.fsm2_en = val.fsm2_en; + fsm_enable.fsm3_en = val.fsm3_en; + fsm_enable.fsm4_en = val.fsm4_en; + fsm_enable.fsm5_en = val.fsm5_en; + fsm_enable.fsm6_en = val.fsm6_en; + fsm_enable.fsm7_en = val.fsm7_en; + fsm_enable.fsm8_en = val.fsm8_en; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); + } + if (ret == 0) + { + ret = lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable Finite State Machine (FSM) feature.[get] + * + * @param ctx read / write interface definitions + * @param val Enable Finite State Machine (FSM) feature. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fsm_mode_get(stmdev_ctx_t *ctx, lsm6dsv_fsm_mode_t *val) +{ + lsm6dsv_fsm_enable_t fsm_enable; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); + } + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + val->fsm1_en = fsm_enable.fsm1_en; + val->fsm2_en = fsm_enable.fsm2_en; + val->fsm3_en = fsm_enable.fsm3_en; + val->fsm4_en = fsm_enable.fsm4_en; + val->fsm5_en = fsm_enable.fsm5_en; + val->fsm6_en = fsm_enable.fsm6_en; + val->fsm7_en = fsm_enable.fsm7_en; + val->fsm8_en = fsm_enable.fsm8_en; + + return ret; +} + +/** + * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[set] + * + * @param ctx read / write interface definitions + * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fsm_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + + ret = lsm6dsv_write_reg(ctx, LSM6DSV_FSM_LONG_COUNTER_L, (uint8_t *)&buff[0], 2); + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[get] + * + * @param ctx read / write interface definitions + * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fsm_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FSM_LONG_COUNTER_L, &buff[0], 2); + } + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief FSM output registers[get] + * + * @param ctx read / write interface definitions + * @param val FSM output registers + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fsm_out_get(stmdev_ctx_t *ctx, lsm6dsv_fsm_out_t *val) +{ + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FSM_OUTS1, (uint8_t *)val, 8); + } + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Finite State Machine Output Data Rate (ODR) configuration.[set] + * + * @param ctx read / write interface definitions + * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fsm_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv_fsm_data_rate_t val) +{ + lsm6dsv_fsm_odr_t fsm_odr; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FSM_ODR, (uint8_t *)&fsm_odr, 1); + } + + if (ret == 0) + { + fsm_odr.fsm_odr = (uint8_t)val & 0x07U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_FSM_ODR, (uint8_t *)&fsm_odr, 1); + } + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Finite State Machine Output Data Rate (ODR) configuration.[get] + * + * @param ctx read / write interface definitions + * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fsm_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv_fsm_data_rate_t *val) +{ + lsm6dsv_fsm_odr_t fsm_odr; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FSM_ODR, (uint8_t *)&fsm_odr, 1); + } + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + + switch (fsm_odr.fsm_odr) + { + case LSM6DSV_FSM_15Hz: + *val = LSM6DSV_FSM_15Hz; + break; + + case LSM6DSV_FSM_30Hz: + *val = LSM6DSV_FSM_30Hz; + break; + + case LSM6DSV_FSM_60Hz: + *val = LSM6DSV_FSM_60Hz; + break; + + case LSM6DSV_FSM_120Hz: + *val = LSM6DSV_FSM_120Hz; + break; + + case LSM6DSV_FSM_240Hz: + *val = LSM6DSV_FSM_240Hz; + break; + + case LSM6DSV_FSM_480Hz: + *val = LSM6DSV_FSM_480Hz; + break; + + case LSM6DSV_FSM_960Hz: + *val = LSM6DSV_FSM_960Hz; + break; + + default: + *val = LSM6DSV_FSM_15Hz; + break; + } + return ret; +} + +/** + * @brief External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB).[set] + * + * @param ctx read / write interface definitions + * @param val External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fsm_ext_sens_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = lsm6dsv_ln_pg_write(ctx, LSM6DSV_FSM_EXT_SENSITIVITY_L, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB).[get] + * + * @param ctx read / write interface definitions + * @param val External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fsm_ext_sens_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_FSM_EXT_SENSITIVITY_L, &buff[0], 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set] + * + * @param ctx read / write interface definitions + * @param val External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fsm_ext_sens_offset_set(stmdev_ctx_t *ctx, + lsm6dsv_xl_fsm_ext_sens_offset_t val) +{ + uint8_t buff[6]; + int32_t ret; + + buff[1] = (uint8_t)(val.x / 256U); + buff[0] = (uint8_t)(val.x - (buff[1] * 256U)); + buff[3] = (uint8_t)(val.y / 256U); + buff[2] = (uint8_t)(val.y - (buff[3] * 256U)); + buff[5] = (uint8_t)(val.z / 256U); + buff[4] = (uint8_t)(val.z - (buff[5] * 256U)); + ret = lsm6dsv_ln_pg_write(ctx, LSM6DSV_FSM_EXT_OFFX_L, (uint8_t *)&buff[0], 6); + + return ret; +} + +/** + * @brief External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get] + * + * @param ctx read / write interface definitions + * @param val External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fsm_ext_sens_offset_get(stmdev_ctx_t *ctx, + lsm6dsv_xl_fsm_ext_sens_offset_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_FSM_EXT_OFFX_L, &buff[0], 6); + + val->x = buff[1]; + val->x = (val->x * 256U) + buff[0]; + val->y = buff[3]; + val->y = (val->y * 256U) + buff[2]; + val->z = buff[5]; + val->z = (val->z * 256U) + buff[4]; + + return ret; +} + +/** + * @brief External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set] + * + * @param ctx read / write interface definitions + * @param val External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fsm_ext_sens_matrix_set(stmdev_ctx_t *ctx, + lsm6dsv_xl_fsm_ext_sens_matrix_t val) +{ + uint8_t buff[12]; + int32_t ret; + + buff[1] = (uint8_t)(val.xx / 256U); + buff[0] = (uint8_t)(val.xx - (buff[1] * 256U)); + buff[3] = (uint8_t)(val.xy / 256U); + buff[2] = (uint8_t)(val.xy - (buff[3] * 256U)); + buff[5] = (uint8_t)(val.xz / 256U); + buff[4] = (uint8_t)(val.xz - (buff[5] * 256U)); + buff[7] = (uint8_t)(val.yy / 256U); + buff[6] = (uint8_t)(val.yy - (buff[7] * 256U)); + buff[9] = (uint8_t)(val.yz / 256U); + buff[8] = (uint8_t)(val.yz - (buff[9] * 256U)); + buff[11] = (uint8_t)(val.zz / 256U); + buff[10] = (uint8_t)(val.zz - (buff[11] * 256U)); + ret = lsm6dsv_ln_pg_write(ctx, LSM6DSV_FSM_EXT_MATRIX_XX_L, (uint8_t *)&buff[0], 12); + + return ret; +} + +/** + * @brief External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get] + * + * @param ctx read / write interface definitions + * @param val External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fsm_ext_sens_matrix_get(stmdev_ctx_t *ctx, + lsm6dsv_xl_fsm_ext_sens_matrix_t *val) +{ + uint8_t buff[12]; + int32_t ret; + + ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_FSM_EXT_MATRIX_XX_L, &buff[0], 12); + + val->xx = buff[1]; + val->xx = (val->xx * 256U) + buff[0]; + val->xy = buff[3]; + val->xy = (val->xy * 256U) + buff[2]; + val->xz = buff[5]; + val->xz = (val->xz * 256U) + buff[4]; + val->yy = buff[7]; + val->yy = (val->yy * 256U) + buff[6]; + val->yz = buff[9]; + val->yz = (val->yz * 256U) + buff[8]; + val->zz = buff[11]; + val->zz = (val->zz * 256U) + buff[10]; + + return ret; +} + +/** + * @brief External sensor z-axis coordinates rotation.[set] + * + * @param ctx read / write interface definitions + * @param val Z_EQ_Y, Z_EQ_MIN_Y, Z_EQ_X, Z_EQ_MIN_X, Z_EQ_MIN_Z, Z_EQ_Z, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fsm_ext_sens_z_orient_set(stmdev_ctx_t *ctx, + lsm6dsv_fsm_ext_sens_z_orient_t val) +{ + lsm6dsv_ext_cfg_a_t ext_cfg_a; + int32_t ret; + + ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); + if (ret == 0) + { + ext_cfg_a.ext_z_axis = (uint8_t)val & 0x07U; + ret = lsm6dsv_ln_pg_write(ctx, LSM6DSV_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); + } + + return ret; +} + +/** + * @brief External sensor z-axis coordinates rotation.[get] + * + * @param ctx read / write interface definitions + * @param val Z_EQ_Y, Z_EQ_MIN_Y, Z_EQ_X, Z_EQ_MIN_X, Z_EQ_MIN_Z, Z_EQ_Z, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fsm_ext_sens_z_orient_get(stmdev_ctx_t *ctx, + lsm6dsv_fsm_ext_sens_z_orient_t *val) +{ + lsm6dsv_ext_cfg_a_t ext_cfg_a; + int32_t ret; + + ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); + switch (ext_cfg_a.ext_z_axis) + { + case LSM6DSV_Z_EQ_Y: + *val = LSM6DSV_Z_EQ_Y; + break; + + case LSM6DSV_Z_EQ_MIN_Y: + *val = LSM6DSV_Z_EQ_MIN_Y; + break; + + case LSM6DSV_Z_EQ_X: + *val = LSM6DSV_Z_EQ_X; + break; + + case LSM6DSV_Z_EQ_MIN_X: + *val = LSM6DSV_Z_EQ_MIN_X; + break; + + case LSM6DSV_Z_EQ_MIN_Z: + *val = LSM6DSV_Z_EQ_MIN_Z; + break; + + case LSM6DSV_Z_EQ_Z: + *val = LSM6DSV_Z_EQ_Z; + break; + + default: + *val = LSM6DSV_Z_EQ_Y; + break; + } + return ret; +} + +/** + * @brief External sensor Y-axis coordinates rotation.[set] + * + * @param ctx read / write interface definitions + * @param val Y_EQ_Y, Y_EQ_MIN_Y, Y_EQ_X, Y_EQ_MIN_X, Y_EQ_MIN_Z, Y_EQ_Z, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fsm_ext_sens_y_orient_set(stmdev_ctx_t *ctx, + lsm6dsv_fsm_ext_sens_y_orient_t val) +{ + lsm6dsv_ext_cfg_a_t ext_cfg_a; + int32_t ret; + + ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); + if (ret == 0) + { + ext_cfg_a.ext_y_axis = (uint8_t)val & 0x7U; + ret = lsm6dsv_ln_pg_write(ctx, LSM6DSV_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); + } + + return ret; +} + +/** + * @brief External sensor Y-axis coordinates rotation.[get] + * + * @param ctx read / write interface definitions + * @param val Y_EQ_Y, Y_EQ_MIN_Y, Y_EQ_X, Y_EQ_MIN_X, Y_EQ_MIN_Z, Y_EQ_Z, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fsm_ext_sens_y_orient_get(stmdev_ctx_t *ctx, + lsm6dsv_fsm_ext_sens_y_orient_t *val) +{ + lsm6dsv_ext_cfg_a_t ext_cfg_a; + int32_t ret; + + ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); + switch (ext_cfg_a.ext_y_axis) + { + case LSM6DSV_Y_EQ_Y: + *val = LSM6DSV_Y_EQ_Y; + break; + + case LSM6DSV_Y_EQ_MIN_Y: + *val = LSM6DSV_Y_EQ_MIN_Y; + break; + + case LSM6DSV_Y_EQ_X: + *val = LSM6DSV_Y_EQ_X; + break; + + case LSM6DSV_Y_EQ_MIN_X: + *val = LSM6DSV_Y_EQ_MIN_X; + break; + + case LSM6DSV_Y_EQ_MIN_Z: + *val = LSM6DSV_Y_EQ_MIN_Z; + break; + + case LSM6DSV_Y_EQ_Z: + *val = LSM6DSV_Y_EQ_Z; + break; + + default: + *val = LSM6DSV_Y_EQ_Y; + break; + } + return ret; +} + +/** + * @brief External sensor X-axis coordinates rotation.[set] + * + * @param ctx read / write interface definitions + * @param val X_EQ_Y, X_EQ_MIN_Y, X_EQ_X, X_EQ_MIN_X, X_EQ_MIN_Z, X_EQ_Z, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fsm_ext_sens_x_orient_set(stmdev_ctx_t *ctx, + lsm6dsv_fsm_ext_sens_x_orient_t val) +{ + lsm6dsv_ext_cfg_b_t ext_cfg_b; + int32_t ret; + + ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EXT_CFG_B, (uint8_t *)&ext_cfg_b, 1); + if (ret == 0) + { + ext_cfg_b.ext_x_axis = (uint8_t)val & 0x7U; + ret = lsm6dsv_ln_pg_write(ctx, LSM6DSV_EXT_CFG_B, (uint8_t *)&ext_cfg_b, 1); + } + + return ret; +} + +/** + * @brief External sensor X-axis coordinates rotation.[get] + * + * @param ctx read / write interface definitions + * @param val X_EQ_Y, X_EQ_MIN_Y, X_EQ_X, X_EQ_MIN_X, X_EQ_MIN_Z, X_EQ_Z, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fsm_ext_sens_x_orient_get(stmdev_ctx_t *ctx, + lsm6dsv_fsm_ext_sens_x_orient_t *val) +{ + lsm6dsv_ext_cfg_b_t ext_cfg_b; + int32_t ret; + + ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EXT_CFG_B, (uint8_t *)&ext_cfg_b, 1); + switch (ext_cfg_b.ext_x_axis) + { + case LSM6DSV_X_EQ_Y: + *val = LSM6DSV_X_EQ_Y; + break; + + case LSM6DSV_X_EQ_MIN_Y: + *val = LSM6DSV_X_EQ_MIN_Y; + break; + + case LSM6DSV_X_EQ_X: + *val = LSM6DSV_X_EQ_X; + break; + + case LSM6DSV_X_EQ_MIN_X: + *val = LSM6DSV_X_EQ_MIN_X; + break; + + case LSM6DSV_X_EQ_MIN_Z: + *val = LSM6DSV_X_EQ_MIN_Z; + break; + + case LSM6DSV_X_EQ_Z: + *val = LSM6DSV_X_EQ_Z; + break; + + default: + *val = LSM6DSV_X_EQ_Y; + break; + } + return ret; +} + +/** + * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[set] + * + * @param ctx read / write interface definitions + * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fsm_long_cnt_timeout_set(stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = lsm6dsv_ln_pg_write(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_FSM_LC_TIMEOUT_L, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[get] + * + * @param ctx read / write interface definitions + * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fsm_long_cnt_timeout_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_FSM_LC_TIMEOUT_L, &buff[0], 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief FSM number of programs.[set] + * + * @param ctx read / write interface definitions + * @param val FSM number of programs. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_fsm_programs_t fsm_programs; + int32_t ret; + + ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); + if (ret == 0) + { + fsm_programs.fsm_n_prog = val; + ret = lsm6dsv_ln_pg_write(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); + } + + return ret; +} + +/** + * @brief FSM number of programs.[get] + * + * @param ctx read / write interface definitions + * @param val FSM number of programs. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_fsm_programs_t fsm_programs; + int32_t ret; + + ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); + *val = fsm_programs.fsm_n_prog; + + return ret; +} + +/** + * @brief FSM start address. First available address is 0x35C.[set] + * + * @param ctx read / write interface definitions + * @param val FSM start address. First available address is 0x35C. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = lsm6dsv_ln_pg_write(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_FSM_START_ADD_L, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief FSM start address. First available address is 0x35C.[get] + * + * @param ctx read / write interface definitions + * @param val FSM start address. First available address is 0x35C. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_FSM_START_ADD_L, &buff[0], 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Free fall + * @brief This section group all the functions concerning the free + * fall detection. + * @{ + * + */ + +/** + * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[set] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ff_time_windows_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_wake_up_dur_t wake_up_dur; + lsm6dsv_free_fall_t free_fall; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + } + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + if (ret == 0) + { + free_fall.ff_dur = (uint8_t)val & 0x1FU; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + return ret; +} + +/** + * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[get] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ff_time_windows_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_wake_up_dur_t wake_up_dur; + lsm6dsv_free_fall_t free_fall; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; + + return ret; +} + +/** + * @brief Free fall threshold setting.[set] + * + * @param ctx read / write interface definitions + * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ff_thresholds_set(stmdev_ctx_t *ctx, + lsm6dsv_ff_thresholds_t val) +{ + lsm6dsv_free_fall_t free_fall; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret == 0) + { + free_fall.ff_ths = (uint8_t)val & 0x7U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + return ret; +} + +/** + * @brief Free fall threshold setting.[get] + * + * @param ctx read / write interface definitions + * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ff_thresholds_get(stmdev_ctx_t *ctx, + lsm6dsv_ff_thresholds_t *val) +{ + lsm6dsv_free_fall_t free_fall; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FREE_FALL, (uint8_t *)&free_fall, 1); + switch (free_fall.ff_ths) + { + case LSM6DSV_156_mg: + *val = LSM6DSV_156_mg; + break; + + case LSM6DSV_219_mg: + *val = LSM6DSV_219_mg; + break; + + case LSM6DSV_250_mg: + *val = LSM6DSV_250_mg; + break; + + case LSM6DSV_312_mg: + *val = LSM6DSV_312_mg; + break; + + case LSM6DSV_344_mg: + *val = LSM6DSV_344_mg; + break; + + case LSM6DSV_406_mg: + *val = LSM6DSV_406_mg; + break; + + case LSM6DSV_469_mg: + *val = LSM6DSV_469_mg; + break; + + case LSM6DSV_500_mg: + *val = LSM6DSV_500_mg; + break; + + default: + *val = LSM6DSV_156_mg; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Optical Image Stabilization (OIS) + * @brief This section groups all the functions concerning + * Optical Image Stabilization (OIS). + * @{ + * + */ + +/** + * @brief Enable the full control of OIS configurations from the UI (User Interface).[set] + * + * @param ctx read / write interface definitions + * @param val OIS_CTRL_FROM_OIS, OIS_CTRL_FROM_UI, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ois_ctrl_mode_set(stmdev_ctx_t *ctx, + lsm6dsv_ois_ctrl_mode_t val) +{ + lsm6dsv_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret == 0) + { + func_cfg_access.ois_ctrl_from_ui = (uint8_t)val & 0x1U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Enable the full control of OIS configurations from the UI (User Interface).[get] + * + * @param ctx read / write interface definitions + * @param val OIS_CTRL_FROM_OIS, OIS_CTRL_FROM_UI, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ois_ctrl_mode_get(stmdev_ctx_t *ctx, + lsm6dsv_ois_ctrl_mode_t *val) +{ + lsm6dsv_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + switch (func_cfg_access.ois_ctrl_from_ui) + { + case LSM6DSV_OIS_CTRL_FROM_OIS: + *val = LSM6DSV_OIS_CTRL_FROM_OIS; + break; + + case LSM6DSV_OIS_CTRL_FROM_UI: + *val = LSM6DSV_OIS_CTRL_FROM_UI; + break; + + default: + *val = LSM6DSV_OIS_CTRL_FROM_OIS; + break; + } + return ret; +} + +/** + * @brief Resets the control registers of OIS from the UI (User Interface)[set] + * + * @param ctx read / write interface definitions + * @param val Resets the control registers of OIS from the UI (User Interface) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ois_reset_set(stmdev_ctx_t *ctx, int8_t val) +{ + lsm6dsv_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret == 0) + { + func_cfg_access.spi2_reset = (uint8_t)val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Resets the control registers of OIS from the UI (User Interface)[get] + * + * @param ctx read / write interface definitions + * @param val Resets the control registers of OIS from the UI (User Interface) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ois_reset_get(stmdev_ctx_t *ctx, int8_t *val) +{ + lsm6dsv_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + *val = (int8_t)func_cfg_access.spi2_reset; + + return ret; +} + +/** + * @brief Enable/disable pull up on OIS interface.[set] + * + * @param ctx read / write interface definitions + * @param val Enable/disable pull up on OIS interface. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ois_interface_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret == 0) + { + pin_ctrl.ois_pu_dis = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + + return ret; +} + +/** + * @brief Enable/disable pull up on OIS interface.[get] + * + * @param ctx read / write interface definitions + * @param val Enable/disable pull up on OIS interface. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ois_interface_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + *val = pin_ctrl.ois_pu_dis; + + return ret; +} + +/** + * @brief Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.[set] + * + * @param ctx read / write interface definitions + * @param val Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ois_handshake_from_ui_set(stmdev_ctx_t *ctx, + lsm6dsv_ois_handshake_t val) +{ + lsm6dsv_ui_handshake_ctrl_t ui_handshake_ctrl; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_HANDSHAKE_CTRL, (uint8_t *)&ui_handshake_ctrl, 1); + if (ret == 0) + { + ui_handshake_ctrl.ui_shared_ack = val.ack; + ui_handshake_ctrl.ui_shared_req = val.req; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_UI_HANDSHAKE_CTRL, (uint8_t *)&ui_handshake_ctrl, 1); + } + + return ret; +} + +/** + * @brief Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.[get] + * + * @param ctx read / write interface definitions + * @param val Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ois_handshake_from_ui_get(stmdev_ctx_t *ctx, + lsm6dsv_ois_handshake_t *val) +{ + lsm6dsv_ui_handshake_ctrl_t ui_handshake_ctrl; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_HANDSHAKE_CTRL, (uint8_t *)&ui_handshake_ctrl, 1); + val->ack = ui_handshake_ctrl.ui_shared_ack; + val->req = ui_handshake_ctrl.ui_shared_req; + + return ret; +} + +/** + * @brief Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.[set] + * + * @param ctx read / write interface definitions + * @param val Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ois_handshake_from_ois_set(stmdev_ctx_t *ctx, + lsm6dsv_ois_handshake_t val) +{ + lsm6dsv_spi2_handshake_ctrl_t spi2_handshake_ctrl; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_SPI2_HANDSHAKE_CTRL, (uint8_t *)&spi2_handshake_ctrl, 1); + if (ret == 0) + { + spi2_handshake_ctrl.spi2_shared_ack = val.ack; + spi2_handshake_ctrl.spi2_shared_req = val.req; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_SPI2_HANDSHAKE_CTRL, (uint8_t *)&spi2_handshake_ctrl, 1); + } + + return ret; +} + +/** + * @brief Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.[get] + * + * @param ctx read / write interface definitions + * @param val Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ois_handshake_from_ois_get(stmdev_ctx_t *ctx, + lsm6dsv_ois_handshake_t *val) +{ + lsm6dsv_spi2_handshake_ctrl_t spi2_handshake_ctrl; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_SPI2_HANDSHAKE_CTRL, (uint8_t *)&spi2_handshake_ctrl, 1); + val->ack = spi2_handshake_ctrl.spi2_shared_ack; + val->req = spi2_handshake_ctrl.spi2_shared_req; + + return ret; +} + +/** + * @brief User interface (UI) / SPI2 (OIS) shared registers[set] + * + * @param ctx read / write interface definitions + * @param val User interface (UI) / SPI2 (OIS) shared registers + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ois_shared_set(stmdev_ctx_t *ctx, uint8_t val[6]) +{ + int32_t ret; + + ret = lsm6dsv_write_reg(ctx, LSM6DSV_UI_SPI2_SHARED_0, val, 6); + + return ret; +} + +/** + * @brief User interface (UI) / SPI2 (OIS) shared registers[get] + * + * @param ctx read / write interface definitions + * @param val User interface (UI) / SPI2 (OIS) shared registers + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ois_shared_get(stmdev_ctx_t *ctx, uint8_t val[6]) +{ + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_SPI2_SHARED_0, val, 6); + + return ret; +} + +/** + * @brief In User Interface (UI) full control mode, enables SPI2 (OIS Interface) for reading OIS data. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[set] + * + * @param ctx read / write interface definitions + * @param val In User Interface (UI) full control mode, enables SPI2 (OIS Interface) for reading OIS data. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ois_on_spi2_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_ui_ctrl1_ois_t ui_ctrl1_ois; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + if (ret == 0) + { + ui_ctrl1_ois.spi2_read_en = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + } + + return ret; +} + +/** + * @brief In User Interface (UI) full control mode, enables SPI2 (OIS Interface) for reading OIS data. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[get] + * + * @param ctx read / write interface definitions + * @param val In User Interface (UI) full control mode, enables SPI2 (OIS Interface) for reading OIS data. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ois_on_spi2_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_ui_ctrl1_ois_t ui_ctrl1_ois; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + *val = ui_ctrl1_ois.spi2_read_en; + + return ret; +} + +/** + * @brief Enables gyroscope/accelerometer OIS chain. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[set] + * + * @param ctx read / write interface definitions + * @param val Enables gyroscope/accelerometer OIS chain. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ois_chain_set(stmdev_ctx_t *ctx, lsm6dsv_ois_chain_t val) +{ + lsm6dsv_ui_ctrl1_ois_t ui_ctrl1_ois; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + if (ret == 0) + { + ui_ctrl1_ois.ois_g_en = val.gy; + ui_ctrl1_ois.ois_xl_en = val.xl; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + } + + return ret; +} + +/** + * @brief Enables gyroscope/accelerometer OIS chain.[get] + * + * @param ctx read / write interface definitions + * @param val Enables gyroscope/accelerometer OIS chain. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ois_chain_get(stmdev_ctx_t *ctx, lsm6dsv_ois_chain_t *val) +{ + lsm6dsv_ui_ctrl1_ois_t ui_ctrl1_ois; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + val->gy = ui_ctrl1_ois.ois_g_en; + val->xl = ui_ctrl1_ois.ois_xl_en; + + return ret; +} + +/** + * @brief Gyroscope OIS full-scale selection[set] + * + * @param ctx read / write interface definitions + * @param val OIS_125dps, OIS_250dps, OIS_500dps, OIS_1000dps, OIS_2000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ois_gy_full_scale_set(stmdev_ctx_t *ctx, + lsm6dsv_ois_gy_full_scale_t val) +{ + lsm6dsv_ui_ctrl2_ois_t ui_ctrl2_ois; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1); + if (ret == 0) + { + ui_ctrl2_ois.fs_g_ois = (uint8_t)val & 0x03U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1); + } + + return ret; +} + +/** + * @brief Gyroscope OIS full-scale selection[get] + * + * @param ctx read / write interface definitions + * @param val OIS_125dps, OIS_250dps, OIS_500dps, OIS_1000dps, OIS_2000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ois_gy_full_scale_get(stmdev_ctx_t *ctx, + lsm6dsv_ois_gy_full_scale_t *val) +{ + lsm6dsv_ui_ctrl2_ois_t ui_ctrl2_ois; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1); + switch (ui_ctrl2_ois.fs_g_ois) + { + case LSM6DSV_OIS_125dps: + *val = LSM6DSV_OIS_125dps; + break; + + case LSM6DSV_OIS_250dps: + *val = LSM6DSV_OIS_250dps; + break; + + case LSM6DSV_OIS_500dps: + *val = LSM6DSV_OIS_500dps; + break; + + case LSM6DSV_OIS_1000dps: + *val = LSM6DSV_OIS_1000dps; + break; + + case LSM6DSV_OIS_2000dps: + *val = LSM6DSV_OIS_2000dps; + break; + + default: + *val = LSM6DSV_OIS_125dps; + break; + } + return ret; +} + +/** + * @brief Selects accelerometer OIS channel full-scale.[set] + * + * @param ctx read / write interface definitions + * @param val OIS_2g, OIS_4g, OIS_8g, OIS_16g, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ois_xl_full_scale_set(stmdev_ctx_t *ctx, + lsm6dsv_ois_xl_full_scale_t val) +{ + lsm6dsv_ui_ctrl3_ois_t ui_ctrl3_ois; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1); + if (ret == 0) + { + ui_ctrl3_ois.fs_xl_ois = (uint8_t)val & 0x3U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1); + } + + return ret; +} + +/** + * @brief Selects accelerometer OIS channel full-scale.[get] + * + * @param ctx read / write interface definitions + * @param val OIS_2g, OIS_4g, OIS_8g, OIS_16g, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ois_xl_full_scale_get(stmdev_ctx_t *ctx, + lsm6dsv_ois_xl_full_scale_t *val) +{ + lsm6dsv_ui_ctrl3_ois_t ui_ctrl3_ois; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1); + switch (ui_ctrl3_ois.fs_xl_ois) + { + case LSM6DSV_OIS_2g: + *val = LSM6DSV_OIS_2g; + break; + + case LSM6DSV_OIS_4g: + *val = LSM6DSV_OIS_4g; + break; + + case LSM6DSV_OIS_8g: + *val = LSM6DSV_OIS_8g; + break; + + case LSM6DSV_OIS_16g: + *val = LSM6DSV_OIS_16g; + break; + + default: + *val = LSM6DSV_OIS_2g; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Orientation 6D (and 4D) + * @brief This section groups all the functions concerning six position + * detection (6D). + * @{ + * + */ + +/** + * @brief Threshold for 4D/6D function.[set] + * + * @param ctx read / write interface definitions + * @param val DEG_80, DEG_70, DEG_60, DEG_50, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_6d_threshold_set(stmdev_ctx_t *ctx, lsm6dsv_6d_threshold_t val) +{ + lsm6dsv_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret == 0) + { + tap_ths_6d.sixd_ths = (uint8_t)val & 0x03U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + } + + return ret; +} + +/** + * @brief Threshold for 4D/6D function.[get] + * + * @param ctx read / write interface definitions + * @param val DEG_80, DEG_70, DEG_60, DEG_50, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_6d_threshold_get(stmdev_ctx_t *ctx, lsm6dsv_6d_threshold_t *val) +{ + lsm6dsv_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + switch (tap_ths_6d.sixd_ths) + { + case LSM6DSV_DEG_80: + *val = LSM6DSV_DEG_80; + break; + + case LSM6DSV_DEG_70: + *val = LSM6DSV_DEG_70; + break; + + case LSM6DSV_DEG_60: + *val = LSM6DSV_DEG_60; + break; + + case LSM6DSV_DEG_50: + *val = LSM6DSV_DEG_50; + break; + + default: + *val = LSM6DSV_DEG_80; + break; + } + return ret; +} + +/** + * @brief 4D orientation detection enable. Z-axis position detection is disabled.[set] + * + * @param ctx read / write interface definitions + * @param val 4D orientation detection enable. Z-axis position detection is disabled. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret == 0) + { + tap_ths_6d.d4d_en = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + } + + return ret; +} + +/** + * @brief 4D orientation detection enable. Z-axis position detection is disabled.[get] + * + * @param ctx read / write interface definitions + * @param val 4D orientation detection enable. Z-axis position detection is disabled. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + *val = tap_ths_6d.d4d_en; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup SenseWire (I3C) + * @brief This section group all the functions concerning the + * usage of SenseWire (I3C) + * @{ + * + */ + +/** + * @brief Selects the action the device will perform after "Reset whole chip" I3C pattern.[set] + * + * @param ctx read / write interface definitions + * @param val SW_RST_DYN_ADDRESS_RST, GLOBAL_RST, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_i3c_reset_mode_set(stmdev_ctx_t *ctx, + lsm6dsv_i3c_reset_mode_t val) +{ + lsm6dsv_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret == 0) + { + pin_ctrl.ibhr_por_en = (uint8_t)val & 0x01U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + + return ret; +} + +/** + * @brief Selects the action the device will perform after "Reset whole chip" I3C pattern.[get] + * + * @param ctx read / write interface definitions + * @param val SW_RST_DYN_ADDRESS_RST, I3C_GLOBAL_RST, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_i3c_reset_mode_get(stmdev_ctx_t *ctx, + lsm6dsv_i3c_reset_mode_t *val) +{ + lsm6dsv_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + switch (pin_ctrl.ibhr_por_en) + { + case LSM6DSV_SW_RST_DYN_ADDRESS_RST: + *val = LSM6DSV_SW_RST_DYN_ADDRESS_RST; + break; + + case LSM6DSV_I3C_GLOBAL_RST: + *val = LSM6DSV_I3C_GLOBAL_RST; + break; + + default: + *val = LSM6DSV_SW_RST_DYN_ADDRESS_RST; + break; + } + return ret; +} + +/** + * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[set] + * + * @param ctx read / write interface definitions + * @param val IBI_2us, IBI_50us, IBI_1ms, IBI_25ms, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_i3c_ibi_time_set(stmdev_ctx_t *ctx, lsm6dsv_i3c_ibi_time_t val) +{ + lsm6dsv_ctrl5_t ctrl5; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret == 0) + { + ctrl5.bus_act_sel = (uint8_t)val & 0x03U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL5, (uint8_t *)&ctrl5, 1); + } + + return ret; +} + +/** + * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[get] + * + * @param ctx read / write interface definitions + * @param val IBI_2us, IBI_50us, IBI_1ms, IBI_25ms, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_i3c_ibi_time_get(stmdev_ctx_t *ctx, lsm6dsv_i3c_ibi_time_t *val) +{ + lsm6dsv_ctrl5_t ctrl5; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL5, (uint8_t *)&ctrl5, 1); + switch (ctrl5.bus_act_sel) + { + case LSM6DSV_IBI_2us: + *val = LSM6DSV_IBI_2us; + break; + + case LSM6DSV_IBI_50us: + *val = LSM6DSV_IBI_50us; + break; + + case LSM6DSV_IBI_1ms: + *val = LSM6DSV_IBI_1ms; + break; + + case LSM6DSV_IBI_25ms: + *val = LSM6DSV_IBI_25ms; + break; + + default: + *val = LSM6DSV_IBI_2us; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Sensor hub + * @brief This section groups all the functions that manage the + * sensor hub. + * @{ + * + */ + +/** + * @brief Sensor Hub master I2C pull-up enable.[set] + * + * @param ctx read / write interface definitions + * @param val Sensor Hub master I2C pull-up enable. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_sh_master_interface_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.shub_pu_en = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Sensor Hub master I2C pull-up enable.[get] + * + * @param ctx read / write interface definitions + * @param val Sensor Hub master I2C pull-up enable. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_sh_master_interface_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1); + *val = if_cfg.shub_pu_en; + + return ret; +} + +/** + * @brief Sensor hub output registers.[get] + * + * @param ctx read / write interface definitions + * @param val Sensor hub output registers. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_sh_read_data_raw_get(stmdev_ctx_t *ctx, + lsm6dsv_emb_sh_read_t *val, + uint8_t len) +{ + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_SENSOR_HUB_1, (uint8_t *) val, + len); + } + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + + return ret; +} + +/** + * @brief Number of external sensors to be read by the sensor hub.[set] + * + * @param ctx read / write interface definitions + * @param val SLV_0, SLV_0_1, SLV_0_1_2, SLV_0_1_2_3, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_sh_slave_connected_set(stmdev_ctx_t *ctx, + lsm6dsv_sh_slave_connected_t val) +{ + lsm6dsv_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + master_config.aux_sens_on = (uint8_t)val & 0x3U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Number of external sensors to be read by the sensor hub.[get] + * + * @param ctx read / write interface definitions + * @param val SLV_0, SLV_0_1, SLV_0_1_2, SLV_0_1_2_3, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_sh_slave_connected_get(stmdev_ctx_t *ctx, + lsm6dsv_sh_slave_connected_t *val) +{ + lsm6dsv_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + switch (master_config.aux_sens_on) + { + case LSM6DSV_SLV_0: + *val = LSM6DSV_SLV_0; + break; + + case LSM6DSV_SLV_0_1: + *val = LSM6DSV_SLV_0_1; + break; + + case LSM6DSV_SLV_0_1_2: + *val = LSM6DSV_SLV_0_1_2; + break; + + case LSM6DSV_SLV_0_1_2_3: + *val = LSM6DSV_SLV_0_1_2_3; + break; + + default: + *val = LSM6DSV_SLV_0; + break; + } + return ret; +} + +/** + * @brief Sensor hub I2C master enable.[set] + * + * @param ctx read / write interface definitions + * @param val Sensor hub I2C master enable. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + master_config.master_on = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Sensor hub I2C master enable.[get] + * + * @param ctx read / write interface definitions + * @param val Sensor hub I2C master enable. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + *val = master_config.master_on; + + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief I2C interface pass-through.[set] + * + * @param ctx read / write interface definitions + * @param val I2C interface pass-through. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + master_config.pass_through_mode = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief I2C interface pass-through.[get] + * + * @param ctx read / write interface definitions + * @param val I2C interface pass-through. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + *val = master_config.pass_through_mode; + + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Sensor hub trigger signal selection.[set] + * + * @param ctx read / write interface definitions + * @param val SH_TRG_XL_GY_DRDY, SH_TRIG_INT2, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_sh_syncro_mode_set(stmdev_ctx_t *ctx, + lsm6dsv_sh_syncro_mode_t val) +{ + lsm6dsv_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + master_config.start_config = (uint8_t)val & 0x01U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Sensor hub trigger signal selection.[get] + * + * @param ctx read / write interface definitions + * @param val SH_TRG_XL_GY_DRDY, SH_TRIG_INT2, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_sh_syncro_mode_get(stmdev_ctx_t *ctx, + lsm6dsv_sh_syncro_mode_t *val) +{ + lsm6dsv_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + switch (master_config.start_config) + { + case LSM6DSV_SH_TRG_XL_GY_DRDY: + *val = LSM6DSV_SH_TRG_XL_GY_DRDY; + break; + + case LSM6DSV_SH_TRIG_INT2: + *val = LSM6DSV_SH_TRIG_INT2; + break; + + default: + *val = LSM6DSV_SH_TRG_XL_GY_DRDY; + break; + } + return ret; +} + +/** + * @brief Slave 0 write operation is performed only at the first sensor hub cycle.[set] + * + * @param ctx read / write interface definitions + * @param val EACH_SH_CYCLE, ONLY_FIRST_CYCLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_sh_write_mode_set(stmdev_ctx_t *ctx, + lsm6dsv_sh_write_mode_t val) +{ + lsm6dsv_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + master_config.write_once = (uint8_t)val & 0x01U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Slave 0 write operation is performed only at the first sensor hub cycle.[get] + * + * @param ctx read / write interface definitions + * @param val EACH_SH_CYCLE, ONLY_FIRST_CYCLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_sh_write_mode_get(stmdev_ctx_t *ctx, + lsm6dsv_sh_write_mode_t *val) +{ + lsm6dsv_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + + switch (master_config.write_once) + { + case LSM6DSV_EACH_SH_CYCLE: + *val = LSM6DSV_EACH_SH_CYCLE; + break; + + case LSM6DSV_ONLY_FIRST_CYCLE: + *val = LSM6DSV_ONLY_FIRST_CYCLE; + break; + + default: + *val = LSM6DSV_EACH_SH_CYCLE; + break; + } + return ret; +} + +/** + * @brief Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.[set] + * + * @param ctx read / write interface definitions + * @param val Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_sh_reset_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + if (ret == 0) + { + master_config.rst_master_regs = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.[get] + * + * @param ctx read / write interface definitions + * @param val Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } + + *val = master_config.rst_master_regs; + + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Configure slave 0 for perform a write.[set] + * + * @param ctx read / write interface definitions + * @param val a structure that contain + * - uint8_t slv1_add; 8 bit i2c device address + * - uint8_t slv1_subadd; 8 bit register device address + * - uint8_t slv1_data; 8 bit data to write + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_sh_cfg_write(stmdev_ctx_t *ctx, + lsm6dsv_sh_cfg_write_t *val) +{ + lsm6dsv_slv0_add_t reg; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + reg.slave0_add = val->slv0_add; + reg.rw_0 = 0; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV0_ADD, (uint8_t *)®, 1); + } + + if (ret == 0) + { + ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV0_SUBADD, + &(val->slv0_subadd), 1); + } + + if (ret == 0) + { + ret = lsm6dsv_write_reg(ctx, LSM6DSV_DATAWRITE_SLV0, + &(val->slv0_data), 1); + } + + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Rate at which the master communicates.[set] + * + * @param ctx read / write interface definitions + * @param val SH_15Hz, SH_30Hz, SH_60Hz, SH_120Hz, SH_240Hz, SH_480Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_sh_data_rate_set(stmdev_ctx_t *ctx, lsm6dsv_sh_data_rate_t val) +{ + lsm6dsv_slv0_config_t slv0_config; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); + } + + if (ret == 0) + { + slv0_config.shub_odr = (uint8_t)val & 0x07U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); + } + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Rate at which the master communicates.[get] + * + * @param ctx read / write interface definitions + * @param val SH_15Hz, SH_30Hz, SH_60Hz, SH_120Hz, SH_240Hz, SH_480Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_sh_data_rate_get(stmdev_ctx_t *ctx, lsm6dsv_sh_data_rate_t *val) +{ + lsm6dsv_slv0_config_t slv0_config; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); + } + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + switch (slv0_config.shub_odr) + { + case LSM6DSV_SH_15Hz: + *val = LSM6DSV_SH_15Hz; + break; + + case LSM6DSV_SH_30Hz: + *val = LSM6DSV_SH_30Hz; + break; + + case LSM6DSV_SH_60Hz: + *val = LSM6DSV_SH_60Hz; + break; + + case LSM6DSV_SH_120Hz: + *val = LSM6DSV_SH_120Hz; + break; + + case LSM6DSV_SH_240Hz: + *val = LSM6DSV_SH_240Hz; + break; + + case LSM6DSV_SH_480Hz: + *val = LSM6DSV_SH_480Hz; + break; + + default: + *val = LSM6DSV_SH_15Hz; + break; + } + return ret; +} + +/** + * @brief Configure slave 0 for perform a read.[set] + * + * @param ctx read / write interface definitions + * @param val Structure that contain + * - uint8_t slv1_add; 8 bit i2c device address + * - uint8_t slv1_subadd; 8 bit register device address + * - uint8_t slv1_len; num of bit to read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_sh_slv0_cfg_read(stmdev_ctx_t *ctx, + lsm6dsv_sh_cfg_read_t *val) +{ + lsm6dsv_slv0_add_t slv0_add; + lsm6dsv_slv0_config_t slv0_config; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + + if (ret == 0) + { + slv0_add.slave0_add = val->slv_add; + slv0_add.rw_0 = 1; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV0_ADD, (uint8_t *)&slv0_add, 1); + } + + if (ret == 0) + { + ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV0_SUBADD, + &(val->slv_subadd), 1); + } + + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_SLV0_CONFIG, + (uint8_t *)&slv0_config, 1); + } + + if (ret == 0) + { + slv0_config.slave0_numop = val->slv_len; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV0_CONFIG, + (uint8_t *)&slv0_config, 1); + } + + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Configure slave 0 for perform a write/read.[set] + * + * @param ctx read / write interface definitions + * @param val Structure that contain + * - uint8_t slv1_add; 8 bit i2c device address + * - uint8_t slv1_subadd; 8 bit register device address + * - uint8_t slv1_len; num of bit to read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_sh_slv1_cfg_read(stmdev_ctx_t *ctx, + lsm6dsv_sh_cfg_read_t *val) +{ + lsm6dsv_slv1_add_t slv1_add; + lsm6dsv_slv1_config_t slv1_config; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + + if (ret == 0) + { + slv1_add.slave1_add = val->slv_add; + slv1_add.r_1 = 1; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV1_ADD, (uint8_t *)&slv1_add, 1); + } + + if (ret == 0) + { + ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV1_SUBADD, + &(val->slv_subadd), 1); + } + + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_SLV1_CONFIG, + (uint8_t *)&slv1_config, 1); + } + + if (ret == 0) + { + slv1_config.slave1_numop = val->slv_len; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV1_CONFIG, + (uint8_t *)&slv1_config, 1); + } + + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Configure slave 0 for perform a write/read.[set] + * + * @param ctx read / write interface definitions + * @param val Structure that contain + * - uint8_t slv2_add; 8 bit i2c device address + * - uint8_t slv2_subadd; 8 bit register device address + * - uint8_t slv2_len; num of bit to read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_sh_slv2_cfg_read(stmdev_ctx_t *ctx, + lsm6dsv_sh_cfg_read_t *val) +{ + lsm6dsv_slv2_add_t slv2_add; + lsm6dsv_slv2_config_t slv2_config; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + + if (ret == 0) + { + slv2_add.slave2_add = val->slv_add; + slv2_add.r_2 = 1; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV2_ADD, (uint8_t *)&slv2_add, 1); + } + + if (ret == 0) + { + ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV2_SUBADD, + &(val->slv_subadd), 1); + } + + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_SLV2_CONFIG, + (uint8_t *)&slv2_config, 1); + } + + if (ret == 0) + { + slv2_config.slave2_numop = val->slv_len; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV2_CONFIG, + (uint8_t *)&slv2_config, 1); + } + + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Configure slave 0 for perform a write/read.[set] + * + * @param ctx read / write interface definitions + * @param val Structure that contain + * - uint8_t slv3_add; 8 bit i2c device address + * - uint8_t slv3_subadd; 8 bit register device address + * - uint8_t slv3_len; num of bit to read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_sh_slv3_cfg_read(stmdev_ctx_t *ctx, + lsm6dsv_sh_cfg_read_t *val) +{ + lsm6dsv_slv3_add_t slv3_add; + lsm6dsv_slv3_config_t slv3_config; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + + if (ret == 0) + { + slv3_add.slave3_add = val->slv_add; + slv3_add.r_3 = 1; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV3_ADD, (uint8_t *)&slv3_add, 1); + } + + if (ret == 0) + { + ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV3_SUBADD, + &(val->slv_subadd), 1); + } + + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_SLV3_CONFIG, + (uint8_t *)&slv3_config, 1); + } + + if (ret == 0) + { + slv3_config.slave3_numop = val->slv_len; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV3_CONFIG, + (uint8_t *)&slv3_config, 1); + } + + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Serial interfaces + * @brief This section groups all the functions concerning + * serial interfaces management (not auxiliary) + * @{ + * + */ + +/** + * @brief Enables pull-up on SDO pin of UI (User Interface).[set] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDO pin of UI (User Interface). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret == 0) + { + pin_ctrl.sdo_pu_en = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + + return ret; +} + +/** + * @brief Enables pull-up on SDO pin of UI (User Interface).[get] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDO pin of UI (User Interface). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + *val = pin_ctrl.sdo_pu_en; + + return ret; +} + +/** + * @brief Disables I2C and I3C on UI (User Interface).[set] + * + * @param ctx read / write interface definitions + * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ui_i2c_i3c_mode_set(stmdev_ctx_t *ctx, + lsm6dsv_ui_i2c_i3c_mode_t val) +{ + lsm6dsv_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.i2c_i3c_disable = (uint8_t)val & 0x1U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Disables I2C and I3C on UI (User Interface).[get] + * + * @param ctx read / write interface definitions + * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ui_i2c_i3c_mode_get(stmdev_ctx_t *ctx, + lsm6dsv_ui_i2c_i3c_mode_t *val) +{ + lsm6dsv_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1); + switch (if_cfg.i2c_i3c_disable) + { + case LSM6DSV_I2C_I3C_ENABLE: + *val = LSM6DSV_I2C_I3C_ENABLE; + break; + + case LSM6DSV_I2C_I3C_DISABLE: + *val = LSM6DSV_I2C_I3C_DISABLE; + break; + + default: + *val = LSM6DSV_I2C_I3C_ENABLE; + break; + } + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val SPI_4_WIRE, SPI_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsv_spi_mode_t val) +{ + lsm6dsv_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.sim = (uint8_t)val & 0x01U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val SPI_4_WIRE, SPI_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsv_spi_mode_t *val) +{ + lsm6dsv_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1); + switch (if_cfg.sim) + { + case LSM6DSV_SPI_4_WIRE: + *val = LSM6DSV_SPI_4_WIRE; + break; + + case LSM6DSV_SPI_3_WIRE: + *val = LSM6DSV_SPI_3_WIRE; + break; + + default: + *val = LSM6DSV_SPI_4_WIRE; + break; + } + return ret; +} + +/** + * @brief Enables pull-up on SDA pin.[set] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDA pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ui_sda_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.sda_pu_en = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Enables pull-up on SDA pin.[get] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDA pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_ui_sda_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1); + *val = if_cfg.sda_pu_en; + + return ret; +} + +/** + * @brief SPI2 (OIS Inteface) Serial Interface Mode selection. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[set] + * + * @param ctx read / write interface definitions + * @param val SPI2_4_WIRE, SPI2_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_spi2_mode_set(stmdev_ctx_t *ctx, lsm6dsv_spi2_mode_t val) +{ + lsm6dsv_ui_ctrl1_ois_t ui_ctrl1_ois; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + if (ret == 0) + { + ui_ctrl1_ois.sim_ois = (uint8_t)val & 0x01U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + } + + return ret; +} + +/** + * @brief SPI2 (OIS Inteface) Serial Interface Mode selection. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[get] + * + * @param ctx read / write interface definitions + * @param val SPI2_4_WIRE, SPI2_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_spi2_mode_get(stmdev_ctx_t *ctx, lsm6dsv_spi2_mode_t *val) +{ + lsm6dsv_ui_ctrl1_ois_t ui_ctrl1_ois; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + switch (ui_ctrl1_ois.sim_ois) + { + case LSM6DSV_SPI2_4_WIRE: + *val = LSM6DSV_SPI2_4_WIRE; + break; + + case LSM6DSV_SPI2_3_WIRE: + *val = LSM6DSV_SPI2_3_WIRE; + break; + + default: + *val = LSM6DSV_SPI2_4_WIRE; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Significant motion detection + * @brief This section groups all the functions that manage the + * significant motion detection. + * @{ + * + */ + + +/** + * @brief Enables significant motion detection function.[set] + * + * @param ctx read / write interface definitions + * @param val Enables significant motion detection function. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_sigmot_mode_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + if (ret == 0) + { + emb_func_en_a.sign_motion_en = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enables significant motion detection function.[get] + * + * @param ctx read / write interface definitions + * @param val Enables significant motion detection function. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_sigmot_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + *val = emb_func_en_a.sign_motion_en; + + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Step Counter (Pedometer) + * @brief This section groups all the functions that manage pedometer. + * @{ + * + */ + +/** + * @brief Step counter mode[set] + * + * @param ctx read / write interface definitions + * @param val Step counter mode + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_stpcnt_mode_set(stmdev_ctx_t *ctx, + lsm6dsv_stpcnt_mode_t val) +{ + lsm6dsv_emb_func_en_a_t emb_func_en_a; + lsm6dsv_emb_func_en_b_t emb_func_en_b; + lsm6dsv_pedo_cmd_reg_t pedo_cmd_reg; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + emb_func_en_a.pedo_en = val.step_counter_enable; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + if (ret == 0) + { + ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + + return ret; +} + +/** + * @brief Step counter mode[get] + * + * @param ctx read / write interface definitions + * @param val false_step_rej, step_counter, step_detector, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_stpcnt_mode_get(stmdev_ctx_t *ctx, + lsm6dsv_stpcnt_mode_t *val) +{ + lsm6dsv_emb_func_en_a_t emb_func_en_a; + lsm6dsv_pedo_cmd_reg_t pedo_cmd_reg; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + if (ret == 0) + { + ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + val->step_counter_enable = emb_func_en_a.pedo_en; + + return ret; +} + +/** + * @brief Step counter output, number of detected steps.[get] + * + * @param ctx read / write interface definitions + * @param val Step counter output, number of detected steps. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_STEP_COUNTER_L, &buff[0], 2); + } + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief Reset step counter.[set] + * + * @param ctx read / write interface definitions + * @param val Reset step counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_stpcnt_rst_step_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_emb_func_src_t emb_func_src; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } + + if (ret == 0) + { + emb_func_src.pedo_rst_step = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Reset step counter.[get] + * + * @param ctx read / write interface definitions + * @param val Reset step counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_stpcnt_rst_step_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_emb_func_src_t emb_func_src; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } + + *val = emb_func_src.pedo_rst_step; + + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Pedometer debounce configuration.[set] + * + * @param ctx read / write interface definitions + * @param val Pedometer debounce configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_stpcnt_debounce_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_pedo_deb_steps_conf_t pedo_deb_steps_conf; + int32_t ret; + + ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); + if (ret == 0) + { + pedo_deb_steps_conf.deb_step = val; + ret = lsm6dsv_ln_pg_write(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); + } + + return ret; +} + +/** + * @brief Pedometer debounce configuration.[get] + * + * @param ctx read / write interface definitions + * @param val Pedometer debounce configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_stpcnt_debounce_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_pedo_deb_steps_conf_t pedo_deb_steps_conf; + int32_t ret; + + ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); + *val = pedo_deb_steps_conf.deb_step; + + return ret; +} + +/** + * @brief Time period register for step detection on delta time.[set] + * + * @param ctx read / write interface definitions + * @param val Time period register for step detection on delta time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = lsm6dsv_ln_pg_write(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_PEDO_SC_DELTAT_L, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief Time period register for step detection on delta time.[get] + * + * @param ctx read / write interface definitions + * @param val Time period register for step detection on delta time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_stpcnt_period_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_PEDO_SC_DELTAT_L, &buff[0], 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Tap - Double Tap + * @brief This section groups all the functions that manage the + * tap and double tap event generation. + * @{ + * + */ + +/** + * @brief Enable axis for Tap - Double Tap detection.[set] + * + * @param ctx read / write interface definitions + * @param val Enable axis for Tap - Double Tap detection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_tap_detection_set(stmdev_ctx_t *ctx, + lsm6dsv_tap_detection_t val) +{ + lsm6dsv_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret == 0) + { + tap_cfg0.tap_x_en = val.tap_x_en; + tap_cfg0.tap_y_en = val.tap_y_en; + tap_cfg0.tap_z_en = val.tap_z_en; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + return ret; +} + +/** + * @brief Enable axis for Tap - Double Tap detection.[get] + * + * @param ctx read / write interface definitions + * @param val Enable axis for Tap - Double Tap detection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_tap_detection_get(stmdev_ctx_t *ctx, + lsm6dsv_tap_detection_t *val) +{ + lsm6dsv_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + val->tap_x_en = tap_cfg0.tap_x_en; + val->tap_y_en = tap_cfg0.tap_y_en; + val->tap_z_en = tap_cfg0.tap_z_en; + + return ret; +} + +/** + * @brief axis Tap - Double Tap recognition thresholds.[set] + * + * @param ctx read / write interface definitions + * @param val axis Tap - Double Tap recognition thresholds. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_tap_thresholds_set(stmdev_ctx_t *ctx, + lsm6dsv_tap_thresholds_t val) +{ + lsm6dsv_tap_ths_6d_t tap_ths_6d; + lsm6dsv_tap_cfg2_t tap_cfg2; + lsm6dsv_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + } + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + } + + tap_cfg1.tap_ths_x = val.x; + tap_cfg2.tap_ths_y = val.y; + tap_ths_6d.tap_ths_z = val.z; + + if (ret == 0) + { + ret = lsm6dsv_write_reg(ctx, LSM6DSV_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + } + if (ret == 0) + { + ret = lsm6dsv_write_reg(ctx, LSM6DSV_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + } + if (ret == 0) + { + ret = lsm6dsv_write_reg(ctx, LSM6DSV_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + } + + return ret; +} + +/** + * @brief axis Tap - Double Tap recognition thresholds.[get] + * + * @param ctx read / write interface definitions + * @param val axis Tap - Double Tap recognition thresholds. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_tap_thresholds_get(stmdev_ctx_t *ctx, + lsm6dsv_tap_thresholds_t *val) +{ + lsm6dsv_tap_ths_6d_t tap_ths_6d; + lsm6dsv_tap_cfg2_t tap_cfg2; + lsm6dsv_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + } + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + } + + val->x = tap_cfg1.tap_ths_x; + val->y = tap_cfg2.tap_ths_y; + val->z = tap_ths_6d.tap_ths_z; + + return ret; +} + +/** + * @brief Selection of axis priority for TAP detection.[set] + * + * @param ctx read / write interface definitions + * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY , + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_tap_axis_priority_set(stmdev_ctx_t *ctx, + lsm6dsv_tap_axis_priority_t val) +{ + lsm6dsv_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret == 0) + { + tap_cfg1.tap_priority = (uint8_t)val & 0x7U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + } + + return ret; +} + +/** + * @brief Selection of axis priority for TAP detection.[get] + * + * @param ctx read / write interface definitions + * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY , + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_tap_axis_priority_get(stmdev_ctx_t *ctx, + lsm6dsv_tap_axis_priority_t *val) +{ + lsm6dsv_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + switch (tap_cfg1.tap_priority) + { + case LSM6DSV_XYZ : + *val = LSM6DSV_XYZ ; + break; + + case LSM6DSV_YXZ : + *val = LSM6DSV_YXZ ; + break; + + case LSM6DSV_XZY: + *val = LSM6DSV_XZY; + break; + + case LSM6DSV_ZYX : + *val = LSM6DSV_ZYX ; + break; + + case LSM6DSV_YZX : + *val = LSM6DSV_YZX ; + break; + + case LSM6DSV_ZXY : + *val = LSM6DSV_ZXY ; + break; + + default: + *val = LSM6DSV_XYZ ; + break; + } + return ret; +} + +/** + * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[set] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_tap_time_windows_set(stmdev_ctx_t *ctx, + lsm6dsv_tap_time_windows_t val) +{ + lsm6dsv_tap_dur_t tap_dur; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_DUR, (uint8_t *)&tap_dur, 1); + if (ret == 0) + { + tap_dur.shock = val.shock; + tap_dur.quiet = val.quiet; + tap_dur.dur = val.tap_gap; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_TAP_DUR, (uint8_t *)&tap_dur, 1); + } + + return ret; +} + +/** + * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[get] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_tap_time_windows_get(stmdev_ctx_t *ctx, + lsm6dsv_tap_time_windows_t *val) +{ + lsm6dsv_tap_dur_t tap_dur; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_DUR, (uint8_t *)&tap_dur, 1); + val->shock = tap_dur.shock; + val->quiet = tap_dur.quiet; + val->tap_gap = tap_dur.dur; + + return ret; +} + +/** + * @brief Single/double-tap event enable.[set] + * + * @param ctx read / write interface definitions + * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_tap_mode_set(stmdev_ctx_t *ctx, lsm6dsv_tap_mode_t val) +{ + lsm6dsv_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret == 0) + { + wake_up_ths.single_double_tap = (uint8_t)val & 0x01U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + } + + return ret; +} + +/** + * @brief Single/double-tap event enable.[get] + * + * @param ctx read / write interface definitions + * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_tap_mode_get(stmdev_ctx_t *ctx, lsm6dsv_tap_mode_t *val) +{ + lsm6dsv_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + switch (wake_up_ths.single_double_tap) + { + case LSM6DSV_ONLY_SINGLE: + *val = LSM6DSV_ONLY_SINGLE; + break; + + case LSM6DSV_BOTH_SINGLE_DOUBLE: + *val = LSM6DSV_BOTH_SINGLE_DOUBLE; + break; + + default: + *val = LSM6DSV_ONLY_SINGLE; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Tilt detection + * @brief This section groups all the functions that manage the tilt + * event detection. + * @{ + * + */ + +/** + * @brief Tilt calculation.[set] + * + * @param ctx read / write interface definitions + * @param val Tilt calculation. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_tilt_mode_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + if (ret == 0) + { + emb_func_en_a.tilt_en = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Tilt calculation.[get] + * + * @param ctx read / write interface definitions + * @param val Tilt calculation. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_tilt_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + *val = emb_func_en_a.tilt_en; + + ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Timestamp + * @brief This section groups all the functions that manage the + * timestamp generation. + * @{ + * + */ + +/** + * @brief Timestamp data output.[get] + * + * @param ctx read / write interface definitions + * @param val Timestamp data output. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) +{ + uint8_t buff[4]; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_TIMESTAMP0, &buff[0], 4); + *val = buff[3]; + *val = (*val * 256U) + buff[2]; + *val = (*val * 256U) + buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief Enables timestamp counter.[set] + * + * @param ctx read / write interface definitions + * @param val Enables timestamp counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_functions_enable_t functions_enable; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret == 0) + { + functions_enable.timestamp_en = val; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + return ret; +} + +/** + * @brief Enables timestamp counter.[get] + * + * @param ctx read / write interface definitions + * @param val Enables timestamp counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_functions_enable_t functions_enable; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + *val = functions_enable.timestamp_en; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Wake Up - Activity - Inactivity (Sleep) + * @brief This section groups all the functions that manage the Wake Up + * event generation. + * @{ + * + */ + +/** + * @brief Enable activity/inactivity (sleep) function.[set] + * + * @param ctx read / write interface definitions + * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_act_mode_set(stmdev_ctx_t *ctx, lsm6dsv_act_mode_t val) +{ + lsm6dsv_functions_enable_t functions_enable; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret == 0) + { + functions_enable.inact_en = (uint8_t)val & 0x3U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + return ret; +} + +/** + * @brief Enable activity/inactivity (sleep) function.[get] + * + * @param ctx read / write interface definitions + * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_act_mode_get(stmdev_ctx_t *ctx, lsm6dsv_act_mode_t *val) +{ + lsm6dsv_functions_enable_t functions_enable; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + switch (functions_enable.inact_en) + { + case LSM6DSV_XL_AND_GY_NOT_AFFECTED: + *val = LSM6DSV_XL_AND_GY_NOT_AFFECTED; + break; + + case LSM6DSV_XL_LOW_POWER_GY_NOT_AFFECTED: + *val = LSM6DSV_XL_LOW_POWER_GY_NOT_AFFECTED; + break; + + case LSM6DSV_XL_LOW_POWER_GY_SLEEP: + *val = LSM6DSV_XL_LOW_POWER_GY_SLEEP; + break; + + case LSM6DSV_XL_LOW_POWER_GY_POWER_DOWN: + *val = LSM6DSV_XL_LOW_POWER_GY_POWER_DOWN; + break; + + default: + *val = LSM6DSV_XL_AND_GY_NOT_AFFECTED; + break; + } + return ret; +} + +/** + * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[set] + * + * @param ctx read / write interface definitions + * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_act_from_sleep_to_act_dur_set(stmdev_ctx_t *ctx, + lsm6dsv_act_from_sleep_to_act_dur_t val) +{ + lsm6dsv_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret == 0) + { + inactivity_dur.inact_dur = (uint8_t)val & 0x3U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + return ret; +} + +/** + * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[get] + * + * @param ctx read / write interface definitions + * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_act_from_sleep_to_act_dur_get(stmdev_ctx_t *ctx, + lsm6dsv_act_from_sleep_to_act_dur_t *val) +{ + lsm6dsv_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + switch (inactivity_dur.inact_dur) + { + case LSM6DSV_SLEEP_TO_ACT_AT_1ST_SAMPLE: + *val = LSM6DSV_SLEEP_TO_ACT_AT_1ST_SAMPLE; + break; + + case LSM6DSV_SLEEP_TO_ACT_AT_2ND_SAMPLE: + *val = LSM6DSV_SLEEP_TO_ACT_AT_2ND_SAMPLE; + break; + + case LSM6DSV_SLEEP_TO_ACT_AT_3RD_SAMPLE: + *val = LSM6DSV_SLEEP_TO_ACT_AT_3RD_SAMPLE; + break; + + case LSM6DSV_SLEEP_TO_ACT_AT_4th_SAMPLE: + *val = LSM6DSV_SLEEP_TO_ACT_AT_4th_SAMPLE; + break; + + default: + *val = LSM6DSV_SLEEP_TO_ACT_AT_1ST_SAMPLE; + break; + } + return ret; +} + +/** + * @brief Selects the accelerometer data rate during Inactivity.[set] + * + * @param ctx read / write interface definitions + * @param val 1Hz875, 15Hz, 30Hz, 60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_act_sleep_xl_odr_set(stmdev_ctx_t *ctx, + lsm6dsv_act_sleep_xl_odr_t val) +{ + lsm6dsv_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret == 0) + { + inactivity_dur.xl_inact_odr = (uint8_t)val & 0x03U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + return ret; +} + +/** + * @brief Selects the accelerometer data rate during Inactivity.[get] + * + * @param ctx read / write interface definitions + * @param val 1Hz875, 15Hz, 30Hz, 60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_act_sleep_xl_odr_get(stmdev_ctx_t *ctx, + lsm6dsv_act_sleep_xl_odr_t *val) +{ + lsm6dsv_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + switch (inactivity_dur.xl_inact_odr) + { + case LSM6DSV_1Hz875: + *val = LSM6DSV_1Hz875; + break; + + case LSM6DSV_15Hz: + *val = LSM6DSV_15Hz; + break; + + case LSM6DSV_30Hz: + *val = LSM6DSV_30Hz; + break; + + case LSM6DSV_60Hz: + *val = LSM6DSV_60Hz; + break; + + default: + *val = LSM6DSV_1Hz875; + break; + } + return ret; +} + +/** + * @brief Wakeup and activity/inactivity threshold.[set] + * + * @param ctx read / write interface definitions + * @param val Wakeup and activity/inactivity threshold. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_act_thresholds_set(stmdev_ctx_t *ctx, + lsm6dsv_act_thresholds_t *val) +{ + lsm6dsv_inactivity_ths_t inactivity_ths; + lsm6dsv_inactivity_dur_t inactivity_dur; + lsm6dsv_wake_up_ths_t wake_up_ths; + lsm6dsv_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + ret += lsm6dsv_read_reg(ctx, LSM6DSV_INACTIVITY_THS, (uint8_t *)&inactivity_ths, + 1); + ret += lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + ret += lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + + inactivity_dur.wu_inact_ths_w = val->inactivity_cfg.wu_inact_ths_w; + inactivity_dur.xl_inact_odr = val->inactivity_cfg.xl_inact_odr; + inactivity_dur.inact_dur = val->inactivity_cfg.inact_dur; + + inactivity_ths.inact_ths = val->inactivity_ths; + wake_up_ths.wk_ths = val->threshold; + wake_up_dur.wake_dur = val->duration; + + ret += lsm6dsv_write_reg(ctx, LSM6DSV_INACTIVITY_DUR, + (uint8_t *)&inactivity_dur, 1); + ret += lsm6dsv_write_reg(ctx, LSM6DSV_INACTIVITY_THS, + (uint8_t *)&inactivity_ths, 1); + ret += lsm6dsv_write_reg(ctx, LSM6DSV_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + ret += lsm6dsv_write_reg(ctx, LSM6DSV_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + + return ret; +} + +/** + * @brief Wakeup and activity/inactivity threshold.[get] + * + * @param ctx read / write interface definitions + * @param val Wakeup and activity/inactivity threshold. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_act_thresholds_get(stmdev_ctx_t *ctx, + lsm6dsv_act_thresholds_t *val) +{ + lsm6dsv_inactivity_dur_t inactivity_dur; + lsm6dsv_inactivity_ths_t inactivity_ths; + lsm6dsv_wake_up_ths_t wake_up_ths; + lsm6dsv_wake_up_dur_t wake_up_dur; + int32_t ret; + + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + ret += lsm6dsv_read_reg(ctx, LSM6DSV_INACTIVITY_THS, (uint8_t *)&inactivity_ths, + 1); + ret += lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + ret += lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + + val->inactivity_cfg.wu_inact_ths_w = inactivity_dur.wu_inact_ths_w; + val->inactivity_cfg.xl_inact_odr = inactivity_dur.xl_inact_odr; + val->inactivity_cfg.inact_dur = inactivity_dur.inact_dur; + + val->inactivity_ths = inactivity_ths.inact_ths; + val->threshold = wake_up_ths.wk_ths; + val->duration = wake_up_dur.wake_dur; + + return ret; +} + +/** + * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [set] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_act_wkup_time_windows_set(stmdev_ctx_t *ctx, + lsm6dsv_act_wkup_time_windows_t val) +{ + lsm6dsv_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + wake_up_dur.wake_dur = val.shock; + wake_up_dur.sleep_dur = val.quiet; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + } + + return ret; +} + +/** + * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [get] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_act_wkup_time_windows_get(stmdev_ctx_t *ctx, + lsm6dsv_act_wkup_time_windows_t *val) +{ + lsm6dsv_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + val->shock = wake_up_dur.wake_dur; + val->quiet = wake_up_dur.sleep_dur; + + return ret; +} + +/** + * @} + * + */ diff --git a/sensor/stmemsc/lsm6dsv_STdC/driver/lsm6dsv_reg.h b/sensor/stmemsc/lsm6dsv_STdC/driver/lsm6dsv_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..b946224ecb96d3140986f523394efe819b3a8281 --- /dev/null +++ b/sensor/stmemsc/lsm6dsv_STdC/driver/lsm6dsv_reg.h @@ -0,0 +1,4810 @@ +/** + ****************************************************************************** + * @file lsm6dsv_reg.h + * @author Sensors Software Solution Team + * @brief This file contains all the functions prototypes for the + * lsm6dsv_reg.c driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2022 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef LSM6DSV_REGS_H +#define LSM6DSV_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include + +/** @addtogroup LSM6DSV + * @{ + * + */ + +/** @defgroup Endianness definitions + * @{ + * + */ + +#ifndef DRV_BYTE_ORDER +#ifndef __BYTE_ORDER__ + +#define DRV_LITTLE_ENDIAN 1234 +#define DRV_BIG_ENDIAN 4321 + +/** if _BYTE_ORDER is not defined, choose the endianness of your architecture + * by uncommenting the define which fits your platform endianness + */ +//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN +#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN + +#else /* defined __BYTE_ORDER__ */ + +#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ +#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ +#define DRV_BYTE_ORDER __BYTE_ORDER__ + +#endif /* __BYTE_ORDER__*/ +#endif /* DRV_BYTE_ORDER */ + +/** + * @} + * + */ + +/** @defgroup STMicroelectronics sensors common types + * @{ + * + */ + +#ifndef MEMS_SHARED_TYPES +#define MEMS_SHARED_TYPES + +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} bitwise_t; + +#define PROPERTY_DISABLE (0U) +#define PROPERTY_ENABLE (1U) + +/** @addtogroup Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); +typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); + +typedef struct +{ + /** Component mandatory fields **/ + stmdev_write_ptr write_reg; + stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; + /** Customizable optional pointer **/ + void *handle; +} stmdev_ctx_t; + +/** + * @} + * + */ + +#endif /* MEMS_SHARED_TYPES */ + +#ifndef MEMS_UCF_SHARED_TYPES +#define MEMS_UCF_SHARED_TYPES + +/** @defgroup Generic address-data structure definition + * @brief This structure is useful to load a predefined configuration + * of a sensor. + * You can create a sensor configuration by your own or using + * Unico / Unicleo tools available on STMicroelectronics + * web site. + * + * @{ + * + */ + +typedef struct +{ + uint8_t address; + uint8_t data; +} ucf_line_t; + +/** + * @} + * + */ + +#endif /* MEMS_UCF_SHARED_TYPES */ + +/** + * @} + * + */ + +/** @defgroup LSM6DSV_Infos + * @{ + * + */ + +/** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ +#define LSM6DSV_I2C_ADD_L 0xD5U +#define LSM6DSV_I2C_ADD_H 0xD7U + +/** Device Identification (Who am I) **/ +#define LSM6DSV_ID 0x70U + +/** + * @} + * + */ + +/** @defgroup bitfields page main + * @{ + * + */ + +#define LSM6DSV_FUNC_CFG_ACCESS 0x1U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ois_ctrl_from_ui : 1; + uint8_t spi2_reset : 1; + uint8_t sw_por : 1; + uint8_t fsm_wr_ctrl_en : 1; + uint8_t not_used0 : 2; + uint8_t shub_reg_access : 1; + uint8_t emb_func_reg_access : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t emb_func_reg_access : 1; + uint8_t shub_reg_access : 1; + uint8_t not_used0 : 2; + uint8_t fsm_wr_ctrl_en : 1; + uint8_t sw_por : 1; + uint8_t spi2_reset : 1; + uint8_t ois_ctrl_from_ui : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_func_cfg_access_t; + +#define LSM6DSV_PIN_CTRL 0x2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 5; + uint8_t ibhr_por_en : 1; + uint8_t sdo_pu_en : 1; + uint8_t ois_pu_dis : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ois_pu_dis : 1; + uint8_t sdo_pu_en : 1; + uint8_t ibhr_por_en : 1; + uint8_t not_used0 : 5; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_pin_ctrl_t; + +#define LSM6DSV_IF_CFG 0x3U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t i2c_i3c_disable : 1; + uint8_t not_used0 : 1; + uint8_t sim : 1; + uint8_t pp_od : 1; + uint8_t h_lactive : 1; + uint8_t asf_ctrl : 1; + uint8_t shub_pu_en : 1; + uint8_t sda_pu_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sda_pu_en : 1; + uint8_t shub_pu_en : 1; + uint8_t asf_ctrl : 1; + uint8_t h_lactive : 1; + uint8_t pp_od : 1; + uint8_t sim : 1; + uint8_t not_used0 : 1; + uint8_t i2c_i3c_disable : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_if_cfg_t; + +#define LSM6DSV_FIFO_CTRL1 0x7U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wtm : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t wtm : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fifo_ctrl1_t; + +#define LSM6DSV_FIFO_CTRL2 0x8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xl_dualc_batch_from_fsm : 1; + uint8_t uncompr_rate : 2; + uint8_t not_used0 : 1; + uint8_t odr_chg_en : 1; + uint8_t not_used1 : 1; + uint8_t fifo_compr_rt_en : 1; + uint8_t stop_on_wtm : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t stop_on_wtm : 1; + uint8_t fifo_compr_rt_en : 1; + uint8_t not_used1 : 1; + uint8_t odr_chg_en : 1; + uint8_t not_used0 : 1; + uint8_t uncompr_rate : 2; + uint8_t xl_dualc_batch_from_fsm : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fifo_ctrl2_t; + +#define LSM6DSV_FIFO_CTRL3 0x9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bdr_xl : 4; + uint8_t bdr_gy : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bdr_gy : 4; + uint8_t bdr_xl : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fifo_ctrl3_t; + +#define LSM6DSV_FIFO_CTRL4 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_mode : 3; + uint8_t g_eis_fifo_en : 1; + uint8_t odr_t_batch : 2; + uint8_t dec_ts_batch : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dec_ts_batch : 2; + uint8_t odr_t_batch : 2; + uint8_t g_eis_fifo_en : 1; + uint8_t fifo_mode : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fifo_ctrl4_t; + +#define LSM6DSV_COUNTER_BDR_REG1 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t cnt_bdr_th : 2; + uint8_t not_used0 : 3; + uint8_t trig_counter_bdr : 2; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t trig_counter_bdr : 2; + uint8_t not_used0 : 3; + uint8_t cnt_bdr_th : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_counter_bdr_reg1_t; + +#define LSM6DSV_COUNTER_BDR_REG2 0x0CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t cnt_bdr_th : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t cnt_bdr_th : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_counter_bdr_reg2_t; + +#define LSM6DSV_INT1_CTRL 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_drdy_xl : 1; + uint8_t int1_drdy_g : 1; + uint8_t not_used0 : 1; + uint8_t int1_fifo_th : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_fifo_full : 1; + uint8_t int1_cnt_bdr : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t int1_cnt_bdr : 1; + uint8_t int1_fifo_full : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_fifo_th : 1; + uint8_t not_used0 : 1; + uint8_t int1_drdy_g : 1; + uint8_t int1_drdy_xl : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_int1_ctrl_t; + +#define LSM6DSV_INT2_CTRL 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_drdy_xl : 1; + uint8_t int2_drdy_g : 1; + uint8_t int2_drdy_g_eis : 1; + uint8_t int2_fifo_th : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_fifo_full : 1; + uint8_t int2_cnt_bdr : 1; + uint8_t int2_emb_func_endop : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_emb_func_endop : 1; + uint8_t int2_cnt_bdr : 1; + uint8_t int2_fifo_full : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_fifo_th : 1; + uint8_t int2_drdy_g_eis : 1; + uint8_t int2_drdy_g : 1; + uint8_t int2_drdy_xl : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_int2_ctrl_t; + +#define LSM6DSV_WHO_AM_I 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t id : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t id : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_who_am_i_t; + +#define LSM6DSV_CTRL1 0x10U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t odr_xl : 4; + uint8_t op_mode_xl : 3; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t op_mode_xl : 3; + uint8_t odr_xl : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ctrl1_t; + +#define LSM6DSV_CTRL2 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t odr_g : 4; + uint8_t op_mode_g : 3; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t op_mode_g : 3; + uint8_t odr_g : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ctrl2_t; + +#define LSM6DSV_CTRL3 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sw_reset : 1; + uint8_t not_used0 : 1; + uint8_t if_inc : 1; + uint8_t not_used1 : 3; + uint8_t bdu : 1; + uint8_t boot : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t boot : 1; + uint8_t bdu : 1; + uint8_t not_used1 : 3; + uint8_t if_inc : 1; + uint8_t not_used0 : 1; + uint8_t sw_reset : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ctrl3_t; + +#define LSM6DSV_CTRL4 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_in_lh : 1; + uint8_t drdy_pulsed : 1; + uint8_t int2_drdy_temp : 1; + uint8_t drdy_mask : 1; + uint8_t int2_on_int1 : 1; + uint8_t not_used0 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 3; + uint8_t int2_on_int1 : 1; + uint8_t drdy_mask : 1; + uint8_t int2_drdy_temp : 1; + uint8_t drdy_pulsed : 1; + uint8_t int2_in_lh : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ctrl4_t; + +#define LSM6DSV_CTRL5 0x14U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int_en_i3c : 1; + uint8_t bus_act_sel : 2; + uint8_t not_used0 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 5; + uint8_t bus_act_sel : 2; + uint8_t int_en_i3c : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ctrl5_t; + +#define LSM6DSV_CTRL6 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_g : 4; + uint8_t lpf1_g_bw : 3; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t lpf1_g_bw : 3; + uint8_t fs_g : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ctrl6_t; + +#define LSM6DSV_CTRL7 0x16U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t lpf1_g_en : 1; + uint8_t not_used0 : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 7; + uint8_t lpf1_g_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ctrl7_t; + +#define LSM6DSV_CTRL8 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_xl : 2; + uint8_t not_used0 : 1; + uint8_t xl_dualc_en : 1; + uint8_t not_used1 : 1; + uint8_t hp_lpf2_xl_bw : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t hp_lpf2_xl_bw : 3; + uint8_t not_used1 : 1; + uint8_t xl_dualc_en : 1; + uint8_t not_used0 : 1; + uint8_t fs_xl : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ctrl8_t; + +#define LSM6DSV_CTRL9 0x18U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t usr_off_on_out : 1; + uint8_t usr_off_w : 1; + uint8_t not_used0 : 1; + uint8_t lpf2_xl_en : 1; + uint8_t hp_slope_xl_en : 1; + uint8_t xl_fastsettl_mode : 1; + uint8_t hp_ref_mode_xl : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t hp_ref_mode_xl : 1; + uint8_t xl_fastsettl_mode : 1; + uint8_t hp_slope_xl_en : 1; + uint8_t lpf2_xl_en : 1; + uint8_t not_used0 : 1; + uint8_t usr_off_w : 1; + uint8_t usr_off_on_out : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ctrl9_t; + +#define LSM6DSV_CTRL10 0x19U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t st_xl : 2; + uint8_t st_g : 2; + uint8_t not_used0 : 2; + uint8_t emb_func_debug : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t emb_func_debug : 1; + uint8_t not_used0 : 2; + uint8_t st_g : 2; + uint8_t st_xl : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ctrl10_t; + +#define LSM6DSV_CTRL_STATUS 0x1AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t fsm_wr_ctrl_status : 1; + uint8_t not_used1 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 5; + uint8_t fsm_wr_ctrl_status : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ctrl_status_t; + +#define LSM6DSV_FIFO_STATUS1 0x1BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t diff_fifo : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t diff_fifo : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fifo_status1_t; + +#define LSM6DSV_FIFO_STATUS2 0x1CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t diff_fifo : 1; + uint8_t not_used0 : 2; + uint8_t fifo_ovr_latched : 1; + uint8_t counter_bdr_ia : 1; + uint8_t fifo_full_ia : 1; + uint8_t fifo_ovr_ia : 1; + uint8_t fifo_wtm_ia : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_wtm_ia : 1; + uint8_t fifo_ovr_ia : 1; + uint8_t fifo_full_ia : 1; + uint8_t counter_bdr_ia : 1; + uint8_t fifo_ovr_latched : 1; + uint8_t not_used0 : 2; + uint8_t diff_fifo : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fifo_status2_t; + +#define LSM6DSV_ALL_INT_SRC 0x1DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ff_ia : 1; + uint8_t wu_ia : 1; + uint8_t tap_ia : 1; + uint8_t not_used0 : 1; + uint8_t d6d_ia : 1; + uint8_t sleep_change_ia : 1; + uint8_t shub_ia : 1; + uint8_t emb_func_ia : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t emb_func_ia : 1; + uint8_t shub_ia : 1; + uint8_t sleep_change_ia : 1; + uint8_t d6d_ia : 1; + uint8_t not_used0 : 1; + uint8_t tap_ia : 1; + uint8_t wu_ia : 1; + uint8_t ff_ia : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_all_int_src_t; + +#define LSM6DSV_STATUS_REG 0x1EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xlda : 1; + uint8_t gda : 1; + uint8_t tda : 1; + uint8_t not_used1 : 1; + uint8_t gda_eis : 1; + uint8_t ois_drdy : 1; + uint8_t not_used0 : 1; + uint8_t timestamp_endcount : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp_endcount : 1; + uint8_t not_used0 : 1; + uint8_t ois_drdy : 1; + uint8_t gda_eis : 1; + uint8_t not_used1 : 1; + uint8_t tda : 1; + uint8_t gda : 1; + uint8_t xlda : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_status_reg_t; + +#define LSM6DSV_OUT_TEMP_L 0x20U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t temp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t temp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_out_temp_l_t; + +#define LSM6DSV_OUT_TEMP_H 0x21U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t temp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t temp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_out_temp_h_t; + +#define LSM6DSV_OUTX_L_G 0x22U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_outx_l_g_t; + +#define LSM6DSV_OUTX_H_G 0x23U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_outx_h_g_t; + +#define LSM6DSV_OUTY_L_G 0x24U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_outy_l_g_t; + +#define LSM6DSV_OUTY_H_G 0x25U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_outy_h_g_t; + +#define LSM6DSV_OUTZ_L_G 0x26U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_outz_l_g_t; + +#define LSM6DSV_OUTZ_H_G 0x27U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_outz_h_g_t; + +#define LSM6DSV_OUTX_L_A 0x28U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_outx_l_a_t; + +#define LSM6DSV_OUTX_H_A 0x29U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_outx_h_a_t; + +#define LSM6DSV_OUTY_L_A 0x2AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_outy_l_a_t; + +#define LSM6DSV_OUTY_H_A 0x2BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_outy_h_a_t; + +#define LSM6DSV_OUTZ_L_A 0x2CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_outz_l_a_t; + +#define LSM6DSV_OUTZ_H_A 0x2DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_outz_h_a_t; + +#define LSM6DSV_UI_OUTX_L_G_OIS_EIS 0x2EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outx_g_ois_eis : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outx_g_ois_eis : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ui_outx_l_g_ois_eis_t; + +#define LSM6DSV_UI_OUTX_H_G_OIS_EIS 0x2FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outx_g_ois_eis : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outx_g_ois_eis : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ui_outx_h_g_ois_eis_t; + +#define LSM6DSV_UI_OUTY_L_G_OIS_EIS 0x30U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outy_g_ois_eis : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outy_g_ois_eis : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ui_outy_l_g_ois_eis_t; + +#define LSM6DSV_UI_OUTY_H_G_OIS_EIS 0x31U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outy_g_ois_eis : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outy_g_ois_eis : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ui_outy_h_g_ois_eis_t; + +#define LSM6DSV_UI_OUTZ_L_G_OIS_EIS 0x32U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outz_g_ois_eis : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outz_g_ois_eis : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ui_outz_l_g_ois_eis_t; + +#define LSM6DSV_UI_OUTZ_H_G_OIS_EIS 0x33U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outz_g_ois_eis : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outz_g_ois_eis : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ui_outz_h_g_ois_eis_t; + +#define LSM6DSV_UI_OUTX_L_A_OIS_DUALC 0x34U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outx_a_ois_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outx_a_ois_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ui_outx_l_a_ois_dualc_t; + +#define LSM6DSV_UI_OUTX_H_A_OIS_DUALC 0x35U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outx_a_ois_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outx_a_ois_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ui_outx_h_a_ois_dualc_t; + +#define LSM6DSV_UI_OUTY_L_A_OIS_DUALC 0x36U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outy_a_ois_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outy_a_ois_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ui_outy_l_a_ois_dualc_t; + +#define LSM6DSV_UI_OUTY_H_A_OIS_DUALC 0x37U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outy_a_ois_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outy_a_ois_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ui_outy_h_a_ois_dualc_t; + +#define LSM6DSV_UI_OUTZ_L_A_OIS_DUALC 0x38U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outz_a_ois_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outz_a_ois_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ui_outz_l_a_ois_dualc_t; + +#define LSM6DSV_UI_OUTZ_H_A_OIS_DUALC 0x39U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outz_a_ois_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outz_a_ois_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ui_outz_h_a_ois_dualc_t; + +#define LSM6DSV_TIMESTAMP0 0x40U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_timestamp0_t; + +#define LSM6DSV_TIMESTAMP1 0x41U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_timestamp1_t; + +#define LSM6DSV_TIMESTAMP2 0x42U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_timestamp2_t; + +#define LSM6DSV_TIMESTAMP3 0x43U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_timestamp3_t; + +#define LSM6DSV_UI_STATUS_REG_OIS 0x44U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xlda_ois : 1; + uint8_t gda_ois : 1; + uint8_t gyro_settling : 1; + uint8_t not_used0 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 5; + uint8_t gyro_settling : 1; + uint8_t gda_ois : 1; + uint8_t xlda_ois : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ui_status_reg_ois_t; + +#define LSM6DSV_WAKE_UP_SRC 0x45U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t z_wu : 1; + uint8_t y_wu : 1; + uint8_t x_wu : 1; + uint8_t wu_ia : 1; + uint8_t sleep_state : 1; + uint8_t ff_ia : 1; + uint8_t sleep_change_ia : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t sleep_change_ia : 1; + uint8_t ff_ia : 1; + uint8_t sleep_state : 1; + uint8_t wu_ia : 1; + uint8_t x_wu : 1; + uint8_t y_wu : 1; + uint8_t z_wu : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_wake_up_src_t; + +#define LSM6DSV_TAP_SRC 0x46U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t z_tap : 1; + uint8_t y_tap : 1; + uint8_t x_tap : 1; + uint8_t tap_sign : 1; + uint8_t double_tap : 1; + uint8_t single_tap : 1; + uint8_t tap_ia : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t tap_ia : 1; + uint8_t single_tap : 1; + uint8_t double_tap : 1; + uint8_t tap_sign : 1; + uint8_t x_tap : 1; + uint8_t y_tap : 1; + uint8_t z_tap : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_tap_src_t; + +#define LSM6DSV_D6D_SRC 0x47U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xl : 1; + uint8_t xh : 1; + uint8_t yl : 1; + uint8_t yh : 1; + uint8_t zl : 1; + uint8_t zh : 1; + uint8_t d6d_ia : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t d6d_ia : 1; + uint8_t zh : 1; + uint8_t zl : 1; + uint8_t yh : 1; + uint8_t yl : 1; + uint8_t xh : 1; + uint8_t xl : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_d6d_src_t; + +#define LSM6DSV_EMB_FUNC_STATUS_MAINPAGE 0x49U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t is_step_det : 1; + uint8_t is_tilt : 1; + uint8_t is_sigmot : 1; + uint8_t not_used1 : 1; + uint8_t is_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t is_sigmot : 1; + uint8_t is_tilt : 1; + uint8_t is_step_det : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_emb_func_status_mainpage_t; + +#define LSM6DSV_FSM_STATUS_MAINPAGE 0x4AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm1 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm8 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_status_mainpage_t; + +#define LSM6DSV_INTERNAL_FREQ 0x4FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t freq_fine : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t freq_fine : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_internal_freq_t; + +#define LSM6DSV_FUNCTIONS_ENABLE 0x50U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t inact_en : 2; + uint8_t not_used0 : 1; + uint8_t dis_rst_lir_all_int : 1; + uint8_t not_used1 : 2; + uint8_t timestamp_en : 1; + uint8_t interrupts_enable : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t interrupts_enable : 1; + uint8_t timestamp_en : 1; + uint8_t not_used1 : 2; + uint8_t dis_rst_lir_all_int : 1; + uint8_t not_used0 : 1; + uint8_t inact_en : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_functions_enable_t; + +#define LSM6DSV_DEN 0x51U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t den_xl_g : 1; + uint8_t den_z : 1; + uint8_t den_y : 1; + uint8_t den_x : 1; + uint8_t den_xl_en : 1; + uint8_t lvl2_en : 1; + uint8_t lvl1_en : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t lvl1_en : 1; + uint8_t lvl2_en : 1; + uint8_t den_xl_en : 1; + uint8_t den_x : 1; + uint8_t den_y : 1; + uint8_t den_z : 1; + uint8_t den_xl_g : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_den_t; + +#define LSM6DSV_INACTIVITY_DUR 0x54U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t inact_dur : 2; + uint8_t xl_inact_odr : 2; + uint8_t wu_inact_ths_w : 3; + uint8_t sleep_status_on_int : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sleep_status_on_int : 1; + uint8_t wu_inact_ths_w : 3; + uint8_t xl_inact_odr : 2; + uint8_t inact_dur : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_inactivity_dur_t; + +#define LSM6DSV_INACTIVITY_THS 0x55U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t inact_ths : 6; + uint8_t not_used0 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 2; + uint8_t inact_ths : 6; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_inactivity_ths_t; + +#define LSM6DSV_TAP_CFG0 0x56U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t lir : 1; + uint8_t tap_z_en : 1; + uint8_t tap_y_en : 1; + uint8_t tap_x_en : 1; + uint8_t slope_fds : 1; + uint8_t hw_func_mask_xl_settl : 1; + uint8_t low_pass_on_6d : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t low_pass_on_6d : 1; + uint8_t hw_func_mask_xl_settl : 1; + uint8_t slope_fds : 1; + uint8_t tap_x_en : 1; + uint8_t tap_y_en : 1; + uint8_t tap_z_en : 1; + uint8_t lir : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_tap_cfg0_t; + +#define LSM6DSV_TAP_CFG1 0x57U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tap_ths_x : 5; + uint8_t tap_priority : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tap_priority : 3; + uint8_t tap_ths_x : 5; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_tap_cfg1_t; + +#define LSM6DSV_TAP_CFG2 0x58U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tap_ths_y : 5; + uint8_t not_used0 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 3; + uint8_t tap_ths_y : 5; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_tap_cfg2_t; + +#define LSM6DSV_TAP_THS_6D 0x59U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tap_ths_z : 5; + uint8_t sixd_ths : 2; + uint8_t d4d_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t d4d_en : 1; + uint8_t sixd_ths : 2; + uint8_t tap_ths_z : 5; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_tap_ths_6d_t; + +#define LSM6DSV_TAP_DUR 0x5AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t shock : 2; + uint8_t quiet : 2; + uint8_t dur : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dur : 4; + uint8_t quiet : 2; + uint8_t shock : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_tap_dur_t; + +#define LSM6DSV_WAKE_UP_THS 0x5BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wk_ths : 6; + uint8_t usr_off_on_wu : 1; + uint8_t single_double_tap : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t single_double_tap : 1; + uint8_t usr_off_on_wu : 1; + uint8_t wk_ths : 6; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_wake_up_ths_t; + +#define LSM6DSV_WAKE_UP_DUR 0x5CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sleep_dur : 4; + uint8_t not_used0 : 1; + uint8_t wake_dur : 2; + uint8_t ff_dur : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ff_dur : 1; + uint8_t wake_dur : 2; + uint8_t not_used0 : 1; + uint8_t sleep_dur : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_wake_up_dur_t; + +#define LSM6DSV_FREE_FALL 0x5DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ff_ths : 3; + uint8_t ff_dur : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ff_dur : 5; + uint8_t ff_ths : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_free_fall_t; + +#define LSM6DSV_MD1_CFG 0x5EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_shub : 1; + uint8_t int1_emb_func : 1; + uint8_t int1_6d : 1; + uint8_t int1_double_tap : 1; + uint8_t int1_ff : 1; + uint8_t int1_wu : 1; + uint8_t int1_single_tap : 1; + uint8_t int1_sleep_change : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_sleep_change : 1; + uint8_t int1_single_tap : 1; + uint8_t int1_wu : 1; + uint8_t int1_ff : 1; + uint8_t int1_double_tap : 1; + uint8_t int1_6d : 1; + uint8_t int1_emb_func : 1; + uint8_t int1_shub : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_md1_cfg_t; + +#define LSM6DSV_MD2_CFG 0x5FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_timestamp : 1; + uint8_t int2_emb_func : 1; + uint8_t int2_6d : 1; + uint8_t int2_double_tap : 1; + uint8_t int2_ff : 1; + uint8_t int2_wu : 1; + uint8_t int2_single_tap : 1; + uint8_t int2_sleep_change : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_sleep_change : 1; + uint8_t int2_single_tap : 1; + uint8_t int2_wu : 1; + uint8_t int2_ff : 1; + uint8_t int2_double_tap : 1; + uint8_t int2_6d : 1; + uint8_t int2_emb_func : 1; + uint8_t int2_timestamp : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_md2_cfg_t; + +#define LSM6DSV_EMB_FUNC_CFG 0x63U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t emb_func_disable : 1; + uint8_t emb_func_irq_mask_xl_settl : 1; + uint8_t emb_func_irq_mask_g_settl : 1; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t emb_func_irq_mask_g_settl : 1; + uint8_t emb_func_irq_mask_xl_settl : 1; + uint8_t emb_func_disable : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_emb_func_cfg_t; + +#define LSM6DSV_UI_HANDSHAKE_CTRL 0x64U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_shared_req : 1; + uint8_t ui_shared_ack : 1; + uint8_t not_used0 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 6; + uint8_t ui_shared_ack : 1; + uint8_t ui_shared_req : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ui_handshake_ctrl_t; + +#define LSM6DSV_UI_SPI2_SHARED_0 0x65U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_spi2_shared : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_spi2_shared : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ui_spi2_shared_0_t; + +#define LSM6DSV_UI_SPI2_SHARED_1 0x66U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_spi2_shared : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_spi2_shared : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ui_spi2_shared_1_t; + +#define LSM6DSV_UI_SPI2_SHARED_2 0x67U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_spi2_shared : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_spi2_shared : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ui_spi2_shared_2_t; + +#define LSM6DSV_UI_SPI2_SHARED_3 0x68U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_spi2_shared : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_spi2_shared : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ui_spi2_shared_3_t; + +#define LSM6DSV_UI_SPI2_SHARED_4 0x69U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_spi2_shared : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_spi2_shared : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ui_spi2_shared_4_t; + +#define LSM6DSV_UI_SPI2_SHARED_5 0x6AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_spi2_shared : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_spi2_shared : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ui_spi2_shared_5_t; + +#define LSM6DSV_CTRL_EIS 0x6BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_g_eis : 3; + uint8_t g_eis_on_g_ois_out_reg : 1; + uint8_t lpf_g_eis_bw : 1; + uint8_t not_used0 : 1; + uint8_t odr_g_eis : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t odr_g_eis : 2; + uint8_t not_used0 : 1; + uint8_t lpf_g_eis_bw : 1; + uint8_t g_eis_on_g_ois_out_reg : 1; + uint8_t fs_g_eis : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ctrl_eis_t; + +#define LSM6DSV_UI_INT_OIS 0x6FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 4; + uint8_t st_ois_clampdis : 1; + uint8_t not_used1 : 1; + uint8_t drdy_mask_ois : 1; + uint8_t int2_drdy_ois : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_drdy_ois : 1; + uint8_t drdy_mask_ois : 1; + uint8_t not_used1 : 1; + uint8_t st_ois_clampdis : 1; + uint8_t not_used0 : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ui_int_ois_t; + +#define LSM6DSV_UI_CTRL1_OIS 0x70U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_read_en : 1; + uint8_t ois_g_en : 1; + uint8_t ois_xl_en : 1; + uint8_t not_used0 : 2; + uint8_t sim_ois : 1; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t sim_ois : 1; + uint8_t not_used0 : 2; + uint8_t ois_xl_en : 1; + uint8_t ois_g_en : 1; + uint8_t spi2_read_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ui_ctrl1_ois_t; + +#define LSM6DSV_UI_CTRL2_OIS 0x71U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_g_ois : 3; + uint8_t lpf1_g_ois_bw : 2; + uint8_t not_used0 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 3; + uint8_t lpf1_g_ois_bw : 2; + uint8_t fs_g_ois : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ui_ctrl2_ois_t; + +#define LSM6DSV_UI_CTRL3_OIS 0x72U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_xl_ois : 2; + uint8_t not_used0 : 1; + uint8_t lpf_xl_ois_bw : 3; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t lpf_xl_ois_bw : 3; + uint8_t not_used0 : 1; + uint8_t fs_xl_ois : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ui_ctrl3_ois_t; + +#define LSM6DSV_X_OFS_USR 0x73U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t x_ofs_usr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t x_ofs_usr : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_x_ofs_usr_t; + +#define LSM6DSV_Y_OFS_USR 0x74U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t y_ofs_usr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t y_ofs_usr : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_y_ofs_usr_t; + +#define LSM6DSV_Z_OFS_USR 0x75U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t z_ofs_usr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t z_ofs_usr : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_z_ofs_usr_t; + +#define LSM6DSV_FIFO_DATA_OUT_TAG 0x78U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t tag_cnt : 2; + uint8_t tag_sensor : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tag_sensor : 5; + uint8_t tag_cnt : 2; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fifo_data_out_tag_t; + +#define LSM6DSV_FIFO_DATA_OUT_X_L 0x79U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fifo_data_out_x_l_t; + +#define LSM6DSV_FIFO_DATA_OUT_X_H 0x7AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fifo_data_out_x_h_t; + +#define LSM6DSV_FIFO_DATA_OUT_Y_L 0x7BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fifo_data_out_y_l_t; + +#define LSM6DSV_FIFO_DATA_OUT_Y_H 0x7CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fifo_data_out_y_h_t; + +#define LSM6DSV_FIFO_DATA_OUT_Z_L 0x7DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fifo_data_out_z_l_t; + +#define LSM6DSV_FIFO_DATA_OUT_Z_H 0x7EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fifo_data_out_z_h_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page spi2 + * @{ + * + */ + +#define LSM6DSV_SPI2_WHO_AM_I 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t id : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t id : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_spi2_who_am_i_t; + +#define LSM6DSV_SPI2_STATUS_REG_OIS 0x1EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xlda : 1; + uint8_t gda : 1; + uint8_t gyro_settling : 1; + uint8_t not_used0 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 5; + uint8_t gyro_settling : 1; + uint8_t gda : 1; + uint8_t xlda : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_spi2_status_reg_ois_t; + +#define LSM6DSV_SPI2_OUT_TEMP_L 0x20U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t temp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t temp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_spi2_out_temp_l_t; + +#define LSM6DSV_SPI2_OUT_TEMP_H 0x21U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t temp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t temp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_spi2_out_temp_h_t; + +#define LSM6DSV_SPI2_OUTX_L_G_OIS 0x22U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outx_g_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outx_g_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_spi2_outx_l_g_ois_t; + +#define LSM6DSV_SPI2_OUTX_H_G_OIS 0x23U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outx_g_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outx_g_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_spi2_outx_h_g_ois_t; + +#define LSM6DSV_SPI2_OUTY_L_G_OIS 0x24U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outy_g_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outy_g_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_spi2_outy_l_g_ois_t; + +#define LSM6DSV_SPI2_OUTY_H_G_OIS 0x25U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outy_g_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outy_g_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_spi2_outy_h_g_ois_t; + +#define LSM6DSV_SPI2_OUTZ_L_G_OIS 0x26U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outz_g_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outz_g_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_spi2_outz_l_g_ois_t; + +#define LSM6DSV_SPI2_OUTZ_H_G_OIS 0x27U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outz_g_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outz_g_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_spi2_outz_h_g_ois_t; + +#define LSM6DSV_SPI2_OUTX_L_A_OIS 0x28U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outx_a_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outx_a_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_spi2_outx_l_a_ois_t; + +#define LSM6DSV_SPI2_OUTX_H_A_OIS 0x29U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outx_a_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outx_a_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_spi2_outx_h_a_ois_t; + +#define LSM6DSV_SPI2_OUTY_L_A_OIS 0x2AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outy_a_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outy_a_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_spi2_outy_l_a_ois_t; + +#define LSM6DSV_SPI2_OUTY_H_A_OIS 0x2BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outy_a_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outy_a_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_spi2_outy_h_a_ois_t; + +#define LSM6DSV_SPI2_OUTZ_L_A_OIS 0x2CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outz_a_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outz_a_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_spi2_outz_l_a_ois_t; + +#define LSM6DSV_SPI2_OUTZ_H_A_OIS 0x2DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outz_a_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outz_a_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_spi2_outz_h_a_ois_t; + +#define LSM6DSV_SPI2_HANDSHAKE_CTRL 0x6EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_shared_ack : 1; + uint8_t spi2_shared_req : 1; + uint8_t not_used0 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 6; + uint8_t spi2_shared_req : 1; + uint8_t spi2_shared_ack : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_spi2_handshake_ctrl_t; + +#define LSM6DSV_SPI2_INT_OIS 0x6FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t st_xl_ois : 2; + uint8_t st_g_ois : 2; + uint8_t st_ois_clampdis : 1; + uint8_t not_used0 : 1; + uint8_t drdy_mask_ois : 1; + uint8_t int2_drdy_ois : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_drdy_ois : 1; + uint8_t drdy_mask_ois : 1; + uint8_t not_used0 : 1; + uint8_t st_ois_clampdis : 1; + uint8_t st_g_ois : 2; + uint8_t st_xl_ois : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_spi2_int_ois_t; + +#define LSM6DSV_SPI2_CTRL1_OIS 0x70U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_read_en : 1; + uint8_t ois_g_en : 1; + uint8_t ois_xl_en : 1; + uint8_t not_used0 : 2; + uint8_t sim_ois : 1; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t sim_ois : 1; + uint8_t not_used0 : 2; + uint8_t ois_xl_en : 1; + uint8_t ois_g_en : 1; + uint8_t spi2_read_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_spi2_ctrl1_ois_t; + +#define LSM6DSV_SPI2_CTRL2_OIS 0x71U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_g_ois : 3; + uint8_t lpf1_g_ois_bw : 2; + uint8_t not_used0 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 3; + uint8_t lpf1_g_ois_bw : 2; + uint8_t fs_g_ois : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_spi2_ctrl2_ois_t; + +#define LSM6DSV_SPI2_CTRL3_OIS 0x72U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_xl_ois : 2; + uint8_t not_used0 : 1; + uint8_t lpf_xl_ois_bw : 3; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t lpf_xl_ois_bw : 3; + uint8_t not_used0 : 1; + uint8_t fs_xl_ois : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_spi2_ctrl3_ois_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page embedded + * @{ + * + */ + +#define LSM6DSV_PAGE_SEL 0x2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 4; + uint8_t page_sel : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_sel : 4; + uint8_t not_used0 : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_page_sel_t; + +#define LSM6DSV_EMB_FUNC_EN_A 0x4U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t pedo_en : 1; + uint8_t tilt_en : 1; + uint8_t sign_motion_en : 1; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t sign_motion_en : 1; + uint8_t tilt_en : 1; + uint8_t pedo_en : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_emb_func_en_a_t; + +#define LSM6DSV_EMB_FUNC_EN_B 0x5U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_en : 1; + uint8_t not_used0 : 2; + uint8_t fifo_compr_en : 1; + uint8_t not_used1 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 4; + uint8_t fifo_compr_en : 1; + uint8_t not_used0 : 2; + uint8_t fsm_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_emb_func_en_b_t; + +#define LSM6DSV_EMB_FUNC_EXEC_STATUS 0x7U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t emb_func_endop : 1; + uint8_t emb_func_exec_ovr : 1; + uint8_t not_used0 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 6; + uint8_t emb_func_exec_ovr : 1; + uint8_t emb_func_endop : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_emb_func_exec_status_t; + +#define LSM6DSV_PAGE_ADDRESS 0x8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t page_addr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_addr : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_page_address_t; + +#define LSM6DSV_PAGE_VALUE 0x9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t page_value : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_value : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_page_value_t; + +#define LSM6DSV_EMB_FUNC_INT1 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t int1_step_detector : 1; + uint8_t int1_tilt : 1; + uint8_t int1_sig_mot : 1; + uint8_t not_used1 : 1; + uint8_t int1_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t int1_sig_mot : 1; + uint8_t int1_tilt : 1; + uint8_t int1_step_detector : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_emb_func_int1_t; + +#define LSM6DSV_FSM_INT1 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_fsm1 : 1; + uint8_t int1_fsm2 : 1; + uint8_t int1_fsm3 : 1; + uint8_t int1_fsm4 : 1; + uint8_t int1_fsm5 : 1; + uint8_t int1_fsm6 : 1; + uint8_t int1_fsm7 : 1; + uint8_t int1_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_fsm8 : 1; + uint8_t int1_fsm7 : 1; + uint8_t int1_fsm6 : 1; + uint8_t int1_fsm5 : 1; + uint8_t int1_fsm4 : 1; + uint8_t int1_fsm3 : 1; + uint8_t int1_fsm2 : 1; + uint8_t int1_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_int1_t; + +#define LSM6DSV_EMB_FUNC_INT2 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t int2_step_detector : 1; + uint8_t int2_tilt : 1; + uint8_t int2_sig_mot : 1; + uint8_t not_used1 : 1; + uint8_t int2_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t int2_sig_mot : 1; + uint8_t int2_tilt : 1; + uint8_t int2_step_detector : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_emb_func_int2_t; + +#define LSM6DSV_FSM_INT2 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_fsm1 : 1; + uint8_t int2_fsm2 : 1; + uint8_t int2_fsm3 : 1; + uint8_t int2_fsm4 : 1; + uint8_t int2_fsm5 : 1; + uint8_t int2_fsm6 : 1; + uint8_t int2_fsm7 : 1; + uint8_t int2_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_fsm8 : 1; + uint8_t int2_fsm7 : 1; + uint8_t int2_fsm6 : 1; + uint8_t int2_fsm5 : 1; + uint8_t int2_fsm4 : 1; + uint8_t int2_fsm3 : 1; + uint8_t int2_fsm2 : 1; + uint8_t int2_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_int2_t; + +#define LSM6DSV_EMB_FUNC_STATUS 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t is_step_det : 1; + uint8_t is_tilt : 1; + uint8_t is_sigmot : 1; + uint8_t not_used1 : 1; + uint8_t is_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t is_sigmot : 1; + uint8_t is_tilt : 1; + uint8_t is_step_det : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ + +} lsm6dsv_emb_func_status_t; + +#define LSM6DSV_FSM_STATUS 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm1 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm8 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ + +} lsm6dsv_fsm_status_t; + +#define LSM6DSV_PAGE_RW 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 5; + uint8_t page_read : 1; + uint8_t page_write : 1; + uint8_t emb_func_lir : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t emb_func_lir : 1; + uint8_t page_write : 1; + uint8_t page_read : 1; + uint8_t not_used0 : 5; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_page_rw_t; + +#define LSM6DSV_EMB_FUNC_FIFO_EN_A 0x44U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 6; + uint8_t step_counter_fifo_en : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t step_counter_fifo_en : 1; + uint8_t not_used0 : 6; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_emb_func_fifo_en_a_t; + +#define LSM6DSV_FSM_ENABLE 0x46U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm1_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm8_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm8_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm1_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_enable_t; + +#define LSM6DSV_FSM_LONG_COUNTER_L 0x48U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_long_counter_l_t; + +#define LSM6DSV_FSM_LONG_COUNTER_H 0x49U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_long_counter_h_t; + +#define LSM6DSV_INT_ACK_MASK 0x4BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t iack_mask : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t iack_mask : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_int_ack_mask_t; + +#define LSM6DSV_FSM_OUTS1 0x4CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm1_n_v : 1; + uint8_t fsm1_p_v : 1; + uint8_t fsm1_n_z : 1; + uint8_t fsm1_p_z : 1; + uint8_t fsm1_n_y : 1; + uint8_t fsm1_p_y : 1; + uint8_t fsm1_n_x : 1; + uint8_t fsm1_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm1_p_x : 1; + uint8_t fsm1_n_x : 1; + uint8_t fsm1_p_y : 1; + uint8_t fsm1_n_y : 1; + uint8_t fsm1_p_z : 1; + uint8_t fsm1_n_z : 1; + uint8_t fsm1_p_v : 1; + uint8_t fsm1_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_outs1_t; + +#define LSM6DSV_FSM_OUTS2 0x4DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm2_n_v : 1; + uint8_t fsm2_p_v : 1; + uint8_t fsm2_n_z : 1; + uint8_t fsm2_p_z : 1; + uint8_t fsm2_n_y : 1; + uint8_t fsm2_p_y : 1; + uint8_t fsm2_n_x : 1; + uint8_t fsm2_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm2_p_x : 1; + uint8_t fsm2_n_x : 1; + uint8_t fsm2_p_y : 1; + uint8_t fsm2_n_y : 1; + uint8_t fsm2_p_z : 1; + uint8_t fsm2_n_z : 1; + uint8_t fsm2_p_v : 1; + uint8_t fsm2_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_outs2_t; + +#define LSM6DSV_FSM_OUTS3 0x4EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm3_n_v : 1; + uint8_t fsm3_p_v : 1; + uint8_t fsm3_n_z : 1; + uint8_t fsm3_p_z : 1; + uint8_t fsm3_n_y : 1; + uint8_t fsm3_p_y : 1; + uint8_t fsm3_n_x : 1; + uint8_t fsm3_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm3_p_x : 1; + uint8_t fsm3_n_x : 1; + uint8_t fsm3_p_y : 1; + uint8_t fsm3_n_y : 1; + uint8_t fsm3_p_z : 1; + uint8_t fsm3_n_z : 1; + uint8_t fsm3_p_v : 1; + uint8_t fsm3_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_outs3_t; + +#define LSM6DSV_FSM_OUTS4 0x4FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm4_n_v : 1; + uint8_t fsm4_p_v : 1; + uint8_t fsm4_n_z : 1; + uint8_t fsm4_p_z : 1; + uint8_t fsm4_n_y : 1; + uint8_t fsm4_p_y : 1; + uint8_t fsm4_n_x : 1; + uint8_t fsm4_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm4_p_x : 1; + uint8_t fsm4_n_x : 1; + uint8_t fsm4_p_y : 1; + uint8_t fsm4_n_y : 1; + uint8_t fsm4_p_z : 1; + uint8_t fsm4_n_z : 1; + uint8_t fsm4_p_v : 1; + uint8_t fsm4_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_outs4_t; + +#define LSM6DSV_FSM_OUTS5 0x50U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm5_n_v : 1; + uint8_t fsm5_p_v : 1; + uint8_t fsm5_n_z : 1; + uint8_t fsm5_p_z : 1; + uint8_t fsm5_n_y : 1; + uint8_t fsm5_p_y : 1; + uint8_t fsm5_n_x : 1; + uint8_t fsm5_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm5_p_x : 1; + uint8_t fsm5_n_x : 1; + uint8_t fsm5_p_y : 1; + uint8_t fsm5_n_y : 1; + uint8_t fsm5_p_z : 1; + uint8_t fsm5_n_z : 1; + uint8_t fsm5_p_v : 1; + uint8_t fsm5_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_outs5_t; + +#define LSM6DSV_FSM_OUTS6 0x51U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm6_n_v : 1; + uint8_t fsm6_p_v : 1; + uint8_t fsm6_n_z : 1; + uint8_t fsm6_p_z : 1; + uint8_t fsm6_n_y : 1; + uint8_t fsm6_p_y : 1; + uint8_t fsm6_n_x : 1; + uint8_t fsm6_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm6_p_x : 1; + uint8_t fsm6_n_x : 1; + uint8_t fsm6_p_y : 1; + uint8_t fsm6_n_y : 1; + uint8_t fsm6_p_z : 1; + uint8_t fsm6_n_z : 1; + uint8_t fsm6_p_v : 1; + uint8_t fsm6_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_outs6_t; + +#define LSM6DSV_FSM_OUTS7 0x52U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm7_n_v : 1; + uint8_t fsm7_p_v : 1; + uint8_t fsm7_n_z : 1; + uint8_t fsm7_p_z : 1; + uint8_t fsm7_n_y : 1; + uint8_t fsm7_p_y : 1; + uint8_t fsm7_n_x : 1; + uint8_t fsm7_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm7_p_x : 1; + uint8_t fsm7_n_x : 1; + uint8_t fsm7_p_y : 1; + uint8_t fsm7_n_y : 1; + uint8_t fsm7_p_z : 1; + uint8_t fsm7_n_z : 1; + uint8_t fsm7_p_v : 1; + uint8_t fsm7_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_outs7_t; + +#define LSM6DSV_FSM_OUTS8 0x53U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm8_n_v : 1; + uint8_t fsm8_p_v : 1; + uint8_t fsm8_n_z : 1; + uint8_t fsm8_p_z : 1; + uint8_t fsm8_n_y : 1; + uint8_t fsm8_p_y : 1; + uint8_t fsm8_n_x : 1; + uint8_t fsm8_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm8_p_x : 1; + uint8_t fsm8_n_x : 1; + uint8_t fsm8_p_y : 1; + uint8_t fsm8_n_y : 1; + uint8_t fsm8_p_z : 1; + uint8_t fsm8_n_z : 1; + uint8_t fsm8_p_v : 1; + uint8_t fsm8_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_outs8_t; + +#define LSM6DSV_FSM_ODR 0x5FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t fsm_odr : 3; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t fsm_odr : 3; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ + +} lsm6dsv_fsm_odr_t; + +#define LSM6DSV_STEP_COUNTER_L 0x62U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t step : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t step : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_step_counter_l_t; + +#define LSM6DSV_STEP_COUNTER_H 0x63U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t step : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t step : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_step_counter_h_t; + +#define LSM6DSV_EMB_FUNC_SRC 0x64U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t stepcounter_bit_set : 1; + uint8_t step_overflow : 1; + uint8_t step_count_delta_ia : 1; + uint8_t step_detected : 1; + uint8_t not_used1 : 1; + uint8_t pedo_rst_step : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pedo_rst_step : 1; + uint8_t not_used1 : 1; + uint8_t step_detected : 1; + uint8_t step_count_delta_ia : 1; + uint8_t step_overflow : 1; + uint8_t stepcounter_bit_set : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_emb_func_src_t; + +#define LSM6DSV_EMB_FUNC_INIT_A 0x66U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t step_det_init : 1; + uint8_t tilt_init : 1; + uint8_t sig_mot_init : 1; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t sig_mot_init : 1; + uint8_t tilt_init : 1; + uint8_t step_det_init : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_emb_func_init_a_t; + +#define LSM6DSV_EMB_FUNC_INIT_B 0x67U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_init : 1; + uint8_t not_used0 : 2; + uint8_t fifo_compr_init : 1; + uint8_t not_used1 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 4; + uint8_t fifo_compr_init : 1; + uint8_t not_used0 : 2; + uint8_t fsm_init : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_emb_func_init_b_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page pg0_emb_adv + * @{ + * + */ +#define LSM6DSV_EMB_ADV_PG_0 0x000U + +#define LSM6DSV_FSM_EXT_SENSITIVITY_L 0xBAU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_s : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_ext_sensitivity_l_t; + +#define LSM6DSV_FSM_EXT_SENSITIVITY_H 0xBBU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_s : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_ext_sensitivity_h_t; + +#define LSM6DSV_FSM_EXT_OFFX_L 0xC0U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_offx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_offx : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_ext_offx_l_t; + +#define LSM6DSV_FSM_EXT_OFFX_H 0xC1U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_offx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_offx : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_ext_offx_h_t; + +#define LSM6DSV_FSM_EXT_OFFY_L 0xC2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_offy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_offy : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_ext_offy_l_t; + +#define LSM6DSV_FSM_EXT_OFFY_H 0xC3U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_offy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_offy : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_ext_offy_h_t; + +#define LSM6DSV_FSM_EXT_OFFZ_L 0xC4U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_offz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_offz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_ext_offz_l_t; + +#define LSM6DSV_FSM_EXT_OFFZ_H 0xC5U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_offz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_offz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_ext_offz_h_t; + +#define LSM6DSV_FSM_EXT_MATRIX_XX_L 0xC6U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_xx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_xx : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_ext_matrix_xx_l_t; + +#define LSM6DSV_FSM_EXT_MATRIX_XX_H 0xC7U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_xx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_xx : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_ext_matrix_xx_h_t; + +#define LSM6DSV_FSM_EXT_MATRIX_XY_L 0xC8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_xy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_xy : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_ext_matrix_xy_l_t; + +#define LSM6DSV_FSM_EXT_MATRIX_XY_H 0xC9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_xy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_xy : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_ext_matrix_xy_h_t; + +#define LSM6DSV_FSM_EXT_MATRIX_XZ_L 0xCAU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_xz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_xz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_ext_matrix_xz_l_t; + +#define LSM6DSV_FSM_EXT_MATRIX_XZ_H 0xCBU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_xz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_xz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_ext_matrix_xz_h_t; + +#define LSM6DSV_FSM_EXT_MATRIX_YY_L 0xCCU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_yy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_yy : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_ext_matrix_yy_l_t; + +#define LSM6DSV_FSM_EXT_MATRIX_YY_H 0xCDU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_yy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_yy : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_ext_matrix_yy_h_t; + +#define LSM6DSV_FSM_EXT_MATRIX_YZ_L 0xCEU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_yz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_yz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_ext_matrix_yz_l_t; + +#define LSM6DSV_FSM_EXT_MATRIX_YZ_H 0xCFU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_yz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_yz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_ext_matrix_yz_h_t; + +#define LSM6DSV_FSM_EXT_MATRIX_ZZ_L 0xD0U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_zz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_zz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_ext_matrix_zz_l_t; + +#define LSM6DSV_FSM_EXT_MATRIX_ZZ_H 0xD1U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_zz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_zz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_ext_matrix_zz_h_t; + +#define LSM6DSV_EXT_CFG_A 0xD4U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ext_z_axis : 3; + uint8_t not_used0 : 1; + uint8_t ext_y_axis : 3; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t ext_y_axis : 3; + uint8_t not_used0 : 1; + uint8_t ext_z_axis : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ext_cfg_a_t; + +#define LSM6DSV_EXT_CFG_B 0xD5U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ext_x_axis : 3; + uint8_t not_used0 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 5; + uint8_t ext_x_axis : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ext_cfg_b_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page pg1_emb_adv + * @{ + * + */ +#define LSM6DSV_EMB_ADV_PG_1 0x100U + +#define LSM6DSV_FSM_LC_TIMEOUT_L 0x7AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc_timeout : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc_timeout : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_lc_timeout_l_t; + +#define LSM6DSV_FSM_LC_TIMEOUT_H 0x7BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc_timeout : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc_timeout : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_lc_timeout_h_t; + +#define LSM6DSV_FSM_PROGRAMS 0x7CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_n_prog : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_n_prog : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_programs_t; + +#define LSM6DSV_FSM_START_ADD_L 0x7EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_start : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_start : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_start_add_l_t; + +#define LSM6DSV_FSM_START_ADD_H 0x7FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_start : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_start : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_fsm_start_add_h_t; + +#define LSM6DSV_PEDO_CMD_REG 0x83U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t carry_count_en : 1; + uint8_t not_used1 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 4; + uint8_t carry_count_en : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_pedo_cmd_reg_t; + +#define LSM6DSV_PEDO_DEB_STEPS_CONF 0x84U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t deb_step : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t deb_step : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_pedo_deb_steps_conf_t; + +#define LSM6DSV_PEDO_SC_DELTAT_L 0xD0U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t pd_sc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pd_sc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_pedo_sc_deltat_l_t; + +#define LSM6DSV_PEDO_SC_DELTAT_H 0xD1U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t pd_sc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pd_sc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_pedo_sc_deltat_h_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page pg2_emb_adv + * @{ + * + */ +#define LSM6DSV_EMB_ADV_PG_2 0x200U + +#define LSM6DSV_EXT_FORMAT 0x00 +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t ext_format_sel : 1; + uint8_t not_used1 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 5; + uint8_t ext_format_sel : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ext_format_t; + +#define LSM6DSV_EXT_3BYTE_SENSITIVITY_L 0x02U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ext_3byte_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ext_3byte_s : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ext_3byte_sensitivity_l_t; + +#define LSM6DSV_EXT_3BYTE_SENSITIVITY_H 0x03U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ext_3byte_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ext_3byte_s : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ext_3byte_sensitivity_h_t; + +#define LSM6DSV_EXT_3BYTE_OFFSET_XL 0x06U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ext_3byte_off : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ext_3byte_off : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ext_3byte_offset_xl_t; + +#define LSM6DSV_EXT_3BYTE_OFFSET_L 0x07U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ext_3byte_off : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ext_3byte_off : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ext_3byte_offset_l_t; + +#define LSM6DSV_EXT_3BYTE_OFFSET_H 0x08U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ext_3byte_off : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ext_3byte_off : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_ext_3byte_offset_h_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page sensor_hub + * @{ + * + */ + +#define LSM6DSV_SENSOR_HUB_1 0x2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub1 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub1 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_sensor_hub_1_t; + +#define LSM6DSV_SENSOR_HUB_2 0x3U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub2 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub2 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_sensor_hub_2_t; + +#define LSM6DSV_SENSOR_HUB_3 0x4U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub3 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub3 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_sensor_hub_3_t; + +#define LSM6DSV_SENSOR_HUB_4 0x5U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub4 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub4 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_sensor_hub_4_t; + +#define LSM6DSV_SENSOR_HUB_5 0x6U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub5 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub5 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_sensor_hub_5_t; + +#define LSM6DSV_SENSOR_HUB_6 0x7U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub6 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub6 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_sensor_hub_6_t; + +#define LSM6DSV_SENSOR_HUB_7 0x8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub7 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub7 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_sensor_hub_7_t; + +#define LSM6DSV_SENSOR_HUB_8 0x9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub8 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub8 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_sensor_hub_8_t; + +#define LSM6DSV_SENSOR_HUB_9 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub9 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub9 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_sensor_hub_9_t; + +#define LSM6DSV_SENSOR_HUB_10 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub10 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub10 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_sensor_hub_10_t; + +#define LSM6DSV_SENSOR_HUB_11 0x0CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub11 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub11 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_sensor_hub_11_t; + +#define LSM6DSV_SENSOR_HUB_12 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub12 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub12 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_sensor_hub_12_t; + +#define LSM6DSV_SENSOR_HUB_13 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub13 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub13 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_sensor_hub_13_t; + +#define LSM6DSV_SENSOR_HUB_14 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub14 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub14 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_sensor_hub_14_t; + +#define LSM6DSV_SENSOR_HUB_15 0x10U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub15 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub15 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_sensor_hub_15_t; + +#define LSM6DSV_SENSOR_HUB_16 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub16 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub16 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_sensor_hub_16_t; + +#define LSM6DSV_SENSOR_HUB_17 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub17 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub17 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_sensor_hub_17_t; + +#define LSM6DSV_SENSOR_HUB_18 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub18 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub18 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_sensor_hub_18_t; + +#define LSM6DSV_MASTER_CONFIG 0x14U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t aux_sens_on : 2; + uint8_t master_on : 1; + uint8_t not_used0 : 1; + uint8_t pass_through_mode : 1; + uint8_t start_config : 1; + uint8_t write_once : 1; + uint8_t rst_master_regs : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t rst_master_regs : 1; + uint8_t write_once : 1; + uint8_t start_config : 1; + uint8_t pass_through_mode : 1; + uint8_t not_used0 : 1; + uint8_t master_on : 1; + uint8_t aux_sens_on : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_master_config_t; + +#define LSM6DSV_SLV0_ADD 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t rw_0 : 1; + uint8_t slave0_add : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave0_add : 7; + uint8_t rw_0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_slv0_add_t; + +#define LSM6DSV_SLV0_SUBADD 0x16U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave0_reg : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave0_reg : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_slv0_subadd_t; + +#define LSM6DSV_SLV0_CONFIG 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave0_numop : 3; + uint8_t batch_ext_sens_0_en : 1; + uint8_t not_used0 : 1; + uint8_t shub_odr : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t shub_odr : 3; + uint8_t not_used0 : 1; + uint8_t batch_ext_sens_0_en : 1; + uint8_t slave0_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_slv0_config_t; + +#define LSM6DSV_SLV1_ADD 0x18U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t r_1 : 1; + uint8_t slave1_add : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave1_add : 7; + uint8_t r_1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_slv1_add_t; + +#define LSM6DSV_SLV1_SUBADD 0x19U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave1_reg : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave1_reg : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_slv1_subadd_t; + +#define LSM6DSV_SLV1_CONFIG 0x1AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave1_numop : 3; + uint8_t batch_ext_sens_1_en : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t batch_ext_sens_1_en : 1; + uint8_t slave1_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_slv1_config_t; + +#define LSM6DSV_SLV2_ADD 0x1BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t r_2 : 1; + uint8_t slave2_add : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave2_add : 7; + uint8_t r_2 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_slv2_add_t; + +#define LSM6DSV_SLV2_SUBADD 0x1CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave2_reg : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave2_reg : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_slv2_subadd_t; + +#define LSM6DSV_SLV2_CONFIG 0x1DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave2_numop : 3; + uint8_t batch_ext_sens_2_en : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t batch_ext_sens_2_en : 1; + uint8_t slave2_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_slv2_config_t; + +#define LSM6DSV_SLV3_ADD 0x1EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t r_3 : 1; + uint8_t slave3_add : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave3_add : 7; + uint8_t r_3 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_slv3_add_t; + +#define LSM6DSV_SLV3_SUBADD 0x1FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave3_reg : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave3_reg : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_slv3_subadd_t; + +#define LSM6DSV_SLV3_CONFIG 0x20U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave3_numop : 3; + uint8_t batch_ext_sens_3_en : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t batch_ext_sens_3_en : 1; + uint8_t slave3_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_slv3_config_t; + +#define LSM6DSV_DATAWRITE_SLV0 0x21U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave0_dataw : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave0_dataw : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_datawrite_slv0_t; + +#define LSM6DSV_STATUS_MASTER 0x22U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sens_hub_endop : 1; + uint8_t not_used0 : 2; + uint8_t slave0_nack : 1; + uint8_t slave1_nack : 1; + uint8_t slave2_nack : 1; + uint8_t slave3_nack : 1; + uint8_t wr_once_done : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t wr_once_done : 1; + uint8_t slave3_nack : 1; + uint8_t slave2_nack : 1; + uint8_t slave1_nack : 1; + uint8_t slave0_nack : 1; + uint8_t not_used0 : 2; + uint8_t sens_hub_endop : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv_status_master_t; + +/** + * @} + * + */ + +typedef union +{ + lsm6dsv_func_cfg_access_t func_cfg_access; + lsm6dsv_pin_ctrl_t pin_ctrl; + lsm6dsv_if_cfg_t if_cfg; + lsm6dsv_fifo_ctrl1_t fifo_ctrl1; + lsm6dsv_fifo_ctrl2_t fifo_ctrl2; + lsm6dsv_fifo_ctrl3_t fifo_ctrl3; + lsm6dsv_fifo_ctrl4_t fifo_ctrl4; + lsm6dsv_counter_bdr_reg1_t counter_bdr_reg1; + lsm6dsv_counter_bdr_reg2_t counter_bdr_reg2; + lsm6dsv_int1_ctrl_t int1_ctrl; + lsm6dsv_int2_ctrl_t int2_ctrl; + lsm6dsv_who_am_i_t who_am_i; + lsm6dsv_ctrl1_t ctrl1; + lsm6dsv_ctrl2_t ctrl2; + lsm6dsv_ctrl3_t ctrl3; + lsm6dsv_ctrl4_t ctrl4; + lsm6dsv_ctrl5_t ctrl5; + lsm6dsv_ctrl6_t ctrl6; + lsm6dsv_ctrl7_t ctrl7; + lsm6dsv_ctrl8_t ctrl8; + lsm6dsv_ctrl9_t ctrl9; + lsm6dsv_ctrl10_t ctrl10; + lsm6dsv_ctrl_status_t ctrl_status; + lsm6dsv_fifo_status1_t fifo_status1; + lsm6dsv_fifo_status2_t fifo_status2; + lsm6dsv_all_int_src_t all_int_src; + lsm6dsv_status_reg_t status_reg; + lsm6dsv_out_temp_l_t out_temp_l; + lsm6dsv_out_temp_h_t out_temp_h; + lsm6dsv_outx_l_g_t outx_l_g; + lsm6dsv_outx_h_g_t outx_h_g; + lsm6dsv_outy_l_g_t outy_l_g; + lsm6dsv_outy_h_g_t outy_h_g; + lsm6dsv_outz_l_g_t outz_l_g; + lsm6dsv_outz_h_g_t outz_h_g; + lsm6dsv_outx_l_a_t outx_l_a; + lsm6dsv_outx_h_a_t outx_h_a; + lsm6dsv_outy_l_a_t outy_l_a; + lsm6dsv_outy_h_a_t outy_h_a; + lsm6dsv_outz_l_a_t outz_l_a; + lsm6dsv_outz_h_a_t outz_h_a; + lsm6dsv_ui_outx_l_g_ois_eis_t ui_outx_l_g_ois_eis; + lsm6dsv_ui_outx_h_g_ois_eis_t ui_outx_h_g_ois_eis; + lsm6dsv_ui_outy_l_g_ois_eis_t ui_outy_l_g_ois_eis; + lsm6dsv_ui_outy_h_g_ois_eis_t ui_outy_h_g_ois_eis; + lsm6dsv_ui_outz_l_g_ois_eis_t ui_outz_l_g_ois_eis; + lsm6dsv_ui_outz_h_g_ois_eis_t ui_outz_h_g_ois_eis; + lsm6dsv_ui_outx_l_a_ois_dualc_t ui_outx_l_a_ois_dualc; + lsm6dsv_ui_outx_h_a_ois_dualc_t ui_outx_h_a_ois_dualc; + lsm6dsv_ui_outy_l_a_ois_dualc_t ui_outy_l_a_ois_dualc; + lsm6dsv_ui_outy_h_a_ois_dualc_t ui_outy_h_a_ois_dualc; + lsm6dsv_ui_outz_l_a_ois_dualc_t ui_outz_l_a_ois_dualc; + lsm6dsv_ui_outz_h_a_ois_dualc_t ui_outz_h_a_ois_dualc; + lsm6dsv_timestamp0_t timestamp0; + lsm6dsv_timestamp1_t timestamp1; + lsm6dsv_timestamp2_t timestamp2; + lsm6dsv_timestamp3_t timestamp3; + lsm6dsv_ui_status_reg_ois_t ui_status_reg_ois; + lsm6dsv_wake_up_src_t wake_up_src; + lsm6dsv_tap_src_t tap_src; + lsm6dsv_d6d_src_t d6d_src; + lsm6dsv_emb_func_status_mainpage_t emb_func_status_mainpage; + lsm6dsv_fsm_status_mainpage_t fsm_status_mainpage; + lsm6dsv_internal_freq_t internal_freq; + lsm6dsv_functions_enable_t functions_enable; + lsm6dsv_den_t den; + lsm6dsv_inactivity_dur_t inactivity_dur; + lsm6dsv_inactivity_ths_t inactivity_ths; + lsm6dsv_tap_cfg0_t tap_cfg0; + lsm6dsv_tap_cfg1_t tap_cfg1; + lsm6dsv_tap_cfg2_t tap_cfg2; + lsm6dsv_tap_ths_6d_t tap_ths_6d; + lsm6dsv_tap_dur_t tap_dur; + lsm6dsv_wake_up_ths_t wake_up_ths; + lsm6dsv_wake_up_dur_t wake_up_dur; + lsm6dsv_free_fall_t free_fall; + lsm6dsv_md1_cfg_t md1_cfg; + lsm6dsv_md2_cfg_t md2_cfg; + lsm6dsv_emb_func_cfg_t emb_func_cfg; + lsm6dsv_ui_handshake_ctrl_t ui_handshake_ctrl; + lsm6dsv_ui_spi2_shared_0_t ui_spi2_shared_0; + lsm6dsv_ui_spi2_shared_1_t ui_spi2_shared_1; + lsm6dsv_ui_spi2_shared_2_t ui_spi2_shared_2; + lsm6dsv_ui_spi2_shared_3_t ui_spi2_shared_3; + lsm6dsv_ui_spi2_shared_4_t ui_spi2_shared_4; + lsm6dsv_ui_spi2_shared_5_t ui_spi2_shared_5; + lsm6dsv_ctrl_eis_t ctrl_eis; + lsm6dsv_ui_int_ois_t ui_int_ois; + lsm6dsv_ui_ctrl1_ois_t ui_ctrl1_ois; + lsm6dsv_ui_ctrl2_ois_t ui_ctrl2_ois; + lsm6dsv_ui_ctrl3_ois_t ui_ctrl3_ois; + lsm6dsv_x_ofs_usr_t x_ofs_usr; + lsm6dsv_y_ofs_usr_t y_ofs_usr; + lsm6dsv_z_ofs_usr_t z_ofs_usr; + lsm6dsv_fifo_data_out_tag_t fifo_data_out_tag; + lsm6dsv_fifo_data_out_x_l_t fifo_data_out_x_l; + lsm6dsv_fifo_data_out_x_h_t fifo_data_out_x_h; + lsm6dsv_fifo_data_out_y_l_t fifo_data_out_y_l; + lsm6dsv_fifo_data_out_y_h_t fifo_data_out_y_h; + lsm6dsv_fifo_data_out_z_l_t fifo_data_out_z_l; + lsm6dsv_fifo_data_out_z_h_t fifo_data_out_z_h; + lsm6dsv_spi2_who_am_i_t spi2_who_am_i; + lsm6dsv_spi2_status_reg_ois_t spi2_status_reg_ois; + lsm6dsv_spi2_out_temp_l_t spi2_out_temp_l; + lsm6dsv_spi2_out_temp_h_t spi2_out_temp_h; + lsm6dsv_spi2_outx_l_g_ois_t spi2_outx_l_g_ois; + lsm6dsv_spi2_outx_h_g_ois_t spi2_outx_h_g_ois; + lsm6dsv_spi2_outy_l_g_ois_t spi2_outy_l_g_ois; + lsm6dsv_spi2_outy_h_g_ois_t spi2_outy_h_g_ois; + lsm6dsv_spi2_outz_l_g_ois_t spi2_outz_l_g_ois; + lsm6dsv_spi2_outz_h_g_ois_t spi2_outz_h_g_ois; + lsm6dsv_spi2_outx_l_a_ois_t spi2_outx_l_a_ois; + lsm6dsv_spi2_outx_h_a_ois_t spi2_outx_h_a_ois; + lsm6dsv_spi2_outy_l_a_ois_t spi2_outy_l_a_ois; + lsm6dsv_spi2_outy_h_a_ois_t spi2_outy_h_a_ois; + lsm6dsv_spi2_outz_l_a_ois_t spi2_outz_l_a_ois; + lsm6dsv_spi2_outz_h_a_ois_t spi2_outz_h_a_ois; + lsm6dsv_spi2_handshake_ctrl_t spi2_handshake_ctrl; + lsm6dsv_spi2_int_ois_t spi2_int_ois; + lsm6dsv_spi2_ctrl1_ois_t spi2_ctrl1_ois; + lsm6dsv_spi2_ctrl2_ois_t spi2_ctrl2_ois; + lsm6dsv_spi2_ctrl3_ois_t spi2_ctrl3_ois; + lsm6dsv_page_sel_t page_sel; + lsm6dsv_emb_func_en_a_t emb_func_en_a; + lsm6dsv_emb_func_en_b_t emb_func_en_b; + lsm6dsv_emb_func_exec_status_t emb_func_exec_status; + lsm6dsv_page_address_t page_address; + lsm6dsv_page_value_t page_value; + lsm6dsv_emb_func_int1_t emb_func_int1; + lsm6dsv_fsm_int1_t fsm_int1; + lsm6dsv_emb_func_int2_t emb_func_int2; + lsm6dsv_fsm_int2_t fsm_int2; + lsm6dsv_emb_func_status_t emb_func_status; + lsm6dsv_fsm_status_t fsm_status; + lsm6dsv_page_rw_t page_rw; + lsm6dsv_emb_func_fifo_en_a_t emb_func_fifo_en_a; + lsm6dsv_fsm_enable_t fsm_enable; + lsm6dsv_fsm_long_counter_l_t fsm_long_counter_l; + lsm6dsv_fsm_long_counter_h_t fsm_long_counter_h; + lsm6dsv_int_ack_mask_t int_ack_mask; + lsm6dsv_fsm_outs1_t fsm_outs1; + lsm6dsv_fsm_outs2_t fsm_outs2; + lsm6dsv_fsm_outs3_t fsm_outs3; + lsm6dsv_fsm_outs4_t fsm_outs4; + lsm6dsv_fsm_outs5_t fsm_outs5; + lsm6dsv_fsm_outs6_t fsm_outs6; + lsm6dsv_fsm_outs7_t fsm_outs7; + lsm6dsv_fsm_outs8_t fsm_outs8; + lsm6dsv_fsm_odr_t fsm_odr; + lsm6dsv_step_counter_l_t step_counter_l; + lsm6dsv_step_counter_h_t step_counter_h; + lsm6dsv_emb_func_src_t emb_func_src; + lsm6dsv_emb_func_init_a_t emb_func_init_a; + lsm6dsv_emb_func_init_b_t emb_func_init_b; + lsm6dsv_fsm_ext_sensitivity_l_t fsm_ext_sensitivity_l; + lsm6dsv_fsm_ext_sensitivity_h_t fsm_ext_sensitivity_h; + lsm6dsv_fsm_ext_offx_l_t fsm_ext_offx_l; + lsm6dsv_fsm_ext_offx_h_t fsm_ext_offx_h; + lsm6dsv_fsm_ext_offy_l_t fsm_ext_offy_l; + lsm6dsv_fsm_ext_offy_h_t fsm_ext_offy_h; + lsm6dsv_fsm_ext_offz_l_t fsm_ext_offz_l; + lsm6dsv_fsm_ext_offz_h_t fsm_ext_offz_h; + lsm6dsv_fsm_ext_matrix_xx_l_t fsm_ext_matrix_xx_l; + lsm6dsv_fsm_ext_matrix_xx_h_t fsm_ext_matrix_xx_h; + lsm6dsv_fsm_ext_matrix_xy_l_t fsm_ext_matrix_xy_l; + lsm6dsv_fsm_ext_matrix_xy_h_t fsm_ext_matrix_xy_h; + lsm6dsv_fsm_ext_matrix_xz_l_t fsm_ext_matrix_xz_l; + lsm6dsv_fsm_ext_matrix_xz_h_t fsm_ext_matrix_xz_h; + lsm6dsv_fsm_ext_matrix_yy_l_t fsm_ext_matrix_yy_l; + lsm6dsv_fsm_ext_matrix_yy_h_t fsm_ext_matrix_yy_h; + lsm6dsv_fsm_ext_matrix_yz_l_t fsm_ext_matrix_yz_l; + lsm6dsv_fsm_ext_matrix_yz_h_t fsm_ext_matrix_yz_h; + lsm6dsv_fsm_ext_matrix_zz_l_t fsm_ext_matrix_zz_l; + lsm6dsv_fsm_ext_matrix_zz_h_t fsm_ext_matrix_zz_h; + lsm6dsv_ext_cfg_a_t ext_cfg_a; + lsm6dsv_ext_cfg_b_t ext_cfg_b; + lsm6dsv_fsm_lc_timeout_l_t fsm_lc_timeout_l; + lsm6dsv_fsm_lc_timeout_h_t fsm_lc_timeout_h; + lsm6dsv_fsm_programs_t fsm_programs; + lsm6dsv_fsm_start_add_l_t fsm_start_add_l; + lsm6dsv_fsm_start_add_h_t fsm_start_add_h; + lsm6dsv_pedo_cmd_reg_t pedo_cmd_reg; + lsm6dsv_pedo_deb_steps_conf_t pedo_deb_steps_conf; + lsm6dsv_pedo_sc_deltat_l_t pedo_sc_deltat_l; + lsm6dsv_pedo_sc_deltat_h_t pedo_sc_deltat_h; + lsm6dsv_sensor_hub_1_t sensor_hub_1; + lsm6dsv_sensor_hub_2_t sensor_hub_2; + lsm6dsv_sensor_hub_3_t sensor_hub_3; + lsm6dsv_sensor_hub_4_t sensor_hub_4; + lsm6dsv_sensor_hub_5_t sensor_hub_5; + lsm6dsv_sensor_hub_6_t sensor_hub_6; + lsm6dsv_sensor_hub_7_t sensor_hub_7; + lsm6dsv_sensor_hub_8_t sensor_hub_8; + lsm6dsv_sensor_hub_9_t sensor_hub_9; + lsm6dsv_sensor_hub_10_t sensor_hub_10; + lsm6dsv_sensor_hub_11_t sensor_hub_11; + lsm6dsv_sensor_hub_12_t sensor_hub_12; + lsm6dsv_sensor_hub_13_t sensor_hub_13; + lsm6dsv_sensor_hub_14_t sensor_hub_14; + lsm6dsv_sensor_hub_15_t sensor_hub_15; + lsm6dsv_sensor_hub_16_t sensor_hub_16; + lsm6dsv_sensor_hub_17_t sensor_hub_17; + lsm6dsv_sensor_hub_18_t sensor_hub_18; + lsm6dsv_master_config_t master_config; + lsm6dsv_slv0_add_t slv0_add; + lsm6dsv_slv0_subadd_t slv0_subadd; + lsm6dsv_slv0_config_t slv0_config; + lsm6dsv_slv1_add_t slv1_add; + lsm6dsv_slv1_subadd_t slv1_subadd; + lsm6dsv_slv1_config_t slv1_config; + lsm6dsv_slv2_add_t slv2_add; + lsm6dsv_slv2_subadd_t slv2_subadd; + lsm6dsv_slv2_config_t slv2_config; + lsm6dsv_slv3_add_t slv3_add; + lsm6dsv_slv3_subadd_t slv3_subadd; + lsm6dsv_slv3_config_t slv3_config; + lsm6dsv_datawrite_slv0_t datawrite_slv0; + lsm6dsv_status_master_t status_master; + bitwise_t bitwise; + uint8_t byte; +} lsm6dsv_reg_t; + +/** + * @} + * + */ + +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + +int32_t lsm6dsv_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); +int32_t lsm6dsv_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); + +float_t lsm6dsv_from_fs2_to_mg(int16_t lsb); +float_t lsm6dsv_from_fs4_to_mg(int16_t lsb); +float_t lsm6dsv_from_fs8_to_mg(int16_t lsb); +float_t lsm6dsv_from_fs16_to_mg(int16_t lsb); + +float_t lsm6dsv_from_fs125_to_mdps(int16_t lsb); +float_t lsm6dsv_from_fs500_to_mdps(int16_t lsb); +float_t lsm6dsv_from_fs250_to_mdps(int16_t lsb); +float_t lsm6dsv_from_fs1000_to_mdps(int16_t lsb); +float_t lsm6dsv_from_fs2000_to_mdps(int16_t lsb); +float_t lsm6dsv_from_fs4000_to_mdps(int16_t lsb); + +float_t lsm6dsv_from_lsb_to_celsius(int16_t lsb); + +float_t lsm6dsv_from_lsb_to_nsec(uint32_t lsb); + +int32_t lsm6dsv_xl_offset_on_out_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_xl_offset_on_out_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + float_t z_mg; + float_t y_mg; + float_t x_mg; +} lsm6dsv_xl_offset_mg_t; +int32_t lsm6dsv_xl_offset_mg_set(stmdev_ctx_t *ctx, + lsm6dsv_xl_offset_mg_t val); +int32_t lsm6dsv_xl_offset_mg_get(stmdev_ctx_t *ctx, + lsm6dsv_xl_offset_mg_t *val); + +typedef enum +{ + LSM6DSV_READY = 0x0, + LSM6DSV_GLOBAL_RST = 0x1, + LSM6DSV_RESTORE_CAL_PARAM = 0x2, + LSM6DSV_RESTORE_CTRL_REGS = 0x4, +} lsm6dsv_reset_t; +int32_t lsm6dsv_reset_set(stmdev_ctx_t *ctx, lsm6dsv_reset_t val); +int32_t lsm6dsv_reset_get(stmdev_ctx_t *ctx, lsm6dsv_reset_t *val); + +typedef enum +{ + LSM6DSV_MAIN_MEM_BANK = 0x0, + LSM6DSV_EMBED_FUNC_MEM_BANK = 0x1, + LSM6DSV_SENSOR_HUB_MEM_BANK = 0x2, +} lsm6dsv_mem_bank_t; +int32_t lsm6dsv_mem_bank_set(stmdev_ctx_t *ctx, lsm6dsv_mem_bank_t val); +int32_t lsm6dsv_mem_bank_get(stmdev_ctx_t *ctx, lsm6dsv_mem_bank_t *val); + +int32_t lsm6dsv_device_id_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV_ODR_OFF = 0x0, + LSM6DSV_ODR_AT_1Hz875 = 0x1, + LSM6DSV_ODR_AT_7Hz5 = 0x2, + LSM6DSV_ODR_AT_15Hz = 0x3, + LSM6DSV_ODR_AT_30Hz = 0x4, + LSM6DSV_ODR_AT_60Hz = 0x5, + LSM6DSV_ODR_AT_120Hz = 0x6, + LSM6DSV_ODR_AT_240Hz = 0x7, + LSM6DSV_ODR_AT_480Hz = 0x8, + LSM6DSV_ODR_AT_960Hz = 0x9, + LSM6DSV_ODR_AT_1920Hz = 0xA, + LSM6DSV_ODR_AT_3840Hz = 0xB, + LSM6DSV_ODR_AT_7680Hz = 0xC, +} lsm6dsv_data_rate_t; +int32_t lsm6dsv_xl_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv_data_rate_t val); +int32_t lsm6dsv_xl_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv_data_rate_t *val); +int32_t lsm6dsv_gy_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv_data_rate_t val); +int32_t lsm6dsv_gy_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv_data_rate_t *val); + +typedef enum +{ + LSM6DSV_XL_HIGH_PERFORMANCE_MD = 0x0, + LSM6DSV_XL_HIGH_ACCURACY_ODR_MD = 0x1, + LSM6DSV_XL_LOW_POWER_2_AVG_MD = 0x4, + LSM6DSV_XL_LOW_POWER_4_AVG_MD = 0x5, + LSM6DSV_XL_LOW_POWER_8_AVG_MD = 0x6, + LSM6DSV_XL_NORMAL_MD = 0x7, +} lsm6dsv_xl_mode_t; +int32_t lsm6dsv_xl_mode_set(stmdev_ctx_t *ctx, lsm6dsv_xl_mode_t val); +int32_t lsm6dsv_xl_mode_get(stmdev_ctx_t *ctx, lsm6dsv_xl_mode_t *val); + +typedef enum +{ + LSM6DSV_GY_HIGH_PERFORMANCE_MD = 0x0, + LSM6DSV_GY_HIGH_ACCURACY_ODR_MD = 0x1, + LSM6DSV_GY_SLEEP_MD = 0x4, + LSM6DSV_GY_LOW_POWER_MD = 0x5, +} lsm6dsv_gy_mode_t; +int32_t lsm6dsv_gy_mode_set(stmdev_ctx_t *ctx, lsm6dsv_gy_mode_t val); +int32_t lsm6dsv_gy_mode_get(stmdev_ctx_t *ctx, lsm6dsv_gy_mode_t *val); + +int32_t lsm6dsv_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV_DRDY_LATCHED = 0x0, + LSM6DSV_DRDY_PULSED = 0x1, +} lsm6dsv_data_ready_mode_t; +int32_t lsm6dsv_data_ready_mode_set(stmdev_ctx_t *ctx, + lsm6dsv_data_ready_mode_t val); +int32_t lsm6dsv_data_ready_mode_get(stmdev_ctx_t *ctx, + lsm6dsv_data_ready_mode_t *val); + +typedef struct +{ + uint8_t enable : 1; /* interrupt enable */ + uint8_t lir : 1; /* interrupt pulsed or latched */ +} lsm6dsv_interrupt_mode_t; +int32_t lsm6dsv_interrupt_enable_set(stmdev_ctx_t *ctx, + lsm6dsv_interrupt_mode_t val); +int32_t lsm6dsv_interrupt_enable_get(stmdev_ctx_t *ctx, + lsm6dsv_interrupt_mode_t *val); + +typedef enum +{ + LSM6DSV_125dps = 0x0, + LSM6DSV_250dps = 0x1, + LSM6DSV_500dps = 0x2, + LSM6DSV_1000dps = 0x3, + LSM6DSV_2000dps = 0x4, + LSM6DSV_4000dps = 0x5, +} lsm6dsv_gy_full_scale_t; +int32_t lsm6dsv_gy_full_scale_set(stmdev_ctx_t *ctx, + lsm6dsv_gy_full_scale_t val); +int32_t lsm6dsv_gy_full_scale_get(stmdev_ctx_t *ctx, + lsm6dsv_gy_full_scale_t *val); + +typedef enum +{ + LSM6DSV_2g = 0x0, + LSM6DSV_4g = 0x1, + LSM6DSV_8g = 0x2, + LSM6DSV_16g = 0x3, +} lsm6dsv_xl_full_scale_t; +int32_t lsm6dsv_xl_full_scale_set(stmdev_ctx_t *ctx, + lsm6dsv_xl_full_scale_t val); +int32_t lsm6dsv_xl_full_scale_get(stmdev_ctx_t *ctx, + lsm6dsv_xl_full_scale_t *val); + +int32_t lsm6dsv_xl_dual_channel_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_xl_dual_channel_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV_XL_ST_DISABLE = 0x0, + LSM6DSV_XL_ST_POSITIVE = 0x1, + LSM6DSV_XL_ST_NEGATIVE = 0x2, +} lsm6dsv_xl_self_test_t; +int32_t lsm6dsv_xl_self_test_set(stmdev_ctx_t *ctx, + lsm6dsv_xl_self_test_t val); +int32_t lsm6dsv_xl_self_test_get(stmdev_ctx_t *ctx, + lsm6dsv_xl_self_test_t *val); + +typedef enum +{ + LSM6DSV_OIS_XL_ST_DISABLE = 0x0, + LSM6DSV_OIS_XL_ST_POSITIVE = 0x1, + LSM6DSV_OIS_XL_ST_NEGATIVE = 0x2, +} lsm6dsv_ois_xl_self_test_t; +int32_t lsm6dsv_ois_xl_self_test_set(stmdev_ctx_t *ctx, + lsm6dsv_ois_xl_self_test_t val); +int32_t lsm6dsv_ois_xl_self_test_get(stmdev_ctx_t *ctx, + lsm6dsv_ois_xl_self_test_t *val); + +typedef enum +{ + LSM6DSV_GY_ST_DISABLE = 0x0, + LSM6DSV_GY_ST_POSITIVE = 0x1, + LSM6DSV_GY_ST_NEGATIVE = 0x2, + +} lsm6dsv_gy_self_test_t; +int32_t lsm6dsv_gy_self_test_set(stmdev_ctx_t *ctx, + lsm6dsv_gy_self_test_t val); +int32_t lsm6dsv_gy_self_test_get(stmdev_ctx_t *ctx, + lsm6dsv_gy_self_test_t *val); + +typedef enum +{ + LSM6DSV_OIS_GY_ST_DISABLE = 0x0, + LSM6DSV_OIS_GY_ST_POSITIVE = 0x1, + LSM6DSV_OIS_GY_ST_NEGATIVE = 0x2, + LSM6DSV_OIS_GY_ST_CLAMP_POS = 0x5, + LSM6DSV_OIS_GY_ST_CLAMP_NEG = 0x6, + +} lsm6dsv_ois_gy_self_test_t; +int32_t lsm6dsv_ois_gy_self_test_set(stmdev_ctx_t *ctx, + lsm6dsv_ois_gy_self_test_t val); +int32_t lsm6dsv_ois_gy_self_test_get(stmdev_ctx_t *ctx, + lsm6dsv_ois_gy_self_test_t *val); + +typedef struct +{ + uint8_t drdy_xl : 1; + uint8_t drdy_gy : 1; + uint8_t drdy_temp : 1; + uint8_t drdy_eis : 1; + uint8_t drdy_ois : 1; + uint8_t gy_settling : 1; + uint8_t timestamp : 1; + uint8_t free_fall : 1; + uint8_t wake_up : 1; + uint8_t wake_up_z : 1; + uint8_t wake_up_y : 1; + uint8_t wake_up_x : 1; + uint8_t single_tap : 1; + uint8_t double_tap : 1; + uint8_t tap_z : 1; + uint8_t tap_y : 1; + uint8_t tap_x : 1; + uint8_t tap_sign : 1; + uint8_t six_d : 1; + uint8_t six_d_xl : 1; + uint8_t six_d_xh : 1; + uint8_t six_d_yl : 1; + uint8_t six_d_yh : 1; + uint8_t six_d_zl : 1; + uint8_t six_d_zh : 1; + uint8_t sleep_change : 1; + uint8_t sleep_state : 1; + uint8_t step_detector : 1; + uint8_t step_count_inc : 1; + uint8_t step_count_overflow : 1; + uint8_t step_on_delta_time : 1; + uint8_t emb_func_stand_by : 1; + uint8_t emb_func_time_exceed : 1; + uint8_t tilt : 1; + uint8_t sig_mot : 1; + uint8_t fsm_lc : 1; + uint8_t fsm1 : 1; + uint8_t fsm2 : 1; + uint8_t fsm3 : 1; + uint8_t fsm4 : 1; + uint8_t fsm5 : 1; + uint8_t fsm6 : 1; + uint8_t fsm7 : 1; + uint8_t fsm8 : 1; + uint8_t sh_endop : 1; + uint8_t sh_slave0_nack : 1; + uint8_t sh_slave1_nack : 1; + uint8_t sh_slave2_nack : 1; + uint8_t sh_slave3_nack : 1; + uint8_t sh_wr_once : 1; + uint8_t fifo_bdr : 1; + uint8_t fifo_full : 1; + uint8_t fifo_ovr : 1; + uint8_t fifo_th : 1; +} lsm6dsv_all_sources_t; +int32_t lsm6dsv_all_sources_get(stmdev_ctx_t *ctx, + lsm6dsv_all_sources_t *val); + +typedef struct +{ + uint8_t drdy_xl : 1; + uint8_t drdy_g : 1; + uint8_t drdy_g_eis : 1; + uint8_t fifo_th : 1; + uint8_t fifo_ovr : 1; + uint8_t fifo_full : 1; + uint8_t cnt_bdr : 1; + uint8_t emb_func_endop : 1; + uint8_t timestamp : 1; + uint8_t shub : 1; + uint8_t emb_func : 1; + uint8_t sixd : 1; + uint8_t single_tap : 1; + uint8_t double_tap : 1; + uint8_t wakeup : 1; + uint8_t freefall : 1; + uint8_t sleep_change : 1; +} lsm6dsv_pin_int_route_t; +int32_t lsm6dsv_pin_int1_route_set(stmdev_ctx_t *ctx, + lsm6dsv_pin_int_route_t *val); +int32_t lsm6dsv_pin_int1_route_get(stmdev_ctx_t *ctx, + lsm6dsv_pin_int_route_t *val); +int32_t lsm6dsv_pin_int2_route_set(stmdev_ctx_t *ctx, + lsm6dsv_pin_int_route_t *val); +int32_t lsm6dsv_pin_int2_route_get(stmdev_ctx_t *ctx, + lsm6dsv_pin_int_route_t *val); + +typedef struct +{ + uint8_t drdy_xl : 1; + uint8_t drdy_gy : 1; + uint8_t drdy_temp : 1; +} lsm6dsv_data_ready_t; +int32_t lsm6dsv_flag_data_ready_get(stmdev_ctx_t *ctx, + lsm6dsv_data_ready_t *val); + +int32_t lsm6dsv_int_ack_mask_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_int_ack_mask_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); + +int32_t lsm6dsv_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val); + +int32_t lsm6dsv_ois_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val); + +int32_t lsm6dsv_ois_eis_angular_rate_raw_get(stmdev_ctx_t *ctx, + int16_t *val); + +int32_t lsm6dsv_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); + +int32_t lsm6dsv_dual_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); + +int32_t lsm6dsv_ois_dual_acceleration_raw_get(stmdev_ctx_t *ctx, + int16_t *val); + +int32_t lsm6dsv_odr_cal_reg_get(stmdev_ctx_t *ctx, int8_t *val); + +int32_t lsm6dsv_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, + uint8_t *buf, uint8_t len); +int32_t lsm6dsv_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, + uint8_t len); + +int32_t lsm6dsv_emb_function_dbg_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_emb_function_dbg_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV_DEN_ACT_LOW = 0x0, + LSM6DSV_DEN_ACT_HIGH = 0x1, +} lsm6dsv_den_polarity_t; +int32_t lsm6dsv_den_polarity_set(stmdev_ctx_t *ctx, + lsm6dsv_den_polarity_t val); +int32_t lsm6dsv_den_polarity_get(stmdev_ctx_t *ctx, + lsm6dsv_den_polarity_t *val); + +typedef struct +{ + uint8_t stamp_in_gy_data : 1; + uint8_t stamp_in_xl_data : 1; + uint8_t den_x : 1; + uint8_t den_y : 1; + uint8_t den_z : 1; + enum + { + DEN_NOT_DEFINED = 0x00, + LEVEL_TRIGGER = 0x02, + LEVEL_LATCHED = 0x03, + } mode; +} lsm6dsv_den_conf_t; +int32_t lsm6dsv_den_conf_set(stmdev_ctx_t *ctx, lsm6dsv_den_conf_t val); +int32_t lsm6dsv_den_conf_get(stmdev_ctx_t *ctx, lsm6dsv_den_conf_t *val); + +typedef enum +{ + LSM6DSV_EIS_125dps = 0x0, + LSM6DSV_EIS_250dps = 0x1, + LSM6DSV_EIS_500dps = 0x2, + LSM6DSV_EIS_1000dps = 0x3, + LSM6DSV_EIS_2000dps = 0x4, +} lsm6dsv_eis_gy_full_scale_t; +int32_t lsm6dsv_eis_gy_full_scale_set(stmdev_ctx_t *ctx, + lsm6dsv_eis_gy_full_scale_t val); +int32_t lsm6dsv_eis_gy_full_scale_get(stmdev_ctx_t *ctx, + lsm6dsv_eis_gy_full_scale_t *val); + +int32_t lsm6dsv_eis_gy_on_spi2_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_eis_gy_on_spi2_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV_EIS_ODR_OFF = 0x0, + LSM6DSV_EIS_1920Hz = 0x1, + LSM6DSV_EIS_960Hz = 0x2, +} lsm6dsv_gy_eis_data_rate_t; +int32_t lsm6dsv_gy_eis_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv_gy_eis_data_rate_t val); +int32_t lsm6dsv_gy_eis_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv_gy_eis_data_rate_t *val); + +int32_t lsm6dsv_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv_fifo_xl_dual_fsm_batch_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_fifo_xl_dual_fsm_batch_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV_CMP_DISABLE = 0x0, + LSM6DSV_CMP_8_TO_1 = 0x1, + LSM6DSV_CMP_16_TO_1 = 0x2, + LSM6DSV_CMP_32_TO_1 = 0x3, +} lsm6dsv_fifo_compress_algo_t; +int32_t lsm6dsv_fifo_compress_algo_set(stmdev_ctx_t *ctx, + lsm6dsv_fifo_compress_algo_t val); +int32_t lsm6dsv_fifo_compress_algo_get(stmdev_ctx_t *ctx, + lsm6dsv_fifo_compress_algo_t *val); + +int32_t lsm6dsv_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, + uint8_t val); +int32_t lsm6dsv_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t lsm6dsv_fifo_compress_algo_real_time_set(stmdev_ctx_t *ctx, + uint8_t val); +int32_t lsm6dsv_fifo_compress_algo_real_time_get(stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t lsm6dsv_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV_XL_NOT_BATCHED = 0x0, + LSM6DSV_XL_BATCHED_AT_1Hz875 = 0x1, + LSM6DSV_XL_BATCHED_AT_7Hz5 = 0x2, + LSM6DSV_XL_BATCHED_AT_15Hz = 0x3, + LSM6DSV_XL_BATCHED_AT_30Hz = 0x4, + LSM6DSV_XL_BATCHED_AT_60Hz = 0x5, + LSM6DSV_XL_BATCHED_AT_120Hz = 0x6, + LSM6DSV_XL_BATCHED_AT_240Hz = 0x7, + LSM6DSV_XL_BATCHED_AT_480Hz = 0x8, + LSM6DSV_XL_BATCHED_AT_960Hz = 0x9, + LSM6DSV_XL_BATCHED_AT_1920Hz = 0xa, + LSM6DSV_XL_BATCHED_AT_3840Hz = 0xb, + LSM6DSV_XL_BATCHED_AT_7680Hz = 0xc, +} lsm6dsv_fifo_xl_batch_t; +int32_t lsm6dsv_fifo_xl_batch_set(stmdev_ctx_t *ctx, + lsm6dsv_fifo_xl_batch_t val); +int32_t lsm6dsv_fifo_xl_batch_get(stmdev_ctx_t *ctx, + lsm6dsv_fifo_xl_batch_t *val); + +typedef enum +{ + LSM6DSV_GY_NOT_BATCHED = 0x0, + LSM6DSV_GY_BATCHED_AT_1Hz875 = 0x1, + LSM6DSV_GY_BATCHED_AT_7Hz5 = 0x2, + LSM6DSV_GY_BATCHED_AT_15Hz = 0x3, + LSM6DSV_GY_BATCHED_AT_30Hz = 0x4, + LSM6DSV_GY_BATCHED_AT_60Hz = 0x5, + LSM6DSV_GY_BATCHED_AT_120Hz = 0x6, + LSM6DSV_GY_BATCHED_AT_240Hz = 0x7, + LSM6DSV_GY_BATCHED_AT_480Hz = 0x8, + LSM6DSV_GY_BATCHED_AT_960Hz = 0x9, + LSM6DSV_GY_BATCHED_AT_1920Hz = 0xa, + LSM6DSV_GY_BATCHED_AT_3840Hz = 0xb, + LSM6DSV_GY_BATCHED_AT_7680Hz = 0xc, +} lsm6dsv_fifo_gy_batch_t; +int32_t lsm6dsv_fifo_gy_batch_set(stmdev_ctx_t *ctx, + lsm6dsv_fifo_gy_batch_t val); +int32_t lsm6dsv_fifo_gy_batch_get(stmdev_ctx_t *ctx, + lsm6dsv_fifo_gy_batch_t *val); + +typedef enum +{ + LSM6DSV_BYPASS_MODE = 0x0, + LSM6DSV_FIFO_MODE = 0x1, + LSM6DSV_STREAM_WTM_TO_FULL_MODE = 0x2, + LSM6DSV_STREAM_TO_FIFO_MODE = 0x3, + LSM6DSV_BYPASS_TO_STREAM_MODE = 0x4, + LSM6DSV_STREAM_MODE = 0x6, + LSM6DSV_BYPASS_TO_FIFO_MODE = 0x7, +} lsm6dsv_fifo_mode_t; +int32_t lsm6dsv_fifo_mode_set(stmdev_ctx_t *ctx, lsm6dsv_fifo_mode_t val); +int32_t lsm6dsv_fifo_mode_get(stmdev_ctx_t *ctx, + lsm6dsv_fifo_mode_t *val); + +int32_t lsm6dsv_fifo_gy_eis_batch_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_fifo_gy_eis_batch_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV_TEMP_NOT_BATCHED = 0x0, + LSM6DSV_TEMP_BATCHED_AT_1Hz875 = 0x1, + LSM6DSV_TEMP_BATCHED_AT_15Hz = 0x2, + LSM6DSV_TEMP_BATCHED_AT_60Hz = 0x3, +} lsm6dsv_fifo_temp_batch_t; +int32_t lsm6dsv_fifo_temp_batch_set(stmdev_ctx_t *ctx, + lsm6dsv_fifo_temp_batch_t val); +int32_t lsm6dsv_fifo_temp_batch_get(stmdev_ctx_t *ctx, + lsm6dsv_fifo_temp_batch_t *val); + +typedef enum +{ + LSM6DSV_TMSTMP_NOT_BATCHED = 0x0, + LSM6DSV_TMSTMP_DEC_1 = 0x1, + LSM6DSV_TMSTMP_DEC_8 = 0x2, + LSM6DSV_TMSTMP_DEC_32 = 0x3, +} lsm6dsv_fifo_timestamp_batch_t; +int32_t lsm6dsv_fifo_timestamp_batch_set(stmdev_ctx_t *ctx, + lsm6dsv_fifo_timestamp_batch_t val); +int32_t lsm6dsv_fifo_timestamp_batch_get(stmdev_ctx_t *ctx, + lsm6dsv_fifo_timestamp_batch_t *val); + +int32_t lsm6dsv_fifo_batch_counter_threshold_set(stmdev_ctx_t *ctx, + uint16_t val); +int32_t lsm6dsv_fifo_batch_counter_threshold_get(stmdev_ctx_t *ctx, + uint16_t *val); + +typedef enum +{ + LSM6DSV_XL_BATCH_EVENT = 0x0, + LSM6DSV_GY_BATCH_EVENT = 0x1, + LSM6DSV_GY_EIS_BATCH_EVENT = 0x2, +} lsm6dsv_fifo_batch_cnt_event_t; +int32_t lsm6dsv_fifo_batch_cnt_event_set(stmdev_ctx_t *ctx, + lsm6dsv_fifo_batch_cnt_event_t val); +int32_t lsm6dsv_fifo_batch_cnt_event_get(stmdev_ctx_t *ctx, + lsm6dsv_fifo_batch_cnt_event_t *val); + +typedef struct +{ + uint16_t fifo_level : 9; + uint8_t fifo_bdr : 1; + uint8_t fifo_full : 1; + uint8_t fifo_ovr : 1; + uint8_t fifo_th : 1; +} lsm6dsv_fifo_status_t; + +int32_t lsm6dsv_fifo_status_get(stmdev_ctx_t *ctx, + lsm6dsv_fifo_status_t *val); + +typedef struct +{ + enum + { + LSM6DSV_FIFO_EMPTY = 0x0, + LSM6DSV_GY_NC_TAG = 0x1, + LSM6DSV_XL_NC_TAG = 0x2, + LSM6DSV_TEMPERATURE_TAG = 0x3, + LSM6DSV_TIMESTAMP_TAG = 0x4, + LSM6DSV_CFG_CHANGE_TAG = 0x5, + LSM6DSV_XL_NC_T_2_TAG = 0x6, + LSM6DSV_XL_NC_T_1_TAG = 0x7, + LSM6DSV_XL_2XC_TAG = 0x8, + LSM6DSV_XL_3XC_TAG = 0x9, + LSM6DSV_GY_NC_T_2_TAG = 0xA, + LSM6DSV_GY_NC_T_1_TAG = 0xB, + LSM6DSV_GY_2XC_TAG = 0xC, + LSM6DSV_GY_3XC_TAG = 0xD, + LSM6DSV_SENSORHUB_SLAVE0_TAG = 0xE, + LSM6DSV_SENSORHUB_SLAVE1_TAG = 0xF, + LSM6DSV_SENSORHUB_SLAVE2_TAG = 0x10, + LSM6DSV_SENSORHUB_SLAVE3_TAG = 0x11, + LSM6DSV_STEP_COUNTER_TAG = 0x12, + LSM6DSV_SENSORHUB_NACK_TAG = 0x19, + LSM6DSV_XL_DUAL_CORE = 0x1D, + LSM6DSV_GY_ENHANCED_EIS = 0x1E, + } tag; + uint8_t cnt; + uint8_t data[6]; +} lsm6dsv_fifo_out_raw_t; +int32_t lsm6dsv_fifo_out_raw_get(stmdev_ctx_t *ctx, + lsm6dsv_fifo_out_raw_t *val); + +int32_t lsm6dsv_fifo_stpcnt_batch_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_fifo_stpcnt_batch_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv_fifo_batch_sh_slave_0_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_fifo_batch_sh_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv_fifo_batch_sh_slave_1_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_fifo_batch_sh_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv_fifo_batch_sh_slave_2_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_fifo_batch_sh_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv_fifo_batch_sh_slave_3_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_fifo_batch_sh_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV_AUTO = 0x0, + LSM6DSV_ALWAYS_ACTIVE = 0x1, +} lsm6dsv_filt_anti_spike_t; +int32_t lsm6dsv_filt_anti_spike_set(stmdev_ctx_t *ctx, + lsm6dsv_filt_anti_spike_t val); +int32_t lsm6dsv_filt_anti_spike_get(stmdev_ctx_t *ctx, + lsm6dsv_filt_anti_spike_t *val); + +typedef struct +{ + uint8_t drdy : 1; + uint8_t ois_drdy : 1; + uint8_t irq_xl : 1; + uint8_t irq_g : 1; +} lsm6dsv_filt_settling_mask_t; +int32_t lsm6dsv_filt_settling_mask_set(stmdev_ctx_t *ctx, + lsm6dsv_filt_settling_mask_t val); +int32_t lsm6dsv_filt_settling_mask_get(stmdev_ctx_t *ctx, + lsm6dsv_filt_settling_mask_t *val); + +typedef struct +{ + uint8_t ois_drdy : 1; +} lsm6dsv_filt_ois_settling_mask_t; +int32_t lsm6dsv_filt_ois_settling_mask_set(stmdev_ctx_t *ctx, + lsm6dsv_filt_ois_settling_mask_t val); +int32_t lsm6dsv_filt_ois_settling_mask_get(stmdev_ctx_t *ctx, + lsm6dsv_filt_ois_settling_mask_t *val); + +typedef enum +{ + LSM6DSV_GY_ULTRA_LIGHT = 0x0, + LSM6DSV_GY_VERY_LIGHT = 0x1, + LSM6DSV_GY_LIGHT = 0x2, + LSM6DSV_GY_MEDIUM = 0x3, + LSM6DSV_GY_STRONG = 0x4, + LSM6DSV_GY_VERY_STRONG = 0x5, + LSM6DSV_GY_AGGRESSIVE = 0x6, + LSM6DSV_GY_XTREME = 0x7, +} lsm6dsv_filt_gy_lp1_bandwidth_t; +int32_t lsm6dsv_filt_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, + lsm6dsv_filt_gy_lp1_bandwidth_t val); +int32_t lsm6dsv_filt_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, + lsm6dsv_filt_gy_lp1_bandwidth_t *val); + +int32_t lsm6dsv_filt_gy_lp1_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_filt_gy_lp1_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV_XL_ULTRA_LIGHT = 0x0, + LSM6DSV_XL_VERY_LIGHT = 0x1, + LSM6DSV_XL_LIGHT = 0x2, + LSM6DSV_XL_MEDIUM = 0x3, + LSM6DSV_XL_STRONG = 0x4, + LSM6DSV_XL_VERY_STRONG = 0x5, + LSM6DSV_XL_AGGRESSIVE = 0x6, + LSM6DSV_XL_XTREME = 0x7, +} lsm6dsv_filt_xl_lp2_bandwidth_t; +int32_t lsm6dsv_filt_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, + lsm6dsv_filt_xl_lp2_bandwidth_t val); +int32_t lsm6dsv_filt_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, + lsm6dsv_filt_xl_lp2_bandwidth_t *val); + +int32_t lsm6dsv_filt_xl_lp2_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_filt_xl_lp2_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv_filt_xl_hp_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_filt_xl_hp_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv_filt_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_filt_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV_HP_MD_NORMAL = 0x0, + LSM6DSV_HP_MD_REFERENCE = 0x1, +} lsm6dsv_filt_xl_hp_mode_t; +int32_t lsm6dsv_filt_xl_hp_mode_set(stmdev_ctx_t *ctx, + lsm6dsv_filt_xl_hp_mode_t val); +int32_t lsm6dsv_filt_xl_hp_mode_get(stmdev_ctx_t *ctx, + lsm6dsv_filt_xl_hp_mode_t *val); + +typedef enum +{ + LSM6DSV_WK_FEED_SLOPE = 0x0, + LSM6DSV_WK_FEED_HIGH_PASS = 0x1, + LSM6DSV_WK_FEED_LP_WITH_OFFSET = 0x2, +} lsm6dsv_filt_wkup_act_feed_t; +int32_t lsm6dsv_filt_wkup_act_feed_set(stmdev_ctx_t *ctx, + lsm6dsv_filt_wkup_act_feed_t val); +int32_t lsm6dsv_filt_wkup_act_feed_get(stmdev_ctx_t *ctx, + lsm6dsv_filt_wkup_act_feed_t *val); + +int32_t lsm6dsv_mask_trigger_xl_settl_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_mask_trigger_xl_settl_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV_SIXD_FEED_ODR_DIV_2 = 0x0, + LSM6DSV_SIXD_FEED_LOW_PASS = 0x1, +} lsm6dsv_filt_sixd_feed_t; +int32_t lsm6dsv_filt_sixd_feed_set(stmdev_ctx_t *ctx, + lsm6dsv_filt_sixd_feed_t val); +int32_t lsm6dsv_filt_sixd_feed_get(stmdev_ctx_t *ctx, + lsm6dsv_filt_sixd_feed_t *val); + +typedef enum +{ + LSM6DSV_EIS_LP_NORMAL = 0x0, + LSM6DSV_EIS_LP_LIGHT = 0x1, +} lsm6dsv_filt_gy_eis_lp_bandwidth_t; +int32_t lsm6dsv_filt_gy_eis_lp_bandwidth_set(stmdev_ctx_t *ctx, + lsm6dsv_filt_gy_eis_lp_bandwidth_t val); +int32_t lsm6dsv_filt_gy_eis_lp_bandwidth_get(stmdev_ctx_t *ctx, + lsm6dsv_filt_gy_eis_lp_bandwidth_t *val); + +typedef enum +{ + LSM6DSV_OIS_GY_LP_NORMAL = 0x0, + LSM6DSV_OIS_GY_LP_STRONG = 0x1, + LSM6DSV_OIS_GY_LP_AGGRESSIVE = 0x2, + LSM6DSV_OIS_GY_LP_LIGHT = 0x3, +} lsm6dsv_filt_gy_ois_lp_bandwidth_t; +int32_t lsm6dsv_filt_gy_ois_lp_bandwidth_set(stmdev_ctx_t *ctx, + lsm6dsv_filt_gy_ois_lp_bandwidth_t val); +int32_t lsm6dsv_filt_gy_ois_lp_bandwidth_get(stmdev_ctx_t *ctx, + lsm6dsv_filt_gy_ois_lp_bandwidth_t *val); + +typedef enum +{ + LSM6DSV_OIS_XL_LP_ULTRA_LIGHT = 0x0, + LSM6DSV_OIS_XL_LP_VERY_LIGHT = 0x1, + LSM6DSV_OIS_XL_LP_LIGHT = 0x2, + LSM6DSV_OIS_XL_LP_NORMAL = 0x3, + LSM6DSV_OIS_XL_LP_STRONG = 0x4, + LSM6DSV_OIS_XL_LP_VERY_STRONG = 0x5, + LSM6DSV_OIS_XL_LP_AGGRESSIVE = 0x6, + LSM6DSV_OIS_XL_LP_XTREME = 0x7, +} lsm6dsv_filt_xl_ois_lp_bandwidth_t; +int32_t lsm6dsv_filt_xl_ois_lp_bandwidth_set(stmdev_ctx_t *ctx, + lsm6dsv_filt_xl_ois_lp_bandwidth_t val); +int32_t lsm6dsv_filt_xl_ois_lp_bandwidth_get(stmdev_ctx_t *ctx, + lsm6dsv_filt_xl_ois_lp_bandwidth_t *val); + +typedef enum +{ + LSM6DSV_PROTECT_CTRL_REGS = 0x0, + LSM6DSV_WRITE_CTRL_REG = 0x1, +} lsm6dsv_fsm_permission_t; +int32_t lsm6dsv_fsm_permission_set(stmdev_ctx_t *ctx, + lsm6dsv_fsm_permission_t val); +int32_t lsm6dsv_fsm_permission_get(stmdev_ctx_t *ctx, + lsm6dsv_fsm_permission_t *val); +int32_t lsm6dsv_fsm_permission_status(stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t fsm1_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm8_en : 1; +} lsm6dsv_fsm_mode_t; +int32_t lsm6dsv_fsm_mode_set(stmdev_ctx_t *ctx, lsm6dsv_fsm_mode_t val); +int32_t lsm6dsv_fsm_mode_get(stmdev_ctx_t *ctx, lsm6dsv_fsm_mode_t *val); + +int32_t lsm6dsv_fsm_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv_fsm_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val); + + +typedef struct +{ + uint8_t fsm_outs1; + uint8_t fsm_outs2; + uint8_t fsm_outs3; + uint8_t fsm_outs4; + uint8_t fsm_outs5; + uint8_t fsm_outs6; + uint8_t fsm_outs7; + uint8_t fsm_outs8; +} lsm6dsv_fsm_out_t; +int32_t lsm6dsv_fsm_out_get(stmdev_ctx_t *ctx, lsm6dsv_fsm_out_t *val); + +typedef enum +{ + LSM6DSV_FSM_15Hz = 0x0, + LSM6DSV_FSM_30Hz = 0x1, + LSM6DSV_FSM_60Hz = 0x2, + LSM6DSV_FSM_120Hz = 0x3, + LSM6DSV_FSM_240Hz = 0x4, + LSM6DSV_FSM_480Hz = 0x5, + LSM6DSV_FSM_960Hz = 0x6, +} lsm6dsv_fsm_data_rate_t; +int32_t lsm6dsv_fsm_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv_fsm_data_rate_t val); +int32_t lsm6dsv_fsm_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv_fsm_data_rate_t *val); + +int32_t lsm6dsv_fsm_ext_sens_sensitivity_set(stmdev_ctx_t *ctx, + uint16_t val); +int32_t lsm6dsv_fsm_ext_sens_sensitivity_get(stmdev_ctx_t *ctx, + uint16_t *val); + +typedef struct +{ + uint16_t z; + uint16_t y; + uint16_t x; +} lsm6dsv_xl_fsm_ext_sens_offset_t; +int32_t lsm6dsv_fsm_ext_sens_offset_set(stmdev_ctx_t *ctx, + lsm6dsv_xl_fsm_ext_sens_offset_t val); +int32_t lsm6dsv_fsm_ext_sens_offset_get(stmdev_ctx_t *ctx, + lsm6dsv_xl_fsm_ext_sens_offset_t *val); + +typedef struct +{ + uint16_t xx; + uint16_t xy; + uint16_t xz; + uint16_t yy; + uint16_t yz; + uint16_t zz; +} lsm6dsv_xl_fsm_ext_sens_matrix_t; +int32_t lsm6dsv_fsm_ext_sens_matrix_set(stmdev_ctx_t *ctx, + lsm6dsv_xl_fsm_ext_sens_matrix_t val); +int32_t lsm6dsv_fsm_ext_sens_matrix_get(stmdev_ctx_t *ctx, + lsm6dsv_xl_fsm_ext_sens_matrix_t *val); + +typedef enum +{ + LSM6DSV_Z_EQ_Y = 0x0, + LSM6DSV_Z_EQ_MIN_Y = 0x1, + LSM6DSV_Z_EQ_X = 0x2, + LSM6DSV_Z_EQ_MIN_X = 0x3, + LSM6DSV_Z_EQ_MIN_Z = 0x4, + LSM6DSV_Z_EQ_Z = 0x5, +} lsm6dsv_fsm_ext_sens_z_orient_t; +int32_t lsm6dsv_fsm_ext_sens_z_orient_set(stmdev_ctx_t *ctx, + lsm6dsv_fsm_ext_sens_z_orient_t val); +int32_t lsm6dsv_fsm_ext_sens_z_orient_get(stmdev_ctx_t *ctx, + lsm6dsv_fsm_ext_sens_z_orient_t *val); + +typedef enum +{ + LSM6DSV_Y_EQ_Y = 0x0, + LSM6DSV_Y_EQ_MIN_Y = 0x1, + LSM6DSV_Y_EQ_X = 0x2, + LSM6DSV_Y_EQ_MIN_X = 0x3, + LSM6DSV_Y_EQ_MIN_Z = 0x4, + LSM6DSV_Y_EQ_Z = 0x5, +} lsm6dsv_fsm_ext_sens_y_orient_t; +int32_t lsm6dsv_fsm_ext_sens_y_orient_set(stmdev_ctx_t *ctx, + lsm6dsv_fsm_ext_sens_y_orient_t val); +int32_t lsm6dsv_fsm_ext_sens_y_orient_get(stmdev_ctx_t *ctx, + lsm6dsv_fsm_ext_sens_y_orient_t *val); + +typedef enum +{ + LSM6DSV_X_EQ_Y = 0x0, + LSM6DSV_X_EQ_MIN_Y = 0x1, + LSM6DSV_X_EQ_X = 0x2, + LSM6DSV_X_EQ_MIN_X = 0x3, + LSM6DSV_X_EQ_MIN_Z = 0x4, + LSM6DSV_X_EQ_Z = 0x5, +} lsm6dsv_fsm_ext_sens_x_orient_t; +int32_t lsm6dsv_fsm_ext_sens_x_orient_set(stmdev_ctx_t *ctx, + lsm6dsv_fsm_ext_sens_x_orient_t val); +int32_t lsm6dsv_fsm_ext_sens_x_orient_get(stmdev_ctx_t *ctx, + lsm6dsv_fsm_ext_sens_x_orient_t *val); + +int32_t lsm6dsv_fsm_long_cnt_timeout_set(stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv_fsm_long_cnt_timeout_get(stmdev_ctx_t *ctx, uint16_t *val); + +int32_t lsm6dsv_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val); + +int32_t lsm6dsv_ff_time_windows_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_ff_time_windows_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV_156_mg = 0x0, + LSM6DSV_219_mg = 0x1, + LSM6DSV_250_mg = 0x2, + LSM6DSV_312_mg = 0x3, + LSM6DSV_344_mg = 0x4, + LSM6DSV_406_mg = 0x5, + LSM6DSV_469_mg = 0x6, + LSM6DSV_500_mg = 0x7, +} lsm6dsv_ff_thresholds_t; +int32_t lsm6dsv_ff_thresholds_set(stmdev_ctx_t *ctx, + lsm6dsv_ff_thresholds_t val); +int32_t lsm6dsv_ff_thresholds_get(stmdev_ctx_t *ctx, + lsm6dsv_ff_thresholds_t *val); + +typedef enum +{ + LSM6DSV_OIS_CTRL_FROM_OIS = 0x0, + LSM6DSV_OIS_CTRL_FROM_UI = 0x1, +} lsm6dsv_ois_ctrl_mode_t; +int32_t lsm6dsv_ois_ctrl_mode_set(stmdev_ctx_t *ctx, + lsm6dsv_ois_ctrl_mode_t val); +int32_t lsm6dsv_ois_ctrl_mode_get(stmdev_ctx_t *ctx, + lsm6dsv_ois_ctrl_mode_t *val); + +int32_t lsm6dsv_ois_reset_set(stmdev_ctx_t *ctx, int8_t val); +int32_t lsm6dsv_ois_reset_get(stmdev_ctx_t *ctx, int8_t *val); + +int32_t lsm6dsv_ois_interface_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_ois_interface_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t ack : 1; + uint8_t req : 1; +} lsm6dsv_ois_handshake_t; +int32_t lsm6dsv_ois_handshake_from_ui_set(stmdev_ctx_t *ctx, + lsm6dsv_ois_handshake_t val); +int32_t lsm6dsv_ois_handshake_from_ui_get(stmdev_ctx_t *ctx, + lsm6dsv_ois_handshake_t *val); +int32_t lsm6dsv_ois_handshake_from_ois_set(stmdev_ctx_t *ctx, + lsm6dsv_ois_handshake_t val); +int32_t lsm6dsv_ois_handshake_from_ois_get(stmdev_ctx_t *ctx, + lsm6dsv_ois_handshake_t *val); + +int32_t lsm6dsv_ois_shared_set(stmdev_ctx_t *ctx, uint8_t val[6]); +int32_t lsm6dsv_ois_shared_get(stmdev_ctx_t *ctx, uint8_t val[6]); + +int32_t lsm6dsv_ois_on_spi2_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_ois_on_spi2_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t gy : 1; + uint8_t xl : 1; +} lsm6dsv_ois_chain_t; +int32_t lsm6dsv_ois_chain_set(stmdev_ctx_t *ctx, lsm6dsv_ois_chain_t val); +int32_t lsm6dsv_ois_chain_get(stmdev_ctx_t *ctx, + lsm6dsv_ois_chain_t *val); + +typedef enum +{ + LSM6DSV_OIS_125dps = 0x0, + LSM6DSV_OIS_250dps = 0x1, + LSM6DSV_OIS_500dps = 0x2, + LSM6DSV_OIS_1000dps = 0x3, + LSM6DSV_OIS_2000dps = 0x4, +} lsm6dsv_ois_gy_full_scale_t; +int32_t lsm6dsv_ois_gy_full_scale_set(stmdev_ctx_t *ctx, + lsm6dsv_ois_gy_full_scale_t val); +int32_t lsm6dsv_ois_gy_full_scale_get(stmdev_ctx_t *ctx, + lsm6dsv_ois_gy_full_scale_t *val); + +typedef enum +{ + LSM6DSV_OIS_2g = 0x0, + LSM6DSV_OIS_4g = 0x1, + LSM6DSV_OIS_8g = 0x2, + LSM6DSV_OIS_16g = 0x3, +} lsm6dsv_ois_xl_full_scale_t; +int32_t lsm6dsv_ois_xl_full_scale_set(stmdev_ctx_t *ctx, + lsm6dsv_ois_xl_full_scale_t val); +int32_t lsm6dsv_ois_xl_full_scale_get(stmdev_ctx_t *ctx, + lsm6dsv_ois_xl_full_scale_t *val); + +typedef enum +{ + LSM6DSV_DEG_80 = 0x0, + LSM6DSV_DEG_70 = 0x1, + LSM6DSV_DEG_60 = 0x2, + LSM6DSV_DEG_50 = 0x3, +} lsm6dsv_6d_threshold_t; +int32_t lsm6dsv_6d_threshold_set(stmdev_ctx_t *ctx, + lsm6dsv_6d_threshold_t val); +int32_t lsm6dsv_6d_threshold_get(stmdev_ctx_t *ctx, + lsm6dsv_6d_threshold_t *val); + +int32_t lsm6dsv_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV_SW_RST_DYN_ADDRESS_RST = 0x0, + LSM6DSV_I3C_GLOBAL_RST = 0x1, +} lsm6dsv_i3c_reset_mode_t; +int32_t lsm6dsv_i3c_reset_mode_set(stmdev_ctx_t *ctx, + lsm6dsv_i3c_reset_mode_t val); +int32_t lsm6dsv_i3c_reset_mode_get(stmdev_ctx_t *ctx, + lsm6dsv_i3c_reset_mode_t *val); + +typedef enum +{ + LSM6DSV_IBI_2us = 0x0, + LSM6DSV_IBI_50us = 0x1, + LSM6DSV_IBI_1ms = 0x2, + LSM6DSV_IBI_25ms = 0x3, +} lsm6dsv_i3c_ibi_time_t; +int32_t lsm6dsv_i3c_ibi_time_set(stmdev_ctx_t *ctx, + lsm6dsv_i3c_ibi_time_t val); +int32_t lsm6dsv_i3c_ibi_time_get(stmdev_ctx_t *ctx, + lsm6dsv_i3c_ibi_time_t *val); + +int32_t lsm6dsv_sh_master_interface_pull_up_set(stmdev_ctx_t *ctx, + uint8_t val); +int32_t lsm6dsv_sh_master_interface_pull_up_get(stmdev_ctx_t *ctx, + uint8_t *val); + +typedef struct +{ + lsm6dsv_sensor_hub_1_t sh_byte_1; + lsm6dsv_sensor_hub_2_t sh_byte_2; + lsm6dsv_sensor_hub_3_t sh_byte_3; + lsm6dsv_sensor_hub_4_t sh_byte_4; + lsm6dsv_sensor_hub_5_t sh_byte_5; + lsm6dsv_sensor_hub_6_t sh_byte_6; + lsm6dsv_sensor_hub_7_t sh_byte_7; + lsm6dsv_sensor_hub_8_t sh_byte_8; + lsm6dsv_sensor_hub_9_t sh_byte_9; + lsm6dsv_sensor_hub_10_t sh_byte_10; + lsm6dsv_sensor_hub_11_t sh_byte_11; + lsm6dsv_sensor_hub_12_t sh_byte_12; + lsm6dsv_sensor_hub_13_t sh_byte_13; + lsm6dsv_sensor_hub_14_t sh_byte_14; + lsm6dsv_sensor_hub_15_t sh_byte_15; + lsm6dsv_sensor_hub_16_t sh_byte_16; + lsm6dsv_sensor_hub_17_t sh_byte_17; + lsm6dsv_sensor_hub_18_t sh_byte_18; +} lsm6dsv_emb_sh_read_t; +int32_t lsm6dsv_sh_read_data_raw_get(stmdev_ctx_t *ctx, + lsm6dsv_emb_sh_read_t *val, + uint8_t len); + +typedef enum +{ + LSM6DSV_SLV_0 = 0x0, + LSM6DSV_SLV_0_1 = 0x1, + LSM6DSV_SLV_0_1_2 = 0x2, + LSM6DSV_SLV_0_1_2_3 = 0x3, +} lsm6dsv_sh_slave_connected_t; +int32_t lsm6dsv_sh_slave_connected_set(stmdev_ctx_t *ctx, + lsm6dsv_sh_slave_connected_t val); +int32_t lsm6dsv_sh_slave_connected_get(stmdev_ctx_t *ctx, + lsm6dsv_sh_slave_connected_t *val); + +int32_t lsm6dsv_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV_SH_TRG_XL_GY_DRDY = 0x0, + LSM6DSV_SH_TRIG_INT2 = 0x1, +} lsm6dsv_sh_syncro_mode_t; +int32_t lsm6dsv_sh_syncro_mode_set(stmdev_ctx_t *ctx, + lsm6dsv_sh_syncro_mode_t val); +int32_t lsm6dsv_sh_syncro_mode_get(stmdev_ctx_t *ctx, + lsm6dsv_sh_syncro_mode_t *val); + +typedef enum +{ + LSM6DSV_EACH_SH_CYCLE = 0x0, + LSM6DSV_ONLY_FIRST_CYCLE = 0x1, +} lsm6dsv_sh_write_mode_t; +int32_t lsm6dsv_sh_write_mode_set(stmdev_ctx_t *ctx, + lsm6dsv_sh_write_mode_t val); +int32_t lsm6dsv_sh_write_mode_get(stmdev_ctx_t *ctx, + lsm6dsv_sh_write_mode_t *val); + +int32_t lsm6dsv_sh_reset_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t slv0_add; + uint8_t slv0_subadd; + uint8_t slv0_data; +} lsm6dsv_sh_cfg_write_t; +int32_t lsm6dsv_sh_cfg_write(stmdev_ctx_t *ctx, + lsm6dsv_sh_cfg_write_t *val); +typedef enum +{ + LSM6DSV_SH_15Hz = 0x1, + LSM6DSV_SH_30Hz = 0x2, + LSM6DSV_SH_60Hz = 0x3, + LSM6DSV_SH_120Hz = 0x4, + LSM6DSV_SH_240Hz = 0x5, + LSM6DSV_SH_480Hz = 0x6, +} lsm6dsv_sh_data_rate_t; +int32_t lsm6dsv_sh_data_rate_set(stmdev_ctx_t *ctx, + lsm6dsv_sh_data_rate_t val); +int32_t lsm6dsv_sh_data_rate_get(stmdev_ctx_t *ctx, + lsm6dsv_sh_data_rate_t *val); + +typedef struct +{ + uint8_t slv_add; + uint8_t slv_subadd; + uint8_t slv_len; +} lsm6dsv_sh_cfg_read_t; +int32_t lsm6dsv_sh_slv0_cfg_read(stmdev_ctx_t *ctx, + lsm6dsv_sh_cfg_read_t *val); +int32_t lsm6dsv_sh_slv1_cfg_read(stmdev_ctx_t *ctx, + lsm6dsv_sh_cfg_read_t *val); +int32_t lsm6dsv_sh_slv2_cfg_read(stmdev_ctx_t *ctx, + lsm6dsv_sh_cfg_read_t *val); +int32_t lsm6dsv_sh_slv3_cfg_read(stmdev_ctx_t *ctx, + lsm6dsv_sh_cfg_read_t *val); + +int32_t lsm6dsv_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV_I2C_I3C_ENABLE = 0x0, + LSM6DSV_I2C_I3C_DISABLE = 0x1, +} lsm6dsv_ui_i2c_i3c_mode_t; +int32_t lsm6dsv_ui_i2c_i3c_mode_set(stmdev_ctx_t *ctx, + lsm6dsv_ui_i2c_i3c_mode_t val); +int32_t lsm6dsv_ui_i2c_i3c_mode_get(stmdev_ctx_t *ctx, + lsm6dsv_ui_i2c_i3c_mode_t *val); + +typedef enum +{ + LSM6DSV_SPI_4_WIRE = 0x0, + LSM6DSV_SPI_3_WIRE = 0x1, +} lsm6dsv_spi_mode_t; +int32_t lsm6dsv_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsv_spi_mode_t val); +int32_t lsm6dsv_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsv_spi_mode_t *val); + +int32_t lsm6dsv_ui_sda_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_ui_sda_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV_SPI2_4_WIRE = 0x0, + LSM6DSV_SPI2_3_WIRE = 0x1, +} lsm6dsv_spi2_mode_t; +int32_t lsm6dsv_spi2_mode_set(stmdev_ctx_t *ctx, lsm6dsv_spi2_mode_t val); +int32_t lsm6dsv_spi2_mode_get(stmdev_ctx_t *ctx, + lsm6dsv_spi2_mode_t *val); + +int32_t lsm6dsv_sigmot_mode_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_sigmot_mode_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t step_counter_enable : 1; + uint8_t false_step_rej : 1; +} lsm6dsv_stpcnt_mode_t; +int32_t lsm6dsv_stpcnt_mode_set(stmdev_ctx_t *ctx, + lsm6dsv_stpcnt_mode_t val); +int32_t lsm6dsv_stpcnt_mode_get(stmdev_ctx_t *ctx, + lsm6dsv_stpcnt_mode_t *val); + +int32_t lsm6dsv_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val); + +int32_t lsm6dsv_stpcnt_rst_step_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_stpcnt_rst_step_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv_stpcnt_debounce_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_stpcnt_debounce_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv_stpcnt_period_get(stmdev_ctx_t *ctx, uint16_t *val); + +typedef struct +{ + uint8_t tap_x_en : 1; + uint8_t tap_y_en : 1; + uint8_t tap_z_en : 1; +} lsm6dsv_tap_detection_t; +int32_t lsm6dsv_tap_detection_set(stmdev_ctx_t *ctx, + lsm6dsv_tap_detection_t val); +int32_t lsm6dsv_tap_detection_get(stmdev_ctx_t *ctx, + lsm6dsv_tap_detection_t *val); + +typedef struct +{ + uint8_t x : 5; + uint8_t y : 5; + uint8_t z : 5; +} lsm6dsv_tap_thresholds_t; +int32_t lsm6dsv_tap_thresholds_set(stmdev_ctx_t *ctx, + lsm6dsv_tap_thresholds_t val); +int32_t lsm6dsv_tap_thresholds_get(stmdev_ctx_t *ctx, + lsm6dsv_tap_thresholds_t *val); + +typedef enum +{ + LSM6DSV_XYZ = 0x0, + LSM6DSV_YXZ = 0x1, + LSM6DSV_XZY = 0x2, + LSM6DSV_ZYX = 0x3, + LSM6DSV_YZX = 0x5, + LSM6DSV_ZXY = 0x6, +} lsm6dsv_tap_axis_priority_t; +int32_t lsm6dsv_tap_axis_priority_set(stmdev_ctx_t *ctx, + lsm6dsv_tap_axis_priority_t val); +int32_t lsm6dsv_tap_axis_priority_get(stmdev_ctx_t *ctx, + lsm6dsv_tap_axis_priority_t *val); + +typedef struct +{ + uint8_t shock : 2; + uint8_t quiet : 2; + uint8_t tap_gap : 4; +} lsm6dsv_tap_time_windows_t; +int32_t lsm6dsv_tap_time_windows_set(stmdev_ctx_t *ctx, + lsm6dsv_tap_time_windows_t val); +int32_t lsm6dsv_tap_time_windows_get(stmdev_ctx_t *ctx, + lsm6dsv_tap_time_windows_t *val); + +typedef enum +{ + LSM6DSV_ONLY_SINGLE = 0x0, + LSM6DSV_BOTH_SINGLE_DOUBLE = 0x1, +} lsm6dsv_tap_mode_t; +int32_t lsm6dsv_tap_mode_set(stmdev_ctx_t *ctx, lsm6dsv_tap_mode_t val); +int32_t lsm6dsv_tap_mode_get(stmdev_ctx_t *ctx, lsm6dsv_tap_mode_t *val); + +int32_t lsm6dsv_tilt_mode_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_tilt_mode_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); + +int32_t lsm6dsv_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV_XL_AND_GY_NOT_AFFECTED = 0x0, + LSM6DSV_XL_LOW_POWER_GY_NOT_AFFECTED = 0x1, + LSM6DSV_XL_LOW_POWER_GY_SLEEP = 0x2, + LSM6DSV_XL_LOW_POWER_GY_POWER_DOWN = 0x3, +} lsm6dsv_act_mode_t; +int32_t lsm6dsv_act_mode_set(stmdev_ctx_t *ctx, lsm6dsv_act_mode_t val); +int32_t lsm6dsv_act_mode_get(stmdev_ctx_t *ctx, lsm6dsv_act_mode_t *val); + +typedef enum +{ + LSM6DSV_SLEEP_TO_ACT_AT_1ST_SAMPLE = 0x0, + LSM6DSV_SLEEP_TO_ACT_AT_2ND_SAMPLE = 0x1, + LSM6DSV_SLEEP_TO_ACT_AT_3RD_SAMPLE = 0x2, + LSM6DSV_SLEEP_TO_ACT_AT_4th_SAMPLE = 0x3, +} lsm6dsv_act_from_sleep_to_act_dur_t; +int32_t lsm6dsv_act_from_sleep_to_act_dur_set(stmdev_ctx_t *ctx, + lsm6dsv_act_from_sleep_to_act_dur_t val); +int32_t lsm6dsv_act_from_sleep_to_act_dur_get(stmdev_ctx_t *ctx, + lsm6dsv_act_from_sleep_to_act_dur_t *val); + +typedef enum +{ + LSM6DSV_1Hz875 = 0x0, + LSM6DSV_15Hz = 0x1, + LSM6DSV_30Hz = 0x2, + LSM6DSV_60Hz = 0x3, +} lsm6dsv_act_sleep_xl_odr_t; +int32_t lsm6dsv_act_sleep_xl_odr_set(stmdev_ctx_t *ctx, + lsm6dsv_act_sleep_xl_odr_t val); +int32_t lsm6dsv_act_sleep_xl_odr_get(stmdev_ctx_t *ctx, + lsm6dsv_act_sleep_xl_odr_t *val); + +typedef struct +{ + lsm6dsv_inactivity_dur_t inactivity_cfg; + uint8_t inactivity_ths; + uint8_t threshold; + uint8_t duration; +} lsm6dsv_act_thresholds_t; +int32_t lsm6dsv_act_thresholds_set(stmdev_ctx_t *ctx, + lsm6dsv_act_thresholds_t *val); +int32_t lsm6dsv_act_thresholds_get(stmdev_ctx_t *ctx, + lsm6dsv_act_thresholds_t *val); + +typedef struct +{ + uint8_t shock : 2; + uint8_t quiet : 4; +} lsm6dsv_act_wkup_time_windows_t; +int32_t lsm6dsv_act_wkup_time_windows_set(stmdev_ctx_t *ctx, + lsm6dsv_act_wkup_time_windows_t val); +int32_t lsm6dsv_act_wkup_time_windows_get(stmdev_ctx_t *ctx, + lsm6dsv_act_wkup_time_windows_t *val); + +/** + * @} + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /*LSM6DSV_DRIVER_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.c b/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.c index 7d319e171a73a953c281c093ae09e530a32b50d7..2a715b5187d90f7bb46000c4a3606652123441f1 100644 --- a/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.c +++ b/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm9ds1_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lsm9ds1_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t lsm9ds1_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm9ds1_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak lsm9ds1_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.h b/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.h index 800fcaed318c9df5827964ae14cefa4475de5bf9..925c51fd90a36c36b99136602e6533960f2e3ec3 100644 --- a/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.h +++ b/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -941,6 +944,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t lsm9ds1_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.c b/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.c index 161fc89e73750e01ff2d06b57e392c1e9e00f60e..fdd0a0bafaf16d5ce46ca72b42897f65fcfc2224 100644 --- a/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.c +++ b/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t stts22h_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak stts22h_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t stts22h_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t stts22h_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak stts22h_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.h b/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.h index 2ed5c4b74a94409218e4cd3865944724615d01a5..934640dc41ac6b67b14c9ab21cacf78a559e3741 100644 --- a/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.h +++ b/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -277,6 +280,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t stts22h_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); diff --git a/sensor/stmemsc/stts751_STdC/driver/stts751_reg.c b/sensor/stmemsc/stts751_STdC/driver/stts751_reg.c index b44227771803c34f3a8cb2e6fba09d1dbbe99840..552b99bb648ed70a1536ea299d996f3bd51951cb 100644 --- a/sensor/stmemsc/stts751_STdC/driver/stts751_reg.c +++ b/sensor/stmemsc/stts751_STdC/driver/stts751_reg.c @@ -46,9 +46,9 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t stts751_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak stts751_read_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; @@ -67,9 +67,9 @@ int32_t stts751_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t stts751_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) +int32_t __weak stts751_write_reg(stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) { int32_t ret; diff --git a/sensor/stmemsc/stts751_STdC/driver/stts751_reg.h b/sensor/stmemsc/stts751_STdC/driver/stts751_reg.h index 9e5318b2447b94478c329ea6c81c757fe769f16b..f5f59c67374eea8c06307bbd92eeebeec81bdd54 100644 --- a/sensor/stmemsc/stts751_STdC/driver/stts751_reg.h +++ b/sensor/stmemsc/stts751_STdC/driver/stts751_reg.h @@ -111,12 +111,15 @@ typedef struct typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct { /** Component mandatory fields **/ stmdev_write_ptr write_reg; stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; } stmdev_ctx_t; @@ -290,6 +293,19 @@ typedef union * */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + int32_t stts751_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len);