diff --git a/sensor/stmemsc/CMakeLists.txt b/sensor/stmemsc/CMakeLists.txt
index b1397e65f6afa695254724df90b4e919b6af7229..c28b24b93c7f03f5ed3704ae48970ae0ca8f115d 100644
--- a/sensor/stmemsc/CMakeLists.txt
+++ b/sensor/stmemsc/CMakeLists.txt
@@ -7,6 +7,7 @@
set(stmems_pids
a3g4250d
ais2dw12
+ ais2ih
ais328dq
ais3624dq
asm330lhh
@@ -40,9 +41,11 @@ set(stmems_pids
lis3dhh
lis3dsh
lis3mdl
+ lps22ch
lps22hb
lps22hh
lps25hb
+ lps27hhtw
lps27hhw
lps33hw
lps33k
@@ -50,11 +53,12 @@ set(stmems_pids
lsm303agr
lsm303ah
lsm6ds3
- lsm6ds3tr_c
+ lsm6ds3tr-c
lsm6dsl
lsm6dsm
lsm6dso
lsm6dso32
+ lsm6dso32x
lsm6dsox
lsm6dsr
lsm6dsrx
diff --git a/sensor/stmemsc/README b/sensor/stmemsc/README
index eb2203dfd2f904ff1e76b21ec352c9dc2a17a41c..3ce80d52b6ac585a2b67e2261f7b0ee5e078a09f 100644
--- a/sensor/stmemsc/README
+++ b/sensor/stmemsc/README
@@ -6,7 +6,7 @@ Origin:
https://www.st.com/en/embedded-software/c-driver-mems.html
Status:
- version v1.03
+ version v2.00
Purpose:
ST Microelectronics standard C platform-independent drivers for MEMS
@@ -31,7 +31,7 @@ Description:
I2C or SPI platform driver like the following:
/** Please note that is MANDATORY: return 0 -> no Error.**/
- int platform_wr(void *handle, u8_t reg, u8_t *bufp, u16_t len);
+ int platform_wr(void *handle, u8_t reg, const u8_t *bufp, u16_t len);
int platform_rd(void *handle, u8_t reg, u8_t *bufp, u16_t len);
stmdev_ctx_t stmdev_ctx = {
@@ -46,7 +46,7 @@ URL:
https://www.st.com/en/embedded-software/c-driver-mems.html
commit:
- version v1.03
+ version v2.00
Maintained-by:
ST Microelectronics
diff --git a/sensor/stmemsc/_resources/FIFO_decompression_utility/fifo_utility.c b/sensor/stmemsc/_resources/FIFO_decompression_utility/fifo_utility.c
index c2a0db4f9a640428e9e0d5ed348912d582de4064..bfb70e8f050cb32bd0a1ec5cf1e8a3c4236c375a 100644
--- a/sensor/stmemsc/_resources/FIFO_decompression_utility/fifo_utility.c
+++ b/sensor/stmemsc/_resources/FIFO_decompression_utility/fifo_utility.c
@@ -94,7 +94,8 @@ static st_fifo_compression_type get_compression_type(uint8_t tag);
static uint8_t is_tag_valid(uint8_t tag);
static void get_diff_2x(int16_t diff[6], uint8_t input[6]);
static void get_diff_3x(int16_t diff[9], uint8_t input[6]);
-static void byte_cpy(uint8_t *destination, uint8_t *source, uint32_t len);
+static void byte_cpy(uint8_t *destination, uint8_t *source,
+ uint32_t len);
/* Private variables ---------------------------------------------------------*/
static uint8_t tag_counter_old = 0x00U;
@@ -114,7 +115,7 @@ static int16_t last_data_gy[3] = {0};
/**
* @defgroup FIFO_pubblic_functions
- * @brief This section provide a set of usefull APIs for managing data
+ * @brief This section provide a set of useful APIs for managing data
* compression in smart FIFO.
* @{
*
@@ -143,11 +144,12 @@ st_fifo_status st_fifo_init(float_t bdr_xl_in,
uint32_t i;
st_fifo_status ret = ST_FIFO_ERR;
- if ((bdr_xl_in < 0.0f) || (bdr_gy_in < 0.0f) || (bdr_vsens_in < 0.0f)) {
+ if ((bdr_xl_in < 0.0f) || (bdr_gy_in < 0.0f) ||
+ (bdr_vsens_in < 0.0f)) {
ret = ST_FIFO_ERR;
}
- else {
+ else {
tag_counter_old = 0x00U;
bdr_xl = bdr_xl_in;
bdr_gy = bdr_gy_in;
@@ -165,7 +167,6 @@ st_fifo_status st_fifo_init(float_t bdr_xl_in,
for (i = 0; i < 3U; i++) {
last_data_xl[i] = 0;
last_data_gy[i] = 0;
-
ret = ST_FIFO_OK;
}
}
@@ -199,39 +200,37 @@ st_fifo_status st_fifo_decompress(st_fifo_out_slot *fifo_out_slot,
uint8_t bdr_vsens_cfg;
uint32_t last_timestamp;
int16_t diff[9];
-
- float_t bdr_acc_vect[] = { 0, 13 , 26, 52, 104,
- 208, 416 , 833, 1666, 3333,
- 6666, 1.625, 0, 0, 0,
- 0 };
-
+ float_t bdr_acc_vect[] = { 0, 13, 26, 52, 104,
+ 208, 416, 833, 1666, 3333,
+ 6666, 1.625, 0, 0, 0,
+ 0
+ };
float_t bdr_gyr_vect[] = { 0, 13, 26, 52, 104, 208, 416,
- 833, 1666, 3333, 6666, 0, 0, 0,
- 0, 0};
-
- float_t bdr_vsens_vect[] = { 0, 13, 26, 52, 104 , 208, 416,
+ 833, 1666, 3333, 6666, 0, 0, 0,
+ 0, 0
+ };
+ float_t bdr_vsens_vect[] = { 0, 13, 26, 52, 104, 208, 416,
0, 0, 0, 0, 1.625, 0, 0,
- 0, 0};
+ 0, 0
+ };
for (uint16_t i = 0; i < stream_size; i++) {
-
tag = (fifo_raw_slot[i].fifo_data_out[0] & TAG_SENSOR_MASK);
tag = tag >> TAG_SENSOR_SHIFT;
-
tag_counter = (fifo_raw_slot[i].fifo_data_out[0] & TAG_COUNTER_MASK);
tag_counter = tag_counter >> TAG_COUNTER_SHIFT;
if ((has_even_parity(fifo_raw_slot[i].fifo_data_out[0]) == 0U) ||
- (is_tag_valid(tag) == 0U)){
+ (is_tag_valid(tag) == 0U)) {
return ST_FIFO_ERR;
}
if ((tag_counter != (tag_counter_old)) && (bdr_max != 0.0f)) {
-
- if (tag_counter < tag_counter_old){
+ if (tag_counter < tag_counter_old) {
diff_tag_counter = tag_counter + 4U - tag_counter_old;
}
- else{
+
+ else {
diff_tag_counter = tag_counter - tag_counter_old;
}
@@ -239,44 +238,40 @@ st_fifo_status st_fifo_decompress(st_fifo_out_slot *fifo_out_slot,
}
if (tag == TAG_ODRCHG) {
-
bdr_acc_cfg = (fifo_raw_slot[i].fifo_data_out[6] & BDR_XL_MASK);
bdr_acc_cfg = bdr_acc_cfg >> BDR_XL_SHIFT;
-
bdr_gyr_cfg = (fifo_raw_slot[i].fifo_data_out[6] & BDR_GY_MASK);
bdr_gyr_cfg = bdr_gyr_cfg >> BDR_GY_SHIFT;
-
- bdr_vsens_cfg =(fifo_raw_slot[i].fifo_data_out[3] & BDR_VSENS_MASK);
+ bdr_vsens_cfg = (fifo_raw_slot[i].fifo_data_out[3] & BDR_VSENS_MASK);
bdr_vsens_cfg = bdr_vsens_cfg >> BDR_VSENS_SHIFT;
-
bdr_xl_old = bdr_xl;
bdr_gy_old = bdr_gy;
-
bdr_xl = bdr_acc_vect[bdr_acc_cfg];
bdr_gy = bdr_gyr_vect[bdr_gyr_cfg];
bdr_vsens = bdr_vsens_vect[bdr_vsens_cfg];
bdr_max = ((bdr_xl > bdr_gy) ? bdr_xl : bdr_gy);
bdr_max = ((bdr_max > bdr_vsens) ? bdr_max : bdr_vsens);
-
bdr_chg_xl_flag = 1;
bdr_chg_gy_flag = 1;
+ }
- } else if (tag == TAG_TS) {
-
- byte_cpy( (uint8_t*)×tamp, &fifo_raw_slot[i].fifo_data_out[1], 4);
-
- } else {
+ else if (tag == TAG_TS) {
+ byte_cpy( (uint8_t *)×tamp, &fifo_raw_slot[i].fifo_data_out[1],
+ 4);
+ }
+ else {
st_fifo_compression_type compression_type = get_compression_type(tag);
st_fifo_sensor_type sensor_type = get_sensor_type(tag);
- switch (compression_type){
+ switch (compression_type) {
case ST_FIFO_COMPRESSION_NC:
- if (tag == TAG_STEP_COUNTER){
- byte_cpy((uint8_t*)&fifo_out_slot[j].timestamp,
+ if (tag == TAG_STEP_COUNTER) {
+ byte_cpy((uint8_t *)&fifo_out_slot[j].timestamp,
&fifo_raw_slot[i].fifo_data_out[3], 4);
}
- else{
+
+ else {
fifo_out_slot[j].timestamp = timestamp;
}
@@ -285,128 +280,127 @@ st_fifo_status st_fifo_decompress(st_fifo_out_slot *fifo_out_slot,
&fifo_raw_slot[i].fifo_data_out[1], 6);
if (sensor_type == ST_FIFO_ACCELEROMETER) {
- byte_cpy((uint8_t*)last_data_xl, fifo_out_slot[j].raw_data, 6);
+ byte_cpy((uint8_t *)last_data_xl, fifo_out_slot[j].raw_data, 6);
last_timestamp_xl = timestamp;
bdr_chg_xl_flag = 0;
}
if (sensor_type == ST_FIFO_GYROSCOPE) {
- byte_cpy((uint8_t*)last_data_gy, fifo_out_slot[j].raw_data, 6);
+ byte_cpy((uint8_t *)last_data_gy, fifo_out_slot[j].raw_data, 6);
last_timestamp_gy = timestamp;
bdr_chg_gy_flag = 0;
}
j++;
break;
+
case ST_FIFO_COMPRESSION_NC_T_1:
fifo_out_slot[j].sensor_tag = get_sensor_type(tag);
byte_cpy(fifo_out_slot[j].raw_data,
&fifo_raw_slot[i].fifo_data_out[1], 6);
if (sensor_type == ST_FIFO_ACCELEROMETER) {
-
-
- if (bdr_chg_xl_flag != 0U){
+ if (bdr_chg_xl_flag != 0U) {
last_timestamp = (last_timestamp_xl +
(TIMESTAMP_FREQ / (uint32_t)bdr_xl_old));
}
- else{
+
+ else {
last_timestamp = ((uint32_t)timestamp -
((uint32_t)TIMESTAMP_FREQ / (uint32_t)bdr_xl));
}
fifo_out_slot[j].timestamp = last_timestamp;
- byte_cpy((uint8_t*)last_data_xl,
- (uint8_t*) fifo_out_slot[j].raw_data, 6);
+ byte_cpy((uint8_t *)last_data_xl,
+ (uint8_t *) fifo_out_slot[j].raw_data, 6);
last_timestamp_xl = last_timestamp;
}
if (sensor_type == ST_FIFO_GYROSCOPE) {
-
-
- if (bdr_chg_gy_flag != 0U){
+ if (bdr_chg_gy_flag != 0U) {
last_timestamp = (last_timestamp_gy +
(TIMESTAMP_FREQ / (uint32_t)bdr_gy_old));
}
- else{
+
+ else {
last_timestamp = (timestamp -
(TIMESTAMP_FREQ / (uint32_t)bdr_gy));
}
fifo_out_slot[j].timestamp = last_timestamp;
- byte_cpy((uint8_t*)last_data_gy, fifo_out_slot[j].raw_data, 6);
+ byte_cpy((uint8_t *)last_data_gy, fifo_out_slot[j].raw_data, 6);
last_timestamp_gy = last_timestamp;
}
j++;
break;
+
case ST_FIFO_COMPRESSION_NC_T_2:
fifo_out_slot[j].sensor_tag = get_sensor_type(tag);
byte_cpy(fifo_out_slot[j].raw_data,
&fifo_raw_slot[i].fifo_data_out[1], 6);
if (sensor_type == ST_FIFO_ACCELEROMETER) {
- if (bdr_chg_xl_flag != 0U){
+ if (bdr_chg_xl_flag != 0U) {
last_timestamp = (last_timestamp_xl +
(TIMESTAMP_FREQ / (uint32_t)bdr_xl_old));
}
- else{
+
+ else {
last_timestamp = (timestamp -
((2U * TIMESTAMP_FREQ) / (uint32_t) bdr_xl));
}
fifo_out_slot[j].timestamp = last_timestamp;
- byte_cpy((uint8_t*)last_data_xl, fifo_out_slot[j].raw_data, 6);
+ byte_cpy((uint8_t *)last_data_xl, fifo_out_slot[j].raw_data, 6);
last_timestamp_xl = last_timestamp;
}
- if (sensor_type == ST_FIFO_GYROSCOPE) {
- if (bdr_chg_gy_flag != 0U){
+ if (sensor_type == ST_FIFO_GYROSCOPE) {
+ if (bdr_chg_gy_flag != 0U) {
last_timestamp = (last_timestamp_gy +
(TIMESTAMP_FREQ / (uint32_t)bdr_gy_old));
}
- else{
+
+ else {
last_timestamp = (timestamp -
(2U * TIMESTAMP_FREQ / (uint32_t)bdr_gy));
}
fifo_out_slot[j].timestamp = last_timestamp;
- byte_cpy((uint8_t*)last_data_gy,
- (uint8_t*)fifo_out_slot[j].raw_data, 6);
+ byte_cpy((uint8_t *)last_data_gy,
+ (uint8_t *)fifo_out_slot[j].raw_data, 6);
last_timestamp_gy = last_timestamp;
}
j++;
break;
+
case ST_FIFO_COMPRESSION_2X:
get_diff_2x(diff, &fifo_raw_slot[i].fifo_data_out[1]);
-
fifo_out_slot[j].sensor_tag = sensor_type;
if (sensor_type == ST_FIFO_ACCELEROMETER) {
data[0] = last_data_xl[0] + diff[0];
data[1] = last_data_xl[1] + diff[1];
data[2] = last_data_xl[2] + diff[2];
- byte_cpy(fifo_out_slot[j].raw_data,(uint8_t*)data, 6);
+ byte_cpy(fifo_out_slot[j].raw_data, (uint8_t *)data, 6);
fifo_out_slot[j].timestamp =
- (timestamp - (2U * TIMESTAMP_FREQ / (uint32_t)bdr_xl));
-
- byte_cpy((uint8_t*)last_data_xl, fifo_out_slot[j].raw_data, 6);
+ (timestamp - (2U * TIMESTAMP_FREQ / (uint32_t)bdr_xl));
+ byte_cpy((uint8_t *)last_data_xl, fifo_out_slot[j].raw_data, 6);
}
if (sensor_type == ST_FIFO_GYROSCOPE) {
data[0] = last_data_gy[0] + diff[0];
data[1] = last_data_gy[1] + diff[1];
data[2] = last_data_gy[2] + diff[2];
- byte_cpy(fifo_out_slot[j].raw_data,(uint8_t*)data, 6);
+ byte_cpy(fifo_out_slot[j].raw_data, (uint8_t *)data, 6);
fifo_out_slot[j].timestamp =
- (timestamp - (2U * TIMESTAMP_FREQ / (uint32_t)bdr_gy));
-
- byte_cpy((uint8_t*)last_data_gy, fifo_out_slot[j].raw_data, 6);
+ (timestamp - (2U * TIMESTAMP_FREQ / (uint32_t)bdr_gy));
+ byte_cpy((uint8_t *)last_data_gy, fifo_out_slot[j].raw_data, 6);
}
j++;
-
fifo_out_slot[j].sensor_tag = sensor_type;
if (sensor_type == ST_FIFO_ACCELEROMETER) {
@@ -414,9 +408,9 @@ st_fifo_status st_fifo_decompress(st_fifo_out_slot *fifo_out_slot,
data[0] = last_data_xl[0] + diff[3];
data[1] = last_data_xl[1] + diff[4];
data[2] = last_data_xl[2] + diff[5];
- byte_cpy(fifo_out_slot[j].raw_data,(uint8_t*)data, 6);
+ byte_cpy(fifo_out_slot[j].raw_data, (uint8_t *)data, 6);
fifo_out_slot[j].timestamp = last_timestamp;
- byte_cpy((uint8_t*)last_data_xl, fifo_out_slot[j].raw_data, 6);
+ byte_cpy((uint8_t *)last_data_xl, fifo_out_slot[j].raw_data, 6);
last_timestamp_xl = last_timestamp;
}
@@ -425,67 +419,64 @@ st_fifo_status st_fifo_decompress(st_fifo_out_slot *fifo_out_slot,
data[0] = last_data_gy[0] + diff[3];
data[1] = last_data_gy[1] + diff[4];
data[2] = last_data_gy[2] + diff[5];
- byte_cpy(fifo_out_slot[j].raw_data,(uint8_t*)data, 6);
+ byte_cpy(fifo_out_slot[j].raw_data, (uint8_t *)data, 6);
fifo_out_slot[j].timestamp = last_timestamp;
- byte_cpy((uint8_t*)last_data_gy, fifo_out_slot[j].raw_data, 6);
+ byte_cpy((uint8_t *)last_data_gy, fifo_out_slot[j].raw_data, 6);
last_timestamp_gy = last_timestamp;
}
j++;
break;
- default: //(compression_type == ST_FIFO_COMPRESSION_3X)
+ default: //(compression_type == ST_FIFO_COMPRESSION_3X)
get_diff_3x(diff, &fifo_raw_slot[i].fifo_data_out[1]);
-
fifo_out_slot[j].sensor_tag = sensor_type;
if (sensor_type == ST_FIFO_ACCELEROMETER) {
data[0] = last_data_xl[0] + diff[0];
data[1] = last_data_xl[1] + diff[1];
data[2] = last_data_xl[2] + diff[2];
- byte_cpy(fifo_out_slot[j].raw_data,(uint8_t*)data, 6);
+ byte_cpy(fifo_out_slot[j].raw_data, (uint8_t *)data, 6);
fifo_out_slot[j].timestamp =
- (timestamp - (2U * TIMESTAMP_FREQ / (uint32_t)bdr_xl));
- byte_cpy((uint8_t*)last_data_xl, fifo_out_slot[j].raw_data, 6);
+ (timestamp - (2U * TIMESTAMP_FREQ / (uint32_t)bdr_xl));
+ byte_cpy((uint8_t *)last_data_xl, fifo_out_slot[j].raw_data, 6);
}
if (sensor_type == ST_FIFO_GYROSCOPE) {
data[0] = last_data_gy[0] + diff[0];
data[1] = last_data_gy[1] + diff[1];
data[2] = last_data_gy[2] + diff[2];
- byte_cpy(fifo_out_slot[j].raw_data,(uint8_t*)data, 6);
+ byte_cpy(fifo_out_slot[j].raw_data, (uint8_t *)data, 6);
fifo_out_slot[j].timestamp =
- (timestamp - (2U * TIMESTAMP_FREQ / (uint32_t)bdr_gy));
- byte_cpy((uint8_t*)last_data_gy,
- (uint8_t*)fifo_out_slot[j].raw_data, 6);
+ (timestamp - (2U * TIMESTAMP_FREQ / (uint32_t)bdr_gy));
+ byte_cpy((uint8_t *)last_data_gy,
+ (uint8_t *)fifo_out_slot[j].raw_data, 6);
}
j++;
-
fifo_out_slot[j].sensor_tag = sensor_type;
if (sensor_type == ST_FIFO_ACCELEROMETER) {
data[0] = last_data_xl[0] + diff[3];
data[1] = last_data_xl[1] + diff[4];
data[2] = last_data_xl[2] + diff[5];
- byte_cpy(fifo_out_slot[j].raw_data,(uint8_t*)data, 6);
+ byte_cpy(fifo_out_slot[j].raw_data, (uint8_t *)data, 6);
fifo_out_slot[j].timestamp =
- (timestamp -(TIMESTAMP_FREQ / (uint32_t)bdr_xl));
- byte_cpy((uint8_t*)last_data_xl, fifo_out_slot[j].raw_data, 6);
+ (timestamp - (TIMESTAMP_FREQ / (uint32_t)bdr_xl));
+ byte_cpy((uint8_t *)last_data_xl, fifo_out_slot[j].raw_data, 6);
}
if (sensor_type == ST_FIFO_GYROSCOPE) {
data[0] = last_data_gy[0] + diff[3];
data[1] = last_data_gy[1] + diff[4];
data[2] = last_data_gy[2] + diff[5];
- byte_cpy(fifo_out_slot[j].raw_data,(uint8_t*)data, 6);
+ byte_cpy(fifo_out_slot[j].raw_data, (uint8_t *)data, 6);
fifo_out_slot[j].timestamp =
- (timestamp - (TIMESTAMP_FREQ / (uint32_t)bdr_gy));
- byte_cpy((uint8_t*)last_data_gy, fifo_out_slot[j].raw_data, 6);
+ (timestamp - (TIMESTAMP_FREQ / (uint32_t)bdr_gy));
+ byte_cpy((uint8_t *)last_data_gy, fifo_out_slot[j].raw_data, 6);
}
j++;
-
fifo_out_slot[j].timestamp = timestamp;
fifo_out_slot[j].sensor_tag = sensor_type;
@@ -493,8 +484,8 @@ st_fifo_status st_fifo_decompress(st_fifo_out_slot *fifo_out_slot,
data[0] = last_data_xl[0] + diff[6];
data[1] = last_data_xl[1] + diff[7];
data[2] = last_data_xl[2] + diff[8];
- byte_cpy(fifo_out_slot[j].raw_data,(uint8_t*)data, 6);
- byte_cpy((uint8_t*)last_data_xl, fifo_out_slot[j].raw_data, 6);
+ byte_cpy(fifo_out_slot[j].raw_data, (uint8_t *)data, 6);
+ byte_cpy((uint8_t *)last_data_xl, fifo_out_slot[j].raw_data, 6);
last_timestamp_xl = timestamp;
}
@@ -502,18 +493,18 @@ st_fifo_status st_fifo_decompress(st_fifo_out_slot *fifo_out_slot,
data[0] = last_data_gy[0] + diff[6];
data[1] = last_data_gy[1] + diff[7];
data[2] = last_data_gy[2] + diff[8];
- byte_cpy(fifo_out_slot[j].raw_data,(uint8_t*)data, 6);
- byte_cpy((uint8_t*)last_data_gy, fifo_out_slot[j].raw_data, 6);
+ byte_cpy(fifo_out_slot[j].raw_data, (uint8_t *)data, 6);
+ byte_cpy((uint8_t *)last_data_gy, fifo_out_slot[j].raw_data, 6);
last_timestamp_gy = timestamp;
}
j++;
break;
- }
-
- *out_slot_size = j;
}
+ *out_slot_size = j;
+ }
+
tag_counter_old = tag_counter;
}
@@ -527,29 +518,27 @@ st_fifo_status st_fifo_decompress(st_fifo_out_slot *fifo_out_slot,
* @param out_slot_size decoded srteam size.
*
*/
-void st_fifo_sort(st_fifo_out_slot *fifo_out_slot, uint16_t out_slot_size)
+void st_fifo_sort(st_fifo_out_slot *fifo_out_slot,
+ uint16_t out_slot_size)
{
-
int32_t j, i;
st_fifo_out_slot temp;
for (i = 1; i < (int32_t)out_slot_size; i++) {
-
- byte_cpy((uint8_t*)&temp, (uint8_t*)&fifo_out_slot[i],
+ byte_cpy((uint8_t *)&temp, (uint8_t *)&fifo_out_slot[i],
sizeof(st_fifo_out_slot));
-
j = i - 1;
while ((j >= 0) && (fifo_out_slot[j].timestamp > temp.timestamp)) {
- byte_cpy((uint8_t*)&fifo_out_slot[j + 1], (uint8_t*)&fifo_out_slot[j],
+ byte_cpy((uint8_t *)&fifo_out_slot[j + 1],
+ (uint8_t *)&fifo_out_slot[j],
sizeof(st_fifo_out_slot));
j--;
}
- byte_cpy((uint8_t*)&fifo_out_slot[j + 1], (uint8_t*)&temp,
+ byte_cpy((uint8_t *)&fifo_out_slot[j + 1], (uint8_t *)&temp,
sizeof(st_fifo_out_slot));
}
-
}
/**
@@ -565,18 +554,17 @@ void st_fifo_sort(st_fifo_out_slot *fifo_out_slot, uint16_t out_slot_size)
* decoded FIFO stream.
*
*/
-uint16_t st_fifo_get_sensor_occurrence(st_fifo_out_slot *fifo_out_slot,
+uint16_t st_fifo_get_sensor_occurrence(st_fifo_out_slot
+ *fifo_out_slot,
uint16_t out_slot_size,
st_fifo_sensor_type sensor_type)
{
uint16_t occurrence = 0;
for (uint16_t i = 0; i < out_slot_size; i++) {
-
- if (fifo_out_slot[i].sensor_tag == sensor_type){
+ if (fifo_out_slot[i].sensor_tag == sensor_type) {
occurrence++;
}
-
}
return occurrence;
@@ -601,15 +589,12 @@ void st_fifo_extract_sensor(st_fifo_out_slot *sensor_out_slot,
uint16_t temp_i = 0;
for (uint16_t i = 0; i < out_slot_size; i++) {
-
if (fifo_out_slot[i].sensor_tag == sensor_type) {
-
- byte_cpy((uint8_t*)&sensor_out_slot[temp_i], (uint8_t*)&fifo_out_slot[i],
+ byte_cpy((uint8_t *)&sensor_out_slot[temp_i],
+ (uint8_t *)&fifo_out_slot[i],
sizeof(st_fifo_out_slot));
-
temp_i++;
}
-
}
}
@@ -638,10 +623,11 @@ static uint8_t is_tag_valid(uint8_t tag)
{
uint8_t ret;
- if (tag > TAG_VALID_LIMIT){
+ if (tag > TAG_VALID_LIMIT) {
ret = 0;
}
- else{
+
+ else {
ret = 1;
}
@@ -659,81 +645,105 @@ static uint8_t is_tag_valid(uint8_t tag)
static st_fifo_sensor_type get_sensor_type(uint8_t tag)
{
st_fifo_sensor_type ret;
+
switch (tag) {
case TAG_GY:
ret = ST_FIFO_GYROSCOPE;
break;
+
case TAG_XL:
ret = ST_FIFO_ACCELEROMETER;
break;
+
case TAG_TEMP:
ret = ST_FIFO_TEMPERATURE;
break;
+
case TAG_EXT_SENS_0:
ret = ST_FIFO_EXT_SENSOR0;
break;
+
case TAG_EXT_SENS_1:
ret = ST_FIFO_EXT_SENSOR1;
break;
+
case TAG_EXT_SENS_2:
ret = ST_FIFO_EXT_SENSOR2;
break;
+
case TAG_EXT_SENS_3:
ret = ST_FIFO_EXT_SENSOR3;
break;
+
case TAG_STEP_COUNTER:
ret = ST_FIFO_STEP_COUNTER;
break;
+
case TAG_XL_UNCOMPRESSED_T_2:
ret = ST_FIFO_ACCELEROMETER;
break;
+
case TAG_XL_UNCOMPRESSED_T_1:
ret = ST_FIFO_ACCELEROMETER;
break;
+
case TAG_XL_COMPRESSED_2X:
ret = ST_FIFO_ACCELEROMETER;
break;
+
case TAG_XL_COMPRESSED_3X:
ret = ST_FIFO_ACCELEROMETER;
break;
+
case TAG_GY_UNCOMPRESSED_T_2:
ret = ST_FIFO_GYROSCOPE;
break;
+
case TAG_GY_UNCOMPRESSED_T_1:
ret = ST_FIFO_GYROSCOPE;
break;
+
case TAG_GY_COMPRESSED_2X:
ret = ST_FIFO_GYROSCOPE;
break;
+
case TAG_GY_COMPRESSED_3X:
ret = ST_FIFO_GYROSCOPE;
break;
+
case TAG_GAME_RV:
ret = ST_FIFO_6X_GAME_RV;
break;
+
case TAG_GEOM_RV:
ret = ST_FIFO_6X_GEOM_RV;
break;
+
case TAG_NORM_RV:
ret = ST_FIFO_9X_RV;
break;
+
case TAG_GYRO_BIAS:
ret = ST_FIFO_GYRO_BIAS;
break;
+
case TAG_GRAVITIY:
ret = ST_FIFO_GRAVITY;
break;
+
case TAG_MAG_CAL:
ret = ST_FIFO_MAGNETOMETER_CALIB;
break;
+
case TAG_EXT_SENS_NACK:
ret = ST_FIFO_EXT_SENSOR_NACK;
break;
+
default:
ret = ST_FIFO_NONE;
break;
-
}
+
return ret;
}
@@ -748,59 +758,77 @@ static st_fifo_sensor_type get_sensor_type(uint8_t tag)
static st_fifo_compression_type get_compression_type(uint8_t tag)
{
st_fifo_compression_type ret;
+
switch (tag) {
case TAG_GY:
ret = ST_FIFO_COMPRESSION_NC;
break;
+
case TAG_XL:
ret = ST_FIFO_COMPRESSION_NC;
break;
+
case TAG_TEMP:
ret = ST_FIFO_COMPRESSION_NC;
break;
+
case TAG_EXT_SENS_0:
ret = ST_FIFO_COMPRESSION_NC;
break;
+
case TAG_EXT_SENS_1:
ret = ST_FIFO_COMPRESSION_NC;
break;
+
case TAG_EXT_SENS_2:
ret = ST_FIFO_COMPRESSION_NC;
break;
+
case TAG_EXT_SENS_3:
ret = ST_FIFO_COMPRESSION_NC;
break;
+
case TAG_STEP_COUNTER:
ret = ST_FIFO_COMPRESSION_NC;
break;
+
case TAG_XL_UNCOMPRESSED_T_2:
ret = ST_FIFO_COMPRESSION_NC_T_2;
break;
+
case TAG_XL_UNCOMPRESSED_T_1:
ret = ST_FIFO_COMPRESSION_NC_T_1;
break;
+
case TAG_XL_COMPRESSED_2X:
ret = ST_FIFO_COMPRESSION_2X;
break;
+
case TAG_XL_COMPRESSED_3X:
ret = ST_FIFO_COMPRESSION_3X;
break;
+
case TAG_GY_UNCOMPRESSED_T_2:
ret = ST_FIFO_COMPRESSION_NC_T_2;
break;
+
case TAG_GY_UNCOMPRESSED_T_1:
ret = ST_FIFO_COMPRESSION_NC_T_1;
break;
+
case TAG_GY_COMPRESSED_2X:
ret = ST_FIFO_COMPRESSION_2X;
break;
+
case TAG_GY_COMPRESSED_3X:
ret = ST_FIFO_COMPRESSION_3X;
break;
+
default:
ret = ST_FIFO_COMPRESSION_NC;
break;
}
+
return ret;
}
@@ -818,7 +846,7 @@ static uint8_t has_even_parity(uint8_t x)
uint8_t ret = 1;
for (i = 0U; i < 8U; i++) {
- if( ( x & (b << i) ) != 0x00U){
+ if ( ( x & (b << i) ) != 0x00U) {
count++;
}
}
@@ -840,10 +868,12 @@ static uint8_t has_even_parity(uint8_t x)
static void get_diff_2x(int16_t diff[6], uint8_t input[6])
{
uint8_t i;
- for (i = 0; i < 6U; i++){
- if (input[i] < 128U ){
+
+ for (i = 0; i < 6U; i++) {
+ if (input[i] < 128U ) {
diff[i] = (int16_t)input[i];
}
+
else {
diff[i] = ((int16_t)input[i] - 256);
}
@@ -863,16 +893,16 @@ static void get_diff_3x(int16_t diff[9], uint8_t input[6])
uint16_t dummy;
for (uint8_t i = 0; i < 3U; i++) {
-
- byte_cpy((uint8_t*)&decode_temp, &input[2U * i], 2);
+ byte_cpy((uint8_t *)&decode_temp, &input[2U * i], 2);
for (uint8_t j = 0; j < 3U; j++) {
-
dummy = decode_temp & ( (uint16_t)0x1FU << (5U * j) );
dummy = dummy >> (5U * j);
+
if (dummy >= 16U) {
dummy -= 32U;
}
+
diff[j + (3U * i)] = (int16_t)dummy;
}
}
@@ -885,14 +915,14 @@ static void get_diff_3x(int16_t diff[9], uint8_t input[6])
* @param source Source buffer.(ptr)
*
*/
-static void byte_cpy(uint8_t *destination, uint8_t *source, uint32_t len)
+static void byte_cpy(uint8_t *destination, uint8_t *source,
+ uint32_t len)
{
uint32_t i;
- for ( i = 0; i < len; i++ ){
+ for ( i = 0; i < len; i++ ) {
destination[i] = source[i];
}
-
}
/**
diff --git a/sensor/stmemsc/_resources/FIFO_decompression_utility/fifo_utility.h b/sensor/stmemsc/_resources/FIFO_decompression_utility/fifo_utility.h
index 4e79b450944132f6cdbb27dba7c67bab942088db..7fda6af29de7dd15def0967ec952ce53f298d345 100644
--- a/sensor/stmemsc/_resources/FIFO_decompression_utility/fifo_utility.h
+++ b/sensor/stmemsc/_resources/FIFO_decompression_utility/fifo_utility.h
@@ -104,16 +104,19 @@ typedef union {
*
*/
-st_fifo_status st_fifo_init(float_t bdr_xl, float_t bdr_gy, float_t bdr_vsens);
+st_fifo_status st_fifo_init(float_t bdr_xl, float_t bdr_gy,
+ float_t bdr_vsens);
st_fifo_status st_fifo_decompress(st_fifo_out_slot *fifo_out_slot,
st_fifo_raw_slot *fifo_raw_slot,
uint16_t *out_slot_size,
uint16_t stream_size);
-void st_fifo_sort(st_fifo_out_slot *fifo_out_slot, uint16_t out_slot_size);
+void st_fifo_sort(st_fifo_out_slot *fifo_out_slot,
+ uint16_t out_slot_size);
-uint16_t st_fifo_get_sensor_occurrence(st_fifo_out_slot *fifo_out_slot,
+uint16_t st_fifo_get_sensor_occurrence(st_fifo_out_slot
+ *fifo_out_slot,
uint16_t out_slot_size,
st_fifo_sensor_type sensor_type);
diff --git a/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.c b/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.c
index 150a1d8f3845b8b5eabe7b8df9bb8de4ff572af2..0ff649d26e2203f92365a855f5cc034f66ce9742 100644
--- a/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.c
+++ b/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file a3g4250d_reg.c
- * @author Sensors Software Solution Team
- * @brief A3G4250D driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file a3g4250d_reg.c
+ * @author Sensors Software Solution Team
+ * @brief A3G4250D driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "a3g4250d_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t a3g4250d_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t a3g4250d_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t a3g4250d_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t a3g4250d_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t a3g4250d_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -86,12 +92,12 @@ int32_t a3g4250d_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
float_t a3g4250d_from_fs245dps_to_mdps(int16_t lsb)
{
- return ( (float_t)lsb * 8.75f );
+ return ((float_t)lsb * 8.75f);
}
float_t a3g4250d_from_lsb_to_celsius(int16_t lsb)
{
- return ( (float_t)lsb + 25.0f );
+ return ((float_t)lsb + 25.0f);
}
/**
@@ -120,11 +126,15 @@ int32_t a3g4250d_data_rate_set(stmdev_ctx_t *ctx, a3g4250d_dr_t val)
a3g4250d_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0){
+ ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.dr = ((uint8_t)val & 0x30U) >> 4;
ctrl_reg1.pd = ((uint8_t)val & 0x0FU);
- ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
}
return ret;
@@ -143,30 +153,38 @@ int32_t a3g4250d_data_rate_get(stmdev_ctx_t *ctx, a3g4250d_dr_t *val)
a3g4250d_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
- switch ( ( ctrl_reg1.dr << 4 ) + ctrl_reg1.pd ){
+ switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pd)
+ {
case A3G4250D_ODR_OFF:
*val = A3G4250D_ODR_OFF;
break;
+
case A3G4250D_ODR_SLEEP:
*val = A3G4250D_ODR_SLEEP;
break;
+
case A3G4250D_ODR_100Hz:
*val = A3G4250D_ODR_100Hz;
break;
+
case A3G4250D_ODR_200Hz:
*val = A3G4250D_ODR_200Hz;
break;
+
case A3G4250D_ODR_400Hz:
*val = A3G4250D_ODR_400Hz;
break;
+
case A3G4250D_ODR_800Hz:
*val = A3G4250D_ODR_800Hz;
break;
+
default:
*val = A3G4250D_ODR_OFF;
- break;
+ break;
}
return ret;
@@ -180,11 +198,12 @@ int32_t a3g4250d_data_rate_get(stmdev_ctx_t *ctx, a3g4250d_dr_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t a3g4250d_status_reg_get(stmdev_ctx_t *ctx,
- a3g4250d_status_reg_t *val)
+int32_t a3g4250d_status_reg_get(stmdev_ctx_t *ctx, a3g4250d_status_reg_t *val)
{
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_STATUS_REG, (uint8_t*) val, 1);
+
+ ret = a3g4250d_read_reg(ctx, A3G4250D_STATUS_REG, (uint8_t *) val, 1);
+
return ret;
}
@@ -201,7 +220,8 @@ int32_t a3g4250d_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
a3g4250d_status_reg_t status_reg;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_STATUS_REG,(uint8_t*)&status_reg, 1);
+ ret = a3g4250d_read_reg(ctx, A3G4250D_STATUS_REG,
+ (uint8_t *)&status_reg, 1);
*val = status_reg.zyxda;
return ret;
@@ -229,7 +249,9 @@ int32_t a3g4250d_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t a3g4250d_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = a3g4250d_read_reg(ctx, A3G4250D_OUT_TEMP, buff, 1);
+
return ret;
}
@@ -265,7 +287,7 @@ int32_t a3g4250d_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
/**
* @defgroup A3G4250D_common
- * @brief This section groups common usefull functions.
+ * @brief This section groups common useful functions.
* @{
*
*/
@@ -281,7 +303,9 @@ int32_t a3g4250d_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
int32_t a3g4250d_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = a3g4250d_read_reg(ctx, A3G4250D_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -298,11 +322,16 @@ int32_t a3g4250d_self_test_set(stmdev_ctx_t *ctx, a3g4250d_st_t val)
a3g4250d_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG4,(uint8_t*)&ctrl_reg4, 1);
- if(ret == 0){
+ ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.st = (uint8_t)val;
- ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG4,(uint8_t*)&ctrl_reg4, 1);
+ ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -319,21 +348,26 @@ int32_t a3g4250d_self_test_get(stmdev_ctx_t *ctx, a3g4250d_st_t *val)
a3g4250d_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
- switch (ctrl_reg4.st){
+ switch (ctrl_reg4.st)
+ {
case A3G4250D_GY_ST_DISABLE:
*val = A3G4250D_GY_ST_DISABLE;
break;
+
case A3G4250D_GY_ST_POSITIVE:
*val = A3G4250D_GY_ST_POSITIVE;
break;
+
case A3G4250D_GY_ST_NEGATIVE:
*val = A3G4250D_GY_ST_NEGATIVE;
break;
+
default:
*val = A3G4250D_GY_ST_DISABLE;
- break;
+ break;
}
return ret;
@@ -352,11 +386,16 @@ int32_t a3g4250d_data_format_set(stmdev_ctx_t *ctx, a3g4250d_ble_t val)
a3g4250d_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG4,(uint8_t*)&ctrl_reg4, 1);
- if(ret == 0){
+ ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.ble = (uint8_t)val;
- ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG4,(uint8_t*)&ctrl_reg4, 1);
+ ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -373,18 +412,24 @@ int32_t a3g4250d_data_format_get(stmdev_ctx_t *ctx, a3g4250d_ble_t *val)
a3g4250d_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG4,(uint8_t*)&ctrl_reg4, 1);
- switch (ctrl_reg4.ble){
+ ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ switch (ctrl_reg4.ble)
+ {
case A3G4250D_AUX_LSB_AT_LOW_ADD:
*val = A3G4250D_AUX_LSB_AT_LOW_ADD;
break;
+
case A3G4250D_AUX_MSB_AT_LOW_ADD:
*val = A3G4250D_AUX_MSB_AT_LOW_ADD;
break;
+
default:
*val = A3G4250D_AUX_LSB_AT_LOW_ADD;
- break;
+ break;
}
+
return ret;
}
@@ -401,10 +446,14 @@ int32_t a3g4250d_boot_set(stmdev_ctx_t *ctx, uint8_t val)
a3g4250d_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG5,(uint8_t*)&ctrl_reg5, 1);
- if(ret == 0){
+ ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.boot = val;
- ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG5,(uint8_t*)&ctrl_reg5, 1);
+ ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
}
return ret;
@@ -423,7 +472,8 @@ int32_t a3g4250d_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
a3g4250d_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG5,(uint8_t*)&ctrl_reg5, 1);
+ ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
*val = ctrl_reg5.boot;
return ret;
@@ -455,10 +505,14 @@ int32_t a3g4250d_lp_bandwidth_set(stmdev_ctx_t *ctx, a3g4250d_bw_t val)
a3g4250d_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG1,(uint8_t*)&ctrl_reg1, 1);
- if(ret == 0){
+ ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.bw = (uint8_t)val;
- ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG1,(uint8_t*)&ctrl_reg1, 1);
+ ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
}
return ret;
@@ -477,24 +531,30 @@ int32_t a3g4250d_lp_bandwidth_get(stmdev_ctx_t *ctx, a3g4250d_bw_t *val)
a3g4250d_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG1,(uint8_t*)&ctrl_reg1, 1);
+ ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
- switch (ctrl_reg1.bw){
- case A3G4250D_CUT_OFF_LOW:
+ switch (ctrl_reg1.bw)
+ {
+ case A3G4250D_CUT_OFF_LOW:
*val = A3G4250D_CUT_OFF_LOW;
break;
+
case A3G4250D_CUT_OFF_MEDIUM:
*val = A3G4250D_CUT_OFF_MEDIUM;
break;
+
case A3G4250D_CUT_OFF_HIGH:
*val = A3G4250D_CUT_OFF_HIGH;
break;
+
case A3G4250D_CUT_OFF_VERY_HIGH:
*val = A3G4250D_CUT_OFF_VERY_HIGH;
break;
+
default:
*val = A3G4250D_CUT_OFF_LOW;
- break;
+ break;
}
return ret;
@@ -513,10 +573,14 @@ int32_t a3g4250d_hp_bandwidth_set(stmdev_ctx_t *ctx, a3g4250d_hpcf_t val)
a3g4250d_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG2,(uint8_t*)&ctrl_reg2, 1);
- if(ret == 0){
+ ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpcf = (uint8_t)val;
- ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG2,(uint8_t*)&ctrl_reg2, 1);
+ ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
}
return ret;
@@ -535,42 +599,54 @@ int32_t a3g4250d_hp_bandwidth_get(stmdev_ctx_t *ctx, a3g4250d_hpcf_t *val)
a3g4250d_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG2,(uint8_t*)&ctrl_reg2, 1);
+ ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
- switch (ctrl_reg2.hpcf){
+ switch (ctrl_reg2.hpcf)
+ {
case A3G4250D_HP_LEVEL_0:
*val = A3G4250D_HP_LEVEL_0;
break;
+
case A3G4250D_HP_LEVEL_1:
*val = A3G4250D_HP_LEVEL_1;
break;
+
case A3G4250D_HP_LEVEL_2:
*val = A3G4250D_HP_LEVEL_2;
break;
+
case A3G4250D_HP_LEVEL_3:
*val = A3G4250D_HP_LEVEL_3;
break;
+
case A3G4250D_HP_LEVEL_4:
*val = A3G4250D_HP_LEVEL_4;
break;
+
case A3G4250D_HP_LEVEL_5:
*val = A3G4250D_HP_LEVEL_5;
break;
+
case A3G4250D_HP_LEVEL_6:
*val = A3G4250D_HP_LEVEL_6;
break;
+
case A3G4250D_HP_LEVEL_7:
*val = A3G4250D_HP_LEVEL_7;
break;
+
case A3G4250D_HP_LEVEL_8:
*val = A3G4250D_HP_LEVEL_8;
break;
+
case A3G4250D_HP_LEVEL_9:
*val = A3G4250D_HP_LEVEL_9;
break;
+
default:
*val = A3G4250D_HP_LEVEL_0;
- break;
+ break;
}
return ret;
@@ -589,10 +665,14 @@ int32_t a3g4250d_hp_mode_set(stmdev_ctx_t *ctx, a3g4250d_hpm_t val)
a3g4250d_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG2,(uint8_t*)&ctrl_reg2, 1);
- if(ret == 0){
+ ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpm = (uint8_t)val;
- ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG2,(uint8_t*)&ctrl_reg2, 1);
+ ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
}
return ret;
@@ -611,24 +691,30 @@ int32_t a3g4250d_hp_mode_get(stmdev_ctx_t *ctx, a3g4250d_hpm_t *val)
a3g4250d_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG2,(uint8_t*)&ctrl_reg2, 1);
+ ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
- switch (ctrl_reg2.hpm){
+ switch (ctrl_reg2.hpm)
+ {
case A3G4250D_HP_NORMAL_MODE_WITH_RST:
*val = A3G4250D_HP_NORMAL_MODE_WITH_RST;
break;
+
case A3G4250D_HP_REFERENCE_SIGNAL:
*val = A3G4250D_HP_REFERENCE_SIGNAL;
break;
+
case A3G4250D_HP_NORMAL_MODE:
*val = A3G4250D_HP_NORMAL_MODE;
break;
+
case A3G4250D_HP_AUTO_RESET_ON_INT:
*val = A3G4250D_HP_AUTO_RESET_ON_INT;
break;
+
default:
*val = A3G4250D_HP_NORMAL_MODE_WITH_RST;
- break;
+ break;
}
return ret;
@@ -647,11 +733,15 @@ int32_t a3g4250d_filter_path_set(stmdev_ctx_t *ctx, a3g4250d_out_sel_t val)
a3g4250d_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG5,(uint8_t*)&ctrl_reg5, 1);
- if(ret == 0){
+ ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.out_sel = (uint8_t)val & 0x03U;
- ctrl_reg5.hpen = ( (uint8_t)val & 0x04U ) >> 2;
- ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG5,(uint8_t*)&ctrl_reg5, 1);
+ ctrl_reg5.hpen = ((uint8_t)val & 0x04U) >> 2;
+ ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
}
return ret;
@@ -670,24 +760,30 @@ int32_t a3g4250d_filter_path_get(stmdev_ctx_t *ctx, a3g4250d_out_sel_t *val)
a3g4250d_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG5,(uint8_t*)&ctrl_reg5, 1);
+ ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
- switch ( ( ctrl_reg5.hpen << 2 ) + ctrl_reg5.out_sel ){
+ switch ((ctrl_reg5.hpen << 2) + ctrl_reg5.out_sel)
+ {
case A3G4250D_ONLY_LPF1_ON_OUT:
*val = A3G4250D_ONLY_LPF1_ON_OUT;
break;
+
case A3G4250D_LPF1_HP_ON_OUT:
*val = A3G4250D_LPF1_HP_ON_OUT;
break;
+
case A3G4250D_LPF1_LPF2_ON_OUT:
*val = A3G4250D_LPF1_LPF2_ON_OUT;
break;
+
case A3G4250D_LPF1_HP_LPF2_ON_OUT:
*val = A3G4250D_LPF1_HP_LPF2_ON_OUT;
break;
+
default:
*val = A3G4250D_ONLY_LPF1_ON_OUT;
- break;
+ break;
}
return ret;
@@ -707,11 +803,15 @@ int32_t a3g4250d_filter_path_internal_set(stmdev_ctx_t *ctx,
a3g4250d_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG5,(uint8_t*)&ctrl_reg5, 1);
- if(ret == 0){
+ ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.int1_sel = (uint8_t)val & 0x03U;
- ctrl_reg5.hpen = ( (uint8_t)val & 0x04U ) >> 2;
- ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG5,(uint8_t*)&ctrl_reg5, 1);
+ ctrl_reg5.hpen = ((uint8_t)val & 0x04U) >> 2;
+ ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
}
return ret;
@@ -731,24 +831,30 @@ int32_t a3g4250d_filter_path_internal_get(stmdev_ctx_t *ctx,
a3g4250d_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG5,(uint8_t*)&ctrl_reg5, 1);
+ ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
- switch ( ( ctrl_reg5.hpen << 2 ) + ctrl_reg5.int1_sel ){
+ switch ((ctrl_reg5.hpen << 2) + ctrl_reg5.int1_sel)
+ {
case A3G4250D_ONLY_LPF1_ON_INT:
*val = A3G4250D_ONLY_LPF1_ON_INT;
break;
+
case A3G4250D_LPF1_HP_ON_INT:
*val = A3G4250D_LPF1_HP_ON_INT;
break;
+
case A3G4250D_LPF1_LPF2_ON_INT:
*val = A3G4250D_LPF1_LPF2_ON_INT;
break;
+
case A3G4250D_LPF1_HP_LPF2_ON_INT:
*val = A3G4250D_LPF1_HP_LPF2_ON_INT;
break;
+
default:
*val = A3G4250D_ONLY_LPF1_ON_INT;
- break;
+ break;
}
return ret;
@@ -767,10 +873,14 @@ int32_t a3g4250d_hp_reference_value_set(stmdev_ctx_t *ctx, uint8_t val)
a3g4250d_reference_t reference;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_REFERENCE,(uint8_t*)&reference, 1);
- if(ret == 0){
+ ret = a3g4250d_read_reg(ctx, A3G4250D_REFERENCE,
+ (uint8_t *)&reference, 1);
+
+ if (ret == 0)
+ {
reference.ref = val;
- ret = a3g4250d_write_reg(ctx, A3G4250D_REFERENCE,(uint8_t*)&reference, 1);
+ ret = a3g4250d_write_reg(ctx, A3G4250D_REFERENCE,
+ (uint8_t *)&reference, 1);
}
return ret;
@@ -784,12 +894,14 @@ int32_t a3g4250d_hp_reference_value_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t a3g4250d_hp_reference_value_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t a3g4250d_hp_reference_value_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
a3g4250d_reference_t reference;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_REFERENCE,(uint8_t*)&reference, 1);
+ ret = a3g4250d_read_reg(ctx, A3G4250D_REFERENCE,
+ (uint8_t *)&reference, 1);
*val = reference.ref;
return ret;
@@ -821,10 +933,14 @@ int32_t a3g4250d_spi_mode_set(stmdev_ctx_t *ctx, a3g4250d_sim_t val)
a3g4250d_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG4,(uint8_t*)&ctrl_reg4, 1);
- if(ret == 0){
+ ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.sim = (uint8_t)val;
- ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG4,(uint8_t*)&ctrl_reg4, 1);
+ ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
}
return ret;
@@ -843,18 +959,22 @@ int32_t a3g4250d_spi_mode_get(stmdev_ctx_t *ctx, a3g4250d_sim_t *val)
a3g4250d_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG4,(uint8_t*)&ctrl_reg4, 1);
+ ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
- switch (ctrl_reg4.sim){
+ switch (ctrl_reg4.sim)
+ {
case A3G4250D_SPI_4_WIRE:
*val = A3G4250D_SPI_4_WIRE;
break;
+
case A3G4250D_SPI_3_WIRE:
*val = A3G4250D_SPI_3_WIRE;
break;
+
default:
*val = A3G4250D_SPI_4_WIRE;
- break;
+ break;
}
return ret;
@@ -867,7 +987,8 @@ int32_t a3g4250d_spi_mode_get(stmdev_ctx_t *ctx, a3g4250d_sim_t *val)
/**
* @defgroup A3G4250D_interrupt_pins
- * @brief This section groups all the functions that manage interrup pins
+ * @brief This section groups all the functions that
+ * manage interrupt pins
* @{
*
*/
@@ -887,11 +1008,15 @@ int32_t a3g4250d_pin_int1_route_set(stmdev_ctx_t *ctx,
a3g4250d_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG3,(uint8_t*)&ctrl_reg3, 1);
- if(ret == 0){
+ ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.i1_int1 = val.i1_int1;
ctrl_reg3.i1_boot = val.i1_boot;
- ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG3,(uint8_t*)&ctrl_reg3, 1);
+ ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
}
return ret;
@@ -912,7 +1037,8 @@ int32_t a3g4250d_pin_int1_route_get(stmdev_ctx_t *ctx,
a3g4250d_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG3,(uint8_t*)&ctrl_reg3, 1);
+ ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
val->i1_int1 = ctrl_reg3.i1_int1;
val->i1_boot = ctrl_reg3.i1_boot;
@@ -932,13 +1058,17 @@ int32_t a3g4250d_pin_int2_route_set(stmdev_ctx_t *ctx,
a3g4250d_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG3,(uint8_t*)&ctrl_reg3, 1);
- if(ret == 0){
+ ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.i2_empty = val.i2_empty;
ctrl_reg3.i2_orun = val.i2_orun;
ctrl_reg3.i2_wtm = val.i2_wtm;
ctrl_reg3.i2_drdy = val.i2_drdy;
- ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG3,(uint8_t*)&ctrl_reg3, 1);
+ ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
}
return ret;
@@ -958,7 +1088,8 @@ int32_t a3g4250d_pin_int2_route_get(stmdev_ctx_t *ctx,
a3g4250d_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG3,(uint8_t*)&ctrl_reg3, 1);
+ ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
val->i2_empty = ctrl_reg3.i2_empty;
val->i2_orun = ctrl_reg3.i2_orun;
val->i2_wtm = ctrl_reg3.i2_wtm;
@@ -980,10 +1111,14 @@ int32_t a3g4250d_pin_mode_set(stmdev_ctx_t *ctx, a3g4250d_pp_od_t val)
a3g4250d_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG3,(uint8_t*)&ctrl_reg3, 1);
- if(ret == 0){
+ ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.pp_od = (uint8_t)val;
- ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG3,(uint8_t*)&ctrl_reg3, 1);
+ ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
}
return ret;
@@ -997,23 +1132,28 @@ int32_t a3g4250d_pin_mode_set(stmdev_ctx_t *ctx, a3g4250d_pp_od_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t a3g4250d_pin_mode_get(stmdev_ctx_t *ctx, a3g4250d_pp_od_t *val)
+int32_t a3g4250d_pin_mode_get(stmdev_ctx_t *ctx,
+ a3g4250d_pp_od_t *val)
{
a3g4250d_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG3,(uint8_t*)&ctrl_reg3, 1);
+ ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch (ctrl_reg3.pp_od ){
+ switch (ctrl_reg3.pp_od)
+ {
case A3G4250D_PUSH_PULL:
*val = A3G4250D_PUSH_PULL;
break;
+
case A3G4250D_OPEN_DRAIN:
*val = A3G4250D_OPEN_DRAIN;
break;
+
default:
*val = A3G4250D_PUSH_PULL;
- break;
+ break;
}
return ret;
@@ -1033,10 +1173,14 @@ int32_t a3g4250d_pin_polarity_set(stmdev_ctx_t *ctx,
a3g4250d_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG3,(uint8_t*)&ctrl_reg3, 1);
- if(ret == 0){
+ ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.h_lactive = (uint8_t)val;
- ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG3,(uint8_t*)&ctrl_reg3, 1);
+ ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
}
return ret;
@@ -1056,18 +1200,22 @@ int32_t a3g4250d_pin_polarity_get(stmdev_ctx_t *ctx,
a3g4250d_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG3,(uint8_t*)&ctrl_reg3, 1);
+ ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch (ctrl_reg3.h_lactive){
+ switch (ctrl_reg3.h_lactive)
+ {
case A3G4250D_ACTIVE_HIGH:
*val = A3G4250D_ACTIVE_HIGH;
break;
+
case A3G4250D_ACTIVE_LOW:
*val = A3G4250D_ACTIVE_LOW;
break;
+
default:
*val = A3G4250D_ACTIVE_HIGH;
- break;
+ break;
}
return ret;
@@ -1081,16 +1229,17 @@ int32_t a3g4250d_pin_polarity_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t a3g4250d_int_notification_set(stmdev_ctx_t *ctx,
- a3g4250d_lir_t val)
+int32_t a3g4250d_int_notification_set(stmdev_ctx_t *ctx, a3g4250d_lir_t val)
{
a3g4250d_int1_cfg_t int1_cfg;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_CFG,(uint8_t*)&int1_cfg, 1);
- if(ret == 0){
+ ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_CFG, (uint8_t *)&int1_cfg, 1);
+
+ if (ret == 0)
+ {
int1_cfg.lir = (uint8_t)val;
- ret = a3g4250d_write_reg(ctx, A3G4250D_INT1_CFG,(uint8_t*)&int1_cfg, 1);
+ ret = a3g4250d_write_reg(ctx, A3G4250D_INT1_CFG, (uint8_t *)&int1_cfg, 1);
}
return ret;
@@ -1104,24 +1253,26 @@ int32_t a3g4250d_int_notification_set(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t a3g4250d_int_notification_get(stmdev_ctx_t *ctx,
- a3g4250d_lir_t *val)
+int32_t a3g4250d_int_notification_get(stmdev_ctx_t *ctx, a3g4250d_lir_t *val)
{
a3g4250d_int1_cfg_t int1_cfg;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_CFG,(uint8_t*)&int1_cfg, 1);
+ ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_CFG, (uint8_t *)&int1_cfg, 1);
- switch (int1_cfg.lir){
+ switch (int1_cfg.lir)
+ {
case A3G4250D_INT_PULSED:
*val = A3G4250D_INT_PULSED;
break;
+
case A3G4250D_INT_LATCHED:
*val = A3G4250D_INT_LATCHED;
break;
+
default:
*val = A3G4250D_INT_PULSED;
- break;
+ break;
}
return ret;
@@ -1152,7 +1303,9 @@ int32_t a3g4250d_int_on_threshold_conf_set(stmdev_ctx_t *ctx,
a3g4250d_int1_cfg_t *val)
{
int32_t ret;
- ret = a3g4250d_write_reg(ctx, A3G4250D_INT1_CFG, (uint8_t*) val, 1);
+
+ ret = a3g4250d_write_reg(ctx, A3G4250D_INT1_CFG, (uint8_t *) val, 1);
+
return ret;
}
@@ -1168,7 +1321,9 @@ int32_t a3g4250d_int_on_threshold_conf_get(stmdev_ctx_t *ctx,
a3g4250d_int1_cfg_t *val)
{
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_CFG, (uint8_t*) val, 1);
+
+ ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_CFG, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1185,10 +1340,12 @@ int32_t a3g4250d_int_on_threshold_mode_set(stmdev_ctx_t *ctx,
a3g4250d_int1_cfg_t int1_cfg;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_CFG,(uint8_t*)&int1_cfg, 1);
- if(ret == 0){
+ ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_CFG, (uint8_t *)&int1_cfg, 1);
+
+ if (ret == 0)
+ {
int1_cfg.and_or = (uint8_t)val;
- ret = a3g4250d_write_reg(ctx, A3G4250D_INT1_CFG,(uint8_t*)&int1_cfg, 1);
+ ret = a3g4250d_write_reg(ctx, A3G4250D_INT1_CFG, (uint8_t *)&int1_cfg, 1);
}
return ret;
@@ -1208,18 +1365,23 @@ int32_t a3g4250d_int_on_threshold_mode_get(stmdev_ctx_t *ctx,
a3g4250d_int1_cfg_t int1_cfg;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_CFG,(uint8_t*)&int1_cfg, 1);
- switch (int1_cfg.and_or){
+ ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_CFG, (uint8_t *)&int1_cfg, 1);
+
+ switch (int1_cfg.and_or)
+ {
case A3G4250D_INT1_ON_TH_OR:
*val = A3G4250D_INT1_ON_TH_OR;
break;
+
case A3G4250D_INT1_ON_TH_AND:
*val = A3G4250D_INT1_ON_TH_AND;
break;
+
default:
*val = A3G4250D_INT1_ON_TH_OR;
- break;
+ break;
}
+
return ret;
}
@@ -1235,7 +1397,9 @@ int32_t a3g4250d_int_on_threshold_src_get(stmdev_ctx_t *ctx,
a3g4250d_int1_src_t *val)
{
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_SRC, (uint8_t*) val, 1);
+
+ ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_SRC, (uint8_t *) val, 1);
+
return ret;
}
@@ -1254,21 +1418,28 @@ int32_t a3g4250d_int_x_treshold_set(stmdev_ctx_t *ctx, uint16_t val)
int32_t ret;
ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_TSH_XH,
- (uint8_t*)&int1_tsh_xh, 1);
- if(ret == 0){
+ (uint8_t *)&int1_tsh_xh, 1);
+
+ if (ret == 0)
+ {
int1_tsh_xh.thsx = (uint8_t)(val / 256U) & 0x7FU;
ret = a3g4250d_write_reg(ctx, A3G4250D_INT1_TSH_XH,
- (uint8_t*)&int1_tsh_xh, 1);
+ (uint8_t *)&int1_tsh_xh, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_TSH_XL,
- (uint8_t*)&int1_tsh_xl, 1);
+ (uint8_t *)&int1_tsh_xl, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
int1_tsh_xl.thsx = (uint8_t)(val - (int1_tsh_xh.thsx * 256U));
ret = a3g4250d_write_reg(ctx, A3G4250D_INT1_TSH_XL,
- (uint8_t*)&int1_tsh_xl, 1);
+ (uint8_t *)&int1_tsh_xl, 1);
}
+
return ret;
}
@@ -1287,16 +1458,17 @@ int32_t a3g4250d_int_x_treshold_get(stmdev_ctx_t *ctx, uint16_t *val)
int32_t ret;
ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_TSH_XH,
- (uint8_t*)&int1_tsh_xh, 1);
- if(ret == 0){
- ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_TSH_XL,
- (uint8_t*)&int1_tsh_xl, 1);
+ (uint8_t *)&int1_tsh_xh, 1);
+ if (ret == 0)
+ {
+ ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_TSH_XL,
+ (uint8_t *)&int1_tsh_xl, 1);
*val = int1_tsh_xh.thsx;
*val = *val * 256U;
*val += int1_tsh_xl.thsx;
-
}
+
return ret;
}
@@ -1315,21 +1487,28 @@ int32_t a3g4250d_int_y_treshold_set(stmdev_ctx_t *ctx, uint16_t val)
int32_t ret;
ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_TSH_YH,
- (uint8_t*)&int1_tsh_yh, 1);
+ (uint8_t *)&int1_tsh_yh, 1);
int1_tsh_yh.thsy = (uint8_t)(val / 256U) & 0x7FU;
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = a3g4250d_write_reg(ctx, A3G4250D_INT1_TSH_YH,
- (uint8_t*)&int1_tsh_yh, 1);
+ (uint8_t *)&int1_tsh_yh, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_TSH_YL,
- (uint8_t*)&int1_tsh_yl, 1);
+ (uint8_t *)&int1_tsh_yl, 1);
int1_tsh_yl.thsy = (uint8_t)(val - (int1_tsh_yh.thsy * 256U));
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = a3g4250d_write_reg(ctx, A3G4250D_INT1_TSH_YL,
- (uint8_t*)&int1_tsh_yl, 1);
+ (uint8_t *)&int1_tsh_yl, 1);
}
+
return ret;
}
@@ -1348,15 +1527,17 @@ int32_t a3g4250d_int_y_treshold_get(stmdev_ctx_t *ctx, uint16_t *val)
int32_t ret;
ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_TSH_YH,
- (uint8_t*)&int1_tsh_yh, 1);
- if(ret == 0){
- ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_TSH_YL,
- (uint8_t*)&int1_tsh_yl, 1);
+ (uint8_t *)&int1_tsh_yh, 1);
+ if (ret == 0)
+ {
+ ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_TSH_YL,
+ (uint8_t *)&int1_tsh_yl, 1);
*val = int1_tsh_yh.thsy;
*val = *val * 256U;
*val += int1_tsh_yl.thsy;
}
+
return ret;
}
@@ -1375,21 +1556,28 @@ int32_t a3g4250d_int_z_treshold_set(stmdev_ctx_t *ctx, uint16_t val)
int32_t ret;
ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_TSH_ZH,
- (uint8_t*)&int1_tsh_zh, 1);
+ (uint8_t *)&int1_tsh_zh, 1);
int1_tsh_zh.thsz = (uint8_t)(val / 256U) & 0x7FU;;
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = a3g4250d_write_reg(ctx, A3G4250D_INT1_TSH_ZH,
- (uint8_t*)&int1_tsh_zh, 1);
+ (uint8_t *)&int1_tsh_zh, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_TSH_ZL,
- (uint8_t*)&int1_tsh_zl, 1);
+ (uint8_t *)&int1_tsh_zl, 1);
int1_tsh_zl.thsz = (uint8_t)(val - (int1_tsh_zh.thsz * 256U));
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = a3g4250d_write_reg(ctx, A3G4250D_INT1_TSH_ZL,
- (uint8_t*)&int1_tsh_zl, 1);
+ (uint8_t *)&int1_tsh_zl, 1);
}
+
return ret;
}
@@ -1408,15 +1596,17 @@ int32_t a3g4250d_int_z_treshold_get(stmdev_ctx_t *ctx, uint16_t *val)
int32_t ret;
ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_TSH_ZH,
- (uint8_t*)&int1_tsh_zh, 1);
- if(ret == 0){
- ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_TSH_ZL,
- (uint8_t*)&int1_tsh_zl, 1);
+ (uint8_t *)&int1_tsh_zh, 1);
+ if (ret == 0)
+ {
+ ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_TSH_ZL,
+ (uint8_t *)&int1_tsh_zl, 1);
*val = int1_tsh_zh.thsz;
*val = *val * 256U;
*val += int1_tsh_zl.thsz;
}
+
return ret;
}
@@ -1428,24 +1618,33 @@ int32_t a3g4250d_int_z_treshold_get(stmdev_ctx_t *ctx, uint16_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t a3g4250d_int_on_threshold_dur_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t a3g4250d_int_on_threshold_dur_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
a3g4250d_int1_duration_t int1_duration;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_DURATION,
- (uint8_t*)&int1_duration, 1);
- if(ret == 0){
+ ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_DURATION,
+ (uint8_t *)&int1_duration, 1);
+
+ if (ret == 0)
+ {
int1_duration.d = val;
- if (val != PROPERTY_DISABLE){
+
+ if (val != PROPERTY_DISABLE)
+ {
int1_duration.wait = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
int1_duration.wait = PROPERTY_DISABLE;
}
+
ret = a3g4250d_write_reg(ctx, A3G4250D_INT1_DURATION,
- (uint8_t*)&int1_duration, 1);
+ (uint8_t *)&int1_duration, 1);
}
+
return ret;
}
@@ -1457,13 +1656,14 @@ int32_t a3g4250d_int_on_threshold_dur_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t a3g4250d_int_on_threshold_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t a3g4250d_int_on_threshold_dur_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
a3g4250d_int1_duration_t int1_duration;
int32_t ret;
ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_DURATION,
- (uint8_t*)&int1_duration, 1);
+ (uint8_t *)&int1_duration, 1);
*val = int1_duration.d;
return ret;
@@ -1494,10 +1694,14 @@ int32_t a3g4250d_fifo_enable_set(stmdev_ctx_t *ctx, uint8_t val)
a3g4250d_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG5,(uint8_t*)&ctrl_reg5, 1);
- if(ret == 0){
+ ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.fifo_en = val;
- ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG5,(uint8_t*)&ctrl_reg5, 1);
+ ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
}
return ret;
@@ -1516,7 +1720,8 @@ int32_t a3g4250d_fifo_enable_get(stmdev_ctx_t *ctx, uint8_t *val)
a3g4250d_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG5,(uint8_t*)&ctrl_reg5, 1);
+ ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
*val = ctrl_reg5.fifo_en;
return ret;
@@ -1536,11 +1741,13 @@ int32_t a3g4250d_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = a3g4250d_read_reg(ctx, A3G4250D_FIFO_CTRL_REG,
- (uint8_t*)&fifo_ctrl_reg, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl_reg, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl_reg.wtm = val;
ret = a3g4250d_write_reg(ctx, A3G4250D_FIFO_CTRL_REG,
- (uint8_t*)&fifo_ctrl_reg, 1);
+ (uint8_t *)&fifo_ctrl_reg, 1);
}
return ret;
@@ -1560,7 +1767,7 @@ int32_t a3g4250d_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = a3g4250d_read_reg(ctx, A3G4250D_FIFO_CTRL_REG,
- (uint8_t*)&fifo_ctrl_reg, 1);
+ (uint8_t *)&fifo_ctrl_reg, 1);
*val = fifo_ctrl_reg.wtm;
return ret;
@@ -1574,17 +1781,20 @@ int32_t a3g4250d_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t a3g4250d_fifo_mode_set(stmdev_ctx_t *ctx, a3g4250d_fifo_mode_t val)
+int32_t a3g4250d_fifo_mode_set(stmdev_ctx_t *ctx,
+ a3g4250d_fifo_mode_t val)
{
a3g4250d_fifo_ctrl_reg_t fifo_ctrl_reg;
int32_t ret;
ret = a3g4250d_read_reg(ctx, A3G4250D_FIFO_CTRL_REG,
- (uint8_t*)&fifo_ctrl_reg, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl_reg, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl_reg.fm = (uint8_t)val;
ret = a3g4250d_write_reg(ctx, A3G4250D_FIFO_CTRL_REG,
- (uint8_t*)&fifo_ctrl_reg, 1);
+ (uint8_t *)&fifo_ctrl_reg, 1);
}
return ret;
@@ -1598,27 +1808,32 @@ int32_t a3g4250d_fifo_mode_set(stmdev_ctx_t *ctx, a3g4250d_fifo_mode_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t a3g4250d_fifo_mode_get(stmdev_ctx_t *ctx, a3g4250d_fifo_mode_t *val)
+int32_t a3g4250d_fifo_mode_get(stmdev_ctx_t *ctx,
+ a3g4250d_fifo_mode_t *val)
{
a3g4250d_fifo_ctrl_reg_t fifo_ctrl_reg;
int32_t ret;
ret = a3g4250d_read_reg(ctx, A3G4250D_FIFO_CTRL_REG,
- (uint8_t*)&fifo_ctrl_reg, 1);
+ (uint8_t *)&fifo_ctrl_reg, 1);
- switch (fifo_ctrl_reg.fm){
+ switch (fifo_ctrl_reg.fm)
+ {
case A3G4250D_FIFO_BYPASS_MODE:
*val = A3G4250D_FIFO_BYPASS_MODE;
break;
+
case A3G4250D_FIFO_MODE:
*val = A3G4250D_FIFO_MODE;
break;
+
case A3G4250D_FIFO_STREAM_MODE:
*val = A3G4250D_FIFO_STREAM_MODE;
break;
+
default:
*val = A3G4250D_FIFO_BYPASS_MODE;
- break;
+ break;
}
return ret;
@@ -1638,7 +1853,7 @@ int32_t a3g4250d_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = a3g4250d_read_reg(ctx, A3G4250D_FIFO_SRC_REG,
- (uint8_t*)&fifo_src_reg, 1);
+ (uint8_t *)&fifo_src_reg, 1);
*val = fifo_src_reg.fss;
return ret;
@@ -1658,7 +1873,7 @@ int32_t a3g4250d_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = a3g4250d_read_reg(ctx, A3G4250D_FIFO_SRC_REG,
- (uint8_t*)&fifo_src_reg, 1);
+ (uint8_t *)&fifo_src_reg, 1);
*val = fifo_src_reg.empty;
return ret;
@@ -1678,7 +1893,7 @@ int32_t a3g4250d_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = a3g4250d_read_reg(ctx, A3G4250D_FIFO_SRC_REG,
- (uint8_t*)&fifo_src_reg, 1);
+ (uint8_t *)&fifo_src_reg, 1);
*val = fifo_src_reg.ovrn;
return ret;
@@ -1701,7 +1916,7 @@ int32_t a3g4250d_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = a3g4250d_read_reg(ctx, A3G4250D_FIFO_SRC_REG,
- (uint8_t*)&fifo_src_reg, 1);
+ (uint8_t *)&fifo_src_reg, 1);
*val = fifo_src_reg.wtm;
return ret;
diff --git a/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.h b/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.h
index d1f067ad889d4501d470d881372a58c22dc86fbf..d4e0c535525a061da04e8fa7003055dc45b6fa50 100644
--- a/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.h
+++ b/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file a3g4250d_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * a3g4250d_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file a3g4250d_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * a3g4250d_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef A3G4250D_REGS_H
#define A3G4250D_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup A3G4250D
@@ -71,7 +72,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -104,10 +106,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -128,7 +131,7 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
+ * You can create a sensor configuration by your own or using
* Unico / Unicleo tools available on STMicroelectronics
* web site.
*
@@ -136,7 +139,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -173,7 +177,8 @@ typedef struct {
#define A3G4250D_WHO_AM_I 0x0FU
#define A3G4250D_CTRL_REG1 0x20U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t pd : 4; /* xen yen zen pd */
uint8_t bw : 2;
@@ -186,7 +191,8 @@ typedef struct {
} a3g4250d_ctrl_reg1_t;
#define A3G4250D_CTRL_REG2 0x21U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t hpcf : 4;
uint8_t hpm : 2;
@@ -199,7 +205,8 @@ typedef struct {
} a3g4250d_ctrl_reg2_t;
#define A3G4250D_CTRL_REG3 0x22U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t i2_empty : 1;
uint8_t i2_orun : 1;
@@ -222,7 +229,8 @@ typedef struct {
} a3g4250d_ctrl_reg3_t;
#define A3G4250D_CTRL_REG4 0x23U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t st : 2;
@@ -239,7 +247,8 @@ typedef struct {
} a3g4250d_ctrl_reg4_t;
#define A3G4250D_CTRL_REG5 0x24U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t out_sel : 2;
uint8_t int1_sel : 2;
@@ -258,13 +267,15 @@ typedef struct {
} a3g4250d_ctrl_reg5_t;
#define A3G4250D_REFERENCE 0x25U
-typedef struct {
+typedef struct
+{
uint8_t ref : 8;
} a3g4250d_reference_t;
#define A3G4250D_OUT_TEMP 0x26U
#define A3G4250D_STATUS_REG 0x27U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xda : 1;
uint8_t yda : 1;
@@ -293,7 +304,8 @@ typedef struct {
#define A3G4250D_OUT_Z_L 0x2CU
#define A3G4250D_OUT_Z_H 0x2DU
#define A3G4250D_FIFO_CTRL_REG 0x2EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wtm : 5;
uint8_t fm : 3;
@@ -304,7 +316,8 @@ typedef struct {
} a3g4250d_fifo_ctrl_reg_t;
#define A3G4250D_FIFO_SRC_REG 0x2FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fss : 5;
uint8_t empty : 1;
@@ -319,7 +332,8 @@ typedef struct {
} a3g4250d_fifo_src_reg_t;
#define A3G4250D_INT1_CFG 0x30U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlie : 1;
uint8_t xhie : 1;
@@ -342,7 +356,8 @@ typedef struct {
} a3g4250d_int1_cfg_t;
#define A3G4250D_INT1_SRC 0x31U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
@@ -365,7 +380,8 @@ typedef struct {
} a3g4250d_int1_src_t;
#define A3G4250D_INT1_TSH_XH 0x32U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t thsx : 7;
uint8_t not_used_01 : 1;
@@ -376,12 +392,14 @@ typedef struct {
} a3g4250d_int1_tsh_xh_t;
#define A3G4250D_INT1_TSH_XL 0x33U
-typedef struct {
+typedef struct
+{
uint8_t thsx : 8;
} a3g4250d_int1_tsh_xl_t;
#define A3G4250D_INT1_TSH_YH 0x34U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t thsy : 7;
uint8_t not_used_01 : 1;
@@ -392,12 +410,14 @@ typedef struct {
} a3g4250d_int1_tsh_yh_t;
#define A3G4250D_INT1_TSH_YL 0x35U
-typedef struct {
+typedef struct
+{
uint8_t thsy : 8;
} a3g4250d_int1_tsh_yl_t;
#define A3G4250D_INT1_TSH_ZH 0x36U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t thsz : 7;
uint8_t not_used_01 : 1;
@@ -408,12 +428,14 @@ typedef struct {
} a3g4250d_int1_tsh_zh_t;
#define A3G4250D_INT1_TSH_ZL 0x37U
-typedef struct {
+typedef struct
+{
uint8_t thsz : 8;
} a3g4250d_int1_tsh_zl_t;
#define A3G4250D_INT1_DURATION 0x38U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d : 7;
uint8_t wait : 1;
@@ -424,10 +446,10 @@ typedef struct {
} a3g4250d_int1_duration_t;
/**
- * @defgroup LSM9DS1_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @defgroup A3G4250D_Register_Union
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -436,7 +458,8 @@ typedef struct {
*
*/
-typedef union{
+typedef union
+{
a3g4250d_ctrl_reg1_t ctrl_reg1;
a3g4250d_ctrl_reg2_t ctrl_reg2;
a3g4250d_ctrl_reg3_t ctrl_reg3;
@@ -464,9 +487,11 @@ typedef union{
*
*/
-int32_t a3g4250d_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t a3g4250d_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t a3g4250d_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t a3g4250d_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
float_t a3g4250d_from_fs245dps_to_mdps(int16_t lsb);
@@ -481,7 +506,8 @@ int32_t a3g4250d_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t a3g4250d_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t a3g4250d_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
A3G4250D_ODR_OFF = 0x00,
A3G4250D_ODR_SLEEP = 0x08,
A3G4250D_ODR_100Hz = 0x0F,
@@ -503,7 +529,8 @@ int32_t a3g4250d_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val);
int32_t a3g4250d_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
-typedef enum {
+typedef enum
+{
A3G4250D_GY_ST_DISABLE = 0,
A3G4250D_GY_ST_POSITIVE = 1,
A3G4250D_GY_ST_NEGATIVE = 3,
@@ -511,7 +538,8 @@ typedef enum {
int32_t a3g4250d_self_test_set(stmdev_ctx_t *ctx, a3g4250d_st_t val);
int32_t a3g4250d_self_test_get(stmdev_ctx_t *ctx, a3g4250d_st_t *val);
-typedef enum {
+typedef enum
+{
A3G4250D_AUX_LSB_AT_LOW_ADD = 0,
A3G4250D_AUX_MSB_AT_LOW_ADD = 1,
} a3g4250d_ble_t;
@@ -521,7 +549,8 @@ int32_t a3g4250d_data_format_get(stmdev_ctx_t *ctx, a3g4250d_ble_t *val);
int32_t a3g4250d_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t a3g4250d_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
A3G4250D_CUT_OFF_LOW = 0,
A3G4250D_CUT_OFF_MEDIUM = 1,
A3G4250D_CUT_OFF_HIGH = 2,
@@ -530,7 +559,8 @@ typedef enum {
int32_t a3g4250d_lp_bandwidth_set(stmdev_ctx_t *ctx, a3g4250d_bw_t val);
int32_t a3g4250d_lp_bandwidth_get(stmdev_ctx_t *ctx, a3g4250d_bw_t *val);
-typedef enum {
+typedef enum
+{
A3G4250D_HP_LEVEL_0 = 0,
A3G4250D_HP_LEVEL_1 = 1,
A3G4250D_HP_LEVEL_2 = 2,
@@ -542,12 +572,11 @@ typedef enum {
A3G4250D_HP_LEVEL_8 = 8,
A3G4250D_HP_LEVEL_9 = 9,
} a3g4250d_hpcf_t;
-int32_t a3g4250d_hp_bandwidth_set(stmdev_ctx_t *ctx,
- a3g4250d_hpcf_t val);
-int32_t a3g4250d_hp_bandwidth_get(stmdev_ctx_t *ctx,
- a3g4250d_hpcf_t *val);
+int32_t a3g4250d_hp_bandwidth_set(stmdev_ctx_t *ctx, a3g4250d_hpcf_t val);
+int32_t a3g4250d_hp_bandwidth_get(stmdev_ctx_t *ctx, a3g4250d_hpcf_t *val);
-typedef enum {
+typedef enum
+{
A3G4250D_HP_NORMAL_MODE_WITH_RST = 0,
A3G4250D_HP_REFERENCE_SIGNAL = 1,
A3G4250D_HP_NORMAL_MODE = 2,
@@ -556,18 +585,18 @@ typedef enum {
int32_t a3g4250d_hp_mode_set(stmdev_ctx_t *ctx, a3g4250d_hpm_t val);
int32_t a3g4250d_hp_mode_get(stmdev_ctx_t *ctx, a3g4250d_hpm_t *val);
-typedef enum {
+typedef enum
+{
A3G4250D_ONLY_LPF1_ON_OUT = 0,
A3G4250D_LPF1_HP_ON_OUT = 1,
A3G4250D_LPF1_LPF2_ON_OUT = 2,
A3G4250D_LPF1_HP_LPF2_ON_OUT = 6,
} a3g4250d_out_sel_t;
-int32_t a3g4250d_filter_path_set(stmdev_ctx_t *ctx,
- a3g4250d_out_sel_t val);
-int32_t a3g4250d_filter_path_get(stmdev_ctx_t *ctx,
- a3g4250d_out_sel_t *val);
+int32_t a3g4250d_filter_path_set(stmdev_ctx_t *ctx, a3g4250d_out_sel_t val);
+int32_t a3g4250d_filter_path_get(stmdev_ctx_t *ctx, a3g4250d_out_sel_t *val);
-typedef enum {
+typedef enum
+{
A3G4250D_ONLY_LPF1_ON_INT = 0,
A3G4250D_LPF1_HP_ON_INT = 1,
A3G4250D_LPF1_LPF2_ON_INT = 2,
@@ -581,14 +610,16 @@ int32_t a3g4250d_filter_path_internal_get(stmdev_ctx_t *ctx,
int32_t a3g4250d_hp_reference_value_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t a3g4250d_hp_reference_value_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
A3G4250D_SPI_4_WIRE = 0,
A3G4250D_SPI_3_WIRE = 1,
} a3g4250d_sim_t;
int32_t a3g4250d_spi_mode_set(stmdev_ctx_t *ctx, a3g4250d_sim_t val);
int32_t a3g4250d_spi_mode_get(stmdev_ctx_t *ctx, a3g4250d_sim_t *val);
-typedef struct {
+typedef struct
+{
uint8_t i1_int1 : 1;
uint8_t i1_boot : 1;
} a3g4250d_int1_route_t;
@@ -597,7 +628,8 @@ int32_t a3g4250d_pin_int1_route_set(stmdev_ctx_t *ctx,
int32_t a3g4250d_pin_int1_route_get(stmdev_ctx_t *ctx,
a3g4250d_int1_route_t *val);
-typedef struct {
+typedef struct
+{
uint8_t i2_empty : 1;
uint8_t i2_orun : 1;
uint8_t i2_wtm : 1;
@@ -608,14 +640,16 @@ int32_t a3g4250d_pin_int2_route_set(stmdev_ctx_t *ctx,
int32_t a3g4250d_pin_int2_route_get(stmdev_ctx_t *ctx,
a3g4250d_int2_route_t *val);
-typedef enum {
+typedef enum
+{
A3G4250D_PUSH_PULL = 0,
A3G4250D_OPEN_DRAIN = 1,
} a3g4250d_pp_od_t;
int32_t a3g4250d_pin_mode_set(stmdev_ctx_t *ctx, a3g4250d_pp_od_t val);
int32_t a3g4250d_pin_mode_get(stmdev_ctx_t *ctx, a3g4250d_pp_od_t *val);
-typedef enum {
+typedef enum
+{
A3G4250D_ACTIVE_HIGH = 0,
A3G4250D_ACTIVE_LOW = 1,
} a3g4250d_h_lactive_t;
@@ -624,21 +658,21 @@ int32_t a3g4250d_pin_polarity_set(stmdev_ctx_t *ctx,
int32_t a3g4250d_pin_polarity_get(stmdev_ctx_t *ctx,
a3g4250d_h_lactive_t *val);
-typedef enum {
+typedef enum
+{
A3G4250D_INT_PULSED = 0,
A3G4250D_INT_LATCHED = 1,
} a3g4250d_lir_t;
-int32_t a3g4250d_int_notification_set(stmdev_ctx_t *ctx,
- a3g4250d_lir_t val);
-int32_t a3g4250d_int_notification_get(stmdev_ctx_t *ctx,
- a3g4250d_lir_t *val);
+int32_t a3g4250d_int_notification_set(stmdev_ctx_t *ctx, a3g4250d_lir_t val);
+int32_t a3g4250d_int_notification_get(stmdev_ctx_t *ctx, a3g4250d_lir_t *val);
int32_t a3g4250d_int_on_threshold_conf_set(stmdev_ctx_t *ctx,
a3g4250d_int1_cfg_t *val);
int32_t a3g4250d_int_on_threshold_conf_get(stmdev_ctx_t *ctx,
a3g4250d_int1_cfg_t *val);
-typedef enum {
+typedef enum
+{
A3G4250D_INT1_ON_TH_AND = 1,
A3G4250D_INT1_ON_TH_OR = 0,
} a3g4250d_and_or_t;
@@ -668,7 +702,8 @@ int32_t a3g4250d_fifo_enable_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t a3g4250d_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t a3g4250d_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
A3G4250D_FIFO_BYPASS_MODE = 0x00,
A3G4250D_FIFO_MODE = 0x01,
A3G4250D_FIFO_STREAM_MODE = 0x02,
diff --git a/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.c b/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.c
index f04e75e7b85e122a994a98e37f724fbda3a22809..66fac817de6da9344ba7ad102223545d114c6586 100644
--- a/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.c
+++ b/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file ais2dw12_reg.c
- * @author Sensors Software Solution Team
- * @brief AIS2DW12 driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file ais2dw12_reg.c
+ * @author Sensors Software Solution Team
+ * @brief AIS2DW12 driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "ais2dw12_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais2dw12_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t ais2dw12_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t ais2dw12_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais2dw12_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t ais2dw12_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -86,7 +92,8 @@ int32_t ais2dw12_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
static void bytecpy(uint8_t *target, uint8_t *source)
{
- if ( (target != NULL) && (source != NULL) ) {
+ if ((target != NULL) && (source != NULL))
+ {
*target = *source;
}
}
@@ -150,17 +157,21 @@ float_t ais2dw12_from_lsb_to_celsius(int16_t lsb)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais2dw12_power_mode_set(stmdev_ctx_t *ctx, ais2dw12_mode_t val)
+int32_t ais2dw12_power_mode_set(stmdev_ctx_t *ctx,
+ ais2dw12_mode_t val)
{
ais2dw12_ctrl1_t ctrl1;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL1,(uint8_t*) &ctrl1, 1);
- if (ret == 0) {
- ctrl1.op_mode = ( (uint8_t) val & 0x0CU ) >> 2;
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1);
+
+ if (ret == 0)
+ {
+ ctrl1.op_mode = ((uint8_t) val & 0x0CU) >> 2;
ctrl1.pw_mode = (uint8_t) val & 0x03U ;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL1,(uint8_t*) &ctrl1, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1);
}
+
return ret;
}
@@ -173,41 +184,53 @@ int32_t ais2dw12_power_mode_set(stmdev_ctx_t *ctx, ais2dw12_mode_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais2dw12_power_mode_get(stmdev_ctx_t *ctx, ais2dw12_mode_t *val)
+int32_t ais2dw12_power_mode_get(stmdev_ctx_t *ctx,
+ ais2dw12_mode_t *val)
{
ais2dw12_ctrl1_t ctrl1;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL1,(uint8_t*) &ctrl1, 1);
- switch ( (ctrl1.op_mode << 2) + ctrl1.pw_mode) {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1);
+
+ switch ((ctrl1.op_mode << 2) + ctrl1.pw_mode)
+ {
case AIS2DW12_PWR_MD_4:
*val = AIS2DW12_PWR_MD_4;
break;
+
case AIS2DW12_PWR_MD_3:
*val = AIS2DW12_PWR_MD_3;
break;
+
case AIS2DW12_PWR_MD_2:
*val = AIS2DW12_PWR_MD_2;
break;
+
case AIS2DW12_PWR_MD_12bit:
*val = AIS2DW12_PWR_MD_12bit;
break;
+
case AIS2DW12_SINGLE_PWR_MD_4:
*val = AIS2DW12_SINGLE_PWR_MD_4;
break;
+
case AIS2DW12_SINGLE_PWR_MD_3:
*val = AIS2DW12_SINGLE_PWR_MD_3;
break;
+
case AIS2DW12_SINGLE_PWR_MD_2:
*val = AIS2DW12_SINGLE_PWR_MD_2;
break;
+
case AIS2DW12_SINGLE_PWR_MD_12bit:
*val = AIS2DW12_SINGLE_PWR_MD_12bit;
break;
+
default:
*val = AIS2DW12_PWR_MD_4;
break;
}
+
return ret;
}
@@ -225,18 +248,25 @@ int32_t ais2dw12_data_rate_set(stmdev_ctx_t *ctx, ais2dw12_odr_t val)
ais2dw12_ctrl3_t ctrl3;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL1,(uint8_t*) &ctrl1, 1);
- if (ret == 0) {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1);
+
+ if (ret == 0)
+ {
ctrl1.odr = (uint8_t) val;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL1,(uint8_t*) &ctrl1, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1);
}
- if (ret == 0) {
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3,(uint8_t*) &ctrl3, 1);
+
+ if (ret == 0)
+ {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) &ctrl3, 1);
}
- if (ret == 0) {
- ctrl3.slp_mode = ( (uint8_t) val & 0x30U ) >> 4;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL3,(uint8_t*) &ctrl3, 1);
+
+ if (ret == 0)
+ {
+ ctrl3.slp_mode = ((uint8_t) val & 0x30U) >> 4;
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) &ctrl3, 1);
}
+
return ret;
}
@@ -254,37 +284,48 @@ int32_t ais2dw12_data_rate_get(stmdev_ctx_t *ctx, ais2dw12_odr_t *val)
ais2dw12_ctrl3_t ctrl3;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL1,(uint8_t*) &ctrl1, 1);
- if (ret == 0) {
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3,(uint8_t*) &ctrl3, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1);
+
+ if (ret == 0)
+ {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) &ctrl3, 1);
- switch ((ctrl3.slp_mode << 4) + ctrl1.odr) {
+ switch ((ctrl3.slp_mode << 4) + ctrl1.odr)
+ {
case AIS2DW12_XL_ODR_OFF:
*val = AIS2DW12_XL_ODR_OFF;
break;
+
case AIS2DW12_XL_ODR_12Hz5:
*val = AIS2DW12_XL_ODR_12Hz5;
break;
+
case AIS2DW12_XL_ODR_25Hz:
*val = AIS2DW12_XL_ODR_25Hz;
break;
- case AIS2DW12_XL_ODR_50Hz:
+
+ case AIS2DW12_XL_ODR_50Hz:
*val = AIS2DW12_XL_ODR_50Hz;
break;
+
case AIS2DW12_XL_ODR_100Hz:
*val = AIS2DW12_XL_ODR_100Hz;
break;
+
case AIS2DW12_XL_SET_SW_TRIG:
*val = AIS2DW12_XL_SET_SW_TRIG;
break;
+
case AIS2DW12_XL_SET_PIN_TRIG:
*val = AIS2DW12_XL_SET_PIN_TRIG;
break;
+
default:
*val = AIS2DW12_XL_ODR_OFF;
break;
}
}
+
return ret;
}
@@ -301,11 +342,14 @@ int32_t ais2dw12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
ais2dw12_ctrl2_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.bdu = val;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL2,(uint8_t*) ®, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -317,12 +361,13 @@ int32_t ais2dw12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais2dw12_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ais2dw12_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ais2dw12_ctrl2_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2,(uint8_t*) ®, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
*val = reg.bdu;
return ret;
@@ -341,11 +386,14 @@ int32_t ais2dw12_full_scale_set(stmdev_ctx_t *ctx, ais2dw12_fs_t val)
ais2dw12_ctrl6_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL6,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL6, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.fs = (uint8_t) val;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL6,(uint8_t*) ®, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL6, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -362,19 +410,23 @@ int32_t ais2dw12_full_scale_get(stmdev_ctx_t *ctx, ais2dw12_fs_t *val)
ais2dw12_ctrl6_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL6,(uint8_t*) ®, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL6, (uint8_t *) ®, 1);
- switch (reg.fs) {
+ switch (reg.fs)
+ {
case AIS2DW12_2g:
*val = AIS2DW12_2g;
break;
+
case AIS2DW12_4g:
*val = AIS2DW12_4g;
break;
+
default:
*val = AIS2DW12_2g;
break;
}
+
return ret;
}
@@ -386,10 +438,13 @@ int32_t ais2dw12_full_scale_get(stmdev_ctx_t *ctx, ais2dw12_fs_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais2dw12_status_reg_get(stmdev_ctx_t *ctx, ais2dw12_status_t *val)
+int32_t ais2dw12_status_reg_get(stmdev_ctx_t *ctx,
+ ais2dw12_status_t *val)
{
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_STATUS, (uint8_t*) val, 1);
+
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_STATUS, (uint8_t *) val, 1);
+
return ret;
}
@@ -406,7 +461,7 @@ int32_t ais2dw12_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
ais2dw12_status_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_STATUS,(uint8_t*) ®, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_STATUS, (uint8_t *) ®, 1);
*val = reg.drdy;
return ret;
@@ -427,10 +482,10 @@ int32_t ais2dw12_all_sources_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = ais2dw12_read_reg(ctx, AIS2DW12_STATUS_DUP, reg, 5);
- bytecpy(( uint8_t*)&val->status_dup, ®[0]);
- bytecpy(( uint8_t*)&val->wake_up_src, ®[1]);
- bytecpy(( uint8_t*)&val->sixd_src, ®[3]);
- bytecpy(( uint8_t*)&val->all_int_src, ®[4]);
+ bytecpy((uint8_t *)&val->status_dup, ®[0]);
+ bytecpy((uint8_t *)&val->wake_up_src, ®[1]);
+ bytecpy((uint8_t *)&val->sixd_src, ®[3]);
+ bytecpy((uint8_t *)&val->all_int_src, ®[4]);
return ret;
}
@@ -448,7 +503,9 @@ int32_t ais2dw12_all_sources_get(stmdev_ctx_t *ctx,
int32_t ais2dw12_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = ais2dw12_write_reg(ctx, AIS2DW12_X_OFS_USR, buff, 1);
+
return ret;
}
@@ -465,7 +522,9 @@ int32_t ais2dw12_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t ais2dw12_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = ais2dw12_read_reg(ctx, AIS2DW12_X_OFS_USR, buff, 1);
+
return ret;
}
@@ -482,7 +541,9 @@ int32_t ais2dw12_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t ais2dw12_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = ais2dw12_write_reg(ctx, AIS2DW12_Y_OFS_USR, buff, 1);
+
return ret;
}
@@ -499,7 +560,9 @@ int32_t ais2dw12_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t ais2dw12_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = ais2dw12_read_reg(ctx, AIS2DW12_Y_OFS_USR, buff, 1);
+
return ret;
}
@@ -516,7 +579,9 @@ int32_t ais2dw12_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t ais2dw12_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = ais2dw12_write_reg(ctx, AIS2DW12_Z_OFS_USR, buff, 1);
+
return ret;
}
@@ -533,7 +598,9 @@ int32_t ais2dw12_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t ais2dw12_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = ais2dw12_read_reg(ctx, AIS2DW12_Z_OFS_USR, buff, 1);
+
return ret;
}
@@ -553,11 +620,14 @@ int32_t ais2dw12_offset_weight_set(stmdev_ctx_t *ctx,
ais2dw12_ctrl7_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.usr_off_w = (uint8_t) val;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL7,(uint8_t*) ®, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -576,18 +646,23 @@ int32_t ais2dw12_offset_weight_get(stmdev_ctx_t *ctx,
ais2dw12_ctrl7_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7,(uint8_t*) ®, 1);
- switch (reg.usr_off_w) {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
+
+ switch (reg.usr_off_w)
+ {
case AIS2DW12_LSb_977ug:
*val = AIS2DW12_LSb_977ug;
break;
+
case AIS2DW12_LSb_15mg6:
*val = AIS2DW12_LSb_15mg6;
break;
+
default:
*val = AIS2DW12_LSb_977ug;
break;
}
+
return ret;
}
@@ -619,7 +694,7 @@ int32_t ais2dw12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
ret = ais2dw12_read_reg(ctx, AIS2DW12_OUT_T_L, buff, 2);
*val = (int16_t)buff[1];
- *val = (*val * 256) + (int16_t)buff[0];
+ *val = (*val * 256) + (int16_t)buff[0];
return ret;
}
@@ -640,11 +715,12 @@ int32_t ais2dw12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
ret = ais2dw12_read_reg(ctx, AIS2DW12_OUT_X_L, buff, 6);
val[0] = (int16_t)buff[1];
- val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
- val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
val[2] = (int16_t)buff[5];
- val[2] = (val[2] * 256) + (int16_t)buff[4];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -671,7 +747,9 @@ int32_t ais2dw12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
int32_t ais2dw12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = ais2dw12_read_reg(ctx, AIS2DW12_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -689,11 +767,14 @@ int32_t ais2dw12_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
ais2dw12_ctrl2_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.if_add_inc = val;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL2,(uint8_t*) ®, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -711,7 +792,7 @@ int32_t ais2dw12_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
ais2dw12_ctrl2_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2,(uint8_t*) ®, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
*val = reg.if_add_inc;
return ret;
@@ -730,10 +811,12 @@ int32_t ais2dw12_reset_set(stmdev_ctx_t *ctx, uint8_t val)
ais2dw12_ctrl2_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.soft_reset = val;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL2,(uint8_t*) ®, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
}
return ret;
@@ -752,7 +835,7 @@ int32_t ais2dw12_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
ais2dw12_ctrl2_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2,(uint8_t*) ®, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
*val = reg.soft_reset;
return ret;
@@ -771,11 +854,14 @@ int32_t ais2dw12_boot_set(stmdev_ctx_t *ctx, uint8_t val)
ais2dw12_ctrl2_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.boot = val;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL2,(uint8_t*) ®, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -792,7 +878,7 @@ int32_t ais2dw12_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
ais2dw12_ctrl2_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2,(uint8_t*) ®, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
*val = reg.boot;
return ret;
@@ -811,10 +897,12 @@ int32_t ais2dw12_self_test_set(stmdev_ctx_t *ctx, ais2dw12_st_t val)
ais2dw12_ctrl3_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.st = (uint8_t) val;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL3,(uint8_t*) ®, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) ®, 1);
}
return ret;
@@ -833,22 +921,27 @@ int32_t ais2dw12_self_test_get(stmdev_ctx_t *ctx, ais2dw12_st_t *val)
ais2dw12_ctrl3_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3,(uint8_t*) ®, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) ®, 1);
- switch (reg.st) {
+ switch (reg.st)
+ {
case AIS2DW12_XL_ST_DISABLE:
*val = AIS2DW12_XL_ST_DISABLE;
break;
+
case AIS2DW12_XL_ST_POSITIVE:
*val = AIS2DW12_XL_ST_POSITIVE;
break;
+
case AIS2DW12_XL_ST_NEGATIVE:
*val = AIS2DW12_XL_ST_NEGATIVE;
break;
+
default:
*val = AIS2DW12_XL_ST_DISABLE;
break;
}
+
return ret;
}
@@ -866,10 +959,12 @@ int32_t ais2dw12_data_ready_mode_set(stmdev_ctx_t *ctx,
ais2dw12_ctrl7_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.drdy_pulsed = (uint8_t) val;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL7,(uint8_t*) ®, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
}
return ret;
@@ -889,19 +984,23 @@ int32_t ais2dw12_data_ready_mode_get(stmdev_ctx_t *ctx,
ais2dw12_ctrl7_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7,(uint8_t*) ®, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
- switch (reg.drdy_pulsed) {
+ switch (reg.drdy_pulsed)
+ {
case AIS2DW12_DRDY_LATCHED:
*val = AIS2DW12_DRDY_LATCHED;
break;
+
case AIS2DW12_DRDY_PULSED:
*val = AIS2DW12_DRDY_PULSED;
break;
+
default:
*val = AIS2DW12_DRDY_LATCHED;
break;
}
+
return ret;
}
@@ -926,23 +1025,30 @@ int32_t ais2dw12_data_ready_mode_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais2dw12_filter_path_set(stmdev_ctx_t *ctx, ais2dw12_fds_t val)
+int32_t ais2dw12_filter_path_set(stmdev_ctx_t *ctx,
+ ais2dw12_fds_t val)
{
ais2dw12_ctrl6_t ctrl6;
ais2dw12_ctrl7_t ctrl_reg7;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL6,(uint8_t*) &ctrl6, 1);
- if (ret == 0) {
- ctrl6.fds = ( (uint8_t) val & 0x10U ) >> 4;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL6,(uint8_t*) &ctrl6, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1);
+
+ if (ret == 0)
+ {
+ ctrl6.fds = ((uint8_t) val & 0x10U) >> 4;
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1);
}
- if (ret == 0) {
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7,(uint8_t*) &ctrl_reg7, 1);
+
+ if (ret == 0)
+ {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) &ctrl_reg7, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ctrl_reg7.usr_off_on_out = (uint8_t) val & 0x01U;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL7,(uint8_t*) &ctrl_reg7, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) &ctrl_reg7, 1);
}
return ret;
@@ -956,31 +1062,39 @@ int32_t ais2dw12_filter_path_set(stmdev_ctx_t *ctx, ais2dw12_fds_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais2dw12_filter_path_get(stmdev_ctx_t *ctx, ais2dw12_fds_t *val)
+int32_t ais2dw12_filter_path_get(stmdev_ctx_t *ctx,
+ ais2dw12_fds_t *val)
{
ais2dw12_ctrl6_t ctrl6;
ais2dw12_ctrl7_t ctrl_reg7;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL6,(uint8_t*) &ctrl6, 1);
- if (ret == 0) {
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7,(uint8_t*) &ctrl_reg7, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1);
- switch ((ctrl6.fds << 4 ) + ctrl_reg7.usr_off_on_out) {
+ if (ret == 0)
+ {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) &ctrl_reg7, 1);
+
+ switch ((ctrl6.fds << 4) + ctrl_reg7.usr_off_on_out)
+ {
case AIS2DW12_LPF_ON_OUT:
*val = AIS2DW12_LPF_ON_OUT;
break;
+
case AIS2DW12_USER_OFFSET_ON_OUT:
*val = AIS2DW12_USER_OFFSET_ON_OUT;
break;
+
case AIS2DW12_HIGH_PASS_ON_OUT:
*val = AIS2DW12_HIGH_PASS_ON_OUT;
break;
+
default:
*val = AIS2DW12_LPF_ON_OUT;
break;
}
}
+
return ret;
}
@@ -994,15 +1108,17 @@ int32_t ais2dw12_filter_path_get(stmdev_ctx_t *ctx, ais2dw12_fds_t *val)
*
*/
int32_t ais2dw12_filter_bandwidth_set(stmdev_ctx_t *ctx,
- ais2dw12_bw_filt_t val)
+ ais2dw12_bw_filt_t val)
{
ais2dw12_ctrl6_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL6,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL6, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.bw_filt = (uint8_t) val;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL6,(uint8_t*) ®, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL6, (uint8_t *) ®, 1);
}
return ret;
@@ -1018,30 +1134,36 @@ int32_t ais2dw12_filter_bandwidth_set(stmdev_ctx_t *ctx,
*
*/
int32_t ais2dw12_filter_bandwidth_get(stmdev_ctx_t *ctx,
- ais2dw12_bw_filt_t *val)
+ ais2dw12_bw_filt_t *val)
{
ais2dw12_ctrl6_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL6,(uint8_t*) ®, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL6, (uint8_t *) ®, 1);
- switch (reg.bw_filt) {
+ switch (reg.bw_filt)
+ {
case AIS2DW12_ODR_DIV_2:
*val = AIS2DW12_ODR_DIV_2;
break;
+
case AIS2DW12_ODR_DIV_4:
*val = AIS2DW12_ODR_DIV_4;
break;
+
case AIS2DW12_ODR_DIV_10:
*val = AIS2DW12_ODR_DIV_10;
break;
+
case AIS2DW12_ODR_DIV_20:
*val = AIS2DW12_ODR_DIV_20;
break;
+
default:
*val = AIS2DW12_ODR_DIV_2;
break;
}
+
return ret;
}
@@ -1058,11 +1180,14 @@ int32_t ais2dw12_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val)
ais2dw12_ctrl7_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.hp_ref_mode = val;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL7,(uint8_t*) ®, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1079,7 +1204,7 @@ int32_t ais2dw12_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
ais2dw12_ctrl7_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7,(uint8_t*) ®, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
*val = reg.hp_ref_mode;
return ret;
@@ -1111,11 +1236,14 @@ int32_t ais2dw12_spi_mode_set(stmdev_ctx_t *ctx, ais2dw12_sim_t val)
ais2dw12_ctrl2_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.sim = (uint8_t) val;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL2,(uint8_t*) ®, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1132,19 +1260,23 @@ int32_t ais2dw12_spi_mode_get(stmdev_ctx_t *ctx, ais2dw12_sim_t *val)
ais2dw12_ctrl2_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2,(uint8_t*) ®, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
- switch (reg.sim) {
+ switch (reg.sim)
+ {
case AIS2DW12_SPI_4_WIRE:
*val = AIS2DW12_SPI_4_WIRE;
break;
+
case AIS2DW12_SPI_3_WIRE:
*val = AIS2DW12_SPI_3_WIRE;
break;
+
default:
*val = AIS2DW12_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -1163,11 +1295,14 @@ int32_t ais2dw12_i2c_interface_set(stmdev_ctx_t *ctx,
ais2dw12_ctrl2_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.i2c_disable = (uint8_t) val;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL2,(uint8_t*) ®, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1185,19 +1320,23 @@ int32_t ais2dw12_i2c_interface_get(stmdev_ctx_t *ctx,
ais2dw12_ctrl2_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2,(uint8_t*) ®, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
- switch (reg.i2c_disable) {
+ switch (reg.i2c_disable)
+ {
case AIS2DW12_I2C_ENABLE:
*val = AIS2DW12_I2C_ENABLE;
break;
+
case AIS2DW12_I2C_DISABLE:
*val = AIS2DW12_I2C_DISABLE;
break;
+
default:
*val = AIS2DW12_I2C_ENABLE;
break;
}
+
return ret;
}
@@ -1209,16 +1348,20 @@ int32_t ais2dw12_i2c_interface_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais2dw12_cs_mode_set(stmdev_ctx_t *ctx, ais2dw12_cs_pu_disc_t val)
+int32_t ais2dw12_cs_mode_set(stmdev_ctx_t *ctx,
+ ais2dw12_cs_pu_disc_t val)
{
ais2dw12_ctrl2_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.cs_pu_disc = (uint8_t) val;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL2,(uint8_t*) ®, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1230,24 +1373,29 @@ int32_t ais2dw12_cs_mode_set(stmdev_ctx_t *ctx, ais2dw12_cs_pu_disc_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais2dw12_cs_mode_get(stmdev_ctx_t *ctx, ais2dw12_cs_pu_disc_t *val)
+int32_t ais2dw12_cs_mode_get(stmdev_ctx_t *ctx,
+ ais2dw12_cs_pu_disc_t *val)
{
ais2dw12_ctrl2_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2,(uint8_t*) ®, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
- switch (reg.cs_pu_disc) {
+ switch (reg.cs_pu_disc)
+ {
case AIS2DW12_PULL_UP_CONNECT:
*val = AIS2DW12_PULL_UP_CONNECT;
break;
+
case AIS2DW12_PULL_UP_DISCONNECT:
*val = AIS2DW12_PULL_UP_DISCONNECT;
break;
+
default:
*val = AIS2DW12_PULL_UP_CONNECT;
break;
}
+
return ret;
}
@@ -1277,11 +1425,14 @@ int32_t ais2dw12_pin_polarity_set(stmdev_ctx_t *ctx,
ais2dw12_ctrl3_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.h_lactive = (uint8_t) val;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL3,(uint8_t*) ®, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1299,19 +1450,23 @@ int32_t ais2dw12_pin_polarity_get(stmdev_ctx_t *ctx,
ais2dw12_ctrl3_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3,(uint8_t*) ®, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) ®, 1);
- switch (reg.h_lactive) {
+ switch (reg.h_lactive)
+ {
case AIS2DW12_ACTIVE_HIGH:
*val = AIS2DW12_ACTIVE_HIGH;
break;
+
case AIS2DW12_ACTIVE_LOW:
*val = AIS2DW12_ACTIVE_LOW;
break;
+
default:
*val = AIS2DW12_ACTIVE_HIGH;
break;
}
+
return ret;
}
@@ -1329,11 +1484,14 @@ int32_t ais2dw12_int_notification_set(stmdev_ctx_t *ctx,
ais2dw12_ctrl3_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.lir = (uint8_t) val;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL3,(uint8_t*) ®, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1351,19 +1509,23 @@ int32_t ais2dw12_int_notification_get(stmdev_ctx_t *ctx,
ais2dw12_ctrl3_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3,(uint8_t*) ®, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) ®, 1);
- switch (reg.lir) {
+ switch (reg.lir)
+ {
case AIS2DW12_INT_PULSED:
*val = AIS2DW12_INT_PULSED;
break;
+
case AIS2DW12_INT_LATCHED:
*val = AIS2DW12_INT_LATCHED;
break;
+
default:
*val = AIS2DW12_INT_PULSED;
break;
}
+
return ret;
}
@@ -1380,11 +1542,14 @@ int32_t ais2dw12_pin_mode_set(stmdev_ctx_t *ctx, ais2dw12_pp_od_t val)
ais2dw12_ctrl3_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.pp_od = (uint8_t) val;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL3,(uint8_t*) ®, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1396,24 +1561,29 @@ int32_t ais2dw12_pin_mode_set(stmdev_ctx_t *ctx, ais2dw12_pp_od_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais2dw12_pin_mode_get(stmdev_ctx_t *ctx, ais2dw12_pp_od_t *val)
+int32_t ais2dw12_pin_mode_get(stmdev_ctx_t *ctx,
+ ais2dw12_pp_od_t *val)
{
ais2dw12_ctrl3_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3,(uint8_t*) ®, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) ®, 1);
- switch (reg.pp_od) {
+ switch (reg.pp_od)
+ {
case AIS2DW12_PUSH_PULL:
*val = AIS2DW12_PUSH_PULL;
break;
+
case AIS2DW12_OPEN_DRAIN:
*val = AIS2DW12_OPEN_DRAIN;
break;
+
default:
*val = AIS2DW12_PUSH_PULL;
break;
}
+
return ret;
}
@@ -1433,28 +1603,38 @@ int32_t ais2dw12_pin_int1_route_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL5_INT2,
- (uint8_t*)&ctrl5_int2_pad_ctrl, 1);
+ (uint8_t *)&ctrl5_int2_pad_ctrl, 1);
- if (ret == 0) {
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7,(uint8_t*) ®, 1);
+ if (ret == 0)
+ {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
if ((val->int1_ff |
val->int1_wu |
val->int1_6d |
ctrl5_int2_pad_ctrl.int2_sleep_state |
- ctrl5_int2_pad_ctrl.int2_sleep_chg ) != PROPERTY_DISABLE){
+ ctrl5_int2_pad_ctrl.int2_sleep_chg) != PROPERTY_DISABLE)
+ {
reg.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
reg.interrupts_enable = PROPERTY_DISABLE;
}
ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL4_INT1,
- (uint8_t*) val, 1);
- } if (ret == 0) {
- ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL7,(uint8_t*) ®, 1);
+ (uint8_t *) val, 1);
}
+
+ if (ret == 0)
+ {
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
+ }
+
return ret;
}
@@ -1470,8 +1650,10 @@ int32_t ais2dw12_pin_int1_route_get(stmdev_ctx_t *ctx,
ais2dw12_ctrl4_int1_t *val)
{
int32_t ret;
+
ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL4_INT1,
- (uint8_t*) val, 1);
+ (uint8_t *) val, 1);
+
return ret;
}
@@ -1491,27 +1673,35 @@ int32_t ais2dw12_pin_int2_route_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL4_INT1,
- (uint8_t*) &ctrl4_int1_pad_ctrl, 1);
+ (uint8_t *) &ctrl4_int1_pad_ctrl, 1);
- if (ret == 0) {
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7,(uint8_t*) ®, 1);
+ if (ret == 0)
+ {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
if ((ctrl4_int1_pad_ctrl.int1_ff |
ctrl4_int1_pad_ctrl.int1_wu |
ctrl4_int1_pad_ctrl.int1_6d |
- val->int2_sleep_state | val->int2_sleep_chg ) != PROPERTY_DISABLE) {
- reg.interrupts_enable = PROPERTY_ENABLE;
+ val->int2_sleep_state | val->int2_sleep_chg) != PROPERTY_DISABLE)
+ {
+ reg.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
reg.interrupts_enable = PROPERTY_DISABLE;
}
ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL5_INT2,
- (uint8_t*) val, 1);
+ (uint8_t *) val, 1);
}
- if (ret == 0) {
- ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL7,(uint8_t*) ®, 1);
+
+ if (ret == 0)
+ {
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
}
return ret;
@@ -1529,8 +1719,10 @@ int32_t ais2dw12_pin_int2_route_get(stmdev_ctx_t *ctx,
ais2dw12_ctrl5_int2_t *val)
{
int32_t ret;
+
ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL5_INT2,
- (uint8_t*) val, 1);
+ (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1546,11 +1738,14 @@ int32_t ais2dw12_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
ais2dw12_ctrl7_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.int2_on_int1 = val;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL7,(uint8_t*) ®, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1567,7 +1762,7 @@ int32_t ais2dw12_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
ais2dw12_ctrl7_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7,(uint8_t*) ®, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
*val = reg.int2_on_int1;
return ret;
@@ -1599,11 +1794,14 @@ int32_t ais2dw12_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
ais2dw12_wake_up_ths_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_THS,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_THS, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.wk_ths = val;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_WAKE_UP_THS,(uint8_t*) ®, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_WAKE_UP_THS, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1620,7 +1818,7 @@ int32_t ais2dw12_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
ais2dw12_wake_up_ths_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_THS,(uint8_t*) ®, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_THS, (uint8_t *) ®, 1);
*val = reg.wk_ths;
return ret;
@@ -1639,11 +1837,14 @@ int32_t ais2dw12_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
ais2dw12_wake_up_dur_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_DUR,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.wake_dur = val;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_WAKE_UP_DUR,(uint8_t*) ®, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1660,7 +1861,7 @@ int32_t ais2dw12_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
ais2dw12_wake_up_dur_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_DUR,(uint8_t*) ®, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
*val = reg.wake_dur;
return ret;
@@ -1680,11 +1881,14 @@ int32_t ais2dw12_wkup_feed_data_set(stmdev_ctx_t *ctx,
ais2dw12_ctrl7_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.usr_off_on_wu = (uint8_t) val;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL7,(uint8_t*) ®, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1702,19 +1906,23 @@ int32_t ais2dw12_wkup_feed_data_get(stmdev_ctx_t *ctx,
ais2dw12_ctrl7_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7,(uint8_t*) ®, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
- switch (reg.usr_off_on_wu) {
+ switch (reg.usr_off_on_wu)
+ {
case AIS2DW12_HP_FEED:
*val = AIS2DW12_HP_FEED;
break;
+
case AIS2DW12_USER_OFFSET_FEED:
*val = AIS2DW12_USER_OFFSET_FEED;
break;
+
default:
*val = AIS2DW12_HP_FEED;
break;
}
+
return ret;
}
@@ -1741,23 +1949,34 @@ int32_t ais2dw12_wkup_feed_data_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais2dw12_act_mode_set(stmdev_ctx_t *ctx, ais2dw12_sleep_on_t val)
+int32_t ais2dw12_act_mode_set(stmdev_ctx_t *ctx,
+ ais2dw12_sleep_on_t val)
{
ais2dw12_wake_up_ths_t wake_up_ths;
ais2dw12_wake_up_dur_t wake_up_dur;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_THS,(uint8_t*) &wake_up_ths, 1);
- if (ret == 0) {
- ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_THS,
+ (uint8_t *) &wake_up_ths, 1);
+
+ if (ret == 0)
+ {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_DUR,
+ (uint8_t *) &wake_up_dur, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
wake_up_ths.sleep_on = (uint8_t) val & 0x01U;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_WAKE_UP_THS,(uint8_t*) &wake_up_ths, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_WAKE_UP_THS,
+ (uint8_t *) &wake_up_ths, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
wake_up_dur.stationary = ((uint8_t)val & 0x02U) >> 1;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_WAKE_UP_DUR,
+ (uint8_t *) &wake_up_dur, 1);
}
return ret;
@@ -1772,31 +1991,41 @@ int32_t ais2dw12_act_mode_set(stmdev_ctx_t *ctx, ais2dw12_sleep_on_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais2dw12_act_mode_get(stmdev_ctx_t *ctx, ais2dw12_sleep_on_t *val)
+int32_t ais2dw12_act_mode_get(stmdev_ctx_t *ctx,
+ ais2dw12_sleep_on_t *val)
{
ais2dw12_wake_up_ths_t wake_up_ths;
ais2dw12_wake_up_dur_t wake_up_dur;;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_THS,(uint8_t*) &wake_up_ths, 1);
- if (ret == 0) {
- ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_THS,
+ (uint8_t *) &wake_up_ths, 1);
+
+ if (ret == 0)
+ {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_DUR,
+ (uint8_t *) &wake_up_dur, 1);
- switch ((wake_up_dur.stationary << 1) + wake_up_ths.sleep_on){
+ switch ((wake_up_dur.stationary << 1) + wake_up_ths.sleep_on)
+ {
case AIS2DW12_NO_DETECTION:
*val = AIS2DW12_NO_DETECTION;
break;
+
case AIS2DW12_DETECT_ACT_INACT:
*val = AIS2DW12_DETECT_ACT_INACT;
break;
+
case AIS2DW12_DETECT_STAT_MOTION:
*val = AIS2DW12_DETECT_STAT_MOTION;
break;
+
default:
*val = AIS2DW12_NO_DETECTION;
break;
}
}
+
return ret;
}
@@ -1813,11 +2042,14 @@ int32_t ais2dw12_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
ais2dw12_wake_up_dur_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_DUR,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.sleep_dur = val;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_WAKE_UP_DUR,(uint8_t*) ®, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1834,7 +2066,7 @@ int32_t ais2dw12_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
ais2dw12_wake_up_dur_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_DUR,(uint8_t*) ®, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
*val = reg.sleep_dur;
return ret;
@@ -1866,11 +2098,14 @@ int32_t ais2dw12_6d_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
ais2dw12_sixd_ths_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_SIXD_THS,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_SIXD_THS, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg._6d_ths = val;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_SIXD_THS,(uint8_t*) ®, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_SIXD_THS, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1887,7 +2122,7 @@ int32_t ais2dw12_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
ais2dw12_sixd_ths_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_SIXD_THS,(uint8_t*) ®, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_SIXD_THS, (uint8_t *) ®, 1);
*val = reg._6d_ths;
return ret;
@@ -1906,10 +2141,12 @@ int32_t ais2dw12_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
ais2dw12_sixd_ths_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_SIXD_THS,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_SIXD_THS, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg._4d_en = val;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_SIXD_THS,(uint8_t*) ®, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_SIXD_THS, (uint8_t *) ®, 1);
}
return ret;
@@ -1928,7 +2165,7 @@ int32_t ais2dw12_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
ais2dw12_sixd_ths_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_SIXD_THS,(uint8_t*) ®, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_SIXD_THS, (uint8_t *) ®, 1);
*val = reg._4d_en;
return ret;
@@ -1942,10 +2179,13 @@ int32_t ais2dw12_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais2dw12_6d_src_get(stmdev_ctx_t *ctx, ais2dw12_sixd_src_t *val)
+int32_t ais2dw12_6d_src_get(stmdev_ctx_t *ctx,
+ ais2dw12_sixd_src_t *val)
{
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_SIXD_SRC, (uint8_t*) val, 1);
+
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_SIXD_SRC, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1962,11 +2202,14 @@ int32_t ais2dw12_6d_feed_data_set(stmdev_ctx_t *ctx,
ais2dw12_ctrl7_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.lpass_on6d = (uint8_t) val;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL7,(uint8_t*) ®, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1984,19 +2227,23 @@ int32_t ais2dw12_6d_feed_data_get(stmdev_ctx_t *ctx,
ais2dw12_ctrl7_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7,(uint8_t*) ®, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
- switch (reg.lpass_on6d) {
+ switch (reg.lpass_on6d)
+ {
case AIS2DW12_ODR_DIV_2_FEED:
*val = AIS2DW12_ODR_DIV_2_FEED;
break;
+
case AIS2DW12_LPF2_FEED:
*val = AIS2DW12_LPF2_FEED;
break;
+
default:
*val = AIS2DW12_ODR_DIV_2_FEED;
break;
}
+
return ret;
}
@@ -2028,17 +2275,27 @@ int32_t ais2dw12_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
ais2dw12_free_fall_t free_fall;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
- if (ret == 0) {
- ret = ais2dw12_read_reg(ctx, AIS2DW12_FREE_FALL,(uint8_t*) &free_fall, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_DUR,
+ (uint8_t *) &wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_FREE_FALL,
+ (uint8_t *) &free_fall, 1);
}
- if(ret == 0) {
- wake_up_dur.ff_dur = ( (uint8_t) val & 0x20U) >> 5;
+
+ if (ret == 0)
+ {
+ wake_up_dur.ff_dur = ((uint8_t) val & 0x20U) >> 5;
free_fall.ff_dur = (uint8_t) val & 0x1FU;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_WAKE_UP_DUR,
+ (uint8_t *) &wake_up_dur, 1);
}
- if(ret == 0) {
- ret = ais2dw12_write_reg(ctx, AIS2DW12_FREE_FALL,(uint8_t*) &free_fall, 1);
+
+ if (ret == 0)
+ {
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_FREE_FALL,
+ (uint8_t *) &free_fall, 1);
}
return ret;
@@ -2059,11 +2316,16 @@ int32_t ais2dw12_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
ais2dw12_free_fall_t free_fall;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
- if (ret == 0) {
- ret = ais2dw12_read_reg(ctx, AIS2DW12_FREE_FALL,(uint8_t*) &free_fall, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_DUR,
+ (uint8_t *) &wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_FREE_FALL,
+ (uint8_t *) &free_fall, 1);
*val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
}
+
return ret;
}
@@ -2075,15 +2337,18 @@ int32_t ais2dw12_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais2dw12_ff_threshold_set(stmdev_ctx_t *ctx, ais2dw12_ff_ths_t val)
+int32_t ais2dw12_ff_threshold_set(stmdev_ctx_t *ctx,
+ ais2dw12_ff_ths_t val)
{
ais2dw12_free_fall_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_FREE_FALL,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_FREE_FALL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.ff_ths = (uint8_t) val;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_FREE_FALL,(uint8_t*) ®, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_FREE_FALL, (uint8_t *) ®, 1);
}
return ret;
@@ -2103,37 +2368,47 @@ int32_t ais2dw12_ff_threshold_get(stmdev_ctx_t *ctx,
ais2dw12_free_fall_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_FREE_FALL,(uint8_t*) ®, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_FREE_FALL, (uint8_t *) ®, 1);
- switch (reg.ff_ths) {
+ switch (reg.ff_ths)
+ {
case AIS2DW12_FF_TSH_5LSb_FS2g:
*val = AIS2DW12_FF_TSH_5LSb_FS2g;
break;
+
case AIS2DW12_FF_TSH_7LSb_FS2g:
*val = AIS2DW12_FF_TSH_7LSb_FS2g;
break;
+
case AIS2DW12_FF_TSH_8LSb_FS2g:
*val = AIS2DW12_FF_TSH_8LSb_FS2g;
break;
+
case AIS2DW12_FF_TSH_10LSb_FS2g:
*val = AIS2DW12_FF_TSH_10LSb_FS2g;
break;
+
case AIS2DW12_FF_TSH_11LSb_FS2g:
*val = AIS2DW12_FF_TSH_11LSb_FS2g;
break;
+
case AIS2DW12_FF_TSH_13LSb_FS2g:
*val = AIS2DW12_FF_TSH_13LSb_FS2g;
break;
+
case AIS2DW12_FF_TSH_15LSb_FS2g:
*val = AIS2DW12_FF_TSH_15LSb_FS2g;
break;
+
case AIS2DW12_FF_TSH_16LSb_FS2g:
*val = AIS2DW12_FF_TSH_16LSb_FS2g;
break;
+
default:
*val = AIS2DW12_FF_TSH_5LSb_FS2g;
break;
}
+
return ret;
}
@@ -2162,10 +2437,12 @@ int32_t ais2dw12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
ais2dw12_fifo_ctrl_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_FIFO_CTRL,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.fth = val;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_FIFO_CTRL,(uint8_t*) ®, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1);
}
return ret;
@@ -2184,7 +2461,7 @@ int32_t ais2dw12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
ais2dw12_fifo_ctrl_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_FIFO_CTRL,(uint8_t*) ®, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1);
*val = reg.fth;
return ret;
@@ -2198,16 +2475,20 @@ int32_t ais2dw12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais2dw12_fifo_mode_set(stmdev_ctx_t *ctx, ais2dw12_fmode_t val)
+int32_t ais2dw12_fifo_mode_set(stmdev_ctx_t *ctx,
+ ais2dw12_fmode_t val)
{
ais2dw12_fifo_ctrl_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_FIFO_CTRL,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.fmode = (uint8_t) val;
- ret = ais2dw12_write_reg(ctx, AIS2DW12_FIFO_CTRL,(uint8_t*) ®, 1);
+ ret = ais2dw12_write_reg(ctx, AIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -2219,33 +2500,41 @@ int32_t ais2dw12_fifo_mode_set(stmdev_ctx_t *ctx, ais2dw12_fmode_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais2dw12_fifo_mode_get(stmdev_ctx_t *ctx, ais2dw12_fmode_t *val)
+int32_t ais2dw12_fifo_mode_get(stmdev_ctx_t *ctx,
+ ais2dw12_fmode_t *val)
{
ais2dw12_fifo_ctrl_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_FIFO_CTRL,(uint8_t*) ®, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1);
- switch (reg.fmode) {
+ switch (reg.fmode)
+ {
case AIS2DW12_BYPASS_MODE:
*val = AIS2DW12_BYPASS_MODE;
break;
+
case AIS2DW12_FIFO_MODE:
*val = AIS2DW12_FIFO_MODE;
break;
+
case AIS2DW12_STREAM_TO_FIFO_MODE:
*val = AIS2DW12_STREAM_TO_FIFO_MODE;
break;
+
case AIS2DW12_BYPASS_TO_STREAM_MODE:
*val = AIS2DW12_BYPASS_TO_STREAM_MODE;
break;
+
case AIS2DW12_STREAM_MODE:
*val = AIS2DW12_STREAM_MODE;
break;
+
default:
*val = AIS2DW12_BYPASS_MODE;
break;
}
+
return ret;
}
@@ -2262,7 +2551,7 @@ int32_t ais2dw12_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val)
ais2dw12_fifo_samples_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_FIFO_SAMPLES,(uint8_t*) ®, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_FIFO_SAMPLES, (uint8_t *) ®, 1);
*val = reg.diff;
return ret;
@@ -2280,7 +2569,7 @@ int32_t ais2dw12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
ais2dw12_fifo_samples_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_FIFO_SAMPLES,(uint8_t*) ®, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_FIFO_SAMPLES, (uint8_t *) ®, 1);
*val = reg.fifo_ovr;
return ret;
@@ -2298,7 +2587,7 @@ int32_t ais2dw12_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
ais2dw12_fifo_samples_t reg;
int32_t ret;
- ret = ais2dw12_read_reg(ctx, AIS2DW12_FIFO_SAMPLES,(uint8_t*) ®, 1);
+ ret = ais2dw12_read_reg(ctx, AIS2DW12_FIFO_SAMPLES, (uint8_t *) ®, 1);
*val = reg.fifo_fth;
return ret;
diff --git a/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.h b/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.h
index 98d1d6d1847143cbcecf0c264b064e6c00e7db34..e06f042214117cfb28cdd7462fa8f52a557c63d1 100644
--- a/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.h
+++ b/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.h
@@ -1,29 +1,29 @@
-/*
- ******************************************************************************
- * @file ais2dw12_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * ais2dw12_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file ais2dw12_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * ais2dw12_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef AIS2DW12_REGS_H
#define AIS2DW12_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -75,7 +75,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -113,10 +114,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -145,7 +147,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -183,7 +186,8 @@ typedef struct {
#define AIS2DW12_OUT_T_H 0x0EU
#define AIS2DW12_WHO_AM_I 0x0FU
#define AIS2DW12_CTRL1 0x20U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t pw_mode : 2;
uint8_t op_mode : 2;
@@ -196,7 +200,8 @@ typedef struct {
} ais2dw12_ctrl1_t;
#define AIS2DW12_CTRL2 0x21U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t i2c_disable : 1;
@@ -219,9 +224,11 @@ typedef struct {
} ais2dw12_ctrl2_t;
#define AIS2DW12_CTRL3 0x22U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t slp_mode : 2; /* slp_mode_sel + slp_mode_1 */
+uint8_t slp_mode :
+ 2; /* slp_mode_sel + slp_mode_1 */
uint8_t not_used_01 : 1;
uint8_t h_lactive : 1;
uint8_t lir : 1;
@@ -233,12 +240,14 @@ typedef struct {
uint8_t lir : 1;
uint8_t h_lactive : 1;
uint8_t not_used_01 : 1;
- uint8_t slp_mode : 2; /* slp_mode_sel + slp_mode_1 */
+uint8_t slp_mode :
+ 2; /* slp_mode_sel + slp_mode_1 */
#endif /* DRV_BYTE_ORDER */
} ais2dw12_ctrl3_t;
#define AIS2DW12_CTRL4_INT1 0x23U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_drdy : 1;
uint8_t int1_fth : 1;
@@ -261,7 +270,8 @@ typedef struct {
} ais2dw12_ctrl4_int1_t;
#define AIS2DW12_CTRL5_INT2 0x24U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_drdy : 1;
uint8_t int2_fth : 1;
@@ -284,7 +294,8 @@ typedef struct {
} ais2dw12_ctrl5_int2_t;
#define AIS2DW12_CTRL6 0x25U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t fds : 1;
@@ -300,7 +311,8 @@ typedef struct {
#define AIS2DW12_OUT_T 0x26U
#define AIS2DW12_STATUS 0x27U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t drdy : 1;
uint8_t ff_ia : 1;
@@ -327,7 +339,8 @@ typedef struct {
#define AIS2DW12_OUT_Z_L 0x2CU
#define AIS2DW12_OUT_Z_H 0x2DU
#define AIS2DW12_FIFO_CTRL 0x2EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fth : 5;
uint8_t fmode : 3;
@@ -338,7 +351,8 @@ typedef struct {
} ais2dw12_fifo_ctrl_t;
#define AIS2DW12_FIFO_SAMPLES 0x2FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t diff : 6;
uint8_t fifo_ovr : 1;
@@ -351,7 +365,8 @@ typedef struct {
} ais2dw12_fifo_samples_t;
#define AIS2DW12_SIXD_THS 0x30U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 5;
uint8_t _6d_ths : 2;
@@ -364,7 +379,8 @@ typedef struct {
} ais2dw12_sixd_ths_t;
#define AIS2DW12_WAKE_UP_THS 0x34U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wk_ths : 6;
uint8_t sleep_on : 1;
@@ -377,7 +393,8 @@ typedef struct {
} ais2dw12_wake_up_ths_t;
#define AIS2DW12_WAKE_UP_DUR 0x35U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sleep_dur : 4;
uint8_t stationary : 1;
@@ -392,7 +409,8 @@ typedef struct {
} ais2dw12_wake_up_dur_t;
#define AIS2DW12_FREE_FALL 0x36U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ths : 3;
uint8_t ff_dur : 5;
@@ -403,7 +421,8 @@ typedef struct {
} ais2dw12_free_fall_t;
#define AIS2DW12_STATUS_DUP 0x37U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t drdy : 1;
uint8_t ff_ia : 1;
@@ -424,7 +443,8 @@ typedef struct {
} ais2dw12_status_dup_t;
#define AIS2DW12_WAKE_UP_SRC 0x38U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_wu : 1;
uint8_t y_wu : 1;
@@ -445,7 +465,8 @@ typedef struct {
} ais2dw12_wake_up_src_t;
#define AIS2DW12_SIXD_SRC 0x3AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
@@ -468,7 +489,8 @@ typedef struct {
} ais2dw12_sixd_src_t;
#define AIS2DW12_ALL_INT_SRC 0x3BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ia : 1;
uint8_t wu_ia : 1;
@@ -490,7 +512,8 @@ typedef struct {
#define AIS2DW12_Y_OFS_USR 0x3DU
#define AIS2DW12_Z_OFS_USR 0x3EU
#define AIS2DW12_CTRL7 0x3FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lpass_on6d : 1;
uint8_t hp_ref_mode : 1;
@@ -514,9 +537,9 @@ typedef struct {
/**
* @defgroup AIS2DW12_Register_Union
- * @brief This union group all the registers that has a bitfield
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -524,7 +547,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
ais2dw12_ctrl1_t ctrl1;
ais2dw12_ctrl2_t ctrl2;
ais2dw12_ctrl3_t ctrl3;
@@ -552,9 +576,11 @@ typedef union{
*
*/
-int32_t ais2dw12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t ais2dw12_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t ais2dw12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t ais2dw12_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
float_t ais2dw12_from_fs2_to_mg(int16_t lsb);
@@ -564,7 +590,8 @@ float_t ais2dw12_from_fs4_12bit_to_mg(int16_t lsb);
float_t ais2dw12_from_lsb_to_celsius(int16_t lsb);
-typedef enum {
+typedef enum
+{
AIS2DW12_PWR_MD_4 = 0x03,
AIS2DW12_PWR_MD_3 = 0x02,
AIS2DW12_PWR_MD_2 = 0x01,
@@ -574,10 +601,13 @@ typedef enum {
AIS2DW12_SINGLE_PWR_MD_2 = 0x09,
AIS2DW12_SINGLE_PWR_MD_12bit = 0x08,
} ais2dw12_mode_t;
-int32_t ais2dw12_power_mode_set(stmdev_ctx_t *ctx, ais2dw12_mode_t val);
-int32_t ais2dw12_power_mode_get(stmdev_ctx_t *ctx, ais2dw12_mode_t *val);
+int32_t ais2dw12_power_mode_set(stmdev_ctx_t *ctx,
+ ais2dw12_mode_t val);
+int32_t ais2dw12_power_mode_get(stmdev_ctx_t *ctx,
+ ais2dw12_mode_t *val);
-typedef enum {
+typedef enum
+{
AIS2DW12_XL_ODR_OFF = 0x00,
AIS2DW12_XL_ODR_1Hz6 = 0x01,
AIS2DW12_XL_ODR_12Hz5 = 0x02,
@@ -588,23 +618,30 @@ typedef enum {
AIS2DW12_XL_SET_PIN_TRIG = 0x22, /* Use this only in SINGLE mode */
} ais2dw12_odr_t;
int32_t ais2dw12_data_rate_set(stmdev_ctx_t *ctx, ais2dw12_odr_t val);
-int32_t ais2dw12_data_rate_get(stmdev_ctx_t *ctx, ais2dw12_odr_t *val);
+int32_t ais2dw12_data_rate_get(stmdev_ctx_t *ctx,
+ ais2dw12_odr_t *val);
-int32_t ais2dw12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ais2dw12_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ais2dw12_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ais2dw12_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
AIS2DW12_2g = 0,
AIS2DW12_4g = 1,
} ais2dw12_fs_t;
int32_t ais2dw12_full_scale_set(stmdev_ctx_t *ctx, ais2dw12_fs_t val);
-int32_t ais2dw12_full_scale_get(stmdev_ctx_t *ctx, ais2dw12_fs_t *val);
+int32_t ais2dw12_full_scale_get(stmdev_ctx_t *ctx,
+ ais2dw12_fs_t *val);
-int32_t ais2dw12_status_reg_get(stmdev_ctx_t *ctx, ais2dw12_status_t *val);
+int32_t ais2dw12_status_reg_get(stmdev_ctx_t *ctx,
+ ais2dw12_status_t *val);
int32_t ais2dw12_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef struct{
+typedef struct
+{
ais2dw12_status_dup_t status_dup;
ais2dw12_wake_up_src_t wake_up_src;
ais2dw12_sixd_src_t sixd_src;
@@ -622,18 +659,20 @@ int32_t ais2dw12_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t ais2dw12_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t ais2dw12_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff);
-typedef enum {
+typedef enum
+{
AIS2DW12_LSb_977ug = 0,
AIS2DW12_LSb_15mg6 = 1,
} ais2dw12_usr_off_w_t;
int32_t ais2dw12_offset_weight_set(stmdev_ctx_t *ctx,
- ais2dw12_usr_off_w_t val);
+ ais2dw12_usr_off_w_t val);
int32_t ais2dw12_offset_weight_get(stmdev_ctx_t *ctx,
- ais2dw12_usr_off_w_t *val);
+ ais2dw12_usr_off_w_t *val);
int32_t ais2dw12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val);
-int32_t ais2dw12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t ais2dw12_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
int32_t ais2dw12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
@@ -646,7 +685,8 @@ int32_t ais2dw12_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t ais2dw12_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ais2dw12_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
AIS2DW12_XL_ST_DISABLE = 0,
AIS2DW12_XL_ST_POSITIVE = 1,
AIS2DW12_XL_ST_NEGATIVE = 2,
@@ -654,7 +694,8 @@ typedef enum {
int32_t ais2dw12_self_test_set(stmdev_ctx_t *ctx, ais2dw12_st_t val);
int32_t ais2dw12_self_test_get(stmdev_ctx_t *ctx, ais2dw12_st_t *val);
-typedef enum {
+typedef enum
+{
AIS2DW12_DRDY_LATCHED = 0,
AIS2DW12_DRDY_PULSED = 1,
} ais2dw12_drdy_pulsed_t;
@@ -663,36 +704,42 @@ int32_t ais2dw12_data_ready_mode_set(stmdev_ctx_t *ctx,
int32_t ais2dw12_data_ready_mode_get(stmdev_ctx_t *ctx,
ais2dw12_drdy_pulsed_t *val);
-typedef enum {
+typedef enum
+{
AIS2DW12_LPF_ON_OUT = 0x00,
AIS2DW12_USER_OFFSET_ON_OUT = 0x01,
AIS2DW12_HIGH_PASS_ON_OUT = 0x10,
} ais2dw12_fds_t;
-int32_t ais2dw12_filter_path_set(stmdev_ctx_t *ctx, ais2dw12_fds_t val);
-int32_t ais2dw12_filter_path_get(stmdev_ctx_t *ctx, ais2dw12_fds_t *val);
+int32_t ais2dw12_filter_path_set(stmdev_ctx_t *ctx,
+ ais2dw12_fds_t val);
+int32_t ais2dw12_filter_path_get(stmdev_ctx_t *ctx,
+ ais2dw12_fds_t *val);
-typedef enum {
+typedef enum
+{
AIS2DW12_ODR_DIV_2 = 0,
AIS2DW12_ODR_DIV_4 = 1,
AIS2DW12_ODR_DIV_10 = 2,
AIS2DW12_ODR_DIV_20 = 3,
} ais2dw12_bw_filt_t;
int32_t ais2dw12_filter_bandwidth_set(stmdev_ctx_t *ctx,
- ais2dw12_bw_filt_t val);
+ ais2dw12_bw_filt_t val);
int32_t ais2dw12_filter_bandwidth_get(stmdev_ctx_t *ctx,
- ais2dw12_bw_filt_t *val);
+ ais2dw12_bw_filt_t *val);
int32_t ais2dw12_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ais2dw12_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
AIS2DW12_SPI_4_WIRE = 0,
AIS2DW12_SPI_3_WIRE = 1,
} ais2dw12_sim_t;
int32_t ais2dw12_spi_mode_set(stmdev_ctx_t *ctx, ais2dw12_sim_t val);
int32_t ais2dw12_spi_mode_get(stmdev_ctx_t *ctx, ais2dw12_sim_t *val);
-typedef enum {
+typedef enum
+{
AIS2DW12_I2C_ENABLE = 0,
AIS2DW12_I2C_DISABLE = 1,
} ais2dw12_i2c_disable_t;
@@ -701,14 +748,18 @@ int32_t ais2dw12_i2c_interface_set(stmdev_ctx_t *ctx,
int32_t ais2dw12_i2c_interface_get(stmdev_ctx_t *ctx,
ais2dw12_i2c_disable_t *val);
-typedef enum {
+typedef enum
+{
AIS2DW12_PULL_UP_CONNECT = 0,
AIS2DW12_PULL_UP_DISCONNECT = 1,
} ais2dw12_cs_pu_disc_t;
-int32_t ais2dw12_cs_mode_set(stmdev_ctx_t *ctx, ais2dw12_cs_pu_disc_t val);
-int32_t ais2dw12_cs_mode_get(stmdev_ctx_t *ctx, ais2dw12_cs_pu_disc_t *val);
+int32_t ais2dw12_cs_mode_set(stmdev_ctx_t *ctx,
+ ais2dw12_cs_pu_disc_t val);
+int32_t ais2dw12_cs_mode_get(stmdev_ctx_t *ctx,
+ ais2dw12_cs_pu_disc_t *val);
-typedef enum {
+typedef enum
+{
AIS2DW12_ACTIVE_HIGH = 0,
AIS2DW12_ACTIVE_LOW = 1,
} ais2dw12_h_lactive_t;
@@ -717,7 +768,8 @@ int32_t ais2dw12_pin_polarity_set(stmdev_ctx_t *ctx,
int32_t ais2dw12_pin_polarity_get(stmdev_ctx_t *ctx,
ais2dw12_h_lactive_t *val);
-typedef enum {
+typedef enum
+{
AIS2DW12_INT_PULSED = 0,
AIS2DW12_INT_LATCHED = 1,
} ais2dw12_lir_t;
@@ -726,12 +778,15 @@ int32_t ais2dw12_int_notification_set(stmdev_ctx_t *ctx,
int32_t ais2dw12_int_notification_get(stmdev_ctx_t *ctx,
ais2dw12_lir_t *val);
-typedef enum {
+typedef enum
+{
AIS2DW12_PUSH_PULL = 0,
AIS2DW12_OPEN_DRAIN = 1,
} ais2dw12_pp_od_t;
-int32_t ais2dw12_pin_mode_set(stmdev_ctx_t *ctx, ais2dw12_pp_od_t val);
-int32_t ais2dw12_pin_mode_get(stmdev_ctx_t *ctx, ais2dw12_pp_od_t *val);
+int32_t ais2dw12_pin_mode_set(stmdev_ctx_t *ctx,
+ ais2dw12_pp_od_t val);
+int32_t ais2dw12_pin_mode_get(stmdev_ctx_t *ctx,
+ ais2dw12_pp_od_t *val);
int32_t ais2dw12_pin_int1_route_set(stmdev_ctx_t *ctx,
ais2dw12_ctrl4_int1_t *val);
@@ -752,7 +807,8 @@ int32_t ais2dw12_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t ais2dw12_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ais2dw12_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
AIS2DW12_HP_FEED = 0,
AIS2DW12_USER_OFFSET_FEED = 1,
} ais2dw12_usr_off_on_wu_t;
@@ -761,13 +817,16 @@ int32_t ais2dw12_wkup_feed_data_set(stmdev_ctx_t *ctx,
int32_t ais2dw12_wkup_feed_data_get(stmdev_ctx_t *ctx,
ais2dw12_usr_off_on_wu_t *val);
-typedef enum {
+typedef enum
+{
AIS2DW12_NO_DETECTION = 0,
AIS2DW12_DETECT_ACT_INACT = 1,
AIS2DW12_DETECT_STAT_MOTION = 3,
} ais2dw12_sleep_on_t;
-int32_t ais2dw12_act_mode_set(stmdev_ctx_t *ctx, ais2dw12_sleep_on_t val);
-int32_t ais2dw12_act_mode_get(stmdev_ctx_t *ctx, ais2dw12_sleep_on_t *val);
+int32_t ais2dw12_act_mode_set(stmdev_ctx_t *ctx,
+ ais2dw12_sleep_on_t val);
+int32_t ais2dw12_act_mode_get(stmdev_ctx_t *ctx,
+ ais2dw12_sleep_on_t *val);
int32_t ais2dw12_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ais2dw12_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -778,9 +837,11 @@ int32_t ais2dw12_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t ais2dw12_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ais2dw12_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t ais2dw12_6d_src_get(stmdev_ctx_t *ctx, ais2dw12_sixd_src_t *val);
+int32_t ais2dw12_6d_src_get(stmdev_ctx_t *ctx,
+ ais2dw12_sixd_src_t *val);
-typedef enum {
+typedef enum
+{
AIS2DW12_ODR_DIV_2_FEED = 0,
AIS2DW12_LPF2_FEED = 1,
} ais2dw12_lpass_on6d_t;
@@ -792,7 +853,8 @@ int32_t ais2dw12_6d_feed_data_get(stmdev_ctx_t *ctx,
int32_t ais2dw12_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ais2dw12_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
AIS2DW12_FF_TSH_5LSb_FS2g = 0,
AIS2DW12_FF_TSH_7LSb_FS2g = 1,
AIS2DW12_FF_TSH_8LSb_FS2g = 2,
@@ -810,15 +872,18 @@ int32_t ais2dw12_ff_threshold_get(stmdev_ctx_t *ctx,
int32_t ais2dw12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ais2dw12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
AIS2DW12_BYPASS_MODE = 0,
AIS2DW12_FIFO_MODE = 1,
AIS2DW12_STREAM_TO_FIFO_MODE = 3,
AIS2DW12_BYPASS_TO_STREAM_MODE = 4,
AIS2DW12_STREAM_MODE = 6,
} ais2dw12_fmode_t;
-int32_t ais2dw12_fifo_mode_set(stmdev_ctx_t *ctx, ais2dw12_fmode_t val);
-int32_t ais2dw12_fifo_mode_get(stmdev_ctx_t *ctx, ais2dw12_fmode_t *val);
+int32_t ais2dw12_fifo_mode_set(stmdev_ctx_t *ctx,
+ ais2dw12_fmode_t val);
+int32_t ais2dw12_fifo_mode_get(stmdev_ctx_t *ctx,
+ ais2dw12_fmode_t *val);
int32_t ais2dw12_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val);
diff --git a/sensor/stmemsc/ais2ih_STdC/driver/ais2ih_reg.c b/sensor/stmemsc/ais2ih_STdC/driver/ais2ih_reg.c
new file mode 100644
index 0000000000000000000000000000000000000000..f393607c2f0525c672ca73520f59096b562ba4b9
--- /dev/null
+++ b/sensor/stmemsc/ais2ih_STdC/driver/ais2ih_reg.c
@@ -0,0 +1,3252 @@
+/**
+ ******************************************************************************
+ * @file ais2ih_reg.c
+ * @author Sensors Software Solution Team
+ * @brief AIS2IH driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+#include "ais2ih_reg.h"
+
+/**
+ * @defgroup AIS2IH
+ * @brief This file provides a set of functions needed to drive the
+ * ais2ih enhanced inertial module.
+ * @{
+ *
+ */
+
+/**
+ * @defgroup AIS2IH_Interfaces_Functions
+ * @brief This section provide a set of functions used to read and
+ * write a generic register of the device.
+ * MANDATORY: return 0 -> no Error.
+ * @{
+ *
+ */
+
+/**
+ * @brief Read generic device register
+ *
+ * @param ctx read / write interface definitions(ptr)
+ * @param reg register to read
+ * @param data pointer to buffer that store the data read(ptr)
+ * @param len number of consecutive register to read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
+ uint16_t len)
+{
+ int32_t ret;
+
+ ret = ctx->read_reg(ctx->handle, reg, data, len);
+
+ return ret;
+}
+
+/**
+ * @brief Write generic device register
+ *
+ * @param ctx read / write interface definitions(ptr)
+ * @param reg register to write
+ * @param data pointer to data to write in register reg(ptr)
+ * @param len number of consecutive register to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
+{
+ int32_t ret;
+
+ ret = ctx->write_reg(ctx->handle, reg, data, len);
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup AIS2IH_Sensitivity
+ * @brief These functions convert raw-data into engineering units.
+ * @{
+ *
+ */
+
+float_t ais2ih_from_fs2_to_mg(int16_t lsb)
+{
+ return ((float_t)lsb) * 0.061f;
+}
+
+float_t ais2ih_from_fs4_to_mg(int16_t lsb)
+{
+ return ((float_t)lsb) * 0.122f;
+}
+
+float_t ais2ih_from_fs8_to_mg(int16_t lsb)
+{
+ return ((float_t)lsb) * 0.244f;
+}
+
+float_t ais2ih_from_fs16_to_mg(int16_t lsb)
+{
+ return ((float_t)lsb) * 0.488f;
+}
+
+float_t ais2ih_from_fs2_lp1_to_mg(int16_t lsb)
+{
+ return ((float_t)lsb) * 0.061f;
+}
+
+float_t ais2ih_from_fs4_lp1_to_mg(int16_t lsb)
+{
+ return ((float_t)lsb) * 0.122f;
+}
+
+float_t ais2ih_from_fs8_lp1_to_mg(int16_t lsb)
+{
+ return ((float_t)lsb) * 0.244f;
+}
+
+float_t ais2ih_from_fs16_lp1_to_mg(int16_t lsb)
+{
+ return ((float_t)lsb) * 0.488f;
+}
+
+float_t ais2ih_from_lsb_to_celsius(int16_t lsb)
+{
+ return (((float_t)lsb / 256.0f) + 25.0f);
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup AIS2IH_Data_Generation
+ * @brief This section groups all the functions concerning
+ * data generation
+ * @{
+ *
+ */
+
+/**
+ * @brief Select accelerometer operating modes.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of mode / lp_mode in reg CTRL1
+ * and low_noise in reg CTRL6
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_power_mode_set(stmdev_ctx_t *ctx, ais2ih_mode_t val)
+{
+ ais2ih_ctrl1_t ctrl1;
+ ais2ih_ctrl6_t ctrl6;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL1, (uint8_t *) &ctrl1, 1);
+
+ if (ret == 0)
+ {
+ ctrl1.mode = ((uint8_t) val & 0x0CU) >> 2;
+ ctrl1.lp_mode = (uint8_t) val & 0x03U ;
+ ret = ais2ih_write_reg(ctx, AIS2IH_CTRL1, (uint8_t *) &ctrl1, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL6, (uint8_t *) &ctrl6, 1);
+ }
+
+ if (ret == 0)
+ {
+ ctrl6.low_noise = ((uint8_t) val & 0x10U) >> 4;
+ ret = ais2ih_write_reg(ctx, AIS2IH_CTRL6, (uint8_t *) &ctrl6, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Select accelerometer operating modes.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of mode / lp_mode in reg CTRL1
+ * and low_noise in reg CTRL6
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_power_mode_get(stmdev_ctx_t *ctx, ais2ih_mode_t *val)
+{
+ ais2ih_ctrl1_t ctrl1;
+ ais2ih_ctrl6_t ctrl6;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL1, (uint8_t *) &ctrl1, 1);
+
+ if (ret == 0)
+ {
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL6, (uint8_t *) &ctrl6, 1);
+
+ switch (((ctrl6.low_noise << 4) + (ctrl1.mode << 2) +
+ ctrl1.lp_mode))
+ {
+ case AIS2IH_HIGH_PERFORMANCE:
+ *val = AIS2IH_HIGH_PERFORMANCE;
+ break;
+
+ case AIS2IH_CONT_LOW_PWR_4:
+ *val = AIS2IH_CONT_LOW_PWR_4;
+ break;
+
+ case AIS2IH_CONT_LOW_PWR_3:
+ *val = AIS2IH_CONT_LOW_PWR_3;
+ break;
+
+ case AIS2IH_CONT_LOW_PWR_2:
+ *val = AIS2IH_CONT_LOW_PWR_2;
+ break;
+
+ case AIS2IH_CONT_LOW_PWR_12bit:
+ *val = AIS2IH_CONT_LOW_PWR_12bit;
+ break;
+
+ case AIS2IH_SINGLE_LOW_PWR_4:
+ *val = AIS2IH_SINGLE_LOW_PWR_4;
+ break;
+
+ case AIS2IH_SINGLE_LOW_PWR_3:
+ *val = AIS2IH_SINGLE_LOW_PWR_3;
+ break;
+
+ case AIS2IH_SINGLE_LOW_PWR_2:
+ *val = AIS2IH_SINGLE_LOW_PWR_2;
+ break;
+
+ case AIS2IH_SINGLE_LOW_PWR_12bit:
+ *val = AIS2IH_SINGLE_LOW_PWR_12bit;
+ break;
+
+ case AIS2IH_HIGH_PERFORMANCE_LOW_NOISE:
+ *val = AIS2IH_HIGH_PERFORMANCE_LOW_NOISE;
+ break;
+
+ case AIS2IH_CONT_LOW_PWR_LOW_NOISE_4:
+ *val = AIS2IH_CONT_LOW_PWR_LOW_NOISE_4;
+ break;
+
+ case AIS2IH_CONT_LOW_PWR_LOW_NOISE_3:
+ *val = AIS2IH_CONT_LOW_PWR_LOW_NOISE_3;
+ break;
+
+ case AIS2IH_CONT_LOW_PWR_LOW_NOISE_2:
+ *val = AIS2IH_CONT_LOW_PWR_LOW_NOISE_2;
+ break;
+
+ case AIS2IH_CONT_LOW_PWR_LOW_NOISE_12bit:
+ *val = AIS2IH_CONT_LOW_PWR_LOW_NOISE_12bit;
+ break;
+
+ case AIS2IH_SINGLE_LOW_PWR_LOW_NOISE_4:
+ *val = AIS2IH_SINGLE_LOW_PWR_LOW_NOISE_4;
+ break;
+
+ case AIS2IH_SINGLE_LOW_PWR_LOW_NOISE_3:
+ *val = AIS2IH_SINGLE_LOW_PWR_LOW_NOISE_3;
+ break;
+
+ case AIS2IH_SINGLE_LOW_PWR_LOW_NOISE_2:
+ *val = AIS2IH_SINGLE_LOW_PWR_LOW_NOISE_2;
+ break;
+
+ case AIS2IH_SINGLE_LOW_LOW_NOISE_PWR_12bit:
+ *val = AIS2IH_SINGLE_LOW_LOW_NOISE_PWR_12bit;
+ break;
+
+ default:
+ *val = AIS2IH_HIGH_PERFORMANCE;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Accelerometer data rate selection.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of odr in reg CTRL1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_data_rate_set(stmdev_ctx_t *ctx, ais2ih_odr_t val)
+{
+ ais2ih_ctrl1_t ctrl1;
+ ais2ih_ctrl3_t ctrl3;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL1, (uint8_t *) &ctrl1, 1);
+
+ if (ret == 0)
+ {
+ ctrl1.odr = (uint8_t) val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_CTRL1, (uint8_t *) &ctrl1, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL3, (uint8_t *) &ctrl3, 1);
+ }
+
+ if (ret == 0)
+ {
+ ctrl3.slp_mode = ((uint8_t) val & 0x30U) >> 4;
+ ret = ais2ih_write_reg(ctx, AIS2IH_CTRL3, (uint8_t *) &ctrl3, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Accelerometer data rate selection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of odr in reg CTRL1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_data_rate_get(stmdev_ctx_t *ctx, ais2ih_odr_t *val)
+{
+ ais2ih_ctrl1_t ctrl1;
+ ais2ih_ctrl3_t ctrl3;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL1, (uint8_t *) &ctrl1, 1);
+
+ if (ret == 0)
+ {
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL3, (uint8_t *) &ctrl3, 1);
+
+ switch ((ctrl3.slp_mode << 4) + ctrl1.odr)
+ {
+ case AIS2IH_XL_ODR_OFF:
+ *val = AIS2IH_XL_ODR_OFF;
+ break;
+
+ case AIS2IH_XL_ODR_1Hz6_LP_ONLY:
+ *val = AIS2IH_XL_ODR_1Hz6_LP_ONLY;
+ break;
+
+ case AIS2IH_XL_ODR_12Hz5:
+ *val = AIS2IH_XL_ODR_12Hz5;
+ break;
+
+ case AIS2IH_XL_ODR_25Hz:
+ *val = AIS2IH_XL_ODR_25Hz;
+ break;
+
+ case AIS2IH_XL_ODR_50Hz:
+ *val = AIS2IH_XL_ODR_50Hz;
+ break;
+
+ case AIS2IH_XL_ODR_100Hz:
+ *val = AIS2IH_XL_ODR_100Hz;
+ break;
+
+ case AIS2IH_XL_ODR_200Hz:
+ *val = AIS2IH_XL_ODR_200Hz;
+ break;
+
+ case AIS2IH_XL_ODR_400Hz:
+ *val = AIS2IH_XL_ODR_400Hz;
+ break;
+
+ case AIS2IH_XL_ODR_800Hz:
+ *val = AIS2IH_XL_ODR_800Hz;
+ break;
+
+ case AIS2IH_XL_ODR_1k6Hz:
+ *val = AIS2IH_XL_ODR_1k6Hz;
+ break;
+
+ case AIS2IH_XL_SET_SW_TRIG:
+ *val = AIS2IH_XL_SET_SW_TRIG;
+ break;
+
+ case AIS2IH_XL_SET_PIN_TRIG:
+ *val = AIS2IH_XL_SET_PIN_TRIG;
+ break;
+
+ default:
+ *val = AIS2IH_XL_ODR_OFF;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Block data update.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of bdu in reg CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ ais2ih_ctrl2_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.bdu = val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Block data update.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of bdu in reg CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ ais2ih_ctrl2_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
+ *val = reg.bdu;
+
+ return ret;
+}
+
+/**
+ * @brief Accelerometer full-scale selection.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of fs in reg CTRL6
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_full_scale_set(stmdev_ctx_t *ctx, ais2ih_fs_t val)
+{
+ ais2ih_ctrl6_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL6, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.fs = (uint8_t) val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_CTRL6, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Accelerometer full-scale selection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of fs in reg CTRL6
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_full_scale_get(stmdev_ctx_t *ctx, ais2ih_fs_t *val)
+{
+ ais2ih_ctrl6_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL6, (uint8_t *) ®, 1);
+
+ switch (reg.fs)
+ {
+ case AIS2IH_2g:
+ *val = AIS2IH_2g;
+ break;
+
+ case AIS2IH_4g:
+ *val = AIS2IH_4g;
+ break;
+
+ case AIS2IH_8g:
+ *val = AIS2IH_8g;
+ break;
+
+ case AIS2IH_16g:
+ *val = AIS2IH_16g;
+ break;
+
+ default:
+ *val = AIS2IH_2g;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief The STATUS_REG register of the device.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val union of registers from STATUS to
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_status_reg_get(stmdev_ctx_t *ctx, ais2ih_status_t *val)
+{
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_STATUS, (uint8_t *) val, 1);
+
+ return ret;
+}
+
+/**
+ * @brief Accelerometer new data available.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of drdy in reg STATUS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ ais2ih_status_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_STATUS, (uint8_t *) ®, 1);
+ *val = reg.drdy;
+
+ return ret;
+}
+/**
+ * @brief Read all the interrupt/status flag of the device.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val registers STATUS_DUP, WAKE_UP_SRC,
+ * TAP_SRC, SIXD_SRC, ALL_INT_SRC
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_all_sources_get(stmdev_ctx_t *ctx,
+ ais2ih_all_sources_t *val)
+{
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_STATUS_DUP, (uint8_t *) val, 5);
+
+ return ret;
+}
+
+/**
+ * @brief Accelerometer X-axis user offset correction expressed in two’s
+ * complement, weight depends on bit USR_OFF_W. The value must be
+ * in the range [-127 127].[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
+{
+ int32_t ret;
+
+ ret = ais2ih_write_reg(ctx, AIS2IH_X_OFS_USR, buff, 1);
+
+ return ret;
+}
+
+/**
+ * @brief Accelerometer X-axis user offset correction expressed in two’s
+ * complement, weight depends on bit USR_OFF_W. The value must be
+ * in the range [-127 127].[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
+{
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_X_OFS_USR, buff, 1);
+
+ return ret;
+}
+
+/**
+ * @brief Accelerometer Y-axis user offset correction expressed in two’s
+ * complement, weight depends on bit USR_OFF_W. The value must be
+ * in the range [-127 127].[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
+{
+ int32_t ret;
+
+ ret = ais2ih_write_reg(ctx, AIS2IH_Y_OFS_USR, buff, 1);
+
+ return ret;
+}
+
+/**
+ * @brief Accelerometer Y-axis user offset correction expressed in two’s
+ * complement, weight depends on bit USR_OFF_W. The value must be
+ * in the range [-127 127].[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
+{
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_Y_OFS_USR, buff, 1);
+
+ return ret;
+}
+
+/**
+ * @brief Accelerometer Z-axis user offset correction expressed in two’s
+ * complement, weight depends on bit USR_OFF_W. The value must be
+ * in the range [-127 127].[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
+{
+ int32_t ret;
+
+ ret = ais2ih_write_reg(ctx, AIS2IH_Z_OFS_USR, buff, 1);
+
+ return ret;
+}
+
+/**
+ * @brief Accelerometer Z-axis user offset correction expressed in two’s
+ * complement, weight depends on bit USR_OFF_W. The value must be
+ * in the range [-127 127].[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff)
+{
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_Z_OFS_USR, buff, 1);
+
+ return ret;
+}
+
+/**
+ * @brief Weight of XL user offset bits of registers X_OFS_USR,
+ * Y_OFS_USR, Z_OFS_USR.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of usr_off_w in
+ * reg CTRL_REG7
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_offset_weight_set(stmdev_ctx_t *ctx,
+ ais2ih_usr_off_w_t val)
+{
+ ais2ih_ctrl_reg7_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.usr_off_w = (uint8_t) val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Weight of XL user offset bits of registers X_OFS_USR,
+ * Y_OFS_USR, Z_OFS_USR.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of usr_off_w in reg CTRL_REG7
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_offset_weight_get(stmdev_ctx_t *ctx,
+ ais2ih_usr_off_w_t *val)
+{
+ ais2ih_ctrl_reg7_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
+
+ switch (reg.usr_off_w)
+ {
+ case AIS2IH_LSb_977ug:
+ *val = AIS2IH_LSb_977ug;
+ break;
+
+ case AIS2IH_LSb_15mg6:
+ *val = AIS2IH_LSb_15mg6;
+ break;
+
+ default:
+ *val = AIS2IH_LSb_977ug;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup AIS2IH_Data_Output
+ * @brief This section groups all the data output functions.
+ * @{
+ *
+ */
+
+/**
+ * @brief Temperature data output register (r). L and H registers
+ * together express a 16-bit word in two’s complement.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
+{
+ uint8_t buff[2];
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_OUT_T_L, buff, 2);
+ *val = (int16_t)buff[1];
+ *val = (*val * 256) + (int16_t)buff[0];
+
+ return ret;
+}
+
+/**
+ * @brief Linear acceleration output register. The value is expressed as
+ * a 16-bit word in two’s complement.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
+{
+ uint8_t buff[6];
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_OUT_X_L, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup AIS2IH_Common
+ * @brief This section groups common useful functions.
+ * @{
+ *
+ */
+
+/**
+ * @brief Device Who am I.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
+{
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_WHO_AM_I, buff, 1);
+
+ return ret;
+}
+
+/**
+ * @brief Register address automatically incremented during multiple byte
+ * access with a serial interface.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of if_add_inc in reg CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ ais2ih_ctrl2_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.if_add_inc = val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Register address automatically incremented during multiple
+ * byte access with a serial interface.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of if_add_inc in reg CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ ais2ih_ctrl2_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
+ *val = reg.if_add_inc;
+
+ return ret;
+}
+
+/**
+ * @brief Software reset. Restore the default values in user registers.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of soft_reset in reg CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_reset_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ ais2ih_ctrl2_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.soft_reset = val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Software reset. Restore the default values in user registers.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of soft_reset in reg CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ ais2ih_ctrl2_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
+ *val = reg.soft_reset;
+
+ return ret;
+}
+
+/**
+ * @brief Reboot memory content. Reload the calibration parameters.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of boot in reg CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_boot_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ ais2ih_ctrl2_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.boot = val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Reboot memory content. Reload the calibration parameters.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of boot in reg CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ ais2ih_ctrl2_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
+ *val = reg.boot;
+
+ return ret;
+}
+
+/**
+ * @brief Sensor self-test enable.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of st in reg CTRL3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_self_test_set(stmdev_ctx_t *ctx, ais2ih_st_t val)
+{
+ ais2ih_ctrl3_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL3, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.st = (uint8_t) val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_CTRL3, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Sensor self-test enable.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of st in reg CTRL3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_self_test_get(stmdev_ctx_t *ctx, ais2ih_st_t *val)
+{
+ ais2ih_ctrl3_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL3, (uint8_t *) ®, 1);
+
+ switch (reg.st)
+ {
+ case AIS2IH_XL_ST_DISABLE:
+ *val = AIS2IH_XL_ST_DISABLE;
+ break;
+
+ case AIS2IH_XL_ST_POSITIVE:
+ *val = AIS2IH_XL_ST_POSITIVE;
+ break;
+
+ case AIS2IH_XL_ST_NEGATIVE:
+ *val = AIS2IH_XL_ST_NEGATIVE;
+ break;
+
+ default:
+ *val = AIS2IH_XL_ST_DISABLE;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Data-ready pulsed / letched mode.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of drdy_pulsed in reg CTRL_REG7
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_data_ready_mode_set(stmdev_ctx_t *ctx,
+ ais2ih_drdy_pulsed_t val)
+{
+ ais2ih_ctrl_reg7_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.drdy_pulsed = (uint8_t) val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Data-ready pulsed / letched mode.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of drdy_pulsed in reg CTRL_REG7
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_data_ready_mode_get(stmdev_ctx_t *ctx,
+ ais2ih_drdy_pulsed_t *val)
+{
+ ais2ih_ctrl_reg7_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
+
+ switch (reg.drdy_pulsed)
+ {
+ case AIS2IH_DRDY_LATCHED:
+ *val = AIS2IH_DRDY_LATCHED;
+ break;
+
+ case AIS2IH_DRDY_PULSED:
+ *val = AIS2IH_DRDY_PULSED;
+ break;
+
+ default:
+ *val = AIS2IH_DRDY_LATCHED;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup AIS2IH_Filters
+ * @brief This section group all the functions concerning the filters
+ * configuration.
+ * @{
+ *
+ */
+
+/**
+ * @brief Accelerometer filtering path for outputs.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of fds in reg CTRL6
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_filter_path_set(stmdev_ctx_t *ctx, ais2ih_fds_t val)
+{
+ ais2ih_ctrl6_t ctrl6;
+ ais2ih_ctrl_reg7_t ctrl_reg7;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL6, (uint8_t *) &ctrl6, 1);
+
+ if (ret == 0)
+ {
+ ctrl6.fds = ((uint8_t) val & 0x10U) >> 4;
+ ret = ais2ih_write_reg(ctx, AIS2IH_CTRL6, (uint8_t *) &ctrl6, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) &ctrl_reg7, 1);
+ }
+
+ if (ret == 0)
+ {
+ ctrl_reg7.usr_off_on_out = (uint8_t) val & 0x01U;
+ ret = ais2ih_write_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) &ctrl_reg7, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Accelerometer filtering path for outputs.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of fds in reg CTRL6
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_filter_path_get(stmdev_ctx_t *ctx, ais2ih_fds_t *val)
+{
+ ais2ih_ctrl6_t ctrl6;
+ ais2ih_ctrl_reg7_t ctrl_reg7;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL6, (uint8_t *) &ctrl6, 1);
+
+ if (ret == 0)
+ {
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) &ctrl_reg7, 1);
+
+ switch ((ctrl6.fds << 4) + ctrl_reg7.usr_off_on_out)
+ {
+ case AIS2IH_LPF_ON_OUT:
+ *val = AIS2IH_LPF_ON_OUT;
+ break;
+
+ case AIS2IH_USER_OFFSET_ON_OUT:
+ *val = AIS2IH_USER_OFFSET_ON_OUT;
+ break;
+
+ case AIS2IH_HIGH_PASS_ON_OUT:
+ *val = AIS2IH_HIGH_PASS_ON_OUT;
+ break;
+
+ default:
+ *val = AIS2IH_LPF_ON_OUT;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Accelerometer cutoff filter frequency. Valid for low and high
+ * pass filter.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of bw_filt in reg CTRL6
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_filter_bandwidth_set(stmdev_ctx_t *ctx,
+ ais2ih_bw_filt_t val)
+{
+ ais2ih_ctrl6_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL6, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.bw_filt = (uint8_t) val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_CTRL6, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Accelerometer cutoff filter frequency. Valid for low and
+ * high pass filter.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of bw_filt in reg CTRL6
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_filter_bandwidth_get(stmdev_ctx_t *ctx,
+ ais2ih_bw_filt_t *val)
+{
+ ais2ih_ctrl6_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL6, (uint8_t *) ®, 1);
+
+ switch (reg.bw_filt)
+ {
+ case AIS2IH_ODR_DIV_2:
+ *val = AIS2IH_ODR_DIV_2;
+ break;
+
+ case AIS2IH_ODR_DIV_4:
+ *val = AIS2IH_ODR_DIV_4;
+ break;
+
+ case AIS2IH_ODR_DIV_10:
+ *val = AIS2IH_ODR_DIV_10;
+ break;
+
+ case AIS2IH_ODR_DIV_20:
+ *val = AIS2IH_ODR_DIV_20;
+ break;
+
+ default:
+ *val = AIS2IH_ODR_DIV_2;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable HP filter reference mode.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of hp_ref_mode in reg CTRL_REG7
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ ais2ih_ctrl_reg7_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.hp_ref_mode = val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable HP filter reference mode.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of hp_ref_mode in reg CTRL_REG7
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ ais2ih_ctrl_reg7_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
+ *val = reg.hp_ref_mode;
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup AIS2IH_Serial_Interface
+ * @brief This section groups all the functions concerning main serial
+ * interface management (not auxiliary)
+ * @{
+ *
+ */
+
+/**
+ * @brief SPI Serial Interface Mode selection.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of sim in reg CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_spi_mode_set(stmdev_ctx_t *ctx, ais2ih_sim_t val)
+{
+ ais2ih_ctrl2_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.sim = (uint8_t) val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief SPI Serial Interface Mode selection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of sim in reg CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_spi_mode_get(stmdev_ctx_t *ctx, ais2ih_sim_t *val)
+{
+ ais2ih_ctrl2_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
+
+ switch (reg.sim)
+ {
+ case AIS2IH_SPI_4_WIRE:
+ *val = AIS2IH_SPI_4_WIRE;
+ break;
+
+ case AIS2IH_SPI_3_WIRE:
+ *val = AIS2IH_SPI_3_WIRE;
+ break;
+
+ default:
+ *val = AIS2IH_SPI_4_WIRE;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Disable / Enable I2C interface.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of i2c_disable in
+ * reg CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_i2c_interface_set(stmdev_ctx_t *ctx,
+ ais2ih_i2c_disable_t val)
+{
+ ais2ih_ctrl2_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.i2c_disable = (uint8_t) val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Disable / Enable I2C interface.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of i2c_disable in reg CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_i2c_interface_get(stmdev_ctx_t *ctx,
+ ais2ih_i2c_disable_t *val)
+{
+ ais2ih_ctrl2_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
+
+ switch (reg.i2c_disable)
+ {
+ case AIS2IH_I2C_ENABLE:
+ *val = AIS2IH_I2C_ENABLE;
+ break;
+
+ case AIS2IH_I2C_DISABLE:
+ *val = AIS2IH_I2C_DISABLE;
+ break;
+
+ default:
+ *val = AIS2IH_I2C_ENABLE;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Disconnect CS pull-up.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of cs_pu_disc in reg CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_cs_mode_set(stmdev_ctx_t *ctx, ais2ih_cs_pu_disc_t val)
+{
+ ais2ih_ctrl2_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.cs_pu_disc = (uint8_t) val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Disconnect CS pull-up.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of cs_pu_disc in reg CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_cs_mode_get(stmdev_ctx_t *ctx,
+ ais2ih_cs_pu_disc_t *val)
+{
+ ais2ih_ctrl2_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1);
+
+ switch (reg.cs_pu_disc)
+ {
+ case AIS2IH_PULL_UP_CONNECT:
+ *val = AIS2IH_PULL_UP_CONNECT;
+ break;
+
+ case AIS2IH_PULL_UP_DISCONNECT:
+ *val = AIS2IH_PULL_UP_DISCONNECT;
+ break;
+
+ default:
+ *val = AIS2IH_PULL_UP_CONNECT;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup AIS2IH_Interrupt_Pins
+ * @brief This section groups all the functions that manage interrupt pins
+ * @{
+ *
+ */
+
+/**
+ * @brief Interrupt active-high/low.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of h_lactive in reg CTRL3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_pin_polarity_set(stmdev_ctx_t *ctx,
+ ais2ih_h_lactive_t val)
+{
+ ais2ih_ctrl3_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL3, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.h_lactive = (uint8_t) val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_CTRL3, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Interrupt active-high/low.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of h_lactive in reg CTRL3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_pin_polarity_get(stmdev_ctx_t *ctx,
+ ais2ih_h_lactive_t *val)
+{
+ ais2ih_ctrl3_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL3, (uint8_t *) ®, 1);
+
+ switch (reg.h_lactive)
+ {
+ case AIS2IH_ACTIVE_HIGH:
+ *val = AIS2IH_ACTIVE_HIGH;
+ break;
+
+ case AIS2IH_ACTIVE_LOW:
+ *val = AIS2IH_ACTIVE_LOW;
+ break;
+
+ default:
+ *val = AIS2IH_ACTIVE_HIGH;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Latched/pulsed interrupt.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of lir in reg CTRL3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_int_notification_set(stmdev_ctx_t *ctx,
+ ais2ih_lir_t val)
+{
+ ais2ih_ctrl3_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL3, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.lir = (uint8_t) val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_CTRL3, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Latched/pulsed interrupt.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of lir in reg CTRL3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_int_notification_get(stmdev_ctx_t *ctx,
+ ais2ih_lir_t *val)
+{
+ ais2ih_ctrl3_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL3, (uint8_t *) ®, 1);
+
+ switch (reg.lir)
+ {
+ case AIS2IH_INT_PULSED:
+ *val = AIS2IH_INT_PULSED;
+ break;
+
+ case AIS2IH_INT_LATCHED:
+ *val = AIS2IH_INT_LATCHED;
+ break;
+
+ default:
+ *val = AIS2IH_INT_PULSED;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Push-pull/open drain selection on interrupt pads.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of pp_od in reg CTRL3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_pin_mode_set(stmdev_ctx_t *ctx, ais2ih_pp_od_t val)
+{
+ ais2ih_ctrl3_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL3, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.pp_od = (uint8_t) val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_CTRL3, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Push-pull/open drain selection on interrupt pads.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of pp_od in reg CTRL3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_pin_mode_get(stmdev_ctx_t *ctx, ais2ih_pp_od_t *val)
+{
+ ais2ih_ctrl3_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL3, (uint8_t *) ®, 1);
+
+ switch (reg.pp_od)
+ {
+ case AIS2IH_PUSH_PULL:
+ *val = AIS2IH_PUSH_PULL;
+ break;
+
+ case AIS2IH_OPEN_DRAIN:
+ *val = AIS2IH_OPEN_DRAIN;
+ break;
+
+ default:
+ *val = AIS2IH_PUSH_PULL;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Select the signal that need to route on int1 pad.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val register CTRL4_INT1_PAD_CTRL.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_pin_int1_route_set(stmdev_ctx_t *ctx,
+ ais2ih_ctrl4_int1_pad_ctrl_t *val)
+{
+ ais2ih_ctrl5_int2_pad_ctrl_t ctrl5_int2_pad_ctrl;
+ ais2ih_ctrl_reg7_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL5_INT2_PAD_CTRL,
+ (uint8_t *)&ctrl5_int2_pad_ctrl, 1);
+
+ if (ret == 0)
+ {
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
+ }
+
+ if (ret == 0)
+ {
+ if ((val->int1_tap |
+ val->int1_ff |
+ val->int1_wu |
+ val->int1_single_tap |
+ val->int1_6d |
+ ctrl5_int2_pad_ctrl.int2_sleep_state |
+ ctrl5_int2_pad_ctrl.int2_sleep_chg) != PROPERTY_DISABLE)
+ {
+ reg.interrupts_enable = PROPERTY_ENABLE;
+ }
+
+ else
+ {
+ reg.interrupts_enable = PROPERTY_DISABLE;
+ }
+
+ ret = ais2ih_write_reg(ctx, AIS2IH_CTRL4_INT1_PAD_CTRL,
+ (uint8_t *) val, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = ais2ih_write_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Select the signal that need to route on int1 pad.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val register CTRL4_INT1_PAD_CTRL.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_pin_int1_route_get(stmdev_ctx_t *ctx,
+ ais2ih_ctrl4_int1_pad_ctrl_t *val)
+{
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL4_INT1_PAD_CTRL,
+ (uint8_t *) val, 1);
+
+ return ret;
+}
+
+/**
+ * @brief Select the signal that need to route on int2 pad.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val register CTRL5_INT2_PAD_CTRL.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_pin_int2_route_set(stmdev_ctx_t *ctx,
+ ais2ih_ctrl5_int2_pad_ctrl_t *val)
+{
+ ais2ih_ctrl4_int1_pad_ctrl_t ctrl4_int1_pad_ctrl;
+ ais2ih_ctrl_reg7_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL4_INT1_PAD_CTRL,
+ (uint8_t *) &ctrl4_int1_pad_ctrl, 1);
+
+ if (ret == 0)
+ {
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
+ }
+
+ if (ret == 0)
+ {
+ if ((ctrl4_int1_pad_ctrl.int1_tap |
+ ctrl4_int1_pad_ctrl.int1_ff |
+ ctrl4_int1_pad_ctrl.int1_wu |
+ ctrl4_int1_pad_ctrl.int1_single_tap |
+ ctrl4_int1_pad_ctrl.int1_6d |
+ val->int2_sleep_state | val->int2_sleep_chg) != PROPERTY_DISABLE)
+ {
+ reg.interrupts_enable = PROPERTY_ENABLE;
+ }
+
+ else
+ {
+ reg.interrupts_enable = PROPERTY_DISABLE;
+ }
+
+ ret = ais2ih_write_reg(ctx, AIS2IH_CTRL5_INT2_PAD_CTRL,
+ (uint8_t *) val, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = ais2ih_write_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Select the signal that need to route on int2 pad.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val register CTRL5_INT2_PAD_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_pin_int2_route_get(stmdev_ctx_t *ctx,
+ ais2ih_ctrl5_int2_pad_ctrl_t *val)
+{
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL5_INT2_PAD_CTRL,
+ (uint8_t *) val, 1);
+
+ return ret;
+}
+/**
+ * @brief All interrupt signals become available on INT1 pin.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of int2_on_int1 in reg CTRL_REG7
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ ais2ih_ctrl_reg7_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.int2_on_int1 = val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief All interrupt signals become available on INT1 pin.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of int2_on_int1 in reg CTRL_REG7
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ ais2ih_ctrl_reg7_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
+ *val = reg.int2_on_int1;
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup AIS2IH_Wake_Up_Event
+ * @brief This section groups all the functions that manage the Wake
+ * Up event generation.
+ * @{
+ *
+ */
+
+/**
+ * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of wk_ths in reg WAKE_UP_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ ais2ih_wake_up_ths_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_THS, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.wk_ths = val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_WAKE_UP_THS, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of wk_ths in reg WAKE_UP_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ ais2ih_wake_up_ths_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_THS, (uint8_t *) ®, 1);
+ *val = reg.wk_ths;
+
+ return ret;
+}
+
+/**
+ * @brief Wake up duration event.1LSb = 1 / ODR.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of wake_dur in reg WAKE_UP_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ ais2ih_wake_up_dur_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_DUR, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.wake_dur = val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_WAKE_UP_DUR, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Wake up duration event.1LSb = 1 / ODR.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of wake_dur in reg WAKE_UP_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ ais2ih_wake_up_dur_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_DUR, (uint8_t *) ®, 1);
+ *val = reg.wake_dur;
+
+ return ret;
+}
+
+/**
+ * @brief Data sent to wake-up interrupt function.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of usr_off_on_wu in reg CTRL_REG7
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_wkup_feed_data_set(stmdev_ctx_t *ctx,
+ ais2ih_usr_off_on_wu_t val)
+{
+ ais2ih_ctrl_reg7_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.usr_off_on_wu = (uint8_t) val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Data sent to wake-up interrupt function.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of usr_off_on_wu in reg CTRL_REG7
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_wkup_feed_data_get(stmdev_ctx_t *ctx,
+ ais2ih_usr_off_on_wu_t *val)
+{
+ ais2ih_ctrl_reg7_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
+
+ switch (reg.usr_off_on_wu)
+ {
+ case AIS2IH_HP_FEED:
+ *val = AIS2IH_HP_FEED;
+ break;
+
+ case AIS2IH_USER_OFFSET_FEED:
+ *val = AIS2IH_USER_OFFSET_FEED;
+ break;
+
+ default:
+ *val = AIS2IH_HP_FEED;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup AIS2IH_Activity/Inactivity_Detection
+ * @brief This section groups all the functions concerning
+ * activity/inactivity detection.
+ * @{
+ *
+ */
+
+/**
+ * @brief Config activity / inactivity or
+ * stationary / motion detection.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of sleep_on / stationary in
+ * reg WAKE_UP_THS / WAKE_UP_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_act_mode_set(stmdev_ctx_t *ctx, ais2ih_sleep_on_t val)
+{
+ ais2ih_wake_up_ths_t wake_up_ths;
+ ais2ih_wake_up_dur_t wake_up_dur;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_THS,
+ (uint8_t *) &wake_up_ths, 1);
+
+ if (ret == 0)
+ {
+ ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_DUR,
+ (uint8_t *) &wake_up_dur, 1);
+ }
+
+ if (ret == 0)
+ {
+ wake_up_ths.sleep_on = (uint8_t) val & 0x01U;
+ ret = ais2ih_write_reg(ctx, AIS2IH_WAKE_UP_THS,
+ (uint8_t *) &wake_up_ths, 1);
+ }
+
+ if (ret == 0)
+ {
+ wake_up_dur.stationary = ((uint8_t)val & 0x02U) >> 1;
+ ret = ais2ih_write_reg(ctx, AIS2IH_WAKE_UP_DUR,
+ (uint8_t *) &wake_up_dur, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Config activity / inactivity or
+ * stationary / motion detection. [get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of sleep_on in reg WAKE_UP_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_act_mode_get(stmdev_ctx_t *ctx, ais2ih_sleep_on_t *val)
+{
+ ais2ih_wake_up_ths_t wake_up_ths;
+ ais2ih_wake_up_dur_t wake_up_dur;;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_THS,
+ (uint8_t *) &wake_up_ths, 1);
+
+ if (ret == 0)
+ {
+ ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_DUR,
+ (uint8_t *) &wake_up_dur, 1);
+
+ switch ((wake_up_dur.stationary << 1) + wake_up_ths.sleep_on)
+ {
+ case AIS2IH_NO_DETECTION:
+ *val = AIS2IH_NO_DETECTION;
+ break;
+
+ case AIS2IH_DETECT_ACT_INACT:
+ *val = AIS2IH_DETECT_ACT_INACT;
+ break;
+
+ case AIS2IH_DETECT_STAT_MOTION:
+ *val = AIS2IH_DETECT_STAT_MOTION;
+ break;
+
+ default:
+ *val = AIS2IH_NO_DETECTION;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of sleep_dur in reg WAKE_UP_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ ais2ih_wake_up_dur_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_DUR, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.sleep_dur = val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_WAKE_UP_DUR, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of sleep_dur in reg WAKE_UP_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ ais2ih_wake_up_dur_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_DUR, (uint8_t *) ®, 1);
+ *val = reg.sleep_dur;
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup AIS2IH_Tap_Generator
+ * @brief This section groups all the functions that manage the tap
+ * and double tap event generation.
+ * @{
+ *
+ */
+
+/**
+ * @brief Threshold for tap recognition.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of tap_thsx in reg TAP_THS_X
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ ais2ih_tap_ths_x_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_X, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.tap_thsx = val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_TAP_THS_X, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Threshold for tap recognition.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of tap_thsx in reg TAP_THS_X
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ ais2ih_tap_ths_x_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_X, (uint8_t *) ®, 1);
+ *val = reg.tap_thsx;
+
+ return ret;
+}
+
+/**
+ * @brief Threshold for tap recognition.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of tap_thsy in reg TAP_THS_Y
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ ais2ih_tap_ths_y_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_Y, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.tap_thsy = val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_TAP_THS_Y, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Threshold for tap recognition.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of tap_thsy in reg TAP_THS_Y
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ ais2ih_tap_ths_y_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_Y, (uint8_t *) ®, 1);
+ *val = reg.tap_thsy;
+
+ return ret;
+}
+
+/**
+ * @brief Selection of axis priority for TAP detection.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of tap_prior in reg TAP_THS_Y
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_tap_axis_priority_set(stmdev_ctx_t *ctx,
+ ais2ih_tap_prior_t val)
+{
+ ais2ih_tap_ths_y_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_Y, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.tap_prior = (uint8_t) val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_TAP_THS_Y, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Selection of axis priority for TAP detection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of tap_prior in reg TAP_THS_Y
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_tap_axis_priority_get(stmdev_ctx_t *ctx,
+ ais2ih_tap_prior_t *val)
+{
+ ais2ih_tap_ths_y_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_Y, (uint8_t *) ®, 1);
+
+ switch (reg.tap_prior)
+ {
+ case AIS2IH_XYZ:
+ *val = AIS2IH_XYZ;
+ break;
+
+ case AIS2IH_YXZ:
+ *val = AIS2IH_YXZ;
+ break;
+
+ case AIS2IH_XZY:
+ *val = AIS2IH_XZY;
+ break;
+
+ case AIS2IH_ZYX:
+ *val = AIS2IH_ZYX;
+ break;
+
+ case AIS2IH_YZX:
+ *val = AIS2IH_YZX;
+ break;
+
+ case AIS2IH_ZXY:
+ *val = AIS2IH_ZXY;
+ break;
+
+ default:
+ *val = AIS2IH_XYZ;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Threshold for tap recognition.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of tap_thsz in reg TAP_THS_Z
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ ais2ih_tap_ths_z_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_Z, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.tap_thsz = val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_TAP_THS_Z, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Threshold for tap recognition.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of tap_thsz in reg TAP_THS_Z
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ ais2ih_tap_ths_z_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_Z, (uint8_t *) ®, 1);
+ *val = reg.tap_thsz;
+
+ return ret;
+}
+
+/**
+ * @brief Enable Z direction in tap recognition.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of tap_z_en in reg TAP_THS_Z
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ ais2ih_tap_ths_z_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_Z, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.tap_z_en = val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_TAP_THS_Z, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable Z direction in tap recognition.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of tap_z_en in reg TAP_THS_Z
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ ais2ih_tap_ths_z_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_Z, (uint8_t *) ®, 1);
+ *val = reg.tap_z_en;
+
+ return ret;
+}
+
+/**
+ * @brief Enable Y direction in tap recognition.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of tap_y_en in reg TAP_THS_Z
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ ais2ih_tap_ths_z_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_Z, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.tap_y_en = val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_TAP_THS_Z, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable Y direction in tap recognition.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of tap_y_en in reg TAP_THS_Z
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ ais2ih_tap_ths_z_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_Z, (uint8_t *) ®, 1);
+ *val = reg.tap_y_en;
+
+ return ret;
+}
+
+/**
+ * @brief Enable X direction in tap recognition.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of tap_x_en in reg TAP_THS_Z
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ ais2ih_tap_ths_z_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_Z, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.tap_x_en = val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_TAP_THS_Z, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable X direction in tap recognition.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of tap_x_en in reg TAP_THS_Z
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ ais2ih_tap_ths_z_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_Z, (uint8_t *) ®, 1);
+ *val = reg.tap_x_en;
+
+ return ret;
+}
+
+/**
+ * @brief Maximum duration is the maximum time of an overthreshold signal
+ * detection to be recognized as a tap event. The default value
+ * of these bits is 00b which corresponds to 4*ODR_XL time.
+ * If the SHOCK[1:0] bits are set to a different value, 1LSB
+ * corresponds to 8*ODR_XL time.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of shock in reg INT_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ ais2ih_int_dur_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_INT_DUR, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.shock = val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_INT_DUR, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Maximum duration is the maximum time of an overthreshold signal
+ * detection to be recognized as a tap event. The default value
+ * of these bits is 00b which corresponds to 4*ODR_XL time.
+ * If the SHOCK[1:0] bits are set to a different value, 1LSB
+ * corresponds to 8*ODR_XL time.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of shock in reg INT_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ ais2ih_int_dur_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_INT_DUR, (uint8_t *) ®, 1);
+ *val = reg.shock;
+
+ return ret;
+}
+
+/**
+ * @brief Quiet time is the time after the first detected tap in which
+ * there must not be any overthreshold event.
+ * The default value of these bits is 00b which corresponds
+ * to 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
+ * value, 1LSB corresponds to 4*ODR_XL time.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of quiet in reg INT_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ ais2ih_int_dur_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_INT_DUR, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.quiet = val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_INT_DUR, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Quiet time is the time after the first detected tap in which
+ * there must not be any overthreshold event.
+ * The default value of these bits is 00b which corresponds
+ * to 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
+ * value, 1LSB corresponds to 4*ODR_XL time.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of quiet in reg INT_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ ais2ih_int_dur_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_INT_DUR, (uint8_t *) ®, 1);
+ *val = reg.quiet;
+
+ return ret;
+}
+
+/**
+ * @brief When double tap recognition is enabled, this register expresses
+ * the maximum time between two consecutive detected taps to
+ * determine a double tap event.
+ * The default value of these bits is 0000b which corresponds
+ * to 16*ODR_XL time. If the DUR[3:0] bits are set to a different
+ * value, 1LSB corresponds to 32*ODR_XL time.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of latency in reg INT_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ ais2ih_int_dur_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_INT_DUR, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.latency = val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_INT_DUR, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief When double tap recognition is enabled, this register expresses
+ * the maximum time between two consecutive detected taps to
+ * determine a double tap event.
+ * The default value of these bits is 0000b which corresponds
+ * to 16*ODR_XL time. If the DUR[3:0] bits are set to a different
+ * value, 1LSB corresponds to 32*ODR_XL time.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of latency in reg INT_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ ais2ih_int_dur_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_INT_DUR, (uint8_t *) ®, 1);
+ *val = reg.latency;
+
+ return ret;
+}
+
+/**
+ * @brief Single/double-tap event enable.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of single_double_tap in reg WAKE_UP_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_tap_mode_set(stmdev_ctx_t *ctx,
+ ais2ih_single_double_tap_t val)
+{
+ ais2ih_wake_up_ths_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_THS, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.single_double_tap = (uint8_t) val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_WAKE_UP_THS, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Single/double-tap event enable.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of single_double_tap in reg WAKE_UP_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_tap_mode_get(stmdev_ctx_t *ctx,
+ ais2ih_single_double_tap_t *val)
+{
+ ais2ih_wake_up_ths_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_THS, (uint8_t *) ®, 1);
+
+ switch (reg.single_double_tap)
+ {
+ case AIS2IH_ONLY_SINGLE:
+ *val = AIS2IH_ONLY_SINGLE;
+ break;
+
+ case AIS2IH_BOTH_SINGLE_DOUBLE:
+ *val = AIS2IH_BOTH_SINGLE_DOUBLE;
+ break;
+
+ default:
+ *val = AIS2IH_ONLY_SINGLE;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Read the tap / double tap source register.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param ais2ih_tap_src: union of registers from TAP_SRC to
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_tap_src_get(stmdev_ctx_t *ctx, ais2ih_tap_src_t *val)
+{
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_TAP_SRC, (uint8_t *) val, 1);
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup AIS2IH_Six_Position_Detection(6D/4D)
+ * @brief This section groups all the functions concerning six
+ * position detection (6D).
+ * @{
+ *
+ */
+
+/**
+ * @brief Threshold for 4D/6D function.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of 6d_ths in reg TAP_THS_X
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_6d_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ ais2ih_tap_ths_x_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_X, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg._6d_ths = val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_TAP_THS_X, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Threshold for 4D/6D function.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of 6d_ths in reg TAP_THS_X
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ ais2ih_tap_ths_x_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_X, (uint8_t *) ®, 1);
+ *val = reg._6d_ths;
+
+ return ret;
+}
+
+/**
+ * @brief 4D orientation detection enable.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of 4d_en in reg TAP_THS_X
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ ais2ih_tap_ths_x_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_X, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg._4d_en = val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_TAP_THS_X, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief 4D orientation detection enable.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of 4d_en in reg TAP_THS_X
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ ais2ih_tap_ths_x_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_X, (uint8_t *) ®, 1);
+ *val = reg._4d_en;
+
+ return ret;
+}
+
+/**
+ * @brief Read the 6D tap source register.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val union of registers from SIXD_SRC
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_6d_src_get(stmdev_ctx_t *ctx, ais2ih_sixd_src_t *val)
+{
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_SIXD_SRC, (uint8_t *) val, 1);
+
+ return ret;
+}
+/**
+ * @brief Data sent to 6D interrupt function.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of lpass_on6d in reg CTRL_REG7
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_6d_feed_data_set(stmdev_ctx_t *ctx,
+ ais2ih_lpass_on6d_t val)
+{
+ ais2ih_ctrl_reg7_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.lpass_on6d = (uint8_t) val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Data sent to 6D interrupt function.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of lpass_on6d in reg CTRL_REG7
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_6d_feed_data_get(stmdev_ctx_t *ctx,
+ ais2ih_lpass_on6d_t *val)
+{
+ ais2ih_ctrl_reg7_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1);
+
+ switch (reg.lpass_on6d)
+ {
+ case AIS2IH_ODR_DIV_2_FEED:
+ *val = AIS2IH_ODR_DIV_2_FEED;
+ break;
+
+ case AIS2IH_LPF2_FEED:
+ *val = AIS2IH_LPF2_FEED;
+ break;
+
+ default:
+ *val = AIS2IH_ODR_DIV_2_FEED;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup AIS2IH_Free_Fall
+ * @brief This section group all the functions concerning
+ * the free fall detection.
+ * @{
+ *
+ */
+
+/**
+ * @brief Wake up duration event(1LSb = 1 / ODR).[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of ff_dur in reg
+ * WAKE_UP_DUR /F REE_FALL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ ais2ih_wake_up_dur_t wake_up_dur;
+ ais2ih_free_fall_t free_fall;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_DUR,
+ (uint8_t *) &wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ ret = ais2ih_read_reg(ctx, AIS2IH_FREE_FALL, (uint8_t *) &free_fall, 1);
+ }
+
+ if (ret == 0)
+ {
+ wake_up_dur.ff_dur = ((uint8_t) val & 0x20U) >> 5;
+ free_fall.ff_dur = (uint8_t) val & 0x1FU;
+ ret = ais2ih_write_reg(ctx, AIS2IH_WAKE_UP_DUR,
+ (uint8_t *) &wake_up_dur, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = ais2ih_write_reg(ctx, AIS2IH_FREE_FALL, (uint8_t *) &free_fall, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Wake up duration event(1LSb = 1 / ODR).[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of ff_dur in
+ * reg WAKE_UP_DUR /F REE_FALL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ ais2ih_wake_up_dur_t wake_up_dur;
+ ais2ih_free_fall_t free_fall;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_DUR,
+ (uint8_t *) &wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ ret = ais2ih_read_reg(ctx, AIS2IH_FREE_FALL, (uint8_t *) &free_fall, 1);
+ *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Free fall threshold setting.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of ff_ths in reg FREE_FALL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_ff_threshold_set(stmdev_ctx_t *ctx,
+ ais2ih_ff_ths_t val)
+{
+ ais2ih_free_fall_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_FREE_FALL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.ff_ths = (uint8_t) val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_FREE_FALL, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Free fall threshold setting.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of ff_ths in reg FREE_FALL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_ff_threshold_get(stmdev_ctx_t *ctx,
+ ais2ih_ff_ths_t *val)
+{
+ ais2ih_free_fall_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_FREE_FALL, (uint8_t *) ®, 1);
+
+ switch (reg.ff_ths)
+ {
+ case AIS2IH_FF_TSH_5LSb_FS2g:
+ *val = AIS2IH_FF_TSH_5LSb_FS2g;
+ break;
+
+ case AIS2IH_FF_TSH_7LSb_FS2g:
+ *val = AIS2IH_FF_TSH_7LSb_FS2g;
+ break;
+
+ case AIS2IH_FF_TSH_8LSb_FS2g:
+ *val = AIS2IH_FF_TSH_8LSb_FS2g;
+ break;
+
+ case AIS2IH_FF_TSH_10LSb_FS2g:
+ *val = AIS2IH_FF_TSH_10LSb_FS2g;
+ break;
+
+ case AIS2IH_FF_TSH_11LSb_FS2g:
+ *val = AIS2IH_FF_TSH_11LSb_FS2g;
+ break;
+
+ case AIS2IH_FF_TSH_13LSb_FS2g:
+ *val = AIS2IH_FF_TSH_13LSb_FS2g;
+ break;
+
+ case AIS2IH_FF_TSH_15LSb_FS2g:
+ *val = AIS2IH_FF_TSH_15LSb_FS2g;
+ break;
+
+ case AIS2IH_FF_TSH_16LSb_FS2g:
+ *val = AIS2IH_FF_TSH_16LSb_FS2g;
+ break;
+
+ default:
+ *val = AIS2IH_FF_TSH_5LSb_FS2g;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup AIS2IH_Fifo
+ * @brief This section group all the functions concerning the fifo usage
+ * @{
+ *
+ */
+
+/**
+ * @brief FIFO watermark level selection.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of fth in reg FIFO_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ ais2ih_fifo_ctrl_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_FIFO_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.fth = val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_FIFO_CTRL, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief FIFO watermark level selection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of fth in reg FIFO_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ ais2ih_fifo_ctrl_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_FIFO_CTRL, (uint8_t *) ®, 1);
+ *val = reg.fth;
+
+ return ret;
+}
+
+/**
+ * @brief FIFO mode selection.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of fmode in reg FIFO_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_fifo_mode_set(stmdev_ctx_t *ctx, ais2ih_fmode_t val)
+{
+ ais2ih_fifo_ctrl_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_FIFO_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.fmode = (uint8_t) val;
+ ret = ais2ih_write_reg(ctx, AIS2IH_FIFO_CTRL, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief FIFO mode selection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of fmode in reg FIFO_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_fifo_mode_get(stmdev_ctx_t *ctx, ais2ih_fmode_t *val)
+{
+ ais2ih_fifo_ctrl_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_FIFO_CTRL, (uint8_t *) ®, 1);
+
+ switch (reg.fmode)
+ {
+ case AIS2IH_BYPASS_MODE:
+ *val = AIS2IH_BYPASS_MODE;
+ break;
+
+ case AIS2IH_FIFO_MODE:
+ *val = AIS2IH_FIFO_MODE;
+ break;
+
+ case AIS2IH_STREAM_TO_FIFO_MODE:
+ *val = AIS2IH_STREAM_TO_FIFO_MODE;
+ break;
+
+ case AIS2IH_BYPASS_TO_STREAM_MODE:
+ *val = AIS2IH_BYPASS_TO_STREAM_MODE;
+ break;
+
+ case AIS2IH_STREAM_MODE:
+ *val = AIS2IH_STREAM_MODE;
+ break;
+
+ default:
+ *val = AIS2IH_BYPASS_MODE;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Number of unread samples stored in FIFO.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of diff in reg FIFO_SAMPLES
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ ais2ih_fifo_samples_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_FIFO_SAMPLES, (uint8_t *) ®, 1);
+ *val = reg.diff;
+
+ return ret;
+}
+/**
+ * @brief FIFO overrun status.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of fifo_ovr in reg FIFO_SAMPLES
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ ais2ih_fifo_samples_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_FIFO_SAMPLES, (uint8_t *) ®, 1);
+ *val = reg.fifo_ovr;
+
+ return ret;
+}
+/**
+ * @brief FIFO threshold status flag.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of fifo_fth in reg FIFO_SAMPLES
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t ais2ih_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ ais2ih_fifo_samples_t reg;
+ int32_t ret;
+
+ ret = ais2ih_read_reg(ctx, AIS2IH_FIFO_SAMPLES, (uint8_t *) ®, 1);
+ *val = reg.fifo_fth;
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @}
+ *
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/sensor/stmemsc/ais2ih_STdC/driver/ais2ih_reg.h b/sensor/stmemsc/ais2ih_STdC/driver/ais2ih_reg.h
new file mode 100644
index 0000000000000000000000000000000000000000..a6ed9ecce93f46c29365e2fa9342215f6dcd7ace
--- /dev/null
+++ b/sensor/stmemsc/ais2ih_STdC/driver/ais2ih_reg.h
@@ -0,0 +1,1038 @@
+/**
+ ******************************************************************************
+ * @file ais2ih_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * ais2ih_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef AIS2IH_REGS_H
+#define AIS2IH_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include
+#include
+#include
+
+/** @addtogroup AIS2IH
+ * @{
+ *
+ */
+
+/** @defgroup Endianness definitions
+ * @{
+ *
+ */
+
+#ifndef DRV_BYTE_ORDER
+#ifndef __BYTE_ORDER__
+
+#define DRV_LITTLE_ENDIAN 1234
+#define DRV_BIG_ENDIAN 4321
+
+/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
+ * by uncommenting the define which fits your platform endianness
+ */
+//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
+#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
+
+#else /* defined __BYTE_ORDER__ */
+
+#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
+#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
+#define DRV_BYTE_ORDER __BYTE_ORDER__
+
+#endif /* __BYTE_ORDER__*/
+#endif /* DRV_BYTE_ORDER */
+
+/**
+ * @}
+ *
+ */
+
+/** @defgroup STMicroelectronics sensors common types
+ * @{
+ *
+ */
+
+#ifndef MEMS_SHARED_TYPES
+#define MEMS_SHARED_TYPES
+
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
+} bitwise_t;
+
+#define PROPERTY_DISABLE (0U)
+#define PROPERTY_ENABLE (1U)
+
+/** @addtogroup Interfaces_Functions
+ * @brief This section provide a set of functions used to read and
+ * write a generic register of the device.
+ * MANDATORY: return 0 -> no Error.
+ * @{
+ *
+ */
+
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
+
+typedef struct
+{
+ /** Component mandatory fields **/
+ stmdev_write_ptr write_reg;
+ stmdev_read_ptr read_reg;
+ /** Customizable optional pointer **/
+ void *handle;
+} stmdev_ctx_t;
+
+/**
+ * @}
+ *
+ */
+
+#endif /* MEMS_SHARED_TYPES */
+
+#ifndef MEMS_UCF_SHARED_TYPES
+#define MEMS_UCF_SHARED_TYPES
+
+/** @defgroup Generic address-data structure definition
+ * @brief This structure is useful to load a predefined configuration
+ * of a sensor.
+ * You can create a sensor configuration by your own or using
+ * Unico / Unicleo tools available on STMicroelectronics
+ * web site.
+ *
+ * @{
+ *
+ */
+
+typedef struct
+{
+ uint8_t address;
+ uint8_t data;
+} ucf_line_t;
+
+/**
+ * @}
+ *
+ */
+
+#endif /* MEMS_UCF_SHARED_TYPES */
+
+/**
+ * @}
+ *
+ */
+
+/** @defgroup AIS2IH_Infos
+ * @{
+ *
+ */
+
+/** I2C Device Address 8 bit format if SA0=0 -> 31 if SA0=1 -> 33 **/
+#define AIS2IH_I2C_ADD_L 0x31U
+#define AIS2IH_I2C_ADD_H 0x33U
+
+/** Device Identification (Who am I) **/
+#define AIS2IH_ID 0x44U
+
+/**
+ * @}
+ *
+ */
+
+#define AIS2IH_OUT_T_L 0x0DU
+#define AIS2IH_OUT_T_H 0x0EU
+#define AIS2IH_WHO_AM_I 0x0FU
+#define AIS2IH_CTRL1 0x20U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t lp_mode : 2;
+ uint8_t mode : 2;
+ uint8_t odr : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr : 4;
+ uint8_t mode : 2;
+ uint8_t lp_mode : 2;
+#endif /* DRV_BYTE_ORDER */
+} ais2ih_ctrl1_t;
+
+#define AIS2IH_CTRL2 0x21U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t sim : 1;
+ uint8_t i2c_disable : 1;
+ uint8_t if_add_inc : 1;
+ uint8_t bdu : 1;
+ uint8_t cs_pu_disc : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t soft_reset : 1;
+ uint8_t boot : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t boot : 1;
+ uint8_t soft_reset : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t cs_pu_disc : 1;
+ uint8_t bdu : 1;
+ uint8_t if_add_inc : 1;
+ uint8_t i2c_disable : 1;
+ uint8_t sim : 1;
+#endif /* DRV_BYTE_ORDER */
+} ais2ih_ctrl2_t;
+
+#define AIS2IH_CTRL3 0x22U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+uint8_t slp_mode :
+ 2; /* slp_mode_sel + slp_mode_1 */
+ uint8_t not_used_01 : 1;
+ uint8_t h_lactive : 1;
+ uint8_t lir : 1;
+ uint8_t pp_od : 1;
+ uint8_t st : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t st : 2;
+ uint8_t pp_od : 1;
+ uint8_t lir : 1;
+ uint8_t h_lactive : 1;
+ uint8_t not_used_01 : 1;
+uint8_t slp_mode :
+ 2; /* slp_mode_sel + slp_mode_1 */
+#endif /* DRV_BYTE_ORDER */
+} ais2ih_ctrl3_t;
+
+#define AIS2IH_CTRL4_INT1_PAD_CTRL 0x23U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t int1_drdy : 1;
+ uint8_t int1_fth : 1;
+ uint8_t int1_diff5 : 1;
+ uint8_t int1_tap : 1;
+ uint8_t int1_ff : 1;
+ uint8_t int1_wu : 1;
+ uint8_t int1_single_tap : 1;
+ uint8_t int1_6d : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_6d : 1;
+ uint8_t int1_single_tap : 1;
+ uint8_t int1_wu : 1;
+ uint8_t int1_ff : 1;
+ uint8_t int1_tap : 1;
+ uint8_t int1_diff5 : 1;
+ uint8_t int1_fth : 1;
+ uint8_t int1_drdy : 1;
+#endif /* DRV_BYTE_ORDER */
+} ais2ih_ctrl4_int1_pad_ctrl_t;
+
+#define AIS2IH_CTRL5_INT2_PAD_CTRL 0x24U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t int2_drdy : 1;
+ uint8_t int2_fth : 1;
+ uint8_t int2_diff5 : 1;
+ uint8_t int2_ovr : 1;
+ uint8_t int2_drdy_t : 1;
+ uint8_t int2_boot : 1;
+ uint8_t int2_sleep_chg : 1;
+ uint8_t int2_sleep_state : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_sleep_state : 1;
+ uint8_t int2_sleep_chg : 1;
+ uint8_t int2_boot : 1;
+ uint8_t int2_drdy_t : 1;
+ uint8_t int2_ovr : 1;
+ uint8_t int2_diff5 : 1;
+ uint8_t int2_fth : 1;
+ uint8_t int2_drdy : 1;
+#endif /* DRV_BYTE_ORDER */
+} ais2ih_ctrl5_int2_pad_ctrl_t;
+
+#define AIS2IH_CTRL6 0x25U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t not_used_01 : 2;
+ uint8_t low_noise : 1;
+ uint8_t fds : 1;
+ uint8_t fs : 2;
+ uint8_t bw_filt : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bw_filt : 2;
+ uint8_t fs : 2;
+ uint8_t fds : 1;
+ uint8_t low_noise : 1;
+ uint8_t not_used_01 : 2;
+#endif /* DRV_BYTE_ORDER */
+} ais2ih_ctrl6_t;
+
+#define AIS2IH_OUT_T 0x26U
+#define AIS2IH_STATUS 0x27U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t drdy : 1;
+ uint8_t ff_ia : 1;
+ uint8_t _6d_ia : 1;
+ uint8_t single_tap : 1;
+ uint8_t double_tap : 1;
+ uint8_t sleep_state : 1;
+ uint8_t wu_ia : 1;
+ uint8_t fifo_ths : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fifo_ths : 1;
+ uint8_t wu_ia : 1;
+ uint8_t sleep_state : 1;
+ uint8_t double_tap : 1;
+ uint8_t single_tap : 1;
+ uint8_t _6d_ia : 1;
+ uint8_t ff_ia : 1;
+ uint8_t drdy : 1;
+#endif /* DRV_BYTE_ORDER */
+} ais2ih_status_t;
+
+#define AIS2IH_OUT_X_L 0x28U
+#define AIS2IH_OUT_X_H 0x29U
+#define AIS2IH_OUT_Y_L 0x2AU
+#define AIS2IH_OUT_Y_H 0x2BU
+#define AIS2IH_OUT_Z_L 0x2CU
+#define AIS2IH_OUT_Z_H 0x2DU
+#define AIS2IH_FIFO_CTRL 0x2EU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t fth : 5;
+ uint8_t fmode : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fmode : 3;
+ uint8_t fth : 5;
+#endif /* DRV_BYTE_ORDER */
+} ais2ih_fifo_ctrl_t;
+
+#define AIS2IH_FIFO_SAMPLES 0x2FU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t diff : 6;
+ uint8_t fifo_ovr : 1;
+ uint8_t fifo_fth : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fifo_fth : 1;
+ uint8_t fifo_ovr : 1;
+ uint8_t diff : 6;
+#endif /* DRV_BYTE_ORDER */
+} ais2ih_fifo_samples_t;
+
+#define AIS2IH_TAP_THS_X 0x30U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t tap_thsx : 5;
+ uint8_t _6d_ths : 2;
+ uint8_t _4d_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t _4d_en : 1;
+ uint8_t _6d_ths : 2;
+ uint8_t tap_thsx : 5;
+#endif /* DRV_BYTE_ORDER */
+} ais2ih_tap_ths_x_t;
+
+#define AIS2IH_TAP_THS_Y 0x31U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t tap_thsy : 5;
+ uint8_t tap_prior : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t tap_prior : 3;
+ uint8_t tap_thsy : 5;
+#endif /* DRV_BYTE_ORDER */
+} ais2ih_tap_ths_y_t;
+
+#define AIS2IH_TAP_THS_Z 0x32U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t tap_thsz : 5;
+ uint8_t tap_z_en : 1;
+ uint8_t tap_y_en : 1;
+ uint8_t tap_x_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t tap_x_en : 1;
+ uint8_t tap_y_en : 1;
+ uint8_t tap_z_en : 1;
+ uint8_t tap_thsz : 5;
+#endif /* DRV_BYTE_ORDER */
+} ais2ih_tap_ths_z_t;
+
+#define AIS2IH_INT_DUR 0x33U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t shock : 2;
+ uint8_t quiet : 2;
+ uint8_t latency : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t latency : 4;
+ uint8_t quiet : 2;
+ uint8_t shock : 2;
+#endif /* DRV_BYTE_ORDER */
+} ais2ih_int_dur_t;
+
+#define AIS2IH_WAKE_UP_THS 0x34U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t wk_ths : 6;
+ uint8_t sleep_on : 1;
+ uint8_t single_double_tap : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t single_double_tap : 1;
+ uint8_t sleep_on : 1;
+ uint8_t wk_ths : 6;
+#endif /* DRV_BYTE_ORDER */
+} ais2ih_wake_up_ths_t;
+
+#define AIS2IH_WAKE_UP_DUR 0x35U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t sleep_dur : 4;
+ uint8_t stationary : 1;
+ uint8_t wake_dur : 2;
+ uint8_t ff_dur : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t ff_dur : 1;
+ uint8_t wake_dur : 2;
+ uint8_t stationary : 1;
+ uint8_t sleep_dur : 4;
+#endif /* DRV_BYTE_ORDER */
+} ais2ih_wake_up_dur_t;
+
+#define AIS2IH_FREE_FALL 0x36U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t ff_ths : 3;
+ uint8_t ff_dur : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t ff_dur : 5;
+ uint8_t ff_ths : 3;
+#endif /* DRV_BYTE_ORDER */
+} ais2ih_free_fall_t;
+
+#define AIS2IH_STATUS_DUP 0x37U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t drdy : 1;
+ uint8_t ff_ia : 1;
+ uint8_t _6d_ia : 1;
+ uint8_t single_tap : 1;
+ uint8_t double_tap : 1;
+ uint8_t sleep_state_ia : 1;
+ uint8_t drdy_t : 1;
+ uint8_t ovr : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t ovr : 1;
+ uint8_t drdy_t : 1;
+ uint8_t sleep_state_ia : 1;
+ uint8_t double_tap : 1;
+ uint8_t single_tap : 1;
+ uint8_t _6d_ia : 1;
+ uint8_t ff_ia : 1;
+ uint8_t drdy : 1;
+#endif /* DRV_BYTE_ORDER */
+} ais2ih_status_dup_t;
+
+#define AIS2IH_WAKE_UP_SRC 0x38U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t z_wu : 1;
+ uint8_t y_wu : 1;
+ uint8_t x_wu : 1;
+ uint8_t wu_ia : 1;
+ uint8_t sleep_state_ia : 1;
+ uint8_t ff_ia : 1;
+ uint8_t not_used_01 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 2;
+ uint8_t ff_ia : 1;
+ uint8_t sleep_state_ia : 1;
+ uint8_t wu_ia : 1;
+ uint8_t x_wu : 1;
+ uint8_t y_wu : 1;
+ uint8_t z_wu : 1;
+#endif /* DRV_BYTE_ORDER */
+} ais2ih_wake_up_src_t;
+
+#define AIS2IH_TAP_SRC 0x39U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t z_tap : 1;
+ uint8_t y_tap : 1;
+ uint8_t x_tap : 1;
+ uint8_t tap_sign : 1;
+ uint8_t double_tap : 1;
+ uint8_t single_tap : 1;
+ uint8_t tap_ia : 1;
+ uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t tap_ia : 1;
+ uint8_t single_tap : 1;
+ uint8_t double_tap : 1;
+ uint8_t tap_sign : 1;
+ uint8_t x_tap : 1;
+ uint8_t y_tap : 1;
+ uint8_t z_tap : 1;
+#endif /* DRV_BYTE_ORDER */
+} ais2ih_tap_src_t;
+
+#define AIS2IH_SIXD_SRC 0x3AU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t xl : 1;
+ uint8_t xh : 1;
+ uint8_t yl : 1;
+ uint8_t yh : 1;
+ uint8_t zl : 1;
+ uint8_t zh : 1;
+ uint8_t _6d_ia : 1;
+ uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t _6d_ia : 1;
+ uint8_t zh : 1;
+ uint8_t zl : 1;
+ uint8_t yh : 1;
+ uint8_t yl : 1;
+ uint8_t xh : 1;
+ uint8_t xl : 1;
+#endif /* DRV_BYTE_ORDER */
+} ais2ih_sixd_src_t;
+
+#define AIS2IH_ALL_INT_SRC 0x3BU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t ff_ia : 1;
+ uint8_t wu_ia : 1;
+ uint8_t single_tap : 1;
+ uint8_t double_tap : 1;
+ uint8_t _6d_ia : 1;
+ uint8_t sleep_change_ia : 1;
+ uint8_t not_used_01 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 2;
+ uint8_t sleep_change_ia : 1;
+ uint8_t _6d_ia : 1;
+ uint8_t double_tap : 1;
+ uint8_t single_tap : 1;
+ uint8_t wu_ia : 1;
+ uint8_t ff_ia : 1;
+#endif /* DRV_BYTE_ORDER */
+} ais2ih_all_int_src_t;
+
+#define AIS2IH_X_OFS_USR 0x3CU
+#define AIS2IH_Y_OFS_USR 0x3DU
+#define AIS2IH_Z_OFS_USR 0x3EU
+#define AIS2IH_CTRL_REG7 0x3FU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t lpass_on6d : 1;
+ uint8_t hp_ref_mode : 1;
+ uint8_t usr_off_w : 1;
+ uint8_t usr_off_on_wu : 1;
+ uint8_t usr_off_on_out : 1;
+ uint8_t interrupts_enable : 1;
+ uint8_t int2_on_int1 : 1;
+ uint8_t drdy_pulsed : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t drdy_pulsed : 1;
+ uint8_t int2_on_int1 : 1;
+ uint8_t interrupts_enable : 1;
+ uint8_t usr_off_on_out : 1;
+ uint8_t usr_off_on_wu : 1;
+ uint8_t usr_off_w : 1;
+ uint8_t hp_ref_mode : 1;
+ uint8_t lpass_on6d : 1;
+#endif /* DRV_BYTE_ORDER */
+} ais2ih_ctrl_reg7_t;
+
+/**
+ * @defgroup AIS2IH_Register_Union
+ * @brief This union group all the registers having a bit-field
+ * description.
+ * This union is useful but it's not needed by the driver.
+ *
+ * REMOVING this union you are compliant with:
+ * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
+ *
+ * @{
+ *
+ */
+typedef union
+{
+ ais2ih_ctrl1_t ctrl1;
+ ais2ih_ctrl2_t ctrl2;
+ ais2ih_ctrl3_t ctrl3;
+ ais2ih_ctrl4_int1_pad_ctrl_t ctrl4_int1_pad_ctrl;
+ ais2ih_ctrl5_int2_pad_ctrl_t ctrl5_int2_pad_ctrl;
+ ais2ih_ctrl6_t ctrl6;
+ ais2ih_status_t status;
+ ais2ih_fifo_ctrl_t fifo_ctrl;
+ ais2ih_fifo_samples_t fifo_samples;
+ ais2ih_tap_ths_x_t tap_ths_x;
+ ais2ih_tap_ths_y_t tap_ths_y;
+ ais2ih_tap_ths_z_t tap_ths_z;
+ ais2ih_int_dur_t int_dur;
+ ais2ih_wake_up_ths_t wake_up_ths;
+ ais2ih_wake_up_dur_t wake_up_dur;
+ ais2ih_free_fall_t free_fall;
+ ais2ih_status_dup_t status_dup;
+ ais2ih_wake_up_src_t wake_up_src;
+ ais2ih_tap_src_t tap_src;
+ ais2ih_sixd_src_t sixd_src;
+ ais2ih_all_int_src_t all_int_src;
+ ais2ih_ctrl_reg7_t ctrl_reg7;
+ bitwise_t bitwise;
+ uint8_t byte;
+} ais2ih_reg_t;
+
+/**
+ * @}
+ *
+ */
+
+int32_t ais2ih_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
+ uint16_t len);
+int32_t ais2ih_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len);
+
+float_t ais2ih_from_fs2_to_mg(int16_t lsb);
+float_t ais2ih_from_fs4_to_mg(int16_t lsb);
+float_t ais2ih_from_fs8_to_mg(int16_t lsb);
+float_t ais2ih_from_fs16_to_mg(int16_t lsb);
+float_t ais2ih_from_fs2_lp1_to_mg(int16_t lsb);
+float_t ais2ih_from_fs4_lp1_to_mg(int16_t lsb);
+float_t ais2ih_from_fs8_lp1_to_mg(int16_t lsb);
+float_t ais2ih_from_fs16_lp1_to_mg(int16_t lsb);
+float_t ais2ih_from_lsb_to_celsius(int16_t lsb);
+
+typedef enum
+{
+ AIS2IH_HIGH_PERFORMANCE = 0x04,
+ AIS2IH_CONT_LOW_PWR_4 = 0x03,
+ AIS2IH_CONT_LOW_PWR_3 = 0x02,
+ AIS2IH_CONT_LOW_PWR_2 = 0x01,
+ AIS2IH_CONT_LOW_PWR_12bit = 0x00,
+ AIS2IH_SINGLE_LOW_PWR_4 = 0x0B,
+ AIS2IH_SINGLE_LOW_PWR_3 = 0x0A,
+ AIS2IH_SINGLE_LOW_PWR_2 = 0x09,
+ AIS2IH_SINGLE_LOW_PWR_12bit = 0x08,
+ AIS2IH_HIGH_PERFORMANCE_LOW_NOISE = 0x14,
+ AIS2IH_CONT_LOW_PWR_LOW_NOISE_4 = 0x13,
+ AIS2IH_CONT_LOW_PWR_LOW_NOISE_3 = 0x12,
+ AIS2IH_CONT_LOW_PWR_LOW_NOISE_2 = 0x11,
+ AIS2IH_CONT_LOW_PWR_LOW_NOISE_12bit = 0x10,
+ AIS2IH_SINGLE_LOW_PWR_LOW_NOISE_4 = 0x1B,
+ AIS2IH_SINGLE_LOW_PWR_LOW_NOISE_3 = 0x1A,
+ AIS2IH_SINGLE_LOW_PWR_LOW_NOISE_2 = 0x19,
+ AIS2IH_SINGLE_LOW_LOW_NOISE_PWR_12bit = 0x18,
+} ais2ih_mode_t;
+int32_t ais2ih_power_mode_set(stmdev_ctx_t *ctx, ais2ih_mode_t val);
+int32_t ais2ih_power_mode_get(stmdev_ctx_t *ctx, ais2ih_mode_t *val);
+
+typedef enum
+{
+ AIS2IH_XL_ODR_OFF = 0x00,
+ AIS2IH_XL_ODR_1Hz6_LP_ONLY = 0x01,
+ AIS2IH_XL_ODR_12Hz5 = 0x02,
+ AIS2IH_XL_ODR_25Hz = 0x03,
+ AIS2IH_XL_ODR_50Hz = 0x04,
+ AIS2IH_XL_ODR_100Hz = 0x05,
+ AIS2IH_XL_ODR_200Hz = 0x06,
+ AIS2IH_XL_ODR_400Hz = 0x07,
+ AIS2IH_XL_ODR_800Hz = 0x08,
+ AIS2IH_XL_ODR_1k6Hz = 0x09,
+ AIS2IH_XL_SET_SW_TRIG = 0x32, /* Use this only in SINGLE mode */
+ AIS2IH_XL_SET_PIN_TRIG = 0x12, /* Use this only in SINGLE mode */
+} ais2ih_odr_t;
+int32_t ais2ih_data_rate_set(stmdev_ctx_t *ctx, ais2ih_odr_t val);
+int32_t ais2ih_data_rate_get(stmdev_ctx_t *ctx, ais2ih_odr_t *val);
+
+int32_t ais2ih_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t ais2ih_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+ AIS2IH_2g = 0,
+ AIS2IH_4g = 1,
+ AIS2IH_8g = 2,
+ AIS2IH_16g = 3,
+} ais2ih_fs_t;
+int32_t ais2ih_full_scale_set(stmdev_ctx_t *ctx, ais2ih_fs_t val);
+int32_t ais2ih_full_scale_get(stmdev_ctx_t *ctx, ais2ih_fs_t *val);
+
+int32_t ais2ih_status_reg_get(stmdev_ctx_t *ctx,
+ ais2ih_status_t *val);
+
+int32_t ais2ih_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef struct
+{
+ ais2ih_status_dup_t status_dup;
+ ais2ih_wake_up_src_t wake_up_src;
+ ais2ih_tap_src_t tap_src;
+ ais2ih_sixd_src_t sixd_src;
+ ais2ih_all_int_src_t all_int_src;
+} ais2ih_all_sources_t;
+int32_t ais2ih_all_sources_get(stmdev_ctx_t *ctx,
+ ais2ih_all_sources_t *val);
+
+int32_t ais2ih_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t ais2ih_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff);
+
+int32_t ais2ih_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t ais2ih_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff);
+
+int32_t ais2ih_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t ais2ih_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff);
+
+typedef enum
+{
+ AIS2IH_LSb_977ug = 0,
+ AIS2IH_LSb_15mg6 = 1,
+} ais2ih_usr_off_w_t;
+int32_t ais2ih_offset_weight_set(stmdev_ctx_t *ctx,
+ ais2ih_usr_off_w_t val);
+int32_t ais2ih_offset_weight_get(stmdev_ctx_t *ctx,
+ ais2ih_usr_off_w_t *val);
+
+int32_t ais2ih_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+
+int32_t ais2ih_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+
+int32_t ais2ih_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
+
+int32_t ais2ih_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t ais2ih_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t ais2ih_reset_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t ais2ih_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t ais2ih_boot_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t ais2ih_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+ AIS2IH_XL_ST_DISABLE = 0,
+ AIS2IH_XL_ST_POSITIVE = 1,
+ AIS2IH_XL_ST_NEGATIVE = 2,
+} ais2ih_st_t;
+int32_t ais2ih_self_test_set(stmdev_ctx_t *ctx, ais2ih_st_t val);
+int32_t ais2ih_self_test_get(stmdev_ctx_t *ctx, ais2ih_st_t *val);
+
+typedef enum
+{
+ AIS2IH_DRDY_LATCHED = 0,
+ AIS2IH_DRDY_PULSED = 1,
+} ais2ih_drdy_pulsed_t;
+int32_t ais2ih_data_ready_mode_set(stmdev_ctx_t *ctx,
+ ais2ih_drdy_pulsed_t val);
+int32_t ais2ih_data_ready_mode_get(stmdev_ctx_t *ctx,
+ ais2ih_drdy_pulsed_t *val);
+
+typedef enum
+{
+ AIS2IH_LPF_ON_OUT = 0x00,
+ AIS2IH_USER_OFFSET_ON_OUT = 0x01,
+ AIS2IH_HIGH_PASS_ON_OUT = 0x10,
+} ais2ih_fds_t;
+int32_t ais2ih_filter_path_set(stmdev_ctx_t *ctx, ais2ih_fds_t val);
+int32_t ais2ih_filter_path_get(stmdev_ctx_t *ctx, ais2ih_fds_t *val);
+
+typedef enum
+{
+ AIS2IH_ODR_DIV_2 = 0,
+ AIS2IH_ODR_DIV_4 = 1,
+ AIS2IH_ODR_DIV_10 = 2,
+ AIS2IH_ODR_DIV_20 = 3,
+} ais2ih_bw_filt_t;
+int32_t ais2ih_filter_bandwidth_set(stmdev_ctx_t *ctx,
+ ais2ih_bw_filt_t val);
+int32_t ais2ih_filter_bandwidth_get(stmdev_ctx_t *ctx,
+ ais2ih_bw_filt_t *val);
+
+int32_t ais2ih_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t ais2ih_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+ AIS2IH_SPI_4_WIRE = 0,
+ AIS2IH_SPI_3_WIRE = 1,
+} ais2ih_sim_t;
+int32_t ais2ih_spi_mode_set(stmdev_ctx_t *ctx, ais2ih_sim_t val);
+int32_t ais2ih_spi_mode_get(stmdev_ctx_t *ctx, ais2ih_sim_t *val);
+
+typedef enum
+{
+ AIS2IH_I2C_ENABLE = 0,
+ AIS2IH_I2C_DISABLE = 1,
+} ais2ih_i2c_disable_t;
+int32_t ais2ih_i2c_interface_set(stmdev_ctx_t *ctx,
+ ais2ih_i2c_disable_t val);
+int32_t ais2ih_i2c_interface_get(stmdev_ctx_t *ctx,
+ ais2ih_i2c_disable_t *val);
+
+typedef enum
+{
+ AIS2IH_PULL_UP_CONNECT = 0,
+ AIS2IH_PULL_UP_DISCONNECT = 1,
+} ais2ih_cs_pu_disc_t;
+int32_t ais2ih_cs_mode_set(stmdev_ctx_t *ctx,
+ ais2ih_cs_pu_disc_t val);
+int32_t ais2ih_cs_mode_get(stmdev_ctx_t *ctx,
+ ais2ih_cs_pu_disc_t *val);
+
+typedef enum
+{
+ AIS2IH_ACTIVE_HIGH = 0,
+ AIS2IH_ACTIVE_LOW = 1,
+} ais2ih_h_lactive_t;
+int32_t ais2ih_pin_polarity_set(stmdev_ctx_t *ctx,
+ ais2ih_h_lactive_t val);
+int32_t ais2ih_pin_polarity_get(stmdev_ctx_t *ctx,
+ ais2ih_h_lactive_t *val);
+
+typedef enum
+{
+ AIS2IH_INT_PULSED = 0,
+ AIS2IH_INT_LATCHED = 1,
+} ais2ih_lir_t;
+int32_t ais2ih_int_notification_set(stmdev_ctx_t *ctx,
+ ais2ih_lir_t val);
+int32_t ais2ih_int_notification_get(stmdev_ctx_t *ctx,
+ ais2ih_lir_t *val);
+
+typedef enum
+{
+ AIS2IH_PUSH_PULL = 0,
+ AIS2IH_OPEN_DRAIN = 1,
+} ais2ih_pp_od_t;
+int32_t ais2ih_pin_mode_set(stmdev_ctx_t *ctx, ais2ih_pp_od_t val);
+int32_t ais2ih_pin_mode_get(stmdev_ctx_t *ctx, ais2ih_pp_od_t *val);
+
+int32_t ais2ih_pin_int1_route_set(stmdev_ctx_t *ctx,
+ ais2ih_ctrl4_int1_pad_ctrl_t *val);
+int32_t ais2ih_pin_int1_route_get(stmdev_ctx_t *ctx,
+ ais2ih_ctrl4_int1_pad_ctrl_t *val);
+
+int32_t ais2ih_pin_int2_route_set(stmdev_ctx_t *ctx,
+ ais2ih_ctrl5_int2_pad_ctrl_t *val);
+int32_t ais2ih_pin_int2_route_get(stmdev_ctx_t *ctx,
+ ais2ih_ctrl5_int2_pad_ctrl_t *val);
+
+int32_t ais2ih_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t ais2ih_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t ais2ih_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t ais2ih_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t ais2ih_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t ais2ih_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+ AIS2IH_HP_FEED = 0,
+ AIS2IH_USER_OFFSET_FEED = 1,
+} ais2ih_usr_off_on_wu_t;
+int32_t ais2ih_wkup_feed_data_set(stmdev_ctx_t *ctx,
+ ais2ih_usr_off_on_wu_t val);
+int32_t ais2ih_wkup_feed_data_get(stmdev_ctx_t *ctx,
+ ais2ih_usr_off_on_wu_t *val);
+
+typedef enum
+{
+ AIS2IH_NO_DETECTION = 0,
+ AIS2IH_DETECT_ACT_INACT = 1,
+ AIS2IH_DETECT_STAT_MOTION = 3,
+} ais2ih_sleep_on_t;
+int32_t ais2ih_act_mode_set(stmdev_ctx_t *ctx, ais2ih_sleep_on_t val);
+int32_t ais2ih_act_mode_get(stmdev_ctx_t *ctx,
+ ais2ih_sleep_on_t *val);
+
+int32_t ais2ih_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t ais2ih_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t ais2ih_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t ais2ih_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t ais2ih_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t ais2ih_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+ AIS2IH_XYZ = 0,
+ AIS2IH_YXZ = 1,
+ AIS2IH_XZY = 2,
+ AIS2IH_ZYX = 3,
+ AIS2IH_YZX = 5,
+ AIS2IH_ZXY = 6,
+} ais2ih_tap_prior_t;
+int32_t ais2ih_tap_axis_priority_set(stmdev_ctx_t *ctx,
+ ais2ih_tap_prior_t val);
+int32_t ais2ih_tap_axis_priority_get(stmdev_ctx_t *ctx,
+ ais2ih_tap_prior_t *val);
+
+int32_t ais2ih_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t ais2ih_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t ais2ih_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t ais2ih_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t ais2ih_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t ais2ih_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t ais2ih_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t ais2ih_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t ais2ih_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t ais2ih_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t ais2ih_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t ais2ih_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t ais2ih_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t ais2ih_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+ AIS2IH_ONLY_SINGLE = 0,
+ AIS2IH_BOTH_SINGLE_DOUBLE = 1,
+} ais2ih_single_double_tap_t;
+int32_t ais2ih_tap_mode_set(stmdev_ctx_t *ctx,
+ ais2ih_single_double_tap_t val);
+int32_t ais2ih_tap_mode_get(stmdev_ctx_t *ctx,
+ ais2ih_single_double_tap_t *val);
+
+int32_t ais2ih_tap_src_get(stmdev_ctx_t *ctx, ais2ih_tap_src_t *val);
+
+int32_t ais2ih_6d_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t ais2ih_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t ais2ih_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t ais2ih_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t ais2ih_6d_src_get(stmdev_ctx_t *ctx, ais2ih_sixd_src_t *val);
+
+typedef enum
+{
+ AIS2IH_ODR_DIV_2_FEED = 0,
+ AIS2IH_LPF2_FEED = 1,
+} ais2ih_lpass_on6d_t;
+int32_t ais2ih_6d_feed_data_set(stmdev_ctx_t *ctx,
+ ais2ih_lpass_on6d_t val);
+int32_t ais2ih_6d_feed_data_get(stmdev_ctx_t *ctx,
+ ais2ih_lpass_on6d_t *val);
+
+int32_t ais2ih_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t ais2ih_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+ AIS2IH_FF_TSH_5LSb_FS2g = 0,
+ AIS2IH_FF_TSH_7LSb_FS2g = 1,
+ AIS2IH_FF_TSH_8LSb_FS2g = 2,
+ AIS2IH_FF_TSH_10LSb_FS2g = 3,
+ AIS2IH_FF_TSH_11LSb_FS2g = 4,
+ AIS2IH_FF_TSH_13LSb_FS2g = 5,
+ AIS2IH_FF_TSH_15LSb_FS2g = 6,
+ AIS2IH_FF_TSH_16LSb_FS2g = 7,
+} ais2ih_ff_ths_t;
+int32_t ais2ih_ff_threshold_set(stmdev_ctx_t *ctx,
+ ais2ih_ff_ths_t val);
+int32_t ais2ih_ff_threshold_get(stmdev_ctx_t *ctx,
+ ais2ih_ff_ths_t *val);
+
+int32_t ais2ih_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t ais2ih_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+ AIS2IH_BYPASS_MODE = 0,
+ AIS2IH_FIFO_MODE = 1,
+ AIS2IH_STREAM_TO_FIFO_MODE = 3,
+ AIS2IH_BYPASS_TO_STREAM_MODE = 4,
+ AIS2IH_STREAM_MODE = 6,
+} ais2ih_fmode_t;
+int32_t ais2ih_fifo_mode_set(stmdev_ctx_t *ctx, ais2ih_fmode_t val);
+int32_t ais2ih_fifo_mode_get(stmdev_ctx_t *ctx, ais2ih_fmode_t *val);
+
+int32_t ais2ih_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t ais2ih_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t ais2ih_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+/**
+ * @}
+ *
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*AIS2IH_REGS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.c b/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.c
index 0c0c0727f26296c84c65ee9aa0950dccdb208f45..c7dff8ce9d3095cc87cecfa91877d40de57bae0b 100644
--- a/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.c
+++ b/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file ais328dq_reg.c
- * @author Sensors Software Solution Team
- * @brief AIS328DQ driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file ais328dq_reg.c
+ * @author Sensors Software Solution Team
+ * @brief AIS328DQ driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "ais328dq_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais328dq_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t ais328dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t ais328dq_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais328dq_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t ais328dq_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -77,7 +83,7 @@ int32_t ais328dq_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
*
*/
- /**
+/**
* @defgroup AIS328DQ_Sensitivity
* @brief These functions convert raw-data into engineering units.
* @{
@@ -117,6 +123,7 @@ float_t ais328dq_from_fs8_to_mg(int16_t lsb)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of xen in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -124,12 +131,16 @@ int32_t ais328dq_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val)
ais328dq_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0) {
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.xen = val;
ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -138,6 +149,7 @@ int32_t ais328dq_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of xen in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -145,7 +157,8 @@ int32_t ais328dq_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val)
ais328dq_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
*val = ctrl_reg1.xen;
return ret;
@@ -156,6 +169,7 @@ int32_t ais328dq_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of yen in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -163,12 +177,16 @@ int32_t ais328dq_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val)
ais328dq_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0) {
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.yen = val;
ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -177,6 +195,7 @@ int32_t ais328dq_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of yen in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -184,7 +203,8 @@ int32_t ais328dq_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val)
ais328dq_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
*val = ctrl_reg1.yen;
return ret;
@@ -195,6 +215,7 @@ int32_t ais328dq_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of zen in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -202,12 +223,16 @@ int32_t ais328dq_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val)
ais328dq_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0) {
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.zen = val;
ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -216,6 +241,7 @@ int32_t ais328dq_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of zen in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -223,7 +249,8 @@ int32_t ais328dq_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val)
ais328dq_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
*val = ctrl_reg1.zen;
return ret;
@@ -234,6 +261,7 @@ int32_t ais328dq_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of dr in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_data_rate_set(stmdev_ctx_t *ctx, ais328dq_dr_t val)
@@ -242,13 +270,16 @@ int32_t ais328dq_data_rate_set(stmdev_ctx_t *ctx, ais328dq_dr_t val)
int32_t ret;
ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0) {
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.pm = (uint8_t)val & 0x07U;
- ctrl_reg1.dr = ( (uint8_t)val & 0x30U ) >> 4;
+ ctrl_reg1.dr = ((uint8_t)val & 0x30U) >> 4;
ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -257,6 +288,7 @@ int32_t ais328dq_data_rate_set(stmdev_ctx_t *ctx, ais328dq_dr_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of dr in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_data_rate_get(stmdev_ctx_t *ctx, ais328dq_dr_t *val)
@@ -265,40 +297,50 @@ int32_t ais328dq_data_rate_get(stmdev_ctx_t *ctx, ais328dq_dr_t *val)
int32_t ret;
ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pm)
{
case AIS328DQ_ODR_OFF:
*val = AIS328DQ_ODR_OFF;
break;
+
case AIS328DQ_ODR_Hz5:
*val = AIS328DQ_ODR_Hz5;
break;
+
case AIS328DQ_ODR_1Hz:
*val = AIS328DQ_ODR_1Hz;
break;
+
case AIS328DQ_ODR_5Hz2:
*val = AIS328DQ_ODR_5Hz2;
break;
+
case AIS328DQ_ODR_5Hz:
*val = AIS328DQ_ODR_5Hz;
break;
+
case AIS328DQ_ODR_10Hz:
*val = AIS328DQ_ODR_10Hz;
break;
+
case AIS328DQ_ODR_50Hz:
*val = AIS328DQ_ODR_50Hz;
break;
+
case AIS328DQ_ODR_100Hz:
*val = AIS328DQ_ODR_100Hz;
break;
+
case AIS328DQ_ODR_400Hz:
*val = AIS328DQ_ODR_400Hz;
break;
+
case AIS328DQ_ODR_1kHz:
*val = AIS328DQ_ODR_1kHz;
break;
+
default:
*val = AIS328DQ_ODR_OFF;
break;
@@ -312,20 +354,25 @@ int32_t ais328dq_data_rate_get(stmdev_ctx_t *ctx, ais328dq_dr_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of hpm in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_reference_mode_set(stmdev_ctx_t *ctx,
- ais328dq_hpm_t val)
+ ais328dq_hpm_t val)
{
ais328dq_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0) {
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpm = (uint8_t)val;
ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -334,29 +381,33 @@ int32_t ais328dq_reference_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of hpm in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_reference_mode_get(stmdev_ctx_t *ctx,
- ais328dq_hpm_t *val)
+ ais328dq_hpm_t *val)
{
ais328dq_ctrl_reg2_t ctrl_reg2;
int32_t ret;
ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
switch (ctrl_reg2.hpm)
{
case AIS328DQ_NORMAL_MODE:
*val = AIS328DQ_NORMAL_MODE;
break;
+
case AIS328DQ_REF_MODE_ENABLE:
*val = AIS328DQ_REF_MODE_ENABLE;
break;
+
default:
*val = AIS328DQ_NORMAL_MODE;
break;
}
+
return ret;
}
@@ -365,6 +416,7 @@ int32_t ais328dq_reference_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of fs in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_full_scale_set(stmdev_ctx_t *ctx, ais328dq_fs_t val)
@@ -372,12 +424,16 @@ int32_t ais328dq_full_scale_set(stmdev_ctx_t *ctx, ais328dq_fs_t val)
ais328dq_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0) {
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.fs = (uint8_t)val;
ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -386,6 +442,7 @@ int32_t ais328dq_full_scale_set(stmdev_ctx_t *ctx, ais328dq_fs_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of fs in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_full_scale_get(stmdev_ctx_t *ctx, ais328dq_fs_t *val)
@@ -393,19 +450,23 @@ int32_t ais328dq_full_scale_get(stmdev_ctx_t *ctx, ais328dq_fs_t *val)
ais328dq_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
switch (ctrl_reg4.fs)
{
case AIS328DQ_2g:
*val = AIS328DQ_2g;
break;
+
case AIS328DQ_4g:
*val = AIS328DQ_4g;
break;
+
case AIS328DQ_8g:
*val = AIS328DQ_8g;
break;
+
default:
*val = AIS328DQ_2g;
break;
@@ -419,6 +480,7 @@ int32_t ais328dq_full_scale_get(stmdev_ctx_t *ctx, ais328dq_fs_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of bdu in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -426,12 +488,16 @@ int32_t ais328dq_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
ais328dq_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0) {
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.bdu = val;
ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -440,14 +506,17 @@ int32_t ais328dq_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of bdu in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais328dq_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ais328dq_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ais328dq_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
*val = ctrl_reg4.bdu;
return ret;
@@ -458,13 +527,16 @@ int32_t ais328dq_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val registers STATUS_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_status_reg_get(stmdev_ctx_t *ctx,
- ais328dq_status_reg_t *val)
+ ais328dq_status_reg_t *val)
{
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_STATUS_REG, (uint8_t*) val, 1);
+
+ ret = ais328dq_read_reg(ctx, AIS328DQ_STATUS_REG, (uint8_t *) val, 1);
+
return ret;
}
@@ -473,6 +545,7 @@ int32_t ais328dq_status_reg_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of zyxda in reg STATUS_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -481,7 +554,7 @@ int32_t ais328dq_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = ais328dq_read_reg(ctx, AIS328DQ_STATUS_REG,
- (uint8_t*)&status_reg, 1);
+ (uint8_t *)&status_reg, 1);
*val = status_reg.zyxda;
return ret;
@@ -505,6 +578,7 @@ int32_t ais328dq_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
@@ -540,12 +614,15 @@ int32_t ais328dq_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = ais328dq_read_reg(ctx, AIS328DQ_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -554,6 +631,7 @@ int32_t ais328dq_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of boot in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_boot_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -561,12 +639,16 @@ int32_t ais328dq_boot_set(stmdev_ctx_t *ctx, uint8_t val)
ais328dq_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0) {
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.boot = val;
ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -575,6 +657,7 @@ int32_t ais328dq_boot_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of boot in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -582,7 +665,8 @@ int32_t ais328dq_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
ais328dq_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
*val = ctrl_reg2.boot;
return ret;
@@ -593,6 +677,7 @@ int32_t ais328dq_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of st in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_self_test_set(stmdev_ctx_t *ctx, ais328dq_st_t val)
@@ -600,12 +685,16 @@ int32_t ais328dq_self_test_set(stmdev_ctx_t *ctx, ais328dq_st_t val)
ais328dq_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0) {
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.st = (uint8_t)val;
ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -614,6 +703,7 @@ int32_t ais328dq_self_test_set(stmdev_ctx_t *ctx, ais328dq_st_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of st in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_self_test_get(stmdev_ctx_t *ctx, ais328dq_st_t *val)
@@ -621,19 +711,23 @@ int32_t ais328dq_self_test_get(stmdev_ctx_t *ctx, ais328dq_st_t *val)
ais328dq_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
switch (ctrl_reg4.st)
{
case AIS328DQ_ST_DISABLE:
*val = AIS328DQ_ST_DISABLE;
break;
+
case AIS328DQ_ST_POSITIVE:
*val = AIS328DQ_ST_POSITIVE;
break;
+
case AIS328DQ_ST_NEGATIVE:
*val = AIS328DQ_ST_NEGATIVE;
break;
+
default:
*val = AIS328DQ_ST_DISABLE;
break;
@@ -647,19 +741,25 @@ int32_t ais328dq_self_test_get(stmdev_ctx_t *ctx, ais328dq_st_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ble in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais328dq_data_format_set(stmdev_ctx_t *ctx, ais328dq_ble_t val)
+int32_t ais328dq_data_format_set(stmdev_ctx_t *ctx,
+ ais328dq_ble_t val)
{
ais328dq_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0) {
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.ble = (uint8_t)val;
ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -668,23 +768,28 @@ int32_t ais328dq_data_format_set(stmdev_ctx_t *ctx, ais328dq_ble_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of ble in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais328dq_data_format_get(stmdev_ctx_t *ctx, ais328dq_ble_t *val)
+int32_t ais328dq_data_format_get(stmdev_ctx_t *ctx,
+ ais328dq_ble_t *val)
{
ais328dq_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
switch (ctrl_reg4.ble)
{
case AIS328DQ_LSB_AT_LOW_ADD:
*val = AIS328DQ_LSB_AT_LOW_ADD;
break;
+
case AIS328DQ_MSB_AT_LOW_ADD:
*val = AIS328DQ_MSB_AT_LOW_ADD;
break;
+
default:
*val = AIS328DQ_LSB_AT_LOW_ADD;
break;
@@ -711,19 +816,25 @@ int32_t ais328dq_data_format_get(stmdev_ctx_t *ctx, ais328dq_ble_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of hpcf in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais328dq_hp_bandwidth_set(stmdev_ctx_t *ctx, ais328dq_hpcf_t val)
+int32_t ais328dq_hp_bandwidth_set(stmdev_ctx_t *ctx,
+ ais328dq_hpcf_t val)
{
ais328dq_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0) {
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpcf = (uint8_t)val;
ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -732,30 +843,36 @@ int32_t ais328dq_hp_bandwidth_set(stmdev_ctx_t *ctx, ais328dq_hpcf_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of hpcf in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_hp_bandwidth_get(stmdev_ctx_t *ctx,
- ais328dq_hpcf_t *val)
+ ais328dq_hpcf_t *val)
{
ais328dq_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
switch (ctrl_reg2.hpcf)
{
case AIS328DQ_CUT_OFF_8Hz:
*val = AIS328DQ_CUT_OFF_8Hz;
break;
+
case AIS328DQ_CUT_OFF_16Hz:
*val = AIS328DQ_CUT_OFF_16Hz;
break;
+
case AIS328DQ_CUT_OFF_32Hz:
*val = AIS328DQ_CUT_OFF_32Hz;
break;
+
case AIS328DQ_CUT_OFF_64Hz:
*val = AIS328DQ_CUT_OFF_64Hz;
break;
+
default:
*val = AIS328DQ_CUT_OFF_8Hz;
break;
@@ -769,6 +886,7 @@ int32_t ais328dq_hp_bandwidth_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of hpen in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_hp_path_set(stmdev_ctx_t *ctx, ais328dq_hpen_t val)
@@ -776,13 +894,17 @@ int32_t ais328dq_hp_path_set(stmdev_ctx_t *ctx, ais328dq_hpen_t val)
ais328dq_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0) {
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpen = (uint8_t)val & 0x03U;
ctrl_reg2.fds = ((uint8_t)val & 0x04U) >> 2;
ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -791,6 +913,7 @@ int32_t ais328dq_hp_path_set(stmdev_ctx_t *ctx, ais328dq_hpen_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of hpen in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_hp_path_get(stmdev_ctx_t *ctx, ais328dq_hpen_t *val)
@@ -798,38 +921,48 @@ int32_t ais328dq_hp_path_get(stmdev_ctx_t *ctx, ais328dq_hpen_t *val)
ais328dq_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
- switch ( (ctrl_reg2.fds << 2) + ctrl_reg2.hpen )
+ switch ((ctrl_reg2.fds << 2) + ctrl_reg2.hpen)
{
case AIS328DQ_HP_DISABLE:
*val = AIS328DQ_HP_DISABLE;
break;
+
case AIS328DQ_HP_ON_OUT:
*val = AIS328DQ_HP_ON_OUT;
break;
+
case AIS328DQ_HP_ON_INT1:
*val = AIS328DQ_HP_ON_INT1;
break;
+
case AIS328DQ_HP_ON_INT2:
*val = AIS328DQ_HP_ON_INT2;
break;
+
case AIS328DQ_HP_ON_INT1_INT2:
*val = AIS328DQ_HP_ON_INT1_INT2;
break;
+
case AIS328DQ_HP_ON_INT1_INT2_OUT:
*val = AIS328DQ_HP_ON_INT1_INT2_OUT;
break;
+
case AIS328DQ_HP_ON_INT2_OUT:
*val = AIS328DQ_HP_ON_INT2_OUT;
break;
+
case AIS328DQ_HP_ON_INT1_OUT:
*val = AIS328DQ_HP_ON_INT1_OUT;
break;
+
default:
*val = AIS328DQ_HP_DISABLE;
break;
}
+
return ret;
}
@@ -842,14 +975,17 @@ int32_t ais328dq_hp_path_get(stmdev_ctx_t *ctx, ais328dq_hpen_t *val)
* filter.[get]
*
* @param ctx read / write interface definitions(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_hp_reset_get(stmdev_ctx_t *ctx)
{
uint8_t dummy;
int32_t ret;
+
ret = ais328dq_read_reg(ctx, AIS328DQ_HP_FILTER_RESET,
- (uint8_t*)&dummy, 1);
+ (uint8_t *)&dummy, 1);
+
return ret;
}
@@ -858,12 +994,16 @@ int32_t ais328dq_hp_reset_get(stmdev_ctx_t *ctx)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ref in reg REFERENCE
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais328dq_hp_reference_value_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ais328dq_hp_reference_value_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
int32_t ret;
- ret = ais328dq_write_reg(ctx, AIS328DQ_REFERENCE, (uint8_t*)&val, 1);
+
+ ret = ais328dq_write_reg(ctx, AIS328DQ_REFERENCE, (uint8_t *)&val, 1);
+
return ret;
}
@@ -872,12 +1012,16 @@ int32_t ais328dq_hp_reference_value_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ref in reg REFERENCE
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais328dq_hp_reference_value_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ais328dq_hp_reference_value_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
int32_t ret;
+
ret = ais328dq_read_reg(ctx, AIS328DQ_REFERENCE, val, 1);
+
return ret;
}
@@ -899,6 +1043,7 @@ int32_t ais328dq_hp_reference_value_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of sim in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_spi_mode_set(stmdev_ctx_t *ctx, ais328dq_sim_t val)
@@ -906,12 +1051,16 @@ int32_t ais328dq_spi_mode_set(stmdev_ctx_t *ctx, ais328dq_sim_t val)
ais328dq_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0) {
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.sim = (uint8_t)val;
ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -920,6 +1069,7 @@ int32_t ais328dq_spi_mode_set(stmdev_ctx_t *ctx, ais328dq_sim_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of sim in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_spi_mode_get(stmdev_ctx_t *ctx, ais328dq_sim_t *val)
@@ -927,16 +1077,19 @@ int32_t ais328dq_spi_mode_get(stmdev_ctx_t *ctx, ais328dq_sim_t *val)
ais328dq_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
- switch ( ctrl_reg4.sim )
+ switch (ctrl_reg4.sim)
{
case AIS328DQ_SPI_4_WIRE:
*val = AIS328DQ_SPI_4_WIRE;
break;
+
case AIS328DQ_SPI_3_WIRE:
*val = AIS328DQ_SPI_3_WIRE;
break;
+
default:
*val = AIS328DQ_SPI_4_WIRE;
break;
@@ -963,20 +1116,25 @@ int32_t ais328dq_spi_mode_get(stmdev_ctx_t *ctx, ais328dq_sim_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of i1_cfg in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_pin_int1_route_set(stmdev_ctx_t *ctx,
- ais328dq_i1_cfg_t val)
+ ais328dq_i1_cfg_t val)
{
ais328dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.i1_cfg = (uint8_t)val;
ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -985,30 +1143,36 @@ int32_t ais328dq_pin_int1_route_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of i1_cfg in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_pin_int1_route_get(stmdev_ctx_t *ctx,
- ais328dq_i1_cfg_t *val)
+ ais328dq_i1_cfg_t *val)
{
ais328dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.i1_cfg )
+ switch (ctrl_reg3.i1_cfg)
{
case AIS328DQ_PAD1_INT1_SRC:
*val = AIS328DQ_PAD1_INT1_SRC;
break;
+
case AIS328DQ_PAD1_INT1_OR_INT2_SRC:
*val = AIS328DQ_PAD1_INT1_OR_INT2_SRC;
break;
+
case AIS328DQ_PAD1_DRDY:
*val = AIS328DQ_PAD1_DRDY;
break;
+
case AIS328DQ_PAD1_BOOT:
*val = AIS328DQ_PAD1_BOOT;
break;
+
default:
*val = AIS328DQ_PAD1_INT1_SRC;
break;
@@ -1023,20 +1187,25 @@ int32_t ais328dq_pin_int1_route_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of lir1 in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int1_notification_set(stmdev_ctx_t *ctx,
- ais328dq_lir1_t val)
+ ais328dq_lir1_t val)
{
ais328dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.lir1 = (uint8_t)val;
ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1046,24 +1215,28 @@ int32_t ais328dq_int1_notification_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of lir1 in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int1_notification_get(stmdev_ctx_t *ctx,
- ais328dq_lir1_t *val)
+ ais328dq_lir1_t *val)
{
ais328dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.lir1 )
+ switch (ctrl_reg3.lir1)
{
case AIS328DQ_INT1_PULSED:
*val = AIS328DQ_INT1_PULSED;
break;
+
case AIS328DQ_INT1_LATCHED:
*val = AIS328DQ_INT1_LATCHED;
break;
+
default:
*val = AIS328DQ_INT1_PULSED;
break;
@@ -1077,20 +1250,25 @@ int32_t ais328dq_int1_notification_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of i2_cfg in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_pin_int2_route_set(stmdev_ctx_t *ctx,
- ais328dq_i2_cfg_t val)
+ ais328dq_i2_cfg_t val)
{
ais328dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.i2_cfg = (uint8_t)val;
ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1099,30 +1277,36 @@ int32_t ais328dq_pin_int2_route_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of i2_cfg in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_pin_int2_route_get(stmdev_ctx_t *ctx,
- ais328dq_i2_cfg_t *val)
+ ais328dq_i2_cfg_t *val)
{
ais328dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.i2_cfg )
+ switch (ctrl_reg3.i2_cfg)
{
case AIS328DQ_PAD2_INT2_SRC:
*val = AIS328DQ_PAD2_INT2_SRC;
break;
+
case AIS328DQ_PAD2_INT1_OR_INT2_SRC:
*val = AIS328DQ_PAD2_INT1_OR_INT2_SRC;
break;
+
case AIS328DQ_PAD2_DRDY:
*val = AIS328DQ_PAD2_DRDY;
break;
+
case AIS328DQ_PAD2_BOOT:
*val = AIS328DQ_PAD2_BOOT;
break;
+
default:
*val = AIS328DQ_PAD2_INT2_SRC;
break;
@@ -1137,20 +1321,25 @@ int32_t ais328dq_pin_int2_route_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of lir2 in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int2_notification_set(stmdev_ctx_t *ctx,
- ais328dq_lir2_t val)
+ ais328dq_lir2_t val)
{
ais328dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.lir2 = (uint8_t)val;
ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1160,24 +1349,28 @@ int32_t ais328dq_int2_notification_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of lir2 in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int2_notification_get(stmdev_ctx_t *ctx,
- ais328dq_lir2_t *val)
+ ais328dq_lir2_t *val)
{
ais328dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.lir2 )
+ switch (ctrl_reg3.lir2)
{
case AIS328DQ_INT2_PULSED:
*val = AIS328DQ_INT2_PULSED;
break;
+
case AIS328DQ_INT2_LATCHED:
*val = AIS328DQ_INT2_LATCHED;
break;
+
default:
*val = AIS328DQ_INT2_PULSED;
break;
@@ -1191,6 +1384,7 @@ int32_t ais328dq_int2_notification_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of pp_od in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_pin_mode_set(stmdev_ctx_t *ctx, ais328dq_pp_od_t val)
@@ -1198,12 +1392,16 @@ int32_t ais328dq_pin_mode_set(stmdev_ctx_t *ctx, ais328dq_pp_od_t val)
ais328dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.pp_od = (uint8_t)val;
ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1212,23 +1410,28 @@ int32_t ais328dq_pin_mode_set(stmdev_ctx_t *ctx, ais328dq_pp_od_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of pp_od in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais328dq_pin_mode_get(stmdev_ctx_t *ctx, ais328dq_pp_od_t *val)
+int32_t ais328dq_pin_mode_get(stmdev_ctx_t *ctx,
+ ais328dq_pp_od_t *val)
{
ais328dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.pp_od )
+ switch (ctrl_reg3.pp_od)
{
case AIS328DQ_PUSH_PULL:
*val = AIS328DQ_PUSH_PULL;
break;
+
case AIS328DQ_OPEN_DRAIN:
*val = AIS328DQ_OPEN_DRAIN;
break;
+
default:
*val = AIS328DQ_PUSH_PULL;
break;
@@ -1242,19 +1445,25 @@ int32_t ais328dq_pin_mode_get(stmdev_ctx_t *ctx, ais328dq_pp_od_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ihl in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais328dq_pin_polarity_set(stmdev_ctx_t *ctx, ais328dq_ihl_t val)
+int32_t ais328dq_pin_polarity_set(stmdev_ctx_t *ctx,
+ ais328dq_ihl_t val)
{
ais328dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.ihl = (uint8_t)val;
ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1263,23 +1472,28 @@ int32_t ais328dq_pin_polarity_set(stmdev_ctx_t *ctx, ais328dq_ihl_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of ihl in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais328dq_pin_polarity_get(stmdev_ctx_t *ctx, ais328dq_ihl_t *val)
+int32_t ais328dq_pin_polarity_get(stmdev_ctx_t *ctx,
+ ais328dq_ihl_t *val)
{
ais328dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.ihl )
+ switch (ctrl_reg3.ihl)
{
case AIS328DQ_ACTIVE_HIGH:
*val = AIS328DQ_ACTIVE_HIGH;
break;
+
case AIS328DQ_ACTIVE_LOW:
*val = AIS328DQ_ACTIVE_LOW;
break;
+
default:
*val = AIS328DQ_ACTIVE_HIGH;
break;
@@ -1306,16 +1520,19 @@ int32_t ais328dq_pin_polarity_get(stmdev_ctx_t *ctx, ais328dq_ihl_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val enable sign and axis for interrupt on threshold
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int1_on_threshold_conf_set(stmdev_ctx_t *ctx,
- ais328dq_int1_on_th_conf_t val)
+ ais328dq_int1_on_th_conf_t val)
{
ais328dq_int1_cfg_t int1_cfg;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_CFG, (uint8_t*)&int1_cfg, 1);
- if(ret == 0) {
+ ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
+
+ if (ret == 0)
+ {
int1_cfg.xlie = val.int1_xlie;
int1_cfg.xhie = val.int1_xhie;
int1_cfg.ylie = val.int1_ylie;
@@ -1323,8 +1540,9 @@ int32_t ais328dq_int1_on_threshold_conf_set(stmdev_ctx_t *ctx,
int1_cfg.zlie = val.int1_zlie;
int1_cfg.zhie = val.int1_zhie;
ret = ais328dq_write_reg(ctx, AIS328DQ_INT1_CFG,
- (uint8_t*)&int1_cfg, 1);
+ (uint8_t *)&int1_cfg, 1);
}
+
return ret;
}
@@ -1333,15 +1551,16 @@ int32_t ais328dq_int1_on_threshold_conf_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val enable sign and axis for interrupt on threshold
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int1_on_threshold_conf_get(stmdev_ctx_t *ctx,
- ais328dq_int1_on_th_conf_t *val)
+ ais328dq_int1_on_th_conf_t *val)
{
ais328dq_int1_cfg_t int1_cfg;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_CFG, (uint8_t*)&int1_cfg, 1);
+ ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
val->int1_xlie = int1_cfg.xlie;
val->int1_xhie = int1_cfg.xhie;
val->int1_ylie = int1_cfg.ylie;
@@ -1357,20 +1576,24 @@ int32_t ais328dq_int1_on_threshold_conf_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of aoi in reg INT1_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int1_on_threshold_mode_set(stmdev_ctx_t *ctx,
- ais328dq_int1_aoi_t val)
+ ais328dq_int1_aoi_t val)
{
ais328dq_int1_cfg_t int1_cfg;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_CFG, (uint8_t*)&int1_cfg, 1);
- if(ret == 0) {
+ ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
+
+ if (ret == 0)
+ {
int1_cfg.aoi = (uint8_t) val;
ret = ais328dq_write_reg(ctx, AIS328DQ_INT1_CFG,
- (uint8_t*)&int1_cfg, 1);
+ (uint8_t *)&int1_cfg, 1);
}
+
return ret;
}
@@ -1379,24 +1602,27 @@ int32_t ais328dq_int1_on_threshold_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of aoi in reg INT1_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int1_on_threshold_mode_get(stmdev_ctx_t *ctx,
- ais328dq_int1_aoi_t *val)
+ ais328dq_int1_aoi_t *val)
{
ais328dq_int1_cfg_t int1_cfg;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_CFG, (uint8_t*)&int1_cfg, 1);
+ ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
- switch ( int1_cfg.aoi )
+ switch (int1_cfg.aoi)
{
case AIS328DQ_INT1_ON_THRESHOLD_OR:
*val = AIS328DQ_INT1_ON_THRESHOLD_OR;
break;
+
case AIS328DQ_INT1_ON_THRESHOLD_AND:
*val = AIS328DQ_INT1_ON_THRESHOLD_AND;
break;
+
default:
*val = AIS328DQ_INT1_ON_THRESHOLD_OR;
break;
@@ -1410,13 +1636,16 @@ int32_t ais328dq_int1_on_threshold_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val registers INT1_SRC
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int1_src_get(stmdev_ctx_t *ctx,
- ais328dq_int1_src_t *val)
+ ais328dq_int1_src_t *val)
{
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_SRC, (uint8_t*) val, 1);
+
+ ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_SRC, (uint8_t *) val, 1);
+
return ret;
}
@@ -1425,6 +1654,7 @@ int32_t ais328dq_int1_src_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ths in reg INT1_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1432,12 +1662,15 @@ int32_t ais328dq_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
ais328dq_int1_ths_t int1_ths;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_THS, (uint8_t*)&int1_ths, 1);
- if(ret == 0) {
+ ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_THS, (uint8_t *)&int1_ths, 1);
+
+ if (ret == 0)
+ {
int1_ths.ths = val;
ret = ais328dq_write_reg(ctx, AIS328DQ_INT1_THS,
- (uint8_t*)&int1_ths, 1);
+ (uint8_t *)&int1_ths, 1);
}
+
return ret;
}
@@ -1446,6 +1679,7 @@ int32_t ais328dq_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ths in reg INT1_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1453,7 +1687,7 @@ int32_t ais328dq_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
ais328dq_int1_ths_t int1_ths;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_THS, (uint8_t*)&int1_ths, 1);
+ ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_THS, (uint8_t *)&int1_ths, 1);
*val = int1_ths.ths;
return ret;
@@ -1464,6 +1698,7 @@ int32_t ais328dq_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of d in reg INT1_DURATION
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1472,12 +1707,15 @@ int32_t ais328dq_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_DURATION,
- (uint8_t*)&int1_duration, 1);
- if(ret == 0) {
+ (uint8_t *)&int1_duration, 1);
+
+ if (ret == 0)
+ {
int1_duration.d = val;
ret = ais328dq_write_reg(ctx, AIS328DQ_INT1_DURATION,
- (uint8_t*)&int1_duration, 1);
+ (uint8_t *)&int1_duration, 1);
}
+
return ret;
}
@@ -1486,6 +1724,7 @@ int32_t ais328dq_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of d in reg INT1_DURATION
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1494,7 +1733,7 @@ int32_t ais328dq_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_DURATION,
- (uint8_t*)&int1_duration, 1);
+ (uint8_t *)&int1_duration, 1);
*val = int1_duration.d;
return ret;
@@ -1505,17 +1744,20 @@ int32_t ais328dq_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val enable sign and axis for interrupt on threshold
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int2_on_threshold_conf_set(stmdev_ctx_t *ctx,
- ais328dq_int2_on_th_conf_t val)
+ ais328dq_int2_on_th_conf_t val)
{
ais328dq_int2_cfg_t int2_cfg;
int32_t ret;
ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_CFG,
- (uint8_t*)&int2_cfg, 1);
- if(ret == 0) {
+ (uint8_t *)&int2_cfg, 1);
+
+ if (ret == 0)
+ {
int2_cfg.xlie = val.int2_xlie;
int2_cfg.xhie = val.int2_xhie;
int2_cfg.ylie = val.int2_ylie;
@@ -1523,8 +1765,9 @@ int32_t ais328dq_int2_on_threshold_conf_set(stmdev_ctx_t *ctx,
int2_cfg.zlie = val.int2_zlie;
int2_cfg.zhie = val.int2_zhie;
ret = ais328dq_write_reg(ctx, AIS328DQ_INT2_CFG,
- (uint8_t*)&int2_cfg, 1);
+ (uint8_t *)&int2_cfg, 1);
}
+
return ret;
}
@@ -1533,15 +1776,16 @@ int32_t ais328dq_int2_on_threshold_conf_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val enable sign and axis for interrupt on threshold
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int2_on_threshold_conf_get(stmdev_ctx_t *ctx,
- ais328dq_int2_on_th_conf_t *val)
+ ais328dq_int2_on_th_conf_t *val)
{
ais328dq_int2_cfg_t int2_cfg;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_CFG, (uint8_t*)&int2_cfg, 1);
+ ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1);
val->int2_xlie = int2_cfg.xlie;
val->int2_xhie = int2_cfg.xhie;
val->int2_ylie = int2_cfg.ylie;
@@ -1557,20 +1801,24 @@ int32_t ais328dq_int2_on_threshold_conf_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of aoi in reg INT2_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int2_on_threshold_mode_set(stmdev_ctx_t *ctx,
- ais328dq_int2_aoi_t val)
+ ais328dq_int2_aoi_t val)
{
ais328dq_int2_cfg_t int2_cfg;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_CFG, (uint8_t*)&int2_cfg, 1);
- if(ret == 0) {
+ ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1);
+
+ if (ret == 0)
+ {
int2_cfg.aoi = (uint8_t) val;
ret = ais328dq_write_reg(ctx, AIS328DQ_INT2_CFG,
- (uint8_t*)&int2_cfg, 1);
+ (uint8_t *)&int2_cfg, 1);
}
+
return ret;
}
@@ -1579,24 +1827,27 @@ int32_t ais328dq_int2_on_threshold_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of aoi in reg INT2_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int2_on_threshold_mode_get(stmdev_ctx_t *ctx,
- ais328dq_int2_aoi_t *val)
+ ais328dq_int2_aoi_t *val)
{
ais328dq_int2_cfg_t int2_cfg;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_CFG, (uint8_t*)&int2_cfg, 1);
+ ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1);
- switch ( int2_cfg.aoi )
+ switch (int2_cfg.aoi)
{
case AIS328DQ_INT2_ON_THRESHOLD_OR:
*val = AIS328DQ_INT2_ON_THRESHOLD_OR;
break;
+
case AIS328DQ_INT2_ON_THRESHOLD_AND:
*val = AIS328DQ_INT2_ON_THRESHOLD_AND;
break;
+
default:
*val = AIS328DQ_INT2_ON_THRESHOLD_OR;
break;
@@ -1610,13 +1861,16 @@ int32_t ais328dq_int2_on_threshold_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val registers INT2_SRC
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int2_src_get(stmdev_ctx_t *ctx,
- ais328dq_int2_src_t *val)
+ ais328dq_int2_src_t *val)
{
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_SRC, (uint8_t*) val, 1);
+
+ ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_SRC, (uint8_t *) val, 1);
+
return ret;
}
@@ -1625,6 +1879,7 @@ int32_t ais328dq_int2_src_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ths in reg INT2_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1632,12 +1887,15 @@ int32_t ais328dq_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
ais328dq_int2_ths_t int2_ths;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_THS, (uint8_t*)&int2_ths, 1);
- if(ret == 0) {
+ ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_THS, (uint8_t *)&int2_ths, 1);
+
+ if (ret == 0)
+ {
int2_ths.ths = val;
ret = ais328dq_write_reg(ctx, AIS328DQ_INT2_THS,
- (uint8_t*)&int2_ths, 1);
+ (uint8_t *)&int2_ths, 1);
}
+
return ret;
}
@@ -1646,6 +1904,7 @@ int32_t ais328dq_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ths in reg INT2_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1653,7 +1912,7 @@ int32_t ais328dq_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
ais328dq_int2_ths_t int2_ths;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_THS, (uint8_t*)&int2_ths, 1);
+ ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_THS, (uint8_t *)&int2_ths, 1);
*val = int2_ths.ths;
return ret;
@@ -1664,6 +1923,7 @@ int32_t ais328dq_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of d in reg INT2_DURATION
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1672,12 +1932,15 @@ int32_t ais328dq_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_DURATION,
- (uint8_t*)&int2_duration, 1);
- if(ret == 0) {
+ (uint8_t *)&int2_duration, 1);
+
+ if (ret == 0)
+ {
int2_duration.d = val;
ret = ais328dq_write_reg(ctx, AIS328DQ_INT2_DURATION,
- (uint8_t*)&int2_duration, 1);
+ (uint8_t *)&int2_duration, 1);
}
+
return ret;
}
@@ -1686,6 +1949,7 @@ int32_t ais328dq_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of d in reg INT2_DURATION
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1694,7 +1958,7 @@ int32_t ais328dq_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_DURATION,
- (uint8_t*)&int2_duration, 1);
+ (uint8_t *)&int2_duration, 1);
*val = int2_duration.d;
return ret;
@@ -1718,6 +1982,7 @@ int32_t ais328dq_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of turnon in reg CTRL_REG5
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1725,12 +1990,16 @@ int32_t ais328dq_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val)
ais328dq_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if(ret == 0) {
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.turnon = val;
ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG5,
- (uint8_t*)&ctrl_reg5, 1);
+ (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -1739,6 +2008,7 @@ int32_t ais328dq_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of turnon in reg CTRL_REG5
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1746,7 +2016,8 @@ int32_t ais328dq_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val)
ais328dq_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
*val = ctrl_reg5.turnon;
return ret;
@@ -1770,20 +2041,24 @@ int32_t ais328dq_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of 6d in reg INT1_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int1_6d_mode_set(stmdev_ctx_t *ctx,
- ais328dq_int1_6d_t val)
+ ais328dq_int1_6d_t val)
{
ais328dq_int1_cfg_t int1_cfg;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_CFG, (uint8_t*)&int1_cfg, 1);
- if(ret == 0) {
+ ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
+
+ if (ret == 0)
+ {
int1_cfg._6d = (uint8_t)val & 0x01U;
int1_cfg.aoi = ((uint8_t)val & 0x02U) >> 1;
- ret = ais328dq_write_reg(ctx, AIS328DQ_INT1_CFG, (uint8_t*)&int1_cfg, 1);
+ ret = ais328dq_write_reg(ctx, AIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
}
+
return ret;
}
@@ -1792,27 +2067,31 @@ int32_t ais328dq_int1_6d_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of 6d in reg INT1_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int1_6d_mode_get(stmdev_ctx_t *ctx,
- ais328dq_int1_6d_t *val)
+ ais328dq_int1_6d_t *val)
{
ais328dq_int1_cfg_t int1_cfg;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_CFG, (uint8_t*)&int1_cfg, 1);
+ ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
switch ((int1_cfg.aoi << 1) + int1_cfg._6d)
{
case AIS328DQ_6D_INT1_DISABLE:
*val = AIS328DQ_6D_INT1_DISABLE;
break;
+
case AIS328DQ_6D_INT1_MOVEMENT:
*val = AIS328DQ_6D_INT1_MOVEMENT;
break;
- case AIS328DQ_6D_INT1_POSITION:
+
+ case AIS328DQ_6D_INT1_POSITION:
*val = AIS328DQ_6D_INT1_POSITION;
break;
+
default:
*val = AIS328DQ_6D_INT1_DISABLE;
break;
@@ -1826,13 +2105,16 @@ int32_t ais328dq_int1_6d_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val registers INT1_SRC
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int1_6d_src_get(stmdev_ctx_t *ctx,
- ais328dq_int1_src_t *val)
+ ais328dq_int1_src_t *val)
{
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_SRC, (uint8_t*) val, 1);
+
+ ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_SRC, (uint8_t *) val, 1);
+
return ret;
}
@@ -1841,6 +2123,7 @@ int32_t ais328dq_int1_6d_src_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ths in reg INT1_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int1_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1848,11 +2131,14 @@ int32_t ais328dq_int1_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
ais328dq_int1_ths_t int1_ths;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_THS, (uint8_t*)&int1_ths, 1);
- if(ret == 0) {
+ ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_THS, (uint8_t *)&int1_ths, 1);
+
+ if (ret == 0)
+ {
int1_ths.ths = val;
- ret = ais328dq_write_reg(ctx, AIS328DQ_INT1_THS, (uint8_t*)&int1_ths, 1);
+ ret = ais328dq_write_reg(ctx, AIS328DQ_INT1_THS, (uint8_t *)&int1_ths, 1);
}
+
return ret;
}
@@ -1861,6 +2147,7 @@ int32_t ais328dq_int1_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ths in reg INT1_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int1_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1868,7 +2155,7 @@ int32_t ais328dq_int1_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
ais328dq_int1_ths_t int1_ths;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_THS, (uint8_t*)&int1_ths, 1);
+ ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_THS, (uint8_t *)&int1_ths, 1);
*val = int1_ths.ths;
return ret;
@@ -1879,21 +2166,25 @@ int32_t ais328dq_int1_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of 6d in reg INT2_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int2_6d_mode_set(stmdev_ctx_t *ctx,
- ais328dq_int2_6d_t val)
+ ais328dq_int2_6d_t val)
{
ais328dq_int2_cfg_t int2_cfg;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_CFG, (uint8_t*)&int2_cfg, 1);
- if(ret == 0) {
+ ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1);
+
+ if (ret == 0)
+ {
int2_cfg._6d = (uint8_t)val & 0x01U;
int2_cfg.aoi = ((uint8_t)val & 0x02U) >> 1;
ret = ais328dq_write_reg(ctx, AIS328DQ_INT2_CFG,
- (uint8_t*)&int2_cfg, 1);
+ (uint8_t *)&int2_cfg, 1);
}
+
return ret;
}
@@ -1902,27 +2193,31 @@ int32_t ais328dq_int2_6d_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of 6d in reg INT2_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int2_6d_mode_get(stmdev_ctx_t *ctx,
- ais328dq_int2_6d_t *val)
+ ais328dq_int2_6d_t *val)
{
ais328dq_int2_cfg_t int2_cfg;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_CFG, (uint8_t*)&int2_cfg, 1);
+ ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1);
switch ((int2_cfg.aoi << 1) + int2_cfg._6d)
{
case AIS328DQ_6D_INT2_DISABLE:
*val = AIS328DQ_6D_INT2_DISABLE;
break;
+
case AIS328DQ_6D_INT2_MOVEMENT:
*val = AIS328DQ_6D_INT2_MOVEMENT;
break;
- case AIS328DQ_6D_INT2_POSITION:
+
+ case AIS328DQ_6D_INT2_POSITION:
*val = AIS328DQ_6D_INT2_POSITION;
break;
+
default:
*val = AIS328DQ_6D_INT2_DISABLE;
break;
@@ -1936,13 +2231,16 @@ int32_t ais328dq_int2_6d_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val registers INT2_SRC
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int2_6d_src_get(stmdev_ctx_t *ctx,
- ais328dq_int2_src_t *val)
+ ais328dq_int2_src_t *val)
{
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_SRC, (uint8_t*) val, 1);
+
+ ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_SRC, (uint8_t *) val, 1);
+
return ret;
}
@@ -1951,6 +2249,7 @@ int32_t ais328dq_int2_6d_src_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ths in reg INT2_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int2_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1958,12 +2257,15 @@ int32_t ais328dq_int2_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
ais328dq_int2_ths_t int2_ths;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_THS, (uint8_t*)&int2_ths, 1);
- if(ret == 0) {
+ ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_THS, (uint8_t *)&int2_ths, 1);
+
+ if (ret == 0)
+ {
int2_ths.ths = val;
ret = ais328dq_write_reg(ctx, AIS328DQ_INT2_THS,
- (uint8_t*)&int2_ths, 1);
+ (uint8_t *)&int2_ths, 1);
}
+
return ret;
}
@@ -1972,6 +2274,7 @@ int32_t ais328dq_int2_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ths in reg INT2_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais328dq_int2_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1979,7 +2282,7 @@ int32_t ais328dq_int2_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
ais328dq_int2_ths_t int2_ths;
int32_t ret;
- ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_THS, (uint8_t*)&int2_ths, 1);
+ ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_THS, (uint8_t *)&int2_ths, 1);
*val = int2_ths.ths;
return ret;
diff --git a/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.h b/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.h
index 8dafa488daec77e6c281a1e462fe266e9ae2ffad..fb14038d6c75789babcbe5cc8a02cd7f8f9336d4 100644
--- a/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.h
+++ b/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file ais328dq_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * ais328dq_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file ais328dq_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * ais328dq_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef AIS328DQ_REGS_H
#define AIS328DQ_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup AIS328DQ
@@ -74,7 +75,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -107,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -131,7 +134,7 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
+ * You can create a sensor configuration by your own or using
* Unico / Unicleo tools available on STMicroelectronics
* web site.
*
@@ -139,7 +142,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -188,9 +192,9 @@ typedef struct {
*
*/
-#define AIS328DQ_FROM_FS_2g_TO_mg(lsb) (float)( (lsb >> 4 ) * 0.98f )
-#define AIS328DQ_FROM_FS_4g_TO_mg(lsb) (float)( (lsb >> 4 ) * 1.95f )
-#define AIS328DQ_FROM_FS_8g_TO_mg(lsb) (float)( (lsb >> 4 ) * 3.91f )
+#define AIS328DQ_FROM_FS_2g_TO_mg(lsb) (float_t)( (lsb >> 4 ) * 0.98f )
+#define AIS328DQ_FROM_FS_4g_TO_mg(lsb) (float_t)( (lsb >> 4 ) * 1.95f )
+#define AIS328DQ_FROM_FS_8g_TO_mg(lsb) (float_t)( (lsb >> 4 ) * 3.91f )
/**
* @}
@@ -199,7 +203,8 @@ typedef struct {
#define AIS328DQ_WHO_AM_I 0x0FU
#define AIS328DQ_CTRL_REG1 0x20U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xen : 1;
uint8_t yen : 1;
@@ -216,7 +221,8 @@ typedef struct {
} ais328dq_ctrl_reg1_t;
#define AIS328DQ_CTRL_REG2 0x21U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t hpcf : 2;
uint8_t hpen : 2;
@@ -233,7 +239,8 @@ typedef struct {
} ais328dq_ctrl_reg2_t;
#define AIS328DQ_CTRL_REG3 0x22U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t i1_cfg : 2;
uint8_t lir1 : 1;
@@ -252,7 +259,8 @@ typedef struct {
} ais328dq_ctrl_reg3_t;
#define AIS328DQ_CTRL_REG4 0x23U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t st : 3; /* STsign + ST */
@@ -269,7 +277,8 @@ typedef struct {
} ais328dq_ctrl_reg4_t;
#define AIS328DQ_CTRL_REG5 0x24U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t turnon : 2;
uint8_t not_used_01 : 6;
@@ -282,7 +291,8 @@ typedef struct {
#define AIS328DQ_HP_FILTER_RESET 0x25U
#define AIS328DQ_REFERENCE 0x26U
#define AIS328DQ_STATUS_REG 0x27U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xda : 1;
uint8_t yda : 1;
@@ -311,7 +321,8 @@ typedef struct {
#define AIS328DQ_OUT_Z_L 0x2CU
#define AIS328DQ_OUT_Z_H 0x2DU
#define AIS328DQ_INT1_CFG 0x30U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlie : 1;
uint8_t xhie : 1;
@@ -334,7 +345,8 @@ typedef struct {
} ais328dq_int1_cfg_t;
#define AIS328DQ_INT1_SRC 0x31U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
@@ -357,7 +369,8 @@ typedef struct {
} ais328dq_int1_src_t;
#define AIS328DQ_INT1_THS 0x32U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t not_used_01 : 1;
@@ -368,7 +381,8 @@ typedef struct {
} ais328dq_int1_ths_t;
#define AIS328DQ_INT1_DURATION 0x33U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d : 7;
uint8_t not_used_01 : 1;
@@ -379,7 +393,8 @@ typedef struct {
} ais328dq_int1_duration_t;
#define AIS328DQ_INT2_CFG 0x34U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlie : 1;
uint8_t xhie : 1;
@@ -402,7 +417,8 @@ typedef struct {
} ais328dq_int2_cfg_t;
#define AIS328DQ_INT2_SRC 0x35U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
@@ -425,7 +441,8 @@ typedef struct {
} ais328dq_int2_src_t;
#define AIS328DQ_INT2_THS 0x36U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t not_used_01 : 1;
@@ -436,7 +453,8 @@ typedef struct {
} ais328dq_int2_ths_t;
#define AIS328DQ_INT2_DURATION 0x37U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d : 7;
uint8_t not_used_01 : 1;
@@ -448,9 +466,9 @@ typedef struct {
/**
* @defgroup AIS328DQ_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -458,7 +476,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
ais328dq_ctrl_reg1_t ctrl_reg1;
ais328dq_ctrl_reg2_t ctrl_reg2;
ais328dq_ctrl_reg3_t ctrl_reg3;
@@ -482,10 +501,12 @@ typedef union{
*
*/
-int32_t ais328dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t ais328dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len);
+int32_t ais328dq_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t ais328dq_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
- uint16_t len);
float_t ais328dq_from_fs2_to_mg(int16_t lsb);
float_t ais328dq_from_fs4_to_mg(int16_t lsb);
@@ -500,7 +521,8 @@ int32_t ais328dq_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t ais328dq_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ais328dq_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
AIS328DQ_ODR_OFF = 0x00,
AIS328DQ_ODR_Hz5 = 0x02,
AIS328DQ_ODR_1Hz = 0x03,
@@ -515,40 +537,47 @@ typedef enum {
int32_t ais328dq_data_rate_set(stmdev_ctx_t *ctx, ais328dq_dr_t val);
int32_t ais328dq_data_rate_get(stmdev_ctx_t *ctx, ais328dq_dr_t *val);
-typedef enum {
+typedef enum
+{
AIS328DQ_NORMAL_MODE = 0,
AIS328DQ_REF_MODE_ENABLE = 1,
} ais328dq_hpm_t;
int32_t ais328dq_reference_mode_set(stmdev_ctx_t *ctx,
- ais328dq_hpm_t val);
+ ais328dq_hpm_t val);
int32_t ais328dq_reference_mode_get(stmdev_ctx_t *ctx,
- ais328dq_hpm_t *val);
+ ais328dq_hpm_t *val);
-typedef enum {
+typedef enum
+{
AIS328DQ_2g = 0,
AIS328DQ_4g = 1,
AIS328DQ_8g = 3,
} ais328dq_fs_t;
int32_t ais328dq_full_scale_set(stmdev_ctx_t *ctx, ais328dq_fs_t val);
-int32_t ais328dq_full_scale_get(stmdev_ctx_t *ctx, ais328dq_fs_t *val);
+int32_t ais328dq_full_scale_get(stmdev_ctx_t *ctx,
+ ais328dq_fs_t *val);
-int32_t ais328dq_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ais328dq_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ais328dq_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ais328dq_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t ais328dq_status_reg_get(stmdev_ctx_t *ctx,
- ais328dq_status_reg_t *val);
+ ais328dq_status_reg_t *val);
int32_t ais328dq_flag_data_ready_get(stmdev_ctx_t *ctx,
- uint8_t *val);
+ uint8_t *val);
-int32_t ais328dq_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t ais328dq_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
int32_t ais328dq_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t ais328dq_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ais328dq_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
AIS328DQ_ST_DISABLE = 0,
AIS328DQ_ST_POSITIVE = 1,
AIS328DQ_ST_NEGATIVE = 5,
@@ -556,25 +585,30 @@ typedef enum {
int32_t ais328dq_self_test_set(stmdev_ctx_t *ctx, ais328dq_st_t val);
int32_t ais328dq_self_test_get(stmdev_ctx_t *ctx, ais328dq_st_t *val);
-typedef enum {
+typedef enum
+{
AIS328DQ_LSB_AT_LOW_ADD = 0,
AIS328DQ_MSB_AT_LOW_ADD = 1,
} ais328dq_ble_t;
-int32_t ais328dq_data_format_set(stmdev_ctx_t *ctx, ais328dq_ble_t val);
-int32_t ais328dq_data_format_get(stmdev_ctx_t *ctx, ais328dq_ble_t *val);
+int32_t ais328dq_data_format_set(stmdev_ctx_t *ctx,
+ ais328dq_ble_t val);
+int32_t ais328dq_data_format_get(stmdev_ctx_t *ctx,
+ ais328dq_ble_t *val);
-typedef enum {
+typedef enum
+{
AIS328DQ_CUT_OFF_8Hz = 0,
AIS328DQ_CUT_OFF_16Hz = 1,
AIS328DQ_CUT_OFF_32Hz = 2,
AIS328DQ_CUT_OFF_64Hz = 3,
} ais328dq_hpcf_t;
int32_t ais328dq_hp_bandwidth_set(stmdev_ctx_t *ctx,
- ais328dq_hpcf_t val);
+ ais328dq_hpcf_t val);
int32_t ais328dq_hp_bandwidth_get(stmdev_ctx_t *ctx,
- ais328dq_hpcf_t *val);
+ ais328dq_hpcf_t *val);
-typedef enum {
+typedef enum
+{
AIS328DQ_HP_DISABLE = 0,
AIS328DQ_HP_ON_OUT = 4,
AIS328DQ_HP_ON_INT1 = 1,
@@ -589,73 +623,85 @@ int32_t ais328dq_hp_path_get(stmdev_ctx_t *ctx, ais328dq_hpen_t *val);
int32_t ais328dq_hp_reset_get(stmdev_ctx_t *ctx);
-int32_t ais328dq_hp_reference_value_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ais328dq_hp_reference_value_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ais328dq_hp_reference_value_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ais328dq_hp_reference_value_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
AIS328DQ_SPI_4_WIRE = 0,
AIS328DQ_SPI_3_WIRE = 1,
} ais328dq_sim_t;
int32_t ais328dq_spi_mode_set(stmdev_ctx_t *ctx, ais328dq_sim_t val);
int32_t ais328dq_spi_mode_get(stmdev_ctx_t *ctx, ais328dq_sim_t *val);
-typedef enum {
+typedef enum
+{
AIS328DQ_PAD1_INT1_SRC = 0,
AIS328DQ_PAD1_INT1_OR_INT2_SRC = 1,
AIS328DQ_PAD1_DRDY = 2,
AIS328DQ_PAD1_BOOT = 3,
} ais328dq_i1_cfg_t;
int32_t ais328dq_pin_int1_route_set(stmdev_ctx_t *ctx,
- ais328dq_i1_cfg_t val);
+ ais328dq_i1_cfg_t val);
int32_t ais328dq_pin_int1_route_get(stmdev_ctx_t *ctx,
- ais328dq_i1_cfg_t *val);
+ ais328dq_i1_cfg_t *val);
-typedef enum {
+typedef enum
+{
AIS328DQ_INT1_PULSED = 0,
AIS328DQ_INT1_LATCHED = 1,
} ais328dq_lir1_t;
int32_t ais328dq_int1_notification_set(stmdev_ctx_t *ctx,
- ais328dq_lir1_t val);
+ ais328dq_lir1_t val);
int32_t ais328dq_int1_notification_get(stmdev_ctx_t *ctx,
- ais328dq_lir1_t *val);
+ ais328dq_lir1_t *val);
-typedef enum {
+typedef enum
+{
AIS328DQ_PAD2_INT2_SRC = 0,
AIS328DQ_PAD2_INT1_OR_INT2_SRC = 1,
AIS328DQ_PAD2_DRDY = 2,
AIS328DQ_PAD2_BOOT = 3,
} ais328dq_i2_cfg_t;
int32_t ais328dq_pin_int2_route_set(stmdev_ctx_t *ctx,
- ais328dq_i2_cfg_t val);
+ ais328dq_i2_cfg_t val);
int32_t ais328dq_pin_int2_route_get(stmdev_ctx_t *ctx,
- ais328dq_i2_cfg_t *val);
+ ais328dq_i2_cfg_t *val);
-typedef enum {
+typedef enum
+{
AIS328DQ_INT2_PULSED = 0,
AIS328DQ_INT2_LATCHED = 1,
} ais328dq_lir2_t;
int32_t ais328dq_int2_notification_set(stmdev_ctx_t *ctx,
- ais328dq_lir2_t val);
+ ais328dq_lir2_t val);
int32_t ais328dq_int2_notification_get(stmdev_ctx_t *ctx,
- ais328dq_lir2_t *val);
+ ais328dq_lir2_t *val);
-typedef enum {
+typedef enum
+{
AIS328DQ_PUSH_PULL = 0,
AIS328DQ_OPEN_DRAIN = 1,
} ais328dq_pp_od_t;
-int32_t ais328dq_pin_mode_set(stmdev_ctx_t *ctx, ais328dq_pp_od_t val);
-int32_t ais328dq_pin_mode_get(stmdev_ctx_t *ctx, ais328dq_pp_od_t *val);
+int32_t ais328dq_pin_mode_set(stmdev_ctx_t *ctx,
+ ais328dq_pp_od_t val);
+int32_t ais328dq_pin_mode_get(stmdev_ctx_t *ctx,
+ ais328dq_pp_od_t *val);
-typedef enum {
+typedef enum
+{
AIS328DQ_ACTIVE_HIGH = 0,
AIS328DQ_ACTIVE_LOW = 1,
} ais328dq_ihl_t;
int32_t ais328dq_pin_polarity_set(stmdev_ctx_t *ctx,
- ais328dq_ihl_t val);
+ ais328dq_ihl_t val);
int32_t ais328dq_pin_polarity_get(stmdev_ctx_t *ctx,
- ais328dq_ihl_t *val);
+ ais328dq_ihl_t *val);
-typedef struct {
+typedef struct
+{
uint8_t int1_xlie : 1;
uint8_t int1_xhie : 1;
uint8_t int1_ylie : 1;
@@ -664,21 +710,22 @@ typedef struct {
uint8_t int1_zhie : 1;
} ais328dq_int1_on_th_conf_t;
int32_t ais328dq_int1_on_threshold_conf_set(stmdev_ctx_t *ctx,
- ais328dq_int1_on_th_conf_t val);
+ ais328dq_int1_on_th_conf_t val);
int32_t ais328dq_int1_on_threshold_conf_get(stmdev_ctx_t *ctx,
- ais328dq_int1_on_th_conf_t *val);
+ ais328dq_int1_on_th_conf_t *val);
-typedef enum {
+typedef enum
+{
AIS328DQ_INT1_ON_THRESHOLD_OR = 0,
AIS328DQ_INT1_ON_THRESHOLD_AND = 1,
} ais328dq_int1_aoi_t;
int32_t ais328dq_int1_on_threshold_mode_set(stmdev_ctx_t *ctx,
- ais328dq_int1_aoi_t val);
+ ais328dq_int1_aoi_t val);
int32_t ais328dq_int1_on_threshold_mode_get(stmdev_ctx_t *ctx,
- ais328dq_int1_aoi_t *val);
+ ais328dq_int1_aoi_t *val);
int32_t ais328dq_int1_src_get(stmdev_ctx_t *ctx,
- ais328dq_int1_src_t *val);
+ ais328dq_int1_src_t *val);
int32_t ais328dq_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ais328dq_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -686,7 +733,8 @@ int32_t ais328dq_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t ais328dq_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ais328dq_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef struct {
+typedef struct
+{
uint8_t int2_xlie : 1;
uint8_t int2_xhie : 1;
uint8_t int2_ylie : 1;
@@ -695,21 +743,22 @@ typedef struct {
uint8_t int2_zhie : 1;
} ais328dq_int2_on_th_conf_t;
int32_t ais328dq_int2_on_threshold_conf_set(stmdev_ctx_t *ctx,
- ais328dq_int2_on_th_conf_t val);
+ ais328dq_int2_on_th_conf_t val);
int32_t ais328dq_int2_on_threshold_conf_get(stmdev_ctx_t *ctx,
- ais328dq_int2_on_th_conf_t *val);
+ ais328dq_int2_on_th_conf_t *val);
-typedef enum {
+typedef enum
+{
AIS328DQ_INT2_ON_THRESHOLD_OR = 0,
AIS328DQ_INT2_ON_THRESHOLD_AND = 1,
} ais328dq_int2_aoi_t;
int32_t ais328dq_int2_on_threshold_mode_set(stmdev_ctx_t *ctx,
- ais328dq_int2_aoi_t val);
+ ais328dq_int2_aoi_t val);
int32_t ais328dq_int2_on_threshold_mode_get(stmdev_ctx_t *ctx,
- ais328dq_int2_aoi_t *val);
+ ais328dq_int2_aoi_t *val);
int32_t ais328dq_int2_src_get(stmdev_ctx_t *ctx,
- ais328dq_int2_src_t *val);
+ ais328dq_int2_src_t *val);
int32_t ais328dq_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ais328dq_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -720,37 +769,41 @@ int32_t ais328dq_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t ais328dq_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ais328dq_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
AIS328DQ_6D_INT1_DISABLE = 0,
AIS328DQ_6D_INT1_MOVEMENT = 1,
AIS328DQ_6D_INT1_POSITION = 3,
} ais328dq_int1_6d_t;
int32_t ais328dq_int1_6d_mode_set(stmdev_ctx_t *ctx,
- ais328dq_int1_6d_t val);
+ ais328dq_int1_6d_t val);
int32_t ais328dq_int1_6d_mode_get(stmdev_ctx_t *ctx,
- ais328dq_int1_6d_t *val);
+ ais328dq_int1_6d_t *val);
int32_t ais328dq_int1_6d_src_get(stmdev_ctx_t *ctx,
- ais328dq_int1_src_t *val);
+ ais328dq_int1_src_t *val);
int32_t ais328dq_int1_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ais328dq_int1_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ais328dq_int1_6d_treshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
AIS328DQ_6D_INT2_DISABLE = 0,
AIS328DQ_6D_INT2_MOVEMENT = 1,
AIS328DQ_6D_INT2_POSITION = 3,
} ais328dq_int2_6d_t;
int32_t ais328dq_int2_6d_mode_set(stmdev_ctx_t *ctx,
- ais328dq_int2_6d_t val);
+ ais328dq_int2_6d_t val);
int32_t ais328dq_int2_6d_mode_get(stmdev_ctx_t *ctx,
- ais328dq_int2_6d_t *val);
+ ais328dq_int2_6d_t *val);
int32_t ais328dq_int2_6d_src_get(stmdev_ctx_t *ctx,
- ais328dq_int2_src_t *val);
+ ais328dq_int2_src_t *val);
int32_t ais328dq_int2_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ais328dq_int2_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ais328dq_int2_6d_treshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
/**
*@}
diff --git a/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.c b/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.c
index c47186cb86e35ae81214541ad6bce5fa80d035e8..a6fb76602992ccb9de496a8a8b910216ed1e338c 100644
--- a/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.c
+++ b/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file ais3624dq_reg.c
- * @author Sensors Software Solution Team
- * @brief AIS3624DQ driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file ais3624dq_reg.c
+ * @author Sensors Software Solution Team
+ * @brief AIS3624DQ driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "ais3624dq_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais3624dq_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t ais3624dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t ais3624dq_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais3624dq_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t ais3624dq_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -77,7 +83,7 @@ int32_t ais3624dq_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
*
*/
- /**
+/**
* @defgroup AIS3624DQ_Sensitivity
* @brief These functions convert raw-data into engineering units.
* @{
@@ -86,17 +92,17 @@ int32_t ais3624dq_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
float_t ais3624dq_from_fs6_to_mg(int16_t lsb)
{
- return ((float)lsb * 2.9f / 16.0f);
+ return ((float_t)lsb * 2.9f / 16.0f);
}
float_t ais3624dq_from_fs12_to_mg(int16_t lsb)
{
- return ((float)lsb * 5.9f / 16.0f);
+ return ((float_t)lsb * 5.9f / 16.0f);
}
float_t ais3624dq_from_fs24_to_mg(int16_t lsb)
{
- return ((float)lsb * 11.7f / 16.0f);
+ return ((float_t)lsb * 11.7f / 16.0f);
}
/**
@@ -115,8 +121,9 @@ float_t ais3624dq_from_fs24_to_mg(int16_t lsb)
/**
* @brief X axis enable/disable.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of xen in reg CTRL_REG1
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of xen in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -124,20 +131,25 @@ int32_t ais3624dq_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val)
ais3624dq_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0) {
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.xen = val;
ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
/**
* @brief X axis enable/disable.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of xen in reg CTRL_REG1
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of xen in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -145,7 +157,8 @@ int32_t ais3624dq_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val)
ais3624dq_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
*val = ctrl_reg1.xen;
return ret;
@@ -154,8 +167,9 @@ int32_t ais3624dq_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @brief Y axis enable/disable.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of yen in reg CTRL_REG1
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of yen in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -163,20 +177,25 @@ int32_t ais3624dq_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val)
ais3624dq_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0) {
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.yen = val;
ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
/**
* @brief Y axis enable/disable.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of yen in reg CTRL_REG1
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of yen in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -184,7 +203,8 @@ int32_t ais3624dq_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val)
ais3624dq_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
*val = ctrl_reg1.yen;
return ret;
@@ -193,8 +213,9 @@ int32_t ais3624dq_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @brief Z axis enable/disable.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of zen in reg CTRL_REG1
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of zen in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -202,20 +223,25 @@ int32_t ais3624dq_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val)
ais3624dq_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0) {
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.zen = val;
ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
/**
* @brief Z axis enable/disable.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of zen in reg CTRL_REG1
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of zen in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -223,7 +249,8 @@ int32_t ais3624dq_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val)
ais3624dq_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
*val = ctrl_reg1.zen;
return ret;
@@ -232,8 +259,9 @@ int32_t ais3624dq_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @brief Accelerometer data rate selection.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of dr in reg CTRL_REG1
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of dr in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_data_rate_set(stmdev_ctx_t *ctx, ais3624dq_dr_t val)
@@ -242,63 +270,78 @@ int32_t ais3624dq_data_rate_set(stmdev_ctx_t *ctx, ais3624dq_dr_t val)
int32_t ret;
ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0) {
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.pm = (uint8_t)val & 0x07U;
- ctrl_reg1.dr = ( (uint8_t)val & 0x30U ) >> 4;
+ ctrl_reg1.dr = ((uint8_t)val & 0x30U) >> 4;
ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
/**
* @brief Accelerometer data rate selection.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of dr in reg CTRL_REG1
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of dr in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais3624dq_data_rate_get(stmdev_ctx_t *ctx, ais3624dq_dr_t *val)
+int32_t ais3624dq_data_rate_get(stmdev_ctx_t *ctx,
+ ais3624dq_dr_t *val)
{
ais3624dq_ctrl_reg1_t ctrl_reg1;
int32_t ret;
ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pm)
{
case AIS3624DQ_ODR_OFF:
*val = AIS3624DQ_ODR_OFF;
break;
+
case AIS3624DQ_ODR_Hz5:
*val = AIS3624DQ_ODR_Hz5;
break;
+
case AIS3624DQ_ODR_1Hz:
*val = AIS3624DQ_ODR_1Hz;
break;
+
case AIS3624DQ_ODR_5Hz2:
*val = AIS3624DQ_ODR_5Hz2;
break;
+
case AIS3624DQ_ODR_5Hz:
*val = AIS3624DQ_ODR_5Hz;
break;
+
case AIS3624DQ_ODR_10Hz:
*val = AIS3624DQ_ODR_10Hz;
break;
+
case AIS3624DQ_ODR_50Hz:
*val = AIS3624DQ_ODR_50Hz;
break;
+
case AIS3624DQ_ODR_100Hz:
*val = AIS3624DQ_ODR_100Hz;
break;
+
case AIS3624DQ_ODR_400Hz:
*val = AIS3624DQ_ODR_400Hz;
break;
+
case AIS3624DQ_ODR_1kHz:
*val = AIS3624DQ_ODR_1kHz;
break;
+
default:
*val = AIS3624DQ_ODR_OFF;
break;
@@ -310,8 +353,9 @@ int32_t ais3624dq_data_rate_get(stmdev_ctx_t *ctx, ais3624dq_dr_t *val)
/**
* @brief High pass filter mode selection.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of hpm in reg CTRL_REG2
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of hpm in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_reference_mode_set(stmdev_ctx_t *ctx,
@@ -320,20 +364,25 @@ int32_t ais3624dq_reference_mode_set(stmdev_ctx_t *ctx,
ais3624dq_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0) {
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpm = (uint8_t)val;
ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
/**
* @brief High pass filter mode selection.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of hpm in reg CTRL_REG2
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of hpm in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_reference_mode_get(stmdev_ctx_t *ctx,
@@ -343,69 +392,84 @@ int32_t ais3624dq_reference_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
switch (ctrl_reg2.hpm)
{
case AIS3624DQ_NORMAL_MODE:
*val = AIS3624DQ_NORMAL_MODE;
break;
+
case AIS3624DQ_REF_MODE_ENABLE:
*val = AIS3624DQ_REF_MODE_ENABLE;
break;
+
default:
*val = AIS3624DQ_NORMAL_MODE;
break;
}
+
return ret;
}
/**
* @brief Accelerometer full-scale selection.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of fs in reg CTRL_REG4
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of fs in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais3624dq_full_scale_set(stmdev_ctx_t *ctx, ais3624dq_fs_t val)
+int32_t ais3624dq_full_scale_set(stmdev_ctx_t *ctx,
+ ais3624dq_fs_t val)
{
ais3624dq_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0) {
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.fs = (uint8_t)val;
ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
/**
* @brief Accelerometer full-scale selection.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of fs in reg CTRL_REG4
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of fs in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais3624dq_full_scale_get(stmdev_ctx_t *ctx, ais3624dq_fs_t *val)
+int32_t ais3624dq_full_scale_get(stmdev_ctx_t *ctx,
+ ais3624dq_fs_t *val)
{
ais3624dq_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
switch (ctrl_reg4.fs)
{
case AIS3624DQ_6g:
*val = AIS3624DQ_6g;
break;
+
case AIS3624DQ_12g:
*val = AIS3624DQ_12g;
break;
+
case AIS3624DQ_24g:
*val = AIS3624DQ_24g;
break;
+
default:
*val = AIS3624DQ_6g;
break;
@@ -417,37 +481,46 @@ int32_t ais3624dq_full_scale_get(stmdev_ctx_t *ctx, ais3624dq_fs_t *val)
/**
* @brief Block data update.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of bdu in reg CTRL_REG4
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of bdu in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais3624dq_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ais3624dq_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
ais3624dq_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0) {
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.bdu = val;
ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
/**
* @brief Block data update.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of bdu in reg CTRL_REG4
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of bdu in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais3624dq_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ais3624dq_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ais3624dq_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
*val = ctrl_reg4.bdu;
return ret;
@@ -456,23 +529,27 @@ int32_t ais3624dq_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @brief The STATUS_REG register is read by the interface.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val registers STATUS_REG
+ * @param ctx read / write interface definitions(ptr)
+ * @param val registers STATUS_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_status_reg_get(stmdev_ctx_t *ctx,
ais3624dq_status_reg_t *val)
{
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_STATUS_REG, (uint8_t*) val, 1);
+
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_STATUS_REG, (uint8_t *) val, 1);
+
return ret;
}
/**
* @brief Accelerometer new data available.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of zyxda in reg STATUS_REG
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of zyxda in reg STATUS_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -481,7 +558,7 @@ int32_t ais3624dq_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = ais3624dq_read_reg(ctx, AIS3624DQ_STATUS_REG,
- (uint8_t*)&status_reg, 1);
+ (uint8_t *)&status_reg, 1);
*val = status_reg.zyxda;
return ret;
@@ -503,22 +580,24 @@ int32_t ais3624dq_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @brief Linear acceleration output register. The value is expressed
* as a 16-bit word in two’s complement.[get]
*
- * @param ctx read / write interface definitions(ptr)
+ * @param ctx read / write interface definitions(ptr)
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais3624dq_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
+int32_t ais3624dq_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
{
uint8_t buff[6];
int32_t ret;
ret = ais3624dq_read_reg(ctx, AIS3624DQ_OUT_X_L, buff, 6);
val[0] = (int16_t)buff[1];
- val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
- val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
val[2] = (int16_t)buff[5];
- val[2] = (val[2] * 256) + (int16_t)buff[4];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
return ret;
}
@@ -538,22 +617,26 @@ int32_t ais3624dq_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
/**
* @brief Device Who am I.[get]
*
- * @param ctx read / write interface definitions(ptr)
+ * @param ctx read / write interface definitions(ptr)
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = ais3624dq_read_reg(ctx, AIS3624DQ_WHO_AM_I, buff, 1);
+
return ret;
}
/**
* @brief Reboot memory content. Reload the calibration parameters.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of boot in reg CTRL_REG2
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of boot in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_boot_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -561,20 +644,25 @@ int32_t ais3624dq_boot_set(stmdev_ctx_t *ctx, uint8_t val)
ais3624dq_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0) {
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.boot = val;
ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
/**
* @brief Reboot memory content. Reload the calibration parameters.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of boot in reg CTRL_REG2
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of boot in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -582,7 +670,8 @@ int32_t ais3624dq_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
ais3624dq_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
*val = ctrl_reg2.boot;
return ret;
@@ -591,8 +680,9 @@ int32_t ais3624dq_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @brief Linear acceleration sensor self-test enable.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of st in reg CTRL_REG4
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of st in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_self_test_set(stmdev_ctx_t *ctx, ais3624dq_st_t val)
@@ -600,40 +690,50 @@ int32_t ais3624dq_self_test_set(stmdev_ctx_t *ctx, ais3624dq_st_t val)
ais3624dq_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0) {
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.st = (uint8_t)val;
ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
/**
* @brief Linear acceleration sensor self-test enable.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of st in reg CTRL_REG4
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of st in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais3624dq_self_test_get(stmdev_ctx_t *ctx, ais3624dq_st_t *val)
+int32_t ais3624dq_self_test_get(stmdev_ctx_t *ctx,
+ ais3624dq_st_t *val)
{
ais3624dq_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
switch (ctrl_reg4.st)
{
case AIS3624DQ_ST_DISABLE:
*val = AIS3624DQ_ST_DISABLE;
break;
+
case AIS3624DQ_ST_POSITIVE:
*val = AIS3624DQ_ST_POSITIVE;
break;
+
case AIS3624DQ_ST_NEGATIVE:
*val = AIS3624DQ_ST_NEGATIVE;
break;
+
default:
*val = AIS3624DQ_ST_DISABLE;
break;
@@ -645,46 +745,57 @@ int32_t ais3624dq_self_test_get(stmdev_ctx_t *ctx, ais3624dq_st_t *val)
/**
* @brief Big/Little Endian Data selection.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of ble in reg CTRL_REG4
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of ble in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais3624dq_data_format_set(stmdev_ctx_t *ctx, ais3624dq_ble_t val)
+int32_t ais3624dq_data_format_set(stmdev_ctx_t *ctx,
+ ais3624dq_ble_t val)
{
ais3624dq_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0) {
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.ble = (uint8_t)val;
ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
/**
* @brief Big/Little Endian Data selection.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of ble in reg CTRL_REG4
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of ble in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais3624dq_data_format_get(stmdev_ctx_t *ctx, ais3624dq_ble_t *val)
+int32_t ais3624dq_data_format_get(stmdev_ctx_t *ctx,
+ ais3624dq_ble_t *val)
{
ais3624dq_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
switch (ctrl_reg4.ble)
{
case AIS3624DQ_LSB_AT_LOW_ADD:
*val = AIS3624DQ_LSB_AT_LOW_ADD;
break;
+
case AIS3624DQ_MSB_AT_LOW_ADD:
*val = AIS3624DQ_MSB_AT_LOW_ADD;
break;
+
default:
*val = AIS3624DQ_LSB_AT_LOW_ADD;
break;
@@ -709,29 +820,36 @@ int32_t ais3624dq_data_format_get(stmdev_ctx_t *ctx, ais3624dq_ble_t *val)
/**
* @brief High pass filter cut-off frequency configuration.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of hpcf in reg CTRL_REG2
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of hpcf in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais3624dq_hp_bandwidth_set(stmdev_ctx_t *ctx, ais3624dq_hpcf_t val)
+int32_t ais3624dq_hp_bandwidth_set(stmdev_ctx_t *ctx,
+ ais3624dq_hpcf_t val)
{
ais3624dq_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0) {
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpcf = (uint8_t)val;
ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
/**
* @brief High pass filter cut-off frequency configuration.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of hpcf in reg CTRL_REG2
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of hpcf in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_hp_bandwidth_get(stmdev_ctx_t *ctx,
@@ -740,22 +858,27 @@ int32_t ais3624dq_hp_bandwidth_get(stmdev_ctx_t *ctx,
ais3624dq_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
switch (ctrl_reg2.hpcf)
{
case AIS3624DQ_CUT_OFF_8Hz:
*val = AIS3624DQ_CUT_OFF_8Hz;
break;
+
case AIS3624DQ_CUT_OFF_16Hz:
*val = AIS3624DQ_CUT_OFF_16Hz;
break;
+
case AIS3624DQ_CUT_OFF_32Hz:
*val = AIS3624DQ_CUT_OFF_32Hz;
break;
+
case AIS3624DQ_CUT_OFF_64Hz:
*val = AIS3624DQ_CUT_OFF_64Hz;
break;
+
default:
*val = AIS3624DQ_CUT_OFF_8Hz;
break;
@@ -767,8 +890,9 @@ int32_t ais3624dq_hp_bandwidth_get(stmdev_ctx_t *ctx,
/**
* @brief Select High Pass filter path.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of hpen in reg CTRL_REG2
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of hpen in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_hp_path_set(stmdev_ctx_t *ctx, ais3624dq_hpen_t val)
@@ -776,60 +900,76 @@ int32_t ais3624dq_hp_path_set(stmdev_ctx_t *ctx, ais3624dq_hpen_t val)
ais3624dq_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0) {
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpen = (uint8_t)val & 0x03U;
ctrl_reg2.fds = ((uint8_t)val & 0x04U) >> 2;
ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
/**
* @brief Select High Pass filter path.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of hpen in reg CTRL_REG2
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of hpen in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais3624dq_hp_path_get(stmdev_ctx_t *ctx, ais3624dq_hpen_t *val)
+int32_t ais3624dq_hp_path_get(stmdev_ctx_t *ctx,
+ ais3624dq_hpen_t *val)
{
ais3624dq_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
- switch ( (ctrl_reg2.fds << 2) + ctrl_reg2.hpen )
+ switch ((ctrl_reg2.fds << 2) + ctrl_reg2.hpen)
{
case AIS3624DQ_HP_DISABLE:
*val = AIS3624DQ_HP_DISABLE;
break;
+
case AIS3624DQ_HP_ON_OUT:
*val = AIS3624DQ_HP_ON_OUT;
break;
+
case AIS3624DQ_HP_ON_INT1:
*val = AIS3624DQ_HP_ON_INT1;
break;
+
case AIS3624DQ_HP_ON_INT2:
*val = AIS3624DQ_HP_ON_INT2;
break;
+
case AIS3624DQ_HP_ON_INT1_INT2:
*val = AIS3624DQ_HP_ON_INT1_INT2;
break;
+
case AIS3624DQ_HP_ON_INT1_INT2_OUT:
*val = AIS3624DQ_HP_ON_INT1_INT2_OUT;
break;
+
case AIS3624DQ_HP_ON_INT2_OUT:
*val = AIS3624DQ_HP_ON_INT2_OUT;
break;
+
case AIS3624DQ_HP_ON_INT1_OUT:
*val = AIS3624DQ_HP_ON_INT1_OUT;
break;
+
default:
*val = AIS3624DQ_HP_DISABLE;
break;
}
+
return ret;
}
@@ -841,43 +981,54 @@ int32_t ais3624dq_hp_path_get(stmdev_ctx_t *ctx, ais3624dq_hpen_t *val)
* overcome the settling time of the high pass
* filter.[get]
*
- * @param ctx read / write interface definitions(ptr)
+ * @param ctx read / write interface definitions(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_hp_reset_get(stmdev_ctx_t *ctx)
{
uint8_t dummy;
int32_t ret;
+
ret = ais3624dq_read_reg(ctx, AIS3624DQ_HP_FILTER_RESET,
- (uint8_t*)&dummy, 1);
+ (uint8_t *)&dummy, 1);
+
return ret;
}
/**
* @brief Reference value for high-pass filter.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of ref in reg REFERENCE
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of ref in reg REFERENCE
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais3624dq_hp_reference_value_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ais3624dq_hp_reference_value_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
int32_t ret;
- ret = ais3624dq_write_reg(ctx, AIS3624DQ_REFERENCE, (uint8_t*)&val, 1);
+
+ ret = ais3624dq_write_reg(ctx, AIS3624DQ_REFERENCE, (uint8_t *)&val, 1);
+
return ret;
}
/**
* @brief Reference value for high-pass filter.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of ref in reg REFERENCE
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of ref in reg REFERENCE
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais3624dq_hp_reference_value_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ais3624dq_hp_reference_value_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
int32_t ret;
+
ret = ais3624dq_read_reg(ctx, AIS3624DQ_REFERENCE, val, 1);
+
return ret;
}
@@ -897,8 +1048,9 @@ int32_t ais3624dq_hp_reference_value_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @brief SPI 3- or 4-wire interface.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of sim in reg CTRL_REG4
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of sim in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_spi_mode_set(stmdev_ctx_t *ctx, ais3624dq_sim_t val)
@@ -906,37 +1058,46 @@ int32_t ais3624dq_spi_mode_set(stmdev_ctx_t *ctx, ais3624dq_sim_t val)
ais3624dq_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0) {
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.sim = (uint8_t)val;
ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
/**
* @brief SPI 3- or 4-wire interface.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of sim in reg CTRL_REG4
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of sim in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais3624dq_spi_mode_get(stmdev_ctx_t *ctx, ais3624dq_sim_t *val)
+int32_t ais3624dq_spi_mode_get(stmdev_ctx_t *ctx,
+ ais3624dq_sim_t *val)
{
ais3624dq_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
- switch ( ctrl_reg4.sim )
+ switch (ctrl_reg4.sim)
{
case AIS3624DQ_SPI_4_WIRE:
*val = AIS3624DQ_SPI_4_WIRE;
break;
+
case AIS3624DQ_SPI_3_WIRE:
*val = AIS3624DQ_SPI_3_WIRE;
break;
+
default:
*val = AIS3624DQ_SPI_4_WIRE;
break;
@@ -961,8 +1122,9 @@ int32_t ais3624dq_spi_mode_get(stmdev_ctx_t *ctx, ais3624dq_sim_t *val)
/**
* @brief Data signal on INT 1 pad control bits.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of i1_cfg in reg CTRL_REG3
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of i1_cfg in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_pin_int1_route_set(stmdev_ctx_t *ctx,
@@ -971,20 +1133,25 @@ int32_t ais3624dq_pin_int1_route_set(stmdev_ctx_t *ctx,
ais3624dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.i1_cfg = (uint8_t)val;
ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
/**
* @brief Data signal on INT 1 pad control bits.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of i1_cfg in reg CTRL_REG3
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of i1_cfg in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_pin_int1_route_get(stmdev_ctx_t *ctx,
@@ -993,22 +1160,27 @@ int32_t ais3624dq_pin_int1_route_get(stmdev_ctx_t *ctx,
ais3624dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.i1_cfg )
+ switch (ctrl_reg3.i1_cfg)
{
case AIS3624DQ_PAD1_INT1_SRC:
*val = AIS3624DQ_PAD1_INT1_SRC;
break;
+
case AIS3624DQ_PAD1_INT1_OR_INT2_SRC:
*val = AIS3624DQ_PAD1_INT1_OR_INT2_SRC;
break;
+
case AIS3624DQ_PAD1_DRDY:
*val = AIS3624DQ_PAD1_DRDY;
break;
+
case AIS3624DQ_PAD1_BOOT:
*val = AIS3624DQ_PAD1_BOOT;
break;
+
default:
*val = AIS3624DQ_PAD1_INT1_SRC;
break;
@@ -1021,8 +1193,9 @@ int32_t ais3624dq_pin_int1_route_get(stmdev_ctx_t *ctx,
* @brief Latch interrupt request on INT1_SRC register, with INT1_SRC
* register cleared by reading INT1_SRC register.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of lir1 in reg CTRL_REG3
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of lir1 in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_int1_notification_set(stmdev_ctx_t *ctx,
@@ -1031,12 +1204,16 @@ int32_t ais3624dq_int1_notification_set(stmdev_ctx_t *ctx,
ais3624dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.lir1 = (uint8_t)val;
ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1044,8 +1221,9 @@ int32_t ais3624dq_int1_notification_set(stmdev_ctx_t *ctx,
* @brief Latch interrupt request on INT1_SRC register, with INT1_SRC
* register cleared by reading INT1_SRC register.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of lir1 in reg CTRL_REG3
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of lir1 in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_int1_notification_get(stmdev_ctx_t *ctx,
@@ -1054,16 +1232,19 @@ int32_t ais3624dq_int1_notification_get(stmdev_ctx_t *ctx,
ais3624dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.lir1 )
+ switch (ctrl_reg3.lir1)
{
case AIS3624DQ_INT1_PULSED:
*val = AIS3624DQ_INT1_PULSED;
break;
+
case AIS3624DQ_INT1_LATCHED:
*val = AIS3624DQ_INT1_LATCHED;
break;
+
default:
*val = AIS3624DQ_INT1_PULSED;
break;
@@ -1075,8 +1256,9 @@ int32_t ais3624dq_int1_notification_get(stmdev_ctx_t *ctx,
/**
* @brief Data signal on INT 2 pad control bits.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of i2_cfg in reg CTRL_REG3
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of i2_cfg in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_pin_int2_route_set(stmdev_ctx_t *ctx,
@@ -1085,20 +1267,25 @@ int32_t ais3624dq_pin_int2_route_set(stmdev_ctx_t *ctx,
ais3624dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.i2_cfg = (uint8_t)val;
ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
/**
* @brief Data signal on INT 2 pad control bits.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of i2_cfg in reg CTRL_REG3
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of i2_cfg in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_pin_int2_route_get(stmdev_ctx_t *ctx,
@@ -1107,22 +1294,27 @@ int32_t ais3624dq_pin_int2_route_get(stmdev_ctx_t *ctx,
ais3624dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.i2_cfg )
+ switch (ctrl_reg3.i2_cfg)
{
case AIS3624DQ_PAD2_INT2_SRC:
*val = AIS3624DQ_PAD2_INT2_SRC;
break;
+
case AIS3624DQ_PAD2_INT1_OR_INT2_SRC:
*val = AIS3624DQ_PAD2_INT1_OR_INT2_SRC;
break;
+
case AIS3624DQ_PAD2_DRDY:
*val = AIS3624DQ_PAD2_DRDY;
break;
+
case AIS3624DQ_PAD2_BOOT:
*val = AIS3624DQ_PAD2_BOOT;
break;
+
default:
*val = AIS3624DQ_PAD2_INT2_SRC;
break;
@@ -1135,8 +1327,9 @@ int32_t ais3624dq_pin_int2_route_get(stmdev_ctx_t *ctx,
* @brief Latch interrupt request on INT2_SRC register, with INT2_SRC
* register cleared by reading INT2_SRC itself.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of lir2 in reg CTRL_REG3
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of lir2 in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_int2_notification_set(stmdev_ctx_t *ctx,
@@ -1145,12 +1338,16 @@ int32_t ais3624dq_int2_notification_set(stmdev_ctx_t *ctx,
ais3624dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.lir2 = (uint8_t)val;
ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1158,8 +1355,9 @@ int32_t ais3624dq_int2_notification_set(stmdev_ctx_t *ctx,
* @brief Latch interrupt request on INT2_SRC register, with INT2_SRC
* register cleared by reading INT2_SRC itself.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of lir2 in reg CTRL_REG3
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of lir2 in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_int2_notification_get(stmdev_ctx_t *ctx,
@@ -1168,16 +1366,19 @@ int32_t ais3624dq_int2_notification_get(stmdev_ctx_t *ctx,
ais3624dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.lir2 )
+ switch (ctrl_reg3.lir2)
{
case AIS3624DQ_INT2_PULSED:
*val = AIS3624DQ_INT2_PULSED;
break;
+
case AIS3624DQ_INT2_LATCHED:
*val = AIS3624DQ_INT2_LATCHED;
break;
+
default:
*val = AIS3624DQ_INT2_PULSED;
break;
@@ -1189,46 +1390,57 @@ int32_t ais3624dq_int2_notification_get(stmdev_ctx_t *ctx,
/**
* @brief Push-pull/open drain selection on interrupt pads.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of pp_od in reg CTRL_REG3
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of pp_od in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais3624dq_pin_mode_set(stmdev_ctx_t *ctx, ais3624dq_pp_od_t val)
+int32_t ais3624dq_pin_mode_set(stmdev_ctx_t *ctx,
+ ais3624dq_pp_od_t val)
{
ais3624dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.pp_od = (uint8_t)val;
ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
/**
* @brief Push-pull/open drain selection on interrupt pads.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of pp_od in reg CTRL_REG3
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of pp_od in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais3624dq_pin_mode_get(stmdev_ctx_t *ctx, ais3624dq_pp_od_t *val)
+int32_t ais3624dq_pin_mode_get(stmdev_ctx_t *ctx,
+ ais3624dq_pp_od_t *val)
{
ais3624dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.pp_od )
+ switch (ctrl_reg3.pp_od)
{
case AIS3624DQ_PUSH_PULL:
*val = AIS3624DQ_PUSH_PULL;
break;
+
case AIS3624DQ_OPEN_DRAIN:
*val = AIS3624DQ_OPEN_DRAIN;
break;
+
default:
*val = AIS3624DQ_PUSH_PULL;
break;
@@ -1240,46 +1452,57 @@ int32_t ais3624dq_pin_mode_get(stmdev_ctx_t *ctx, ais3624dq_pp_od_t *val)
/**
* @brief Interrupt active-high/low.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of ihl in reg CTRL_REG3
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of ihl in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais3624dq_pin_polarity_set(stmdev_ctx_t *ctx, ais3624dq_ihl_t val)
+int32_t ais3624dq_pin_polarity_set(stmdev_ctx_t *ctx,
+ ais3624dq_ihl_t val)
{
ais3624dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.ihl = (uint8_t)val;
ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
/**
* @brief Interrupt active-high/low.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of ihl in reg CTRL_REG3
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of ihl in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais3624dq_pin_polarity_get(stmdev_ctx_t *ctx, ais3624dq_ihl_t *val)
+int32_t ais3624dq_pin_polarity_get(stmdev_ctx_t *ctx,
+ ais3624dq_ihl_t *val)
{
ais3624dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.ihl )
+ switch (ctrl_reg3.ihl)
{
case AIS3624DQ_ACTIVE_HIGH:
*val = AIS3624DQ_ACTIVE_HIGH;
break;
+
case AIS3624DQ_ACTIVE_LOW:
*val = AIS3624DQ_ACTIVE_LOW;
break;
+
default:
*val = AIS3624DQ_ACTIVE_HIGH;
break;
@@ -1304,18 +1527,22 @@ int32_t ais3624dq_pin_polarity_get(stmdev_ctx_t *ctx, ais3624dq_ihl_t *val)
/**
* @brief Configure the interrupt 1 threshold sign.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val enable sign and axis for interrupt on threshold
+ * @param ctx read / write interface definitions(ptr)
+ * @param val enable sign and axis for interrupt on threshold
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_int1_on_threshold_conf_set(stmdev_ctx_t *ctx,
- ais3624dq_int1_on_th_conf_t val)
+ ais3624dq_int1_on_th_conf_t val)
{
ais3624dq_int1_cfg_t int1_cfg;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_CFG, (uint8_t*)&int1_cfg, 1);
- if(ret == 0) {
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_CFG,
+ (uint8_t *)&int1_cfg, 1);
+
+ if (ret == 0)
+ {
int1_cfg.xlie = val.int1_xlie;
int1_cfg.xhie = val.int1_xhie;
int1_cfg.ylie = val.int1_ylie;
@@ -1323,16 +1550,18 @@ int32_t ais3624dq_int1_on_threshold_conf_set(stmdev_ctx_t *ctx,
int1_cfg.zlie = val.int1_zlie;
int1_cfg.zhie = val.int1_zhie;
ret = ais3624dq_write_reg(ctx, AIS3624DQ_INT1_CFG,
- (uint8_t*)&int1_cfg, 1);
+ (uint8_t *)&int1_cfg, 1);
}
+
return ret;
}
/**
* @brief Configure the interrupt 1 threshold sign.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val enable sign and axis for interrupt on threshold
+ * @param ctx read / write interface definitions(ptr)
+ * @param val enable sign and axis for interrupt on threshold
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_int1_on_threshold_conf_get(stmdev_ctx_t *ctx,
@@ -1341,7 +1570,8 @@ int32_t ais3624dq_int1_on_threshold_conf_get(stmdev_ctx_t *ctx,
ais3624dq_int1_cfg_t int1_cfg;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_CFG, (uint8_t*)&int1_cfg, 1);
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_CFG,
+ (uint8_t *)&int1_cfg, 1);
val->int1_xlie = int1_cfg.xlie;
val->int1_xhie = int1_cfg.xhie;
val->int1_ylie = int1_cfg.ylie;
@@ -1355,8 +1585,9 @@ int32_t ais3624dq_int1_on_threshold_conf_get(stmdev_ctx_t *ctx,
/**
* @brief AND/OR combination of Interrupt 1 events.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of aoi in reg INT1_CFG
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of aoi in reg INT1_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_int1_on_threshold_mode_set(stmdev_ctx_t *ctx,
@@ -1365,20 +1596,25 @@ int32_t ais3624dq_int1_on_threshold_mode_set(stmdev_ctx_t *ctx,
ais3624dq_int1_cfg_t int1_cfg;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_CFG, (uint8_t*)&int1_cfg, 1);
- if(ret == 0) {
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_CFG,
+ (uint8_t *)&int1_cfg, 1);
+
+ if (ret == 0)
+ {
int1_cfg.aoi = (uint8_t) val;
ret = ais3624dq_write_reg(ctx, AIS3624DQ_INT1_CFG,
- (uint8_t*)&int1_cfg, 1);
+ (uint8_t *)&int1_cfg, 1);
}
+
return ret;
}
/**
* @brief AND/OR combination of Interrupt 1 events.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of aoi in reg INT1_CFG
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of aoi in reg INT1_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_int1_on_threshold_mode_get(stmdev_ctx_t *ctx,
@@ -1387,16 +1623,19 @@ int32_t ais3624dq_int1_on_threshold_mode_get(stmdev_ctx_t *ctx,
ais3624dq_int1_cfg_t int1_cfg;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_CFG, (uint8_t*)&int1_cfg, 1);
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_CFG,
+ (uint8_t *)&int1_cfg, 1);
- switch ( int1_cfg.aoi )
+ switch (int1_cfg.aoi)
{
case AIS3624DQ_INT1_ON_THRESHOLD_OR:
*val = AIS3624DQ_INT1_ON_THRESHOLD_OR;
break;
+
case AIS3624DQ_INT1_ON_THRESHOLD_AND:
*val = AIS3624DQ_INT1_ON_THRESHOLD_AND;
break;
+
default:
*val = AIS3624DQ_INT1_ON_THRESHOLD_OR;
break;
@@ -1408,23 +1647,27 @@ int32_t ais3624dq_int1_on_threshold_mode_get(stmdev_ctx_t *ctx,
/**
* @brief Interrupt generator 1 on threshold source register.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val registers INT1_SRC
+ * @param ctx read / write interface definitions(ptr)
+ * @param val registers INT1_SRC
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_int1_src_get(stmdev_ctx_t *ctx,
ais3624dq_int1_src_t *val)
{
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_SRC, (uint8_t*) val, 1);
+
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_SRC, (uint8_t *) val, 1);
+
return ret;
}
/**
* @brief Interrupt 1 threshold.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of ths in reg INT1_THS
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of ths in reg INT1_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1432,20 +1675,25 @@ int32_t ais3624dq_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
ais3624dq_int1_ths_t int1_ths;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_THS, (uint8_t*)&int1_ths, 1);
- if(ret == 0) {
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_THS,
+ (uint8_t *)&int1_ths, 1);
+
+ if (ret == 0)
+ {
int1_ths.ths = val;
ret = ais3624dq_write_reg(ctx, AIS3624DQ_INT1_THS,
- (uint8_t*)&int1_ths, 1);
+ (uint8_t *)&int1_ths, 1);
}
+
return ret;
}
/**
* @brief Interrupt 1 threshold.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of ths in reg INT1_THS
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of ths in reg INT1_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1453,7 +1701,8 @@ int32_t ais3624dq_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
ais3624dq_int1_ths_t int1_ths;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_THS, (uint8_t*)&int1_ths, 1);
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_THS,
+ (uint8_t *)&int1_ths, 1);
*val = int1_ths.ths;
return ret;
@@ -1462,8 +1711,9 @@ int32_t ais3624dq_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @brief Duration value for interrupt 1 generator.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of d in reg INT1_DURATION
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of d in reg INT1_DURATION
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1472,20 +1722,24 @@ int32_t ais3624dq_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_DURATION,
- (uint8_t*)&int1_duration, 1);
- if(ret == 0) {
+ (uint8_t *)&int1_duration, 1);
+
+ if (ret == 0)
+ {
int1_duration.d = val;
ret = ais3624dq_write_reg(ctx, AIS3624DQ_INT1_DURATION,
- (uint8_t*)&int1_duration, 1);
+ (uint8_t *)&int1_duration, 1);
}
+
return ret;
}
/**
* @brief Duration value for interrupt 1 generator.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of d in reg INT1_DURATION
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of d in reg INT1_DURATION
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1494,7 +1748,7 @@ int32_t ais3624dq_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_DURATION,
- (uint8_t*)&int1_duration, 1);
+ (uint8_t *)&int1_duration, 1);
*val = int1_duration.d;
return ret;
@@ -1503,19 +1757,22 @@ int32_t ais3624dq_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @brief Configure the interrupt 2 threshold sign.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val enable sign and axis for interrupt on threshold
+ * @param ctx read / write interface definitions(ptr)
+ * @param val enable sign and axis for interrupt on threshold
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_int2_on_threshold_conf_set(stmdev_ctx_t *ctx,
- ais3624dq_int2_on_th_conf_t val)
+ ais3624dq_int2_on_th_conf_t val)
{
ais3624dq_int2_cfg_t int2_cfg;
int32_t ret;
ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_CFG,
- (uint8_t*)&int2_cfg, 1);
- if(ret == 0) {
+ (uint8_t *)&int2_cfg, 1);
+
+ if (ret == 0)
+ {
int2_cfg.xlie = val.int2_xlie;
int2_cfg.xhie = val.int2_xhie;
int2_cfg.ylie = val.int2_ylie;
@@ -1523,25 +1780,28 @@ int32_t ais3624dq_int2_on_threshold_conf_set(stmdev_ctx_t *ctx,
int2_cfg.zlie = val.int2_zlie;
int2_cfg.zhie = val.int2_zhie;
ret = ais3624dq_write_reg(ctx, AIS3624DQ_INT2_CFG,
- (uint8_t*)&int2_cfg, 1);
+ (uint8_t *)&int2_cfg, 1);
}
+
return ret;
}
/**
* @brief Configure the interrupt 2 threshold sign.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val enable sign and axis for interrupt on threshold
+ * @param ctx read / write interface definitions(ptr)
+ * @param val enable sign and axis for interrupt on threshold
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_int2_on_threshold_conf_get(stmdev_ctx_t *ctx,
- ais3624dq_int2_on_th_conf_t *val)
+ ais3624dq_int2_on_th_conf_t *val)
{
ais3624dq_int2_cfg_t int2_cfg;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_CFG, (uint8_t*)&int2_cfg, 1);
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_CFG,
+ (uint8_t *)&int2_cfg, 1);
val->int2_xlie = int2_cfg.xlie;
val->int2_xhie = int2_cfg.xhie;
val->int2_ylie = int2_cfg.ylie;
@@ -1555,8 +1815,9 @@ int32_t ais3624dq_int2_on_threshold_conf_get(stmdev_ctx_t *ctx,
/**
* @brief AND/OR combination of Interrupt 2 events.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of aoi in reg INT2_CFG
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of aoi in reg INT2_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_int2_on_threshold_mode_set(stmdev_ctx_t *ctx,
@@ -1565,20 +1826,25 @@ int32_t ais3624dq_int2_on_threshold_mode_set(stmdev_ctx_t *ctx,
ais3624dq_int2_cfg_t int2_cfg;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_CFG, (uint8_t*)&int2_cfg, 1);
- if(ret == 0) {
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_CFG,
+ (uint8_t *)&int2_cfg, 1);
+
+ if (ret == 0)
+ {
int2_cfg.aoi = (uint8_t) val;
ret = ais3624dq_write_reg(ctx, AIS3624DQ_INT2_CFG,
- (uint8_t*)&int2_cfg, 1);
+ (uint8_t *)&int2_cfg, 1);
}
+
return ret;
}
/**
* @brief AND/OR combination of Interrupt 2 events.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of aoi in reg INT2_CFG
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of aoi in reg INT2_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_int2_on_threshold_mode_get(stmdev_ctx_t *ctx,
@@ -1587,16 +1853,19 @@ int32_t ais3624dq_int2_on_threshold_mode_get(stmdev_ctx_t *ctx,
ais3624dq_int2_cfg_t int2_cfg;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_CFG, (uint8_t*)&int2_cfg, 1);
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_CFG,
+ (uint8_t *)&int2_cfg, 1);
- switch ( int2_cfg.aoi )
+ switch (int2_cfg.aoi)
{
case AIS3624DQ_INT2_ON_THRESHOLD_OR:
*val = AIS3624DQ_INT2_ON_THRESHOLD_OR;
break;
+
case AIS3624DQ_INT2_ON_THRESHOLD_AND:
*val = AIS3624DQ_INT2_ON_THRESHOLD_AND;
break;
+
default:
*val = AIS3624DQ_INT2_ON_THRESHOLD_OR;
break;
@@ -1608,23 +1877,27 @@ int32_t ais3624dq_int2_on_threshold_mode_get(stmdev_ctx_t *ctx,
/**
* @brief Interrupt generator 1 on threshold source register.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val registers INT2_SRC
+ * @param ctx read / write interface definitions(ptr)
+ * @param val registers INT2_SRC
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_int2_src_get(stmdev_ctx_t *ctx,
ais3624dq_int2_src_t *val)
{
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_SRC, (uint8_t*) val, 1);
+
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_SRC, (uint8_t *) val, 1);
+
return ret;
}
/**
* @brief Interrupt 2 threshold.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of ths in reg INT2_THS
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of ths in reg INT2_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1632,20 +1905,25 @@ int32_t ais3624dq_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
ais3624dq_int2_ths_t int2_ths;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_THS, (uint8_t*)&int2_ths, 1);
- if(ret == 0) {
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_THS,
+ (uint8_t *)&int2_ths, 1);
+
+ if (ret == 0)
+ {
int2_ths.ths = val;
ret = ais3624dq_write_reg(ctx, AIS3624DQ_INT2_THS,
- (uint8_t*)&int2_ths, 1);
+ (uint8_t *)&int2_ths, 1);
}
+
return ret;
}
/**
* @brief Interrupt 2 threshold.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of ths in reg INT2_THS
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of ths in reg INT2_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1653,7 +1931,8 @@ int32_t ais3624dq_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
ais3624dq_int2_ths_t int2_ths;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_THS, (uint8_t*)&int2_ths, 1);
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_THS,
+ (uint8_t *)&int2_ths, 1);
*val = int2_ths.ths;
return ret;
@@ -1662,8 +1941,9 @@ int32_t ais3624dq_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @brief Duration value for interrupt 2 generator.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of d in reg INT2_DURATION
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of d in reg INT2_DURATION
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1672,20 +1952,24 @@ int32_t ais3624dq_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_DURATION,
- (uint8_t*)&int2_duration, 1);
- if(ret == 0) {
+ (uint8_t *)&int2_duration, 1);
+
+ if (ret == 0)
+ {
int2_duration.d = val;
ret = ais3624dq_write_reg(ctx, AIS3624DQ_INT2_DURATION,
- (uint8_t*)&int2_duration, 1);
+ (uint8_t *)&int2_duration, 1);
}
+
return ret;
}
/**
* @brief Duration value for interrupt 2 generator.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of d in reg INT2_DURATION
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of d in reg INT2_DURATION
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1694,7 +1978,7 @@ int32_t ais3624dq_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_DURATION,
- (uint8_t*)&int2_duration, 1);
+ (uint8_t *)&int2_duration, 1);
*val = int2_duration.d;
return ret;
@@ -1716,8 +2000,9 @@ int32_t ais3624dq_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @brief Turn-on mode selection for sleep to wake function.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of turnon in reg CTRL_REG5
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of turnon in reg CTRL_REG5
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1725,20 +2010,25 @@ int32_t ais3624dq_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val)
ais3624dq_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if(ret == 0) {
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.turnon = val;
ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG5,
- (uint8_t*)&ctrl_reg5, 1);
+ (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
/**
* @brief Turn-on mode selection for sleep to wake function.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of turnon in reg CTRL_REG5
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of turnon in reg CTRL_REG5
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1746,7 +2036,8 @@ int32_t ais3624dq_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val)
ais3624dq_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
*val = ctrl_reg5.turnon;
return ret;
@@ -1768,8 +2059,9 @@ int32_t ais3624dq_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @brief Configure the 6d on interrupt 1 generator.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of 6d in reg INT1_CFG
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of 6d in reg INT1_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_int1_6d_mode_set(stmdev_ctx_t *ctx,
@@ -1778,20 +2070,26 @@ int32_t ais3624dq_int1_6d_mode_set(stmdev_ctx_t *ctx,
ais3624dq_int1_cfg_t int1_cfg;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_CFG, (uint8_t*)&int1_cfg, 1);
- if(ret == 0) {
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_CFG,
+ (uint8_t *)&int1_cfg, 1);
+
+ if (ret == 0)
+ {
int1_cfg._6d = (uint8_t)val & 0x01U;
int1_cfg.aoi = ((uint8_t)val & 0x02U) >> 1;
- ret = ais3624dq_write_reg(ctx, AIS3624DQ_INT1_CFG, (uint8_t*)&int1_cfg, 1);
+ ret = ais3624dq_write_reg(ctx, AIS3624DQ_INT1_CFG,
+ (uint8_t *)&int1_cfg, 1);
}
+
return ret;
}
/**
* @brief Configure the 6d on interrupt 1 generator.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of 6d in reg INT1_CFG
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of 6d in reg INT1_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_int1_6d_mode_get(stmdev_ctx_t *ctx,
@@ -1800,19 +2098,23 @@ int32_t ais3624dq_int1_6d_mode_get(stmdev_ctx_t *ctx,
ais3624dq_int1_cfg_t int1_cfg;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_CFG, (uint8_t*)&int1_cfg, 1);
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_CFG,
+ (uint8_t *)&int1_cfg, 1);
switch ((int1_cfg.aoi << 1) + int1_cfg._6d)
{
case AIS3624DQ_6D_INT1_DISABLE:
*val = AIS3624DQ_6D_INT1_DISABLE;
break;
+
case AIS3624DQ_6D_INT1_MOVEMENT:
*val = AIS3624DQ_6D_INT1_MOVEMENT;
break;
- case AIS3624DQ_6D_INT1_POSITION:
+
+ case AIS3624DQ_6D_INT1_POSITION:
*val = AIS3624DQ_6D_INT1_POSITION;
break;
+
default:
*val = AIS3624DQ_6D_INT1_DISABLE;
break;
@@ -1824,23 +2126,27 @@ int32_t ais3624dq_int1_6d_mode_get(stmdev_ctx_t *ctx,
/**
* @brief 6D on interrupt generator 1 source register.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val registers INT1_SRC
+ * @param ctx read / write interface definitions(ptr)
+ * @param val registers INT1_SRC
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_int1_6d_src_get(stmdev_ctx_t *ctx,
ais3624dq_int1_src_t *val)
{
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_SRC, (uint8_t*) val, 1);
+
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_SRC, (uint8_t *) val, 1);
+
return ret;
}
/**
* @brief Interrupt 1 threshold.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of ths in reg INT1_THS
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of ths in reg INT1_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_int1_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1848,27 +2154,35 @@ int32_t ais3624dq_int1_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
ais3624dq_int1_ths_t int1_ths;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_THS, (uint8_t*)&int1_ths, 1);
- if(ret == 0) {
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_THS,
+ (uint8_t *)&int1_ths, 1);
+
+ if (ret == 0)
+ {
int1_ths.ths = val;
- ret = ais3624dq_write_reg(ctx, AIS3624DQ_INT1_THS, (uint8_t*)&int1_ths, 1);
+ ret = ais3624dq_write_reg(ctx, AIS3624DQ_INT1_THS,
+ (uint8_t *)&int1_ths, 1);
}
+
return ret;
}
/**
* @brief Interrupt 1 threshold.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of ths in reg INT1_THS
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of ths in reg INT1_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais3624dq_int1_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ais3624dq_int1_6d_treshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ais3624dq_int1_ths_t int1_ths;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_THS, (uint8_t*)&int1_ths, 1);
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_THS,
+ (uint8_t *)&int1_ths, 1);
*val = int1_ths.ths;
return ret;
@@ -1877,8 +2191,9 @@ int32_t ais3624dq_int1_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @brief Configure the 6d on interrupt 2 generator.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of 6d in reg INT2_CFG
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of 6d in reg INT2_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_int2_6d_mode_set(stmdev_ctx_t *ctx,
@@ -1887,21 +2202,26 @@ int32_t ais3624dq_int2_6d_mode_set(stmdev_ctx_t *ctx,
ais3624dq_int2_cfg_t int2_cfg;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_CFG, (uint8_t*)&int2_cfg, 1);
- if(ret == 0) {
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_CFG,
+ (uint8_t *)&int2_cfg, 1);
+
+ if (ret == 0)
+ {
int2_cfg._6d = (uint8_t)val & 0x01U;
int2_cfg.aoi = ((uint8_t)val & 0x02U) >> 1;
ret = ais3624dq_write_reg(ctx, AIS3624DQ_INT2_CFG,
- (uint8_t*)&int2_cfg, 1);
+ (uint8_t *)&int2_cfg, 1);
}
+
return ret;
}
/**
* @brief Configure the 6d on interrupt 2 generator.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of 6d in reg INT2_CFG
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of 6d in reg INT2_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_int2_6d_mode_get(stmdev_ctx_t *ctx,
@@ -1910,19 +2230,23 @@ int32_t ais3624dq_int2_6d_mode_get(stmdev_ctx_t *ctx,
ais3624dq_int2_cfg_t int2_cfg;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_CFG, (uint8_t*)&int2_cfg, 1);
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_CFG,
+ (uint8_t *)&int2_cfg, 1);
switch ((int2_cfg.aoi << 1) + int2_cfg._6d)
{
case AIS3624DQ_6D_INT2_DISABLE:
*val = AIS3624DQ_6D_INT2_DISABLE;
break;
+
case AIS3624DQ_6D_INT2_MOVEMENT:
*val = AIS3624DQ_6D_INT2_MOVEMENT;
break;
- case AIS3624DQ_6D_INT2_POSITION:
+
+ case AIS3624DQ_6D_INT2_POSITION:
*val = AIS3624DQ_6D_INT2_POSITION;
break;
+
default:
*val = AIS3624DQ_6D_INT2_DISABLE;
break;
@@ -1934,23 +2258,27 @@ int32_t ais3624dq_int2_6d_mode_get(stmdev_ctx_t *ctx,
/**
* @brief 6D on interrupt generator 2 source register.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val registers INT2_SRC
+ * @param ctx read / write interface definitions(ptr)
+ * @param val registers INT2_SRC
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_int2_6d_src_get(stmdev_ctx_t *ctx,
ais3624dq_int2_src_t *val)
{
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_SRC, (uint8_t*) val, 1);
+
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_SRC, (uint8_t *) val, 1);
+
return ret;
}
/**
* @brief Interrupt 2 threshold.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of ths in reg INT2_THS
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of ths in reg INT2_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t ais3624dq_int2_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1958,28 +2286,35 @@ int32_t ais3624dq_int2_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
ais3624dq_int2_ths_t int2_ths;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_THS, (uint8_t*)&int2_ths, 1);
- if(ret == 0) {
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_THS,
+ (uint8_t *)&int2_ths, 1);
+
+ if (ret == 0)
+ {
int2_ths.ths = val;
ret = ais3624dq_write_reg(ctx, AIS3624DQ_INT2_THS,
- (uint8_t*)&int2_ths, 1);
+ (uint8_t *)&int2_ths, 1);
}
+
return ret;
}
/**
* @brief Interrupt 2 threshold.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of ths in reg INT2_THS
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of ths in reg INT2_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ais3624dq_int2_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ais3624dq_int2_6d_treshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ais3624dq_int2_ths_t int2_ths;
int32_t ret;
- ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_THS, (uint8_t*)&int2_ths, 1);
+ ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_THS,
+ (uint8_t *)&int2_ths, 1);
*val = int2_ths.ths;
return ret;
diff --git a/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.h b/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.h
index b87685d7e7118518194c7630f70798abf9a98488..7161da6cc0027c9e4717c32c3235b52997c9c853 100644
--- a/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.h
+++ b/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file ais3624dq_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * ais3624dq_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file ais3624dq_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * ais3624dq_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef AIS3624DQ_REGS_H
#define AIS3624DQ_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup AIS3624DQ
@@ -74,7 +75,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -107,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -131,7 +134,7 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
+ * You can create a sensor configuration by your own or using
* Unico / Unicleo tools available on STMicroelectronics
* web site.
*
@@ -139,7 +142,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -175,7 +179,8 @@ typedef struct {
#define AIS3624DQ_WHO_AM_I 0x0FU
#define AIS3624DQ_CTRL_REG1 0x20U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xen : 1;
uint8_t yen : 1;
@@ -192,7 +197,8 @@ typedef struct {
} ais3624dq_ctrl_reg1_t;
#define AIS3624DQ_CTRL_REG2 0x21U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t hpcf : 2;
uint8_t hpen : 2;
@@ -209,7 +215,8 @@ typedef struct {
} ais3624dq_ctrl_reg2_t;
#define AIS3624DQ_CTRL_REG3 0x22U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t i1_cfg : 2;
uint8_t lir1 : 1;
@@ -228,7 +235,8 @@ typedef struct {
} ais3624dq_ctrl_reg3_t;
#define AIS3624DQ_CTRL_REG4 0x23U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t st : 3; /* STsign + ST */
@@ -245,7 +253,8 @@ typedef struct {
} ais3624dq_ctrl_reg4_t;
#define AIS3624DQ_CTRL_REG5 0x24U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t turnon : 2;
uint8_t not_used_01 : 6;
@@ -258,7 +267,8 @@ typedef struct {
#define AIS3624DQ_HP_FILTER_RESET 0x25U
#define AIS3624DQ_REFERENCE 0x26U
#define AIS3624DQ_STATUS_REG 0x27U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xda : 1;
uint8_t yda : 1;
@@ -287,7 +297,8 @@ typedef struct {
#define AIS3624DQ_OUT_Z_L 0x2CU
#define AIS3624DQ_OUT_Z_H 0x2DU
#define AIS3624DQ_INT1_CFG 0x30U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlie : 1;
uint8_t xhie : 1;
@@ -310,7 +321,8 @@ typedef struct {
} ais3624dq_int1_cfg_t;
#define AIS3624DQ_INT1_SRC 0x31U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
@@ -333,7 +345,8 @@ typedef struct {
} ais3624dq_int1_src_t;
#define AIS3624DQ_INT1_THS 0x32U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t not_used_01 : 1;
@@ -344,7 +357,8 @@ typedef struct {
} ais3624dq_int1_ths_t;
#define AIS3624DQ_INT1_DURATION 0x33U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d : 7;
uint8_t not_used_01 : 1;
@@ -356,7 +370,8 @@ typedef struct {
} ais3624dq_int1_duration_t;
#define AIS3624DQ_INT2_CFG 0x34U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlie : 1;
uint8_t xhie : 1;
@@ -380,7 +395,8 @@ typedef struct {
} ais3624dq_int2_cfg_t;
#define AIS3624DQ_INT2_SRC 0x35U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
@@ -404,7 +420,8 @@ typedef struct {
} ais3624dq_int2_src_t;
#define AIS3624DQ_INT2_THS 0x36U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t not_used_01 : 1;
@@ -415,7 +432,8 @@ typedef struct {
} ais3624dq_int2_ths_t;
#define AIS3624DQ_INT2_DURATION 0x37U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d : 7;
uint8_t not_used_01 : 1;
@@ -427,9 +445,9 @@ typedef struct {
/**
* @defgroup AIS3624DQ_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -437,7 +455,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
ais3624dq_ctrl_reg1_t ctrl_reg1;
ais3624dq_ctrl_reg2_t ctrl_reg2;
ais3624dq_ctrl_reg3_t ctrl_reg3;
@@ -461,9 +480,11 @@ typedef union{
*
*/
-int32_t ais3624dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t ais3624dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t ais3624dq_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t ais3624dq_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
float_t ais3624dq_from_fs6_to_mg(int16_t lsb);
@@ -479,7 +500,8 @@ int32_t ais3624dq_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t ais3624dq_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ais3624dq_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
AIS3624DQ_ODR_OFF = 0x00,
AIS3624DQ_ODR_Hz5 = 0x02,
AIS3624DQ_ODR_1Hz = 0x03,
@@ -491,10 +513,13 @@ typedef enum {
AIS3624DQ_ODR_400Hz = 0x21,
AIS3624DQ_ODR_1kHz = 0x31,
} ais3624dq_dr_t;
-int32_t ais3624dq_data_rate_set(stmdev_ctx_t *ctx, ais3624dq_dr_t val);
-int32_t ais3624dq_data_rate_get(stmdev_ctx_t *ctx, ais3624dq_dr_t *val);
+int32_t ais3624dq_data_rate_set(stmdev_ctx_t *ctx,
+ ais3624dq_dr_t val);
+int32_t ais3624dq_data_rate_get(stmdev_ctx_t *ctx,
+ ais3624dq_dr_t *val);
-typedef enum {
+typedef enum
+{
AIS3624DQ_NORMAL_MODE = 0,
AIS3624DQ_REF_MODE_ENABLE = 1,
} ais3624dq_hpm_t;
@@ -503,16 +528,21 @@ int32_t ais3624dq_reference_mode_set(stmdev_ctx_t *ctx,
int32_t ais3624dq_reference_mode_get(stmdev_ctx_t *ctx,
ais3624dq_hpm_t *val);
-typedef enum {
+typedef enum
+{
AIS3624DQ_6g = 0,
AIS3624DQ_12g = 1,
AIS3624DQ_24g = 3,
} ais3624dq_fs_t;
-int32_t ais3624dq_full_scale_set(stmdev_ctx_t *ctx, ais3624dq_fs_t val);
-int32_t ais3624dq_full_scale_get(stmdev_ctx_t *ctx, ais3624dq_fs_t *val);
+int32_t ais3624dq_full_scale_set(stmdev_ctx_t *ctx,
+ ais3624dq_fs_t val);
+int32_t ais3624dq_full_scale_get(stmdev_ctx_t *ctx,
+ ais3624dq_fs_t *val);
-int32_t ais3624dq_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ais3624dq_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ais3624dq_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ais3624dq_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t ais3624dq_status_reg_get(stmdev_ctx_t *ctx,
ais3624dq_status_reg_t *val);
@@ -520,29 +550,37 @@ int32_t ais3624dq_status_reg_get(stmdev_ctx_t *ctx,
int32_t ais3624dq_flag_data_ready_get(stmdev_ctx_t *ctx,
uint8_t *val);
-int32_t ais3624dq_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t ais3624dq_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
int32_t ais3624dq_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t ais3624dq_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ais3624dq_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
AIS3624DQ_ST_DISABLE = 0,
AIS3624DQ_ST_POSITIVE = 1,
AIS3624DQ_ST_NEGATIVE = 5,
} ais3624dq_st_t;
-int32_t ais3624dq_self_test_set(stmdev_ctx_t *ctx, ais3624dq_st_t val);
-int32_t ais3624dq_self_test_get(stmdev_ctx_t *ctx, ais3624dq_st_t *val);
+int32_t ais3624dq_self_test_set(stmdev_ctx_t *ctx,
+ ais3624dq_st_t val);
+int32_t ais3624dq_self_test_get(stmdev_ctx_t *ctx,
+ ais3624dq_st_t *val);
-typedef enum {
+typedef enum
+{
AIS3624DQ_LSB_AT_LOW_ADD = 0,
AIS3624DQ_MSB_AT_LOW_ADD = 1,
} ais3624dq_ble_t;
-int32_t ais3624dq_data_format_set(stmdev_ctx_t *ctx, ais3624dq_ble_t val);
-int32_t ais3624dq_data_format_get(stmdev_ctx_t *ctx, ais3624dq_ble_t *val);
+int32_t ais3624dq_data_format_set(stmdev_ctx_t *ctx,
+ ais3624dq_ble_t val);
+int32_t ais3624dq_data_format_get(stmdev_ctx_t *ctx,
+ ais3624dq_ble_t *val);
-typedef enum {
+typedef enum
+{
AIS3624DQ_CUT_OFF_8Hz = 0,
AIS3624DQ_CUT_OFF_16Hz = 1,
AIS3624DQ_CUT_OFF_32Hz = 2,
@@ -553,7 +591,8 @@ int32_t ais3624dq_hp_bandwidth_set(stmdev_ctx_t *ctx,
int32_t ais3624dq_hp_bandwidth_get(stmdev_ctx_t *ctx,
ais3624dq_hpcf_t *val);
-typedef enum {
+typedef enum
+{
AIS3624DQ_HP_DISABLE = 0,
AIS3624DQ_HP_ON_OUT = 4,
AIS3624DQ_HP_ON_INT1 = 1,
@@ -563,22 +602,30 @@ typedef enum {
AIS3624DQ_HP_ON_INT2_OUT = 6,
AIS3624DQ_HP_ON_INT1_OUT = 5,
} ais3624dq_hpen_t;
-int32_t ais3624dq_hp_path_set(stmdev_ctx_t *ctx, ais3624dq_hpen_t val);
-int32_t ais3624dq_hp_path_get(stmdev_ctx_t *ctx, ais3624dq_hpen_t *val);
+int32_t ais3624dq_hp_path_set(stmdev_ctx_t *ctx,
+ ais3624dq_hpen_t val);
+int32_t ais3624dq_hp_path_get(stmdev_ctx_t *ctx,
+ ais3624dq_hpen_t *val);
int32_t ais3624dq_hp_reset_get(stmdev_ctx_t *ctx);
-int32_t ais3624dq_hp_reference_value_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ais3624dq_hp_reference_value_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ais3624dq_hp_reference_value_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ais3624dq_hp_reference_value_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
AIS3624DQ_SPI_4_WIRE = 0,
AIS3624DQ_SPI_3_WIRE = 1,
} ais3624dq_sim_t;
-int32_t ais3624dq_spi_mode_set(stmdev_ctx_t *ctx, ais3624dq_sim_t val);
-int32_t ais3624dq_spi_mode_get(stmdev_ctx_t *ctx, ais3624dq_sim_t *val);
+int32_t ais3624dq_spi_mode_set(stmdev_ctx_t *ctx,
+ ais3624dq_sim_t val);
+int32_t ais3624dq_spi_mode_get(stmdev_ctx_t *ctx,
+ ais3624dq_sim_t *val);
-typedef enum {
+typedef enum
+{
AIS3624DQ_PAD1_INT1_SRC = 0,
AIS3624DQ_PAD1_INT1_OR_INT2_SRC = 1,
AIS3624DQ_PAD1_DRDY = 2,
@@ -589,7 +636,8 @@ int32_t ais3624dq_pin_int1_route_set(stmdev_ctx_t *ctx,
int32_t ais3624dq_pin_int1_route_get(stmdev_ctx_t *ctx,
ais3624dq_i1_cfg_t *val);
-typedef enum {
+typedef enum
+{
AIS3624DQ_INT1_PULSED = 0,
AIS3624DQ_INT1_LATCHED = 1,
} ais3624dq_lir1_t;
@@ -598,7 +646,8 @@ int32_t ais3624dq_int1_notification_set(stmdev_ctx_t *ctx,
int32_t ais3624dq_int1_notification_get(stmdev_ctx_t *ctx,
ais3624dq_lir1_t *val);
-typedef enum {
+typedef enum
+{
AIS3624DQ_PAD2_INT2_SRC = 0,
AIS3624DQ_PAD2_INT1_OR_INT2_SRC = 1,
AIS3624DQ_PAD2_DRDY = 2,
@@ -609,7 +658,8 @@ int32_t ais3624dq_pin_int2_route_set(stmdev_ctx_t *ctx,
int32_t ais3624dq_pin_int2_route_get(stmdev_ctx_t *ctx,
ais3624dq_i2_cfg_t *val);
-typedef enum {
+typedef enum
+{
AIS3624DQ_INT2_PULSED = 0,
AIS3624DQ_INT2_LATCHED = 1,
} ais3624dq_lir2_t;
@@ -618,14 +668,18 @@ int32_t ais3624dq_int2_notification_set(stmdev_ctx_t *ctx,
int32_t ais3624dq_int2_notification_get(stmdev_ctx_t *ctx,
ais3624dq_lir2_t *val);
-typedef enum {
+typedef enum
+{
AIS3624DQ_PUSH_PULL = 0,
AIS3624DQ_OPEN_DRAIN = 1,
} ais3624dq_pp_od_t;
-int32_t ais3624dq_pin_mode_set(stmdev_ctx_t *ctx, ais3624dq_pp_od_t val);
-int32_t ais3624dq_pin_mode_get(stmdev_ctx_t *ctx, ais3624dq_pp_od_t *val);
+int32_t ais3624dq_pin_mode_set(stmdev_ctx_t *ctx,
+ ais3624dq_pp_od_t val);
+int32_t ais3624dq_pin_mode_get(stmdev_ctx_t *ctx,
+ ais3624dq_pp_od_t *val);
-typedef enum {
+typedef enum
+{
AIS3624DQ_ACTIVE_HIGH = 0,
AIS3624DQ_ACTIVE_LOW = 1,
} ais3624dq_ihl_t;
@@ -634,7 +688,8 @@ int32_t ais3624dq_pin_polarity_set(stmdev_ctx_t *ctx,
int32_t ais3624dq_pin_polarity_get(stmdev_ctx_t *ctx,
ais3624dq_ihl_t *val);
-typedef struct {
+typedef struct
+{
uint8_t int1_xlie : 1;
uint8_t int1_xhie : 1;
uint8_t int1_ylie : 1;
@@ -647,7 +702,8 @@ int32_t ais3624dq_int1_on_threshold_conf_set(stmdev_ctx_t *ctx,
int32_t ais3624dq_int1_on_threshold_conf_get(stmdev_ctx_t *ctx,
ais3624dq_int1_on_th_conf_t *val);
-typedef enum {
+typedef enum
+{
AIS3624DQ_INT1_ON_THRESHOLD_OR = 0,
AIS3624DQ_INT1_ON_THRESHOLD_AND = 1,
} ais3624dq_int1_aoi_t;
@@ -665,7 +721,8 @@ int32_t ais3624dq_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t ais3624dq_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ais3624dq_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef struct {
+typedef struct
+{
uint8_t int2_xlie : 1;
uint8_t int2_xhie : 1;
uint8_t int2_ylie : 1;
@@ -678,7 +735,8 @@ int32_t ais3624dq_int2_on_threshold_conf_set(stmdev_ctx_t *ctx,
int32_t ais3624dq_int2_on_threshold_conf_get(stmdev_ctx_t *ctx,
ais3624dq_int2_on_th_conf_t *val);
-typedef enum {
+typedef enum
+{
AIS3624DQ_INT2_ON_THRESHOLD_OR = 0,
AIS3624DQ_INT2_ON_THRESHOLD_AND = 1,
} ais3624dq_int2_aoi_t;
@@ -699,7 +757,8 @@ int32_t ais3624dq_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t ais3624dq_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ais3624dq_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
AIS3624DQ_6D_INT1_DISABLE = 0,
AIS3624DQ_6D_INT1_MOVEMENT = 1,
AIS3624DQ_6D_INT1_POSITION = 3,
@@ -712,10 +771,13 @@ int32_t ais3624dq_int1_6d_mode_get(stmdev_ctx_t *ctx,
int32_t ais3624dq_int1_6d_src_get(stmdev_ctx_t *ctx,
ais3624dq_int1_src_t *val);
-int32_t ais3624dq_int1_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ais3624dq_int1_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ais3624dq_int1_6d_treshold_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ais3624dq_int1_6d_treshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
AIS3624DQ_6D_INT2_DISABLE = 0,
AIS3624DQ_6D_INT2_MOVEMENT = 1,
AIS3624DQ_6D_INT2_POSITION = 3,
@@ -728,8 +790,10 @@ int32_t ais3624dq_int2_6d_mode_get(stmdev_ctx_t *ctx,
int32_t ais3624dq_int2_6d_src_get(stmdev_ctx_t *ctx,
ais3624dq_int2_src_t *val);
-int32_t ais3624dq_int2_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ais3624dq_int2_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ais3624dq_int2_6d_treshold_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ais3624dq_int2_6d_treshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
/**
*@}
diff --git a/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.c b/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.c
index fcf95d2e71510634a9a532d4fc1d21db73ae1d87..e151b90386510b3a4d9542816f3ab854ba0517c6 100644
--- a/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.c
+++ b/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file asm330lhh_reg.c
- * @author Sensors Software Solution Team
- * @brief ASM330LHH driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file asm330lhh_reg.c
+ * @author Sensors Software Solution Team
+ * @brief ASM330LHH driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "asm330lhh_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t asm330lhh_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t asm330lhh_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t asm330lhh_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t asm330lhh_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t asm330lhh_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -171,12 +177,16 @@ int32_t asm330lhh_xl_full_scale_set(stmdev_ctx_t *ctx,
asm330lhh_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
ctrl1_xl.fs_xl = (uint8_t)val;
ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
+ (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -194,24 +204,32 @@ int32_t asm330lhh_xl_full_scale_get(stmdev_ctx_t *ctx,
asm330lhh_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- switch (ctrl1_xl.fs_xl){
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
+
+ switch (ctrl1_xl.fs_xl)
+ {
case ASM330LHH_2g:
*val = ASM330LHH_2g;
break;
+
case ASM330LHH_16g:
*val = ASM330LHH_16g;
break;
+
case ASM330LHH_4g:
*val = ASM330LHH_4g;
break;
+
case ASM330LHH_8g:
*val = ASM330LHH_8g;
break;
+
default:
*val = ASM330LHH_2g;
break;
}
+
return ret;
}
@@ -229,12 +247,16 @@ int32_t asm330lhh_xl_data_rate_set(stmdev_ctx_t *ctx,
asm330lhh_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
- ctrl1_xl.odr_xl= (uint8_t)val;
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl1_xl.odr_xl = (uint8_t)val;
ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
+ (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -252,48 +274,64 @@ int32_t asm330lhh_xl_data_rate_get(stmdev_ctx_t *ctx,
asm330lhh_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- switch (ctrl1_xl.odr_xl){
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
+
+ switch (ctrl1_xl.odr_xl)
+ {
case ASM330LHH_XL_ODR_OFF:
*val = ASM330LHH_XL_ODR_OFF;
break;
+
case ASM330LHH_XL_ODR_12Hz5:
*val = ASM330LHH_XL_ODR_12Hz5;
break;
+
case ASM330LHH_XL_ODR_26Hz:
*val = ASM330LHH_XL_ODR_26Hz;
break;
+
case ASM330LHH_XL_ODR_52Hz:
*val = ASM330LHH_XL_ODR_52Hz;
break;
+
case ASM330LHH_XL_ODR_104Hz:
*val = ASM330LHH_XL_ODR_104Hz;
break;
+
case ASM330LHH_XL_ODR_208Hz:
*val = ASM330LHH_XL_ODR_208Hz;
break;
+
case ASM330LHH_XL_ODR_417Hz:
*val = ASM330LHH_XL_ODR_417Hz;
break;
+
case ASM330LHH_XL_ODR_833Hz:
*val = ASM330LHH_XL_ODR_833Hz;
break;
+
case ASM330LHH_XL_ODR_1667Hz:
*val = ASM330LHH_XL_ODR_1667Hz;
break;
+
case ASM330LHH_XL_ODR_3333Hz:
*val = ASM330LHH_XL_ODR_3333Hz;
break;
+
case ASM330LHH_XL_ODR_6667Hz:
*val = ASM330LHH_XL_ODR_6667Hz;
break;
+
case ASM330LHH_XL_ODR_6Hz5:
*val = ASM330LHH_XL_ODR_6Hz5;
break;
+
default:
*val = ASM330LHH_XL_ODR_OFF;
break;
}
+
return ret;
}
@@ -311,11 +349,14 @@ int32_t asm330lhh_gy_full_scale_set(stmdev_ctx_t *ctx,
asm330lhh_ctrl2_g_t ctrl2_g;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- if(ret == 0){
- ctrl2_g.fs_g= (uint8_t)val;
- ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
+
+ if (ret == 0)
+ {
+ ctrl2_g.fs_g = (uint8_t)val;
+ ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
}
+
return ret;
}
@@ -333,30 +374,39 @@ int32_t asm330lhh_gy_full_scale_get(stmdev_ctx_t *ctx,
asm330lhh_ctrl2_g_t ctrl2_g;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- switch (ctrl2_g.fs_g){
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
+
+ switch (ctrl2_g.fs_g)
+ {
case ASM330LHH_125dps:
*val = ASM330LHH_125dps;
break;
+
case ASM330LHH_250dps:
*val = ASM330LHH_250dps;
break;
+
case ASM330LHH_500dps:
*val = ASM330LHH_500dps;
break;
+
case ASM330LHH_1000dps:
*val = ASM330LHH_1000dps;
break;
+
case ASM330LHH_2000dps:
*val = ASM330LHH_2000dps;
break;
+
case ASM330LHH_4000dps:
*val = ASM330LHH_4000dps;
break;
+
default:
*val = ASM330LHH_125dps;
break;
}
+
return ret;
}
@@ -374,11 +424,14 @@ int32_t asm330lhh_gy_data_rate_set(stmdev_ctx_t *ctx,
asm330lhh_ctrl2_g_t ctrl2_g;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- if(ret == 0){
- ctrl2_g.odr_g= (uint8_t)val;
- ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
+
+ if (ret == 0)
+ {
+ ctrl2_g.odr_g = (uint8_t)val;
+ ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
}
+
return ret;
}
@@ -396,45 +449,59 @@ int32_t asm330lhh_gy_data_rate_get(stmdev_ctx_t *ctx,
asm330lhh_ctrl2_g_t ctrl2_g;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- switch (ctrl2_g.odr_g){
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
+
+ switch (ctrl2_g.odr_g)
+ {
case ASM330LHH_GY_ODR_OFF:
*val = ASM330LHH_GY_ODR_OFF;
break;
+
case ASM330LHH_GY_ODR_12Hz5:
*val = ASM330LHH_GY_ODR_12Hz5;
break;
+
case ASM330LHH_GY_ODR_26Hz:
*val = ASM330LHH_GY_ODR_26Hz;
break;
+
case ASM330LHH_GY_ODR_52Hz:
*val = ASM330LHH_GY_ODR_52Hz;
break;
+
case ASM330LHH_GY_ODR_104Hz:
*val = ASM330LHH_GY_ODR_104Hz;
break;
+
case ASM330LHH_GY_ODR_208Hz:
*val = ASM330LHH_GY_ODR_208Hz;
break;
+
case ASM330LHH_GY_ODR_417Hz:
*val = ASM330LHH_GY_ODR_417Hz;
break;
+
case ASM330LHH_GY_ODR_833Hz:
*val = ASM330LHH_GY_ODR_833Hz;
break;
+
case ASM330LHH_GY_ODR_1667Hz:
*val = ASM330LHH_GY_ODR_1667Hz;
break;
+
case ASM330LHH_GY_ODR_3333Hz:
*val = ASM330LHH_GY_ODR_3333Hz;
break;
+
case ASM330LHH_GY_ODR_6667Hz:
*val = ASM330LHH_GY_ODR_6667Hz;
break;
+
default:
*val = ASM330LHH_GY_ODR_OFF;
break;
}
+
return ret;
}
@@ -446,16 +513,20 @@ int32_t asm330lhh_gy_data_rate_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t asm330lhh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t asm330lhh_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
asm330lhh_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.bdu= (uint8_t)val;
- ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.bdu = (uint8_t)val;
+ ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -467,12 +538,13 @@ int32_t asm330lhh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t asm330lhh_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t asm330lhh_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
asm330lhh_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.bdu;
return ret;
@@ -488,16 +560,19 @@ int32_t asm330lhh_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t asm330lhh_xl_offset_weight_set(stmdev_ctx_t *ctx,
- asm330lhh_usr_off_w_t val)
+ asm330lhh_usr_off_w_t val)
{
asm330lhh_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
- ctrl6_c.usr_off_w= (uint8_t)val;
- ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl6_c.usr_off_w = (uint8_t)val;
+ ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -516,19 +591,23 @@ int32_t asm330lhh_xl_offset_weight_get(stmdev_ctx_t *ctx,
asm330lhh_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
- switch (ctrl6_c.usr_off_w){
+ switch (ctrl6_c.usr_off_w)
+ {
case ASM330LHH_LSb_1mg:
*val = ASM330LHH_LSb_1mg;
break;
+
case ASM330LHH_LSb_16mg:
*val = ASM330LHH_LSb_16mg;
break;
+
default:
*val = ASM330LHH_LSb_1mg;
break;
}
+
return ret;
}
@@ -548,18 +627,24 @@ int32_t asm330lhh_all_sources_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_ALL_INT_SRC,
- (uint8_t*)&val->all_int_src, 1);
- if(ret == 0){
+ (uint8_t *)&val->all_int_src, 1);
+
+ if (ret == 0)
+ {
ret = asm330lhh_read_reg(ctx, ASM330LHH_WAKE_UP_SRC,
- (uint8_t*)&val->wake_up_src, 1);
+ (uint8_t *)&val->wake_up_src, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = asm330lhh_read_reg(ctx, ASM330LHH_D6D_SRC,
- (uint8_t*)&val->d6d_src, 1);
+ (uint8_t *)&val->d6d_src, 1);
}
- if(ret == 0){
- ret = asm330lhh_read_reg(ctx, ASM330LHH_STATUS_REG,
- (uint8_t*)&val->status_reg, 1);
+
+ if (ret == 0)
+ {
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_STATUS_REG,
+ (uint8_t *)&val->status_reg, 1);
}
return ret;
@@ -577,7 +662,9 @@ int32_t asm330lhh_status_reg_get(stmdev_ctx_t *ctx,
asm330lhh_status_reg_t *val)
{
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_STATUS_REG, (uint8_t*) val, 1);
+
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_STATUS_REG, (uint8_t *) val, 1);
+
return ret;
}
@@ -589,13 +676,14 @@ int32_t asm330lhh_status_reg_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t asm330lhh_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t asm330lhh_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
asm330lhh_status_reg_t status_reg;
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_STATUS_REG,
- (uint8_t*)&status_reg, 1);
+ (uint8_t *)&status_reg, 1);
*val = status_reg.xlda;
return ret;
@@ -609,13 +697,14 @@ int32_t asm330lhh_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t asm330lhh_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t asm330lhh_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
asm330lhh_status_reg_t status_reg;
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_STATUS_REG,
- (uint8_t*)&status_reg, 1);
+ (uint8_t *)&status_reg, 1);
*val = status_reg.gda;
return ret;
@@ -629,13 +718,14 @@ int32_t asm330lhh_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t asm330lhh_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t asm330lhh_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
asm330lhh_status_reg_t status_reg;
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_STATUS_REG,
- (uint8_t*)&status_reg, 1);
+ (uint8_t *)&status_reg, 1);
*val = status_reg.tda;
return ret;
@@ -651,10 +741,13 @@ int32_t asm330lhh_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t asm330lhh_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t asm330lhh_xl_usr_offset_x_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
+
ret = asm330lhh_write_reg(ctx, ASM330LHH_X_OFS_USR, buff, 1);
+
return ret;
}
@@ -668,10 +761,13 @@ int32_t asm330lhh_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t asm330lhh_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t asm330lhh_xl_usr_offset_x_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
+
ret = asm330lhh_read_reg(ctx, ASM330LHH_X_OFS_USR, buff, 1);
+
return ret;
}
@@ -685,10 +781,13 @@ int32_t asm330lhh_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t asm330lhh_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t asm330lhh_xl_usr_offset_y_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
+
ret = asm330lhh_write_reg(ctx, ASM330LHH_Y_OFS_USR, buff, 1);
+
return ret;
}
@@ -702,10 +801,13 @@ int32_t asm330lhh_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t asm330lhh_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t asm330lhh_xl_usr_offset_y_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
+
ret = asm330lhh_read_reg(ctx, ASM330LHH_Y_OFS_USR, buff, 1);
+
return ret;
}
@@ -719,10 +821,13 @@ int32_t asm330lhh_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t asm330lhh_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t asm330lhh_xl_usr_offset_z_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
+
ret = asm330lhh_write_reg(ctx, ASM330LHH_Z_OFS_USR, buff, 1);
+
return ret;
}
@@ -736,10 +841,13 @@ int32_t asm330lhh_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t asm330lhh_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t asm330lhh_xl_usr_offset_z_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
+
ret = asm330lhh_read_reg(ctx, ASM330LHH_Z_OFS_USR, buff, 1);
+
return ret;
}
@@ -756,11 +864,14 @@ int32_t asm330lhh_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val)
asm330lhh_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
- ctrl7_g.usr_off_on_out= (uint8_t)val;
- ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
+ ctrl7_g.usr_off_on_out = (uint8_t)val;
+ ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
}
+
return ret;
}
@@ -777,7 +888,7 @@ int32_t asm330lhh_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val)
asm330lhh_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
*val = ctrl7_g.usr_off_on_out;
return ret;
@@ -806,7 +917,6 @@ int32_t asm330lhh_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t asm330lhh_timestamp_rst(stmdev_ctx_t *ctx)
{
uint8_t rst_val = 0xAA;
-
return asm330lhh_write_reg(ctx, ASM330LHH_TIMESTAMP2, &rst_val, 1);
}
@@ -823,12 +933,16 @@ int32_t asm330lhh_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
asm330lhh_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
- ctrl10_c.timestamp_en= (uint8_t)val;
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL10_C,
+ (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl10_c.timestamp_en = (uint8_t)val;
ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL10_C,
- (uint8_t*)&ctrl10_c, 1);
+ (uint8_t *)&ctrl10_c, 1);
}
+
return ret;
}
@@ -845,7 +959,8 @@ int32_t asm330lhh_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
asm330lhh_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL10_C,
+ (uint8_t *)&ctrl10_c, 1);
*val = ctrl10_c.timestamp_en;
return ret;
@@ -901,11 +1016,14 @@ int32_t asm330lhh_rounding_mode_set(stmdev_ctx_t *ctx,
asm330lhh_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
- ctrl5_c.rounding= (uint8_t)val;
- ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl5_c.rounding = (uint8_t)val;
+ ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -923,24 +1041,31 @@ int32_t asm330lhh_rounding_mode_get(stmdev_ctx_t *ctx,
asm330lhh_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- switch (ctrl5_c.rounding){
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ switch (ctrl5_c.rounding)
+ {
case ASM330LHH_NO_ROUND:
*val = ASM330LHH_NO_ROUND;
break;
+
case ASM330LHH_ROUND_XL:
*val = ASM330LHH_ROUND_XL;
break;
+
case ASM330LHH_ROUND_GY:
*val = ASM330LHH_ROUND_GY;
break;
+
case ASM330LHH_ROUND_GY_XL:
*val = ASM330LHH_ROUND_GY_XL;
break;
+
default:
*val = ASM330LHH_NO_ROUND;
break;
}
+
return ret;
}
@@ -975,12 +1100,13 @@ int32_t asm330lhh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t asm330lhh_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
+int32_t asm330lhh_angular_rate_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
{
uint8_t buff[6];
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_OUTX_L_G, buff, 6);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_OUTX_L_G, buff, 6);
val[0] = (int16_t)buff[1];
val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
@@ -1000,12 +1126,13 @@ int32_t asm330lhh_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t asm330lhh_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
+int32_t asm330lhh_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
{
uint8_t buff[6];
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_OUTX_L_A, buff, 6);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_OUTX_L_A, buff, 6);
val[0] = (int16_t)buff[1];
val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
@@ -1027,7 +1154,9 @@ int32_t asm330lhh_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
int32_t asm330lhh_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *val)
{
int32_t ret;
+
ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_DATA_OUT_X_L, val, 6);
+
return ret;
}
@@ -1038,7 +1167,7 @@ int32_t asm330lhh_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @defgroup ASM330LHH_common
- * @brief This section groups common usefull functions.
+ * @brief This section groups common useful functions.
* @{
*
*/
@@ -1056,11 +1185,16 @@ int32_t asm330lhh_device_conf_set(stmdev_ctx_t *ctx, uint8_t val)
asm330lhh_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
ctrl9_xl.device_conf = (uint8_t)val;
- ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -1077,7 +1211,8 @@ int32_t asm330lhh_device_conf_get(stmdev_ctx_t *ctx, uint8_t *val)
asm330lhh_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
*val = ctrl9_xl.device_conf;
return ret;
@@ -1099,12 +1234,15 @@ int32_t asm330lhh_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_INTERNAL_FREQ_FINE,
- (uint8_t*)&internal_freq_fine, 1);
- if(ret == 0){
- internal_freq_fine.freq_fine= (uint8_t)val;
+ (uint8_t *)&internal_freq_fine, 1);
+
+ if (ret == 0)
+ {
+ internal_freq_fine.freq_fine = (uint8_t)val;
ret = asm330lhh_write_reg(ctx, ASM330LHH_INTERNAL_FREQ_FINE,
- (uint8_t*)&internal_freq_fine, 1);
+ (uint8_t *)&internal_freq_fine, 1);
}
+
return ret;
}
@@ -1124,7 +1262,7 @@ int32_t asm330lhh_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_INTERNAL_FREQ_FINE,
- (uint8_t*)&internal_freq_fine, 1);
+ (uint8_t *)&internal_freq_fine, 1);
*val = internal_freq_fine.freq_fine;
return ret;
@@ -1146,12 +1284,15 @@ int32_t asm330lhh_data_ready_mode_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if(ret == 0){
- counter_bdr_reg1.dataready_pulsed= (uint8_t)val;
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
+ counter_bdr_reg1.dataready_pulsed = (uint8_t)val;
ret = asm330lhh_write_reg(ctx, ASM330LHH_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
}
+
return ret;
}
@@ -1171,18 +1312,23 @@ int32_t asm330lhh_data_ready_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- switch (counter_bdr_reg1.dataready_pulsed){
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ switch (counter_bdr_reg1.dataready_pulsed)
+ {
case ASM330LHH_DRDY_LATCHED:
*val = ASM330LHH_DRDY_LATCHED;
break;
+
case ASM330LHH_DRDY_PULSED:
*val = ASM330LHH_DRDY_PULSED;
break;
+
default:
*val = ASM330LHH_DRDY_LATCHED;
break;
}
+
return ret;
}
@@ -1197,7 +1343,9 @@ int32_t asm330lhh_data_ready_mode_get(stmdev_ctx_t *ctx,
int32_t asm330lhh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = asm330lhh_read_reg(ctx, ASM330LHH_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -1214,11 +1362,14 @@ int32_t asm330lhh_reset_set(stmdev_ctx_t *ctx, uint8_t val)
asm330lhh_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.sw_reset= (uint8_t)val;
- ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.sw_reset = (uint8_t)val;
+ ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1235,7 +1386,7 @@ int32_t asm330lhh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
asm330lhh_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.sw_reset;
return ret;
@@ -1255,11 +1406,14 @@ int32_t asm330lhh_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
asm330lhh_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.if_inc= (uint8_t)val;
- ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.if_inc = (uint8_t)val;
+ ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1277,7 +1431,7 @@ int32_t asm330lhh_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
asm330lhh_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.if_inc;
return ret;
@@ -1296,11 +1450,14 @@ int32_t asm330lhh_boot_set(stmdev_ctx_t *ctx, uint8_t val)
asm330lhh_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.boot= (uint8_t)val;
- ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.boot = (uint8_t)val;
+ ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1317,7 +1474,7 @@ int32_t asm330lhh_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
asm330lhh_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.boot;
return ret;
@@ -1339,11 +1496,14 @@ int32_t asm330lhh_xl_self_test_set(stmdev_ctx_t *ctx,
asm330lhh_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
- ctrl5_c.st_xl= (uint8_t)val;
- ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl5_c.st_xl = (uint8_t)val;
+ ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -1361,22 +1521,27 @@ int32_t asm330lhh_xl_self_test_get(stmdev_ctx_t *ctx,
asm330lhh_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
- switch (ctrl5_c.st_xl){
+ switch (ctrl5_c.st_xl)
+ {
case ASM330LHH_XL_ST_DISABLE:
*val = ASM330LHH_XL_ST_DISABLE;
break;
+
case ASM330LHH_XL_ST_POSITIVE:
*val = ASM330LHH_XL_ST_POSITIVE;
break;
+
case ASM330LHH_XL_ST_NEGATIVE:
*val = ASM330LHH_XL_ST_NEGATIVE;
break;
+
default:
*val = ASM330LHH_XL_ST_DISABLE;
break;
}
+
return ret;
}
@@ -1394,11 +1559,14 @@ int32_t asm330lhh_gy_self_test_set(stmdev_ctx_t *ctx,
asm330lhh_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
- ctrl5_c.st_g= (uint8_t)val;
- ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl5_c.st_g = (uint8_t)val;
+ ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -1416,22 +1584,27 @@ int32_t asm330lhh_gy_self_test_get(stmdev_ctx_t *ctx,
asm330lhh_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
- switch (ctrl5_c.st_g){
+ switch (ctrl5_c.st_g)
+ {
case ASM330LHH_GY_ST_DISABLE:
*val = ASM330LHH_GY_ST_DISABLE;
break;
+
case ASM330LHH_GY_ST_POSITIVE:
*val = ASM330LHH_GY_ST_POSITIVE;
break;
+
case ASM330LHH_GY_ST_NEGATIVE:
*val = ASM330LHH_GY_ST_NEGATIVE;
break;
+
default:
*val = ASM330LHH_GY_ST_DISABLE;
break;
}
+
return ret;
}
@@ -1461,12 +1634,16 @@ int32_t asm330lhh_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val)
asm330lhh_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
- ctrl1_xl.lpf2_xl_en= (uint8_t)val;
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl1_xl.lpf2_xl_en = (uint8_t)val;
ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
+ (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -1483,7 +1660,8 @@ int32_t asm330lhh_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val)
asm330lhh_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
*val = ctrl1_xl.lpf2_xl_en;
return ret;
@@ -1503,11 +1681,14 @@ int32_t asm330lhh_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val)
asm330lhh_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ctrl4_c.lpf1_sel_g= (uint8_t)val;
- ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl4_c.lpf1_sel_g = (uint8_t)val;
+ ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -1525,7 +1706,7 @@ int32_t asm330lhh_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val)
asm330lhh_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.lpf1_sel_g;
return ret;
@@ -1540,16 +1721,20 @@ int32_t asm330lhh_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t asm330lhh_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t asm330lhh_filter_settling_mask_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
asm330lhh_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ctrl4_c.drdy_mask= (uint8_t)val;
- ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl4_c.drdy_mask = (uint8_t)val;
+ ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -1568,7 +1753,7 @@ int32_t asm330lhh_filter_settling_mask_get(stmdev_ctx_t *ctx,
asm330lhh_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.drdy_mask;
return ret;
@@ -1588,11 +1773,14 @@ int32_t asm330lhh_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
asm330lhh_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
- ctrl6_c.ftype= (uint8_t)val;
- ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl6_c.ftype = (uint8_t)val;
+ ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -1610,37 +1798,47 @@ int32_t asm330lhh_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
asm330lhh_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
- switch (ctrl6_c.ftype){
+ switch (ctrl6_c.ftype)
+ {
case ASM330LHH_ULTRA_LIGHT:
*val = ASM330LHH_ULTRA_LIGHT;
break;
+
case ASM330LHH_VERY_LIGHT:
*val = ASM330LHH_VERY_LIGHT;
break;
+
case ASM330LHH_LIGHT:
*val = ASM330LHH_LIGHT;
break;
+
case ASM330LHH_MEDIUM:
*val = ASM330LHH_MEDIUM;
break;
+
case ASM330LHH_STRONG:
*val = ASM330LHH_STRONG;
break;
+
case ASM330LHH_VERY_STRONG:
*val = ASM330LHH_VERY_STRONG;
break;
+
case ASM330LHH_AGGRESSIVE:
*val = ASM330LHH_AGGRESSIVE;
break;
+
case ASM330LHH_XTREME:
*val = ASM330LHH_XTREME;
break;
+
default:
*val = ASM330LHH_ULTRA_LIGHT;
break;
}
+
return ret;
}
@@ -1657,12 +1855,16 @@ int32_t asm330lhh_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val)
asm330lhh_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
- ctrl8_xl.low_pass_on_6d= (uint8_t)val;
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl8_xl.low_pass_on_6d = (uint8_t)val;
ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL8_XL,
- (uint8_t*)&ctrl8_xl, 1);
+ (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -1679,7 +1881,8 @@ int32_t asm330lhh_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val)
asm330lhh_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
*val = ctrl8_xl.low_pass_on_6d;
return ret;
@@ -1700,14 +1903,18 @@ int32_t asm330lhh_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
asm330lhh_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
ctrl8_xl.hp_slope_xl_en = (((uint8_t)val & 0x10U) >> 4);
ctrl8_xl.hp_ref_mode_xl = (((uint8_t)val & 0x20U) >> 5);
ctrl8_xl.hpcf_xl = (uint8_t)val & 0x07U;
ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL8_XL,
- (uint8_t*)&ctrl8_xl, 1);
+ (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -1726,82 +1933,110 @@ int32_t asm330lhh_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
asm330lhh_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- switch (( (ctrl8_xl.hp_ref_mode_xl << 5) +(ctrl8_xl.hp_slope_xl_en << 4) +
- ctrl8_xl.hpcf_xl )){
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
+
+ switch (((ctrl8_xl.hp_ref_mode_xl << 5) + (ctrl8_xl.hp_slope_xl_en <<
+ 4) +
+ ctrl8_xl.hpcf_xl))
+ {
case ASM330LHH_HP_PATH_DISABLE_ON_OUT:
*val = ASM330LHH_HP_PATH_DISABLE_ON_OUT;
break;
+
case ASM330LHH_SLOPE_ODR_DIV_4:
*val = ASM330LHH_SLOPE_ODR_DIV_4;
break;
+
case ASM330LHH_HP_ODR_DIV_10:
*val = ASM330LHH_HP_ODR_DIV_10;
break;
+
case ASM330LHH_HP_ODR_DIV_20:
*val = ASM330LHH_HP_ODR_DIV_20;
break;
+
case ASM330LHH_HP_ODR_DIV_45:
*val = ASM330LHH_HP_ODR_DIV_45;
break;
+
case ASM330LHH_HP_ODR_DIV_100:
*val = ASM330LHH_HP_ODR_DIV_100;
break;
+
case ASM330LHH_HP_ODR_DIV_200:
*val = ASM330LHH_HP_ODR_DIV_200;
break;
+
case ASM330LHH_HP_ODR_DIV_400:
*val = ASM330LHH_HP_ODR_DIV_400;
break;
+
case ASM330LHH_HP_ODR_DIV_800:
*val = ASM330LHH_HP_ODR_DIV_800;
break;
+
case ASM330LHH_HP_REF_MD_ODR_DIV_10:
*val = ASM330LHH_HP_REF_MD_ODR_DIV_10;
break;
+
case ASM330LHH_HP_REF_MD_ODR_DIV_20:
*val = ASM330LHH_HP_REF_MD_ODR_DIV_20;
break;
+
case ASM330LHH_HP_REF_MD_ODR_DIV_45:
*val = ASM330LHH_HP_REF_MD_ODR_DIV_45;
break;
+
case ASM330LHH_HP_REF_MD_ODR_DIV_100:
*val = ASM330LHH_HP_REF_MD_ODR_DIV_100;
break;
+
case ASM330LHH_HP_REF_MD_ODR_DIV_200:
*val = ASM330LHH_HP_REF_MD_ODR_DIV_200;
break;
+
case ASM330LHH_HP_REF_MD_ODR_DIV_400:
*val = ASM330LHH_HP_REF_MD_ODR_DIV_400;
break;
+
case ASM330LHH_HP_REF_MD_ODR_DIV_800:
*val = ASM330LHH_HP_REF_MD_ODR_DIV_800;
break;
+
case ASM330LHH_LP_ODR_DIV_10:
*val = ASM330LHH_LP_ODR_DIV_10;
break;
+
case ASM330LHH_LP_ODR_DIV_20:
*val = ASM330LHH_LP_ODR_DIV_20;
break;
+
case ASM330LHH_LP_ODR_DIV_45:
*val = ASM330LHH_LP_ODR_DIV_45;
break;
+
case ASM330LHH_LP_ODR_DIV_100:
*val = ASM330LHH_LP_ODR_DIV_100;
break;
+
case ASM330LHH_LP_ODR_DIV_200:
*val = ASM330LHH_LP_ODR_DIV_200;
break;
+
case ASM330LHH_LP_ODR_DIV_400:
*val = ASM330LHH_LP_ODR_DIV_400;
break;
+
case ASM330LHH_LP_ODR_DIV_800:
*val = ASM330LHH_LP_ODR_DIV_800;
break;
+
default:
*val = ASM330LHH_HP_PATH_DISABLE_ON_OUT;
break;
}
+
return ret;
}
@@ -1820,12 +2055,16 @@ int32_t asm330lhh_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val)
asm330lhh_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
- ctrl8_xl.fastsettl_mode_xl= (uint8_t)val;
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl8_xl.fastsettl_mode_xl = (uint8_t)val;
ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL8_XL,
- (uint8_t*)&ctrl8_xl, 1);
+ (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -1839,12 +2078,14 @@ int32_t asm330lhh_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t asm330lhh_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t asm330lhh_xl_fast_settling_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
asm330lhh_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
*val = ctrl8_xl.fastsettl_mode_xl;
return ret;
@@ -1865,12 +2106,16 @@ int32_t asm330lhh_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
asm330lhh_int_cfg0_t int_cfg0;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_INT_CFG0, (uint8_t*)&int_cfg0, 1);
- if(ret == 0){
- int_cfg0.slope_fds= (uint8_t)val;
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_INT_CFG0,
+ (uint8_t *)&int_cfg0, 1);
+
+ if (ret == 0)
+ {
+ int_cfg0.slope_fds = (uint8_t)val;
ret = asm330lhh_write_reg(ctx, ASM330LHH_INT_CFG0,
- (uint8_t*)&int_cfg0, 1);
+ (uint8_t *)&int_cfg0, 1);
}
+
return ret;
}
@@ -1889,18 +2134,24 @@ int32_t asm330lhh_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
asm330lhh_int_cfg0_t int_cfg0;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_INT_CFG0, (uint8_t*)&int_cfg0, 1);
- switch (int_cfg0.slope_fds){
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_INT_CFG0,
+ (uint8_t *)&int_cfg0, 1);
+
+ switch (int_cfg0.slope_fds)
+ {
case ASM330LHH_USE_SLOPE:
*val = ASM330LHH_USE_SLOPE;
break;
+
case ASM330LHH_USE_HPF:
*val = ASM330LHH_USE_HPF;
break;
+
default:
*val = ASM330LHH_USE_SLOPE;
break;
}
+
return ret;
}
@@ -1919,12 +2170,15 @@ int32_t asm330lhh_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
asm330lhh_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
ctrl7_g.hp_en_g = (((uint8_t)val & 0x80U) >> 7);
ctrl7_g.hpm_g = (uint8_t)val & 0x03U;
- ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
}
+
return ret;
}
@@ -1943,28 +2197,35 @@ int32_t asm330lhh_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
asm330lhh_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
- switch ((ctrl7_g.hp_en_g << 7) + ctrl7_g.hpm_g){
+ switch ((ctrl7_g.hp_en_g << 7) + ctrl7_g.hpm_g)
+ {
case ASM330LHH_HP_FILTER_NONE:
*val = ASM330LHH_HP_FILTER_NONE;
break;
+
case ASM330LHH_HP_FILTER_16mHz:
*val = ASM330LHH_HP_FILTER_16mHz;
break;
+
case ASM330LHH_HP_FILTER_65mHz:
*val = ASM330LHH_HP_FILTER_65mHz;
break;
+
case ASM330LHH_HP_FILTER_260mHz:
*val = ASM330LHH_HP_FILTER_260mHz;
break;
+
case ASM330LHH_HP_FILTER_1Hz04:
*val = ASM330LHH_HP_FILTER_1Hz04;
break;
+
default:
*val = ASM330LHH_HP_FILTER_NONE;
break;
}
+
return ret;
}
@@ -1995,11 +2256,16 @@ int32_t asm330lhh_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
asm330lhh_pin_ctrl_t pin_ctrl;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
- if(ret == 0){
- pin_ctrl.sdo_pu_en= (uint8_t)val;
- ret = asm330lhh_write_reg(ctx, ASM330LHH_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_PIN_CTRL,
+ (uint8_t *)&pin_ctrl, 1);
+
+ if (ret == 0)
+ {
+ pin_ctrl.sdo_pu_en = (uint8_t)val;
+ ret = asm330lhh_write_reg(ctx, ASM330LHH_PIN_CTRL,
+ (uint8_t *)&pin_ctrl, 1);
}
+
return ret;
}
@@ -2017,19 +2283,24 @@ int32_t asm330lhh_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
asm330lhh_pin_ctrl_t pin_ctrl;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_PIN_CTRL,
+ (uint8_t *)&pin_ctrl, 1);
- switch (pin_ctrl.sdo_pu_en){
+ switch (pin_ctrl.sdo_pu_en)
+ {
case ASM330LHH_PULL_UP_DISC:
*val = ASM330LHH_PULL_UP_DISC;
break;
+
case ASM330LHH_PULL_UP_CONNECT:
*val = ASM330LHH_PULL_UP_CONNECT;
break;
+
default:
*val = ASM330LHH_PULL_UP_DISC;
break;
}
+
return ret;
}
@@ -2046,11 +2317,14 @@ int32_t asm330lhh_spi_mode_set(stmdev_ctx_t *ctx, asm330lhh_sim_t val)
asm330lhh_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.sim= (uint8_t)val;
- ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.sim = (uint8_t)val;
+ ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -2062,24 +2336,29 @@ int32_t asm330lhh_spi_mode_set(stmdev_ctx_t *ctx, asm330lhh_sim_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t asm330lhh_spi_mode_get(stmdev_ctx_t *ctx, asm330lhh_sim_t *val)
+int32_t asm330lhh_spi_mode_get(stmdev_ctx_t *ctx,
+ asm330lhh_sim_t *val)
{
asm330lhh_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
- switch (ctrl3_c.sim){
+ switch (ctrl3_c.sim)
+ {
case ASM330LHH_SPI_4_WIRE:
*val = ASM330LHH_SPI_4_WIRE;
break;
+
case ASM330LHH_SPI_3_WIRE:
*val = ASM330LHH_SPI_3_WIRE;
break;
+
default:
*val = ASM330LHH_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -2097,11 +2376,14 @@ int32_t asm330lhh_i2c_interface_set(stmdev_ctx_t *ctx,
asm330lhh_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ctrl4_c.i2c_disable= (uint8_t)val;
- ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl4_c.i2c_disable = (uint8_t)val;
+ ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -2119,19 +2401,23 @@ int32_t asm330lhh_i2c_interface_get(stmdev_ctx_t *ctx,
asm330lhh_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
- switch (ctrl4_c.i2c_disable){
+ switch (ctrl4_c.i2c_disable)
+ {
case ASM330LHH_I2C_ENABLE:
*val = ASM330LHH_I2C_ENABLE;
break;
+
case ASM330LHH_I2C_DISABLE:
*val = ASM330LHH_I2C_DISABLE;
break;
+
default:
*val = ASM330LHH_I2C_ENABLE;
break;
}
+
return ret;
}
@@ -2143,7 +2429,7 @@ int32_t asm330lhh_i2c_interface_get(stmdev_ctx_t *ctx,
/**
* @defgroup ASM330LHH_interrupt_pins
* @brief This section groups all the functions that manage
- * interrup pins
+ * interrupt pins
* @{
*
*/
@@ -2164,14 +2450,19 @@ int32_t asm330lhh_pin_int1_route_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = asm330lhh_write_reg(ctx, ASM330LHH_INT1_CTRL,
- (uint8_t*)&val->int1_ctrl, 1);
+ (uint8_t *)&val->int1_ctrl, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = asm330lhh_write_reg(ctx, ASM330LHH_MD1_CFG,
- (uint8_t*)&val->md1_cfg, 1);
+ (uint8_t *)&val->md1_cfg, 1);
}
- if(ret == 0){
- ret = asm330lhh_read_reg(ctx, ASM330LHH_INT_CFG1, (uint8_t*)&tap_cfg2, 1);
+
+ if (ret == 0)
+ {
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_INT_CFG1,
+ (uint8_t *)&tap_cfg2, 1);
+
if ((val->int1_ctrl.den_drdy_flag |
val->int1_ctrl.int1_boot |
val->int1_ctrl.int1_cnt_bdr |
@@ -2183,17 +2474,23 @@ int32_t asm330lhh_pin_int1_route_set(stmdev_ctx_t *ctx,
val->md1_cfg.int1_6d |
val->md1_cfg.int1_ff |
val->md1_cfg.int1_wu |
- val->md1_cfg.int1_sleep_change)!= PROPERTY_DISABLE){
+ val->md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
+ {
tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
}
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = asm330lhh_write_reg(ctx, ASM330LHH_INT_CFG1,
- (uint8_t*)&tap_cfg2, 1);
+ (uint8_t *)&tap_cfg2, 1);
}
+
return ret;
}
@@ -2212,12 +2509,14 @@ int32_t asm330lhh_pin_int1_route_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_INT1_CTRL,
- (uint8_t*)&val->int1_ctrl, 1);
+ (uint8_t *)&val->int1_ctrl, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = asm330lhh_read_reg(ctx, ASM330LHH_MD1_CFG,
- (uint8_t*)&val->md1_cfg, 1);
+ (uint8_t *)&val->md1_cfg, 1);
}
+
return ret;
}
@@ -2236,19 +2535,23 @@ int32_t asm330lhh_pin_int2_route_set(stmdev_ctx_t *ctx,
asm330lhh_int_cfg1_t tap_cfg2;
int32_t ret;
-
ret = asm330lhh_write_reg(ctx, ASM330LHH_INT2_CTRL,
- (uint8_t*)&val->int2_ctrl, 1);
+ (uint8_t *)&val->int2_ctrl, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = asm330lhh_write_reg(ctx, ASM330LHH_MD2_CFG,
- (uint8_t*)&val->md2_cfg, 1);
+ (uint8_t *)&val->md2_cfg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = asm330lhh_read_reg(ctx, ASM330LHH_INT_CFG1,
- (uint8_t*)&tap_cfg2, 1);
+ (uint8_t *)&tap_cfg2, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
if ((val->int2_ctrl.int2_drdy_xl |
val->int2_ctrl.int2_drdy_g |
val->int2_ctrl.int2_drdy_temp |
@@ -2259,15 +2562,20 @@ int32_t asm330lhh_pin_int2_route_set(stmdev_ctx_t *ctx,
val->md2_cfg.int2_6d |
val->md2_cfg.int2_ff |
val->md2_cfg.int2_wu |
- val->md2_cfg.int2_sleep_change) != PROPERTY_DISABLE){
+ val->md2_cfg.int2_sleep_change) != PROPERTY_DISABLE)
+ {
tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
}
+
ret = asm330lhh_write_reg(ctx, ASM330LHH_INT_CFG1,
- (uint8_t*)&tap_cfg2, 1);
+ (uint8_t *)&tap_cfg2, 1);
}
+
return ret;
}
@@ -2285,12 +2593,15 @@ int32_t asm330lhh_pin_int2_route_get(stmdev_ctx_t *ctx,
{
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_INT2_CTRL,
- (uint8_t*)&val->int2_ctrl, 1);
- if(ret == 0){
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_INT2_CTRL,
+ (uint8_t *)&val->int2_ctrl, 1);
+
+ if (ret == 0)
+ {
ret = asm330lhh_read_reg(ctx, ASM330LHH_MD2_CFG,
- (uint8_t*)&val->md2_cfg, 1);
+ (uint8_t *)&val->md2_cfg, 1);
}
+
return ret;
}
@@ -2302,16 +2613,20 @@ int32_t asm330lhh_pin_int2_route_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t asm330lhh_pin_mode_set(stmdev_ctx_t *ctx, asm330lhh_pp_od_t val)
+int32_t asm330lhh_pin_mode_set(stmdev_ctx_t *ctx,
+ asm330lhh_pp_od_t val)
{
asm330lhh_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.pp_od= (uint8_t)val;
- ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.pp_od = (uint8_t)val;
+ ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -2323,24 +2638,29 @@ int32_t asm330lhh_pin_mode_set(stmdev_ctx_t *ctx, asm330lhh_pp_od_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t asm330lhh_pin_mode_get(stmdev_ctx_t *ctx, asm330lhh_pp_od_t *val)
+int32_t asm330lhh_pin_mode_get(stmdev_ctx_t *ctx,
+ asm330lhh_pp_od_t *val)
{
asm330lhh_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
- switch (ctrl3_c.pp_od){
+ switch (ctrl3_c.pp_od)
+ {
case ASM330LHH_PUSH_PULL:
*val = ASM330LHH_PUSH_PULL;
break;
+
case ASM330LHH_OPEN_DRAIN:
*val = ASM330LHH_OPEN_DRAIN;
break;
+
default:
*val = ASM330LHH_PUSH_PULL;
break;
}
+
return ret;
}
@@ -2358,11 +2678,14 @@ int32_t asm330lhh_pin_polarity_set(stmdev_ctx_t *ctx,
asm330lhh_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.h_lactive= (uint8_t)val;
- ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.h_lactive = (uint8_t)val;
+ ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -2380,19 +2703,23 @@ int32_t asm330lhh_pin_polarity_get(stmdev_ctx_t *ctx,
asm330lhh_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
- switch (ctrl3_c.h_lactive){
+ switch (ctrl3_c.h_lactive)
+ {
case ASM330LHH_ACTIVE_HIGH:
*val = ASM330LHH_ACTIVE_HIGH;
break;
+
case ASM330LHH_ACTIVE_LOW:
*val = ASM330LHH_ACTIVE_LOW;
break;
+
default:
*val = ASM330LHH_ACTIVE_HIGH;
break;
}
+
return ret;
}
@@ -2409,11 +2736,14 @@ int32_t asm330lhh_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
asm330lhh_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ctrl4_c.int2_on_int1= (uint8_t)val;
- ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl4_c.int2_on_int1 = (uint8_t)val;
+ ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -2430,7 +2760,7 @@ int32_t asm330lhh_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
asm330lhh_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.int2_on_int1;
return ret;
@@ -2450,13 +2780,17 @@ int32_t asm330lhh_int_notification_set(stmdev_ctx_t *ctx,
asm330lhh_int_cfg0_t int_cfg0;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_INT_CFG0, (uint8_t*)&int_cfg0, 1);
- if(ret == 0){
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_INT_CFG0,
+ (uint8_t *)&int_cfg0, 1);
+
+ if (ret == 0)
+ {
int_cfg0.lir = (uint8_t)val & 0x01U;
int_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
ret = asm330lhh_write_reg(ctx, ASM330LHH_INT_CFG0,
- (uint8_t*)&int_cfg0, 1);
+ (uint8_t *)&int_cfg0, 1);
}
+
return ret;
}
@@ -2475,19 +2809,24 @@ int32_t asm330lhh_int_notification_get(stmdev_ctx_t *ctx,
int32_t ret;
*val = ASM330LHH_ALL_INT_PULSED;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_INT_CFG0, (uint8_t*)&int_cfg0, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_INT_CFG0,
+ (uint8_t *)&int_cfg0, 1);
- switch ((int_cfg0.lir << 1) + int_cfg0.int_clr_on_read){
+ switch ((int_cfg0.lir << 1) + int_cfg0.int_clr_on_read)
+ {
case ASM330LHH_ALL_INT_PULSED:
*val = ASM330LHH_ALL_INT_PULSED;
break;
+
case ASM330LHH_ALL_INT_LATCHED:
*val = ASM330LHH_ALL_INT_LATCHED;
break;
+
default:
*val = ASM330LHH_ALL_INT_PULSED;
break;
}
+
return ret;
}
@@ -2521,12 +2860,15 @@ int32_t asm330lhh_wkup_ths_weight_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
- wake_up_dur.wake_ths_w= (uint8_t)val;
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ wake_up_dur.wake_ths_w = (uint8_t)val;
ret = asm330lhh_write_reg(ctx, ASM330LHH_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -2547,19 +2889,23 @@ int32_t asm330lhh_wkup_ths_weight_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
- switch (wake_up_dur.wake_ths_w){
+ switch (wake_up_dur.wake_ths_w)
+ {
case ASM330LHH_LSb_FS_DIV_64:
*val = ASM330LHH_LSb_FS_DIV_64;
break;
+
case ASM330LHH_LSb_FS_DIV_256:
*val = ASM330LHH_LSb_FS_DIV_256;
break;
+
default:
*val = ASM330LHH_LSb_FS_DIV_64;
break;
}
+
return ret;
}
@@ -2578,12 +2924,15 @@ int32_t asm330lhh_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
- if(ret == 0){
- wake_up_ths.wk_ths= (uint8_t)val;
+ (uint8_t *)&wake_up_ths, 1);
+
+ if (ret == 0)
+ {
+ wake_up_ths.wk_ths = (uint8_t)val;
ret = asm330lhh_write_reg(ctx, ASM330LHH_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
}
+
return ret;
}
@@ -2602,7 +2951,7 @@ int32_t asm330lhh_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
*val = wake_up_ths.wk_ths;
return ret;
@@ -2616,18 +2965,22 @@ int32_t asm330lhh_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t asm330lhh_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t asm330lhh_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
asm330lhh_wake_up_ths_t wake_up_ths;
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
- if(ret == 0){
- wake_up_ths.usr_off_on_wu= (uint8_t)val;
+ (uint8_t *)&wake_up_ths, 1);
+
+ if (ret == 0)
+ {
+ wake_up_ths.usr_off_on_wu = (uint8_t)val;
ret = asm330lhh_write_reg(ctx, ASM330LHH_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
}
+
return ret;
}
@@ -2646,7 +2999,7 @@ int32_t asm330lhh_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
*val = wake_up_ths.usr_off_on_wu;
return ret;
@@ -2666,12 +3019,15 @@ int32_t asm330lhh_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
- wake_up_dur.wake_dur= (uint8_t)val;
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ wake_up_dur.wake_dur = (uint8_t)val;
ret = asm330lhh_write_reg(ctx, ASM330LHH_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -2689,7 +3045,7 @@ int32_t asm330lhh_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
*val = wake_up_dur.wake_dur;
return ret;
@@ -2721,11 +3077,14 @@ int32_t asm330lhh_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
asm330lhh_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ctrl4_c.sleep_g= (uint8_t)val;
- ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl4_c.sleep_g = (uint8_t)val;
+ ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -2742,7 +3101,7 @@ int32_t asm330lhh_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
asm330lhh_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.sleep_g;
return ret;
@@ -2764,12 +3123,16 @@ int32_t asm330lhh_act_pin_notification_set(stmdev_ctx_t *ctx,
asm330lhh_int_cfg0_t int_cfg0;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_INT_CFG0, (uint8_t*)&int_cfg0, 1);
- if(ret == 0){
- int_cfg0. sleep_status_on_int= (uint8_t)val;
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_INT_CFG0,
+ (uint8_t *)&int_cfg0, 1);
+
+ if (ret == 0)
+ {
+ int_cfg0. sleep_status_on_int = (uint8_t)val;
ret = asm330lhh_write_reg(ctx, ASM330LHH_INT_CFG0,
- (uint8_t*)&int_cfg0, 1);
+ (uint8_t *)&int_cfg0, 1);
}
+
return ret;
}
@@ -2784,23 +3147,29 @@ int32_t asm330lhh_act_pin_notification_set(stmdev_ctx_t *ctx,
*
*/
int32_t asm330lhh_act_pin_notification_get(stmdev_ctx_t *ctx,
- asm330lhh_sleep_status_on_int_t *val)
+ asm330lhh_sleep_status_on_int_t *val)
{
asm330lhh_int_cfg0_t int_cfg0;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_INT_CFG0, (uint8_t*)&int_cfg0, 1);
- switch (int_cfg0. sleep_status_on_int){
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_INT_CFG0,
+ (uint8_t *)&int_cfg0, 1);
+
+ switch (int_cfg0. sleep_status_on_int)
+ {
case ASM330LHH_DRIVE_SLEEP_CHG_EVENT:
*val = ASM330LHH_DRIVE_SLEEP_CHG_EVENT;
break;
+
case ASM330LHH_DRIVE_SLEEP_STATUS:
*val = ASM330LHH_DRIVE_SLEEP_STATUS;
break;
+
default:
*val = ASM330LHH_DRIVE_SLEEP_CHG_EVENT;
break;
}
+
return ret;
}
@@ -2812,16 +3181,22 @@ int32_t asm330lhh_act_pin_notification_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t asm330lhh_act_mode_set(stmdev_ctx_t *ctx, asm330lhh_inact_en_t val)
+int32_t asm330lhh_act_mode_set(stmdev_ctx_t *ctx,
+ asm330lhh_inact_en_t val)
{
asm330lhh_int_cfg1_t int_cfg1;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_INT_CFG1, (uint8_t*)&int_cfg1, 1);
- if(ret == 0){
- int_cfg1.inact_en= (uint8_t)val;
- ret = asm330lhh_write_reg(ctx, ASM330LHH_INT_CFG1, (uint8_t*)&int_cfg1, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_INT_CFG1,
+ (uint8_t *)&int_cfg1, 1);
+
+ if (ret == 0)
+ {
+ int_cfg1.inact_en = (uint8_t)val;
+ ret = asm330lhh_write_reg(ctx, ASM330LHH_INT_CFG1,
+ (uint8_t *)&int_cfg1, 1);
}
+
return ret;
}
@@ -2839,25 +3214,32 @@ int32_t asm330lhh_act_mode_get(stmdev_ctx_t *ctx,
asm330lhh_int_cfg1_t int_cfg1;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_INT_CFG1, (uint8_t*)&int_cfg1, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_INT_CFG1,
+ (uint8_t *)&int_cfg1, 1);
- switch (int_cfg1.inact_en){
+ switch (int_cfg1.inact_en)
+ {
case ASM330LHH_XL_AND_GY_NOT_AFFECTED:
*val = ASM330LHH_XL_AND_GY_NOT_AFFECTED;
break;
+
case ASM330LHH_XL_12Hz5_GY_NOT_AFFECTED:
*val = ASM330LHH_XL_12Hz5_GY_NOT_AFFECTED;
break;
+
case ASM330LHH_XL_12Hz5_GY_SLEEP:
*val = ASM330LHH_XL_12Hz5_GY_SLEEP;
break;
+
case ASM330LHH_XL_12Hz5_GY_PD:
*val = ASM330LHH_XL_12Hz5_GY_PD;
break;
+
default:
*val = ASM330LHH_XL_AND_GY_NOT_AFFECTED;
break;
}
+
return ret;
}
@@ -2875,12 +3257,15 @@ int32_t asm330lhh_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
- wake_up_dur.sleep_dur= (uint8_t)val;
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ wake_up_dur.sleep_dur = (uint8_t)val;
ret = asm330lhh_write_reg(ctx, ASM330LHH_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -2898,7 +3283,7 @@ int32_t asm330lhh_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
*val = wake_up_dur.sleep_dur;
return ret;
@@ -2932,12 +3317,15 @@ int32_t asm330lhh_6d_threshold_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_THS_6D,
- (uint8_t*)&ths_6d, 1);
- if(ret == 0){
- ths_6d.sixd_ths= (uint8_t)val;
+ (uint8_t *)&ths_6d, 1);
+
+ if (ret == 0)
+ {
+ ths_6d.sixd_ths = (uint8_t)val;
ret = asm330lhh_write_reg(ctx, ASM330LHH_THS_6D,
- (uint8_t*)&ths_6d, 1);
+ (uint8_t *)&ths_6d, 1);
}
+
return ret;
}
@@ -2956,25 +3344,31 @@ int32_t asm330lhh_6d_threshold_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_THS_6D,
- (uint8_t*)&ths_6d, 1);
+ (uint8_t *)&ths_6d, 1);
- switch (ths_6d.sixd_ths){
+ switch (ths_6d.sixd_ths)
+ {
case ASM330LHH_DEG_80:
*val = ASM330LHH_DEG_80;
break;
+
case ASM330LHH_DEG_70:
*val = ASM330LHH_DEG_70;
break;
+
case ASM330LHH_DEG_60:
*val = ASM330LHH_DEG_60;
break;
+
case ASM330LHH_DEG_50:
*val = ASM330LHH_DEG_50;
break;
+
default:
*val = ASM330LHH_DEG_80;
break;
}
+
return ret;
}
@@ -2992,12 +3386,15 @@ int32_t asm330lhh_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_THS_6D,
- (uint8_t*)&ths_6d, 1);
- if(ret == 0){
- ths_6d.d4d_en= (uint8_t)val;
+ (uint8_t *)&ths_6d, 1);
+
+ if (ret == 0)
+ {
+ ths_6d.d4d_en = (uint8_t)val;
ret = asm330lhh_write_reg(ctx, ASM330LHH_THS_6D,
- (uint8_t*)&ths_6d, 1);
+ (uint8_t *)&ths_6d, 1);
}
+
return ret;
}
@@ -3015,7 +3412,7 @@ int32_t asm330lhh_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_THS_6D,
- (uint8_t*)&ths_6d, 1);
+ (uint8_t *)&ths_6d, 1);
*val = ths_6d.d4d_en;
return ret;
@@ -3048,12 +3445,16 @@ int32_t asm330lhh_ff_threshold_set(stmdev_ctx_t *ctx,
asm330lhh_free_fall_t free_fall;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_FREE_FALL, (uint8_t*)&free_fall, 1);
- if(ret == 0){
- free_fall.ff_ths= (uint8_t)val;
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_FREE_FALL,
+ (uint8_t *)&free_fall, 1);
+
+ if (ret == 0)
+ {
+ free_fall.ff_ths = (uint8_t)val;
ret = asm330lhh_write_reg(ctx, ASM330LHH_FREE_FALL,
- (uint8_t*)&free_fall, 1);
+ (uint8_t *)&free_fall, 1);
}
+
return ret;
}
@@ -3071,37 +3472,48 @@ int32_t asm330lhh_ff_threshold_get(stmdev_ctx_t *ctx,
asm330lhh_free_fall_t free_fall;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_FREE_FALL, (uint8_t*)&free_fall, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_FREE_FALL,
+ (uint8_t *)&free_fall, 1);
- switch (free_fall.ff_ths){
+ switch (free_fall.ff_ths)
+ {
case ASM330LHH_FF_TSH_156mg:
*val = ASM330LHH_FF_TSH_156mg;
break;
+
case ASM330LHH_FF_TSH_219mg:
*val = ASM330LHH_FF_TSH_219mg;
break;
+
case ASM330LHH_FF_TSH_250mg:
*val = ASM330LHH_FF_TSH_250mg;
break;
+
case ASM330LHH_FF_TSH_312mg:
*val = ASM330LHH_FF_TSH_312mg;
break;
+
case ASM330LHH_FF_TSH_344mg:
*val = ASM330LHH_FF_TSH_344mg;
break;
+
case ASM330LHH_FF_TSH_406mg:
*val = ASM330LHH_FF_TSH_406mg;
break;
+
case ASM330LHH_FF_TSH_469mg:
*val = ASM330LHH_FF_TSH_469mg;
break;
+
case ASM330LHH_FF_TSH_500mg:
*val = ASM330LHH_FF_TSH_500mg;
break;
+
default:
*val = ASM330LHH_FF_TSH_156mg;
break;
}
+
return ret;
}
@@ -3120,21 +3532,28 @@ int32_t asm330lhh_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
wake_up_dur.ff_dur = (val & 0x20U) >> 5;
ret = asm330lhh_write_reg(ctx, ASM330LHH_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = asm330lhh_read_reg(ctx, ASM330LHH_FREE_FALL,
- (uint8_t*)&free_fall, 1);
+ (uint8_t *)&free_fall, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
free_fall.ff_dur = val & 0x1FU;
ret = asm330lhh_write_reg(ctx, ASM330LHH_FREE_FALL,
- (uint8_t*)&free_fall, 1);
+ (uint8_t *)&free_fall, 1);
}
+
return ret;
}
@@ -3153,12 +3572,14 @@ int32_t asm330lhh_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = asm330lhh_read_reg(ctx, ASM330LHH_FREE_FALL,
- (uint8_t*)&free_fall, 1);
+ (uint8_t *)&free_fall, 1);
}
+
*val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
return ret;
@@ -3192,16 +3613,20 @@ int32_t asm330lhh_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl2.wtm = (uint8_t)((val / 256U) & 0x01U);
ret = asm330lhh_write_reg(ctx, ASM330LHH_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
fifo_ctrl1.wtm = (uint8_t)(val - (fifo_ctrl2.wtm * 256U));
ret = asm330lhh_write_reg(ctx, ASM330LHH_FIFO_CTRL1,
- (uint8_t*)&fifo_ctrl1, 1);
+ (uint8_t *)&fifo_ctrl1, 1);
}
return ret;
@@ -3222,13 +3647,17 @@ int32_t asm330lhh_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_CTRL1,
- (uint8_t*)&fifo_ctrl1, 1);
+ (uint8_t *)&fifo_ctrl1, 1);
}
+
*val = fifo_ctrl2.wtm;
*val = (*val * 256U) + fifo_ctrl1.wtm;
+
return ret;
}
/**
@@ -3246,11 +3675,13 @@ int32_t asm330lhh_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
- fifo_ctrl2.odrchg_en= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl2.odrchg_en = (uint8_t)val;
ret = asm330lhh_write_reg(ctx, ASM330LHH_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
return ret;
@@ -3271,7 +3702,7 @@ int32_t asm330lhh_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
*val = fifo_ctrl2.odrchg_en;
return ret;
@@ -3292,12 +3723,15 @@ int32_t asm330lhh_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
- fifo_ctrl2.stop_on_wtm= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl2.stop_on_wtm = (uint8_t)val;
ret = asm330lhh_write_reg(ctx, ASM330LHH_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
+
return ret;
}
@@ -3310,13 +3744,14 @@ int32_t asm330lhh_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t asm330lhh_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t asm330lhh_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
asm330lhh_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
*val = fifo_ctrl2.stop_on_wtm;
return ret;
@@ -3338,12 +3773,15 @@ int32_t asm330lhh_fifo_xl_batch_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
- if(ret == 0){
- fifo_ctrl3.bdr_xl= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl3, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl3.bdr_xl = (uint8_t)val;
ret = asm330lhh_write_reg(ctx, ASM330LHH_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
+ (uint8_t *)&fifo_ctrl3, 1);
}
+
return ret;
}
@@ -3363,49 +3801,63 @@ int32_t asm330lhh_fifo_xl_batch_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
+ (uint8_t *)&fifo_ctrl3, 1);
- switch (fifo_ctrl3.bdr_xl){
+ switch (fifo_ctrl3.bdr_xl)
+ {
case ASM330LHH_XL_NOT_BATCHED:
*val = ASM330LHH_XL_NOT_BATCHED;
break;
+
case ASM330LHH_XL_BATCHED_AT_12Hz5:
*val = ASM330LHH_XL_BATCHED_AT_12Hz5;
break;
+
case ASM330LHH_XL_BATCHED_AT_26Hz:
*val = ASM330LHH_XL_BATCHED_AT_26Hz;
break;
+
case ASM330LHH_XL_BATCHED_AT_52Hz:
*val = ASM330LHH_XL_BATCHED_AT_52Hz;
break;
+
case ASM330LHH_XL_BATCHED_AT_104Hz:
*val = ASM330LHH_XL_BATCHED_AT_104Hz;
break;
+
case ASM330LHH_XL_BATCHED_AT_208Hz:
*val = ASM330LHH_XL_BATCHED_AT_208Hz;
break;
+
case ASM330LHH_XL_BATCHED_AT_417Hz:
*val = ASM330LHH_XL_BATCHED_AT_417Hz;
break;
+
case ASM330LHH_XL_BATCHED_AT_833Hz:
*val = ASM330LHH_XL_BATCHED_AT_833Hz;
break;
+
case ASM330LHH_XL_BATCHED_AT_1667Hz:
*val = ASM330LHH_XL_BATCHED_AT_1667Hz;
break;
+
case ASM330LHH_XL_BATCHED_AT_3333Hz:
*val = ASM330LHH_XL_BATCHED_AT_3333Hz;
break;
+
case ASM330LHH_XL_BATCHED_AT_6667Hz:
*val = ASM330LHH_XL_BATCHED_AT_6667Hz;
break;
+
case ASM330LHH_XL_BATCHED_AT_6Hz5:
*val = ASM330LHH_XL_BATCHED_AT_6Hz5;
break;
+
default:
*val = ASM330LHH_XL_NOT_BATCHED;
break;
}
+
return ret;
}
@@ -3425,12 +3877,15 @@ int32_t asm330lhh_fifo_gy_batch_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
- if(ret == 0){
- fifo_ctrl3.bdr_gy= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl3, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl3.bdr_gy = (uint8_t)val;
ret = asm330lhh_write_reg(ctx, ASM330LHH_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
+ (uint8_t *)&fifo_ctrl3, 1);
}
+
return ret;
}
@@ -3450,49 +3905,63 @@ int32_t asm330lhh_fifo_gy_batch_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
+ (uint8_t *)&fifo_ctrl3, 1);
- switch (fifo_ctrl3.bdr_gy){
+ switch (fifo_ctrl3.bdr_gy)
+ {
case ASM330LHH_GY_NOT_BATCHED:
*val = ASM330LHH_GY_NOT_BATCHED;
break;
+
case ASM330LHH_GY_BATCHED_AT_12Hz5:
*val = ASM330LHH_GY_BATCHED_AT_12Hz5;
break;
+
case ASM330LHH_GY_BATCHED_AT_26Hz:
*val = ASM330LHH_GY_BATCHED_AT_26Hz;
break;
+
case ASM330LHH_GY_BATCHED_AT_52Hz:
*val = ASM330LHH_GY_BATCHED_AT_52Hz;
break;
+
case ASM330LHH_GY_BATCHED_AT_104Hz:
*val = ASM330LHH_GY_BATCHED_AT_104Hz;
break;
+
case ASM330LHH_GY_BATCHED_AT_208Hz:
*val = ASM330LHH_GY_BATCHED_AT_208Hz;
break;
+
case ASM330LHH_GY_BATCHED_AT_417Hz:
*val = ASM330LHH_GY_BATCHED_AT_417Hz;
break;
+
case ASM330LHH_GY_BATCHED_AT_833Hz:
*val = ASM330LHH_GY_BATCHED_AT_833Hz;
break;
+
case ASM330LHH_GY_BATCHED_AT_1667Hz:
*val = ASM330LHH_GY_BATCHED_AT_1667Hz;
break;
+
case ASM330LHH_GY_BATCHED_AT_3333Hz:
*val = ASM330LHH_GY_BATCHED_AT_3333Hz;
break;
+
case ASM330LHH_GY_BATCHED_AT_6667Hz:
*val = ASM330LHH_GY_BATCHED_AT_6667Hz;
break;
+
case ASM330LHH_GY_BATCHED_6Hz5:
*val = ASM330LHH_GY_BATCHED_6Hz5;
break;
+
default:
*val = ASM330LHH_GY_NOT_BATCHED;
break;
}
+
return ret;
}
@@ -3511,12 +3980,15 @@ int32_t asm330lhh_fifo_mode_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
- fifo_ctrl4.fifo_mode= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl4.fifo_mode = (uint8_t)val;
ret = asm330lhh_write_reg(ctx, ASM330LHH_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -3535,31 +4007,39 @@ int32_t asm330lhh_fifo_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
- switch (fifo_ctrl4.fifo_mode){
+ switch (fifo_ctrl4.fifo_mode)
+ {
case ASM330LHH_BYPASS_MODE:
*val = ASM330LHH_BYPASS_MODE;
break;
+
case ASM330LHH_FIFO_MODE:
*val = ASM330LHH_FIFO_MODE;
break;
+
case ASM330LHH_STREAM_TO_FIFO_MODE:
*val = ASM330LHH_STREAM_TO_FIFO_MODE;
break;
+
case ASM330LHH_BYPASS_TO_STREAM_MODE:
*val = ASM330LHH_BYPASS_TO_STREAM_MODE;
break;
+
case ASM330LHH_STREAM_MODE:
*val = ASM330LHH_STREAM_MODE;
break;
+
case ASM330LHH_BYPASS_TO_FIFO_MODE:
*val = ASM330LHH_BYPASS_TO_FIFO_MODE;
break;
+
default:
*val = ASM330LHH_BYPASS_MODE;
break;
}
+
return ret;
}
@@ -3579,12 +4059,15 @@ int32_t asm330lhh_fifo_temp_batch_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
- fifo_ctrl4.odr_t_batch= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl4.odr_t_batch = (uint8_t)val;
ret = asm330lhh_write_reg(ctx, ASM330LHH_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -3604,25 +4087,31 @@ int32_t asm330lhh_fifo_temp_batch_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
- switch (fifo_ctrl4.odr_t_batch){
+ switch (fifo_ctrl4.odr_t_batch)
+ {
case ASM330LHH_TEMP_NOT_BATCHED:
*val = ASM330LHH_TEMP_NOT_BATCHED;
break;
+
case ASM330LHH_TEMP_BATCHED_AT_52Hz:
*val = ASM330LHH_TEMP_BATCHED_AT_52Hz;
break;
+
case ASM330LHH_TEMP_BATCHED_AT_12Hz5:
*val = ASM330LHH_TEMP_BATCHED_AT_12Hz5;
break;
+
case ASM330LHH_TEMP_BATCHED_AT_1Hz6:
*val = ASM330LHH_TEMP_BATCHED_AT_1Hz6;
break;
+
default:
*val = ASM330LHH_TEMP_NOT_BATCHED;
break;
}
+
return ret;
}
@@ -3643,12 +4132,15 @@ int32_t asm330lhh_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
- fifo_ctrl4.odr_ts_batch= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl4.odr_ts_batch = (uint8_t)val;
ret = asm330lhh_write_reg(ctx, ASM330LHH_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -3670,25 +4162,31 @@ int32_t asm330lhh_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
- switch (fifo_ctrl4.odr_ts_batch){
+ switch (fifo_ctrl4.odr_ts_batch)
+ {
case ASM330LHH_NO_DECIMATION:
*val = ASM330LHH_NO_DECIMATION;
break;
+
case ASM330LHH_DEC_1:
*val = ASM330LHH_DEC_1;
break;
+
case ASM330LHH_DEC_8:
*val = ASM330LHH_DEC_8;
break;
+
case ASM330LHH_DEC_32:
*val = ASM330LHH_DEC_32;
break;
+
default:
*val = ASM330LHH_NO_DECIMATION;
break;
}
+
return ret;
}
@@ -3709,12 +4207,15 @@ int32_t asm330lhh_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if(ret == 0){
- counter_bdr_reg1.trig_counter_bdr= (uint8_t)val;
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
+ counter_bdr_reg1.trig_counter_bdr = (uint8_t)val;
ret = asm330lhh_write_reg(ctx, ASM330LHH_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
}
+
return ret;
}
@@ -3735,19 +4236,23 @@ int32_t asm330lhh_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
- switch (counter_bdr_reg1.trig_counter_bdr){
+ switch (counter_bdr_reg1.trig_counter_bdr)
+ {
case ASM330LHH_XL_BATCH_EVENT:
*val = ASM330LHH_XL_BATCH_EVENT;
break;
+
case ASM330LHH_GYRO_BATCH_EVENT:
*val = ASM330LHH_GYRO_BATCH_EVENT;
break;
+
default:
*val = ASM330LHH_XL_BATCH_EVENT;
break;
}
+
return ret;
}
@@ -3760,18 +4265,22 @@ int32_t asm330lhh_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t asm330lhh_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t asm330lhh_rst_batch_counter_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
asm330lhh_counter_bdr_reg1_t counter_bdr_reg1;
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if(ret == 0){
- counter_bdr_reg1.rst_counter_bdr= (uint8_t)val;
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
+ counter_bdr_reg1.rst_counter_bdr = (uint8_t)val;
ret = asm330lhh_write_reg(ctx, ASM330LHH_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
}
+
return ret;
}
@@ -3784,13 +4293,14 @@ int32_t asm330lhh_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t asm330lhh_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t asm330lhh_rst_batch_counter_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
asm330lhh_counter_bdr_reg1_t counter_bdr_reg1;
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
*val = counter_bdr_reg1.rst_counter_bdr;
return ret;
@@ -3813,17 +4323,23 @@ int32_t asm330lhh_batch_counter_threshold_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if (ret == 0){
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
counter_bdr_reg1.cnt_bdr_th = (uint8_t)((val / 256U) & 0x07U);
ret = asm330lhh_write_reg(ctx, ASM330LHH_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
}
- if (ret == 0){
- counter_bdr_reg2.cnt_bdr_th = (uint8_t)(val - (counter_bdr_reg1.cnt_bdr_th * 256U));
+
+ if (ret == 0)
+ {
+ counter_bdr_reg2.cnt_bdr_th = (uint8_t)(val -
+ (counter_bdr_reg1.cnt_bdr_th * 256U));
ret = asm330lhh_write_reg(ctx, ASM330LHH_COUNTER_BDR_REG2,
- (uint8_t*)&counter_bdr_reg2, 1);
+ (uint8_t *)&counter_bdr_reg2, 1);
}
+
return ret;
}
@@ -3844,14 +4360,17 @@ int32_t asm330lhh_batch_counter_threshold_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if (ret == 0){
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
ret = asm330lhh_read_reg(ctx, ASM330LHH_COUNTER_BDR_REG2,
- (uint8_t*)&counter_bdr_reg2, 1);
+ (uint8_t *)&counter_bdr_reg2, 1);
}
*val = counter_bdr_reg1.cnt_bdr_th;
*val = (*val * 256U) + counter_bdr_reg2.cnt_bdr_th;
+
return ret;
}
@@ -3863,21 +4382,24 @@ int32_t asm330lhh_batch_counter_threshold_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t asm330lhh_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
+int32_t asm330lhh_fifo_data_level_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
asm330lhh_fifo_status1_t fifo_status1;
asm330lhh_fifo_status2_t fifo_status2;
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_STATUS1,
- (uint8_t*)&fifo_status1, 1);
- if (ret == 0){
- ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
+ (uint8_t *)&fifo_status1, 1);
+ if (ret == 0)
+ {
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_STATUS2,
+ (uint8_t *)&fifo_status2, 1);
*val = fifo_status2.diff_fifo;
*val = (*val * 256U) + fifo_status1.diff_fifo;
}
+
return ret;
}
@@ -3893,7 +4415,9 @@ int32_t asm330lhh_fifo_status_get(stmdev_ctx_t *ctx,
asm330lhh_fifo_status2_t *val)
{
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_STATUS2, (uint8_t*)val, 1);
+
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_STATUS2, (uint8_t *)val, 1);
+
return ret;
}
@@ -3911,7 +4435,7 @@ int32_t asm330lhh_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
+ (uint8_t *)&fifo_status2, 1);
*val = fifo_status2.fifo_full_ia;
return ret;
@@ -3932,7 +4456,7 @@ int32_t asm330lhh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
+ (uint8_t *)&fifo_status2, 1);
*val = fifo_status2. fifo_ovr_ia;
return ret;
@@ -3952,7 +4476,7 @@ int32_t asm330lhh_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
+ (uint8_t *)&fifo_status2, 1);
*val = fifo_status2.fifo_wtm_ia;
return ret;
@@ -3973,28 +4497,35 @@ int32_t asm330lhh_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_DATA_OUT_TAG,
- (uint8_t*)&fifo_data_out_tag, 1);
+ (uint8_t *)&fifo_data_out_tag, 1);
- switch (fifo_data_out_tag.tag_sensor){
+ switch (fifo_data_out_tag.tag_sensor)
+ {
case ASM330LHH_GYRO_NC_TAG:
*val = ASM330LHH_GYRO_NC_TAG;
break;
+
case ASM330LHH_XL_NC_TAG:
*val = ASM330LHH_XL_NC_TAG;
break;
+
case ASM330LHH_TEMPERATURE_TAG:
*val = ASM330LHH_TEMPERATURE_TAG;
break;
+
case ASM330LHH_TIMESTAMP_TAG:
*val = ASM330LHH_TIMESTAMP_TAG;
break;
+
case ASM330LHH_CFG_CHANGE_TAG:
*val = ASM330LHH_CFG_CHANGE_TAG;
break;
+
default:
*val = ASM330LHH_CFG_CHANGE_TAG;
break;
}
+
return ret;
}
@@ -4019,16 +4550,20 @@ int32_t asm330lhh_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t asm330lhh_den_mode_set(stmdev_ctx_t *ctx, asm330lhh_den_mode_t val)
+int32_t asm330lhh_den_mode_set(stmdev_ctx_t *ctx,
+ asm330lhh_den_mode_t val)
{
asm330lhh_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
- ctrl6_c.den_mode= (uint8_t)val;
- ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl6_c.den_mode = (uint8_t)val;
+ ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -4046,28 +4581,35 @@ int32_t asm330lhh_den_mode_get(stmdev_ctx_t *ctx,
asm330lhh_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
- switch (ctrl6_c.den_mode){
+ switch (ctrl6_c.den_mode)
+ {
case ASM330LHH_DEN_DISABLE:
*val = ASM330LHH_DEN_DISABLE;
break;
+
case ASM330LHH_LEVEL_FIFO:
*val = ASM330LHH_LEVEL_FIFO;
break;
+
case ASM330LHH_LEVEL_LETCHED:
*val = ASM330LHH_LEVEL_LETCHED;
break;
+
case ASM330LHH_LEVEL_TRIGGER:
*val = ASM330LHH_LEVEL_TRIGGER;
break;
+
case ASM330LHH_EDGE_TRIGGER:
*val = ASM330LHH_EDGE_TRIGGER;
break;
+
default:
*val = ASM330LHH_DEN_DISABLE;
break;
}
+
return ret;
}
@@ -4085,12 +4627,16 @@ int32_t asm330lhh_den_polarity_set(stmdev_ctx_t *ctx,
asm330lhh_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
- ctrl9_xl.den_lh= (uint8_t)val;
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl9_xl.den_lh = (uint8_t)val;
ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
+ (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -4108,19 +4654,24 @@ int32_t asm330lhh_den_polarity_get(stmdev_ctx_t *ctx,
asm330lhh_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
- switch (ctrl9_xl.den_lh){
+ switch (ctrl9_xl.den_lh)
+ {
case ASM330LHH_DEN_ACT_LOW:
*val = ASM330LHH_DEN_ACT_LOW;
break;
+
case ASM330LHH_DEN_ACT_HIGH:
*val = ASM330LHH_DEN_ACT_HIGH;
break;
+
default:
*val = ASM330LHH_DEN_ACT_LOW;
break;
}
+
return ret;
}
@@ -4138,12 +4689,16 @@ int32_t asm330lhh_den_enable_set(stmdev_ctx_t *ctx,
asm330lhh_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
- ctrl9_xl.den_xl_g= (uint8_t)val;
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl9_xl.den_xl_g = (uint8_t)val;
ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
+ (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -4161,22 +4716,28 @@ int32_t asm330lhh_den_enable_get(stmdev_ctx_t *ctx,
asm330lhh_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
- switch (ctrl9_xl.den_xl_g){
+ switch (ctrl9_xl.den_xl_g)
+ {
case ASM330LHH_STAMP_IN_GY_DATA:
*val = ASM330LHH_STAMP_IN_GY_DATA;
break;
+
case ASM330LHH_STAMP_IN_XL_DATA:
*val = ASM330LHH_STAMP_IN_XL_DATA;
break;
+
case ASM330LHH_STAMP_IN_GY_XL_DATA:
*val = ASM330LHH_STAMP_IN_GY_XL_DATA;
break;
+
default:
*val = ASM330LHH_STAMP_IN_GY_DATA;
break;
}
+
return ret;
}
@@ -4193,12 +4754,16 @@ int32_t asm330lhh_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
asm330lhh_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
- ctrl9_xl.den_z= (uint8_t)val;
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl9_xl.den_z = (uint8_t)val;
ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
+ (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -4215,7 +4780,8 @@ int32_t asm330lhh_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val)
asm330lhh_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
*val = ctrl9_xl.den_z;
return ret;
@@ -4234,12 +4800,16 @@ int32_t asm330lhh_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
asm330lhh_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
- ctrl9_xl.den_y= (uint8_t)val;
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl9_xl.den_y = (uint8_t)val;
ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
+ (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -4256,7 +4826,8 @@ int32_t asm330lhh_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val)
asm330lhh_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
*val = ctrl9_xl.den_y;
return ret;
@@ -4275,11 +4846,16 @@ int32_t asm330lhh_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val)
asm330lhh_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
- ctrl9_xl.den_x= (uint8_t)val;
- ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl9_xl.den_x = (uint8_t)val;
+ ret = asm330lhh_write_reg(ctx, ASM330LHH_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -4296,7 +4872,8 @@ int32_t asm330lhh_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val)
asm330lhh_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
*val = ctrl9_xl.den_x;
return ret;
diff --git a/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.h b/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.h
index 176895cd46ee616b51387a60eccd74c8b8096eca..69ee6baf0aec93b3185dab22dd309c92c9547d35 100644
--- a/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.h
+++ b/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file asm330lhh_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * asm330lhh_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file asm330lhh_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * asm330lhh_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef ASM330LHH_REGS_H
#define ASM330LHH_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup ASM330LHH
@@ -74,7 +75,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -107,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -139,7 +142,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -174,7 +178,8 @@ typedef struct {
*/
#define ASM330LHH_PIN_CTRL 0x02U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 6;
uint8_t sdo_pu_en : 1;
@@ -187,12 +192,14 @@ typedef struct {
} asm330lhh_pin_ctrl_t;
#define ASM330LHH_FIFO_CTRL1 0x07U
-typedef struct {
+typedef struct
+{
uint8_t wtm : 8;
} asm330lhh_fifo_ctrl1_t;
#define ASM330LHH_FIFO_CTRL2 0x08U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wtm : 1;
uint8_t not_used_01 : 3;
@@ -209,7 +216,8 @@ typedef struct {
} asm330lhh_fifo_ctrl2_t;
#define ASM330LHH_FIFO_CTRL3 0x09U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bdr_xl : 4;
uint8_t bdr_gy : 4;
@@ -220,7 +228,8 @@ typedef struct {
} asm330lhh_fifo_ctrl3_t;
#define ASM330LHH_FIFO_CTRL4 0x0AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fifo_mode : 3;
uint8_t not_used_01 : 1;
@@ -235,7 +244,8 @@ typedef struct {
} asm330lhh_fifo_ctrl4_t;
#define ASM330LHH_COUNTER_BDR_REG1 0x0BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t cnt_bdr_th : 3;
uint8_t not_used_01 : 2;
@@ -252,12 +262,14 @@ typedef struct {
} asm330lhh_counter_bdr_reg1_t;
#define ASM330LHH_COUNTER_BDR_REG2 0x0CU
-typedef struct {
+typedef struct
+{
uint8_t cnt_bdr_th : 8;
} asm330lhh_counter_bdr_reg2_t;
#define ASM330LHH_INT1_CTRL 0x0DU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_drdy_xl : 1;
uint8_t int1_drdy_g : 1;
@@ -280,7 +292,8 @@ typedef struct {
} asm330lhh_int1_ctrl_t;
#define ASM330LHH_INT2_CTRL 0x0EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_drdy_xl : 1;
uint8_t int2_drdy_g : 1;
@@ -304,7 +317,8 @@ typedef struct {
#define ASM330LHH_WHO_AM_I 0x0FU
#define ASM330LHH_CTRL1_XL 0x10U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t lpf2_xl_en : 1;
@@ -319,7 +333,8 @@ typedef struct {
} asm330lhh_ctrl1_xl_t;
#define ASM330LHH_CTRL2_G 0x11U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fs_g : 4; /* fs_4000 + fs_125 + fs_g */
uint8_t odr_g : 4;
@@ -330,7 +345,8 @@ typedef struct {
} asm330lhh_ctrl2_g_t;
#define ASM330LHH_CTRL3_C 0x12U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sw_reset : 1;
uint8_t not_used_01 : 1;
@@ -353,7 +369,8 @@ typedef struct {
} asm330lhh_ctrl3_c_t;
#define ASM330LHH_CTRL4_C 0x13U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t lpf1_sel_g : 1;
@@ -376,7 +393,8 @@ typedef struct {
} asm330lhh_ctrl4_c_t;
#define ASM330LHH_CTRL5_C 0x14U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_xl : 2;
uint8_t st_g : 2;
@@ -393,14 +411,17 @@ typedef struct {
} asm330lhh_ctrl5_c_t;
#define ASM330LHH_CTRL6_C 0x15U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ftype : 3;
uint8_t usr_off_w : 1;
uint8_t not_used_01 : 1;
- uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */
+uint8_t den_mode :
+ 3; /* trig_en + lvl1_en + lvl2_en */
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */
+uint8_t den_mode :
+ 3; /* trig_en + lvl1_en + lvl2_en */
uint8_t not_used_01 : 1;
uint8_t usr_off_w : 1;
uint8_t ftype : 3;
@@ -408,7 +429,8 @@ typedef struct {
} asm330lhh_ctrl6_c_t;
#define ASM330LHH_CTRL7_G 0x16U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t usr_off_on_out : 1;
@@ -427,7 +449,8 @@ typedef struct {
} asm330lhh_ctrl7_g_t;
#define ASM330LHH_CTRL8_XL 0x17U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t low_pass_on_6d : 1;
uint8_t not_used_01 : 1;
@@ -446,7 +469,8 @@ typedef struct {
} asm330lhh_ctrl8_xl_t;
#define ASM330LHH_CTRL9_XL 0x18U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t device_conf : 1;
@@ -467,7 +491,8 @@ typedef struct {
} asm330lhh_ctrl9_xl_t;
#define ASM330LHH_CTRL10_C 0x19U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 5;
uint8_t timestamp_en : 1;
@@ -480,7 +505,8 @@ typedef struct {
} asm330lhh_ctrl10_c_t;
#define ASM330LHH_ALL_INT_SRC 0x1AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ia : 1;
uint8_t wu_ia : 1;
@@ -501,7 +527,8 @@ typedef struct {
} asm330lhh_all_int_src_t;
#define ASM330LHH_WAKE_UP_SRC 0x1BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_wu : 1;
uint8_t y_wu : 1;
@@ -522,7 +549,8 @@ typedef struct {
} asm330lhh_wake_up_src_t;
#define ASM330LHH_TAP_SRC 0x1CU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_tap : 1;
uint8_t y_tap : 1;
@@ -545,7 +573,8 @@ typedef struct {
} asm330lhh_tap_src_t;
#define ASM330LHH_D6D_SRC 0x1DU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
@@ -568,7 +597,8 @@ typedef struct {
} asm330lhh_d6d_src_t;
#define ASM330LHH_STATUS_REG 0x1EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlda : 1;
uint8_t gda : 1;
@@ -597,12 +627,14 @@ typedef struct {
#define ASM330LHH_OUTZ_L_A 0x2CU
#define ASM330LHH_OUTZ_H_A 0x2DU
#define ASM330LHH_FIFO_STATUS1 0x3AU
-typedef struct {
+typedef struct
+{
uint8_t diff_fifo : 8;
} asm330lhh_fifo_status1_t;
#define ASM330LHH_FIFO_STATUS2 0x3BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t diff_fifo : 2;
uint8_t not_used_01 : 1;
@@ -627,7 +659,8 @@ typedef struct {
#define ASM330LHH_TIMESTAMP2 0x42U
#define ASM330LHH_TIMESTAMP3 0x43U
#define ASM330LHH_INT_CFG0 0x56U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lir : 1;
uint8_t not_used_01 : 3;
@@ -646,7 +679,8 @@ typedef struct {
} asm330lhh_int_cfg0_t;
#define ASM330LHH_INT_CFG1 0x58U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 5;
uint8_t inact_en : 2;
@@ -659,7 +693,8 @@ typedef struct {
} asm330lhh_int_cfg1_t;
#define ASM330LHH_THS_6D 0x59U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 5;
uint8_t sixd_ths : 2;
@@ -672,7 +707,8 @@ typedef struct {
} asm330lhh_ths_6d_t;
#define ASM330LHH_INT_DUR2 0x5AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shock : 2;
uint8_t quiet : 2;
@@ -685,7 +721,8 @@ typedef struct {
} asm330lhh_int_dur2_t;
#define ASM330LHH_WAKE_UP_THS 0x5BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wk_ths : 6;
uint8_t usr_off_on_wu : 1;
@@ -698,7 +735,8 @@ typedef struct {
} asm330lhh_wake_up_ths_t;
#define ASM330LHH_WAKE_UP_DUR 0x5CU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sleep_dur : 4;
uint8_t wake_ths_w : 1;
@@ -713,7 +751,8 @@ typedef struct {
} asm330lhh_wake_up_dur_t;
#define ASM330LHH_FREE_FALL 0x5DU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ths : 3;
uint8_t ff_dur : 5;
@@ -724,7 +763,8 @@ typedef struct {
} asm330lhh_free_fall_t;
#define ASM330LHH_MD1_CFG 0x5EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t int1_6d : 1;
@@ -745,7 +785,8 @@ typedef struct {
} asm330lhh_md1_cfg_t;
#define ASM330LHH_MD2_CFG 0x5FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_timestamp : 1;
uint8_t not_used_01 : 1;
@@ -768,7 +809,8 @@ typedef struct {
} asm330lhh_md2_cfg_t;
#define ASM330LHH_INTERNAL_FREQ_FINE 0x63U
-typedef struct {
+typedef struct
+{
uint8_t freq_fine : 8;
} asm330lhh_internal_freq_fine_t;
@@ -776,7 +818,8 @@ typedef struct {
#define ASM330LHH_Y_OFS_USR 0x74U
#define ASM330LHH_Z_OFS_USR 0x75U
#define ASM330LHH_FIFO_DATA_OUT_TAG 0x78U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tag_parity : 1;
uint8_t tag_cnt : 2;
@@ -797,9 +840,9 @@ typedef struct {
/**
* @defgroup ASM330LHH_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -807,7 +850,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
asm330lhh_pin_ctrl_t pin_ctrl;
asm330lhh_fifo_ctrl1_t fifo_ctrl1;
asm330lhh_fifo_ctrl2_t fifo_ctrl2;
@@ -853,34 +897,43 @@ typedef union{
*
*/
-int32_t asm330lhh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
- uint16_t len);
-int32_t asm330lhh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
- uint16_t len);
+int32_t asm330lhh_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len);
+int32_t asm330lhh_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len);
float_t asm330lhh_from_fs2g_to_mg(int16_t lsb);
float_t asm330lhh_from_fs4g_to_mg(int16_t lsb);
float_t asm330lhh_from_fs8g_to_mg(int16_t lsb);
float_t asm330lhh_from_fs16g_to_mg(int16_t lsb);
+
float_t asm330lhh_from_fs125dps_to_mdps(int16_t lsb);
float_t asm330lhh_from_fs250dps_to_mdps(int16_t lsb);
float_t asm330lhh_from_fs500dps_to_mdps(int16_t lsb);
float_t asm330lhh_from_fs1000dps_to_mdps(int16_t lsb);
float_t asm330lhh_from_fs2000dps_to_mdps(int16_t lsb);
float_t asm330lhh_from_fs4000dps_to_mdps(int16_t lsb);
+
float_t asm330lhh_from_lsb_to_celsius(int16_t lsb);
+
float_t asm330lhh_from_lsb_to_nsec(int32_t lsb);
-typedef enum {
+typedef enum
+{
ASM330LHH_2g = 0,
ASM330LHH_16g = 1, /* if XL_FS_MODE = '1' -> ASM330LHH_2g */
ASM330LHH_4g = 2,
ASM330LHH_8g = 3,
} asm330lhh_fs_xl_t;
-int32_t asm330lhh_xl_full_scale_set(stmdev_ctx_t *ctx, asm330lhh_fs_xl_t val);
-int32_t asm330lhh_xl_full_scale_get(stmdev_ctx_t *ctx, asm330lhh_fs_xl_t *val);
+int32_t asm330lhh_xl_full_scale_set(stmdev_ctx_t *ctx,
+ asm330lhh_fs_xl_t val);
+int32_t asm330lhh_xl_full_scale_get(stmdev_ctx_t *ctx,
+ asm330lhh_fs_xl_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_XL_ODR_OFF = 0,
ASM330LHH_XL_ODR_12Hz5 = 1,
ASM330LHH_XL_ODR_26Hz = 2,
@@ -894,10 +947,13 @@ typedef enum {
ASM330LHH_XL_ODR_6667Hz = 10,
ASM330LHH_XL_ODR_6Hz5 = 11, /* (low power only) */
} asm330lhh_odr_xl_t;
-int32_t asm330lhh_xl_data_rate_set(stmdev_ctx_t *ctx, asm330lhh_odr_xl_t val);
-int32_t asm330lhh_xl_data_rate_get(stmdev_ctx_t *ctx, asm330lhh_odr_xl_t *val);
+int32_t asm330lhh_xl_data_rate_set(stmdev_ctx_t *ctx,
+ asm330lhh_odr_xl_t val);
+int32_t asm330lhh_xl_data_rate_get(stmdev_ctx_t *ctx,
+ asm330lhh_odr_xl_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_125dps = 2,
ASM330LHH_250dps = 0,
ASM330LHH_500dps = 4,
@@ -905,10 +961,13 @@ typedef enum {
ASM330LHH_2000dps = 12,
ASM330LHH_4000dps = 1,
} asm330lhh_fs_g_t;
-int32_t asm330lhh_gy_full_scale_set(stmdev_ctx_t *ctx, asm330lhh_fs_g_t val);
-int32_t asm330lhh_gy_full_scale_get(stmdev_ctx_t *ctx, asm330lhh_fs_g_t *val);
+int32_t asm330lhh_gy_full_scale_set(stmdev_ctx_t *ctx,
+ asm330lhh_fs_g_t val);
+int32_t asm330lhh_gy_full_scale_get(stmdev_ctx_t *ctx,
+ asm330lhh_fs_g_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_GY_ODR_OFF = 0,
ASM330LHH_GY_ODR_12Hz5 = 1,
ASM330LHH_GY_ODR_26Hz = 2,
@@ -922,49 +981,62 @@ typedef enum {
ASM330LHH_GY_ODR_6667Hz = 10,
} asm330lhh_odr_g_t;
int32_t asm330lhh_gy_data_rate_set(stmdev_ctx_t *ctx,
- asm330lhh_odr_g_t val);
+ asm330lhh_odr_g_t val);
int32_t asm330lhh_gy_data_rate_get(stmdev_ctx_t *ctx,
- asm330lhh_odr_g_t *val);
+ asm330lhh_odr_g_t *val);
-int32_t asm330lhh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t asm330lhh_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t asm330lhh_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t asm330lhh_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_LSb_1mg = 0,
ASM330LHH_LSb_16mg = 1,
} asm330lhh_usr_off_w_t;
int32_t asm330lhh_xl_offset_weight_set(stmdev_ctx_t *ctx,
- asm330lhh_usr_off_w_t val);
+ asm330lhh_usr_off_w_t val);
int32_t asm330lhh_xl_offset_weight_get(stmdev_ctx_t *ctx,
- asm330lhh_usr_off_w_t *val);
+ asm330lhh_usr_off_w_t *val);
-typedef struct {
+typedef struct
+{
asm330lhh_all_int_src_t all_int_src;
asm330lhh_wake_up_src_t wake_up_src;
asm330lhh_tap_src_t tap_src;
asm330lhh_d6d_src_t d6d_src;
asm330lhh_status_reg_t status_reg;
- } asm330lhh_all_sources_t;
+} asm330lhh_all_sources_t;
int32_t asm330lhh_all_sources_get(stmdev_ctx_t *ctx,
- asm330lhh_all_sources_t *val);
+ asm330lhh_all_sources_t *val);
int32_t asm330lhh_status_reg_get(stmdev_ctx_t *ctx,
asm330lhh_status_reg_t *val);
-int32_t asm330lhh_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t asm330lhh_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t asm330lhh_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t asm330lhh_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t asm330lhh_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t asm330lhh_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t asm330lhh_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t asm330lhh_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t asm330lhh_xl_usr_offset_x_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t asm330lhh_xl_usr_offset_x_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
-int32_t asm330lhh_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t asm330lhh_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t asm330lhh_xl_usr_offset_y_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t asm330lhh_xl_usr_offset_y_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
-int32_t asm330lhh_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t asm330lhh_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t asm330lhh_xl_usr_offset_z_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t asm330lhh_xl_usr_offset_z_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
int32_t asm330lhh_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t asm330lhh_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -976,22 +1048,26 @@ int32_t asm330lhh_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t asm330lhh_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_NO_ROUND = 0,
ASM330LHH_ROUND_XL = 1,
ASM330LHH_ROUND_GY = 2,
ASM330LHH_ROUND_GY_XL = 3,
} asm330lhh_rounding_t;
int32_t asm330lhh_rounding_mode_set(stmdev_ctx_t *ctx,
- asm330lhh_rounding_t val);
+ asm330lhh_rounding_t val);
int32_t asm330lhh_rounding_mode_get(stmdev_ctx_t *ctx,
- asm330lhh_rounding_t *val);
+ asm330lhh_rounding_t *val);
-int32_t asm330lhh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t asm330lhh_temperature_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
-int32_t asm330lhh_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t asm330lhh_angular_rate_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
-int32_t asm330lhh_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t asm330lhh_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
int32_t asm330lhh_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1001,14 +1077,15 @@ int32_t asm330lhh_device_conf_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t asm330lhh_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t asm330lhh_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_DRDY_LATCHED = 0,
ASM330LHH_DRDY_PULSED = 1,
} asm330lhh_dataready_pulsed_t;
int32_t asm330lhh_data_ready_mode_set(stmdev_ctx_t *ctx,
- asm330lhh_dataready_pulsed_t val);
+ asm330lhh_dataready_pulsed_t val);
int32_t asm330lhh_data_ready_mode_get(stmdev_ctx_t *ctx,
- asm330lhh_dataready_pulsed_t *val);
+ asm330lhh_dataready_pulsed_t *val);
int32_t asm330lhh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
@@ -1021,21 +1098,27 @@ int32_t asm330lhh_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t asm330lhh_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t asm330lhh_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_XL_ST_DISABLE = 0,
ASM330LHH_XL_ST_POSITIVE = 1,
ASM330LHH_XL_ST_NEGATIVE = 2,
} asm330lhh_st_xl_t;
-int32_t asm330lhh_xl_self_test_set(stmdev_ctx_t *ctx, asm330lhh_st_xl_t val);
-int32_t asm330lhh_xl_self_test_get(stmdev_ctx_t *ctx, asm330lhh_st_xl_t *val);
+int32_t asm330lhh_xl_self_test_set(stmdev_ctx_t *ctx,
+ asm330lhh_st_xl_t val);
+int32_t asm330lhh_xl_self_test_get(stmdev_ctx_t *ctx,
+ asm330lhh_st_xl_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_GY_ST_DISABLE = 0,
ASM330LHH_GY_ST_POSITIVE = 1,
ASM330LHH_GY_ST_NEGATIVE = 3,
} asm330lhh_st_g_t;
-int32_t asm330lhh_gy_self_test_set(stmdev_ctx_t *ctx, asm330lhh_st_g_t val);
-int32_t asm330lhh_gy_self_test_get(stmdev_ctx_t *ctx, asm330lhh_st_g_t *val);
+int32_t asm330lhh_gy_self_test_set(stmdev_ctx_t *ctx,
+ asm330lhh_st_g_t val);
+int32_t asm330lhh_gy_self_test_get(stmdev_ctx_t *ctx,
+ asm330lhh_st_g_t *val);
int32_t asm330lhh_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t asm330lhh_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1043,10 +1126,13 @@ int32_t asm330lhh_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t asm330lhh_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t asm330lhh_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t asm330lhh_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t asm330lhh_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t asm330lhh_filter_settling_mask_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t asm330lhh_filter_settling_mask_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_ULTRA_LIGHT = 0,
ASM330LHH_VERY_LIGHT = 1,
ASM330LHH_LIGHT = 2,
@@ -1056,13 +1142,16 @@ typedef enum {
ASM330LHH_AGGRESSIVE = 6,
ASM330LHH_XTREME = 7,
} asm330lhh_ftype_t;
-int32_t asm330lhh_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, asm330lhh_ftype_t val);
-int32_t asm330lhh_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, asm330lhh_ftype_t *val);
+int32_t asm330lhh_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
+ asm330lhh_ftype_t val);
+int32_t asm330lhh_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
+ asm330lhh_ftype_t *val);
int32_t asm330lhh_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t asm330lhh_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_HP_PATH_DISABLE_ON_OUT = 0x00,
ASM330LHH_SLOPE_ODR_DIV_4 = 0x10,
ASM330LHH_HP_ODR_DIV_10 = 0x11,
@@ -1088,23 +1177,27 @@ typedef enum {
ASM330LHH_LP_ODR_DIV_800 = 0x07,
} asm330lhh_hp_slope_xl_en_t;
int32_t asm330lhh_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
- asm330lhh_hp_slope_xl_en_t val);
+ asm330lhh_hp_slope_xl_en_t val);
int32_t asm330lhh_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
- asm330lhh_hp_slope_xl_en_t *val);
+ asm330lhh_hp_slope_xl_en_t *val);
-int32_t asm330lhh_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t asm330lhh_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t asm330lhh_xl_fast_settling_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t asm330lhh_xl_fast_settling_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_USE_SLOPE = 0,
ASM330LHH_USE_HPF = 1,
} asm330lhh_slope_fds_t;
int32_t asm330lhh_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
- asm330lhh_slope_fds_t val);
+ asm330lhh_slope_fds_t val);
int32_t asm330lhh_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
- asm330lhh_slope_fds_t *val);
+ asm330lhh_slope_fds_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_HP_FILTER_NONE = 0x00,
ASM330LHH_HP_FILTER_16mHz = 0x80,
ASM330LHH_HP_FILTER_65mHz = 0x81,
@@ -1112,91 +1205,110 @@ typedef enum {
ASM330LHH_HP_FILTER_1Hz04 = 0x83,
} asm330lhh_hpm_g_t;
int32_t asm330lhh_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
- asm330lhh_hpm_g_t val);
+ asm330lhh_hpm_g_t val);
int32_t asm330lhh_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
- asm330lhh_hpm_g_t *val);
+ asm330lhh_hpm_g_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_PULL_UP_DISC = 0,
ASM330LHH_PULL_UP_CONNECT = 1,
} asm330lhh_sdo_pu_en_t;
-int32_t asm330lhh_sdo_sa0_mode_set(stmdev_ctx_t *ctx, asm330lhh_sdo_pu_en_t val);
-int32_t asm330lhh_sdo_sa0_mode_get(stmdev_ctx_t *ctx, asm330lhh_sdo_pu_en_t *val);
+int32_t asm330lhh_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
+ asm330lhh_sdo_pu_en_t val);
+int32_t asm330lhh_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
+ asm330lhh_sdo_pu_en_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_SPI_4_WIRE = 0,
ASM330LHH_SPI_3_WIRE = 1,
} asm330lhh_sim_t;
-int32_t asm330lhh_spi_mode_set(stmdev_ctx_t *ctx, asm330lhh_sim_t val);
-int32_t asm330lhh_spi_mode_get(stmdev_ctx_t *ctx, asm330lhh_sim_t *val);
+int32_t asm330lhh_spi_mode_set(stmdev_ctx_t *ctx,
+ asm330lhh_sim_t val);
+int32_t asm330lhh_spi_mode_get(stmdev_ctx_t *ctx,
+ asm330lhh_sim_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_I2C_ENABLE = 0,
ASM330LHH_I2C_DISABLE = 1,
} asm330lhh_i2c_disable_t;
int32_t asm330lhh_i2c_interface_set(stmdev_ctx_t *ctx,
- asm330lhh_i2c_disable_t val);
+ asm330lhh_i2c_disable_t val);
int32_t asm330lhh_i2c_interface_get(stmdev_ctx_t *ctx,
- asm330lhh_i2c_disable_t *val);
+ asm330lhh_i2c_disable_t *val);
-typedef struct {
- asm330lhh_int1_ctrl_t int1_ctrl;
- asm330lhh_md1_cfg_t md1_cfg;
+typedef struct
+{
+ asm330lhh_int1_ctrl_t int1_ctrl;
+ asm330lhh_md1_cfg_t md1_cfg;
} asm330lhh_pin_int1_route_t;
int32_t asm330lhh_pin_int1_route_set(stmdev_ctx_t *ctx,
- asm330lhh_pin_int1_route_t *val);
+ asm330lhh_pin_int1_route_t *val);
int32_t asm330lhh_pin_int1_route_get(stmdev_ctx_t *ctx,
- asm330lhh_pin_int1_route_t *val);
+ asm330lhh_pin_int1_route_t *val);
-typedef struct {
+typedef struct
+{
asm330lhh_int2_ctrl_t int2_ctrl;
asm330lhh_md2_cfg_t md2_cfg;
} asm330lhh_pin_int2_route_t;
int32_t asm330lhh_pin_int2_route_set(stmdev_ctx_t *ctx,
- asm330lhh_pin_int2_route_t *val);
+ asm330lhh_pin_int2_route_t *val);
int32_t asm330lhh_pin_int2_route_get(stmdev_ctx_t *ctx,
- asm330lhh_pin_int2_route_t *val);
+ asm330lhh_pin_int2_route_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_PUSH_PULL = 0,
ASM330LHH_OPEN_DRAIN = 1,
} asm330lhh_pp_od_t;
-int32_t asm330lhh_pin_mode_set(stmdev_ctx_t *ctx, asm330lhh_pp_od_t val);
-int32_t asm330lhh_pin_mode_get(stmdev_ctx_t *ctx, asm330lhh_pp_od_t *val);
+int32_t asm330lhh_pin_mode_set(stmdev_ctx_t *ctx,
+ asm330lhh_pp_od_t val);
+int32_t asm330lhh_pin_mode_get(stmdev_ctx_t *ctx,
+ asm330lhh_pp_od_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_ACTIVE_HIGH = 0,
ASM330LHH_ACTIVE_LOW = 1,
} asm330lhh_h_lactive_t;
-int32_t asm330lhh_pin_polarity_set(stmdev_ctx_t *ctx, asm330lhh_h_lactive_t val);
-int32_t asm330lhh_pin_polarity_get(stmdev_ctx_t *ctx, asm330lhh_h_lactive_t *val);
+int32_t asm330lhh_pin_polarity_set(stmdev_ctx_t *ctx,
+ asm330lhh_h_lactive_t val);
+int32_t asm330lhh_pin_polarity_get(stmdev_ctx_t *ctx,
+ asm330lhh_h_lactive_t *val);
int32_t asm330lhh_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t asm330lhh_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_ALL_INT_PULSED = 0,
ASM330LHH_ALL_INT_LATCHED = 3,
} asm330lhh_lir_t;
-int32_t asm330lhh_int_notification_set(stmdev_ctx_t *ctx, asm330lhh_lir_t val);
-int32_t asm330lhh_int_notification_get(stmdev_ctx_t *ctx, asm330lhh_lir_t *val);
+int32_t asm330lhh_int_notification_set(stmdev_ctx_t *ctx,
+ asm330lhh_lir_t val);
+int32_t asm330lhh_int_notification_get(stmdev_ctx_t *ctx,
+ asm330lhh_lir_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_LSb_FS_DIV_64 = 0,
ASM330LHH_LSb_FS_DIV_256 = 1,
} asm330lhh_wake_ths_w_t;
int32_t asm330lhh_wkup_ths_weight_set(stmdev_ctx_t *ctx,
- asm330lhh_wake_ths_w_t val);
+ asm330lhh_wake_ths_w_t val);
int32_t asm330lhh_wkup_ths_weight_get(stmdev_ctx_t *ctx,
- asm330lhh_wake_ths_w_t *val);
+ asm330lhh_wake_ths_w_t *val);
int32_t asm330lhh_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t asm330lhh_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t asm330lhh_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx,
- uint8_t val);
+ uint8_t val);
int32_t asm330lhh_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx,
- uint8_t *val);
+ uint8_t *val);
int32_t asm330lhh_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t asm330lhh_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1204,44 +1316,48 @@ int32_t asm330lhh_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t asm330lhh_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t asm330lhh_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_DRIVE_SLEEP_CHG_EVENT = 0,
ASM330LHH_DRIVE_SLEEP_STATUS = 1,
} asm330lhh_sleep_status_on_int_t;
int32_t asm330lhh_act_pin_notification_set(stmdev_ctx_t *ctx,
- asm330lhh_sleep_status_on_int_t val);
+ asm330lhh_sleep_status_on_int_t val);
int32_t asm330lhh_act_pin_notification_get(stmdev_ctx_t *ctx,
- asm330lhh_sleep_status_on_int_t *val);
+ asm330lhh_sleep_status_on_int_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_XL_AND_GY_NOT_AFFECTED = 0,
ASM330LHH_XL_12Hz5_GY_NOT_AFFECTED = 1,
ASM330LHH_XL_12Hz5_GY_SLEEP = 2,
ASM330LHH_XL_12Hz5_GY_PD = 3,
} asm330lhh_inact_en_t;
int32_t asm330lhh_act_mode_set(stmdev_ctx_t *ctx,
- asm330lhh_inact_en_t val);
+ asm330lhh_inact_en_t val);
int32_t asm330lhh_act_mode_get(stmdev_ctx_t *ctx,
- asm330lhh_inact_en_t *val);
+ asm330lhh_inact_en_t *val);
int32_t asm330lhh_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t asm330lhh_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_DEG_80 = 0,
ASM330LHH_DEG_70 = 1,
ASM330LHH_DEG_60 = 2,
ASM330LHH_DEG_50 = 3,
} asm330lhh_sixd_ths_t;
int32_t asm330lhh_6d_threshold_set(stmdev_ctx_t *ctx,
- asm330lhh_sixd_ths_t val);
+ asm330lhh_sixd_ths_t val);
int32_t asm330lhh_6d_threshold_get(stmdev_ctx_t *ctx,
- asm330lhh_sixd_ths_t *val);
+ asm330lhh_sixd_ths_t *val);
int32_t asm330lhh_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t asm330lhh_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_FF_TSH_156mg = 0,
ASM330LHH_FF_TSH_219mg = 1,
ASM330LHH_FF_TSH_250mg = 2,
@@ -1252,25 +1368,29 @@ typedef enum {
ASM330LHH_FF_TSH_500mg = 7,
} asm330lhh_ff_ths_t;
int32_t asm330lhh_ff_threshold_set(stmdev_ctx_t *ctx,
- asm330lhh_ff_ths_t val);
+ asm330lhh_ff_ths_t val);
int32_t asm330lhh_ff_threshold_get(stmdev_ctx_t *ctx,
- asm330lhh_ff_ths_t *val);
+ asm330lhh_ff_ths_t *val);
int32_t asm330lhh_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t asm330lhh_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t asm330lhh_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val);
-int32_t asm330lhh_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t asm330lhh_fifo_watermark_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
int32_t asm330lhh_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
- uint8_t val);
+ uint8_t val);
int32_t asm330lhh_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
- uint8_t *val);
+ uint8_t *val);
-int32_t asm330lhh_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t asm330lhh_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t asm330lhh_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t asm330lhh_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_XL_NOT_BATCHED = 0,
ASM330LHH_XL_BATCHED_AT_12Hz5 = 1,
ASM330LHH_XL_BATCHED_AT_26Hz = 2,
@@ -1284,10 +1404,13 @@ typedef enum {
ASM330LHH_XL_BATCHED_AT_6667Hz = 10,
ASM330LHH_XL_BATCHED_AT_6Hz5 = 11,
} asm330lhh_bdr_xl_t;
-int32_t asm330lhh_fifo_xl_batch_set(stmdev_ctx_t *ctx, asm330lhh_bdr_xl_t val);
-int32_t asm330lhh_fifo_xl_batch_get(stmdev_ctx_t *ctx, asm330lhh_bdr_xl_t *val);
+int32_t asm330lhh_fifo_xl_batch_set(stmdev_ctx_t *ctx,
+ asm330lhh_bdr_xl_t val);
+int32_t asm330lhh_fifo_xl_batch_get(stmdev_ctx_t *ctx,
+ asm330lhh_bdr_xl_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_GY_NOT_BATCHED = 0,
ASM330LHH_GY_BATCHED_AT_12Hz5 = 1,
ASM330LHH_GY_BATCHED_AT_26Hz = 2,
@@ -1301,10 +1424,13 @@ typedef enum {
ASM330LHH_GY_BATCHED_AT_6667Hz = 10,
ASM330LHH_GY_BATCHED_6Hz5 = 11,
} asm330lhh_bdr_gy_t;
-int32_t asm330lhh_fifo_gy_batch_set(stmdev_ctx_t *ctx, asm330lhh_bdr_gy_t val);
-int32_t asm330lhh_fifo_gy_batch_get(stmdev_ctx_t *ctx, asm330lhh_bdr_gy_t *val);
+int32_t asm330lhh_fifo_gy_batch_set(stmdev_ctx_t *ctx,
+ asm330lhh_bdr_gy_t val);
+int32_t asm330lhh_fifo_gy_batch_get(stmdev_ctx_t *ctx,
+ asm330lhh_bdr_gy_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_BYPASS_MODE = 0,
ASM330LHH_FIFO_MODE = 1,
ASM330LHH_STREAM_TO_FIFO_MODE = 3,
@@ -1312,52 +1438,60 @@ typedef enum {
ASM330LHH_STREAM_MODE = 6,
ASM330LHH_BYPASS_TO_FIFO_MODE = 7,
} asm330lhh_fifo_mode_t;
-int32_t asm330lhh_fifo_mode_set(stmdev_ctx_t *ctx, asm330lhh_fifo_mode_t val);
-int32_t asm330lhh_fifo_mode_get(stmdev_ctx_t *ctx, asm330lhh_fifo_mode_t *val);
+int32_t asm330lhh_fifo_mode_set(stmdev_ctx_t *ctx,
+ asm330lhh_fifo_mode_t val);
+int32_t asm330lhh_fifo_mode_get(stmdev_ctx_t *ctx,
+ asm330lhh_fifo_mode_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_TEMP_NOT_BATCHED = 0,
ASM330LHH_TEMP_BATCHED_AT_52Hz = 1,
ASM330LHH_TEMP_BATCHED_AT_12Hz5 = 2,
ASM330LHH_TEMP_BATCHED_AT_1Hz6 = 3,
} asm330lhh_odr_t_batch_t;
int32_t asm330lhh_fifo_temp_batch_set(stmdev_ctx_t *ctx,
- asm330lhh_odr_t_batch_t val);
+ asm330lhh_odr_t_batch_t val);
int32_t asm330lhh_fifo_temp_batch_get(stmdev_ctx_t *ctx,
- asm330lhh_odr_t_batch_t *val);
+ asm330lhh_odr_t_batch_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_NO_DECIMATION = 0,
ASM330LHH_DEC_1 = 1,
ASM330LHH_DEC_8 = 2,
ASM330LHH_DEC_32 = 3,
} asm330lhh_odr_ts_batch_t;
int32_t asm330lhh_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
- asm330lhh_odr_ts_batch_t val);
+ asm330lhh_odr_ts_batch_t val);
int32_t asm330lhh_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
- asm330lhh_odr_ts_batch_t *val);
+ asm330lhh_odr_ts_batch_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_XL_BATCH_EVENT = 0,
ASM330LHH_GYRO_BATCH_EVENT = 1,
} asm330lhh_trig_counter_bdr_t;
int32_t asm330lhh_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
- asm330lhh_trig_counter_bdr_t val);
+ asm330lhh_trig_counter_bdr_t val);
int32_t asm330lhh_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
- asm330lhh_trig_counter_bdr_t *val);
+ asm330lhh_trig_counter_bdr_t *val);
-int32_t asm330lhh_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t asm330lhh_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t asm330lhh_rst_batch_counter_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t asm330lhh_rst_batch_counter_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t asm330lhh_batch_counter_threshold_set(stmdev_ctx_t *ctx,
- uint16_t val);
+ uint16_t val);
int32_t asm330lhh_batch_counter_threshold_get(stmdev_ctx_t *ctx,
- uint16_t *val);
+ uint16_t *val);
-int32_t asm330lhh_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t asm330lhh_fifo_data_level_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
int32_t asm330lhh_fifo_status_get(stmdev_ctx_t *ctx,
- asm330lhh_fifo_status2_t *val);
+ asm330lhh_fifo_status2_t *val);
int32_t asm330lhh_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1365,7 +1499,8 @@ int32_t asm330lhh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t asm330lhh_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_GYRO_NC_TAG = 1,
ASM330LHH_XL_NC_TAG,
ASM330LHH_TEMPERATURE_TAG,
@@ -1373,9 +1508,10 @@ typedef enum {
ASM330LHH_CFG_CHANGE_TAG,
} asm330lhh_fifo_tag_t;
int32_t asm330lhh_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
- asm330lhh_fifo_tag_t *val);
+ asm330lhh_fifo_tag_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_DEN_DISABLE = 0,
ASM330LHH_LEVEL_FIFO = 6,
ASM330LHH_LEVEL_LETCHED = 3,
@@ -1383,37 +1519,42 @@ typedef enum {
ASM330LHH_EDGE_TRIGGER = 4,
} asm330lhh_den_mode_t;
int32_t asm330lhh_den_mode_set(stmdev_ctx_t *ctx,
- asm330lhh_den_mode_t val);
+ asm330lhh_den_mode_t val);
int32_t asm330lhh_den_mode_get(stmdev_ctx_t *ctx,
- asm330lhh_den_mode_t *val);
+ asm330lhh_den_mode_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_DEN_ACT_LOW = 0,
ASM330LHH_DEN_ACT_HIGH = 1,
} asm330lhh_den_lh_t;
int32_t asm330lhh_den_polarity_set(stmdev_ctx_t *ctx,
- asm330lhh_den_lh_t val);
+ asm330lhh_den_lh_t val);
int32_t asm330lhh_den_polarity_get(stmdev_ctx_t *ctx,
- asm330lhh_den_lh_t *val);
+ asm330lhh_den_lh_t *val);
-typedef enum {
+typedef enum
+{
ASM330LHH_STAMP_IN_GY_DATA = 0,
ASM330LHH_STAMP_IN_XL_DATA = 1,
ASM330LHH_STAMP_IN_GY_XL_DATA = 2,
} asm330lhh_den_xl_g_t;
int32_t asm330lhh_den_enable_set(stmdev_ctx_t *ctx,
- asm330lhh_den_xl_g_t val);
+ asm330lhh_den_xl_g_t val);
int32_t asm330lhh_den_enable_get(stmdev_ctx_t *ctx,
- asm330lhh_den_xl_g_t *val);
+ asm330lhh_den_xl_g_t *val);
int32_t asm330lhh_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t asm330lhh_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t asm330lhh_den_mark_axis_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t asm330lhh_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t asm330lhh_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t asm330lhh_den_mark_axis_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t asm330lhh_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t asm330lhh_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t asm330lhh_den_mark_axis_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
/**
*@}
diff --git a/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.c b/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.c
index b17e3cf14c107a45101dabb1a7dc03aaafe724c1..b8a6dfba7cc09973447dfa06b5536368df49aa94 100644
--- a/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.c
+++ b/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file h3lis100dl_reg.c
- * @author Sensors Software Solution Team
- * @brief H3LIS100DL driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file h3lis100dl_reg.c
+ * @author Sensors Software Solution Team
+ * @brief H3LIS100DL driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "h3lis100dl_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis100dl_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t h3lis100dl_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t h3lis100dl_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis100dl_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t h3lis100dl_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -77,7 +83,7 @@ int32_t h3lis100dl_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
*
*/
- /**
+/**
* @defgroup H3LIS100DL_Sensitivity
* @brief These functions convert raw-data into engineering units.
* @{
@@ -86,7 +92,7 @@ int32_t h3lis100dl_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
float_t h3lis100dl_from_fs100g_to_mg(int8_t lsb)
{
- return ( (float_t)lsb / 256.0f ) * 780.0f;
+ return ((float_t)lsb / 256.0f) * 780.0f;
}
/**
@@ -107,6 +113,7 @@ float_t h3lis100dl_from_fs100g_to_mg(int8_t lsb)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of xen in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -114,12 +121,16 @@ int32_t h3lis100dl_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val)
h3lis100dl_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0) {
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.xen = val;
ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -128,6 +139,7 @@ int32_t h3lis100dl_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of xen in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -135,7 +147,8 @@ int32_t h3lis100dl_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val)
h3lis100dl_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
*val = ctrl_reg1.xen;
return ret;
@@ -146,6 +159,7 @@ int32_t h3lis100dl_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of yen in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -153,12 +167,16 @@ int32_t h3lis100dl_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val)
h3lis100dl_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0) {
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.yen = val;
ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -167,6 +185,7 @@ int32_t h3lis100dl_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of yen in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -174,7 +193,8 @@ int32_t h3lis100dl_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val)
h3lis100dl_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
*val = ctrl_reg1.yen;
return ret;
@@ -185,6 +205,7 @@ int32_t h3lis100dl_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of zen in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -192,12 +213,16 @@ int32_t h3lis100dl_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val)
h3lis100dl_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0) {
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.zen = val;
ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -206,6 +231,7 @@ int32_t h3lis100dl_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of zen in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -213,7 +239,8 @@ int32_t h3lis100dl_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val)
h3lis100dl_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
*val = ctrl_reg1.zen;
return ret;
@@ -224,21 +251,26 @@ int32_t h3lis100dl_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of dr in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis100dl_data_rate_set(stmdev_ctx_t *ctx, h3lis100dl_dr_t val)
+int32_t h3lis100dl_data_rate_set(stmdev_ctx_t *ctx,
+ h3lis100dl_dr_t val)
{
h3lis100dl_ctrl_reg1_t ctrl_reg1;
int32_t ret;
ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0) {
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.pm = (uint8_t)val & 0x07U;
- ctrl_reg1.dr = ( (uint8_t)val & 0x30U ) >> 4;
+ ctrl_reg1.dr = ((uint8_t)val & 0x30U) >> 4;
ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -247,45 +279,56 @@ int32_t h3lis100dl_data_rate_set(stmdev_ctx_t *ctx, h3lis100dl_dr_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of dr in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis100dl_data_rate_get(stmdev_ctx_t *ctx, h3lis100dl_dr_t *val)
+int32_t h3lis100dl_data_rate_get(stmdev_ctx_t *ctx,
+ h3lis100dl_dr_t *val)
{
h3lis100dl_ctrl_reg1_t ctrl_reg1;
int32_t ret;
ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pm)
{
case H3LIS100DL_ODR_OFF:
*val = H3LIS100DL_ODR_OFF;
break;
+
case H3LIS100DL_ODR_Hz5:
*val = H3LIS100DL_ODR_Hz5;
break;
+
case H3LIS100DL_ODR_1Hz:
*val = H3LIS100DL_ODR_1Hz;
break;
+
case H3LIS100DL_ODR_2Hz:
*val = H3LIS100DL_ODR_2Hz;
break;
+
case H3LIS100DL_ODR_5Hz:
*val = H3LIS100DL_ODR_5Hz;
break;
+
case H3LIS100DL_ODR_10Hz:
*val = H3LIS100DL_ODR_10Hz;
break;
+
case H3LIS100DL_ODR_50Hz:
*val = H3LIS100DL_ODR_50Hz;
break;
+
case H3LIS100DL_ODR_100Hz:
*val = H3LIS100DL_ODR_100Hz;
break;
+
case H3LIS100DL_ODR_400Hz:
*val = H3LIS100DL_ODR_400Hz;
break;
+
default:
*val = H3LIS100DL_ODR_OFF;
break;
@@ -299,20 +342,25 @@ int32_t h3lis100dl_data_rate_get(stmdev_ctx_t *ctx, h3lis100dl_dr_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of hpm in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_reference_mode_set(stmdev_ctx_t *ctx,
- h3lis100dl_hpm_t val)
+ h3lis100dl_hpm_t val)
{
h3lis100dl_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0) {
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpm = (uint8_t)val;
ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -321,29 +369,33 @@ int32_t h3lis100dl_reference_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of hpm in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_reference_mode_get(stmdev_ctx_t *ctx,
- h3lis100dl_hpm_t *val)
+ h3lis100dl_hpm_t *val)
{
h3lis100dl_ctrl_reg2_t ctrl_reg2;
int32_t ret;
ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
switch (ctrl_reg2.hpm)
{
case H3LIS100DL_NORMAL_MODE:
*val = H3LIS100DL_NORMAL_MODE;
break;
+
case H3LIS100DL_REF_MODE_ENABLE:
*val = H3LIS100DL_REF_MODE_ENABLE;
break;
+
default:
*val = H3LIS100DL_NORMAL_MODE;
break;
}
+
return ret;
}
@@ -352,13 +404,16 @@ int32_t h3lis100dl_reference_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val registers STATUS_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_status_reg_get(stmdev_ctx_t *ctx,
- h3lis100dl_status_reg_t *val)
+ h3lis100dl_status_reg_t *val)
{
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_STATUS_REG, (uint8_t*) val, 1);
+
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_STATUS_REG, (uint8_t *) val, 1);
+
return ret;
}
@@ -367,15 +422,17 @@ int32_t h3lis100dl_status_reg_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of zyxda in reg STATUS_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis100dl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t h3lis100dl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
h3lis100dl_status_reg_t status_reg;
int32_t ret;
ret = h3lis100dl_read_reg(ctx, H3LIS100DL_STATUS_REG,
- (uint8_t*)&status_reg, 1);
+ (uint8_t *)&status_reg, 1);
*val = status_reg.zyxda;
return ret;
@@ -399,20 +456,22 @@ int32_t h3lis100dl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis100dl_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
+int32_t h3lis100dl_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
{
uint8_t buff[6];
int32_t ret;
ret = h3lis100dl_read_reg(ctx, (H3LIS100DL_OUT_X - 1U), buff, 6);
val[0] = (int16_t)buff[1];
- val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
- val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
val[2] = (int16_t)buff[5];
- val[2] = (val[2] * 256) + (int16_t)buff[4];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
return ret;
}
@@ -434,12 +493,15 @@ int32_t h3lis100dl_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = h3lis100dl_read_reg(ctx, H3LIS100DL_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -448,6 +510,7 @@ int32_t h3lis100dl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of boot in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_boot_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -455,12 +518,16 @@ int32_t h3lis100dl_boot_set(stmdev_ctx_t *ctx, uint8_t val)
h3lis100dl_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0) {
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.boot = val;
ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -469,6 +536,7 @@ int32_t h3lis100dl_boot_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of boot in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -476,7 +544,8 @@ int32_t h3lis100dl_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
h3lis100dl_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
*val = ctrl_reg2.boot;
return ret;
@@ -500,19 +569,25 @@ int32_t h3lis100dl_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of hpcf in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis100dl_hp_bandwidth_set(stmdev_ctx_t *ctx, h3lis100dl_hpcf_t val)
+int32_t h3lis100dl_hp_bandwidth_set(stmdev_ctx_t *ctx,
+ h3lis100dl_hpcf_t val)
{
h3lis100dl_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0) {
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpcf = (uint8_t)val;
ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -521,30 +596,36 @@ int32_t h3lis100dl_hp_bandwidth_set(stmdev_ctx_t *ctx, h3lis100dl_hpcf_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of hpcf in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_hp_bandwidth_get(stmdev_ctx_t *ctx,
- h3lis100dl_hpcf_t *val)
+ h3lis100dl_hpcf_t *val)
{
h3lis100dl_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
switch (ctrl_reg2.hpcf)
{
case H3LIS100DL_CUT_OFF_8Hz:
*val = H3LIS100DL_CUT_OFF_8Hz;
break;
+
case H3LIS100DL_CUT_OFF_16Hz:
*val = H3LIS100DL_CUT_OFF_16Hz;
break;
+
case H3LIS100DL_CUT_OFF_32Hz:
*val = H3LIS100DL_CUT_OFF_32Hz;
break;
+
case H3LIS100DL_CUT_OFF_64Hz:
*val = H3LIS100DL_CUT_OFF_64Hz;
break;
+
default:
*val = H3LIS100DL_CUT_OFF_8Hz;
break;
@@ -558,20 +639,26 @@ int32_t h3lis100dl_hp_bandwidth_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of hpen in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis100dl_hp_path_set(stmdev_ctx_t *ctx, h3lis100dl_hpen_t val)
+int32_t h3lis100dl_hp_path_set(stmdev_ctx_t *ctx,
+ h3lis100dl_hpen_t val)
{
h3lis100dl_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0) {
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpen = (uint8_t)val & 0x03U;
ctrl_reg2.fds = ((uint8_t)val & 0x04U) >> 2;
ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -580,45 +667,57 @@ int32_t h3lis100dl_hp_path_set(stmdev_ctx_t *ctx, h3lis100dl_hpen_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of hpen in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis100dl_hp_path_get(stmdev_ctx_t *ctx, h3lis100dl_hpen_t *val)
+int32_t h3lis100dl_hp_path_get(stmdev_ctx_t *ctx,
+ h3lis100dl_hpen_t *val)
{
h3lis100dl_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
- switch ( (ctrl_reg2.fds << 2) + ctrl_reg2.hpen )
+ switch ((ctrl_reg2.fds << 2) + ctrl_reg2.hpen)
{
case H3LIS100DL_HP_DISABLE:
*val = H3LIS100DL_HP_DISABLE;
break;
+
case H3LIS100DL_HP_ON_OUT:
*val = H3LIS100DL_HP_ON_OUT;
break;
+
case H3LIS100DL_HP_ON_INT1:
*val = H3LIS100DL_HP_ON_INT1;
break;
+
case H3LIS100DL_HP_ON_INT2:
*val = H3LIS100DL_HP_ON_INT2;
break;
+
case H3LIS100DL_HP_ON_INT1_INT2:
*val = H3LIS100DL_HP_ON_INT1_INT2;
break;
+
case H3LIS100DL_HP_ON_INT1_INT2_OUT:
*val = H3LIS100DL_HP_ON_INT1_INT2_OUT;
break;
+
case H3LIS100DL_HP_ON_INT2_OUT:
*val = H3LIS100DL_HP_ON_INT2_OUT;
break;
+
case H3LIS100DL_HP_ON_INT1_OUT:
*val = H3LIS100DL_HP_ON_INT1_OUT;
break;
+
default:
*val = H3LIS100DL_HP_DISABLE;
break;
}
+
return ret;
}
@@ -631,14 +730,17 @@ int32_t h3lis100dl_hp_path_get(stmdev_ctx_t *ctx, h3lis100dl_hpen_t *val)
* filter.[get]
*
* @param ctx read / write interface definitions(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_hp_reset_get(stmdev_ctx_t *ctx)
{
uint8_t dummy;
int32_t ret;
+
ret = h3lis100dl_read_reg(ctx, H3LIS100DL_HP_FILTER_RESET,
- (uint8_t*)&dummy, 1);
+ (uint8_t *)&dummy, 1);
+
return ret;
}
@@ -647,12 +749,16 @@ int32_t h3lis100dl_hp_reset_get(stmdev_ctx_t *ctx)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ref in reg REFERENCE
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis100dl_hp_reference_value_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t h3lis100dl_hp_reference_value_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
int32_t ret;
- ret = h3lis100dl_write_reg(ctx, H3LIS100DL_REFERENCE, (uint8_t*)&val, 1);
+
+ ret = h3lis100dl_write_reg(ctx, H3LIS100DL_REFERENCE, (uint8_t *)&val, 1);
+
return ret;
}
@@ -661,12 +767,16 @@ int32_t h3lis100dl_hp_reference_value_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ref in reg REFERENCE
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis100dl_hp_reference_value_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t h3lis100dl_hp_reference_value_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
int32_t ret;
+
ret = h3lis100dl_read_reg(ctx, H3LIS100DL_REFERENCE, val, 1);
+
return ret;
}
@@ -688,19 +798,25 @@ int32_t h3lis100dl_hp_reference_value_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of sim in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis100dl_spi_mode_set(stmdev_ctx_t *ctx, h3lis100dl_sim_t val)
+int32_t h3lis100dl_spi_mode_set(stmdev_ctx_t *ctx,
+ h3lis100dl_sim_t val)
{
h3lis100dl_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0) {
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.sim = (uint8_t)val;
ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -709,23 +825,28 @@ int32_t h3lis100dl_spi_mode_set(stmdev_ctx_t *ctx, h3lis100dl_sim_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of sim in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis100dl_spi_mode_get(stmdev_ctx_t *ctx, h3lis100dl_sim_t *val)
+int32_t h3lis100dl_spi_mode_get(stmdev_ctx_t *ctx,
+ h3lis100dl_sim_t *val)
{
h3lis100dl_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
- switch ( ctrl_reg4.sim )
+ switch (ctrl_reg4.sim)
{
case H3LIS100DL_SPI_4_WIRE:
*val = H3LIS100DL_SPI_4_WIRE;
break;
+
case H3LIS100DL_SPI_3_WIRE:
*val = H3LIS100DL_SPI_3_WIRE;
break;
+
default:
*val = H3LIS100DL_SPI_4_WIRE;
break;
@@ -752,20 +873,25 @@ int32_t h3lis100dl_spi_mode_get(stmdev_ctx_t *ctx, h3lis100dl_sim_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of i1_cfg in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_pin_int1_route_set(stmdev_ctx_t *ctx,
- h3lis100dl_i1_cfg_t val)
+ h3lis100dl_i1_cfg_t val)
{
h3lis100dl_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.i1_cfg = (uint8_t)val;
ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -774,30 +900,36 @@ int32_t h3lis100dl_pin_int1_route_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of i1_cfg in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_pin_int1_route_get(stmdev_ctx_t *ctx,
- h3lis100dl_i1_cfg_t *val)
+ h3lis100dl_i1_cfg_t *val)
{
h3lis100dl_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.i1_cfg )
+ switch (ctrl_reg3.i1_cfg)
{
case H3LIS100DL_PAD1_INT1_SRC:
*val = H3LIS100DL_PAD1_INT1_SRC;
break;
+
case H3LIS100DL_PAD1_INT1_OR_INT2_SRC:
*val = H3LIS100DL_PAD1_INT1_OR_INT2_SRC;
break;
+
case H3LIS100DL_PAD1_DRDY:
*val = H3LIS100DL_PAD1_DRDY;
break;
+
case H3LIS100DL_PAD1_BOOT:
*val = H3LIS100DL_PAD1_BOOT;
break;
+
default:
*val = H3LIS100DL_PAD1_INT1_SRC;
break;
@@ -812,20 +944,25 @@ int32_t h3lis100dl_pin_int1_route_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of lir1 in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_int1_notification_set(stmdev_ctx_t *ctx,
- h3lis100dl_lir1_t val)
+ h3lis100dl_lir1_t val)
{
h3lis100dl_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.lir1 = (uint8_t)val;
ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -835,24 +972,28 @@ int32_t h3lis100dl_int1_notification_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of lir1 in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_int1_notification_get(stmdev_ctx_t *ctx,
- h3lis100dl_lir1_t *val)
+ h3lis100dl_lir1_t *val)
{
h3lis100dl_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.lir1 )
+ switch (ctrl_reg3.lir1)
{
case H3LIS100DL_INT1_PULSED:
*val = H3LIS100DL_INT1_PULSED;
break;
+
case H3LIS100DL_INT1_LATCHED:
*val = H3LIS100DL_INT1_LATCHED;
break;
+
default:
*val = H3LIS100DL_INT1_PULSED;
break;
@@ -866,20 +1007,25 @@ int32_t h3lis100dl_int1_notification_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of i2_cfg in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_pin_int2_route_set(stmdev_ctx_t *ctx,
- h3lis100dl_i2_cfg_t val)
+ h3lis100dl_i2_cfg_t val)
{
h3lis100dl_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.i2_cfg = (uint8_t)val;
ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -888,30 +1034,36 @@ int32_t h3lis100dl_pin_int2_route_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of i2_cfg in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_pin_int2_route_get(stmdev_ctx_t *ctx,
- h3lis100dl_i2_cfg_t *val)
+ h3lis100dl_i2_cfg_t *val)
{
h3lis100dl_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.i2_cfg )
+ switch (ctrl_reg3.i2_cfg)
{
case H3LIS100DL_PAD2_INT2_SRC:
*val = H3LIS100DL_PAD2_INT2_SRC;
break;
+
case H3LIS100DL_PAD2_INT1_OR_INT2_SRC:
*val = H3LIS100DL_PAD2_INT1_OR_INT2_SRC;
break;
+
case H3LIS100DL_PAD2_DRDY:
*val = H3LIS100DL_PAD2_DRDY;
break;
+
case H3LIS100DL_PAD2_BOOT:
*val = H3LIS100DL_PAD2_BOOT;
break;
+
default:
*val = H3LIS100DL_PAD2_INT2_SRC;
break;
@@ -926,20 +1078,25 @@ int32_t h3lis100dl_pin_int2_route_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of lir2 in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_int2_notification_set(stmdev_ctx_t *ctx,
- h3lis100dl_lir2_t val)
+ h3lis100dl_lir2_t val)
{
h3lis100dl_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.lir2 = (uint8_t)val;
ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -949,24 +1106,28 @@ int32_t h3lis100dl_int2_notification_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of lir2 in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_int2_notification_get(stmdev_ctx_t *ctx,
- h3lis100dl_lir2_t *val)
+ h3lis100dl_lir2_t *val)
{
h3lis100dl_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.lir2 )
+ switch (ctrl_reg3.lir2)
{
case H3LIS100DL_INT2_PULSED:
*val = H3LIS100DL_INT2_PULSED;
break;
+
case H3LIS100DL_INT2_LATCHED:
*val = H3LIS100DL_INT2_LATCHED;
break;
+
default:
*val = H3LIS100DL_INT2_PULSED;
break;
@@ -980,19 +1141,25 @@ int32_t h3lis100dl_int2_notification_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of pp_od in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis100dl_pin_mode_set(stmdev_ctx_t *ctx, h3lis100dl_pp_od_t val)
+int32_t h3lis100dl_pin_mode_set(stmdev_ctx_t *ctx,
+ h3lis100dl_pp_od_t val)
{
h3lis100dl_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.pp_od = (uint8_t)val;
ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1001,23 +1168,28 @@ int32_t h3lis100dl_pin_mode_set(stmdev_ctx_t *ctx, h3lis100dl_pp_od_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of pp_od in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis100dl_pin_mode_get(stmdev_ctx_t *ctx, h3lis100dl_pp_od_t *val)
+int32_t h3lis100dl_pin_mode_get(stmdev_ctx_t *ctx,
+ h3lis100dl_pp_od_t *val)
{
h3lis100dl_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.pp_od )
+ switch (ctrl_reg3.pp_od)
{
case H3LIS100DL_PUSH_PULL:
*val = H3LIS100DL_PUSH_PULL;
break;
+
case H3LIS100DL_OPEN_DRAIN:
*val = H3LIS100DL_OPEN_DRAIN;
break;
+
default:
*val = H3LIS100DL_PUSH_PULL;
break;
@@ -1031,19 +1203,25 @@ int32_t h3lis100dl_pin_mode_get(stmdev_ctx_t *ctx, h3lis100dl_pp_od_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ihl in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis100dl_pin_polarity_set(stmdev_ctx_t *ctx, h3lis100dl_ihl_t val)
+int32_t h3lis100dl_pin_polarity_set(stmdev_ctx_t *ctx,
+ h3lis100dl_ihl_t val)
{
h3lis100dl_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.ihl = (uint8_t)val;
ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1052,23 +1230,28 @@ int32_t h3lis100dl_pin_polarity_set(stmdev_ctx_t *ctx, h3lis100dl_ihl_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of ihl in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis100dl_pin_polarity_get(stmdev_ctx_t *ctx, h3lis100dl_ihl_t *val)
+int32_t h3lis100dl_pin_polarity_get(stmdev_ctx_t *ctx,
+ h3lis100dl_ihl_t *val)
{
h3lis100dl_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.ihl )
+ switch (ctrl_reg3.ihl)
{
case H3LIS100DL_ACTIVE_HIGH:
*val = H3LIS100DL_ACTIVE_HIGH;
break;
+
case H3LIS100DL_ACTIVE_LOW:
*val = H3LIS100DL_ACTIVE_LOW;
break;
+
default:
*val = H3LIS100DL_ACTIVE_HIGH;
break;
@@ -1095,6 +1278,7 @@ int32_t h3lis100dl_pin_polarity_get(stmdev_ctx_t *ctx, h3lis100dl_ihl_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val enable sign and axis for interrupt on threshold
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_int1_on_threshold_conf_set(stmdev_ctx_t *ctx,
@@ -1103,8 +1287,11 @@ int32_t h3lis100dl_int1_on_threshold_conf_set(stmdev_ctx_t *ctx,
h3lis100dl_int1_cfg_t int1_cfg;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT1_CFG, (uint8_t*)&int1_cfg, 1);
- if(ret == 0) {
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT1_CFG,
+ (uint8_t *)&int1_cfg, 1);
+
+ if (ret == 0)
+ {
int1_cfg.xlie = val.int1_xlie;
int1_cfg.xhie = val.int1_xhie;
int1_cfg.ylie = val.int1_ylie;
@@ -1112,8 +1299,9 @@ int32_t h3lis100dl_int1_on_threshold_conf_set(stmdev_ctx_t *ctx,
int1_cfg.zlie = val.int1_zlie;
int1_cfg.zhie = val.int1_zhie;
ret = h3lis100dl_write_reg(ctx, H3LIS100DL_INT1_CFG,
- (uint8_t*)&int1_cfg, 1);
+ (uint8_t *)&int1_cfg, 1);
}
+
return ret;
}
@@ -1122,15 +1310,17 @@ int32_t h3lis100dl_int1_on_threshold_conf_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val enable sign and axis for interrupt on threshold
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_int1_on_threshold_conf_get(stmdev_ctx_t *ctx,
- int1_on_th_conf_t *val)
+ int1_on_th_conf_t *val)
{
h3lis100dl_int1_cfg_t int1_cfg;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT1_CFG, (uint8_t*)&int1_cfg, 1);
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT1_CFG,
+ (uint8_t *)&int1_cfg, 1);
val->int1_xlie = int1_cfg.xlie;
val->int1_xhie = int1_cfg.xhie;
val->int1_ylie = int1_cfg.ylie;
@@ -1146,20 +1336,25 @@ int32_t h3lis100dl_int1_on_threshold_conf_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of aoi in reg INT1_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_int1_on_threshold_mode_set(stmdev_ctx_t *ctx,
- h3lis100dl_int1_aoi_t val)
+ h3lis100dl_int1_aoi_t val)
{
h3lis100dl_int1_cfg_t int1_cfg;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT1_CFG, (uint8_t*)&int1_cfg, 1);
- if(ret == 0) {
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT1_CFG,
+ (uint8_t *)&int1_cfg, 1);
+
+ if (ret == 0)
+ {
int1_cfg.aoi = (uint8_t) val;
ret = h3lis100dl_write_reg(ctx, H3LIS100DL_INT1_CFG,
- (uint8_t*)&int1_cfg, 1);
+ (uint8_t *)&int1_cfg, 1);
}
+
return ret;
}
@@ -1168,24 +1363,28 @@ int32_t h3lis100dl_int1_on_threshold_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of aoi in reg INT1_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_int1_on_threshold_mode_get(stmdev_ctx_t *ctx,
- h3lis100dl_int1_aoi_t *val)
+ h3lis100dl_int1_aoi_t *val)
{
h3lis100dl_int1_cfg_t int1_cfg;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT1_CFG, (uint8_t*)&int1_cfg, 1);
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT1_CFG,
+ (uint8_t *)&int1_cfg, 1);
- switch ( int1_cfg.aoi )
+ switch (int1_cfg.aoi)
{
case H3LIS100DL_INT1_ON_THRESHOLD_OR:
*val = H3LIS100DL_INT1_ON_THRESHOLD_OR;
break;
+
case H3LIS100DL_INT1_ON_THRESHOLD_AND:
*val = H3LIS100DL_INT1_ON_THRESHOLD_AND;
break;
+
default:
*val = H3LIS100DL_INT1_ON_THRESHOLD_OR;
break;
@@ -1199,13 +1398,16 @@ int32_t h3lis100dl_int1_on_threshold_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val registers INT1_SRC
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_int1_src_get(stmdev_ctx_t *ctx,
- h3lis100dl_int1_src_t *val)
+ h3lis100dl_int1_src_t *val)
{
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT1_SRC, (uint8_t*) val, 1);
+
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT1_SRC, (uint8_t *) val, 1);
+
return ret;
}
@@ -1214,6 +1416,7 @@ int32_t h3lis100dl_int1_src_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ths in reg INT1_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1221,12 +1424,16 @@ int32_t h3lis100dl_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
h3lis100dl_int1_ths_t int1_ths;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT1_THS, (uint8_t*)&int1_ths, 1);
- if(ret == 0) {
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT1_THS,
+ (uint8_t *)&int1_ths, 1);
+
+ if (ret == 0)
+ {
int1_ths.ths = val;
ret = h3lis100dl_write_reg(ctx, H3LIS100DL_INT1_THS,
- (uint8_t*)&int1_ths, 1);
+ (uint8_t *)&int1_ths, 1);
}
+
return ret;
}
@@ -1235,6 +1442,7 @@ int32_t h3lis100dl_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ths in reg INT1_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1242,7 +1450,8 @@ int32_t h3lis100dl_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
h3lis100dl_int1_ths_t int1_ths;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT1_THS, (uint8_t*)&int1_ths, 1);
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT1_THS,
+ (uint8_t *)&int1_ths, 1);
*val = int1_ths.ths;
return ret;
@@ -1253,6 +1462,7 @@ int32_t h3lis100dl_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of d in reg INT1_DURATION
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1261,12 +1471,15 @@ int32_t h3lis100dl_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT1_DURATION,
- (uint8_t*)&int1_duration, 1);
- if(ret == 0) {
+ (uint8_t *)&int1_duration, 1);
+
+ if (ret == 0)
+ {
int1_duration.d = val;
ret = h3lis100dl_write_reg(ctx, H3LIS100DL_INT1_DURATION,
- (uint8_t*)&int1_duration, 1);
+ (uint8_t *)&int1_duration, 1);
}
+
return ret;
}
@@ -1275,6 +1488,7 @@ int32_t h3lis100dl_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of d in reg INT1_DURATION
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1283,7 +1497,7 @@ int32_t h3lis100dl_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT1_DURATION,
- (uint8_t*)&int1_duration, 1);
+ (uint8_t *)&int1_duration, 1);
*val = int1_duration.d;
return ret;
@@ -1294,6 +1508,7 @@ int32_t h3lis100dl_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val enable sign and axis for interrupt on threshold
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_int2_on_threshold_conf_set(stmdev_ctx_t *ctx,
@@ -1303,8 +1518,10 @@ int32_t h3lis100dl_int2_on_threshold_conf_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT2_CFG,
- (uint8_t*)&int2_cfg, 1);
- if(ret == 0) {
+ (uint8_t *)&int2_cfg, 1);
+
+ if (ret == 0)
+ {
int2_cfg.xlie = val.int2_xlie;
int2_cfg.xhie = val.int2_xhie;
int2_cfg.ylie = val.int2_ylie;
@@ -1312,8 +1529,9 @@ int32_t h3lis100dl_int2_on_threshold_conf_set(stmdev_ctx_t *ctx,
int2_cfg.zlie = val.int2_zlie;
int2_cfg.zhie = val.int2_zhie;
ret = h3lis100dl_write_reg(ctx, H3LIS100DL_INT2_CFG,
- (uint8_t*)&int2_cfg, 1);
+ (uint8_t *)&int2_cfg, 1);
}
+
return ret;
}
@@ -1322,6 +1540,7 @@ int32_t h3lis100dl_int2_on_threshold_conf_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val enable sign and axis for interrupt on threshold
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_int2_on_threshold_conf_get(stmdev_ctx_t *ctx,
@@ -1330,7 +1549,8 @@ int32_t h3lis100dl_int2_on_threshold_conf_get(stmdev_ctx_t *ctx,
h3lis100dl_int2_cfg_t int2_cfg;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT2_CFG, (uint8_t*)&int2_cfg, 1);
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT2_CFG,
+ (uint8_t *)&int2_cfg, 1);
val->int2_xlie = int2_cfg.xlie;
val->int2_xhie = int2_cfg.xhie;
val->int2_ylie = int2_cfg.ylie;
@@ -1346,20 +1566,25 @@ int32_t h3lis100dl_int2_on_threshold_conf_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of aoi in reg INT2_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_int2_on_threshold_mode_set(stmdev_ctx_t *ctx,
- h3lis100dl_int2_aoi_t val)
+ h3lis100dl_int2_aoi_t val)
{
h3lis100dl_int2_cfg_t int2_cfg;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT2_CFG, (uint8_t*)&int2_cfg, 1);
- if(ret == 0) {
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT2_CFG,
+ (uint8_t *)&int2_cfg, 1);
+
+ if (ret == 0)
+ {
int2_cfg.aoi = (uint8_t) val;
ret = h3lis100dl_write_reg(ctx, H3LIS100DL_INT2_CFG,
- (uint8_t*)&int2_cfg, 1);
+ (uint8_t *)&int2_cfg, 1);
}
+
return ret;
}
@@ -1368,24 +1593,28 @@ int32_t h3lis100dl_int2_on_threshold_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of aoi in reg INT2_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_int2_on_threshold_mode_get(stmdev_ctx_t *ctx,
- h3lis100dl_int2_aoi_t *val)
+ h3lis100dl_int2_aoi_t *val)
{
h3lis100dl_int2_cfg_t int2_cfg;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT2_CFG, (uint8_t*)&int2_cfg, 1);
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT2_CFG,
+ (uint8_t *)&int2_cfg, 1);
- switch ( int2_cfg.aoi )
+ switch (int2_cfg.aoi)
{
case H3LIS100DL_INT2_ON_THRESHOLD_OR:
*val = H3LIS100DL_INT2_ON_THRESHOLD_OR;
break;
+
case H3LIS100DL_INT2_ON_THRESHOLD_AND:
*val = H3LIS100DL_INT2_ON_THRESHOLD_AND;
break;
+
default:
*val = H3LIS100DL_INT2_ON_THRESHOLD_OR;
break;
@@ -1399,13 +1628,16 @@ int32_t h3lis100dl_int2_on_threshold_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val registers INT2_SRC
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_int2_src_get(stmdev_ctx_t *ctx,
- h3lis100dl_int2_src_t *val)
+ h3lis100dl_int2_src_t *val)
{
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT2_SRC, (uint8_t*) val, 1);
+
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT2_SRC, (uint8_t *) val, 1);
+
return ret;
}
@@ -1414,6 +1646,7 @@ int32_t h3lis100dl_int2_src_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ths in reg INT2_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1421,12 +1654,16 @@ int32_t h3lis100dl_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
h3lis100dl_int2_ths_t int2_ths;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT2_THS, (uint8_t*)&int2_ths, 1);
- if(ret == 0) {
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT2_THS,
+ (uint8_t *)&int2_ths, 1);
+
+ if (ret == 0)
+ {
int2_ths.ths = val;
ret = h3lis100dl_write_reg(ctx, H3LIS100DL_INT2_THS,
- (uint8_t*)&int2_ths, 1);
+ (uint8_t *)&int2_ths, 1);
}
+
return ret;
}
@@ -1435,6 +1672,7 @@ int32_t h3lis100dl_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ths in reg INT2_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1442,7 +1680,8 @@ int32_t h3lis100dl_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
h3lis100dl_int2_ths_t int2_ths;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT2_THS, (uint8_t*)&int2_ths, 1);
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT2_THS,
+ (uint8_t *)&int2_ths, 1);
*val = int2_ths.ths;
return ret;
@@ -1453,6 +1692,7 @@ int32_t h3lis100dl_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of d in reg INT2_DURATION
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1461,12 +1701,15 @@ int32_t h3lis100dl_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT2_DURATION,
- (uint8_t*)&int2_duration, 1);
- if(ret == 0) {
+ (uint8_t *)&int2_duration, 1);
+
+ if (ret == 0)
+ {
int2_duration.d = val;
ret = h3lis100dl_write_reg(ctx, H3LIS100DL_INT2_DURATION,
- (uint8_t*)&int2_duration, 1);
+ (uint8_t *)&int2_duration, 1);
}
+
return ret;
}
@@ -1475,6 +1718,7 @@ int32_t h3lis100dl_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of d in reg INT2_DURATION
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1483,7 +1727,7 @@ int32_t h3lis100dl_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT2_DURATION,
- (uint8_t*)&int2_duration, 1);
+ (uint8_t *)&int2_duration, 1);
*val = int2_duration.d;
return ret;
@@ -1507,6 +1751,7 @@ int32_t h3lis100dl_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of turnon in reg CTRL_REG5
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1514,12 +1759,16 @@ int32_t h3lis100dl_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val)
h3lis100dl_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if(ret == 0) {
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.turnon = val;
ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG5,
- (uint8_t*)&ctrl_reg5, 1);
+ (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -1528,6 +1777,7 @@ int32_t h3lis100dl_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of turnon in reg CTRL_REG5
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis100dl_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1535,7 +1785,8 @@ int32_t h3lis100dl_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val)
h3lis100dl_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
*val = ctrl_reg5.turnon;
return ret;
diff --git a/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.h b/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.h
index 826938e34cbd6ec2aff7082c5263ec545ff74ac9..6a6249d28933f1b15f77cfc6f261beac610bf982 100644
--- a/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.h
+++ b/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file h3lis100dl_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * h3lis100dl_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file h3lis100dl_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * h3lis100dl_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef H3LIS100DL_REGS_H
#define H3LIS100DL_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup H3LIS100DL
@@ -74,7 +75,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -107,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -131,7 +134,7 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
+ * You can create a sensor configuration by your own or using
* Unico / Unicleo tools available on STMicroelectronics
* web site.
*
@@ -139,7 +142,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -176,7 +180,8 @@ typedef struct {
#define H3LIS100DL_WHO_AM_I 0x0FU
#define H3LIS100DL_CTRL_REG1 0x20U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xen : 1;
uint8_t yen : 1;
@@ -193,7 +198,8 @@ typedef struct {
} h3lis100dl_ctrl_reg1_t;
#define H3LIS100DL_CTRL_REG2 0x21U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t hpcf : 2;
uint8_t hpen : 2;
@@ -210,7 +216,8 @@ typedef struct {
} h3lis100dl_ctrl_reg2_t;
#define H3LIS100DL_CTRL_REG3 0x22U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t i1_cfg : 2;
uint8_t lir1 : 1;
@@ -229,7 +236,8 @@ typedef struct {
} h3lis100dl_ctrl_reg3_t;
#define H3LIS100DL_CTRL_REG4 0x23U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t not_used_01 : 6;
@@ -240,7 +248,8 @@ typedef struct {
} h3lis100dl_ctrl_reg4_t;
#define H3LIS100DL_CTRL_REG5 0x24U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t turnon : 2;
uint8_t not_used_01 : 6;
@@ -253,7 +262,8 @@ typedef struct {
#define H3LIS100DL_HP_FILTER_RESET 0x25U
#define H3LIS100DL_REFERENCE 0x26U
#define H3LIS100DL_STATUS_REG 0x27U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xda : 1;
uint8_t yda : 1;
@@ -279,7 +289,8 @@ typedef struct {
#define H3LIS100DL_OUT_Y 0x2BU
#define H3LIS100DL_OUT_Z 0x2DU
#define H3LIS100DL_INT1_CFG 0x30U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlie : 1;
uint8_t xhie : 1;
@@ -302,7 +313,8 @@ typedef struct {
} h3lis100dl_int1_cfg_t;
#define H3LIS100DL_INT1_SRC 0x31U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
@@ -325,7 +337,8 @@ typedef struct {
} h3lis100dl_int1_src_t;
#define H3LIS100DL_INT1_THS 0x32U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t not_used_01 : 1;
@@ -336,7 +349,8 @@ typedef struct {
} h3lis100dl_int1_ths_t;
#define H3LIS100DL_INT1_DURATION 0x33U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d : 7;
uint8_t not_used_01 : 1;
@@ -347,7 +361,8 @@ typedef struct {
} h3lis100dl_int1_duration_t;
#define H3LIS100DL_INT2_CFG 0x34U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlie : 1;
uint8_t xhie : 1;
@@ -370,7 +385,8 @@ typedef struct {
} h3lis100dl_int2_cfg_t;
#define H3LIS100DL_INT2_SRC 0x35U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
@@ -393,7 +409,8 @@ typedef struct {
} h3lis100dl_int2_src_t;
#define H3LIS100DL_INT2_THS 0x36U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t not_used_01 : 1;
@@ -404,7 +421,8 @@ typedef struct {
} h3lis100dl_int2_ths_t;
#define H3LIS100DL_INT2_DURATION 0x37U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d : 7;
uint8_t not_used_01 : 1;
@@ -416,9 +434,9 @@ typedef struct {
/**
* @defgroup H3LIS100DL_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -426,7 +444,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
h3lis100dl_ctrl_reg1_t ctrl_reg1;
h3lis100dl_ctrl_reg2_t ctrl_reg2;
h3lis100dl_ctrl_reg3_t ctrl_reg3;
@@ -450,10 +469,12 @@ typedef union{
*
*/
-int32_t h3lis100dl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
- uint16_t len);
-int32_t h3lis100dl_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t h3lis100dl_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
+int32_t h3lis100dl_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len);
float_t h3lis100dl_from_fs100g_to_mg(int8_t lsb);
@@ -466,7 +487,8 @@ int32_t h3lis100dl_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t h3lis100dl_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t h3lis100dl_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
H3LIS100DL_ODR_OFF = 0x00,
H3LIS100DL_ODR_Hz5 = 0x02,
H3LIS100DL_ODR_1Hz = 0x03,
@@ -477,43 +499,49 @@ typedef enum {
H3LIS100DL_ODR_100Hz = 0x11,
H3LIS100DL_ODR_400Hz = 0x21,
} h3lis100dl_dr_t;
-int32_t h3lis100dl_data_rate_set(stmdev_ctx_t *ctx, h3lis100dl_dr_t val);
-int32_t h3lis100dl_data_rate_get(stmdev_ctx_t *ctx, h3lis100dl_dr_t *val);
+int32_t h3lis100dl_data_rate_set(stmdev_ctx_t *ctx,
+ h3lis100dl_dr_t val);
+int32_t h3lis100dl_data_rate_get(stmdev_ctx_t *ctx,
+ h3lis100dl_dr_t *val);
-typedef enum {
+typedef enum
+{
H3LIS100DL_NORMAL_MODE = 0,
H3LIS100DL_REF_MODE_ENABLE = 1,
} h3lis100dl_hpm_t;
int32_t h3lis100dl_reference_mode_set(stmdev_ctx_t *ctx,
- h3lis100dl_hpm_t val);
+ h3lis100dl_hpm_t val);
int32_t h3lis100dl_reference_mode_get(stmdev_ctx_t *ctx,
- h3lis100dl_hpm_t *val);
+ h3lis100dl_hpm_t *val);
int32_t h3lis100dl_status_reg_get(stmdev_ctx_t *ctx,
- h3lis100dl_status_reg_t *val);
+ h3lis100dl_status_reg_t *val);
int32_t h3lis100dl_flag_data_ready_get(stmdev_ctx_t *ctx,
- uint8_t *val);
+ uint8_t *val);
-int32_t h3lis100dl_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t h3lis100dl_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
int32_t h3lis100dl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t h3lis100dl_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t h3lis100dl_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
H3LIS100DL_CUT_OFF_8Hz = 0,
H3LIS100DL_CUT_OFF_16Hz = 1,
H3LIS100DL_CUT_OFF_32Hz = 2,
H3LIS100DL_CUT_OFF_64Hz = 3,
} h3lis100dl_hpcf_t;
int32_t h3lis100dl_hp_bandwidth_set(stmdev_ctx_t *ctx,
- h3lis100dl_hpcf_t val);
+ h3lis100dl_hpcf_t val);
int32_t h3lis100dl_hp_bandwidth_get(stmdev_ctx_t *ctx,
- h3lis100dl_hpcf_t *val);
+ h3lis100dl_hpcf_t *val);
-typedef enum {
+typedef enum
+{
H3LIS100DL_HP_DISABLE = 0,
H3LIS100DL_HP_ON_OUT = 4,
H3LIS100DL_HP_ON_INT1 = 1,
@@ -523,78 +551,94 @@ typedef enum {
H3LIS100DL_HP_ON_INT2_OUT = 6,
H3LIS100DL_HP_ON_INT1_OUT = 5,
} h3lis100dl_hpen_t;
-int32_t h3lis100dl_hp_path_set(stmdev_ctx_t *ctx, h3lis100dl_hpen_t val);
-int32_t h3lis100dl_hp_path_get(stmdev_ctx_t *ctx, h3lis100dl_hpen_t *val);
+int32_t h3lis100dl_hp_path_set(stmdev_ctx_t *ctx,
+ h3lis100dl_hpen_t val);
+int32_t h3lis100dl_hp_path_get(stmdev_ctx_t *ctx,
+ h3lis100dl_hpen_t *val);
int32_t h3lis100dl_hp_reset_get(stmdev_ctx_t *ctx);
-int32_t h3lis100dl_hp_reference_value_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t h3lis100dl_hp_reference_value_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t h3lis100dl_hp_reference_value_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t h3lis100dl_hp_reference_value_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
H3LIS100DL_SPI_4_WIRE = 0,
H3LIS100DL_SPI_3_WIRE = 1,
} h3lis100dl_sim_t;
-int32_t h3lis100dl_spi_mode_set(stmdev_ctx_t *ctx, h3lis100dl_sim_t val);
-int32_t h3lis100dl_spi_mode_get(stmdev_ctx_t *ctx, h3lis100dl_sim_t *val);
+int32_t h3lis100dl_spi_mode_set(stmdev_ctx_t *ctx,
+ h3lis100dl_sim_t val);
+int32_t h3lis100dl_spi_mode_get(stmdev_ctx_t *ctx,
+ h3lis100dl_sim_t *val);
-typedef enum {
+typedef enum
+{
H3LIS100DL_PAD1_INT1_SRC = 0,
H3LIS100DL_PAD1_INT1_OR_INT2_SRC = 1,
H3LIS100DL_PAD1_DRDY = 2,
H3LIS100DL_PAD1_BOOT = 3,
} h3lis100dl_i1_cfg_t;
int32_t h3lis100dl_pin_int1_route_set(stmdev_ctx_t *ctx,
- h3lis100dl_i1_cfg_t val);
+ h3lis100dl_i1_cfg_t val);
int32_t h3lis100dl_pin_int1_route_get(stmdev_ctx_t *ctx,
- h3lis100dl_i1_cfg_t *val);
+ h3lis100dl_i1_cfg_t *val);
-typedef enum {
+typedef enum
+{
H3LIS100DL_INT1_PULSED = 0,
H3LIS100DL_INT1_LATCHED = 1,
} h3lis100dl_lir1_t;
int32_t h3lis100dl_int1_notification_set(stmdev_ctx_t *ctx,
- h3lis100dl_lir1_t val);
+ h3lis100dl_lir1_t val);
int32_t h3lis100dl_int1_notification_get(stmdev_ctx_t *ctx,
- h3lis100dl_lir1_t *val);
+ h3lis100dl_lir1_t *val);
-typedef enum {
+typedef enum
+{
H3LIS100DL_PAD2_INT2_SRC = 0,
H3LIS100DL_PAD2_INT1_OR_INT2_SRC = 1,
H3LIS100DL_PAD2_DRDY = 2,
H3LIS100DL_PAD2_BOOT = 3,
} h3lis100dl_i2_cfg_t;
int32_t h3lis100dl_pin_int2_route_set(stmdev_ctx_t *ctx,
- h3lis100dl_i2_cfg_t val);
+ h3lis100dl_i2_cfg_t val);
int32_t h3lis100dl_pin_int2_route_get(stmdev_ctx_t *ctx,
- h3lis100dl_i2_cfg_t *val);
+ h3lis100dl_i2_cfg_t *val);
-typedef enum {
+typedef enum
+{
H3LIS100DL_INT2_PULSED = 0,
H3LIS100DL_INT2_LATCHED = 1,
} h3lis100dl_lir2_t;
int32_t h3lis100dl_int2_notification_set(stmdev_ctx_t *ctx,
- h3lis100dl_lir2_t val);
+ h3lis100dl_lir2_t val);
int32_t h3lis100dl_int2_notification_get(stmdev_ctx_t *ctx,
- h3lis100dl_lir2_t *val);
+ h3lis100dl_lir2_t *val);
-typedef enum {
+typedef enum
+{
H3LIS100DL_PUSH_PULL = 0,
H3LIS100DL_OPEN_DRAIN = 1,
} h3lis100dl_pp_od_t;
-int32_t h3lis100dl_pin_mode_set(stmdev_ctx_t *ctx, h3lis100dl_pp_od_t val);
-int32_t h3lis100dl_pin_mode_get(stmdev_ctx_t *ctx, h3lis100dl_pp_od_t *val);
+int32_t h3lis100dl_pin_mode_set(stmdev_ctx_t *ctx,
+ h3lis100dl_pp_od_t val);
+int32_t h3lis100dl_pin_mode_get(stmdev_ctx_t *ctx,
+ h3lis100dl_pp_od_t *val);
-typedef enum {
+typedef enum
+{
H3LIS100DL_ACTIVE_HIGH = 0,
H3LIS100DL_ACTIVE_LOW = 1,
} h3lis100dl_ihl_t;
int32_t h3lis100dl_pin_polarity_set(stmdev_ctx_t *ctx,
- h3lis100dl_ihl_t val);
+ h3lis100dl_ihl_t val);
int32_t h3lis100dl_pin_polarity_get(stmdev_ctx_t *ctx,
- h3lis100dl_ihl_t *val);
+ h3lis100dl_ihl_t *val);
-typedef struct {
+typedef struct
+{
uint8_t int1_xlie : 1;
uint8_t int1_xhie : 1;
uint8_t int1_ylie : 1;
@@ -603,21 +647,22 @@ typedef struct {
uint8_t int1_zhie : 1;
} int1_on_th_conf_t;
int32_t h3lis100dl_int1_on_threshold_conf_set(stmdev_ctx_t *ctx,
- int1_on_th_conf_t val);
+ int1_on_th_conf_t val);
int32_t h3lis100dl_int1_on_threshold_conf_get(stmdev_ctx_t *ctx,
- int1_on_th_conf_t *val);
+ int1_on_th_conf_t *val);
-typedef enum {
+typedef enum
+{
H3LIS100DL_INT1_ON_THRESHOLD_OR = 0,
H3LIS100DL_INT1_ON_THRESHOLD_AND = 1,
} h3lis100dl_int1_aoi_t;
int32_t h3lis100dl_int1_on_threshold_mode_set(stmdev_ctx_t *ctx,
- h3lis100dl_int1_aoi_t val);
+ h3lis100dl_int1_aoi_t val);
int32_t h3lis100dl_int1_on_threshold_mode_get(stmdev_ctx_t *ctx,
- h3lis100dl_int1_aoi_t *val);
+ h3lis100dl_int1_aoi_t *val);
int32_t h3lis100dl_int1_src_get(stmdev_ctx_t *ctx,
- h3lis100dl_int1_src_t *val);
+ h3lis100dl_int1_src_t *val);
int32_t h3lis100dl_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t h3lis100dl_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -625,7 +670,8 @@ int32_t h3lis100dl_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t h3lis100dl_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t h3lis100dl_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef struct {
+typedef struct
+{
uint8_t int2_xlie : 1;
uint8_t int2_xhie : 1;
uint8_t int2_ylie : 1;
@@ -634,21 +680,22 @@ typedef struct {
uint8_t int2_zhie : 1;
} int2_on_th_conf_t;
int32_t h3lis100dl_int2_on_threshold_conf_set(stmdev_ctx_t *ctx,
- int2_on_th_conf_t val);
+ int2_on_th_conf_t val);
int32_t h3lis100dl_int2_on_threshold_conf_get(stmdev_ctx_t *ctx,
- int2_on_th_conf_t *val);
+ int2_on_th_conf_t *val);
-typedef enum {
+typedef enum
+{
H3LIS100DL_INT2_ON_THRESHOLD_OR = 0,
H3LIS100DL_INT2_ON_THRESHOLD_AND = 1,
} h3lis100dl_int2_aoi_t;
int32_t h3lis100dl_int2_on_threshold_mode_set(stmdev_ctx_t *ctx,
- h3lis100dl_int2_aoi_t val);
+ h3lis100dl_int2_aoi_t val);
int32_t h3lis100dl_int2_on_threshold_mode_get(stmdev_ctx_t *ctx,
- h3lis100dl_int2_aoi_t *val);
+ h3lis100dl_int2_aoi_t *val);
int32_t h3lis100dl_int2_src_get(stmdev_ctx_t *ctx,
- h3lis100dl_int2_src_t *val);
+ h3lis100dl_int2_src_t *val);
int32_t h3lis100dl_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t h3lis100dl_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val);
diff --git a/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.c b/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.c
index f39f006001a127abec043ff991a0783a94b10172..f23b05225702f89ba2c8f59e9dbf896c37db4aec 100644
--- a/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.c
+++ b/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file h3lis331dl_reg.c
- * @author Sensors Software Solution Team
- * @brief H3LIS331DL driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file h3lis331dl_reg.c
+ * @author Sensors Software Solution Team
+ * @brief H3LIS331DL driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "h3lis331dl_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis331dl_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t h3lis331dl_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t h3lis331dl_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis331dl_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t h3lis331dl_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -77,7 +83,7 @@ int32_t h3lis331dl_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
*
*/
- /**
+/**
* @defgroup H3LIS331DL_Sensitivity
* @brief These functions convert raw-data into engineering units.
* @{
@@ -117,6 +123,7 @@ float_t h3lis331dl_from_fs400_to_mg(int16_t lsb)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of xen in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -125,12 +132,15 @@ int32_t h3lis331dl_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0) {
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.xen = val;
ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -139,6 +149,7 @@ int32_t h3lis331dl_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of xen in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -147,7 +158,7 @@ int32_t h3lis331dl_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
*val = ctrl_reg1.xen;
return ret;
@@ -158,6 +169,7 @@ int32_t h3lis331dl_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of yen in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -166,12 +178,15 @@ int32_t h3lis331dl_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0) {
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.yen = val;
ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -180,6 +195,7 @@ int32_t h3lis331dl_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of yen in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -188,7 +204,7 @@ int32_t h3lis331dl_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
*val = ctrl_reg1.yen;
return ret;
@@ -199,6 +215,7 @@ int32_t h3lis331dl_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of zen in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -207,12 +224,15 @@ int32_t h3lis331dl_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0) {
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.zen = val;
ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -221,6 +241,7 @@ int32_t h3lis331dl_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of zen in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -229,7 +250,7 @@ int32_t h3lis331dl_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
*val = ctrl_reg1.zen;
return ret;
@@ -240,21 +261,26 @@ int32_t h3lis331dl_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of dr in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis331dl_data_rate_set(stmdev_ctx_t *ctx, h3lis331dl_dr_t val)
+int32_t h3lis331dl_data_rate_set(stmdev_ctx_t *ctx,
+ h3lis331dl_dr_t val)
{
h3lis331dl_ctrl_reg1_t ctrl_reg1;
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0) {
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.pm = (uint8_t)val & 0x07U;
- ctrl_reg1.dr = ( (uint8_t)val & 0x30U ) >> 4;
+ ctrl_reg1.dr = ((uint8_t)val & 0x30U) >> 4;
ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -263,48 +289,60 @@ int32_t h3lis331dl_data_rate_set(stmdev_ctx_t *ctx, h3lis331dl_dr_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of dr in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis331dl_data_rate_get(stmdev_ctx_t *ctx, h3lis331dl_dr_t *val)
+int32_t h3lis331dl_data_rate_get(stmdev_ctx_t *ctx,
+ h3lis331dl_dr_t *val)
{
h3lis331dl_ctrl_reg1_t ctrl_reg1;
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pm)
{
case H3LIS331DL_ODR_OFF:
*val = H3LIS331DL_ODR_OFF;
break;
+
case H3LIS331DL_ODR_Hz5:
*val = H3LIS331DL_ODR_Hz5;
break;
+
case H3LIS331DL_ODR_1Hz:
*val = H3LIS331DL_ODR_1Hz;
break;
+
case H3LIS331DL_ODR_5Hz2:
*val = H3LIS331DL_ODR_5Hz2;
break;
+
case H3LIS331DL_ODR_5Hz:
*val = H3LIS331DL_ODR_5Hz;
break;
+
case H3LIS331DL_ODR_10Hz:
*val = H3LIS331DL_ODR_10Hz;
break;
+
case H3LIS331DL_ODR_50Hz:
*val = H3LIS331DL_ODR_50Hz;
break;
+
case H3LIS331DL_ODR_100Hz:
*val = H3LIS331DL_ODR_100Hz;
break;
+
case H3LIS331DL_ODR_400Hz:
*val = H3LIS331DL_ODR_400Hz;
break;
+
case H3LIS331DL_ODR_1kHz:
*val = H3LIS331DL_ODR_1kHz;
break;
+
default:
*val = H3LIS331DL_ODR_OFF;
break;
@@ -318,21 +356,25 @@ int32_t h3lis331dl_data_rate_get(stmdev_ctx_t *ctx, h3lis331dl_dr_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of hpm in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_reference_mode_set(stmdev_ctx_t *ctx,
- h3lis331dl_hpm_t val)
+ h3lis331dl_hpm_t val)
{
h3lis331dl_ctrl_reg2_t ctrl_reg2;
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0) {
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpm = (uint8_t)val;
ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -341,29 +383,33 @@ int32_t h3lis331dl_reference_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of hpm in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_reference_mode_get(stmdev_ctx_t *ctx,
- h3lis331dl_hpm_t *val)
+ h3lis331dl_hpm_t *val)
{
h3lis331dl_ctrl_reg2_t ctrl_reg2;
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
switch (ctrl_reg2.hpm)
{
case H3LIS331DL_NORMAL_MODE:
*val = H3LIS331DL_NORMAL_MODE;
break;
+
case H3LIS331DL_REF_MODE_ENABLE:
*val = H3LIS331DL_REF_MODE_ENABLE;
break;
+
default:
*val = H3LIS331DL_NORMAL_MODE;
break;
}
+
return ret;
}
@@ -372,20 +418,25 @@ int32_t h3lis331dl_reference_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of fs in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis331dl_full_scale_set(stmdev_ctx_t *ctx, h3lis331dl_fs_t val)
+int32_t h3lis331dl_full_scale_set(stmdev_ctx_t *ctx,
+ h3lis331dl_fs_t val)
{
h3lis331dl_ctrl_reg4_t ctrl_reg4;
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0) {
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.fs = (uint8_t)val;
ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -394,27 +445,32 @@ int32_t h3lis331dl_full_scale_set(stmdev_ctx_t *ctx, h3lis331dl_fs_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of fs in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis331dl_full_scale_get(stmdev_ctx_t *ctx, h3lis331dl_fs_t *val)
+int32_t h3lis331dl_full_scale_get(stmdev_ctx_t *ctx,
+ h3lis331dl_fs_t *val)
{
h3lis331dl_ctrl_reg4_t ctrl_reg4;
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
switch (ctrl_reg4.fs)
{
case H3LIS331DL_100g:
*val = H3LIS331DL_100g;
break;
+
case H3LIS331DL_200g:
*val = H3LIS331DL_200g;
break;
+
case H3LIS331DL_400g:
*val = H3LIS331DL_400g;
break;
+
default:
*val = H3LIS331DL_100g;
break;
@@ -428,20 +484,25 @@ int32_t h3lis331dl_full_scale_get(stmdev_ctx_t *ctx, h3lis331dl_fs_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of bdu in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis331dl_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t h3lis331dl_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
h3lis331dl_ctrl_reg4_t ctrl_reg4;
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0) {
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.bdu = val;
ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -450,15 +511,17 @@ int32_t h3lis331dl_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of bdu in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis331dl_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t h3lis331dl_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
h3lis331dl_ctrl_reg4_t ctrl_reg4;
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
*val = ctrl_reg4.bdu;
return ret;
@@ -469,14 +532,17 @@ int32_t h3lis331dl_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val registers STATUS_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_status_reg_get(stmdev_ctx_t *ctx,
- h3lis331dl_status_reg_t *val)
+ h3lis331dl_status_reg_t *val)
{
int32_t ret;
+
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_STATUS_REG,
- (uint8_t*) val, 1);
+ (uint8_t *) val, 1);
+
return ret;
}
@@ -485,15 +551,17 @@ int32_t h3lis331dl_status_reg_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of zyxda in reg STATUS_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis331dl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t h3lis331dl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
h3lis331dl_status_reg_t status_reg;
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_STATUS_REG,
- (uint8_t*)&status_reg, 1);
+ (uint8_t *)&status_reg, 1);
*val = status_reg.zyxda;
return ret;
@@ -517,20 +585,23 @@ int32_t h3lis331dl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis331dl_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
+int32_t h3lis331dl_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
{
uint8_t buff[6];
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_OUT_X_L, buff, 6);
val[0] = (int16_t)buff[1];
- val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
- val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
val[2] = (int16_t)buff[5];
- val[2] = (val[2] * 256) + (int16_t)buff[4];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -551,12 +622,15 @@ int32_t h3lis331dl_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -565,6 +639,7 @@ int32_t h3lis331dl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of boot in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_boot_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -573,12 +648,15 @@ int32_t h3lis331dl_boot_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0) {
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.boot = val;
ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -587,6 +665,7 @@ int32_t h3lis331dl_boot_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of boot in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -595,7 +674,7 @@ int32_t h3lis331dl_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
*val = ctrl_reg2.boot;
return ret;
@@ -606,6 +685,7 @@ int32_t h3lis331dl_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ble in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_data_format_set(stmdev_ctx_t *ctx,
@@ -615,12 +695,15 @@ int32_t h3lis331dl_data_format_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0) {
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.ble = (uint8_t)val;
ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -629,6 +712,7 @@ int32_t h3lis331dl_data_format_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of ble in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_data_format_get(stmdev_ctx_t *ctx,
@@ -638,16 +722,18 @@ int32_t h3lis331dl_data_format_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
switch (ctrl_reg4.ble)
{
case H3LIS331DL_LSB_AT_LOW_ADD:
*val = H3LIS331DL_LSB_AT_LOW_ADD;
break;
+
case H3LIS331DL_MSB_AT_LOW_ADD:
*val = H3LIS331DL_MSB_AT_LOW_ADD;
break;
+
default:
*val = H3LIS331DL_LSB_AT_LOW_ADD;
break;
@@ -674,6 +760,7 @@ int32_t h3lis331dl_data_format_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of hpcf in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_hp_bandwidth_set(stmdev_ctx_t *ctx,
@@ -683,12 +770,15 @@ int32_t h3lis331dl_hp_bandwidth_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0) {
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpcf = (uint8_t)val;
ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -697,31 +787,36 @@ int32_t h3lis331dl_hp_bandwidth_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of hpcf in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_hp_bandwidth_get(stmdev_ctx_t *ctx,
- h3lis331dl_hpcf_t *val)
+ h3lis331dl_hpcf_t *val)
{
h3lis331dl_ctrl_reg2_t ctrl_reg2;
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
switch (ctrl_reg2.hpcf)
{
case H3LIS331DL_CUT_OFF_8Hz:
*val = H3LIS331DL_CUT_OFF_8Hz;
break;
+
case H3LIS331DL_CUT_OFF_16Hz:
*val = H3LIS331DL_CUT_OFF_16Hz;
break;
+
case H3LIS331DL_CUT_OFF_32Hz:
*val = H3LIS331DL_CUT_OFF_32Hz;
break;
+
case H3LIS331DL_CUT_OFF_64Hz:
*val = H3LIS331DL_CUT_OFF_64Hz;
break;
+
default:
*val = H3LIS331DL_CUT_OFF_8Hz;
break;
@@ -735,21 +830,26 @@ int32_t h3lis331dl_hp_bandwidth_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of hpen in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis331dl_hp_path_set(stmdev_ctx_t *ctx, h3lis331dl_hpen_t val)
+int32_t h3lis331dl_hp_path_set(stmdev_ctx_t *ctx,
+ h3lis331dl_hpen_t val)
{
h3lis331dl_ctrl_reg2_t ctrl_reg2;
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0) {
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpen = (uint8_t)val & 0x03U;
ctrl_reg2.fds = ((uint8_t)val & 0x04U) >> 2;
ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -758,46 +858,57 @@ int32_t h3lis331dl_hp_path_set(stmdev_ctx_t *ctx, h3lis331dl_hpen_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of hpen in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis331dl_hp_path_get(stmdev_ctx_t *ctx, h3lis331dl_hpen_t *val)
+int32_t h3lis331dl_hp_path_get(stmdev_ctx_t *ctx,
+ h3lis331dl_hpen_t *val)
{
h3lis331dl_ctrl_reg2_t ctrl_reg2;
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
- switch ( (ctrl_reg2.fds << 2) + ctrl_reg2.hpen )
+ switch ((ctrl_reg2.fds << 2) + ctrl_reg2.hpen)
{
case H3LIS331DL_HP_DISABLE:
*val = H3LIS331DL_HP_DISABLE;
break;
+
case H3LIS331DL_HP_ON_OUT:
*val = H3LIS331DL_HP_ON_OUT;
break;
+
case H3LIS331DL_HP_ON_INT1:
*val = H3LIS331DL_HP_ON_INT1;
break;
+
case H3LIS331DL_HP_ON_INT2:
*val = H3LIS331DL_HP_ON_INT2;
break;
+
case H3LIS331DL_HP_ON_INT1_INT2:
*val = H3LIS331DL_HP_ON_INT1_INT2;
break;
+
case H3LIS331DL_HP_ON_INT1_INT2_OUT:
*val = H3LIS331DL_HP_ON_INT1_INT2_OUT;
break;
+
case H3LIS331DL_HP_ON_INT2_OUT:
*val = H3LIS331DL_HP_ON_INT2_OUT;
break;
+
case H3LIS331DL_HP_ON_INT1_OUT:
*val = H3LIS331DL_HP_ON_INT1_OUT;
break;
+
default:
*val = H3LIS331DL_HP_DISABLE;
break;
}
+
return ret;
}
@@ -810,14 +921,17 @@ int32_t h3lis331dl_hp_path_get(stmdev_ctx_t *ctx, h3lis331dl_hpen_t *val)
* filter.[get]
*
* @param ctx read / write interface definitions(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_hp_reset_get(stmdev_ctx_t *ctx)
{
uint8_t dummy;
int32_t ret;
+
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_HP_FILTER_RESET,
- (uint8_t*)&dummy, 1);
+ (uint8_t *)&dummy, 1);
+
return ret;
}
@@ -826,12 +940,16 @@ int32_t h3lis331dl_hp_reset_get(stmdev_ctx_t *ctx)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ref in reg REFERENCE
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis331dl_hp_reference_value_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t h3lis331dl_hp_reference_value_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
int32_t ret;
- ret = h3lis331dl_write_reg(ctx, H3LIS331DL_REFERENCE, (uint8_t*)&val, 1);
+
+ ret = h3lis331dl_write_reg(ctx, H3LIS331DL_REFERENCE, (uint8_t *)&val, 1);
+
return ret;
}
@@ -840,12 +958,16 @@ int32_t h3lis331dl_hp_reference_value_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ref in reg REFERENCE
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis331dl_hp_reference_value_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t h3lis331dl_hp_reference_value_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
int32_t ret;
+
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_REFERENCE, val, 1);
+
return ret;
}
@@ -867,20 +989,25 @@ int32_t h3lis331dl_hp_reference_value_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of sim in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis331dl_spi_mode_set(stmdev_ctx_t *ctx, h3lis331dl_sim_t val)
+int32_t h3lis331dl_spi_mode_set(stmdev_ctx_t *ctx,
+ h3lis331dl_sim_t val)
{
h3lis331dl_ctrl_reg4_t ctrl_reg4;
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0) {
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.sim = (uint8_t)val;
ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -889,24 +1016,28 @@ int32_t h3lis331dl_spi_mode_set(stmdev_ctx_t *ctx, h3lis331dl_sim_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of sim in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis331dl_spi_mode_get(stmdev_ctx_t *ctx, h3lis331dl_sim_t *val)
+int32_t h3lis331dl_spi_mode_get(stmdev_ctx_t *ctx,
+ h3lis331dl_sim_t *val)
{
h3lis331dl_ctrl_reg4_t ctrl_reg4;
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
- switch ( ctrl_reg4.sim )
+ switch (ctrl_reg4.sim)
{
case H3LIS331DL_SPI_4_WIRE:
*val = H3LIS331DL_SPI_4_WIRE;
break;
+
case H3LIS331DL_SPI_3_WIRE:
*val = H3LIS331DL_SPI_3_WIRE;
break;
+
default:
*val = H3LIS331DL_SPI_4_WIRE;
break;
@@ -933,21 +1064,25 @@ int32_t h3lis331dl_spi_mode_get(stmdev_ctx_t *ctx, h3lis331dl_sim_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of i1_cfg in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_pin_int1_route_set(stmdev_ctx_t *ctx,
- h3lis331dl_i1_cfg_t val)
+ h3lis331dl_i1_cfg_t val)
{
h3lis331dl_ctrl_reg3_t ctrl_reg3;
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.i1_cfg = (uint8_t)val;
ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -956,31 +1091,36 @@ int32_t h3lis331dl_pin_int1_route_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of i1_cfg in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_pin_int1_route_get(stmdev_ctx_t *ctx,
- h3lis331dl_i1_cfg_t *val)
+ h3lis331dl_i1_cfg_t *val)
{
h3lis331dl_ctrl_reg3_t ctrl_reg3;
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.i1_cfg )
+ switch (ctrl_reg3.i1_cfg)
{
case H3LIS331DL_PAD1_INT1_SRC:
*val = H3LIS331DL_PAD1_INT1_SRC;
break;
+
case H3LIS331DL_PAD1_INT1_OR_INT2_SRC:
*val = H3LIS331DL_PAD1_INT1_OR_INT2_SRC;
break;
+
case H3LIS331DL_PAD1_DRDY:
*val = H3LIS331DL_PAD1_DRDY;
break;
+
case H3LIS331DL_PAD1_BOOT:
*val = H3LIS331DL_PAD1_BOOT;
break;
+
default:
*val = H3LIS331DL_PAD1_INT1_SRC;
break;
@@ -995,21 +1135,25 @@ int32_t h3lis331dl_pin_int1_route_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of lir1 in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_int1_notification_set(stmdev_ctx_t *ctx,
- h3lis331dl_lir1_t val)
+ h3lis331dl_lir1_t val)
{
h3lis331dl_ctrl_reg3_t ctrl_reg3;
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.lir1 = (uint8_t)val;
ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1019,25 +1163,28 @@ int32_t h3lis331dl_int1_notification_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of lir1 in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_int1_notification_get(stmdev_ctx_t *ctx,
- h3lis331dl_lir1_t *val)
+ h3lis331dl_lir1_t *val)
{
h3lis331dl_ctrl_reg3_t ctrl_reg3;
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.lir1 )
+ switch (ctrl_reg3.lir1)
{
case H3LIS331DL_INT1_PULSED:
*val = H3LIS331DL_INT1_PULSED;
break;
+
case H3LIS331DL_INT1_LATCHED:
*val = H3LIS331DL_INT1_LATCHED;
break;
+
default:
*val = H3LIS331DL_INT1_PULSED;
break;
@@ -1051,21 +1198,25 @@ int32_t h3lis331dl_int1_notification_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of i2_cfg in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_pin_int2_route_set(stmdev_ctx_t *ctx,
- h3lis331dl_i2_cfg_t val)
+ h3lis331dl_i2_cfg_t val)
{
h3lis331dl_ctrl_reg3_t ctrl_reg3;
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.i2_cfg = (uint8_t)val;
ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1074,31 +1225,36 @@ int32_t h3lis331dl_pin_int2_route_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of i2_cfg in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_pin_int2_route_get(stmdev_ctx_t *ctx,
- h3lis331dl_i2_cfg_t *val)
+ h3lis331dl_i2_cfg_t *val)
{
h3lis331dl_ctrl_reg3_t ctrl_reg3;
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.i2_cfg )
+ switch (ctrl_reg3.i2_cfg)
{
case H3LIS331DL_PAD2_INT2_SRC:
*val = H3LIS331DL_PAD2_INT2_SRC;
break;
+
case H3LIS331DL_PAD2_INT1_OR_INT2_SRC:
*val = H3LIS331DL_PAD2_INT1_OR_INT2_SRC;
break;
+
case H3LIS331DL_PAD2_DRDY:
*val = H3LIS331DL_PAD2_DRDY;
break;
+
case H3LIS331DL_PAD2_BOOT:
*val = H3LIS331DL_PAD2_BOOT;
break;
+
default:
*val = H3LIS331DL_PAD2_INT2_SRC;
break;
@@ -1113,21 +1269,25 @@ int32_t h3lis331dl_pin_int2_route_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of lir2 in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_int2_notification_set(stmdev_ctx_t *ctx,
- h3lis331dl_lir2_t val)
+ h3lis331dl_lir2_t val)
{
h3lis331dl_ctrl_reg3_t ctrl_reg3;
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.lir2 = (uint8_t)val;
ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1137,25 +1297,28 @@ int32_t h3lis331dl_int2_notification_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of lir2 in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_int2_notification_get(stmdev_ctx_t *ctx,
- h3lis331dl_lir2_t *val)
+ h3lis331dl_lir2_t *val)
{
h3lis331dl_ctrl_reg3_t ctrl_reg3;
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.lir2 )
+ switch (ctrl_reg3.lir2)
{
case H3LIS331DL_INT2_PULSED:
*val = H3LIS331DL_INT2_PULSED;
break;
+
case H3LIS331DL_INT2_LATCHED:
*val = H3LIS331DL_INT2_LATCHED;
break;
+
default:
*val = H3LIS331DL_INT2_PULSED;
break;
@@ -1169,20 +1332,25 @@ int32_t h3lis331dl_int2_notification_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of pp_od in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis331dl_pin_mode_set(stmdev_ctx_t *ctx, h3lis331dl_pp_od_t val)
+int32_t h3lis331dl_pin_mode_set(stmdev_ctx_t *ctx,
+ h3lis331dl_pp_od_t val)
{
h3lis331dl_ctrl_reg3_t ctrl_reg3;
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.pp_od = (uint8_t)val;
ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1191,24 +1359,28 @@ int32_t h3lis331dl_pin_mode_set(stmdev_ctx_t *ctx, h3lis331dl_pp_od_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of pp_od in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t h3lis331dl_pin_mode_get(stmdev_ctx_t *ctx, h3lis331dl_pp_od_t *val)
+int32_t h3lis331dl_pin_mode_get(stmdev_ctx_t *ctx,
+ h3lis331dl_pp_od_t *val)
{
h3lis331dl_ctrl_reg3_t ctrl_reg3;
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.pp_od )
+ switch (ctrl_reg3.pp_od)
{
case H3LIS331DL_PUSH_PULL:
*val = H3LIS331DL_PUSH_PULL;
break;
+
case H3LIS331DL_OPEN_DRAIN:
*val = H3LIS331DL_OPEN_DRAIN;
break;
+
default:
*val = H3LIS331DL_PUSH_PULL;
break;
@@ -1222,6 +1394,7 @@ int32_t h3lis331dl_pin_mode_get(stmdev_ctx_t *ctx, h3lis331dl_pp_od_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ihl in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_pin_polarity_set(stmdev_ctx_t *ctx,
@@ -1231,12 +1404,15 @@ int32_t h3lis331dl_pin_polarity_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.ihl = (uint8_t)val;
ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1245,6 +1421,7 @@ int32_t h3lis331dl_pin_polarity_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of ihl in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_pin_polarity_get(stmdev_ctx_t *ctx,
@@ -1254,16 +1431,18 @@ int32_t h3lis331dl_pin_polarity_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.ihl )
+ switch (ctrl_reg3.ihl)
{
case H3LIS331DL_ACTIVE_HIGH:
*val = H3LIS331DL_ACTIVE_HIGH;
break;
+
case H3LIS331DL_ACTIVE_LOW:
*val = H3LIS331DL_ACTIVE_LOW;
break;
+
default:
*val = H3LIS331DL_ACTIVE_HIGH;
break;
@@ -1290,6 +1469,7 @@ int32_t h3lis331dl_pin_polarity_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val enable sign and axis for interrupt on threshold
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_int1_on_threshold_conf_set(stmdev_ctx_t *ctx,
@@ -1298,8 +1478,11 @@ int32_t h3lis331dl_int1_on_threshold_conf_set(stmdev_ctx_t *ctx,
h3lis331dl_int1_cfg_t int1_cfg;
int32_t ret;
- ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT1_CFG, (uint8_t*)&int1_cfg, 1);
- if(ret == 0) {
+ ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT1_CFG,
+ (uint8_t *)&int1_cfg, 1);
+
+ if (ret == 0)
+ {
int1_cfg.xlie = val.int1_xlie;
int1_cfg.xhie = val.int1_xhie;
int1_cfg.ylie = val.int1_ylie;
@@ -1307,8 +1490,9 @@ int32_t h3lis331dl_int1_on_threshold_conf_set(stmdev_ctx_t *ctx,
int1_cfg.zlie = val.int1_zlie;
int1_cfg.zhie = val.int1_zhie;
ret = h3lis331dl_write_reg(ctx, H3LIS331DL_INT1_CFG,
- (uint8_t*)&int1_cfg, 1);
+ (uint8_t *)&int1_cfg, 1);
}
+
return ret;
}
@@ -1317,15 +1501,17 @@ int32_t h3lis331dl_int1_on_threshold_conf_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val enable sign and axis for interrupt on threshold
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_int1_on_threshold_conf_get(stmdev_ctx_t *ctx,
- h3lis331dl_int1_on_th_conf_t *val)
+ h3lis331dl_int1_on_th_conf_t *val)
{
h3lis331dl_int1_cfg_t int1_cfg;
int32_t ret;
- ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT1_CFG, (uint8_t*)&int1_cfg, 1);
+ ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT1_CFG,
+ (uint8_t *)&int1_cfg, 1);
val->int1_xlie = int1_cfg.xlie;
val->int1_xhie = int1_cfg.xhie;
val->int1_ylie = int1_cfg.ylie;
@@ -1341,20 +1527,25 @@ int32_t h3lis331dl_int1_on_threshold_conf_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of aoi in reg INT1_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_int1_on_threshold_mode_set(stmdev_ctx_t *ctx,
- h3lis331dl_int1_aoi_t val)
+ h3lis331dl_int1_aoi_t val)
{
h3lis331dl_int1_cfg_t int1_cfg;
int32_t ret;
- ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT1_CFG, (uint8_t*)&int1_cfg, 1);
- if(ret == 0) {
+ ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT1_CFG,
+ (uint8_t *)&int1_cfg, 1);
+
+ if (ret == 0)
+ {
int1_cfg.aoi = (uint8_t) val;
ret = h3lis331dl_write_reg(ctx, H3LIS331DL_INT1_CFG,
- (uint8_t*)&int1_cfg, 1);
+ (uint8_t *)&int1_cfg, 1);
}
+
return ret;
}
@@ -1363,24 +1554,28 @@ int32_t h3lis331dl_int1_on_threshold_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of aoi in reg INT1_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_int1_on_threshold_mode_get(stmdev_ctx_t *ctx,
- h3lis331dl_int1_aoi_t *val)
+ h3lis331dl_int1_aoi_t *val)
{
h3lis331dl_int1_cfg_t int1_cfg;
int32_t ret;
- ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT1_CFG, (uint8_t*)&int1_cfg, 1);
+ ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT1_CFG,
+ (uint8_t *)&int1_cfg, 1);
- switch ( int1_cfg.aoi )
+ switch (int1_cfg.aoi)
{
case H3LIS331DL_INT1_ON_THRESHOLD_OR:
*val = H3LIS331DL_INT1_ON_THRESHOLD_OR;
break;
+
case H3LIS331DL_INT1_ON_THRESHOLD_AND:
*val = H3LIS331DL_INT1_ON_THRESHOLD_AND;
break;
+
default:
*val = H3LIS331DL_INT1_ON_THRESHOLD_OR;
break;
@@ -1394,13 +1589,16 @@ int32_t h3lis331dl_int1_on_threshold_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val registers INT1_SRC
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_int1_src_get(stmdev_ctx_t *ctx,
- h3lis331dl_int1_src_t *val)
+ h3lis331dl_int1_src_t *val)
{
int32_t ret;
- ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT1_SRC, (uint8_t*) val, 1);
+
+ ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT1_SRC, (uint8_t *) val, 1);
+
return ret;
}
@@ -1409,6 +1607,7 @@ int32_t h3lis331dl_int1_src_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ths in reg INT1_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1416,12 +1615,16 @@ int32_t h3lis331dl_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
h3lis331dl_int1_ths_t int1_ths;
int32_t ret;
- ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT1_THS, (uint8_t*)&int1_ths, 1);
- if(ret == 0) {
+ ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT1_THS,
+ (uint8_t *)&int1_ths, 1);
+
+ if (ret == 0)
+ {
int1_ths.ths = val;
ret = h3lis331dl_write_reg(ctx, H3LIS331DL_INT1_THS,
- (uint8_t*)&int1_ths, 1);
+ (uint8_t *)&int1_ths, 1);
}
+
return ret;
}
@@ -1430,6 +1633,7 @@ int32_t h3lis331dl_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ths in reg INT1_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1437,7 +1641,8 @@ int32_t h3lis331dl_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
h3lis331dl_int1_ths_t int1_ths;
int32_t ret;
- ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT1_THS, (uint8_t*)&int1_ths, 1);
+ ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT1_THS,
+ (uint8_t *)&int1_ths, 1);
*val = int1_ths.ths;
return ret;
@@ -1448,6 +1653,7 @@ int32_t h3lis331dl_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of d in reg INT1_DURATION
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1456,12 +1662,15 @@ int32_t h3lis331dl_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT1_DURATION,
- (uint8_t*)&int1_duration, 1);
- if(ret == 0) {
+ (uint8_t *)&int1_duration, 1);
+
+ if (ret == 0)
+ {
int1_duration.d = val;
ret = h3lis331dl_write_reg(ctx, H3LIS331DL_INT1_DURATION,
- (uint8_t*)&int1_duration, 1);
+ (uint8_t *)&int1_duration, 1);
}
+
return ret;
}
@@ -1470,6 +1679,7 @@ int32_t h3lis331dl_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of d in reg INT1_DURATION
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1478,7 +1688,7 @@ int32_t h3lis331dl_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT1_DURATION,
- (uint8_t*)&int1_duration, 1);
+ (uint8_t *)&int1_duration, 1);
*val = int1_duration.d;
return ret;
@@ -1489,6 +1699,7 @@ int32_t h3lis331dl_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val enable sign and axis for interrupt on threshold
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_int2_on_threshold_conf_set(stmdev_ctx_t *ctx,
@@ -1498,8 +1709,10 @@ int32_t h3lis331dl_int2_on_threshold_conf_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT2_CFG,
- (uint8_t*)&int2_cfg, 1);
- if(ret == 0) {
+ (uint8_t *)&int2_cfg, 1);
+
+ if (ret == 0)
+ {
int2_cfg.xlie = val.int2_xlie;
int2_cfg.xhie = val.int2_xhie;
int2_cfg.ylie = val.int2_ylie;
@@ -1507,8 +1720,9 @@ int32_t h3lis331dl_int2_on_threshold_conf_set(stmdev_ctx_t *ctx,
int2_cfg.zlie = val.int2_zlie;
int2_cfg.zhie = val.int2_zhie;
ret = h3lis331dl_write_reg(ctx, H3LIS331DL_INT2_CFG,
- (uint8_t*)&int2_cfg, 1);
+ (uint8_t *)&int2_cfg, 1);
}
+
return ret;
}
@@ -1517,6 +1731,7 @@ int32_t h3lis331dl_int2_on_threshold_conf_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val enable sign and axis for interrupt on threshold
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_int2_on_threshold_conf_get(stmdev_ctx_t *ctx,
@@ -1525,7 +1740,8 @@ int32_t h3lis331dl_int2_on_threshold_conf_get(stmdev_ctx_t *ctx,
h3lis331dl_int2_cfg_t int2_cfg;
int32_t ret;
- ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT2_CFG, (uint8_t*)&int2_cfg, 1);
+ ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT2_CFG,
+ (uint8_t *)&int2_cfg, 1);
val->int2_xlie = int2_cfg.xlie;
val->int2_xhie = int2_cfg.xhie;
val->int2_ylie = int2_cfg.ylie;
@@ -1541,20 +1757,25 @@ int32_t h3lis331dl_int2_on_threshold_conf_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of aoi in reg INT2_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_int2_on_threshold_mode_set(stmdev_ctx_t *ctx,
- h3lis331dl_int2_aoi_t val)
+ h3lis331dl_int2_aoi_t val)
{
h3lis331dl_int2_cfg_t int2_cfg;
int32_t ret;
- ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT2_CFG, (uint8_t*)&int2_cfg, 1);
- if(ret == 0) {
+ ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT2_CFG,
+ (uint8_t *)&int2_cfg, 1);
+
+ if (ret == 0)
+ {
int2_cfg.aoi = (uint8_t) val;
ret = h3lis331dl_write_reg(ctx, H3LIS331DL_INT2_CFG,
- (uint8_t*)&int2_cfg, 1);
+ (uint8_t *)&int2_cfg, 1);
}
+
return ret;
}
@@ -1563,24 +1784,28 @@ int32_t h3lis331dl_int2_on_threshold_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of aoi in reg INT2_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_int2_on_threshold_mode_get(stmdev_ctx_t *ctx,
- h3lis331dl_int2_aoi_t *val)
+ h3lis331dl_int2_aoi_t *val)
{
h3lis331dl_int2_cfg_t int2_cfg;
int32_t ret;
- ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT2_CFG, (uint8_t*)&int2_cfg, 1);
+ ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT2_CFG,
+ (uint8_t *)&int2_cfg, 1);
- switch ( int2_cfg.aoi )
+ switch (int2_cfg.aoi)
{
case H3LIS331DL_INT2_ON_THRESHOLD_OR:
*val = H3LIS331DL_INT2_ON_THRESHOLD_OR;
break;
+
case H3LIS331DL_INT2_ON_THRESHOLD_AND:
*val = H3LIS331DL_INT2_ON_THRESHOLD_AND;
break;
+
default:
*val = H3LIS331DL_INT2_ON_THRESHOLD_OR;
break;
@@ -1594,13 +1819,16 @@ int32_t h3lis331dl_int2_on_threshold_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val registers INT2_SRC
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_int2_src_get(stmdev_ctx_t *ctx,
- h3lis331dl_int2_src_t *val)
+ h3lis331dl_int2_src_t *val)
{
int32_t ret;
- ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT2_SRC, (uint8_t*) val, 1);
+
+ ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT2_SRC, (uint8_t *) val, 1);
+
return ret;
}
@@ -1609,6 +1837,7 @@ int32_t h3lis331dl_int2_src_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ths in reg INT2_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1616,12 +1845,16 @@ int32_t h3lis331dl_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
h3lis331dl_int2_ths_t int2_ths;
int32_t ret;
- ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT2_THS, (uint8_t*)&int2_ths, 1);
- if(ret == 0) {
+ ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT2_THS,
+ (uint8_t *)&int2_ths, 1);
+
+ if (ret == 0)
+ {
int2_ths.ths = val;
ret = h3lis331dl_write_reg(ctx, H3LIS331DL_INT2_THS,
- (uint8_t*)&int2_ths, 1);
+ (uint8_t *)&int2_ths, 1);
}
+
return ret;
}
@@ -1630,6 +1863,7 @@ int32_t h3lis331dl_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ths in reg INT2_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1637,7 +1871,8 @@ int32_t h3lis331dl_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
h3lis331dl_int2_ths_t int2_ths;
int32_t ret;
- ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT2_THS, (uint8_t*)&int2_ths, 1);
+ ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT2_THS,
+ (uint8_t *)&int2_ths, 1);
*val = int2_ths.ths;
return ret;
@@ -1648,6 +1883,7 @@ int32_t h3lis331dl_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of d in reg INT2_DURATION
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1656,12 +1892,15 @@ int32_t h3lis331dl_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT2_DURATION,
- (uint8_t*)&int2_duration, 1);
- if(ret == 0) {
+ (uint8_t *)&int2_duration, 1);
+
+ if (ret == 0)
+ {
int2_duration.d = val;
ret = h3lis331dl_write_reg(ctx, H3LIS331DL_INT2_DURATION,
- (uint8_t*)&int2_duration, 1);
+ (uint8_t *)&int2_duration, 1);
}
+
return ret;
}
@@ -1670,6 +1909,7 @@ int32_t h3lis331dl_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of d in reg INT2_DURATION
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1678,7 +1918,7 @@ int32_t h3lis331dl_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT2_DURATION,
- (uint8_t*)&int2_duration, 1);
+ (uint8_t *)&int2_duration, 1);
*val = int2_duration.d;
return ret;
@@ -1702,6 +1942,7 @@ int32_t h3lis331dl_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of turnon in reg CTRL_REG5
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1710,12 +1951,15 @@ int32_t h3lis331dl_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG5,
- (uint8_t*)&ctrl_reg5, 1);
- if(ret == 0) {
+ (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.turnon = val;
ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG5,
- (uint8_t*)&ctrl_reg5, 1);
+ (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -1724,6 +1968,7 @@ int32_t h3lis331dl_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of turnon in reg CTRL_REG5
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t h3lis331dl_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1732,7 +1977,7 @@ int32_t h3lis331dl_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG5,
- (uint8_t*)&ctrl_reg5, 1);
+ (uint8_t *)&ctrl_reg5, 1);
*val = ctrl_reg5.turnon;
return ret;
diff --git a/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.h b/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.h
index 849134b4ba996120a44c117e8dc6e144577aed8d..d47761538cbed9599b5f529f6ab1f7efa7f2878b 100644
--- a/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.h
+++ b/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.h
@@ -1,29 +1,29 @@
-/*
- ******************************************************************************
- * @file h3lis331dl_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * h3lis331dl_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file h3lis331dl_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * h3lis331dl_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef H3LIS331DL_REGS_H
#define H3LIS331DL_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -75,7 +75,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -108,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -132,7 +134,7 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
+ * You can create a sensor configuration by your own or using
* Unico / Unicleo tools available on STMicroelectronics
* web site.
*
@@ -140,7 +142,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -176,7 +179,8 @@ typedef struct {
#define H3LIS331DL_WHO_AM_I 0x0FU
#define H3LIS331DL_CTRL_REG1 0x20U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xen : 1;
uint8_t yen : 1;
@@ -193,7 +197,8 @@ typedef struct {
} h3lis331dl_ctrl_reg1_t;
#define H3LIS331DL_CTRL_REG2 0x21U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t hpcf : 2;
uint8_t hpen : 2;
@@ -210,7 +215,8 @@ typedef struct {
} h3lis331dl_ctrl_reg2_t;
#define H3LIS331DL_CTRL_REG3 0x22U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t i1_cfg : 2;
uint8_t lir1 : 1;
@@ -229,7 +235,8 @@ typedef struct {
} h3lis331dl_ctrl_reg3_t;
#define H3LIS331DL_CTRL_REG4 0x23U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t not_used_01 : 3;
@@ -246,7 +253,8 @@ typedef struct {
} h3lis331dl_ctrl_reg4_t;
#define H3LIS331DL_CTRL_REG5 0x24U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t turnon : 2;
uint8_t not_used_01 : 6;
@@ -259,7 +267,8 @@ typedef struct {
#define H3LIS331DL_HP_FILTER_RESET 0x25U
#define H3LIS331DL_REFERENCE 0x26U
#define H3LIS331DL_STATUS_REG 0x27U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xda : 1;
uint8_t yda : 1;
@@ -288,7 +297,8 @@ typedef struct {
#define H3LIS331DL_OUT_Z_L 0x2CU
#define H3LIS331DL_OUT_Z_H 0x2DU
#define H3LIS331DL_INT1_CFG 0x30U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlie : 1;
uint8_t xhie : 1;
@@ -311,7 +321,8 @@ typedef struct {
} h3lis331dl_int1_cfg_t;
#define H3LIS331DL_INT1_SRC 0x31U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
@@ -334,7 +345,8 @@ typedef struct {
} h3lis331dl_int1_src_t;
#define H3LIS331DL_INT1_THS 0x32U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t not_used_01 : 1;
@@ -345,7 +357,8 @@ typedef struct {
} h3lis331dl_int1_ths_t;
#define H3LIS331DL_INT1_DURATION 0x33U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d : 7;
uint8_t not_used_01 : 1;
@@ -356,7 +369,8 @@ typedef struct {
} h3lis331dl_int1_duration_t;
#define H3LIS331DL_INT2_CFG 0x34U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlie : 1;
uint8_t xhie : 1;
@@ -379,7 +393,8 @@ typedef struct {
} h3lis331dl_int2_cfg_t;
#define H3LIS331DL_INT2_SRC 0x35U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
@@ -402,7 +417,8 @@ typedef struct {
} h3lis331dl_int2_src_t;
#define H3LIS331DL_INT2_THS 0x36U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t not_used_01 : 1;
@@ -413,7 +429,8 @@ typedef struct {
} h3lis331dl_int2_ths_t;
#define H3LIS331DL_INT2_DURATION 0x37U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d : 7;
uint8_t not_used_01 : 1;
@@ -425,9 +442,9 @@ typedef struct {
/**
* @defgroup H3LIS331DL_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -435,7 +452,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
h3lis331dl_ctrl_reg1_t ctrl_reg1;
h3lis331dl_ctrl_reg2_t ctrl_reg2;
h3lis331dl_ctrl_reg3_t ctrl_reg3;
@@ -459,10 +477,12 @@ typedef union{
*
*/
-int32_t h3lis331dl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
- uint16_t len);
-int32_t h3lis331dl_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t h3lis331dl_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
+int32_t h3lis331dl_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len);
float_t h3lis331dl_from_fs100_to_mg(int16_t lsb);
float_t h3lis331dl_from_fs200_to_mg(int16_t lsb);
@@ -477,7 +497,8 @@ int32_t h3lis331dl_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t h3lis331dl_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t h3lis331dl_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
H3LIS331DL_ODR_OFF = 0x00,
H3LIS331DL_ODR_Hz5 = 0x02,
H3LIS331DL_ODR_1Hz = 0x03,
@@ -489,19 +510,23 @@ typedef enum {
H3LIS331DL_ODR_400Hz = 0x21,
H3LIS331DL_ODR_1kHz = 0x31,
} h3lis331dl_dr_t;
-int32_t h3lis331dl_data_rate_set(stmdev_ctx_t *ctx, h3lis331dl_dr_t val);
-int32_t h3lis331dl_data_rate_get(stmdev_ctx_t *ctx, h3lis331dl_dr_t *val);
+int32_t h3lis331dl_data_rate_set(stmdev_ctx_t *ctx,
+ h3lis331dl_dr_t val);
+int32_t h3lis331dl_data_rate_get(stmdev_ctx_t *ctx,
+ h3lis331dl_dr_t *val);
-typedef enum {
+typedef enum
+{
H3LIS331DL_NORMAL_MODE = 0,
H3LIS331DL_REF_MODE_ENABLE = 1,
} h3lis331dl_hpm_t;
int32_t h3lis331dl_reference_mode_set(stmdev_ctx_t *ctx,
- h3lis331dl_hpm_t val);
+ h3lis331dl_hpm_t val);
int32_t h3lis331dl_reference_mode_get(stmdev_ctx_t *ctx,
- h3lis331dl_hpm_t *val);
+ h3lis331dl_hpm_t *val);
-typedef enum {
+typedef enum
+{
H3LIS331DL_100g = 0,
H3LIS331DL_200g = 1,
H3LIS331DL_400g = 3,
@@ -511,23 +536,27 @@ int32_t h3lis331dl_full_scale_set(stmdev_ctx_t *ctx,
int32_t h3lis331dl_full_scale_get(stmdev_ctx_t *ctx,
h3lis331dl_fs_t *val);
-int32_t h3lis331dl_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t h3lis331dl_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t h3lis331dl_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t h3lis331dl_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t h3lis331dl_status_reg_get(stmdev_ctx_t *ctx,
- h3lis331dl_status_reg_t *val);
+ h3lis331dl_status_reg_t *val);
int32_t h3lis331dl_flag_data_ready_get(stmdev_ctx_t *ctx,
- uint8_t *val);
+ uint8_t *val);
-int32_t h3lis331dl_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t h3lis331dl_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
int32_t h3lis331dl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t h3lis331dl_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t h3lis331dl_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
H3LIS331DL_LSB_AT_LOW_ADD = 0,
H3LIS331DL_MSB_AT_LOW_ADD = 1,
} h3lis331dl_ble_t;
@@ -536,18 +565,20 @@ int32_t h3lis331dl_data_format_set(stmdev_ctx_t *ctx,
int32_t h3lis331dl_data_format_get(stmdev_ctx_t *ctx,
h3lis331dl_ble_t *val);
-typedef enum {
+typedef enum
+{
H3LIS331DL_CUT_OFF_8Hz = 0,
H3LIS331DL_CUT_OFF_16Hz = 1,
H3LIS331DL_CUT_OFF_32Hz = 2,
H3LIS331DL_CUT_OFF_64Hz = 3,
} h3lis331dl_hpcf_t;
int32_t h3lis331dl_hp_bandwidth_set(stmdev_ctx_t *ctx,
- h3lis331dl_hpcf_t val);
+ h3lis331dl_hpcf_t val);
int32_t h3lis331dl_hp_bandwidth_get(stmdev_ctx_t *ctx,
- h3lis331dl_hpcf_t *val);
+ h3lis331dl_hpcf_t *val);
-typedef enum {
+typedef enum
+{
H3LIS331DL_HP_DISABLE = 0,
H3LIS331DL_HP_ON_OUT = 4,
H3LIS331DL_HP_ON_INT1 = 1,
@@ -557,62 +588,74 @@ typedef enum {
H3LIS331DL_HP_ON_INT2_OUT = 6,
H3LIS331DL_HP_ON_INT1_OUT = 5,
} h3lis331dl_hpen_t;
-int32_t h3lis331dl_hp_path_set(stmdev_ctx_t *ctx, h3lis331dl_hpen_t val);
-int32_t h3lis331dl_hp_path_get(stmdev_ctx_t *ctx, h3lis331dl_hpen_t *val);
+int32_t h3lis331dl_hp_path_set(stmdev_ctx_t *ctx,
+ h3lis331dl_hpen_t val);
+int32_t h3lis331dl_hp_path_get(stmdev_ctx_t *ctx,
+ h3lis331dl_hpen_t *val);
int32_t h3lis331dl_hp_reset_get(stmdev_ctx_t *ctx);
-int32_t h3lis331dl_hp_reference_value_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t h3lis331dl_hp_reference_value_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t h3lis331dl_hp_reference_value_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t h3lis331dl_hp_reference_value_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
H3LIS331DL_SPI_4_WIRE = 0,
H3LIS331DL_SPI_3_WIRE = 1,
} h3lis331dl_sim_t;
-int32_t h3lis331dl_spi_mode_set(stmdev_ctx_t *ctx, h3lis331dl_sim_t val);
-int32_t h3lis331dl_spi_mode_get(stmdev_ctx_t *ctx, h3lis331dl_sim_t *val);
+int32_t h3lis331dl_spi_mode_set(stmdev_ctx_t *ctx,
+ h3lis331dl_sim_t val);
+int32_t h3lis331dl_spi_mode_get(stmdev_ctx_t *ctx,
+ h3lis331dl_sim_t *val);
-typedef enum {
+typedef enum
+{
H3LIS331DL_PAD1_INT1_SRC = 0,
H3LIS331DL_PAD1_INT1_OR_INT2_SRC = 1,
H3LIS331DL_PAD1_DRDY = 2,
H3LIS331DL_PAD1_BOOT = 3,
} h3lis331dl_i1_cfg_t;
int32_t h3lis331dl_pin_int1_route_set(stmdev_ctx_t *ctx,
- h3lis331dl_i1_cfg_t val);
+ h3lis331dl_i1_cfg_t val);
int32_t h3lis331dl_pin_int1_route_get(stmdev_ctx_t *ctx,
- h3lis331dl_i1_cfg_t *val);
+ h3lis331dl_i1_cfg_t *val);
-typedef enum {
+typedef enum
+{
H3LIS331DL_INT1_PULSED = 0,
H3LIS331DL_INT1_LATCHED = 1,
} h3lis331dl_lir1_t;
int32_t h3lis331dl_int1_notification_set(stmdev_ctx_t *ctx,
- h3lis331dl_lir1_t val);
+ h3lis331dl_lir1_t val);
int32_t h3lis331dl_int1_notification_get(stmdev_ctx_t *ctx,
- h3lis331dl_lir1_t *val);
+ h3lis331dl_lir1_t *val);
-typedef enum {
+typedef enum
+{
H3LIS331DL_PAD2_INT2_SRC = 0,
H3LIS331DL_PAD2_INT1_OR_INT2_SRC = 1,
H3LIS331DL_PAD2_DRDY = 2,
H3LIS331DL_PAD2_BOOT = 3,
} h3lis331dl_i2_cfg_t;
int32_t h3lis331dl_pin_int2_route_set(stmdev_ctx_t *ctx,
- h3lis331dl_i2_cfg_t val);
+ h3lis331dl_i2_cfg_t val);
int32_t h3lis331dl_pin_int2_route_get(stmdev_ctx_t *ctx,
- h3lis331dl_i2_cfg_t *val);
+ h3lis331dl_i2_cfg_t *val);
-typedef enum {
+typedef enum
+{
H3LIS331DL_INT2_PULSED = 0,
H3LIS331DL_INT2_LATCHED = 1,
} h3lis331dl_lir2_t;
int32_t h3lis331dl_int2_notification_set(stmdev_ctx_t *ctx,
- h3lis331dl_lir2_t val);
+ h3lis331dl_lir2_t val);
int32_t h3lis331dl_int2_notification_get(stmdev_ctx_t *ctx,
- h3lis331dl_lir2_t *val);
+ h3lis331dl_lir2_t *val);
-typedef enum {
+typedef enum
+{
H3LIS331DL_PUSH_PULL = 0,
H3LIS331DL_OPEN_DRAIN = 1,
} h3lis331dl_pp_od_t;
@@ -621,16 +664,18 @@ int32_t h3lis331dl_pin_mode_set(stmdev_ctx_t *ctx,
int32_t h3lis331dl_pin_mode_get(stmdev_ctx_t *ctx,
h3lis331dl_pp_od_t *val);
-typedef enum {
+typedef enum
+{
H3LIS331DL_ACTIVE_HIGH = 0,
H3LIS331DL_ACTIVE_LOW = 1,
} h3lis331dl_ihl_t;
int32_t h3lis331dl_pin_polarity_set(stmdev_ctx_t *ctx,
- h3lis331dl_ihl_t val);
+ h3lis331dl_ihl_t val);
int32_t h3lis331dl_pin_polarity_get(stmdev_ctx_t *ctx,
- h3lis331dl_ihl_t *val);
+ h3lis331dl_ihl_t *val);
-typedef struct {
+typedef struct
+{
uint8_t int1_xlie : 1;
uint8_t int1_xhie : 1;
uint8_t int1_ylie : 1;
@@ -639,21 +684,22 @@ typedef struct {
uint8_t int1_zhie : 1;
} h3lis331dl_int1_on_th_conf_t;
int32_t h3lis331dl_int1_on_threshold_conf_set(stmdev_ctx_t *ctx,
- h3lis331dl_int1_on_th_conf_t val);
+ h3lis331dl_int1_on_th_conf_t val);
int32_t h3lis331dl_int1_on_threshold_conf_get(stmdev_ctx_t *ctx,
- h3lis331dl_int1_on_th_conf_t *val);
+ h3lis331dl_int1_on_th_conf_t *val);
-typedef enum {
+typedef enum
+{
H3LIS331DL_INT1_ON_THRESHOLD_OR = 0,
H3LIS331DL_INT1_ON_THRESHOLD_AND = 1,
} h3lis331dl_int1_aoi_t;
int32_t h3lis331dl_int1_on_threshold_mode_set(stmdev_ctx_t *ctx,
- h3lis331dl_int1_aoi_t val);
+ h3lis331dl_int1_aoi_t val);
int32_t h3lis331dl_int1_on_threshold_mode_get(stmdev_ctx_t *ctx,
- h3lis331dl_int1_aoi_t *val);
+ h3lis331dl_int1_aoi_t *val);
int32_t h3lis331dl_int1_src_get(stmdev_ctx_t *ctx,
- h3lis331dl_int1_src_t *val);
+ h3lis331dl_int1_src_t *val);
int32_t h3lis331dl_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t h3lis331dl_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -661,7 +707,8 @@ int32_t h3lis331dl_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t h3lis331dl_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t h3lis331dl_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef struct {
+typedef struct
+{
uint8_t int2_xlie : 1;
uint8_t int2_xhie : 1;
uint8_t int2_ylie : 1;
@@ -670,21 +717,22 @@ typedef struct {
uint8_t int2_zhie : 1;
} h3lis331dl_int2_on_th_conf_t;
int32_t h3lis331dl_int2_on_threshold_conf_set(stmdev_ctx_t *ctx,
- h3lis331dl_int2_on_th_conf_t val);
+ h3lis331dl_int2_on_th_conf_t val);
int32_t h3lis331dl_int2_on_threshold_conf_get(stmdev_ctx_t *ctx,
- h3lis331dl_int2_on_th_conf_t *val);
+ h3lis331dl_int2_on_th_conf_t *val);
-typedef enum {
+typedef enum
+{
H3LIS331DL_INT2_ON_THRESHOLD_OR = 0,
H3LIS331DL_INT2_ON_THRESHOLD_AND = 1,
} h3lis331dl_int2_aoi_t;
int32_t h3lis331dl_int2_on_threshold_mode_set(stmdev_ctx_t *ctx,
- h3lis331dl_int2_aoi_t val);
+ h3lis331dl_int2_aoi_t val);
int32_t h3lis331dl_int2_on_threshold_mode_get(stmdev_ctx_t *ctx,
- h3lis331dl_int2_aoi_t *val);
+ h3lis331dl_int2_aoi_t *val);
int32_t h3lis331dl_int2_src_get(stmdev_ctx_t *ctx,
- h3lis331dl_int2_src_t *val);
+ h3lis331dl_int2_src_t *val);
int32_t h3lis331dl_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t h3lis331dl_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val);
diff --git a/sensor/stmemsc/hts221_STdC/driver/hts221_reg.c b/sensor/stmemsc/hts221_STdC/driver/hts221_reg.c
index e500e8139e9dbceecc9cc0cffe60aeac04c906c3..6981bf0f0d8799128b467fd8ea88f8cb671fa0d8 100644
--- a/sensor/stmemsc/hts221_STdC/driver/hts221_reg.c
+++ b/sensor/stmemsc/hts221_STdC/driver/hts221_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file hts221_reg.c
- * @author Sensors Software Solution Team
- * @brief HTS221 driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file hts221_reg.c
+ * @author Sensors Software Solution Team
+ * @brief HTS221 driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "hts221_reg.h"
@@ -45,11 +45,13 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t hts221_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t hts221_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -63,11 +65,14 @@ int32_t hts221_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t hts221_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t hts221_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -96,11 +101,12 @@ int32_t hts221_humidity_avg_set(stmdev_ctx_t *ctx, hts221_avgh_t val)
hts221_av_conf_t reg;
int32_t ret;
- ret = hts221_read_reg(ctx, HTS221_AV_CONF, (uint8_t*) ®, 1);
+ ret = hts221_read_reg(ctx, HTS221_AV_CONF, (uint8_t *) ®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.avgh = (uint8_t)val;
- ret = hts221_write_reg(ctx, HTS221_AV_CONF, (uint8_t*) ®, 1);
+ ret = hts221_write_reg(ctx, HTS221_AV_CONF, (uint8_t *) ®, 1);
}
return ret;
@@ -119,33 +125,42 @@ int32_t hts221_humidity_avg_get(stmdev_ctx_t *ctx, hts221_avgh_t *val)
hts221_av_conf_t reg;
int32_t ret;
- ret = hts221_read_reg(ctx, HTS221_AV_CONF, (uint8_t*) ®, 1);
+ ret = hts221_read_reg(ctx, HTS221_AV_CONF, (uint8_t *) ®, 1);
- switch (reg.avgh) {
+ switch (reg.avgh)
+ {
case HTS221_H_AVG_4:
*val = HTS221_H_AVG_4;
break;
+
case HTS221_H_AVG_8:
*val = HTS221_H_AVG_8;
break;
+
case HTS221_H_AVG_16:
*val = HTS221_H_AVG_16;
break;
+
case HTS221_H_AVG_32:
*val = HTS221_H_AVG_32;
break;
+
case HTS221_H_AVG_64:
*val = HTS221_H_AVG_64;
break;
+
case HTS221_H_AVG_128:
*val = HTS221_H_AVG_128;
break;
+
case HTS221_H_AVG_256:
*val = HTS221_H_AVG_256;
break;
+
case HTS221_H_AVG_512:
*val = HTS221_H_AVG_512;
break;
+
default:
*val = HTS221_H_AVG_ND;
break;
@@ -162,16 +177,18 @@ int32_t hts221_humidity_avg_get(stmdev_ctx_t *ctx, hts221_avgh_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t hts221_temperature_avg_set(stmdev_ctx_t *ctx, hts221_avgt_t val)
+int32_t hts221_temperature_avg_set(stmdev_ctx_t *ctx,
+ hts221_avgt_t val)
{
hts221_av_conf_t reg;
int32_t ret;
- ret = hts221_read_reg(ctx, HTS221_AV_CONF, (uint8_t*) ®, 1);
+ ret = hts221_read_reg(ctx, HTS221_AV_CONF, (uint8_t *) ®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.avgt = (uint8_t)val;
- ret = hts221_write_reg(ctx, HTS221_AV_CONF, (uint8_t*) ®, 1);
+ ret = hts221_write_reg(ctx, HTS221_AV_CONF, (uint8_t *) ®, 1);
}
return ret;
@@ -185,38 +202,48 @@ int32_t hts221_temperature_avg_set(stmdev_ctx_t *ctx, hts221_avgt_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t hts221_temperature_avg_get(stmdev_ctx_t *ctx, hts221_avgt_t *val)
+int32_t hts221_temperature_avg_get(stmdev_ctx_t *ctx,
+ hts221_avgt_t *val)
{
hts221_av_conf_t reg;
int32_t ret;
- ret = hts221_read_reg(ctx, HTS221_AV_CONF, (uint8_t*) ®, 1);
+ ret = hts221_read_reg(ctx, HTS221_AV_CONF, (uint8_t *) ®, 1);
- switch (reg.avgh) {
+ switch (reg.avgh)
+ {
case HTS221_T_AVG_2:
*val = HTS221_T_AVG_2;
break;
+
case HTS221_T_AVG_4:
*val = HTS221_T_AVG_4;
break;
+
case HTS221_T_AVG_8:
*val = HTS221_T_AVG_8;
break;
+
case HTS221_T_AVG_16:
*val = HTS221_T_AVG_16;
break;
+
case HTS221_T_AVG_32:
*val = HTS221_T_AVG_32;
break;
+
case HTS221_T_AVG_64:
*val = HTS221_T_AVG_64;
break;
+
case HTS221_T_AVG_128:
*val = HTS221_T_AVG_128;
break;
+
case HTS221_T_AVG_256:
*val = HTS221_T_AVG_256;
break;
+
default:
*val = HTS221_T_AVG_ND;
break;
@@ -238,11 +265,12 @@ int32_t hts221_data_rate_set(stmdev_ctx_t *ctx, hts221_odr_t val)
hts221_ctrl_reg1_t reg;
int32_t ret;
- ret = hts221_read_reg(ctx, HTS221_CTRL_REG1, (uint8_t*) ®, 1);
+ ret = hts221_read_reg(ctx, HTS221_CTRL_REG1, (uint8_t *) ®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.odr = (uint8_t)val;
- ret = hts221_write_reg(ctx, HTS221_CTRL_REG1, (uint8_t*) ®, 1);
+ ret = hts221_write_reg(ctx, HTS221_CTRL_REG1, (uint8_t *) ®, 1);
}
return ret;
@@ -261,21 +289,26 @@ int32_t hts221_data_rate_get(stmdev_ctx_t *ctx, hts221_odr_t *val)
hts221_ctrl_reg1_t reg;
int32_t ret;
- ret = hts221_read_reg(ctx, HTS221_CTRL_REG1, (uint8_t*) ®, 1);
+ ret = hts221_read_reg(ctx, HTS221_CTRL_REG1, (uint8_t *) ®, 1);
- switch (reg.odr) {
+ switch (reg.odr)
+ {
case HTS221_ONE_SHOT:
*val = HTS221_ONE_SHOT;
break;
+
case HTS221_ODR_1Hz:
*val = HTS221_ODR_1Hz;
break;
+
case HTS221_ODR_7Hz:
*val = HTS221_ODR_7Hz;
break;
+
case HTS221_ODR_12Hz5:
*val = HTS221_ODR_12Hz5;
break;
+
default:
*val = HTS221_ODR_ND;
break;
@@ -297,11 +330,12 @@ int32_t hts221_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
hts221_ctrl_reg1_t reg;
int32_t ret;
- ret = hts221_read_reg(ctx, HTS221_CTRL_REG1, (uint8_t*) ®, 1);
+ ret = hts221_read_reg(ctx, HTS221_CTRL_REG1, (uint8_t *) ®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.bdu = val;
- ret = hts221_write_reg(ctx, HTS221_CTRL_REG1, (uint8_t*) ®, 1);
+ ret = hts221_write_reg(ctx, HTS221_CTRL_REG1, (uint8_t *) ®, 1);
}
return ret;
@@ -320,7 +354,7 @@ int32_t hts221_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
hts221_ctrl_reg1_t reg;
int32_t ret;
- ret = hts221_read_reg(ctx, HTS221_CTRL_REG1, (uint8_t*) ®, 1);
+ ret = hts221_read_reg(ctx, HTS221_CTRL_REG1, (uint8_t *) ®, 1);
*val = reg.bdu;
return ret;
@@ -339,11 +373,12 @@ int32_t hts221_one_shoot_trigger_set(stmdev_ctx_t *ctx, uint8_t val)
hts221_ctrl_reg2_t reg;
int32_t ret;
- ret = hts221_read_reg(ctx, HTS221_CTRL_REG2, (uint8_t*) ®, 1);
+ ret = hts221_read_reg(ctx, HTS221_CTRL_REG2, (uint8_t *) ®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.one_shot = val;
- ret = hts221_write_reg(ctx, HTS221_CTRL_REG2, (uint8_t*) ®, 1);
+ ret = hts221_write_reg(ctx, HTS221_CTRL_REG2, (uint8_t *) ®, 1);
}
return ret;
@@ -362,7 +397,7 @@ int32_t hts221_one_shoot_trigger_get(stmdev_ctx_t *ctx, uint8_t *val)
hts221_ctrl_reg2_t reg;
int32_t ret;
- ret = hts221_read_reg(ctx, HTS221_CTRL_REG2, (uint8_t*) ®, 1);
+ ret = hts221_read_reg(ctx, HTS221_CTRL_REG2, (uint8_t *) ®, 1);
*val = reg.one_shot;
return ret;
@@ -381,7 +416,7 @@ int32_t hts221_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
hts221_status_reg_t reg;
int32_t ret;
- ret = hts221_read_reg(ctx, HTS221_STATUS_REG, (uint8_t*) ®, 1);
+ ret = hts221_read_reg(ctx, HTS221_STATUS_REG, (uint8_t *) ®, 1);
*val = reg.t_da;
return ret;
@@ -400,7 +435,7 @@ int32_t hts221_hum_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
hts221_status_reg_t reg;
int32_t ret;
- ret = hts221_read_reg(ctx, HTS221_STATUS_REG, (uint8_t*) ®, 1);
+ ret = hts221_read_reg(ctx, HTS221_STATUS_REG, (uint8_t *) ®, 1);
*val = reg.h_da;
return ret;
@@ -421,7 +456,7 @@ int32_t hts221_humidity_raw_get(stmdev_ctx_t *ctx, int16_t *val)
ret = hts221_read_reg(ctx, HTS221_HUMIDITY_OUT_L, buff, 2);
*val = (int16_t)buff[1];
- *val = (*val * 256) + (int16_t)buff[0];
+ *val = (*val * 256) + (int16_t)buff[0];
return ret;
}
@@ -441,7 +476,7 @@ int32_t hts221_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
ret = hts221_read_reg(ctx, HTS221_TEMP_OUT_L, buff, 2);
*val = (int16_t)buff[1];
- *val = (*val * 256) + (int16_t)buff[0];
+ *val = (*val * 256) + (int16_t)buff[0];
return ret;
}
@@ -453,7 +488,7 @@ int32_t hts221_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
/**
* @defgroup HTS221_common
- * @brief This section group common usefull functions
+ * @brief This section group common useful functions
* @{
*
*/
@@ -469,7 +504,9 @@ int32_t hts221_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
int32_t hts221_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = hts221_read_reg(ctx, HTS221_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -486,12 +523,14 @@ int32_t hts221_power_on_set(stmdev_ctx_t *ctx, uint8_t val)
hts221_ctrl_reg1_t reg;
int32_t ret;
- ret = hts221_read_reg(ctx, HTS221_CTRL_REG1, (uint8_t*) ®, 1);
+ ret = hts221_read_reg(ctx, HTS221_CTRL_REG1, (uint8_t *) ®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.pd = val;
- ret = hts221_write_reg(ctx, HTS221_CTRL_REG1, (uint8_t*) ®, 1);
+ ret = hts221_write_reg(ctx, HTS221_CTRL_REG1, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -506,12 +545,12 @@ int32_t hts221_power_on_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t hts221_power_on_get(stmdev_ctx_t *ctx, uint8_t *val)
{
hts221_ctrl_reg1_t reg;
- int32_t mm_error;
+ int32_t ret;
- mm_error = hts221_read_reg(ctx, HTS221_CTRL_REG1, (uint8_t*) ®, 1);
+ ret = hts221_read_reg(ctx, HTS221_CTRL_REG1, (uint8_t *) ®, 1);
*val = reg.pd;
- return mm_error;
+ return ret;
}
/**
@@ -527,11 +566,12 @@ int32_t hts221_heater_set(stmdev_ctx_t *ctx, uint8_t val)
hts221_ctrl_reg2_t reg;
int32_t ret;
- ret = hts221_read_reg(ctx, HTS221_CTRL_REG2, (uint8_t*) ®, 1);
+ ret = hts221_read_reg(ctx, HTS221_CTRL_REG2, (uint8_t *) ®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.heater = val;
- ret = hts221_write_reg(ctx, HTS221_CTRL_REG2, (uint8_t*) ®, 1);
+ ret = hts221_write_reg(ctx, HTS221_CTRL_REG2, (uint8_t *) ®, 1);
}
return ret;
@@ -550,7 +590,7 @@ int32_t hts221_heater_get(stmdev_ctx_t *ctx, uint8_t *val)
hts221_ctrl_reg2_t reg;
int32_t ret;
- ret = hts221_read_reg(ctx, HTS221_CTRL_REG2, (uint8_t*) ®, 1);
+ ret = hts221_read_reg(ctx, HTS221_CTRL_REG2, (uint8_t *) ®, 1);
*val = reg.heater;
return ret;
@@ -569,11 +609,12 @@ int32_t hts221_boot_set(stmdev_ctx_t *ctx, uint8_t val)
hts221_ctrl_reg2_t reg;
int32_t ret;
- ret = hts221_read_reg(ctx, HTS221_CTRL_REG2, (uint8_t*) ®, 1);
+ ret = hts221_read_reg(ctx, HTS221_CTRL_REG2, (uint8_t *) ®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.boot = val;
- ret = hts221_write_reg(ctx, HTS221_CTRL_REG2, (uint8_t*) ®, 1);
+ ret = hts221_write_reg(ctx, HTS221_CTRL_REG2, (uint8_t *) ®, 1);
}
return ret;
@@ -592,7 +633,7 @@ int32_t hts221_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
hts221_ctrl_reg2_t reg;
int32_t ret;
- ret = hts221_read_reg(ctx, HTS221_CTRL_REG2, (uint8_t*) ®, 1);
+ ret = hts221_read_reg(ctx, HTS221_CTRL_REG2, (uint8_t *) ®, 1);
*val = reg.boot;
return ret;
@@ -609,7 +650,9 @@ int32_t hts221_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t hts221_status_get(stmdev_ctx_t *ctx, hts221_status_reg_t *val)
{
int32_t ret;
- ret = hts221_read_reg(ctx, HTS221_STATUS_REG, (uint8_t*) val, 1);
+
+ ret = hts221_read_reg(ctx, HTS221_STATUS_REG, (uint8_t *) val, 1);
+
return ret;
}
@@ -638,11 +681,12 @@ int32_t hts221_drdy_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
hts221_ctrl_reg3_t reg;
int32_t ret;
- ret = hts221_read_reg(ctx, HTS221_CTRL_REG3, (uint8_t*) ®, 1);
+ ret = hts221_read_reg(ctx, HTS221_CTRL_REG3, (uint8_t *) ®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.drdy = val;
- ret = hts221_write_reg(ctx, HTS221_CTRL_REG3, (uint8_t*) ®, 1);
+ ret = hts221_write_reg(ctx, HTS221_CTRL_REG3, (uint8_t *) ®, 1);
}
return ret;
@@ -661,7 +705,7 @@ int32_t hts221_drdy_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
hts221_ctrl_reg3_t reg;
int32_t ret;
- ret = hts221_read_reg(ctx, HTS221_CTRL_REG3, (uint8_t*) ®, 1);
+ ret = hts221_read_reg(ctx, HTS221_CTRL_REG3, (uint8_t *) ®, 1);
*val = reg.drdy;
return ret;
@@ -679,11 +723,12 @@ int32_t hts221_pin_mode_set(stmdev_ctx_t *ctx, hts221_pp_od_t val)
hts221_ctrl_reg3_t reg;
int32_t ret;
- ret = hts221_read_reg(ctx, HTS221_CTRL_REG3, (uint8_t*) ®, 1);
+ ret = hts221_read_reg(ctx, HTS221_CTRL_REG3, (uint8_t *) ®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.pp_od = (uint8_t)val;
- ret = hts221_write_reg(ctx, HTS221_CTRL_REG3, (uint8_t*) ®, 1);
+ ret = hts221_write_reg(ctx, HTS221_CTRL_REG3, (uint8_t *) ®, 1);
}
return ret;
@@ -702,15 +747,18 @@ int32_t hts221_pin_mode_get(stmdev_ctx_t *ctx, hts221_pp_od_t *val)
hts221_ctrl_reg3_t reg;
int32_t ret;
- ret = hts221_read_reg(ctx, HTS221_CTRL_REG3, (uint8_t*) ®, 1);
+ ret = hts221_read_reg(ctx, HTS221_CTRL_REG3, (uint8_t *) ®, 1);
- switch (reg.pp_od) {
+ switch (reg.pp_od)
+ {
case HTS221_PUSH_PULL:
*val = HTS221_PUSH_PULL;
break;
+
case HTS221_OPEN_DRAIN:
*val = HTS221_OPEN_DRAIN;
break;
+
default:
*val = HTS221_PIN_MODE_ND;
break;
@@ -727,16 +775,18 @@ int32_t hts221_pin_mode_get(stmdev_ctx_t *ctx, hts221_pp_od_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t hts221_int_polarity_set(stmdev_ctx_t *ctx, hts221_drdy_h_l_t val)
+int32_t hts221_int_polarity_set(stmdev_ctx_t *ctx,
+ hts221_drdy_h_l_t val)
{
hts221_ctrl_reg3_t reg;
int32_t ret;
- ret = hts221_read_reg(ctx, HTS221_CTRL_REG3, (uint8_t*) ®, 1);
+ ret = hts221_read_reg(ctx, HTS221_CTRL_REG3, (uint8_t *) ®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.drdy_h_l = (uint8_t)val;
- ret = hts221_write_reg(ctx, HTS221_CTRL_REG3, (uint8_t*) ®, 1);
+ ret = hts221_write_reg(ctx, HTS221_CTRL_REG3, (uint8_t *) ®, 1);
}
return ret;
@@ -750,20 +800,24 @@ int32_t hts221_int_polarity_set(stmdev_ctx_t *ctx, hts221_drdy_h_l_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t hts221_int_polarity_get(stmdev_ctx_t *ctx, hts221_drdy_h_l_t *val)
+int32_t hts221_int_polarity_get(stmdev_ctx_t *ctx,
+ hts221_drdy_h_l_t *val)
{
hts221_ctrl_reg3_t reg;
int32_t ret;
- ret = hts221_read_reg(ctx, HTS221_CTRL_REG3, (uint8_t*) ®, 1);
+ ret = hts221_read_reg(ctx, HTS221_CTRL_REG3, (uint8_t *) ®, 1);
- switch (reg.drdy_h_l) {
+ switch (reg.drdy_h_l)
+ {
case HTS221_ACTIVE_HIGH:
*val = HTS221_ACTIVE_HIGH;
break;
+
case HTS221_ACTIVE_LOW:
*val = HTS221_ACTIVE_LOW;
break;
+
default:
*val = HTS221_ACTIVE_ND;
break;
@@ -839,8 +893,9 @@ int32_t hts221_temp_deg_point_0_get(stmdev_ctx_t *ctx, float_t *val)
ret = hts221_read_reg(ctx, HTS221_T0_DEGC_X8, &coeff_l, 1);
- if(ret == 0){
- ret = hts221_read_reg(ctx, HTS221_T1_T0_MSB, (uint8_t*) ®, 1);
+ if (ret == 0)
+ {
+ ret = hts221_read_reg(ctx, HTS221_T1_T0_MSB, (uint8_t *) ®, 1);
coeff_h = reg.t0_msb;
*val = ((coeff_h * 256) + coeff_l) / 8.0f;
}
@@ -864,8 +919,9 @@ int32_t hts221_temp_deg_point_1_get(stmdev_ctx_t *ctx, float_t *val)
ret = hts221_read_reg(ctx, HTS221_T1_DEGC_X8, &coeff_l, 1);
- if(ret == 0){
- ret = hts221_read_reg(ctx, HTS221_T1_T0_MSB, (uint8_t*) ®, 1);
+ if (ret == 0)
+ {
+ ret = hts221_read_reg(ctx, HTS221_T1_T0_MSB, (uint8_t *) ®, 1);
coeff_h = reg.t1_msb;
*val = ((coeff_h * 256) + coeff_l) / 8.0f;
}
@@ -886,9 +942,11 @@ int32_t hts221_hum_adc_point_0_get(stmdev_ctx_t *ctx, float_t *val)
uint8_t coeff_p[2];
int16_t coeff;
int32_t ret;
+
ret = hts221_read_reg(ctx, HTS221_H0_T0_OUT_L, coeff_p, 2);
coeff = (coeff_p[1] * 256) + coeff_p[0];
*val = coeff * 1.0f;
+
return ret;
}
@@ -905,9 +963,11 @@ int32_t hts221_hum_adc_point_1_get(stmdev_ctx_t *ctx, float_t *val)
uint8_t coeff_p[2];
int16_t coeff;
int32_t ret;
+
ret = hts221_read_reg(ctx, HTS221_H1_T0_OUT_L, coeff_p, 2);
coeff = (coeff_p[1] * 256) + coeff_p[0];
*val = coeff * 1.0f;
+
return ret;
}
@@ -924,9 +984,11 @@ int32_t hts221_temp_adc_point_0_get(stmdev_ctx_t *ctx, float_t *val)
uint8_t coeff_p[2];
int16_t coeff;
int32_t ret;
+
ret = hts221_read_reg(ctx, HTS221_T0_OUT_L, coeff_p, 2);
coeff = (coeff_p[1] * 256) + coeff_p[0];
*val = coeff * 1.0f;
+
return ret;
}
@@ -943,9 +1005,11 @@ int32_t hts221_temp_adc_point_1_get(stmdev_ctx_t *ctx, float_t *val)
uint8_t coeff_p[2];
int16_t coeff;
int32_t ret;
+
ret = hts221_read_reg(ctx, HTS221_T1_OUT_L, coeff_p, 2);
coeff = (coeff_p[1] * 256) + coeff_p[0];
*val = coeff * 1.0f;
+
return ret;
}
diff --git a/sensor/stmemsc/hts221_STdC/driver/hts221_reg.h b/sensor/stmemsc/hts221_STdC/driver/hts221_reg.h
index e1e2b20188cb1917b4d3ebb6ddc6b2e8a551824d..ca5f7e14248049c10486f6bb205c5a5f28f3c433 100644
--- a/sensor/stmemsc/hts221_STdC/driver/hts221_reg.h
+++ b/sensor/stmemsc/hts221_STdC/driver/hts221_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file hts221_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * hts221_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file hts221_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * hts221_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef HTS221_REGS_H
#define HTS221_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup HTS221
@@ -74,7 +75,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -107,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -131,7 +134,7 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
+ * You can create a sensor configuration by your own or using
* Unico / Unicleo tools available on STMicroelectronics
* web site.
*
@@ -139,7 +142,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -174,7 +178,8 @@ typedef struct {
#define HTS221_WHO_AM_I 0x0FU
#define HTS221_AV_CONF 0x10U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t avgh : 3;
uint8_t avgt : 3;
@@ -187,7 +192,8 @@ typedef struct {
} hts221_av_conf_t;
#define HTS221_CTRL_REG1 0x20U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t odr : 2;
uint8_t bdu : 1;
@@ -202,7 +208,8 @@ typedef struct {
} hts221_ctrl_reg1_t;
#define HTS221_CTRL_REG2 0x21U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t one_shot : 1;
uint8_t heater : 1;
@@ -217,7 +224,8 @@ typedef struct {
} hts221_ctrl_reg2_t;
#define HTS221_CTRL_REG3 0x22U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t drdy : 1;
@@ -234,7 +242,8 @@ typedef struct {
} hts221_ctrl_reg3_t;
#define HTS221_STATUS_REG 0x27U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t t_da : 1;
uint8_t h_da : 1;
@@ -255,7 +264,8 @@ typedef struct {
#define HTS221_T0_DEGC_X8 0x32U
#define HTS221_T1_DEGC_X8 0x33U
#define HTS221_T1_T0_MSB 0x35U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t t0_msb : 2;
uint8_t t1_msb : 2;
@@ -278,9 +288,9 @@ typedef struct {
/**
* @defgroup HTS221_Register_Union
- * @brief This union group all the registers that has a bitfield
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -288,7 +298,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
hts221_av_conf_t av_conf;
hts221_ctrl_reg1_t ctrl_reg1;
hts221_ctrl_reg2_t ctrl_reg2;
@@ -304,12 +315,14 @@ typedef union{
*
*/
-int32_t hts221_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t hts221_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
uint16_t len);
-int32_t hts221_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t hts221_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-typedef enum {
+typedef enum
+{
HTS221_H_AVG_4 = 0,
HTS221_H_AVG_8 = 1,
HTS221_H_AVG_16 = 2,
@@ -321,9 +334,11 @@ typedef enum {
HTS221_H_AVG_ND = 8,
} hts221_avgh_t;
int32_t hts221_humidity_avg_set(stmdev_ctx_t *ctx, hts221_avgh_t val);
-int32_t hts221_humidity_avg_get(stmdev_ctx_t *ctx, hts221_avgh_t *val);
+int32_t hts221_humidity_avg_get(stmdev_ctx_t *ctx,
+ hts221_avgh_t *val);
-typedef enum {
+typedef enum
+{
HTS221_T_AVG_2 = 0,
HTS221_T_AVG_4 = 1,
HTS221_T_AVG_8 = 2,
@@ -334,10 +349,13 @@ typedef enum {
HTS221_T_AVG_256 = 7,
HTS221_T_AVG_ND = 8,
} hts221_avgt_t;
-int32_t hts221_temperature_avg_set(stmdev_ctx_t *ctx, hts221_avgt_t val);
-int32_t hts221_temperature_avg_get(stmdev_ctx_t *ctx, hts221_avgt_t *val);
+int32_t hts221_temperature_avg_set(stmdev_ctx_t *ctx,
+ hts221_avgt_t val);
+int32_t hts221_temperature_avg_get(stmdev_ctx_t *ctx,
+ hts221_avgt_t *val);
-typedef enum {
+typedef enum
+{
HTS221_ONE_SHOT = 0,
HTS221_ODR_1Hz = 1,
HTS221_ODR_7Hz = 2,
@@ -373,12 +391,14 @@ int32_t hts221_heater_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t hts221_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t hts221_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t hts221_status_get(stmdev_ctx_t *ctx, hts221_status_reg_t *val);
+int32_t hts221_status_get(stmdev_ctx_t *ctx,
+ hts221_status_reg_t *val);
int32_t hts221_drdy_on_int_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t hts221_drdy_on_int_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
HTS221_PUSH_PULL = 0,
HTS221_OPEN_DRAIN = 1,
HTS221_PIN_MODE_ND = 2,
@@ -386,13 +406,16 @@ typedef enum {
int32_t hts221_pin_mode_set(stmdev_ctx_t *ctx, hts221_pp_od_t val);
int32_t hts221_pin_mode_get(stmdev_ctx_t *ctx, hts221_pp_od_t *val);
-typedef enum {
+typedef enum
+{
HTS221_ACTIVE_HIGH = 0,
HTS221_ACTIVE_LOW = 1,
HTS221_ACTIVE_ND = 2,
} hts221_drdy_h_l_t;
-int32_t hts221_int_polarity_set(stmdev_ctx_t *ctx, hts221_drdy_h_l_t val);
-int32_t hts221_int_polarity_get(stmdev_ctx_t *ctx, hts221_drdy_h_l_t *val);
+int32_t hts221_int_polarity_set(stmdev_ctx_t *ctx,
+ hts221_drdy_h_l_t val);
+int32_t hts221_int_polarity_get(stmdev_ctx_t *ctx,
+ hts221_drdy_h_l_t *val);
int32_t hts221_hum_rh_point_0_get(stmdev_ctx_t *ctx, float_t *val);
int32_t hts221_hum_rh_point_1_get(stmdev_ctx_t *ctx, float_t *val);
diff --git a/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.c b/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.c
index febf5638289ff4e53176ca0c73494d6ca48fe308..cbd41af1ecc891b08554ead45415050486a39673 100644
--- a/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.c
+++ b/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file i3g4250d_reg.c
- * @author Sensors Software Solution Team
- * @brief I3G4250D driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file i3g4250d_reg.c
+ * @author Sensors Software Solution Team
+ * @brief I3G4250D driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "i3g4250d_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t i3g4250d_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t i3g4250d_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t i3g4250d_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t i3g4250d_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t i3g4250d_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -86,12 +92,12 @@ int32_t i3g4250d_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
float_t i3g4250d_from_fs245dps_to_mdps(int16_t lsb)
{
- return ( (float_t)lsb * 8.75f );
+ return ((float_t)lsb * 8.75f);
}
float_t i3g4250d_from_lsb_to_celsius(int16_t lsb)
{
- return ( (float_t)lsb + 25.0f );
+ return ((float_t)lsb + 25.0f);
}
/**
@@ -112,7 +118,7 @@ float_t i3g4250d_from_lsb_to_celsius(int16_t lsb)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Change the values of dr in reg CTRL_REG1
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_data_rate_set(stmdev_ctx_t *ctx, i3g4250d_dr_t val)
@@ -120,11 +126,15 @@ int32_t i3g4250d_data_rate_set(stmdev_ctx_t *ctx, i3g4250d_dr_t val)
i3g4250d_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0){
+ ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.dr = ((uint8_t)val & 0x30U) >> 4;
ctrl_reg1.pd = ((uint8_t)val & 0x0FU);
- ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
}
return ret;
@@ -135,7 +145,7 @@ int32_t i3g4250d_data_rate_set(stmdev_ctx_t *ctx, i3g4250d_dr_t val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Get the values of dr in reg CTRL_REG1.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_data_rate_get(stmdev_ctx_t *ctx, i3g4250d_dr_t *val)
@@ -143,30 +153,38 @@ int32_t i3g4250d_data_rate_get(stmdev_ctx_t *ctx, i3g4250d_dr_t *val)
i3g4250d_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
- switch ( ( ctrl_reg1.dr << 4 ) + ctrl_reg1.pd ){
+ switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pd)
+ {
case I3G4250D_ODR_OFF:
*val = I3G4250D_ODR_OFF;
break;
+
case I3G4250D_ODR_SLEEP:
*val = I3G4250D_ODR_SLEEP;
break;
+
case I3G4250D_ODR_100Hz:
*val = I3G4250D_ODR_100Hz;
break;
+
case I3G4250D_ODR_200Hz:
*val = I3G4250D_ODR_200Hz;
break;
+
case I3G4250D_ODR_400Hz:
*val = I3G4250D_ODR_400Hz;
break;
+
case I3G4250D_ODR_800Hz:
*val = I3G4250D_ODR_800Hz;
break;
+
default:
*val = I3G4250D_ODR_OFF;
- break;
+ break;
}
return ret;
@@ -175,8 +193,9 @@ int32_t i3g4250d_data_rate_get(stmdev_ctx_t *ctx, i3g4250d_dr_t *val)
/**
* @brief Gyroscope full-scale selection.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of fs in reg CTRL_REG4
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of fs in reg CTRL_REG4
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_full_scale_set(stmdev_ctx_t *ctx, i3g4250d_fs_t val)
@@ -185,20 +204,24 @@ int32_t i3g4250d_full_scale_set(stmdev_ctx_t *ctx, i3g4250d_fs_t val)
int32_t ret;
ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0) {
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.fs = (uint8_t)val;
ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
/**
* @brief Gyroscope full-scale selection.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of fs in reg CTRL_REG4
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of fs in reg CTRL_REG4
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_full_scale_get(stmdev_ctx_t *ctx, i3g4250d_fs_t *val)
@@ -207,19 +230,22 @@ int32_t i3g4250d_full_scale_get(stmdev_ctx_t *ctx, i3g4250d_fs_t *val)
int32_t ret;
ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
switch (ctrl_reg4.fs)
{
case I3G4250D_245dps:
*val = I3G4250D_245dps;
break;
+
case I3G4250D_500dps:
*val = I3G4250D_500dps;
break;
+
case I3G4250D_2000dps:
*val = I3G4250D_2000dps;
break;
+
default:
*val = I3G4250D_245dps;
break;
@@ -233,14 +259,16 @@ int32_t i3g4250d_full_scale_get(stmdev_ctx_t *ctx, i3g4250d_fs_t *val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val registers STATUS_REG
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_status_reg_get(stmdev_ctx_t *ctx,
i3g4250d_status_reg_t *val)
{
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_STATUS_REG, (uint8_t*) val, 1);
+
+ ret = i3g4250d_read_reg(ctx, I3G4250D_STATUS_REG, (uint8_t *) val, 1);
+
return ret;
}
@@ -249,7 +277,7 @@ int32_t i3g4250d_status_reg_get(stmdev_ctx_t *ctx,
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Change the values of "zyxda" in reg STATUS_REG.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -257,7 +285,8 @@ int32_t i3g4250d_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
i3g4250d_status_reg_t status_reg;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_STATUS_REG,(uint8_t*)&status_reg, 1);
+ ret = i3g4250d_read_reg(ctx, I3G4250D_STATUS_REG,
+ (uint8_t *)&status_reg, 1);
*val = status_reg.zyxda;
return ret;
@@ -279,13 +308,15 @@ int32_t i3g4250d_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param buff Buffer that stores the data read.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = i3g4250d_read_reg(ctx, I3G4250D_OUT_TEMP, buff, 1);
+
return ret;
}
@@ -295,7 +326,7 @@ int32_t i3g4250d_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx Read / write interface definitions.(ptr)
* @param buff Buffer that stores the data read.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
@@ -321,7 +352,7 @@ int32_t i3g4250d_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
/**
* @defgroup I3G4250D_common
- * @brief This section groups common usefull functions.
+ * @brief This section groups common useful functions.
* @{
*
*/
@@ -329,15 +360,17 @@ int32_t i3g4250d_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
/**
* @brief Device Who amI.[get]
*
- * @param ctx Read / write interface definitions.(ptr)
- * @param buff Buffer that stores the data read.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @param ctx Read / write interface definitions.(ptr)
+ * @param buff Buffer that stores the data read.(ptr)
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = i3g4250d_read_reg(ctx, I3G4250D_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -346,7 +379,7 @@ int32_t i3g4250d_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val change the values of st in reg CTRL_REG4.
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_self_test_set(stmdev_ctx_t *ctx, i3g4250d_st_t val)
@@ -354,11 +387,16 @@ int32_t i3g4250d_self_test_set(stmdev_ctx_t *ctx, i3g4250d_st_t val)
i3g4250d_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG4,(uint8_t*)&ctrl_reg4, 1);
- if(ret == 0){
+ ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.st = (uint8_t)val;
- ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG4,(uint8_t*)&ctrl_reg4, 1);
+ ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -367,7 +405,7 @@ int32_t i3g4250d_self_test_set(stmdev_ctx_t *ctx, i3g4250d_st_t val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Get the values of st in reg CTRL_REG4.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_self_test_get(stmdev_ctx_t *ctx, i3g4250d_st_t *val)
@@ -375,21 +413,26 @@ int32_t i3g4250d_self_test_get(stmdev_ctx_t *ctx, i3g4250d_st_t *val)
i3g4250d_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
- switch (ctrl_reg4.st){
+ switch (ctrl_reg4.st)
+ {
case I3G4250D_GY_ST_DISABLE:
*val = I3G4250D_GY_ST_DISABLE;
break;
+
case I3G4250D_GY_ST_POSITIVE:
*val = I3G4250D_GY_ST_POSITIVE;
break;
+
case I3G4250D_GY_ST_NEGATIVE:
*val = I3G4250D_GY_ST_NEGATIVE;
break;
+
default:
*val = I3G4250D_GY_ST_DISABLE;
- break;
+ break;
}
return ret;
@@ -398,58 +441,71 @@ int32_t i3g4250d_self_test_get(stmdev_ctx_t *ctx, i3g4250d_st_t *val)
/**
* @brief Big/Little Endian data selection.[set]
*
- * @param ctx Read / write interface definitions.(ptr)
- * @param val Change the values of "ble" in reg CTRL_REG4.
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @param ctx Read / write interface definitions.(ptr)
+ * @param val Change the values of "ble" in reg CTRL_REG4.
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t i3g4250d_data_format_set(stmdev_ctx_t *ctx, i3g4250d_ble_t val)
+int32_t i3g4250d_data_format_set(stmdev_ctx_t *ctx,
+ i3g4250d_ble_t val)
{
i3g4250d_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG4,(uint8_t*)&ctrl_reg4, 1);
- if(ret == 0){
+ ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.ble = (uint8_t)val;
- ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG4,(uint8_t*)&ctrl_reg4, 1);
+ ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
/**
* @brief Big/Little Endian data selection.[get]
*
- * @param ctx Read / write interface definitions.(ptr)
- * @param val Get the values of "ble" in reg CTRL_REG4.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @param ctx Read / write interface definitions.(ptr)
+ * @param val Get the values of "ble" in reg CTRL_REG4.(ptr)
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t i3g4250d_data_format_get(stmdev_ctx_t *ctx, i3g4250d_ble_t *val)
+int32_t i3g4250d_data_format_get(stmdev_ctx_t *ctx,
+ i3g4250d_ble_t *val)
{
i3g4250d_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG4,(uint8_t*)&ctrl_reg4, 1);
- switch (ctrl_reg4.ble){
+ ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ switch (ctrl_reg4.ble)
+ {
case I3G4250D_AUX_LSB_AT_LOW_ADD:
*val = I3G4250D_AUX_LSB_AT_LOW_ADD;
break;
+
case I3G4250D_AUX_MSB_AT_LOW_ADD:
*val = I3G4250D_AUX_MSB_AT_LOW_ADD;
break;
+
default:
*val = I3G4250D_AUX_LSB_AT_LOW_ADD;
- break;
+ break;
}
+
return ret;
}
/**
* @brief Reboot memory content. Reload the calibration parameters.[set]
*
- * @param ctx Read / write interface definitions.(ptr)
- * @param val Change the values of boot in reg CTRL_REG5.
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @param ctx Read / write interface definitions.(ptr)
+ * @param val Change the values of boot in reg CTRL_REG5.
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_boot_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -457,10 +513,14 @@ int32_t i3g4250d_boot_set(stmdev_ctx_t *ctx, uint8_t val)
i3g4250d_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG5,(uint8_t*)&ctrl_reg5, 1);
- if(ret == 0){
+ ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.boot = val;
- ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG5,(uint8_t*)&ctrl_reg5, 1);
+ ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
}
return ret;
@@ -471,7 +531,7 @@ int32_t i3g4250d_boot_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Get the values of boot in reg CTRL_REG5.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -479,7 +539,8 @@ int32_t i3g4250d_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
i3g4250d_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG5,(uint8_t*)&ctrl_reg5, 1);
+ ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
*val = ctrl_reg5.boot;
return ret;
@@ -501,20 +562,25 @@ int32_t i3g4250d_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @brief Lowpass filter bandwidth selection.[set]
*
- * @param ctx Read / write interface definitions.(ptr)
- * @param val Change the values of "bw" in reg CTRL_REG1.
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @param ctx Read / write interface definitions.(ptr)
+ * @param val Change the values of "bw" in reg CTRL_REG1.
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t i3g4250d_lp_bandwidth_set(stmdev_ctx_t *ctx, i3g4250d_bw_t val)
+int32_t i3g4250d_lp_bandwidth_set(stmdev_ctx_t *ctx,
+ i3g4250d_bw_t val)
{
i3g4250d_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG1,(uint8_t*)&ctrl_reg1, 1);
- if(ret == 0){
+ ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.bw = (uint8_t)val;
- ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG1,(uint8_t*)&ctrl_reg1, 1);
+ ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
}
return ret;
@@ -525,32 +591,39 @@ int32_t i3g4250d_lp_bandwidth_set(stmdev_ctx_t *ctx, i3g4250d_bw_t val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Get the values of "bw" in reg CTRL_REG1.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t i3g4250d_lp_bandwidth_get(stmdev_ctx_t *ctx, i3g4250d_bw_t *val)
+int32_t i3g4250d_lp_bandwidth_get(stmdev_ctx_t *ctx,
+ i3g4250d_bw_t *val)
{
i3g4250d_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG1,(uint8_t*)&ctrl_reg1, 1);
+ ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
- switch (ctrl_reg1.bw){
- case I3G4250D_CUT_OFF_LOW:
+ switch (ctrl_reg1.bw)
+ {
+ case I3G4250D_CUT_OFF_LOW:
*val = I3G4250D_CUT_OFF_LOW;
break;
+
case I3G4250D_CUT_OFF_MEDIUM:
*val = I3G4250D_CUT_OFF_MEDIUM;
break;
+
case I3G4250D_CUT_OFF_HIGH:
*val = I3G4250D_CUT_OFF_HIGH;
break;
+
case I3G4250D_CUT_OFF_VERY_HIGH:
*val = I3G4250D_CUT_OFF_VERY_HIGH;
break;
+
default:
*val = I3G4250D_CUT_OFF_LOW;
- break;
+ break;
}
return ret;
@@ -561,18 +634,23 @@ int32_t i3g4250d_lp_bandwidth_get(stmdev_ctx_t *ctx, i3g4250d_bw_t *val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Change the values of "hpcf" in reg CTRL_REG2.
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t i3g4250d_hp_bandwidth_set(stmdev_ctx_t *ctx, i3g4250d_hpcf_t val)
+int32_t i3g4250d_hp_bandwidth_set(stmdev_ctx_t *ctx,
+ i3g4250d_hpcf_t val)
{
i3g4250d_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG2,(uint8_t*)&ctrl_reg2, 1);
- if(ret == 0){
+ ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpcf = (uint8_t)val;
- ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG2,(uint8_t*)&ctrl_reg2, 1);
+ ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
}
return ret;
@@ -583,50 +661,63 @@ int32_t i3g4250d_hp_bandwidth_set(stmdev_ctx_t *ctx, i3g4250d_hpcf_t val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Get the values of hpcf in reg CTRL_REG2.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t i3g4250d_hp_bandwidth_get(stmdev_ctx_t *ctx, i3g4250d_hpcf_t *val)
+int32_t i3g4250d_hp_bandwidth_get(stmdev_ctx_t *ctx,
+ i3g4250d_hpcf_t *val)
{
i3g4250d_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG2,(uint8_t*)&ctrl_reg2, 1);
+ ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
- switch (ctrl_reg2.hpcf){
+ switch (ctrl_reg2.hpcf)
+ {
case I3G4250D_HP_LEVEL_0:
*val = I3G4250D_HP_LEVEL_0;
break;
+
case I3G4250D_HP_LEVEL_1:
*val = I3G4250D_HP_LEVEL_1;
break;
+
case I3G4250D_HP_LEVEL_2:
*val = I3G4250D_HP_LEVEL_2;
break;
+
case I3G4250D_HP_LEVEL_3:
*val = I3G4250D_HP_LEVEL_3;
break;
+
case I3G4250D_HP_LEVEL_4:
*val = I3G4250D_HP_LEVEL_4;
break;
+
case I3G4250D_HP_LEVEL_5:
*val = I3G4250D_HP_LEVEL_5;
break;
+
case I3G4250D_HP_LEVEL_6:
*val = I3G4250D_HP_LEVEL_6;
break;
+
case I3G4250D_HP_LEVEL_7:
*val = I3G4250D_HP_LEVEL_7;
break;
+
case I3G4250D_HP_LEVEL_8:
*val = I3G4250D_HP_LEVEL_8;
break;
+
case I3G4250D_HP_LEVEL_9:
*val = I3G4250D_HP_LEVEL_9;
break;
+
default:
*val = I3G4250D_HP_LEVEL_0;
- break;
+ break;
}
return ret;
@@ -637,7 +728,7 @@ int32_t i3g4250d_hp_bandwidth_get(stmdev_ctx_t *ctx, i3g4250d_hpcf_t *val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Change the values of "hpm" in reg CTRL_REG2.
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_hp_mode_set(stmdev_ctx_t *ctx, i3g4250d_hpm_t val)
@@ -645,10 +736,14 @@ int32_t i3g4250d_hp_mode_set(stmdev_ctx_t *ctx, i3g4250d_hpm_t val)
i3g4250d_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG2,(uint8_t*)&ctrl_reg2, 1);
- if(ret == 0){
+ ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpm = (uint8_t)val;
- ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG2,(uint8_t*)&ctrl_reg2, 1);
+ ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
}
return ret;
@@ -659,7 +754,7 @@ int32_t i3g4250d_hp_mode_set(stmdev_ctx_t *ctx, i3g4250d_hpm_t val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Get the values of hpm in reg CTRL_REG2.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_hp_mode_get(stmdev_ctx_t *ctx, i3g4250d_hpm_t *val)
@@ -667,24 +762,30 @@ int32_t i3g4250d_hp_mode_get(stmdev_ctx_t *ctx, i3g4250d_hpm_t *val)
i3g4250d_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG2,(uint8_t*)&ctrl_reg2, 1);
+ ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
- switch (ctrl_reg2.hpm){
+ switch (ctrl_reg2.hpm)
+ {
case I3G4250D_HP_NORMAL_MODE_WITH_RST:
*val = I3G4250D_HP_NORMAL_MODE_WITH_RST;
break;
+
case I3G4250D_HP_REFERENCE_SIGNAL:
*val = I3G4250D_HP_REFERENCE_SIGNAL;
break;
+
case I3G4250D_HP_NORMAL_MODE:
*val = I3G4250D_HP_NORMAL_MODE;
break;
+
case I3G4250D_HP_AUTO_RESET_ON_INT:
*val = I3G4250D_HP_AUTO_RESET_ON_INT;
break;
+
default:
*val = I3G4250D_HP_NORMAL_MODE_WITH_RST;
- break;
+ break;
}
return ret;
@@ -695,19 +796,24 @@ int32_t i3g4250d_hp_mode_get(stmdev_ctx_t *ctx, i3g4250d_hpm_t *val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Change the values of "out_sel" in reg CTRL_REG5.
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t i3g4250d_filter_path_set(stmdev_ctx_t *ctx, i3g4250d_out_sel_t val)
+int32_t i3g4250d_filter_path_set(stmdev_ctx_t *ctx,
+ i3g4250d_out_sel_t val)
{
i3g4250d_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG5,(uint8_t*)&ctrl_reg5, 1);
- if(ret == 0){
+ ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.out_sel = (uint8_t)val & 0x03U;
- ctrl_reg5.hpen = ( (uint8_t)val & 0x04U ) >> 2;
- ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG5,(uint8_t*)&ctrl_reg5, 1);
+ ctrl_reg5.hpen = ((uint8_t)val & 0x04U) >> 2;
+ ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
}
return ret;
@@ -718,32 +824,39 @@ int32_t i3g4250d_filter_path_set(stmdev_ctx_t *ctx, i3g4250d_out_sel_t val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Get the values of out_sel in reg CTRL_REG5.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t i3g4250d_filter_path_get(stmdev_ctx_t *ctx, i3g4250d_out_sel_t *val)
+int32_t i3g4250d_filter_path_get(stmdev_ctx_t *ctx,
+ i3g4250d_out_sel_t *val)
{
i3g4250d_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG5,(uint8_t*)&ctrl_reg5, 1);
+ ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
- switch ( ( ctrl_reg5.hpen << 2 ) + ctrl_reg5.out_sel ){
+ switch ((ctrl_reg5.hpen << 2) + ctrl_reg5.out_sel)
+ {
case I3G4250D_ONLY_LPF1_ON_OUT:
*val = I3G4250D_ONLY_LPF1_ON_OUT;
break;
+
case I3G4250D_LPF1_HP_ON_OUT:
*val = I3G4250D_LPF1_HP_ON_OUT;
break;
+
case I3G4250D_LPF1_LPF2_ON_OUT:
*val = I3G4250D_LPF1_LPF2_ON_OUT;
break;
+
case I3G4250D_LPF1_HP_LPF2_ON_OUT:
*val = I3G4250D_LPF1_HP_LPF2_ON_OUT;
break;
+
default:
*val = I3G4250D_ONLY_LPF1_ON_OUT;
- break;
+ break;
}
return ret;
@@ -754,7 +867,7 @@ int32_t i3g4250d_filter_path_get(stmdev_ctx_t *ctx, i3g4250d_out_sel_t *val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Change the values of int1_sel in reg CTRL_REG5
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_filter_path_internal_set(stmdev_ctx_t *ctx,
@@ -763,11 +876,15 @@ int32_t i3g4250d_filter_path_internal_set(stmdev_ctx_t *ctx,
i3g4250d_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG5,(uint8_t*)&ctrl_reg5, 1);
- if(ret == 0){
+ ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.int1_sel = (uint8_t)val & 0x03U;
- ctrl_reg5.hpen = ( (uint8_t)val & 0x04U ) >> 2;
- ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG5,(uint8_t*)&ctrl_reg5, 1);
+ ctrl_reg5.hpen = ((uint8_t)val & 0x04U) >> 2;
+ ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
}
return ret;
@@ -778,7 +895,7 @@ int32_t i3g4250d_filter_path_internal_set(stmdev_ctx_t *ctx,
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Get the values of int1_sel in reg CTRL_REG5.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_filter_path_internal_get(stmdev_ctx_t *ctx,
@@ -787,24 +904,30 @@ int32_t i3g4250d_filter_path_internal_get(stmdev_ctx_t *ctx,
i3g4250d_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG5,(uint8_t*)&ctrl_reg5, 1);
+ ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
- switch ( ( ctrl_reg5.hpen << 2 ) + ctrl_reg5.int1_sel ){
+ switch ((ctrl_reg5.hpen << 2) + ctrl_reg5.int1_sel)
+ {
case I3G4250D_ONLY_LPF1_ON_INT:
*val = I3G4250D_ONLY_LPF1_ON_INT;
break;
+
case I3G4250D_LPF1_HP_ON_INT:
*val = I3G4250D_LPF1_HP_ON_INT;
break;
+
case I3G4250D_LPF1_LPF2_ON_INT:
*val = I3G4250D_LPF1_LPF2_ON_INT;
break;
+
case I3G4250D_LPF1_HP_LPF2_ON_INT:
*val = I3G4250D_LPF1_HP_LPF2_ON_INT;
break;
+
default:
*val = I3G4250D_ONLY_LPF1_ON_INT;
- break;
+ break;
}
return ret;
@@ -815,18 +938,23 @@ int32_t i3g4250d_filter_path_internal_get(stmdev_ctx_t *ctx,
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Change the values of ref in reg REFERENCE
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t i3g4250d_hp_reference_value_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t i3g4250d_hp_reference_value_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
i3g4250d_reference_t reference;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_REFERENCE,(uint8_t*)&reference, 1);
- if(ret == 0){
+ ret = i3g4250d_read_reg(ctx, I3G4250D_REFERENCE,
+ (uint8_t *)&reference, 1);
+
+ if (ret == 0)
+ {
reference.ref = val;
- ret = i3g4250d_write_reg(ctx, I3G4250D_REFERENCE,(uint8_t*)&reference, 1);
+ ret = i3g4250d_write_reg(ctx, I3G4250D_REFERENCE,
+ (uint8_t *)&reference, 1);
}
return ret;
@@ -837,15 +965,17 @@ int32_t i3g4250d_hp_reference_value_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Get the values of ref in reg REFERENCE.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t i3g4250d_hp_reference_value_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t i3g4250d_hp_reference_value_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
i3g4250d_reference_t reference;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_REFERENCE,(uint8_t*)&reference, 1);
+ ret = i3g4250d_read_reg(ctx, I3G4250D_REFERENCE,
+ (uint8_t *)&reference, 1);
*val = reference.ref;
return ret;
@@ -869,7 +999,7 @@ int32_t i3g4250d_hp_reference_value_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Change the values of sim in reg CTRL_REG4
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_spi_mode_set(stmdev_ctx_t *ctx, i3g4250d_sim_t val)
@@ -877,10 +1007,14 @@ int32_t i3g4250d_spi_mode_set(stmdev_ctx_t *ctx, i3g4250d_sim_t val)
i3g4250d_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG4,(uint8_t*)&ctrl_reg4, 1);
- if(ret == 0){
+ ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.sim = (uint8_t)val;
- ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG4,(uint8_t*)&ctrl_reg4, 1);
+ ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
}
return ret;
@@ -891,7 +1025,7 @@ int32_t i3g4250d_spi_mode_set(stmdev_ctx_t *ctx, i3g4250d_sim_t val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Get the values of sim in reg CTRL_REG4.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_spi_mode_get(stmdev_ctx_t *ctx, i3g4250d_sim_t *val)
@@ -899,18 +1033,22 @@ int32_t i3g4250d_spi_mode_get(stmdev_ctx_t *ctx, i3g4250d_sim_t *val)
i3g4250d_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG4,(uint8_t*)&ctrl_reg4, 1);
+ ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
- switch (ctrl_reg4.sim){
+ switch (ctrl_reg4.sim)
+ {
case I3G4250D_SPI_4_WIRE:
*val = I3G4250D_SPI_4_WIRE;
break;
+
case I3G4250D_SPI_3_WIRE:
*val = I3G4250D_SPI_3_WIRE;
break;
+
default:
*val = I3G4250D_SPI_4_WIRE;
- break;
+ break;
}
return ret;
@@ -923,7 +1061,7 @@ int32_t i3g4250d_spi_mode_get(stmdev_ctx_t *ctx, i3g4250d_sim_t *val)
/**
* @defgroup I3G4250D_interrupt_pins
- * @brief This section groups all the functions that manage interrup pins
+ * @brief This section groups all the functions that manage interrupt pins
* @{
*
*/
@@ -934,7 +1072,7 @@ int32_t i3g4250d_spi_mode_get(stmdev_ctx_t *ctx, i3g4250d_sim_t *val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Configure CTRL_REG3 int1 pad
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_pin_int1_route_set(stmdev_ctx_t *ctx,
@@ -943,11 +1081,15 @@ int32_t i3g4250d_pin_int1_route_set(stmdev_ctx_t *ctx,
i3g4250d_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG3,(uint8_t*)&ctrl_reg3, 1);
- if(ret == 0){
+ ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.i1_int1 = val.i1_int1;
ctrl_reg3.i1_boot = val.i1_boot;
- ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG3,(uint8_t*)&ctrl_reg3, 1);
+ ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
}
return ret;
@@ -958,7 +1100,7 @@ int32_t i3g4250d_pin_int1_route_set(stmdev_ctx_t *ctx,
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Read CTRL_REG3 int1 pad.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
@@ -968,7 +1110,8 @@ int32_t i3g4250d_pin_int1_route_get(stmdev_ctx_t *ctx,
i3g4250d_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG3,(uint8_t*)&ctrl_reg3, 1);
+ ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
val->i1_int1 = ctrl_reg3.i1_int1;
val->i1_boot = ctrl_reg3.i1_boot;
@@ -979,7 +1122,7 @@ int32_t i3g4250d_pin_int1_route_get(stmdev_ctx_t *ctx,
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Configure CTRL_REG3 int2 pad
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_pin_int2_route_set(stmdev_ctx_t *ctx,
@@ -988,13 +1131,17 @@ int32_t i3g4250d_pin_int2_route_set(stmdev_ctx_t *ctx,
i3g4250d_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG3,(uint8_t*)&ctrl_reg3, 1);
- if(ret == 0){
+ ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.i2_empty = val.i2_empty;
ctrl_reg3.i2_orun = val.i2_orun;
ctrl_reg3.i2_wtm = val.i2_wtm;
ctrl_reg3.i2_drdy = val.i2_drdy;
- ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG3,(uint8_t*)&ctrl_reg3, 1);
+ ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
}
return ret;
@@ -1005,7 +1152,7 @@ int32_t i3g4250d_pin_int2_route_set(stmdev_ctx_t *ctx,
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Read CTRL_REG3 int2 pad.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_pin_int2_route_get(stmdev_ctx_t *ctx,
@@ -1014,7 +1161,8 @@ int32_t i3g4250d_pin_int2_route_get(stmdev_ctx_t *ctx,
i3g4250d_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG3,(uint8_t*)&ctrl_reg3, 1);
+ ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
val->i2_empty = ctrl_reg3.i2_empty;
val->i2_orun = ctrl_reg3.i2_orun;
val->i2_wtm = ctrl_reg3.i2_wtm;
@@ -1027,7 +1175,7 @@ int32_t i3g4250d_pin_int2_route_get(stmdev_ctx_t *ctx,
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Change the values of pp_od in reg CTRL_REG3
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
@@ -1036,10 +1184,14 @@ int32_t i3g4250d_pin_mode_set(stmdev_ctx_t *ctx, i3g4250d_pp_od_t val)
i3g4250d_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG3,(uint8_t*)&ctrl_reg3, 1);
- if(ret == 0){
+ ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.pp_od = (uint8_t)val;
- ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG3,(uint8_t*)&ctrl_reg3, 1);
+ ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
}
return ret;
@@ -1050,26 +1202,31 @@ int32_t i3g4250d_pin_mode_set(stmdev_ctx_t *ctx, i3g4250d_pp_od_t val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Get the values of pp_od in reg CTRL_REG3.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t i3g4250d_pin_mode_get(stmdev_ctx_t *ctx, i3g4250d_pp_od_t *val)
+int32_t i3g4250d_pin_mode_get(stmdev_ctx_t *ctx,
+ i3g4250d_pp_od_t *val)
{
i3g4250d_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG3,(uint8_t*)&ctrl_reg3, 1);
+ ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch (ctrl_reg3.pp_od ){
+ switch (ctrl_reg3.pp_od)
+ {
case I3G4250D_PUSH_PULL:
*val = I3G4250D_PUSH_PULL;
break;
+
case I3G4250D_OPEN_DRAIN:
*val = I3G4250D_OPEN_DRAIN;
break;
+
default:
*val = I3G4250D_PUSH_PULL;
- break;
+ break;
}
return ret;
@@ -1080,7 +1237,7 @@ int32_t i3g4250d_pin_mode_get(stmdev_ctx_t *ctx, i3g4250d_pp_od_t *val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Change the values of h_lactive in reg CTRL_REG3.
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_pin_polarity_set(stmdev_ctx_t *ctx,
@@ -1089,10 +1246,14 @@ int32_t i3g4250d_pin_polarity_set(stmdev_ctx_t *ctx,
i3g4250d_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG3,(uint8_t*)&ctrl_reg3, 1);
- if(ret == 0){
+ ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.h_lactive = (uint8_t)val;
- ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG3,(uint8_t*)&ctrl_reg3, 1);
+ ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
}
return ret;
@@ -1103,7 +1264,7 @@ int32_t i3g4250d_pin_polarity_set(stmdev_ctx_t *ctx,
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Get the values of h_lactive in reg CTRL_REG3.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_pin_polarity_get(stmdev_ctx_t *ctx,
@@ -1112,18 +1273,22 @@ int32_t i3g4250d_pin_polarity_get(stmdev_ctx_t *ctx,
i3g4250d_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG3,(uint8_t*)&ctrl_reg3, 1);
+ ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch (ctrl_reg3.h_lactive){
+ switch (ctrl_reg3.h_lactive)
+ {
case I3G4250D_ACTIVE_HIGH:
*val = I3G4250D_ACTIVE_HIGH;
break;
+
case I3G4250D_ACTIVE_LOW:
*val = I3G4250D_ACTIVE_LOW;
break;
+
default:
*val = I3G4250D_ACTIVE_HIGH;
- break;
+ break;
}
return ret;
@@ -1134,7 +1299,7 @@ int32_t i3g4250d_pin_polarity_get(stmdev_ctx_t *ctx,
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Change the values of lir in reg INT1_CFG.
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_int_notification_set(stmdev_ctx_t *ctx,
@@ -1143,10 +1308,12 @@ int32_t i3g4250d_int_notification_set(stmdev_ctx_t *ctx,
i3g4250d_int1_cfg_t int1_cfg;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_CFG,(uint8_t*)&int1_cfg, 1);
- if(ret == 0){
+ ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_CFG, (uint8_t *)&int1_cfg, 1);
+
+ if (ret == 0)
+ {
int1_cfg.lir = (uint8_t)val;
- ret = i3g4250d_write_reg(ctx, I3G4250D_INT1_CFG,(uint8_t*)&int1_cfg, 1);
+ ret = i3g4250d_write_reg(ctx, I3G4250D_INT1_CFG, (uint8_t *)&int1_cfg, 1);
}
return ret;
@@ -1157,7 +1324,7 @@ int32_t i3g4250d_int_notification_set(stmdev_ctx_t *ctx,
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Get the values of lir in reg INT1_CFG.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_int_notification_get(stmdev_ctx_t *ctx,
@@ -1166,18 +1333,21 @@ int32_t i3g4250d_int_notification_get(stmdev_ctx_t *ctx,
i3g4250d_int1_cfg_t int1_cfg;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_CFG,(uint8_t*)&int1_cfg, 1);
+ ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_CFG, (uint8_t *)&int1_cfg, 1);
- switch (int1_cfg.lir){
+ switch (int1_cfg.lir)
+ {
case I3G4250D_INT_PULSED:
*val = I3G4250D_INT_PULSED;
break;
+
case I3G4250D_INT_LATCHED:
*val = I3G4250D_INT_LATCHED;
break;
+
default:
*val = I3G4250D_INT_PULSED;
- break;
+ break;
}
return ret;
@@ -1201,14 +1371,16 @@ int32_t i3g4250d_int_notification_get(stmdev_ctx_t *ctx,
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Struct of registers INT1_CFG
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_int_on_threshold_conf_set(stmdev_ctx_t *ctx,
i3g4250d_int1_cfg_t *val)
{
int32_t ret;
- ret = i3g4250d_write_reg(ctx, I3G4250D_INT1_CFG, (uint8_t*) val, 1);
+
+ ret = i3g4250d_write_reg(ctx, I3G4250D_INT1_CFG, (uint8_t *) val, 1);
+
return ret;
}
@@ -1217,14 +1389,16 @@ int32_t i3g4250d_int_on_threshold_conf_set(stmdev_ctx_t *ctx,
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Struct of registers from INT1_CFG to.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_int_on_threshold_conf_get(stmdev_ctx_t *ctx,
i3g4250d_int1_cfg_t *val)
{
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_CFG, (uint8_t*) val, 1);
+
+ ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_CFG, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1232,7 +1406,7 @@ int32_t i3g4250d_int_on_threshold_conf_get(stmdev_ctx_t *ctx,
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Change the values of and_or in reg INT1_CFG
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_int_on_threshold_mode_set(stmdev_ctx_t *ctx,
@@ -1241,10 +1415,12 @@ int32_t i3g4250d_int_on_threshold_mode_set(stmdev_ctx_t *ctx,
i3g4250d_int1_cfg_t int1_cfg;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_CFG,(uint8_t*)&int1_cfg, 1);
- if(ret == 0){
+ ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_CFG, (uint8_t *)&int1_cfg, 1);
+
+ if (ret == 0)
+ {
int1_cfg.and_or = (uint8_t)val;
- ret = i3g4250d_write_reg(ctx, I3G4250D_INT1_CFG,(uint8_t*)&int1_cfg, 1);
+ ret = i3g4250d_write_reg(ctx, I3G4250D_INT1_CFG, (uint8_t *)&int1_cfg, 1);
}
return ret;
@@ -1255,7 +1431,7 @@ int32_t i3g4250d_int_on_threshold_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Get the values of and_or in reg INT1_CFG.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_int_on_threshold_mode_get(stmdev_ctx_t *ctx,
@@ -1264,18 +1440,23 @@ int32_t i3g4250d_int_on_threshold_mode_get(stmdev_ctx_t *ctx,
i3g4250d_int1_cfg_t int1_cfg;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_CFG,(uint8_t*)&int1_cfg, 1);
- switch (int1_cfg.and_or){
+ ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_CFG, (uint8_t *)&int1_cfg, 1);
+
+ switch (int1_cfg.and_or)
+ {
case I3G4250D_INT1_ON_TH_OR:
*val = I3G4250D_INT1_ON_TH_OR;
break;
+
case I3G4250D_INT1_ON_TH_AND:
*val = I3G4250D_INT1_ON_TH_AND;
break;
+
default:
*val = I3G4250D_INT1_ON_TH_OR;
- break;
+ break;
}
+
return ret;
}
@@ -1284,14 +1465,16 @@ int32_t i3g4250d_int_on_threshold_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Union of registers from INT1_SRC to.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_int_on_threshold_src_get(stmdev_ctx_t *ctx,
i3g4250d_int1_src_t *val)
{
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_SRC, (uint8_t*) val, 1);
+
+ ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_SRC, (uint8_t *) val, 1);
+
return ret;
}
@@ -1300,7 +1483,7 @@ int32_t i3g4250d_int_on_threshold_src_get(stmdev_ctx_t *ctx,
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Change the values of thsx in reg INT1_TSH_XH
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_int_x_treshold_set(stmdev_ctx_t *ctx, uint16_t val)
@@ -1310,21 +1493,28 @@ int32_t i3g4250d_int_x_treshold_set(stmdev_ctx_t *ctx, uint16_t val)
int32_t ret;
ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_TSH_XH,
- (uint8_t*)&int1_tsh_xh, 1);
- if(ret == 0){
+ (uint8_t *)&int1_tsh_xh, 1);
+
+ if (ret == 0)
+ {
int1_tsh_xh.thsx = (uint8_t)(val / 256U) & 0x7FU;
ret = i3g4250d_write_reg(ctx, I3G4250D_INT1_TSH_XH,
- (uint8_t*)&int1_tsh_xh, 1);
+ (uint8_t *)&int1_tsh_xh, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_TSH_XL,
- (uint8_t*)&int1_tsh_xl, 1);
+ (uint8_t *)&int1_tsh_xl, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
int1_tsh_xl.thsx = (uint8_t)(val - (int1_tsh_xh.thsx * 256U));
ret = i3g4250d_write_reg(ctx, I3G4250D_INT1_TSH_XL,
- (uint8_t*)&int1_tsh_xl, 1);
+ (uint8_t *)&int1_tsh_xl, 1);
}
+
return ret;
}
@@ -1333,7 +1523,7 @@ int32_t i3g4250d_int_x_treshold_set(stmdev_ctx_t *ctx, uint16_t val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Get the values of thsx in reg INT1_TSH_XH.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_int_x_treshold_get(stmdev_ctx_t *ctx, uint16_t *val)
@@ -1343,16 +1533,17 @@ int32_t i3g4250d_int_x_treshold_get(stmdev_ctx_t *ctx, uint16_t *val)
int32_t ret;
ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_TSH_XH,
- (uint8_t*)&int1_tsh_xh, 1);
- if(ret == 0){
- ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_TSH_XL,
- (uint8_t*)&int1_tsh_xl, 1);
+ (uint8_t *)&int1_tsh_xh, 1);
+ if (ret == 0)
+ {
+ ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_TSH_XL,
+ (uint8_t *)&int1_tsh_xl, 1);
*val = int1_tsh_xh.thsx;
*val = *val * 256U;
*val += int1_tsh_xl.thsx;
-
}
+
return ret;
}
@@ -1361,7 +1552,7 @@ int32_t i3g4250d_int_x_treshold_get(stmdev_ctx_t *ctx, uint16_t *val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Change the values of thsy in reg INT1_TSH_YH
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_int_y_treshold_set(stmdev_ctx_t *ctx, uint16_t val)
@@ -1371,21 +1562,28 @@ int32_t i3g4250d_int_y_treshold_set(stmdev_ctx_t *ctx, uint16_t val)
int32_t ret;
ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_TSH_YH,
- (uint8_t*)&int1_tsh_yh, 1);
+ (uint8_t *)&int1_tsh_yh, 1);
int1_tsh_yh.thsy = (uint8_t)(val / 256U) & 0x7FU;
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = i3g4250d_write_reg(ctx, I3G4250D_INT1_TSH_YH,
- (uint8_t*)&int1_tsh_yh, 1);
+ (uint8_t *)&int1_tsh_yh, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_TSH_YL,
- (uint8_t*)&int1_tsh_yl, 1);
+ (uint8_t *)&int1_tsh_yl, 1);
int1_tsh_yl.thsy = (uint8_t)(val - (int1_tsh_yh.thsy * 256U));
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = i3g4250d_write_reg(ctx, I3G4250D_INT1_TSH_YL,
- (uint8_t*)&int1_tsh_yl, 1);
+ (uint8_t *)&int1_tsh_yl, 1);
}
+
return ret;
}
@@ -1394,7 +1592,7 @@ int32_t i3g4250d_int_y_treshold_set(stmdev_ctx_t *ctx, uint16_t val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Get the values of thsy in reg INT1_TSH_YH.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_int_y_treshold_get(stmdev_ctx_t *ctx, uint16_t *val)
@@ -1404,15 +1602,17 @@ int32_t i3g4250d_int_y_treshold_get(stmdev_ctx_t *ctx, uint16_t *val)
int32_t ret;
ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_TSH_YH,
- (uint8_t*)&int1_tsh_yh, 1);
- if(ret == 0){
- ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_TSH_YL,
- (uint8_t*)&int1_tsh_yl, 1);
+ (uint8_t *)&int1_tsh_yh, 1);
+ if (ret == 0)
+ {
+ ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_TSH_YL,
+ (uint8_t *)&int1_tsh_yl, 1);
*val = int1_tsh_yh.thsy;
*val = *val * 256U;
*val += int1_tsh_yl.thsy;
}
+
return ret;
}
@@ -1421,7 +1621,7 @@ int32_t i3g4250d_int_y_treshold_get(stmdev_ctx_t *ctx, uint16_t *val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Change the values of thsz in reg INT1_TSH_ZH.
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_int_z_treshold_set(stmdev_ctx_t *ctx, uint16_t val)
@@ -1431,21 +1631,28 @@ int32_t i3g4250d_int_z_treshold_set(stmdev_ctx_t *ctx, uint16_t val)
int32_t ret;
ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_TSH_ZH,
- (uint8_t*)&int1_tsh_zh, 1);
+ (uint8_t *)&int1_tsh_zh, 1);
int1_tsh_zh.thsz = (uint8_t)(val / 256U) & 0x7FU;;
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = i3g4250d_write_reg(ctx, I3G4250D_INT1_TSH_ZH,
- (uint8_t*)&int1_tsh_zh, 1);
+ (uint8_t *)&int1_tsh_zh, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_TSH_ZL,
- (uint8_t*)&int1_tsh_zl, 1);
+ (uint8_t *)&int1_tsh_zl, 1);
int1_tsh_zl.thsz = (uint8_t)(val - (int1_tsh_zh.thsz * 256U));
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = i3g4250d_write_reg(ctx, I3G4250D_INT1_TSH_ZL,
- (uint8_t*)&int1_tsh_zl, 1);
+ (uint8_t *)&int1_tsh_zl, 1);
}
+
return ret;
}
@@ -1454,7 +1661,7 @@ int32_t i3g4250d_int_z_treshold_set(stmdev_ctx_t *ctx, uint16_t val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Get the values of thsz in reg INT1_TSH_ZH.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_int_z_treshold_get(stmdev_ctx_t *ctx, uint16_t *val)
@@ -1464,15 +1671,17 @@ int32_t i3g4250d_int_z_treshold_get(stmdev_ctx_t *ctx, uint16_t *val)
int32_t ret;
ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_TSH_ZH,
- (uint8_t*)&int1_tsh_zh, 1);
- if(ret == 0){
- ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_TSH_ZL,
- (uint8_t*)&int1_tsh_zl, 1);
+ (uint8_t *)&int1_tsh_zh, 1);
+ if (ret == 0)
+ {
+ ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_TSH_ZL,
+ (uint8_t *)&int1_tsh_zl, 1);
*val = int1_tsh_zh.thsz;
*val = *val * 256U;
*val += int1_tsh_zl.thsz;
}
+
return ret;
}
@@ -1481,27 +1690,36 @@ int32_t i3g4250d_int_z_treshold_get(stmdev_ctx_t *ctx, uint16_t *val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Change the values of d in reg INT1_DURATION
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t i3g4250d_int_on_threshold_dur_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t i3g4250d_int_on_threshold_dur_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
i3g4250d_int1_duration_t int1_duration;
int32_t ret;
ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_DURATION,
- (uint8_t*)&int1_duration, 1);
- if(ret == 0){
+ (uint8_t *)&int1_duration, 1);
+
+ if (ret == 0)
+ {
int1_duration.d = val;
- if (val != PROPERTY_DISABLE){
+
+ if (val != PROPERTY_DISABLE)
+ {
int1_duration.wait = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
int1_duration.wait = PROPERTY_DISABLE;
}
+
ret = i3g4250d_write_reg(ctx, I3G4250D_INT1_DURATION,
- (uint8_t*)&int1_duration, 1);
+ (uint8_t *)&int1_duration, 1);
}
+
return ret;
}
@@ -1510,16 +1728,17 @@ int32_t i3g4250d_int_on_threshold_dur_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Get the values of d in reg INT1_DURATION.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t i3g4250d_int_on_threshold_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t i3g4250d_int_on_threshold_dur_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
i3g4250d_int1_duration_t int1_duration;
int32_t ret;
ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_DURATION,
- (uint8_t*)&int1_duration, 1);
+ (uint8_t *)&int1_duration, 1);
*val = int1_duration.d;
return ret;
@@ -1542,7 +1761,7 @@ int32_t i3g4250d_int_on_threshold_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Change the values of fifo_en in reg CTRL_REG5
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_fifo_enable_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1550,10 +1769,14 @@ int32_t i3g4250d_fifo_enable_set(stmdev_ctx_t *ctx, uint8_t val)
i3g4250d_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG5,(uint8_t*)&ctrl_reg5, 1);
- if(ret == 0){
+ ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.fifo_en = val;
- ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG5,(uint8_t*)&ctrl_reg5, 1);
+ ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
}
return ret;
@@ -1564,7 +1787,7 @@ int32_t i3g4250d_fifo_enable_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Get the values of fifo_en in reg CTRL_REG5.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_fifo_enable_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1572,7 +1795,8 @@ int32_t i3g4250d_fifo_enable_get(stmdev_ctx_t *ctx, uint8_t *val)
i3g4250d_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG5,(uint8_t*)&ctrl_reg5, 1);
+ ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
*val = ctrl_reg5.fifo_en;
return ret;
@@ -1583,7 +1807,7 @@ int32_t i3g4250d_fifo_enable_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Change the values of wtm in reg FIFO_CTRL_REG
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1592,11 +1816,13 @@ int32_t i3g4250d_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = i3g4250d_read_reg(ctx, I3G4250D_FIFO_CTRL_REG,
- (uint8_t*)&fifo_ctrl_reg, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl_reg, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl_reg.wtm = val;
ret = i3g4250d_write_reg(ctx, I3G4250D_FIFO_CTRL_REG,
- (uint8_t*)&fifo_ctrl_reg, 1);
+ (uint8_t *)&fifo_ctrl_reg, 1);
}
return ret;
@@ -1607,7 +1833,7 @@ int32_t i3g4250d_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Get the values of wtm in reg FIFO_CTRL_REG.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1616,7 +1842,7 @@ int32_t i3g4250d_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = i3g4250d_read_reg(ctx, I3G4250D_FIFO_CTRL_REG,
- (uint8_t*)&fifo_ctrl_reg, 1);
+ (uint8_t *)&fifo_ctrl_reg, 1);
*val = fifo_ctrl_reg.wtm;
return ret;
@@ -1627,20 +1853,23 @@ int32_t i3g4250d_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Change the values of fm in reg FIFO_CTRL_REG
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t i3g4250d_fifo_mode_set(stmdev_ctx_t *ctx, i3g4250d_fifo_mode_t val)
+int32_t i3g4250d_fifo_mode_set(stmdev_ctx_t *ctx,
+ i3g4250d_fifo_mode_t val)
{
i3g4250d_fifo_ctrl_reg_t fifo_ctrl_reg;
int32_t ret;
ret = i3g4250d_read_reg(ctx, I3G4250D_FIFO_CTRL_REG,
- (uint8_t*)&fifo_ctrl_reg, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl_reg, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl_reg.fm = (uint8_t)val;
ret = i3g4250d_write_reg(ctx, I3G4250D_FIFO_CTRL_REG,
- (uint8_t*)&fifo_ctrl_reg, 1);
+ (uint8_t *)&fifo_ctrl_reg, 1);
}
return ret;
@@ -1651,30 +1880,35 @@ int32_t i3g4250d_fifo_mode_set(stmdev_ctx_t *ctx, i3g4250d_fifo_mode_t val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Get the values of fm in reg FIFO_CTRL_REG.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t i3g4250d_fifo_mode_get(stmdev_ctx_t *ctx, i3g4250d_fifo_mode_t *val)
+int32_t i3g4250d_fifo_mode_get(stmdev_ctx_t *ctx,
+ i3g4250d_fifo_mode_t *val)
{
i3g4250d_fifo_ctrl_reg_t fifo_ctrl_reg;
int32_t ret;
ret = i3g4250d_read_reg(ctx, I3G4250D_FIFO_CTRL_REG,
- (uint8_t*)&fifo_ctrl_reg, 1);
+ (uint8_t *)&fifo_ctrl_reg, 1);
- switch (fifo_ctrl_reg.fm){
+ switch (fifo_ctrl_reg.fm)
+ {
case I3G4250D_FIFO_BYPASS_MODE:
*val = I3G4250D_FIFO_BYPASS_MODE;
break;
+
case I3G4250D_FIFO_MODE:
*val = I3G4250D_FIFO_MODE;
break;
+
case I3G4250D_FIFO_STREAM_MODE:
*val = I3G4250D_FIFO_STREAM_MODE;
break;
+
default:
*val = I3G4250D_FIFO_BYPASS_MODE;
- break;
+ break;
}
return ret;
@@ -1685,7 +1919,7 @@ int32_t i3g4250d_fifo_mode_get(stmdev_ctx_t *ctx, i3g4250d_fifo_mode_t *val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Get the values of fss in reg FIFO_SRC_REG.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1694,7 +1928,7 @@ int32_t i3g4250d_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = i3g4250d_read_reg(ctx, I3G4250D_FIFO_SRC_REG,
- (uint8_t*)&fifo_src_reg, 1);
+ (uint8_t *)&fifo_src_reg, 1);
*val = fifo_src_reg.fss;
return ret;
@@ -1705,7 +1939,7 @@ int32_t i3g4250d_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Get the values of empty in reg FIFO_SRC_REG.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1714,7 +1948,7 @@ int32_t i3g4250d_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = i3g4250d_read_reg(ctx, I3G4250D_FIFO_SRC_REG,
- (uint8_t*)&fifo_src_reg, 1);
+ (uint8_t *)&fifo_src_reg, 1);
*val = fifo_src_reg.empty;
return ret;
@@ -1725,7 +1959,7 @@ int32_t i3g4250d_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Get the values of ovrn in reg FIFO_SRC_REG.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t i3g4250d_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1734,7 +1968,7 @@ int32_t i3g4250d_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = i3g4250d_read_reg(ctx, I3G4250D_FIFO_SRC_REG,
- (uint8_t*)&fifo_src_reg, 1);
+ (uint8_t *)&fifo_src_reg, 1);
*val = fifo_src_reg.ovrn;
return ret;
@@ -1747,7 +1981,7 @@ int32_t i3g4250d_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Get the values of wtm in reg FIFO_SRC_REG.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
@@ -1757,7 +1991,7 @@ int32_t i3g4250d_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = i3g4250d_read_reg(ctx, I3G4250D_FIFO_SRC_REG,
- (uint8_t*)&fifo_src_reg, 1);
+ (uint8_t *)&fifo_src_reg, 1);
*val = fifo_src_reg.wtm;
return ret;
diff --git a/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.h b/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.h
index 4048dc4ce10ab7dfd81aaa4f72e9c0b8d2efba71..76fbfb5af05e26038f9d2dec8e0fe202bbb2fde5 100644
--- a/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.h
+++ b/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file i3g4250d_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * i3g4250d_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file i3g4250d_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * i3g4250d_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef I3G4250D_REGS_H
#define I3G4250D_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup I3G4250D
@@ -72,7 +73,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -105,10 +107,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -129,7 +132,7 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
+ * You can create a sensor configuration by your own or using
* Unico / Unicleo tools available on STMicroelectronics
* web site.
*
@@ -137,7 +140,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -174,7 +178,8 @@ typedef struct {
#define I3G4250D_WHO_AM_I 0x0FU
#define I3G4250D_CTRL_REG1 0x20U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t pd : 4; /* xen yen zen pd */
uint8_t bw : 2;
@@ -187,7 +192,8 @@ typedef struct {
} i3g4250d_ctrl_reg1_t;
#define I3G4250D_CTRL_REG2 0x21U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t hpcf : 4;
uint8_t hpm : 2;
@@ -200,7 +206,8 @@ typedef struct {
} i3g4250d_ctrl_reg2_t;
#define I3G4250D_CTRL_REG3 0x22U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t i2_empty : 1;
uint8_t i2_orun : 1;
@@ -223,7 +230,8 @@ typedef struct {
} i3g4250d_ctrl_reg3_t;
#define I3G4250D_CTRL_REG4 0x23U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t st : 2;
@@ -242,7 +250,8 @@ typedef struct {
} i3g4250d_ctrl_reg4_t;
#define I3G4250D_CTRL_REG5 0x24U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t out_sel : 2;
uint8_t int1_sel : 2;
@@ -261,13 +270,15 @@ typedef struct {
} i3g4250d_ctrl_reg5_t;
#define I3G4250D_REFERENCE 0x25U
-typedef struct {
+typedef struct
+{
uint8_t ref : 8;
} i3g4250d_reference_t;
#define I3G4250D_OUT_TEMP 0x26U
#define I3G4250D_STATUS_REG 0x27U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xda : 1;
uint8_t yda : 1;
@@ -296,7 +307,8 @@ typedef struct {
#define I3G4250D_OUT_Z_L 0x2CU
#define I3G4250D_OUT_Z_H 0x2DU
#define I3G4250D_FIFO_CTRL_REG 0x2EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wtm : 5;
uint8_t fm : 3;
@@ -307,7 +319,8 @@ typedef struct {
} i3g4250d_fifo_ctrl_reg_t;
#define I3G4250D_FIFO_SRC_REG 0x2FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fss : 5;
uint8_t empty : 1;
@@ -322,7 +335,8 @@ typedef struct {
} i3g4250d_fifo_src_reg_t;
#define I3G4250D_INT1_CFG 0x30U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlie : 1;
uint8_t xhie : 1;
@@ -345,7 +359,8 @@ typedef struct {
} i3g4250d_int1_cfg_t;
#define I3G4250D_INT1_SRC 0x31U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
@@ -368,7 +383,8 @@ typedef struct {
} i3g4250d_int1_src_t;
#define I3G4250D_INT1_TSH_XH 0x32U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t thsx : 7;
uint8_t not_used_01 : 1;
@@ -379,12 +395,14 @@ typedef struct {
} i3g4250d_int1_tsh_xh_t;
#define I3G4250D_INT1_TSH_XL 0x33U
-typedef struct {
+typedef struct
+{
uint8_t thsx : 8;
} i3g4250d_int1_tsh_xl_t;
#define I3G4250D_INT1_TSH_YH 0x34U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t thsy : 7;
uint8_t not_used_01 : 1;
@@ -395,12 +413,14 @@ typedef struct {
} i3g4250d_int1_tsh_yh_t;
#define I3G4250D_INT1_TSH_YL 0x35U
-typedef struct {
+typedef struct
+{
uint8_t thsy : 8;
} i3g4250d_int1_tsh_yl_t;
#define I3G4250D_INT1_TSH_ZH 0x36U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t thsz : 7;
uint8_t not_used_01 : 1;
@@ -411,12 +431,14 @@ typedef struct {
} i3g4250d_int1_tsh_zh_t;
#define I3G4250D_INT1_TSH_ZL 0x37U
-typedef struct {
+typedef struct
+{
uint8_t thsz : 8;
} i3g4250d_int1_tsh_zl_t;
#define I3G4250D_INT1_DURATION 0x38U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d : 7;
uint8_t wait : 1;
@@ -428,9 +450,9 @@ typedef struct {
/**
* @defgroup LSM9DS1_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -439,7 +461,8 @@ typedef struct {
*
*/
-typedef union{
+typedef union
+{
i3g4250d_ctrl_reg1_t ctrl_reg1;
i3g4250d_ctrl_reg2_t ctrl_reg2;
i3g4250d_ctrl_reg3_t ctrl_reg3;
@@ -467,9 +490,11 @@ typedef union{
*
*/
-int32_t i3g4250d_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t i3g4250d_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t i3g4250d_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t i3g4250d_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
float_t i3g4250d_from_fs245dps_to_mdps(int16_t lsb);
@@ -484,7 +509,8 @@ int32_t i3g4250d_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t i3g4250d_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t i3g4250d_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
I3G4250D_ODR_OFF = 0x00,
I3G4250D_ODR_SLEEP = 0x08,
I3G4250D_ODR_100Hz = 0x0F,
@@ -495,26 +521,31 @@ typedef enum {
int32_t i3g4250d_data_rate_set(stmdev_ctx_t *ctx, i3g4250d_dr_t val);
int32_t i3g4250d_data_rate_get(stmdev_ctx_t *ctx, i3g4250d_dr_t *val);
-typedef enum {
+typedef enum
+{
I3G4250D_245dps = 0x00,
I3G4250D_500dps = 0x01,
I3G4250D_2000dps = 0x02,
} i3g4250d_fs_t;
int32_t i3g4250d_full_scale_set(stmdev_ctx_t *ctx, i3g4250d_fs_t val);
-int32_t i3g4250d_full_scale_get(stmdev_ctx_t *ctx, i3g4250d_fs_t *val);
+int32_t i3g4250d_full_scale_get(stmdev_ctx_t *ctx,
+ i3g4250d_fs_t *val);
int32_t i3g4250d_status_reg_get(stmdev_ctx_t *ctx,
i3g4250d_status_reg_t *val);
int32_t i3g4250d_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t i3g4250d_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t i3g4250d_temperature_raw_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
-int32_t i3g4250d_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t i3g4250d_angular_rate_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
int32_t i3g4250d_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
-typedef enum {
+typedef enum
+{
I3G4250D_GY_ST_DISABLE = 0,
I3G4250D_GY_ST_POSITIVE = 1,
I3G4250D_GY_ST_NEGATIVE = 3,
@@ -522,26 +553,33 @@ typedef enum {
int32_t i3g4250d_self_test_set(stmdev_ctx_t *ctx, i3g4250d_st_t val);
int32_t i3g4250d_self_test_get(stmdev_ctx_t *ctx, i3g4250d_st_t *val);
-typedef enum {
+typedef enum
+{
I3G4250D_AUX_LSB_AT_LOW_ADD = 0,
I3G4250D_AUX_MSB_AT_LOW_ADD = 1,
} i3g4250d_ble_t;
-int32_t i3g4250d_data_format_set(stmdev_ctx_t *ctx, i3g4250d_ble_t val);
-int32_t i3g4250d_data_format_get(stmdev_ctx_t *ctx, i3g4250d_ble_t *val);
+int32_t i3g4250d_data_format_set(stmdev_ctx_t *ctx,
+ i3g4250d_ble_t val);
+int32_t i3g4250d_data_format_get(stmdev_ctx_t *ctx,
+ i3g4250d_ble_t *val);
int32_t i3g4250d_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t i3g4250d_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
I3G4250D_CUT_OFF_LOW = 0,
I3G4250D_CUT_OFF_MEDIUM = 1,
I3G4250D_CUT_OFF_HIGH = 2,
I3G4250D_CUT_OFF_VERY_HIGH = 3,
} i3g4250d_bw_t;
-int32_t i3g4250d_lp_bandwidth_set(stmdev_ctx_t *ctx, i3g4250d_bw_t val);
-int32_t i3g4250d_lp_bandwidth_get(stmdev_ctx_t *ctx, i3g4250d_bw_t *val);
+int32_t i3g4250d_lp_bandwidth_set(stmdev_ctx_t *ctx,
+ i3g4250d_bw_t val);
+int32_t i3g4250d_lp_bandwidth_get(stmdev_ctx_t *ctx,
+ i3g4250d_bw_t *val);
-typedef enum {
+typedef enum
+{
I3G4250D_HP_LEVEL_0 = 0,
I3G4250D_HP_LEVEL_1 = 1,
I3G4250D_HP_LEVEL_2 = 2,
@@ -558,7 +596,8 @@ int32_t i3g4250d_hp_bandwidth_set(stmdev_ctx_t *ctx,
int32_t i3g4250d_hp_bandwidth_get(stmdev_ctx_t *ctx,
i3g4250d_hpcf_t *val);
-typedef enum {
+typedef enum
+{
I3G4250D_HP_NORMAL_MODE_WITH_RST = 0,
I3G4250D_HP_REFERENCE_SIGNAL = 1,
I3G4250D_HP_NORMAL_MODE = 2,
@@ -567,7 +606,8 @@ typedef enum {
int32_t i3g4250d_hp_mode_set(stmdev_ctx_t *ctx, i3g4250d_hpm_t val);
int32_t i3g4250d_hp_mode_get(stmdev_ctx_t *ctx, i3g4250d_hpm_t *val);
-typedef enum {
+typedef enum
+{
I3G4250D_ONLY_LPF1_ON_OUT = 0,
I3G4250D_LPF1_HP_ON_OUT = 1,
I3G4250D_LPF1_LPF2_ON_OUT = 2,
@@ -578,7 +618,8 @@ int32_t i3g4250d_filter_path_set(stmdev_ctx_t *ctx,
int32_t i3g4250d_filter_path_get(stmdev_ctx_t *ctx,
i3g4250d_out_sel_t *val);
-typedef enum {
+typedef enum
+{
I3G4250D_ONLY_LPF1_ON_INT = 0,
I3G4250D_LPF1_HP_ON_INT = 1,
I3G4250D_LPF1_LPF2_ON_INT = 2,
@@ -589,17 +630,21 @@ int32_t i3g4250d_filter_path_internal_set(stmdev_ctx_t *ctx,
int32_t i3g4250d_filter_path_internal_get(stmdev_ctx_t *ctx,
i3g4250d_int1_sel_t *val);
-int32_t i3g4250d_hp_reference_value_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t i3g4250d_hp_reference_value_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t i3g4250d_hp_reference_value_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t i3g4250d_hp_reference_value_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
I3G4250D_SPI_4_WIRE = 0,
I3G4250D_SPI_3_WIRE = 1,
} i3g4250d_sim_t;
int32_t i3g4250d_spi_mode_set(stmdev_ctx_t *ctx, i3g4250d_sim_t val);
int32_t i3g4250d_spi_mode_get(stmdev_ctx_t *ctx, i3g4250d_sim_t *val);
-typedef struct {
+typedef struct
+{
uint8_t i1_int1 : 1;
uint8_t i1_boot : 1;
} i3g4250d_int1_route_t;
@@ -608,7 +653,8 @@ int32_t i3g4250d_pin_int1_route_set(stmdev_ctx_t *ctx,
int32_t i3g4250d_pin_int1_route_get(stmdev_ctx_t *ctx,
i3g4250d_int1_route_t *val);
-typedef struct {
+typedef struct
+{
uint8_t i2_empty : 1;
uint8_t i2_orun : 1;
uint8_t i2_wtm : 1;
@@ -619,14 +665,18 @@ int32_t i3g4250d_pin_int2_route_set(stmdev_ctx_t *ctx,
int32_t i3g4250d_pin_int2_route_get(stmdev_ctx_t *ctx,
i3g4250d_int2_route_t *val);
-typedef enum {
+typedef enum
+{
I3G4250D_PUSH_PULL = 0,
I3G4250D_OPEN_DRAIN = 1,
} i3g4250d_pp_od_t;
-int32_t i3g4250d_pin_mode_set(stmdev_ctx_t *ctx, i3g4250d_pp_od_t val);
-int32_t i3g4250d_pin_mode_get(stmdev_ctx_t *ctx, i3g4250d_pp_od_t *val);
+int32_t i3g4250d_pin_mode_set(stmdev_ctx_t *ctx,
+ i3g4250d_pp_od_t val);
+int32_t i3g4250d_pin_mode_get(stmdev_ctx_t *ctx,
+ i3g4250d_pp_od_t *val);
-typedef enum {
+typedef enum
+{
I3G4250D_ACTIVE_HIGH = 0,
I3G4250D_ACTIVE_LOW = 1,
} i3g4250d_h_lactive_t;
@@ -635,7 +685,8 @@ int32_t i3g4250d_pin_polarity_set(stmdev_ctx_t *ctx,
int32_t i3g4250d_pin_polarity_get(stmdev_ctx_t *ctx,
i3g4250d_h_lactive_t *val);
-typedef enum {
+typedef enum
+{
I3G4250D_INT_PULSED = 0,
I3G4250D_INT_LATCHED = 1,
} i3g4250d_lir_t;
@@ -649,7 +700,8 @@ int32_t i3g4250d_int_on_threshold_conf_set(stmdev_ctx_t *ctx,
int32_t i3g4250d_int_on_threshold_conf_get(stmdev_ctx_t *ctx,
i3g4250d_int1_cfg_t *val);
-typedef enum {
+typedef enum
+{
I3G4250D_INT1_ON_TH_AND = 1,
I3G4250D_INT1_ON_TH_OR = 0,
} i3g4250d_and_or_t;
@@ -670,8 +722,10 @@ int32_t i3g4250d_int_y_treshold_get(stmdev_ctx_t *ctx, uint16_t *val);
int32_t i3g4250d_int_z_treshold_set(stmdev_ctx_t *ctx, uint16_t val);
int32_t i3g4250d_int_z_treshold_get(stmdev_ctx_t *ctx, uint16_t *val);
-int32_t i3g4250d_int_on_threshold_dur_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t i3g4250d_int_on_threshold_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t i3g4250d_int_on_threshold_dur_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t i3g4250d_int_on_threshold_dur_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t i3g4250d_fifo_enable_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t i3g4250d_fifo_enable_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -679,13 +733,16 @@ int32_t i3g4250d_fifo_enable_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t i3g4250d_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t i3g4250d_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
I3G4250D_FIFO_BYPASS_MODE = 0x00,
I3G4250D_FIFO_MODE = 0x01,
I3G4250D_FIFO_STREAM_MODE = 0x02,
} i3g4250d_fifo_mode_t;
-int32_t i3g4250d_fifo_mode_set(stmdev_ctx_t *ctx, i3g4250d_fifo_mode_t val);
-int32_t i3g4250d_fifo_mode_get(stmdev_ctx_t *ctx, i3g4250d_fifo_mode_t *val);
+int32_t i3g4250d_fifo_mode_set(stmdev_ctx_t *ctx,
+ i3g4250d_fifo_mode_t val);
+int32_t i3g4250d_fifo_mode_get(stmdev_ctx_t *ctx,
+ i3g4250d_fifo_mode_t *val);
int32_t i3g4250d_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val);
diff --git a/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.c b/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.c
index 82d6b3040ec83bb79f7cfba43f2cba09af33bbd5..2177ca29bea7325bbea9cd5add39dc3652b9a9d9 100644
--- a/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.c
+++ b/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file iis2dh_reg.c
- * @author Sensors Software Solution Team
- * @brief IIS2DH driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file iis2dh_reg.c
+ * @author Sensors Software Solution Team
+ * @brief IIS2DH driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "iis2dh_reg.h"
@@ -46,11 +46,13 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dh_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t iis2dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +66,14 @@ int32_t iis2dh_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dh_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t iis2dh_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -77,7 +82,7 @@ int32_t iis2dh_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
*
*/
- /**
+/**
* @defgroup IIS2DH_Sensitivity
* @brief These functions convert raw-data into engineering units.
* @{
@@ -86,77 +91,77 @@ int32_t iis2dh_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
float_t iis2dh_from_fs2_hr_to_mg(int16_t lsb)
{
- return ( (float_t)lsb / 16.0f ) * 0.98f;
+ return ((float_t)lsb / 16.0f) * 0.98f;
}
float_t iis2dh_from_fs4_hr_to_mg(int16_t lsb)
{
- return ( (float_t)lsb / 16.0f ) * 1.95f;
+ return ((float_t)lsb / 16.0f) * 1.95f;
}
float_t iis2dh_from_fs8_hr_to_mg(int16_t lsb)
{
- return ( (float_t)lsb / 16.0f ) * 3.91f;
+ return ((float_t)lsb / 16.0f) * 3.91f;
}
float_t iis2dh_from_fs16_hr_to_mg(int16_t lsb)
{
- return ( (float_t)lsb / 16.0f ) * 11.72f;
+ return ((float_t)lsb / 16.0f) * 11.72f;
}
float_t iis2dh_from_lsb_hr_to_celsius(int16_t lsb)
{
- return ( ( (float_t)lsb / 64.0f ) / 4.0f ) + 25.0f;
+ return (((float_t)lsb / 64.0f) / 4.0f) + 25.0f;
}
float_t iis2dh_from_fs2_nm_to_mg(int16_t lsb)
{
- return ( (float_t)lsb / 64.0f ) * 3.91f;
+ return ((float_t)lsb / 64.0f) * 3.91f;
}
float_t iis2dh_from_fs4_nm_to_mg(int16_t lsb)
{
- return ( (float_t)lsb / 64.0f ) * 7.81f;
+ return ((float_t)lsb / 64.0f) * 7.81f;
}
float_t iis2dh_from_fs8_nm_to_mg(int16_t lsb)
{
- return ( (float_t)lsb / 64.0f ) * 15.63f;
+ return ((float_t)lsb / 64.0f) * 15.63f;
}
float_t iis2dh_from_fs16_nm_to_mg(int16_t lsb)
{
- return ( (float_t)lsb / 64.0f ) * 46.95f;
+ return ((float_t)lsb / 64.0f) * 46.95f;
}
float_t iis2dh_from_lsb_nm_to_celsius(int16_t lsb)
{
- return ( ( (float_t)lsb / 64.0f ) / 4.0f ) + 25.0f;
+ return (((float_t)lsb / 64.0f) / 4.0f) + 25.0f;
}
float_t iis2dh_from_fs2_lp_to_mg(int16_t lsb)
{
- return ( (float_t)lsb / 256.0f ) * 15.63f;
+ return ((float_t)lsb / 256.0f) * 15.63f;
}
float_t iis2dh_from_fs4_lp_to_mg(int16_t lsb)
{
- return ( (float_t)lsb / 256.0f ) * 31.25f;
+ return ((float_t)lsb / 256.0f) * 31.25f;
}
float_t iis2dh_from_fs8_lp_to_mg(int16_t lsb)
{
- return ( (float_t)lsb / 256.0f ) * 62.5f;
+ return ((float_t)lsb / 256.0f) * 62.5f;
}
float_t iis2dh_from_fs16_lp_to_mg(int16_t lsb)
{
- return ( (float_t)lsb / 256.0f ) * 188.68f;
+ return ((float_t)lsb / 256.0f) * 188.68f;
}
float_t iis2dh_from_lsb_lp_to_celsius(int16_t lsb)
{
- return ( ( (float_t)lsb / 256.0f ) * 1.0f ) + 25.0f;
+ return (((float_t)lsb / 256.0f) * 1.0f) + 25.0f;
}
/**
@@ -182,7 +187,9 @@ float_t iis2dh_from_lsb_lp_to_celsius(int16_t lsb)
int32_t iis2dh_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = iis2dh_read_reg(ctx, IIS2DH_STATUS_REG_AUX, buff, 1);
+
return ret;
}
/**
@@ -199,7 +206,7 @@ int32_t iis2dh_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = iis2dh_read_reg(ctx, IIS2DH_STATUS_REG_AUX,
- (uint8_t*)&status_reg_aux, 1);
+ (uint8_t *)&status_reg_aux, 1);
*val = status_reg_aux.tda;
return ret;
@@ -218,7 +225,7 @@ int32_t iis2dh_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = iis2dh_read_reg(ctx, IIS2DH_STATUS_REG_AUX,
- (uint8_t*)&status_reg_aux, 1);
+ (uint8_t *)&status_reg_aux, 1);
*val = status_reg_aux.tor;
return ret;
@@ -238,7 +245,7 @@ int32_t iis2dh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
ret = iis2dh_read_reg(ctx, IIS2DH_OUT_TEMP_L, buff, 2);
*val = (int16_t)buff[1];
- *val = (*val * 256) + (int16_t)buff[0];
+ *val = (*val * 256) + (int16_t)buff[0];
return ret;
}
@@ -250,17 +257,22 @@ int32_t iis2dh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dh_temperature_meas_set(stmdev_ctx_t *ctx, iis2dh_temp_en_t val)
+int32_t iis2dh_temperature_meas_set(stmdev_ctx_t *ctx,
+ iis2dh_temp_en_t val)
{
iis2dh_temp_cfg_reg_t temp_cfg_reg;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_TEMP_CFG_REG, (uint8_t*)&temp_cfg_reg, 1);
- if (ret == 0) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_TEMP_CFG_REG,
+ (uint8_t *)&temp_cfg_reg, 1);
+
+ if (ret == 0)
+ {
temp_cfg_reg.temp_en = (uint8_t) val;
ret = iis2dh_write_reg(ctx, IIS2DH_TEMP_CFG_REG,
- (uint8_t*)&temp_cfg_reg, 1);
+ (uint8_t *)&temp_cfg_reg, 1);
}
+
return ret;
}
@@ -272,23 +284,30 @@ int32_t iis2dh_temperature_meas_set(stmdev_ctx_t *ctx, iis2dh_temp_en_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dh_temperature_meas_get(stmdev_ctx_t *ctx, iis2dh_temp_en_t *val)
+int32_t iis2dh_temperature_meas_get(stmdev_ctx_t *ctx,
+ iis2dh_temp_en_t *val)
{
iis2dh_temp_cfg_reg_t temp_cfg_reg;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_TEMP_CFG_REG, (uint8_t*)&temp_cfg_reg, 1);
- switch (temp_cfg_reg.temp_en) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_TEMP_CFG_REG,
+ (uint8_t *)&temp_cfg_reg, 1);
+
+ switch (temp_cfg_reg.temp_en)
+ {
case IIS2DH_TEMP_DISABLE:
*val = IIS2DH_TEMP_DISABLE;
break;
+
case IIS2DH_TEMP_ENABLE:
*val = IIS2DH_TEMP_ENABLE;
break;
+
default:
*val = IIS2DH_TEMP_DISABLE;
break;
}
+
return ret;
}
@@ -301,34 +320,48 @@ int32_t iis2dh_temperature_meas_get(stmdev_ctx_t *ctx, iis2dh_temp_en_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dh_operating_mode_set(stmdev_ctx_t *ctx, iis2dh_op_md_t val)
+int32_t iis2dh_operating_mode_set(stmdev_ctx_t *ctx,
+ iis2dh_op_md_t val)
{
iis2dh_ctrl_reg1_t ctrl_reg1;
iis2dh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if (ret == 0) {
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
}
- if (ret == 0) {
- if ( val == IIS2DH_HR_12bit ) {
+
+ if (ret == 0)
+ {
+ if (val == IIS2DH_HR_12bit)
+ {
ctrl_reg1.lpen = 0;
ctrl_reg4.hr = 1;
}
- if (val == IIS2DH_NM_10bit) {
+
+ if (val == IIS2DH_NM_10bit)
+ {
ctrl_reg1.lpen = 0;
ctrl_reg4.hr = 0;
}
- if (val == IIS2DH_LP_8bit) {
+
+ if (val == IIS2DH_LP_8bit)
+ {
ctrl_reg1.lpen = 1;
ctrl_reg4.hr = 0;
}
- ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+
+ ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
}
- if (ret == 0) {
- ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -340,23 +373,35 @@ int32_t iis2dh_operating_mode_set(stmdev_ctx_t *ctx, iis2dh_op_md_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dh_operating_mode_get(stmdev_ctx_t *ctx, iis2dh_op_md_t *val)
+int32_t iis2dh_operating_mode_get(stmdev_ctx_t *ctx,
+ iis2dh_op_md_t *val)
{
iis2dh_ctrl_reg1_t ctrl_reg1;
iis2dh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if (ret == 0) {
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if ( ctrl_reg1.lpen == PROPERTY_ENABLE ) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ if (ctrl_reg1.lpen == PROPERTY_ENABLE)
+ {
*val = IIS2DH_LP_8bit;
- } else if (ctrl_reg4.hr == PROPERTY_ENABLE ) {
+ }
+
+ else if (ctrl_reg4.hr == PROPERTY_ENABLE)
+ {
*val = IIS2DH_HR_12bit;
- } else {
+ }
+
+ else
+ {
*val = IIS2DH_NM_10bit;
}
}
+
return ret;
}
@@ -373,11 +418,14 @@ int32_t iis2dh_data_rate_set(stmdev_ctx_t *ctx, iis2dh_odr_t val)
iis2dh_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if (ret == 0) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.odr = (uint8_t)val;
- ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -394,42 +442,55 @@ int32_t iis2dh_data_rate_get(stmdev_ctx_t *ctx, iis2dh_odr_t *val)
iis2dh_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- switch (ctrl_reg1.odr) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ switch (ctrl_reg1.odr)
+ {
case IIS2DH_POWER_DOWN:
*val = IIS2DH_POWER_DOWN;
break;
+
case IIS2DH_ODR_1Hz:
*val = IIS2DH_ODR_1Hz;
break;
+
case IIS2DH_ODR_10Hz:
*val = IIS2DH_ODR_10Hz;
break;
+
case IIS2DH_ODR_25Hz:
*val = IIS2DH_ODR_25Hz;
break;
+
case IIS2DH_ODR_50Hz:
*val = IIS2DH_ODR_50Hz;
break;
+
case IIS2DH_ODR_100Hz:
*val = IIS2DH_ODR_100Hz;
break;
+
case IIS2DH_ODR_200Hz:
*val = IIS2DH_ODR_200Hz;
break;
+
case IIS2DH_ODR_400Hz:
*val = IIS2DH_ODR_400Hz;
break;
+
case IIS2DH_ODR_1kHz620_LP:
*val = IIS2DH_ODR_1kHz620_LP;
break;
+
case IIS2DH_ODR_5kHz376_LP_1kHz344_NM_HP:
*val = IIS2DH_ODR_5kHz376_LP_1kHz344_NM_HP;
break;
+
default:
*val = IIS2DH_POWER_DOWN;
break;
}
+
return ret;
}
@@ -442,16 +503,20 @@ int32_t iis2dh_data_rate_get(stmdev_ctx_t *ctx, iis2dh_odr_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dh_high_pass_on_outputs_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t iis2dh_high_pass_on_outputs_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
iis2dh_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if (ret == 0) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.fds = val;
- ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -464,12 +529,13 @@ int32_t iis2dh_high_pass_on_outputs_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dh_high_pass_on_outputs_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t iis2dh_high_pass_on_outputs_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
iis2dh_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
*val = (uint8_t)ctrl_reg2.fds;
return ret;
@@ -489,16 +555,20 @@ int32_t iis2dh_high_pass_on_outputs_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dh_high_pass_bandwidth_set(stmdev_ctx_t *ctx, iis2dh_hpcf_t val)
+int32_t iis2dh_high_pass_bandwidth_set(stmdev_ctx_t *ctx,
+ iis2dh_hpcf_t val)
{
iis2dh_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if (ret == 0) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpcf = (uint8_t)val;
- ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -516,29 +586,37 @@ int32_t iis2dh_high_pass_bandwidth_set(stmdev_ctx_t *ctx, iis2dh_hpcf_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dh_high_pass_bandwidth_get(stmdev_ctx_t *ctx, iis2dh_hpcf_t *val)
+int32_t iis2dh_high_pass_bandwidth_get(stmdev_ctx_t *ctx,
+ iis2dh_hpcf_t *val)
{
iis2dh_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- switch (ctrl_reg2.hpcf) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ switch (ctrl_reg2.hpcf)
+ {
case IIS2DH_AGGRESSIVE:
*val = IIS2DH_AGGRESSIVE;
break;
+
case IIS2DH_STRONG:
*val = IIS2DH_STRONG;
break;
+
case IIS2DH_MEDIUM:
*val = IIS2DH_MEDIUM;
break;
+
case IIS2DH_LIGHT:
*val = IIS2DH_LIGHT;
break;
+
default:
*val = IIS2DH_LIGHT;
break;
}
+
return ret;
}
@@ -555,11 +633,14 @@ int32_t iis2dh_high_pass_mode_set(stmdev_ctx_t *ctx, iis2dh_hpm_t val)
iis2dh_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if (ret == 0) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpm = (uint8_t)val;
- ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -571,29 +652,37 @@ int32_t iis2dh_high_pass_mode_set(stmdev_ctx_t *ctx, iis2dh_hpm_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dh_high_pass_mode_get(stmdev_ctx_t *ctx, iis2dh_hpm_t *val)
+int32_t iis2dh_high_pass_mode_get(stmdev_ctx_t *ctx,
+ iis2dh_hpm_t *val)
{
iis2dh_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- switch (ctrl_reg2.hpm) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ switch (ctrl_reg2.hpm)
+ {
case IIS2DH_NORMAL_WITH_RST:
*val = IIS2DH_NORMAL_WITH_RST;
break;
+
case IIS2DH_REFERENCE_MODE:
*val = IIS2DH_REFERENCE_MODE;
break;
+
case IIS2DH_NORMAL:
*val = IIS2DH_NORMAL;
break;
+
case IIS2DH_AUTORST_ON_INT:
*val = IIS2DH_AUTORST_ON_INT;
break;
+
default:
*val = IIS2DH_NORMAL_WITH_RST;
break;
}
+
return ret;
}
@@ -610,11 +699,14 @@ int32_t iis2dh_full_scale_set(stmdev_ctx_t *ctx, iis2dh_fs_t val)
iis2dh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if (ret == 0) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.fs = (uint8_t)val;
- ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -631,24 +723,31 @@ int32_t iis2dh_full_scale_get(stmdev_ctx_t *ctx, iis2dh_fs_t *val)
iis2dh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- switch (ctrl_reg4.fs) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ switch (ctrl_reg4.fs)
+ {
case IIS2DH_2g:
*val = IIS2DH_2g;
break;
+
case IIS2DH_4g:
*val = IIS2DH_4g;
break;
+
case IIS2DH_8g:
*val = IIS2DH_8g;
break;
+
case IIS2DH_16g:
*val = IIS2DH_16g;
break;
+
default:
*val = IIS2DH_2g;
break;
}
+
return ret;
}
@@ -665,11 +764,14 @@ int32_t iis2dh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if (ret == 0) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.bdu = val;
- ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -686,7 +788,7 @@ int32_t iis2dh_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
*val = (uint8_t)ctrl_reg4.bdu;
return ret;
@@ -704,7 +806,9 @@ int32_t iis2dh_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t iis2dh_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = iis2dh_write_reg(ctx, IIS2DH_REFERENCE, buff, 1);
+
return ret;
}
@@ -720,7 +824,9 @@ int32_t iis2dh_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t iis2dh_filter_reference_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = iis2dh_read_reg(ctx, IIS2DH_REFERENCE, buff, 1);
+
return ret;
}
/**
@@ -736,7 +842,7 @@ int32_t iis2dh_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dh_status_reg_t status_reg;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_STATUS_REG, (uint8_t*)&status_reg, 1);
+ ret = iis2dh_read_reg(ctx, IIS2DH_STATUS_REG, (uint8_t *)&status_reg, 1);
*val = status_reg.zyxda;
return ret;
@@ -754,7 +860,7 @@ int32_t iis2dh_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dh_status_reg_t status_reg;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_STATUS_REG, (uint8_t*)&status_reg, 1);
+ ret = iis2dh_read_reg(ctx, IIS2DH_STATUS_REG, (uint8_t *)&status_reg, 1);
*val = status_reg.zyxor;
return ret;
@@ -774,11 +880,12 @@ int32_t iis2dh_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
ret = iis2dh_read_reg(ctx, IIS2DH_OUT_X_L, buff, 6);
val[0] = (int16_t)buff[1];
- val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
- val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
val[2] = (int16_t)buff[5];
- val[2] = (val[2] * 256) + (int16_t)buff[4];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
/**
@@ -788,7 +895,7 @@ int32_t iis2dh_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
/**
* @defgroup IIS2DH_Common
- * @brief This section group common usefull functions
+ * @brief This section group common useful functions
* @{
*
*/
@@ -804,7 +911,9 @@ int32_t iis2dh_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
int32_t iis2dh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = iis2dh_read_reg(ctx, IIS2DH_WHO_AM_I, buff, 1);
+
return ret;
}
/**
@@ -820,11 +929,14 @@ int32_t iis2dh_self_test_set(stmdev_ctx_t *ctx, iis2dh_st_t val)
iis2dh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if (ret == 0) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.st = (uint8_t)val;
- ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -841,21 +953,27 @@ int32_t iis2dh_self_test_get(stmdev_ctx_t *ctx, iis2dh_st_t *val)
iis2dh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- switch (ctrl_reg4.st) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ switch (ctrl_reg4.st)
+ {
case IIS2DH_ST_DISABLE:
*val = IIS2DH_ST_DISABLE;
break;
+
case IIS2DH_ST_POSITIVE:
*val = IIS2DH_ST_POSITIVE;
break;
+
case IIS2DH_ST_NEGATIVE:
*val = IIS2DH_ST_NEGATIVE;
break;
+
default:
*val = IIS2DH_ST_DISABLE;
break;
}
+
return ret;
}
@@ -872,11 +990,14 @@ int32_t iis2dh_data_format_set(stmdev_ctx_t *ctx, iis2dh_ble_t val)
iis2dh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if (ret == 0) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.ble = (uint8_t)val;
- ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -893,18 +1014,23 @@ int32_t iis2dh_data_format_get(stmdev_ctx_t *ctx, iis2dh_ble_t *val)
iis2dh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- switch (ctrl_reg4.ble) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ switch (ctrl_reg4.ble)
+ {
case IIS2DH_LSB_AT_LOW_ADD:
*val = IIS2DH_LSB_AT_LOW_ADD;
break;
+
case IIS2DH_MSB_AT_LOW_ADD:
*val = IIS2DH_MSB_AT_LOW_ADD;
break;
+
default:
*val = IIS2DH_LSB_AT_LOW_ADD;
break;
}
+
return ret;
}
@@ -921,11 +1047,14 @@ int32_t iis2dh_boot_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.boot = val;
- ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -942,7 +1071,7 @@ int32_t iis2dh_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
*val = (uint8_t)ctrl_reg5.boot;
return ret;
@@ -959,7 +1088,9 @@ int32_t iis2dh_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t iis2dh_int_occurrencies_get(stmdev_ctx_t *ctx, uint8_t *val)
{
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_INT_COUNTER_REG, (uint8_t*) val, 1);
+
+ ret = iis2dh_read_reg(ctx, IIS2DH_INT_COUNTER_REG, (uint8_t *) val, 1);
+
return ret;
}
@@ -974,7 +1105,9 @@ int32_t iis2dh_int_occurrencies_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t iis2dh_status_get(stmdev_ctx_t *ctx, iis2dh_status_reg_t *val)
{
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_STATUS_REG, (uint8_t*) val, 1);
+
+ ret = iis2dh_read_reg(ctx, IIS2DH_STATUS_REG, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -998,10 +1131,13 @@ int32_t iis2dh_status_get(stmdev_ctx_t *ctx, iis2dh_status_reg_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dh_int1_gen_conf_set(stmdev_ctx_t *ctx, iis2dh_int1_cfg_t *val)
+int32_t iis2dh_int1_gen_conf_set(stmdev_ctx_t *ctx,
+ iis2dh_int1_cfg_t *val)
{
int32_t ret;
- ret = iis2dh_write_reg(ctx, IIS2DH_INT1_CFG, (uint8_t*) val, 1);
+
+ ret = iis2dh_write_reg(ctx, IIS2DH_INT1_CFG, (uint8_t *) val, 1);
+
return ret;
}
@@ -1013,10 +1149,13 @@ int32_t iis2dh_int1_gen_conf_set(stmdev_ctx_t *ctx, iis2dh_int1_cfg_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dh_int1_gen_conf_get(stmdev_ctx_t *ctx, iis2dh_int1_cfg_t *val)
+int32_t iis2dh_int1_gen_conf_get(stmdev_ctx_t *ctx,
+ iis2dh_int1_cfg_t *val)
{
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_INT1_CFG, (uint8_t*) val, 1);
+
+ ret = iis2dh_read_reg(ctx, IIS2DH_INT1_CFG, (uint8_t *) val, 1);
+
return ret;
}
@@ -1028,10 +1167,13 @@ int32_t iis2dh_int1_gen_conf_get(stmdev_ctx_t *ctx, iis2dh_int1_cfg_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dh_int1_gen_source_get(stmdev_ctx_t *ctx, iis2dh_int1_src_t *val)
+int32_t iis2dh_int1_gen_source_get(stmdev_ctx_t *ctx,
+ iis2dh_int1_src_t *val)
{
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_INT1_SRC, (uint8_t*) val, 1);
+
+ ret = iis2dh_read_reg(ctx, IIS2DH_INT1_SRC, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1049,11 +1191,14 @@ int32_t iis2dh_int1_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dh_int1_ths_t int1_ths;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_INT1_THS, (uint8_t*)&int1_ths, 1);
- if (ret == 0) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_INT1_THS, (uint8_t *)&int1_ths, 1);
+
+ if (ret == 0)
+ {
int1_ths.ths = val;
- ret = iis2dh_write_reg(ctx, IIS2DH_INT1_THS, (uint8_t*)&int1_ths, 1);
+ ret = iis2dh_write_reg(ctx, IIS2DH_INT1_THS, (uint8_t *)&int1_ths, 1);
}
+
return ret;
}
@@ -1072,7 +1217,7 @@ int32_t iis2dh_int1_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dh_int1_ths_t int1_ths;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_INT1_THS, (uint8_t*)&int1_ths, 1);
+ ret = iis2dh_read_reg(ctx, IIS2DH_INT1_THS, (uint8_t *)&int1_ths, 1);
*val = (uint8_t)int1_ths.ths;
return ret;
@@ -1093,12 +1238,15 @@ int32_t iis2dh_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = iis2dh_read_reg(ctx, IIS2DH_INT1_DURATION,
- (uint8_t*)&int1_duration, 1);
- if (ret == 0) {
+ (uint8_t *)&int1_duration, 1);
+
+ if (ret == 0)
+ {
int1_duration.d = val;
ret = iis2dh_write_reg(ctx, IIS2DH_INT1_DURATION,
- (uint8_t*)&int1_duration, 1);
+ (uint8_t *)&int1_duration, 1);
}
+
return ret;
}
@@ -1117,7 +1265,7 @@ int32_t iis2dh_int1_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = iis2dh_read_reg(ctx, IIS2DH_INT1_DURATION,
- (uint8_t*)&int1_duration, 1);
+ (uint8_t *)&int1_duration, 1);
*val = (uint8_t)int1_duration.d;
return ret;
@@ -1144,10 +1292,13 @@ int32_t iis2dh_int1_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dh_int2_gen_conf_set(stmdev_ctx_t *ctx, iis2dh_int2_cfg_t *val)
+int32_t iis2dh_int2_gen_conf_set(stmdev_ctx_t *ctx,
+ iis2dh_int2_cfg_t *val)
{
int32_t ret;
- ret = iis2dh_write_reg(ctx, IIS2DH_INT2_CFG, (uint8_t*) val, 1);
+
+ ret = iis2dh_write_reg(ctx, IIS2DH_INT2_CFG, (uint8_t *) val, 1);
+
return ret;
}
@@ -1159,10 +1310,13 @@ int32_t iis2dh_int2_gen_conf_set(stmdev_ctx_t *ctx, iis2dh_int2_cfg_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dh_int2_gen_conf_get(stmdev_ctx_t *ctx, iis2dh_int2_cfg_t *val)
+int32_t iis2dh_int2_gen_conf_get(stmdev_ctx_t *ctx,
+ iis2dh_int2_cfg_t *val)
{
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_INT2_CFG, (uint8_t*) val, 1);
+
+ ret = iis2dh_read_reg(ctx, IIS2DH_INT2_CFG, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1173,10 +1327,13 @@ int32_t iis2dh_int2_gen_conf_get(stmdev_ctx_t *ctx, iis2dh_int2_cfg_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dh_int2_gen_source_get(stmdev_ctx_t *ctx, iis2dh_int2_src_t *val)
+int32_t iis2dh_int2_gen_source_get(stmdev_ctx_t *ctx,
+ iis2dh_int2_src_t *val)
{
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_INT2_SRC, (uint8_t*) val, 1);
+
+ ret = iis2dh_read_reg(ctx, IIS2DH_INT2_SRC, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1194,11 +1351,14 @@ int32_t iis2dh_int2_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dh_int2_ths_t int2_ths;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_INT2_THS, (uint8_t*)&int2_ths, 1);
- if (ret == 0) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_INT2_THS, (uint8_t *)&int2_ths, 1);
+
+ if (ret == 0)
+ {
int2_ths.ths = val;
- ret = iis2dh_write_reg(ctx, IIS2DH_INT2_THS, (uint8_t*)&int2_ths, 1);
+ ret = iis2dh_write_reg(ctx, IIS2DH_INT2_THS, (uint8_t *)&int2_ths, 1);
}
+
return ret;
}
@@ -1217,7 +1377,7 @@ int32_t iis2dh_int2_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dh_int2_ths_t int2_ths;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_INT2_THS, (uint8_t*)&int2_ths, 1);
+ ret = iis2dh_read_reg(ctx, IIS2DH_INT2_THS, (uint8_t *)&int2_ths, 1);
*val = (uint8_t)int2_ths.ths;
return ret;
@@ -1238,12 +1398,15 @@ int32_t iis2dh_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = iis2dh_read_reg(ctx, IIS2DH_INT2_DURATION,
- (uint8_t*)&int2_duration, 1);
- if (ret == 0) {
+ (uint8_t *)&int2_duration, 1);
+
+ if (ret == 0)
+ {
int2_duration.d = val;
ret = iis2dh_write_reg(ctx, IIS2DH_INT2_DURATION,
- (uint8_t*)&int2_duration, 1);
+ (uint8_t *)&int2_duration, 1);
}
+
return ret;
}
@@ -1262,7 +1425,7 @@ int32_t iis2dh_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = iis2dh_read_reg(ctx, IIS2DH_INT2_DURATION,
- (uint8_t*)&int2_duration, 1);
+ (uint8_t *)&int2_duration, 1);
*val = (uint8_t)int2_duration.d;
return ret;
@@ -1275,7 +1438,7 @@ int32_t iis2dh_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @defgroup IIS2DH_Interrupt_pins
- * @brief This section group all the functions that manage interrup pins
+ * @brief This section group all the functions that manage interrupt pins
* @{
*
*/
@@ -1288,16 +1451,20 @@ int32_t iis2dh_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dh_high_pass_int_conf_set(stmdev_ctx_t *ctx, iis2dh_hp_t val)
+int32_t iis2dh_high_pass_int_conf_set(stmdev_ctx_t *ctx,
+ iis2dh_hp_t val)
{
iis2dh_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if (ret == 0) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hp = (uint8_t)val;
- ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -1309,41 +1476,53 @@ int32_t iis2dh_high_pass_int_conf_set(stmdev_ctx_t *ctx, iis2dh_hp_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dh_high_pass_int_conf_get(stmdev_ctx_t *ctx, iis2dh_hp_t *val)
+int32_t iis2dh_high_pass_int_conf_get(stmdev_ctx_t *ctx,
+ iis2dh_hp_t *val)
{
iis2dh_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- switch (ctrl_reg2.hp) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ switch (ctrl_reg2.hp)
+ {
case IIS2DH_DISC_FROM_INT_GENERATOR:
*val = IIS2DH_DISC_FROM_INT_GENERATOR;
break;
+
case IIS2DH_ON_INT1_GEN:
*val = IIS2DH_ON_INT1_GEN;
break;
+
case IIS2DH_ON_INT2_GEN:
*val = IIS2DH_ON_INT2_GEN;
break;
+
case IIS2DH_ON_TAP_GEN:
*val = IIS2DH_ON_TAP_GEN;
break;
+
case IIS2DH_ON_INT1_INT2_GEN:
*val = IIS2DH_ON_INT1_INT2_GEN;
break;
+
case IIS2DH_ON_INT1_TAP_GEN:
*val = IIS2DH_ON_INT1_TAP_GEN;
break;
+
case IIS2DH_ON_INT2_TAP_GEN:
*val = IIS2DH_ON_INT2_TAP_GEN;
break;
+
case IIS2DH_ON_INT1_INT2_TAP_GEN:
*val = IIS2DH_ON_INT1_INT2_TAP_GEN;
break;
+
default:
*val = IIS2DH_DISC_FROM_INT_GENERATOR;
break;
}
+
return ret;
}
@@ -1355,10 +1534,13 @@ int32_t iis2dh_high_pass_int_conf_get(stmdev_ctx_t *ctx, iis2dh_hp_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dh_pin_int1_config_set(stmdev_ctx_t *ctx, iis2dh_ctrl_reg3_t *val)
+int32_t iis2dh_pin_int1_config_set(stmdev_ctx_t *ctx,
+ iis2dh_ctrl_reg3_t *val)
{
int32_t ret;
- ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG3, (uint8_t*) val, 1);
+
+ ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG3, (uint8_t *) val, 1);
+
return ret;
}
@@ -1370,10 +1552,13 @@ int32_t iis2dh_pin_int1_config_set(stmdev_ctx_t *ctx, iis2dh_ctrl_reg3_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dh_pin_int1_config_get(stmdev_ctx_t *ctx, iis2dh_ctrl_reg3_t *val)
+int32_t iis2dh_pin_int1_config_get(stmdev_ctx_t *ctx,
+ iis2dh_ctrl_reg3_t *val)
{
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG3, (uint8_t*) val, 1);
+
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG3, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1391,11 +1576,14 @@ int32_t iis2dh_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.d4d_int2 = val;
- ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -1413,7 +1601,7 @@ int32_t iis2dh_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
*val = (uint8_t)ctrl_reg5.d4d_int2;
return ret;
@@ -1435,11 +1623,14 @@ int32_t iis2dh_int2_pin_notification_mode_set(stmdev_ctx_t *ctx,
iis2dh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.lir_int2 = (uint8_t)val;
- ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -1459,18 +1650,23 @@ int32_t iis2dh_int2_pin_notification_mode_get(stmdev_ctx_t *ctx,
iis2dh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- switch (ctrl_reg5.lir_int2) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
+
+ switch (ctrl_reg5.lir_int2)
+ {
case IIS2DH_INT2_PULSED:
*val = IIS2DH_INT2_PULSED;
break;
+
case IIS2DH_INT2_LATCHED:
*val = IIS2DH_INT2_LATCHED;
break;
+
default:
*val = IIS2DH_INT2_PULSED;
break;
}
+
return ret;
}
@@ -1488,11 +1684,14 @@ int32_t iis2dh_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.d4d_int1 = val;
- ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -1510,7 +1709,7 @@ int32_t iis2dh_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
*val = (uint8_t)ctrl_reg5.d4d_int1;
return ret;
@@ -1531,11 +1730,14 @@ int32_t iis2dh_int1_pin_notification_mode_set(stmdev_ctx_t *ctx,
iis2dh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.lir_int1 = (uint8_t)val;
- ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -1554,18 +1756,23 @@ int32_t iis2dh_int1_pin_notification_mode_get(stmdev_ctx_t *ctx,
iis2dh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- switch (ctrl_reg5.lir_int1) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
+
+ switch (ctrl_reg5.lir_int1)
+ {
case IIS2DH_INT1_PULSED:
*val = IIS2DH_INT1_PULSED;
break;
+
case IIS2DH_INT1_LATCHED:
*val = IIS2DH_INT1_LATCHED;
break;
+
default:
*val = IIS2DH_INT1_PULSED;
break;
}
+
return ret;
}
@@ -1577,10 +1784,13 @@ int32_t iis2dh_int1_pin_notification_mode_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dh_pin_int2_config_set(stmdev_ctx_t *ctx, iis2dh_ctrl_reg6_t *val)
+int32_t iis2dh_pin_int2_config_set(stmdev_ctx_t *ctx,
+ iis2dh_ctrl_reg6_t *val)
{
int32_t ret;
- ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG6, (uint8_t*) val, 1);
+
+ ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG6, (uint8_t *) val, 1);
+
return ret;
}
@@ -1592,10 +1802,13 @@ int32_t iis2dh_pin_int2_config_set(stmdev_ctx_t *ctx, iis2dh_ctrl_reg6_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dh_pin_int2_config_get(stmdev_ctx_t *ctx, iis2dh_ctrl_reg6_t *val)
+int32_t iis2dh_pin_int2_config_get(stmdev_ctx_t *ctx,
+ iis2dh_ctrl_reg6_t *val)
{
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG6, (uint8_t*) val, 1);
+
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG6, (uint8_t *) val, 1);
+
return ret;
}
@@ -1624,11 +1837,14 @@ int32_t iis2dh_fifo_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.fifo_en = val;
- ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -1645,7 +1861,7 @@ int32_t iis2dh_fifo_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
*val = (uint8_t)ctrl_reg5.fifo_en;
return ret;
@@ -1665,12 +1881,15 @@ int32_t iis2dh_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_CTRL_REG,
- (uint8_t*)&fifo_ctrl_reg, 1);
- if (ret == 0) {
+ (uint8_t *)&fifo_ctrl_reg, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl_reg.fth = val;
ret = iis2dh_write_reg(ctx, IIS2DH_FIFO_CTRL_REG,
- (uint8_t*)&fifo_ctrl_reg, 1);
+ (uint8_t *)&fifo_ctrl_reg, 1);
}
+
return ret;
}
@@ -1688,7 +1907,7 @@ int32_t iis2dh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_CTRL_REG,
- (uint8_t*)&fifo_ctrl_reg, 1);
+ (uint8_t *)&fifo_ctrl_reg, 1);
*val = (uint8_t)fifo_ctrl_reg.fth;
return ret;
@@ -1702,18 +1921,22 @@ int32_t iis2dh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dh_fifo_trigger_event_set(stmdev_ctx_t *ctx, iis2dh_tr_t val)
+int32_t iis2dh_fifo_trigger_event_set(stmdev_ctx_t *ctx,
+ iis2dh_tr_t val)
{
iis2dh_fifo_ctrl_reg_t fifo_ctrl_reg;
int32_t ret;
ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_CTRL_REG,
- (uint8_t*)&fifo_ctrl_reg, 1);
- if (ret == 0) {
+ (uint8_t *)&fifo_ctrl_reg, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl_reg.tr = (uint8_t)val;
ret = iis2dh_write_reg(ctx, IIS2DH_FIFO_CTRL_REG,
- (uint8_t*)&fifo_ctrl_reg, 1);
+ (uint8_t *)&fifo_ctrl_reg, 1);
}
+
return ret;
}
@@ -1725,24 +1948,30 @@ int32_t iis2dh_fifo_trigger_event_set(stmdev_ctx_t *ctx, iis2dh_tr_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dh_fifo_trigger_event_get(stmdev_ctx_t *ctx, iis2dh_tr_t *val)
+int32_t iis2dh_fifo_trigger_event_get(stmdev_ctx_t *ctx,
+ iis2dh_tr_t *val)
{
iis2dh_fifo_ctrl_reg_t fifo_ctrl_reg;
int32_t ret;
ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_CTRL_REG,
- (uint8_t*)&fifo_ctrl_reg, 1);
- switch (fifo_ctrl_reg.tr) {
+ (uint8_t *)&fifo_ctrl_reg, 1);
+
+ switch (fifo_ctrl_reg.tr)
+ {
case IIS2DH_INT1_GEN:
*val = IIS2DH_INT1_GEN;
break;
+
case IIS2DH_INT2_GEN:
*val = IIS2DH_INT2_GEN;
break;
+
default:
*val = IIS2DH_INT1_GEN;
break;
}
+
return ret;
}
@@ -1760,12 +1989,15 @@ int32_t iis2dh_fifo_mode_set(stmdev_ctx_t *ctx, iis2dh_fm_t val)
int32_t ret;
ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_CTRL_REG,
- (uint8_t*)&fifo_ctrl_reg, 1);
- if (ret == 0) {
+ (uint8_t *)&fifo_ctrl_reg, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl_reg.fm = (uint8_t)val;
ret = iis2dh_write_reg(ctx, IIS2DH_FIFO_CTRL_REG,
- (uint8_t*)&fifo_ctrl_reg, 1);
+ (uint8_t *)&fifo_ctrl_reg, 1);
}
+
return ret;
}
@@ -1783,24 +2015,31 @@ int32_t iis2dh_fifo_mode_get(stmdev_ctx_t *ctx, iis2dh_fm_t *val)
int32_t ret;
ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_CTRL_REG,
- (uint8_t*)&fifo_ctrl_reg, 1);
- switch (fifo_ctrl_reg.fm) {
+ (uint8_t *)&fifo_ctrl_reg, 1);
+
+ switch (fifo_ctrl_reg.fm)
+ {
case IIS2DH_BYPASS_MODE:
*val = IIS2DH_BYPASS_MODE;
break;
+
case IIS2DH_FIFO_MODE:
*val = IIS2DH_FIFO_MODE;
break;
+
case IIS2DH_DYNAMIC_STREAM_MODE:
*val = IIS2DH_DYNAMIC_STREAM_MODE;
break;
+
case IIS2DH_STREAM_TO_FIFO_MODE:
*val = IIS2DH_STREAM_TO_FIFO_MODE;
break;
+
default:
*val = IIS2DH_BYPASS_MODE;
break;
}
+
return ret;
}
@@ -1812,10 +2051,13 @@ int32_t iis2dh_fifo_mode_get(stmdev_ctx_t *ctx, iis2dh_fm_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dh_fifo_status_get(stmdev_ctx_t *ctx, iis2dh_fifo_src_reg_t *val)
+int32_t iis2dh_fifo_status_get(stmdev_ctx_t *ctx,
+ iis2dh_fifo_src_reg_t *val)
{
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_SRC_REG, (uint8_t*) val, 1);
+
+ ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_SRC_REG, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1831,7 +2073,8 @@ int32_t iis2dh_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dh_fifo_src_reg_t fifo_src_reg;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1);
+ ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_SRC_REG,
+ (uint8_t *)&fifo_src_reg, 1);
*val = (uint8_t)fifo_src_reg.fss;
return ret;
@@ -1849,7 +2092,8 @@ int32_t iis2dh_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dh_fifo_src_reg_t fifo_src_reg;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1);
+ ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_SRC_REG,
+ (uint8_t *)&fifo_src_reg, 1);
*val = (uint8_t)fifo_src_reg.empty;
return ret;
@@ -1867,7 +2111,8 @@ int32_t iis2dh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dh_fifo_src_reg_t fifo_src_reg;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1);
+ ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_SRC_REG,
+ (uint8_t *)&fifo_src_reg, 1);
*val = (uint8_t)fifo_src_reg.ovrn_fifo;
return ret;
@@ -1885,7 +2130,8 @@ int32_t iis2dh_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dh_fifo_src_reg_t fifo_src_reg;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1);
+ ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_SRC_REG,
+ (uint8_t *)&fifo_src_reg, 1);
*val = (uint8_t)fifo_src_reg.wtm;
return ret;
@@ -1911,10 +2157,13 @@ int32_t iis2dh_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dh_tap_conf_set(stmdev_ctx_t *ctx, iis2dh_click_cfg_t *val)
+int32_t iis2dh_tap_conf_set(stmdev_ctx_t *ctx,
+ iis2dh_click_cfg_t *val)
{
int32_t ret;
- ret = iis2dh_write_reg(ctx, IIS2DH_CLICK_CFG, (uint8_t*) val, 1);
+
+ ret = iis2dh_write_reg(ctx, IIS2DH_CLICK_CFG, (uint8_t *) val, 1);
+
return ret;
}
@@ -1926,10 +2175,13 @@ int32_t iis2dh_tap_conf_set(stmdev_ctx_t *ctx, iis2dh_click_cfg_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dh_tap_conf_get(stmdev_ctx_t *ctx, iis2dh_click_cfg_t *val)
+int32_t iis2dh_tap_conf_get(stmdev_ctx_t *ctx,
+ iis2dh_click_cfg_t *val)
{
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CLICK_CFG, (uint8_t*) val, 1);
+
+ ret = iis2dh_read_reg(ctx, IIS2DH_CLICK_CFG, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1940,10 +2192,13 @@ int32_t iis2dh_tap_conf_get(stmdev_ctx_t *ctx, iis2dh_click_cfg_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dh_tap_source_get(stmdev_ctx_t *ctx, iis2dh_click_src_t *val)
+int32_t iis2dh_tap_source_get(stmdev_ctx_t *ctx,
+ iis2dh_click_src_t *val)
{
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CLICK_SRC, (uint8_t*) val, 1);
+
+ ret = iis2dh_read_reg(ctx, IIS2DH_CLICK_SRC, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1960,11 +2215,14 @@ int32_t iis2dh_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dh_click_ths_t click_ths;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CLICK_THS, (uint8_t*)&click_ths, 1);
- if (ret == 0) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_CLICK_THS, (uint8_t *)&click_ths, 1);
+
+ if (ret == 0)
+ {
click_ths.ths = val;
- ret = iis2dh_write_reg(ctx, IIS2DH_CLICK_THS, (uint8_t*)&click_ths, 1);
+ ret = iis2dh_write_reg(ctx, IIS2DH_CLICK_THS, (uint8_t *)&click_ths, 1);
}
+
return ret;
}
@@ -1982,7 +2240,7 @@ int32_t iis2dh_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dh_click_ths_t click_ths;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CLICK_THS, (uint8_t*)&click_ths, 1);
+ ret = iis2dh_read_reg(ctx, IIS2DH_CLICK_THS, (uint8_t *)&click_ths, 1);
*val = (uint8_t)click_ths.ths;
return ret;
@@ -2003,11 +2261,14 @@ int32_t iis2dh_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dh_time_limit_t time_limit;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_TIME_LIMIT, (uint8_t*)&time_limit, 1);
- if (ret == 0) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_TIME_LIMIT, (uint8_t *)&time_limit, 1);
+
+ if (ret == 0)
+ {
time_limit.tli = val;
- ret = iis2dh_write_reg(ctx, IIS2DH_TIME_LIMIT, (uint8_t*)&time_limit, 1);
+ ret = iis2dh_write_reg(ctx, IIS2DH_TIME_LIMIT, (uint8_t *)&time_limit, 1);
}
+
return ret;
}
@@ -2026,7 +2287,7 @@ int32_t iis2dh_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dh_time_limit_t time_limit;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_TIME_LIMIT, (uint8_t*)&time_limit, 1);
+ ret = iis2dh_read_reg(ctx, IIS2DH_TIME_LIMIT, (uint8_t *)&time_limit, 1);
*val = (uint8_t)time_limit.tli;
return ret;
@@ -2048,12 +2309,16 @@ int32_t iis2dh_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dh_time_latency_t time_latency;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_TIME_LATENCY, (uint8_t*)&time_latency, 1);
- if (ret == 0) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_TIME_LATENCY,
+ (uint8_t *)&time_latency, 1);
+
+ if (ret == 0)
+ {
time_latency.tla = val;
ret = iis2dh_write_reg(ctx, IIS2DH_TIME_LATENCY,
- (uint8_t*)&time_latency, 1);
+ (uint8_t *)&time_latency, 1);
}
+
return ret;
}
@@ -2073,7 +2338,8 @@ int32_t iis2dh_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dh_time_latency_t time_latency;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_TIME_LATENCY, (uint8_t*)&time_latency, 1);
+ ret = iis2dh_read_reg(ctx, IIS2DH_TIME_LATENCY,
+ (uint8_t *)&time_latency, 1);
*val = (uint8_t)time_latency.tla;
return ret;
@@ -2095,11 +2361,16 @@ int32_t iis2dh_double_tap_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dh_time_window_t time_window;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_TIME_WINDOW, (uint8_t*)&time_window, 1);
- if (ret == 0) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_TIME_WINDOW,
+ (uint8_t *)&time_window, 1);
+
+ if (ret == 0)
+ {
time_window.tw = val;
- ret = iis2dh_write_reg(ctx, IIS2DH_TIME_WINDOW, (uint8_t*)&time_window, 1);
+ ret = iis2dh_write_reg(ctx, IIS2DH_TIME_WINDOW,
+ (uint8_t *)&time_window, 1);
}
+
return ret;
}
@@ -2119,7 +2390,8 @@ int32_t iis2dh_double_tap_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dh_time_window_t time_window;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_TIME_WINDOW, (uint8_t*)&time_window, 1);
+ ret = iis2dh_read_reg(ctx, IIS2DH_TIME_WINDOW,
+ (uint8_t *)&time_window, 1);
*val = (uint8_t)time_window.tw;
return ret;
@@ -2153,11 +2425,14 @@ int32_t iis2dh_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dh_act_ths_t act_ths;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_ACT_THS, (uint8_t*)&act_ths, 1);
- if (ret == 0) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_ACT_THS, (uint8_t *)&act_ths, 1);
+
+ if (ret == 0)
+ {
act_ths.acth = val;
- ret = iis2dh_write_reg(ctx, IIS2DH_ACT_THS, (uint8_t*)&act_ths, 1);
+ ret = iis2dh_write_reg(ctx, IIS2DH_ACT_THS, (uint8_t *)&act_ths, 1);
}
+
return ret;
}
@@ -2176,7 +2451,7 @@ int32_t iis2dh_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dh_act_ths_t act_ths;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_ACT_THS, (uint8_t*)&act_ths, 1);
+ ret = iis2dh_read_reg(ctx, IIS2DH_ACT_THS, (uint8_t *)&act_ths, 1);
*val = (uint8_t)act_ths.acth;
return ret;
@@ -2196,11 +2471,14 @@ int32_t iis2dh_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dh_act_dur_t act_dur;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_ACT_DUR, (uint8_t*)&act_dur, 1);
- if (ret == 0) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_ACT_DUR, (uint8_t *)&act_dur, 1);
+
+ if (ret == 0)
+ {
act_dur.actd = val;
- ret = iis2dh_write_reg(ctx, IIS2DH_ACT_DUR, (uint8_t*)&act_dur, 1);
+ ret = iis2dh_write_reg(ctx, IIS2DH_ACT_DUR, (uint8_t *)&act_dur, 1);
}
+
return ret;
}
@@ -2218,7 +2496,7 @@ int32_t iis2dh_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dh_act_dur_t act_dur;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_ACT_DUR, (uint8_t*)&act_dur, 1);
+ ret = iis2dh_read_reg(ctx, IIS2DH_ACT_DUR, (uint8_t *)&act_dur, 1);
*val = (uint8_t)act_dur.actd;
return ret;
@@ -2250,11 +2528,14 @@ int32_t iis2dh_spi_mode_set(stmdev_ctx_t *ctx, iis2dh_sim_t val)
iis2dh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if (ret == 0) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.sim = (uint8_t)val;
- ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -2271,18 +2552,23 @@ int32_t iis2dh_spi_mode_get(stmdev_ctx_t *ctx, iis2dh_sim_t *val)
iis2dh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- switch (ctrl_reg4.sim) {
+ ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ switch (ctrl_reg4.sim)
+ {
case IIS2DH_SPI_4_WIRE:
*val = IIS2DH_SPI_4_WIRE;
break;
+
case IIS2DH_SPI_3_WIRE:
*val = IIS2DH_SPI_3_WIRE;
break;
+
default:
*val = IIS2DH_SPI_4_WIRE;
break;
}
+
return ret;
}
diff --git a/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.h b/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.h
index 3b3e27c74a3fff62f550206ac9fe52979fef44b2..587466d9d4293447245a1f1c60b9af8431fde1f6 100644
--- a/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.h
+++ b/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file iis2dh_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * iis2dh_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file iis2dh_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * iis2dh_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef IIS2DH_REGS_H
#define IIS2DH_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup IIS2DH
@@ -74,7 +75,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -107,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -131,15 +134,16 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
- * Unico / Unicleo tools available on STMicroelectronics
- * web site.
+ * You can create a sensor configuration by your own or using
+ * Unico / Unicleo tools available on STMicroelectronics
+ * web site.
*
* @{
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -174,7 +178,8 @@ typedef struct {
*/
#define IIS2DH_STATUS_REG_AUX 0x07U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t tda : 1;
@@ -196,7 +201,8 @@ typedef struct {
#define IIS2DH_WHO_AM_I 0x0FU
#define IIS2DH_TEMP_CFG_REG 0x1FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 6;
uint8_t temp_en : 2;
@@ -207,7 +213,8 @@ typedef struct {
} iis2dh_temp_cfg_reg_t;
#define IIS2DH_CTRL_REG1 0x20U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xen : 1;
uint8_t yen : 1;
@@ -224,7 +231,8 @@ typedef struct {
} iis2dh_ctrl_reg1_t;
#define IIS2DH_CTRL_REG2 0x21U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t hp : 3; /* HPCLICK + HPIS2 + HPIS1 -> HP */
uint8_t fds : 1;
@@ -239,7 +247,8 @@ typedef struct {
} iis2dh_ctrl_reg2_t;
#define IIS2DH_CTRL_REG3 0x22U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t i1_overrun : 1;
@@ -262,7 +271,8 @@ typedef struct {
} iis2dh_ctrl_reg3_t;
#define IIS2DH_CTRL_REG4 0x23U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t st : 2;
@@ -281,7 +291,8 @@ typedef struct {
} iis2dh_ctrl_reg4_t;
#define IIS2DH_CTRL_REG5 0x24U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d4d_int2 : 1;
uint8_t lir_int2 : 1;
@@ -302,7 +313,8 @@ typedef struct {
} iis2dh_ctrl_reg5_t;
#define IIS2DH_CTRL_REG6 0x25U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t h_lactive : 1;
@@ -326,7 +338,8 @@ typedef struct {
#define IIS2DH_REFERENCE 0x26U
#define IIS2DH_STATUS_REG 0x27U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xda : 1;
uint8_t yda : 1;
@@ -355,7 +368,8 @@ typedef struct {
#define IIS2DH_OUT_Z_L 0x2CU
#define IIS2DH_OUT_Z_H 0x2DU
#define IIS2DH_FIFO_CTRL_REG 0x2EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fth : 5;
uint8_t tr : 1;
@@ -368,7 +382,8 @@ typedef struct {
} iis2dh_fifo_ctrl_reg_t;
#define IIS2DH_FIFO_SRC_REG 0x2FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fss : 5;
uint8_t empty : 1;
@@ -383,7 +398,8 @@ typedef struct {
} iis2dh_fifo_src_reg_t;
#define IIS2DH_INT1_CFG 0x30U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlie : 1;
uint8_t xhie : 1;
@@ -406,7 +422,8 @@ typedef struct {
} iis2dh_int1_cfg_t;
#define IIS2DH_INT1_SRC 0x31U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
@@ -429,7 +446,8 @@ typedef struct {
} iis2dh_int1_src_t;
#define IIS2DH_INT1_THS 0x32U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t not_used_01 : 1;
@@ -440,7 +458,8 @@ typedef struct {
} iis2dh_int1_ths_t;
#define IIS2DH_INT1_DURATION 0x33U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d : 7;
uint8_t not_used_01 : 1;
@@ -451,7 +470,8 @@ typedef struct {
} iis2dh_int1_duration_t;
#define IIS2DH_INT2_CFG 0x34U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlie : 1;
uint8_t xhie : 1;
@@ -474,7 +494,8 @@ typedef struct {
} iis2dh_int2_cfg_t;
#define IIS2DH_INT2_SRC 0x35U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
@@ -497,7 +518,8 @@ typedef struct {
} iis2dh_int2_src_t;
#define IIS2DH_INT2_THS 0x36U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t not_used_01 : 1;
@@ -508,7 +530,8 @@ typedef struct {
} iis2dh_int2_ths_t;
#define IIS2DH_INT2_DURATION 0x37U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d : 7;
uint8_t not_used_01 : 1;
@@ -517,7 +540,8 @@ typedef struct {
} iis2dh_int2_duration_t;
#define IIS2DH_CLICK_CFG 0x38U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xs : 1;
uint8_t xd : 1;
@@ -538,7 +562,8 @@ typedef struct {
} iis2dh_click_cfg_t;
#define IIS2DH_CLICK_SRC 0x39U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t x : 1;
uint8_t y : 1;
@@ -561,7 +586,8 @@ typedef struct {
} iis2dh_click_src_t;
#define IIS2DH_CLICK_THS 0x3AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t not_used_01 : 1;
@@ -572,7 +598,8 @@ typedef struct {
} iis2dh_click_ths_t;
#define IIS2DH_TIME_LIMIT 0x3BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tli : 7;
uint8_t not_used_01 : 1;
@@ -583,17 +610,20 @@ typedef struct {
} iis2dh_time_limit_t;
#define IIS2DH_TIME_LATENCY 0x3CU
-typedef struct {
+typedef struct
+{
uint8_t tla : 8;
} iis2dh_time_latency_t;
#define IIS2DH_TIME_WINDOW 0x3DU
-typedef struct {
+typedef struct
+{
uint8_t tw : 8;
} iis2dh_time_window_t;
#define IIS2DH_ACT_THS 0x3EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t acth : 7;
uint8_t not_used_01 : 1;
@@ -604,23 +634,25 @@ typedef struct {
} iis2dh_act_ths_t;
#define IIS2DH_ACT_DUR 0x3FU
-typedef struct {
+typedef struct
+{
uint8_t actd : 8;
} iis2dh_act_dur_t;
/**
* @defgroup IIS2DH_Register_Union
- * @brief This union group all the registers that has a bitfield
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is usefull but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
- * REMOVING this union you are complient with:
+ * REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
*
* @{
*
*/
-typedef union{
+typedef union
+{
iis2dh_status_reg_aux_t status_reg_aux;
iis2dh_temp_cfg_reg_t temp_cfg_reg;
iis2dh_ctrl_reg1_t ctrl_reg1;
@@ -657,9 +689,10 @@ typedef union{
*
*/
-int32_t iis2dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t iis2dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
uint16_t len);
-int32_t iis2dh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t iis2dh_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
float_t iis2dh_from_fs2_hr_to_mg(int16_t lsb);
@@ -687,22 +720,29 @@ int32_t iis2dh_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t iis2dh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val);
-typedef enum {
+typedef enum
+{
IIS2DH_TEMP_DISABLE = 0,
IIS2DH_TEMP_ENABLE = 3,
} iis2dh_temp_en_t;
-int32_t iis2dh_temperature_meas_set(stmdev_ctx_t *ctx, iis2dh_temp_en_t val);
-int32_t iis2dh_temperature_meas_get(stmdev_ctx_t *ctx, iis2dh_temp_en_t *val);
+int32_t iis2dh_temperature_meas_set(stmdev_ctx_t *ctx,
+ iis2dh_temp_en_t val);
+int32_t iis2dh_temperature_meas_get(stmdev_ctx_t *ctx,
+ iis2dh_temp_en_t *val);
-typedef enum {
+typedef enum
+{
IIS2DH_HR_12bit = 0,
IIS2DH_NM_10bit = 1,
IIS2DH_LP_8bit = 2,
} iis2dh_op_md_t;
-int32_t iis2dh_operating_mode_set(stmdev_ctx_t *ctx, iis2dh_op_md_t val);
-int32_t iis2dh_operating_mode_get(stmdev_ctx_t *ctx, iis2dh_op_md_t *val);
+int32_t iis2dh_operating_mode_set(stmdev_ctx_t *ctx,
+ iis2dh_op_md_t val);
+int32_t iis2dh_operating_mode_get(stmdev_ctx_t *ctx,
+ iis2dh_op_md_t *val);
-typedef enum {
+typedef enum
+{
IIS2DH_POWER_DOWN = 0x00,
IIS2DH_ODR_1Hz = 0x01,
IIS2DH_ODR_10Hz = 0x02,
@@ -717,28 +757,37 @@ typedef enum {
int32_t iis2dh_data_rate_set(stmdev_ctx_t *ctx, iis2dh_odr_t val);
int32_t iis2dh_data_rate_get(stmdev_ctx_t *ctx, iis2dh_odr_t *val);
-int32_t iis2dh_high_pass_on_outputs_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis2dh_high_pass_on_outputs_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis2dh_high_pass_on_outputs_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t iis2dh_high_pass_on_outputs_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS2DH_AGGRESSIVE = 0,
IIS2DH_STRONG = 1,
IIS2DH_MEDIUM = 2,
IIS2DH_LIGHT = 3,
} iis2dh_hpcf_t;
-int32_t iis2dh_high_pass_bandwidth_set(stmdev_ctx_t *ctx, iis2dh_hpcf_t val);
-int32_t iis2dh_high_pass_bandwidth_get(stmdev_ctx_t *ctx, iis2dh_hpcf_t *val);
+int32_t iis2dh_high_pass_bandwidth_set(stmdev_ctx_t *ctx,
+ iis2dh_hpcf_t val);
+int32_t iis2dh_high_pass_bandwidth_get(stmdev_ctx_t *ctx,
+ iis2dh_hpcf_t *val);
-typedef enum {
+typedef enum
+{
IIS2DH_NORMAL_WITH_RST = 0,
IIS2DH_REFERENCE_MODE = 1,
IIS2DH_NORMAL = 2,
IIS2DH_AUTORST_ON_INT = 3,
} iis2dh_hpm_t;
-int32_t iis2dh_high_pass_mode_set(stmdev_ctx_t *ctx, iis2dh_hpm_t val);
-int32_t iis2dh_high_pass_mode_get(stmdev_ctx_t *ctx, iis2dh_hpm_t *val);
+int32_t iis2dh_high_pass_mode_set(stmdev_ctx_t *ctx,
+ iis2dh_hpm_t val);
+int32_t iis2dh_high_pass_mode_get(stmdev_ctx_t *ctx,
+ iis2dh_hpm_t *val);
-typedef enum {
+typedef enum
+{
IIS2DH_2g = 0,
IIS2DH_4g = 1,
IIS2DH_8g = 2,
@@ -761,7 +810,8 @@ int32_t iis2dh_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val);
int32_t iis2dh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
-typedef enum {
+typedef enum
+{
IIS2DH_ST_DISABLE = 0,
IIS2DH_ST_POSITIVE = 1,
IIS2DH_ST_NEGATIVE = 2,
@@ -769,7 +819,8 @@ typedef enum {
int32_t iis2dh_self_test_set(stmdev_ctx_t *ctx, iis2dh_st_t val);
int32_t iis2dh_self_test_get(stmdev_ctx_t *ctx, iis2dh_st_t *val);
-typedef enum {
+typedef enum
+{
IIS2DH_LSB_AT_LOW_ADD = 0,
IIS2DH_MSB_AT_LOW_ADD = 1,
} iis2dh_ble_t;
@@ -780,31 +831,41 @@ int32_t iis2dh_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2dh_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t iis2dh_int_occurrencies_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t iis2dh_status_get(stmdev_ctx_t *ctx, iis2dh_status_reg_t *val);
+int32_t iis2dh_status_get(stmdev_ctx_t *ctx,
+ iis2dh_status_reg_t *val);
-int32_t iis2dh_int1_gen_conf_set(stmdev_ctx_t *ctx, iis2dh_int1_cfg_t *val);
-int32_t iis2dh_int1_gen_conf_get(stmdev_ctx_t *ctx, iis2dh_int1_cfg_t *val);
+int32_t iis2dh_int1_gen_conf_set(stmdev_ctx_t *ctx,
+ iis2dh_int1_cfg_t *val);
+int32_t iis2dh_int1_gen_conf_get(stmdev_ctx_t *ctx,
+ iis2dh_int1_cfg_t *val);
-int32_t iis2dh_int1_gen_source_get(stmdev_ctx_t *ctx, iis2dh_int1_src_t *val);
+int32_t iis2dh_int1_gen_source_get(stmdev_ctx_t *ctx,
+ iis2dh_int1_src_t *val);
int32_t iis2dh_int1_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis2dh_int1_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis2dh_int1_gen_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t iis2dh_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2dh_int1_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t iis2dh_int2_gen_conf_set(stmdev_ctx_t *ctx, iis2dh_int2_cfg_t *val);
-int32_t iis2dh_int2_gen_conf_get(stmdev_ctx_t *ctx, iis2dh_int2_cfg_t *val);
+int32_t iis2dh_int2_gen_conf_set(stmdev_ctx_t *ctx,
+ iis2dh_int2_cfg_t *val);
+int32_t iis2dh_int2_gen_conf_get(stmdev_ctx_t *ctx,
+ iis2dh_int2_cfg_t *val);
-int32_t iis2dh_int2_gen_source_get(stmdev_ctx_t *ctx, iis2dh_int2_src_t *val);
+int32_t iis2dh_int2_gen_source_get(stmdev_ctx_t *ctx,
+ iis2dh_int2_src_t *val);
int32_t iis2dh_int2_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis2dh_int2_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis2dh_int2_gen_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t iis2dh_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2dh_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS2DH_DISC_FROM_INT_GENERATOR = 0,
IIS2DH_ON_INT1_GEN = 1,
IIS2DH_ON_INT2_GEN = 2,
@@ -814,8 +875,10 @@ typedef enum {
IIS2DH_ON_INT2_TAP_GEN = 6,
IIS2DH_ON_INT1_INT2_TAP_GEN = 7,
} iis2dh_hp_t;
-int32_t iis2dh_high_pass_int_conf_set(stmdev_ctx_t *ctx, iis2dh_hp_t val);
-int32_t iis2dh_high_pass_int_conf_get(stmdev_ctx_t *ctx, iis2dh_hp_t *val);
+int32_t iis2dh_high_pass_int_conf_set(stmdev_ctx_t *ctx,
+ iis2dh_hp_t val);
+int32_t iis2dh_high_pass_int_conf_get(stmdev_ctx_t *ctx,
+ iis2dh_hp_t *val);
int32_t iis2dh_pin_int1_config_set(stmdev_ctx_t *ctx,
iis2dh_ctrl_reg3_t *val);
@@ -823,9 +886,11 @@ int32_t iis2dh_pin_int1_config_get(stmdev_ctx_t *ctx,
iis2dh_ctrl_reg3_t *val);
int32_t iis2dh_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis2dh_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis2dh_int2_pin_detect_4d_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS2DH_INT2_PULSED = 0,
IIS2DH_INT2_LATCHED = 1,
} iis2dh_lir_int2_t;
@@ -835,9 +900,11 @@ int32_t iis2dh_int2_pin_notification_mode_get(stmdev_ctx_t *ctx,
iis2dh_lir_int2_t *val);
int32_t iis2dh_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis2dh_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis2dh_int1_pin_detect_4d_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS2DH_INT1_PULSED = 0,
IIS2DH_INT1_LATCHED = 1,
} iis2dh_lir_int1_t;
@@ -857,14 +924,18 @@ int32_t iis2dh_fifo_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t iis2dh_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2dh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS2DH_INT1_GEN = 0,
IIS2DH_INT2_GEN = 1,
} iis2dh_tr_t;
-int32_t iis2dh_fifo_trigger_event_set(stmdev_ctx_t *ctx, iis2dh_tr_t val);
-int32_t iis2dh_fifo_trigger_event_get(stmdev_ctx_t *ctx, iis2dh_tr_t *val);
+int32_t iis2dh_fifo_trigger_event_set(stmdev_ctx_t *ctx,
+ iis2dh_tr_t val);
+int32_t iis2dh_fifo_trigger_event_get(stmdev_ctx_t *ctx,
+ iis2dh_tr_t *val);
-typedef enum {
+typedef enum
+{
IIS2DH_BYPASS_MODE = 0,
IIS2DH_FIFO_MODE = 1,
IIS2DH_DYNAMIC_STREAM_MODE = 2,
@@ -874,7 +945,7 @@ int32_t iis2dh_fifo_mode_set(stmdev_ctx_t *ctx, iis2dh_fm_t val);
int32_t iis2dh_fifo_mode_get(stmdev_ctx_t *ctx, iis2dh_fm_t *val);
int32_t iis2dh_fifo_status_get(stmdev_ctx_t *ctx,
- iis2dh_fifo_src_reg_t *val);
+ iis2dh_fifo_src_reg_t *val);
int32_t iis2dh_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -884,15 +955,19 @@ int32_t iis2dh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t iis2dh_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t iis2dh_tap_conf_set(stmdev_ctx_t *ctx, iis2dh_click_cfg_t *val);
-int32_t iis2dh_tap_conf_get(stmdev_ctx_t *ctx, iis2dh_click_cfg_t *val);
+int32_t iis2dh_tap_conf_set(stmdev_ctx_t *ctx,
+ iis2dh_click_cfg_t *val);
+int32_t iis2dh_tap_conf_get(stmdev_ctx_t *ctx,
+ iis2dh_click_cfg_t *val);
-int32_t iis2dh_tap_source_get(stmdev_ctx_t *ctx, iis2dh_click_src_t *val);
+int32_t iis2dh_tap_source_get(stmdev_ctx_t *ctx,
+ iis2dh_click_src_t *val);
int32_t iis2dh_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2dh_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS2DH_TAP_PULSED = 0,
IIS2DH_TAP_LATCHED = 1,
} iis2dh_lir_click_t;
@@ -908,7 +983,8 @@ int32_t iis2dh_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2dh_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t iis2dh_double_tap_timeout_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis2dh_double_tap_timeout_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis2dh_double_tap_timeout_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t iis2dh_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2dh_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -916,7 +992,8 @@ int32_t iis2dh_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t iis2dh_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2dh_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS2DH_PULL_UP_DISCONNECT = 0,
IIS2DH_PULL_UP_CONNECT = 1,
} iis2dh_sdo_pu_disc_t;
@@ -925,7 +1002,8 @@ int32_t iis2dh_pin_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
int32_t iis2dh_pin_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
iis2dh_sdo_pu_disc_t *val);
-typedef enum {
+typedef enum
+{
IIS2DH_SPI_4_WIRE = 0,
IIS2DH_SPI_3_WIRE = 1,
} iis2dh_sim_t;
diff --git a/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.c b/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.c
index 00f94b449645f056d83931a1f6b056cbc0e6c3d2..8cf67d85ccec64f352c84c3b3c747a2c9e3df042 100644
--- a/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.c
+++ b/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file iis2dlpc_reg.c
- * @author Sensors Software Solution Team
- * @brief IIS2DLPC driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file iis2dlpc_reg.c
+ * @author Sensors Software Solution Team
+ * @brief IIS2DLPC driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "iis2dlpc_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dlpc_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t iis2dlpc_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t iis2dlpc_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dlpc_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t iis2dlpc_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -77,7 +83,7 @@ int32_t iis2dlpc_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
*
*/
- /**
+/**
* @defgroup IIS2DLPC_Sensitivity
* @brief These functions convert raw-data into engineering units.
* @{
@@ -101,7 +107,7 @@ float_t iis2dlpc_from_fs8_to_mg(int16_t lsb)
float_t iis2dlpc_from_fs16_to_mg(int16_t lsb)
{
- return ((float_t)lsb) *0.488f;
+ return ((float_t)lsb) * 0.488f;
}
float_t iis2dlpc_from_fs2_lp1_to_mg(int16_t lsb)
@@ -126,7 +132,7 @@ float_t iis2dlpc_from_fs16_lp1_to_mg(int16_t lsb)
float_t iis2dlpc_from_lsb_to_celsius(int16_t lsb)
{
- return (((float_t)lsb / 16.0f) + 25.0f);
+ return (((float_t)lsb / 256.0f) + 25.0f);
}
/**
@@ -151,27 +157,38 @@ float_t iis2dlpc_from_lsb_to_celsius(int16_t lsb)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dlpc_power_mode_set(stmdev_ctx_t *ctx, iis2dlpc_mode_t val)
+int32_t iis2dlpc_power_mode_set(stmdev_ctx_t *ctx,
+ iis2dlpc_mode_t val)
{
iis2dlpc_ctrl1_t ctrl1;
iis2dlpc_ctrl6_t ctrl6;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL1,(uint8_t*) &ctrl1, 1);
- if (ret == 0) {
- ctrl1.mode = ( (uint8_t) val & 0x0CU ) >> 2;
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL1, (uint8_t *) &ctrl1, 1);
+
+ if (ret == 0)
+ {
+ ctrl1.mode = ((uint8_t) val & 0x0CU) >> 2;
ctrl1.lp_mode = (uint8_t) val & 0x03U ;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL1,(uint8_t*) &ctrl1, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL1, (uint8_t *) &ctrl1, 1);
}
- if (ret == 0) {
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &ctrl6, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6, (uint8_t *) &ctrl6, 1);
+ }
+
+ if (ret == 0)
+ {
+ ctrl6.low_noise = ((uint8_t) val & 0x10U) >> 4;
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL6, (uint8_t *) &ctrl6, 1);
}
- if (ret == 0) {
- ctrl6.low_noise = ( (uint8_t) val & 0x10U ) >> 4;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &ctrl6, 1);
- } else {
+
+ else
+ {
ret = ret;
}
+
return ret;
}
@@ -184,77 +201,100 @@ int32_t iis2dlpc_power_mode_set(stmdev_ctx_t *ctx, iis2dlpc_mode_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dlpc_power_mode_get(stmdev_ctx_t *ctx, iis2dlpc_mode_t *val)
+int32_t iis2dlpc_power_mode_get(stmdev_ctx_t *ctx,
+ iis2dlpc_mode_t *val)
{
iis2dlpc_ctrl1_t ctrl1;
iis2dlpc_ctrl6_t ctrl6;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL1,(uint8_t*) &ctrl1, 1);
- if (ret == 0) {
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &ctrl6, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL1, (uint8_t *) &ctrl1, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6, (uint8_t *) &ctrl6, 1);
switch (((ctrl6.low_noise << 4) + (ctrl1.mode << 2) +
- ctrl1.lp_mode)) {
+ ctrl1.lp_mode))
+ {
case IIS2DLPC_HIGH_PERFORMANCE:
*val = IIS2DLPC_HIGH_PERFORMANCE;
break;
+
case IIS2DLPC_CONT_LOW_PWR_4:
*val = IIS2DLPC_CONT_LOW_PWR_4;
break;
+
case IIS2DLPC_CONT_LOW_PWR_3:
*val = IIS2DLPC_CONT_LOW_PWR_3;
break;
+
case IIS2DLPC_CONT_LOW_PWR_2:
*val = IIS2DLPC_CONT_LOW_PWR_2;
break;
+
case IIS2DLPC_CONT_LOW_PWR_12bit:
*val = IIS2DLPC_CONT_LOW_PWR_12bit;
break;
+
case IIS2DLPC_SINGLE_LOW_PWR_4:
*val = IIS2DLPC_SINGLE_LOW_PWR_4;
break;
+
case IIS2DLPC_SINGLE_LOW_PWR_3:
*val = IIS2DLPC_SINGLE_LOW_PWR_3;
break;
+
case IIS2DLPC_SINGLE_LOW_PWR_2:
*val = IIS2DLPC_SINGLE_LOW_PWR_2;
break;
+
case IIS2DLPC_SINGLE_LOW_PWR_12bit:
*val = IIS2DLPC_SINGLE_LOW_PWR_12bit;
break;
+
case IIS2DLPC_HIGH_PERFORMANCE_LOW_NOISE:
*val = IIS2DLPC_HIGH_PERFORMANCE_LOW_NOISE;
break;
+
case IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_4:
*val = IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_4;
break;
+
case IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_3:
*val = IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_3;
break;
+
case IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_2:
*val = IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_2;
break;
+
case IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_12bit:
*val = IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_12bit;
break;
+
case IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_4:
*val = IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_4;
break;
+
case IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_3:
*val = IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_3;
break;
+
case IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_2:
*val = IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_2;
break;
+
case IIS2DLPC_SINGLE_LOW_LOW_NOISE_PWR_12bit:
*val = IIS2DLPC_SINGLE_LOW_LOW_NOISE_PWR_12bit;
break;
+
default:
*val = IIS2DLPC_HIGH_PERFORMANCE;
break;
}
}
+
return ret;
}
@@ -272,20 +312,30 @@ int32_t iis2dlpc_data_rate_set(stmdev_ctx_t *ctx, iis2dlpc_odr_t val)
iis2dlpc_ctrl3_t ctrl3;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL1,(uint8_t*) &ctrl1, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL1, (uint8_t *) &ctrl1, 1);
+
+ if (ret == 0)
+ {
ctrl1.odr = (uint8_t) val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL1,(uint8_t*) &ctrl1, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL1, (uint8_t *) &ctrl1, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) &ctrl3, 1);
}
- if (ret == 0) {
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &ctrl3, 1);
+
+ if (ret == 0)
+ {
+ ctrl3.slp_mode = ((uint8_t) val & 0x30U) >> 4;
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) &ctrl3, 1);
}
- if (ret == 0) {
- ctrl3.slp_mode = ( (uint8_t) val & 0x30U ) >> 4;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &ctrl3, 1);
- } else {
+
+ else
+ {
ret = ret;
}
+
return ret;
}
@@ -303,52 +353,68 @@ int32_t iis2dlpc_data_rate_get(stmdev_ctx_t *ctx, iis2dlpc_odr_t *val)
iis2dlpc_ctrl3_t ctrl3;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL1,(uint8_t*) &ctrl1, 1);
- if (ret == 0) {
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &ctrl3, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL1, (uint8_t *) &ctrl1, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) &ctrl3, 1);
- switch ((ctrl3.slp_mode << 4) + ctrl1.odr) {
+ switch ((ctrl3.slp_mode << 4) + ctrl1.odr)
+ {
case IIS2DLPC_XL_ODR_OFF:
*val = IIS2DLPC_XL_ODR_OFF;
break;
+
case IIS2DLPC_XL_ODR_1Hz6_LP_ONLY:
*val = IIS2DLPC_XL_ODR_1Hz6_LP_ONLY;
break;
+
case IIS2DLPC_XL_ODR_12Hz5:
*val = IIS2DLPC_XL_ODR_12Hz5;
break;
+
case IIS2DLPC_XL_ODR_25Hz:
*val = IIS2DLPC_XL_ODR_25Hz;
break;
- case IIS2DLPC_XL_ODR_50Hz:
+
+ case IIS2DLPC_XL_ODR_50Hz:
*val = IIS2DLPC_XL_ODR_50Hz;
break;
+
case IIS2DLPC_XL_ODR_100Hz:
*val = IIS2DLPC_XL_ODR_100Hz;
break;
+
case IIS2DLPC_XL_ODR_200Hz:
*val = IIS2DLPC_XL_ODR_200Hz;
break;
+
case IIS2DLPC_XL_ODR_400Hz:
*val = IIS2DLPC_XL_ODR_400Hz;
break;
- case IIS2DLPC_XL_ODR_800Hz:
+
+ case IIS2DLPC_XL_ODR_800Hz:
*val = IIS2DLPC_XL_ODR_800Hz;
break;
+
case IIS2DLPC_XL_ODR_1k6Hz:
*val = IIS2DLPC_XL_ODR_1k6Hz;
break;
+
case IIS2DLPC_XL_SET_SW_TRIG:
*val = IIS2DLPC_XL_SET_SW_TRIG;
break;
+
case IIS2DLPC_XL_SET_PIN_TRIG:
*val = IIS2DLPC_XL_SET_PIN_TRIG;
break;
+
default:
*val = IIS2DLPC_XL_ODR_OFF;
break;
}
}
+
return ret;
}
@@ -365,11 +431,14 @@ int32_t iis2dlpc_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dlpc_ctrl2_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.bdu = val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -381,12 +450,13 @@ int32_t iis2dlpc_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dlpc_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t iis2dlpc_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
iis2dlpc_ctrl2_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
*val = reg.bdu;
return ret;
@@ -405,11 +475,14 @@ int32_t iis2dlpc_full_scale_set(stmdev_ctx_t *ctx, iis2dlpc_fs_t val)
iis2dlpc_ctrl6_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.fs = (uint8_t) val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL6, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -426,25 +499,31 @@ int32_t iis2dlpc_full_scale_get(stmdev_ctx_t *ctx, iis2dlpc_fs_t *val)
iis2dlpc_ctrl6_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6, (uint8_t *) ®, 1);
- switch (reg.fs) {
+ switch (reg.fs)
+ {
case IIS2DLPC_2g:
*val = IIS2DLPC_2g;
break;
+
case IIS2DLPC_4g:
*val = IIS2DLPC_4g;
break;
+
case IIS2DLPC_8g:
*val = IIS2DLPC_8g;
break;
+
case IIS2DLPC_16g:
*val = IIS2DLPC_16g;
break;
+
default:
*val = IIS2DLPC_2g;
break;
}
+
return ret;
}
@@ -456,10 +535,13 @@ int32_t iis2dlpc_full_scale_get(stmdev_ctx_t *ctx, iis2dlpc_fs_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dlpc_status_reg_get(stmdev_ctx_t *ctx, iis2dlpc_status_t *val)
+int32_t iis2dlpc_status_reg_get(stmdev_ctx_t *ctx,
+ iis2dlpc_status_t *val)
{
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_STATUS, (uint8_t*) val, 1);
+
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_STATUS, (uint8_t *) val, 1);
+
return ret;
}
@@ -476,7 +558,7 @@ int32_t iis2dlpc_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dlpc_status_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_STATUS,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_STATUS, (uint8_t *) ®, 1);
*val = reg.drdy;
return ret;
@@ -494,7 +576,9 @@ int32_t iis2dlpc_all_sources_get(stmdev_ctx_t *ctx,
iis2dlpc_all_sources_t *val)
{
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_STATUS_DUP, (uint8_t*) val, 5);
+
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_STATUS_DUP, (uint8_t *) val, 5);
+
return ret;
}
@@ -511,7 +595,9 @@ int32_t iis2dlpc_all_sources_get(stmdev_ctx_t *ctx,
int32_t iis2dlpc_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = iis2dlpc_write_reg(ctx, IIS2DLPC_X_OFS_USR, buff, 1);
+
return ret;
}
@@ -528,7 +614,9 @@ int32_t iis2dlpc_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t iis2dlpc_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = iis2dlpc_read_reg(ctx, IIS2DLPC_X_OFS_USR, buff, 1);
+
return ret;
}
@@ -545,7 +633,9 @@ int32_t iis2dlpc_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t iis2dlpc_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = iis2dlpc_write_reg(ctx, IIS2DLPC_Y_OFS_USR, buff, 1);
+
return ret;
}
@@ -562,7 +652,9 @@ int32_t iis2dlpc_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t iis2dlpc_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = iis2dlpc_read_reg(ctx, IIS2DLPC_Y_OFS_USR, buff, 1);
+
return ret;
}
@@ -579,7 +671,9 @@ int32_t iis2dlpc_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t iis2dlpc_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = iis2dlpc_write_reg(ctx, IIS2DLPC_Z_OFS_USR, buff, 1);
+
return ret;
}
@@ -596,7 +690,9 @@ int32_t iis2dlpc_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t iis2dlpc_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = iis2dlpc_read_reg(ctx, IIS2DLPC_Z_OFS_USR, buff, 1);
+
return ret;
}
@@ -616,11 +712,14 @@ int32_t iis2dlpc_offset_weight_set(stmdev_ctx_t *ctx,
iis2dlpc_ctrl7_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.usr_off_w = (uint8_t) val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL7,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -639,18 +738,23 @@ int32_t iis2dlpc_offset_weight_get(stmdev_ctx_t *ctx,
iis2dlpc_ctrl7_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7,(uint8_t*) ®, 1);
- switch (reg.usr_off_w) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
+
+ switch (reg.usr_off_w)
+ {
case IIS2DLPC_LSb_977ug:
*val = IIS2DLPC_LSb_977ug;
break;
+
case IIS2DLPC_LSb_15mg6:
*val = IIS2DLPC_LSb_15mg6;
break;
+
default:
*val = IIS2DLPC_LSb_977ug;
break;
}
+
return ret;
}
@@ -682,7 +786,7 @@ int32_t iis2dlpc_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
ret = iis2dlpc_read_reg(ctx, IIS2DLPC_OUT_T_L, buff, 2);
*val = (int16_t)buff[1];
- *val = (*val * 256) + (int16_t)buff[0];
+ *val = (*val * 256) + (int16_t)buff[0];
return ret;
}
@@ -735,7 +839,9 @@ int32_t iis2dlpc_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
int32_t iis2dlpc_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -753,11 +859,14 @@ int32_t iis2dlpc_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dlpc_ctrl2_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.if_add_inc = val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -775,7 +884,7 @@ int32_t iis2dlpc_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dlpc_ctrl2_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
*val = reg.if_add_inc;
return ret;
@@ -794,10 +903,12 @@ int32_t iis2dlpc_reset_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dlpc_ctrl2_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.soft_reset = val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
}
return ret;
@@ -816,7 +927,7 @@ int32_t iis2dlpc_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dlpc_ctrl2_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
*val = reg.soft_reset;
return ret;
@@ -835,11 +946,14 @@ int32_t iis2dlpc_boot_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dlpc_ctrl2_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.boot = val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -856,7 +970,7 @@ int32_t iis2dlpc_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dlpc_ctrl2_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
*val = reg.boot;
return ret;
@@ -875,10 +989,12 @@ int32_t iis2dlpc_self_test_set(stmdev_ctx_t *ctx, iis2dlpc_st_t val)
iis2dlpc_ctrl3_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.st = (uint8_t) val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) ®, 1);
}
return ret;
@@ -897,22 +1013,27 @@ int32_t iis2dlpc_self_test_get(stmdev_ctx_t *ctx, iis2dlpc_st_t *val)
iis2dlpc_ctrl3_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) ®, 1);
- switch (reg.st) {
+ switch (reg.st)
+ {
case IIS2DLPC_XL_ST_DISABLE:
*val = IIS2DLPC_XL_ST_DISABLE;
break;
+
case IIS2DLPC_XL_ST_POSITIVE:
*val = IIS2DLPC_XL_ST_POSITIVE;
break;
+
case IIS2DLPC_XL_ST_NEGATIVE:
*val = IIS2DLPC_XL_ST_NEGATIVE;
break;
+
default:
*val = IIS2DLPC_XL_ST_DISABLE;
break;
}
+
return ret;
}
@@ -930,10 +1051,12 @@ int32_t iis2dlpc_data_ready_mode_set(stmdev_ctx_t *ctx,
iis2dlpc_ctrl7_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.drdy_pulsed = (uint8_t) val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL7,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
}
return ret;
@@ -953,19 +1076,23 @@ int32_t iis2dlpc_data_ready_mode_get(stmdev_ctx_t *ctx,
iis2dlpc_ctrl7_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
- switch (reg.drdy_pulsed) {
+ switch (reg.drdy_pulsed)
+ {
case IIS2DLPC_DRDY_LATCHED:
*val = IIS2DLPC_DRDY_LATCHED;
break;
+
case IIS2DLPC_DRDY_PULSED:
*val = IIS2DLPC_DRDY_PULSED;
break;
+
default:
*val = IIS2DLPC_DRDY_LATCHED;
break;
}
+
return ret;
}
@@ -990,26 +1117,37 @@ int32_t iis2dlpc_data_ready_mode_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dlpc_filter_path_set(stmdev_ctx_t *ctx, iis2dlpc_fds_t val)
+int32_t iis2dlpc_filter_path_set(stmdev_ctx_t *ctx,
+ iis2dlpc_fds_t val)
{
iis2dlpc_ctrl6_t ctrl6;
iis2dlpc_ctrl7_t ctrl_reg7;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &ctrl6, 1);
- if (ret == 0) {
- ctrl6.fds = ( (uint8_t) val & 0x10U ) >> 4;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &ctrl6, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6, (uint8_t *) &ctrl6, 1);
+
+ if (ret == 0)
+ {
+ ctrl6.fds = ((uint8_t) val & 0x10U) >> 4;
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL6, (uint8_t *) &ctrl6, 1);
}
- if (ret == 0) {
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7,(uint8_t*) &ctrl_reg7, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) &ctrl_reg7, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ctrl_reg7.usr_off_on_out = (uint8_t) val & 0x01U;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL7,(uint8_t*) &ctrl_reg7, 1);
- } else {
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) &ctrl_reg7, 1);
+ }
+
+ else
+ {
ret = ret;
}
+
return ret;
}
@@ -1021,31 +1159,39 @@ int32_t iis2dlpc_filter_path_set(stmdev_ctx_t *ctx, iis2dlpc_fds_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dlpc_filter_path_get(stmdev_ctx_t *ctx, iis2dlpc_fds_t *val)
+int32_t iis2dlpc_filter_path_get(stmdev_ctx_t *ctx,
+ iis2dlpc_fds_t *val)
{
iis2dlpc_ctrl6_t ctrl6;
iis2dlpc_ctrl7_t ctrl_reg7;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &ctrl6, 1);
- if (ret == 0) {
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7,(uint8_t*) &ctrl_reg7, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6, (uint8_t *) &ctrl6, 1);
- switch ((ctrl6.fds << 4 ) + ctrl_reg7.usr_off_on_out) {
+ if (ret == 0)
+ {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) &ctrl_reg7, 1);
+
+ switch ((ctrl6.fds << 4) + ctrl_reg7.usr_off_on_out)
+ {
case IIS2DLPC_LPF_ON_OUT:
*val = IIS2DLPC_LPF_ON_OUT;
break;
+
case IIS2DLPC_USER_OFFSET_ON_OUT:
*val = IIS2DLPC_USER_OFFSET_ON_OUT;
break;
+
case IIS2DLPC_HIGH_PASS_ON_OUT:
*val = IIS2DLPC_HIGH_PASS_ON_OUT;
break;
+
default:
*val = IIS2DLPC_LPF_ON_OUT;
break;
}
}
+
return ret;
}
@@ -1059,15 +1205,17 @@ int32_t iis2dlpc_filter_path_get(stmdev_ctx_t *ctx, iis2dlpc_fds_t *val)
*
*/
int32_t iis2dlpc_filter_bandwidth_set(stmdev_ctx_t *ctx,
- iis2dlpc_bw_filt_t val)
+ iis2dlpc_bw_filt_t val)
{
iis2dlpc_ctrl6_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.bw_filt = (uint8_t) val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL6, (uint8_t *) ®, 1);
}
return ret;
@@ -1083,30 +1231,36 @@ int32_t iis2dlpc_filter_bandwidth_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2dlpc_filter_bandwidth_get(stmdev_ctx_t *ctx,
- iis2dlpc_bw_filt_t *val)
+ iis2dlpc_bw_filt_t *val)
{
iis2dlpc_ctrl6_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6, (uint8_t *) ®, 1);
- switch (reg.bw_filt) {
+ switch (reg.bw_filt)
+ {
case IIS2DLPC_ODR_DIV_2:
*val = IIS2DLPC_ODR_DIV_2;
break;
+
case IIS2DLPC_ODR_DIV_4:
*val = IIS2DLPC_ODR_DIV_4;
break;
+
case IIS2DLPC_ODR_DIV_10:
*val = IIS2DLPC_ODR_DIV_10;
break;
+
case IIS2DLPC_ODR_DIV_20:
*val = IIS2DLPC_ODR_DIV_20;
break;
+
default:
*val = IIS2DLPC_ODR_DIV_2;
break;
}
+
return ret;
}
@@ -1123,11 +1277,14 @@ int32_t iis2dlpc_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dlpc_ctrl7_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.hp_ref_mode = val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL7,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1144,7 +1301,7 @@ int32_t iis2dlpc_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dlpc_ctrl7_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
*val = reg.hp_ref_mode;
return ret;
@@ -1176,11 +1333,14 @@ int32_t iis2dlpc_spi_mode_set(stmdev_ctx_t *ctx, iis2dlpc_sim_t val)
iis2dlpc_ctrl2_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.sim = (uint8_t) val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1197,19 +1357,23 @@ int32_t iis2dlpc_spi_mode_get(stmdev_ctx_t *ctx, iis2dlpc_sim_t *val)
iis2dlpc_ctrl2_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
- switch (reg.sim) {
+ switch (reg.sim)
+ {
case IIS2DLPC_SPI_4_WIRE:
*val = IIS2DLPC_SPI_4_WIRE;
break;
+
case IIS2DLPC_SPI_3_WIRE:
*val = IIS2DLPC_SPI_3_WIRE;
break;
+
default:
*val = IIS2DLPC_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -1228,11 +1392,14 @@ int32_t iis2dlpc_i2c_interface_set(stmdev_ctx_t *ctx,
iis2dlpc_ctrl2_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.i2c_disable = (uint8_t) val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1250,19 +1417,23 @@ int32_t iis2dlpc_i2c_interface_get(stmdev_ctx_t *ctx,
iis2dlpc_ctrl2_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
- switch (reg.i2c_disable) {
+ switch (reg.i2c_disable)
+ {
case IIS2DLPC_I2C_ENABLE:
*val = IIS2DLPC_I2C_ENABLE;
break;
+
case IIS2DLPC_I2C_DISABLE:
*val = IIS2DLPC_I2C_DISABLE;
break;
+
default:
*val = IIS2DLPC_I2C_ENABLE;
break;
}
+
return ret;
}
@@ -1274,16 +1445,20 @@ int32_t iis2dlpc_i2c_interface_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dlpc_cs_mode_set(stmdev_ctx_t *ctx, iis2dlpc_cs_pu_disc_t val)
+int32_t iis2dlpc_cs_mode_set(stmdev_ctx_t *ctx,
+ iis2dlpc_cs_pu_disc_t val)
{
iis2dlpc_ctrl2_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.cs_pu_disc = (uint8_t) val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1295,24 +1470,29 @@ int32_t iis2dlpc_cs_mode_set(stmdev_ctx_t *ctx, iis2dlpc_cs_pu_disc_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dlpc_cs_mode_get(stmdev_ctx_t *ctx, iis2dlpc_cs_pu_disc_t *val)
+int32_t iis2dlpc_cs_mode_get(stmdev_ctx_t *ctx,
+ iis2dlpc_cs_pu_disc_t *val)
{
iis2dlpc_ctrl2_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1);
- switch (reg.cs_pu_disc) {
+ switch (reg.cs_pu_disc)
+ {
case IIS2DLPC_PULL_UP_CONNECT:
*val = IIS2DLPC_PULL_UP_CONNECT;
break;
+
case IIS2DLPC_PULL_UP_DISCONNECT:
*val = IIS2DLPC_PULL_UP_DISCONNECT;
break;
+
default:
*val = IIS2DLPC_PULL_UP_CONNECT;
break;
}
+
return ret;
}
@@ -1342,11 +1522,14 @@ int32_t iis2dlpc_pin_polarity_set(stmdev_ctx_t *ctx,
iis2dlpc_ctrl3_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.h_lactive = (uint8_t) val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1364,19 +1547,23 @@ int32_t iis2dlpc_pin_polarity_get(stmdev_ctx_t *ctx,
iis2dlpc_ctrl3_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) ®, 1);
- switch (reg.h_lactive) {
+ switch (reg.h_lactive)
+ {
case IIS2DLPC_ACTIVE_HIGH:
*val = IIS2DLPC_ACTIVE_HIGH;
break;
+
case IIS2DLPC_ACTIVE_LOW:
*val = IIS2DLPC_ACTIVE_LOW;
break;
+
default:
*val = IIS2DLPC_ACTIVE_HIGH;
break;
}
+
return ret;
}
@@ -1394,11 +1581,14 @@ int32_t iis2dlpc_int_notification_set(stmdev_ctx_t *ctx,
iis2dlpc_ctrl3_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.lir = (uint8_t) val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1416,19 +1606,23 @@ int32_t iis2dlpc_int_notification_get(stmdev_ctx_t *ctx,
iis2dlpc_ctrl3_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) ®, 1);
- switch (reg.lir) {
+ switch (reg.lir)
+ {
case IIS2DLPC_INT_PULSED:
*val = IIS2DLPC_INT_PULSED;
break;
+
case IIS2DLPC_INT_LATCHED:
*val = IIS2DLPC_INT_LATCHED;
break;
+
default:
*val = IIS2DLPC_INT_PULSED;
break;
}
+
return ret;
}
@@ -1445,11 +1639,14 @@ int32_t iis2dlpc_pin_mode_set(stmdev_ctx_t *ctx, iis2dlpc_pp_od_t val)
iis2dlpc_ctrl3_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.pp_od = (uint8_t) val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1461,24 +1658,29 @@ int32_t iis2dlpc_pin_mode_set(stmdev_ctx_t *ctx, iis2dlpc_pp_od_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dlpc_pin_mode_get(stmdev_ctx_t *ctx, iis2dlpc_pp_od_t *val)
+int32_t iis2dlpc_pin_mode_get(stmdev_ctx_t *ctx,
+ iis2dlpc_pp_od_t *val)
{
iis2dlpc_ctrl3_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) ®, 1);
- switch (reg.pp_od) {
+ switch (reg.pp_od)
+ {
case IIS2DLPC_PUSH_PULL:
*val = IIS2DLPC_PUSH_PULL;
break;
+
case IIS2DLPC_OPEN_DRAIN:
*val = IIS2DLPC_OPEN_DRAIN;
break;
+
default:
*val = IIS2DLPC_PUSH_PULL;
break;
}
+
return ret;
}
@@ -1498,32 +1700,45 @@ int32_t iis2dlpc_pin_int1_route_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL5_INT2_PAD_CTRL,
- (uint8_t*) &ctrl5_int2_pad_ctrl, 1);
- if (ret == 0) {
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7,(uint8_t*) ®, 1);
- }
- if (ret == 0) {
- if (( ctrl5_int2_pad_ctrl.int2_sleep_state
- | ctrl5_int2_pad_ctrl.int2_sleep_chg
- | val->int1_tap
- | val->int1_ff
- | val->int1_wu
- | val->int1_single_tap
- | val->int1_6d ) != PROPERTY_DISABLE) {
+ (uint8_t *) &ctrl5_int2_pad_ctrl, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
+ }
+
+ if (ret == 0)
+ {
+ if ((ctrl5_int2_pad_ctrl.int2_sleep_state
+ | ctrl5_int2_pad_ctrl.int2_sleep_chg
+ | val->int1_tap
+ | val->int1_ff
+ | val->int1_wu
+ | val->int1_single_tap
+ | val->int1_6d) != PROPERTY_DISABLE)
+ {
reg.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
reg.interrupts_enable = PROPERTY_DISABLE;
}
ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL4_INT1_PAD_CTRL,
- (uint8_t*) val, 1);
+ (uint8_t *) val, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
}
- if (ret == 0) {
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL7,(uint8_t*) ®, 1);
- } else {
+
+ else
+ {
ret = ret;
}
+
return ret;
}
@@ -1539,8 +1754,10 @@ int32_t iis2dlpc_pin_int1_route_get(stmdev_ctx_t *ctx,
iis2dlpc_ctrl4_int1_pad_ctrl_t *val)
{
int32_t ret;
+
ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL4_INT1_PAD_CTRL,
- (uint8_t*) val, 1);
+ (uint8_t *) val, 1);
+
return ret;
}
@@ -1560,32 +1777,45 @@ int32_t iis2dlpc_pin_int2_route_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL4_INT1_PAD_CTRL,
- (uint8_t*)&ctrl4_int1_pad, 1);
- if (ret == 0) {
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7,(uint8_t*) &ctrl_reg7, 1);
+ (uint8_t *)&ctrl4_int1_pad, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) &ctrl_reg7, 1);
}
- if (ret == 0) {
- if (( val->int2_sleep_state
+
+ if (ret == 0)
+ {
+ if ((val->int2_sleep_state
| val->int2_sleep_chg
| ctrl4_int1_pad.int1_tap
| ctrl4_int1_pad.int1_ff
| ctrl4_int1_pad.int1_wu
| ctrl4_int1_pad.int1_single_tap
- | ctrl4_int1_pad.int1_6d ) != PROPERTY_DISABLE) {
+ | ctrl4_int1_pad.int1_6d) != PROPERTY_DISABLE)
+ {
ctrl_reg7.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
ctrl_reg7.interrupts_enable = PROPERTY_DISABLE;
}
ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL5_INT2_PAD_CTRL,
- (uint8_t*) val, 1);
+ (uint8_t *) val, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) &ctrl_reg7, 1);
}
- if (ret == 0) {
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL7,(uint8_t*) &ctrl_reg7, 1);
- } else {
+
+ else
+ {
ret = ret;
}
+
return ret;
}
@@ -1601,8 +1831,10 @@ int32_t iis2dlpc_pin_int2_route_get(stmdev_ctx_t *ctx,
iis2dlpc_ctrl5_int2_pad_ctrl_t *val)
{
int32_t ret;
+
ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL5_INT2_PAD_CTRL,
- (uint8_t*) val, 1);
+ (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1618,11 +1850,14 @@ int32_t iis2dlpc_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dlpc_ctrl7_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.int2_on_int1 = val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL7,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1639,7 +1874,7 @@ int32_t iis2dlpc_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dlpc_ctrl7_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
*val = reg.int2_on_int1;
return ret;
@@ -1671,11 +1906,14 @@ int32_t iis2dlpc_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dlpc_wake_up_ths_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.wk_ths = val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_THS, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1692,7 +1930,7 @@ int32_t iis2dlpc_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dlpc_wake_up_ths_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS, (uint8_t *) ®, 1);
*val = reg.wk_ths;
return ret;
@@ -1711,11 +1949,14 @@ int32_t iis2dlpc_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dlpc_wake_up_dur_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.wake_dur = val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_DUR, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1732,7 +1973,7 @@ int32_t iis2dlpc_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dlpc_wake_up_dur_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR, (uint8_t *) ®, 1);
*val = reg.wake_dur;
return ret;
@@ -1752,11 +1993,14 @@ int32_t iis2dlpc_wkup_feed_data_set(stmdev_ctx_t *ctx,
iis2dlpc_ctrl7_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.usr_off_on_wu = (uint8_t) val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL7,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1774,19 +2018,23 @@ int32_t iis2dlpc_wkup_feed_data_get(stmdev_ctx_t *ctx,
iis2dlpc_ctrl7_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
- switch (reg.usr_off_on_wu) {
+ switch (reg.usr_off_on_wu)
+ {
case IIS2DLPC_HP_FEED:
*val = IIS2DLPC_HP_FEED;
break;
+
case IIS2DLPC_USER_OFFSET_FEED:
*val = IIS2DLPC_USER_OFFSET_FEED;
break;
+
default:
*val = IIS2DLPC_HP_FEED;
break;
}
+
return ret;
}
@@ -1813,21 +2061,32 @@ int32_t iis2dlpc_wkup_feed_data_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dlpc_act_mode_set(stmdev_ctx_t *ctx, iis2dlpc_sleep_on_t val)
+int32_t iis2dlpc_act_mode_set(stmdev_ctx_t *ctx,
+ iis2dlpc_sleep_on_t val)
{
iis2dlpc_wake_up_ths_t wake_up_ths;
iis2dlpc_wake_up_dur_t wake_up_dur;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) &wake_up_ths, 1);
- if (ret == 0) {
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS,
+ (uint8_t *) &wake_up_ths, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,
+ (uint8_t *) &wake_up_dur, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
wake_up_ths.sleep_on = (uint8_t) val & 0x01U;
wake_up_dur.stationary = ((uint8_t)val & 0x02U) >> 1;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) &wake_up_ths, 2);
- } else {
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_THS,
+ (uint8_t *) &wake_up_ths, 2);
+ }
+
+ else
+ {
ret = ret;
}
@@ -1843,31 +2102,41 @@ int32_t iis2dlpc_act_mode_set(stmdev_ctx_t *ctx, iis2dlpc_sleep_on_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dlpc_act_mode_get(stmdev_ctx_t *ctx, iis2dlpc_sleep_on_t *val)
+int32_t iis2dlpc_act_mode_get(stmdev_ctx_t *ctx,
+ iis2dlpc_sleep_on_t *val)
{
iis2dlpc_wake_up_ths_t wake_up_ths;
iis2dlpc_wake_up_dur_t wake_up_dur;;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) &wake_up_ths, 1);
- if (ret == 0) {
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS,
+ (uint8_t *) &wake_up_ths, 1);
- switch ((wake_up_dur.stationary << 1) + wake_up_ths.sleep_on){
+ if (ret == 0)
+ {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,
+ (uint8_t *) &wake_up_dur, 1);
+
+ switch ((wake_up_dur.stationary << 1) + wake_up_ths.sleep_on)
+ {
case IIS2DLPC_NO_DETECTION:
*val = IIS2DLPC_NO_DETECTION;
break;
+
case IIS2DLPC_DETECT_ACT_INACT:
*val = IIS2DLPC_DETECT_ACT_INACT;
break;
+
case IIS2DLPC_DETECT_STAT_MOTION:
*val = IIS2DLPC_DETECT_STAT_MOTION;
break;
+
default:
*val = IIS2DLPC_NO_DETECTION;
break;
}
}
+
return ret;
}
@@ -1884,11 +2153,14 @@ int32_t iis2dlpc_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dlpc_wake_up_dur_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.sleep_dur = val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_DUR, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1905,7 +2177,7 @@ int32_t iis2dlpc_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dlpc_wake_up_dur_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR, (uint8_t *) ®, 1);
*val = reg.sleep_dur;
return ret;
@@ -1937,11 +2209,14 @@ int32_t iis2dlpc_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dlpc_tap_ths_x_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.tap_thsx = val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_X, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1958,7 +2233,7 @@ int32_t iis2dlpc_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dlpc_tap_ths_x_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X, (uint8_t *) ®, 1);
*val = reg.tap_thsx;
return ret;
@@ -1977,11 +2252,14 @@ int32_t iis2dlpc_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dlpc_tap_ths_y_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Y,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Y, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.tap_thsy = val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Y,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Y, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1998,7 +2276,7 @@ int32_t iis2dlpc_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dlpc_tap_ths_y_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Y,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Y, (uint8_t *) ®, 1);
*val = reg.tap_thsy;
return ret;
@@ -2018,11 +2296,14 @@ int32_t iis2dlpc_tap_axis_priority_set(stmdev_ctx_t *ctx,
iis2dlpc_tap_ths_y_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Y,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Y, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.tap_prior = (uint8_t) val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Y,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Y, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -2040,31 +2321,39 @@ int32_t iis2dlpc_tap_axis_priority_get(stmdev_ctx_t *ctx,
iis2dlpc_tap_ths_y_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Y,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Y, (uint8_t *) ®, 1);
- switch (reg.tap_prior) {
+ switch (reg.tap_prior)
+ {
case IIS2DLPC_XYZ:
*val = IIS2DLPC_XYZ;
break;
+
case IIS2DLPC_YXZ:
*val = IIS2DLPC_YXZ;
break;
+
case IIS2DLPC_XZY:
*val = IIS2DLPC_XZY;
break;
+
case IIS2DLPC_ZYX:
*val = IIS2DLPC_ZYX;
break;
+
case IIS2DLPC_YZX:
*val = IIS2DLPC_YZX;
break;
+
case IIS2DLPC_ZXY:
*val = IIS2DLPC_ZXY;
break;
+
default:
*val = IIS2DLPC_XYZ;
break;
}
+
return ret;
}
@@ -2081,10 +2370,12 @@ int32_t iis2dlpc_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dlpc_tap_ths_z_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.tap_thsz = val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Z, (uint8_t *) ®, 1);
}
return ret;
@@ -2103,7 +2394,7 @@ int32_t iis2dlpc_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dlpc_tap_ths_z_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z, (uint8_t *) ®, 1);
*val = reg.tap_thsz;
return ret;
@@ -2117,16 +2408,20 @@ int32_t iis2dlpc_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dlpc_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t iis2dlpc_tap_detection_on_z_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
iis2dlpc_tap_ths_z_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.tap_z_en = val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Z, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -2138,12 +2433,13 @@ int32_t iis2dlpc_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dlpc_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t iis2dlpc_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
iis2dlpc_tap_ths_z_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z, (uint8_t *) ®, 1);
*val = reg.tap_z_en;
return ret;
@@ -2157,16 +2453,20 @@ int32_t iis2dlpc_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dlpc_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t iis2dlpc_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
iis2dlpc_tap_ths_z_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.tap_y_en = val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Z, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -2178,12 +2478,13 @@ int32_t iis2dlpc_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dlpc_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t iis2dlpc_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
iis2dlpc_tap_ths_z_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z, (uint8_t *) ®, 1);
*val = reg.tap_y_en;
return ret;
@@ -2197,16 +2498,20 @@ int32_t iis2dlpc_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dlpc_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t iis2dlpc_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
iis2dlpc_tap_ths_z_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.tap_x_en = val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Z, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -2218,12 +2523,13 @@ int32_t iis2dlpc_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dlpc_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t iis2dlpc_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
iis2dlpc_tap_ths_z_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z, (uint8_t *) ®, 1);
*val = reg.tap_x_en;
return ret;
@@ -2246,10 +2552,12 @@ int32_t iis2dlpc_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dlpc_int_dur_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.shock = val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_INT_DUR, (uint8_t *) ®, 1);
}
return ret;
@@ -2272,7 +2580,7 @@ int32_t iis2dlpc_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dlpc_int_dur_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR, (uint8_t *) ®, 1);
*val = reg.shock;
return ret;
@@ -2295,11 +2603,14 @@ int32_t iis2dlpc_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dlpc_int_dur_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.quiet = val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_INT_DUR, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -2320,7 +2631,7 @@ int32_t iis2dlpc_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dlpc_int_dur_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR, (uint8_t *) ®, 1);
*val = reg.quiet;
return ret;
@@ -2344,11 +2655,14 @@ int32_t iis2dlpc_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dlpc_int_dur_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.latency = val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_INT_DUR, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -2370,7 +2684,7 @@ int32_t iis2dlpc_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dlpc_int_dur_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR, (uint8_t *) ®, 1);
*val = reg.latency;
return ret;
@@ -2390,11 +2704,14 @@ int32_t iis2dlpc_tap_mode_set(stmdev_ctx_t *ctx,
iis2dlpc_wake_up_ths_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.single_double_tap = (uint8_t) val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_THS, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -2412,15 +2729,18 @@ int32_t iis2dlpc_tap_mode_get(stmdev_ctx_t *ctx,
iis2dlpc_wake_up_ths_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS, (uint8_t *) ®, 1);
- switch (reg.single_double_tap) {
+ switch (reg.single_double_tap)
+ {
case IIS2DLPC_ONLY_SINGLE:
*val = IIS2DLPC_ONLY_SINGLE;
break;
+
case IIS2DLPC_BOTH_SINGLE_DOUBLE:
*val = IIS2DLPC_BOTH_SINGLE_DOUBLE;
break;
+
default:
*val = IIS2DLPC_ONLY_SINGLE;
break;
@@ -2437,10 +2757,13 @@ int32_t iis2dlpc_tap_mode_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dlpc_tap_src_get(stmdev_ctx_t *ctx, iis2dlpc_tap_src_t *val)
+int32_t iis2dlpc_tap_src_get(stmdev_ctx_t *ctx,
+ iis2dlpc_tap_src_t *val)
{
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_SRC, (uint8_t*) val, 1);
+
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_SRC, (uint8_t *) val, 1);
+
return ret;
}
@@ -2470,11 +2793,14 @@ int32_t iis2dlpc_6d_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dlpc_tap_ths_x_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg._6d_ths = val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_X, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -2491,7 +2817,7 @@ int32_t iis2dlpc_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dlpc_tap_ths_x_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X, (uint8_t *) ®, 1);
*val = reg._6d_ths;
return ret;
@@ -2510,10 +2836,12 @@ int32_t iis2dlpc_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dlpc_tap_ths_x_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg._4d_en = val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_X, (uint8_t *) ®, 1);
}
return ret;
@@ -2532,7 +2860,7 @@ int32_t iis2dlpc_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dlpc_tap_ths_x_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X, (uint8_t *) ®, 1);
*val = reg._4d_en;
return ret;
@@ -2546,10 +2874,13 @@ int32_t iis2dlpc_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dlpc_6d_src_get(stmdev_ctx_t *ctx, iis2dlpc_sixd_src_t *val)
+int32_t iis2dlpc_6d_src_get(stmdev_ctx_t *ctx,
+ iis2dlpc_sixd_src_t *val)
{
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_SIXD_SRC, (uint8_t*) val, 1);
+
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_SIXD_SRC, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -2566,11 +2897,14 @@ int32_t iis2dlpc_6d_feed_data_set(stmdev_ctx_t *ctx,
iis2dlpc_ctrl7_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.lpass_on6d = (uint8_t) val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL7,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -2588,19 +2922,23 @@ int32_t iis2dlpc_6d_feed_data_get(stmdev_ctx_t *ctx,
iis2dlpc_ctrl7_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1);
- switch (reg.lpass_on6d) {
+ switch (reg.lpass_on6d)
+ {
case IIS2DLPC_ODR_DIV_2_FEED:
*val = IIS2DLPC_ODR_DIV_2_FEED;
break;
+
case IIS2DLPC_LPF2_FEED:
*val = IIS2DLPC_LPF2_FEED;
break;
+
default:
*val = IIS2DLPC_ODR_DIV_2_FEED;
break;
}
+
return ret;
}
@@ -2632,17 +2970,27 @@ int32_t iis2dlpc_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dlpc_free_fall_t free_fall;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
- if (ret == 0) {
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FREE_FALL,(uint8_t*) &free_fall, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,
+ (uint8_t *) &wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FREE_FALL,
+ (uint8_t *) &free_fall, 1);
}
- if(ret == 0) {
- wake_up_dur.ff_dur = ( (uint8_t) val & 0x20U) >> 5;
+
+ if (ret == 0)
+ {
+ wake_up_dur.ff_dur = ((uint8_t) val & 0x20U) >> 5;
free_fall.ff_dur = (uint8_t) val & 0x1FU;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_DUR,
+ (uint8_t *) &wake_up_dur, 1);
}
- if(ret == 0) {
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_FREE_FALL,(uint8_t*) &free_fall, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_FREE_FALL,
+ (uint8_t *) &free_fall, 1);
}
return ret;
@@ -2663,11 +3011,16 @@ int32_t iis2dlpc_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dlpc_free_fall_t free_fall;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
- if (ret == 0) {
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FREE_FALL,(uint8_t*) &free_fall, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,
+ (uint8_t *) &wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FREE_FALL,
+ (uint8_t *) &free_fall, 1);
*val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
}
+
return ret;
}
@@ -2679,15 +3032,18 @@ int32_t iis2dlpc_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dlpc_ff_threshold_set(stmdev_ctx_t *ctx, iis2dlpc_ff_ths_t val)
+int32_t iis2dlpc_ff_threshold_set(stmdev_ctx_t *ctx,
+ iis2dlpc_ff_ths_t val)
{
iis2dlpc_free_fall_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FREE_FALL,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FREE_FALL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.ff_ths = (uint8_t) val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_FREE_FALL,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_FREE_FALL, (uint8_t *) ®, 1);
}
return ret;
@@ -2707,37 +3063,47 @@ int32_t iis2dlpc_ff_threshold_get(stmdev_ctx_t *ctx,
iis2dlpc_free_fall_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FREE_FALL,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FREE_FALL, (uint8_t *) ®, 1);
- switch (reg.ff_ths) {
+ switch (reg.ff_ths)
+ {
case IIS2DLPC_FF_TSH_5LSb_FS2g:
*val = IIS2DLPC_FF_TSH_5LSb_FS2g;
break;
+
case IIS2DLPC_FF_TSH_7LSb_FS2g:
*val = IIS2DLPC_FF_TSH_7LSb_FS2g;
break;
+
case IIS2DLPC_FF_TSH_8LSb_FS2g:
*val = IIS2DLPC_FF_TSH_8LSb_FS2g;
break;
+
case IIS2DLPC_FF_TSH_10LSb_FS2g:
*val = IIS2DLPC_FF_TSH_10LSb_FS2g;
break;
+
case IIS2DLPC_FF_TSH_11LSb_FS2g:
*val = IIS2DLPC_FF_TSH_11LSb_FS2g;
break;
+
case IIS2DLPC_FF_TSH_13LSb_FS2g:
*val = IIS2DLPC_FF_TSH_13LSb_FS2g;
break;
+
case IIS2DLPC_FF_TSH_15LSb_FS2g:
*val = IIS2DLPC_FF_TSH_15LSb_FS2g;
break;
+
case IIS2DLPC_FF_TSH_16LSb_FS2g:
*val = IIS2DLPC_FF_TSH_16LSb_FS2g;
break;
+
default:
*val = IIS2DLPC_FF_TSH_5LSb_FS2g;
break;
}
+
return ret;
}
@@ -2766,10 +3132,12 @@ int32_t iis2dlpc_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
iis2dlpc_fifo_ctrl_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_CTRL,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.fth = val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_FIFO_CTRL,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_FIFO_CTRL, (uint8_t *) ®, 1);
}
return ret;
@@ -2788,7 +3156,7 @@ int32_t iis2dlpc_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dlpc_fifo_ctrl_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_CTRL,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_CTRL, (uint8_t *) ®, 1);
*val = reg.fth;
return ret;
@@ -2802,16 +3170,20 @@ int32_t iis2dlpc_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dlpc_fifo_mode_set(stmdev_ctx_t *ctx, iis2dlpc_fmode_t val)
+int32_t iis2dlpc_fifo_mode_set(stmdev_ctx_t *ctx,
+ iis2dlpc_fmode_t val)
{
iis2dlpc_fifo_ctrl_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_CTRL,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.fmode = (uint8_t) val;
- ret = iis2dlpc_write_reg(ctx, IIS2DLPC_FIFO_CTRL,(uint8_t*) ®, 1);
+ ret = iis2dlpc_write_reg(ctx, IIS2DLPC_FIFO_CTRL, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -2823,33 +3195,41 @@ int32_t iis2dlpc_fifo_mode_set(stmdev_ctx_t *ctx, iis2dlpc_fmode_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2dlpc_fifo_mode_get(stmdev_ctx_t *ctx, iis2dlpc_fmode_t *val)
+int32_t iis2dlpc_fifo_mode_get(stmdev_ctx_t *ctx,
+ iis2dlpc_fmode_t *val)
{
iis2dlpc_fifo_ctrl_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_CTRL,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_CTRL, (uint8_t *) ®, 1);
- switch (reg.fmode) {
+ switch (reg.fmode)
+ {
case IIS2DLPC_BYPASS_MODE:
*val = IIS2DLPC_BYPASS_MODE;
break;
+
case IIS2DLPC_FIFO_MODE:
*val = IIS2DLPC_FIFO_MODE;
break;
+
case IIS2DLPC_STREAM_TO_FIFO_MODE:
*val = IIS2DLPC_STREAM_TO_FIFO_MODE;
break;
+
case IIS2DLPC_BYPASS_TO_STREAM_MODE:
*val = IIS2DLPC_BYPASS_TO_STREAM_MODE;
break;
+
case IIS2DLPC_STREAM_MODE:
*val = IIS2DLPC_STREAM_MODE;
break;
+
default:
*val = IIS2DLPC_BYPASS_MODE;
break;
}
+
return ret;
}
@@ -2866,7 +3246,7 @@ int32_t iis2dlpc_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dlpc_fifo_samples_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_SAMPLES,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_SAMPLES, (uint8_t *) ®, 1);
*val = reg.diff;
return ret;
@@ -2884,7 +3264,7 @@ int32_t iis2dlpc_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dlpc_fifo_samples_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_SAMPLES,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_SAMPLES, (uint8_t *) ®, 1);
*val = reg.fifo_ovr;
return ret;
@@ -2902,7 +3282,7 @@ int32_t iis2dlpc_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2dlpc_fifo_samples_t reg;
int32_t ret;
- ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_SAMPLES,(uint8_t*) ®, 1);
+ ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_SAMPLES, (uint8_t *) ®, 1);
*val = reg.fifo_fth;
return ret;
diff --git a/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.h b/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.h
index eaf3ee69ff08dbc90bb0e441ca801032c5cc8515..b47d5feaf46dc5a9eb82c134a82909e878d50be2 100644
--- a/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.h
+++ b/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file iis2dlpc_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * iis2dlpc_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file iis2dlpc_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * iis2dlpc_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef IIS2DLPC_REGS_H
#define IIS2DLPC_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup IIS2DLPC
@@ -74,7 +75,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -107,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -131,15 +134,16 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
- * Unico / Unicleo tools available on STMicroelectronics
- * web site.
+ * You can create a sensor configuration by your own or using
+ * Unico / Unicleo tools available on STMicroelectronics
+ * web site.
*
* @{
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -177,7 +181,8 @@ typedef struct {
#define IIS2DLPC_OUT_T_H 0x0EU
#define IIS2DLPC_WHO_AM_I 0x0FU
#define IIS2DLPC_CTRL1 0x20U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lp_mode : 2;
uint8_t mode : 2;
@@ -190,7 +195,8 @@ typedef struct {
} iis2dlpc_ctrl1_t;
#define IIS2DLPC_CTRL2 0x21U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t i2c_disable : 1;
@@ -213,9 +219,11 @@ typedef struct {
} iis2dlpc_ctrl2_t;
#define IIS2DLPC_CTRL3 0x22U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t slp_mode : 2; /* slp_mode_sel + slp_mode_1 */
+uint8_t slp_mode :
+ 2; /* slp_mode_sel + slp_mode_1 */
uint8_t not_used_01 : 1;
uint8_t h_lactive : 1;
uint8_t lir : 1;
@@ -227,12 +235,14 @@ typedef struct {
uint8_t lir : 1;
uint8_t h_lactive : 1;
uint8_t not_used_01 : 1;
- uint8_t slp_mode : 2; /* slp_mode_sel + slp_mode_1 */
+uint8_t slp_mode :
+ 2; /* slp_mode_sel + slp_mode_1 */
#endif /* DRV_BYTE_ORDER */
} iis2dlpc_ctrl3_t;
#define IIS2DLPC_CTRL4_INT1_PAD_CTRL 0x23U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_drdy : 1;
uint8_t int1_fth : 1;
@@ -255,7 +265,8 @@ typedef struct {
} iis2dlpc_ctrl4_int1_pad_ctrl_t;
#define IIS2DLPC_CTRL5_INT2_PAD_CTRL 0x24U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_drdy : 1;
uint8_t int2_fth : 1;
@@ -278,7 +289,8 @@ typedef struct {
} iis2dlpc_ctrl5_int2_pad_ctrl_t;
#define IIS2DLPC_CTRL6 0x25U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t low_noise : 1;
@@ -296,7 +308,8 @@ typedef struct {
#define IIS2DLPC_OUT_T 0x26U
#define IIS2DLPC_STATUS 0x27U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t drdy : 1;
uint8_t ff_ia : 1;
@@ -325,7 +338,8 @@ typedef struct {
#define IIS2DLPC_OUT_Z_L 0x2CU
#define IIS2DLPC_OUT_Z_H 0x2DU
#define IIS2DLPC_FIFO_CTRL 0x2EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fth : 5;
uint8_t fmode : 3;
@@ -336,7 +350,8 @@ typedef struct {
} iis2dlpc_fifo_ctrl_t;
#define IIS2DLPC_FIFO_SAMPLES 0x2FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t diff : 6;
uint8_t fifo_ovr : 1;
@@ -349,7 +364,8 @@ typedef struct {
} iis2dlpc_fifo_samples_t;
#define IIS2DLPC_TAP_THS_X 0x30U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_thsx : 5;
uint8_t _6d_ths : 2;
@@ -362,7 +378,8 @@ typedef struct {
} iis2dlpc_tap_ths_x_t;
#define IIS2DLPC_TAP_THS_Y 0x31U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_thsy : 5;
uint8_t tap_prior : 3;
@@ -373,7 +390,8 @@ typedef struct {
} iis2dlpc_tap_ths_y_t;
#define IIS2DLPC_TAP_THS_Z 0x32U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_thsz : 5;
uint8_t tap_z_en : 1;
@@ -388,7 +406,8 @@ typedef struct {
} iis2dlpc_tap_ths_z_t;
#define IIS2DLPC_INT_DUR 0x33U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shock : 2;
uint8_t quiet : 2;
@@ -401,7 +420,8 @@ typedef struct {
} iis2dlpc_int_dur_t;
#define IIS2DLPC_WAKE_UP_THS 0x34U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wk_ths : 6;
uint8_t sleep_on : 1;
@@ -414,7 +434,8 @@ typedef struct {
} iis2dlpc_wake_up_ths_t;
#define IIS2DLPC_WAKE_UP_DUR 0x35U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sleep_dur : 4;
uint8_t stationary : 1;
@@ -429,7 +450,8 @@ typedef struct {
} iis2dlpc_wake_up_dur_t;
#define IIS2DLPC_FREE_FALL 0x36U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ths : 3;
uint8_t ff_dur : 5;
@@ -440,7 +462,8 @@ typedef struct {
} iis2dlpc_free_fall_t;
#define IIS2DLPC_STATUS_DUP 0x37U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t drdy : 1;
uint8_t ff_ia : 1;
@@ -463,7 +486,8 @@ typedef struct {
} iis2dlpc_status_dup_t;
#define IIS2DLPC_WAKE_UP_SRC 0x38U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_wu : 1;
uint8_t y_wu : 1;
@@ -484,7 +508,8 @@ typedef struct {
} iis2dlpc_wake_up_src_t;
#define IIS2DLPC_TAP_SRC 0x39U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_tap : 1;
uint8_t y_tap : 1;
@@ -507,7 +532,8 @@ typedef struct {
} iis2dlpc_tap_src_t;
#define IIS2DLPC_SIXD_SRC 0x3AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
@@ -530,7 +556,8 @@ typedef struct {
} iis2dlpc_sixd_src_t;
#define IIS2DLPC_ALL_INT_SRC 0x3BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ia : 1;
uint8_t wu_ia : 1;
@@ -554,7 +581,8 @@ typedef struct {
#define IIS2DLPC_Y_OFS_USR 0x3DU
#define IIS2DLPC_Z_OFS_USR 0x3EU
#define IIS2DLPC_CTRL7 0x3FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lpass_on6d : 1;
uint8_t hp_ref_mode : 1;
@@ -578,17 +606,18 @@ typedef struct {
/**
* @defgroup IIS2DLPC_Register_Union
- * @brief This union group all the registers that has a bitfield
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is usefull but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
- * REMOVING this union you are complient with:
+ * REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
*
* @{
*
*/
-typedef union{
+typedef union
+{
iis2dlpc_ctrl1_t ctrl1;
iis2dlpc_ctrl2_t ctrl2;
iis2dlpc_ctrl3_t ctrl3;
@@ -620,22 +649,27 @@ typedef union{
*
*/
-int32_t iis2dlpc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t iis2dlpc_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t iis2dlpc_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t iis2dlpc_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-extern float_t iis2dlpc_from_fs2_to_mg(int16_t lsb);
-extern float_t iis2dlpc_from_fs4_to_mg(int16_t lsb);
-extern float_t iis2dlpc_from_fs8_to_mg(int16_t lsb);
-extern float_t iis2dlpc_from_fs16_to_mg(int16_t lsb);
-extern float_t iis2dlpc_from_fs2_lp1_to_mg(int16_t lsb);
-extern float_t iis2dlpc_from_fs4_lp1_to_mg(int16_t lsb);
-extern float_t iis2dlpc_from_fs8_lp1_to_mg(int16_t lsb);
-extern float_t iis2dlpc_from_fs16_lp1_to_mg(int16_t lsb);
-extern float_t iis2dlpc_from_lsb_to_celsius(int16_t lsb);
-
-typedef enum {
+float_t iis2dlpc_from_fs2_to_mg(int16_t lsb);
+float_t iis2dlpc_from_fs4_to_mg(int16_t lsb);
+float_t iis2dlpc_from_fs8_to_mg(int16_t lsb);
+float_t iis2dlpc_from_fs16_to_mg(int16_t lsb);
+
+float_t iis2dlpc_from_fs2_lp1_to_mg(int16_t lsb);
+float_t iis2dlpc_from_fs4_lp1_to_mg(int16_t lsb);
+float_t iis2dlpc_from_fs8_lp1_to_mg(int16_t lsb);
+float_t iis2dlpc_from_fs16_lp1_to_mg(int16_t lsb);
+
+float_t iis2dlpc_from_lsb_to_celsius(int16_t lsb);
+
+typedef enum
+{
IIS2DLPC_HIGH_PERFORMANCE = 0x04,
IIS2DLPC_CONT_LOW_PWR_4 = 0x03,
IIS2DLPC_CONT_LOW_PWR_3 = 0x02,
@@ -655,10 +689,13 @@ typedef enum {
IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_2 = 0x19,
IIS2DLPC_SINGLE_LOW_LOW_NOISE_PWR_12bit = 0x18,
} iis2dlpc_mode_t;
-int32_t iis2dlpc_power_mode_set(stmdev_ctx_t *ctx, iis2dlpc_mode_t val);
-int32_t iis2dlpc_power_mode_get(stmdev_ctx_t *ctx, iis2dlpc_mode_t *val);
+int32_t iis2dlpc_power_mode_set(stmdev_ctx_t *ctx,
+ iis2dlpc_mode_t val);
+int32_t iis2dlpc_power_mode_get(stmdev_ctx_t *ctx,
+ iis2dlpc_mode_t *val);
-typedef enum {
+typedef enum
+{
IIS2DLPC_XL_ODR_OFF = 0x00,
IIS2DLPC_XL_ODR_1Hz6_LP_ONLY = 0x01,
IIS2DLPC_XL_ODR_12Hz5 = 0x02,
@@ -673,25 +710,32 @@ typedef enum {
IIS2DLPC_XL_SET_PIN_TRIG = 0x22, /* Use this only in SINGLE mode */
} iis2dlpc_odr_t;
int32_t iis2dlpc_data_rate_set(stmdev_ctx_t *ctx, iis2dlpc_odr_t val);
-int32_t iis2dlpc_data_rate_get(stmdev_ctx_t *ctx, iis2dlpc_odr_t *val);
+int32_t iis2dlpc_data_rate_get(stmdev_ctx_t *ctx,
+ iis2dlpc_odr_t *val);
-int32_t iis2dlpc_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis2dlpc_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis2dlpc_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t iis2dlpc_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS2DLPC_2g = 0,
IIS2DLPC_4g = 1,
IIS2DLPC_8g = 2,
IIS2DLPC_16g = 3,
} iis2dlpc_fs_t;
int32_t iis2dlpc_full_scale_set(stmdev_ctx_t *ctx, iis2dlpc_fs_t val);
-int32_t iis2dlpc_full_scale_get(stmdev_ctx_t *ctx, iis2dlpc_fs_t *val);
+int32_t iis2dlpc_full_scale_get(stmdev_ctx_t *ctx,
+ iis2dlpc_fs_t *val);
-int32_t iis2dlpc_status_reg_get(stmdev_ctx_t *ctx, iis2dlpc_status_t *val);
+int32_t iis2dlpc_status_reg_get(stmdev_ctx_t *ctx,
+ iis2dlpc_status_t *val);
int32_t iis2dlpc_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef struct{
+typedef struct
+{
iis2dlpc_status_dup_t status_dup;
iis2dlpc_wake_up_src_t wake_up_src;
iis2dlpc_tap_src_t tap_src;
@@ -710,18 +754,20 @@ int32_t iis2dlpc_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t iis2dlpc_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t iis2dlpc_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff);
-typedef enum {
+typedef enum
+{
IIS2DLPC_LSb_977ug = 0,
IIS2DLPC_LSb_15mg6 = 1,
} iis2dlpc_usr_off_w_t;
int32_t iis2dlpc_offset_weight_set(stmdev_ctx_t *ctx,
- iis2dlpc_usr_off_w_t val);
+ iis2dlpc_usr_off_w_t val);
int32_t iis2dlpc_offset_weight_get(stmdev_ctx_t *ctx,
- iis2dlpc_usr_off_w_t *val);
+ iis2dlpc_usr_off_w_t *val);
int32_t iis2dlpc_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val);
-int32_t iis2dlpc_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t iis2dlpc_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
int32_t iis2dlpc_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
@@ -734,7 +780,8 @@ int32_t iis2dlpc_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t iis2dlpc_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2dlpc_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS2DLPC_XL_ST_DISABLE = 0,
IIS2DLPC_XL_ST_POSITIVE = 1,
IIS2DLPC_XL_ST_NEGATIVE = 2,
@@ -742,7 +789,8 @@ typedef enum {
int32_t iis2dlpc_self_test_set(stmdev_ctx_t *ctx, iis2dlpc_st_t val);
int32_t iis2dlpc_self_test_get(stmdev_ctx_t *ctx, iis2dlpc_st_t *val);
-typedef enum {
+typedef enum
+{
IIS2DLPC_DRDY_LATCHED = 0,
IIS2DLPC_DRDY_PULSED = 1,
} iis2dlpc_drdy_pulsed_t;
@@ -751,36 +799,42 @@ int32_t iis2dlpc_data_ready_mode_set(stmdev_ctx_t *ctx,
int32_t iis2dlpc_data_ready_mode_get(stmdev_ctx_t *ctx,
iis2dlpc_drdy_pulsed_t *val);
-typedef enum {
+typedef enum
+{
IIS2DLPC_LPF_ON_OUT = 0x00,
IIS2DLPC_USER_OFFSET_ON_OUT = 0x01,
IIS2DLPC_HIGH_PASS_ON_OUT = 0x10,
} iis2dlpc_fds_t;
-int32_t iis2dlpc_filter_path_set(stmdev_ctx_t *ctx, iis2dlpc_fds_t val);
-int32_t iis2dlpc_filter_path_get(stmdev_ctx_t *ctx, iis2dlpc_fds_t *val);
+int32_t iis2dlpc_filter_path_set(stmdev_ctx_t *ctx,
+ iis2dlpc_fds_t val);
+int32_t iis2dlpc_filter_path_get(stmdev_ctx_t *ctx,
+ iis2dlpc_fds_t *val);
-typedef enum {
+typedef enum
+{
IIS2DLPC_ODR_DIV_2 = 0,
IIS2DLPC_ODR_DIV_4 = 1,
IIS2DLPC_ODR_DIV_10 = 2,
IIS2DLPC_ODR_DIV_20 = 3,
} iis2dlpc_bw_filt_t;
int32_t iis2dlpc_filter_bandwidth_set(stmdev_ctx_t *ctx,
- iis2dlpc_bw_filt_t val);
+ iis2dlpc_bw_filt_t val);
int32_t iis2dlpc_filter_bandwidth_get(stmdev_ctx_t *ctx,
- iis2dlpc_bw_filt_t *val);
+ iis2dlpc_bw_filt_t *val);
int32_t iis2dlpc_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2dlpc_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS2DLPC_SPI_4_WIRE = 0,
IIS2DLPC_SPI_3_WIRE = 1,
} iis2dlpc_sim_t;
int32_t iis2dlpc_spi_mode_set(stmdev_ctx_t *ctx, iis2dlpc_sim_t val);
int32_t iis2dlpc_spi_mode_get(stmdev_ctx_t *ctx, iis2dlpc_sim_t *val);
-typedef enum {
+typedef enum
+{
IIS2DLPC_I2C_ENABLE = 0,
IIS2DLPC_I2C_DISABLE = 1,
} iis2dlpc_i2c_disable_t;
@@ -789,14 +843,18 @@ int32_t iis2dlpc_i2c_interface_set(stmdev_ctx_t *ctx,
int32_t iis2dlpc_i2c_interface_get(stmdev_ctx_t *ctx,
iis2dlpc_i2c_disable_t *val);
-typedef enum {
+typedef enum
+{
IIS2DLPC_PULL_UP_CONNECT = 0,
IIS2DLPC_PULL_UP_DISCONNECT = 1,
} iis2dlpc_cs_pu_disc_t;
-int32_t iis2dlpc_cs_mode_set(stmdev_ctx_t *ctx, iis2dlpc_cs_pu_disc_t val);
-int32_t iis2dlpc_cs_mode_get(stmdev_ctx_t *ctx, iis2dlpc_cs_pu_disc_t *val);
+int32_t iis2dlpc_cs_mode_set(stmdev_ctx_t *ctx,
+ iis2dlpc_cs_pu_disc_t val);
+int32_t iis2dlpc_cs_mode_get(stmdev_ctx_t *ctx,
+ iis2dlpc_cs_pu_disc_t *val);
-typedef enum {
+typedef enum
+{
IIS2DLPC_ACTIVE_HIGH = 0,
IIS2DLPC_ACTIVE_LOW = 1,
} iis2dlpc_h_lactive_t;
@@ -805,7 +863,8 @@ int32_t iis2dlpc_pin_polarity_set(stmdev_ctx_t *ctx,
int32_t iis2dlpc_pin_polarity_get(stmdev_ctx_t *ctx,
iis2dlpc_h_lactive_t *val);
-typedef enum {
+typedef enum
+{
IIS2DLPC_INT_PULSED = 0,
IIS2DLPC_INT_LATCHED = 1,
} iis2dlpc_lir_t;
@@ -814,12 +873,15 @@ int32_t iis2dlpc_int_notification_set(stmdev_ctx_t *ctx,
int32_t iis2dlpc_int_notification_get(stmdev_ctx_t *ctx,
iis2dlpc_lir_t *val);
-typedef enum {
+typedef enum
+{
IIS2DLPC_PUSH_PULL = 0,
IIS2DLPC_OPEN_DRAIN = 1,
} iis2dlpc_pp_od_t;
-int32_t iis2dlpc_pin_mode_set(stmdev_ctx_t *ctx, iis2dlpc_pp_od_t val);
-int32_t iis2dlpc_pin_mode_get(stmdev_ctx_t *ctx, iis2dlpc_pp_od_t *val);
+int32_t iis2dlpc_pin_mode_set(stmdev_ctx_t *ctx,
+ iis2dlpc_pp_od_t val);
+int32_t iis2dlpc_pin_mode_get(stmdev_ctx_t *ctx,
+ iis2dlpc_pp_od_t *val);
int32_t iis2dlpc_pin_int1_route_set(stmdev_ctx_t *ctx,
iis2dlpc_ctrl4_int1_pad_ctrl_t *val);
@@ -840,7 +902,8 @@ int32_t iis2dlpc_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t iis2dlpc_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2dlpc_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS2DLPC_HP_FEED = 0,
IIS2DLPC_USER_OFFSET_FEED = 1,
} iis2dlpc_usr_off_on_wu_t;
@@ -849,13 +912,16 @@ int32_t iis2dlpc_wkup_feed_data_set(stmdev_ctx_t *ctx,
int32_t iis2dlpc_wkup_feed_data_get(stmdev_ctx_t *ctx,
iis2dlpc_usr_off_on_wu_t *val);
-typedef enum {
+typedef enum
+{
IIS2DLPC_NO_DETECTION = 0,
IIS2DLPC_DETECT_ACT_INACT = 1,
IIS2DLPC_DETECT_STAT_MOTION = 3,
} iis2dlpc_sleep_on_t;
-int32_t iis2dlpc_act_mode_set(stmdev_ctx_t *ctx, iis2dlpc_sleep_on_t val);
-int32_t iis2dlpc_act_mode_get(stmdev_ctx_t *ctx, iis2dlpc_sleep_on_t *val);
+int32_t iis2dlpc_act_mode_set(stmdev_ctx_t *ctx,
+ iis2dlpc_sleep_on_t val);
+int32_t iis2dlpc_act_mode_get(stmdev_ctx_t *ctx,
+ iis2dlpc_sleep_on_t *val);
int32_t iis2dlpc_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2dlpc_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -866,7 +932,8 @@ int32_t iis2dlpc_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t iis2dlpc_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2dlpc_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS2DLPC_XYZ = 0,
IIS2DLPC_YXZ = 1,
IIS2DLPC_XZY = 2,
@@ -882,14 +949,20 @@ int32_t iis2dlpc_tap_axis_priority_get(stmdev_ctx_t *ctx,
int32_t iis2dlpc_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2dlpc_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t iis2dlpc_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis2dlpc_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis2dlpc_tap_detection_on_z_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t iis2dlpc_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t iis2dlpc_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis2dlpc_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis2dlpc_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t iis2dlpc_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t iis2dlpc_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis2dlpc_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis2dlpc_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t iis2dlpc_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t iis2dlpc_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2dlpc_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -900,7 +973,8 @@ int32_t iis2dlpc_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t iis2dlpc_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2dlpc_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS2DLPC_ONLY_SINGLE = 0,
IIS2DLPC_BOTH_SINGLE_DOUBLE = 1,
} iis2dlpc_single_double_tap_t;
@@ -909,7 +983,8 @@ int32_t iis2dlpc_tap_mode_set(stmdev_ctx_t *ctx,
int32_t iis2dlpc_tap_mode_get(stmdev_ctx_t *ctx,
iis2dlpc_single_double_tap_t *val);
-int32_t iis2dlpc_tap_src_get(stmdev_ctx_t *ctx, iis2dlpc_tap_src_t *val);
+int32_t iis2dlpc_tap_src_get(stmdev_ctx_t *ctx,
+ iis2dlpc_tap_src_t *val);
int32_t iis2dlpc_6d_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2dlpc_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -917,9 +992,11 @@ int32_t iis2dlpc_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t iis2dlpc_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2dlpc_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t iis2dlpc_6d_src_get(stmdev_ctx_t *ctx, iis2dlpc_sixd_src_t *val);
+int32_t iis2dlpc_6d_src_get(stmdev_ctx_t *ctx,
+ iis2dlpc_sixd_src_t *val);
-typedef enum {
+typedef enum
+{
IIS2DLPC_ODR_DIV_2_FEED = 0,
IIS2DLPC_LPF2_FEED = 1,
} iis2dlpc_lpass_on6d_t;
@@ -931,7 +1008,8 @@ int32_t iis2dlpc_6d_feed_data_get(stmdev_ctx_t *ctx,
int32_t iis2dlpc_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2dlpc_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS2DLPC_FF_TSH_5LSb_FS2g = 0,
IIS2DLPC_FF_TSH_7LSb_FS2g = 1,
IIS2DLPC_FF_TSH_8LSb_FS2g = 2,
@@ -949,15 +1027,18 @@ int32_t iis2dlpc_ff_threshold_get(stmdev_ctx_t *ctx,
int32_t iis2dlpc_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2dlpc_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS2DLPC_BYPASS_MODE = 0,
IIS2DLPC_FIFO_MODE = 1,
IIS2DLPC_STREAM_TO_FIFO_MODE = 3,
IIS2DLPC_BYPASS_TO_STREAM_MODE = 4,
IIS2DLPC_STREAM_MODE = 6,
} iis2dlpc_fmode_t;
-int32_t iis2dlpc_fifo_mode_set(stmdev_ctx_t *ctx, iis2dlpc_fmode_t val);
-int32_t iis2dlpc_fifo_mode_get(stmdev_ctx_t *ctx, iis2dlpc_fmode_t *val);
+int32_t iis2dlpc_fifo_mode_set(stmdev_ctx_t *ctx,
+ iis2dlpc_fmode_t val);
+int32_t iis2dlpc_fifo_mode_get(stmdev_ctx_t *ctx,
+ iis2dlpc_fmode_t *val);
int32_t iis2dlpc_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val);
diff --git a/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.c b/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.c
index 618dd9cf23440764318b208272efc2f71d0a6a2a..f6ca0f0a6efd1be1ded164c0307bd50135c261cd 100644
--- a/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.c
+++ b/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file iis2iclx_reg.c
- * @author Sensors Software Solution Team
- * @brief IIS2ICLX driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file iis2iclx_reg.c
+ * @author Sensors Software Solution Team
+ * @brief IIS2ICLX driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "iis2iclx_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2iclx_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t iis2iclx_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t iis2iclx_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2iclx_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t iis2iclx_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -136,17 +142,20 @@ float_t iis2iclx_from_lsb_to_nsec(int32_t lsb)
*
*/
int32_t iis2iclx_xl_full_scale_set(stmdev_ctx_t *ctx,
- iis2iclx_fs_xl_t val)
+ iis2iclx_fs_xl_t val)
{
iis2iclx_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
ctrl1_xl.fs_xl = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
+ (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -159,29 +168,36 @@ int32_t iis2iclx_xl_full_scale_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_xl_full_scale_get(stmdev_ctx_t *ctx,
- iis2iclx_fs_xl_t *val)
+ iis2iclx_fs_xl_t *val)
{
iis2iclx_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- switch (ctrl1_xl.fs_xl){
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ switch (ctrl1_xl.fs_xl)
+ {
case IIS2ICLX_500mg:
*val = IIS2ICLX_500mg;
break;
+
case IIS2ICLX_3g:
*val = IIS2ICLX_3g;
break;
+
case IIS2ICLX_1g:
*val = IIS2ICLX_1g;
break;
+
case IIS2ICLX_2g:
*val = IIS2ICLX_2g;
break;
+
default:
*val = IIS2ICLX_500mg;
break;
}
+
return ret;
}
@@ -209,81 +225,114 @@ int32_t iis2iclx_xl_data_rate_set(stmdev_ctx_t *ctx,
/* Check the Finite State Machine data rate constraints */
ret = iis2iclx_fsm_enable_get(ctx, &fsm_enable);
- if (ret == 0) {
- if ( (fsm_enable.fsm_enable_a.fsm1_en |
- fsm_enable.fsm_enable_a.fsm2_en |
- fsm_enable.fsm_enable_a.fsm3_en |
- fsm_enable.fsm_enable_a.fsm4_en |
- fsm_enable.fsm_enable_a.fsm5_en |
- fsm_enable.fsm_enable_a.fsm6_en |
- fsm_enable.fsm_enable_a.fsm7_en |
- fsm_enable.fsm_enable_a.fsm8_en |
- fsm_enable.fsm_enable_b.fsm9_en |
- fsm_enable.fsm_enable_b.fsm10_en |
- fsm_enable.fsm_enable_b.fsm11_en |
- fsm_enable.fsm_enable_b.fsm12_en |
- fsm_enable.fsm_enable_b.fsm13_en |
- fsm_enable.fsm_enable_b.fsm14_en |
- fsm_enable.fsm_enable_b.fsm15_en |
- fsm_enable.fsm_enable_b.fsm16_en ) == PROPERTY_ENABLE ){
+ if (ret == 0)
+ {
+ if ((fsm_enable.fsm_enable_a.fsm1_en |
+ fsm_enable.fsm_enable_a.fsm2_en |
+ fsm_enable.fsm_enable_a.fsm3_en |
+ fsm_enable.fsm_enable_a.fsm4_en |
+ fsm_enable.fsm_enable_a.fsm5_en |
+ fsm_enable.fsm_enable_a.fsm6_en |
+ fsm_enable.fsm_enable_a.fsm7_en |
+ fsm_enable.fsm_enable_a.fsm8_en |
+ fsm_enable.fsm_enable_b.fsm9_en |
+ fsm_enable.fsm_enable_b.fsm10_en |
+ fsm_enable.fsm_enable_b.fsm11_en |
+ fsm_enable.fsm_enable_b.fsm12_en |
+ fsm_enable.fsm_enable_b.fsm13_en |
+ fsm_enable.fsm_enable_b.fsm14_en |
+ fsm_enable.fsm_enable_b.fsm15_en |
+ fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
+ {
ret = iis2iclx_fsm_data_rate_get(ctx, &fsm_odr);
- if (ret == 0) {
- switch (fsm_odr) {
- case IIS2ICLX_ODR_FSM_12Hz5:
- if (val == IIS2ICLX_XL_ODR_OFF){
+ if (ret == 0)
+ {
+ switch (fsm_odr)
+ {
+ case IIS2ICLX_ODR_FSM_12Hz5:
+ if (val == IIS2ICLX_XL_ODR_OFF)
+ {
odr_xl = IIS2ICLX_XL_ODR_12Hz5;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
- case IIS2ICLX_ODR_FSM_26Hz:
- if (val == IIS2ICLX_XL_ODR_OFF){
+ case IIS2ICLX_ODR_FSM_26Hz:
+ if (val == IIS2ICLX_XL_ODR_OFF)
+ {
odr_xl = IIS2ICLX_XL_ODR_26Hz;
+ }
- } else if (val == IIS2ICLX_XL_ODR_12Hz5){
+ else if (val == IIS2ICLX_XL_ODR_12Hz5)
+ {
odr_xl = IIS2ICLX_XL_ODR_26Hz;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
- case IIS2ICLX_ODR_FSM_52Hz:
- if (val == IIS2ICLX_XL_ODR_OFF){
+ case IIS2ICLX_ODR_FSM_52Hz:
+ if (val == IIS2ICLX_XL_ODR_OFF)
+ {
odr_xl = IIS2ICLX_XL_ODR_52Hz;
+ }
- } else if (val == IIS2ICLX_XL_ODR_12Hz5){
+ else if (val == IIS2ICLX_XL_ODR_12Hz5)
+ {
odr_xl = IIS2ICLX_XL_ODR_52Hz;
+ }
- } else if (val == IIS2ICLX_XL_ODR_26Hz){
+ else if (val == IIS2ICLX_XL_ODR_26Hz)
+ {
odr_xl = IIS2ICLX_XL_ODR_52Hz;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
- case IIS2ICLX_ODR_FSM_104Hz:
- if (val == IIS2ICLX_XL_ODR_OFF){
+ case IIS2ICLX_ODR_FSM_104Hz:
+ if (val == IIS2ICLX_XL_ODR_OFF)
+ {
odr_xl = IIS2ICLX_XL_ODR_104Hz;
+ }
- } else if (val == IIS2ICLX_XL_ODR_12Hz5){
+ else if (val == IIS2ICLX_XL_ODR_12Hz5)
+ {
odr_xl = IIS2ICLX_XL_ODR_104Hz;
+ }
- } else if (val == IIS2ICLX_XL_ODR_26Hz){
+ else if (val == IIS2ICLX_XL_ODR_26Hz)
+ {
odr_xl = IIS2ICLX_XL_ODR_104Hz;
+ }
- } else if (val == IIS2ICLX_XL_ODR_52Hz){
+ else if (val == IIS2ICLX_XL_ODR_52Hz)
+ {
odr_xl = IIS2ICLX_XL_ODR_104Hz;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
+
default:
odr_xl = val;
break;
@@ -294,65 +343,101 @@ int32_t iis2iclx_xl_data_rate_set(stmdev_ctx_t *ctx,
/* Check the Machine Learning Core data rate constraints */
mlc_enable = PROPERTY_DISABLE;
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = iis2iclx_mlc_get(ctx, &mlc_enable);
- if ( mlc_enable == PROPERTY_ENABLE ){
+ if (mlc_enable == PROPERTY_ENABLE)
+ {
ret = iis2iclx_mlc_data_rate_get(ctx, &mlc_odr);
- if (ret == 0) {
- switch (mlc_odr) {
- case IIS2ICLX_ODR_PRGS_12Hz5:
- if (val == IIS2ICLX_XL_ODR_OFF){
+ if (ret == 0)
+ {
+ switch (mlc_odr)
+ {
+ case IIS2ICLX_ODR_PRGS_12Hz5:
+ if (val == IIS2ICLX_XL_ODR_OFF)
+ {
odr_xl = IIS2ICLX_XL_ODR_12Hz5;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
+
case IIS2ICLX_ODR_PRGS_26Hz:
- if (val == IIS2ICLX_XL_ODR_OFF){
+ if (val == IIS2ICLX_XL_ODR_OFF)
+ {
odr_xl = IIS2ICLX_XL_ODR_26Hz;
+ }
- } else if (val == IIS2ICLX_XL_ODR_12Hz5){
+ else if (val == IIS2ICLX_XL_ODR_12Hz5)
+ {
odr_xl = IIS2ICLX_XL_ODR_26Hz;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
- case IIS2ICLX_ODR_PRGS_52Hz:
- if (val == IIS2ICLX_XL_ODR_OFF){
+ case IIS2ICLX_ODR_PRGS_52Hz:
+ if (val == IIS2ICLX_XL_ODR_OFF)
+ {
odr_xl = IIS2ICLX_XL_ODR_52Hz;
+ }
- } else if (val == IIS2ICLX_XL_ODR_12Hz5){
+ else if (val == IIS2ICLX_XL_ODR_12Hz5)
+ {
odr_xl = IIS2ICLX_XL_ODR_52Hz;
+ }
- } else if (val == IIS2ICLX_XL_ODR_26Hz){
+ else if (val == IIS2ICLX_XL_ODR_26Hz)
+ {
odr_xl = IIS2ICLX_XL_ODR_52Hz;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
+
case IIS2ICLX_ODR_PRGS_104Hz:
- if (val == IIS2ICLX_XL_ODR_OFF){
+ if (val == IIS2ICLX_XL_ODR_OFF)
+ {
odr_xl = IIS2ICLX_XL_ODR_104Hz;
+ }
- } else if (val == IIS2ICLX_XL_ODR_12Hz5){
+ else if (val == IIS2ICLX_XL_ODR_12Hz5)
+ {
odr_xl = IIS2ICLX_XL_ODR_104Hz;
+ }
- } else if (val == IIS2ICLX_XL_ODR_26Hz){
+ else if (val == IIS2ICLX_XL_ODR_26Hz)
+ {
odr_xl = IIS2ICLX_XL_ODR_104Hz;
+ }
- } else if (val == IIS2ICLX_XL_ODR_52Hz){
+ else if (val == IIS2ICLX_XL_ODR_52Hz)
+ {
odr_xl = IIS2ICLX_XL_ODR_104Hz;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
+
default:
odr_xl = val;
break;
@@ -360,49 +445,68 @@ int32_t iis2iclx_xl_data_rate_set(stmdev_ctx_t *ctx,
}
}
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_SEL, (uint8_t*)&page_sel, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_SEL, (uint8_t *)&page_sel, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_sel.not_used_01 = 0x01U;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
+ (uint8_t *)&page_sel, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_ODR_CFG_B,
- (uint8_t*)&emb_func_odr_cfg_b, 1);
+ (uint8_t *)&emb_func_odr_cfg_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
emb_func_odr_cfg_b.not_used_01 = 0x03U;
emb_func_odr_cfg_b.not_used_02 = 0x02U;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_EMB_FUNC_ODR_CFG_B,
- (uint8_t*)&emb_func_odr_cfg_b, 1);
+ (uint8_t *)&emb_func_odr_cfg_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_ODR_CFG_C,
- (uint8_t*)&emb_func_odr_cfg_c, 1);
+ (uint8_t *)&emb_func_odr_cfg_c, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
emb_func_odr_cfg_c.not_used_01 = 0x05U;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_EMB_FUNC_ODR_CFG_C,
- (uint8_t*)&emb_func_odr_cfg_c, 1);
+ (uint8_t *)&emb_func_odr_cfg_c, 1);
}
- if(ret == 0){
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
}
- if(ret == 0){
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
+ if (ret == 0)
+ {
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
}
- if(ret == 0){
- ctrl1_xl.odr_xl= (uint8_t)odr_xl;
+
+ if (ret == 0)
+ {
+ ctrl1_xl.odr_xl = (uint8_t)odr_xl;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
+ (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -415,41 +519,52 @@ int32_t iis2iclx_xl_data_rate_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_xl_data_rate_get(stmdev_ctx_t *ctx,
- iis2iclx_odr_xl_t *val)
+ iis2iclx_odr_xl_t *val)
{
iis2iclx_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- switch (ctrl1_xl.odr_xl){
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ switch (ctrl1_xl.odr_xl)
+ {
case IIS2ICLX_XL_ODR_OFF:
*val = IIS2ICLX_XL_ODR_OFF;
break;
+
case IIS2ICLX_XL_ODR_12Hz5:
*val = IIS2ICLX_XL_ODR_12Hz5;
break;
+
case IIS2ICLX_XL_ODR_26Hz:
*val = IIS2ICLX_XL_ODR_26Hz;
break;
+
case IIS2ICLX_XL_ODR_52Hz:
*val = IIS2ICLX_XL_ODR_52Hz;
break;
+
case IIS2ICLX_XL_ODR_104Hz:
*val = IIS2ICLX_XL_ODR_104Hz;
break;
+
case IIS2ICLX_XL_ODR_208Hz:
*val = IIS2ICLX_XL_ODR_208Hz;
break;
+
case IIS2ICLX_XL_ODR_416Hz:
*val = IIS2ICLX_XL_ODR_416Hz;
break;
+
case IIS2ICLX_XL_ODR_833Hz:
*val = IIS2ICLX_XL_ODR_833Hz;
break;
+
default:
*val = IIS2ICLX_XL_ODR_OFF;
break;
}
+
return ret;
}
@@ -466,11 +581,14 @@ int32_t iis2iclx_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
iis2iclx_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.bdu= (uint8_t)val;
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.bdu = (uint8_t)val;
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -482,12 +600,13 @@ int32_t iis2iclx_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis2iclx_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t iis2iclx_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
iis2iclx_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.bdu;
return ret;
@@ -503,16 +622,19 @@ int32_t iis2iclx_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t iis2iclx_xl_offset_weight_set(stmdev_ctx_t *ctx,
- iis2iclx_usr_off_w_t val)
+ iis2iclx_usr_off_w_t val)
{
iis2iclx_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
- ctrl6_c.usr_off_w= (uint8_t)val;
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl6_c.usr_off_w = (uint8_t)val;
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -526,24 +648,28 @@ int32_t iis2iclx_xl_offset_weight_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_xl_offset_weight_get(stmdev_ctx_t *ctx,
- iis2iclx_usr_off_w_t *val)
+ iis2iclx_usr_off_w_t *val)
{
iis2iclx_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
- switch (ctrl6_c.usr_off_w){
+ switch (ctrl6_c.usr_off_w)
+ {
case IIS2ICLX_LSb_1mg:
*val = IIS2ICLX_LSb_1mg;
break;
+
case IIS2ICLX_LSb_16mg:
*val = IIS2ICLX_LSb_16mg;
break;
+
default:
*val = IIS2ICLX_LSb_1mg;
break;
}
+
return ret;
}
@@ -558,44 +684,62 @@ int32_t iis2iclx_xl_offset_weight_get(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_all_sources_get(stmdev_ctx_t *ctx,
- iis2iclx_all_sources_t *val)
+ iis2iclx_all_sources_t *val)
{
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_ALL_INT_SRC,
- (uint8_t*)&val->all_int_src, 1);
- if(ret == 0){
+ (uint8_t *)&val->all_int_src, 1);
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_SRC,
- (uint8_t*)&val->wake_up_src, 1);
+ (uint8_t *)&val->wake_up_src, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_SRC,
- (uint8_t*)&val->tap_src, 1);
+ (uint8_t *)&val->tap_src, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_DEN_SRC,
- (uint8_t*)&val->den_src, 1);
+ (uint8_t *)&val->den_src, 1);
}
- if(ret == 0){
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_STATUS_REG,
- (uint8_t*)&val->status_reg, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_STATUS_REG,
+ (uint8_t *)&val->status_reg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_STATUS,
- (uint8_t*)&val->emb_func_status, 1);
+ (uint8_t *)&val->emb_func_status, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FSM_STATUS_A,
- (uint8_t*)&val->fsm_status_a, 1);
+ (uint8_t *)&val->fsm_status_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FSM_STATUS_B,
- (uint8_t*)&val->fsm_status_b, 1);
+ (uint8_t *)&val->fsm_status_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
@@ -611,10 +755,12 @@ int32_t iis2iclx_all_sources_get(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_status_reg_get(stmdev_ctx_t *ctx,
- iis2iclx_status_reg_t *val)
+ iis2iclx_status_reg_t *val)
{
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_STATUS_REG, (uint8_t*) val, 1);
+
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_STATUS_REG, (uint8_t *) val, 1);
+
return ret;
}
@@ -626,13 +772,14 @@ int32_t iis2iclx_status_reg_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis2iclx_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t iis2iclx_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
iis2iclx_status_reg_t status_reg;
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_STATUS_REG,
- (uint8_t*)&status_reg, 1);
+ (uint8_t *)&status_reg, 1);
*val = status_reg.xlda;
return ret;
@@ -646,13 +793,14 @@ int32_t iis2iclx_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis2iclx_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t iis2iclx_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
iis2iclx_status_reg_t status_reg;
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_STATUS_REG,
- (uint8_t*)&status_reg, 1);
+ (uint8_t *)&status_reg, 1);
*val = status_reg.tda;
return ret;
@@ -671,7 +819,9 @@ int32_t iis2iclx_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t iis2iclx_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = iis2iclx_write_reg(ctx, IIS2ICLX_X_OFS_USR, buff, 1);
+
return ret;
}
@@ -688,7 +838,9 @@ int32_t iis2iclx_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t iis2iclx_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = iis2iclx_read_reg(ctx, IIS2ICLX_X_OFS_USR, buff, 1);
+
return ret;
}
@@ -705,7 +857,9 @@ int32_t iis2iclx_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t iis2iclx_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = iis2iclx_write_reg(ctx, IIS2ICLX_Y_OFS_USR, buff, 1);
+
return ret;
}
@@ -722,7 +876,9 @@ int32_t iis2iclx_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t iis2iclx_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = iis2iclx_read_reg(ctx, IIS2ICLX_Y_OFS_USR, buff, 1);
+
return ret;
}
@@ -739,11 +895,14 @@ int32_t iis2iclx_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val)
iis2iclx_ctrl7_xl_t ctrl7_xl;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL7_XL, (uint8_t*)&ctrl7_xl, 1);
- if(ret == 0){
- ctrl7_xl.usr_off_on_out= (uint8_t)val;
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL7_XL, (uint8_t*)&ctrl7_xl, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL7_XL, (uint8_t *)&ctrl7_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl7_xl.usr_off_on_out = (uint8_t)val;
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL7_XL, (uint8_t *)&ctrl7_xl, 1);
}
+
return ret;
}
@@ -760,7 +919,7 @@ int32_t iis2iclx_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2iclx_ctrl7_xl_t ctrl7_xl;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL7_XL, (uint8_t*)&ctrl7_xl, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL7_XL, (uint8_t *)&ctrl7_xl, 1);
*val = ctrl7_xl.usr_off_on_out;
return ret;
@@ -792,12 +951,15 @@ int32_t iis2iclx_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
iis2iclx_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
- ctrl10_c.timestamp_en= (uint8_t)val;
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl10_c.timestamp_en = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL10_C,
- (uint8_t*)&ctrl10_c, 1);
+ (uint8_t *)&ctrl10_c, 1);
}
+
return ret;
}
@@ -814,7 +976,7 @@ int32_t iis2iclx_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2iclx_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
*val = ctrl10_c.timestamp_en;
return ret;
@@ -837,7 +999,7 @@ int32_t iis2iclx_timestamp_raw_get(stmdev_ctx_t *ctx, int32_t *val)
ret = iis2iclx_read_reg(ctx, IIS2ICLX_TIMESTAMP0, buff, 4);
val[0] = (int16_t)buff[1];
- val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
val[1] = (val[1] * 256) + (int16_t)buff[2];
@@ -873,7 +1035,7 @@ int32_t iis2iclx_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
ret = iis2iclx_read_reg(ctx, IIS2ICLX_OUT_TEMP_L, buff, 2);
*val = (int16_t)buff[1];
- *val = (*val * 256) + (int16_t)buff[0];
+ *val = (*val * 256) + (int16_t)buff[0];
return ret;
}
@@ -894,9 +1056,9 @@ int32_t iis2iclx_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
ret = iis2iclx_read_reg(ctx, IIS2ICLX_OUTX_L_A, buff, 4);
val[0] = (int16_t)buff[1];
- val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
- val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
return ret;
}
@@ -912,7 +1074,9 @@ int32_t iis2iclx_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
int32_t iis2iclx_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_DATA_OUT_X_L, buff, 6);
+
return ret;
}
@@ -923,11 +1087,54 @@ int32_t iis2iclx_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
/**
* @defgroup IIS2ICLX_common
- * @brief This section groups common usefull functions.
+ * @brief This section groups common useful functions.
* @{
*
*/
+/**
+ * @brief DEVICE_CONF bit configuration[set]
+ *
+ * @param ctx Read / write interface definitions.(ptr)
+ * @param val Change the values of device_conf in reg CTRL9_XL
+ * @retval Interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t iis2iclx_device_conf_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ iis2iclx_ctrl9_xl_t ctrl9_xl;
+ int32_t ret;
+
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl9_xl.device_conf = (uint8_t)val;
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief DEVICE_CONF bit configuration[get]
+ *
+ * @param ctx Read / write interface definitions.(ptr)
+ * @param val Get the values of device_conf in reg CTRL9_XL
+ * @retval Interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t iis2iclx_device_conf_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ iis2iclx_ctrl9_xl_t ctrl9_xl;
+ int32_t ret;
+
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+ *val = ctrl9_xl.device_conf;
+
+ return ret;
+}
+
/**
* @brief Difference in percentage of the effective ODR (and timestamp rate)
* with respect to the typical.[set]
@@ -944,12 +1151,15 @@ int32_t iis2iclx_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_INTERNAL_FREQ_FINE,
- (uint8_t*)&internal_freq_fine, 1);
- if(ret == 0){
- internal_freq_fine.freq_fine= (uint8_t)val;
+ (uint8_t *)&internal_freq_fine, 1);
+
+ if (ret == 0)
+ {
+ internal_freq_fine.freq_fine = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_INTERNAL_FREQ_FINE,
- (uint8_t*)&internal_freq_fine, 1);
+ (uint8_t *)&internal_freq_fine, 1);
}
+
return ret;
}
@@ -969,7 +1179,7 @@ int32_t iis2iclx_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_INTERNAL_FREQ_FINE,
- (uint8_t*)&internal_freq_fine, 1);
+ (uint8_t *)&internal_freq_fine, 1);
*val = internal_freq_fine.freq_fine;
return ret;
@@ -985,18 +1195,21 @@ int32_t iis2iclx_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t iis2iclx_mem_bank_set(stmdev_ctx_t *ctx,
- iis2iclx_reg_access_t val)
+ iis2iclx_reg_access_t val)
{
iis2iclx_func_cfg_access_t func_cfg_access;
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
- if(ret == 0){
- func_cfg_access.reg_access= (uint8_t)val;
+ (uint8_t *)&func_cfg_access, 1);
+
+ if (ret == 0)
+ {
+ func_cfg_access.reg_access = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
+ (uint8_t *)&func_cfg_access, 1);
}
+
return ret;
}
@@ -1010,27 +1223,33 @@ int32_t iis2iclx_mem_bank_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_mem_bank_get(stmdev_ctx_t *ctx,
- iis2iclx_reg_access_t *val)
+ iis2iclx_reg_access_t *val)
{
iis2iclx_func_cfg_access_t func_cfg_access;
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
- switch (func_cfg_access.reg_access){
+ (uint8_t *)&func_cfg_access, 1);
+
+ switch (func_cfg_access.reg_access)
+ {
case IIS2ICLX_USER_BANK:
*val = IIS2ICLX_USER_BANK;
break;
+
case IIS2ICLX_SENSOR_HUB_BANK:
*val = IIS2ICLX_SENSOR_HUB_BANK;
break;
+
case IIS2ICLX_EMBEDDED_FUNC_BANK:
*val = IIS2ICLX_EMBEDDED_FUNC_BANK;
break;
+
default:
*val = IIS2ICLX_USER_BANK;
break;
}
+
return ret;
}
@@ -1044,7 +1263,7 @@ int32_t iis2iclx_mem_bank_get(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t add,
- uint8_t *val)
+ uint8_t *val)
{
iis2iclx_page_rw_t page_rw;
iis2iclx_page_sel_t page_sel;
@@ -1052,40 +1271,59 @@ int32_t iis2iclx_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t add,
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t*)&page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x02U; /* page_write enable */
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t*)&page_rw, 1);
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_SEL, (uint8_t*)&page_sel, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_SEL, (uint8_t *)&page_sel, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_sel.page_sel = (uint8_t)((add >> 8) & 0x0FU);
page_sel.not_used_01 = 1;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
+ (uint8_t *)&page_sel, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_address.page_addr = (uint8_t)(add & 0xFFU);
ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_ADDRESS,
- (uint8_t*)&page_address, 1);
+ (uint8_t *)&page_address, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_VALUE, val, 1);
}
- if(ret == 0){
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t*)&page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x00; /* page_write disable */
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t*)&page_rw, 1);
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -1095,82 +1333,108 @@ int32_t iis2iclx_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t add,
* @param ctx Read / write interface definitions.(ptr)
* @param buf Page line address.(ptr)
* @param val Value to write.
- * @param len buffer lengh.
+ * @param len buffer length.
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
int32_t iis2iclx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t add,
- uint8_t *buf, uint8_t len)
+ uint8_t *buf, uint8_t len)
{
iis2iclx_page_rw_t page_rw;
iis2iclx_page_sel_t page_sel;
iis2iclx_page_address_t page_address;
int32_t ret;
+
uint8_t msb, lsb;
uint8_t i ;
-
msb = (uint8_t)((add >> 8) & 0x0FU);
lsb = (uint8_t)(add & 0xFFU);
-
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t*)&page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x02U; /* page_write enable*/
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t*)&page_rw, 1);
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_SEL, (uint8_t*)&page_sel, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_SEL, (uint8_t *)&page_sel, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_sel.page_sel = msb;
page_sel.not_used_01 = 1;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
+ (uint8_t *)&page_sel, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_address.page_addr = lsb;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_ADDRESS,
- (uint8_t*)&page_address, 1);
+ (uint8_t *)&page_address, 1);
}
- for (i = 0; i < len; i++){
- if(ret == 0){
+
+ for (i = 0; i < len; i++)
+ {
+ if (ret == 0)
+ {
ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_VALUE, &buf[i], 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
/* Check if page wrap */
- if (lsb == 0x00U){
+ if (lsb == 0x00U)
+ {
msb++;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
+ (uint8_t *)&page_sel, 1);
}
+
lsb++;
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_sel.page_sel = msb;
page_sel.not_used_01 = 1;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
+ (uint8_t *)&page_sel, 1);
}
}
}
- if(ret == 0){
+ if (ret == 0)
+ {
page_sel.page_sel = 0;
page_sel.not_used_01 = 1;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
+ (uint8_t *)&page_sel, 1);
}
- if(ret == 0){
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t*)&page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x00U; /* page_write disable */
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t*)&page_rw, 1);
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -1184,7 +1448,7 @@ int32_t iis2iclx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t add,
*
*/
int32_t iis2iclx_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add,
- uint8_t *val)
+ uint8_t *val)
{
iis2iclx_page_rw_t page_rw;
iis2iclx_page_sel_t page_sel;
@@ -1192,40 +1456,59 @@ int32_t iis2iclx_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add,
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t*)&page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x01U; /* page_read enable*/
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t*)&page_rw, 1);
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_SEL, (uint8_t*)&page_sel, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_SEL, (uint8_t *)&page_sel, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_sel.page_sel = (uint8_t)((add >> 8) & 0x0FU);
page_sel.not_used_01 = 1;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
+ (uint8_t *)&page_sel, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_address.page_addr = (uint8_t)(add & 0x00FFU);
ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_ADDRESS,
- (uint8_t*)&page_address, 1);
+ (uint8_t *)&page_address, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_VALUE, val, 2);
}
- if(ret == 0){
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t*)&page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x00U; /* page_read disable */
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t*)&page_rw, 1);
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -1239,18 +1522,21 @@ int32_t iis2iclx_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add,
*
*/
int32_t iis2iclx_data_ready_mode_set(stmdev_ctx_t *ctx,
- iis2iclx_dataready_pulsed_t val)
+ iis2iclx_dataready_pulsed_t val)
{
iis2iclx_counter_bdr_reg1_t counter_bdr_reg1;
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if(ret == 0){
- counter_bdr_reg1.dataready_pulsed= (uint8_t)val;
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
+ counter_bdr_reg1.dataready_pulsed = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
}
+
return ret;
}
@@ -1264,24 +1550,29 @@ int32_t iis2iclx_data_ready_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_data_ready_mode_get(stmdev_ctx_t *ctx,
- iis2iclx_dataready_pulsed_t *val)
+ iis2iclx_dataready_pulsed_t *val)
{
iis2iclx_counter_bdr_reg1_t counter_bdr_reg1;
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- switch (counter_bdr_reg1.dataready_pulsed){
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ switch (counter_bdr_reg1.dataready_pulsed)
+ {
case IIS2ICLX_DRDY_LATCHED:
*val = IIS2ICLX_DRDY_LATCHED;
break;
+
case IIS2ICLX_DRDY_PULSED:
*val = IIS2ICLX_DRDY_PULSED;
break;
+
default:
*val = IIS2ICLX_DRDY_LATCHED;
break;
}
+
return ret;
}
@@ -1296,7 +1587,9 @@ int32_t iis2iclx_data_ready_mode_get(stmdev_ctx_t *ctx,
int32_t iis2iclx_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = iis2iclx_read_reg(ctx, IIS2ICLX_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -1313,11 +1606,14 @@ int32_t iis2iclx_reset_set(stmdev_ctx_t *ctx, uint8_t val)
iis2iclx_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.sw_reset= (uint8_t)val;
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.sw_reset = (uint8_t)val;
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1334,7 +1630,7 @@ int32_t iis2iclx_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2iclx_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.sw_reset;
return ret;
@@ -1354,11 +1650,14 @@ int32_t iis2iclx_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
iis2iclx_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.if_inc= (uint8_t)val;
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.if_inc = (uint8_t)val;
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1376,7 +1675,7 @@ int32_t iis2iclx_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2iclx_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.if_inc;
return ret;
@@ -1395,11 +1694,14 @@ int32_t iis2iclx_boot_set(stmdev_ctx_t *ctx, uint8_t val)
iis2iclx_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.boot= (uint8_t)val;
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.boot = (uint8_t)val;
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1416,7 +1718,7 @@ int32_t iis2iclx_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2iclx_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.boot;
return ret;
@@ -1433,16 +1735,19 @@ int32_t iis2iclx_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t iis2iclx_xl_self_test_set(stmdev_ctx_t *ctx,
- iis2iclx_st_xl_t val)
+ iis2iclx_st_xl_t val)
{
iis2iclx_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
- ctrl5_c.st_xl= (uint8_t)val;
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl5_c.st_xl = (uint8_t)val;
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -1455,27 +1760,32 @@ int32_t iis2iclx_xl_self_test_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_xl_self_test_get(stmdev_ctx_t *ctx,
- iis2iclx_st_xl_t *val)
+ iis2iclx_st_xl_t *val)
{
iis2iclx_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
- switch (ctrl5_c.st_xl){
+ switch (ctrl5_c.st_xl)
+ {
case IIS2ICLX_XL_ST_DISABLE:
*val = IIS2ICLX_XL_ST_DISABLE;
break;
+
case IIS2ICLX_XL_ST_POSITIVE:
*val = IIS2ICLX_XL_ST_POSITIVE;
break;
+
case IIS2ICLX_XL_ST_NEGATIVE:
*val = IIS2ICLX_XL_ST_NEGATIVE;
break;
+
default:
*val = IIS2ICLX_XL_ST_DISABLE;
break;
}
+
return ret;
}
@@ -1505,12 +1815,15 @@ int32_t iis2iclx_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val)
iis2iclx_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
- ctrl1_xl.lpf2_xl_en= (uint8_t)val;
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl1_xl.lpf2_xl_en = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
+ (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -1527,7 +1840,7 @@ int32_t iis2iclx_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2iclx_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
*val = ctrl1_xl.lpf2_xl_en;
return ret;
@@ -1542,16 +1855,20 @@ int32_t iis2iclx_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis2iclx_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t iis2iclx_filter_settling_mask_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
iis2iclx_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ctrl4_c.drdy_mask= (uint8_t)val;
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl4_c.drdy_mask = (uint8_t)val;
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -1565,12 +1882,12 @@ int32_t iis2iclx_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val)
*
*/
int32_t iis2iclx_filter_settling_mask_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
iis2iclx_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.drdy_mask;
return ret;
@@ -1586,19 +1903,22 @@ int32_t iis2iclx_filter_settling_mask_get(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
- iis2iclx_hp_slope_xl_en_t val)
+ iis2iclx_hp_slope_xl_en_t val)
{
iis2iclx_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
ctrl8_xl.hp_slope_xl_en = (((uint8_t)val & 0x10U) >> 4);
ctrl8_xl.hp_ref_mode_xl = (((uint8_t)val & 0x20U) >> 5);
ctrl8_xl.hpcf_xl = (uint8_t)val & 0x07U;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL8_XL,
- (uint8_t*)&ctrl8_xl, 1);
+ (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -1612,87 +1932,114 @@ int32_t iis2iclx_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
- iis2iclx_hp_slope_xl_en_t *val)
+ iis2iclx_hp_slope_xl_en_t *val)
{
iis2iclx_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- switch (( (ctrl8_xl.hp_ref_mode_xl << 5) +(ctrl8_xl.hp_slope_xl_en << 4) +
- ctrl8_xl.hpcf_xl )){
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ switch (((ctrl8_xl.hp_ref_mode_xl << 5) + (ctrl8_xl.hp_slope_xl_en <<
+ 4) +
+ ctrl8_xl.hpcf_xl))
+ {
case IIS2ICLX_HP_PATH_DISABLE_ON_OUT:
*val = IIS2ICLX_HP_PATH_DISABLE_ON_OUT;
break;
+
case IIS2ICLX_SLOPE_ODR_DIV_4:
*val = IIS2ICLX_SLOPE_ODR_DIV_4;
break;
+
case IIS2ICLX_HP_ODR_DIV_10:
*val = IIS2ICLX_HP_ODR_DIV_10;
break;
+
case IIS2ICLX_HP_ODR_DIV_20:
*val = IIS2ICLX_HP_ODR_DIV_20;
break;
+
case IIS2ICLX_HP_ODR_DIV_45:
*val = IIS2ICLX_HP_ODR_DIV_45;
break;
+
case IIS2ICLX_HP_ODR_DIV_100:
*val = IIS2ICLX_HP_ODR_DIV_100;
break;
+
case IIS2ICLX_HP_ODR_DIV_200:
*val = IIS2ICLX_HP_ODR_DIV_200;
break;
+
case IIS2ICLX_HP_ODR_DIV_400:
*val = IIS2ICLX_HP_ODR_DIV_400;
break;
+
case IIS2ICLX_HP_ODR_DIV_800:
*val = IIS2ICLX_HP_ODR_DIV_800;
break;
+
case IIS2ICLX_HP_REF_MD_ODR_DIV_10:
*val = IIS2ICLX_HP_REF_MD_ODR_DIV_10;
break;
+
case IIS2ICLX_HP_REF_MD_ODR_DIV_20:
*val = IIS2ICLX_HP_REF_MD_ODR_DIV_20;
break;
+
case IIS2ICLX_HP_REF_MD_ODR_DIV_45:
*val = IIS2ICLX_HP_REF_MD_ODR_DIV_45;
break;
+
case IIS2ICLX_HP_REF_MD_ODR_DIV_100:
*val = IIS2ICLX_HP_REF_MD_ODR_DIV_100;
break;
+
case IIS2ICLX_HP_REF_MD_ODR_DIV_200:
*val = IIS2ICLX_HP_REF_MD_ODR_DIV_200;
break;
+
case IIS2ICLX_HP_REF_MD_ODR_DIV_400:
*val = IIS2ICLX_HP_REF_MD_ODR_DIV_400;
break;
+
case IIS2ICLX_HP_REF_MD_ODR_DIV_800:
*val = IIS2ICLX_HP_REF_MD_ODR_DIV_800;
break;
+
case IIS2ICLX_LP_ODR_DIV_10:
*val = IIS2ICLX_LP_ODR_DIV_10;
break;
+
case IIS2ICLX_LP_ODR_DIV_20:
*val = IIS2ICLX_LP_ODR_DIV_20;
break;
+
case IIS2ICLX_LP_ODR_DIV_45:
*val = IIS2ICLX_LP_ODR_DIV_45;
break;
+
case IIS2ICLX_LP_ODR_DIV_100:
*val = IIS2ICLX_LP_ODR_DIV_100;
break;
+
case IIS2ICLX_LP_ODR_DIV_200:
*val = IIS2ICLX_LP_ODR_DIV_200;
break;
+
case IIS2ICLX_LP_ODR_DIV_400:
*val = IIS2ICLX_LP_ODR_DIV_400;
break;
+
case IIS2ICLX_LP_ODR_DIV_800:
*val = IIS2ICLX_LP_ODR_DIV_800;
break;
+
default:
*val = IIS2ICLX_HP_PATH_DISABLE_ON_OUT;
break;
}
+
return ret;
}
@@ -1711,12 +2058,15 @@ int32_t iis2iclx_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val)
iis2iclx_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
- ctrl8_xl.fastsettl_mode_xl= (uint8_t)val;
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl8_xl.fastsettl_mode_xl = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL8_XL,
- (uint8_t*)&ctrl8_xl, 1);
+ (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -1735,7 +2085,7 @@ int32_t iis2iclx_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2iclx_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
*val = ctrl8_xl.fastsettl_mode_xl;
return ret;
@@ -1751,17 +2101,20 @@ int32_t iis2iclx_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t iis2iclx_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
- iis2iclx_slope_fds_t val)
+ iis2iclx_slope_fds_t val)
{
iis2iclx_tap_cfg0_t tap_cfg0;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
- if(ret == 0){
- tap_cfg0.slope_fds= (uint8_t)val;
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
+
+ if (ret == 0)
+ {
+ tap_cfg0.slope_fds = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_TAP_CFG0,
- (uint8_t*)&tap_cfg0, 1);
+ (uint8_t *)&tap_cfg0, 1);
}
+
return ret;
}
@@ -1775,23 +2128,28 @@ int32_t iis2iclx_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
- iis2iclx_slope_fds_t *val)
+ iis2iclx_slope_fds_t *val)
{
iis2iclx_tap_cfg0_t tap_cfg0;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
- switch (tap_cfg0.slope_fds){
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
+
+ switch (tap_cfg0.slope_fds)
+ {
case IIS2ICLX_USE_SLOPE:
*val = IIS2ICLX_USE_SLOPE;
break;
+
case IIS2ICLX_USE_HPF:
*val = IIS2ICLX_USE_HPF;
break;
+
default:
*val = IIS2ICLX_USE_SLOPE;
break;
}
+
return ret;
}
@@ -1817,16 +2175,19 @@ int32_t iis2iclx_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
- iis2iclx_sdo_pu_en_t val)
+ iis2iclx_sdo_pu_en_t val)
{
iis2iclx_pin_ctrl_t pin_ctrl;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
- if(ret == 0){
- pin_ctrl.sdo_pu_en= (uint8_t)val;
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
+
+ if (ret == 0)
+ {
+ pin_ctrl.sdo_pu_en = (uint8_t)val;
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
}
+
return ret;
}
@@ -1839,24 +2200,28 @@ int32_t iis2iclx_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
- iis2iclx_sdo_pu_en_t *val)
+ iis2iclx_sdo_pu_en_t *val)
{
iis2iclx_pin_ctrl_t pin_ctrl;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
- switch (pin_ctrl.sdo_pu_en){
+ switch (pin_ctrl.sdo_pu_en)
+ {
case IIS2ICLX_PULL_UP_DISC:
*val = IIS2ICLX_PULL_UP_DISC;
break;
+
case IIS2ICLX_PULL_UP_CONNECT:
*val = IIS2ICLX_PULL_UP_CONNECT;
break;
+
default:
*val = IIS2ICLX_PULL_UP_DISC;
break;
}
+
return ret;
}
@@ -1873,11 +2238,14 @@ int32_t iis2iclx_spi_mode_set(stmdev_ctx_t *ctx, iis2iclx_sim_t val)
iis2iclx_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.sim= (uint8_t)val;
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.sim = (uint8_t)val;
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1894,19 +2262,23 @@ int32_t iis2iclx_spi_mode_get(stmdev_ctx_t *ctx, iis2iclx_sim_t *val)
iis2iclx_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
- switch (ctrl3_c.sim){
+ switch (ctrl3_c.sim)
+ {
case IIS2ICLX_SPI_4_WIRE:
*val = IIS2ICLX_SPI_4_WIRE;
break;
+
case IIS2ICLX_SPI_3_WIRE:
*val = IIS2ICLX_SPI_3_WIRE;
break;
+
default:
*val = IIS2ICLX_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -1919,16 +2291,19 @@ int32_t iis2iclx_spi_mode_get(stmdev_ctx_t *ctx, iis2iclx_sim_t *val)
*
*/
int32_t iis2iclx_i2c_interface_set(stmdev_ctx_t *ctx,
- iis2iclx_i2c_disable_t val)
+ iis2iclx_i2c_disable_t val)
{
iis2iclx_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ctrl4_c.i2c_disable= (uint8_t)val;
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl4_c.i2c_disable = (uint8_t)val;
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -1941,24 +2316,28 @@ int32_t iis2iclx_i2c_interface_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_i2c_interface_get(stmdev_ctx_t *ctx,
- iis2iclx_i2c_disable_t *val)
+ iis2iclx_i2c_disable_t *val)
{
iis2iclx_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
- switch (ctrl4_c.i2c_disable){
+ switch (ctrl4_c.i2c_disable)
+ {
case IIS2ICLX_I2C_ENABLE:
*val = IIS2ICLX_I2C_ENABLE;
break;
+
case IIS2ICLX_I2C_DISABLE:
*val = IIS2ICLX_I2C_DISABLE;
break;
+
default:
*val = IIS2ICLX_I2C_ENABLE;
break;
}
+
return ret;
}
@@ -1970,7 +2349,7 @@ int32_t iis2iclx_i2c_interface_get(stmdev_ctx_t *ctx,
/**
* @defgroup IIS2ICLX_interrupt_pins
* @brief This section groups all the functions that manage
- * interrup pins
+ * interrupt pins
* @{
*
*/
@@ -1985,35 +2364,46 @@ int32_t iis2iclx_i2c_interface_get(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_pin_int1_route_set(stmdev_ctx_t *ctx,
- iis2iclx_pin_int1_route_t *val)
+ iis2iclx_pin_int1_route_t *val)
{
iis2iclx_pin_int2_route_t pin_int2_route;
iis2iclx_tap_cfg2_t tap_cfg2;
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = iis2iclx_write_reg(ctx, IIS2ICLX_MLC_INT1,
- (uint8_t*)&val->mlc_int1, 1);
+ (uint8_t *)&val->mlc_int1, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = iis2iclx_write_reg(ctx, IIS2ICLX_EMB_FUNC_INT1,
- (uint8_t*)&val->emb_func_int1, 1);
+ (uint8_t *)&val->emb_func_int1, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = iis2iclx_write_reg(ctx, IIS2ICLX_FSM_INT1_A,
- (uint8_t*)&val->fsm_int1_a, 1);
+ (uint8_t *)&val->fsm_int1_a, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = iis2iclx_write_reg(ctx, IIS2ICLX_FSM_INT1_B,
- (uint8_t*)&val->fsm_int1_b, 1);
+ (uint8_t *)&val->fsm_int1_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
- if (ret == 0) {
- if ( ( val->emb_func_int1.int1_fsm_lc
+ if (ret == 0)
+ {
+ if ((val->emb_func_int1.int1_fsm_lc
| val->fsm_int1_a.int1_fsm1
| val->fsm_int1_a.int1_fsm2
| val->fsm_int1_a.int1_fsm3
@@ -2037,27 +2427,39 @@ int32_t iis2iclx_pin_int1_route_set(stmdev_ctx_t *ctx,
| val->mlc_int1.int1_mlc5
| val->mlc_int1.int1_mlc6
| val->mlc_int1.int1_mlc7
- | val->mlc_int1.int1_mlc8) != PROPERTY_DISABLE){
+ | val->mlc_int1.int1_mlc8) != PROPERTY_DISABLE)
+ {
val->md1_cfg.int1_emb_func = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
val->md1_cfg.int1_emb_func = PROPERTY_DISABLE;
}
+
ret = iis2iclx_write_reg(ctx, IIS2ICLX_INT1_CTRL,
- (uint8_t*)&val->int1_ctrl, 1);
+ (uint8_t *)&val->int1_ctrl, 1);
}
- if (ret == 0) {
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_MD1_CFG, (uint8_t*)&val->md1_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_MD1_CFG,
+ (uint8_t *)&val->md1_cfg, 1);
}
- if (ret == 0) {
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = iis2iclx_pin_int2_route_get(ctx, &pin_int2_route);
}
- if (ret == 0) {
- if ( ( pin_int2_route.int2_ctrl.int2_cnt_bdr
+
+ if (ret == 0)
+ {
+ if ((pin_int2_route.int2_ctrl.int2_cnt_bdr
| pin_int2_route.int2_ctrl.int2_drdy_temp
| pin_int2_route.int2_ctrl.int2_drdy_xl
| pin_int2_route.int2_ctrl.int2_fifo_full
@@ -2078,14 +2480,20 @@ int32_t iis2iclx_pin_int1_route_set(stmdev_ctx_t *ctx,
| val->md1_cfg.int1_double_tap
| val->md1_cfg.int1_wu
| val->md1_cfg.int1_single_tap
- | val->md1_cfg.int1_sleep_change) != PROPERTY_DISABLE) {
+ | val->md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
+ {
tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
}
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
+
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_TAP_CFG2,
+ (uint8_t *) &tap_cfg2, 1);
}
+
return ret;
}
@@ -2099,37 +2507,51 @@ int32_t iis2iclx_pin_int1_route_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_pin_int1_route_get(stmdev_ctx_t *ctx,
- iis2iclx_pin_int1_route_t *val)
+ iis2iclx_pin_int1_route_t *val)
{
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_MLC_INT1,
- (uint8_t*)&val->mlc_int1, 1);
+ (uint8_t *)&val->mlc_int1, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_INT1,
- (uint8_t*)&val->emb_func_int1, 1);
+ (uint8_t *)&val->emb_func_int1, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FSM_INT1_A,
- (uint8_t*)&val->fsm_int1_a, 1);
+ (uint8_t *)&val->fsm_int1_a, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FSM_INT1_B,
- (uint8_t*)&val->fsm_int1_b, 1);
+ (uint8_t *)&val->fsm_int1_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_INT1_CTRL,
- (uint8_t*)&val->int1_ctrl, 1);
+ (uint8_t *)&val->int1_ctrl, 1);
}
- if (ret == 0) {
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_MD1_CFG, (uint8_t*)&val->md1_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_MD1_CFG,
+ (uint8_t *)&val->md1_cfg, 1);
}
return ret;
@@ -2145,80 +2567,102 @@ int32_t iis2iclx_pin_int1_route_get(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_pin_int2_route_set(stmdev_ctx_t *ctx,
- iis2iclx_pin_int2_route_t *val)
+ iis2iclx_pin_int2_route_t *val)
{
iis2iclx_pin_int1_route_t pin_int1_route;
iis2iclx_tap_cfg2_t tap_cfg2;
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = iis2iclx_write_reg(ctx, IIS2ICLX_MLC_INT2,
- (uint8_t*)&val->mlc_int2, 1);
+ (uint8_t *)&val->mlc_int2, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = iis2iclx_write_reg(ctx, IIS2ICLX_EMB_FUNC_INT2,
- (uint8_t*)&val->emb_func_int2, 1);
+ (uint8_t *)&val->emb_func_int2, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = iis2iclx_write_reg(ctx, IIS2ICLX_FSM_INT2_A,
- (uint8_t*)&val->fsm_int2_a, 1);
+ (uint8_t *)&val->fsm_int2_a, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = iis2iclx_write_reg(ctx, IIS2ICLX_FSM_INT2_B,
- (uint8_t*)&val->fsm_int2_b, 1);
+ (uint8_t *)&val->fsm_int2_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
- if (ret == 0) {
- if (( val->emb_func_int2.int2_fsm_lc
- | val->fsm_int2_a.int2_fsm1
- | val->fsm_int2_a.int2_fsm2
- | val->fsm_int2_a.int2_fsm3
- | val->fsm_int2_a.int2_fsm4
- | val->fsm_int2_a.int2_fsm5
- | val->fsm_int2_a.int2_fsm6
- | val->fsm_int2_a.int2_fsm7
- | val->fsm_int2_a.int2_fsm8
- | val->fsm_int2_b.int2_fsm9
- | val->fsm_int2_b.int2_fsm10
- | val->fsm_int2_b.int2_fsm11
- | val->fsm_int2_b.int2_fsm12
- | val->fsm_int2_b.int2_fsm13
- | val->fsm_int2_b.int2_fsm14
- | val->fsm_int2_b.int2_fsm15
- | val->fsm_int2_b.int2_fsm16
- | val->mlc_int2.int2_mlc1
- | val->mlc_int2.int2_mlc2
- | val->mlc_int2.int2_mlc3
- | val->mlc_int2.int2_mlc4
- | val->mlc_int2.int2_mlc5
- | val->mlc_int2.int2_mlc6
- | val->mlc_int2.int2_mlc7
- | val->mlc_int2.int2_mlc8)!= PROPERTY_DISABLE ){
+ if (ret == 0)
+ {
+ if ((val->emb_func_int2.int2_fsm_lc
+ | val->fsm_int2_a.int2_fsm1
+ | val->fsm_int2_a.int2_fsm2
+ | val->fsm_int2_a.int2_fsm3
+ | val->fsm_int2_a.int2_fsm4
+ | val->fsm_int2_a.int2_fsm5
+ | val->fsm_int2_a.int2_fsm6
+ | val->fsm_int2_a.int2_fsm7
+ | val->fsm_int2_a.int2_fsm8
+ | val->fsm_int2_b.int2_fsm9
+ | val->fsm_int2_b.int2_fsm10
+ | val->fsm_int2_b.int2_fsm11
+ | val->fsm_int2_b.int2_fsm12
+ | val->fsm_int2_b.int2_fsm13
+ | val->fsm_int2_b.int2_fsm14
+ | val->fsm_int2_b.int2_fsm15
+ | val->fsm_int2_b.int2_fsm16
+ | val->mlc_int2.int2_mlc1
+ | val->mlc_int2.int2_mlc2
+ | val->mlc_int2.int2_mlc3
+ | val->mlc_int2.int2_mlc4
+ | val->mlc_int2.int2_mlc5
+ | val->mlc_int2.int2_mlc6
+ | val->mlc_int2.int2_mlc7
+ | val->mlc_int2.int2_mlc8) != PROPERTY_DISABLE)
+ {
val->md2_cfg.int2_emb_func = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
val->md2_cfg.int2_emb_func = PROPERTY_DISABLE;
}
+
ret = iis2iclx_write_reg(ctx, IIS2ICLX_INT2_CTRL,
- (uint8_t*)&val->int2_ctrl, 1);
+ (uint8_t *)&val->int2_ctrl, 1);
}
- if (ret == 0) {
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_MD2_CFG, (uint8_t*)&val->md2_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_MD2_CFG,
+ (uint8_t *)&val->md2_cfg, 1);
}
- if (ret == 0) {
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = iis2iclx_pin_int1_route_get(ctx, &pin_int1_route);
}
- if (ret == 0) {
- if ( ( val->int2_ctrl.int2_cnt_bdr
+ if (ret == 0)
+ {
+ if ((val->int2_ctrl.int2_cnt_bdr
| val->int2_ctrl.int2_drdy_temp
| val->int2_ctrl.int2_drdy_xl
| val->int2_ctrl.int2_fifo_full
@@ -2238,14 +2682,20 @@ int32_t iis2iclx_pin_int2_route_set(stmdev_ctx_t *ctx,
| pin_int1_route.md1_cfg.int1_double_tap
| pin_int1_route.md1_cfg.int1_wu
| pin_int1_route.md1_cfg.int1_single_tap
- | pin_int1_route.md1_cfg.int1_sleep_change ) != PROPERTY_DISABLE) {
+ | pin_int1_route.md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
+ {
tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
}
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
+
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_TAP_CFG2,
+ (uint8_t *) &tap_cfg2, 1);
}
+
return ret;
}
@@ -2259,38 +2709,53 @@ int32_t iis2iclx_pin_int2_route_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_pin_int2_route_get(stmdev_ctx_t *ctx,
- iis2iclx_pin_int2_route_t *val)
+ iis2iclx_pin_int2_route_t *val)
{
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_MLC_INT2,
- (uint8_t*)&val->mlc_int2, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_MLC_INT2,
+ (uint8_t *)&val->mlc_int2, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_INT2,
- (uint8_t*)&val->emb_func_int2, 1);
+ (uint8_t *)&val->emb_func_int2, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FSM_INT2_A,
- (uint8_t*)&val->fsm_int2_a, 1);
+ (uint8_t *)&val->fsm_int2_a, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FSM_INT2_B,
- (uint8_t*)&val->fsm_int2_b, 1);
+ (uint8_t *)&val->fsm_int2_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_INT2_CTRL,
- (uint8_t*)&val->int2_ctrl, 1);
+ (uint8_t *)&val->int2_ctrl, 1);
}
- if (ret == 0) {
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_MD2_CFG, (uint8_t*)&val->md2_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_MD2_CFG,
+ (uint8_t *)&val->md2_cfg, 1);
}
+
return ret;
}
@@ -2307,11 +2772,14 @@ int32_t iis2iclx_pin_mode_set(stmdev_ctx_t *ctx, iis2iclx_pp_od_t val)
iis2iclx_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.pp_od= (uint8_t)val;
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.pp_od = (uint8_t)val;
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -2323,24 +2791,29 @@ int32_t iis2iclx_pin_mode_set(stmdev_ctx_t *ctx, iis2iclx_pp_od_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis2iclx_pin_mode_get(stmdev_ctx_t *ctx, iis2iclx_pp_od_t *val)
+int32_t iis2iclx_pin_mode_get(stmdev_ctx_t *ctx,
+ iis2iclx_pp_od_t *val)
{
iis2iclx_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
- switch (ctrl3_c.pp_od){
+ switch (ctrl3_c.pp_od)
+ {
case IIS2ICLX_PUSH_PULL:
*val = IIS2ICLX_PUSH_PULL;
break;
+
case IIS2ICLX_OPEN_DRAIN:
*val = IIS2ICLX_OPEN_DRAIN;
break;
+
default:
*val = IIS2ICLX_PUSH_PULL;
break;
}
+
return ret;
}
@@ -2353,16 +2826,19 @@ int32_t iis2iclx_pin_mode_get(stmdev_ctx_t *ctx, iis2iclx_pp_od_t *val)
*
*/
int32_t iis2iclx_pin_polarity_set(stmdev_ctx_t *ctx,
- iis2iclx_h_lactive_t val)
+ iis2iclx_h_lactive_t val)
{
iis2iclx_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.h_lactive= (uint8_t)val;
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.h_lactive = (uint8_t)val;
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -2375,24 +2851,28 @@ int32_t iis2iclx_pin_polarity_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_pin_polarity_get(stmdev_ctx_t *ctx,
- iis2iclx_h_lactive_t *val)
+ iis2iclx_h_lactive_t *val)
{
iis2iclx_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
- switch (ctrl3_c.h_lactive){
+ switch (ctrl3_c.h_lactive)
+ {
case IIS2ICLX_ACTIVE_HIGH:
*val = IIS2ICLX_ACTIVE_HIGH;
break;
+
case IIS2ICLX_ACTIVE_LOW:
*val = IIS2ICLX_ACTIVE_LOW;
break;
+
default:
*val = IIS2ICLX_ACTIVE_HIGH;
break;
}
+
return ret;
}
@@ -2409,11 +2889,14 @@ int32_t iis2iclx_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
iis2iclx_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ctrl4_c.int2_on_int1= (uint8_t)val;
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl4_c.int2_on_int1 = (uint8_t)val;
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -2430,7 +2913,7 @@ int32_t iis2iclx_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2iclx_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.int2_on_int1;
return ret;
@@ -2445,32 +2928,43 @@ int32_t iis2iclx_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t iis2iclx_int_notification_set(stmdev_ctx_t *ctx,
- iis2iclx_lir_t val)
+ iis2iclx_lir_t val)
{
iis2iclx_tap_cfg0_t tap_cfg0;
iis2iclx_page_rw_t page_rw;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
- if(ret == 0){
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
+
+ if (ret == 0)
+ {
tap_cfg0.lir = (uint8_t)val & 0x01U;
tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_TAP_CFG0,
- (uint8_t*)&tap_cfg0, 1);
+ (uint8_t *)&tap_cfg0, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
}
- if(ret == 0){
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t*)&page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t*)&page_rw, 1);
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -2483,41 +2977,53 @@ int32_t iis2iclx_int_notification_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_int_notification_get(stmdev_ctx_t *ctx,
- iis2iclx_lir_t *val)
+ iis2iclx_lir_t *val)
{
iis2iclx_tap_cfg0_t tap_cfg0;
iis2iclx_page_rw_t page_rw;
int32_t ret;
*val = IIS2ICLX_ALL_INT_PULSED;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
}
- if(ret == 0){
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t*)&page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
- switch ((page_rw.emb_func_lir << 1) + tap_cfg0.lir){
+
+ switch ((page_rw.emb_func_lir << 1) + tap_cfg0.lir)
+ {
case IIS2ICLX_ALL_INT_PULSED:
*val = IIS2ICLX_ALL_INT_PULSED;
break;
+
case IIS2ICLX_BASE_LATCHED_EMB_PULSED:
*val = IIS2ICLX_BASE_LATCHED_EMB_PULSED;
break;
+
case IIS2ICLX_BASE_PULSED_EMB_LATCHED:
*val = IIS2ICLX_BASE_PULSED_EMB_LATCHED;
break;
+
case IIS2ICLX_ALL_INT_LATCHED:
*val = IIS2ICLX_ALL_INT_LATCHED;
break;
+
default:
*val = IIS2ICLX_ALL_INT_PULSED;
break;
}
+
return ret;
}
@@ -2545,18 +3051,21 @@ int32_t iis2iclx_int_notification_get(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_wkup_ths_weight_set(stmdev_ctx_t *ctx,
- iis2iclx_wake_ths_w_t val)
+ iis2iclx_wake_ths_w_t val)
{
iis2iclx_wake_up_dur_t wake_up_dur;
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
- wake_up_dur.wake_ths_w= (uint8_t)val;
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ wake_up_dur.wake_ths_w = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -2571,25 +3080,29 @@ int32_t iis2iclx_wkup_ths_weight_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_wkup_ths_weight_get(stmdev_ctx_t *ctx,
- iis2iclx_wake_ths_w_t *val)
+ iis2iclx_wake_ths_w_t *val)
{
iis2iclx_wake_up_dur_t wake_up_dur;
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
- switch (wake_up_dur.wake_ths_w){
+ switch (wake_up_dur.wake_ths_w)
+ {
case IIS2ICLX_LSb_FS_DIV_64:
*val = IIS2ICLX_LSb_FS_DIV_64;
break;
+
case IIS2ICLX_LSb_FS_DIV_256:
*val = IIS2ICLX_LSb_FS_DIV_256;
break;
+
default:
*val = IIS2ICLX_LSb_FS_DIV_64;
break;
}
+
return ret;
}
@@ -2608,12 +3121,15 @@ int32_t iis2iclx_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
- if(ret == 0){
- wake_up_ths.wk_ths= (uint8_t)val;
+ (uint8_t *)&wake_up_ths, 1);
+
+ if (ret == 0)
+ {
+ wake_up_ths.wk_ths = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
}
+
return ret;
}
@@ -2632,7 +3148,7 @@ int32_t iis2iclx_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
*val = wake_up_ths.wk_ths;
return ret;
@@ -2646,18 +3162,22 @@ int32_t iis2iclx_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis2iclx_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t iis2iclx_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
iis2iclx_wake_up_ths_t wake_up_ths;
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
- if(ret == 0){
- wake_up_ths.usr_off_on_wu= (uint8_t)val;
+ (uint8_t *)&wake_up_ths, 1);
+
+ if (ret == 0)
+ {
+ wake_up_ths.usr_off_on_wu = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
}
+
return ret;
}
@@ -2670,13 +3190,13 @@ int32_t iis2iclx_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, uint8_t val)
*
*/
int32_t iis2iclx_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
iis2iclx_wake_up_ths_t wake_up_ths;
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
*val = wake_up_ths.usr_off_on_wu;
return ret;
@@ -2696,12 +3216,15 @@ int32_t iis2iclx_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
- wake_up_dur.wake_dur= (uint8_t)val;
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ wake_up_dur.wake_dur = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -2719,7 +3242,7 @@ int32_t iis2iclx_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
*val = wake_up_dur.wake_dur;
return ret;
@@ -2749,17 +3272,20 @@ int32_t iis2iclx_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t iis2iclx_act_pin_notification_set(stmdev_ctx_t *ctx,
- iis2iclx_sleep_status_on_int_t val)
+ iis2iclx_sleep_status_on_int_t val)
{
iis2iclx_tap_cfg0_t tap_cfg0;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
- if(ret == 0){
- tap_cfg0. sleep_status_on_int= (uint8_t)val;
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
+
+ if (ret == 0)
+ {
+ tap_cfg0. sleep_status_on_int = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_TAP_CFG0,
- (uint8_t*)&tap_cfg0, 1);
+ (uint8_t *)&tap_cfg0, 1);
}
+
return ret;
}
@@ -2774,23 +3300,28 @@ int32_t iis2iclx_act_pin_notification_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_act_pin_notification_get(stmdev_ctx_t *ctx,
- iis2iclx_sleep_status_on_int_t *val)
+ iis2iclx_sleep_status_on_int_t *val)
{
iis2iclx_tap_cfg0_t tap_cfg0;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
- switch (tap_cfg0. sleep_status_on_int){
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
+
+ switch (tap_cfg0. sleep_status_on_int)
+ {
case IIS2ICLX_DRIVE_SLEEP_CHG_EVENT:
*val = IIS2ICLX_DRIVE_SLEEP_CHG_EVENT;
break;
+
case IIS2ICLX_DRIVE_SLEEP_STATUS:
*val = IIS2ICLX_DRIVE_SLEEP_STATUS;
break;
+
default:
*val = IIS2ICLX_DRIVE_SLEEP_CHG_EVENT;
break;
}
+
return ret;
}
@@ -2808,12 +3339,15 @@ int32_t iis2iclx_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
- wake_up_dur.sleep_dur= (uint8_t)val;
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ wake_up_dur.sleep_dur = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -2831,7 +3365,7 @@ int32_t iis2iclx_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
*val = wake_up_dur.sleep_dur;
return ret;
@@ -2858,17 +3392,21 @@ int32_t iis2iclx_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis2iclx_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t iis2iclx_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
iis2iclx_tap_cfg0_t tap_cfg0;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
- if(ret == 0){
- tap_cfg0.tap_y_en= (uint8_t)val;
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
+
+ if (ret == 0)
+ {
+ tap_cfg0.tap_y_en = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_TAP_CFG0,
- (uint8_t*)&tap_cfg0, 1);
+ (uint8_t *)&tap_cfg0, 1);
}
+
return ret;
}
@@ -2880,12 +3418,13 @@ int32_t iis2iclx_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis2iclx_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t iis2iclx_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
iis2iclx_tap_cfg0_t tap_cfg0;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
*val = tap_cfg0.tap_y_en;
return ret;
@@ -2899,17 +3438,21 @@ int32_t iis2iclx_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis2iclx_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t iis2iclx_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
iis2iclx_tap_cfg0_t tap_cfg0;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
- if(ret == 0){
- tap_cfg0.tap_x_en= (uint8_t)val;
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
+
+ if (ret == 0)
+ {
+ tap_cfg0.tap_x_en = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_TAP_CFG0,
- (uint8_t*)&tap_cfg0, 1);
+ (uint8_t *)&tap_cfg0, 1);
}
+
return ret;
}
@@ -2921,12 +3464,13 @@ int32_t iis2iclx_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis2iclx_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t iis2iclx_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
iis2iclx_tap_cfg0_t tap_cfg0;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
*val = tap_cfg0.tap_x_en;
return ret;
@@ -2945,12 +3489,15 @@ int32_t iis2iclx_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
iis2iclx_tap_cfg1_t tap_cfg1;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG1, (uint8_t*)&tap_cfg1, 1);
- if(ret == 0){
- tap_cfg1.tap_ths_x= (uint8_t)val;
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
+
+ if (ret == 0)
+ {
+ tap_cfg1.tap_ths_x = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_TAP_CFG1,
- (uint8_t*)&tap_cfg1, 1);
+ (uint8_t *)&tap_cfg1, 1);
}
+
return ret;
}
@@ -2967,7 +3514,7 @@ int32_t iis2iclx_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2iclx_tap_cfg1_t tap_cfg1;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG1, (uint8_t*)&tap_cfg1, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
*val = tap_cfg1.tap_ths_x;
return ret;
@@ -2982,16 +3529,19 @@ int32_t iis2iclx_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t iis2iclx_tap_axis_priority_set(stmdev_ctx_t *ctx,
- iis2iclx_tap_priority_t val)
+ iis2iclx_tap_priority_t val)
{
iis2iclx_tap_cfg1_t tap_cfg1;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG1, (uint8_t*)&tap_cfg1, 1);
- if(ret == 0){
- tap_cfg1.tap_priority= (uint8_t)val;
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_TAP_CFG1, (uint8_t*)&tap_cfg1, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
+
+ if (ret == 0)
+ {
+ tap_cfg1.tap_priority = (uint8_t)val;
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
}
+
return ret;
}
@@ -3004,24 +3554,28 @@ int32_t iis2iclx_tap_axis_priority_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_tap_axis_priority_get(stmdev_ctx_t *ctx,
- iis2iclx_tap_priority_t *val)
+ iis2iclx_tap_priority_t *val)
{
iis2iclx_tap_cfg1_t tap_cfg1;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG1, (uint8_t*)&tap_cfg1, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
- switch (tap_cfg1.tap_priority){
+ switch (tap_cfg1.tap_priority)
+ {
case IIS2ICLX_XY:
*val = IIS2ICLX_XY;
break;
+
case IIS2ICLX_YX:
*val = IIS2ICLX_YX;
break;
+
default:
*val = IIS2ICLX_XY;
break;
}
+
return ret;
}
@@ -3038,12 +3592,15 @@ int32_t iis2iclx_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val)
iis2iclx_tap_cfg2_t tap_cfg2;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG2, (uint8_t*)&tap_cfg2, 1);
- if(ret == 0){
- tap_cfg2.tap_ths_y= (uint8_t)val;
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
+
+ if (ret == 0)
+ {
+ tap_cfg2.tap_ths_y = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_TAP_CFG2,
- (uint8_t*)&tap_cfg2, 1);
+ (uint8_t *)&tap_cfg2, 1);
}
+
return ret;
}
@@ -3060,7 +3617,7 @@ int32_t iis2iclx_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2iclx_tap_cfg2_t tap_cfg2;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG2, (uint8_t*)&tap_cfg2, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
*val = tap_cfg2.tap_ths_y;
return ret;
@@ -3083,12 +3640,15 @@ int32_t iis2iclx_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
iis2iclx_int_dur2_t int_dur2;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_INT_DUR2, (uint8_t*)&int_dur2, 1);
- if(ret == 0){
- int_dur2.shock= (uint8_t)val;
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_INT_DUR2, (uint8_t *)&int_dur2, 1);
+
+ if (ret == 0)
+ {
+ int_dur2.shock = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_INT_DUR2,
- (uint8_t*)&int_dur2, 1);
+ (uint8_t *)&int_dur2, 1);
}
+
return ret;
}
@@ -3109,7 +3669,7 @@ int32_t iis2iclx_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2iclx_int_dur2_t int_dur2;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_INT_DUR2, (uint8_t *)&int_dur2, 1);
*val = int_dur2.shock;
return ret;
@@ -3132,12 +3692,15 @@ int32_t iis2iclx_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
iis2iclx_int_dur2_t int_dur2;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_INT_DUR2, (uint8_t*)&int_dur2, 1);
- if(ret == 0){
- int_dur2.quiet= (uint8_t)val;
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_INT_DUR2, (uint8_t *)&int_dur2, 1);
+
+ if (ret == 0)
+ {
+ int_dur2.quiet = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_INT_DUR2,
- (uint8_t*)&int_dur2, 1);
+ (uint8_t *)&int_dur2, 1);
}
+
return ret;
}
@@ -3158,7 +3721,7 @@ int32_t iis2iclx_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2iclx_int_dur2_t int_dur2;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_INT_DUR2, (uint8_t *)&int_dur2, 1);
*val = int_dur2.quiet;
return ret;
@@ -3183,12 +3746,15 @@ int32_t iis2iclx_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
iis2iclx_int_dur2_t int_dur2;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_INT_DUR2, (uint8_t*)&int_dur2, 1);
- if(ret == 0){
- int_dur2.dur= (uint8_t)val;
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_INT_DUR2, (uint8_t *)&int_dur2, 1);
+
+ if (ret == 0)
+ {
+ int_dur2.dur = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_INT_DUR2,
- (uint8_t*)&int_dur2, 1);
+ (uint8_t *)&int_dur2, 1);
}
+
return ret;
}
@@ -3209,7 +3775,7 @@ int32_t iis2iclx_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2iclx_int_dur2_t int_dur2;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_INT_DUR2, (uint8_t *)&int_dur2, 1);
*val = int_dur2.dur;
return ret;
@@ -3224,18 +3790,21 @@ int32_t iis2iclx_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t iis2iclx_tap_mode_set(stmdev_ctx_t *ctx,
- iis2iclx_single_double_tap_t val)
+ iis2iclx_single_double_tap_t val)
{
iis2iclx_wake_up_ths_t wake_up_ths;
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
- if(ret == 0){
- wake_up_ths.single_double_tap= (uint8_t)val;
+ (uint8_t *)&wake_up_ths, 1);
+
+ if (ret == 0)
+ {
+ wake_up_ths.single_double_tap = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
}
+
return ret;
}
@@ -3248,25 +3817,29 @@ int32_t iis2iclx_tap_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_tap_mode_get(stmdev_ctx_t *ctx,
- iis2iclx_single_double_tap_t *val)
+ iis2iclx_single_double_tap_t *val)
{
iis2iclx_wake_up_ths_t wake_up_ths;
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
- switch (wake_up_ths.single_double_tap){
+ switch (wake_up_ths.single_double_tap)
+ {
case IIS2ICLX_ONLY_SINGLE:
*val = IIS2ICLX_ONLY_SINGLE;
break;
+
case IIS2ICLX_BOTH_SINGLE_DOUBLE:
*val = IIS2ICLX_BOTH_SINGLE_DOUBLE;
break;
+
default:
*val = IIS2ICLX_ONLY_SINGLE;
break;
}
+
return ret;
}
@@ -3298,17 +3871,22 @@ int32_t iis2iclx_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl1.wtm = (uint8_t)(0x00FFU & val);
ret = iis2iclx_write_reg(ctx, IIS2ICLX_FIFO_CTRL1,
- (uint8_t*)&fifo_ctrl1, 1);
+ (uint8_t *)&fifo_ctrl1, 1);
}
- if(ret == 0){
- fifo_ctrl2.wtm = (uint8_t)(( 0x0100U & val ) >> 8);
+
+ if (ret == 0)
+ {
+ fifo_ctrl2.wtm = (uint8_t)((0x0100U & val) >> 8);
ret = iis2iclx_write_reg(ctx, IIS2ICLX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
+
return ret;
}
@@ -3327,14 +3905,18 @@ int32_t iis2iclx_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL1,
- (uint8_t*)&fifo_ctrl1, 1);
+ (uint8_t *)&fifo_ctrl1, 1);
}
+
*val = fifo_ctrl2.wtm;
*val = *val << 8;
*val += fifo_ctrl1.wtm;
+
return ret;
}
@@ -3347,17 +3929,19 @@ int32_t iis2iclx_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
*
*/
int32_t iis2iclx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
- uint8_t val)
+ uint8_t val)
{
iis2iclx_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
- fifo_ctrl2.odrchg_en= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl2.odrchg_en = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
return ret;
@@ -3372,13 +3956,13 @@ int32_t iis2iclx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
iis2iclx_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
*val = fifo_ctrl2.odrchg_en;
return ret;
@@ -3399,12 +3983,15 @@ int32_t iis2iclx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
- fifo_ctrl2.stop_on_wtm= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl2.stop_on_wtm = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
+
return ret;
}
@@ -3423,7 +4010,7 @@ int32_t iis2iclx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
*val = fifo_ctrl2.stop_on_wtm;
return ret;
@@ -3439,18 +4026,21 @@ int32_t iis2iclx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t iis2iclx_fifo_xl_batch_set(stmdev_ctx_t *ctx,
- iis2iclx_bdr_xl_t val)
+ iis2iclx_bdr_xl_t val)
{
iis2iclx_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
- if(ret == 0){
- fifo_ctrl3.bdr_xl= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl3, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl3.bdr_xl = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
+ (uint8_t *)&fifo_ctrl3, 1);
}
+
return ret;
}
@@ -3464,43 +4054,57 @@ int32_t iis2iclx_fifo_xl_batch_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_fifo_xl_batch_get(stmdev_ctx_t *ctx,
- iis2iclx_bdr_xl_t *val)
+ iis2iclx_bdr_xl_t *val)
{
iis2iclx_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
+ (uint8_t *)&fifo_ctrl3, 1);
- switch (fifo_ctrl3.bdr_xl){
+ switch (fifo_ctrl3.bdr_xl)
+ {
case IIS2ICLX_XL_NOT_BATCHED:
*val = IIS2ICLX_XL_NOT_BATCHED;
break;
+
+ case IIS2ICLX_XL_BATCHED_AT_1Hz6:
+ *val = IIS2ICLX_XL_BATCHED_AT_1Hz6;
+ break;
+
case IIS2ICLX_XL_BATCHED_AT_12Hz5:
*val = IIS2ICLX_XL_BATCHED_AT_12Hz5;
break;
+
case IIS2ICLX_XL_BATCHED_AT_26Hz:
*val = IIS2ICLX_XL_BATCHED_AT_26Hz;
break;
+
case IIS2ICLX_XL_BATCHED_AT_52Hz:
*val = IIS2ICLX_XL_BATCHED_AT_52Hz;
break;
+
case IIS2ICLX_XL_BATCHED_AT_104Hz:
*val = IIS2ICLX_XL_BATCHED_AT_104Hz;
break;
+
case IIS2ICLX_XL_BATCHED_AT_208Hz:
*val = IIS2ICLX_XL_BATCHED_AT_208Hz;
break;
+
case IIS2ICLX_XL_BATCHED_AT_417Hz:
*val = IIS2ICLX_XL_BATCHED_AT_417Hz;
break;
+
case IIS2ICLX_XL_BATCHED_AT_833Hz:
*val = IIS2ICLX_XL_BATCHED_AT_833Hz;
break;
+
default:
*val = IIS2ICLX_XL_NOT_BATCHED;
break;
}
+
return ret;
}
@@ -3513,18 +4117,21 @@ int32_t iis2iclx_fifo_xl_batch_get(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_fifo_mode_set(stmdev_ctx_t *ctx,
- iis2iclx_fifo_mode_t val)
+ iis2iclx_fifo_mode_t val)
{
iis2iclx_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
- fifo_ctrl4.fifo_mode= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl4.fifo_mode = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -3537,37 +4144,45 @@ int32_t iis2iclx_fifo_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_fifo_mode_get(stmdev_ctx_t *ctx,
- iis2iclx_fifo_mode_t *val)
+ iis2iclx_fifo_mode_t *val)
{
iis2iclx_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
- switch (fifo_ctrl4.fifo_mode){
+ switch (fifo_ctrl4.fifo_mode)
+ {
case IIS2ICLX_BYPASS_MODE:
*val = IIS2ICLX_BYPASS_MODE;
break;
+
case IIS2ICLX_FIFO_MODE:
*val = IIS2ICLX_FIFO_MODE;
break;
+
case IIS2ICLX_STREAM_TO_FIFO_MODE:
*val = IIS2ICLX_STREAM_TO_FIFO_MODE;
break;
+
case IIS2ICLX_BYPASS_TO_STREAM_MODE:
*val = IIS2ICLX_BYPASS_TO_STREAM_MODE;
break;
+
case IIS2ICLX_STREAM_MODE:
*val = IIS2ICLX_STREAM_MODE;
break;
+
case IIS2ICLX_BYPASS_TO_FIFO_MODE:
*val = IIS2ICLX_BYPASS_TO_FIFO_MODE;
break;
+
default:
*val = IIS2ICLX_BYPASS_MODE;
break;
}
+
return ret;
}
@@ -3581,18 +4196,21 @@ int32_t iis2iclx_fifo_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_fifo_temp_batch_set(stmdev_ctx_t *ctx,
- iis2iclx_odr_t_batch_t val)
+ iis2iclx_odr_t_batch_t val)
{
iis2iclx_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
- fifo_ctrl4.odr_t_batch= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl4.odr_t_batch = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -3606,28 +4224,37 @@ int32_t iis2iclx_fifo_temp_batch_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_fifo_temp_batch_get(stmdev_ctx_t *ctx,
- iis2iclx_odr_t_batch_t *val)
+ iis2iclx_odr_t_batch_t *val)
{
iis2iclx_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
- switch (fifo_ctrl4.odr_t_batch){
+ switch (fifo_ctrl4.odr_t_batch)
+ {
case IIS2ICLX_TEMP_NOT_BATCHED:
*val = IIS2ICLX_TEMP_NOT_BATCHED;
break;
+
+ case IIS2ICLX_TEMP_BATCHED_AT_1Hz6:
+ *val = IIS2ICLX_TEMP_BATCHED_AT_1Hz6;
+ break;
+
case IIS2ICLX_TEMP_BATCHED_AT_52Hz:
*val = IIS2ICLX_TEMP_BATCHED_AT_52Hz;
break;
+
case IIS2ICLX_TEMP_BATCHED_AT_12Hz5:
*val = IIS2ICLX_TEMP_BATCHED_AT_12Hz5;
break;
+
default:
*val = IIS2ICLX_TEMP_NOT_BATCHED;
break;
}
+
return ret;
}
@@ -3642,18 +4269,21 @@ int32_t iis2iclx_fifo_temp_batch_get(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
- iis2iclx_odr_ts_batch_t val)
+ iis2iclx_odr_ts_batch_t val)
{
iis2iclx_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
- fifo_ctrl4.odr_ts_batch= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl4.odr_ts_batch = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -3669,31 +4299,37 @@ int32_t iis2iclx_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
- iis2iclx_odr_ts_batch_t *val)
+ iis2iclx_odr_ts_batch_t *val)
{
iis2iclx_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
- switch (fifo_ctrl4.odr_ts_batch){
+ switch (fifo_ctrl4.odr_ts_batch)
+ {
case IIS2ICLX_NO_DECIMATION:
*val = IIS2ICLX_NO_DECIMATION;
break;
+
case IIS2ICLX_DEC_1:
*val = IIS2ICLX_DEC_1;
break;
+
case IIS2ICLX_DEC_8:
*val = IIS2ICLX_DEC_8;
break;
+
case IIS2ICLX_DEC_32:
*val = IIS2ICLX_DEC_32;
break;
+
default:
*val = IIS2ICLX_NO_DECIMATION;
break;
}
+
return ret;
}
@@ -3712,12 +4348,15 @@ int32_t iis2iclx_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if(ret == 0){
- counter_bdr_reg1.rst_counter_bdr= (uint8_t)val;
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
+ counter_bdr_reg1.rst_counter_bdr = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
}
+
return ret;
}
@@ -3730,13 +4369,14 @@ int32_t iis2iclx_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis2iclx_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t iis2iclx_rst_batch_counter_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
iis2iclx_counter_bdr_reg1_t counter_bdr_reg1;
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
*val = counter_bdr_reg1.rst_counter_bdr;
return ret;
@@ -3752,23 +4392,29 @@ int32_t iis2iclx_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t iis2iclx_batch_counter_threshold_set(stmdev_ctx_t *ctx,
- uint16_t val)
+ uint16_t val)
{
iis2iclx_counter_bdr_reg2_t counter_bdr_reg1;
iis2iclx_counter_bdr_reg2_t counter_bdr_reg2;
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if (ret == 0){
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
counter_bdr_reg1.cnt_bdr_th = (uint8_t)((0x0700U & val) >> 8);
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_COUNTER_BDR_REG1, (uint8_t*)&counter_bdr_reg1, 1);
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_COUNTER_BDR_REG1,
+ (uint8_t *)&counter_bdr_reg1, 1);
}
- if (ret == 0){
+
+ if (ret == 0)
+ {
counter_bdr_reg2.cnt_bdr_th = (uint8_t)(0x00FFU & val);
ret = iis2iclx_write_reg(ctx, IIS2ICLX_COUNTER_BDR_REG2,
- (uint8_t*)&counter_bdr_reg2, 1);
+ (uint8_t *)&counter_bdr_reg2, 1);
}
+
return ret;
}
@@ -3782,22 +4428,25 @@ int32_t iis2iclx_batch_counter_threshold_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_batch_counter_threshold_get(stmdev_ctx_t *ctx,
- uint16_t *val)
+ uint16_t *val)
{
iis2iclx_counter_bdr_reg1_t counter_bdr_reg1;
iis2iclx_counter_bdr_reg2_t counter_bdr_reg2;
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if (ret == 0){
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_COUNTER_BDR_REG2,
- (uint8_t*)&counter_bdr_reg2, 1);
+ (uint8_t *)&counter_bdr_reg2, 1);
}
*val = counter_bdr_reg1.cnt_bdr_th;
*val = *val << 8;
*val += counter_bdr_reg2.cnt_bdr_th;
+
return ret;
}
@@ -3816,14 +4465,17 @@ int32_t iis2iclx_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_STATUS1,
- (uint8_t*)&fifo_status1, 1);
- if (ret == 0){
+ (uint8_t *)&fifo_status1, 1);
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
+ (uint8_t *)&fifo_status2, 1);
*val = fifo_status2.diff_fifo;
*val = *val << 8;
*val += fifo_status1.diff_fifo;
}
+
return ret;
}
@@ -3836,10 +4488,12 @@ int32_t iis2iclx_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
*
*/
int32_t iis2iclx_fifo_status_get(stmdev_ctx_t *ctx,
- iis2iclx_fifo_status2_t *val)
+ iis2iclx_fifo_status2_t *val)
{
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_STATUS2, (uint8_t*)val, 1);
+
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_STATUS2, (uint8_t *)val, 1);
+
return ret;
}
@@ -3857,7 +4511,7 @@ int32_t iis2iclx_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
+ (uint8_t *)&fifo_status2, 1);
*val = fifo_status2.fifo_full_ia;
return ret;
@@ -3878,7 +4532,7 @@ int32_t iis2iclx_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
+ (uint8_t *)&fifo_status2, 1);
*val = fifo_status2. fifo_ovr_ia;
return ret;
@@ -3898,7 +4552,7 @@ int32_t iis2iclx_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
+ (uint8_t *)&fifo_status2, 1);
*val = fifo_status2.fifo_wtm_ia;
return ret;
@@ -3913,46 +4567,57 @@ int32_t iis2iclx_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t iis2iclx_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
- iis2iclx_fifo_tag_t *val)
+ iis2iclx_fifo_tag_t *val)
{
iis2iclx_fifo_data_out_tag_t fifo_data_out_tag;
int32_t ret;
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_DATA_OUT_TAG,
- (uint8_t*)&fifo_data_out_tag, 1);
+ (uint8_t *)&fifo_data_out_tag, 1);
- switch (fifo_data_out_tag.tag_sensor){
+ switch (fifo_data_out_tag.tag_sensor)
+ {
case IIS2ICLX_XL_NC_TAG:
*val = IIS2ICLX_XL_NC_TAG;
break;
+
case IIS2ICLX_TEMPERATURE_TAG:
*val = IIS2ICLX_TEMPERATURE_TAG;
break;
+
case IIS2ICLX_TIMESTAMP_TAG:
*val = IIS2ICLX_TIMESTAMP_TAG;
break;
+
case IIS2ICLX_CFG_CHANGE_TAG:
*val = IIS2ICLX_CFG_CHANGE_TAG;
break;
+
case IIS2ICLX_SENSORHUB_SLAVE0_TAG:
*val = IIS2ICLX_SENSORHUB_SLAVE0_TAG;
break;
+
case IIS2ICLX_SENSORHUB_SLAVE1_TAG:
*val = IIS2ICLX_SENSORHUB_SLAVE1_TAG;
break;
+
case IIS2ICLX_SENSORHUB_SLAVE2_TAG:
*val = IIS2ICLX_SENSORHUB_SLAVE2_TAG;
break;
+
case IIS2ICLX_SENSORHUB_SLAVE3_TAG:
*val = IIS2ICLX_SENSORHUB_SLAVE3_TAG;
break;
+
case IIS2ICLX_SENSORHUB_NACK_TAG:
*val = IIS2ICLX_SENSORHUB_NACK_TAG;
break;
+
default:
*val = IIS2ICLX_SENSORHUB_NACK_TAG;
break;
}
+
return ret;
}
@@ -3971,18 +4636,24 @@ int32_t iis2iclx_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val)
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
- slv0_config. batch_ext_sens_0_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ slv0_config. batch_ext_sens_0_en = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -4002,14 +4673,18 @@ int32_t iis2iclx_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val)
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = slv0_config. batch_ext_sens_0_en;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -4028,18 +4703,25 @@ int32_t iis2iclx_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_SLV1_CONFIG,
- (uint8_t*)&slv1_config, 1);
+ (uint8_t *)&slv1_config, 1);
}
- if(ret == 0){
- slv1_config. batch_ext_sens_1_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ slv1_config. batch_ext_sens_1_en = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV1_CONFIG,
- (uint8_t*)&slv1_config, 1);
+ (uint8_t *)&slv1_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -4059,14 +4741,18 @@ int32_t iis2iclx_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val)
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_SLV1_CONFIG,
- (uint8_t*)&slv1_config, 1);
+ (uint8_t *)&slv1_config, 1);
*val = slv1_config. batch_ext_sens_1_en;
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -4086,18 +4772,24 @@ int32_t iis2iclx_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val)
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_SLV2_CONFIG,
- (uint8_t*)&slv2_config, 1);
+ (uint8_t *)&slv2_config, 1);
}
- if(ret == 0){
- slv2_config. batch_ext_sens_2_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ slv2_config. batch_ext_sens_2_en = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV2_CONFIG,
- (uint8_t*)&slv2_config, 1);
+ (uint8_t *)&slv2_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -4116,14 +4808,19 @@ int32_t iis2iclx_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_SLV2_CONFIG,
- (uint8_t*)&slv2_config, 1);
+ (uint8_t *)&slv2_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = slv2_config. batch_ext_sens_2_en;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -4142,18 +4839,25 @@ int32_t iis2iclx_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_SLV3_CONFIG,
- (uint8_t*)&slv3_config, 1);
+ (uint8_t *)&slv3_config, 1);
}
- if(ret == 0){
- slv3_config. batch_ext_sens_3_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ slv3_config. batch_ext_sens_3_en = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV3_CONFIG,
- (uint8_t*)&slv3_config, 1);
+ (uint8_t *)&slv3_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -4173,14 +4877,18 @@ int32_t iis2iclx_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val)
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_SLV3_CONFIG,
- (uint8_t*)&slv3_config, 1);
+ (uint8_t *)&slv3_config, 1);
*val = slv3_config. batch_ext_sens_3_en;
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -4205,25 +4913,33 @@ int32_t iis2iclx_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis2iclx_den_mode_set(stmdev_ctx_t *ctx, iis2iclx_den_mode_t val)
+int32_t iis2iclx_den_mode_set(stmdev_ctx_t *ctx,
+ iis2iclx_den_mode_t val)
{
iis2iclx_ctrl6_c_t ctrl6_c;
iis2iclx_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
- ctrl9_xl.den_en= ( (uint8_t)val & 0x70U ) >> 4;
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl9_xl.den_en = ((uint8_t)val & 0x70U) >> 4;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
+ (uint8_t *)&ctrl9_xl, 1);
}
- if(ret == 0){
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
}
- if(ret == 0){
- ctrl6_c.den_mode= (uint8_t)val & 0x07U;
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl6_c.den_mode = (uint8_t)val & 0x07U;
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -4236,36 +4952,46 @@ int32_t iis2iclx_den_mode_set(stmdev_ctx_t *ctx, iis2iclx_den_mode_t val)
*
*/
int32_t iis2iclx_den_mode_get(stmdev_ctx_t *ctx,
- iis2iclx_den_mode_t *val)
+ iis2iclx_den_mode_t *val)
{
iis2iclx_ctrl6_c_t ctrl6_c;
iis2iclx_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
}
- switch ( (ctrl9_xl.den_en << 4) + ctrl6_c.den_mode){
+
+ switch ((ctrl9_xl.den_en << 4) + ctrl6_c.den_mode)
+ {
case IIS2ICLX_DEN_DISABLE:
*val = IIS2ICLX_DEN_DISABLE;
break;
+
case IIS2ICLX_LEVEL_FIFO:
*val = IIS2ICLX_LEVEL_FIFO;
break;
+
case IIS2ICLX_LEVEL_LETCHED:
*val = IIS2ICLX_LEVEL_LETCHED;
break;
+
case IIS2ICLX_LEVEL_TRIGGER:
*val = IIS2ICLX_LEVEL_TRIGGER;
break;
+
case IIS2ICLX_EDGE_TRIGGER:
*val = IIS2ICLX_EDGE_TRIGGER;
break;
+
default:
*val = IIS2ICLX_DEN_DISABLE;
break;
}
+
return ret;
}
@@ -4278,17 +5004,20 @@ int32_t iis2iclx_den_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_den_polarity_set(stmdev_ctx_t *ctx,
- iis2iclx_den_lh_t val)
+ iis2iclx_den_lh_t val)
{
iis2iclx_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
- ctrl9_xl.den_lh= (uint8_t)val;
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl9_xl.den_lh = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
+ (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -4301,24 +5030,28 @@ int32_t iis2iclx_den_polarity_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_den_polarity_get(stmdev_ctx_t *ctx,
- iis2iclx_den_lh_t *val)
+ iis2iclx_den_lh_t *val)
{
iis2iclx_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
- switch (ctrl9_xl.den_lh){
+ switch (ctrl9_xl.den_lh)
+ {
case IIS2ICLX_DEN_ACT_LOW:
*val = IIS2ICLX_DEN_ACT_LOW;
break;
+
case IIS2ICLX_DEN_ACT_HIGH:
*val = IIS2ICLX_DEN_ACT_HIGH;
break;
+
default:
*val = IIS2ICLX_DEN_ACT_LOW;
break;
}
+
return ret;
}
@@ -4335,12 +5068,15 @@ int32_t iis2iclx_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
iis2iclx_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
- ctrl9_xl.den_y= (uint8_t)val;
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl9_xl.den_y = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
+ (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -4357,7 +5093,7 @@ int32_t iis2iclx_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2iclx_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
*val = ctrl9_xl.den_y;
return ret;
@@ -4376,11 +5112,14 @@ int32_t iis2iclx_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
iis2iclx_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
- ctrl9_xl.den_x= (uint8_t)val;
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl9_xl.den_x = (uint8_t)val;
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -4397,7 +5136,7 @@ int32_t iis2iclx_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2iclx_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
*val = ctrl9_xl.den_x;
return ret;
@@ -4426,20 +5165,25 @@ int32_t iis2iclx_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t iis2iclx_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
iis2iclx_emb_func_status_t emb_func_status;
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_STATUS,
- (uint8_t*)&emb_func_status, 1);
+ (uint8_t *)&emb_func_status, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = emb_func_status.is_fsm_lc;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -4454,22 +5198,28 @@ int32_t iis2iclx_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
int32_t iis2iclx_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val)
{
int32_t ret;
- iis2iclx_emb_func_en_b_t emb_func_en_b;
+ iis2iclx_emb_func_en_b_t emb_func_en_b;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if(ret == 0){
- emb_func_en_b.fsm_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ emb_func_en_b.fsm_en = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -4484,21 +5234,28 @@ int32_t iis2iclx_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t iis2iclx_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val)
{
int32_t ret;
- iis2iclx_emb_func_en_b_t emb_func_en_b;
+ iis2iclx_emb_func_en_b_t emb_func_en_b;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = emb_func_en_b.fsm_en;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -4511,54 +5268,70 @@ int32_t iis2iclx_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t iis2iclx_fsm_enable_set(stmdev_ctx_t *ctx,
- iis2iclx_emb_fsm_enable_t *val)
+ iis2iclx_emb_fsm_enable_t *val)
{
iis2iclx_emb_func_en_b_t emb_func_en_b;
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_write_reg(ctx, IIS2ICLX_FSM_ENABLE_A,
- (uint8_t*)&val->fsm_enable_a, 1);
+ (uint8_t *)&val->fsm_enable_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_write_reg(ctx, IIS2ICLX_FSM_ENABLE_B,
- (uint8_t*)&val->fsm_enable_b, 1);
+ (uint8_t *)&val->fsm_enable_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
- }
- if(ret == 0){
- if ( (val->fsm_enable_a.fsm1_en |
- val->fsm_enable_a.fsm2_en |
- val->fsm_enable_a.fsm3_en |
- val->fsm_enable_a.fsm4_en |
- val->fsm_enable_a.fsm5_en |
- val->fsm_enable_a.fsm6_en |
- val->fsm_enable_a.fsm7_en |
- val->fsm_enable_a.fsm8_en |
- val->fsm_enable_b.fsm9_en |
- val->fsm_enable_b.fsm10_en |
- val->fsm_enable_b.fsm11_en |
- val->fsm_enable_b.fsm12_en |
- val->fsm_enable_b.fsm13_en |
- val->fsm_enable_b.fsm14_en |
- val->fsm_enable_b.fsm15_en |
- val->fsm_enable_b.fsm16_en ) != PROPERTY_DISABLE){
+ (uint8_t *)&emb_func_en_b, 1);
+ }
+
+ if (ret == 0)
+ {
+ if ((val->fsm_enable_a.fsm1_en |
+ val->fsm_enable_a.fsm2_en |
+ val->fsm_enable_a.fsm3_en |
+ val->fsm_enable_a.fsm4_en |
+ val->fsm_enable_a.fsm5_en |
+ val->fsm_enable_a.fsm6_en |
+ val->fsm_enable_a.fsm7_en |
+ val->fsm_enable_a.fsm8_en |
+ val->fsm_enable_b.fsm9_en |
+ val->fsm_enable_b.fsm10_en |
+ val->fsm_enable_b.fsm11_en |
+ val->fsm_enable_b.fsm12_en |
+ val->fsm_enable_b.fsm13_en |
+ val->fsm_enable_b.fsm14_en |
+ val->fsm_enable_b.fsm15_en |
+ val->fsm_enable_b.fsm16_en) != PROPERTY_DISABLE)
+ {
emb_func_en_b.fsm_en = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
emb_func_en_b.fsm_en = PROPERTY_DISABLE;
}
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_write_reg(ctx, IIS2ICLX_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -4571,22 +5344,29 @@ int32_t iis2iclx_fsm_enable_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_fsm_enable_get(stmdev_ctx_t *ctx,
- iis2iclx_emb_fsm_enable_t *val)
+ iis2iclx_emb_fsm_enable_t *val)
{
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FSM_ENABLE_A,
- (uint8_t*)&val->fsm_enable_a, 1);
+ (uint8_t *)&val->fsm_enable_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FSM_ENABLE_B,
- (uint8_t*)&val->fsm_enable_b, 1);
+ (uint8_t *)&val->fsm_enable_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -4605,14 +5385,19 @@ int32_t iis2iclx_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val)
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
- buff[1] = (uint8_t) (val / 256U);
- buff[0] = (uint8_t) (val - (buff[1] * 256U));
+
+ if (ret == 0)
+ {
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
ret = iis2iclx_write_reg(ctx, IIS2ICLX_FSM_LONG_COUNTER_L, buff, 2);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -4631,14 +5416,19 @@ int32_t iis2iclx_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val)
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FSM_LONG_COUNTER_L, buff, 2);
*val = buff[1];
*val = (*val * 256U) + buff[0];
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -4652,24 +5442,31 @@ int32_t iis2iclx_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val)
*
*/
int32_t iis2iclx_long_clr_set(stmdev_ctx_t *ctx,
- iis2iclx_fsm_lc_clr_t val)
+ iis2iclx_fsm_lc_clr_t val)
{
iis2iclx_fsm_long_counter_clear_t fsm_long_counter_clear;
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FSM_LONG_COUNTER_CLEAR,
- (uint8_t*)&fsm_long_counter_clear, 1);
+ (uint8_t *)&fsm_long_counter_clear, 1);
}
- if(ret == 0){
- fsm_long_counter_clear.fsm_lc_clr= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ fsm_long_counter_clear.fsm_lc_clr = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_FSM_LONG_COUNTER_CLEAR,
- (uint8_t*)&fsm_long_counter_clear, 1);
+ (uint8_t *)&fsm_long_counter_clear, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -4682,34 +5479,43 @@ int32_t iis2iclx_long_clr_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_long_clr_get(stmdev_ctx_t *ctx,
- iis2iclx_fsm_lc_clr_t *val)
+ iis2iclx_fsm_lc_clr_t *val)
{
iis2iclx_fsm_long_counter_clear_t fsm_long_counter_clear;
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FSM_LONG_COUNTER_CLEAR,
- (uint8_t*)&fsm_long_counter_clear, 1);
+ (uint8_t *)&fsm_long_counter_clear, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
- switch (fsm_long_counter_clear.fsm_lc_clr){
+
+ switch (fsm_long_counter_clear.fsm_lc_clr)
+ {
case IIS2ICLX_LC_NORMAL:
*val = IIS2ICLX_LC_NORMAL;
break;
+
case IIS2ICLX_LC_CLEAR:
*val = IIS2ICLX_LC_CLEAR;
break;
+
case IIS2ICLX_LC_CLEAR_DONE:
*val = IIS2ICLX_LC_CLEAR_DONE;
break;
+
default:
*val = IIS2ICLX_LC_NORMAL;
break;
}
+
return ret;
}
@@ -4721,19 +5527,24 @@ int32_t iis2iclx_long_clr_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis2iclx_fsm_out_get(stmdev_ctx_t *ctx, iis2iclx_fsm_out_t *val)
+int32_t iis2iclx_fsm_out_get(stmdev_ctx_t *ctx,
+ iis2iclx_fsm_out_t *val)
{
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_FSM_OUTS1,
- (uint8_t*)&val->fsm_outs1, 16);
+ (uint8_t *)&val->fsm_outs1, 16);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -4746,27 +5557,33 @@ int32_t iis2iclx_fsm_out_get(stmdev_ctx_t *ctx, iis2iclx_fsm_out_t *val)
*
*/
int32_t iis2iclx_fsm_data_rate_set(stmdev_ctx_t *ctx,
- iis2iclx_fsm_odr_t val)
+ iis2iclx_fsm_odr_t val)
{
iis2iclx_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_ODR_CFG_B,
- (uint8_t*)&emb_func_odr_cfg_b, 1);
+ (uint8_t *)&emb_func_odr_cfg_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
emb_func_odr_cfg_b.not_used_01 = 3; /* set default values */
emb_func_odr_cfg_b.not_used_02 = 1; /* set default values */
- emb_func_odr_cfg_b.fsm_odr= (uint8_t)val;
+ emb_func_odr_cfg_b.fsm_odr = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_EMB_FUNC_ODR_CFG_B,
- (uint8_t*)&emb_func_odr_cfg_b, 1);
- }
- if(ret == 0){
+ (uint8_t *)&emb_func_odr_cfg_b, 1);
+ }
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -4779,37 +5596,47 @@ int32_t iis2iclx_fsm_data_rate_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_fsm_data_rate_get(stmdev_ctx_t *ctx,
- iis2iclx_fsm_odr_t *val)
+ iis2iclx_fsm_odr_t *val)
{
iis2iclx_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_ODR_CFG_B,
- (uint8_t*)&emb_func_odr_cfg_b, 1);
+ (uint8_t *)&emb_func_odr_cfg_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
- switch (emb_func_odr_cfg_b.fsm_odr){
+
+ switch (emb_func_odr_cfg_b.fsm_odr)
+ {
case IIS2ICLX_ODR_FSM_12Hz5:
*val = IIS2ICLX_ODR_FSM_12Hz5;
break;
+
case IIS2ICLX_ODR_FSM_26Hz:
*val = IIS2ICLX_ODR_FSM_26Hz;
break;
+
case IIS2ICLX_ODR_FSM_52Hz:
*val = IIS2ICLX_ODR_FSM_52Hz;
break;
+
case IIS2ICLX_ODR_FSM_104Hz:
*val = IIS2ICLX_ODR_FSM_104Hz;
break;
+
default:
*val = IIS2ICLX_ODR_FSM_12Hz5;
break;
}
+
return ret;
}
@@ -4828,18 +5655,24 @@ int32_t iis2iclx_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val)
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_INIT_B,
- (uint8_t*)&emb_func_init_b, 1);
+ (uint8_t *)&emb_func_init_b, 1);
}
- if(ret == 0){
- emb_func_init_b.fsm_init= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ emb_func_init_b.fsm_init = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_EMB_FUNC_INIT_B,
- (uint8_t*)&emb_func_init_b, 1);
+ (uint8_t *)&emb_func_init_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -4857,14 +5690,19 @@ int32_t iis2iclx_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_INIT_B,
- (uint8_t*)&emb_func_init_b, 1);
+ (uint8_t *)&emb_func_init_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = emb_func_init_b.fsm_init;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -4879,19 +5717,23 @@ int32_t iis2iclx_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis2iclx_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint16_t val)
+int32_t iis2iclx_long_cnt_int_value_set(stmdev_ctx_t *ctx,
+ uint16_t val)
{
uint8_t buff[2];
int32_t ret;
- buff[1] = (uint8_t) (val / 256U);
- buff[0] = (uint8_t) (val - (buff[1] * 256U));
-
- ret = iis2iclx_ln_pg_write_byte(ctx, IIS2ICLX_FSM_LC_TIMEOUT_L, &buff[0]);
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
+ ret = iis2iclx_ln_pg_write_byte(ctx, IIS2ICLX_FSM_LC_TIMEOUT_L,
+ &buff[0]);
- if(ret == 0){
- ret = iis2iclx_ln_pg_write_byte(ctx, IIS2ICLX_FSM_LC_TIMEOUT_H, &buff[1]);
+ if (ret == 0)
+ {
+ ret = iis2iclx_ln_pg_write_byte(ctx, IIS2ICLX_FSM_LC_TIMEOUT_H,
+ &buff[1]);
}
+
return ret;
}
@@ -4906,15 +5748,19 @@ int32_t iis2iclx_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint16_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis2iclx_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint16_t *val)
+int32_t iis2iclx_long_cnt_int_value_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
uint8_t buff[2];
int32_t ret;
- ret = iis2iclx_ln_pg_read_byte(ctx, IIS2ICLX_FSM_LC_TIMEOUT_L, &buff[0]);
+ ret = iis2iclx_ln_pg_read_byte(ctx, IIS2ICLX_FSM_LC_TIMEOUT_L,
+ &buff[0]);
- if(ret == 0){
- ret = iis2iclx_ln_pg_read_byte(ctx, IIS2ICLX_FSM_LC_TIMEOUT_H, &buff[1]);
+ if (ret == 0)
+ {
+ ret = iis2iclx_ln_pg_read_byte(ctx, IIS2ICLX_FSM_LC_TIMEOUT_H,
+ &buff[1]);
*val = buff[1];
*val = (*val * 256U) + buff[0];
}
@@ -4930,15 +5776,19 @@ int32_t iis2iclx_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint16_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis2iclx_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t iis2iclx_fsm_number_of_programs_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
ret = iis2iclx_ln_pg_write_byte(ctx, IIS2ICLX_FSM_PROGRAMS, buff);
- if(ret == 0){
- ret = iis2iclx_ln_pg_write_byte(ctx, IIS2ICLX_FSM_PROGRAMS + 0x01U, buff);
+ if (ret == 0)
+ {
+ ret = iis2iclx_ln_pg_write_byte(ctx, IIS2ICLX_FSM_PROGRAMS + 0x01U,
+ buff);
}
+
return ret;
}
@@ -4950,7 +5800,8 @@ int32_t iis2iclx_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis2iclx_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t iis2iclx_fsm_number_of_programs_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
@@ -4968,19 +5819,23 @@ int32_t iis2iclx_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis2iclx_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val)
+int32_t iis2iclx_fsm_start_address_set(stmdev_ctx_t *ctx,
+ uint16_t val)
{
uint8_t buff[2];
int32_t ret;
- buff[1] = (uint8_t) (val / 256U);
- buff[0] = (uint8_t) (val - (buff[1] * 256U));
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
+ ret = iis2iclx_ln_pg_write_byte(ctx, IIS2ICLX_FSM_START_ADD_L,
+ &buff[0]);
- ret = iis2iclx_ln_pg_write_byte(ctx, IIS2ICLX_FSM_START_ADD_L, &buff[0]);
-
- if(ret == 0){
- ret = iis2iclx_ln_pg_write_byte(ctx, IIS2ICLX_FSM_START_ADD_H, &buff[1]);
+ if (ret == 0)
+ {
+ ret = iis2iclx_ln_pg_write_byte(ctx, IIS2ICLX_FSM_START_ADD_H,
+ &buff[1]);
}
+
return ret;
}
@@ -4993,18 +5848,23 @@ int32_t iis2iclx_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis2iclx_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val)
+int32_t iis2iclx_fsm_start_address_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
uint8_t buff[2];
int32_t ret;
- ret = iis2iclx_ln_pg_read_byte(ctx, IIS2ICLX_FSM_START_ADD_L, &buff[0]);
+ ret = iis2iclx_ln_pg_read_byte(ctx, IIS2ICLX_FSM_START_ADD_L,
+ &buff[0]);
- if(ret == 0){
- ret = iis2iclx_ln_pg_read_byte(ctx, IIS2ICLX_FSM_START_ADD_H, &buff[1]);
+ if (ret == 0)
+ {
+ ret = iis2iclx_ln_pg_read_byte(ctx, IIS2ICLX_FSM_START_ADD_H,
+ &buff[1]);
*val = buff[1];
*val = (*val * 256U) + buff[0];
}
+
return ret;
}
@@ -5036,25 +5896,36 @@ int32_t iis2iclx_mlc_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_EN_B, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_EN_B, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.mlc_en = val;
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_EMB_FUNC_EN_B, (uint8_t*)®, 1);
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_EMB_FUNC_EN_B, (uint8_t *)®, 1);
}
- if ((val != PROPERTY_DISABLE) && (ret == 0)){
+
+ if ((val != PROPERTY_DISABLE) && (ret == 0))
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_INIT_B,
- (uint8_t*)®, 1);
- if (ret == 0) {
+ (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.mlc_en = val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_EMB_FUNC_INIT_B,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -5072,13 +5943,18 @@ int32_t iis2iclx_mlc_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_EN_B, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_EN_B, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
*val = reg.mlc_en;
}
+
return ret;
}
@@ -5093,7 +5969,7 @@ int32_t iis2iclx_mlc_status_get(stmdev_ctx_t *ctx,
iis2iclx_mlc_status_mainpage_t *val)
{
return iis2iclx_read_reg(ctx, IIS2ICLX_MLC_STATUS_MAINPAGE,
- (uint8_t*) val, 1);
+ (uint8_t *) val, 1);
}
/**
@@ -5105,21 +5981,28 @@ int32_t iis2iclx_mlc_status_get(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_mlc_data_rate_set(stmdev_ctx_t *ctx,
- iis2iclx_mlc_odr_t val)
+ iis2iclx_mlc_odr_t val)
{
iis2iclx_emb_func_odr_cfg_c_t reg;
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_ODR_CFG_C,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.mlc_odr = (uint8_t)val;
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_EMB_FUNC_ODR_CFG_C, (uint8_t*)®, 1);
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_EMB_FUNC_ODR_CFG_C,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
@@ -5141,30 +6024,41 @@ int32_t iis2iclx_mlc_data_rate_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_ODR_CFG_C,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
- switch (reg.mlc_odr) {
+
+ if (ret == 0)
+ {
+ switch (reg.mlc_odr)
+ {
case IIS2ICLX_ODR_PRGS_12Hz5:
*val = IIS2ICLX_ODR_PRGS_12Hz5;
break;
+
case IIS2ICLX_ODR_PRGS_26Hz:
*val = IIS2ICLX_ODR_PRGS_26Hz;
break;
+
case IIS2ICLX_ODR_PRGS_52Hz:
*val = IIS2ICLX_ODR_PRGS_52Hz;
break;
+
case IIS2ICLX_ODR_PRGS_104Hz:
*val = IIS2ICLX_ODR_PRGS_104Hz;
break;
+
default:
*val = IIS2ICLX_ODR_PRGS_12Hz5;
break;
}
+
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -5178,13 +6072,19 @@ int32_t iis2iclx_mlc_data_rate_get(stmdev_ctx_t *ctx,
int32_t iis2iclx_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_MLC0_SRC, buff, 8);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -5210,18 +6110,23 @@ int32_t iis2iclx_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
*/
int32_t iis2iclx_sh_read_data_raw_get(stmdev_ctx_t *ctx,
- iis2iclx_emb_sh_read_t *val)
+ iis2iclx_emb_sh_read_t *val)
{
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
- if(ret == 0){
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_SENSOR_HUB_1, (uint8_t*)val, 18);
+ if (ret == 0)
+ {
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_SENSOR_HUB_1, (uint8_t *)val,
+ 18);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -5234,25 +6139,31 @@ int32_t iis2iclx_sh_read_data_raw_get(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_sh_slave_connected_set(stmdev_ctx_t *ctx,
- iis2iclx_aux_sens_on_t val)
+ iis2iclx_aux_sens_on_t val)
{
iis2iclx_master_config_t master_config;
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- master_config.aux_sens_on= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ master_config.aux_sens_on = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -5265,37 +6176,47 @@ int32_t iis2iclx_sh_slave_connected_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_sh_slave_connected_get(stmdev_ctx_t *ctx,
- iis2iclx_aux_sens_on_t *val)
+ iis2iclx_aux_sens_on_t *val)
{
iis2iclx_master_config_t master_config;
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
- switch (master_config.aux_sens_on){
+
+ switch (master_config.aux_sens_on)
+ {
case IIS2ICLX_SLV_0:
*val = IIS2ICLX_SLV_0;
break;
+
case IIS2ICLX_SLV_0_1:
*val = IIS2ICLX_SLV_0_1;
break;
+
case IIS2ICLX_SLV_0_1_2:
*val = IIS2ICLX_SLV_0_1_2;
break;
+
case IIS2ICLX_SLV_0_1_2_3:
*val = IIS2ICLX_SLV_0_1_2_3;
break;
+
default:
*val = IIS2ICLX_SLV_0;
break;
}
+
return ret;
}
@@ -5314,18 +6235,24 @@ int32_t iis2iclx_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- master_config.master_on= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ master_config.master_on = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -5344,14 +6271,18 @@ int32_t iis2iclx_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = master_config.master_on;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -5364,25 +6295,31 @@ int32_t iis2iclx_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t iis2iclx_sh_pin_mode_set(stmdev_ctx_t *ctx,
- iis2iclx_shub_pu_en_t val)
+ iis2iclx_shub_pu_en_t val)
{
iis2iclx_master_config_t master_config;
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- master_config.shub_pu_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ master_config.shub_pu_en = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -5395,30 +6332,39 @@ int32_t iis2iclx_sh_pin_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_sh_pin_mode_get(stmdev_ctx_t *ctx,
- iis2iclx_shub_pu_en_t *val)
+ iis2iclx_shub_pu_en_t *val)
{
iis2iclx_master_config_t master_config;
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
- switch (master_config.shub_pu_en){
+
+ switch (master_config.shub_pu_en)
+ {
case IIS2ICLX_EXT_PULL_UP:
*val = IIS2ICLX_EXT_PULL_UP;
break;
+
case IIS2ICLX_INTERNAL_PULL_UP:
*val = IIS2ICLX_INTERNAL_PULL_UP;
break;
+
default:
*val = IIS2ICLX_EXT_PULL_UP;
break;
}
+
return ret;
}
@@ -5437,18 +6383,24 @@ int32_t iis2iclx_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- master_config.pass_through_mode= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ master_config.pass_through_mode = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -5467,14 +6419,18 @@ int32_t iis2iclx_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = master_config.pass_through_mode;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -5487,25 +6443,31 @@ int32_t iis2iclx_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t iis2iclx_sh_syncro_mode_set(stmdev_ctx_t *ctx,
- iis2iclx_start_config_t val)
+ iis2iclx_start_config_t val)
{
iis2iclx_master_config_t master_config;
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- master_config.start_config= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ master_config.start_config = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -5518,31 +6480,39 @@ int32_t iis2iclx_sh_syncro_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_sh_syncro_mode_get(stmdev_ctx_t *ctx,
- iis2iclx_start_config_t *val)
+ iis2iclx_start_config_t *val)
{
iis2iclx_master_config_t master_config;
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
- switch (master_config.start_config){
+
+ switch (master_config.start_config)
+ {
case IIS2ICLX_EXT_ON_INT2_PIN:
*val = IIS2ICLX_EXT_ON_INT2_PIN;
break;
+
case IIS2ICLX_XL_GY_DRDY:
*val = IIS2ICLX_XL_GY_DRDY;
break;
+
default:
*val = IIS2ICLX_EXT_ON_INT2_PIN;
break;
}
+
return ret;
}
@@ -5556,25 +6526,31 @@ int32_t iis2iclx_sh_syncro_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_sh_write_mode_set(stmdev_ctx_t *ctx,
- iis2iclx_write_once_t val)
+ iis2iclx_write_once_t val)
{
iis2iclx_master_config_t master_config;
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- master_config.write_once= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ master_config.write_once = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -5588,31 +6564,39 @@ int32_t iis2iclx_sh_write_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_sh_write_mode_get(stmdev_ctx_t *ctx,
- iis2iclx_write_once_t *val)
+ iis2iclx_write_once_t *val)
{
iis2iclx_master_config_t master_config;
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
- switch (master_config.write_once){
+
+ switch (master_config.write_once)
+ {
case IIS2ICLX_EACH_SH_CYCLE:
*val = IIS2ICLX_EACH_SH_CYCLE;
break;
+
case IIS2ICLX_ONLY_FIRST_CYCLE:
*val = IIS2ICLX_ONLY_FIRST_CYCLE;
break;
+
default:
*val = IIS2ICLX_EACH_SH_CYCLE;
break;
}
+
return ret;
}
@@ -5630,23 +6614,31 @@ int32_t iis2iclx_sh_reset_set(stmdev_ctx_t *ctx)
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
master_config.rst_master_regs = PROPERTY_ENABLE;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
master_config.rst_master_regs = PROPERTY_DISABLE;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -5665,14 +6657,18 @@ int32_t iis2iclx_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
*val = master_config.rst_master_regs;
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -5685,25 +6681,31 @@ int32_t iis2iclx_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t iis2iclx_sh_data_rate_set(stmdev_ctx_t *ctx,
- iis2iclx_shub_odr_t val)
+ iis2iclx_shub_odr_t val)
{
iis2iclx_slv0_config_t slv0_config;
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv0_config.shub_odr = (uint8_t)val;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -5716,37 +6718,47 @@ int32_t iis2iclx_sh_data_rate_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_sh_data_rate_get(stmdev_ctx_t *ctx,
- iis2iclx_shub_odr_t *val)
+ iis2iclx_shub_odr_t *val)
{
iis2iclx_slv0_config_t slv0_config;
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
- switch (slv0_config.shub_odr){
+
+ switch (slv0_config.shub_odr)
+ {
case IIS2ICLX_SH_ODR_104Hz:
*val = IIS2ICLX_SH_ODR_104Hz;
break;
+
case IIS2ICLX_SH_ODR_52Hz:
*val = IIS2ICLX_SH_ODR_52Hz;
break;
+
case IIS2ICLX_SH_ODR_26Hz:
*val = IIS2ICLX_SH_ODR_26Hz;
break;
+
case IIS2ICLX_SH_ODR_13Hz:
*val = IIS2ICLX_SH_ODR_13Hz;
break;
+
default:
*val = IIS2ICLX_SH_ODR_104Hz;
break;
}
+
return ret;
}
@@ -5762,30 +6774,38 @@ int32_t iis2iclx_sh_data_rate_get(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_sh_cfg_write(stmdev_ctx_t *ctx,
- iis2iclx_sh_cfg_write_t *val)
+ iis2iclx_sh_cfg_write_t *val)
{
iis2iclx_slv0_add_t slv0_add;
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
- if(ret == 0){
- slv0_add.slave0 = (uint8_t) (val->slv0_add >> 1);
+ if (ret == 0)
+ {
+ slv0_add.slave0 = (uint8_t)(val->slv0_add >> 1);
slv0_add.rw_0 = 0;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV0_ADD,
- (uint8_t*)&(slv0_add), 1);
+ (uint8_t *) & (slv0_add), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV0_SUBADD,
- (uint8_t*)&(val->slv0_subadd), 1);
+ (uint8_t *) & (val->slv0_subadd), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_write_reg(ctx, IIS2ICLX_DATAWRITE_SLV0,
- (uint8_t*)&(val->slv0_data), 1);
+ (uint8_t *) & (val->slv0_data), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -5801,7 +6821,7 @@ int32_t iis2iclx_sh_cfg_write(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
- iis2iclx_sh_cfg_read_t *val)
+ iis2iclx_sh_cfg_read_t *val)
{
iis2iclx_slv0_config_t slv0_config;
iis2iclx_slv0_add_t slv0_add;
@@ -5809,28 +6829,38 @@ int32_t iis2iclx_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
slv0_add.slave0 = (uint8_t) val->slv_add >> 1;
slv0_add.rw_0 = 1;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV0_ADD,
- (uint8_t*)&(slv0_add), 1);
+ (uint8_t *) & (slv0_add), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV0_SUBADD,
- &(val->slv_subadd), 1);
+ &(val->slv_subadd), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv0_config.slave0_numop = val->slv_len;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -5846,34 +6876,45 @@ int32_t iis2iclx_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
- iis2iclx_sh_cfg_read_t *val)
+ iis2iclx_sh_cfg_read_t *val)
{
iis2iclx_slv1_config_t slv1_config;
iis2iclx_slv1_add_t slv1_add;
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
- if(ret == 0){
- slv1_add.slave1_add = (uint8_t) (val->slv_add >> 1);
+
+ if (ret == 0)
+ {
+ slv1_add.slave1_add = (uint8_t)(val->slv_add >> 1);
slv1_add.r_1 = 1;
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV1_ADD, (uint8_t*)&slv1_add, 1);
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV1_ADD, (uint8_t *)&slv1_add, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV1_SUBADD,
- &(val->slv_subadd), 1);
+ &(val->slv_subadd), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_SLV1_CONFIG,
- (uint8_t*)&slv1_config, 1);
+ (uint8_t *)&slv1_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv1_config.slave1_numop = val->slv_len;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV1_CONFIG,
- (uint8_t*)&slv1_config, 1);
+ (uint8_t *)&slv1_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
-}
+ }
+
return ret;
}
@@ -5889,7 +6930,7 @@ int32_t iis2iclx_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
- iis2iclx_sh_cfg_read_t *val)
+ iis2iclx_sh_cfg_read_t *val)
{
iis2iclx_slv2_config_t slv2_config;
iis2iclx_slv2_add_t slv2_add;
@@ -5897,28 +6938,38 @@ int32_t iis2iclx_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
- if(ret == 0){
- slv2_add.slave2_add = (uint8_t) (val->slv_add >> 1);
+ if (ret == 0)
+ {
+ slv2_add.slave2_add = (uint8_t)(val->slv_add >> 1);
slv2_add.r_2 = 1;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV2_ADD,
- (uint8_t*)&slv2_add, 1);
+ (uint8_t *)&slv2_add, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV2_SUBADD,
- (uint8_t*)&(val->slv_subadd), 1);
+ (uint8_t *) & (val->slv_subadd), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_SLV2_CONFIG,
- (uint8_t*)&slv2_config, 1);
+ (uint8_t *)&slv2_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv2_config.slave2_numop = val->slv_len;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV2_CONFIG,
- (uint8_t*)&slv2_config, 1);
+ (uint8_t *)&slv2_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -5934,7 +6985,7 @@ int32_t iis2iclx_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
- iis2iclx_sh_cfg_read_t *val)
+ iis2iclx_sh_cfg_read_t *val)
{
iis2iclx_slv3_config_t slv3_config;
iis2iclx_slv3_add_t slv3_add;
@@ -5942,28 +6993,38 @@ int32_t iis2iclx_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
- if(ret == 0){
- slv3_add.slave3_add = (uint8_t) (val->slv_add >> 1);
+ if (ret == 0)
+ {
+ slv3_add.slave3_add = (uint8_t)(val->slv_add >> 1);
slv3_add.r_3 = 1;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV3_ADD,
- (uint8_t*)&slv3_add, 1);
+ (uint8_t *)&slv3_add, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV3_SUBADD,
- &(val->slv_subadd), 1);
+ &(val->slv_subadd), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_read_reg(ctx, IIS2ICLX_SLV3_CONFIG,
- (uint8_t*)&slv3_config, 1);
+ (uint8_t *)&slv3_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv3_config.slave3_numop = val->slv_len;
ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV3_CONFIG,
- (uint8_t*)&slv3_config, 1);
+ (uint8_t *)&slv3_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
+
return ret;
}
@@ -5976,76 +7037,99 @@ int32_t iis2iclx_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
*
*/
int32_t iis2iclx_sh_status_get(stmdev_ctx_t *ctx,
- iis2iclx_status_master_t *val)
+ iis2iclx_status_master_t *val)
{
int32_t ret;
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
- if(ret == 0){
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_STATUS_MASTER, (uint8_t*)val, 1);
+ if (ret == 0)
+ {
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_STATUS_MASTER, (uint8_t *)val, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
}
- return ret;
+ return ret;
}
-int32_t iis2iclx_bus_mode_set(stmdev_ctx_t *ctx, iis2iclx_bus_mode_t val)
+int32_t iis2iclx_bus_mode_set(stmdev_ctx_t *ctx,
+ iis2iclx_bus_mode_t val)
{
iis2iclx_ctrl9_xl_t ctrl9_xl;
iis2iclx_ctrl3_c_t ctrl3_c;
iis2iclx_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if (ret == 0) {
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
ctrl9_xl.device_conf = PROPERTY_ENABLE;
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
}
- if (ret == 0) {
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C,(uint8_t*)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ctrl3_c.sim = ((uint8_t)val & 0x02U) >> 1;
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
- if (ret == 0) {
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL4_C,(uint8_t*)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ctrl4_c.i2c_disable = ((uint8_t)val & 0x01U);
- ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
-int32_t iis2iclx_bus_mode_get(stmdev_ctx_t *ctx, iis2iclx_bus_mode_t *val)
+int32_t iis2iclx_bus_mode_get(stmdev_ctx_t *ctx,
+ iis2iclx_bus_mode_t *val)
{
iis2iclx_ctrl3_c_t ctrl3_c;
iis2iclx_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C,(uint8_t*)&ctrl3_c, 1);
- if (ret == 0) {
- ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL4_C,(uint8_t*)&ctrl4_c, 1);
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
- switch ( ( ctrl3_c.sim << 1 ) | ctrl4_c.i2c_disable ) {
- case IIS2ICLX_SEL_BY_HW:
- *val = IIS2ICLX_SEL_BY_HW;
- break;
- case IIS2ICLX_SPI_4W:
- *val = IIS2ICLX_SPI_4W;
- break;
- case IIS2ICLX_SPI_3W:
- *val = IIS2ICLX_SPI_3W;
- break;
- default:
- *val = IIS2ICLX_SEL_BY_HW;
- break;
+ switch ((ctrl3_c.sim << 1) | ctrl4_c.i2c_disable)
+ {
+ case IIS2ICLX_SEL_BY_HW:
+ *val = IIS2ICLX_SEL_BY_HW;
+ break;
+
+ case IIS2ICLX_SPI_4W:
+ *val = IIS2ICLX_SPI_4W;
+ break;
+
+ case IIS2ICLX_SPI_3W:
+ *val = IIS2ICLX_SPI_3W;
+ break;
+
+ default:
+ *val = IIS2ICLX_SEL_BY_HW;
+ break;
}
+
return ret;
}
diff --git a/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.h b/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.h
index dbe71736d0b809b3d9765163651dade65452c716..e3d64a0e9eabcc745536a7d9db356f0f1b45015e 100644
--- a/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.h
+++ b/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file iis2iclx_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * iis2iclx_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file iis2iclx_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * iis2iclx_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef IIS2ICLX_REGS_H
#define IIS2ICLX_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup IIS2ICLX
@@ -74,7 +75,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -107,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -139,7 +142,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -174,18 +178,22 @@ typedef struct {
*/
#define IIS2ICLX_FUNC_CFG_ACCESS 0x01U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 6;
- uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */
+uint8_t reg_access :
+ 2; /* shub_reg_access + func_cfg_access */
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */
+uint8_t reg_access :
+ 2; /* shub_reg_access + func_cfg_access */
uint8_t not_used_01 : 6;
#endif /* DRV_BYTE_ORDER */
} iis2iclx_func_cfg_access_t;
#define IIS2ICLX_PIN_CTRL 0x02U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 6;
uint8_t sdo_pu_en : 1;
@@ -198,12 +206,14 @@ typedef struct {
} iis2iclx_pin_ctrl_t;
#define IIS2ICLX_FIFO_CTRL1 0x07U
-typedef struct {
+typedef struct
+{
uint8_t wtm : 8;
} iis2iclx_fifo_ctrl1_t;
#define IIS2ICLX_FIFO_CTRL2 0x08U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wtm : 1;
uint8_t not_used_01 : 3;
@@ -220,7 +230,8 @@ typedef struct {
} iis2iclx_fifo_ctrl2_t;
#define IIS2ICLX_FIFO_CTRL3 0x09U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bdr_xl : 4;
uint8_t not_used_01 : 4;
@@ -231,7 +242,8 @@ typedef struct {
} iis2iclx_fifo_ctrl3_t;
#define IIS2ICLX_FIFO_CTRL4 0x0AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fifo_mode : 3;
uint8_t not_used_01 : 1;
@@ -246,7 +258,8 @@ typedef struct {
} iis2iclx_fifo_ctrl4_t;
#define IIS2ICLX_COUNTER_BDR_REG1 0x0BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t cnt_bdr_th : 1;
uint8_t not_used_01 : 5;
@@ -261,12 +274,14 @@ typedef struct {
} iis2iclx_counter_bdr_reg1_t;
#define IIS2ICLX_COUNTER_BDR_REG2 0x0CU
-typedef struct {
+typedef struct
+{
uint8_t cnt_bdr_th : 8;
} iis2iclx_counter_bdr_reg2_t;
#define IIS2ICLX_INT1_CTRL 0x0DU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_drdy_xl : 1;
uint8_t not_used_01 : 1;
@@ -289,7 +304,8 @@ typedef struct {
} iis2iclx_int1_ctrl_t;
#define IIS2ICLX_INT2_CTRL 0x0EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_drdy_xl : 1;
uint8_t not_used_01 : 1;
@@ -313,7 +329,8 @@ typedef struct {
#define IIS2ICLX_WHO_AM_I 0x0FU
#define IIS2ICLX_CTRL1_XL 0x10U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t lpf2_xl_en : 1;
@@ -328,7 +345,8 @@ typedef struct {
} iis2iclx_ctrl1_xl_t;
#define IIS2ICLX_CTRL3_C 0x12U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sw_reset : 1;
uint8_t not_used_01 : 1;
@@ -351,7 +369,8 @@ typedef struct {
} iis2iclx_ctrl3_c_t;
#define IIS2ICLX_CTRL4_C 0x13U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t i2c_disable : 1;
@@ -370,7 +389,8 @@ typedef struct {
} iis2iclx_ctrl4_c_t;
#define IIS2ICLX_CTRL5_C 0x14U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_xl : 2;
uint8_t not_used_01 : 6;
@@ -381,14 +401,17 @@ typedef struct {
} iis2iclx_ctrl5_c_t;
#define IIS2ICLX_CTRL6_C 0x15U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t usr_off_w : 1;
uint8_t not_used_02 : 1;
- uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */
+uint8_t den_mode :
+ 3; /* trig_en + lvl1_en + lvl2_en */
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */
+uint8_t den_mode :
+ 3; /* trig_en + lvl1_en + lvl2_en */
uint8_t not_used_02 : 1;
uint8_t usr_off_w : 1;
uint8_t not_used_01 : 3;
@@ -396,7 +419,8 @@ typedef struct {
} iis2iclx_ctrl6_c_t;
#define IIS2ICLX_CTRL7_XL 0x16U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t usr_off_on_out : 1;
@@ -409,7 +433,8 @@ typedef struct {
} iis2iclx_ctrl7_xl_t;
#define IIS2ICLX_CTRL8_XL 0x17U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t hp_slope_xl_en : 1;
@@ -426,7 +451,8 @@ typedef struct {
} iis2iclx_ctrl8_xl_t;
#define IIS2ICLX_CTRL9_XL 0x18U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t device_conf : 1;
@@ -445,7 +471,8 @@ typedef struct {
} iis2iclx_ctrl9_xl_t;
#define IIS2ICLX_CTRL10_C 0x19U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 5;
uint8_t timestamp_en : 1;
@@ -458,7 +485,8 @@ typedef struct {
} iis2iclx_ctrl10_c_t;
#define IIS2ICLX_ALL_INT_SRC 0x1AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t wu_ia : 1;
@@ -481,7 +509,8 @@ typedef struct {
} iis2iclx_all_int_src_t;
#define IIS2ICLX_WAKE_UP_SRC 0x1BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t y_wu : 1;
@@ -504,7 +533,8 @@ typedef struct {
} iis2iclx_wake_up_src_t;
#define IIS2ICLX_TAP_SRC 0x1CU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t y_tap : 1;
@@ -527,7 +557,8 @@ typedef struct {
} iis2iclx_tap_src_t;
#define IIS2ICLX_DEN_SRC 0x1DU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 7;
uint8_t den_drdy : 1;
@@ -538,7 +569,8 @@ typedef struct {
} iis2iclx_den_src_t;
#define IIS2ICLX_STATUS_REG 0x1EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlda : 1;
uint8_t not_used_01 : 1;
@@ -559,7 +591,8 @@ typedef struct {
#define IIS2ICLX_OUTY_L_A 0x2AU
#define IIS2ICLX_OUTY_H_A 0x2BU
#define IIS2ICLX_EMB_FUNC_STATUS_MAINPAGE 0x35U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 7;
uint8_t is_fsm_lc : 1;
@@ -570,7 +603,8 @@ typedef struct {
} iis2iclx_emb_func_status_mainpage_t;
#define IIS2ICLX_FSM_STATUS_A_MAINPAGE 0x36U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_fsm1 : 1;
uint8_t is_fsm2 : 1;
@@ -593,7 +627,8 @@ typedef struct {
} iis2iclx_fsm_status_a_mainpage_t;
#define IIS2ICLX_FSM_STATUS_B_MAINPAGE 0x37U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_fsm9 : 1;
uint8_t is_fsm10 : 1;
@@ -616,7 +651,8 @@ typedef struct {
} iis2iclx_fsm_status_b_mainpage_t;
#define IIS2ICLX_MLC_STATUS_MAINPAGE 0x38U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_mlc1 : 1;
uint8_t is_mlc2 : 1;
@@ -639,7 +675,8 @@ typedef struct {
} iis2iclx_mlc_status_mainpage_t;
#define IIS2ICLX_STATUS_MASTER_MAINPAGE 0x39U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sens_hub_endop : 1;
uint8_t not_used_01 : 2;
@@ -660,12 +697,14 @@ typedef struct {
} iis2iclx_status_master_mainpage_t;
#define IIS2ICLX_FIFO_STATUS1 0x3AU
-typedef struct {
+typedef struct
+{
uint8_t diff_fifo : 8;
} iis2iclx_fifo_status1_t;
#define IIS2ICLX_FIFO_STATUS2 0x3BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t diff_fifo : 2;
uint8_t not_used_01 : 1;
@@ -690,7 +729,8 @@ typedef struct {
#define IIS2ICLX_TIMESTAMP2 0x42U
#define IIS2ICLX_TIMESTAMP3 0x43U
#define IIS2ICLX_TAP_CFG0 0x56U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lir : 1;
uint8_t not_used_01 : 1;
@@ -713,7 +753,8 @@ typedef struct {
} iis2iclx_tap_cfg0_t;
#define IIS2ICLX_TAP_CFG1 0x57U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_ths_x : 5;
uint8_t tap_priority : 1;
@@ -726,7 +767,8 @@ typedef struct {
} iis2iclx_tap_cfg1_t;
#define IIS2ICLX_TAP_CFG2 0x58U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_ths_y : 5;
uint8_t not_used_01 : 2;
@@ -739,7 +781,8 @@ typedef struct {
} iis2iclx_tap_cfg2_t;
#define IIS2ICLX_INT_DUR2 0x5AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shock : 2;
uint8_t quiet : 2;
@@ -752,7 +795,8 @@ typedef struct {
} iis2iclx_int_dur2_t;
#define IIS2ICLX_WAKE_UP_THS 0x5BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wk_ths : 6;
uint8_t usr_off_on_wu : 1;
@@ -765,7 +809,8 @@ typedef struct {
} iis2iclx_wake_up_ths_t;
#define IIS2ICLX_WAKE_UP_DUR 0x5CU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sleep_dur : 4;
uint8_t wake_ths_w : 1;
@@ -780,7 +825,8 @@ typedef struct {
} iis2iclx_wake_up_dur_t;
#define IIS2ICLX_MD1_CFG 0x5EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_shub : 1;
uint8_t int1_emb_func : 1;
@@ -803,7 +849,8 @@ typedef struct {
} iis2iclx_md1_cfg_t;
#define IIS2ICLX_MD2_CFG 0x5FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_timestamp : 1;
uint8_t int2_emb_func : 1;
@@ -826,14 +873,16 @@ typedef struct {
} iis2iclx_md2_cfg_t;
#define IIS2ICLX_INTERNAL_FREQ_FINE 0x63U
-typedef struct {
+typedef struct
+{
uint8_t freq_fine : 8;
} iis2iclx_internal_freq_fine_t;
#define IIS2ICLX_X_OFS_USR 0x73U
#define IIS2ICLX_Y_OFS_USR 0x74U
#define IIS2ICLX_FIFO_DATA_OUT_TAG 0x78U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tag_parity : 1;
uint8_t tag_cnt : 2;
@@ -852,7 +901,8 @@ typedef struct {
#define IIS2ICLX_FIFO_DATA_OUT_Z_L 0x7DU
#define IIS2ICLX_FIFO_DATA_OUT_Z_H 0x7EU
#define IIS2ICLX_PAGE_SEL 0x02U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 4;
uint8_t page_sel : 4;
@@ -863,7 +913,8 @@ typedef struct {
} iis2iclx_page_sel_t;
#define IIS2ICLX_EMB_FUNC_EN_B 0x05U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fsm_en : 1;
uint8_t not_used_01 : 3;
@@ -878,17 +929,20 @@ typedef struct {
} iis2iclx_emb_func_en_b_t;
#define IIS2ICLX_PAGE_ADDRESS 0x08U
-typedef struct {
+typedef struct
+{
uint8_t page_addr : 8;
} iis2iclx_page_address_t;
#define IIS2ICLX_PAGE_VALUE 0x09U
-typedef struct {
+typedef struct
+{
uint8_t page_value : 8;
} iis2iclx_page_value_t;
#define IIS2ICLX_EMB_FUNC_INT1 0x0AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 7;
uint8_t int1_fsm_lc : 1;
@@ -899,7 +953,8 @@ typedef struct {
} iis2iclx_emb_func_int1_t;
#define IIS2ICLX_FSM_INT1_A 0x0BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_fsm1 : 1;
uint8_t int1_fsm2 : 1;
@@ -922,7 +977,8 @@ typedef struct {
} iis2iclx_fsm_int1_a_t;
#define IIS2ICLX_FSM_INT1_B 0x0CU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_fsm9 : 1;
uint8_t int1_fsm10 : 1;
@@ -945,7 +1001,8 @@ typedef struct {
} iis2iclx_fsm_int1_b_t;
#define IIS2ICLX_MLC_INT1 0x0DU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_mlc1 : 1;
uint8_t int1_mlc2 : 1;
@@ -968,7 +1025,8 @@ typedef struct {
} iis2iclx_mlc_int1_t;
#define IIS2ICLX_EMB_FUNC_INT2 0x0EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 7;
uint8_t int2_fsm_lc : 1;
@@ -979,7 +1037,8 @@ typedef struct {
} iis2iclx_emb_func_int2_t;
#define IIS2ICLX_FSM_INT2_A 0x0FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_fsm1 : 1;
uint8_t int2_fsm2 : 1;
@@ -1002,7 +1061,8 @@ typedef struct {
} iis2iclx_fsm_int2_a_t;
#define IIS2ICLX_FSM_INT2_B 0x10U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_fsm9 : 1;
uint8_t int2_fsm10 : 1;
@@ -1025,7 +1085,8 @@ typedef struct {
} iis2iclx_fsm_int2_b_t;
#define IIS2ICLX_MLC_INT2 0x11U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_mlc1 : 1;
uint8_t int2_mlc2 : 1;
@@ -1048,7 +1109,8 @@ typedef struct {
} iis2iclx_mlc_int2_t;
#define IIS2ICLX_EMB_FUNC_STATUS 0x12U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 7;
uint8_t is_fsm_lc : 1;
@@ -1059,7 +1121,8 @@ typedef struct {
} iis2iclx_emb_func_status_t;
#define IIS2ICLX_FSM_STATUS_A 0x13U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_fsm1 : 1;
uint8_t is_fsm2 : 1;
@@ -1082,7 +1145,8 @@ typedef struct {
} iis2iclx_fsm_status_a_t;
#define IIS2ICLX_FSM_STATUS_B 0x14U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_fsm9 : 1;
uint8_t is_fsm10 : 1;
@@ -1105,7 +1169,8 @@ typedef struct {
} iis2iclx_fsm_status_b_t;
#define IIS2ICLX_MLC_STATUS 0x15U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_mlc1 : 1;
uint8_t is_mlc2 : 1;
@@ -1128,7 +1193,8 @@ typedef struct {
} iis2iclx_mlc_status_t;
#define IIS2ICLX_PAGE_RW 0x17U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 5;
uint8_t page_rw : 2; /* page_write + page_read */
@@ -1141,7 +1207,8 @@ typedef struct {
} iis2iclx_page_rw_t;
#define IIS2ICLX_FSM_ENABLE_A 0x46U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fsm1_en : 1;
uint8_t fsm2_en : 1;
@@ -1164,7 +1231,8 @@ typedef struct {
} iis2iclx_fsm_enable_a_t;
#define IIS2ICLX_FSM_ENABLE_B 0x47U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fsm9_en : 1;
uint8_t fsm10_en : 1;
@@ -1189,18 +1257,22 @@ typedef struct {
#define IIS2ICLX_FSM_LONG_COUNTER_L 0x48U
#define IIS2ICLX_FSM_LONG_COUNTER_H 0x49U
#define IIS2ICLX_FSM_LONG_COUNTER_CLEAR 0x4AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */
+uint8_t fsm_lc_clr :
+ 2; /* fsm_lc_cleared + fsm_lc_clear */
uint8_t not_used_01 : 6;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used_01 : 6;
- uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */
+uint8_t fsm_lc_clr :
+ 2; /* fsm_lc_cleared + fsm_lc_clear */
#endif /* DRV_BYTE_ORDER */
} iis2iclx_fsm_long_counter_clear_t;
#define IIS2ICLX_FSM_OUTS1 0x4CU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1223,7 +1295,8 @@ typedef struct {
} iis2iclx_fsm_outs1_t;
#define IIS2ICLX_FSM_OUTS2 0x4DU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1246,7 +1319,8 @@ typedef struct {
} iis2iclx_fsm_outs2_t;
#define IIS2ICLX_FSM_OUTS3 0x4EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1269,7 +1343,8 @@ typedef struct {
} iis2iclx_fsm_outs3_t;
#define IIS2ICLX_FSM_OUTS4 0x4FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1292,7 +1367,8 @@ typedef struct {
} iis2iclx_fsm_outs4_t;
#define IIS2ICLX_FSM_OUTS5 0x50U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1315,7 +1391,8 @@ typedef struct {
} iis2iclx_fsm_outs5_t;
#define IIS2ICLX_FSM_OUTS6 0x51U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1338,7 +1415,8 @@ typedef struct {
} iis2iclx_fsm_outs6_t;
#define IIS2ICLX_FSM_OUTS7 0x52U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1361,7 +1439,8 @@ typedef struct {
} iis2iclx_fsm_outs7_t;
#define IIS2ICLX_FSM_OUTS8 0x53U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1384,7 +1463,8 @@ typedef struct {
} iis2iclx_fsm_outs8_t;
#define IIS2ICLX_FSM_OUTS9 0x54U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1407,7 +1487,8 @@ typedef struct {
} iis2iclx_fsm_outs9_t;
#define IIS2ICLX_FSM_OUTS10 0x55U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1430,7 +1511,8 @@ typedef struct {
} iis2iclx_fsm_outs10_t;
#define IIS2ICLX_FSM_OUTS11 0x56U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1453,7 +1535,8 @@ typedef struct {
} iis2iclx_fsm_outs11_t;
#define IIS2ICLX_FSM_OUTS12 0x57U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1476,7 +1559,8 @@ typedef struct {
} iis2iclx_fsm_outs12_t;
#define IIS2ICLX_FSM_OUTS13 0x58U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1499,7 +1583,8 @@ typedef struct {
} iis2iclx_fsm_outs13_t;
#define IIS2ICLX_FSM_OUTS14 0x59U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1522,7 +1607,8 @@ typedef struct {
} iis2iclx_fsm_outs14_t;
#define IIS2ICLX_FSM_OUTS15 0x5AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1545,7 +1631,8 @@ typedef struct {
} iis2iclx_fsm_outs15_t;
#define IIS2ICLX_FSM_OUTS16 0x5BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1568,7 +1655,8 @@ typedef struct {
} iis2iclx_fsm_outs16_t;
#define IIS2ICLX_EMB_FUNC_ODR_CFG_B 0x5FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t fsm_odr : 2;
@@ -1581,7 +1669,8 @@ typedef struct {
} iis2iclx_emb_func_odr_cfg_b_t;
#define IIS2ICLX_EMB_FUNC_ODR_CFG_C 0x60U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 4;
uint8_t mlc_odr : 2;
@@ -1594,7 +1683,8 @@ typedef struct {
} iis2iclx_emb_func_odr_cfg_c_t;
#define IIS2ICLX_EMB_FUNC_INIT_B 0x67U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fsm_init : 1;
uint8_t not_used_01 : 3;
@@ -1623,421 +1713,440 @@ typedef struct {
#define IIS2ICLX_FSM_START_ADD_L 0x17EU
#define IIS2ICLX_FSM_START_ADD_H 0x17FU
#define IIS2ICLX_SENSOR_HUB_1 0x02U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} iis2iclx_sensor_hub_1_t;
#define IIS2ICLX_SENSOR_HUB_2 0x03U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} iis2iclx_sensor_hub_2_t;
#define IIS2ICLX_SENSOR_HUB_3 0x04U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} iis2iclx_sensor_hub_3_t;
#define IIS2ICLX_SENSOR_HUB_4 0x05U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} iis2iclx_sensor_hub_4_t;
#define IIS2ICLX_SENSOR_HUB_5 0x06U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} iis2iclx_sensor_hub_5_t;
#define IIS2ICLX_SENSOR_HUB_6 0x07U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} iis2iclx_sensor_hub_6_t;
#define IIS2ICLX_SENSOR_HUB_7 0x08U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} iis2iclx_sensor_hub_7_t;
#define IIS2ICLX_SENSOR_HUB_8 0x09U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} iis2iclx_sensor_hub_8_t;
#define IIS2ICLX_SENSOR_HUB_9 0x0AU
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} iis2iclx_sensor_hub_9_t;
#define IIS2ICLX_SENSOR_HUB_10 0x0BU
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} iis2iclx_sensor_hub_10_t;
#define IIS2ICLX_SENSOR_HUB_11 0x0CU
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} iis2iclx_sensor_hub_11_t;
#define IIS2ICLX_SENSOR_HUB_12 0x0DU
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} iis2iclx_sensor_hub_12_t;
#define IIS2ICLX_SENSOR_HUB_13 0x0EU
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} iis2iclx_sensor_hub_13_t;
#define IIS2ICLX_SENSOR_HUB_14 0x0FU
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} iis2iclx_sensor_hub_14_t;
#define IIS2ICLX_SENSOR_HUB_15 0x10U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} iis2iclx_sensor_hub_15_t;
#define IIS2ICLX_SENSOR_HUB_16 0x11U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} iis2iclx_sensor_hub_16_t;
#define IIS2ICLX_SENSOR_HUB_17 0x12U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} iis2iclx_sensor_hub_17_t;
#define IIS2ICLX_SENSOR_HUB_18 0x13U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} iis2iclx_sensor_hub_18_t;
#define IIS2ICLX_MASTER_CONFIG 0x14U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t aux_sens_on : 2;
uint8_t master_on : 1;
@@ -2058,7 +2167,8 @@ typedef struct {
} iis2iclx_master_config_t;
#define IIS2ICLX_SLV0_ADD 0x15U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t rw_0 : 1;
uint8_t slave0 : 7;
@@ -2069,12 +2179,14 @@ typedef struct {
} iis2iclx_slv0_add_t;
#define IIS2ICLX_SLV0_SUBADD 0x16U
-typedef struct {
+typedef struct
+{
uint8_t slave0_reg : 8;
} iis2iclx_slv0_subadd_t;
#define IIS2ICLX_SLV0_CONFIG 0x17U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave0_numop : 3;
uint8_t batch_ext_sens_0_en : 1;
@@ -2089,7 +2201,8 @@ typedef struct {
} iis2iclx_slv0_config_t;
#define IIS2ICLX_SLV1_ADD 0x18U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_1 : 1;
uint8_t slave1_add : 7;
@@ -2100,12 +2213,14 @@ typedef struct {
} iis2iclx_slv1_add_t;
#define IIS2ICLX_SLV1_SUBADD 0x19U
-typedef struct {
+typedef struct
+{
uint8_t slave1_reg : 8;
} iis2iclx_slv1_subadd_t;
#define IIS2ICLX_SLV1_CONFIG 0x1AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave1_numop : 3;
uint8_t batch_ext_sens_1_en : 1;
@@ -2118,7 +2233,8 @@ typedef struct {
} iis2iclx_slv1_config_t;
#define IIS2ICLX_SLV2_ADD 0x1BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_2 : 1;
uint8_t slave2_add : 7;
@@ -2129,12 +2245,14 @@ typedef struct {
} iis2iclx_slv2_add_t;
#define IIS2ICLX_SLV2_SUBADD 0x1CU
-typedef struct {
+typedef struct
+{
uint8_t slave2_reg : 8;
} iis2iclx_slv2_subadd_t;
#define IIS2ICLX_SLV2_CONFIG 0x1DU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave2_numop : 3;
uint8_t batch_ext_sens_2_en : 1;
@@ -2147,7 +2265,8 @@ typedef struct {
} iis2iclx_slv2_config_t;
#define IIS2ICLX_SLV3_ADD 0x1EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_3 : 1;
uint8_t slave3_add : 7;
@@ -2158,12 +2277,14 @@ typedef struct {
} iis2iclx_slv3_add_t;
#define IIS2ICLX_SLV3_SUBADD 0x1FU
-typedef struct {
+typedef struct
+{
uint8_t slave3_reg : 8;
} iis2iclx_slv3_subadd_t;
#define IIS2ICLX_SLV3_CONFIG 0x20U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave3_numop : 3;
uint8_t batch_ext_sens_3_en : 1;
@@ -2176,12 +2297,14 @@ typedef struct {
} iis2iclx_slv3_config_t;
#define IIS2ICLX_DATAWRITE_SLV0 0x21U
-typedef struct {
+typedef struct
+{
uint8_t slave0_dataw : 8;
} iis2iclx_datawrite_slv0_t;
#define IIS2ICLX_STATUS_MASTER 0x22U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sens_hub_endop : 1;
uint8_t not_used_01 : 2;
@@ -2203,9 +2326,9 @@ typedef struct {
/**
* @defgroup IIS2ICLX_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -2213,7 +2336,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
iis2iclx_func_cfg_access_t func_cfg_access;
iis2iclx_pin_ctrl_t pin_ctrl;
iis2iclx_fifo_ctrl1_t fifo_ctrl1;
@@ -2331,28 +2455,36 @@ typedef union{
*
*/
-int32_t iis2iclx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
- uint16_t len);
-int32_t iis2iclx_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t iis2iclx_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
+int32_t iis2iclx_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len);
-extern float_t iis2iclx_from_fs500mg_to_mg(int16_t lsb);
-extern float_t iis2iclx_from_fs1g_to_mg(int16_t lsb);
-extern float_t iis2iclx_from_fs2g_to_mg(int16_t lsb);
-extern float_t iis2iclx_from_fs3g_to_mg(int16_t lsb);
-extern float_t iis2iclx_from_lsb_to_celsius(int16_t lsb);
-extern float_t iis2iclx_from_lsb_to_nsec(int32_t lsb);
+float_t iis2iclx_from_fs500mg_to_mg(int16_t lsb);
+float_t iis2iclx_from_fs1g_to_mg(int16_t lsb);
+float_t iis2iclx_from_fs2g_to_mg(int16_t lsb);
+float_t iis2iclx_from_fs3g_to_mg(int16_t lsb);
-typedef enum {
+float_t iis2iclx_from_lsb_to_celsius(int16_t lsb);
+
+float_t iis2iclx_from_lsb_to_nsec(int32_t lsb);
+
+typedef enum
+{
IIS2ICLX_500mg = 0,
IIS2ICLX_3g = 1,
IIS2ICLX_1g = 2,
IIS2ICLX_2g = 3,
} iis2iclx_fs_xl_t;
-int32_t iis2iclx_xl_full_scale_set(stmdev_ctx_t *ctx, iis2iclx_fs_xl_t val);
-int32_t iis2iclx_xl_full_scale_get(stmdev_ctx_t *ctx, iis2iclx_fs_xl_t *val);
+int32_t iis2iclx_xl_full_scale_set(stmdev_ctx_t *ctx,
+ iis2iclx_fs_xl_t val);
+int32_t iis2iclx_xl_full_scale_get(stmdev_ctx_t *ctx,
+ iis2iclx_fs_xl_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_XL_ODR_OFF = 0,
IIS2ICLX_XL_ODR_12Hz5 = 1,
IIS2ICLX_XL_ODR_26Hz = 2,
@@ -2362,40 +2494,48 @@ typedef enum {
IIS2ICLX_XL_ODR_416Hz = 6,
IIS2ICLX_XL_ODR_833Hz = 7,
} iis2iclx_odr_xl_t;
-int32_t iis2iclx_xl_data_rate_set(stmdev_ctx_t *ctx, iis2iclx_odr_xl_t val);
-int32_t iis2iclx_xl_data_rate_get(stmdev_ctx_t *ctx, iis2iclx_odr_xl_t *val);
-
-int32_t iis2iclx_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis2iclx_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
-
-typedef enum {
+int32_t iis2iclx_xl_data_rate_set(stmdev_ctx_t *ctx,
+ iis2iclx_odr_xl_t val);
+int32_t iis2iclx_xl_data_rate_get(stmdev_ctx_t *ctx,
+ iis2iclx_odr_xl_t *val);
+
+int32_t iis2iclx_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t iis2iclx_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+typedef enum
+{
IIS2ICLX_LSb_1mg = 0,
IIS2ICLX_LSb_16mg = 1,
} iis2iclx_usr_off_w_t;
int32_t iis2iclx_xl_offset_weight_set(stmdev_ctx_t *ctx,
- iis2iclx_usr_off_w_t val);
+ iis2iclx_usr_off_w_t val);
int32_t iis2iclx_xl_offset_weight_get(stmdev_ctx_t *ctx,
- iis2iclx_usr_off_w_t *val);
+ iis2iclx_usr_off_w_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_HIGH_PERFORMANCE_MD = 0,
IIS2ICLX_LOW_NORMAL_POWER_MD = 1,
} iis2iclx_xl_hm_mode_t;
int32_t iis2iclx_xl_power_mode_set(stmdev_ctx_t *ctx,
- iis2iclx_xl_hm_mode_t val);
+ iis2iclx_xl_hm_mode_t val);
int32_t iis2iclx_xl_power_mode_get(stmdev_ctx_t *ctx,
- iis2iclx_xl_hm_mode_t *val);
+ iis2iclx_xl_hm_mode_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_GY_HIGH_PERFORMANCE = 0,
IIS2ICLX_GY_NORMAL = 1,
} iis2iclx_g_hm_mode_t;
int32_t iis2iclx_gy_power_mode_set(stmdev_ctx_t *ctx,
- iis2iclx_g_hm_mode_t val);
+ iis2iclx_g_hm_mode_t val);
int32_t iis2iclx_gy_power_mode_get(stmdev_ctx_t *ctx,
- iis2iclx_g_hm_mode_t *val);
+ iis2iclx_g_hm_mode_t *val);
-typedef struct {
+typedef struct
+{
iis2iclx_all_int_src_t all_int_src;
iis2iclx_wake_up_src_t wake_up_src;
iis2iclx_tap_src_t tap_src;
@@ -2404,22 +2544,28 @@ typedef struct {
iis2iclx_emb_func_status_t emb_func_status;
iis2iclx_fsm_status_a_t fsm_status_a;
iis2iclx_fsm_status_b_t fsm_status_b;
- } iis2iclx_all_sources_t;
+} iis2iclx_all_sources_t;
int32_t iis2iclx_all_sources_get(stmdev_ctx_t *ctx,
- iis2iclx_all_sources_t *val);
+ iis2iclx_all_sources_t *val);
int32_t iis2iclx_status_reg_get(stmdev_ctx_t *ctx,
- iis2iclx_status_reg_t *val);
+ iis2iclx_status_reg_t *val);
-int32_t iis2iclx_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis2iclx_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t iis2iclx_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis2iclx_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t iis2iclx_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t iis2iclx_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t iis2iclx_xl_usr_offset_x_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t iis2iclx_xl_usr_offset_x_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
-int32_t iis2iclx_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t iis2iclx_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t iis2iclx_xl_usr_offset_y_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t iis2iclx_xl_usr_offset_y_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
int32_t iis2iclx_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2iclx_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -2431,37 +2577,46 @@ int32_t iis2iclx_timestamp_raw_get(stmdev_ctx_t *ctx, int32_t *val);
int32_t iis2iclx_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val);
-int32_t iis2iclx_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t iis2iclx_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
int32_t iis2iclx_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t iis2iclx_device_conf_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t iis2iclx_device_conf_get(stmdev_ctx_t *ctx, uint8_t *val);
+
int32_t iis2iclx_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2iclx_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_USER_BANK = 0,
IIS2ICLX_SENSOR_HUB_BANK = 1,
IIS2ICLX_EMBEDDED_FUNC_BANK = 2,
} iis2iclx_reg_access_t;
-int32_t iis2iclx_mem_bank_set(stmdev_ctx_t *ctx, iis2iclx_reg_access_t val);
-int32_t iis2iclx_mem_bank_get(stmdev_ctx_t *ctx, iis2iclx_reg_access_t *val);
+int32_t iis2iclx_mem_bank_set(stmdev_ctx_t *ctx,
+ iis2iclx_reg_access_t val);
+int32_t iis2iclx_mem_bank_get(stmdev_ctx_t *ctx,
+ iis2iclx_reg_access_t *val);
int32_t iis2iclx_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address,
- uint8_t *val);
+ uint8_t *val);
int32_t iis2iclx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address,
- uint8_t *buf, uint8_t len);
+ uint8_t *buf, uint8_t len);
int32_t iis2iclx_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add,
- uint8_t *val);
-int32_t iis2iclx_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *val);
+ uint8_t *val);
+int32_t iis2iclx_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_DRDY_LATCHED = 0,
IIS2ICLX_DRDY_PULSED = 1,
} iis2iclx_dataready_pulsed_t;
int32_t iis2iclx_data_ready_mode_set(stmdev_ctx_t *ctx,
- iis2iclx_dataready_pulsed_t val);
+ iis2iclx_dataready_pulsed_t val);
int32_t iis2iclx_data_ready_mode_get(stmdev_ctx_t *ctx,
- iis2iclx_dataready_pulsed_t *val);
+ iis2iclx_dataready_pulsed_t *val);
int32_t iis2iclx_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
@@ -2474,21 +2629,27 @@ int32_t iis2iclx_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t iis2iclx_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2iclx_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_XL_ST_DISABLE = 0,
IIS2ICLX_XL_ST_POSITIVE = 1,
IIS2ICLX_XL_ST_NEGATIVE = 2,
} iis2iclx_st_xl_t;
-int32_t iis2iclx_xl_self_test_set(stmdev_ctx_t *ctx, iis2iclx_st_xl_t val);
-int32_t iis2iclx_xl_self_test_get(stmdev_ctx_t *ctx, iis2iclx_st_xl_t *val);
+int32_t iis2iclx_xl_self_test_set(stmdev_ctx_t *ctx,
+ iis2iclx_st_xl_t val);
+int32_t iis2iclx_xl_self_test_get(stmdev_ctx_t *ctx,
+ iis2iclx_st_xl_t *val);
int32_t iis2iclx_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2iclx_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t iis2iclx_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis2iclx_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis2iclx_filter_settling_mask_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t iis2iclx_filter_settling_mask_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_HP_PATH_DISABLE_ON_OUT = 0x00,
IIS2ICLX_SLOPE_ODR_DIV_4 = 0x10,
IIS2ICLX_HP_ODR_DIV_10 = 0x11,
@@ -2514,59 +2675,68 @@ typedef enum {
IIS2ICLX_LP_ODR_DIV_800 = 0x07,
} iis2iclx_hp_slope_xl_en_t;
int32_t iis2iclx_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
- iis2iclx_hp_slope_xl_en_t val);
+ iis2iclx_hp_slope_xl_en_t val);
int32_t iis2iclx_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
- iis2iclx_hp_slope_xl_en_t *val);
+ iis2iclx_hp_slope_xl_en_t *val);
int32_t iis2iclx_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis2iclx_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis2iclx_xl_fast_settling_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_USE_SLOPE = 0,
IIS2ICLX_USE_HPF = 1,
} iis2iclx_slope_fds_t;
int32_t iis2iclx_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
- iis2iclx_slope_fds_t val);
+ iis2iclx_slope_fds_t val);
int32_t iis2iclx_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
- iis2iclx_slope_fds_t *val);
+ iis2iclx_slope_fds_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_PULL_UP_DISC = 0,
IIS2ICLX_PULL_UP_CONNECT = 1,
} iis2iclx_sdo_pu_en_t;
-int32_t iis2iclx_sdo_sa0_mode_set(stmdev_ctx_t *ctx, iis2iclx_sdo_pu_en_t val);
-int32_t iis2iclx_sdo_sa0_mode_get(stmdev_ctx_t *ctx, iis2iclx_sdo_pu_en_t *val);
+int32_t iis2iclx_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
+ iis2iclx_sdo_pu_en_t val);
+int32_t iis2iclx_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
+ iis2iclx_sdo_pu_en_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_SPI_4_WIRE = 0,
IIS2ICLX_SPI_3_WIRE = 1,
} iis2iclx_sim_t;
int32_t iis2iclx_spi_mode_set(stmdev_ctx_t *ctx, iis2iclx_sim_t val);
int32_t iis2iclx_spi_mode_get(stmdev_ctx_t *ctx, iis2iclx_sim_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_I2C_ENABLE = 0,
IIS2ICLX_I2C_DISABLE = 1,
} iis2iclx_i2c_disable_t;
int32_t iis2iclx_i2c_interface_set(stmdev_ctx_t *ctx,
- iis2iclx_i2c_disable_t val);
+ iis2iclx_i2c_disable_t val);
int32_t iis2iclx_i2c_interface_get(stmdev_ctx_t *ctx,
- iis2iclx_i2c_disable_t *val);
-
-typedef struct {
- iis2iclx_int1_ctrl_t int1_ctrl;
- iis2iclx_md1_cfg_t md1_cfg;
- iis2iclx_emb_func_int1_t emb_func_int1;
- iis2iclx_fsm_int1_a_t fsm_int1_a;
- iis2iclx_fsm_int1_b_t fsm_int1_b;
- iis2iclx_mlc_int1_t mlc_int1;
+ iis2iclx_i2c_disable_t *val);
+
+typedef struct
+{
+ iis2iclx_int1_ctrl_t int1_ctrl;
+ iis2iclx_md1_cfg_t md1_cfg;
+ iis2iclx_emb_func_int1_t emb_func_int1;
+ iis2iclx_fsm_int1_a_t fsm_int1_a;
+ iis2iclx_fsm_int1_b_t fsm_int1_b;
+ iis2iclx_mlc_int1_t mlc_int1;
} iis2iclx_pin_int1_route_t;
int32_t iis2iclx_pin_int1_route_set(stmdev_ctx_t *ctx,
- iis2iclx_pin_int1_route_t *val);
+ iis2iclx_pin_int1_route_t *val);
int32_t iis2iclx_pin_int1_route_get(stmdev_ctx_t *ctx,
- iis2iclx_pin_int1_route_t *val);
+ iis2iclx_pin_int1_route_t *val);
-typedef struct {
+typedef struct
+{
iis2iclx_int2_ctrl_t int2_ctrl;
iis2iclx_md2_cfg_t md2_cfg;
iis2iclx_emb_func_int2_t emb_func_int2;
@@ -2575,85 +2745,101 @@ typedef struct {
iis2iclx_mlc_int2_t mlc_int2;
} iis2iclx_pin_int2_route_t;
int32_t iis2iclx_pin_int2_route_set(stmdev_ctx_t *ctx,
- iis2iclx_pin_int2_route_t *val);
+ iis2iclx_pin_int2_route_t *val);
int32_t iis2iclx_pin_int2_route_get(stmdev_ctx_t *ctx,
- iis2iclx_pin_int2_route_t *val);
+ iis2iclx_pin_int2_route_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_PUSH_PULL = 0,
IIS2ICLX_OPEN_DRAIN = 1,
} iis2iclx_pp_od_t;
-int32_t iis2iclx_pin_mode_set(stmdev_ctx_t *ctx, iis2iclx_pp_od_t val);
-int32_t iis2iclx_pin_mode_get(stmdev_ctx_t *ctx, iis2iclx_pp_od_t *val);
+int32_t iis2iclx_pin_mode_set(stmdev_ctx_t *ctx,
+ iis2iclx_pp_od_t val);
+int32_t iis2iclx_pin_mode_get(stmdev_ctx_t *ctx,
+ iis2iclx_pp_od_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_ACTIVE_HIGH = 0,
IIS2ICLX_ACTIVE_LOW = 1,
} iis2iclx_h_lactive_t;
-int32_t iis2iclx_pin_polarity_set(stmdev_ctx_t *ctx, iis2iclx_h_lactive_t val);
-int32_t iis2iclx_pin_polarity_get(stmdev_ctx_t *ctx, iis2iclx_h_lactive_t *val);
+int32_t iis2iclx_pin_polarity_set(stmdev_ctx_t *ctx,
+ iis2iclx_h_lactive_t val);
+int32_t iis2iclx_pin_polarity_get(stmdev_ctx_t *ctx,
+ iis2iclx_h_lactive_t *val);
int32_t iis2iclx_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2iclx_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_ALL_INT_PULSED = 0,
IIS2ICLX_BASE_LATCHED_EMB_PULSED = 1,
IIS2ICLX_BASE_PULSED_EMB_LATCHED = 2,
IIS2ICLX_ALL_INT_LATCHED = 3,
} iis2iclx_lir_t;
-int32_t iis2iclx_int_notification_set(stmdev_ctx_t *ctx, iis2iclx_lir_t val);
-int32_t iis2iclx_int_notification_get(stmdev_ctx_t *ctx, iis2iclx_lir_t *val);
+int32_t iis2iclx_int_notification_set(stmdev_ctx_t *ctx,
+ iis2iclx_lir_t val);
+int32_t iis2iclx_int_notification_get(stmdev_ctx_t *ctx,
+ iis2iclx_lir_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_LSb_FS_DIV_64 = 0,
IIS2ICLX_LSb_FS_DIV_256 = 1,
} iis2iclx_wake_ths_w_t;
int32_t iis2iclx_wkup_ths_weight_set(stmdev_ctx_t *ctx,
- iis2iclx_wake_ths_w_t val);
+ iis2iclx_wake_ths_w_t val);
int32_t iis2iclx_wkup_ths_weight_get(stmdev_ctx_t *ctx,
- iis2iclx_wake_ths_w_t *val);
+ iis2iclx_wake_ths_w_t *val);
int32_t iis2iclx_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2iclx_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t iis2iclx_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx,
- uint8_t val);
+ uint8_t val);
int32_t iis2iclx_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx,
- uint8_t *val);
+ uint8_t *val);
int32_t iis2iclx_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2iclx_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_DRIVE_SLEEP_CHG_EVENT = 0,
IIS2ICLX_DRIVE_SLEEP_STATUS = 1,
} iis2iclx_sleep_status_on_int_t;
int32_t iis2iclx_act_pin_notification_set(stmdev_ctx_t *ctx,
- iis2iclx_sleep_status_on_int_t val);
+ iis2iclx_sleep_status_on_int_t val);
int32_t iis2iclx_act_pin_notification_get(stmdev_ctx_t *ctx,
- iis2iclx_sleep_status_on_int_t *val);
+ iis2iclx_sleep_status_on_int_t *val);
int32_t iis2iclx_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2iclx_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t iis2iclx_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis2iclx_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis2iclx_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t iis2iclx_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t iis2iclx_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis2iclx_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis2iclx_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t iis2iclx_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t iis2iclx_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2iclx_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_XY = 0,
IIS2ICLX_YX = 1,
} iis2iclx_tap_priority_t;
int32_t iis2iclx_tap_axis_priority_set(stmdev_ctx_t *ctx,
- iis2iclx_tap_priority_t val);
+ iis2iclx_tap_priority_t val);
int32_t iis2iclx_tap_axis_priority_get(stmdev_ctx_t *ctx,
- iis2iclx_tap_priority_t *val);
+ iis2iclx_tap_priority_t *val);
int32_t iis2iclx_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2iclx_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -2667,28 +2853,32 @@ int32_t iis2iclx_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t iis2iclx_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2iclx_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_ONLY_SINGLE = 0,
IIS2ICLX_BOTH_SINGLE_DOUBLE = 1,
} iis2iclx_single_double_tap_t;
int32_t iis2iclx_tap_mode_set(stmdev_ctx_t *ctx,
- iis2iclx_single_double_tap_t val);
+ iis2iclx_single_double_tap_t val);
int32_t iis2iclx_tap_mode_get(stmdev_ctx_t *ctx,
- iis2iclx_single_double_tap_t *val);
+ iis2iclx_single_double_tap_t *val);
int32_t iis2iclx_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val);
int32_t iis2iclx_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val);
int32_t iis2iclx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
- uint8_t val);
+ uint8_t val);
int32_t iis2iclx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
- uint8_t *val);
+ uint8_t *val);
int32_t iis2iclx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis2iclx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis2iclx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
- IIS2ICLX_XL_NOT_BATCHED = 0,
+typedef enum
+{
+ IIS2ICLX_XL_NOT_BATCHED = 0,
+ IIS2ICLX_XL_BATCHED_AT_1Hz6 = 11,
IIS2ICLX_XL_BATCHED_AT_12Hz5 = 1,
IIS2ICLX_XL_BATCHED_AT_26Hz = 2,
IIS2ICLX_XL_BATCHED_AT_52Hz = 3,
@@ -2697,10 +2887,13 @@ typedef enum {
IIS2ICLX_XL_BATCHED_AT_417Hz = 6,
IIS2ICLX_XL_BATCHED_AT_833Hz = 7,
} iis2iclx_bdr_xl_t;
-int32_t iis2iclx_fifo_xl_batch_set(stmdev_ctx_t *ctx, iis2iclx_bdr_xl_t val);
-int32_t iis2iclx_fifo_xl_batch_get(stmdev_ctx_t *ctx, iis2iclx_bdr_xl_t *val);
+int32_t iis2iclx_fifo_xl_batch_set(stmdev_ctx_t *ctx,
+ iis2iclx_bdr_xl_t val);
+int32_t iis2iclx_fifo_xl_batch_get(stmdev_ctx_t *ctx,
+ iis2iclx_bdr_xl_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_BYPASS_MODE = 0,
IIS2ICLX_FIFO_MODE = 1,
IIS2ICLX_STREAM_TO_FIFO_MODE = 3,
@@ -2708,42 +2901,50 @@ typedef enum {
IIS2ICLX_STREAM_MODE = 6,
IIS2ICLX_BYPASS_TO_FIFO_MODE = 7,
} iis2iclx_fifo_mode_t;
-int32_t iis2iclx_fifo_mode_set(stmdev_ctx_t *ctx, iis2iclx_fifo_mode_t val);
-int32_t iis2iclx_fifo_mode_get(stmdev_ctx_t *ctx, iis2iclx_fifo_mode_t *val);
+int32_t iis2iclx_fifo_mode_set(stmdev_ctx_t *ctx,
+ iis2iclx_fifo_mode_t val);
+int32_t iis2iclx_fifo_mode_get(stmdev_ctx_t *ctx,
+ iis2iclx_fifo_mode_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_TEMP_NOT_BATCHED = 0,
+ IIS2ICLX_TEMP_BATCHED_AT_1Hz6 = 1,
IIS2ICLX_TEMP_BATCHED_AT_12Hz5 = 2,
IIS2ICLX_TEMP_BATCHED_AT_52Hz = 3,
} iis2iclx_odr_t_batch_t;
int32_t iis2iclx_fifo_temp_batch_set(stmdev_ctx_t *ctx,
- iis2iclx_odr_t_batch_t val);
+ iis2iclx_odr_t_batch_t val);
int32_t iis2iclx_fifo_temp_batch_get(stmdev_ctx_t *ctx,
- iis2iclx_odr_t_batch_t *val);
+ iis2iclx_odr_t_batch_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_NO_DECIMATION = 0,
IIS2ICLX_DEC_1 = 1,
IIS2ICLX_DEC_8 = 2,
IIS2ICLX_DEC_32 = 3,
} iis2iclx_odr_ts_batch_t;
int32_t iis2iclx_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
- iis2iclx_odr_ts_batch_t val);
+ iis2iclx_odr_ts_batch_t val);
int32_t iis2iclx_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
- iis2iclx_odr_ts_batch_t *val);
+ iis2iclx_odr_ts_batch_t *val);
-int32_t iis2iclx_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis2iclx_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis2iclx_rst_batch_counter_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t iis2iclx_rst_batch_counter_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t iis2iclx_batch_counter_threshold_set(stmdev_ctx_t *ctx,
- uint16_t val);
+ uint16_t val);
int32_t iis2iclx_batch_counter_threshold_get(stmdev_ctx_t *ctx,
- uint16_t *val);
+ uint16_t *val);
-int32_t iis2iclx_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t iis2iclx_fifo_data_level_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
int32_t iis2iclx_fifo_status_get(stmdev_ctx_t *ctx,
- iis2iclx_fifo_status2_t *val);
+ iis2iclx_fifo_status2_t *val);
int32_t iis2iclx_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -2751,7 +2952,8 @@ int32_t iis2iclx_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t iis2iclx_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_XL_NC_TAG = 2,
IIS2ICLX_TEMPERATURE_TAG,
IIS2ICLX_TIMESTAMP_TAG,
@@ -2763,21 +2965,26 @@ typedef enum {
IIS2ICLX_SENSORHUB_NACK_TAG = 0x19,
} iis2iclx_fifo_tag_t;
int32_t iis2iclx_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
- iis2iclx_fifo_tag_t *val);
+ iis2iclx_fifo_tag_t *val);
int32_t iis2iclx_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis2iclx_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis2iclx_sh_batch_slave_0_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t iis2iclx_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis2iclx_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis2iclx_sh_batch_slave_1_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t iis2iclx_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis2iclx_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis2iclx_sh_batch_slave_2_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t iis2iclx_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis2iclx_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis2iclx_sh_batch_slave_3_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_DEN_DISABLE = 0x00,
IIS2ICLX_LEVEL_FIFO = 0x76,
IIS2ICLX_LEVEL_LETCHED = 0x73,
@@ -2785,18 +2992,19 @@ typedef enum {
IIS2ICLX_EDGE_TRIGGER = 0x74,
} iis2iclx_den_mode_t;
int32_t iis2iclx_den_mode_set(stmdev_ctx_t *ctx,
- iis2iclx_den_mode_t val);
+ iis2iclx_den_mode_t val);
int32_t iis2iclx_den_mode_get(stmdev_ctx_t *ctx,
- iis2iclx_den_mode_t *val);
+ iis2iclx_den_mode_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_DEN_ACT_LOW = 0,
IIS2ICLX_DEN_ACT_HIGH = 1,
} iis2iclx_den_lh_t;
int32_t iis2iclx_den_polarity_set(stmdev_ctx_t *ctx,
- iis2iclx_den_lh_t val);
+ iis2iclx_den_lh_t val);
int32_t iis2iclx_den_polarity_get(stmdev_ctx_t *ctx,
- iis2iclx_den_lh_t *val);
+ iis2iclx_den_lh_t *val);
int32_t iis2iclx_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2iclx_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -2805,75 +3013,86 @@ int32_t iis2iclx_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2iclx_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t iis2iclx_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
- uint8_t *val);
+ uint8_t *val);
int32_t iis2iclx_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2iclx_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef struct {
- iis2iclx_fsm_enable_a_t fsm_enable_a;
- iis2iclx_fsm_enable_b_t fsm_enable_b;
+typedef struct
+{
+ iis2iclx_fsm_enable_a_t fsm_enable_a;
+ iis2iclx_fsm_enable_b_t fsm_enable_b;
} iis2iclx_emb_fsm_enable_t;
int32_t iis2iclx_fsm_enable_set(stmdev_ctx_t *ctx,
- iis2iclx_emb_fsm_enable_t *val);
+ iis2iclx_emb_fsm_enable_t *val);
int32_t iis2iclx_fsm_enable_get(stmdev_ctx_t *ctx,
- iis2iclx_emb_fsm_enable_t *val);
+ iis2iclx_emb_fsm_enable_t *val);
int32_t iis2iclx_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val);
int32_t iis2iclx_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_LC_NORMAL = 0,
IIS2ICLX_LC_CLEAR = 1,
IIS2ICLX_LC_CLEAR_DONE = 2,
} iis2iclx_fsm_lc_clr_t;
int32_t iis2iclx_long_clr_set(stmdev_ctx_t *ctx,
- iis2iclx_fsm_lc_clr_t val);
+ iis2iclx_fsm_lc_clr_t val);
int32_t iis2iclx_long_clr_get(stmdev_ctx_t *ctx,
- iis2iclx_fsm_lc_clr_t *val);
-
-typedef struct {
- iis2iclx_fsm_outs1_t fsm_outs1;
- iis2iclx_fsm_outs2_t fsm_outs2;
- iis2iclx_fsm_outs3_t fsm_outs3;
- iis2iclx_fsm_outs4_t fsm_outs4;
- iis2iclx_fsm_outs5_t fsm_outs5;
- iis2iclx_fsm_outs6_t fsm_outs6;
- iis2iclx_fsm_outs7_t fsm_outs7;
- iis2iclx_fsm_outs8_t fsm_outs8;
- iis2iclx_fsm_outs9_t fsm_outs9;
- iis2iclx_fsm_outs10_t fsm_outs10;
- iis2iclx_fsm_outs11_t fsm_outs11;
- iis2iclx_fsm_outs12_t fsm_outs12;
- iis2iclx_fsm_outs13_t fsm_outs13;
- iis2iclx_fsm_outs14_t fsm_outs14;
- iis2iclx_fsm_outs15_t fsm_outs15;
- iis2iclx_fsm_outs16_t fsm_outs16;
+ iis2iclx_fsm_lc_clr_t *val);
+
+typedef struct
+{
+ iis2iclx_fsm_outs1_t fsm_outs1;
+ iis2iclx_fsm_outs2_t fsm_outs2;
+ iis2iclx_fsm_outs3_t fsm_outs3;
+ iis2iclx_fsm_outs4_t fsm_outs4;
+ iis2iclx_fsm_outs5_t fsm_outs5;
+ iis2iclx_fsm_outs6_t fsm_outs6;
+ iis2iclx_fsm_outs7_t fsm_outs7;
+ iis2iclx_fsm_outs8_t fsm_outs8;
+ iis2iclx_fsm_outs9_t fsm_outs9;
+ iis2iclx_fsm_outs10_t fsm_outs10;
+ iis2iclx_fsm_outs11_t fsm_outs11;
+ iis2iclx_fsm_outs12_t fsm_outs12;
+ iis2iclx_fsm_outs13_t fsm_outs13;
+ iis2iclx_fsm_outs14_t fsm_outs14;
+ iis2iclx_fsm_outs15_t fsm_outs15;
+ iis2iclx_fsm_outs16_t fsm_outs16;
} iis2iclx_fsm_out_t;
-int32_t iis2iclx_fsm_out_get(stmdev_ctx_t *ctx, iis2iclx_fsm_out_t *val);
+int32_t iis2iclx_fsm_out_get(stmdev_ctx_t *ctx,
+ iis2iclx_fsm_out_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_ODR_FSM_12Hz5 = 0,
IIS2ICLX_ODR_FSM_26Hz = 1,
IIS2ICLX_ODR_FSM_52Hz = 2,
IIS2ICLX_ODR_FSM_104Hz = 3,
} iis2iclx_fsm_odr_t;
int32_t iis2iclx_fsm_data_rate_set(stmdev_ctx_t *ctx,
- iis2iclx_fsm_odr_t val);
+ iis2iclx_fsm_odr_t val);
int32_t iis2iclx_fsm_data_rate_get(stmdev_ctx_t *ctx,
- iis2iclx_fsm_odr_t *val);
+ iis2iclx_fsm_odr_t *val);
int32_t iis2iclx_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2iclx_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t iis2iclx_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint16_t val);
-int32_t iis2iclx_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t iis2iclx_long_cnt_int_value_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t iis2iclx_long_cnt_int_value_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
-int32_t iis2iclx_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t iis2iclx_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t iis2iclx_fsm_number_of_programs_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t iis2iclx_fsm_number_of_programs_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
-int32_t iis2iclx_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val);
-int32_t iis2iclx_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t iis2iclx_fsm_start_address_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t iis2iclx_fsm_start_address_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
int32_t iis2iclx_mlc_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2iclx_mlc_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -2881,132 +3100,144 @@ int32_t iis2iclx_mlc_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t iis2iclx_mlc_status_get(stmdev_ctx_t *ctx,
iis2iclx_mlc_status_mainpage_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_ODR_PRGS_12Hz5 = 0,
IIS2ICLX_ODR_PRGS_26Hz = 1,
IIS2ICLX_ODR_PRGS_52Hz = 2,
IIS2ICLX_ODR_PRGS_104Hz = 3,
} iis2iclx_mlc_odr_t;
int32_t iis2iclx_mlc_data_rate_set(stmdev_ctx_t *ctx,
- iis2iclx_mlc_odr_t val);
+ iis2iclx_mlc_odr_t val);
int32_t iis2iclx_mlc_data_rate_get(stmdev_ctx_t *ctx,
iis2iclx_mlc_odr_t *val);
int32_t iis2iclx_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff);
-typedef struct {
- iis2iclx_sensor_hub_1_t sh_byte_1;
- iis2iclx_sensor_hub_2_t sh_byte_2;
- iis2iclx_sensor_hub_3_t sh_byte_3;
- iis2iclx_sensor_hub_4_t sh_byte_4;
- iis2iclx_sensor_hub_5_t sh_byte_5;
- iis2iclx_sensor_hub_6_t sh_byte_6;
- iis2iclx_sensor_hub_7_t sh_byte_7;
- iis2iclx_sensor_hub_8_t sh_byte_8;
- iis2iclx_sensor_hub_9_t sh_byte_9;
- iis2iclx_sensor_hub_10_t sh_byte_10;
- iis2iclx_sensor_hub_11_t sh_byte_11;
- iis2iclx_sensor_hub_12_t sh_byte_12;
- iis2iclx_sensor_hub_13_t sh_byte_13;
- iis2iclx_sensor_hub_14_t sh_byte_14;
- iis2iclx_sensor_hub_15_t sh_byte_15;
- iis2iclx_sensor_hub_16_t sh_byte_16;
- iis2iclx_sensor_hub_17_t sh_byte_17;
- iis2iclx_sensor_hub_18_t sh_byte_18;
+typedef struct
+{
+ iis2iclx_sensor_hub_1_t sh_byte_1;
+ iis2iclx_sensor_hub_2_t sh_byte_2;
+ iis2iclx_sensor_hub_3_t sh_byte_3;
+ iis2iclx_sensor_hub_4_t sh_byte_4;
+ iis2iclx_sensor_hub_5_t sh_byte_5;
+ iis2iclx_sensor_hub_6_t sh_byte_6;
+ iis2iclx_sensor_hub_7_t sh_byte_7;
+ iis2iclx_sensor_hub_8_t sh_byte_8;
+ iis2iclx_sensor_hub_9_t sh_byte_9;
+ iis2iclx_sensor_hub_10_t sh_byte_10;
+ iis2iclx_sensor_hub_11_t sh_byte_11;
+ iis2iclx_sensor_hub_12_t sh_byte_12;
+ iis2iclx_sensor_hub_13_t sh_byte_13;
+ iis2iclx_sensor_hub_14_t sh_byte_14;
+ iis2iclx_sensor_hub_15_t sh_byte_15;
+ iis2iclx_sensor_hub_16_t sh_byte_16;
+ iis2iclx_sensor_hub_17_t sh_byte_17;
+ iis2iclx_sensor_hub_18_t sh_byte_18;
} iis2iclx_emb_sh_read_t;
int32_t iis2iclx_sh_read_data_raw_get(stmdev_ctx_t *ctx,
- iis2iclx_emb_sh_read_t *val);
+ iis2iclx_emb_sh_read_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_SLV_0 = 0,
IIS2ICLX_SLV_0_1 = 1,
IIS2ICLX_SLV_0_1_2 = 2,
IIS2ICLX_SLV_0_1_2_3 = 3,
} iis2iclx_aux_sens_on_t;
int32_t iis2iclx_sh_slave_connected_set(stmdev_ctx_t *ctx,
- iis2iclx_aux_sens_on_t val);
+ iis2iclx_aux_sens_on_t val);
int32_t iis2iclx_sh_slave_connected_get(stmdev_ctx_t *ctx,
- iis2iclx_aux_sens_on_t *val);
+ iis2iclx_aux_sens_on_t *val);
int32_t iis2iclx_sh_master_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2iclx_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_EXT_PULL_UP = 0,
IIS2ICLX_INTERNAL_PULL_UP = 1,
} iis2iclx_shub_pu_en_t;
int32_t iis2iclx_sh_pin_mode_set(stmdev_ctx_t *ctx,
- iis2iclx_shub_pu_en_t val);
+ iis2iclx_shub_pu_en_t val);
int32_t iis2iclx_sh_pin_mode_get(stmdev_ctx_t *ctx,
- iis2iclx_shub_pu_en_t *val);
+ iis2iclx_shub_pu_en_t *val);
int32_t iis2iclx_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2iclx_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
- IIS2ICLX_EXT_ON_INT2_PIN = 0,
- IIS2ICLX_XL_GY_DRDY = 1,
+typedef enum
+{
+ IIS2ICLX_EXT_ON_INT2_PIN = 1,
+ IIS2ICLX_XL_GY_DRDY = 0,
} iis2iclx_start_config_t;
int32_t iis2iclx_sh_syncro_mode_set(stmdev_ctx_t *ctx,
- iis2iclx_start_config_t val);
+ iis2iclx_start_config_t val);
int32_t iis2iclx_sh_syncro_mode_get(stmdev_ctx_t *ctx,
- iis2iclx_start_config_t *val);
+ iis2iclx_start_config_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_EACH_SH_CYCLE = 0,
IIS2ICLX_ONLY_FIRST_CYCLE = 1,
} iis2iclx_write_once_t;
int32_t iis2iclx_sh_write_mode_set(stmdev_ctx_t *ctx,
- iis2iclx_write_once_t val);
+ iis2iclx_write_once_t val);
int32_t iis2iclx_sh_write_mode_get(stmdev_ctx_t *ctx,
- iis2iclx_write_once_t *val);
+ iis2iclx_write_once_t *val);
int32_t iis2iclx_sh_reset_set(stmdev_ctx_t *ctx);
int32_t iis2iclx_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_SH_ODR_104Hz = 0,
IIS2ICLX_SH_ODR_52Hz = 1,
IIS2ICLX_SH_ODR_26Hz = 2,
IIS2ICLX_SH_ODR_13Hz = 3,
} iis2iclx_shub_odr_t;
int32_t iis2iclx_sh_data_rate_set(stmdev_ctx_t *ctx,
- iis2iclx_shub_odr_t val);
+ iis2iclx_shub_odr_t val);
int32_t iis2iclx_sh_data_rate_get(stmdev_ctx_t *ctx,
- iis2iclx_shub_odr_t *val);
+ iis2iclx_shub_odr_t *val);
-typedef struct{
+typedef struct
+{
uint8_t slv0_add;
uint8_t slv0_subadd;
uint8_t slv0_data;
} iis2iclx_sh_cfg_write_t;
int32_t iis2iclx_sh_cfg_write(stmdev_ctx_t *ctx,
- iis2iclx_sh_cfg_write_t *val);
+ iis2iclx_sh_cfg_write_t *val);
-typedef struct{
+typedef struct
+{
uint8_t slv_add;
uint8_t slv_subadd;
uint8_t slv_len;
} iis2iclx_sh_cfg_read_t;
int32_t iis2iclx_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
- iis2iclx_sh_cfg_read_t *val);
+ iis2iclx_sh_cfg_read_t *val);
int32_t iis2iclx_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
- iis2iclx_sh_cfg_read_t *val);
+ iis2iclx_sh_cfg_read_t *val);
int32_t iis2iclx_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
- iis2iclx_sh_cfg_read_t *val);
+ iis2iclx_sh_cfg_read_t *val);
int32_t iis2iclx_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
- iis2iclx_sh_cfg_read_t *val);
+ iis2iclx_sh_cfg_read_t *val);
int32_t iis2iclx_sh_status_get(stmdev_ctx_t *ctx,
- iis2iclx_status_master_t *val);
+ iis2iclx_status_master_t *val);
-typedef enum {
+typedef enum
+{
IIS2ICLX_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */
IIS2ICLX_SPI_4W = 0x01, /* Only SPI: SDO / SDI separated pins */
IIS2ICLX_SPI_3W = 0x03, /* Only SPI: SDO / SDI share the same pin */
} iis2iclx_bus_mode_t;
-int32_t iis2iclx_bus_mode_set(stmdev_ctx_t *ctx, iis2iclx_bus_mode_t val);
-int32_t iis2iclx_bus_mode_get(stmdev_ctx_t *ctx, iis2iclx_bus_mode_t *val);
+int32_t iis2iclx_bus_mode_set(stmdev_ctx_t *ctx,
+ iis2iclx_bus_mode_t val);
+int32_t iis2iclx_bus_mode_get(stmdev_ctx_t *ctx,
+ iis2iclx_bus_mode_t *val);
/**
*@}
diff --git a/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.c b/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.c
index 3fa901f6b026c6e986fbe24c705b5f759666e679..180dab2d4794cb0426339ce1a7b4a5c1110b80f7 100644
--- a/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.c
+++ b/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file iis2mdc_reg.c
- * @author Sensors Software Solution Team
- * @brief IIS2MDC driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file iis2mdc_reg.c
+ * @author Sensors Software Solution Team
+ * @brief IIS2MDC driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "iis2mdc_reg.h"
/**
@@ -45,11 +45,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2mdc_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t iis2mdc_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -63,11 +66,14 @@ int32_t iis2mdc_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2mdc_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t iis2mdc_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -124,15 +130,14 @@ int32_t iis2mdc_mag_user_offset_set(stmdev_ctx_t *ctx, int16_t *val)
uint8_t buff[6];
int32_t ret;
- buff[1] = (uint8_t) ((uint16_t)val[0] / 256U);
- buff[0] = (uint8_t) ((uint16_t)val[0] - (buff[1] * 256U));
- buff[3] = (uint8_t) ((uint16_t)val[1] / 256U);
- buff[2] = (uint8_t) ((uint16_t)val[1] - (buff[3] * 256U));
- buff[5] = (uint8_t) ((uint16_t)val[2] / 256U);
- buff[4] = (uint8_t) ((uint16_t)val[2] - (buff[5] * 256U));
+ buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
+ buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
+ buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
+ buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
+ buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
+ buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
ret = iis2mdc_write_reg(ctx, IIS2MDC_OFFSET_X_REG_L, buff, 6);
-
return ret;
}
@@ -173,16 +178,20 @@ int32_t iis2mdc_mag_user_offset_get(stmdev_ctx_t *ctx, int16_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2mdc_operating_mode_set(stmdev_ctx_t *ctx, iis2mdc_md_t val)
+int32_t iis2mdc_operating_mode_set(stmdev_ctx_t *ctx,
+ iis2mdc_md_t val)
{
iis2mdc_cfg_reg_a_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.md = (uint8_t)val;
- ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t*) ®, 1);
+ ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -194,26 +203,33 @@ int32_t iis2mdc_operating_mode_set(stmdev_ctx_t *ctx, iis2mdc_md_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2mdc_operating_mode_get(stmdev_ctx_t *ctx, iis2mdc_md_t *val)
+int32_t iis2mdc_operating_mode_get(stmdev_ctx_t *ctx,
+ iis2mdc_md_t *val)
{
iis2mdc_cfg_reg_a_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t*) ®, 1);
- switch (reg.md) {
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
+
+ switch (reg.md)
+ {
case IIS2MDC_CONTINUOUS_MODE:
*val = IIS2MDC_CONTINUOUS_MODE;
break;
+
case IIS2MDC_SINGLE_TRIGGER:
*val = IIS2MDC_SINGLE_TRIGGER;
break;
+
case IIS2MDC_POWER_DOWN:
*val = IIS2MDC_POWER_DOWN;
break;
+
default:
*val = IIS2MDC_CONTINUOUS_MODE;
break;
}
+
return ret;
}
@@ -230,11 +246,14 @@ int32_t iis2mdc_data_rate_set(stmdev_ctx_t *ctx, iis2mdc_odr_t val)
iis2mdc_cfg_reg_a_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.odr = (uint8_t)val;
- ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t*) ®, 1);
+ ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -251,24 +270,31 @@ int32_t iis2mdc_data_rate_get(stmdev_ctx_t *ctx, iis2mdc_odr_t *val)
iis2mdc_cfg_reg_a_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t*) ®, 1);
- switch (reg.odr) {
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
+
+ switch (reg.odr)
+ {
case IIS2MDC_ODR_10Hz:
*val = IIS2MDC_ODR_10Hz;
break;
+
case IIS2MDC_ODR_20Hz:
*val = IIS2MDC_ODR_20Hz;
break;
+
case IIS2MDC_ODR_50Hz:
*val = IIS2MDC_ODR_50Hz;
break;
+
case IIS2MDC_ODR_100Hz:
*val = IIS2MDC_ODR_100Hz;
break;
+
default:
*val = IIS2MDC_ODR_10Hz;
break;
}
+
return ret;
}
@@ -285,11 +311,14 @@ int32_t iis2mdc_power_mode_set(stmdev_ctx_t *ctx, iis2mdc_lp_t val)
iis2mdc_cfg_reg_a_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.lp = (uint8_t)val;
- ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t*) ®, 1);
+ ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -306,18 +335,23 @@ int32_t iis2mdc_power_mode_get(stmdev_ctx_t *ctx, iis2mdc_lp_t *val)
iis2mdc_cfg_reg_a_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t*) ®, 1);
- switch (reg.lp) {
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
+
+ switch (reg.lp)
+ {
case IIS2MDC_HIGH_RESOLUTION:
*val = IIS2MDC_HIGH_RESOLUTION;
break;
+
case IIS2MDC_LOW_POWER:
*val = IIS2MDC_LOW_POWER;
break;
+
default:
*val = IIS2MDC_HIGH_RESOLUTION;
break;
}
+
return ret;
}
@@ -334,11 +368,14 @@ int32_t iis2mdc_offset_temp_comp_set(stmdev_ctx_t *ctx, uint8_t val)
iis2mdc_cfg_reg_a_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.comp_temp_en = val;
- ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t*) ®, 1);
+ ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -355,7 +392,7 @@ int32_t iis2mdc_offset_temp_comp_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2mdc_cfg_reg_a_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t*) ®, 1);
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
*val = reg.comp_temp_en;
return ret;
@@ -375,11 +412,14 @@ int32_t iis2mdc_low_pass_bandwidth_set(stmdev_ctx_t *ctx,
iis2mdc_cfg_reg_b_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.lpf = (uint8_t)val;
- ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t*) ®, 1);
+ ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -397,18 +437,23 @@ int32_t iis2mdc_low_pass_bandwidth_get(stmdev_ctx_t *ctx,
iis2mdc_cfg_reg_b_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t*) ®, 1);
- switch (reg.lpf) {
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t *) ®, 1);
+
+ switch (reg.lpf)
+ {
case IIS2MDC_ODR_DIV_2:
*val = IIS2MDC_ODR_DIV_2;
break;
+
case IIS2MDC_ODR_DIV_4:
*val = IIS2MDC_ODR_DIV_4;
break;
+
default:
*val = IIS2MDC_ODR_DIV_2;
break;
}
+
return ret;
}
@@ -421,16 +466,20 @@ int32_t iis2mdc_low_pass_bandwidth_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2mdc_set_rst_mode_set(stmdev_ctx_t *ctx, iis2mdc_set_rst_t val)
+int32_t iis2mdc_set_rst_mode_set(stmdev_ctx_t *ctx,
+ iis2mdc_set_rst_t val)
{
iis2mdc_cfg_reg_b_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.set_rst = (uint8_t)val;
- ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t*) ®, 1);
+ ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -442,26 +491,33 @@ int32_t iis2mdc_set_rst_mode_set(stmdev_ctx_t *ctx, iis2mdc_set_rst_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2mdc_set_rst_mode_get(stmdev_ctx_t *ctx, iis2mdc_set_rst_t *val)
+int32_t iis2mdc_set_rst_mode_get(stmdev_ctx_t *ctx,
+ iis2mdc_set_rst_t *val)
{
iis2mdc_cfg_reg_b_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t*) ®, 1);
- switch (reg.set_rst) {
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t *) ®, 1);
+
+ switch (reg.set_rst)
+ {
case IIS2MDC_SET_SENS_ODR_DIV_63:
*val = IIS2MDC_SET_SENS_ODR_DIV_63;
break;
+
case IIS2MDC_SENS_OFF_CANC_EVERY_ODR:
*val = IIS2MDC_SENS_OFF_CANC_EVERY_ODR;
break;
+
case IIS2MDC_SET_SENS_ONLY_AT_POWER_ON:
*val = IIS2MDC_SET_SENS_ONLY_AT_POWER_ON;
break;
+
default:
*val = IIS2MDC_SET_SENS_ODR_DIV_63;
break;
}
+
return ret;
}
@@ -478,16 +534,20 @@ int32_t iis2mdc_set_rst_mode_get(stmdev_ctx_t *ctx, iis2mdc_set_rst_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2mdc_set_rst_sensor_single_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t iis2mdc_set_rst_sensor_single_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
iis2mdc_cfg_reg_b_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.off_canc_one_shot = val;
- ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t*) ®, 1);
+ ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -503,12 +563,13 @@ int32_t iis2mdc_set_rst_sensor_single_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2mdc_set_rst_sensor_single_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t iis2mdc_set_rst_sensor_single_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
iis2mdc_cfg_reg_b_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t*) ®, 1);
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t *) ®, 1);
*val = reg.off_canc_one_shot;
return ret;
@@ -527,11 +588,14 @@ int32_t iis2mdc_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
iis2mdc_cfg_reg_c_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.bdu = val;
- ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t*) ®, 1);
+ ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -548,7 +612,7 @@ int32_t iis2mdc_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2mdc_cfg_reg_c_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t*) ®, 1);
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
*val = reg.bdu;
return ret;
@@ -567,7 +631,7 @@ int32_t iis2mdc_mag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2mdc_status_reg_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_STATUS_REG, (uint8_t*) ®, 1);
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_STATUS_REG, (uint8_t *) ®, 1);
*val = reg.zyxda;
return ret;
@@ -586,7 +650,7 @@ int32_t iis2mdc_mag_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2mdc_status_reg_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_STATUS_REG, (uint8_t*) ®, 1);
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_STATUS_REG, (uint8_t *) ®, 1);
*val = reg.zyxor;
return ret;
@@ -607,11 +671,11 @@ int32_t iis2mdc_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val)
ret = iis2mdc_read_reg(ctx, IIS2MDC_OUTX_L_REG, buff, 6);
val[0] = (int16_t)buff[1];
- val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
- val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
val[2] = (int16_t)buff[5];
- val[2] = (val[2] * 256) + (int16_t)buff[4];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
return ret;
}
@@ -643,7 +707,7 @@ int32_t iis2mdc_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
/**
* @defgroup IIS2MDC_common
- * @brief This section group common usefull functions
+ * @brief This section group common useful functions
* @{
*
*/
@@ -659,7 +723,9 @@ int32_t iis2mdc_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
int32_t iis2mdc_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = iis2mdc_read_reg(ctx, IIS2MDC_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -677,11 +743,14 @@ int32_t iis2mdc_reset_set(stmdev_ctx_t *ctx, uint8_t val)
iis2mdc_cfg_reg_a_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.soft_rst = val;
- ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t*) ®, 1);
+ ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -698,7 +767,7 @@ int32_t iis2mdc_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2mdc_cfg_reg_a_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t*) ®, 1);
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
*val = reg.soft_rst;
return ret;
@@ -717,11 +786,14 @@ int32_t iis2mdc_boot_set(stmdev_ctx_t *ctx, uint8_t val)
iis2mdc_cfg_reg_a_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.reboot = val;
- ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t*) ®, 1);
+ ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -738,7 +810,7 @@ int32_t iis2mdc_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2mdc_cfg_reg_a_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t*) ®, 1);
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1);
*val = reg.reboot;
return ret;
@@ -757,11 +829,14 @@ int32_t iis2mdc_self_test_set(stmdev_ctx_t *ctx, uint8_t val)
iis2mdc_cfg_reg_c_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.self_test = val;
- ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t*) ®, 1);
+ ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -778,7 +853,7 @@ int32_t iis2mdc_self_test_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2mdc_cfg_reg_c_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t*) ®, 1);
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
*val = reg.self_test;
return ret;
@@ -797,11 +872,14 @@ int32_t iis2mdc_data_format_set(stmdev_ctx_t *ctx, iis2mdc_ble_t val)
iis2mdc_cfg_reg_c_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.ble = (uint8_t)val;
- ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t*) ®, 1);
+ ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -818,18 +896,23 @@ int32_t iis2mdc_data_format_get(stmdev_ctx_t *ctx, iis2mdc_ble_t *val)
iis2mdc_cfg_reg_c_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t*) ®, 1);
- switch (reg.ble) {
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
+
+ switch (reg.ble)
+ {
case IIS2MDC_LSB_AT_LOW_ADD:
*val = IIS2MDC_LSB_AT_LOW_ADD;
break;
+
case IIS2MDC_MSB_AT_LOW_ADD:
*val = IIS2MDC_MSB_AT_LOW_ADD;
break;
+
default:
*val = IIS2MDC_LSB_AT_LOW_ADD;
break;
}
+
return ret;
}
@@ -841,10 +924,13 @@ int32_t iis2mdc_data_format_get(stmdev_ctx_t *ctx, iis2mdc_ble_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2mdc_status_get(stmdev_ctx_t *ctx, iis2mdc_status_reg_t *val)
+int32_t iis2mdc_status_get(stmdev_ctx_t *ctx,
+ iis2mdc_status_reg_t *val)
{
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_STATUS_REG, (uint8_t*) val, 1);
+
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_STATUS_REG, (uint8_t *) val, 1);
+
return ret;
}
@@ -877,11 +963,14 @@ int32_t iis2mdc_offset_int_conf_set(stmdev_ctx_t *ctx,
iis2mdc_cfg_reg_b_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.int_on_dataoff = (uint8_t)val;
- ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t*) ®, 1);
+ ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -901,18 +990,23 @@ int32_t iis2mdc_offset_int_conf_get(stmdev_ctx_t *ctx,
iis2mdc_cfg_reg_b_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t*) ®, 1);
- switch (reg.int_on_dataoff) {
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t *) ®, 1);
+
+ switch (reg.int_on_dataoff)
+ {
case IIS2MDC_CHECK_BEFORE:
*val = IIS2MDC_CHECK_BEFORE;
break;
+
case IIS2MDC_CHECK_AFTER:
*val = IIS2MDC_CHECK_AFTER;
break;
+
default:
*val = IIS2MDC_CHECK_BEFORE;
break;
}
+
return ret;
}
@@ -929,11 +1023,14 @@ int32_t iis2mdc_drdy_on_pin_set(stmdev_ctx_t *ctx, uint8_t val)
iis2mdc_cfg_reg_c_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.drdy_on_pin = val;
- ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t*) ®, 1);
+ ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -950,7 +1047,7 @@ int32_t iis2mdc_drdy_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2mdc_cfg_reg_c_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t*) ®, 1);
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
*val = reg.drdy_on_pin;
return ret;
@@ -969,11 +1066,14 @@ int32_t iis2mdc_int_on_pin_set(stmdev_ctx_t *ctx, uint8_t val)
iis2mdc_cfg_reg_c_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.int_on_pin = val;
- ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t*) ®, 1);
+ ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -990,7 +1090,7 @@ int32_t iis2mdc_int_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val)
iis2mdc_cfg_reg_c_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t*) ®, 1);
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
*val = reg.int_on_pin;
return ret;
@@ -1008,7 +1108,9 @@ int32_t iis2mdc_int_gen_conf_set(stmdev_ctx_t *ctx,
iis2mdc_int_crtl_reg_t *val)
{
int32_t ret;
- ret = iis2mdc_write_reg(ctx, IIS2MDC_INT_CRTL_REG, (uint8_t*) val, 1);
+
+ ret = iis2mdc_write_reg(ctx, IIS2MDC_INT_CRTL_REG, (uint8_t *) val, 1);
+
return ret;
}
@@ -1024,7 +1126,9 @@ int32_t iis2mdc_int_gen_conf_get(stmdev_ctx_t *ctx,
iis2mdc_int_crtl_reg_t *val)
{
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_INT_CRTL_REG, (uint8_t*) val, 1);
+
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_INT_CRTL_REG, (uint8_t *) val, 1);
+
return ret;
}
@@ -1040,7 +1144,9 @@ int32_t iis2mdc_int_gen_source_get(stmdev_ctx_t *ctx,
iis2mdc_int_source_reg_t *val)
{
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_INT_SOURCE_REG, (uint8_t*) val, 1);
+
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_INT_SOURCE_REG, (uint8_t *) val, 1);
+
return ret;
}
@@ -1059,8 +1165,8 @@ int32_t iis2mdc_int_gen_treshold_set(stmdev_ctx_t *ctx, int16_t val)
uint8_t buff[2];
int32_t ret;
- buff[1] = (uint8_t) ((uint16_t)val / 256U);
- buff[0] = (uint8_t) ((uint16_t)val - (buff[1] * 256U));
+ buff[1] = (uint8_t)((uint16_t)val / 256U);
+ buff[0] = (uint8_t)((uint16_t)val - (buff[1] * 256U));
ret = iis2mdc_write_reg(ctx, IIS2MDC_INT_THS_L_REG, buff, 2);
return ret;
@@ -1083,7 +1189,7 @@ int32_t iis2mdc_int_gen_treshold_get(stmdev_ctx_t *ctx, int16_t *val)
ret = iis2mdc_read_reg(ctx, IIS2MDC_INT_THS_L_REG, buff, 2);
*val = (int16_t)buff[1];
- *val = (*val * 256) + (int16_t)buff[0];
+ *val = (*val * 256) + (int16_t)buff[0];
return ret;
}
@@ -1109,16 +1215,20 @@ int32_t iis2mdc_int_gen_treshold_get(stmdev_ctx_t *ctx, int16_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2mdc_i2c_interface_set(stmdev_ctx_t *ctx, iis2mdc_i2c_dis_t val)
+int32_t iis2mdc_i2c_interface_set(stmdev_ctx_t *ctx,
+ iis2mdc_i2c_dis_t val)
{
iis2mdc_cfg_reg_c_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.i2c_dis = (uint8_t)val;
- ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t*) ®, 1);
+ ret = iis2mdc_write_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1130,23 +1240,29 @@ int32_t iis2mdc_i2c_interface_set(stmdev_ctx_t *ctx, iis2mdc_i2c_dis_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis2mdc_i2c_interface_get(stmdev_ctx_t *ctx, iis2mdc_i2c_dis_t *val)
+int32_t iis2mdc_i2c_interface_get(stmdev_ctx_t *ctx,
+ iis2mdc_i2c_dis_t *val)
{
iis2mdc_cfg_reg_c_t reg;
int32_t ret;
- ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t*) ®, 1);
- switch (reg.i2c_dis) {
+ ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1);
+
+ switch (reg.i2c_dis)
+ {
case IIS2MDC_I2C_ENABLE:
*val = IIS2MDC_I2C_ENABLE;
break;
+
case IIS2MDC_I2C_DISABLE:
*val = IIS2MDC_I2C_DISABLE;
break;
+
default:
*val = IIS2MDC_I2C_ENABLE;
break;
}
+
return ret;
}
diff --git a/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.h b/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.h
index aaab3efd53a6c2c65b7948a1273037cb467a242b..b68d8f4bf14d0ecf16fc09034b6d5a045bc5a663 100644
--- a/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.h
+++ b/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file iis2mdc_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * iis2mdc_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file iis2mdc_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * iis2mdc_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef IIS2MDC_REGS_H
#define IIS2MDC_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup IIS2MDC
@@ -74,7 +75,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -107,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -131,15 +134,16 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
- * Unico / Unicleo tools available on STMicroelectronics
- * web site.
+ * You can create a sensor configuration by your own or using
+ * Unico / Unicleo tools available on STMicroelectronics
+ * web site.
*
* @{
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -180,7 +184,8 @@ typedef struct {
#define IIS2MDC_OFFSET_Z_REG_H 0x4AU
#define IIS2MDC_WHO_AM_I 0x4FU
#define IIS2MDC_CFG_REG_A 0x60U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t md : 2;
uint8_t odr : 2;
@@ -199,7 +204,8 @@ typedef struct {
} iis2mdc_cfg_reg_a_t;
#define IIS2MDC_CFG_REG_B 0x61U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lpf : 1;
uint8_t set_rst : 2; /* OFF_CANC + Set_FREQ */
@@ -216,7 +222,8 @@ typedef struct {
} iis2mdc_cfg_reg_b_t;
#define IIS2MDC_CFG_REG_C 0x62U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t drdy_on_pin : 1;
uint8_t self_test : 1;
@@ -239,7 +246,8 @@ typedef struct {
} iis2mdc_cfg_reg_c_t;
#define IIS2MDC_INT_CRTL_REG 0x63U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ien : 1;
uint8_t iel : 1;
@@ -260,7 +268,8 @@ typedef struct {
} iis2mdc_int_crtl_reg_t;
#define IIS2MDC_INT_SOURCE_REG 0x64U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t _int : 1;
uint8_t mroi : 1;
@@ -286,7 +295,8 @@ typedef struct {
#define IIS2MDC_INT_THS_L_REG 0x65U
#define IIS2MDC_INT_THS_H_REG 0x66U
#define IIS2MDC_STATUS_REG 0x67U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xda : 1;
uint8_t yda : 1;
@@ -317,7 +327,8 @@ typedef struct {
#define IIS2MDC_TEMP_OUT_L_REG 0x6EU
#define IIS2MDC_TEMP_OUT_H_REG 0x6FU
-typedef union{
+typedef union
+{
iis2mdc_cfg_reg_a_t cfg_reg_a;
iis2mdc_cfg_reg_b_t cfg_reg_b;
iis2mdc_cfg_reg_c_t cfg_reg_c;
@@ -328,9 +339,11 @@ typedef union{
uint8_t byte;
} iis2mdc_reg_t;
-int32_t iis2mdc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t iis2mdc_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t iis2mdc_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t iis2mdc_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
float_t iis2mdc_from_lsb_to_mgauss(int16_t lsb);
@@ -338,15 +351,19 @@ float_t iis2mdc_from_lsb_to_celsius(int16_t lsb);
int32_t iis2mdc_mag_user_offset_set(stmdev_ctx_t *ctx, int16_t *val);
int32_t iis2mdc_mag_user_offset_get(stmdev_ctx_t *ctx, int16_t *val);
-typedef enum {
+typedef enum
+{
IIS2MDC_CONTINUOUS_MODE = 0,
IIS2MDC_SINGLE_TRIGGER = 1,
IIS2MDC_POWER_DOWN = 2,
} iis2mdc_md_t;
-int32_t iis2mdc_operating_mode_set(stmdev_ctx_t *ctx, iis2mdc_md_t val);
-int32_t iis2mdc_operating_mode_get(stmdev_ctx_t *ctx, iis2mdc_md_t *val);
+int32_t iis2mdc_operating_mode_set(stmdev_ctx_t *ctx,
+ iis2mdc_md_t val);
+int32_t iis2mdc_operating_mode_get(stmdev_ctx_t *ctx,
+ iis2mdc_md_t *val);
-typedef enum {
+typedef enum
+{
IIS2MDC_ODR_10Hz = 0,
IIS2MDC_ODR_20Hz = 1,
IIS2MDC_ODR_50Hz = 2,
@@ -355,7 +372,8 @@ typedef enum {
int32_t iis2mdc_data_rate_set(stmdev_ctx_t *ctx, iis2mdc_odr_t val);
int32_t iis2mdc_data_rate_get(stmdev_ctx_t *ctx, iis2mdc_odr_t *val);
-typedef enum {
+typedef enum
+{
IIS2MDC_HIGH_RESOLUTION = 0,
IIS2MDC_LOW_POWER = 1,
} iis2mdc_lp_t;
@@ -365,7 +383,8 @@ int32_t iis2mdc_power_mode_get(stmdev_ctx_t *ctx, iis2mdc_lp_t *val);
int32_t iis2mdc_offset_temp_comp_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2mdc_offset_temp_comp_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS2MDC_ODR_DIV_2 = 0,
IIS2MDC_ODR_DIV_4 = 1,
} iis2mdc_lpf_t;
@@ -374,7 +393,8 @@ int32_t iis2mdc_low_pass_bandwidth_set(stmdev_ctx_t *ctx,
int32_t iis2mdc_low_pass_bandwidth_get(stmdev_ctx_t *ctx,
iis2mdc_lpf_t *val);
-typedef enum {
+typedef enum
+{
IIS2MDC_SET_SENS_ODR_DIV_63 = 0,
IIS2MDC_SENS_OFF_CANC_EVERY_ODR = 1,
IIS2MDC_SET_SENS_ONLY_AT_POWER_ON = 2,
@@ -390,7 +410,8 @@ int32_t iis2mdc_set_rst_sensor_single_get(stmdev_ctx_t *ctx,
uint8_t *val);
int32_t iis2mdc_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis2mdc_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis2mdc_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t iis2mdc_mag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -411,16 +432,20 @@ int32_t iis2mdc_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t iis2mdc_self_test_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis2mdc_self_test_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS2MDC_LSB_AT_LOW_ADD = 0,
IIS2MDC_MSB_AT_LOW_ADD = 1,
} iis2mdc_ble_t;
int32_t iis2mdc_data_format_set(stmdev_ctx_t *ctx, iis2mdc_ble_t val);
-int32_t iis2mdc_data_format_get(stmdev_ctx_t *ctx, iis2mdc_ble_t *val);
+int32_t iis2mdc_data_format_get(stmdev_ctx_t *ctx,
+ iis2mdc_ble_t *val);
-int32_t iis2mdc_status_get(stmdev_ctx_t *ctx, iis2mdc_status_reg_t *val);
+int32_t iis2mdc_status_get(stmdev_ctx_t *ctx,
+ iis2mdc_status_reg_t *val);
-typedef enum {
+typedef enum
+{
IIS2MDC_CHECK_BEFORE = 0,
IIS2MDC_CHECK_AFTER = 1,
} iis2mdc_int_on_dataoff_t;
@@ -446,7 +471,8 @@ int32_t iis2mdc_int_gen_source_get(stmdev_ctx_t *ctx,
int32_t iis2mdc_int_gen_treshold_set(stmdev_ctx_t *ctx, int16_t val);
int32_t iis2mdc_int_gen_treshold_get(stmdev_ctx_t *ctx, int16_t *val);
-typedef enum {
+typedef enum
+{
IIS2MDC_I2C_ENABLE = 0,
IIS2MDC_I2C_DISABLE = 1,
} iis2mdc_i2c_dis_t;
diff --git a/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.c b/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.c
index db23190cb5696f04627fa052395980ec3b885a1f..c8e91a9e433e2c87d68470b1493a964fa5636350 100644
--- a/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.c
+++ b/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file iis328dq_reg.c
- * @author Sensors Software Solution Team
- * @brief IIS328DQ driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file iis328dq_reg.c
+ * @author Sensors Software Solution Team
+ * @brief IIS328DQ driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "iis328dq_reg.h"
@@ -43,14 +43,17 @@
* @param reg register to read
* @param data pointer to buffer that store the data read(ptr)
* @param len number of consecutive register to read
- * @retval interface status (MANDATORY: return 0 -> no Error)
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis328dq_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t iis328dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -61,14 +64,17 @@ int32_t iis328dq_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @param reg register to write
* @param data pointer to data to write in register reg(ptr)
* @param len number of consecutive register to write
- * @retval interface status (MANDATORY: return 0 -> no Error)
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis328dq_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t iis328dq_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -77,7 +83,7 @@ int32_t iis328dq_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
*
*/
- /**
+/**
* @defgroup IIS328DQ_Sensitivity
* @brief These functions convert raw-data into engineering units.
* @{
@@ -115,8 +121,9 @@ float_t iis328dq_from_fs8_to_mg(int16_t lsb)
/**
* @brief X axis enable/disable.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of xen in reg CTRL_REG1
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of xen in reg CTRL_REG1
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -124,20 +131,25 @@ int32_t iis328dq_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val)
iis328dq_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0) {
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.xen = val;
ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
/**
* @brief X axis enable/disable.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of xen in reg CTRL_REG1
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of xen in reg CTRL_REG1
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -145,7 +157,8 @@ int32_t iis328dq_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val)
iis328dq_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
*val = ctrl_reg1.xen;
return ret;
@@ -154,8 +167,9 @@ int32_t iis328dq_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @brief Y axis enable/disable.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of yen in reg CTRL_REG1
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of yen in reg CTRL_REG1
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -163,20 +177,25 @@ int32_t iis328dq_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val)
iis328dq_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0) {
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.yen = val;
ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
/**
* @brief Y axis enable/disable.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of yen in reg CTRL_REG1
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of yen in reg CTRL_REG1
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -184,7 +203,8 @@ int32_t iis328dq_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val)
iis328dq_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
*val = ctrl_reg1.yen;
return ret;
@@ -193,8 +213,9 @@ int32_t iis328dq_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @brief Z axis enable/disable.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of zen in reg CTRL_REG1
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of zen in reg CTRL_REG1
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -202,20 +223,25 @@ int32_t iis328dq_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val)
iis328dq_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0) {
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.zen = val;
ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
/**
* @brief Z axis enable/disable.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of zen in reg CTRL_REG1
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of zen in reg CTRL_REG1
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -223,7 +249,8 @@ int32_t iis328dq_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val)
iis328dq_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
*val = ctrl_reg1.zen;
return ret;
@@ -232,8 +259,9 @@ int32_t iis328dq_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @brief Accelerometer data rate selection.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of dr in reg CTRL_REG1
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of dr in reg CTRL_REG1
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_data_rate_set(stmdev_ctx_t *ctx, iis328dq_dr_t val)
@@ -242,21 +270,25 @@ int32_t iis328dq_data_rate_set(stmdev_ctx_t *ctx, iis328dq_dr_t val)
int32_t ret;
ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0) {
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.pm = (uint8_t)val & 0x07U;
- ctrl_reg1.dr = ( (uint8_t)val & 0x30U ) >> 4;
+ ctrl_reg1.dr = ((uint8_t)val & 0x30U) >> 4;
ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
/**
* @brief Accelerometer data rate selection.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of dr in reg CTRL_REG1
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of dr in reg CTRL_REG1
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_data_rate_get(stmdev_ctx_t *ctx, iis328dq_dr_t *val)
@@ -265,40 +297,50 @@ int32_t iis328dq_data_rate_get(stmdev_ctx_t *ctx, iis328dq_dr_t *val)
int32_t ret;
ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pm)
{
case IIS328DQ_ODR_OFF:
*val = IIS328DQ_ODR_OFF;
break;
+
case IIS328DQ_ODR_Hz5:
*val = IIS328DQ_ODR_Hz5;
break;
+
case IIS328DQ_ODR_1Hz:
*val = IIS328DQ_ODR_1Hz;
break;
+
case IIS328DQ_ODR_5Hz2:
*val = IIS328DQ_ODR_5Hz2;
break;
+
case IIS328DQ_ODR_5Hz:
*val = IIS328DQ_ODR_5Hz;
break;
+
case IIS328DQ_ODR_10Hz:
*val = IIS328DQ_ODR_10Hz;
break;
+
case IIS328DQ_ODR_50Hz:
*val = IIS328DQ_ODR_50Hz;
break;
+
case IIS328DQ_ODR_100Hz:
*val = IIS328DQ_ODR_100Hz;
break;
+
case IIS328DQ_ODR_400Hz:
*val = IIS328DQ_ODR_400Hz;
break;
+
case IIS328DQ_ODR_1kHz:
*val = IIS328DQ_ODR_1kHz;
break;
+
default:
*val = IIS328DQ_ODR_OFF;
break;
@@ -310,61 +352,71 @@ int32_t iis328dq_data_rate_get(stmdev_ctx_t *ctx, iis328dq_dr_t *val)
/**
* @brief High pass filter mode selection.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of hpm in reg CTRL_REG2
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of hpm in reg CTRL_REG2
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_reference_mode_set(stmdev_ctx_t *ctx,
- iis328dq_hpm_t val)
+ iis328dq_hpm_t val)
{
iis328dq_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0) {
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpm = (uint8_t)val;
ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
/**
* @brief High pass filter mode selection.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of hpm in reg CTRL_REG2
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of hpm in reg CTRL_REG2
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_reference_mode_get(stmdev_ctx_t *ctx,
- iis328dq_hpm_t *val)
+ iis328dq_hpm_t *val)
{
iis328dq_ctrl_reg2_t ctrl_reg2;
int32_t ret;
ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
switch (ctrl_reg2.hpm)
{
case IIS328DQ_NORMAL_MODE:
*val = IIS328DQ_NORMAL_MODE;
break;
+
case IIS328DQ_REF_MODE_ENABLE:
*val = IIS328DQ_REF_MODE_ENABLE;
break;
+
default:
*val = IIS328DQ_NORMAL_MODE;
break;
}
+
return ret;
}
/**
* @brief Accelerometer full-scale selection.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of fs in reg CTRL_REG4
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of fs in reg CTRL_REG4
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_full_scale_set(stmdev_ctx_t *ctx, iis328dq_fs_t val)
@@ -372,20 +424,25 @@ int32_t iis328dq_full_scale_set(stmdev_ctx_t *ctx, iis328dq_fs_t val)
iis328dq_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0) {
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.fs = (uint8_t)val;
ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
/**
* @brief Accelerometer full-scale selection.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of fs in reg CTRL_REG4
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of fs in reg CTRL_REG4
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_full_scale_get(stmdev_ctx_t *ctx, iis328dq_fs_t *val)
@@ -393,19 +450,23 @@ int32_t iis328dq_full_scale_get(stmdev_ctx_t *ctx, iis328dq_fs_t *val)
iis328dq_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
switch (ctrl_reg4.fs)
{
case IIS328DQ_2g:
*val = IIS328DQ_2g;
break;
+
case IIS328DQ_4g:
*val = IIS328DQ_4g;
break;
+
case IIS328DQ_8g:
*val = IIS328DQ_8g;
break;
+
default:
*val = IIS328DQ_2g;
break;
@@ -417,8 +478,9 @@ int32_t iis328dq_full_scale_get(stmdev_ctx_t *ctx, iis328dq_fs_t *val)
/**
* @brief Block data update.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of bdu in reg CTRL_REG4
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of bdu in reg CTRL_REG4
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -426,28 +488,35 @@ int32_t iis328dq_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
iis328dq_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0) {
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.bdu = val;
ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
/**
* @brief Block data update.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of bdu in reg CTRL_REG4
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of bdu in reg CTRL_REG4
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis328dq_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t iis328dq_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
iis328dq_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
*val = ctrl_reg4.bdu;
return ret;
@@ -456,23 +525,27 @@ int32_t iis328dq_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @brief The STATUS_REG register is read by the interface.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val registers STATUS_REG
+ * @param ctx read / write interface definitions(ptr)
+ * @param val registers STATUS_REG
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_status_reg_get(stmdev_ctx_t *ctx,
- iis328dq_status_reg_t *val)
+ iis328dq_status_reg_t *val)
{
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_STATUS_REG, (uint8_t*) val, 1);
+
+ ret = iis328dq_read_reg(ctx, IIS328DQ_STATUS_REG, (uint8_t *) val, 1);
+
return ret;
}
/**
* @brief Accelerometer new data available.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of zyxda in reg STATUS_REG
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of zyxda in reg STATUS_REG
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -481,7 +554,7 @@ int32_t iis328dq_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = iis328dq_read_reg(ctx, IIS328DQ_STATUS_REG,
- (uint8_t*)&status_reg, 1);
+ (uint8_t *)&status_reg, 1);
*val = status_reg.zyxda;
return ret;
@@ -503,8 +576,9 @@ int32_t iis328dq_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @brief Linear acceleration output register. The value is expressed
* as a 16-bit word in two’s complement.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param buff buffer that stores data read
+ * @param ctx read / write interface definitions(ptr)
+ * @param buff buffer that stores data read
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
@@ -514,11 +588,12 @@ int32_t iis328dq_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
ret = iis328dq_read_reg(ctx, IIS328DQ_OUT_X_L, buff, 6);
val[0] = (int16_t)buff[1];
- val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
- val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
val[2] = (int16_t)buff[5];
- val[2] = (val[2] * 256) + (int16_t)buff[4];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -537,22 +612,26 @@ int32_t iis328dq_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
/**
* @brief Device Who am I.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param buff buffer that stores data read
+ * @param ctx read / write interface definitions(ptr)
+ * @param buff buffer that stores data read
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = iis328dq_read_reg(ctx, IIS328DQ_WHO_AM_I, buff, 1);
+
return ret;
}
/**
* @brief Reboot memory content. Reload the calibration parameters.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of boot in reg CTRL_REG2
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of boot in reg CTRL_REG2
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_boot_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -560,20 +639,25 @@ int32_t iis328dq_boot_set(stmdev_ctx_t *ctx, uint8_t val)
iis328dq_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0) {
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.boot = val;
ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
/**
* @brief Reboot memory content. Reload the calibration parameters.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of boot in reg CTRL_REG2
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of boot in reg CTRL_REG2
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -581,7 +665,8 @@ int32_t iis328dq_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
iis328dq_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
*val = ctrl_reg2.boot;
return ret;
@@ -590,8 +675,9 @@ int32_t iis328dq_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @brief Linear acceleration sensor self-test enable.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of st in reg CTRL_REG4
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of st in reg CTRL_REG4
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_self_test_set(stmdev_ctx_t *ctx, iis328dq_st_t val)
@@ -599,20 +685,25 @@ int32_t iis328dq_self_test_set(stmdev_ctx_t *ctx, iis328dq_st_t val)
iis328dq_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0) {
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.st = (uint8_t)val;
ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
/**
* @brief Linear acceleration sensor self-test enable.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of st in reg CTRL_REG4
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of st in reg CTRL_REG4
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_self_test_get(stmdev_ctx_t *ctx, iis328dq_st_t *val)
@@ -620,19 +711,23 @@ int32_t iis328dq_self_test_get(stmdev_ctx_t *ctx, iis328dq_st_t *val)
iis328dq_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
switch (ctrl_reg4.st)
{
case IIS328DQ_ST_DISABLE:
*val = IIS328DQ_ST_DISABLE;
break;
+
case IIS328DQ_ST_POSITIVE:
*val = IIS328DQ_ST_POSITIVE;
break;
+
case IIS328DQ_ST_NEGATIVE:
*val = IIS328DQ_ST_NEGATIVE;
break;
+
default:
*val = IIS328DQ_ST_DISABLE;
break;
@@ -644,46 +739,57 @@ int32_t iis328dq_self_test_get(stmdev_ctx_t *ctx, iis328dq_st_t *val)
/**
* @brief Big/Little Endian Data selection.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of ble in reg CTRL_REG4
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of ble in reg CTRL_REG4
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis328dq_data_format_set(stmdev_ctx_t *ctx, iis328dq_ble_t val)
+int32_t iis328dq_data_format_set(stmdev_ctx_t *ctx,
+ iis328dq_ble_t val)
{
iis328dq_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0) {
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.ble = (uint8_t)val;
ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
/**
* @brief Big/Little Endian Data selection.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of ble in reg CTRL_REG4
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of ble in reg CTRL_REG4
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis328dq_data_format_get(stmdev_ctx_t *ctx, iis328dq_ble_t *val)
+int32_t iis328dq_data_format_get(stmdev_ctx_t *ctx,
+ iis328dq_ble_t *val)
{
iis328dq_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
switch (ctrl_reg4.ble)
{
case IIS328DQ_LSB_AT_LOW_ADD:
*val = IIS328DQ_LSB_AT_LOW_ADD;
break;
+
case IIS328DQ_MSB_AT_LOW_ADD:
*val = IIS328DQ_MSB_AT_LOW_ADD;
break;
+
default:
*val = IIS328DQ_LSB_AT_LOW_ADD;
break;
@@ -708,53 +814,65 @@ int32_t iis328dq_data_format_get(stmdev_ctx_t *ctx, iis328dq_ble_t *val)
/**
* @brief High pass filter cut-off frequency configuration.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of hpcf in reg CTRL_REG2
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of hpcf in reg CTRL_REG2
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis328dq_hp_bandwidth_set(stmdev_ctx_t *ctx, iis328dq_hpcf_t val)
+int32_t iis328dq_hp_bandwidth_set(stmdev_ctx_t *ctx,
+ iis328dq_hpcf_t val)
{
iis328dq_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0) {
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpcf = (uint8_t)val;
ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
/**
* @brief High pass filter cut-off frequency configuration.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of hpcf in reg CTRL_REG2
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of hpcf in reg CTRL_REG2
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_hp_bandwidth_get(stmdev_ctx_t *ctx,
- iis328dq_hpcf_t *val)
+ iis328dq_hpcf_t *val)
{
iis328dq_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
switch (ctrl_reg2.hpcf)
{
case IIS328DQ_CUT_OFF_8Hz:
*val = IIS328DQ_CUT_OFF_8Hz;
break;
+
case IIS328DQ_CUT_OFF_16Hz:
*val = IIS328DQ_CUT_OFF_16Hz;
break;
+
case IIS328DQ_CUT_OFF_32Hz:
*val = IIS328DQ_CUT_OFF_32Hz;
break;
+
case IIS328DQ_CUT_OFF_64Hz:
*val = IIS328DQ_CUT_OFF_64Hz;
break;
+
default:
*val = IIS328DQ_CUT_OFF_8Hz;
break;
@@ -766,8 +884,9 @@ int32_t iis328dq_hp_bandwidth_get(stmdev_ctx_t *ctx,
/**
* @brief Select High Pass filter path.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of hpen in reg CTRL_REG2
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of hpen in reg CTRL_REG2
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_hp_path_set(stmdev_ctx_t *ctx, iis328dq_hpen_t val)
@@ -775,21 +894,26 @@ int32_t iis328dq_hp_path_set(stmdev_ctx_t *ctx, iis328dq_hpen_t val)
iis328dq_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0) {
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpen = (uint8_t)val & 0x03U;
ctrl_reg2.fds = ((uint8_t)val & 0x04U) >> 2;
ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
/**
* @brief Select High Pass filter path.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of hpen in reg CTRL_REG2
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of hpen in reg CTRL_REG2
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_hp_path_get(stmdev_ctx_t *ctx, iis328dq_hpen_t *val)
@@ -797,38 +921,48 @@ int32_t iis328dq_hp_path_get(stmdev_ctx_t *ctx, iis328dq_hpen_t *val)
iis328dq_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
- switch ( (ctrl_reg2.fds << 2) + ctrl_reg2.hpen )
+ switch ((ctrl_reg2.fds << 2) + ctrl_reg2.hpen)
{
case IIS328DQ_HP_DISABLE:
*val = IIS328DQ_HP_DISABLE;
break;
+
case IIS328DQ_HP_ON_OUT:
*val = IIS328DQ_HP_ON_OUT;
break;
+
case IIS328DQ_HP_ON_INT1:
*val = IIS328DQ_HP_ON_INT1;
break;
+
case IIS328DQ_HP_ON_INT2:
*val = IIS328DQ_HP_ON_INT2;
break;
+
case IIS328DQ_HP_ON_INT1_INT2:
*val = IIS328DQ_HP_ON_INT1_INT2;
break;
+
case IIS328DQ_HP_ON_INT1_INT2_OUT:
*val = IIS328DQ_HP_ON_INT1_INT2_OUT;
break;
+
case IIS328DQ_HP_ON_INT2_OUT:
*val = IIS328DQ_HP_ON_INT2_OUT;
break;
+
case IIS328DQ_HP_ON_INT1_OUT:
*val = IIS328DQ_HP_ON_INT1_OUT;
break;
+
default:
*val = IIS328DQ_HP_DISABLE;
break;
}
+
return ret;
}
@@ -840,43 +974,54 @@ int32_t iis328dq_hp_path_get(stmdev_ctx_t *ctx, iis328dq_hpen_t *val)
* overcome the settling time of the high pass
* filter.[get]
*
- * @param ctx read / write interface definitions(ptr)
+ * @param ctx read / write interface definitions(ptr)
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_hp_reset_get(stmdev_ctx_t *ctx)
{
uint8_t dummy;
int32_t ret;
+
ret = iis328dq_read_reg(ctx, IIS328DQ_HP_FILTER_RESET,
- (uint8_t*)&dummy, 1);
+ (uint8_t *)&dummy, 1);
+
return ret;
}
/**
* @brief Reference value for high-pass filter.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of ref in reg REFERENCE
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of ref in reg REFERENCE
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis328dq_hp_reference_value_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t iis328dq_hp_reference_value_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
int32_t ret;
- ret = iis328dq_write_reg(ctx, IIS328DQ_REFERENCE, (uint8_t*)&val, 1);
+
+ ret = iis328dq_write_reg(ctx, IIS328DQ_REFERENCE, (uint8_t *)&val, 1);
+
return ret;
}
/**
* @brief Reference value for high-pass filter.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of ref in reg REFERENCE
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of ref in reg REFERENCE
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis328dq_hp_reference_value_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t iis328dq_hp_reference_value_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
int32_t ret;
+
ret = iis328dq_read_reg(ctx, IIS328DQ_REFERENCE, val, 1);
+
return ret;
}
@@ -896,8 +1041,9 @@ int32_t iis328dq_hp_reference_value_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @brief SPI 3- or 4-wire interface.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of sim in reg CTRL_REG4
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of sim in reg CTRL_REG4
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_spi_mode_set(stmdev_ctx_t *ctx, iis328dq_sim_t val)
@@ -905,20 +1051,25 @@ int32_t iis328dq_spi_mode_set(stmdev_ctx_t *ctx, iis328dq_sim_t val)
iis328dq_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0) {
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.sim = (uint8_t)val;
ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
/**
* @brief SPI 3- or 4-wire interface.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of sim in reg CTRL_REG4
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of sim in reg CTRL_REG4
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_spi_mode_get(stmdev_ctx_t *ctx, iis328dq_sim_t *val)
@@ -926,16 +1077,19 @@ int32_t iis328dq_spi_mode_get(stmdev_ctx_t *ctx, iis328dq_sim_t *val)
iis328dq_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
- switch ( ctrl_reg4.sim )
+ switch (ctrl_reg4.sim)
{
case IIS328DQ_SPI_4_WIRE:
*val = IIS328DQ_SPI_4_WIRE;
break;
+
case IIS328DQ_SPI_3_WIRE:
*val = IIS328DQ_SPI_3_WIRE;
break;
+
default:
*val = IIS328DQ_SPI_4_WIRE;
break;
@@ -960,54 +1114,65 @@ int32_t iis328dq_spi_mode_get(stmdev_ctx_t *ctx, iis328dq_sim_t *val)
/**
* @brief Data signal on INT 1 pad control bits.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of i1_cfg in reg CTRL_REG3
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of i1_cfg in reg CTRL_REG3
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_pin_int1_route_set(stmdev_ctx_t *ctx,
- iis328dq_i1_cfg_t val)
+ iis328dq_i1_cfg_t val)
{
iis328dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.i1_cfg = (uint8_t)val;
ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
/**
* @brief Data signal on INT 1 pad control bits.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of i1_cfg in reg CTRL_REG3
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of i1_cfg in reg CTRL_REG3
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_pin_int1_route_get(stmdev_ctx_t *ctx,
- iis328dq_i1_cfg_t *val)
+ iis328dq_i1_cfg_t *val)
{
iis328dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.i1_cfg )
+ switch (ctrl_reg3.i1_cfg)
{
case IIS328DQ_PAD1_INT1_SRC:
*val = IIS328DQ_PAD1_INT1_SRC;
break;
+
case IIS328DQ_PAD1_INT1_OR_INT2_SRC:
*val = IIS328DQ_PAD1_INT1_OR_INT2_SRC;
break;
+
case IIS328DQ_PAD1_DRDY:
*val = IIS328DQ_PAD1_DRDY;
break;
+
case IIS328DQ_PAD1_BOOT:
*val = IIS328DQ_PAD1_BOOT;
break;
+
default:
*val = IIS328DQ_PAD1_INT1_SRC;
break;
@@ -1020,22 +1185,27 @@ int32_t iis328dq_pin_int1_route_get(stmdev_ctx_t *ctx,
* @brief Latch interrupt request on INT1_SRC register, with INT1_SRC
* register cleared by reading INT1_SRC register.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of lir1 in reg CTRL_REG3
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of lir1 in reg CTRL_REG3
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int1_notification_set(stmdev_ctx_t *ctx,
- iis328dq_lir1_t val)
+ iis328dq_lir1_t val)
{
iis328dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.lir1 = (uint8_t)val;
ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1043,26 +1213,30 @@ int32_t iis328dq_int1_notification_set(stmdev_ctx_t *ctx,
* @brief Latch interrupt request on INT1_SRC register, with INT1_SRC
* register cleared by reading INT1_SRC register.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of lir1 in reg CTRL_REG3
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of lir1 in reg CTRL_REG3
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int1_notification_get(stmdev_ctx_t *ctx,
- iis328dq_lir1_t *val)
+ iis328dq_lir1_t *val)
{
iis328dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.lir1 )
+ switch (ctrl_reg3.lir1)
{
case IIS328DQ_INT1_PULSED:
*val = IIS328DQ_INT1_PULSED;
break;
+
case IIS328DQ_INT1_LATCHED:
*val = IIS328DQ_INT1_LATCHED;
break;
+
default:
*val = IIS328DQ_INT1_PULSED;
break;
@@ -1074,54 +1248,65 @@ int32_t iis328dq_int1_notification_get(stmdev_ctx_t *ctx,
/**
* @brief Data signal on INT 2 pad control bits.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of i2_cfg in reg CTRL_REG3
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of i2_cfg in reg CTRL_REG3
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_pin_int2_route_set(stmdev_ctx_t *ctx,
- iis328dq_i2_cfg_t val)
+ iis328dq_i2_cfg_t val)
{
iis328dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.i2_cfg = (uint8_t)val;
ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
/**
* @brief Data signal on INT 2 pad control bits.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of i2_cfg in reg CTRL_REG3
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of i2_cfg in reg CTRL_REG3
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_pin_int2_route_get(stmdev_ctx_t *ctx,
- iis328dq_i2_cfg_t *val)
+ iis328dq_i2_cfg_t *val)
{
iis328dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.i2_cfg )
+ switch (ctrl_reg3.i2_cfg)
{
case IIS328DQ_PAD2_INT2_SRC:
*val = IIS328DQ_PAD2_INT2_SRC;
break;
+
case IIS328DQ_PAD2_INT1_OR_INT2_SRC:
*val = IIS328DQ_PAD2_INT1_OR_INT2_SRC;
break;
+
case IIS328DQ_PAD2_DRDY:
*val = IIS328DQ_PAD2_DRDY;
break;
+
case IIS328DQ_PAD2_BOOT:
*val = IIS328DQ_PAD2_BOOT;
break;
+
default:
*val = IIS328DQ_PAD2_INT2_SRC;
break;
@@ -1134,22 +1319,27 @@ int32_t iis328dq_pin_int2_route_get(stmdev_ctx_t *ctx,
* @brief Latch interrupt request on INT2_SRC register, with INT2_SRC
* register cleared by reading INT2_SRC itself.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of lir2 in reg CTRL_REG3
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of lir2 in reg CTRL_REG3
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int2_notification_set(stmdev_ctx_t *ctx,
- iis328dq_lir2_t val)
+ iis328dq_lir2_t val)
{
iis328dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.lir2 = (uint8_t)val;
ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1157,26 +1347,30 @@ int32_t iis328dq_int2_notification_set(stmdev_ctx_t *ctx,
* @brief Latch interrupt request on INT2_SRC register, with INT2_SRC
* register cleared by reading INT2_SRC itself.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of lir2 in reg CTRL_REG3
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of lir2 in reg CTRL_REG3
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int2_notification_get(stmdev_ctx_t *ctx,
- iis328dq_lir2_t *val)
+ iis328dq_lir2_t *val)
{
iis328dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.lir2 )
+ switch (ctrl_reg3.lir2)
{
case IIS328DQ_INT2_PULSED:
*val = IIS328DQ_INT2_PULSED;
break;
+
case IIS328DQ_INT2_LATCHED:
*val = IIS328DQ_INT2_LATCHED;
break;
+
default:
*val = IIS328DQ_INT2_PULSED;
break;
@@ -1188,8 +1382,9 @@ int32_t iis328dq_int2_notification_get(stmdev_ctx_t *ctx,
/**
* @brief Push-pull/open drain selection on interrupt pads.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of pp_od in reg CTRL_REG3
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of pp_od in reg CTRL_REG3
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_pin_mode_set(stmdev_ctx_t *ctx, iis328dq_pp_od_t val)
@@ -1197,37 +1392,46 @@ int32_t iis328dq_pin_mode_set(stmdev_ctx_t *ctx, iis328dq_pp_od_t val)
iis328dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.pp_od = (uint8_t)val;
ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
/**
* @brief Push-pull/open drain selection on interrupt pads.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of pp_od in reg CTRL_REG3
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of pp_od in reg CTRL_REG3
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis328dq_pin_mode_get(stmdev_ctx_t *ctx, iis328dq_pp_od_t *val)
+int32_t iis328dq_pin_mode_get(stmdev_ctx_t *ctx,
+ iis328dq_pp_od_t *val)
{
iis328dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.pp_od )
+ switch (ctrl_reg3.pp_od)
{
case IIS328DQ_PUSH_PULL:
*val = IIS328DQ_PUSH_PULL;
break;
+
case IIS328DQ_OPEN_DRAIN:
*val = IIS328DQ_OPEN_DRAIN;
break;
+
default:
*val = IIS328DQ_PUSH_PULL;
break;
@@ -1239,46 +1443,57 @@ int32_t iis328dq_pin_mode_get(stmdev_ctx_t *ctx, iis328dq_pp_od_t *val)
/**
* @brief Interrupt active-high/low.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of ihl in reg CTRL_REG3
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of ihl in reg CTRL_REG3
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis328dq_pin_polarity_set(stmdev_ctx_t *ctx, iis328dq_ihl_t val)
+int32_t iis328dq_pin_polarity_set(stmdev_ctx_t *ctx,
+ iis328dq_ihl_t val)
{
iis328dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.ihl = (uint8_t)val;
ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
/**
* @brief Interrupt active-high/low.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of ihl in reg CTRL_REG3
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of ihl in reg CTRL_REG3
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis328dq_pin_polarity_get(stmdev_ctx_t *ctx, iis328dq_ihl_t *val)
+int32_t iis328dq_pin_polarity_get(stmdev_ctx_t *ctx,
+ iis328dq_ihl_t *val)
{
iis328dq_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.ihl )
+ switch (ctrl_reg3.ihl)
{
case IIS328DQ_ACTIVE_HIGH:
*val = IIS328DQ_ACTIVE_HIGH;
break;
+
case IIS328DQ_ACTIVE_LOW:
*val = IIS328DQ_ACTIVE_LOW;
break;
+
default:
*val = IIS328DQ_ACTIVE_HIGH;
break;
@@ -1303,18 +1518,21 @@ int32_t iis328dq_pin_polarity_get(stmdev_ctx_t *ctx, iis328dq_ihl_t *val)
/**
* @brief Configure the interrupt 1 threshold sign.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val enable sign and axis for interrupt on threshold
+ * @param ctx read / write interface definitions(ptr)
+ * @param val enable sign and axis for interrupt on threshold
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int1_on_threshold_conf_set(stmdev_ctx_t *ctx,
- int1_on_th_conf_t val)
+ int1_on_th_conf_t val)
{
iis328dq_int1_cfg_t int1_cfg;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_CFG, (uint8_t*)&int1_cfg, 1);
- if(ret == 0) {
+ ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
+
+ if (ret == 0)
+ {
int1_cfg.xlie = val.int1_xlie;
int1_cfg.xhie = val.int1_xhie;
int1_cfg.ylie = val.int1_ylie;
@@ -1322,25 +1540,27 @@ int32_t iis328dq_int1_on_threshold_conf_set(stmdev_ctx_t *ctx,
int1_cfg.zlie = val.int1_zlie;
int1_cfg.zhie = val.int1_zhie;
ret = iis328dq_write_reg(ctx, IIS328DQ_INT1_CFG,
- (uint8_t*)&int1_cfg, 1);
+ (uint8_t *)&int1_cfg, 1);
}
+
return ret;
}
/**
* @brief Configure the interrupt 1 threshold sign.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val enable sign and axis for interrupt on threshold
+ * @param ctx read / write interface definitions(ptr)
+ * @param val enable sign and axis for interrupt on threshold
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int1_on_threshold_conf_get(stmdev_ctx_t *ctx,
- int1_on_th_conf_t *val)
+ int1_on_th_conf_t *val)
{
iis328dq_int1_cfg_t int1_cfg;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_CFG, (uint8_t*)&int1_cfg, 1);
+ ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
val->int1_xlie = int1_cfg.xlie;
val->int1_xhie = int1_cfg.xhie;
val->int1_ylie = int1_cfg.ylie;
@@ -1354,48 +1574,55 @@ int32_t iis328dq_int1_on_threshold_conf_get(stmdev_ctx_t *ctx,
/**
* @brief AND/OR combination of Interrupt 1 events.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of aoi in reg INT1_CFG
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of aoi in reg INT1_CFG
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int1_on_threshold_mode_set(stmdev_ctx_t *ctx,
- iis328dq_int1_aoi_t val)
+ iis328dq_int1_aoi_t val)
{
iis328dq_int1_cfg_t int1_cfg;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_CFG, (uint8_t*)&int1_cfg, 1);
- if(ret == 0) {
+ ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
+
+ if (ret == 0)
+ {
int1_cfg.aoi = (uint8_t) val;
ret = iis328dq_write_reg(ctx, IIS328DQ_INT1_CFG,
- (uint8_t*)&int1_cfg, 1);
+ (uint8_t *)&int1_cfg, 1);
}
+
return ret;
}
/**
* @brief AND/OR combination of Interrupt 1 events.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of aoi in reg INT1_CFG
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of aoi in reg INT1_CFG
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int1_on_threshold_mode_get(stmdev_ctx_t *ctx,
- iis328dq_int1_aoi_t *val)
+ iis328dq_int1_aoi_t *val)
{
iis328dq_int1_cfg_t int1_cfg;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_CFG, (uint8_t*)&int1_cfg, 1);
+ ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
- switch ( int1_cfg.aoi )
+ switch (int1_cfg.aoi)
{
case IIS328DQ_INT1_ON_THRESHOLD_OR:
*val = IIS328DQ_INT1_ON_THRESHOLD_OR;
break;
+
case IIS328DQ_INT1_ON_THRESHOLD_AND:
*val = IIS328DQ_INT1_ON_THRESHOLD_AND;
break;
+
default:
*val = IIS328DQ_INT1_ON_THRESHOLD_OR;
break;
@@ -1407,23 +1634,27 @@ int32_t iis328dq_int1_on_threshold_mode_get(stmdev_ctx_t *ctx,
/**
* @brief Interrupt generator 1 on threshold source register.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val registers INT1_SRC
+ * @param ctx read / write interface definitions(ptr)
+ * @param val registers INT1_SRC
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int1_src_get(stmdev_ctx_t *ctx,
- iis328dq_int1_src_t *val)
+ iis328dq_int1_src_t *val)
{
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_SRC, (uint8_t*) val, 1);
+
+ ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_SRC, (uint8_t *) val, 1);
+
return ret;
}
/**
* @brief Interrupt 1 threshold.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of ths in reg INT1_THS
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of ths in reg INT1_THS
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1431,20 +1662,24 @@ int32_t iis328dq_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
iis328dq_int1_ths_t int1_ths;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_THS, (uint8_t*)&int1_ths, 1);
- if(ret == 0) {
+ ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_THS, (uint8_t *)&int1_ths, 1);
+
+ if (ret == 0)
+ {
int1_ths.ths = val;
ret = iis328dq_write_reg(ctx, IIS328DQ_INT1_THS,
- (uint8_t*)&int1_ths, 1);
+ (uint8_t *)&int1_ths, 1);
}
+
return ret;
}
/**
* @brief Interrupt 1 threshold.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of ths in reg INT1_THS
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of ths in reg INT1_THS
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1452,7 +1687,7 @@ int32_t iis328dq_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
iis328dq_int1_ths_t int1_ths;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_THS, (uint8_t*)&int1_ths, 1);
+ ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_THS, (uint8_t *)&int1_ths, 1);
*val = int1_ths.ths;
return ret;
@@ -1461,8 +1696,9 @@ int32_t iis328dq_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @brief Duration value for interrupt 1 generator.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of d in reg INT1_DURATION
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of d in reg INT1_DURATION
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1471,20 +1707,24 @@ int32_t iis328dq_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_DURATION,
- (uint8_t*)&int1_duration, 1);
- if(ret == 0) {
+ (uint8_t *)&int1_duration, 1);
+
+ if (ret == 0)
+ {
int1_duration.d = val;
ret = iis328dq_write_reg(ctx, IIS328DQ_INT1_DURATION,
- (uint8_t*)&int1_duration, 1);
+ (uint8_t *)&int1_duration, 1);
}
+
return ret;
}
/**
* @brief Duration value for interrupt 1 generator.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of d in reg INT1_DURATION
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of d in reg INT1_DURATION
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1493,7 +1733,7 @@ int32_t iis328dq_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_DURATION,
- (uint8_t*)&int1_duration, 1);
+ (uint8_t *)&int1_duration, 1);
*val = int1_duration.d;
return ret;
@@ -1502,19 +1742,22 @@ int32_t iis328dq_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @brief Configure the interrupt 2 threshold sign.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val enable sign and axis for interrupt on threshold
+ * @param ctx read / write interface definitions(ptr)
+ * @param val enable sign and axis for interrupt on threshold
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int2_on_threshold_conf_set(stmdev_ctx_t *ctx,
- int2_on_th_conf_t val)
+ int2_on_th_conf_t val)
{
iis328dq_int2_cfg_t int2_cfg;
int32_t ret;
ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_CFG,
- (uint8_t*)&int2_cfg, 1);
- if(ret == 0) {
+ (uint8_t *)&int2_cfg, 1);
+
+ if (ret == 0)
+ {
int2_cfg.xlie = val.int2_xlie;
int2_cfg.xhie = val.int2_xhie;
int2_cfg.ylie = val.int2_ylie;
@@ -1522,25 +1765,27 @@ int32_t iis328dq_int2_on_threshold_conf_set(stmdev_ctx_t *ctx,
int2_cfg.zlie = val.int2_zlie;
int2_cfg.zhie = val.int2_zhie;
ret = iis328dq_write_reg(ctx, IIS328DQ_INT2_CFG,
- (uint8_t*)&int2_cfg, 1);
+ (uint8_t *)&int2_cfg, 1);
}
+
return ret;
}
/**
* @brief Configure the interrupt 2 threshold sign.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val enable sign and axis for interrupt on threshold
+ * @param ctx read / write interface definitions(ptr)
+ * @param val enable sign and axis for interrupt on threshold
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int2_on_threshold_conf_get(stmdev_ctx_t *ctx,
- int2_on_th_conf_t *val)
+ int2_on_th_conf_t *val)
{
iis328dq_int2_cfg_t int2_cfg;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_CFG, (uint8_t*)&int2_cfg, 1);
+ ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1);
val->int2_xlie = int2_cfg.xlie;
val->int2_xhie = int2_cfg.xhie;
val->int2_ylie = int2_cfg.ylie;
@@ -1554,48 +1799,55 @@ int32_t iis328dq_int2_on_threshold_conf_get(stmdev_ctx_t *ctx,
/**
* @brief AND/OR combination of Interrupt 2 events.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of aoi in reg INT2_CFG
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of aoi in reg INT2_CFG
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int2_on_threshold_mode_set(stmdev_ctx_t *ctx,
- iis328dq_int2_aoi_t val)
+ iis328dq_int2_aoi_t val)
{
iis328dq_int2_cfg_t int2_cfg;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_CFG, (uint8_t*)&int2_cfg, 1);
- if(ret == 0) {
+ ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1);
+
+ if (ret == 0)
+ {
int2_cfg.aoi = (uint8_t) val;
ret = iis328dq_write_reg(ctx, IIS328DQ_INT2_CFG,
- (uint8_t*)&int2_cfg, 1);
+ (uint8_t *)&int2_cfg, 1);
}
+
return ret;
}
/**
* @brief AND/OR combination of Interrupt 2 events.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of aoi in reg INT2_CFG
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of aoi in reg INT2_CFG
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int2_on_threshold_mode_get(stmdev_ctx_t *ctx,
- iis328dq_int2_aoi_t *val)
+ iis328dq_int2_aoi_t *val)
{
iis328dq_int2_cfg_t int2_cfg;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_CFG, (uint8_t*)&int2_cfg, 1);
+ ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1);
- switch ( int2_cfg.aoi )
+ switch (int2_cfg.aoi)
{
case IIS328DQ_INT2_ON_THRESHOLD_OR:
*val = IIS328DQ_INT2_ON_THRESHOLD_OR;
break;
+
case IIS328DQ_INT2_ON_THRESHOLD_AND:
*val = IIS328DQ_INT2_ON_THRESHOLD_AND;
break;
+
default:
*val = IIS328DQ_INT2_ON_THRESHOLD_OR;
break;
@@ -1607,23 +1859,27 @@ int32_t iis328dq_int2_on_threshold_mode_get(stmdev_ctx_t *ctx,
/**
* @brief Interrupt generator 1 on threshold source register.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val registers INT2_SRC
+ * @param ctx read / write interface definitions(ptr)
+ * @param val registers INT2_SRC
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int2_src_get(stmdev_ctx_t *ctx,
- iis328dq_int2_src_t *val)
+ iis328dq_int2_src_t *val)
{
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_SRC, (uint8_t*) val, 1);
+
+ ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_SRC, (uint8_t *) val, 1);
+
return ret;
}
/**
* @brief Interrupt 2 threshold.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of ths in reg INT2_THS
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of ths in reg INT2_THS
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1631,20 +1887,24 @@ int32_t iis328dq_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
iis328dq_int2_ths_t int2_ths;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_THS, (uint8_t*)&int2_ths, 1);
- if(ret == 0) {
+ ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_THS, (uint8_t *)&int2_ths, 1);
+
+ if (ret == 0)
+ {
int2_ths.ths = val;
ret = iis328dq_write_reg(ctx, IIS328DQ_INT2_THS,
- (uint8_t*)&int2_ths, 1);
+ (uint8_t *)&int2_ths, 1);
}
+
return ret;
}
/**
* @brief Interrupt 2 threshold.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of ths in reg INT2_THS
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of ths in reg INT2_THS
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1652,7 +1912,7 @@ int32_t iis328dq_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
iis328dq_int2_ths_t int2_ths;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_THS, (uint8_t*)&int2_ths, 1);
+ ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_THS, (uint8_t *)&int2_ths, 1);
*val = int2_ths.ths;
return ret;
@@ -1661,8 +1921,9 @@ int32_t iis328dq_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @brief Duration value for interrupt 2 generator.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of d in reg INT2_DURATION
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of d in reg INT2_DURATION
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1671,20 +1932,24 @@ int32_t iis328dq_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_DURATION,
- (uint8_t*)&int2_duration, 1);
- if(ret == 0) {
+ (uint8_t *)&int2_duration, 1);
+
+ if (ret == 0)
+ {
int2_duration.d = val;
ret = iis328dq_write_reg(ctx, IIS328DQ_INT2_DURATION,
- (uint8_t*)&int2_duration, 1);
+ (uint8_t *)&int2_duration, 1);
}
+
return ret;
}
/**
* @brief Duration value for interrupt 2 generator.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of d in reg INT2_DURATION
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of d in reg INT2_DURATION
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1693,7 +1958,7 @@ int32_t iis328dq_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_DURATION,
- (uint8_t*)&int2_duration, 1);
+ (uint8_t *)&int2_duration, 1);
*val = int2_duration.d;
return ret;
@@ -1715,8 +1980,9 @@ int32_t iis328dq_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @brief Turn-on mode selection for sleep to wake function.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of turnon in reg CTRL_REG5
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of turnon in reg CTRL_REG5
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1724,20 +1990,25 @@ int32_t iis328dq_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val)
iis328dq_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if(ret == 0) {
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.turnon = val;
ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG5,
- (uint8_t*)&ctrl_reg5, 1);
+ (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
/**
* @brief Turn-on mode selection for sleep to wake function.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of turnon in reg CTRL_REG5
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of turnon in reg CTRL_REG5
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1745,7 +2016,8 @@ int32_t iis328dq_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val)
iis328dq_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
*val = ctrl_reg5.turnon;
return ret;
@@ -1767,51 +2039,59 @@ int32_t iis328dq_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @brief Configure the 6d on interrupt 1 generator.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of 6d in reg INT1_CFG
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of 6d in reg INT1_CFG
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int1_6d_mode_set(stmdev_ctx_t *ctx,
- iis328dq_int1_6d_t val)
+ iis328dq_int1_6d_t val)
{
iis328dq_int1_cfg_t int1_cfg;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_CFG, (uint8_t*)&int1_cfg, 1);
- if(ret == 0) {
+ ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
+
+ if (ret == 0)
+ {
int1_cfg._6d = (uint8_t)val & 0x01U;
int1_cfg.aoi = ((uint8_t)val & 0x02U) >> 1;
- ret = iis328dq_write_reg(ctx, IIS328DQ_INT1_CFG, (uint8_t*)&int1_cfg, 1);
+ ret = iis328dq_write_reg(ctx, IIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
}
+
return ret;
}
/**
* @brief Configure the 6d on interrupt 1 generator.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of 6d in reg INT1_CFG
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of 6d in reg INT1_CFG
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int1_6d_mode_get(stmdev_ctx_t *ctx,
- iis328dq_int1_6d_t *val)
+ iis328dq_int1_6d_t *val)
{
iis328dq_int1_cfg_t int1_cfg;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_CFG, (uint8_t*)&int1_cfg, 1);
+ ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
switch ((int1_cfg.aoi << 1) + int1_cfg._6d)
{
case IIS328DQ_6D_INT1_DISABLE:
*val = IIS328DQ_6D_INT1_DISABLE;
break;
+
case IIS328DQ_6D_INT1_MOVEMENT:
*val = IIS328DQ_6D_INT1_MOVEMENT;
break;
- case IIS328DQ_6D_INT1_POSITION:
+
+ case IIS328DQ_6D_INT1_POSITION:
*val = IIS328DQ_6D_INT1_POSITION;
break;
+
default:
*val = IIS328DQ_6D_INT1_DISABLE;
break;
@@ -1823,23 +2103,27 @@ int32_t iis328dq_int1_6d_mode_get(stmdev_ctx_t *ctx,
/**
* @brief 6D on interrupt generator 1 source register.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val registers INT1_SRC
+ * @param ctx read / write interface definitions(ptr)
+ * @param val registers INT1_SRC
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int1_6d_src_get(stmdev_ctx_t *ctx,
- iis328dq_int1_src_t *val)
+ iis328dq_int1_src_t *val)
{
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_SRC, (uint8_t*) val, 1);
+
+ ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_SRC, (uint8_t *) val, 1);
+
return ret;
}
/**
* @brief Interrupt 1 threshold.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of ths in reg INT1_THS
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of ths in reg INT1_THS
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int1_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1847,19 +2131,23 @@ int32_t iis328dq_int1_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
iis328dq_int1_ths_t int1_ths;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_THS, (uint8_t*)&int1_ths, 1);
- if(ret == 0) {
+ ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_THS, (uint8_t *)&int1_ths, 1);
+
+ if (ret == 0)
+ {
int1_ths.ths = val;
- ret = iis328dq_write_reg(ctx, IIS328DQ_INT1_THS, (uint8_t*)&int1_ths, 1);
+ ret = iis328dq_write_reg(ctx, IIS328DQ_INT1_THS, (uint8_t *)&int1_ths, 1);
}
+
return ret;
}
/**
* @brief Interrupt 1 threshold.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of ths in reg INT1_THS
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of ths in reg INT1_THS
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int1_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1867,7 +2155,7 @@ int32_t iis328dq_int1_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
iis328dq_int1_ths_t int1_ths;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_THS, (uint8_t*)&int1_ths, 1);
+ ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_THS, (uint8_t *)&int1_ths, 1);
*val = int1_ths.ths;
return ret;
@@ -1876,52 +2164,60 @@ int32_t iis328dq_int1_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @brief Configure the 6d on interrupt 2 generator.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of 6d in reg INT2_CFG
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of 6d in reg INT2_CFG
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int2_6d_mode_set(stmdev_ctx_t *ctx,
- iis328dq_int2_6d_t val)
+ iis328dq_int2_6d_t val)
{
iis328dq_int2_cfg_t int2_cfg;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_CFG, (uint8_t*)&int2_cfg, 1);
- if(ret == 0) {
+ ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1);
+
+ if (ret == 0)
+ {
int2_cfg._6d = (uint8_t)val & 0x01U;
int2_cfg.aoi = ((uint8_t)val & 0x02U) >> 1;
ret = iis328dq_write_reg(ctx, IIS328DQ_INT2_CFG,
- (uint8_t*)&int2_cfg, 1);
+ (uint8_t *)&int2_cfg, 1);
}
+
return ret;
}
/**
* @brief Configure the 6d on interrupt 2 generator.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val Get the values of 6d in reg INT2_CFG
+ * @param ctx read / write interface definitions(ptr)
+ * @param val Get the values of 6d in reg INT2_CFG
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int2_6d_mode_get(stmdev_ctx_t *ctx,
- iis328dq_int2_6d_t *val)
+ iis328dq_int2_6d_t *val)
{
iis328dq_int2_cfg_t int2_cfg;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_CFG, (uint8_t*)&int2_cfg, 1);
+ ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1);
switch ((int2_cfg.aoi << 1) + int2_cfg._6d)
{
case IIS328DQ_6D_INT2_DISABLE:
*val = IIS328DQ_6D_INT2_DISABLE;
break;
+
case IIS328DQ_6D_INT2_MOVEMENT:
*val = IIS328DQ_6D_INT2_MOVEMENT;
break;
- case IIS328DQ_6D_INT2_POSITION:
+
+ case IIS328DQ_6D_INT2_POSITION:
*val = IIS328DQ_6D_INT2_POSITION;
break;
+
default:
*val = IIS328DQ_6D_INT2_DISABLE;
break;
@@ -1933,23 +2229,27 @@ int32_t iis328dq_int2_6d_mode_get(stmdev_ctx_t *ctx,
/**
* @brief 6D on interrupt generator 2 source register.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val registers INT2_SRC
+ * @param ctx read / write interface definitions(ptr)
+ * @param val registers INT2_SRC
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int2_6d_src_get(stmdev_ctx_t *ctx,
- iis328dq_int2_src_t *val)
+ iis328dq_int2_src_t *val)
{
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_SRC, (uint8_t*) val, 1);
+
+ ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_SRC, (uint8_t *) val, 1);
+
return ret;
}
/**
* @brief Interrupt 2 threshold.[set]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of ths in reg INT2_THS
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of ths in reg INT2_THS
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int2_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1957,20 +2257,24 @@ int32_t iis328dq_int2_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
iis328dq_int2_ths_t int2_ths;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_THS, (uint8_t*)&int2_ths, 1);
- if(ret == 0) {
+ ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_THS, (uint8_t *)&int2_ths, 1);
+
+ if (ret == 0)
+ {
int2_ths.ths = val;
ret = iis328dq_write_reg(ctx, IIS328DQ_INT2_THS,
- (uint8_t*)&int2_ths, 1);
+ (uint8_t *)&int2_ths, 1);
}
+
return ret;
}
/**
* @brief Interrupt 2 threshold.[get]
*
- * @param ctx read / write interface definitions(ptr)
- * @param val change the values of ths in reg INT2_THS
+ * @param ctx read / write interface definitions(ptr)
+ * @param val change the values of ths in reg INT2_THS
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t iis328dq_int2_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1978,7 +2282,7 @@ int32_t iis328dq_int2_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
iis328dq_int2_ths_t int2_ths;
int32_t ret;
- ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_THS, (uint8_t*)&int2_ths, 1);
+ ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_THS, (uint8_t *)&int2_ths, 1);
*val = int2_ths.ths;
return ret;
diff --git a/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.h b/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.h
index 8384c56b7891885b0f6a1ec77f49454a82aa9be1..0164acfd89242d5b39d851ba2773eacc5ac7a4b5 100644
--- a/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.h
+++ b/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.h
@@ -1,29 +1,29 @@
-/*
- ******************************************************************************
- * @file iis328dq_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * iis328dq_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file iis328dq_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * iis328dq_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef IIS328DQ_REGS_H
#define IIS328DQ_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -75,7 +75,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -108,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -132,7 +134,7 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
+ * You can create a sensor configuration by your own or using
* Unico / Unicleo tools available on STMicroelectronics
* web site.
*
@@ -140,7 +142,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -177,7 +180,8 @@ typedef struct {
#define IIS328DQ_WHO_AM_I 0x0FU
#define IIS328DQ_CTRL_REG1 0x20U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xen : 1;
uint8_t yen : 1;
@@ -194,7 +198,8 @@ typedef struct {
} iis328dq_ctrl_reg1_t;
#define IIS328DQ_CTRL_REG2 0x21U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t hpcf : 2;
uint8_t hpen : 2;
@@ -211,7 +216,8 @@ typedef struct {
} iis328dq_ctrl_reg2_t;
#define IIS328DQ_CTRL_REG3 0x22U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t i1_cfg : 2;
uint8_t lir1 : 1;
@@ -230,7 +236,8 @@ typedef struct {
} iis328dq_ctrl_reg3_t;
#define IIS328DQ_CTRL_REG4 0x23U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t st : 3; /* STsign + ST */
@@ -247,7 +254,8 @@ typedef struct {
} iis328dq_ctrl_reg4_t;
#define IIS328DQ_CTRL_REG5 0x24U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t turnon : 2;
uint8_t not_used_01 : 6;
@@ -260,7 +268,8 @@ typedef struct {
#define IIS328DQ_HP_FILTER_RESET 0x25U
#define IIS328DQ_REFERENCE 0x26U
#define IIS328DQ_STATUS_REG 0x27U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xda : 1;
uint8_t yda : 1;
@@ -289,7 +298,8 @@ typedef struct {
#define IIS328DQ_OUT_Z_L 0x2CU
#define IIS328DQ_OUT_Z_H 0x2DU
#define IIS328DQ_INT1_CFG 0x30U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlie : 1;
uint8_t xhie : 1;
@@ -312,7 +322,8 @@ typedef struct {
} iis328dq_int1_cfg_t;
#define IIS328DQ_INT1_SRC 0x31U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
@@ -335,7 +346,8 @@ typedef struct {
} iis328dq_int1_src_t;
#define IIS328DQ_INT1_THS 0x32U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t not_used_01 : 1;
@@ -346,7 +358,8 @@ typedef struct {
} iis328dq_int1_ths_t;
#define IIS328DQ_INT1_DURATION 0x33U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d : 7;
uint8_t not_used_01 : 1;
@@ -357,7 +370,8 @@ typedef struct {
} iis328dq_int1_duration_t;
#define IIS328DQ_INT2_CFG 0x34U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlie : 1;
uint8_t xhie : 1;
@@ -380,7 +394,8 @@ typedef struct {
} iis328dq_int2_cfg_t;
#define IIS328DQ_INT2_SRC 0x35U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
@@ -403,7 +418,8 @@ typedef struct {
} iis328dq_int2_src_t;
#define IIS328DQ_INT2_THS 0x36U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t not_used_01 : 1;
@@ -414,7 +430,8 @@ typedef struct {
} iis328dq_int2_ths_t;
#define IIS328DQ_INT2_DURATION 0x37U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d : 7;
uint8_t not_used_01 : 1;
@@ -426,9 +443,9 @@ typedef struct {
/**
* @defgroup IIS328DQ_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -436,7 +453,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
iis328dq_ctrl_reg1_t ctrl_reg1;
iis328dq_ctrl_reg2_t ctrl_reg2;
iis328dq_ctrl_reg3_t ctrl_reg3;
@@ -460,10 +478,12 @@ typedef union{
*
*/
-int32_t iis328dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t iis328dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len);
+int32_t iis328dq_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t iis328dq_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
- uint16_t len);
float_t iis328dq_from_fs2_to_mg(int16_t lsb);
float_t iis328dq_from_fs4_to_mg(int16_t lsb);
@@ -478,7 +498,8 @@ int32_t iis328dq_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t iis328dq_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis328dq_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS328DQ_ODR_OFF = 0x00,
IIS328DQ_ODR_Hz5 = 0x02,
IIS328DQ_ODR_1Hz = 0x03,
@@ -493,40 +514,47 @@ typedef enum {
int32_t iis328dq_data_rate_set(stmdev_ctx_t *ctx, iis328dq_dr_t val);
int32_t iis328dq_data_rate_get(stmdev_ctx_t *ctx, iis328dq_dr_t *val);
-typedef enum {
+typedef enum
+{
IIS328DQ_NORMAL_MODE = 0,
IIS328DQ_REF_MODE_ENABLE = 1,
} iis328dq_hpm_t;
int32_t iis328dq_reference_mode_set(stmdev_ctx_t *ctx,
- iis328dq_hpm_t val);
+ iis328dq_hpm_t val);
int32_t iis328dq_reference_mode_get(stmdev_ctx_t *ctx,
- iis328dq_hpm_t *val);
+ iis328dq_hpm_t *val);
-typedef enum {
+typedef enum
+{
IIS328DQ_2g = 0,
IIS328DQ_4g = 1,
IIS328DQ_8g = 3,
} iis328dq_fs_t;
int32_t iis328dq_full_scale_set(stmdev_ctx_t *ctx, iis328dq_fs_t val);
-int32_t iis328dq_full_scale_get(stmdev_ctx_t *ctx, iis328dq_fs_t *val);
+int32_t iis328dq_full_scale_get(stmdev_ctx_t *ctx,
+ iis328dq_fs_t *val);
-int32_t iis328dq_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis328dq_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis328dq_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t iis328dq_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t iis328dq_status_reg_get(stmdev_ctx_t *ctx,
- iis328dq_status_reg_t *val);
+ iis328dq_status_reg_t *val);
int32_t iis328dq_flag_data_ready_get(stmdev_ctx_t *ctx,
- uint8_t *val);
+ uint8_t *val);
-int32_t iis328dq_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t iis328dq_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
int32_t iis328dq_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t iis328dq_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis328dq_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS328DQ_ST_DISABLE = 0,
IIS328DQ_ST_POSITIVE = 1,
IIS328DQ_ST_NEGATIVE = 5,
@@ -534,25 +562,30 @@ typedef enum {
int32_t iis328dq_self_test_set(stmdev_ctx_t *ctx, iis328dq_st_t val);
int32_t iis328dq_self_test_get(stmdev_ctx_t *ctx, iis328dq_st_t *val);
-typedef enum {
+typedef enum
+{
IIS328DQ_LSB_AT_LOW_ADD = 0,
IIS328DQ_MSB_AT_LOW_ADD = 1,
} iis328dq_ble_t;
-int32_t iis328dq_data_format_set(stmdev_ctx_t *ctx, iis328dq_ble_t val);
-int32_t iis328dq_data_format_get(stmdev_ctx_t *ctx, iis328dq_ble_t *val);
+int32_t iis328dq_data_format_set(stmdev_ctx_t *ctx,
+ iis328dq_ble_t val);
+int32_t iis328dq_data_format_get(stmdev_ctx_t *ctx,
+ iis328dq_ble_t *val);
-typedef enum {
+typedef enum
+{
IIS328DQ_CUT_OFF_8Hz = 0,
IIS328DQ_CUT_OFF_16Hz = 1,
IIS328DQ_CUT_OFF_32Hz = 2,
IIS328DQ_CUT_OFF_64Hz = 3,
} iis328dq_hpcf_t;
int32_t iis328dq_hp_bandwidth_set(stmdev_ctx_t *ctx,
- iis328dq_hpcf_t val);
+ iis328dq_hpcf_t val);
int32_t iis328dq_hp_bandwidth_get(stmdev_ctx_t *ctx,
- iis328dq_hpcf_t *val);
+ iis328dq_hpcf_t *val);
-typedef enum {
+typedef enum
+{
IIS328DQ_HP_DISABLE = 0,
IIS328DQ_HP_ON_OUT = 4,
IIS328DQ_HP_ON_INT1 = 1,
@@ -567,73 +600,85 @@ int32_t iis328dq_hp_path_get(stmdev_ctx_t *ctx, iis328dq_hpen_t *val);
int32_t iis328dq_hp_reset_get(stmdev_ctx_t *ctx);
-int32_t iis328dq_hp_reference_value_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis328dq_hp_reference_value_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis328dq_hp_reference_value_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t iis328dq_hp_reference_value_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS328DQ_SPI_4_WIRE = 0,
IIS328DQ_SPI_3_WIRE = 1,
} iis328dq_sim_t;
int32_t iis328dq_spi_mode_set(stmdev_ctx_t *ctx, iis328dq_sim_t val);
int32_t iis328dq_spi_mode_get(stmdev_ctx_t *ctx, iis328dq_sim_t *val);
-typedef enum {
+typedef enum
+{
IIS328DQ_PAD1_INT1_SRC = 0,
IIS328DQ_PAD1_INT1_OR_INT2_SRC = 1,
IIS328DQ_PAD1_DRDY = 2,
IIS328DQ_PAD1_BOOT = 3,
} iis328dq_i1_cfg_t;
int32_t iis328dq_pin_int1_route_set(stmdev_ctx_t *ctx,
- iis328dq_i1_cfg_t val);
+ iis328dq_i1_cfg_t val);
int32_t iis328dq_pin_int1_route_get(stmdev_ctx_t *ctx,
- iis328dq_i1_cfg_t *val);
+ iis328dq_i1_cfg_t *val);
-typedef enum {
+typedef enum
+{
IIS328DQ_INT1_PULSED = 0,
IIS328DQ_INT1_LATCHED = 1,
} iis328dq_lir1_t;
int32_t iis328dq_int1_notification_set(stmdev_ctx_t *ctx,
- iis328dq_lir1_t val);
+ iis328dq_lir1_t val);
int32_t iis328dq_int1_notification_get(stmdev_ctx_t *ctx,
- iis328dq_lir1_t *val);
+ iis328dq_lir1_t *val);
-typedef enum {
+typedef enum
+{
IIS328DQ_PAD2_INT2_SRC = 0,
IIS328DQ_PAD2_INT1_OR_INT2_SRC = 1,
IIS328DQ_PAD2_DRDY = 2,
IIS328DQ_PAD2_BOOT = 3,
} iis328dq_i2_cfg_t;
int32_t iis328dq_pin_int2_route_set(stmdev_ctx_t *ctx,
- iis328dq_i2_cfg_t val);
+ iis328dq_i2_cfg_t val);
int32_t iis328dq_pin_int2_route_get(stmdev_ctx_t *ctx,
- iis328dq_i2_cfg_t *val);
+ iis328dq_i2_cfg_t *val);
-typedef enum {
+typedef enum
+{
IIS328DQ_INT2_PULSED = 0,
IIS328DQ_INT2_LATCHED = 1,
} iis328dq_lir2_t;
int32_t iis328dq_int2_notification_set(stmdev_ctx_t *ctx,
- iis328dq_lir2_t val);
+ iis328dq_lir2_t val);
int32_t iis328dq_int2_notification_get(stmdev_ctx_t *ctx,
- iis328dq_lir2_t *val);
+ iis328dq_lir2_t *val);
-typedef enum {
+typedef enum
+{
IIS328DQ_PUSH_PULL = 0,
IIS328DQ_OPEN_DRAIN = 1,
} iis328dq_pp_od_t;
-int32_t iis328dq_pin_mode_set(stmdev_ctx_t *ctx, iis328dq_pp_od_t val);
-int32_t iis328dq_pin_mode_get(stmdev_ctx_t *ctx, iis328dq_pp_od_t *val);
+int32_t iis328dq_pin_mode_set(stmdev_ctx_t *ctx,
+ iis328dq_pp_od_t val);
+int32_t iis328dq_pin_mode_get(stmdev_ctx_t *ctx,
+ iis328dq_pp_od_t *val);
-typedef enum {
+typedef enum
+{
IIS328DQ_ACTIVE_HIGH = 0,
IIS328DQ_ACTIVE_LOW = 1,
} iis328dq_ihl_t;
int32_t iis328dq_pin_polarity_set(stmdev_ctx_t *ctx,
- iis328dq_ihl_t val);
+ iis328dq_ihl_t val);
int32_t iis328dq_pin_polarity_get(stmdev_ctx_t *ctx,
- iis328dq_ihl_t *val);
+ iis328dq_ihl_t *val);
-typedef struct {
+typedef struct
+{
uint8_t int1_xlie : 1;
uint8_t int1_xhie : 1;
uint8_t int1_ylie : 1;
@@ -642,21 +687,22 @@ typedef struct {
uint8_t int1_zhie : 1;
} int1_on_th_conf_t;
int32_t iis328dq_int1_on_threshold_conf_set(stmdev_ctx_t *ctx,
- int1_on_th_conf_t val);
+ int1_on_th_conf_t val);
int32_t iis328dq_int1_on_threshold_conf_get(stmdev_ctx_t *ctx,
- int1_on_th_conf_t *val);
+ int1_on_th_conf_t *val);
-typedef enum {
+typedef enum
+{
IIS328DQ_INT1_ON_THRESHOLD_OR = 0,
IIS328DQ_INT1_ON_THRESHOLD_AND = 1,
} iis328dq_int1_aoi_t;
int32_t iis328dq_int1_on_threshold_mode_set(stmdev_ctx_t *ctx,
- iis328dq_int1_aoi_t val);
+ iis328dq_int1_aoi_t val);
int32_t iis328dq_int1_on_threshold_mode_get(stmdev_ctx_t *ctx,
- iis328dq_int1_aoi_t *val);
+ iis328dq_int1_aoi_t *val);
int32_t iis328dq_int1_src_get(stmdev_ctx_t *ctx,
- iis328dq_int1_src_t *val);
+ iis328dq_int1_src_t *val);
int32_t iis328dq_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis328dq_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -664,7 +710,8 @@ int32_t iis328dq_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t iis328dq_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis328dq_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef struct {
+typedef struct
+{
uint8_t int2_xlie : 1;
uint8_t int2_xhie : 1;
uint8_t int2_ylie : 1;
@@ -673,21 +720,22 @@ typedef struct {
uint8_t int2_zhie : 1;
} int2_on_th_conf_t;
int32_t iis328dq_int2_on_threshold_conf_set(stmdev_ctx_t *ctx,
- int2_on_th_conf_t val);
+ int2_on_th_conf_t val);
int32_t iis328dq_int2_on_threshold_conf_get(stmdev_ctx_t *ctx,
- int2_on_th_conf_t *val);
+ int2_on_th_conf_t *val);
-typedef enum {
+typedef enum
+{
IIS328DQ_INT2_ON_THRESHOLD_OR = 0,
IIS328DQ_INT2_ON_THRESHOLD_AND = 1,
} iis328dq_int2_aoi_t;
int32_t iis328dq_int2_on_threshold_mode_set(stmdev_ctx_t *ctx,
- iis328dq_int2_aoi_t val);
+ iis328dq_int2_aoi_t val);
int32_t iis328dq_int2_on_threshold_mode_get(stmdev_ctx_t *ctx,
- iis328dq_int2_aoi_t *val);
+ iis328dq_int2_aoi_t *val);
int32_t iis328dq_int2_src_get(stmdev_ctx_t *ctx,
- iis328dq_int2_src_t *val);
+ iis328dq_int2_src_t *val);
int32_t iis328dq_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis328dq_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -698,37 +746,41 @@ int32_t iis328dq_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t iis328dq_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis328dq_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS328DQ_6D_INT1_DISABLE = 0,
IIS328DQ_6D_INT1_MOVEMENT = 1,
IIS328DQ_6D_INT1_POSITION = 3,
} iis328dq_int1_6d_t;
int32_t iis328dq_int1_6d_mode_set(stmdev_ctx_t *ctx,
- iis328dq_int1_6d_t val);
+ iis328dq_int1_6d_t val);
int32_t iis328dq_int1_6d_mode_get(stmdev_ctx_t *ctx,
- iis328dq_int1_6d_t *val);
+ iis328dq_int1_6d_t *val);
int32_t iis328dq_int1_6d_src_get(stmdev_ctx_t *ctx,
- iis328dq_int1_src_t *val);
+ iis328dq_int1_src_t *val);
int32_t iis328dq_int1_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis328dq_int1_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis328dq_int1_6d_treshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS328DQ_6D_INT2_DISABLE = 0,
IIS328DQ_6D_INT2_MOVEMENT = 1,
IIS328DQ_6D_INT2_POSITION = 3,
} iis328dq_int2_6d_t;
int32_t iis328dq_int2_6d_mode_set(stmdev_ctx_t *ctx,
- iis328dq_int2_6d_t val);
+ iis328dq_int2_6d_t val);
int32_t iis328dq_int2_6d_mode_get(stmdev_ctx_t *ctx,
- iis328dq_int2_6d_t *val);
+ iis328dq_int2_6d_t *val);
int32_t iis328dq_int2_6d_src_get(stmdev_ctx_t *ctx,
- iis328dq_int2_src_t *val);
+ iis328dq_int2_src_t *val);
int32_t iis328dq_int2_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis328dq_int2_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis328dq_int2_6d_treshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
/**
*@}
diff --git a/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.c b/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.c
index c65e5327f854b20bac6248823594247860fbe571..356805d6a963afb9573e4967458c6198953ad065 100644
--- a/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.c
+++ b/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file iis3dhhc_reg.c
- * @author Sensors Software Solution Team
- * @brief IIS3DHHC driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file iis3dhhc_reg.c
+ * @author Sensors Software Solution Team
+ * @brief IIS3DHHC driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "iis3dhhc_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis3dhhc_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t iis3dhhc_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t iis3dhhc_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis3dhhc_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t iis3dhhc_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -77,7 +83,7 @@ int32_t iis3dhhc_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
*
*/
- /**
+/**
* @defgroup IIS3DHHC_Sensitivity
* @brief These functions convert raw-data into engineering units.
* @{
@@ -86,7 +92,7 @@ int32_t iis3dhhc_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
float_t iis3dhhc_from_lsb_to_mg(int16_t lsb)
{
- return ((float_t)lsb *0.076f);
+ return ((float_t)lsb * 0.076f);
}
float_t iis3dhhc_from_lsb_to_celsius(int16_t lsb)
@@ -120,10 +126,14 @@ int32_t iis3dhhc_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
iis3dhhc_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0){
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.bdu = val;
- ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
}
return ret;
@@ -137,12 +147,14 @@ int32_t iis3dhhc_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis3dhhc_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t iis3dhhc_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
iis3dhhc_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
*val = ctrl_reg1.bdu;
return ret;
@@ -156,15 +168,20 @@ int32_t iis3dhhc_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis3dhhc_data_rate_set(stmdev_ctx_t *ctx, iis3dhhc_norm_mod_en_t val)
+int32_t iis3dhhc_data_rate_set(stmdev_ctx_t *ctx,
+ iis3dhhc_norm_mod_en_t val)
{
iis3dhhc_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0){
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.norm_mod_en = (uint8_t)val;
- ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
}
return ret;
@@ -178,20 +195,25 @@ int32_t iis3dhhc_data_rate_set(stmdev_ctx_t *ctx, iis3dhhc_norm_mod_en_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis3dhhc_data_rate_get(stmdev_ctx_t *ctx, iis3dhhc_norm_mod_en_t *val)
+int32_t iis3dhhc_data_rate_get(stmdev_ctx_t *ctx,
+ iis3dhhc_norm_mod_en_t *val)
{
iis3dhhc_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
- switch (ctrl_reg1.norm_mod_en){
+ switch (ctrl_reg1.norm_mod_en)
+ {
case IIS3DHHC_POWER_DOWN:
*val = IIS3DHHC_POWER_DOWN;
break;
+
case IIS3DHHC_1kHz1:
*val = IIS3DHHC_1kHz1;
break;
+
default:
*val = IIS3DHHC_POWER_DOWN;
break;
@@ -213,10 +235,14 @@ int32_t iis3dhhc_offset_temp_comp_set(stmdev_ctx_t *ctx, uint8_t val)
iis3dhhc_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0){
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.off_tcomp_en = val;
- ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
}
return ret;
@@ -235,7 +261,8 @@ int32_t iis3dhhc_offset_temp_comp_get(stmdev_ctx_t *ctx, uint8_t *val)
iis3dhhc_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
*val = ctrl_reg4.off_tcomp_en;
return ret;
@@ -256,7 +283,8 @@ int32_t iis3dhhc_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
ret = iis3dhhc_read_reg(ctx, IIS3DHHC_OUT_TEMP_L, buff, 2);
*val = (int16_t)buff[1];
- *val = (*val * 256) + (int16_t)buff[0];
+ *val = (*val * 256) + (int16_t)buff[0];
+
return ret;
}
@@ -275,11 +303,11 @@ int32_t iis3dhhc_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
ret = iis3dhhc_read_reg(ctx, IIS3DHHC_OUT_X_L_XL, buff, 6);
val[0] = (int16_t)buff[1];
- val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
- val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
val[2] = (int16_t)buff[5];
- val[2] = (val[2] * 256) + (int16_t)buff[4];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
return ret;
}
@@ -297,7 +325,7 @@ int32_t iis3dhhc_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
iis3dhhc_status_t status;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_STATUS, (uint8_t*)&status, 1);
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_STATUS, (uint8_t *)&status, 1);
*val = status.zyxda;
return ret;
@@ -316,7 +344,7 @@ int32_t iis3dhhc_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
iis3dhhc_status_t status;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_STATUS, (uint8_t*)&status, 1);
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_STATUS, (uint8_t *)&status, 1);
*val = status.zyxor;
return ret;
@@ -345,7 +373,9 @@ int32_t iis3dhhc_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t iis3dhhc_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = iis3dhhc_read_reg(ctx, IIS3DHHC_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -362,10 +392,14 @@ int32_t iis3dhhc_reset_set(stmdev_ctx_t *ctx, uint8_t val)
iis3dhhc_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0){
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.sw_reset = val;
- ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
}
return ret;
@@ -384,7 +418,8 @@ int32_t iis3dhhc_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
iis3dhhc_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
*val = ctrl_reg1.sw_reset;
return ret;
@@ -403,10 +438,14 @@ int32_t iis3dhhc_boot_set(stmdev_ctx_t *ctx, uint8_t val)
iis3dhhc_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0){
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.boot = val;
- ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
}
return ret;
@@ -425,7 +464,8 @@ int32_t iis3dhhc_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
iis3dhhc_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
*val = ctrl_reg1.boot;
return ret;
@@ -444,10 +484,14 @@ int32_t iis3dhhc_self_test_set(stmdev_ctx_t *ctx, iis3dhhc_st_t val)
iis3dhhc_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0){
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.st = (uint8_t)val;
- ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
}
return ret;
@@ -466,18 +510,23 @@ int32_t iis3dhhc_self_test_get(stmdev_ctx_t *ctx, iis3dhhc_st_t *val)
iis3dhhc_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
- switch (ctrl_reg4.st){
+ switch (ctrl_reg4.st)
+ {
case IIS3DHHC_ST_DISABLE:
*val = IIS3DHHC_ST_DISABLE;
break;
+
case IIS3DHHC_ST_POSITIVE:
*val = IIS3DHHC_ST_POSITIVE;
break;
+
case IIS3DHHC_ST_NEGATIVE:
*val = IIS3DHHC_ST_NEGATIVE;
break;
+
default:
*val = IIS3DHHC_ST_DISABLE;
break;
@@ -494,15 +543,20 @@ int32_t iis3dhhc_self_test_get(stmdev_ctx_t *ctx, iis3dhhc_st_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis3dhhc_filter_config_set(stmdev_ctx_t *ctx, iis3dhhc_dsp_t val)
+int32_t iis3dhhc_filter_config_set(stmdev_ctx_t *ctx,
+ iis3dhhc_dsp_t val)
{
iis3dhhc_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0){
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.dsp = (uint8_t)val;
- ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
}
return ret;
@@ -516,26 +570,33 @@ int32_t iis3dhhc_filter_config_set(stmdev_ctx_t *ctx, iis3dhhc_dsp_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis3dhhc_filter_config_get(stmdev_ctx_t *ctx, iis3dhhc_dsp_t *val)
+int32_t iis3dhhc_filter_config_get(stmdev_ctx_t *ctx,
+ iis3dhhc_dsp_t *val)
{
iis3dhhc_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
- switch (ctrl_reg4.dsp){
+ switch (ctrl_reg4.dsp)
+ {
case IIS3DHHC_LINEAR_PHASE_440Hz:
*val = IIS3DHHC_LINEAR_PHASE_440Hz;
break;
+
case IIS3DHHC_LINEAR_PHASE_235Hz:
*val = IIS3DHHC_LINEAR_PHASE_235Hz;
break;
+
case IIS3DHHC_NO_LINEAR_PHASE_440Hz:
*val = IIS3DHHC_NO_LINEAR_PHASE_440Hz;
break;
+
case IIS3DHHC_NO_LINEAR_PHASE_235Hz:
*val = IIS3DHHC_NO_LINEAR_PHASE_235Hz;
break;
+
default:
*val = IIS3DHHC_LINEAR_PHASE_440Hz;
break;
@@ -555,7 +616,9 @@ int32_t iis3dhhc_filter_config_get(stmdev_ctx_t *ctx, iis3dhhc_dsp_t *val)
int32_t iis3dhhc_status_get(stmdev_ctx_t *ctx, iis3dhhc_status_t *val)
{
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_STATUS, (uint8_t*) val, 1);
+
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_STATUS, (uint8_t *) val, 1);
+
return ret;
}
@@ -585,10 +648,14 @@ int32_t iis3dhhc_drdy_notification_mode_set(stmdev_ctx_t *ctx,
iis3dhhc_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0){
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.drdy_pulse = (uint8_t)val;
- ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
}
return ret;
@@ -608,15 +675,19 @@ int32_t iis3dhhc_drdy_notification_mode_get(stmdev_ctx_t *ctx,
iis3dhhc_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
- switch (ctrl_reg1.drdy_pulse){
+ switch (ctrl_reg1.drdy_pulse)
+ {
case IIS3DHHC_LATCHED:
*val = IIS3DHHC_LATCHED;
break;
+
case IIS3DHHC_PULSED:
*val = IIS3DHHC_PULSED;
break;
+
default:
*val = IIS3DHHC_LATCHED;
break;
@@ -634,15 +705,20 @@ int32_t iis3dhhc_drdy_notification_mode_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis3dhhc_int1_mode_set(stmdev_ctx_t *ctx, iis3dhhc_int1_ext_t val)
+int32_t iis3dhhc_int1_mode_set(stmdev_ctx_t *ctx,
+ iis3dhhc_int1_ext_t val)
{
iis3dhhc_int1_ctrl_t int1_ctrl;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
- if(ret == 0){
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL,
+ (uint8_t *)&int1_ctrl, 1);
+
+ if (ret == 0)
+ {
int1_ctrl.int1_ext = (uint8_t)val;
- ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
+ ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT1_CTRL,
+ (uint8_t *)&int1_ctrl, 1);
}
return ret;
@@ -657,20 +733,25 @@ int32_t iis3dhhc_int1_mode_set(stmdev_ctx_t *ctx, iis3dhhc_int1_ext_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis3dhhc_int1_mode_get(stmdev_ctx_t *ctx, iis3dhhc_int1_ext_t *val)
+int32_t iis3dhhc_int1_mode_get(stmdev_ctx_t *ctx,
+ iis3dhhc_int1_ext_t *val)
{
iis3dhhc_int1_ctrl_t int1_ctrl;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL,
+ (uint8_t *)&int1_ctrl, 1);
- switch (int1_ctrl.int1_ext){
+ switch (int1_ctrl.int1_ext)
+ {
case IIS3DHHC_PIN_AS_INTERRUPT:
*val = IIS3DHHC_PIN_AS_INTERRUPT;
break;
+
case IIS3DHHC_PIN_AS_TRIGGER:
*val = IIS3DHHC_PIN_AS_TRIGGER;
break;
+
default:
*val = IIS3DHHC_PIN_AS_INTERRUPT;
break;
@@ -688,15 +769,19 @@ int32_t iis3dhhc_int1_mode_get(stmdev_ctx_t *ctx, iis3dhhc_int1_ext_t *val)
*
*/
int32_t iis3dhhc_fifo_threshold_on_int1_set(stmdev_ctx_t *ctx,
- uint8_t val)
+ uint8_t val)
{
iis3dhhc_int1_ctrl_t int1_ctrl;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
- if(ret == 0){
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL,
+ (uint8_t *)&int1_ctrl, 1);
+
+ if (ret == 0)
+ {
int1_ctrl.int1_fth = val;
- ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
+ ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT1_CTRL,
+ (uint8_t *)&int1_ctrl, 1);
}
return ret;
@@ -710,12 +795,14 @@ int32_t iis3dhhc_fifo_threshold_on_int1_set(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis3dhhc_fifo_threshold_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t iis3dhhc_fifo_threshold_on_int1_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
iis3dhhc_int1_ctrl_t int1_ctrl;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL,
+ (uint8_t *)&int1_ctrl, 1);
*val = int1_ctrl.int1_fth;
return ret;
@@ -734,10 +821,14 @@ int32_t iis3dhhc_fifo_full_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
iis3dhhc_int1_ctrl_t int1_ctrl;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
- if(ret == 0){
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL,
+ (uint8_t *)&int1_ctrl, 1);
+
+ if (ret == 0)
+ {
int1_ctrl.int1_fss5 = val;
- ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
+ ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT1_CTRL,
+ (uint8_t *)&int1_ctrl, 1);
}
return ret;
@@ -751,12 +842,14 @@ int32_t iis3dhhc_fifo_full_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis3dhhc_fifo_full_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t iis3dhhc_fifo_full_on_int1_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
iis3dhhc_int1_ctrl_t int1_ctrl;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL,
+ (uint8_t *)&int1_ctrl, 1);
*val = int1_ctrl.int1_fss5;
return ret;
@@ -775,10 +868,14 @@ int32_t iis3dhhc_fifo_ovr_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
iis3dhhc_int1_ctrl_t int1_ctrl;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
- if(ret == 0){
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL,
+ (uint8_t *)&int1_ctrl, 1);
+
+ if (ret == 0)
+ {
int1_ctrl.int1_ovr = val;
- ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
+ ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT1_CTRL,
+ (uint8_t *)&int1_ctrl, 1);
}
return ret;
@@ -797,7 +894,8 @@ int32_t iis3dhhc_fifo_ovr_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
iis3dhhc_int1_ctrl_t int1_ctrl;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL,
+ (uint8_t *)&int1_ctrl, 1);
*val = int1_ctrl.int1_ovr;
return ret;
@@ -816,10 +914,14 @@ int32_t iis3dhhc_boot_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
iis3dhhc_int1_ctrl_t int1_ctrl;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
- if(ret == 0){
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL,
+ (uint8_t *)&int1_ctrl, 1);
+
+ if (ret == 0)
+ {
int1_ctrl.int1_boot = val;
- ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
+ ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT1_CTRL,
+ (uint8_t *)&int1_ctrl, 1);
}
return ret;
@@ -838,7 +940,8 @@ int32_t iis3dhhc_boot_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
iis3dhhc_int1_ctrl_t int1_ctrl;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL,
+ (uint8_t *)&int1_ctrl, 1);
*val = int1_ctrl.int1_boot;
return ret;
@@ -857,10 +960,14 @@ int32_t iis3dhhc_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
iis3dhhc_int1_ctrl_t int1_ctrl;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
- if(ret == 0){
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL,
+ (uint8_t *)&int1_ctrl, 1);
+
+ if (ret == 0)
+ {
int1_ctrl.int1_drdy = val;
- ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
+ ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT1_CTRL,
+ (uint8_t *)&int1_ctrl, 1);
}
return ret;
@@ -879,7 +986,8 @@ int32_t iis3dhhc_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
iis3dhhc_int1_ctrl_t int1_ctrl;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL,
+ (uint8_t *)&int1_ctrl, 1);
*val = int1_ctrl.int1_drdy;
return ret;
@@ -893,15 +1001,20 @@ int32_t iis3dhhc_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis3dhhc_fifo_threshold_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t iis3dhhc_fifo_threshold_on_int2_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
iis3dhhc_int2_ctrl_t int2_ctrl;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
- if(ret == 0){
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL,
+ (uint8_t *)&int2_ctrl, 1);
+
+ if (ret == 0)
+ {
int2_ctrl.int2_fth = val;
- ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+ ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT2_CTRL,
+ (uint8_t *)&int2_ctrl, 1);
}
return ret;
@@ -915,12 +1028,14 @@ int32_t iis3dhhc_fifo_threshold_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis3dhhc_fifo_threshold_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t iis3dhhc_fifo_threshold_on_int2_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
iis3dhhc_int2_ctrl_t int2_ctrl;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL,
+ (uint8_t *)&int2_ctrl, 1);
*val = int2_ctrl.int2_fth;
return ret;
@@ -939,10 +1054,14 @@ int32_t iis3dhhc_fifo_full_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
iis3dhhc_int2_ctrl_t int2_ctrl;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
- if(ret == 0){
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL,
+ (uint8_t *)&int2_ctrl, 1);
+
+ if (ret == 0)
+ {
int2_ctrl.int2_fss5 = val;
- ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+ ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT2_CTRL,
+ (uint8_t *)&int2_ctrl, 1);
}
return ret;
@@ -956,12 +1075,14 @@ int32_t iis3dhhc_fifo_full_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis3dhhc_fifo_full_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t iis3dhhc_fifo_full_on_int2_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
iis3dhhc_int2_ctrl_t int2_ctrl;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL,
+ (uint8_t *)&int2_ctrl, 1);
*val = int2_ctrl.int2_fss5;
return ret;
@@ -980,10 +1101,14 @@ int32_t iis3dhhc_fifo_ovr_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
iis3dhhc_int2_ctrl_t int2_ctrl;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
- if(ret == 0){
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL,
+ (uint8_t *)&int2_ctrl, 1);
+
+ if (ret == 0)
+ {
int2_ctrl.int2_ovr = val;
- ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+ ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT2_CTRL,
+ (uint8_t *)&int2_ctrl, 1);
}
return ret;
@@ -1002,7 +1127,8 @@ int32_t iis3dhhc_fifo_ovr_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val)
iis3dhhc_int2_ctrl_t int2_ctrl;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL,
+ (uint8_t *)&int2_ctrl, 1);
*val = int2_ctrl.int2_ovr;
return ret;
@@ -1021,10 +1147,14 @@ int32_t iis3dhhc_boot_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
iis3dhhc_int2_ctrl_t int2_ctrl;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
- if(ret == 0){
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL,
+ (uint8_t *)&int2_ctrl, 1);
+
+ if (ret == 0)
+ {
int2_ctrl.int2_boot = val;
- ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+ ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT2_CTRL,
+ (uint8_t *)&int2_ctrl, 1);
}
return ret;
@@ -1043,7 +1173,8 @@ int32_t iis3dhhc_boot_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val)
iis3dhhc_int2_ctrl_t int2_ctrl;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL,
+ (uint8_t *)&int2_ctrl, 1);
*val = int2_ctrl.int2_boot;
return ret;
@@ -1062,10 +1193,14 @@ int32_t iis3dhhc_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
iis3dhhc_int2_ctrl_t int2_ctrl;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
- if(ret == 0){
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL,
+ (uint8_t *)&int2_ctrl, 1);
+
+ if (ret == 0)
+ {
int2_ctrl.int2_drdy = val;
- ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+ ret = iis3dhhc_write_reg(ctx, IIS3DHHC_INT2_CTRL,
+ (uint8_t *)&int2_ctrl, 1);
}
return ret;
@@ -1084,7 +1219,8 @@ int32_t iis3dhhc_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val)
iis3dhhc_int2_ctrl_t int2_ctrl;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL,
+ (uint8_t *)&int2_ctrl, 1);
*val = int2_ctrl.int2_drdy;
return ret;
@@ -1103,10 +1239,14 @@ int32_t iis3dhhc_pin_mode_set(stmdev_ctx_t *ctx, iis3dhhc_pp_od_t val)
iis3dhhc_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0){
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.pp_od = (uint8_t)val;
- ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
}
return ret;
@@ -1120,26 +1260,33 @@ int32_t iis3dhhc_pin_mode_set(stmdev_ctx_t *ctx, iis3dhhc_pp_od_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis3dhhc_pin_mode_get(stmdev_ctx_t *ctx, iis3dhhc_pp_od_t *val)
+int32_t iis3dhhc_pin_mode_get(stmdev_ctx_t *ctx,
+ iis3dhhc_pp_od_t *val)
{
iis3dhhc_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
- switch (ctrl_reg4.pp_od){
+ switch (ctrl_reg4.pp_od)
+ {
case IIS3DHHC_ALL_PUSH_PULL:
*val = IIS3DHHC_ALL_PUSH_PULL;
break;
+
case IIS3DHHC_INT1_OD_INT2_PP:
*val = IIS3DHHC_INT1_OD_INT2_PP;
break;
+
case IIS3DHHC_INT1_PP_INT2_OD:
*val = IIS3DHHC_INT1_PP_INT2_OD;
break;
+
case IIS3DHHC_ALL_OPEN_DRAIN:
*val = IIS3DHHC_ALL_OPEN_DRAIN;
break;
+
default:
*val = IIS3DHHC_ALL_PUSH_PULL;
break;
@@ -1174,10 +1321,14 @@ int32_t iis3dhhc_fifo_set(stmdev_ctx_t *ctx, uint8_t val)
iis3dhhc_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0){
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.fifo_en = val;
- ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
}
return ret;
@@ -1196,7 +1347,8 @@ int32_t iis3dhhc_fifo_get(stmdev_ctx_t *ctx, uint8_t *val)
iis3dhhc_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
*val = ctrl_reg4.fifo_en;
return ret;
@@ -1218,10 +1370,14 @@ int32_t iis3dhhc_fifo_block_spi_hs_set(stmdev_ctx_t *ctx, uint8_t val)
iis3dhhc_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if(ret == 0){
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.fifo_spi_hs_on = val;
- ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
}
return ret;
@@ -1238,12 +1394,14 @@ int32_t iis3dhhc_fifo_block_spi_hs_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis3dhhc_fifo_block_spi_hs_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t iis3dhhc_fifo_block_spi_hs_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
iis3dhhc_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
*val = ctrl_reg5.fifo_spi_hs_on;
return ret;
@@ -1262,10 +1420,14 @@ int32_t iis3dhhc_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
iis3dhhc_fifo_ctrl_t fifo_ctrl;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
- if(ret == 0){
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_FIFO_CTRL,
+ (uint8_t *)&fifo_ctrl, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl.fth = val;
- ret = iis3dhhc_write_reg(ctx, IIS3DHHC_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
+ ret = iis3dhhc_write_reg(ctx, IIS3DHHC_FIFO_CTRL,
+ (uint8_t *)&fifo_ctrl, 1);
}
return ret;
@@ -1284,7 +1446,8 @@ int32_t iis3dhhc_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
iis3dhhc_fifo_ctrl_t fifo_ctrl;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_FIFO_CTRL,
+ (uint8_t *)&fifo_ctrl, 1);
*val = fifo_ctrl.fth;
return ret;
@@ -1298,15 +1461,20 @@ int32_t iis3dhhc_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis3dhhc_fifo_mode_set(stmdev_ctx_t *ctx, iis3dhhc_fmode_t val)
+int32_t iis3dhhc_fifo_mode_set(stmdev_ctx_t *ctx,
+ iis3dhhc_fmode_t val)
{
iis3dhhc_fifo_ctrl_t fifo_ctrl;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
- if(ret == 0){
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_FIFO_CTRL,
+ (uint8_t *)&fifo_ctrl, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl.fmode = (uint8_t)val;
- ret = iis3dhhc_write_reg(ctx, IIS3DHHC_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
+ ret = iis3dhhc_write_reg(ctx, IIS3DHHC_FIFO_CTRL,
+ (uint8_t *)&fifo_ctrl, 1);
}
return ret;
@@ -1320,29 +1488,37 @@ int32_t iis3dhhc_fifo_mode_set(stmdev_ctx_t *ctx, iis3dhhc_fmode_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis3dhhc_fifo_mode_get(stmdev_ctx_t *ctx, iis3dhhc_fmode_t *val)
+int32_t iis3dhhc_fifo_mode_get(stmdev_ctx_t *ctx,
+ iis3dhhc_fmode_t *val)
{
iis3dhhc_fifo_ctrl_t fifo_ctrl;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_FIFO_CTRL,
+ (uint8_t *)&fifo_ctrl, 1);
- switch (fifo_ctrl.fmode){
+ switch (fifo_ctrl.fmode)
+ {
case IIS3DHHC_BYPASS_MODE:
*val = IIS3DHHC_BYPASS_MODE;
break;
+
case IIS3DHHC_FIFO_MODE:
*val = IIS3DHHC_FIFO_MODE;
break;
+
case IIS3DHHC_STREAM_TO_FIFO_MODE:
*val = IIS3DHHC_STREAM_TO_FIFO_MODE;
break;
+
case IIS3DHHC_BYPASS_TO_STREAM_MODE:
*val = IIS3DHHC_BYPASS_TO_STREAM_MODE;
break;
+
case IIS3DHHC_DYNAMIC_STREAM_MODE:
*val = IIS3DHHC_DYNAMIC_STREAM_MODE;
break;
+
default:
*val = IIS3DHHC_BYPASS_MODE;
break;
@@ -1359,10 +1535,13 @@ int32_t iis3dhhc_fifo_mode_get(stmdev_ctx_t *ctx, iis3dhhc_fmode_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis3dhhc_fifo_status_get(stmdev_ctx_t *ctx, iis3dhhc_fifo_src_t *val)
+int32_t iis3dhhc_fifo_status_get(stmdev_ctx_t *ctx,
+ iis3dhhc_fifo_src_t *val)
{
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_FIFO_SRC, (uint8_t*) val, 1);
+
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_FIFO_SRC, (uint8_t *) val, 1);
+
return ret;
}
@@ -1379,7 +1558,7 @@ int32_t iis3dhhc_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
iis3dhhc_fifo_src_t fifo_src;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_FIFO_SRC, (uint8_t*)&fifo_src, 1);
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_FIFO_SRC, (uint8_t *)&fifo_src, 1);
*val = fifo_src.fss;
return ret;
@@ -1398,7 +1577,7 @@ int32_t iis3dhhc_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
iis3dhhc_fifo_src_t fifo_src;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_FIFO_SRC, (uint8_t*)&fifo_src, 1);
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_FIFO_SRC, (uint8_t *)&fifo_src, 1);
*val = fifo_src.ovrn;
return ret;
@@ -1417,7 +1596,7 @@ int32_t iis3dhhc_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
iis3dhhc_fifo_src_t fifo_src;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_FIFO_SRC, (uint8_t*)&fifo_src, 1);
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_FIFO_SRC, (uint8_t *)&fifo_src, 1);
*val = fifo_src.fth;
return ret;
@@ -1450,10 +1629,14 @@ int32_t iis3dhhc_auto_add_inc_set(stmdev_ctx_t *ctx, uint8_t val)
iis3dhhc_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0){
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.if_add_inc = val;
- ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = iis3dhhc_write_reg(ctx, IIS3DHHC_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
}
return ret;
@@ -1473,7 +1656,8 @@ int32_t iis3dhhc_auto_add_inc_get(stmdev_ctx_t *ctx, uint8_t *val)
iis3dhhc_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
*val = ctrl_reg1.if_add_inc;
return ret;
diff --git a/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.h b/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.h
index 941291fcce714c13b4c7d751996737181ff7663c..db5fbb49ffe5933f35916ee8355169f9d165ebce 100644
--- a/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.h
+++ b/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.h
@@ -1,29 +1,29 @@
-/*
- ******************************************************************************
- * @file iis3dhhc_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * iis3dhhc_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file iis3dhhc_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * iis3dhhc_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef IIS3DHHC_REGS_H
#define IIS3DHHC_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -75,7 +75,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -108,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -132,7 +134,7 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
+ * You can create a sensor configuration by your own or using
* Unico / Unicleo tools available on STMicroelectronics
* web site.
*
@@ -140,7 +142,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -171,7 +174,8 @@ typedef struct {
*/
#define IIS3DHHC_WHO_AM_I 0x0FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 7;
uint8_t asic_id : 1;
@@ -182,7 +186,8 @@ typedef struct {
} iis3dhhc_id_reg_t;
#define IIS3DHHC_CTRL_REG1 0x20U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bdu : 1;
uint8_t drdy_pulse : 1;
@@ -203,7 +208,8 @@ typedef struct {
} iis3dhhc_ctrl_reg1_t;
#define IIS3DHHC_INT1_CTRL 0x21U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t int1_ext : 1;
@@ -224,7 +230,8 @@ typedef struct {
} iis3dhhc_int1_ctrl_t;
#define IIS3DHHC_INT2_CTRL 0x22U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t int2_fth : 1;
@@ -243,7 +250,8 @@ typedef struct {
} iis3dhhc_int2_ctrl_t;
#define IIS3DHHC_CTRL_REG4 0x23U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t off_tcomp_en : 1;
uint8_t fifo_en : 1;
@@ -260,7 +268,8 @@ typedef struct {
} iis3dhhc_ctrl_reg4_t;
#define IIS3DHHC_CTRL_REG5 0x24U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fifo_spi_hs_on : 1;
uint8_t not_used_01 : 7;
@@ -273,7 +282,8 @@ typedef struct {
#define IIS3DHHC_OUT_TEMP_L 0x25U
#define IIS3DHHC_OUT_TEMP_H 0x26U
#define IIS3DHHC_STATUS 0x27U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xda : 1;
uint8_t yda : 1;
@@ -302,7 +312,8 @@ typedef struct {
#define IIS3DHHC_OUT_Z_L_XL 0x2CU
#define IIS3DHHC_OUT_Z_H_XL 0x2DU
#define IIS3DHHC_FIFO_CTRL 0x2EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fth : 5;
uint8_t fmode : 3;
@@ -313,7 +324,8 @@ typedef struct {
} iis3dhhc_fifo_ctrl_t;
#define IIS3DHHC_FIFO_SRC 0x2FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fss : 6;
uint8_t ovrn : 1;
@@ -327,9 +339,9 @@ typedef struct {
/**
* @defgroup IIS3DHHC_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -337,7 +349,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
iis3dhhc_id_reg_t id_reg;
iis3dhhc_ctrl_reg1_t ctrl_reg1;
iis3dhhc_int1_ctrl_t int1_ctrl;
@@ -356,18 +369,23 @@ typedef union{
*
*/
-int32_t iis3dhhc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t iis3dhhc_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t iis3dhhc_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t iis3dhhc_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
float_t iis3dhhc_from_lsb_to_mg(int16_t lsb);
float_t iis3dhhc_from_lsb_to_celsius(int16_t lsb);
-int32_t iis3dhhc_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis3dhhc_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis3dhhc_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t iis3dhhc_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS3DHHC_POWER_DOWN = 0,
IIS3DHHC_1kHz1 = 1,
} iis3dhhc_norm_mod_en_t;
@@ -377,11 +395,13 @@ int32_t iis3dhhc_data_rate_get(stmdev_ctx_t *ctx,
iis3dhhc_norm_mod_en_t *val);
int32_t iis3dhhc_offset_temp_comp_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis3dhhc_offset_temp_comp_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis3dhhc_offset_temp_comp_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t iis3dhhc_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val);
-int32_t iis3dhhc_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t iis3dhhc_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
int32_t iis3dhhc_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -395,7 +415,8 @@ int32_t iis3dhhc_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t iis3dhhc_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis3dhhc_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS3DHHC_ST_DISABLE = 0,
IIS3DHHC_ST_POSITIVE = 1,
IIS3DHHC_ST_NEGATIVE = 2,
@@ -403,18 +424,23 @@ typedef enum {
int32_t iis3dhhc_self_test_set(stmdev_ctx_t *ctx, iis3dhhc_st_t val);
int32_t iis3dhhc_self_test_get(stmdev_ctx_t *ctx, iis3dhhc_st_t *val);
-typedef enum {
+typedef enum
+{
IIS3DHHC_LINEAR_PHASE_440Hz = 0,
IIS3DHHC_LINEAR_PHASE_235Hz = 1,
IIS3DHHC_NO_LINEAR_PHASE_440Hz = 2,
IIS3DHHC_NO_LINEAR_PHASE_235Hz = 3,
} iis3dhhc_dsp_t;
-int32_t iis3dhhc_filter_config_set(stmdev_ctx_t *ctx, iis3dhhc_dsp_t val);
-int32_t iis3dhhc_filter_config_get(stmdev_ctx_t *ctx, iis3dhhc_dsp_t *val);
+int32_t iis3dhhc_filter_config_set(stmdev_ctx_t *ctx,
+ iis3dhhc_dsp_t val);
+int32_t iis3dhhc_filter_config_get(stmdev_ctx_t *ctx,
+ iis3dhhc_dsp_t *val);
-int32_t iis3dhhc_status_get(stmdev_ctx_t *ctx, iis3dhhc_status_t *val);
+int32_t iis3dhhc_status_get(stmdev_ctx_t *ctx,
+ iis3dhhc_status_t *val);
-typedef enum {
+typedef enum
+{
IIS3DHHC_LATCHED = 0,
IIS3DHHC_PULSED = 1,
} iis3dhhc_drdy_pulse_t;
@@ -423,23 +449,29 @@ int32_t iis3dhhc_drdy_notification_mode_set(stmdev_ctx_t *ctx,
int32_t iis3dhhc_drdy_notification_mode_get(stmdev_ctx_t *ctx,
iis3dhhc_drdy_pulse_t *val);
-typedef enum {
+typedef enum
+{
IIS3DHHC_PIN_AS_INTERRUPT = 0,
IIS3DHHC_PIN_AS_TRIGGER = 1,
} iis3dhhc_int1_ext_t;
-int32_t iis3dhhc_int1_mode_set(stmdev_ctx_t *ctx, iis3dhhc_int1_ext_t val);
-int32_t iis3dhhc_int1_mode_get(stmdev_ctx_t *ctx, iis3dhhc_int1_ext_t *val);
+int32_t iis3dhhc_int1_mode_set(stmdev_ctx_t *ctx,
+ iis3dhhc_int1_ext_t val);
+int32_t iis3dhhc_int1_mode_get(stmdev_ctx_t *ctx,
+ iis3dhhc_int1_ext_t *val);
int32_t iis3dhhc_fifo_threshold_on_int1_set(stmdev_ctx_t *ctx,
uint8_t val);
int32_t iis3dhhc_fifo_threshold_on_int1_get(stmdev_ctx_t *ctx,
uint8_t *val);
-int32_t iis3dhhc_fifo_full_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis3dhhc_fifo_full_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis3dhhc_fifo_full_on_int1_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t iis3dhhc_fifo_full_on_int1_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t iis3dhhc_fifo_ovr_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis3dhhc_fifo_ovr_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis3dhhc_fifo_ovr_on_int1_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t iis3dhhc_boot_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis3dhhc_boot_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -452,11 +484,14 @@ int32_t iis3dhhc_fifo_threshold_on_int2_set(stmdev_ctx_t *ctx,
int32_t iis3dhhc_fifo_threshold_on_int2_get(stmdev_ctx_t *ctx,
uint8_t *val);
-int32_t iis3dhhc_fifo_full_on_int2_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis3dhhc_fifo_full_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis3dhhc_fifo_full_on_int2_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t iis3dhhc_fifo_full_on_int2_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t iis3dhhc_fifo_ovr_on_int2_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis3dhhc_fifo_ovr_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis3dhhc_fifo_ovr_on_int2_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t iis3dhhc_boot_on_int2_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis3dhhc_boot_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -464,33 +499,41 @@ int32_t iis3dhhc_boot_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t iis3dhhc_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis3dhhc_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS3DHHC_ALL_PUSH_PULL = 0,
IIS3DHHC_INT1_OD_INT2_PP = 1,
IIS3DHHC_INT1_PP_INT2_OD = 2,
IIS3DHHC_ALL_OPEN_DRAIN = 3,
} iis3dhhc_pp_od_t;
-int32_t iis3dhhc_pin_mode_set(stmdev_ctx_t *ctx, iis3dhhc_pp_od_t val);
-int32_t iis3dhhc_pin_mode_get(stmdev_ctx_t *ctx, iis3dhhc_pp_od_t *val);
+int32_t iis3dhhc_pin_mode_set(stmdev_ctx_t *ctx,
+ iis3dhhc_pp_od_t val);
+int32_t iis3dhhc_pin_mode_get(stmdev_ctx_t *ctx,
+ iis3dhhc_pp_od_t *val);
int32_t iis3dhhc_fifo_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis3dhhc_fifo_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t iis3dhhc_fifo_block_spi_hs_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis3dhhc_fifo_block_spi_hs_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis3dhhc_fifo_block_spi_hs_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t iis3dhhc_fifo_block_spi_hs_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t iis3dhhc_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis3dhhc_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS3DHHC_BYPASS_MODE = 0,
IIS3DHHC_FIFO_MODE = 1,
IIS3DHHC_STREAM_TO_FIFO_MODE = 3,
IIS3DHHC_BYPASS_TO_STREAM_MODE = 4,
IIS3DHHC_DYNAMIC_STREAM_MODE = 6,
} iis3dhhc_fmode_t;
-int32_t iis3dhhc_fifo_mode_set(stmdev_ctx_t *ctx, iis3dhhc_fmode_t val);
-int32_t iis3dhhc_fifo_mode_get(stmdev_ctx_t *ctx, iis3dhhc_fmode_t *val);
+int32_t iis3dhhc_fifo_mode_set(stmdev_ctx_t *ctx,
+ iis3dhhc_fmode_t val);
+int32_t iis3dhhc_fifo_mode_get(stmdev_ctx_t *ctx,
+ iis3dhhc_fmode_t *val);
int32_t iis3dhhc_fifo_status_get(stmdev_ctx_t *ctx,
iis3dhhc_fifo_src_t *val);
diff --git a/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.c b/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.c
index 8489b6e1fcea7d86ea6de1c26fbe5041a8e77a4a..4c6a77d6d0434826d697eecadf62a444cce2d8d4 100644
--- a/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.c
+++ b/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file iis3dwb_reg.c
- * @author Sensors Software Solution Team
- * @brief IIS3DWB driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file iis3dwb_reg.c
+ * @author Sensors Software Solution Team
+ * @brief IIS3DWB driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "iis3dwb_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis3dwb_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t iis3dwb_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t iis3dwb_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t iis3dwb_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t iis3dwb_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -136,17 +142,20 @@ float_t iis3dwb_from_lsb_to_nsec(int32_t lsb)
*
*/
int32_t iis3dwb_xl_full_scale_set(stmdev_ctx_t *ctx,
- iis3dwb_fs_xl_t val)
+ iis3dwb_fs_xl_t val)
{
iis3dwb_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
ctrl1_xl.fs_xl = (uint8_t)val;
ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
+ (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -159,29 +168,36 @@ int32_t iis3dwb_xl_full_scale_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis3dwb_xl_full_scale_get(stmdev_ctx_t *ctx,
- iis3dwb_fs_xl_t *val)
+ iis3dwb_fs_xl_t *val)
{
iis3dwb_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- switch (ctrl1_xl.fs_xl){
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ switch (ctrl1_xl.fs_xl)
+ {
case IIS3DWB_2g:
*val = IIS3DWB_2g;
break;
+
case IIS3DWB_16g:
*val = IIS3DWB_16g;
break;
+
case IIS3DWB_4g:
*val = IIS3DWB_4g;
break;
+
case IIS3DWB_8g:
*val = IIS3DWB_8g;
break;
+
default:
*val = IIS3DWB_2g;
break;
}
+
return ret;
}
@@ -194,17 +210,20 @@ int32_t iis3dwb_xl_full_scale_get(stmdev_ctx_t *ctx,
*
*/
int32_t iis3dwb_xl_data_rate_set(stmdev_ctx_t *ctx,
- iis3dwb_odr_xl_t val)
+ iis3dwb_odr_xl_t val)
{
iis3dwb_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
- ctrl1_xl.xl_en= (uint8_t)val;
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl1_xl.xl_en = (uint8_t)val;
ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
+ (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -217,23 +236,28 @@ int32_t iis3dwb_xl_data_rate_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis3dwb_xl_data_rate_get(stmdev_ctx_t *ctx,
- iis3dwb_odr_xl_t *val)
+ iis3dwb_odr_xl_t *val)
{
iis3dwb_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- switch (ctrl1_xl.xl_en){
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ switch (ctrl1_xl.xl_en)
+ {
case IIS3DWB_XL_ODR_OFF:
*val = IIS3DWB_XL_ODR_OFF;
break;
+
case IIS3DWB_XL_ODR_26k7Hz:
*val = IIS3DWB_XL_ODR_26k7Hz;
break;
+
default:
*val = IIS3DWB_XL_ODR_OFF;
break;
}
+
return ret;
}
@@ -250,11 +274,14 @@ int32_t iis3dwb_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
iis3dwb_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.bdu= (uint8_t)val;
- ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.bdu = (uint8_t)val;
+ ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -271,7 +298,7 @@ int32_t iis3dwb_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
iis3dwb_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.bdu;
return ret;
@@ -292,11 +319,14 @@ int32_t iis3dwb_xl_offset_weight_set(stmdev_ctx_t *ctx,
iis3dwb_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
- ctrl6_c.usr_off_w= (uint8_t)val;
- ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl6_c.usr_off_w = (uint8_t)val;
+ ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -310,24 +340,28 @@ int32_t iis3dwb_xl_offset_weight_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis3dwb_xl_offset_weight_get(stmdev_ctx_t *ctx,
- iis3dwb_usr_off_w_t *val)
+ iis3dwb_usr_off_w_t *val)
{
iis3dwb_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
- switch (ctrl6_c.usr_off_w){
+ switch (ctrl6_c.usr_off_w)
+ {
case IIS3DWB_LSb_1mg:
*val = IIS3DWB_LSb_1mg;
break;
+
case IIS3DWB_LSb_16mg:
*val = IIS3DWB_LSb_16mg;
break;
+
default:
*val = IIS3DWB_LSb_1mg;
break;
}
+
return ret;
}
@@ -341,29 +375,36 @@ int32_t iis3dwb_xl_offset_weight_get(stmdev_ctx_t *ctx,
*
*/
int32_t iis3dwb_xl_axis_selection_set(stmdev_ctx_t *ctx,
- iis3dwb_xl_axis_sel_t val)
+ iis3dwb_xl_axis_sel_t val)
{
iis3dwb_ctrl4_c_t ctrl4_c;
iis3dwb_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ctrl4_c._1ax_to_3regout = ( (uint8_t)val & 0x10U ) >> 4;
- ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl4_c._1ax_to_3regout = ((uint8_t)val & 0x10U) >> 4;
+ ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
- if(ret == 0){
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ctrl6_c.xl_axis_sel = (uint8_t)val;
- ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
/**
- * @brief select accelerometer axis.[get]
+ * @brief select accelerometer axis.[get]
*
* @param ctx Read / write interface definitions.(ptr)
* @param val Get the values of xl_axis_sel in reg CTRL6_C and
@@ -372,43 +413,54 @@ int32_t iis3dwb_xl_axis_selection_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis3dwb_xl_axis_selection_get(stmdev_ctx_t *ctx,
- iis3dwb_xl_axis_sel_t *val)
+ iis3dwb_xl_axis_sel_t *val)
{
iis3dwb_ctrl4_c_t ctrl4_c;
iis3dwb_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
}
- switch ( ( ctrl4_c._1ax_to_3regout << 4 ) + ctrl6_c.xl_axis_sel ){
+ switch ((ctrl4_c._1ax_to_3regout << 4) + ctrl6_c.xl_axis_sel)
+ {
case IIS3DWB_ENABLE_ALL:
*val = IIS3DWB_ENABLE_ALL;
break;
+
case IIS3DWB_ONLY_X_ON_ONE_OUT_REG:
*val = IIS3DWB_ONLY_X_ON_ONE_OUT_REG;
break;
+
case IIS3DWB_ONLY_Y_ON_ONE_OUT_REG:
*val = IIS3DWB_ONLY_Y_ON_ONE_OUT_REG;
break;
+
case IIS3DWB_ONLY_Z_ON_ONE_OUT_REG:
*val = IIS3DWB_ONLY_Z_ON_ONE_OUT_REG;
break;
+
case IIS3DWB_ONLY_X_ON_ALL_OUT_REG:
*val = IIS3DWB_ONLY_X_ON_ALL_OUT_REG;
break;
+
case IIS3DWB_ONLY_Y_ON_ALL_OUT_REG:
*val = IIS3DWB_ONLY_Y_ON_ALL_OUT_REG;
break;
+
case IIS3DWB_ONLY_Z_ON_ALL_OUT_REG:
*val = IIS3DWB_ONLY_Z_ON_ALL_OUT_REG;
break;
+
default:
*val = IIS3DWB_ENABLE_ALL;
break;
}
+
return ret;
}
@@ -422,19 +474,23 @@ int32_t iis3dwb_xl_axis_selection_get(stmdev_ctx_t *ctx,
*
*/
int32_t iis3dwb_all_sources_get(stmdev_ctx_t *ctx,
- iis3dwb_all_sources_t *val)
+ iis3dwb_all_sources_t *val)
{
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_ALL_INT_SRC,
- (uint8_t*)&val->all_int_src, 1);
- if(ret == 0){
+ (uint8_t *)&val->all_int_src, 1);
+
+ if (ret == 0)
+ {
ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_SRC,
- (uint8_t*)&val->wake_up_src, 1);
+ (uint8_t *)&val->wake_up_src, 1);
}
- if(ret == 0){
- ret = iis3dwb_read_reg(ctx, IIS3DWB_STATUS_REG,
- (uint8_t*)&val->status_reg, 1);
+
+ if (ret == 0)
+ {
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_STATUS_REG,
+ (uint8_t *)&val->status_reg, 1);
}
return ret;
@@ -449,10 +505,12 @@ int32_t iis3dwb_all_sources_get(stmdev_ctx_t *ctx,
*
*/
int32_t iis3dwb_status_reg_get(stmdev_ctx_t *ctx,
- iis3dwb_status_reg_t *val)
+ iis3dwb_status_reg_t *val)
{
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_STATUS_REG, (uint8_t*) val, 1);
+
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_STATUS_REG, (uint8_t *) val, 1);
+
return ret;
}
@@ -464,13 +522,14 @@ int32_t iis3dwb_status_reg_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis3dwb_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t iis3dwb_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
iis3dwb_status_reg_t status_reg;
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_STATUS_REG,
- (uint8_t*)&status_reg, 1);
+ (uint8_t *)&status_reg, 1);
*val = status_reg.xlda;
return ret;
@@ -484,13 +543,14 @@ int32_t iis3dwb_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis3dwb_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t iis3dwb_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
iis3dwb_status_reg_t status_reg;
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_STATUS_REG,
- (uint8_t*)&status_reg, 1);
+ (uint8_t *)&status_reg, 1);
*val = status_reg.tda;
return ret;
@@ -509,7 +569,9 @@ int32_t iis3dwb_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t iis3dwb_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = iis3dwb_write_reg(ctx, IIS3DWB_X_OFS_USR, buff, 1);
+
return ret;
}
@@ -526,7 +588,9 @@ int32_t iis3dwb_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t iis3dwb_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = iis3dwb_read_reg(ctx, IIS3DWB_X_OFS_USR, buff, 1);
+
return ret;
}
@@ -543,7 +607,9 @@ int32_t iis3dwb_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t iis3dwb_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = iis3dwb_write_reg(ctx, IIS3DWB_Y_OFS_USR, buff, 1);
+
return ret;
}
@@ -560,7 +626,9 @@ int32_t iis3dwb_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t iis3dwb_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = iis3dwb_read_reg(ctx, IIS3DWB_Y_OFS_USR, buff, 1);
+
return ret;
}
@@ -577,7 +645,9 @@ int32_t iis3dwb_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t iis3dwb_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = iis3dwb_write_reg(ctx, IIS3DWB_Z_OFS_USR, buff, 1);
+
return ret;
}
@@ -594,7 +664,9 @@ int32_t iis3dwb_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t iis3dwb_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = iis3dwb_read_reg(ctx, IIS3DWB_Z_OFS_USR, buff, 1);
+
return ret;
}
@@ -621,7 +693,6 @@ int32_t iis3dwb_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t iis3dwb_timestamp_rst(stmdev_ctx_t *ctx)
{
uint8_t rst_val = 0xAA;
-
return iis3dwb_write_reg(ctx, IIS3DWB_TIMESTAMP2, &rst_val, 1);
}
@@ -638,12 +709,15 @@ int32_t iis3dwb_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
iis3dwb_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
- ctrl10_c.timestamp_en= (uint8_t)val;
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl10_c.timestamp_en = (uint8_t)val;
ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL10_C,
- (uint8_t*)&ctrl10_c, 1);
+ (uint8_t *)&ctrl10_c, 1);
}
+
return ret;
}
@@ -660,7 +734,7 @@ int32_t iis3dwb_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
iis3dwb_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
*val = ctrl10_c.timestamp_en;
return ret;
@@ -711,16 +785,19 @@ int32_t iis3dwb_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val)
*
*/
int32_t iis3dwb_rounding_mode_set(stmdev_ctx_t *ctx,
- iis3dwb_rounding_t val)
+ iis3dwb_rounding_t val)
{
iis3dwb_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
- ctrl5_c.rounding= (uint8_t)val;
- ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl5_c.rounding = (uint8_t)val;
+ ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -733,23 +810,28 @@ int32_t iis3dwb_rounding_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis3dwb_rounding_mode_get(stmdev_ctx_t *ctx,
- iis3dwb_rounding_t *val)
+ iis3dwb_rounding_t *val)
{
iis3dwb_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- switch (ctrl5_c.rounding){
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ switch (ctrl5_c.rounding)
+ {
case IIS3DWB_NO_ROUND:
*val = IIS3DWB_NO_ROUND;
break;
+
case IIS3DWB_ROUND:
*val = IIS3DWB_ROUND;
break;
+
default:
*val = IIS3DWB_NO_ROUND;
break;
}
+
return ret;
}
@@ -770,7 +852,7 @@ int32_t iis3dwb_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
ret = iis3dwb_read_reg(ctx, IIS3DWB_OUT_TEMP_L, buff, 2);
*val = (int16_t)buff[1];
- *val = (*val * 256) + (int16_t)buff[0];
+ *val = (*val * 256) + (int16_t)buff[0];
return ret;
}
@@ -790,13 +872,12 @@ int32_t iis3dwb_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_OUTX_L_A, buff, 6);
-
val[0] = (int16_t)buff[1];
- val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
- val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
val[2] = (int16_t)buff[5];
- val[2] = (val[2] * 256) + (int16_t)buff[4];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
return ret;
}
@@ -812,7 +893,9 @@ int32_t iis3dwb_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
int32_t iis3dwb_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_DATA_OUT_X_L, buff, 6);
+
return ret;
}
@@ -823,7 +906,7 @@ int32_t iis3dwb_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
/**
* @defgroup IIS3DWB_common
- * @brief This section groups common usefull functions.
+ * @brief This section groups common useful functions.
* @{
*
*/
@@ -844,12 +927,15 @@ int32_t iis3dwb_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_INTERNAL_FREQ_FINE,
- (uint8_t*)&internal_freq_fine, 1);
- if(ret == 0){
- internal_freq_fine.freq_fine= (uint8_t)val;
+ (uint8_t *)&internal_freq_fine, 1);
+
+ if (ret == 0)
+ {
+ internal_freq_fine.freq_fine = (uint8_t)val;
ret = iis3dwb_write_reg(ctx, IIS3DWB_INTERNAL_FREQ_FINE,
- (uint8_t*)&internal_freq_fine, 1);
+ (uint8_t *)&internal_freq_fine, 1);
}
+
return ret;
}
@@ -869,7 +955,7 @@ int32_t iis3dwb_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_INTERNAL_FREQ_FINE,
- (uint8_t*)&internal_freq_fine, 1);
+ (uint8_t *)&internal_freq_fine, 1);
*val = internal_freq_fine.freq_fine;
return ret;
@@ -885,18 +971,21 @@ int32_t iis3dwb_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t iis3dwb_data_ready_mode_set(stmdev_ctx_t *ctx,
- iis3dwb_dataready_pulsed_t val)
+ iis3dwb_dataready_pulsed_t val)
{
iis3dwb_counter_bdr_reg1_t counter_bdr_reg1;
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if(ret == 0){
- counter_bdr_reg1.dataready_pulsed= (uint8_t)val;
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
+ counter_bdr_reg1.dataready_pulsed = (uint8_t)val;
ret = iis3dwb_write_reg(ctx, IIS3DWB_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
}
+
return ret;
}
@@ -910,24 +999,29 @@ int32_t iis3dwb_data_ready_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis3dwb_data_ready_mode_get(stmdev_ctx_t *ctx,
- iis3dwb_dataready_pulsed_t *val)
+ iis3dwb_dataready_pulsed_t *val)
{
iis3dwb_counter_bdr_reg1_t counter_bdr_reg1;
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- switch (counter_bdr_reg1.dataready_pulsed){
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ switch (counter_bdr_reg1.dataready_pulsed)
+ {
case IIS3DWB_DRDY_LATCHED:
*val = IIS3DWB_DRDY_LATCHED;
break;
+
case IIS3DWB_DRDY_PULSED:
*val = IIS3DWB_DRDY_PULSED;
break;
+
default:
*val = IIS3DWB_DRDY_LATCHED;
break;
}
+
return ret;
}
@@ -942,7 +1036,9 @@ int32_t iis3dwb_data_ready_mode_get(stmdev_ctx_t *ctx,
int32_t iis3dwb_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = iis3dwb_read_reg(ctx, IIS3DWB_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -959,11 +1055,14 @@ int32_t iis3dwb_reset_set(stmdev_ctx_t *ctx, uint8_t val)
iis3dwb_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.sw_reset= (uint8_t)val;
- ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.sw_reset = (uint8_t)val;
+ ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -980,7 +1079,7 @@ int32_t iis3dwb_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
iis3dwb_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.sw_reset;
return ret;
@@ -1000,11 +1099,14 @@ int32_t iis3dwb_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
iis3dwb_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.if_inc= (uint8_t)val;
- ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.if_inc = (uint8_t)val;
+ ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1022,7 +1124,7 @@ int32_t iis3dwb_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
iis3dwb_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.if_inc;
return ret;
@@ -1041,11 +1143,14 @@ int32_t iis3dwb_boot_set(stmdev_ctx_t *ctx, uint8_t val)
iis3dwb_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.boot= (uint8_t)val;
- ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.boot = (uint8_t)val;
+ ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1062,7 +1167,7 @@ int32_t iis3dwb_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
iis3dwb_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.boot;
return ret;
@@ -1079,16 +1184,19 @@ int32_t iis3dwb_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t iis3dwb_xl_self_test_set(stmdev_ctx_t *ctx,
- iis3dwb_st_xl_t val)
+ iis3dwb_st_xl_t val)
{
iis3dwb_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
- ctrl5_c.st_xl= (uint8_t)val;
- ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl5_c.st_xl = (uint8_t)val;
+ ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -1101,27 +1209,32 @@ int32_t iis3dwb_xl_self_test_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis3dwb_xl_self_test_get(stmdev_ctx_t *ctx,
- iis3dwb_st_xl_t *val)
+ iis3dwb_st_xl_t *val)
{
iis3dwb_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
- switch (ctrl5_c.st_xl){
+ switch (ctrl5_c.st_xl)
+ {
case IIS3DWB_XL_ST_DISABLE:
*val = IIS3DWB_XL_ST_DISABLE;
break;
+
case IIS3DWB_XL_ST_POSITIVE:
*val = IIS3DWB_XL_ST_POSITIVE;
break;
+
case IIS3DWB_XL_ST_NEGATIVE:
*val = IIS3DWB_XL_ST_NEGATIVE;
break;
+
default:
*val = IIS3DWB_XL_ST_DISABLE;
break;
}
+
return ret;
}
@@ -1153,12 +1266,15 @@ int32_t iis3dwb_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val)
iis3dwb_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
- ctrl1_xl.lpf2_xl_en= (uint8_t)val;
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl1_xl.lpf2_xl_en = (uint8_t)val;
ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
+ (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -1175,7 +1291,7 @@ int32_t iis3dwb_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val)
iis3dwb_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
*val = ctrl1_xl.lpf2_xl_en;
return ret;
@@ -1190,16 +1306,20 @@ int32_t iis3dwb_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis3dwb_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t iis3dwb_filter_settling_mask_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
iis3dwb_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ctrl4_c.drdy_mask= (uint8_t)val;
- ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl4_c.drdy_mask = (uint8_t)val;
+ ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -1213,12 +1333,12 @@ int32_t iis3dwb_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val)
*
*/
int32_t iis3dwb_filter_settling_mask_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
iis3dwb_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.drdy_mask;
return ret;
@@ -1234,26 +1354,33 @@ int32_t iis3dwb_filter_settling_mask_get(stmdev_ctx_t *ctx,
*
*/
int32_t iis3dwb_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
- iis3dwb_hp_slope_xl_en_t val)
+ iis3dwb_hp_slope_xl_en_t val)
{
iis3dwb_ctrl1_xl_t ctrl1_xl;
iis3dwb_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
ctrl1_xl.lpf2_xl_en = ((uint8_t)val & 0x80U) >> 7;
- ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
+ ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
}
- if(ret == 0){
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ctrl8_xl.fds = ((uint8_t)val & 0x10U) >> 4;
ctrl8_xl.hp_ref_mode_xl = ((uint8_t)val & 0x20U) >> 5;
ctrl8_xl.hpcf_xl = (uint8_t)val & 0x07U;
- ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -1267,74 +1394,95 @@ int32_t iis3dwb_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis3dwb_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
- iis3dwb_hp_slope_xl_en_t *val)
+ iis3dwb_hp_slope_xl_en_t *val)
{
iis3dwb_ctrl1_xl_t ctrl1_xl;
iis3dwb_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
}
- switch ( (ctrl1_xl.lpf2_xl_en << 7) + (ctrl8_xl.hp_ref_mode_xl << 5) +
- (ctrl8_xl.fds << 4) + ctrl8_xl.hpcf_xl ){
+ switch ((ctrl1_xl.lpf2_xl_en << 7) + (ctrl8_xl.hp_ref_mode_xl << 5) +
+ (ctrl8_xl.fds << 4) + ctrl8_xl.hpcf_xl)
+ {
case IIS3DWB_SLOPE_ODR_DIV_4:
*val = IIS3DWB_SLOPE_ODR_DIV_4;
break;
+
case IIS3DWB_HP_ODR_DIV_10:
*val = IIS3DWB_HP_ODR_DIV_10;
break;
+
case IIS3DWB_HP_ODR_DIV_20:
*val = IIS3DWB_HP_ODR_DIV_20;
break;
+
case IIS3DWB_HP_ODR_DIV_45:
*val = IIS3DWB_HP_ODR_DIV_45;
break;
+
case IIS3DWB_HP_ODR_DIV_100:
*val = IIS3DWB_HP_ODR_DIV_100;
break;
+
case IIS3DWB_HP_ODR_DIV_200:
*val = IIS3DWB_HP_ODR_DIV_200;
break;
+
case IIS3DWB_HP_ODR_DIV_400:
*val = IIS3DWB_HP_ODR_DIV_400;
break;
+
case IIS3DWB_HP_ODR_DIV_800:
*val = IIS3DWB_HP_ODR_DIV_800;
break;
+
case IIS3DWB_LP_ODR_DIV_4:
*val = IIS3DWB_LP_ODR_DIV_4;
break;
+
case IIS3DWB_LP_6k3Hz:
*val = IIS3DWB_LP_6k3Hz;
break;
+
case IIS3DWB_LP_ODR_DIV_10:
*val = IIS3DWB_LP_ODR_DIV_10;
break;
+
case IIS3DWB_LP_ODR_DIV_20:
*val = IIS3DWB_LP_ODR_DIV_20;
break;
+
case IIS3DWB_LP_ODR_DIV_45:
*val = IIS3DWB_LP_ODR_DIV_45;
break;
+
case IIS3DWB_LP_ODR_DIV_100:
*val = IIS3DWB_LP_ODR_DIV_100;
break;
+
case IIS3DWB_LP_ODR_DIV_200:
*val = IIS3DWB_LP_ODR_DIV_200;
break;
+
case IIS3DWB_LP_ODR_DIV_400:
*val = IIS3DWB_LP_ODR_DIV_400;
break;
+
case IIS3DWB_LP_ODR_DIV_800:
*val = IIS3DWB_LP_ODR_DIV_800;
break;
+
default:
*val = IIS3DWB_SLOPE_ODR_DIV_4;
break;
}
+
return ret;
}
@@ -1353,12 +1501,15 @@ int32_t iis3dwb_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val)
iis3dwb_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
- ctrl8_xl.fastsettl_mode_xl= (uint8_t)val;
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl8_xl.fastsettl_mode_xl = (uint8_t)val;
ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL8_XL,
- (uint8_t*)&ctrl8_xl, 1);
+ (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -1377,7 +1528,7 @@ int32_t iis3dwb_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
iis3dwb_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
*val = ctrl8_xl.fastsettl_mode_xl;
return ret;
@@ -1393,17 +1544,20 @@ int32_t iis3dwb_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t iis3dwb_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
- iis3dwb_slope_fds_t val)
+ iis3dwb_slope_fds_t val)
{
iis3dwb_slope_en_t int_cfg0;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t*)&int_cfg0, 1);
- if(ret == 0){
- int_cfg0.slope_fds= (uint8_t)val;
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&int_cfg0, 1);
+
+ if (ret == 0)
+ {
+ int_cfg0.slope_fds = (uint8_t)val;
ret = iis3dwb_write_reg(ctx, IIS3DWB_SLOPE_EN,
- (uint8_t*)&int_cfg0, 1);
+ (uint8_t *)&int_cfg0, 1);
}
+
return ret;
}
@@ -1417,23 +1571,28 @@ int32_t iis3dwb_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis3dwb_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
- iis3dwb_slope_fds_t *val)
+ iis3dwb_slope_fds_t *val)
{
iis3dwb_slope_en_t int_cfg0;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t*)&int_cfg0, 1);
- switch (int_cfg0.slope_fds){
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&int_cfg0, 1);
+
+ switch (int_cfg0.slope_fds)
+ {
case IIS3DWB_USE_SLOPE:
*val = IIS3DWB_USE_SLOPE;
break;
+
case IIS3DWB_USE_HPF:
*val = IIS3DWB_USE_HPF;
break;
+
default:
*val = IIS3DWB_USE_SLOPE;
break;
}
+
return ret;
}
@@ -1459,16 +1618,19 @@ int32_t iis3dwb_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
*
*/
int32_t iis3dwb_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
- iis3dwb_sdo_pu_en_t val)
+ iis3dwb_sdo_pu_en_t val)
{
iis3dwb_pin_ctrl_t pin_ctrl;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
- if(ret == 0){
- pin_ctrl.sdo_pu_en= (uint8_t)val;
- ret = iis3dwb_write_reg(ctx, IIS3DWB_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
+
+ if (ret == 0)
+ {
+ pin_ctrl.sdo_pu_en = (uint8_t)val;
+ ret = iis3dwb_write_reg(ctx, IIS3DWB_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
}
+
return ret;
}
@@ -1481,24 +1643,28 @@ int32_t iis3dwb_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis3dwb_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
- iis3dwb_sdo_pu_en_t *val)
+ iis3dwb_sdo_pu_en_t *val)
{
iis3dwb_pin_ctrl_t pin_ctrl;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
- switch (pin_ctrl.sdo_pu_en){
+ switch (pin_ctrl.sdo_pu_en)
+ {
case IIS3DWB_PULL_UP_DISC:
*val = IIS3DWB_PULL_UP_DISC;
break;
+
case IIS3DWB_PULL_UP_CONNECT:
*val = IIS3DWB_PULL_UP_CONNECT;
break;
+
default:
*val = IIS3DWB_PULL_UP_DISC;
break;
}
+
return ret;
}
@@ -1515,11 +1681,14 @@ int32_t iis3dwb_spi_mode_set(stmdev_ctx_t *ctx, iis3dwb_sim_t val)
iis3dwb_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.sim= (uint8_t)val;
- ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.sim = (uint8_t)val;
+ ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1536,19 +1705,23 @@ int32_t iis3dwb_spi_mode_get(stmdev_ctx_t *ctx, iis3dwb_sim_t *val)
iis3dwb_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
- switch (ctrl3_c.sim){
+ switch (ctrl3_c.sim)
+ {
case IIS3DWB_SPI_4_WIRE:
*val = IIS3DWB_SPI_4_WIRE;
break;
+
case IIS3DWB_SPI_3_WIRE:
*val = IIS3DWB_SPI_3_WIRE;
break;
+
default:
*val = IIS3DWB_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -1561,16 +1734,19 @@ int32_t iis3dwb_spi_mode_get(stmdev_ctx_t *ctx, iis3dwb_sim_t *val)
*
*/
int32_t iis3dwb_i2c_interface_set(stmdev_ctx_t *ctx,
- iis3dwb_i2c_disable_t val)
+ iis3dwb_i2c_disable_t val)
{
iis3dwb_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ctrl4_c.i2c_disable= (uint8_t)val;
- ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl4_c.i2c_disable = (uint8_t)val;
+ ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -1583,24 +1759,28 @@ int32_t iis3dwb_i2c_interface_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis3dwb_i2c_interface_get(stmdev_ctx_t *ctx,
- iis3dwb_i2c_disable_t *val)
+ iis3dwb_i2c_disable_t *val)
{
iis3dwb_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
- switch (ctrl4_c.i2c_disable){
+ switch (ctrl4_c.i2c_disable)
+ {
case IIS3DWB_I2C_ENABLE:
*val = IIS3DWB_I2C_ENABLE;
break;
+
case IIS3DWB_I2C_DISABLE:
*val = IIS3DWB_I2C_DISABLE;
break;
+
default:
*val = IIS3DWB_I2C_ENABLE;
break;
}
+
return ret;
}
@@ -1612,7 +1792,7 @@ int32_t iis3dwb_i2c_interface_get(stmdev_ctx_t *ctx,
/**
* @defgroup IIS3DWB_interrupt_pins
* @brief This section groups all the functions that manage
- * interrup pins
+ * interrupt pins
* @{
*
*/
@@ -1633,12 +1813,16 @@ int32_t iis3dwb_pin_int1_route_set(stmdev_ctx_t *ctx,
iis3dwb_md1_cfg_t md1_cfg;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
- if(ret == 0){
- ret = iis3dwb_read_reg(ctx, IIS3DWB_MD1_CFG, (uint8_t*)&md1_cfg, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
+
+ if (ret == 0)
+ {
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_MD1_CFG, (uint8_t *)&md1_cfg, 1);
}
- if(ret == 0){
- ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t*)&slope_en, 1);
+
+ if (ret == 0)
+ {
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&slope_en, 1);
}
int1_ctrl.int1_drdy_xl = val->drdy_xl;
@@ -1651,16 +1835,21 @@ int32_t iis3dwb_pin_int1_route_set(stmdev_ctx_t *ctx,
md1_cfg.int1_sleep_change = val->sleep_change | val->sleep_status;
slope_en.sleep_status_on_int = val->sleep_status;
-
- if(ret == 0){
- ret = iis3dwb_write_reg(ctx, IIS3DWB_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
+ if (ret == 0)
+ {
+ ret = iis3dwb_write_reg(ctx, IIS3DWB_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
}
- if(ret == 0){
- ret = iis3dwb_write_reg(ctx, IIS3DWB_MD1_CFG, (uint8_t*)&md1_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = iis3dwb_write_reg(ctx, IIS3DWB_MD1_CFG, (uint8_t *)&md1_cfg, 1);
}
- if(ret == 0){
- ret = iis3dwb_write_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t*)&slope_en, 1);
+
+ if (ret == 0)
+ {
+ ret = iis3dwb_write_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&slope_en, 1);
}
+
return ret;
}
@@ -1679,13 +1868,17 @@ int32_t iis3dwb_pin_int1_route_get(stmdev_ctx_t *ctx,
iis3dwb_slope_en_t slope_en;
iis3dwb_md1_cfg_t md1_cfg;
int32_t ret;
-
- ret = iis3dwb_read_reg(ctx, IIS3DWB_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
- if(ret == 0){
- ret = iis3dwb_read_reg(ctx, IIS3DWB_MD1_CFG, (uint8_t*)&md1_cfg, 1);
+
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
+
+ if (ret == 0)
+ {
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_MD1_CFG, (uint8_t *)&md1_cfg, 1);
}
- if(ret == 0){
- ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t*)&slope_en, 1);
+
+ if (ret == 0)
+ {
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&slope_en, 1);
}
val->drdy_xl = int1_ctrl.int1_drdy_xl;
@@ -1696,11 +1889,14 @@ int32_t iis3dwb_pin_int1_route_get(stmdev_ctx_t *ctx,
val->fifo_bdr = int1_ctrl.int1_cnt_bdr;
val->wake_up = md1_cfg.int1_wu;
- if (slope_en.sleep_status_on_int == PROPERTY_ENABLE) {
+ if (slope_en.sleep_status_on_int == PROPERTY_ENABLE)
+ {
val->sleep_status = PROPERTY_ENABLE;
val->sleep_change = PROPERTY_DISABLE;
}
- else {
+
+ else
+ {
val->sleep_change = md1_cfg.int1_sleep_change;
}
@@ -1716,19 +1912,23 @@ int32_t iis3dwb_pin_int1_route_get(stmdev_ctx_t *ctx,
*
*/
int32_t iis3dwb_pin_int2_route_set(stmdev_ctx_t *ctx,
- iis3dwb_pin_int2_route_t *val)
+ iis3dwb_pin_int2_route_t *val)
{
iis3dwb_int2_ctrl_t int2_ctrl;
iis3dwb_slope_en_t slope_en;
iis3dwb_md2_cfg_t md2_cfg;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
- if(ret == 0){
- ret = iis3dwb_read_reg(ctx, IIS3DWB_MD2_CFG, (uint8_t*)&md2_cfg, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
+
+ if (ret == 0)
+ {
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_MD2_CFG, (uint8_t *)&md2_cfg, 1);
}
- if(ret == 0){
- ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t*)&slope_en, 1);
+
+ if (ret == 0)
+ {
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&slope_en, 1);
}
int2_ctrl.int2_drdy_xl = val->drdy_xl;
@@ -1742,15 +1942,21 @@ int32_t iis3dwb_pin_int2_route_set(stmdev_ctx_t *ctx,
md2_cfg.int2_sleep_change = val->sleep_change | val->sleep_status;
slope_en.sleep_status_on_int = val->sleep_status;
- if(ret == 0){
- ret = iis3dwb_write_reg(ctx, IIS3DWB_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+ if (ret == 0)
+ {
+ ret = iis3dwb_write_reg(ctx, IIS3DWB_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
}
- if(ret == 0){
- ret = iis3dwb_write_reg(ctx, IIS3DWB_MD2_CFG, (uint8_t*)&md2_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = iis3dwb_write_reg(ctx, IIS3DWB_MD2_CFG, (uint8_t *)&md2_cfg, 1);
}
- if(ret == 0){
- ret = iis3dwb_write_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t*)&slope_en, 1);
+
+ if (ret == 0)
+ {
+ ret = iis3dwb_write_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&slope_en, 1);
}
+
return ret;
}
@@ -1763,19 +1969,23 @@ int32_t iis3dwb_pin_int2_route_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis3dwb_pin_int2_route_get(stmdev_ctx_t *ctx,
- iis3dwb_pin_int2_route_t *val)
+ iis3dwb_pin_int2_route_t *val)
{
iis3dwb_int2_ctrl_t int2_ctrl;
iis3dwb_slope_en_t slope_en;
iis3dwb_md2_cfg_t md2_cfg;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
- if(ret == 0){
- ret = iis3dwb_read_reg(ctx, IIS3DWB_MD2_CFG, (uint8_t*)&md2_cfg, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
+
+ if (ret == 0)
+ {
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_MD2_CFG, (uint8_t *)&md2_cfg, 1);
}
- if(ret == 0){
- ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t*)&slope_en, 1);
+
+ if (ret == 0)
+ {
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&slope_en, 1);
}
val->drdy_xl = int2_ctrl.int2_drdy_xl;
@@ -1784,15 +1994,17 @@ int32_t iis3dwb_pin_int2_route_get(stmdev_ctx_t *ctx,
val->fifo_ovr = int2_ctrl.int2_fifo_ovr;
val->fifo_full = int2_ctrl.int2_fifo_full;
val->fifo_bdr = int2_ctrl.int2_cnt_bdr;
-
val->timestamp = md2_cfg.int2_timestamp;
val->wake_up = md2_cfg.int2_wu;
- if (slope_en.sleep_status_on_int == PROPERTY_ENABLE) {
+ if (slope_en.sleep_status_on_int == PROPERTY_ENABLE)
+ {
val->sleep_status = PROPERTY_ENABLE;
val->sleep_change = PROPERTY_DISABLE;
}
- else {
+
+ else
+ {
val->sleep_change = md2_cfg.int2_sleep_change;
}
@@ -1812,11 +2024,14 @@ int32_t iis3dwb_pin_mode_set(stmdev_ctx_t *ctx, iis3dwb_pp_od_t val)
iis3dwb_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.pp_od= (uint8_t)val;
- ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.pp_od = (uint8_t)val;
+ ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1833,19 +2048,23 @@ int32_t iis3dwb_pin_mode_get(stmdev_ctx_t *ctx, iis3dwb_pp_od_t *val)
iis3dwb_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
- switch (ctrl3_c.pp_od){
+ switch (ctrl3_c.pp_od)
+ {
case IIS3DWB_PUSH_PULL:
*val = IIS3DWB_PUSH_PULL;
break;
+
case IIS3DWB_OPEN_DRAIN:
*val = IIS3DWB_OPEN_DRAIN;
break;
+
default:
*val = IIS3DWB_PUSH_PULL;
break;
}
+
return ret;
}
@@ -1858,16 +2077,19 @@ int32_t iis3dwb_pin_mode_get(stmdev_ctx_t *ctx, iis3dwb_pp_od_t *val)
*
*/
int32_t iis3dwb_pin_polarity_set(stmdev_ctx_t *ctx,
- iis3dwb_h_lactive_t val)
+ iis3dwb_h_lactive_t val)
{
iis3dwb_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.h_lactive= (uint8_t)val;
- ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.h_lactive = (uint8_t)val;
+ ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1880,24 +2102,28 @@ int32_t iis3dwb_pin_polarity_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis3dwb_pin_polarity_get(stmdev_ctx_t *ctx,
- iis3dwb_h_lactive_t *val)
+ iis3dwb_h_lactive_t *val)
{
iis3dwb_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
- switch (ctrl3_c.h_lactive){
+ switch (ctrl3_c.h_lactive)
+ {
case IIS3DWB_ACTIVE_HIGH:
*val = IIS3DWB_ACTIVE_HIGH;
break;
+
case IIS3DWB_ACTIVE_LOW:
*val = IIS3DWB_ACTIVE_LOW;
break;
+
default:
*val = IIS3DWB_ACTIVE_HIGH;
break;
}
+
return ret;
}
@@ -1914,11 +2140,14 @@ int32_t iis3dwb_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
iis3dwb_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ctrl4_c.int2_on_int1= (uint8_t)val;
- ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl4_c.int2_on_int1 = (uint8_t)val;
+ ret = iis3dwb_write_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -1935,7 +2164,7 @@ int32_t iis3dwb_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
iis3dwb_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.int2_on_int1;
return ret;
@@ -1949,16 +2178,20 @@ int32_t iis3dwb_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis3dwb_int_notification_set(stmdev_ctx_t *ctx, iis3dwb_lir_t val)
+int32_t iis3dwb_int_notification_set(stmdev_ctx_t *ctx,
+ iis3dwb_lir_t val)
{
iis3dwb_slope_en_t slope_en;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t*)&slope_en, 1);
- if(ret == 0){
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&slope_en, 1);
+
+ if (ret == 0)
+ {
slope_en.lir = (uint8_t)val;
- ret = iis3dwb_write_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t*)&slope_en, 1);
+ ret = iis3dwb_write_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&slope_en, 1);
}
+
return ret;
}
@@ -1970,24 +2203,29 @@ int32_t iis3dwb_int_notification_set(stmdev_ctx_t *ctx, iis3dwb_lir_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis3dwb_int_notification_get(stmdev_ctx_t *ctx, iis3dwb_lir_t *val)
+int32_t iis3dwb_int_notification_get(stmdev_ctx_t *ctx,
+ iis3dwb_lir_t *val)
{
iis3dwb_slope_en_t slope_en;
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t*)&slope_en, 1);
-
- switch (slope_en.lir){
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&slope_en, 1);
+
+ switch (slope_en.lir)
+ {
case IIS3DWB_INT_PULSED:
*val = IIS3DWB_INT_PULSED;
break;
+
case IIS3DWB_INT_LATCHED:
*val = IIS3DWB_INT_LATCHED;
break;
+
default:
*val = IIS3DWB_INT_PULSED;
break;
}
+
return ret;
}
@@ -2015,18 +2253,21 @@ int32_t iis3dwb_int_notification_get(stmdev_ctx_t *ctx, iis3dwb_lir_t *val)
*
*/
int32_t iis3dwb_wkup_ths_weight_set(stmdev_ctx_t *ctx,
- iis3dwb_wake_ths_w_t val)
+ iis3dwb_wake_ths_w_t val)
{
iis3dwb_wake_up_dur_t wake_up_dur;
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
- wake_up_dur.wake_ths_w= (uint8_t)val;
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ wake_up_dur.wake_ths_w = (uint8_t)val;
ret = iis3dwb_write_reg(ctx, IIS3DWB_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -2041,25 +2282,29 @@ int32_t iis3dwb_wkup_ths_weight_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis3dwb_wkup_ths_weight_get(stmdev_ctx_t *ctx,
- iis3dwb_wake_ths_w_t *val)
+ iis3dwb_wake_ths_w_t *val)
{
iis3dwb_wake_up_dur_t wake_up_dur;
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
- switch (wake_up_dur.wake_ths_w){
+ switch (wake_up_dur.wake_ths_w)
+ {
case IIS3DWB_LSb_FS_DIV_64:
*val = IIS3DWB_LSb_FS_DIV_64;
break;
+
case IIS3DWB_LSb_FS_DIV_256:
*val = IIS3DWB_LSb_FS_DIV_256;
break;
+
default:
*val = IIS3DWB_LSb_FS_DIV_64;
break;
}
+
return ret;
}
@@ -2080,21 +2325,28 @@ int32_t iis3dwb_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
- if(ret == 0){
- wake_up_ths.wk_ths= (uint8_t)val;
+ (uint8_t *)&wake_up_ths, 1);
+
+ if (ret == 0)
+ {
+ wake_up_ths.wk_ths = (uint8_t)val;
ret = iis3dwb_write_reg(ctx, IIS3DWB_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
}
- if (ret == 0){
- ret = iis3dwb_read_reg(ctx, IIS3DWB_INTERRUPTS_EN,
- (uint8_t*)&interrupts_en, 1);
+
+ if (ret == 0)
+ {
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_INTERRUPTS_EN,
+ (uint8_t *)&interrupts_en, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
interrupts_en.interrupts_enable = PROPERTY_ENABLE;
ret = iis3dwb_write_reg(ctx, IIS3DWB_INTERRUPTS_EN,
- (uint8_t*)&interrupts_en, 1);
+ (uint8_t *)&interrupts_en, 1);
}
+
return ret;
}
@@ -2113,7 +2365,7 @@ int32_t iis3dwb_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
*val = wake_up_ths.wk_ths;
return ret;
@@ -2127,18 +2379,22 @@ int32_t iis3dwb_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t iis3dwb_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t iis3dwb_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
iis3dwb_wake_up_ths_t wake_up_ths;
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
- if(ret == 0){
- wake_up_ths.usr_off_on_wu= (uint8_t)val;
+ (uint8_t *)&wake_up_ths, 1);
+
+ if (ret == 0)
+ {
+ wake_up_ths.usr_off_on_wu = (uint8_t)val;
ret = iis3dwb_write_reg(ctx, IIS3DWB_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
}
+
return ret;
}
@@ -2151,13 +2407,13 @@ int32_t iis3dwb_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, uint8_t val)
*
*/
int32_t iis3dwb_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
iis3dwb_wake_up_ths_t wake_up_ths;
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
*val = wake_up_ths.usr_off_on_wu;
return ret;
@@ -2177,12 +2433,15 @@ int32_t iis3dwb_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
- wake_up_dur.wake_dur= (uint8_t)val;
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ wake_up_dur.wake_dur = (uint8_t)val;
ret = iis3dwb_write_reg(ctx, IIS3DWB_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -2200,7 +2459,7 @@ int32_t iis3dwb_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
*val = wake_up_dur.wake_dur;
return ret;
@@ -2233,12 +2492,15 @@ int32_t iis3dwb_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
- wake_up_dur.sleep_dur= (uint8_t)val;
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ wake_up_dur.sleep_dur = (uint8_t)val;
ret = iis3dwb_write_reg(ctx, IIS3DWB_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -2256,7 +2518,7 @@ int32_t iis3dwb_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
*val = wake_up_dur.sleep_dur;
return ret;
@@ -2290,17 +2552,22 @@ int32_t iis3dwb_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl1.wtm = (uint8_t)(0x00FFU & val);
ret = iis3dwb_write_reg(ctx, IIS3DWB_FIFO_CTRL1,
- (uint8_t*)&fifo_ctrl1, 1);
+ (uint8_t *)&fifo_ctrl1, 1);
}
- if(ret == 0){
- fifo_ctrl2.wtm = (uint8_t)(( 0x0100U & val ) >> 8);
+
+ if (ret == 0)
+ {
+ fifo_ctrl2.wtm = (uint8_t)((0x0100U & val) >> 8);
ret = iis3dwb_write_reg(ctx, IIS3DWB_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
+
return ret;
}
@@ -2319,14 +2586,18 @@ int32_t iis3dwb_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL1,
- (uint8_t*)&fifo_ctrl1, 1);
+ (uint8_t *)&fifo_ctrl1, 1);
}
+
*val = fifo_ctrl2.wtm;
*val = *val << 8;
*val += fifo_ctrl1.wtm;
+
return ret;
}
@@ -2345,12 +2616,15 @@ int32_t iis3dwb_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
- fifo_ctrl2.stop_on_wtm= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl2.stop_on_wtm = (uint8_t)val;
ret = iis3dwb_write_reg(ctx, IIS3DWB_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
+
return ret;
}
@@ -2369,7 +2643,7 @@ int32_t iis3dwb_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
*val = fifo_ctrl2.stop_on_wtm;
return ret;
@@ -2385,18 +2659,21 @@ int32_t iis3dwb_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t iis3dwb_fifo_xl_batch_set(stmdev_ctx_t *ctx,
- iis3dwb_bdr_xl_t val)
+ iis3dwb_bdr_xl_t val)
{
iis3dwb_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
- if(ret == 0){
- fifo_ctrl3.bdr_xl= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl3, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl3.bdr_xl = (uint8_t)val;
ret = iis3dwb_write_reg(ctx, IIS3DWB_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
+ (uint8_t *)&fifo_ctrl3, 1);
}
+
return ret;
}
@@ -2410,25 +2687,29 @@ int32_t iis3dwb_fifo_xl_batch_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis3dwb_fifo_xl_batch_get(stmdev_ctx_t *ctx,
- iis3dwb_bdr_xl_t *val)
+ iis3dwb_bdr_xl_t *val)
{
iis3dwb_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
+ (uint8_t *)&fifo_ctrl3, 1);
- switch (fifo_ctrl3.bdr_xl){
+ switch (fifo_ctrl3.bdr_xl)
+ {
case IIS3DWB_XL_NOT_BATCHED:
*val = IIS3DWB_XL_NOT_BATCHED;
break;
+
case IIS3DWB_XL_BATCHED_AT_26k7Hz:
*val = IIS3DWB_XL_BATCHED_AT_26k7Hz;
break;
+
default:
*val = IIS3DWB_XL_NOT_BATCHED;
break;
}
+
return ret;
}
@@ -2441,18 +2722,21 @@ int32_t iis3dwb_fifo_xl_batch_get(stmdev_ctx_t *ctx,
*
*/
int32_t iis3dwb_fifo_mode_set(stmdev_ctx_t *ctx,
- iis3dwb_fifo_mode_t val)
+ iis3dwb_fifo_mode_t val)
{
iis3dwb_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
- fifo_ctrl4.fifo_mode= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl4.fifo_mode = (uint8_t)val;
ret = iis3dwb_write_reg(ctx, IIS3DWB_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -2465,37 +2749,45 @@ int32_t iis3dwb_fifo_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis3dwb_fifo_mode_get(stmdev_ctx_t *ctx,
- iis3dwb_fifo_mode_t *val)
+ iis3dwb_fifo_mode_t *val)
{
iis3dwb_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
- switch (fifo_ctrl4.fifo_mode){
+ switch (fifo_ctrl4.fifo_mode)
+ {
case IIS3DWB_BYPASS_MODE:
*val = IIS3DWB_BYPASS_MODE;
break;
+
case IIS3DWB_FIFO_MODE:
*val = IIS3DWB_FIFO_MODE;
break;
+
case IIS3DWB_STREAM_TO_FIFO_MODE:
*val = IIS3DWB_STREAM_TO_FIFO_MODE;
break;
+
case IIS3DWB_BYPASS_TO_STREAM_MODE:
*val = IIS3DWB_BYPASS_TO_STREAM_MODE;
break;
+
case IIS3DWB_STREAM_MODE:
*val = IIS3DWB_STREAM_MODE;
break;
+
case IIS3DWB_BYPASS_TO_FIFO_MODE:
*val = IIS3DWB_BYPASS_TO_FIFO_MODE;
break;
+
default:
*val = IIS3DWB_BYPASS_MODE;
break;
}
+
return ret;
}
@@ -2509,18 +2801,21 @@ int32_t iis3dwb_fifo_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t iis3dwb_fifo_temp_batch_set(stmdev_ctx_t *ctx,
- iis3dwb_odr_t_batch_t val)
+ iis3dwb_odr_t_batch_t val)
{
iis3dwb_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
- fifo_ctrl4.odr_t_batch= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl4.odr_t_batch = (uint8_t)val;
ret = iis3dwb_write_reg(ctx, IIS3DWB_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -2534,25 +2829,29 @@ int32_t iis3dwb_fifo_temp_batch_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis3dwb_fifo_temp_batch_get(stmdev_ctx_t *ctx,
- iis3dwb_odr_t_batch_t *val)
+ iis3dwb_odr_t_batch_t *val)
{
iis3dwb_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
- switch (fifo_ctrl4.odr_t_batch){
+ switch (fifo_ctrl4.odr_t_batch)
+ {
case IIS3DWB_TEMP_NOT_BATCHED:
*val = IIS3DWB_TEMP_NOT_BATCHED;
break;
+
case IIS3DWB_TEMP_BATCHED_AT_104Hz:
*val = IIS3DWB_TEMP_BATCHED_AT_104Hz;
break;
+
default:
*val = IIS3DWB_TEMP_NOT_BATCHED;
break;
}
+
return ret;
}
@@ -2567,18 +2866,21 @@ int32_t iis3dwb_fifo_temp_batch_get(stmdev_ctx_t *ctx,
*
*/
int32_t iis3dwb_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
- iis3dwb_odr_ts_batch_t val)
+ iis3dwb_odr_ts_batch_t val)
{
iis3dwb_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
- fifo_ctrl4.odr_ts_batch= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl4.odr_ts_batch = (uint8_t)val;
ret = iis3dwb_write_reg(ctx, IIS3DWB_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -2594,31 +2896,37 @@ int32_t iis3dwb_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis3dwb_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
- iis3dwb_odr_ts_batch_t *val)
+ iis3dwb_odr_ts_batch_t *val)
{
iis3dwb_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
- switch (fifo_ctrl4.odr_ts_batch){
+ switch (fifo_ctrl4.odr_ts_batch)
+ {
case IIS3DWB_NO_DECIMATION:
*val = IIS3DWB_NO_DECIMATION;
break;
+
case IIS3DWB_DEC_1:
*val = IIS3DWB_DEC_1;
break;
+
case IIS3DWB_DEC_8:
*val = IIS3DWB_DEC_8;
break;
+
case IIS3DWB_DEC_32:
*val = IIS3DWB_DEC_32;
break;
+
default:
*val = IIS3DWB_NO_DECIMATION;
break;
}
+
return ret;
}
@@ -2637,12 +2945,15 @@ int32_t iis3dwb_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if(ret == 0){
- counter_bdr_reg1.rst_counter_bdr= (uint8_t)val;
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
+ counter_bdr_reg1.rst_counter_bdr = (uint8_t)val;
ret = iis3dwb_write_reg(ctx, IIS3DWB_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
}
+
return ret;
}
@@ -2661,7 +2972,7 @@ int32_t iis3dwb_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
*val = counter_bdr_reg1.rst_counter_bdr;
return ret;
@@ -2677,23 +2988,29 @@ int32_t iis3dwb_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t iis3dwb_batch_counter_threshold_set(stmdev_ctx_t *ctx,
- uint16_t val)
+ uint16_t val)
{
iis3dwb_counter_bdr_reg2_t counter_bdr_reg1;
iis3dwb_counter_bdr_reg2_t counter_bdr_reg2;
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if (ret == 0){
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
counter_bdr_reg1.cnt_bdr_th = (uint8_t)((0x0700U & val) >> 8);
- ret = iis3dwb_write_reg(ctx, IIS3DWB_COUNTER_BDR_REG1, (uint8_t*)&counter_bdr_reg1, 1);
+ ret = iis3dwb_write_reg(ctx, IIS3DWB_COUNTER_BDR_REG1,
+ (uint8_t *)&counter_bdr_reg1, 1);
}
- if (ret == 0){
+
+ if (ret == 0)
+ {
counter_bdr_reg2.cnt_bdr_th = (uint8_t)(0x00FFU & val);
ret = iis3dwb_write_reg(ctx, IIS3DWB_COUNTER_BDR_REG2,
- (uint8_t*)&counter_bdr_reg2, 1);
+ (uint8_t *)&counter_bdr_reg2, 1);
}
+
return ret;
}
@@ -2707,22 +3024,25 @@ int32_t iis3dwb_batch_counter_threshold_set(stmdev_ctx_t *ctx,
*
*/
int32_t iis3dwb_batch_counter_threshold_get(stmdev_ctx_t *ctx,
- uint16_t *val)
+ uint16_t *val)
{
iis3dwb_counter_bdr_reg1_t counter_bdr_reg1;
iis3dwb_counter_bdr_reg2_t counter_bdr_reg2;
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if (ret == 0){
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
ret = iis3dwb_read_reg(ctx, IIS3DWB_COUNTER_BDR_REG2,
- (uint8_t*)&counter_bdr_reg2, 1);
+ (uint8_t *)&counter_bdr_reg2, 1);
}
*val = counter_bdr_reg1.cnt_bdr_th;
*val = *val << 8;
*val += counter_bdr_reg2.cnt_bdr_th;
+
return ret;
}
@@ -2741,14 +3061,17 @@ int32_t iis3dwb_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_STATUS1,
- (uint8_t*)&fifo_status1, 1);
- if (ret == 0){
+ (uint8_t *)&fifo_status1, 1);
+
+ if (ret == 0)
+ {
ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
+ (uint8_t *)&fifo_status2, 1);
*val = fifo_status2.diff_fifo;
*val = *val << 8;
*val += fifo_status1.diff_fifo;
}
+
return ret;
}
@@ -2761,10 +3084,12 @@ int32_t iis3dwb_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
*
*/
int32_t iis3dwb_fifo_status_get(stmdev_ctx_t *ctx,
- iis3dwb_fifo_status2_t *val)
+ iis3dwb_fifo_status2_t *val)
{
int32_t ret;
- ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_STATUS2, (uint8_t*)val, 1);
+
+ ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_STATUS2, (uint8_t *)val, 1);
+
return ret;
}
@@ -2782,7 +3107,7 @@ int32_t iis3dwb_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
+ (uint8_t *)&fifo_status2, 1);
*val = fifo_status2.fifo_full_ia;
return ret;
@@ -2803,7 +3128,7 @@ int32_t iis3dwb_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
+ (uint8_t *)&fifo_status2, 1);
*val = fifo_status2. fifo_ovr_ia;
return ret;
@@ -2823,7 +3148,7 @@ int32_t iis3dwb_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
+ (uint8_t *)&fifo_status2, 1);
*val = fifo_status2.fifo_wtm_ia;
return ret;
@@ -2838,28 +3163,33 @@ int32_t iis3dwb_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t iis3dwb_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
- iis3dwb_fifo_tag_t *val)
+ iis3dwb_fifo_tag_t *val)
{
iis3dwb_fifo_data_out_tag_t fifo_data_out_tag;
int32_t ret;
ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_DATA_OUT_TAG,
- (uint8_t*)&fifo_data_out_tag, 1);
+ (uint8_t *)&fifo_data_out_tag, 1);
- switch (fifo_data_out_tag.tag_sensor){
+ switch (fifo_data_out_tag.tag_sensor)
+ {
case IIS3DWB_XL_TAG:
*val = IIS3DWB_XL_TAG;
break;
+
case IIS3DWB_TEMPERATURE_TAG:
*val = IIS3DWB_TEMPERATURE_TAG;
break;
+
case IIS3DWB_TIMESTAMP_TAG:
*val = IIS3DWB_TIMESTAMP_TAG;
break;
+
default:
*val = IIS3DWB_XL_TAG;
break;
}
+
return ret;
}
diff --git a/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.h b/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.h
index 2b0114c6f53e1fb634deff3d4ef2bd67e7fedb4f..110a49a9f7d11bbabd3f230703cf92cfc67038e7 100644
--- a/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.h
+++ b/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file iis3dwb_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * iis3dwb_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file iis3dwb_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * iis3dwb_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef IIS3DWB_REGS_H
#define IIS3DWB_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup IIS3DWB
@@ -74,7 +75,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -107,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -131,7 +134,7 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
+ * You can create a sensor configuration by your own or using
* Unico / Unicleo tools available on STMicroelectronics
* web site.
*
@@ -139,7 +142,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -174,7 +178,8 @@ typedef struct {
*/
#define IIS3DWB_PIN_CTRL 0x02U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 6;
uint8_t sdo_pu_en : 1;
@@ -187,12 +192,14 @@ typedef struct {
} iis3dwb_pin_ctrl_t;
#define IIS3DWB_FIFO_CTRL1 0x07U
-typedef struct {
+typedef struct
+{
uint8_t wtm : 8;
} iis3dwb_fifo_ctrl1_t;
#define IIS3DWB_FIFO_CTRL2 0x08U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wtm : 1;
uint8_t not_used_01 : 6;
@@ -205,7 +212,8 @@ typedef struct {
} iis3dwb_fifo_ctrl2_t;
#define IIS3DWB_FIFO_CTRL3 0x09U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bdr_xl : 4;
uint8_t not_used_01 : 4;
@@ -216,7 +224,8 @@ typedef struct {
} iis3dwb_fifo_ctrl3_t;
#define IIS3DWB_FIFO_CTRL4 0x0AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fifo_mode : 3;
uint8_t not_used_01 : 1;
@@ -231,7 +240,8 @@ typedef struct {
} iis3dwb_fifo_ctrl4_t;
#define IIS3DWB_COUNTER_BDR_REG1 0x0BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t cnt_bdr_th : 3;
uint8_t not_used_01 : 3;
@@ -246,12 +256,14 @@ typedef struct {
} iis3dwb_counter_bdr_reg1_t;
#define IIS3DWB_COUNTER_BDR_REG2 0x0CU
-typedef struct {
+typedef struct
+{
uint8_t cnt_bdr_th : 8;
} iis3dwb_counter_bdr_reg2_t;
#define IIS3DWB_INT1_CTRL 0x0DU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_drdy_xl : 1;
uint8_t not_used_01 : 1;
@@ -274,7 +286,8 @@ typedef struct {
} iis3dwb_int1_ctrl_t;
#define IIS3DWB_INT2_CTRL 0x0EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_drdy_xl : 1;
uint8_t not_used_01 : 1;
@@ -298,7 +311,8 @@ typedef struct {
#define IIS3DWB_WHO_AM_I 0x0FU
#define IIS3DWB_CTRL1_XL 0x10U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t lpf2_xl_en : 1;
@@ -315,7 +329,8 @@ typedef struct {
} iis3dwb_ctrl1_xl_t;
#define IIS3DWB_CTRL3_C 0x12U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sw_reset : 1;
uint8_t not_used_01 : 1;
@@ -338,7 +353,8 @@ typedef struct {
} iis3dwb_ctrl3_c_t;
#define IIS3DWB_CTRL4_C 0x13U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t _1ax_to_3regout : 1;
uint8_t lpf1_sel_g : 1;
@@ -359,7 +375,8 @@ typedef struct {
} iis3dwb_ctrl4_c_t;
#define IIS3DWB_CTRL5_C 0x14U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_xl : 2;
uint8_t not_used_01 : 3;
@@ -376,7 +393,8 @@ typedef struct {
} iis3dwb_ctrl5_c_t;
#define IIS3DWB_CTRL6_C 0x15U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl_axis_sel : 2;
uint8_t not_used_01 : 1;
@@ -391,7 +409,8 @@ typedef struct {
} iis3dwb_ctrl6_c_t;
#define IIS3DWB_CTRL8_XL 0x17U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t fds : 1;
@@ -408,7 +427,8 @@ typedef struct {
} iis3dwb_ctrl8_xl_t;
#define IIS3DWB_CTRL10_C 0x19U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 5;
uint8_t timestamp_en : 1;
@@ -421,7 +441,8 @@ typedef struct {
} iis3dwb_ctrl10_c_t;
#define IIS3DWB_ALL_INT_SRC 0x1AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t wu_ia : 1;
@@ -440,7 +461,8 @@ typedef struct {
} iis3dwb_all_int_src_t;
#define IIS3DWB_WAKE_UP_SRC 0x1BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_wu : 1;
uint8_t y_wu : 1;
@@ -463,7 +485,8 @@ typedef struct {
} iis3dwb_wake_up_src_t;
#define IIS3DWB_STATUS_REG 0x1EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlda : 1;
uint8_t not_used_01 : 1;
@@ -486,12 +509,14 @@ typedef struct {
#define IIS3DWB_OUTZ_L_A 0x2CU
#define IIS3DWB_OUTZ_H_A 0x2DU
#define IIS3DWB_FIFO_STATUS1 0x3AU
-typedef struct {
+typedef struct
+{
uint8_t diff_fifo : 8;
} iis3dwb_fifo_status1_t;
#define IIS3DWB_FIFO_STATUS2 0x3BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t diff_fifo : 2;
uint8_t not_used_01 : 1;
@@ -516,7 +541,8 @@ typedef struct {
#define IIS3DWB_TIMESTAMP2 0x42U
#define IIS3DWB_TIMESTAMP3 0x43U
#define IIS3DWB_SLOPE_EN 0x56U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lir : 1;
uint8_t not_used_01 : 3;
@@ -533,7 +559,8 @@ typedef struct {
} iis3dwb_slope_en_t;
#define IIS3DWB_INTERRUPTS_EN 0x58U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 7;
uint8_t interrupts_enable : 1;
@@ -544,7 +571,8 @@ typedef struct {
} iis3dwb_interrupts_en_t;
#define IIS3DWB_WAKE_UP_THS 0x5BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wk_ths : 6;
uint8_t usr_off_on_wu : 1;
@@ -557,7 +585,8 @@ typedef struct {
} iis3dwb_wake_up_ths_t;
#define IIS3DWB_WAKE_UP_DUR 0x5CU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sleep_dur : 4;
uint8_t wake_ths_w : 1;
@@ -572,7 +601,8 @@ typedef struct {
} iis3dwb_wake_up_dur_t;
#define IIS3DWB_MD1_CFG 0x5EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 5;
uint8_t int1_wu : 1;
@@ -587,7 +617,8 @@ typedef struct {
} iis3dwb_md1_cfg_t;
#define IIS3DWB_MD2_CFG 0x5FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_timestamp : 1;
uint8_t not_used_01 : 4;
@@ -604,7 +635,8 @@ typedef struct {
} iis3dwb_md2_cfg_t;
#define IIS3DWB_INTERNAL_FREQ_FINE 0x63U
-typedef struct {
+typedef struct
+{
uint8_t freq_fine : 8;
} iis3dwb_internal_freq_fine_t;
@@ -612,7 +644,8 @@ typedef struct {
#define IIS3DWB_Y_OFS_USR 0x74U
#define IIS3DWB_Z_OFS_USR 0x75U
#define IIS3DWB_FIFO_DATA_OUT_TAG 0x78U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tag_parity : 1;
uint8_t tag_cnt : 2;
@@ -633,9 +666,9 @@ typedef struct {
/**
* @defgroup IIS3DWB_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -643,7 +676,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
iis3dwb_pin_ctrl_t pin_ctrl;
iis3dwb_fifo_ctrl1_t fifo_ctrl1;
iis3dwb_fifo_ctrl2_t fifo_ctrl2;
@@ -682,38 +716,50 @@ typedef union{
*
*/
-int32_t iis3dwb_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t iis3dwb_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t iis3dwb_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t iis3dwb_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-extern float_t iis3dwb_from_fs2g_to_mg(int16_t lsb);
-extern float_t iis3dwb_from_fs4g_to_mg(int16_t lsb);
-extern float_t iis3dwb_from_fs8g_to_mg(int16_t lsb);
-extern float_t iis3dwb_from_fs16g_to_mg(int16_t lsb);
+float_t iis3dwb_from_fs2g_to_mg(int16_t lsb);
+float_t iis3dwb_from_fs4g_to_mg(int16_t lsb);
+float_t iis3dwb_from_fs8g_to_mg(int16_t lsb);
+float_t iis3dwb_from_fs16g_to_mg(int16_t lsb);
+
extern float_t iis3dwb_from_lsb_to_celsius(int16_t lsb);
+
extern float_t iis3dwb_from_lsb_to_nsec(int32_t lsb);
-typedef enum {
+typedef enum
+{
IIS3DWB_2g = 0,
IIS3DWB_16g = 1, /* if XL_FS_MODE = ‘1’ -> IIS3DWB_2g */
IIS3DWB_4g = 2,
IIS3DWB_8g = 3,
} iis3dwb_fs_xl_t;
-int32_t iis3dwb_xl_full_scale_set(stmdev_ctx_t *ctx, iis3dwb_fs_xl_t val);
-int32_t iis3dwb_xl_full_scale_get(stmdev_ctx_t *ctx, iis3dwb_fs_xl_t *val);
+int32_t iis3dwb_xl_full_scale_set(stmdev_ctx_t *ctx,
+ iis3dwb_fs_xl_t val);
+int32_t iis3dwb_xl_full_scale_get(stmdev_ctx_t *ctx,
+ iis3dwb_fs_xl_t *val);
-typedef enum {
+typedef enum
+{
IIS3DWB_XL_ODR_OFF = 0,
IIS3DWB_XL_ODR_26k7Hz = 5,
} iis3dwb_odr_xl_t;
-int32_t iis3dwb_xl_data_rate_set(stmdev_ctx_t *ctx, iis3dwb_odr_xl_t val);
-int32_t iis3dwb_xl_data_rate_get(stmdev_ctx_t *ctx, iis3dwb_odr_xl_t *val);
+int32_t iis3dwb_xl_data_rate_set(stmdev_ctx_t *ctx,
+ iis3dwb_odr_xl_t val);
+int32_t iis3dwb_xl_data_rate_get(stmdev_ctx_t *ctx,
+ iis3dwb_odr_xl_t *val);
int32_t iis3dwb_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis3dwb_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis3dwb_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS3DWB_LSb_1mg = 0,
IIS3DWB_LSb_16mg = 1,
} iis3dwb_usr_off_w_t;
@@ -722,7 +768,8 @@ int32_t iis3dwb_xl_offset_weight_set(stmdev_ctx_t *ctx,
int32_t iis3dwb_xl_offset_weight_get(stmdev_ctx_t *ctx,
iis3dwb_usr_off_w_t *val);
-typedef enum {
+typedef enum
+{
IIS3DWB_ENABLE_ALL = 0,
IIS3DWB_ONLY_X_ON_ONE_OUT_REG = 0x01,
IIS3DWB_ONLY_Y_ON_ONE_OUT_REG = 0x02,
@@ -736,20 +783,23 @@ int32_t iis3dwb_xl_axis_selection_set(stmdev_ctx_t *ctx,
int32_t iis3dwb_xl_axis_selection_get(stmdev_ctx_t *ctx,
iis3dwb_xl_axis_sel_t *val);
-typedef struct {
+typedef struct
+{
iis3dwb_all_int_src_t all_int_src;
iis3dwb_wake_up_src_t wake_up_src;
iis3dwb_status_reg_t status_reg;
- } iis3dwb_all_sources_t;
+} iis3dwb_all_sources_t;
int32_t iis3dwb_all_sources_get(stmdev_ctx_t *ctx,
iis3dwb_all_sources_t *val);
int32_t iis3dwb_status_reg_get(stmdev_ctx_t *ctx,
iis3dwb_status_reg_t *val);
-int32_t iis3dwb_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis3dwb_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t iis3dwb_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis3dwb_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t iis3dwb_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t iis3dwb_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff);
@@ -770,7 +820,8 @@ int32_t iis3dwb_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t iis3dwb_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val);
-typedef enum {
+typedef enum
+{
IIS3DWB_NO_ROUND = 0,
IIS3DWB_ROUND = 1,
} iis3dwb_rounding_t;
@@ -788,7 +839,8 @@ int32_t iis3dwb_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t iis3dwb_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis3dwb_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS3DWB_DRDY_LATCHED = 0,
IIS3DWB_DRDY_PULSED = 1,
} iis3dwb_dataready_pulsed_t;
@@ -808,13 +860,16 @@ int32_t iis3dwb_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t iis3dwb_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis3dwb_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS3DWB_XL_ST_DISABLE = 0,
IIS3DWB_XL_ST_POSITIVE = 1,
IIS3DWB_XL_ST_NEGATIVE = 2,
} iis3dwb_st_xl_t;
-int32_t iis3dwb_xl_self_test_set(stmdev_ctx_t *ctx, iis3dwb_st_xl_t val);
-int32_t iis3dwb_xl_self_test_get(stmdev_ctx_t *ctx, iis3dwb_st_xl_t *val);
+int32_t iis3dwb_xl_self_test_set(stmdev_ctx_t *ctx,
+ iis3dwb_st_xl_t val);
+int32_t iis3dwb_xl_self_test_get(stmdev_ctx_t *ctx,
+ iis3dwb_st_xl_t *val);
int32_t iis3dwb_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis3dwb_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -824,7 +879,8 @@ int32_t iis3dwb_filter_settling_mask_set(stmdev_ctx_t *ctx,
int32_t iis3dwb_filter_settling_mask_get(stmdev_ctx_t *ctx,
uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS3DWB_SLOPE_ODR_DIV_4 = 0x30,
IIS3DWB_HP_ODR_DIV_10 = 0x11,
IIS3DWB_HP_ODR_DIV_20 = 0x12,
@@ -851,7 +907,8 @@ int32_t iis3dwb_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
int32_t iis3dwb_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis3dwb_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS3DWB_USE_SLOPE = 0,
IIS3DWB_USE_HPF = 1,
} iis3dwb_slope_fds_t;
@@ -860,21 +917,26 @@ int32_t iis3dwb_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
int32_t iis3dwb_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
iis3dwb_slope_fds_t *val);
-typedef enum {
+typedef enum
+{
IIS3DWB_PULL_UP_DISC = 0,
IIS3DWB_PULL_UP_CONNECT = 1,
} iis3dwb_sdo_pu_en_t;
-int32_t iis3dwb_sdo_sa0_mode_set(stmdev_ctx_t *ctx, iis3dwb_sdo_pu_en_t val);
-int32_t iis3dwb_sdo_sa0_mode_get(stmdev_ctx_t *ctx, iis3dwb_sdo_pu_en_t *val);
+int32_t iis3dwb_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
+ iis3dwb_sdo_pu_en_t val);
+int32_t iis3dwb_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
+ iis3dwb_sdo_pu_en_t *val);
-typedef enum {
+typedef enum
+{
IIS3DWB_SPI_4_WIRE = 0,
IIS3DWB_SPI_3_WIRE = 1,
} iis3dwb_sim_t;
int32_t iis3dwb_spi_mode_set(stmdev_ctx_t *ctx, iis3dwb_sim_t val);
int32_t iis3dwb_spi_mode_get(stmdev_ctx_t *ctx, iis3dwb_sim_t *val);
-typedef enum {
+typedef enum
+{
IIS3DWB_I2C_ENABLE = 0,
IIS3DWB_I2C_DISABLE = 1,
} iis3dwb_i2c_disable_t;
@@ -883,7 +945,8 @@ int32_t iis3dwb_i2c_interface_set(stmdev_ctx_t *ctx,
int32_t iis3dwb_i2c_interface_get(stmdev_ctx_t *ctx,
iis3dwb_i2c_disable_t *val);
-typedef struct {
+typedef struct
+{
uint8_t drdy_xl : 1; /* Accelerometer data ready */
uint8_t boot : 1; /* Restoring calibration parameters */
uint8_t fifo_th : 1; /* FIFO threshold reached */
@@ -891,7 +954,8 @@ typedef struct {
uint8_t fifo_full : 1; /* FIFO full */
uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */
uint8_t wake_up : 1; /* wake up event */
- uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */
+uint8_t sleep_change :
+ 1; /* Act/Inact (or Vice-versa) status changed */
uint8_t sleep_status : 1; /* Act/Inact status */
} iis3dwb_pin_int1_route_t;
int32_t iis3dwb_pin_int1_route_set(stmdev_ctx_t *ctx,
@@ -899,7 +963,8 @@ int32_t iis3dwb_pin_int1_route_set(stmdev_ctx_t *ctx,
int32_t iis3dwb_pin_int1_route_get(stmdev_ctx_t *ctx,
iis3dwb_pin_int1_route_t *val);
-typedef struct {
+typedef struct
+{
uint8_t drdy_xl : 1; /* Accelerometer data ready */
uint8_t drdy_temp : 1; /* Temperature data ready */
uint8_t fifo_th : 1; /* FIFO threshold reached */
@@ -908,7 +973,8 @@ typedef struct {
uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */
uint8_t timestamp : 1; /* timestamp overflow */
uint8_t wake_up : 1; /* wake up event */
- uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */
+uint8_t sleep_change :
+ 1; /* Act/Inact (or Vice-versa) status changed */
uint8_t sleep_status : 1; /* Act/Inact status */
} iis3dwb_pin_int2_route_t;
int32_t iis3dwb_pin_int2_route_set(stmdev_ctx_t *ctx,
@@ -916,31 +982,39 @@ int32_t iis3dwb_pin_int2_route_set(stmdev_ctx_t *ctx,
int32_t iis3dwb_pin_int2_route_get(stmdev_ctx_t *ctx,
iis3dwb_pin_int2_route_t *val);
-typedef enum {
+typedef enum
+{
IIS3DWB_PUSH_PULL = 0,
IIS3DWB_OPEN_DRAIN = 1,
} iis3dwb_pp_od_t;
int32_t iis3dwb_pin_mode_set(stmdev_ctx_t *ctx, iis3dwb_pp_od_t val);
int32_t iis3dwb_pin_mode_get(stmdev_ctx_t *ctx, iis3dwb_pp_od_t *val);
-typedef enum {
+typedef enum
+{
IIS3DWB_ACTIVE_HIGH = 0,
IIS3DWB_ACTIVE_LOW = 1,
} iis3dwb_h_lactive_t;
-int32_t iis3dwb_pin_polarity_set(stmdev_ctx_t *ctx, iis3dwb_h_lactive_t val);
-int32_t iis3dwb_pin_polarity_get(stmdev_ctx_t *ctx, iis3dwb_h_lactive_t *val);
+int32_t iis3dwb_pin_polarity_set(stmdev_ctx_t *ctx,
+ iis3dwb_h_lactive_t val);
+int32_t iis3dwb_pin_polarity_get(stmdev_ctx_t *ctx,
+ iis3dwb_h_lactive_t *val);
int32_t iis3dwb_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis3dwb_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS3DWB_INT_PULSED = 0,
IIS3DWB_INT_LATCHED = 1,
} iis3dwb_lir_t;
-int32_t iis3dwb_int_notification_set(stmdev_ctx_t *ctx, iis3dwb_lir_t val);
-int32_t iis3dwb_int_notification_get(stmdev_ctx_t *ctx, iis3dwb_lir_t *val);
+int32_t iis3dwb_int_notification_set(stmdev_ctx_t *ctx,
+ iis3dwb_lir_t val);
+int32_t iis3dwb_int_notification_get(stmdev_ctx_t *ctx,
+ iis3dwb_lir_t *val);
-typedef enum {
+typedef enum
+{
IIS3DWB_LSb_FS_DIV_64 = 0,
IIS3DWB_LSb_FS_DIV_256 = 1,
} iis3dwb_wake_ths_w_t;
@@ -952,8 +1026,10 @@ int32_t iis3dwb_wkup_ths_weight_get(stmdev_ctx_t *ctx,
int32_t iis3dwb_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis3dwb_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t iis3dwb_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis3dwb_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis3dwb_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t iis3dwb_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t iis3dwb_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis3dwb_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -967,14 +1043,18 @@ int32_t iis3dwb_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val);
int32_t iis3dwb_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t iis3dwb_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS3DWB_XL_NOT_BATCHED = 0,
IIS3DWB_XL_BATCHED_AT_26k7Hz = 10,
} iis3dwb_bdr_xl_t;
-int32_t iis3dwb_fifo_xl_batch_set(stmdev_ctx_t *ctx, iis3dwb_bdr_xl_t val);
-int32_t iis3dwb_fifo_xl_batch_get(stmdev_ctx_t *ctx, iis3dwb_bdr_xl_t *val);
+int32_t iis3dwb_fifo_xl_batch_set(stmdev_ctx_t *ctx,
+ iis3dwb_bdr_xl_t val);
+int32_t iis3dwb_fifo_xl_batch_get(stmdev_ctx_t *ctx,
+ iis3dwb_bdr_xl_t *val);
-typedef enum {
+typedef enum
+{
IIS3DWB_BYPASS_MODE = 0,
IIS3DWB_FIFO_MODE = 1,
IIS3DWB_STREAM_TO_FIFO_MODE = 3,
@@ -982,10 +1062,13 @@ typedef enum {
IIS3DWB_STREAM_MODE = 6,
IIS3DWB_BYPASS_TO_FIFO_MODE = 7,
} iis3dwb_fifo_mode_t;
-int32_t iis3dwb_fifo_mode_set(stmdev_ctx_t *ctx, iis3dwb_fifo_mode_t val);
-int32_t iis3dwb_fifo_mode_get(stmdev_ctx_t *ctx, iis3dwb_fifo_mode_t *val);
+int32_t iis3dwb_fifo_mode_set(stmdev_ctx_t *ctx,
+ iis3dwb_fifo_mode_t val);
+int32_t iis3dwb_fifo_mode_get(stmdev_ctx_t *ctx,
+ iis3dwb_fifo_mode_t *val);
-typedef enum {
+typedef enum
+{
IIS3DWB_TEMP_NOT_BATCHED = 0,
IIS3DWB_TEMP_BATCHED_AT_104Hz = 3,
} iis3dwb_odr_t_batch_t;
@@ -994,7 +1077,8 @@ int32_t iis3dwb_fifo_temp_batch_set(stmdev_ctx_t *ctx,
int32_t iis3dwb_fifo_temp_batch_get(stmdev_ctx_t *ctx,
iis3dwb_odr_t_batch_t *val);
-typedef enum {
+typedef enum
+{
IIS3DWB_NO_DECIMATION = 0,
IIS3DWB_DEC_1 = 1,
IIS3DWB_DEC_8 = 2,
@@ -1006,7 +1090,8 @@ int32_t iis3dwb_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
iis3dwb_odr_ts_batch_t *val);
int32_t iis3dwb_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t iis3dwb_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t iis3dwb_rst_batch_counter_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t iis3dwb_batch_counter_threshold_set(stmdev_ctx_t *ctx,
uint16_t val);
@@ -1024,13 +1109,14 @@ int32_t iis3dwb_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t iis3dwb_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
IIS3DWB_XL_TAG = 2,
IIS3DWB_TEMPERATURE_TAG,
IIS3DWB_TIMESTAMP_TAG,
} iis3dwb_fifo_tag_t;
int32_t iis3dwb_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
- iis3dwb_fifo_tag_t *val);
+ iis3dwb_fifo_tag_t *val);
/**
*@}
diff --git a/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.c b/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.c
index 80ac3dde79906dd5cfcdfd955efd2f16bee8f5af..fad8ecd93d691bc2f5da22c3c4780425afcf5074 100644
--- a/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.c
+++ b/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file ism303dac_reg.c
- * @author Sensors Software Solution Team
- * @brief ISM303DAC driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file ism303dac_reg.c
+ * @author Sensors Software Solution Team
+ * @brief ISM303DAC driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "ism303dac_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ism303dac_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t ism303dac_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t ism303dac_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ism303dac_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t ism303dac_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -141,26 +147,36 @@ int32_t ism303dac_xl_all_sources_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_SRC_A,
- (uint8_t*)&(val->fifo_src_a), 1);
- if(ret == 0){
+ (uint8_t *) & (val->fifo_src_a), 1);
+
+ if (ret == 0)
+ {
ret = ism303dac_read_reg(ctx, ISM303DAC_STATUS_DUP_A,
- (uint8_t*)&(val->status_dup_a), 1);
+ (uint8_t *) & (val->status_dup_a), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_SRC_A,
- (uint8_t*)&(val->wake_up_src_a), 1);
+ (uint8_t *) & (val->wake_up_src_a), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism303dac_read_reg(ctx, ISM303DAC_TAP_SRC_A,
- (uint8_t*)&(val->tap_src_a), 1);
+ (uint8_t *) & (val->tap_src_a), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism303dac_read_reg(ctx, ISM303DAC_6D_SRC_A,
- (uint8_t*)&(val->_6d_src_a), 1);
+ (uint8_t *) & (val->_6d_src_a), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism303dac_read_reg(ctx, ISM303DAC_FUNC_SRC_A,
- (uint8_t*)&(val->func_src_a), 1);
+ (uint8_t *) & (val->func_src_a), 1);
}
return ret;
@@ -174,16 +190,20 @@ int32_t ism303dac_xl_all_sources_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism303dac_xl_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ism303dac_xl_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
ism303dac_ctrl1_a_t ctrl1_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL1_A, (uint8_t*)&ctrl1_a, 1);
- if(ret == 0){
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL1_A, (uint8_t *)&ctrl1_a, 1);
+
+ if (ret == 0)
+ {
ctrl1_a.bdu = val;
- ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL1_A,(uint8_t*)&ctrl1_a, 1);
+ ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL1_A, (uint8_t *)&ctrl1_a, 1);
}
+
return ret;
}
@@ -195,12 +215,13 @@ int32_t ism303dac_xl_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism303dac_xl_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism303dac_xl_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism303dac_ctrl1_a_t ctrl1_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL1_A, (uint8_t*)&ctrl1_a, 1);
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL1_A, (uint8_t *)&ctrl1_a, 1);
*val = ctrl1_a.bdu;
return ret;
@@ -214,19 +235,22 @@ int32_t ism303dac_xl_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism303dac_mg_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ism303dac_mg_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
ism303dac_cfg_reg_c_m_t cfg_reg_c_m;
int32_t ret;
-
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_c_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_c_m.bdu = val;
ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
+ (uint8_t *)&cfg_reg_c_m, 1);
}
+
return ret;
}
@@ -238,13 +262,14 @@ int32_t ism303dac_mg_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism303dac_mg_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism303dac_mg_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism303dac_cfg_reg_c_m_t cfg_reg_c_m;
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
+ (uint8_t *)&cfg_reg_c_m, 1);
*val = cfg_reg_c_m.bdu;
return ret;
@@ -265,13 +290,15 @@ int32_t ism303dac_mg_data_format_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_c_m, 1);
+ if (ret == 0)
+ {
cfg_reg_c_m.ble = (uint8_t)val;
ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
+ (uint8_t *)&cfg_reg_c_m, 1);
}
+
return ret;
}
@@ -290,18 +317,23 @@ int32_t ism303dac_mg_data_format_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
- switch (cfg_reg_c_m.ble){
+ (uint8_t *)&cfg_reg_c_m, 1);
+
+ switch (cfg_reg_c_m.ble)
+ {
case ISM303DAC_MG_LSB_AT_LOW_ADD:
*val = ISM303DAC_MG_LSB_AT_LOW_ADD;
break;
+
case ISM303DAC_MG_MSB_AT_LOW_ADD:
*val = ISM303DAC_MG_MSB_AT_LOW_ADD;
break;
+
default:
*val = ISM303DAC_MG_LSB_AT_LOW_ADD;
break;
}
+
return ret;
}
@@ -319,12 +351,14 @@ int32_t ism303dac_xl_full_scale_set(stmdev_ctx_t *ctx,
ism303dac_ctrl1_a_t ctrl1_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL1_A, (uint8_t*)&ctrl1_a, 1);
- if(ret == 0){
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL1_A, (uint8_t *)&ctrl1_a, 1);
+ if (ret == 0)
+ {
ctrl1_a.fs = (uint8_t)val;
- ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL1_A, (uint8_t*)&ctrl1_a, 1);
+ ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL1_A, (uint8_t *)&ctrl1_a, 1);
}
+
return ret;
}
@@ -342,21 +376,26 @@ int32_t ism303dac_xl_full_scale_get(stmdev_ctx_t *ctx,
ism303dac_ctrl1_a_t ctrl1_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL1_A, (uint8_t*)&ctrl1_a, 1);
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL1_A, (uint8_t *)&ctrl1_a, 1);
- switch (ctrl1_a.fs){
+ switch (ctrl1_a.fs)
+ {
case ISM303DAC_XL_2g:
*val = ISM303DAC_XL_2g;
break;
+
case ISM303DAC_XL_16g:
*val = ISM303DAC_XL_16g;
break;
+
case ISM303DAC_XL_4g:
*val = ISM303DAC_XL_4g;
break;
+
case ISM303DAC_XL_8g:
*val = ISM303DAC_XL_8g;
break;
+
default:
*val = ISM303DAC_XL_2g;
break;
@@ -379,13 +418,15 @@ int32_t ism303dac_xl_data_rate_set(stmdev_ctx_t *ctx,
ism303dac_ctrl1_a_t ctrl1_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL1_A, (uint8_t*)&ctrl1_a, 1);
- if(ret == 0){
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL1_A, (uint8_t *)&ctrl1_a, 1);
+ if (ret == 0)
+ {
ctrl1_a.odr = (uint8_t)val & 0x0FU;
ctrl1_a.hf_odr = ((uint8_t)val & 0x10U) >> 4;
- ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL1_A, (uint8_t*)&ctrl1_a, 1);
+ ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL1_A, (uint8_t *)&ctrl1_a, 1);
}
+
return ret;
}
@@ -403,66 +444,86 @@ int32_t ism303dac_xl_data_rate_get(stmdev_ctx_t *ctx,
ism303dac_ctrl1_a_t ctrl1_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL1_A, (uint8_t*)&ctrl1_a, 1);
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL1_A, (uint8_t *)&ctrl1_a, 1);
- switch ((ctrl1_a.hf_odr << 4) + ctrl1_a.odr){
+ switch ((ctrl1_a.hf_odr << 4) + ctrl1_a.odr)
+ {
case ISM303DAC_XL_ODR_OFF:
*val = ISM303DAC_XL_ODR_OFF;
break;
+
case ISM303DAC_XL_ODR_1Hz_LP:
*val = ISM303DAC_XL_ODR_1Hz_LP;
break;
+
case ISM303DAC_XL_ODR_12Hz5_LP:
*val = ISM303DAC_XL_ODR_12Hz5_LP;
break;
+
case ISM303DAC_XL_ODR_25Hz_LP:
*val = ISM303DAC_XL_ODR_25Hz_LP;
break;
+
case ISM303DAC_XL_ODR_50Hz_LP:
*val = ISM303DAC_XL_ODR_50Hz_LP;
break;
+
case ISM303DAC_XL_ODR_100Hz_LP:
*val = ISM303DAC_XL_ODR_100Hz_LP;
break;
+
case ISM303DAC_XL_ODR_200Hz_LP:
*val = ISM303DAC_XL_ODR_200Hz_LP;
break;
+
case ISM303DAC_XL_ODR_400Hz_LP:
*val = ISM303DAC_XL_ODR_400Hz_LP;
break;
+
case ISM303DAC_XL_ODR_800Hz_LP:
*val = ISM303DAC_XL_ODR_800Hz_LP;
break;
+
case ISM303DAC_XL_ODR_12Hz5_HR:
*val = ISM303DAC_XL_ODR_12Hz5_HR;
break;
+
case ISM303DAC_XL_ODR_25Hz_HR:
*val = ISM303DAC_XL_ODR_25Hz_HR;
break;
+
case ISM303DAC_XL_ODR_50Hz_HR:
*val = ISM303DAC_XL_ODR_50Hz_HR;
break;
+
case ISM303DAC_XL_ODR_100Hz_HR:
*val = ISM303DAC_XL_ODR_100Hz_HR;
break;
+
case ISM303DAC_XL_ODR_200Hz_HR:
*val = ISM303DAC_XL_ODR_200Hz_HR;
break;
+
case ISM303DAC_XL_ODR_400Hz_HR:
*val = ISM303DAC_XL_ODR_400Hz_HR;
break;
+
case ISM303DAC_XL_ODR_800Hz_HR:
*val = ISM303DAC_XL_ODR_800Hz_HR;
break;
+
case ISM303DAC_XL_ODR_1k6Hz_HF:
*val = ISM303DAC_XL_ODR_1k6Hz_HF;
break;
+
case ISM303DAC_XL_ODR_3k2Hz_HF:
*val = ISM303DAC_XL_ODR_3k2Hz_HF;
break;
+
case ISM303DAC_XL_ODR_6k4Hz_HF:
*val = ISM303DAC_XL_ODR_6k4Hz_HF;
break;
+
default:
*val = ISM303DAC_XL_ODR_OFF;
break;
@@ -483,7 +544,9 @@ int32_t ism303dac_xl_status_reg_get(stmdev_ctx_t *ctx,
ism303dac_status_a_t *val)
{
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_STATUS_A, (uint8_t*) val, 1);
+
+ ret = ism303dac_read_reg(ctx, ISM303DAC_STATUS_A, (uint8_t *) val, 1);
+
return ret;
}
@@ -499,7 +562,9 @@ int32_t ism303dac_mg_status_get(stmdev_ctx_t *ctx,
ism303dac_status_reg_m_t *val)
{
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_STATUS_REG_M, (uint8_t*) val, 1);
+
+ ret = ism303dac_read_reg(ctx, ISM303DAC_STATUS_REG_M, (uint8_t *) val, 1);
+
return ret;
}
@@ -511,12 +576,14 @@ int32_t ism303dac_mg_status_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism303dac_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism303dac_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism303dac_status_a_t status_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_STATUS_A, (uint8_t*)&status_a, 1);
+ ret = ism303dac_read_reg(ctx, ISM303DAC_STATUS_A,
+ (uint8_t *)&status_a, 1);
*val = status_a.drdy;
return ret;
@@ -536,7 +603,7 @@ int32_t ism303dac_mg_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_STATUS_REG_M,
- (uint8_t*)&status_reg_m, 1);
+ (uint8_t *)&status_reg_m, 1);
*val = status_reg_m.zyxda;
return ret;
@@ -556,7 +623,7 @@ int32_t ism303dac_mg_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_STATUS_REG_M,
- (uint8_t*)&status_reg_m, 1);
+ (uint8_t *)&status_reg_m, 1);
*val = status_reg_m.zyxor;
return ret;
@@ -579,12 +646,12 @@ int32_t ism303dac_mg_user_offset_set(stmdev_ctx_t *ctx, uint16_t *val)
uint8_t buff[6];
int32_t ret;
- buff[1] = (uint8_t) ((uint16_t)val[0] / 256U);
- buff[0] = (uint8_t) ((uint16_t)val[0] - (buff[1] * 256U));
- buff[3] = (uint8_t) ((uint16_t)val[1] / 256U);
- buff[2] = (uint8_t) ((uint16_t)val[1] - (buff[3] * 256U));
- buff[5] = (uint8_t) ((uint16_t)val[2] / 256U);
- buff[4] = (uint8_t) ((uint16_t)val[2] - (buff[5] * 256U));
+ buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
+ buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
+ buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
+ buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
+ buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
+ buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
ret = ism303dac_write_reg(ctx, ISM303DAC_OFFSET_X_REG_L_M, buff, 6);
return ret;
@@ -627,19 +694,21 @@ int32_t ism303dac_mg_user_offset_get(stmdev_ctx_t *ctx, uint16_t *val)
*
*/
int32_t ism303dac_mg_operating_mode_set(stmdev_ctx_t *ctx,
- ism303dac_mg_md_t val)
+ ism303dac_mg_md_t val)
{
ism303dac_cfg_reg_a_m_t cfg_reg_a_m;
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_a_m, 1);
+ if (ret == 0)
+ {
cfg_reg_a_m.md = (uint8_t)val;
ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
+ (uint8_t *)&cfg_reg_a_m, 1);
}
+
return ret;
}
@@ -652,24 +721,28 @@ int32_t ism303dac_mg_operating_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism303dac_mg_operating_mode_get(stmdev_ctx_t *ctx,
- ism303dac_mg_md_t *val)
+ ism303dac_mg_md_t *val)
{
ism303dac_cfg_reg_a_m_t cfg_reg_a_m;
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
+ (uint8_t *)&cfg_reg_a_m, 1);
- switch (cfg_reg_a_m.md){
+ switch (cfg_reg_a_m.md)
+ {
case ISM303DAC_MG_CONTINUOUS_MODE:
*val = ISM303DAC_MG_CONTINUOUS_MODE;
break;
+
case ISM303DAC_MG_SINGLE_TRIGGER:
*val = ISM303DAC_MG_SINGLE_TRIGGER;
break;
+
case ISM303DAC_MG_POWER_DOWN:
*val = ISM303DAC_MG_POWER_DOWN;
break;
+
default:
*val = ISM303DAC_MG_CONTINUOUS_MODE;
break;
@@ -693,13 +766,15 @@ int32_t ism303dac_mg_data_rate_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_a_m, 1);
+ if (ret == 0)
+ {
cfg_reg_a_m.odr = (uint8_t)val;
ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
+ (uint8_t *)&cfg_reg_a_m, 1);
}
+
return ret;
}
@@ -718,21 +793,26 @@ int32_t ism303dac_mg_data_rate_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
+ (uint8_t *)&cfg_reg_a_m, 1);
- switch (cfg_reg_a_m.odr){
+ switch (cfg_reg_a_m.odr)
+ {
case ISM303DAC_MG_ODR_10Hz:
*val = ISM303DAC_MG_ODR_10Hz;
break;
+
case ISM303DAC_MG_ODR_20Hz:
*val = ISM303DAC_MG_ODR_20Hz;
break;
+
case ISM303DAC_MG_ODR_50Hz:
*val = ISM303DAC_MG_ODR_50Hz;
break;
+
case ISM303DAC_MG_ODR_100Hz:
*val = ISM303DAC_MG_ODR_100Hz;
break;
+
default:
*val = ISM303DAC_MG_ODR_10Hz;
break;
@@ -756,13 +836,15 @@ int32_t ism303dac_mg_power_mode_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_a_m, 1);
+ if (ret == 0)
+ {
cfg_reg_a_m.lp = (uint8_t)val;
ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
+ (uint8_t *)&cfg_reg_a_m, 1);
}
+
return ret;
}
@@ -781,15 +863,18 @@ int32_t ism303dac_mg_power_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
+ (uint8_t *)&cfg_reg_a_m, 1);
- switch (cfg_reg_a_m.lp){
+ switch (cfg_reg_a_m.lp)
+ {
case ISM303DAC_MG_HIGH_RESOLUTION:
*val = ISM303DAC_MG_HIGH_RESOLUTION;
break;
+
case ISM303DAC_MG_LOW_POWER:
*val = ISM303DAC_MG_LOW_POWER;
break;
+
default:
*val = ISM303DAC_MG_HIGH_RESOLUTION;
break;
@@ -806,19 +891,22 @@ int32_t ism303dac_mg_power_mode_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism303dac_mg_offset_temp_comp_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ism303dac_mg_offset_temp_comp_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
ism303dac_cfg_reg_a_m_t cfg_reg_a_m;
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_a_m, 1);
+ if (ret == 0)
+ {
cfg_reg_a_m.comp_temp_en = val;
ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
+ (uint8_t *)&cfg_reg_a_m, 1);
}
+
return ret;
}
@@ -830,13 +918,14 @@ int32_t ism303dac_mg_offset_temp_comp_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism303dac_mg_offset_temp_comp_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism303dac_mg_offset_temp_comp_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism303dac_cfg_reg_a_m_t cfg_reg_a_m;
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
+ (uint8_t *)&cfg_reg_a_m, 1);
*val = cfg_reg_a_m.comp_temp_en;
return ret;
@@ -857,13 +946,15 @@ int32_t ism303dac_mg_set_rst_mode_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_B_M,
- (uint8_t*)&cfg_reg_b_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_b_m, 1);
+ if (ret == 0)
+ {
cfg_reg_b_m.set_rst = (uint8_t)val;
ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_B_M,
- (uint8_t*)&cfg_reg_b_m, 1);
+ (uint8_t *)&cfg_reg_b_m, 1);
}
+
return ret;
}
@@ -882,18 +973,22 @@ int32_t ism303dac_mg_set_rst_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_B_M,
- (uint8_t*)&cfg_reg_b_m, 1);
+ (uint8_t *)&cfg_reg_b_m, 1);
- switch (cfg_reg_b_m.set_rst){
+ switch (cfg_reg_b_m.set_rst)
+ {
case ISM303DAC_MG_SET_SENS_ODR_DIV_63:
*val = ISM303DAC_MG_SET_SENS_ODR_DIV_63;
break;
+
case ISM303DAC_MG_SENS_OFF_CANC_EVERY_ODR:
*val = ISM303DAC_MG_SENS_OFF_CANC_EVERY_ODR;
break;
+
case ISM303DAC_MG_SET_SENS_ONLY_AT_POWER_ON:
*val = ISM303DAC_MG_SET_SENS_ONLY_AT_POWER_ON;
break;
+
default:
*val = ISM303DAC_MG_SET_SENS_ODR_DIV_63;
break;
@@ -920,13 +1015,15 @@ int32_t ism303dac_mg_set_rst_sensor_single_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_B_M,
- (uint8_t*)&cfg_reg_b_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_b_m, 1);
+ if (ret == 0)
+ {
cfg_reg_b_m.off_canc_one_shot = val;
ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_B_M,
- (uint8_t*)&cfg_reg_b_m, 1);
+ (uint8_t *)&cfg_reg_b_m, 1);
}
+
return ret;
}
@@ -948,7 +1045,7 @@ int32_t ism303dac_mg_set_rst_sensor_single_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_B_M,
- (uint8_t*)&cfg_reg_b_m, 1);
+ (uint8_t *)&cfg_reg_b_m, 1);
*val = cfg_reg_b_m.off_canc_one_shot;
return ret;
@@ -978,7 +1075,9 @@ int32_t ism303dac_acceleration_module_raw_get(stmdev_ctx_t *ctx,
uint8_t *buff)
{
int32_t ret;
+
ret = ism303dac_read_reg(ctx, ISM303DAC_MODULE_8BIT_A, buff, 1);
+
return ret;
}
@@ -991,10 +1090,13 @@ int32_t ism303dac_acceleration_module_raw_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism303dac_xl_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t ism303dac_xl_temperature_raw_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
+
ret = ism303dac_read_reg(ctx, ISM303DAC_OUT_T_A, buff, 1);
+
return ret;
}
@@ -1007,18 +1109,19 @@ int32_t ism303dac_xl_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism303dac_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
+int32_t ism303dac_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
{
uint8_t buff[6];
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_OUT_X_L_A, buff, 6);
val[0] = (int16_t)buff[1];
- val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
- val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
val[2] = (int16_t)buff[5];
- val[2] = (val[2] * 256) + (int16_t)buff[4];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
return ret;
}
@@ -1038,11 +1141,11 @@ int32_t ism303dac_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val)
ret = ism303dac_read_reg(ctx, ISM303DAC_OUTX_L_REG_M, buff, 6);
val[0] = (int16_t)buff[1];
- val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
- val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
val[2] = (int16_t)buff[5];
- val[2] = (val[2] * 256) + (int16_t)buff[4];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
return ret;
}
@@ -1070,7 +1173,9 @@ int32_t ism303dac_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val)
int32_t ism303dac_xl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = ism303dac_read_reg(ctx, ISM303DAC_WHO_AM_I_A, buff, 1);
+
return ret;
}
@@ -1085,7 +1190,9 @@ int32_t ism303dac_xl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t ism303dac_mg_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = ism303dac_read_reg(ctx, ISM303DAC_WHO_AM_I_M, buff, 1);
+
return ret;
}
@@ -1098,17 +1205,20 @@ int32_t ism303dac_mg_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism303dac_xl_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ism303dac_xl_auto_increment_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
ism303dac_ctrl2_a_t ctrl2_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
- if(ret == 0){
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
+ if (ret == 0)
+ {
ctrl2_a.if_add_inc = val;
- ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
+ ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
}
+
return ret;
}
@@ -1121,12 +1231,13 @@ int32_t ism303dac_xl_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism303dac_xl_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism303dac_xl_auto_increment_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism303dac_ctrl2_a_t ctrl2_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
*val = ctrl2_a.if_add_inc;
return ret;
@@ -1146,12 +1257,14 @@ int32_t ism303dac_xl_reset_set(stmdev_ctx_t *ctx, uint8_t val)
ism303dac_ctrl2_a_t ctrl2_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
- if(ret == 0){
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
+ if (ret == 0)
+ {
ctrl2_a.soft_reset = val;
- ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
+ ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
}
+
return ret;
}
@@ -1168,7 +1281,7 @@ int32_t ism303dac_xl_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
ism303dac_ctrl2_a_t ctrl2_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
*val = ctrl2_a.soft_reset;
return ret;
@@ -1188,13 +1301,15 @@ int32_t ism303dac_mg_reset_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_a_m, 1);
+ if (ret == 0)
+ {
cfg_reg_a_m.soft_rst = val;
ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
+ (uint8_t *)&cfg_reg_a_m, 1);
}
+
return ret;
}
@@ -1212,7 +1327,7 @@ int32_t ism303dac_mg_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
+ (uint8_t *)&cfg_reg_a_m, 1);
*val = cfg_reg_a_m.soft_rst;
return ret;
@@ -1231,12 +1346,14 @@ int32_t ism303dac_xl_boot_set(stmdev_ctx_t *ctx, uint8_t val)
ism303dac_ctrl2_a_t ctrl2_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
- if(ret == 0){
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
+ if (ret == 0)
+ {
ctrl2_a.boot = val;
- ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
+ ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
}
+
return ret;
}
@@ -1253,7 +1370,7 @@ int32_t ism303dac_xl_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
ism303dac_ctrl2_a_t ctrl2_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
*val = ctrl2_a.boot;
return ret;
@@ -1273,13 +1390,15 @@ int32_t ism303dac_mg_boot_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_a_m, 1);
+ if (ret == 0)
+ {
cfg_reg_a_m.reboot = val;
ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
+ (uint8_t *)&cfg_reg_a_m, 1);
}
+
return ret;
}
@@ -1297,7 +1416,7 @@ int32_t ism303dac_mg_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
+ (uint8_t *)&cfg_reg_a_m, 1);
*val = cfg_reg_a_m.reboot;
return ret;
@@ -1317,12 +1436,14 @@ int32_t ism303dac_xl_self_test_set(stmdev_ctx_t *ctx,
ism303dac_ctrl3_a_t ctrl3_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
- if(ret == 0){
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
+ if (ret == 0)
+ {
ctrl3_a.st = (uint8_t)val;
- ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
+ ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
}
+
return ret;
}
@@ -1340,18 +1461,22 @@ int32_t ism303dac_xl_self_test_get(stmdev_ctx_t *ctx,
ism303dac_ctrl3_a_t ctrl3_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
- switch (ctrl3_a.st){
+ switch (ctrl3_a.st)
+ {
case ISM303DAC_XL_ST_DISABLE:
*val = ISM303DAC_XL_ST_DISABLE;
break;
+
case ISM303DAC_XL_ST_POSITIVE:
*val = ISM303DAC_XL_ST_POSITIVE;
break;
+
case ISM303DAC_XL_ST_NEGATIVE:
*val = ISM303DAC_XL_ST_NEGATIVE;
break;
+
default:
*val = ISM303DAC_XL_ST_DISABLE;
break;
@@ -1374,13 +1499,15 @@ int32_t ism303dac_mg_self_test_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_c_m, 1);
+ if (ret == 0)
+ {
cfg_reg_c_m.self_test = val;
ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
+ (uint8_t *)&cfg_reg_c_m, 1);
}
+
return ret;
}
@@ -1398,7 +1525,7 @@ int32_t ism303dac_mg_self_test_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
+ (uint8_t *)&cfg_reg_c_m, 1);
*val = cfg_reg_c_m.self_test;
return ret;
@@ -1418,12 +1545,14 @@ int32_t ism303dac_xl_data_ready_mode_set(stmdev_ctx_t *ctx,
ism303dac_ctrl5_a_t ctrl5_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL5_A, (uint8_t*)&ctrl5_a, 1);
- if(ret == 0){
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL5_A, (uint8_t *)&ctrl5_a, 1);
+ if (ret == 0)
+ {
ctrl5_a.drdy_pulsed = (uint8_t)val;
- ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL5_A, (uint8_t*)&ctrl5_a, 1);
+ ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL5_A, (uint8_t *)&ctrl5_a, 1);
}
+
return ret;
}
@@ -1441,15 +1570,18 @@ int32_t ism303dac_xl_data_ready_mode_get(stmdev_ctx_t *ctx,
ism303dac_ctrl5_a_t ctrl5_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL5_A, (uint8_t*)&ctrl5_a, 1);
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL5_A, (uint8_t *)&ctrl5_a, 1);
- switch (ctrl5_a.drdy_pulsed){
+ switch (ctrl5_a.drdy_pulsed)
+ {
case ISM303DAC_XL_DRDY_LATCHED:
*val = ISM303DAC_XL_DRDY_LATCHED;
break;
+
case ISM303DAC_XL_DRDY_PULSED:
*val = ISM303DAC_XL_DRDY_PULSED;
break;
+
default:
*val = ISM303DAC_XL_DRDY_LATCHED;
break;
@@ -1485,12 +1617,14 @@ int32_t ism303dac_xl_hp_path_set(stmdev_ctx_t *ctx,
ism303dac_ctrl2_a_t ctrl2_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
- if(ret == 0){
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
+ if (ret == 0)
+ {
ctrl2_a.fds_slope = (uint8_t)val;
- ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
+ ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
}
+
return ret;
}
@@ -1508,15 +1642,18 @@ int32_t ism303dac_xl_hp_path_get(stmdev_ctx_t *ctx,
ism303dac_ctrl2_a_t ctrl2_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
- switch (ctrl2_a.fds_slope){
+ switch (ctrl2_a.fds_slope)
+ {
case ISM303DAC_XL_HP_INTERNAL_ONLY:
*val = ISM303DAC_XL_HP_INTERNAL_ONLY;
break;
+
case ISM303DAC_XL_HP_ON_OUTPUTS:
*val = ISM303DAC_XL_HP_ON_OUTPUTS;
break;
+
default:
*val = ISM303DAC_XL_HP_INTERNAL_ONLY;
break;
@@ -1540,13 +1677,15 @@ int32_t ism303dac_mg_low_pass_bandwidth_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_B_M,
- (uint8_t*)&cfg_reg_b_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_b_m, 1);
+ if (ret == 0)
+ {
cfg_reg_b_m.lpf = (uint8_t)val;
ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_B_M,
- (uint8_t*)&cfg_reg_b_m, 1);
+ (uint8_t *)&cfg_reg_b_m, 1);
}
+
return ret;
}
@@ -1565,15 +1704,18 @@ int32_t ism303dac_mg_low_pass_bandwidth_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_B_M,
- (uint8_t*)&cfg_reg_b_m, 1);
+ (uint8_t *)&cfg_reg_b_m, 1);
- switch (cfg_reg_b_m.lpf){
+ switch (cfg_reg_b_m.lpf)
+ {
case ISM303DAC_MG_ODR_DIV_2:
*val = ISM303DAC_MG_ODR_DIV_2;
break;
+
case ISM303DAC_MG_ODR_DIV_4:
*val = ISM303DAC_MG_ODR_DIV_4;
break;
+
default:
*val = ISM303DAC_MG_ODR_DIV_2;
break;
@@ -1609,12 +1751,14 @@ int32_t ism303dac_xl_spi_mode_set(stmdev_ctx_t *ctx,
ism303dac_ctrl2_a_t ctrl2_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
- if(ret == 0){
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
+ if (ret == 0)
+ {
ctrl2_a.sim = (uint8_t)val;
- ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
+ ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
}
+
return ret;
}
@@ -1632,15 +1776,18 @@ int32_t ism303dac_xl_spi_mode_get(stmdev_ctx_t *ctx,
ism303dac_ctrl2_a_t ctrl2_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
- switch (ctrl2_a.sim){
+ switch (ctrl2_a.sim)
+ {
case ISM303DAC_XL_SPI_4_WIRE:
*val = ISM303DAC_XL_SPI_4_WIRE;
break;
+
case ISM303DAC_XL_SPI_3_WIRE:
*val = ISM303DAC_XL_SPI_3_WIRE;
break;
+
default:
*val = ISM303DAC_XL_SPI_4_WIRE;
break;
@@ -1663,12 +1810,14 @@ int32_t ism303dac_xl_i2c_interface_set(stmdev_ctx_t *ctx,
ism303dac_ctrl2_a_t ctrl2_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
- if(ret == 0){
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
+ if (ret == 0)
+ {
ctrl2_a.i2c_disable = (uint8_t)val;
- ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
+ ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
}
+
return ret;
}
@@ -1686,15 +1835,18 @@ int32_t ism303dac_xl_i2c_interface_get(stmdev_ctx_t *ctx,
ism303dac_ctrl2_a_t ctrl2_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
- switch (ctrl2_a.i2c_disable){
+ switch (ctrl2_a.i2c_disable)
+ {
case ISM303DAC_XL_I2C_ENABLE:
*val = ISM303DAC_XL_I2C_ENABLE;
break;
+
case ISM303DAC_XL_I2C_DISABLE:
*val = ISM303DAC_XL_I2C_DISABLE;
break;
+
default:
*val = ISM303DAC_XL_I2C_ENABLE;
break;
@@ -1718,13 +1870,15 @@ int32_t ism303dac_mg_i2c_interface_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_c_m, 1);
+ if (ret == 0)
+ {
cfg_reg_c_m.i2c_dis = (uint8_t)val;
ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
+ (uint8_t *)&cfg_reg_c_m, 1);
}
+
return ret;
}
@@ -1743,15 +1897,18 @@ int32_t ism303dac_mg_i2c_interface_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
+ (uint8_t *)&cfg_reg_c_m, 1);
- switch (cfg_reg_c_m.i2c_dis){
+ switch (cfg_reg_c_m.i2c_dis)
+ {
case ISM303DAC_MG_I2C_ENABLE:
*val = ISM303DAC_MG_I2C_ENABLE;
break;
+
case ISM303DAC_MG_I2C_DISABLE:
*val = ISM303DAC_MG_I2C_DISABLE;
break;
+
default:
*val = ISM303DAC_MG_I2C_ENABLE;
break;
@@ -1776,13 +1933,15 @@ int32_t ism303dac_xl_cs_mode_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_CTRL_A,
- (uint8_t*)&fifo_ctrl_a, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl_a, 1);
+ if (ret == 0)
+ {
fifo_ctrl_a.if_cs_pu_dis = (uint8_t)val;
ret = ism303dac_write_reg(ctx, ISM303DAC_FIFO_CTRL_A,
- (uint8_t*)&fifo_ctrl_a, 1);
+ (uint8_t *)&fifo_ctrl_a, 1);
}
+
return ret;
}
@@ -1801,15 +1960,18 @@ int32_t ism303dac_xl_cs_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_CTRL_A,
- (uint8_t*)&fifo_ctrl_a, 1);
+ (uint8_t *)&fifo_ctrl_a, 1);
- switch (fifo_ctrl_a.if_cs_pu_dis){
+ switch (fifo_ctrl_a.if_cs_pu_dis)
+ {
case ISM303DAC_XL_PULL_UP_CONNECTED:
*val = ISM303DAC_XL_PULL_UP_CONNECTED;
break;
+
case ISM303DAC_XL_PULL_UP_DISCONNECTED:
*val = ISM303DAC_XL_PULL_UP_DISCONNECTED;
break;
+
default:
*val = ISM303DAC_XL_PULL_UP_CONNECTED;
break;
@@ -1845,12 +2007,14 @@ int32_t ism303dac_xl_pin_mode_set(stmdev_ctx_t *ctx,
ism303dac_ctrl3_a_t ctrl3_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
- if(ret == 0){
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
+ if (ret == 0)
+ {
ctrl3_a.pp_od = (uint8_t)val;
- ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
+ ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
}
+
return ret;
}
@@ -1868,15 +2032,18 @@ int32_t ism303dac_xl_pin_mode_get(stmdev_ctx_t *ctx,
ism303dac_ctrl3_a_t ctrl3_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
- switch (ctrl3_a.pp_od){
+ switch (ctrl3_a.pp_od)
+ {
case ISM303DAC_XL_PUSH_PULL:
*val = ISM303DAC_XL_PUSH_PULL;
break;
+
case ISM303DAC_XL_OPEN_DRAIN:
*val = ISM303DAC_XL_OPEN_DRAIN;
break;
+
default:
*val = ISM303DAC_XL_PUSH_PULL;
break;
@@ -1899,12 +2066,14 @@ int32_t ism303dac_xl_pin_polarity_set(stmdev_ctx_t *ctx,
ism303dac_ctrl3_a_t ctrl3_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
- if(ret == 0){
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
+ if (ret == 0)
+ {
ctrl3_a.h_lactive = (uint8_t)val;
- ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
+ ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
}
+
return ret;
}
@@ -1922,15 +2091,18 @@ int32_t ism303dac_xl_pin_polarity_get(stmdev_ctx_t *ctx,
ism303dac_ctrl3_a_t ctrl3_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
- switch (ctrl3_a.h_lactive){
+ switch (ctrl3_a.h_lactive)
+ {
case ISM303DAC_XL_ACTIVE_HIGH:
*val = ISM303DAC_XL_ACTIVE_HIGH;
break;
+
case ISM303DAC_XL_ACTIVE_LOW:
*val = ISM303DAC_XL_ACTIVE_LOW;
break;
+
default:
*val = ISM303DAC_XL_ACTIVE_HIGH;
break;
@@ -1953,12 +2125,14 @@ int32_t ism303dac_xl_int_notification_set(stmdev_ctx_t *ctx,
ism303dac_ctrl3_a_t ctrl3_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
- if(ret == 0){
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
+ if (ret == 0)
+ {
ctrl3_a.lir = (uint8_t)val;
- ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
+ ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
}
+
return ret;
}
@@ -1976,15 +2150,18 @@ int32_t ism303dac_xl_int_notification_get(stmdev_ctx_t *ctx,
ism303dac_ctrl3_a_t ctrl3_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
- switch (ctrl3_a.lir){
+ switch (ctrl3_a.lir)
+ {
case ISM303DAC_XL_INT_PULSED:
*val = ISM303DAC_XL_INT_PULSED;
break;
+
case ISM303DAC_XL_INT_LATCHED:
*val = ISM303DAC_XL_INT_LATCHED;
break;
+
default:
*val = ISM303DAC_XL_INT_PULSED;
break;
@@ -2008,9 +2185,10 @@ int32_t ism303dac_xl_pin_int1_route_set(stmdev_ctx_t *ctx,
ism303dac_wake_up_dur_a_t wake_up_dur_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL4_A, (uint8_t*)&ctrl4_a, 1);
- if(ret == 0){
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL4_A, (uint8_t *)&ctrl4_a, 1);
+ if (ret == 0)
+ {
ctrl4_a.int1_drdy = val.int1_drdy;
ctrl4_a.int1_fth = val.int1_fth;
ctrl4_a.int1_6d = val.int1_6d;
@@ -2018,17 +2196,22 @@ int32_t ism303dac_xl_pin_int1_route_set(stmdev_ctx_t *ctx,
ctrl4_a.int1_ff = val.int1_ff;
ctrl4_a.int1_wu = val.int1_wu;
ctrl4_a.int1_s_tap = val.int1_s_tap;
- ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL4_A, (uint8_t*)&ctrl4_a, 1);
+ ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL4_A, (uint8_t *)&ctrl4_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_DUR_A,
- (uint8_t*)&wake_up_dur_a, 1);
+ (uint8_t *)&wake_up_dur_a, 1);
}
- if(ret == 0){
+ if (ret == 0)
+ {
wake_up_dur_a.int1_fss7 = val.int1_fss7;
- ret = ism303dac_write_reg(ctx, ISM303DAC_WAKE_UP_DUR_A, (uint8_t*)&wake_up_dur_a, 1);
+ ret = ism303dac_write_reg(ctx, ISM303DAC_WAKE_UP_DUR_A,
+ (uint8_t *)&wake_up_dur_a, 1);
}
+
return ret;
}
@@ -2047,9 +2230,10 @@ int32_t ism303dac_xl_pin_int1_route_get(stmdev_ctx_t *ctx,
ism303dac_wake_up_dur_a_t wake_up_dur_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL4_A, (uint8_t*)&ctrl4_a, 1);
- if(ret == 0){
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL4_A, (uint8_t *)&ctrl4_a, 1);
+ if (ret == 0)
+ {
val->int1_drdy = ctrl4_a.int1_drdy;
val->int1_fth = ctrl4_a.int1_fth;
val->int1_6d = ctrl4_a.int1_6d;
@@ -2057,13 +2241,15 @@ int32_t ism303dac_xl_pin_int1_route_get(stmdev_ctx_t *ctx,
val->int1_ff = ctrl4_a.int1_ff;
val->int1_wu = ctrl4_a.int1_wu;
val->int1_s_tap = ctrl4_a.int1_s_tap;
-
- ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_DUR_A, (uint8_t*)&wake_up_dur_a, 1);
+ ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_DUR_A,
+ (uint8_t *)&wake_up_dur_a, 1);
}
- if(ret == 0){
+ if (ret == 0)
+ {
val->int1_fss7 = wake_up_dur_a.int1_fss7;
}
+
return ret;
}
@@ -2081,14 +2267,16 @@ int32_t ism303dac_xl_pin_int2_route_set(stmdev_ctx_t *ctx,
ism303dac_ctrl5_a_t ctrl5_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL5_A, (uint8_t*)&ctrl5_a, 1);
- if(ret == 0){
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL5_A, (uint8_t *)&ctrl5_a, 1);
+ if (ret == 0)
+ {
ctrl5_a.int2_boot = val.int2_boot;
ctrl5_a.int2_fth = val.int2_fth;
ctrl5_a.int2_drdy = val.int2_drdy;
- ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL5_A, (uint8_t*)&ctrl5_a, 1);
+ ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL5_A, (uint8_t *)&ctrl5_a, 1);
}
+
return ret;
}
@@ -2106,13 +2294,15 @@ int32_t ism303dac_xl_pin_int2_route_get(stmdev_ctx_t *ctx,
ism303dac_ctrl5_a_t ctrl5_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL5_A, (uint8_t*)&ctrl5_a, 1);
- if(ret == 0){
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL5_A, (uint8_t *)&ctrl5_a, 1);
+ if (ret == 0)
+ {
val->int2_boot = ctrl5_a.int2_boot;
val->int2_fth = ctrl5_a.int2_fth;
val->int2_drdy = ctrl5_a.int2_drdy;
}
+
return ret;
}
@@ -2129,12 +2319,14 @@ int32_t ism303dac_xl_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
ism303dac_ctrl5_a_t ctrl5_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL5_A, (uint8_t*)&ctrl5_a, 1);
- if(ret == 0){
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL5_A, (uint8_t *)&ctrl5_a, 1);
+ if (ret == 0)
+ {
ctrl5_a.int2_on_int1 = val;
- ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL5_A, (uint8_t*)&ctrl5_a, 1);
+ ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL5_A, (uint8_t *)&ctrl5_a, 1);
}
+
return ret;
}
@@ -2151,7 +2343,7 @@ int32_t ism303dac_xl_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
ism303dac_ctrl5_a_t ctrl5_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL5_A, (uint8_t*)&ctrl5_a, 1);
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL5_A, (uint8_t *)&ctrl5_a, 1);
*val = ctrl5_a.int2_on_int1;
return ret;
@@ -2171,13 +2363,15 @@ int32_t ism303dac_mg_drdy_on_pin_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_c_m, 1);
+ if (ret == 0)
+ {
cfg_reg_c_m.int_mag = val;
ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
+ (uint8_t *)&cfg_reg_c_m, 1);
}
+
return ret;
}
@@ -2195,7 +2389,7 @@ int32_t ism303dac_mg_drdy_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
+ (uint8_t *)&cfg_reg_c_m, 1);
*val = cfg_reg_c_m.int_mag;
return ret;
@@ -2215,13 +2409,15 @@ int32_t ism303dac_mg_int_on_pin_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_c_m, 1);
+ if (ret == 0)
+ {
cfg_reg_c_m.int_mag_pin = val;
ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
+ (uint8_t *)&cfg_reg_c_m, 1);
}
+
return ret;
}
@@ -2239,7 +2435,7 @@ int32_t ism303dac_mg_int_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
+ (uint8_t *)&cfg_reg_c_m, 1);
*val = cfg_reg_c_m.int_mag_pin;
return ret;
@@ -2257,8 +2453,10 @@ int32_t ism303dac_mg_int_gen_conf_set(stmdev_ctx_t *ctx,
ism303dac_int_crtl_reg_m_t *val)
{
int32_t ret;
+
ret = ism303dac_write_reg(ctx, ISM303DAC_INT_CRTL_REG_M,
- (uint8_t*) val, 1);
+ (uint8_t *) val, 1);
+
return ret;
}
@@ -2274,7 +2472,10 @@ int32_t ism303dac_mg_int_gen_conf_get(stmdev_ctx_t *ctx,
ism303dac_int_crtl_reg_m_t *val)
{
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_INT_CRTL_REG_M, (uint8_t*) val, 1);
+
+ ret = ism303dac_read_reg(ctx, ISM303DAC_INT_CRTL_REG_M,
+ (uint8_t *) val, 1);
+
return ret;
}
@@ -2290,7 +2491,10 @@ int32_t ism303dac_mg_int_gen_source_get(stmdev_ctx_t *ctx,
ism303dac_int_source_reg_m_t *val)
{
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_INT_SOURCE_REG_M, (uint8_t*) val, 1);
+
+ ret = ism303dac_read_reg(ctx, ISM303DAC_INT_SOURCE_REG_M,
+ (uint8_t *) val, 1);
+
return ret;
}
@@ -2304,13 +2508,14 @@ int32_t ism303dac_mg_int_gen_source_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism303dac_mg_int_gen_treshold_set(stmdev_ctx_t *ctx, uint16_t val)
+int32_t ism303dac_mg_int_gen_treshold_set(stmdev_ctx_t *ctx,
+ uint16_t val)
{
uint8_t buff[2];
int32_t ret;
- buff[1] = (uint8_t) (val / 256U);
- buff[0] = (uint8_t) (val - (buff[1] * 256U));
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
ret = ism303dac_write_reg(ctx, ISM303DAC_INT_THS_L_REG_M, buff, 2);
return ret;
@@ -2326,7 +2531,8 @@ int32_t ism303dac_mg_int_gen_treshold_set(stmdev_ctx_t *ctx, uint16_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism303dac_mg_int_gen_treshold_get(stmdev_ctx_t *ctx, uint16_t *val)
+int32_t ism303dac_mg_int_gen_treshold_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
uint8_t buff[2];
int32_t ret;
@@ -2345,7 +2551,7 @@ int32_t ism303dac_mg_int_gen_treshold_get(stmdev_ctx_t *ctx, uint16_t *val)
/**
* @defgroup ISM303DAC_interrupt_pins
- * @brief This section groups all the functions that manage interrup pins
+ * @brief This section groups all the functions that manage interrupt pins
* @{
*
*/
@@ -2379,13 +2585,15 @@ int32_t ism303dac_mg_offset_int_conf_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_B_M,
- (uint8_t*)&cfg_reg_b_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_b_m, 1);
+ if (ret == 0)
+ {
cfg_reg_b_m.int_on_dataoff = (uint8_t)val;
ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_B_M,
- (uint8_t*)&cfg_reg_b_m, 1);
+ (uint8_t *)&cfg_reg_b_m, 1);
}
+
return ret;
}
@@ -2405,15 +2613,18 @@ int32_t ism303dac_mg_offset_int_conf_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_B_M,
- (uint8_t*)&cfg_reg_b_m, 1);
+ (uint8_t *)&cfg_reg_b_m, 1);
- switch (cfg_reg_b_m.int_on_dataoff){
+ switch (cfg_reg_b_m.int_on_dataoff)
+ {
case ISM303DAC_MG_CHECK_BEFORE:
*val = ISM303DAC_MG_CHECK_BEFORE;
break;
+
case ISM303DAC_MG_CHECK_AFTER:
*val = ISM303DAC_MG_CHECK_AFTER;
break;
+
default:
*val = ISM303DAC_MG_CHECK_BEFORE;
break;
@@ -2422,7 +2633,7 @@ int32_t ism303dac_mg_offset_int_conf_get(stmdev_ctx_t *ctx,
return ret;
}
- /**
+/**
* @brief Threshold for wakeup [1 LSb = FS_XL / 64].[set]
*
* @param ctx read / write interface definitions.(ptr)
@@ -2430,19 +2641,22 @@ int32_t ism303dac_mg_offset_int_conf_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism303dac_xl_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ism303dac_xl_wkup_threshold_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
ism303dac_wake_up_ths_a_t wake_up_ths_a;
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_THS_A,
- (uint8_t*)&wake_up_ths_a, 1);
- if(ret == 0){
+ (uint8_t *)&wake_up_ths_a, 1);
+ if (ret == 0)
+ {
wake_up_ths_a.wu_ths = val;
ret = ism303dac_write_reg(ctx, ISM303DAC_WAKE_UP_THS_A,
- (uint8_t*)&wake_up_ths_a, 1);
+ (uint8_t *)&wake_up_ths_a, 1);
}
+
return ret;
}
@@ -2454,13 +2668,14 @@ int32_t ism303dac_xl_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism303dac_xl_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism303dac_xl_wkup_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism303dac_wake_up_ths_a_t wake_up_ths_a;
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_THS_A,
- (uint8_t*)&wake_up_ths_a, 1);
+ (uint8_t *)&wake_up_ths_a, 1);
*val = wake_up_ths_a.wu_ths;
return ret;
@@ -2480,13 +2695,15 @@ int32_t ism303dac_xl_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_THS_A,
- (uint8_t*)&wake_up_dur_a, 1);
- if(ret == 0){
+ (uint8_t *)&wake_up_dur_a, 1);
+ if (ret == 0)
+ {
wake_up_dur_a.wu_dur = val;
ret = ism303dac_write_reg(ctx, ISM303DAC_WAKE_UP_THS_A,
- (uint8_t*)&wake_up_dur_a, 1);
+ (uint8_t *)&wake_up_dur_a, 1);
}
+
return ret;
}
@@ -2504,7 +2721,7 @@ int32_t ism303dac_xl_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_DUR_A,
- (uint8_t*)&wake_up_dur_a, 1);
+ (uint8_t *)&wake_up_dur_a, 1);
*val = wake_up_dur_a.wu_dur;
return ret;
@@ -2537,13 +2754,15 @@ int32_t ism303dac_xl_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_THS_A,
- (uint8_t*)&wake_up_ths_a, 1);
- if(ret == 0){
+ (uint8_t *)&wake_up_ths_a, 1);
+ if (ret == 0)
+ {
wake_up_ths_a.sleep_on = val;
ret = ism303dac_write_reg(ctx, ISM303DAC_WAKE_UP_THS_A,
- (uint8_t*)&wake_up_ths_a, 1);
+ (uint8_t *)&wake_up_ths_a, 1);
}
+
return ret;
}
@@ -2561,7 +2780,7 @@ int32_t ism303dac_xl_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_THS_A,
- (uint8_t*)&wake_up_ths_a, 1);
+ (uint8_t *)&wake_up_ths_a, 1);
*val = wake_up_ths_a.sleep_on;
return ret;
@@ -2581,13 +2800,15 @@ int32_t ism303dac_xl_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_DUR_A,
- (uint8_t*)&wake_up_dur_a, 1);
- if(ret == 0){
+ (uint8_t *)&wake_up_dur_a, 1);
+ if (ret == 0)
+ {
wake_up_dur_a.sleep_dur = val;
ret = ism303dac_write_reg(ctx, ISM303DAC_WAKE_UP_DUR_A,
- (uint8_t*)&wake_up_dur_a, 1);
+ (uint8_t *)&wake_up_dur_a, 1);
}
+
return ret;
}
@@ -2599,13 +2820,14 @@ int32_t ism303dac_xl_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism303dac_xl_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism303dac_xl_act_sleep_dur_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism303dac_wake_up_dur_a_t wake_up_dur_a;
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_DUR_A,
- (uint8_t*)&wake_up_dur_a, 1);
+ (uint8_t *)&wake_up_dur_a, 1);
*val = wake_up_dur_a.sleep_dur;
return ret;
@@ -2638,12 +2860,14 @@ int32_t ism303dac_xl_tap_detection_on_z_set(stmdev_ctx_t *ctx,
ism303dac_ctrl3_a_t ctrl3_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
- if(ret == 0){
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
+ if (ret == 0)
+ {
ctrl3_a.tap_z_en = val;
- ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
+ ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
}
+
return ret;
}
@@ -2661,7 +2885,7 @@ int32_t ism303dac_xl_tap_detection_on_z_get(stmdev_ctx_t *ctx,
ism303dac_ctrl3_a_t ctrl3_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
*val = ctrl3_a.tap_z_en;
return ret;
@@ -2681,12 +2905,14 @@ int32_t ism303dac_xl_tap_detection_on_y_set(stmdev_ctx_t *ctx,
ism303dac_ctrl3_a_t ctrl3_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
- if(ret == 0){
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
+ if (ret == 0)
+ {
ctrl3_a.tap_y_en = val;
- ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
+ ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
}
+
return ret;
}
@@ -2704,7 +2930,7 @@ int32_t ism303dac_xl_tap_detection_on_y_get(stmdev_ctx_t *ctx,
ism303dac_ctrl3_a_t ctrl3_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
*val = ctrl3_a.tap_y_en;
return ret;
@@ -2718,17 +2944,20 @@ int32_t ism303dac_xl_tap_detection_on_y_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism303dac_xl_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ism303dac_xl_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
ism303dac_ctrl3_a_t ctrl3_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
- if(ret == 0){
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
+ if (ret == 0)
+ {
ctrl3_a.tap_x_en = val;
- ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
+ ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
}
+
return ret;
}
@@ -2746,7 +2975,7 @@ int32_t ism303dac_xl_tap_detection_on_x_get(stmdev_ctx_t *ctx,
ism303dac_ctrl3_a_t ctrl3_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
+ ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
*val = ctrl3_a.tap_x_en;
return ret;
@@ -2766,13 +2995,15 @@ int32_t ism303dac_xl_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_TAP_6D_THS_A,
- (uint8_t*)&tap_6d_ths_a, 1);
- if(ret == 0){
+ (uint8_t *)&tap_6d_ths_a, 1);
+ if (ret == 0)
+ {
tap_6d_ths_a.tap_ths = val;
ret = ism303dac_write_reg(ctx, ISM303DAC_TAP_6D_THS_A,
- (uint8_t*)&tap_6d_ths_a, 1);
+ (uint8_t *)&tap_6d_ths_a, 1);
}
+
return ret;
}
@@ -2784,13 +3015,14 @@ int32_t ism303dac_xl_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism303dac_xl_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism303dac_xl_tap_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism303dac_tap_6d_ths_a_t tap_6d_ths_a;
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_TAP_6D_THS_A,
- (uint8_t*)&tap_6d_ths_a, 1);
+ (uint8_t *)&tap_6d_ths_a, 1);
*val = tap_6d_ths_a.tap_ths;
return ret;
@@ -2813,13 +3045,16 @@ int32_t ism303dac_xl_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
ism303dac_int_dur_a_t int_dur_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_INT_DUR_A, (uint8_t*)&int_dur_a, 1);
- if(ret == 0){
+ ret = ism303dac_read_reg(ctx, ISM303DAC_INT_DUR_A,
+ (uint8_t *)&int_dur_a, 1);
+ if (ret == 0)
+ {
int_dur_a.shock = val;
ret = ism303dac_write_reg(ctx, ISM303DAC_INT_DUR_A,
- (uint8_t*)&int_dur_a, 1);
+ (uint8_t *)&int_dur_a, 1);
}
+
return ret;
}
@@ -2840,7 +3075,8 @@ int32_t ism303dac_xl_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
ism303dac_int_dur_a_t int_dur_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_INT_DUR_A, (uint8_t*)&int_dur_a, 1);
+ ret = ism303dac_read_reg(ctx, ISM303DAC_INT_DUR_A,
+ (uint8_t *)&int_dur_a, 1);
*val = int_dur_a.shock;
return ret;
@@ -2863,13 +3099,16 @@ int32_t ism303dac_xl_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
ism303dac_int_dur_a_t int_dur_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_INT_DUR_A, (uint8_t*)&int_dur_a, 1);
- if(ret == 0){
+ ret = ism303dac_read_reg(ctx, ISM303DAC_INT_DUR_A,
+ (uint8_t *)&int_dur_a, 1);
+ if (ret == 0)
+ {
int_dur_a.quiet = val;
ret = ism303dac_write_reg(ctx, ISM303DAC_INT_DUR_A,
- (uint8_t*)&int_dur_a, 1);
+ (uint8_t *)&int_dur_a, 1);
}
+
return ret;
}
@@ -2890,7 +3129,8 @@ int32_t ism303dac_xl_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
ism303dac_int_dur_a_t int_dur_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_INT_DUR_A, (uint8_t*)&int_dur_a, 1);
+ ret = ism303dac_read_reg(ctx, ISM303DAC_INT_DUR_A,
+ (uint8_t *)&int_dur_a, 1);
*val = int_dur_a.quiet;
return ret;
@@ -2914,13 +3154,16 @@ int32_t ism303dac_xl_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
ism303dac_int_dur_a_t int_dur_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_INT_DUR_A, (uint8_t*)&int_dur_a, 1);
- if(ret == 0){
+ ret = ism303dac_read_reg(ctx, ISM303DAC_INT_DUR_A,
+ (uint8_t *)&int_dur_a, 1);
+ if (ret == 0)
+ {
int_dur_a.lat = val;
ret = ism303dac_write_reg(ctx, ISM303DAC_INT_DUR_A,
- (uint8_t*)&int_dur_a, 1);
+ (uint8_t *)&int_dur_a, 1);
}
+
return ret;
}
@@ -2942,7 +3185,8 @@ int32_t ism303dac_xl_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
ism303dac_int_dur_a_t int_dur_a;
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_INT_DUR_A, (uint8_t*)&int_dur_a, 1);
+ ret = ism303dac_read_reg(ctx, ISM303DAC_INT_DUR_A,
+ (uint8_t *)&int_dur_a, 1);
*val = int_dur_a.lat;
return ret;
@@ -2957,19 +3201,21 @@ int32_t ism303dac_xl_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t ism303dac_xl_tap_mode_set(stmdev_ctx_t *ctx,
- ism303dac_xl_single_double_tap_t val)
+ ism303dac_xl_single_double_tap_t val)
{
ism303dac_wake_up_ths_a_t wake_up_ths_a;
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_THS_A,
- (uint8_t*)&wake_up_ths_a, 1);
- if(ret == 0){
+ (uint8_t *)&wake_up_ths_a, 1);
+ if (ret == 0)
+ {
wake_up_ths_a.single_double_tap = (uint8_t)val;
ret = ism303dac_write_reg(ctx, ISM303DAC_WAKE_UP_THS_A,
- (uint8_t*)&wake_up_ths_a, 1);
+ (uint8_t *)&wake_up_ths_a, 1);
}
+
return ret;
}
@@ -2982,21 +3228,24 @@ int32_t ism303dac_xl_tap_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism303dac_xl_tap_mode_get(stmdev_ctx_t *ctx,
- ism303dac_xl_single_double_tap_t *val)
+ ism303dac_xl_single_double_tap_t *val)
{
ism303dac_wake_up_ths_a_t wake_up_ths_a;
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_THS_A,
- (uint8_t*)&wake_up_ths_a, 1);
+ (uint8_t *)&wake_up_ths_a, 1);
- switch (wake_up_ths_a.single_double_tap){
+ switch (wake_up_ths_a.single_double_tap)
+ {
case ISM303DAC_XL_ONLY_SINGLE:
*val = ISM303DAC_XL_ONLY_SINGLE;
break;
+
case ISM303DAC_XL_ONLY_DOUBLE:
*val = ISM303DAC_XL_ONLY_DOUBLE;
break;
+
default:
*val = ISM303DAC_XL_ONLY_SINGLE;
break;
@@ -3017,7 +3266,9 @@ int32_t ism303dac_xl_tap_src_get(stmdev_ctx_t *ctx,
ism303dac_tap_src_a_t *val)
{
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_TAP_SRC_A, (uint8_t*) val, 1);
+
+ ret = ism303dac_read_reg(ctx, ISM303DAC_TAP_SRC_A, (uint8_t *) val, 1);
+
return ret;
}
@@ -3043,19 +3294,21 @@ int32_t ism303dac_xl_tap_src_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism303dac_xl_6d_threshold_set(stmdev_ctx_t *ctx,
- ism303dac_xl_6d_ths_t val)
+ ism303dac_xl_6d_ths_t val)
{
ism303dac_tap_6d_ths_a_t tap_6d_ths_a;
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_TAP_6D_THS_A,
- (uint8_t*)&tap_6d_ths_a, 1);
- if(ret == 0){
+ (uint8_t *)&tap_6d_ths_a, 1);
+ if (ret == 0)
+ {
tap_6d_ths_a._6d_ths = (uint8_t)val;
ret = ism303dac_write_reg(ctx, ISM303DAC_TAP_6D_THS_A,
- (uint8_t*)&tap_6d_ths_a, 1);
+ (uint8_t *)&tap_6d_ths_a, 1);
}
+
return ret;
}
@@ -3068,27 +3321,32 @@ int32_t ism303dac_xl_6d_threshold_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism303dac_xl_6d_threshold_get(stmdev_ctx_t *ctx,
- ism303dac_xl_6d_ths_t *val)
+ ism303dac_xl_6d_ths_t *val)
{
ism303dac_tap_6d_ths_a_t tap_6d_ths_a;
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_TAP_6D_THS_A,
- (uint8_t*)&tap_6d_ths_a, 1);
+ (uint8_t *)&tap_6d_ths_a, 1);
- switch (tap_6d_ths_a._6d_ths){
+ switch (tap_6d_ths_a._6d_ths)
+ {
case ISM303DAC_XL_DEG_80:
*val = ISM303DAC_XL_DEG_80;
break;
+
case ISM303DAC_XL_DEG_70:
*val = ISM303DAC_XL_DEG_70;
break;
+
case ISM303DAC_XL_DEG_60:
*val = ISM303DAC_XL_DEG_60;
break;
+
case ISM303DAC_XL_DEG_50:
*val = ISM303DAC_XL_DEG_50;
break;
+
default:
*val = ISM303DAC_XL_DEG_80;
break;
@@ -3111,13 +3369,15 @@ int32_t ism303dac_xl_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_TAP_6D_THS_A,
- (uint8_t*)&tap_6d_ths_a, 1);
- if(ret == 0){
+ (uint8_t *)&tap_6d_ths_a, 1);
+ if (ret == 0)
+ {
tap_6d_ths_a._4d_en = val;
ret = ism303dac_write_reg(ctx, ISM303DAC_TAP_6D_THS_A,
- (uint8_t*)&tap_6d_ths_a, 1);
+ (uint8_t *)&tap_6d_ths_a, 1);
}
+
return ret;
}
@@ -3135,7 +3395,7 @@ int32_t ism303dac_xl_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_TAP_6D_THS_A,
- (uint8_t*)&tap_6d_ths_a, 1);
+ (uint8_t *)&tap_6d_ths_a, 1);
*val = tap_6d_ths_a._4d_en;
return ret;
@@ -3153,7 +3413,9 @@ int32_t ism303dac_xl_6d_src_get(stmdev_ctx_t *ctx,
ism303dac_6d_src_a_t *val)
{
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_6D_SRC_A, (uint8_t*) val, 1);
+
+ ret = ism303dac_read_reg(ctx, ISM303DAC_6D_SRC_A, (uint8_t *) val, 1);
+
return ret;
}
@@ -3185,21 +3447,28 @@ int32_t ism303dac_xl_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_DUR_A,
- (uint8_t*)&wake_up_dur_a, 1);
- if(ret == 0){
+ (uint8_t *)&wake_up_dur_a, 1);
+
+ if (ret == 0)
+ {
wake_up_dur_a.ff_dur = (val & 0x20U) >> 5;
ret = ism303dac_write_reg(ctx, ISM303DAC_WAKE_UP_DUR_A,
- (uint8_t*)&wake_up_dur_a, 1);
+ (uint8_t *)&wake_up_dur_a, 1);
}
- if(ret == 0){
- ret = ism303dac_read_reg(ctx, ISM303DAC_FREE_FALL_A,
- (uint8_t*)&free_fall_a, 1);
+
+ if (ret == 0)
+ {
+ ret = ism303dac_read_reg(ctx, ISM303DAC_FREE_FALL_A,
+ (uint8_t *)&free_fall_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
free_fall_a.ff_dur = val & 0x1FU;
ret = ism303dac_write_reg(ctx, ISM303DAC_FREE_FALL_A,
- (uint8_t*)&free_fall_a, 1);
+ (uint8_t *)&free_fall_a, 1);
}
+
return ret;
}
@@ -3218,12 +3487,16 @@ int32_t ism303dac_xl_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_DUR_A,
- (uint8_t*)&wake_up_dur_a, 1);
- if(ret == 0){
+ (uint8_t *)&wake_up_dur_a, 1);
+
+ if (ret == 0)
+ {
ret = ism303dac_read_reg(ctx, ISM303DAC_FREE_FALL_A,
- (uint8_t*)&free_fall_a, 1);
+ (uint8_t *)&free_fall_a, 1);
}
+
*val = (wake_up_dur_a.ff_dur << 5) + free_fall_a.ff_dur;
+
return ret;
}
@@ -3241,13 +3514,15 @@ int32_t ism303dac_xl_ff_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_FREE_FALL_A,
- (uint8_t*)&free_fall_a, 1);
- if(ret == 0){
+ (uint8_t *)&free_fall_a, 1);
+ if (ret == 0)
+ {
free_fall_a.ff_ths = val;
ret = ism303dac_write_reg(ctx, ISM303DAC_FREE_FALL_A,
- (uint8_t*)&free_fall_a, 1);
+ (uint8_t *)&free_fall_a, 1);
}
+
return ret;
}
@@ -3265,7 +3540,7 @@ int32_t ism303dac_xl_ff_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_FREE_FALL_A,
- (uint8_t*)&free_fall_a, 1);
+ (uint8_t *)&free_fall_a, 1);
*val = free_fall_a.ff_ths;
return ret;
@@ -3299,13 +3574,15 @@ int32_t ism303dac_xl_fifo_xl_module_batch_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_CTRL_A,
- (uint8_t*)&fifo_ctrl_a, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl_a, 1);
+ if (ret == 0)
+ {
fifo_ctrl_a.module_to_fifo = val;
ret = ism303dac_write_reg(ctx, ISM303DAC_FIFO_CTRL_A,
- (uint8_t*)&fifo_ctrl_a, 1);
+ (uint8_t *)&fifo_ctrl_a, 1);
}
+
return ret;
}
@@ -3319,13 +3596,13 @@ int32_t ism303dac_xl_fifo_xl_module_batch_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism303dac_xl_fifo_xl_module_batch_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
ism303dac_fifo_ctrl_a_t fifo_ctrl_a;
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_CTRL_A,
- (uint8_t*)&fifo_ctrl_a, 1);
+ (uint8_t *)&fifo_ctrl_a, 1);
*val = fifo_ctrl_a.module_to_fifo;
return ret;
@@ -3346,13 +3623,15 @@ int32_t ism303dac_xl_fifo_mode_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_CTRL_A,
- (uint8_t*)&fifo_ctrl_a, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl_a, 1);
+ if (ret == 0)
+ {
fifo_ctrl_a.fmode = (uint8_t)val;
ret = ism303dac_write_reg(ctx, ISM303DAC_FIFO_CTRL_A,
- (uint8_t*)&fifo_ctrl_a, 1);
+ (uint8_t *)&fifo_ctrl_a, 1);
}
+
return ret;
}
@@ -3371,24 +3650,30 @@ int32_t ism303dac_xl_fifo_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_CTRL_A,
- (uint8_t*)&fifo_ctrl_a, 1);
+ (uint8_t *)&fifo_ctrl_a, 1);
- switch (fifo_ctrl_a.fmode){
+ switch (fifo_ctrl_a.fmode)
+ {
case ISM303DAC_XL_BYPASS_MODE:
*val = ISM303DAC_XL_BYPASS_MODE;
break;
+
case ISM303DAC_XL_FIFO_MODE:
*val = ISM303DAC_XL_FIFO_MODE;
break;
+
case ISM303DAC_XL_STREAM_TO_FIFO_MODE:
*val = ISM303DAC_XL_STREAM_TO_FIFO_MODE;
break;
+
case ISM303DAC_XL_BYPASS_TO_STREAM_MODE:
*val = ISM303DAC_XL_BYPASS_TO_STREAM_MODE;
break;
+
case ISM303DAC_XL_STREAM_MODE:
*val = ISM303DAC_XL_STREAM_MODE;
break;
+
default:
*val = ISM303DAC_XL_BYPASS_MODE;
break;
@@ -3405,7 +3690,8 @@ int32_t ism303dac_xl_fifo_mode_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism303dac_xl_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ism303dac_xl_fifo_watermark_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
int32_t ret;
@@ -3422,7 +3708,8 @@ int32_t ism303dac_xl_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism303dac_xl_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism303dac_xl_fifo_watermark_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
int32_t ret;
@@ -3439,13 +3726,14 @@ int32_t ism303dac_xl_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism303dac_xl_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism303dac_xl_fifo_full_flag_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism303dac_fifo_src_a_t fifo_src_a;
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_SRC_A,
- (uint8_t*)&fifo_src_a, 1);
+ (uint8_t *)&fifo_src_a, 1);
*val = fifo_src_a.diff;
return ret;
@@ -3459,13 +3747,14 @@ int32_t ism303dac_xl_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism303dac_xl_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism303dac_xl_fifo_ovr_flag_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism303dac_fifo_src_a_t fifo_src_a;
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_SRC_A,
- (uint8_t*)&fifo_src_a, 1);
+ (uint8_t *)&fifo_src_a, 1);
*val = fifo_src_a.fifo_ovr;
return ret;
@@ -3479,13 +3768,14 @@ int32_t ism303dac_xl_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism303dac_xl_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism303dac_xl_fifo_wtm_flag_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism303dac_fifo_src_a_t fifo_src_a;
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_SRC_A,
- (uint8_t*)&fifo_src_a, 1);
+ (uint8_t *)&fifo_src_a, 1);
*val = fifo_src_a.fth;
return ret;
@@ -3499,21 +3789,25 @@ int32_t ism303dac_xl_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism303dac_xl_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
+int32_t ism303dac_xl_fifo_data_level_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
ism303dac_fifo_src_a_t fifo_src_a;
ism303dac_fifo_samples_a_t fifo_samples_a;
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_SRC_A,
- (uint8_t*)&fifo_src_a, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_src_a, 1);
+
+ if (ret == 0)
+ {
ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_SAMPLES_A,
- (uint8_t*)&fifo_samples_a, 1);
+ (uint8_t *)&fifo_samples_a, 1);
*val = fifo_src_a.diff;
*val = *val << 7;
*val += fifo_samples_a.diff;
}
+
return ret;
}
@@ -3526,10 +3820,12 @@ int32_t ism303dac_xl_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
*
*/
int32_t ism303dac_xl_fifo_src_get(stmdev_ctx_t *ctx,
- ism303dac_fifo_src_a_t *val)
+ ism303dac_fifo_src_a_t *val)
{
int32_t ret;
- ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_SRC_A, (uint8_t*) val, 1);
+
+ ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_SRC_A, (uint8_t *) val, 1);
+
return ret;
}
@@ -3560,13 +3856,15 @@ int32_t ism303dac_xl_module_sens_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_FUNC_CTRL_A,
- (uint8_t*)&func_ctrl_a, 1);
- if(ret == 0){
+ (uint8_t *)&func_ctrl_a, 1);
+ if (ret == 0)
+ {
func_ctrl_a.module_on = val;
ret = ism303dac_write_reg(ctx, ISM303DAC_FUNC_CTRL_A,
- (uint8_t*)&func_ctrl_a, 1);
+ (uint8_t *)&func_ctrl_a, 1);
}
+
return ret;
}
@@ -3584,7 +3882,7 @@ int32_t ism303dac_xl_module_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = ism303dac_read_reg(ctx, ISM303DAC_FUNC_CTRL_A,
- (uint8_t*)&func_ctrl_a, 1);
+ (uint8_t *)&func_ctrl_a, 1);
*val = func_ctrl_a.module_on;
return ret;
diff --git a/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.h b/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.h
index b1b5372169e3b0c745a9070753a3b147d150a733..78da311c07dafc1c82e4f1bd95a8a34ae3b61645 100644
--- a/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.h
+++ b/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.h
@@ -1,29 +1,29 @@
-/*
- ******************************************************************************
- * @file ism303dac_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * ism303dac_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file ism303dac_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * ism303dac_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef ISM303DAC_REGS_H
#define ISM303DAC_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -75,7 +75,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -108,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -132,7 +134,7 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
+ * You can create a sensor configuration by your own or using
* Unico / Unicleo tools available on STMicroelectronics
* web site.
*
@@ -140,7 +142,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -178,7 +181,8 @@ typedef struct {
#define ISM303DAC_MODULE_8BIT_A 0x0CU
#define ISM303DAC_WHO_AM_I_A 0x0FU
#define ISM303DAC_CTRL1_A 0x20U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bdu : 1;
uint8_t hf_odr : 1;
@@ -193,7 +197,8 @@ typedef struct {
} ism303dac_ctrl1_a_t;
#define ISM303DAC_CTRL2_A 0x21U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t i2c_disable : 1;
@@ -214,7 +219,8 @@ typedef struct {
} ism303dac_ctrl2_a_t;
#define ISM303DAC_CTRL3_A 0x22U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t pp_od : 1;
uint8_t h_lactive : 1;
@@ -235,7 +241,8 @@ typedef struct {
} ism303dac_ctrl3_a_t;
#define ISM303DAC_CTRL4_A 0x23U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_drdy : 1;
uint8_t int1_fth : 1;
@@ -258,7 +265,8 @@ typedef struct {
} ism303dac_ctrl4_a_t;
#define ISM303DAC_CTRL5_A 0x24U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_drdy : 1;
uint8_t int2_fth : 1;
@@ -277,7 +285,8 @@ typedef struct {
} ism303dac_ctrl5_a_t;
#define ISM303DAC_FIFO_CTRL_A 0x25U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t if_cs_pu_dis : 1;
uint8_t not_used_01 : 2;
@@ -295,7 +304,8 @@ typedef struct {
#define ISM303DAC_OUT_T_A 0x26U
#define ISM303DAC_STATUS_A 0x27U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t drdy : 1;
uint8_t ff_ia : 1;
@@ -325,7 +335,8 @@ typedef struct {
#define ISM303DAC_OUT_Z_H_A 0x2DU
#define ISM303DAC_FIFO_THS_A 0x2EU
#define ISM303DAC_FIFO_SRC_A 0x2FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 5;
uint8_t diff : 1;
@@ -340,12 +351,14 @@ typedef struct {
} ism303dac_fifo_src_a_t;
#define ISM303DAC_FIFO_SAMPLES_A 0x30U
-typedef struct {
+typedef struct
+{
uint8_t diff : 8;
} ism303dac_fifo_samples_a_t;
#define ISM303DAC_TAP_6D_THS_A 0x31U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_ths : 5;
uint8_t _6d_ths : 2;
@@ -358,7 +371,8 @@ typedef struct {
} ism303dac_tap_6d_ths_a_t;
#define ISM303DAC_INT_DUR_A 0x32U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shock : 2;
uint8_t quiet : 2;
@@ -372,7 +386,8 @@ typedef struct {
} ism303dac_int_dur_a_t;
#define ISM303DAC_WAKE_UP_THS_A 0x33U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wu_ths : 6;
uint8_t sleep_on : 1;
@@ -386,7 +401,8 @@ typedef struct {
} ism303dac_wake_up_ths_a_t;
#define ISM303DAC_WAKE_UP_DUR_A 0x34U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sleep_dur : 4;
uint8_t int1_fss7 : 1;
@@ -402,7 +418,8 @@ typedef struct {
} ism303dac_wake_up_dur_a_t;
#define ISM303DAC_FREE_FALL_A 0x35U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ths : 3;
uint8_t ff_dur : 5;
@@ -413,7 +430,8 @@ typedef struct {
} ism303dac_free_fall_a_t;
#define ISM303DAC_STATUS_DUP_A 0x36U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t drdy : 1;
uint8_t ff_ia : 1;
@@ -436,7 +454,8 @@ typedef struct {
} ism303dac_status_dup_a_t;
#define ISM303DAC_WAKE_UP_SRC_A 0x37U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_wu : 1;
uint8_t y_wu : 1;
@@ -457,7 +476,8 @@ typedef struct {
} ism303dac_wake_up_src_a_t;
#define ISM303DAC_TAP_SRC_A 0x38U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_tap : 1;
uint8_t y_tap : 1;
@@ -480,7 +500,8 @@ typedef struct {
} ism303dac_tap_src_a_t;
#define ISM303DAC_6D_SRC_A 0x39U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
@@ -503,7 +524,8 @@ typedef struct {
} ism303dac_6d_src_a_t;
#define ISM303DAC_FUNC_SRC_A 0x3EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t module_ready : 1;
@@ -516,7 +538,8 @@ typedef struct {
} ism303dac_func_src_a_t;
#define ISM303DAC_FUNC_CTRL_A 0x3FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 5;
uint8_t module_on : 1;
@@ -537,7 +560,8 @@ typedef struct {
#define ISM303DAC_OFFSET_Z_REG_H_M 0x4AU
#define ISM303DAC_WHO_AM_I_M 0x4FU
#define ISM303DAC_CFG_REG_A_M 0x60U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t md : 2;
uint8_t odr : 2;
@@ -557,7 +581,8 @@ typedef struct {
} ism303dac_cfg_reg_a_m_t;
#define ISM303DAC_CFG_REG_B_M 0x61U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lpf : 1;
uint8_t set_rst : 2; /* off_canc + set_freq */
@@ -575,7 +600,8 @@ typedef struct {
} ism303dac_cfg_reg_b_m_t;
#define ISM303DAC_CFG_REG_C_M 0x62U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int_mag : 1;
uint8_t self_test : 1;
@@ -598,7 +624,8 @@ typedef struct {
} ism303dac_cfg_reg_c_m_t;
#define ISM303DAC_INT_CRTL_REG_M 0x63U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ien : 1;
uint8_t iel : 1;
@@ -619,7 +646,8 @@ typedef struct {
} ism303dac_int_crtl_reg_m_t;
#define ISM303DAC_INT_SOURCE_REG_M 0x64U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t _int : 1;
uint8_t mroi : 1;
@@ -644,7 +672,8 @@ typedef struct {
#define ISM303DAC_INT_THS_L_REG_M 0x65U
#define ISM303DAC_INT_THS_H_REG_M 0x66U
#define ISM303DAC_STATUS_REG_M 0x67U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xda : 1;
uint8_t yda : 1;
@@ -675,9 +704,9 @@ typedef struct {
/**
* @defgroup ISM303DAC_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -685,7 +714,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
ism303dac_ctrl1_a_t ctrl1_a;
ism303dac_ctrl2_a_t ctrl2_a;
ism303dac_ctrl3_a_t ctrl3_a;
@@ -721,9 +751,11 @@ typedef union{
*
*/
-int32_t ism303dac_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t ism303dac_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t ism303dac_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t ism303dac_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
float_t ism303dac_from_fs2g_to_mg(int16_t lsb);
@@ -735,7 +767,8 @@ float_t ism303dac_from_lsb_to_mG(int16_t lsb);
float_t ism303dac_from_lsb_to_celsius(int16_t lsb);
-typedef struct {
+typedef struct
+{
ism303dac_fifo_src_a_t fifo_src_a;
ism303dac_status_dup_a_t status_dup_a;
ism303dac_wake_up_src_a_t wake_up_src_a;
@@ -756,7 +789,8 @@ int32_t ism303dac_mg_block_data_update_set(stmdev_ctx_t *ctx,
int32_t ism303dac_mg_block_data_update_get(stmdev_ctx_t *ctx,
uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM303DAC_MG_LSB_AT_LOW_ADD = 0,
ISM303DAC_MG_MSB_AT_LOW_ADD = 1,
} ism303dac_mg_ble_t;
@@ -765,7 +799,8 @@ int32_t ism303dac_mg_data_format_set(stmdev_ctx_t *ctx,
int32_t ism303dac_mg_data_format_get(stmdev_ctx_t *ctx,
ism303dac_mg_ble_t *val);
-typedef enum {
+typedef enum
+{
ISM303DAC_XL_2g = 0,
ISM303DAC_XL_16g = 1,
ISM303DAC_XL_4g = 2,
@@ -776,7 +811,8 @@ int32_t ism303dac_xl_full_scale_set(stmdev_ctx_t *ctx,
int32_t ism303dac_xl_full_scale_get(stmdev_ctx_t *ctx,
ism303dac_xl_fs_t *val);
-typedef enum {
+typedef enum
+{
ISM303DAC_XL_ODR_OFF = 0x00,
ISM303DAC_XL_ODR_1Hz_LP = 0x08,
ISM303DAC_XL_ODR_12Hz5_LP = 0x09,
@@ -808,15 +844,19 @@ int32_t ism303dac_xl_status_reg_get(stmdev_ctx_t *ctx,
int32_t ism303dac_mg_status_get(stmdev_ctx_t *ctx,
ism303dac_status_reg_m_t *val);
-int32_t ism303dac_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism303dac_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t ism303dac_mg_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t ism303dac_mg_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t ism303dac_mg_user_offset_set(stmdev_ctx_t *ctx, uint16_t *val);
-int32_t ism303dac_mg_user_offset_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t ism303dac_mg_user_offset_set(stmdev_ctx_t *ctx,
+ uint16_t *val);
+int32_t ism303dac_mg_user_offset_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
-typedef enum {
+typedef enum
+{
ISM303DAC_MG_CONTINUOUS_MODE = 0,
ISM303DAC_MG_SINGLE_TRIGGER = 1,
ISM303DAC_MG_POWER_DOWN = 2,
@@ -826,7 +866,8 @@ int32_t ism303dac_mg_operating_mode_set(stmdev_ctx_t *ctx,
int32_t ism303dac_mg_operating_mode_get(stmdev_ctx_t *ctx,
ism303dac_mg_md_t *val);
-typedef enum {
+typedef enum
+{
ISM303DAC_MG_ODR_10Hz = 0,
ISM303DAC_MG_ODR_20Hz = 1,
ISM303DAC_MG_ODR_50Hz = 2,
@@ -837,7 +878,8 @@ int32_t ism303dac_mg_data_rate_set(stmdev_ctx_t *ctx,
int32_t ism303dac_mg_data_rate_get(stmdev_ctx_t *ctx,
ism303dac_mg_odr_t *val);
-typedef enum {
+typedef enum
+{
ISM303DAC_MG_HIGH_RESOLUTION = 0,
ISM303DAC_MG_LOW_POWER = 1,
} ism303dac_mg_lp_t;
@@ -846,10 +888,13 @@ int32_t ism303dac_mg_power_mode_set(stmdev_ctx_t *ctx,
int32_t ism303dac_mg_power_mode_get(stmdev_ctx_t *ctx,
ism303dac_mg_lp_t *val);
-int32_t ism303dac_mg_offset_temp_comp_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism303dac_mg_offset_temp_comp_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism303dac_mg_offset_temp_comp_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism303dac_mg_offset_temp_comp_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM303DAC_MG_SET_SENS_ODR_DIV_63 = 0,
ISM303DAC_MG_SENS_OFF_CANC_EVERY_ODR = 1,
ISM303DAC_MG_SET_SENS_ONLY_AT_POWER_ON = 2,
@@ -872,14 +917,17 @@ int32_t ism303dac_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val);
int32_t ism303dac_xl_temperature_raw_get(stmdev_ctx_t *ctx,
uint8_t *buff);
-int32_t ism303dac_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t ism303dac_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
int32_t ism303dac_xl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t ism303dac_mg_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t ism303dac_xl_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism303dac_xl_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism303dac_xl_auto_increment_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism303dac_xl_auto_increment_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t ism303dac_xl_reset_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism303dac_xl_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -893,7 +941,8 @@ int32_t ism303dac_xl_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t ism303dac_mg_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism303dac_mg_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM303DAC_XL_ST_DISABLE = 0,
ISM303DAC_XL_ST_POSITIVE = 1,
ISM303DAC_XL_ST_NEGATIVE = 2,
@@ -906,7 +955,8 @@ int32_t ism303dac_xl_self_test_get(stmdev_ctx_t *ctx,
int32_t ism303dac_mg_self_test_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism303dac_mg_self_test_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM303DAC_XL_DRDY_LATCHED = 0,
ISM303DAC_XL_DRDY_PULSED = 1,
} ism303dac_xl_drdy_pulsed_t;
@@ -915,7 +965,8 @@ int32_t ism303dac_xl_data_ready_mode_set(stmdev_ctx_t *ctx,
int32_t ism303dac_xl_data_ready_mode_get(stmdev_ctx_t *ctx,
ism303dac_xl_drdy_pulsed_t *val);
-typedef enum {
+typedef enum
+{
ISM303DAC_XL_HP_INTERNAL_ONLY = 0,
ISM303DAC_XL_HP_ON_OUTPUTS = 1,
} ism303dac_xl_fds_slope_t;
@@ -924,7 +975,8 @@ int32_t ism303dac_xl_hp_path_set(stmdev_ctx_t *ctx,
int32_t ism303dac_xl_hp_path_get(stmdev_ctx_t *ctx,
ism303dac_xl_fds_slope_t *val);
-typedef enum {
+typedef enum
+{
ISM303DAC_MG_ODR_DIV_2 = 0,
ISM303DAC_MG_ODR_DIV_4 = 1,
} ism303dac_mg_lpf_t;
@@ -933,7 +985,8 @@ int32_t ism303dac_mg_low_pass_bandwidth_set(stmdev_ctx_t *ctx,
int32_t ism303dac_mg_low_pass_bandwidth_get(stmdev_ctx_t *ctx,
ism303dac_mg_lpf_t *val);
-typedef enum {
+typedef enum
+{
ISM303DAC_XL_SPI_4_WIRE = 0,
ISM303DAC_XL_SPI_3_WIRE = 1,
} ism303dac_xl_sim_t;
@@ -942,7 +995,8 @@ int32_t ism303dac_xl_spi_mode_set(stmdev_ctx_t *ctx,
int32_t ism303dac_xl_spi_mode_get(stmdev_ctx_t *ctx,
ism303dac_xl_sim_t *val);
-typedef enum {
+typedef enum
+{
ISM303DAC_XL_I2C_ENABLE = 0,
ISM303DAC_XL_I2C_DISABLE = 1,
} ism303dac_xl_i2c_disable_t;
@@ -951,7 +1005,8 @@ int32_t ism303dac_xl_i2c_interface_set(stmdev_ctx_t *ctx,
int32_t ism303dac_xl_i2c_interface_get(stmdev_ctx_t *ctx,
ism303dac_xl_i2c_disable_t *val);
-typedef enum {
+typedef enum
+{
ISM303DAC_MG_I2C_ENABLE = 0,
ISM303DAC_MG_I2C_DISABLE = 1,
} ism303dac_mg_i2c_dis_t;
@@ -960,7 +1015,8 @@ int32_t ism303dac_mg_i2c_interface_set(stmdev_ctx_t *ctx,
int32_t ism303dac_mg_i2c_interface_get(stmdev_ctx_t *ctx,
ism303dac_mg_i2c_dis_t *val);
-typedef enum {
+typedef enum
+{
ISM303DAC_XL_PULL_UP_CONNECTED = 0,
ISM303DAC_XL_PULL_UP_DISCONNECTED = 1,
} ism303dac_xl_if_cs_pu_dis_t;
@@ -969,16 +1025,18 @@ int32_t ism303dac_xl_cs_mode_set(stmdev_ctx_t *ctx,
int32_t ism303dac_xl_cs_mode_get(stmdev_ctx_t *ctx,
ism303dac_xl_if_cs_pu_dis_t *val);
-typedef enum {
+typedef enum
+{
ISM303DAC_XL_PUSH_PULL = 0,
ISM303DAC_XL_OPEN_DRAIN = 1,
} ism303dac_xl_pp_od_t;
int32_t ism303dac_xl_pin_mode_set(stmdev_ctx_t *ctx,
ism303dac_xl_pp_od_t val);
int32_t ism303dac_xl_pin_mode_get(stmdev_ctx_t *ctx,
- ism303dac_xl_pp_od_t *val);
+ ism303dac_xl_pp_od_t *val);
-typedef enum {
+typedef enum
+{
ISM303DAC_XL_ACTIVE_HIGH = 0,
ISM303DAC_XL_ACTIVE_LOW = 1,
} ism303dac_xl_h_lactive_t;
@@ -987,7 +1045,8 @@ int32_t ism303dac_xl_pin_polarity_set(stmdev_ctx_t *ctx,
int32_t ism303dac_xl_pin_polarity_get(stmdev_ctx_t *ctx,
ism303dac_xl_h_lactive_t *val);
-typedef enum {
+typedef enum
+{
ISM303DAC_XL_INT_PULSED = 0,
ISM303DAC_XL_INT_LATCHED = 1,
} ism303dac_xl_lir_t;
@@ -996,7 +1055,8 @@ int32_t ism303dac_xl_int_notification_set(stmdev_ctx_t *ctx,
int32_t ism303dac_xl_int_notification_get(stmdev_ctx_t *ctx,
ism303dac_xl_lir_t *val);
-typedef struct{
+typedef struct
+{
uint8_t int1_drdy : 1;
uint8_t int1_fth : 1;
uint8_t int1_6d : 1;
@@ -1011,7 +1071,8 @@ int32_t ism303dac_xl_pin_int1_route_set(stmdev_ctx_t *ctx,
int32_t ism303dac_xl_pin_int1_route_get(stmdev_ctx_t *ctx,
ism303dac_xl_pin_int1_route_t *val);
-typedef struct{
+typedef struct
+{
uint8_t int2_boot : 1;
uint8_t int2_fth : 1;
uint8_t int2_drdy : 1;
@@ -1043,7 +1104,8 @@ int32_t ism303dac_mg_int_gen_treshold_set(stmdev_ctx_t *ctx,
int32_t ism303dac_mg_int_gen_treshold_get(stmdev_ctx_t *ctx,
uint16_t *val);
-typedef enum {
+typedef enum
+{
ISM303DAC_MG_CHECK_BEFORE = 0,
ISM303DAC_MG_CHECK_AFTER = 1,
} ism303dac_mg_int_on_dataoff_t;
@@ -1052,8 +1114,10 @@ int32_t ism303dac_mg_offset_int_conf_set(stmdev_ctx_t *ctx,
int32_t ism303dac_mg_offset_int_conf_get(stmdev_ctx_t *ctx,
ism303dac_mg_int_on_dataoff_t *val);
-int32_t ism303dac_xl_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism303dac_xl_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism303dac_xl_wkup_threshold_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism303dac_xl_wkup_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t ism303dac_xl_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism303dac_xl_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1061,8 +1125,10 @@ int32_t ism303dac_xl_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t ism303dac_xl_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism303dac_xl_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t ism303dac_xl_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism303dac_xl_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism303dac_xl_act_sleep_dur_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism303dac_xl_act_sleep_dur_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t ism303dac_xl_tap_detection_on_z_set(stmdev_ctx_t *ctx,
uint8_t val);
@@ -1079,8 +1145,10 @@ int32_t ism303dac_xl_tap_detection_on_x_set(stmdev_ctx_t *ctx,
int32_t ism303dac_xl_tap_detection_on_x_get(stmdev_ctx_t *ctx,
uint8_t *val);
-int32_t ism303dac_xl_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism303dac_xl_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism303dac_xl_tap_threshold_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism303dac_xl_tap_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t ism303dac_xl_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism303dac_xl_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1091,7 +1159,8 @@ int32_t ism303dac_xl_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t ism303dac_xl_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism303dac_xl_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM303DAC_XL_ONLY_SINGLE = 0,
ISM303DAC_XL_ONLY_DOUBLE = 1,
} ism303dac_xl_single_double_tap_t;
@@ -1101,9 +1170,10 @@ int32_t ism303dac_xl_tap_mode_get(stmdev_ctx_t *ctx,
ism303dac_xl_single_double_tap_t *val);
int32_t ism303dac_xl_tap_src_get(stmdev_ctx_t *ctx,
- ism303dac_tap_src_a_t *val);
+ ism303dac_tap_src_a_t *val);
-typedef enum {
+typedef enum
+{
ISM303DAC_XL_DEG_80 = 0,
ISM303DAC_XL_DEG_70 = 1,
ISM303DAC_XL_DEG_60 = 2,
@@ -1124,14 +1194,16 @@ int32_t ism303dac_xl_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism303dac_xl_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t ism303dac_xl_ff_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism303dac_xl_ff_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism303dac_xl_ff_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t ism303dac_xl_fifo_xl_module_batch_set(stmdev_ctx_t *ctx,
uint8_t val);
int32_t ism303dac_xl_fifo_xl_module_batch_get(stmdev_ctx_t *ctx,
uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM303DAC_XL_BYPASS_MODE = 0,
ISM303DAC_XL_FIFO_MODE = 1,
ISM303DAC_XL_STREAM_TO_FIFO_MODE = 3,
@@ -1143,16 +1215,22 @@ int32_t ism303dac_xl_fifo_mode_set(stmdev_ctx_t *ctx,
int32_t ism303dac_xl_fifo_mode_get(stmdev_ctx_t *ctx,
ism303dac_xl_fmode_t *val);
-int32_t ism303dac_xl_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism303dac_xl_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism303dac_xl_fifo_watermark_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism303dac_xl_fifo_watermark_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t ism303dac_xl_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism303dac_xl_fifo_full_flag_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t ism303dac_xl_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism303dac_xl_fifo_ovr_flag_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t ism303dac_xl_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism303dac_xl_fifo_wtm_flag_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t ism303dac_xl_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t ism303dac_xl_fifo_data_level_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
int32_t ism303dac_xl_fifo_src_get(stmdev_ctx_t *ctx,
ism303dac_fifo_src_a_t *val);
diff --git a/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.c b/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.c
index 6ee6a101a9ee863ab43568fc05e2f41afe5594e9..d7da7b657935cf91e11bdced7cdf1ab3c8ff4ff3 100644
--- a/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.c
+++ b/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file ism330dhcx_reg.c
- * @author Sensors Software Solution Team
- * @brief ISM330DHCX driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file ism330dhcx_reg.c
+ * @author Sensors Software Solution Team
+ * @brief ISM330DHCX driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "ism330dhcx_reg.h"
@@ -46,11 +46,13 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ism330dhcx_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t ism330dhcx_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +66,13 @@ int32_t ism330dhcx_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ism330dhcx_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t ism330dhcx_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -170,13 +174,16 @@ int32_t ism330dhcx_xl_full_scale_set(stmdev_ctx_t *ctx,
{
ism330dhcx_ctrl1_xl_t ctrl1_xl;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl1_xl.fs_xl = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
+ (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -193,25 +200,32 @@ int32_t ism330dhcx_xl_full_scale_get(stmdev_ctx_t *ctx,
{
ism330dhcx_ctrl1_xl_t ctrl1_xl;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- switch (ctrl1_xl.fs_xl){
+ switch (ctrl1_xl.fs_xl)
+ {
case ISM330DHCX_2g:
*val = ISM330DHCX_2g;
break;
+
case ISM330DHCX_16g:
*val = ISM330DHCX_16g;
break;
+
case ISM330DHCX_4g:
*val = ISM330DHCX_4g;
break;
+
case ISM330DHCX_8g:
*val = ISM330DHCX_8g;
break;
+
default:
*val = ISM330DHCX_2g;
break;
}
+
return ret;
}
@@ -233,84 +247,116 @@ int32_t ism330dhcx_xl_data_rate_set(stmdev_ctx_t *ctx,
ism330dhcx_mlc_odr_t mlc_odr;
ism330dhcx_ctrl1_xl_t ctrl1_xl;
int32_t ret;
-
/* Check the Finite State Machine data rate constraints */
ret = ism330dhcx_fsm_enable_get(ctx, &fsm_enable);
- if (ret == 0) {
- if ( (fsm_enable.fsm_enable_a.fsm1_en |
- fsm_enable.fsm_enable_a.fsm2_en |
- fsm_enable.fsm_enable_a.fsm3_en |
- fsm_enable.fsm_enable_a.fsm4_en |
- fsm_enable.fsm_enable_a.fsm5_en |
- fsm_enable.fsm_enable_a.fsm6_en |
- fsm_enable.fsm_enable_a.fsm7_en |
- fsm_enable.fsm_enable_a.fsm8_en |
- fsm_enable.fsm_enable_b.fsm9_en |
- fsm_enable.fsm_enable_b.fsm10_en |
- fsm_enable.fsm_enable_b.fsm11_en |
- fsm_enable.fsm_enable_b.fsm12_en |
- fsm_enable.fsm_enable_b.fsm13_en |
- fsm_enable.fsm_enable_b.fsm14_en |
- fsm_enable.fsm_enable_b.fsm15_en |
- fsm_enable.fsm_enable_b.fsm16_en ) == PROPERTY_ENABLE ){
+ if (ret == 0)
+ {
+ if ((fsm_enable.fsm_enable_a.fsm1_en |
+ fsm_enable.fsm_enable_a.fsm2_en |
+ fsm_enable.fsm_enable_a.fsm3_en |
+ fsm_enable.fsm_enable_a.fsm4_en |
+ fsm_enable.fsm_enable_a.fsm5_en |
+ fsm_enable.fsm_enable_a.fsm6_en |
+ fsm_enable.fsm_enable_a.fsm7_en |
+ fsm_enable.fsm_enable_a.fsm8_en |
+ fsm_enable.fsm_enable_b.fsm9_en |
+ fsm_enable.fsm_enable_b.fsm10_en |
+ fsm_enable.fsm_enable_b.fsm11_en |
+ fsm_enable.fsm_enable_b.fsm12_en |
+ fsm_enable.fsm_enable_b.fsm13_en |
+ fsm_enable.fsm_enable_b.fsm14_en |
+ fsm_enable.fsm_enable_b.fsm15_en |
+ fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
+ {
ret = ism330dhcx_fsm_data_rate_get(ctx, &fsm_odr);
- if (ret == 0) {
- switch (fsm_odr) {
- case ISM330DHCX_ODR_FSM_12Hz5:
- if (val == ISM330DHCX_XL_ODR_OFF){
+ if (ret == 0)
+ {
+ switch (fsm_odr)
+ {
+ case ISM330DHCX_ODR_FSM_12Hz5:
+ if (val == ISM330DHCX_XL_ODR_OFF)
+ {
odr_xl = ISM330DHCX_XL_ODR_12Hz5;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
- case ISM330DHCX_ODR_FSM_26Hz:
- if (val == ISM330DHCX_XL_ODR_OFF){
+ case ISM330DHCX_ODR_FSM_26Hz:
+ if (val == ISM330DHCX_XL_ODR_OFF)
+ {
odr_xl = ISM330DHCX_XL_ODR_26Hz;
+ }
- } else if (val == ISM330DHCX_XL_ODR_12Hz5){
+ else if (val == ISM330DHCX_XL_ODR_12Hz5)
+ {
odr_xl = ISM330DHCX_XL_ODR_26Hz;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
- case ISM330DHCX_ODR_FSM_52Hz:
- if (val == ISM330DHCX_XL_ODR_OFF){
+ case ISM330DHCX_ODR_FSM_52Hz:
+ if (val == ISM330DHCX_XL_ODR_OFF)
+ {
odr_xl = ISM330DHCX_XL_ODR_52Hz;
+ }
- } else if (val == ISM330DHCX_XL_ODR_12Hz5){
+ else if (val == ISM330DHCX_XL_ODR_12Hz5)
+ {
odr_xl = ISM330DHCX_XL_ODR_52Hz;
+ }
- } else if (val == ISM330DHCX_XL_ODR_26Hz){
+ else if (val == ISM330DHCX_XL_ODR_26Hz)
+ {
odr_xl = ISM330DHCX_XL_ODR_52Hz;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
- case ISM330DHCX_ODR_FSM_104Hz:
- if (val == ISM330DHCX_XL_ODR_OFF){
+ case ISM330DHCX_ODR_FSM_104Hz:
+ if (val == ISM330DHCX_XL_ODR_OFF)
+ {
odr_xl = ISM330DHCX_XL_ODR_104Hz;
+ }
- } else if (val == ISM330DHCX_XL_ODR_12Hz5){
+ else if (val == ISM330DHCX_XL_ODR_12Hz5)
+ {
odr_xl = ISM330DHCX_XL_ODR_104Hz;
+ }
- } else if (val == ISM330DHCX_XL_ODR_26Hz){
+ else if (val == ISM330DHCX_XL_ODR_26Hz)
+ {
odr_xl = ISM330DHCX_XL_ODR_104Hz;
+ }
- } else if (val == ISM330DHCX_XL_ODR_52Hz){
+ else if (val == ISM330DHCX_XL_ODR_52Hz)
+ {
odr_xl = ISM330DHCX_XL_ODR_104Hz;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
+
default:
odr_xl = val;
break;
@@ -321,65 +367,101 @@ int32_t ism330dhcx_xl_data_rate_set(stmdev_ctx_t *ctx,
/* Check the Machine Learning Core data rate constraints */
mlc_enable = PROPERTY_DISABLE;
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mlc_get(ctx, &mlc_enable);
- if ( mlc_enable == PROPERTY_ENABLE ){
+ if (mlc_enable == PROPERTY_ENABLE)
+ {
ret = ism330dhcx_mlc_data_rate_get(ctx, &mlc_odr);
- if (ret == 0) {
- switch (mlc_odr) {
- case ISM330DHCX_ODR_PRGS_12Hz5:
- if (val == ISM330DHCX_XL_ODR_OFF){
+ if (ret == 0)
+ {
+ switch (mlc_odr)
+ {
+ case ISM330DHCX_ODR_PRGS_12Hz5:
+ if (val == ISM330DHCX_XL_ODR_OFF)
+ {
odr_xl = ISM330DHCX_XL_ODR_12Hz5;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
+
case ISM330DHCX_ODR_PRGS_26Hz:
- if (val == ISM330DHCX_XL_ODR_OFF){
+ if (val == ISM330DHCX_XL_ODR_OFF)
+ {
odr_xl = ISM330DHCX_XL_ODR_26Hz;
+ }
- } else if (val == ISM330DHCX_XL_ODR_12Hz5){
+ else if (val == ISM330DHCX_XL_ODR_12Hz5)
+ {
odr_xl = ISM330DHCX_XL_ODR_26Hz;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
- case ISM330DHCX_ODR_PRGS_52Hz:
- if (val == ISM330DHCX_XL_ODR_OFF){
+ case ISM330DHCX_ODR_PRGS_52Hz:
+ if (val == ISM330DHCX_XL_ODR_OFF)
+ {
odr_xl = ISM330DHCX_XL_ODR_52Hz;
+ }
- } else if (val == ISM330DHCX_XL_ODR_12Hz5){
+ else if (val == ISM330DHCX_XL_ODR_12Hz5)
+ {
odr_xl = ISM330DHCX_XL_ODR_52Hz;
+ }
- } else if (val == ISM330DHCX_XL_ODR_26Hz){
+ else if (val == ISM330DHCX_XL_ODR_26Hz)
+ {
odr_xl = ISM330DHCX_XL_ODR_52Hz;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
+
case ISM330DHCX_ODR_PRGS_104Hz:
- if (val == ISM330DHCX_XL_ODR_OFF){
+ if (val == ISM330DHCX_XL_ODR_OFF)
+ {
odr_xl = ISM330DHCX_XL_ODR_104Hz;
+ }
- } else if (val == ISM330DHCX_XL_ODR_12Hz5){
+ else if (val == ISM330DHCX_XL_ODR_12Hz5)
+ {
odr_xl = ISM330DHCX_XL_ODR_104Hz;
+ }
- } else if (val == ISM330DHCX_XL_ODR_26Hz){
+ else if (val == ISM330DHCX_XL_ODR_26Hz)
+ {
odr_xl = ISM330DHCX_XL_ODR_104Hz;
+ }
- } else if (val == ISM330DHCX_XL_ODR_52Hz){
+ else if (val == ISM330DHCX_XL_ODR_52Hz)
+ {
odr_xl = ISM330DHCX_XL_ODR_104Hz;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
+
default:
odr_xl = val;
break;
@@ -387,15 +469,20 @@ int32_t ism330dhcx_xl_data_rate_set(stmdev_ctx_t *ctx,
}
}
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
+ (uint8_t *)&ctrl1_xl, 1);
}
- if(ret == 0){
- ctrl1_xl.odr_xl= (uint8_t)odr_xl;
+
+ if (ret == 0)
+ {
+ ctrl1_xl.odr_xl = (uint8_t)odr_xl;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
+ (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -408,53 +495,68 @@ int32_t ism330dhcx_xl_data_rate_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_xl_data_rate_get(stmdev_ctx_t *ctx,
- ism330dhcx_odr_xl_t *val)
+ ism330dhcx_odr_xl_t *val)
{
ism330dhcx_ctrl1_xl_t ctrl1_xl;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- switch (ctrl1_xl.odr_xl){
+ switch (ctrl1_xl.odr_xl)
+ {
case ISM330DHCX_XL_ODR_OFF:
*val = ISM330DHCX_XL_ODR_OFF;
break;
+
case ISM330DHCX_XL_ODR_12Hz5:
*val = ISM330DHCX_XL_ODR_12Hz5;
break;
+
case ISM330DHCX_XL_ODR_26Hz:
*val = ISM330DHCX_XL_ODR_26Hz;
break;
+
case ISM330DHCX_XL_ODR_52Hz:
*val = ISM330DHCX_XL_ODR_52Hz;
break;
+
case ISM330DHCX_XL_ODR_104Hz:
*val = ISM330DHCX_XL_ODR_104Hz;
break;
+
case ISM330DHCX_XL_ODR_208Hz:
*val = ISM330DHCX_XL_ODR_208Hz;
break;
+
case ISM330DHCX_XL_ODR_417Hz:
*val = ISM330DHCX_XL_ODR_417Hz;
break;
+
case ISM330DHCX_XL_ODR_833Hz:
*val = ISM330DHCX_XL_ODR_833Hz;
break;
+
case ISM330DHCX_XL_ODR_1667Hz:
*val = ISM330DHCX_XL_ODR_1667Hz;
break;
+
case ISM330DHCX_XL_ODR_3333Hz:
*val = ISM330DHCX_XL_ODR_3333Hz;
break;
+
case ISM330DHCX_XL_ODR_6667Hz:
*val = ISM330DHCX_XL_ODR_6667Hz;
break;
+
case ISM330DHCX_XL_ODR_6Hz5:
*val = ISM330DHCX_XL_ODR_6Hz5;
break;
+
default:
*val = ISM330DHCX_XL_ODR_OFF;
break;
}
+
return ret;
}
@@ -471,12 +573,16 @@ int32_t ism330dhcx_gy_full_scale_set(stmdev_ctx_t *ctx,
{
ism330dhcx_ctrl2_g_t ctrl2_g;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL2_G,
+ (uint8_t *)&ctrl2_g, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- if(ret == 0){
- ctrl2_g.fs_g= (uint8_t)val;
- ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
+ if (ret == 0)
+ {
+ ctrl2_g.fs_g = (uint8_t)val;
+ ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL2_G,
+ (uint8_t *)&ctrl2_g, 1);
}
+
return ret;
}
@@ -493,31 +599,40 @@ int32_t ism330dhcx_gy_full_scale_get(stmdev_ctx_t *ctx,
{
ism330dhcx_ctrl2_g_t ctrl2_g;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL2_G,
+ (uint8_t *)&ctrl2_g, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- switch (ctrl2_g.fs_g){
+ switch (ctrl2_g.fs_g)
+ {
case ISM330DHCX_125dps:
*val = ISM330DHCX_125dps;
break;
+
case ISM330DHCX_250dps:
*val = ISM330DHCX_250dps;
break;
+
case ISM330DHCX_500dps:
*val = ISM330DHCX_500dps;
break;
+
case ISM330DHCX_1000dps:
*val = ISM330DHCX_1000dps;
break;
+
case ISM330DHCX_2000dps:
*val = ISM330DHCX_2000dps;
break;
+
case ISM330DHCX_4000dps:
*val = ISM330DHCX_4000dps;
break;
+
default:
*val = ISM330DHCX_125dps;
break;
}
+
return ret;
}
@@ -539,84 +654,116 @@ int32_t ism330dhcx_gy_data_rate_set(stmdev_ctx_t *ctx,
ism330dhcx_mlc_odr_t mlc_odr;
ism330dhcx_ctrl2_g_t ctrl2_g;
int32_t ret;
-
/* Check the Finite State Machine data rate constraints */
ret = ism330dhcx_fsm_enable_get(ctx, &fsm_enable);
- if (ret == 0) {
- if ( (fsm_enable.fsm_enable_a.fsm1_en |
- fsm_enable.fsm_enable_a.fsm2_en |
- fsm_enable.fsm_enable_a.fsm3_en |
- fsm_enable.fsm_enable_a.fsm4_en |
- fsm_enable.fsm_enable_a.fsm5_en |
- fsm_enable.fsm_enable_a.fsm6_en |
- fsm_enable.fsm_enable_a.fsm7_en |
- fsm_enable.fsm_enable_a.fsm8_en |
- fsm_enable.fsm_enable_b.fsm9_en |
- fsm_enable.fsm_enable_b.fsm10_en |
- fsm_enable.fsm_enable_b.fsm11_en |
- fsm_enable.fsm_enable_b.fsm12_en |
- fsm_enable.fsm_enable_b.fsm13_en |
- fsm_enable.fsm_enable_b.fsm14_en |
- fsm_enable.fsm_enable_b.fsm15_en |
- fsm_enable.fsm_enable_b.fsm16_en ) == PROPERTY_ENABLE ){
+ if (ret == 0)
+ {
+ if ((fsm_enable.fsm_enable_a.fsm1_en |
+ fsm_enable.fsm_enable_a.fsm2_en |
+ fsm_enable.fsm_enable_a.fsm3_en |
+ fsm_enable.fsm_enable_a.fsm4_en |
+ fsm_enable.fsm_enable_a.fsm5_en |
+ fsm_enable.fsm_enable_a.fsm6_en |
+ fsm_enable.fsm_enable_a.fsm7_en |
+ fsm_enable.fsm_enable_a.fsm8_en |
+ fsm_enable.fsm_enable_b.fsm9_en |
+ fsm_enable.fsm_enable_b.fsm10_en |
+ fsm_enable.fsm_enable_b.fsm11_en |
+ fsm_enable.fsm_enable_b.fsm12_en |
+ fsm_enable.fsm_enable_b.fsm13_en |
+ fsm_enable.fsm_enable_b.fsm14_en |
+ fsm_enable.fsm_enable_b.fsm15_en |
+ fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
+ {
ret = ism330dhcx_fsm_data_rate_get(ctx, &fsm_odr);
- if (ret == 0) {
- switch (fsm_odr) {
- case ISM330DHCX_ODR_FSM_12Hz5:
- if (val == ISM330DHCX_GY_ODR_OFF){
+ if (ret == 0)
+ {
+ switch (fsm_odr)
+ {
+ case ISM330DHCX_ODR_FSM_12Hz5:
+ if (val == ISM330DHCX_GY_ODR_OFF)
+ {
odr_gy = ISM330DHCX_GY_ODR_12Hz5;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
- case ISM330DHCX_ODR_FSM_26Hz:
- if (val == ISM330DHCX_GY_ODR_OFF){
+ case ISM330DHCX_ODR_FSM_26Hz:
+ if (val == ISM330DHCX_GY_ODR_OFF)
+ {
odr_gy = ISM330DHCX_GY_ODR_26Hz;
+ }
- } else if (val == ISM330DHCX_GY_ODR_12Hz5){
+ else if (val == ISM330DHCX_GY_ODR_12Hz5)
+ {
odr_gy = ISM330DHCX_GY_ODR_26Hz;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
- case ISM330DHCX_ODR_FSM_52Hz:
- if (val == ISM330DHCX_GY_ODR_OFF){
+ case ISM330DHCX_ODR_FSM_52Hz:
+ if (val == ISM330DHCX_GY_ODR_OFF)
+ {
odr_gy = ISM330DHCX_GY_ODR_52Hz;
+ }
- } else if (val == ISM330DHCX_GY_ODR_12Hz5){
+ else if (val == ISM330DHCX_GY_ODR_12Hz5)
+ {
odr_gy = ISM330DHCX_GY_ODR_52Hz;
+ }
- } else if (val == ISM330DHCX_GY_ODR_26Hz){
+ else if (val == ISM330DHCX_GY_ODR_26Hz)
+ {
odr_gy = ISM330DHCX_GY_ODR_52Hz;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
- case ISM330DHCX_ODR_FSM_104Hz:
- if (val == ISM330DHCX_GY_ODR_OFF){
+ case ISM330DHCX_ODR_FSM_104Hz:
+ if (val == ISM330DHCX_GY_ODR_OFF)
+ {
odr_gy = ISM330DHCX_GY_ODR_104Hz;
+ }
- } else if (val == ISM330DHCX_GY_ODR_12Hz5){
+ else if (val == ISM330DHCX_GY_ODR_12Hz5)
+ {
odr_gy = ISM330DHCX_GY_ODR_104Hz;
+ }
- } else if (val == ISM330DHCX_GY_ODR_26Hz){
+ else if (val == ISM330DHCX_GY_ODR_26Hz)
+ {
odr_gy = ISM330DHCX_GY_ODR_104Hz;
+ }
- } else if (val == ISM330DHCX_GY_ODR_52Hz){
+ else if (val == ISM330DHCX_GY_ODR_52Hz)
+ {
odr_gy = ISM330DHCX_GY_ODR_104Hz;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
+
default:
odr_gy = val;
break;
@@ -627,67 +774,101 @@ int32_t ism330dhcx_gy_data_rate_set(stmdev_ctx_t *ctx,
/* Check the Machine Learning Core data rate constraints */
mlc_enable = PROPERTY_DISABLE;
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mlc_get(ctx, &mlc_enable);
- if ( mlc_enable == PROPERTY_ENABLE ){
+ if (mlc_enable == PROPERTY_ENABLE)
+ {
ret = ism330dhcx_mlc_data_rate_get(ctx, &mlc_odr);
- if (ret == 0) {
- switch (mlc_odr) {
- case ISM330DHCX_ODR_PRGS_12Hz5:
- if (val == ISM330DHCX_GY_ODR_OFF){
+ if (ret == 0)
+ {
+ switch (mlc_odr)
+ {
+ case ISM330DHCX_ODR_PRGS_12Hz5:
+ if (val == ISM330DHCX_GY_ODR_OFF)
+ {
odr_gy = ISM330DHCX_GY_ODR_12Hz5;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
- case ISM330DHCX_ODR_PRGS_26Hz:
- if (val == ISM330DHCX_GY_ODR_OFF){
+ case ISM330DHCX_ODR_PRGS_26Hz:
+ if (val == ISM330DHCX_GY_ODR_OFF)
+ {
odr_gy = ISM330DHCX_GY_ODR_26Hz;
+ }
- } else if (val == ISM330DHCX_GY_ODR_12Hz5){
+ else if (val == ISM330DHCX_GY_ODR_12Hz5)
+ {
odr_gy = ISM330DHCX_GY_ODR_26Hz;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
- case ISM330DHCX_ODR_PRGS_52Hz:
- if (val == ISM330DHCX_GY_ODR_OFF){
+ case ISM330DHCX_ODR_PRGS_52Hz:
+ if (val == ISM330DHCX_GY_ODR_OFF)
+ {
odr_gy = ISM330DHCX_GY_ODR_52Hz;
+ }
- } else if (val == ISM330DHCX_GY_ODR_12Hz5){
+ else if (val == ISM330DHCX_GY_ODR_12Hz5)
+ {
odr_gy = ISM330DHCX_GY_ODR_52Hz;
+ }
- } else if (val == ISM330DHCX_GY_ODR_26Hz){
+ else if (val == ISM330DHCX_GY_ODR_26Hz)
+ {
odr_gy = ISM330DHCX_GY_ODR_52Hz;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
- case ISM330DHCX_ODR_PRGS_104Hz:
- if (val == ISM330DHCX_GY_ODR_OFF){
+ case ISM330DHCX_ODR_PRGS_104Hz:
+ if (val == ISM330DHCX_GY_ODR_OFF)
+ {
odr_gy = ISM330DHCX_GY_ODR_104Hz;
+ }
- } else if (val == ISM330DHCX_GY_ODR_12Hz5){
+ else if (val == ISM330DHCX_GY_ODR_12Hz5)
+ {
odr_gy = ISM330DHCX_GY_ODR_104Hz;
+ }
- } else if (val == ISM330DHCX_GY_ODR_26Hz){
+ else if (val == ISM330DHCX_GY_ODR_26Hz)
+ {
odr_gy = ISM330DHCX_GY_ODR_104Hz;
+ }
- } else if (val == ISM330DHCX_GY_ODR_52Hz){
+ else if (val == ISM330DHCX_GY_ODR_52Hz)
+ {
odr_gy = ISM330DHCX_GY_ODR_104Hz;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
+
default:
odr_gy = val;
break;
@@ -695,13 +876,20 @@ int32_t ism330dhcx_gy_data_rate_set(stmdev_ctx_t *ctx,
}
}
}
- if (ret == 0) {
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
+
+ if (ret == 0)
+ {
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL2_G,
+ (uint8_t *)&ctrl2_g, 1);
}
- if(ret == 0){
- ctrl2_g.odr_g= (uint8_t)odr_gy;
- ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
+
+ if (ret == 0)
+ {
+ ctrl2_g.odr_g = (uint8_t)odr_gy;
+ ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL2_G,
+ (uint8_t *)&ctrl2_g, 1);
}
+
return ret;
}
@@ -718,46 +906,60 @@ int32_t ism330dhcx_gy_data_rate_get(stmdev_ctx_t *ctx,
{
ism330dhcx_ctrl2_g_t ctrl2_g;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL2_G,
+ (uint8_t *)&ctrl2_g, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- switch (ctrl2_g.odr_g){
+ switch (ctrl2_g.odr_g)
+ {
case ISM330DHCX_GY_ODR_OFF:
*val = ISM330DHCX_GY_ODR_OFF;
break;
+
case ISM330DHCX_GY_ODR_12Hz5:
*val = ISM330DHCX_GY_ODR_12Hz5;
break;
+
case ISM330DHCX_GY_ODR_26Hz:
*val = ISM330DHCX_GY_ODR_26Hz;
break;
+
case ISM330DHCX_GY_ODR_52Hz:
*val = ISM330DHCX_GY_ODR_52Hz;
break;
+
case ISM330DHCX_GY_ODR_104Hz:
*val = ISM330DHCX_GY_ODR_104Hz;
break;
+
case ISM330DHCX_GY_ODR_208Hz:
*val = ISM330DHCX_GY_ODR_208Hz;
break;
+
case ISM330DHCX_GY_ODR_417Hz:
*val = ISM330DHCX_GY_ODR_417Hz;
break;
+
case ISM330DHCX_GY_ODR_833Hz:
*val = ISM330DHCX_GY_ODR_833Hz;
break;
+
case ISM330DHCX_GY_ODR_1667Hz:
*val = ISM330DHCX_GY_ODR_1667Hz;
break;
+
case ISM330DHCX_GY_ODR_3333Hz:
*val = ISM330DHCX_GY_ODR_3333Hz;
break;
+
case ISM330DHCX_GY_ODR_6667Hz:
*val = ISM330DHCX_GY_ODR_6667Hz;
break;
+
default:
*val = ISM330DHCX_GY_ODR_OFF;
break;
}
+
return ret;
}
@@ -769,16 +971,21 @@ int32_t ism330dhcx_gy_data_rate_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ism330dhcx_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
ism330dhcx_ctrl3_c_t ctrl3_c;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.bdu= (uint8_t)val;
- ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ if (ret == 0)
+ {
+ ctrl3_c.bdu = (uint8_t)val;
+ ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -790,12 +997,13 @@ int32_t ism330dhcx_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dhcx_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dhcx_ctrl3_c_t ctrl3_c;
int32_t ret;
-
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.bdu;
return ret;
@@ -815,12 +1023,16 @@ int32_t ism330dhcx_xl_offset_weight_set(stmdev_ctx_t *ctx,
{
ism330dhcx_ctrl6_c_t ctrl6_c;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL6_C,
+ (uint8_t *)&ctrl6_c, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
- ctrl6_c.usr_off_w= (uint8_t)val;
- ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ if (ret == 0)
+ {
+ ctrl6_c.usr_off_w = (uint8_t)val;
+ ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL6_C,
+ (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -838,20 +1050,24 @@ int32_t ism330dhcx_xl_offset_weight_get(stmdev_ctx_t *ctx,
{
ism330dhcx_ctrl6_c_t ctrl6_c;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL6_C,
+ (uint8_t *)&ctrl6_c, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
-
- switch (ctrl6_c.usr_off_w){
+ switch (ctrl6_c.usr_off_w)
+ {
case ISM330DHCX_LSb_1mg:
*val = ISM330DHCX_LSb_1mg;
break;
+
case ISM330DHCX_LSb_16mg:
*val = ISM330DHCX_LSb_16mg;
break;
+
default:
*val = ISM330DHCX_LSb_1mg;
break;
}
+
return ret;
}
@@ -868,12 +1084,16 @@ int32_t ism330dhcx_xl_power_mode_set(stmdev_ctx_t *ctx,
{
ism330dhcx_ctrl6_c_t ctrl6_c;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL6_C,
+ (uint8_t *)&ctrl6_c, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U;
- ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL6_C,
+ (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -890,19 +1110,24 @@ int32_t ism330dhcx_xl_power_mode_get(stmdev_ctx_t *ctx,
{
ism330dhcx_ctrl6_c_t ctrl6_c;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL6_C,
+ (uint8_t *)&ctrl6_c, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- switch (ctrl6_c.xl_hm_mode){
+ switch (ctrl6_c.xl_hm_mode)
+ {
case ISM330DHCX_HIGH_PERFORMANCE_MD:
*val = ISM330DHCX_HIGH_PERFORMANCE_MD;
break;
+
case ISM330DHCX_LOW_NORMAL_POWER_MD:
*val = ISM330DHCX_LOW_NORMAL_POWER_MD;
break;
+
default:
*val = ISM330DHCX_HIGH_PERFORMANCE_MD;
break;
}
+
return ret;
}
@@ -919,12 +1144,16 @@ int32_t ism330dhcx_gy_power_mode_set(stmdev_ctx_t *ctx,
{
ism330dhcx_ctrl7_g_t ctrl7_g;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL7_G,
+ (uint8_t *)&ctrl7_g, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
- ctrl7_g.g_hm_mode= (uint8_t)val;
- ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ if (ret == 0)
+ {
+ ctrl7_g.g_hm_mode = (uint8_t)val;
+ ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL7_G,
+ (uint8_t *)&ctrl7_g, 1);
}
+
return ret;
}
@@ -941,19 +1170,24 @@ int32_t ism330dhcx_gy_power_mode_get(stmdev_ctx_t *ctx,
{
ism330dhcx_ctrl7_g_t ctrl7_g;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL7_G,
+ (uint8_t *)&ctrl7_g, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- switch (ctrl7_g.g_hm_mode){
+ switch (ctrl7_g.g_hm_mode)
+ {
case ISM330DHCX_GY_HIGH_PERFORMANCE:
*val = ISM330DHCX_GY_HIGH_PERFORMANCE;
break;
+
case ISM330DHCX_GY_NORMAL:
*val = ISM330DHCX_GY_NORMAL;
break;
+
default:
*val = ISM330DHCX_GY_HIGH_PERFORMANCE;
break;
}
+
return ret;
}
@@ -971,41 +1205,58 @@ int32_t ism330dhcx_all_sources_get(stmdev_ctx_t *ctx,
ism330dhcx_all_sources_t *val)
{
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_ALL_INT_SRC,
- (uint8_t*)&val->all_int_src, 1);
- if(ret == 0){
+ (uint8_t *)&val->all_int_src, 1);
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_SRC,
- (uint8_t*)&val->wake_up_src, 1);
+ (uint8_t *)&val->wake_up_src, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_SRC,
- (uint8_t*)&val->tap_src, 1);
+ (uint8_t *)&val->tap_src, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_D6D_SRC,
- (uint8_t*)&val->d6d_src, 1);
+ (uint8_t *)&val->d6d_src, 1);
}
- if(ret == 0){
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_STATUS_REG,
- (uint8_t*)&val->status_reg, 1);
+
+ if (ret == 0)
+ {
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_STATUS_REG,
+ (uint8_t *)&val->status_reg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_STATUS,
- (uint8_t*)&val->emb_func_status, 1);
+ (uint8_t *)&val->emb_func_status, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FSM_STATUS_A,
- (uint8_t*)&val->fsm_status_a, 1);
+ (uint8_t *)&val->fsm_status_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FSM_STATUS_B,
- (uint8_t*)&val->fsm_status_b, 1);
+ (uint8_t *)&val->fsm_status_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
@@ -1024,7 +1275,8 @@ int32_t ism330dhcx_status_reg_get(stmdev_ctx_t *ctx,
ism330dhcx_status_reg_t *val)
{
int32_t ret;
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_STATUS_REG, (uint8_t*) val, 1);
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_STATUS_REG, (uint8_t *) val, 1);
+
return ret;
}
@@ -1036,13 +1288,13 @@ int32_t ism330dhcx_status_reg_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dhcx_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dhcx_status_reg_t status_reg;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_STATUS_REG,
- (uint8_t*)&status_reg, 1);
+ (uint8_t *)&status_reg, 1);
*val = status_reg.xlda;
return ret;
@@ -1056,13 +1308,13 @@ int32_t ism330dhcx_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dhcx_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dhcx_status_reg_t status_reg;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_STATUS_REG,
- (uint8_t*)&status_reg, 1);
+ (uint8_t *)&status_reg, 1);
*val = status_reg.gda;
return ret;
@@ -1081,9 +1333,8 @@ int32_t ism330dhcx_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
{
ism330dhcx_status_reg_t status_reg;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_STATUS_REG,
- (uint8_t*)&status_reg, 1);
+ (uint8_t *)&status_reg, 1);
*val = status_reg.tda;
return ret;
@@ -1099,10 +1350,12 @@ int32_t ism330dhcx_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t ism330dhcx_xl_usr_offset_x_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_X_OFS_USR, buff, 1);
+
return ret;
}
@@ -1116,10 +1369,12 @@ int32_t ism330dhcx_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t ism330dhcx_xl_usr_offset_x_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_X_OFS_USR, buff, 1);
+
return ret;
}
@@ -1133,10 +1388,12 @@ int32_t ism330dhcx_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t ism330dhcx_xl_usr_offset_y_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_Y_OFS_USR, buff, 1);
+
return ret;
}
@@ -1150,10 +1407,12 @@ int32_t ism330dhcx_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t ism330dhcx_xl_usr_offset_y_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_Y_OFS_USR, buff, 1);
+
return ret;
}
@@ -1167,10 +1426,12 @@ int32_t ism330dhcx_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t ism330dhcx_xl_usr_offset_z_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_Z_OFS_USR, buff, 1);
+
return ret;
}
@@ -1184,10 +1445,12 @@ int32_t ism330dhcx_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t ism330dhcx_xl_usr_offset_z_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_Z_OFS_USR, buff, 1);
+
return ret;
}
@@ -1203,13 +1466,16 @@ int32_t ism330dhcx_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_ctrl7_g_t ctrl7_g;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL7_G,
+ (uint8_t *)&ctrl7_g, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
- ctrl7_g.usr_off_on_out= (uint8_t)val;
+ if (ret == 0)
+ {
+ ctrl7_g.usr_off_on_out = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL7_G,
- (uint8_t*)&ctrl7_g, 1);
+ (uint8_t *)&ctrl7_g, 1);
}
+
return ret;
}
@@ -1225,8 +1491,8 @@ int32_t ism330dhcx_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dhcx_ctrl7_g_t ctrl7_g;
int32_t ret;
-
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL7_G,
+ (uint8_t *)&ctrl7_g, 1);
*val = ctrl7_g.usr_off_on_out;
return ret;
@@ -1255,7 +1521,6 @@ int32_t ism330dhcx_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ism330dhcx_timestamp_rst(stmdev_ctx_t *ctx)
{
uint8_t rst_val = 0xAA;
-
return ism330dhcx_write_reg(ctx, ISM330DHCX_TIMESTAMP2, &rst_val, 1);
}
@@ -1271,13 +1536,16 @@ int32_t ism330dhcx_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_ctrl10_c_t ctrl10_c;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL10_C,
+ (uint8_t *)&ctrl10_c, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
- ctrl10_c.timestamp_en= (uint8_t)val;
+ if (ret == 0)
+ {
+ ctrl10_c.timestamp_en = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL10_C,
- (uint8_t*)&ctrl10_c, 1);
+ (uint8_t *)&ctrl10_c, 1);
}
+
return ret;
}
@@ -1293,8 +1561,8 @@ int32_t ism330dhcx_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dhcx_ctrl10_c_t ctrl10_c;
int32_t ret;
-
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL10_C,
+ (uint8_t *)&ctrl10_c, 1);
*val = ctrl10_c.timestamp_en;
return ret;
@@ -1314,7 +1582,6 @@ int32_t ism330dhcx_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val)
{
uint8_t buff[4];
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TIMESTAMP0, buff, 4);
*val = buff[3];
*val = (*val * 256U) + buff[2];
@@ -1349,13 +1616,16 @@ int32_t ism330dhcx_rounding_mode_set(stmdev_ctx_t *ctx,
{
ism330dhcx_ctrl5_c_t ctrl5_c;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL5_C,
+ (uint8_t *)&ctrl5_c, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
- ctrl5_c.rounding= (uint8_t)val;
+ if (ret == 0)
+ {
+ ctrl5_c.rounding = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL5_C,
- (uint8_t*)&ctrl5_c, 1);
+ (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -1372,25 +1642,32 @@ int32_t ism330dhcx_rounding_mode_get(stmdev_ctx_t *ctx,
{
ism330dhcx_ctrl5_c_t ctrl5_c;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL5_C,
+ (uint8_t *)&ctrl5_c, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- switch (ctrl5_c.rounding){
+ switch (ctrl5_c.rounding)
+ {
case ISM330DHCX_NO_ROUND:
*val = ISM330DHCX_NO_ROUND;
break;
+
case ISM330DHCX_ROUND_XL:
*val = ISM330DHCX_ROUND_XL;
break;
+
case ISM330DHCX_ROUND_GY:
*val = ISM330DHCX_ROUND_GY;
break;
+
case ISM330DHCX_ROUND_GY_XL:
*val = ISM330DHCX_ROUND_GY_XL;
break;
+
default:
*val = ISM330DHCX_NO_ROUND;
break;
}
+
return ret;
}
@@ -1404,14 +1681,14 @@ int32_t ism330dhcx_rounding_mode_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
+int32_t ism330dhcx_temperature_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
{
uint8_t buff[2];
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_OUT_TEMP_L, buff, 2);
*val = (int16_t)buff[1];
- *val = (*val * 256) + (int16_t)buff[0];
+ *val = (*val * 256) + (int16_t)buff[0];
return ret;
}
@@ -1425,11 +1702,11 @@ int32_t ism330dhcx_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
+int32_t ism330dhcx_angular_rate_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
{
uint8_t buff[6];
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_OUTX_L_G, buff, 6);
val[0] = (int16_t)buff[1];
val[0] = (val[0] * 256) + (int16_t)buff[0];
@@ -1450,11 +1727,11 @@ int32_t ism330dhcx_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
+int32_t ism330dhcx_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
{
uint8_t buff[6];
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_OUTX_L_A, buff, 6);
val[0] = (int16_t)buff[1];
val[0] = (val[0] * 256) + (int16_t)buff[0];
@@ -1478,6 +1755,7 @@ int32_t ism330dhcx_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_DATA_OUT_X_L, buff, 6);
+
return ret;
}
@@ -1489,18 +1767,22 @@ int32_t ism330dhcx_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val)
+int32_t ism330dhcx_number_of_steps_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
uint8_t buff[2];
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_STEP_COUNTER_L, buff, 2);
*val = buff[1];
*val = (*val * 256U) + buff[0];
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
@@ -1518,20 +1800,26 @@ int32_t ism330dhcx_steps_reset(stmdev_ctx_t *ctx)
{
ism330dhcx_emb_func_src_t emb_func_src;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_SRC,
- (uint8_t*)&emb_func_src, 1);
+ (uint8_t *)&emb_func_src, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
emb_func_src.pedo_rst_step = PROPERTY_ENABLE;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_SRC,
- (uint8_t*)&emb_func_src, 1);
+ (uint8_t *)&emb_func_src, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -1546,12 +1834,17 @@ int32_t ism330dhcx_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MLC0_SRC, buff, 8);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -1562,11 +1855,55 @@ int32_t ism330dhcx_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff)
/**
* @defgroup ISM330DHCX_common
- * @brief This section groups common usefull functions.
+ * @brief This section groups common useful functions.
* @{
*
*/
+/**
+ * @brief DEVICE_CONF bit configuration[set]
+ *
+ * @param ctx Read / write interface definitions.(ptr)
+ * @param val Change the values of device_conf in reg CTRL9_XL
+ * @retval Interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t ism330dhcx_device_conf_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ ism330dhcx_ctrl9_xl_t ctrl9_xl;
+ int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl9_xl.device_conf = (uint8_t)val;
+ ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief DEVICE_CONF bit configuration[get]
+ *
+ * @param ctx Read / write interface definitions.(ptr)
+ * @param val Get the values of device_conf in reg CTRL9_XL
+ * @retval Interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t ism330dhcx_device_conf_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ ism330dhcx_ctrl9_xl_t ctrl9_xl;
+ int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
+ *val = ctrl9_xl.device_conf;
+
+ return ret;
+}
+
/**
* @brief Difference in percentage of the effective ODR (and timestamp rate)
* with respect to the typical.[set]
@@ -1581,14 +1918,16 @@ int32_t ism330dhcx_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_internal_freq_fine_t internal_freq_fine;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INTERNAL_FREQ_FINE,
- (uint8_t*)&internal_freq_fine, 1);
- if(ret == 0){
- internal_freq_fine.freq_fine= (uint8_t)val;
+ (uint8_t *)&internal_freq_fine, 1);
+
+ if (ret == 0)
+ {
+ internal_freq_fine.freq_fine = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_INTERNAL_FREQ_FINE,
- (uint8_t*)&internal_freq_fine, 1);
+ (uint8_t *)&internal_freq_fine, 1);
}
+
return ret;
}
@@ -1606,9 +1945,8 @@ int32_t ism330dhcx_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dhcx_internal_freq_fine_t internal_freq_fine;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INTERNAL_FREQ_FINE,
- (uint8_t*)&internal_freq_fine, 1);
+ (uint8_t *)&internal_freq_fine, 1);
*val = internal_freq_fine.freq_fine;
return ret;
@@ -1628,14 +1966,16 @@ int32_t ism330dhcx_mem_bank_set(stmdev_ctx_t *ctx,
{
ism330dhcx_func_cfg_access_t func_cfg_access;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
- if(ret == 0){
- func_cfg_access.reg_access= (uint8_t)val;
+ (uint8_t *)&func_cfg_access, 1);
+
+ if (ret == 0)
+ {
+ func_cfg_access.reg_access = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
+ (uint8_t *)&func_cfg_access, 1);
}
+
return ret;
}
@@ -1649,27 +1989,32 @@ int32_t ism330dhcx_mem_bank_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_mem_bank_get(stmdev_ctx_t *ctx,
- ism330dhcx_reg_access_t *val)
+ ism330dhcx_reg_access_t *val)
{
ism330dhcx_func_cfg_access_t func_cfg_access;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
- switch (func_cfg_access.reg_access){
+ (uint8_t *)&func_cfg_access, 1);
+
+ switch (func_cfg_access.reg_access)
+ {
case ISM330DHCX_USER_BANK:
*val = ISM330DHCX_USER_BANK;
break;
+
case ISM330DHCX_SENSOR_HUB_BANK:
*val = ISM330DHCX_SENSOR_HUB_BANK;
break;
+
case ISM330DHCX_EMBEDDED_FUNC_BANK:
*val = ISM330DHCX_EMBEDDED_FUNC_BANK;
break;
+
default:
*val = ISM330DHCX_USER_BANK;
break;
}
+
return ret;
}
@@ -1683,51 +2028,71 @@ int32_t ism330dhcx_mem_bank_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t add,
- uint8_t *val)
+ uint8_t *val)
{
ism330dhcx_page_rw_t page_rw;
ism330dhcx_page_sel_t page_sel;
ism330dhcx_page_address_t page_address;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW, (uint8_t*)&page_rw, 1);
- }
- if(ret == 0){
+
+ if (ret == 0)
+ {
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW,
+ (uint8_t *)&page_rw, 1);
+ }
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x02U; /* page_write enable */
- ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_RW, (uint8_t*)&page_rw, 1);
+ ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_RW,
+ (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
+ (uint8_t *)&page_sel, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU);
page_sel.not_used_01 = 1;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
+ (uint8_t *)&page_sel, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U));
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_ADDRESS,
- (uint8_t*)&page_address, 1);
+ (uint8_t *)&page_address, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_VALUE, val, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW,
- (uint8_t*)&page_rw, 1);
+ (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x00; /* page_write disable */
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_RW,
- (uint8_t*)&page_rw, 1);
+ (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -1737,7 +2102,7 @@ int32_t ism330dhcx_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t add,
* @param ctx Read / write interface definitions.(ptr)
* @param buf Page line address.(ptr)
* @param val Value to write.
- * @param len buffer lengh.
+ * @param len buffer length.
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
@@ -1750,71 +2115,99 @@ int32_t ism330dhcx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t add,
uint8_t msb, lsb;
int32_t ret;
uint8_t i ;
-
msb = (uint8_t)((add / 256U) & 0x0FU);
lsb = (uint8_t)(add - (msb * 256U));
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW, (uint8_t*)&page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW,
+ (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x02U; /* page_write enable*/
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_RW,
- (uint8_t*)&page_rw, 1);
+ (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
+ (uint8_t *)&page_sel, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_sel.page_sel = msb;
page_sel.not_used_01 = 1;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
+ (uint8_t *)&page_sel, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_address.page_addr = lsb;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_ADDRESS,
- (uint8_t*)&page_address, 1);
+ (uint8_t *)&page_address, 1);
}
- for (i = 0; i < len; i++){
- if(ret == 0){
+
+ for (i = 0; i < len; i++)
+ {
+ if (ret == 0)
+ {
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_VALUE, &buf[i], 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
/* Check if page wrap */
- if (lsb == 0x00U){
+ if (lsb == 0x00U)
+ {
msb++;
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
+ (uint8_t *)&page_sel, 1);
}
+
lsb++;
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_sel.page_sel = msb;
page_sel.not_used_01 = 1;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
+ (uint8_t *)&page_sel, 1);
}
}
}
- if(ret == 0){
+ if (ret == 0)
+ {
page_sel.page_sel = 0;
page_sel.not_used_01 = 1;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
+ (uint8_t *)&page_sel, 1);
}
- if(ret == 0){
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW, (uint8_t*)&page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW,
+ (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x00U; /* page_write disable */
- ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_RW, (uint8_t*)&page_rw, 1);
+ ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_RW,
+ (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -1828,50 +2221,71 @@ int32_t ism330dhcx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t add,
*
*/
int32_t ism330dhcx_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add,
- uint8_t *val)
+ uint8_t *val)
{
ism330dhcx_page_rw_t page_rw;
ism330dhcx_page_sel_t page_sel;
ism330dhcx_page_address_t page_address;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW, (uint8_t*)&page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW,
+ (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x01U; /* page_read enable*/
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_RW,
- (uint8_t*)&page_rw, 1);
+ (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
+ (uint8_t *)&page_sel, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU);
page_sel.not_used_01 = 1;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
+ (uint8_t *)&page_sel, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U));
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_ADDRESS,
- (uint8_t*)&page_address, 1);
+ (uint8_t *)&page_address, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_VALUE, val, 2);
}
- if(ret == 0){
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW, (uint8_t*)&page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW,
+ (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x00U; /* page_read disable */
- ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_RW, (uint8_t*)&page_rw, 1);
+ ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_RW,
+ (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -1885,18 +2299,20 @@ int32_t ism330dhcx_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add,
*
*/
int32_t ism330dhcx_data_ready_mode_set(stmdev_ctx_t *ctx,
- ism330dhcx_dataready_pulsed_t val)
+ ism330dhcx_dataready_pulsed_t val)
{
ism330dhcx_counter_bdr_reg1_t counter_bdr_reg1;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if(ret == 0){
- counter_bdr_reg1.dataready_pulsed= (uint8_t)val;
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
+ counter_bdr_reg1.dataready_pulsed = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
}
+
return ret;
}
@@ -1910,24 +2326,28 @@ int32_t ism330dhcx_data_ready_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_data_ready_mode_get(stmdev_ctx_t *ctx,
- ism330dhcx_dataready_pulsed_t *val)
+ ism330dhcx_dataready_pulsed_t *val)
{
ism330dhcx_counter_bdr_reg1_t counter_bdr_reg1;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- switch (counter_bdr_reg1.dataready_pulsed){
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ switch (counter_bdr_reg1.dataready_pulsed)
+ {
case ISM330DHCX_DRDY_LATCHED:
*val = ISM330DHCX_DRDY_LATCHED;
break;
+
case ISM330DHCX_DRDY_PULSED:
*val = ISM330DHCX_DRDY_PULSED;
break;
+
default:
*val = ISM330DHCX_DRDY_LATCHED;
break;
}
+
return ret;
}
@@ -1943,6 +2363,7 @@ int32_t ism330dhcx_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -1958,13 +2379,16 @@ int32_t ism330dhcx_reset_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_ctrl3_c_t ctrl3_c;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.sw_reset= (uint8_t)val;
+ if (ret == 0)
+ {
+ ctrl3_c.sw_reset = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL3_C,
- (uint8_t*)&ctrl3_c, 1);
+ (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1980,8 +2404,8 @@ int32_t ism330dhcx_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dhcx_ctrl3_c_t ctrl3_c;
int32_t ret;
-
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.sw_reset;
return ret;
@@ -2000,12 +2424,16 @@ int32_t ism330dhcx_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_ctrl3_c_t ctrl3_c;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.if_inc= (uint8_t)val;
- ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ if (ret == 0)
+ {
+ ctrl3_c.if_inc = (uint8_t)val;
+ ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -2022,8 +2450,8 @@ int32_t ism330dhcx_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dhcx_ctrl3_c_t ctrl3_c;
int32_t ret;
-
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.if_inc;
return ret;
@@ -2041,12 +2469,16 @@ int32_t ism330dhcx_boot_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_ctrl3_c_t ctrl3_c;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.boot= (uint8_t)val;
- ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ if (ret == 0)
+ {
+ ctrl3_c.boot = (uint8_t)val;
+ ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -2062,8 +2494,8 @@ int32_t ism330dhcx_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dhcx_ctrl3_c_t ctrl3_c;
int32_t ret;
-
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.boot;
return ret;
@@ -2080,16 +2512,20 @@ int32_t ism330dhcx_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t ism330dhcx_xl_self_test_set(stmdev_ctx_t *ctx,
- ism330dhcx_st_xl_t val)
+ ism330dhcx_st_xl_t val)
{
ism330dhcx_ctrl5_c_t ctrl5_c;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL5_C,
+ (uint8_t *)&ctrl5_c, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
- ctrl5_c.st_xl= (uint8_t)val;
- ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ if (ret == 0)
+ {
+ ctrl5_c.st_xl = (uint8_t)val;
+ ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL5_C,
+ (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -2102,27 +2538,32 @@ int32_t ism330dhcx_xl_self_test_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_xl_self_test_get(stmdev_ctx_t *ctx,
- ism330dhcx_st_xl_t *val)
+ ism330dhcx_st_xl_t *val)
{
ism330dhcx_ctrl5_c_t ctrl5_c;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL5_C,
+ (uint8_t *)&ctrl5_c, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
-
- switch (ctrl5_c.st_xl){
+ switch (ctrl5_c.st_xl)
+ {
case ISM330DHCX_XL_ST_DISABLE:
*val = ISM330DHCX_XL_ST_DISABLE;
break;
+
case ISM330DHCX_XL_ST_POSITIVE:
*val = ISM330DHCX_XL_ST_POSITIVE;
break;
+
case ISM330DHCX_XL_ST_NEGATIVE:
*val = ISM330DHCX_XL_ST_NEGATIVE;
break;
+
default:
*val = ISM330DHCX_XL_ST_DISABLE;
break;
}
+
return ret;
}
@@ -2135,16 +2576,20 @@ int32_t ism330dhcx_xl_self_test_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_gy_self_test_set(stmdev_ctx_t *ctx,
- ism330dhcx_st_g_t val)
+ ism330dhcx_st_g_t val)
{
ism330dhcx_ctrl5_c_t ctrl5_c;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL5_C,
+ (uint8_t *)&ctrl5_c, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
- ctrl5_c.st_g= (uint8_t)val;
- ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ if (ret == 0)
+ {
+ ctrl5_c.st_g = (uint8_t)val;
+ ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL5_C,
+ (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -2157,27 +2602,32 @@ int32_t ism330dhcx_gy_self_test_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_gy_self_test_get(stmdev_ctx_t *ctx,
- ism330dhcx_st_g_t *val)
+ ism330dhcx_st_g_t *val)
{
ism330dhcx_ctrl5_c_t ctrl5_c;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL5_C,
+ (uint8_t *)&ctrl5_c, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
-
- switch (ctrl5_c.st_g){
+ switch (ctrl5_c.st_g)
+ {
case ISM330DHCX_GY_ST_DISABLE:
*val = ISM330DHCX_GY_ST_DISABLE;
break;
+
case ISM330DHCX_GY_ST_POSITIVE:
*val = ISM330DHCX_GY_ST_POSITIVE;
break;
+
case ISM330DHCX_GY_ST_NEGATIVE:
*val = ISM330DHCX_GY_ST_NEGATIVE;
break;
+
default:
*val = ISM330DHCX_GY_ST_DISABLE;
break;
}
+
return ret;
}
@@ -2206,13 +2656,16 @@ int32_t ism330dhcx_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_ctrl1_xl_t ctrl1_xl;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
- ctrl1_xl.lpf2_xl_en= (uint8_t)val;
+ if (ret == 0)
+ {
+ ctrl1_xl.lpf2_xl_en = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
+ (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -2228,8 +2681,8 @@ int32_t ism330dhcx_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dhcx_ctrl1_xl_t ctrl1_xl;
int32_t ret;
-
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
*val = ctrl1_xl.lpf2_xl_en;
return ret;
@@ -2248,12 +2701,16 @@ int32_t ism330dhcx_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_ctrl4_c_t ctrl4_c;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ctrl4_c.lpf1_sel_g= (uint8_t)val;
- ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ if (ret == 0)
+ {
+ ctrl4_c.lpf1_sel_g = (uint8_t)val;
+ ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -2270,8 +2727,8 @@ int32_t ism330dhcx_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dhcx_ctrl4_c_t ctrl4_c;
int32_t ret;
-
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.lpf1_sel_g;
return ret;
@@ -2286,16 +2743,21 @@ int32_t ism330dhcx_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ism330dhcx_filter_settling_mask_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
ism330dhcx_ctrl4_c_t ctrl4_c;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ctrl4_c.drdy_mask= (uint8_t)val;
- ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ if (ret == 0)
+ {
+ ctrl4_c.drdy_mask = (uint8_t)val;
+ ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -2309,12 +2771,12 @@ int32_t ism330dhcx_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val)
*
*/
int32_t ism330dhcx_filter_settling_mask_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
ism330dhcx_ctrl4_c_t ctrl4_c;
int32_t ret;
-
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.drdy_mask;
return ret;
@@ -2329,16 +2791,20 @@ int32_t ism330dhcx_filter_settling_mask_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
- ism330dhcx_ftype_t val)
+ ism330dhcx_ftype_t val)
{
ism330dhcx_ctrl6_c_t ctrl6_c;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL6_C,
+ (uint8_t *)&ctrl6_c, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
- ctrl6_c.ftype= (uint8_t)val;
- ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ if (ret == 0)
+ {
+ ctrl6_c.ftype = (uint8_t)val;
+ ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL6_C,
+ (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -2351,42 +2817,52 @@ int32_t ism330dhcx_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
- ism330dhcx_ftype_t *val)
+ ism330dhcx_ftype_t *val)
{
ism330dhcx_ctrl6_c_t ctrl6_c;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL6_C,
+ (uint8_t *)&ctrl6_c, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
-
- switch (ctrl6_c.ftype){
+ switch (ctrl6_c.ftype)
+ {
case ISM330DHCX_ULTRA_LIGHT:
*val = ISM330DHCX_ULTRA_LIGHT;
break;
+
case ISM330DHCX_VERY_LIGHT:
*val = ISM330DHCX_VERY_LIGHT;
break;
+
case ISM330DHCX_LIGHT:
*val = ISM330DHCX_LIGHT;
break;
+
case ISM330DHCX_MEDIUM:
*val = ISM330DHCX_MEDIUM;
break;
+
case ISM330DHCX_STRONG:
*val = ISM330DHCX_STRONG;
break;
+
case ISM330DHCX_VERY_STRONG:
*val = ISM330DHCX_VERY_STRONG;
break;
+
case ISM330DHCX_AGGRESSIVE:
*val = ISM330DHCX_AGGRESSIVE;
break;
+
case ISM330DHCX_XTREME:
*val = ISM330DHCX_XTREME;
break;
+
default:
*val = ISM330DHCX_ULTRA_LIGHT;
break;
}
+
return ret;
}
@@ -2402,13 +2878,16 @@ int32_t ism330dhcx_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_ctrl8_xl_t ctrl8_xl;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
- ctrl8_xl.low_pass_on_6d= (uint8_t)val;
+ if (ret == 0)
+ {
+ ctrl8_xl.low_pass_on_6d = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL8_XL,
- (uint8_t*)&ctrl8_xl, 1);
+ (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -2424,8 +2903,8 @@ int32_t ism330dhcx_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dhcx_ctrl8_xl_t ctrl8_xl;
int32_t ret;
-
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
*val = ctrl8_xl.low_pass_on_6d;
return ret;
@@ -2441,19 +2920,22 @@ int32_t ism330dhcx_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t ism330dhcx_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
- ism330dhcx_hp_slope_xl_en_t val)
+ ism330dhcx_hp_slope_xl_en_t val)
{
ism330dhcx_ctrl8_xl_t ctrl8_xl;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl8_xl.hp_slope_xl_en = (((uint8_t)val & 0x10U) >> 4);
ctrl8_xl.hp_ref_mode_xl = (((uint8_t)val & 0x20U) >> 5);
ctrl8_xl.hpcf_xl = (uint8_t)val & 0x07U;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL8_XL,
- (uint8_t*)&ctrl8_xl, 1);
+ (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -2467,87 +2949,114 @@ int32_t ism330dhcx_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
- ism330dhcx_hp_slope_xl_en_t *val)
+ ism330dhcx_hp_slope_xl_en_t *val)
{
ism330dhcx_ctrl8_xl_t ctrl8_xl;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- switch (( (ctrl8_xl.hp_ref_mode_xl << 5) +(ctrl8_xl.hp_slope_xl_en << 4) +
- ctrl8_xl.hpcf_xl )){
+ switch (((ctrl8_xl.hp_ref_mode_xl << 5) + (ctrl8_xl.hp_slope_xl_en <<
+ 4) +
+ ctrl8_xl.hpcf_xl))
+ {
case ISM330DHCX_HP_PATH_DISABLE_ON_OUT:
*val = ISM330DHCX_HP_PATH_DISABLE_ON_OUT;
break;
+
case ISM330DHCX_SLOPE_ODR_DIV_4:
*val = ISM330DHCX_SLOPE_ODR_DIV_4;
break;
+
case ISM330DHCX_HP_ODR_DIV_10:
*val = ISM330DHCX_HP_ODR_DIV_10;
break;
+
case ISM330DHCX_HP_ODR_DIV_20:
*val = ISM330DHCX_HP_ODR_DIV_20;
break;
+
case ISM330DHCX_HP_ODR_DIV_45:
*val = ISM330DHCX_HP_ODR_DIV_45;
break;
+
case ISM330DHCX_HP_ODR_DIV_100:
*val = ISM330DHCX_HP_ODR_DIV_100;
break;
+
case ISM330DHCX_HP_ODR_DIV_200:
*val = ISM330DHCX_HP_ODR_DIV_200;
break;
+
case ISM330DHCX_HP_ODR_DIV_400:
*val = ISM330DHCX_HP_ODR_DIV_400;
break;
+
case ISM330DHCX_HP_ODR_DIV_800:
*val = ISM330DHCX_HP_ODR_DIV_800;
break;
+
case ISM330DHCX_HP_REF_MD_ODR_DIV_10:
*val = ISM330DHCX_HP_REF_MD_ODR_DIV_10;
break;
+
case ISM330DHCX_HP_REF_MD_ODR_DIV_20:
*val = ISM330DHCX_HP_REF_MD_ODR_DIV_20;
break;
+
case ISM330DHCX_HP_REF_MD_ODR_DIV_45:
*val = ISM330DHCX_HP_REF_MD_ODR_DIV_45;
break;
+
case ISM330DHCX_HP_REF_MD_ODR_DIV_100:
*val = ISM330DHCX_HP_REF_MD_ODR_DIV_100;
break;
+
case ISM330DHCX_HP_REF_MD_ODR_DIV_200:
*val = ISM330DHCX_HP_REF_MD_ODR_DIV_200;
break;
+
case ISM330DHCX_HP_REF_MD_ODR_DIV_400:
*val = ISM330DHCX_HP_REF_MD_ODR_DIV_400;
break;
+
case ISM330DHCX_HP_REF_MD_ODR_DIV_800:
*val = ISM330DHCX_HP_REF_MD_ODR_DIV_800;
break;
+
case ISM330DHCX_LP_ODR_DIV_10:
*val = ISM330DHCX_LP_ODR_DIV_10;
break;
+
case ISM330DHCX_LP_ODR_DIV_20:
*val = ISM330DHCX_LP_ODR_DIV_20;
break;
+
case ISM330DHCX_LP_ODR_DIV_45:
*val = ISM330DHCX_LP_ODR_DIV_45;
break;
+
case ISM330DHCX_LP_ODR_DIV_100:
*val = ISM330DHCX_LP_ODR_DIV_100;
break;
+
case ISM330DHCX_LP_ODR_DIV_200:
*val = ISM330DHCX_LP_ODR_DIV_200;
break;
+
case ISM330DHCX_LP_ODR_DIV_400:
*val = ISM330DHCX_LP_ODR_DIV_400;
break;
+
case ISM330DHCX_LP_ODR_DIV_800:
*val = ISM330DHCX_LP_ODR_DIV_800;
break;
+
default:
*val = ISM330DHCX_HP_PATH_DISABLE_ON_OUT;
break;
}
+
return ret;
}
@@ -2561,17 +3070,21 @@ int32_t ism330dhcx_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ism330dhcx_xl_fast_settling_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
ism330dhcx_ctrl8_xl_t ctrl8_xl;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
- ctrl8_xl.fastsettl_mode_xl= (uint8_t)val;
+ if (ret == 0)
+ {
+ ctrl8_xl.fastsettl_mode_xl = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL8_XL,
- (uint8_t*)&ctrl8_xl, 1);
+ (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -2585,12 +3098,13 @@ int32_t ism330dhcx_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dhcx_xl_fast_settling_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dhcx_ctrl8_xl_t ctrl8_xl;
int32_t ret;
-
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
*val = ctrl8_xl.fastsettl_mode_xl;
return ret;
@@ -2606,17 +3120,20 @@ int32_t ism330dhcx_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t ism330dhcx_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
- ism330dhcx_slope_fds_t val)
+ ism330dhcx_slope_fds_t val)
{
ism330dhcx_tap_cfg0_t tap_cfg0;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0,
+ (uint8_t *)&tap_cfg0, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
- if(ret == 0){
- tap_cfg0.slope_fds= (uint8_t)val;
+ if (ret == 0)
+ {
+ tap_cfg0.slope_fds = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_TAP_CFG0,
- (uint8_t*)&tap_cfg0, 1);
+ (uint8_t *)&tap_cfg0, 1);
}
+
return ret;
}
@@ -2630,23 +3147,28 @@ int32_t ism330dhcx_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
- ism330dhcx_slope_fds_t *val)
+ ism330dhcx_slope_fds_t *val)
{
ism330dhcx_tap_cfg0_t tap_cfg0;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0,
+ (uint8_t *)&tap_cfg0, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
- switch (tap_cfg0.slope_fds){
+ switch (tap_cfg0.slope_fds)
+ {
case ISM330DHCX_USE_SLOPE:
*val = ISM330DHCX_USE_SLOPE;
break;
+
case ISM330DHCX_USE_HPF:
*val = ISM330DHCX_USE_HPF;
break;
+
default:
*val = ISM330DHCX_USE_SLOPE;
break;
}
+
return ret;
}
@@ -2660,17 +3182,21 @@ int32_t ism330dhcx_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
- ism330dhcx_hpm_g_t val)
+ ism330dhcx_hpm_g_t val)
{
ism330dhcx_ctrl7_g_t ctrl7_g;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL7_G,
+ (uint8_t *)&ctrl7_g, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl7_g.hp_en_g = (((uint8_t)val & 0x80U) >> 7);
ctrl7_g.hpm_g = (uint8_t)val & 0x03U;
- ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL7_G,
+ (uint8_t *)&ctrl7_g, 1);
}
+
return ret;
}
@@ -2684,33 +3210,40 @@ int32_t ism330dhcx_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
- ism330dhcx_hpm_g_t *val)
+ ism330dhcx_hpm_g_t *val)
{
ism330dhcx_ctrl7_g_t ctrl7_g;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL7_G,
+ (uint8_t *)&ctrl7_g, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
-
- switch ((ctrl7_g.hp_en_g << 7) + ctrl7_g.hpm_g){
+ switch ((ctrl7_g.hp_en_g << 7) + ctrl7_g.hpm_g)
+ {
case ISM330DHCX_HP_FILTER_NONE:
*val = ISM330DHCX_HP_FILTER_NONE;
break;
+
case ISM330DHCX_HP_FILTER_16mHz:
*val = ISM330DHCX_HP_FILTER_16mHz;
break;
+
case ISM330DHCX_HP_FILTER_65mHz:
*val = ISM330DHCX_HP_FILTER_65mHz;
break;
+
case ISM330DHCX_HP_FILTER_260mHz:
*val = ISM330DHCX_HP_FILTER_260mHz;
break;
+
case ISM330DHCX_HP_FILTER_1Hz04:
*val = ISM330DHCX_HP_FILTER_1Hz04;
break;
+
default:
*val = ISM330DHCX_HP_FILTER_NONE;
break;
}
+
return ret;
}
@@ -2737,17 +3270,20 @@ int32_t ism330dhcx_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx,
- ism330dhcx_ois_pu_dis_t val)
+ ism330dhcx_ois_pu_dis_t val)
{
ism330dhcx_pin_ctrl_t pin_ctrl;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PIN_CTRL,
+ (uint8_t *)&pin_ctrl, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
- if(ret == 0){
- pin_ctrl.ois_pu_dis= (uint8_t)val;
+ if (ret == 0)
+ {
+ pin_ctrl.ois_pu_dis = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PIN_CTRL,
- (uint8_t*)&pin_ctrl, 1);
+ (uint8_t *)&pin_ctrl, 1);
}
+
return ret;
}
@@ -2761,24 +3297,28 @@ int32_t ism330dhcx_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx,
- ism330dhcx_ois_pu_dis_t *val)
+ ism330dhcx_ois_pu_dis_t *val)
{
ism330dhcx_pin_ctrl_t pin_ctrl;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PIN_CTRL,
+ (uint8_t *)&pin_ctrl, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
-
- switch (pin_ctrl.ois_pu_dis){
+ switch (pin_ctrl.ois_pu_dis)
+ {
case ISM330DHCX_AUX_PULL_UP_DISC:
*val = ISM330DHCX_AUX_PULL_UP_DISC;
break;
+
case ISM330DHCX_AUX_PULL_UP_CONNECT:
*val = ISM330DHCX_AUX_PULL_UP_CONNECT;
break;
+
default:
*val = ISM330DHCX_AUX_PULL_UP_DISC;
break;
}
+
return ret;
}
@@ -2791,17 +3331,21 @@ int32_t ism330dhcx_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx,
- ism330dhcx_ois_on_t val)
+ ism330dhcx_ois_on_t val)
{
ism330dhcx_ctrl7_g_t ctrl7_g;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL7_G,
+ (uint8_t *)&ctrl7_g, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl7_g.ois_on_en = (uint8_t)val & 0x01U;
ctrl7_g.ois_on = (uint8_t)val & 0x01U;
- ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL7_G,
+ (uint8_t *)&ctrl7_g, 1);
}
+
return ret;
}
@@ -2814,24 +3358,28 @@ int32_t ism330dhcx_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx,
- ism330dhcx_ois_on_t *val)
+ ism330dhcx_ois_on_t *val)
{
ism330dhcx_ctrl7_g_t ctrl7_g;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL7_G,
+ (uint8_t *)&ctrl7_g, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
-
- switch (ctrl7_g.ois_on){
+ switch (ctrl7_g.ois_on)
+ {
case ISM330DHCX_AUX_ON:
*val = ISM330DHCX_AUX_ON;
break;
+
case ISM330DHCX_AUX_ON_BY_AUX_INTERFACE:
*val = ISM330DHCX_AUX_ON_BY_AUX_INTERFACE;
break;
+
default:
*val = ISM330DHCX_AUX_ON;
break;
}
+
return ret;
}
@@ -2844,10 +3392,12 @@ int32_t ism330dhcx_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_aux_status_reg_get(stmdev_ctx_t *ctx,
- ism330dhcx_status_spiaux_t *val)
+ ism330dhcx_status_spiaux_t *val)
{
int32_t ret;
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_STATUS_SPIAUX, (uint8_t*)val, 1);
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_STATUS_SPIAUX,
+ (uint8_t *)val, 1);
+
return ret;
}
@@ -2860,13 +3410,12 @@ int32_t ism330dhcx_aux_status_reg_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
ism330dhcx_status_spiaux_t status_spiaux;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_STATUS_SPIAUX,
- (uint8_t*)&status_spiaux, 1);
+ (uint8_t *)&status_spiaux, 1);
*val = status_spiaux.xlda;
return ret;
@@ -2881,13 +3430,12 @@ int32_t ism330dhcx_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
ism330dhcx_status_spiaux_t status_spiaux;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_STATUS_SPIAUX,
- (uint8_t*)&status_spiaux, 1);
+ (uint8_t *)&status_spiaux, 1);
*val = status_spiaux.gda;
return ret;
@@ -2906,9 +3454,8 @@ int32_t ism330dhcx_aux_gy_flag_settling_get(stmdev_ctx_t *ctx,
{
ism330dhcx_status_spiaux_t status_spiaux;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_STATUS_SPIAUX,
- (uint8_t*)&status_spiaux, 1);
+ (uint8_t *)&status_spiaux, 1);
*val = status_spiaux.gyro_settling;
return ret;
@@ -2924,16 +3471,20 @@ int32_t ism330dhcx_aux_gy_flag_settling_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_aux_xl_self_test_set(stmdev_ctx_t *ctx,
- ism330dhcx_st_xl_ois_t val)
+ ism330dhcx_st_xl_ois_t val)
{
ism330dhcx_int_ois_t int_ois;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_OIS,
+ (uint8_t *)&int_ois, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_OIS, (uint8_t*)&int_ois, 1);
- if(ret == 0){
- int_ois.st_xl_ois= (uint8_t)val;
- ret = ism330dhcx_write_reg(ctx, ISM330DHCX_INT_OIS, (uint8_t*)&int_ois, 1);
+ if (ret == 0)
+ {
+ int_ois.st_xl_ois = (uint8_t)val;
+ ret = ism330dhcx_write_reg(ctx, ISM330DHCX_INT_OIS,
+ (uint8_t *)&int_ois, 1);
}
+
return ret;
}
@@ -2947,27 +3498,32 @@ int32_t ism330dhcx_aux_xl_self_test_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_aux_xl_self_test_get(stmdev_ctx_t *ctx,
- ism330dhcx_st_xl_ois_t *val)
+ ism330dhcx_st_xl_ois_t *val)
{
ism330dhcx_int_ois_t int_ois;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_OIS,
+ (uint8_t *)&int_ois, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_OIS, (uint8_t*)&int_ois, 1);
-
- switch (int_ois.st_xl_ois){
+ switch (int_ois.st_xl_ois)
+ {
case ISM330DHCX_AUX_XL_DISABLE:
*val = ISM330DHCX_AUX_XL_DISABLE;
break;
+
case ISM330DHCX_AUX_XL_POS:
*val = ISM330DHCX_AUX_XL_POS;
break;
+
case ISM330DHCX_AUX_XL_NEG:
*val = ISM330DHCX_AUX_XL_NEG;
break;
+
default:
*val = ISM330DHCX_AUX_XL_DISABLE;
break;
}
+
return ret;
}
@@ -2980,17 +3536,20 @@ int32_t ism330dhcx_aux_xl_self_test_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_aux_den_polarity_set(stmdev_ctx_t *ctx,
- ism330dhcx_den_lh_ois_t val)
+ ism330dhcx_den_lh_ois_t val)
{
ism330dhcx_int_ois_t int_ois;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_OIS,
+ (uint8_t *)&int_ois, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_OIS, (uint8_t*)&int_ois, 1);
- if(ret == 0){
- int_ois.den_lh_ois= (uint8_t)val;
+ if (ret == 0)
+ {
+ int_ois.den_lh_ois = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_INT_OIS,
- (uint8_t*)&int_ois, 1);
+ (uint8_t *)&int_ois, 1);
}
+
return ret;
}
@@ -3003,24 +3562,28 @@ int32_t ism330dhcx_aux_den_polarity_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_aux_den_polarity_get(stmdev_ctx_t *ctx,
- ism330dhcx_den_lh_ois_t *val)
+ ism330dhcx_den_lh_ois_t *val)
{
ism330dhcx_int_ois_t int_ois;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_OIS,
+ (uint8_t *)&int_ois, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_OIS, (uint8_t*)&int_ois, 1);
-
- switch (int_ois.den_lh_ois){
+ switch (int_ois.den_lh_ois)
+ {
case ISM330DHCX_AUX_DEN_ACTIVE_LOW:
*val = ISM330DHCX_AUX_DEN_ACTIVE_LOW;
break;
+
case ISM330DHCX_AUX_DEN_ACTIVE_HIGH:
*val = ISM330DHCX_AUX_DEN_ACTIVE_HIGH;
break;
+
default:
*val = ISM330DHCX_AUX_DEN_ACTIVE_LOW;
break;
}
+
return ret;
}
@@ -3033,27 +3596,34 @@ int32_t ism330dhcx_aux_den_polarity_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_aux_den_mode_set(stmdev_ctx_t *ctx,
- ism330dhcx_lvl2_ois_t val)
+ ism330dhcx_lvl2_ois_t val)
{
ism330dhcx_int_ois_t int_ois;
ism330dhcx_ctrl1_ois_t ctrl1_ois;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_OIS,
+ (uint8_t *)&int_ois, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_OIS, (uint8_t*)&int_ois, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
int_ois.lvl2_ois = (uint8_t)val & 0x01U;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_INT_OIS,
- (uint8_t*)&int_ois, 1);
+ (uint8_t *)&int_ois, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ctrl1_ois.lvl1_ois = ((uint8_t)val & 0x02U) >> 1;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
}
+
return ret;
}
@@ -3066,32 +3636,39 @@ int32_t ism330dhcx_aux_den_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_aux_den_mode_get(stmdev_ctx_t *ctx,
- ism330dhcx_lvl2_ois_t *val)
+ ism330dhcx_lvl2_ois_t *val)
{
ism330dhcx_int_ois_t int_ois;
ism330dhcx_ctrl1_ois_t ctrl1_ois;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_OIS,
+ (uint8_t *)&int_ois, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_OIS, (uint8_t*)&int_ois, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
}
- switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois){
+ switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois)
+ {
case ISM330DHCX_AUX_DEN_DISABLE:
*val = ISM330DHCX_AUX_DEN_DISABLE;
break;
+
case ISM330DHCX_AUX_DEN_LEVEL_LATCH:
*val = ISM330DHCX_AUX_DEN_LEVEL_LATCH;
break;
+
case ISM330DHCX_AUX_DEN_LEVEL_TRIG:
*val = ISM330DHCX_AUX_DEN_LEVEL_TRIG;
break;
+
default:
*val = ISM330DHCX_AUX_DEN_DISABLE;
break;
}
+
return ret;
}
@@ -3104,16 +3681,21 @@ int32_t ism330dhcx_aux_den_mode_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ism330dhcx_aux_drdy_on_int2_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
ism330dhcx_int_ois_t int_ois;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_OIS,
+ (uint8_t *)&int_ois, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_OIS, (uint8_t*)&int_ois, 1);
- if(ret == 0){
- int_ois.int2_drdy_ois= (uint8_t)val;
- ret = ism330dhcx_write_reg(ctx, ISM330DHCX_INT_OIS, (uint8_t*)&int_ois, 1);
+ if (ret == 0)
+ {
+ int_ois.int2_drdy_ois = (uint8_t)val;
+ ret = ism330dhcx_write_reg(ctx, ISM330DHCX_INT_OIS,
+ (uint8_t *)&int_ois, 1);
}
+
return ret;
}
@@ -3126,12 +3708,13 @@ int32_t ism330dhcx_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dhcx_aux_drdy_on_int2_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dhcx_int_ois_t int_ois;
int32_t ret;
-
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_OIS, (uint8_t*)&int_ois, 1);
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_OIS,
+ (uint8_t *)&int_ois, 1);
*val = int_ois.int2_drdy_ois;
return ret;
@@ -3151,19 +3734,21 @@ int32_t ism330dhcx_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t ism330dhcx_aux_mode_set(stmdev_ctx_t *ctx,
- ism330dhcx_ois_en_spi2_t val)
+ ism330dhcx_ois_en_spi2_t val)
{
ism330dhcx_ctrl1_ois_t ctrl1_ois;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl1_ois, 1);
+
+ if (ret == 0)
+ {
ctrl1_ois.ois_en_spi2 = (uint8_t)val & 0x01U;
ctrl1_ois.mode4_en = ((uint8_t)val & 0x02U) >> 1;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
}
+
return ret;
}
@@ -3186,24 +3771,28 @@ int32_t ism330dhcx_aux_mode_get(stmdev_ctx_t *ctx,
{
ism330dhcx_ctrl1_ois_t ctrl1_ois;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
- switch (((ctrl1_ois.mode4_en << 1) + ctrl1_ois.ois_en_spi2)){
+ switch (((ctrl1_ois.mode4_en << 1) + ctrl1_ois.ois_en_spi2))
+ {
case ISM330DHCX_AUX_DISABLE:
*val = ISM330DHCX_AUX_DISABLE;
break;
+
case ISM330DHCX_MODE_3_GY:
*val = ISM330DHCX_MODE_3_GY;
break;
+
case ISM330DHCX_MODE_4_GY_XL:
*val = ISM330DHCX_MODE_4_GY_XL;
break;
+
default:
*val = ISM330DHCX_AUX_DISABLE;
break;
}
+
return ret;
}
@@ -3216,19 +3805,21 @@ int32_t ism330dhcx_aux_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_aux_gy_full_scale_set(stmdev_ctx_t *ctx,
- ism330dhcx_fs_g_ois_t val)
+ ism330dhcx_fs_g_ois_t val)
{
ism330dhcx_ctrl1_ois_t ctrl1_ois;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl1_ois, 1);
+
+ if (ret == 0)
+ {
ctrl1_ois.fs_g_ois = (uint8_t)val & 0x03U;
- ctrl1_ois.fs_125_ois = ( (uint8_t)val & 0x04U ) >> 2;
+ ctrl1_ois.fs_125_ois = ((uint8_t)val & 0x04U) >> 2;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
}
+
return ret;
}
@@ -3245,30 +3836,36 @@ int32_t ism330dhcx_aux_gy_full_scale_get(stmdev_ctx_t *ctx,
{
ism330dhcx_ctrl1_ois_t ctrl1_ois;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
- switch ( ( ctrl1_ois.fs_125_ois << 2 ) + ctrl1_ois.fs_g_ois ){
+ switch ((ctrl1_ois.fs_125_ois << 2) + ctrl1_ois.fs_g_ois)
+ {
case ISM330DHCX_250dps_AUX:
*val = ISM330DHCX_250dps_AUX;
break;
+
case ISM330DHCX_125dps_AUX:
*val = ISM330DHCX_125dps_AUX;
break;
+
case ISM330DHCX_500dps_AUX:
*val = ISM330DHCX_500dps_AUX;
break;
+
case ISM330DHCX_1000dps_AUX:
*val = ISM330DHCX_1000dps_AUX;
break;
+
case ISM330DHCX_2000dps_AUX:
*val = ISM330DHCX_2000dps_AUX;
break;
+
default:
*val = ISM330DHCX_250dps_AUX;
break;
}
+
return ret;
}
@@ -3281,18 +3878,20 @@ int32_t ism330dhcx_aux_gy_full_scale_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_aux_spi_mode_set(stmdev_ctx_t *ctx,
- ism330dhcx_sim_ois_t val)
+ ism330dhcx_sim_ois_t val)
{
ism330dhcx_ctrl1_ois_t ctrl1_ois;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
- if(ret == 0){
- ctrl1_ois.sim_ois= (uint8_t)val;
+ (uint8_t *)&ctrl1_ois, 1);
+
+ if (ret == 0)
+ {
+ ctrl1_ois.sim_ois = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
}
+
return ret;
}
@@ -3305,25 +3904,28 @@ int32_t ism330dhcx_aux_spi_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_aux_spi_mode_get(stmdev_ctx_t *ctx,
- ism330dhcx_sim_ois_t *val)
+ ism330dhcx_sim_ois_t *val)
{
ism330dhcx_ctrl1_ois_t ctrl1_ois;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
- switch (ctrl1_ois.sim_ois){
+ switch (ctrl1_ois.sim_ois)
+ {
case ISM330DHCX_AUX_SPI_4_WIRE:
*val = ISM330DHCX_AUX_SPI_4_WIRE;
break;
+
case ISM330DHCX_AUX_SPI_3_WIRE:
*val = ISM330DHCX_AUX_SPI_3_WIRE;
break;
+
default:
*val = ISM330DHCX_AUX_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -3336,18 +3938,20 @@ int32_t ism330dhcx_aux_spi_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
- ism330dhcx_ftype_ois_t val)
+ ism330dhcx_ftype_ois_t val)
{
ism330dhcx_ctrl2_ois_t ctrl2_ois;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL2_OIS,
- (uint8_t*)&ctrl2_ois, 1);
- if(ret == 0){
- ctrl2_ois.ftype_ois= (uint8_t)val;
+ (uint8_t *)&ctrl2_ois, 1);
+
+ if (ret == 0)
+ {
+ ctrl2_ois.ftype_ois = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL2_OIS,
- (uint8_t*)&ctrl2_ois, 1);
+ (uint8_t *)&ctrl2_ois, 1);
}
+
return ret;
}
@@ -3360,31 +3964,36 @@ int32_t ism330dhcx_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
- ism330dhcx_ftype_ois_t *val)
+ ism330dhcx_ftype_ois_t *val)
{
ism330dhcx_ctrl2_ois_t ctrl2_ois;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL2_OIS,
- (uint8_t*)&ctrl2_ois, 1);
+ (uint8_t *)&ctrl2_ois, 1);
- switch (ctrl2_ois.ftype_ois){
+ switch (ctrl2_ois.ftype_ois)
+ {
case ISM330DHCX_351Hz39:
*val = ISM330DHCX_351Hz39;
break;
+
case ISM330DHCX_236Hz63:
*val = ISM330DHCX_236Hz63;
break;
+
case ISM330DHCX_172Hz70:
*val = ISM330DHCX_172Hz70;
break;
+
case ISM330DHCX_937Hz91:
*val = ISM330DHCX_937Hz91;
break;
+
default:
*val = ISM330DHCX_351Hz39;
break;
}
+
return ret;
}
@@ -3401,15 +4010,17 @@ int32_t ism330dhcx_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx,
{
ism330dhcx_ctrl2_ois_t ctrl2_ois;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL2_OIS,
- (uint8_t*)&ctrl2_ois, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl2_ois, 1);
+
+ if (ret == 0)
+ {
ctrl2_ois.hpm_ois = (uint8_t)val & 0x03U;
ctrl2_ois.hp_en_ois = ((uint8_t)val & 0x10U) >> 4;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL2_OIS,
- (uint8_t*)&ctrl2_ois, 1);
+ (uint8_t *)&ctrl2_ois, 1);
}
+
return ret;
}
@@ -3426,30 +4037,36 @@ int32_t ism330dhcx_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx,
{
ism330dhcx_ctrl2_ois_t ctrl2_ois;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL2_OIS,
- (uint8_t*)&ctrl2_ois, 1);
+ (uint8_t *)&ctrl2_ois, 1);
- switch ((ctrl2_ois.hp_en_ois << 4) + ctrl2_ois.hpm_ois){
+ switch ((ctrl2_ois.hp_en_ois << 4) + ctrl2_ois.hpm_ois)
+ {
case ISM330DHCX_AUX_HP_DISABLE:
*val = ISM330DHCX_AUX_HP_DISABLE;
break;
+
case ISM330DHCX_AUX_HP_Hz016:
*val = ISM330DHCX_AUX_HP_Hz016;
break;
+
case ISM330DHCX_AUX_HP_Hz065:
*val = ISM330DHCX_AUX_HP_Hz065;
break;
+
case ISM330DHCX_AUX_HP_Hz260:
*val = ISM330DHCX_AUX_HP_Hz260;
break;
+
case ISM330DHCX_AUX_HP_1Hz040:
*val = ISM330DHCX_AUX_HP_1Hz040;
break;
+
default:
*val = ISM330DHCX_AUX_HP_DISABLE;
break;
}
+
return ret;
}
@@ -3468,14 +4085,16 @@ int32_t ism330dhcx_aux_gy_clamp_set(stmdev_ctx_t *ctx,
{
ism330dhcx_ctrl3_ois_t ctrl3_ois;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_OIS,
- (uint8_t*)&ctrl3_ois, 1);
- if(ret == 0){
- ctrl3_ois.st_ois_clampdis= (uint8_t)val;
+ (uint8_t *)&ctrl3_ois, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_ois.st_ois_clampdis = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL3_OIS,
- (uint8_t*)&ctrl3_ois, 1);
+ (uint8_t *)&ctrl3_ois, 1);
}
+
return ret;
}
@@ -3490,25 +4109,28 @@ int32_t ism330dhcx_aux_gy_clamp_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_aux_gy_clamp_get(stmdev_ctx_t *ctx,
- ism330dhcx_st_ois_clampdis_t *val)
+ ism330dhcx_st_ois_clampdis_t *val)
{
ism330dhcx_ctrl3_ois_t ctrl3_ois;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_OIS,
- (uint8_t*)&ctrl3_ois, 1);
+ (uint8_t *)&ctrl3_ois, 1);
- switch (ctrl3_ois.st_ois_clampdis){
+ switch (ctrl3_ois.st_ois_clampdis)
+ {
case ISM330DHCX_ENABLE_CLAMP:
*val = ISM330DHCX_ENABLE_CLAMP;
break;
+
case ISM330DHCX_DISABLE_CLAMP:
*val = ISM330DHCX_DISABLE_CLAMP;
break;
+
default:
*val = ISM330DHCX_ENABLE_CLAMP;
break;
}
+
return ret;
}
@@ -3521,18 +4143,20 @@ int32_t ism330dhcx_aux_gy_clamp_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_aux_gy_self_test_set(stmdev_ctx_t *ctx,
- ism330dhcx_st_ois_t val)
+ ism330dhcx_st_ois_t val)
{
ism330dhcx_ctrl3_ois_t ctrl3_ois;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_OIS,
- (uint8_t*)&ctrl3_ois, 1);
- if(ret == 0){
- ctrl3_ois.st_ois= (uint8_t)val;
+ (uint8_t *)&ctrl3_ois, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_ois.st_ois = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL3_OIS,
- (uint8_t*)&ctrl3_ois, 1);
+ (uint8_t *)&ctrl3_ois, 1);
}
+
return ret;
}
@@ -3545,28 +4169,32 @@ int32_t ism330dhcx_aux_gy_self_test_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_aux_gy_self_test_get(stmdev_ctx_t *ctx,
- ism330dhcx_st_ois_t *val)
+ ism330dhcx_st_ois_t *val)
{
ism330dhcx_ctrl3_ois_t ctrl3_ois;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_OIS,
- (uint8_t*)&ctrl3_ois, 1);
+ (uint8_t *)&ctrl3_ois, 1);
- switch (ctrl3_ois.st_ois){
+ switch (ctrl3_ois.st_ois)
+ {
case ISM330DHCX_AUX_GY_DISABLE:
*val = ISM330DHCX_AUX_GY_DISABLE;
break;
+
case ISM330DHCX_AUX_GY_POS:
*val = ISM330DHCX_AUX_GY_POS;
break;
+
case ISM330DHCX_AUX_GY_NEG:
*val = ISM330DHCX_AUX_GY_NEG;
break;
+
default:
*val = ISM330DHCX_AUX_GY_DISABLE;
break;
}
+
return ret;
}
@@ -3583,14 +4211,16 @@ int32_t ism330dhcx_aux_xl_bandwidth_set(stmdev_ctx_t *ctx,
{
ism330dhcx_ctrl3_ois_t ctrl3_ois;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_OIS,
- (uint8_t*)&ctrl3_ois, 1);
- if(ret == 0){
- ctrl3_ois.filter_xl_conf_ois= (uint8_t)val;
+ (uint8_t *)&ctrl3_ois, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_ois.filter_xl_conf_ois = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL3_OIS,
- (uint8_t*)&ctrl3_ois, 1);
+ (uint8_t *)&ctrl3_ois, 1);
}
+
return ret;
}
@@ -3607,39 +4237,48 @@ int32_t ism330dhcx_aux_xl_bandwidth_get(stmdev_ctx_t *ctx,
{
ism330dhcx_ctrl3_ois_t ctrl3_ois;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_OIS,
- (uint8_t*)&ctrl3_ois, 1);
+ (uint8_t *)&ctrl3_ois, 1);
- switch (ctrl3_ois.filter_xl_conf_ois){
+ switch (ctrl3_ois.filter_xl_conf_ois)
+ {
case ISM330DHCX_631Hz:
*val = ISM330DHCX_631Hz;
break;
+
case ISM330DHCX_295Hz:
*val = ISM330DHCX_295Hz;
break;
+
case ISM330DHCX_140Hz:
*val = ISM330DHCX_140Hz;
break;
+
case ISM330DHCX_68Hz2:
*val = ISM330DHCX_68Hz2;
break;
+
case ISM330DHCX_33Hz6:
*val = ISM330DHCX_33Hz6;
break;
+
case ISM330DHCX_16Hz7:
*val = ISM330DHCX_16Hz7;
break;
+
case ISM330DHCX_8Hz3:
*val = ISM330DHCX_8Hz3;
break;
+
case ISM330DHCX_4Hz11:
*val = ISM330DHCX_4Hz11;
break;
+
default:
*val = ISM330DHCX_631Hz;
break;
}
+
return ret;
}
@@ -3652,18 +4291,20 @@ int32_t ism330dhcx_aux_xl_bandwidth_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_aux_xl_full_scale_set(stmdev_ctx_t *ctx,
- ism330dhcx_fs_xl_ois_t val)
+ ism330dhcx_fs_xl_ois_t val)
{
ism330dhcx_ctrl3_ois_t ctrl3_ois;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_OIS,
- (uint8_t*)&ctrl3_ois, 1);
- if(ret == 0){
- ctrl3_ois.fs_xl_ois= (uint8_t)val;
+ (uint8_t *)&ctrl3_ois, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_ois.fs_xl_ois = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL3_OIS,
- (uint8_t*)&ctrl3_ois, 1);
+ (uint8_t *)&ctrl3_ois, 1);
}
+
return ret;
}
@@ -3676,31 +4317,36 @@ int32_t ism330dhcx_aux_xl_full_scale_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_aux_xl_full_scale_get(stmdev_ctx_t *ctx,
- ism330dhcx_fs_xl_ois_t *val)
+ ism330dhcx_fs_xl_ois_t *val)
{
ism330dhcx_ctrl3_ois_t ctrl3_ois;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_OIS,
- (uint8_t*)&ctrl3_ois, 1);
+ (uint8_t *)&ctrl3_ois, 1);
- switch (ctrl3_ois.fs_xl_ois){
+ switch (ctrl3_ois.fs_xl_ois)
+ {
case ISM330DHCX_AUX_2g:
*val = ISM330DHCX_AUX_2g;
break;
+
case ISM330DHCX_AUX_16g:
*val = ISM330DHCX_AUX_16g;
break;
+
case ISM330DHCX_AUX_4g:
*val = ISM330DHCX_AUX_4g;
break;
+
case ISM330DHCX_AUX_8g:
*val = ISM330DHCX_AUX_8g;
break;
+
default:
*val = ISM330DHCX_AUX_2g;
break;
}
+
return ret;
}
@@ -3730,14 +4376,16 @@ int32_t ism330dhcx_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
{
ism330dhcx_pin_ctrl_t pin_ctrl;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PIN_CTRL,
- (uint8_t*)&pin_ctrl, 1);
- if(ret == 0){
- pin_ctrl.sdo_pu_en= (uint8_t)val;
+ (uint8_t *)&pin_ctrl, 1);
+
+ if (ret == 0)
+ {
+ pin_ctrl.sdo_pu_en = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PIN_CTRL,
- (uint8_t*)&pin_ctrl, 1);
+ (uint8_t *)&pin_ctrl, 1);
}
+
return ret;
}
@@ -3750,25 +4398,28 @@ int32_t ism330dhcx_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
- ism330dhcx_sdo_pu_en_t *val)
+ ism330dhcx_sdo_pu_en_t *val)
{
ism330dhcx_pin_ctrl_t pin_ctrl;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PIN_CTRL,
- (uint8_t*)&pin_ctrl, 1);
+ (uint8_t *)&pin_ctrl, 1);
- switch (pin_ctrl.sdo_pu_en){
+ switch (pin_ctrl.sdo_pu_en)
+ {
case ISM330DHCX_PULL_UP_DISC:
*val = ISM330DHCX_PULL_UP_DISC;
break;
+
case ISM330DHCX_PULL_UP_CONNECT:
*val = ISM330DHCX_PULL_UP_CONNECT;
break;
+
default:
*val = ISM330DHCX_PULL_UP_DISC;
break;
}
+
return ret;
}
@@ -3780,17 +4431,21 @@ int32_t ism330dhcx_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_spi_mode_set(stmdev_ctx_t *ctx, ism330dhcx_sim_t val)
+int32_t ism330dhcx_spi_mode_set(stmdev_ctx_t *ctx,
+ ism330dhcx_sim_t val)
{
ism330dhcx_ctrl3_c_t ctrl3_c;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.sim= (uint8_t)val;
+ if (ret == 0)
+ {
+ ctrl3_c.sim = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL3_C,
- (uint8_t*)&ctrl3_c, 1);
+ (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -3802,24 +4457,29 @@ int32_t ism330dhcx_spi_mode_set(stmdev_ctx_t *ctx, ism330dhcx_sim_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_spi_mode_get(stmdev_ctx_t *ctx, ism330dhcx_sim_t *val)
+int32_t ism330dhcx_spi_mode_get(stmdev_ctx_t *ctx,
+ ism330dhcx_sim_t *val)
{
ism330dhcx_ctrl3_c_t ctrl3_c;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
-
- switch (ctrl3_c.sim){
+ switch (ctrl3_c.sim)
+ {
case ISM330DHCX_SPI_4_WIRE:
*val = ISM330DHCX_SPI_4_WIRE;
break;
+
case ISM330DHCX_SPI_3_WIRE:
*val = ISM330DHCX_SPI_3_WIRE;
break;
+
default:
*val = ISM330DHCX_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -3832,17 +4492,20 @@ int32_t ism330dhcx_spi_mode_get(stmdev_ctx_t *ctx, ism330dhcx_sim_t *val)
*
*/
int32_t ism330dhcx_i2c_interface_set(stmdev_ctx_t *ctx,
- ism330dhcx_i2c_disable_t val)
+ ism330dhcx_i2c_disable_t val)
{
ism330dhcx_ctrl4_c_t ctrl4_c;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ctrl4_c.i2c_disable= (uint8_t)val;
+ if (ret == 0)
+ {
+ ctrl4_c.i2c_disable = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL4_C,
- (uint8_t*)&ctrl4_c, 1);
+ (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -3855,24 +4518,28 @@ int32_t ism330dhcx_i2c_interface_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_i2c_interface_get(stmdev_ctx_t *ctx,
- ism330dhcx_i2c_disable_t *val)
+ ism330dhcx_i2c_disable_t *val)
{
ism330dhcx_ctrl4_c_t ctrl4_c;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
-
- switch (ctrl4_c.i2c_disable){
+ switch (ctrl4_c.i2c_disable)
+ {
case ISM330DHCX_I2C_ENABLE:
*val = ISM330DHCX_I2C_ENABLE;
break;
+
case ISM330DHCX_I2C_DISABLE:
*val = ISM330DHCX_I2C_DISABLE;
break;
+
default:
*val = ISM330DHCX_I2C_ENABLE;
break;
}
+
return ret;
}
@@ -3884,7 +4551,7 @@ int32_t ism330dhcx_i2c_interface_get(stmdev_ctx_t *ctx,
/**
* @defgroup ISM330DHCX_interrupt_pins
* @brief This section groups all the functions that manage
- * interrup pins
+ * interrupt pins
* @{
*
*/
@@ -3899,32 +4566,43 @@ int32_t ism330dhcx_i2c_interface_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_pin_int1_route_set(stmdev_ctx_t *ctx,
- ism330dhcx_pin_int1_route_t *val)
+ ism330dhcx_pin_int1_route_t *val)
{
ism330dhcx_tap_cfg2_t tap_cfg2;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_MLC_INT1,
- (uint8_t*)&val->mlc_int1, 1);
+ (uint8_t *)&val->mlc_int1, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_INT1,
- (uint8_t*)&val->emb_func_int1, 1);
+ (uint8_t *)&val->emb_func_int1, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FSM_INT1_A,
- (uint8_t*)&val->fsm_int1_a, 1);
+ (uint8_t *)&val->fsm_int1_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FSM_INT1_B,
- (uint8_t*)&val->fsm_int1_b, 1);
+ (uint8_t *)&val->fsm_int1_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
if ((val->emb_func_int1.int1_fsm_lc |
val->emb_func_int1.int1_sig_mot |
val->emb_func_int1.int1_step_detector |
@@ -3952,22 +4630,31 @@ int32_t ism330dhcx_pin_int1_route_set(stmdev_ctx_t *ctx,
val->mlc_int1.int1_mlc5 |
val->mlc_int1.int1_mlc6 |
val->mlc_int1.int1_mlc7 |
- val->mlc_int1.int1_mlc8) != PROPERTY_DISABLE){
+ val->mlc_int1.int1_mlc8) != PROPERTY_DISABLE)
+ {
val->md1_cfg.int1_emb_func = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
val->md1_cfg.int1_emb_func = PROPERTY_DISABLE;
}
- ret = ism330dhcx_write_reg(ctx, ISM330DHCX_INT1_CTRL,
- (uint8_t*)&val->int1_ctrl, 1);
+
+ ret = ism330dhcx_write_reg(ctx, ISM330DHCX_INT1_CTRL,
+ (uint8_t *)&val->int1_ctrl, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_MD1_CFG,
- (uint8_t*)&val->md1_cfg, 1);
+ (uint8_t *)&val->md1_cfg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG2,
- (uint8_t*)&tap_cfg2, 1);
+ (uint8_t *)&tap_cfg2, 1);
+
if ((val->int1_ctrl.den_drdy_flag |
val->int1_ctrl.int1_boot |
val->int1_ctrl.int1_cnt_bdr |
@@ -3982,17 +4669,23 @@ int32_t ism330dhcx_pin_int1_route_set(stmdev_ctx_t *ctx,
val->md1_cfg.int1_ff |
val->md1_cfg.int1_wu |
val->md1_cfg.int1_single_tap |
- val->md1_cfg.int1_sleep_change)!= PROPERTY_DISABLE){
+ val->md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
+ {
tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
}
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_TAP_CFG2,
- (uint8_t*)&tap_cfg2, 1);
+ (uint8_t *)&tap_cfg2, 1);
}
+
return ret;
}
@@ -4006,38 +4699,52 @@ int32_t ism330dhcx_pin_int1_route_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_pin_int1_route_get(stmdev_ctx_t *ctx,
- ism330dhcx_pin_int1_route_t *val)
+ ism330dhcx_pin_int1_route_t *val)
{
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MLC_INT1,
- (uint8_t*)&val->mlc_int1, 1);
+ (uint8_t *)&val->mlc_int1, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_INT1,
- (uint8_t*)&val->emb_func_int1, 1);
+ (uint8_t *)&val->emb_func_int1, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FSM_INT1_A,
- (uint8_t*)&val->fsm_int1_a, 1);
+ (uint8_t *)&val->fsm_int1_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FSM_INT1_B,
- (uint8_t*)&val->fsm_int1_b, 1);
+ (uint8_t *)&val->fsm_int1_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT1_CTRL,
- (uint8_t*)&val->int1_ctrl, 1);
+ (uint8_t *)&val->int1_ctrl, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MD1_CFG,
- (uint8_t*)&val->md1_cfg, 1);
+ (uint8_t *)&val->md1_cfg, 1);
}
+
return ret;
}
@@ -4051,32 +4758,43 @@ int32_t ism330dhcx_pin_int1_route_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_pin_int2_route_set(stmdev_ctx_t *ctx,
- ism330dhcx_pin_int2_route_t *val)
+ ism330dhcx_pin_int2_route_t *val)
{
ism330dhcx_tap_cfg2_t tap_cfg2;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_MLC_INT2,
- (uint8_t*)&val->mlc_int2, 1);
+ (uint8_t *)&val->mlc_int2, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_INT2,
- (uint8_t*)&val->emb_func_int2, 1);
+ (uint8_t *)&val->emb_func_int2, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FSM_INT2_A,
- (uint8_t*)&val->fsm_int2_a, 1);
+ (uint8_t *)&val->fsm_int2_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FSM_INT2_B,
- (uint8_t*)&val->fsm_int2_b, 1);
+ (uint8_t *)&val->fsm_int2_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
if ((val->emb_func_int2.int2_step_detector |
val->emb_func_int2.int2_tilt |
val->emb_func_int2.int2_sig_mot |
@@ -4104,24 +4822,34 @@ int32_t ism330dhcx_pin_int2_route_set(stmdev_ctx_t *ctx,
val->mlc_int2.int2_mlc5 |
val->mlc_int2.int2_mlc6 |
val->mlc_int2.int2_mlc7 |
- val->mlc_int2.int2_mlc8) != PROPERTY_DISABLE){
+ val->mlc_int2.int2_mlc8) != PROPERTY_DISABLE)
+ {
val->md2_cfg.int2_emb_func = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
val->md2_cfg.int2_emb_func = PROPERTY_DISABLE;
}
- ret = ism330dhcx_write_reg(ctx, ISM330DHCX_INT2_CTRL,
- (uint8_t*)&val->int2_ctrl, 1);
+
+ ret = ism330dhcx_write_reg(ctx, ISM330DHCX_INT2_CTRL,
+ (uint8_t *)&val->int2_ctrl, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_MD2_CFG,
- (uint8_t*)&val->md2_cfg, 1);
+ (uint8_t *)&val->md2_cfg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG2,
- (uint8_t*)&tap_cfg2, 1);
+ (uint8_t *)&tap_cfg2, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
if ((val->int2_ctrl.int2_drdy_xl |
val->int2_ctrl.int2_drdy_g |
val->int2_ctrl.int2_drdy_temp |
@@ -4134,15 +4862,20 @@ int32_t ism330dhcx_pin_int2_route_set(stmdev_ctx_t *ctx,
val->md2_cfg.int2_ff |
val->md2_cfg.int2_wu |
val->md2_cfg.int2_single_tap |
- val->md2_cfg.int2_sleep_change) != PROPERTY_DISABLE){
+ val->md2_cfg.int2_sleep_change) != PROPERTY_DISABLE)
+ {
tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
}
+
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_TAP_CFG2,
- (uint8_t*)&tap_cfg2, 1);
+ (uint8_t *)&tap_cfg2, 1);
}
+
return ret;
}
@@ -4156,38 +4889,52 @@ int32_t ism330dhcx_pin_int2_route_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_pin_int2_route_get(stmdev_ctx_t *ctx,
- ism330dhcx_pin_int2_route_t *val)
+ ism330dhcx_pin_int2_route_t *val)
{
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MLC_INT2,
- (uint8_t*)&val->mlc_int2, 1);
+
+ if (ret == 0)
+ {
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MLC_INT2,
+ (uint8_t *)&val->mlc_int2, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_INT2,
- (uint8_t*)&val->emb_func_int2, 1);
+ (uint8_t *)&val->emb_func_int2, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FSM_INT2_A,
- (uint8_t*)&val->fsm_int2_a, 1);
+ (uint8_t *)&val->fsm_int2_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FSM_INT2_B,
- (uint8_t*)&val->fsm_int2_b, 1);
+ (uint8_t *)&val->fsm_int2_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT2_CTRL,
- (uint8_t*)&val->int2_ctrl, 1);
+ (uint8_t *)&val->int2_ctrl, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MD2_CFG,
- (uint8_t*)&val->md2_cfg, 1);
+ (uint8_t *)&val->md2_cfg, 1);
}
+
return ret;
}
@@ -4199,16 +4946,21 @@ int32_t ism330dhcx_pin_int2_route_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_pin_mode_set(stmdev_ctx_t *ctx, ism330dhcx_pp_od_t val)
+int32_t ism330dhcx_pin_mode_set(stmdev_ctx_t *ctx,
+ ism330dhcx_pp_od_t val)
{
ism330dhcx_ctrl3_c_t ctrl3_c;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.pp_od= (uint8_t)val;
- ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ if (ret == 0)
+ {
+ ctrl3_c.pp_od = (uint8_t)val;
+ ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -4225,20 +4977,24 @@ int32_t ism330dhcx_pin_mode_get(stmdev_ctx_t *ctx,
{
ism330dhcx_ctrl3_c_t ctrl3_c;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
-
- switch (ctrl3_c.pp_od){
+ switch (ctrl3_c.pp_od)
+ {
case ISM330DHCX_PUSH_PULL:
*val = ISM330DHCX_PUSH_PULL;
break;
+
case ISM330DHCX_OPEN_DRAIN:
*val = ISM330DHCX_OPEN_DRAIN;
break;
+
default:
*val = ISM330DHCX_PUSH_PULL;
break;
}
+
return ret;
}
@@ -4251,17 +5007,20 @@ int32_t ism330dhcx_pin_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_pin_polarity_set(stmdev_ctx_t *ctx,
- ism330dhcx_h_lactive_t val)
+ ism330dhcx_h_lactive_t val)
{
ism330dhcx_ctrl3_c_t ctrl3_c;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.h_lactive= (uint8_t)val;
+ if (ret == 0)
+ {
+ ctrl3_c.h_lactive = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL3_C,
- (uint8_t*)&ctrl3_c, 1);
+ (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -4274,24 +5033,28 @@ int32_t ism330dhcx_pin_polarity_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_pin_polarity_get(stmdev_ctx_t *ctx,
- ism330dhcx_h_lactive_t *val)
+ ism330dhcx_h_lactive_t *val)
{
ism330dhcx_ctrl3_c_t ctrl3_c;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
-
- switch (ctrl3_c.h_lactive){
+ switch (ctrl3_c.h_lactive)
+ {
case ISM330DHCX_ACTIVE_HIGH:
*val = ISM330DHCX_ACTIVE_HIGH;
break;
+
case ISM330DHCX_ACTIVE_LOW:
*val = ISM330DHCX_ACTIVE_LOW;
break;
+
default:
*val = ISM330DHCX_ACTIVE_HIGH;
break;
}
+
return ret;
}
@@ -4307,13 +5070,16 @@ int32_t ism330dhcx_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_ctrl4_c_t ctrl4_c;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ctrl4_c.int2_on_int1= (uint8_t)val;
+ if (ret == 0)
+ {
+ ctrl4_c.int2_on_int1 = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL4_C,
- (uint8_t*)&ctrl4_c, 1);
+ (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -4329,8 +5095,8 @@ int32_t ism330dhcx_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dhcx_ctrl4_c_t ctrl4_c;
int32_t ret;
-
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.int2_on_int1;
return ret;
@@ -4345,33 +5111,45 @@ int32_t ism330dhcx_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t ism330dhcx_int_notification_set(stmdev_ctx_t *ctx,
- ism330dhcx_lir_t val)
+ ism330dhcx_lir_t val)
{
ism330dhcx_tap_cfg0_t tap_cfg0;
ism330dhcx_page_rw_t page_rw;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0,
+ (uint8_t *)&tap_cfg0, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
tap_cfg0.lir = (uint8_t)val & 0x01U;
tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_TAP_CFG0,
- (uint8_t*)&tap_cfg0, 1);
+ (uint8_t *)&tap_cfg0, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
}
- if(ret == 0){
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW, (uint8_t*)&page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW,
+ (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_RW,
- (uint8_t*)&page_rw, 1);
+ (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -4384,43 +5162,54 @@ int32_t ism330dhcx_int_notification_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_int_notification_get(stmdev_ctx_t *ctx,
- ism330dhcx_lir_t *val)
+ ism330dhcx_lir_t *val)
{
ism330dhcx_tap_cfg0_t tap_cfg0;
ism330dhcx_page_rw_t page_rw;
int32_t ret;
-
*val = ISM330DHCX_ALL_INT_PULSED;
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0,
- (uint8_t*)&tap_cfg0, 1);
+ (uint8_t *)&tap_cfg0, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW,
- (uint8_t*)&page_rw, 1);
+ (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
- switch ((page_rw.emb_func_lir << 1) + tap_cfg0.lir){
+
+ switch ((page_rw.emb_func_lir << 1) + tap_cfg0.lir)
+ {
case ISM330DHCX_ALL_INT_PULSED:
*val = ISM330DHCX_ALL_INT_PULSED;
break;
+
case ISM330DHCX_BASE_LATCHED_EMB_PULSED:
*val = ISM330DHCX_BASE_LATCHED_EMB_PULSED;
break;
+
case ISM330DHCX_BASE_PULSED_EMB_LATCHED:
*val = ISM330DHCX_BASE_PULSED_EMB_LATCHED;
break;
+
case ISM330DHCX_ALL_INT_LATCHED:
*val = ISM330DHCX_ALL_INT_LATCHED;
break;
+
default:
*val = ISM330DHCX_ALL_INT_PULSED;
break;
}
+
return ret;
}
@@ -4448,18 +5237,20 @@ int32_t ism330dhcx_int_notification_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_wkup_ths_weight_set(stmdev_ctx_t *ctx,
- ism330dhcx_wake_ths_w_t val)
+ ism330dhcx_wake_ths_w_t val)
{
ism330dhcx_wake_up_dur_t wake_up_dur;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
- wake_up_dur.wake_ths_w= (uint8_t)val;
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ wake_up_dur.wake_ths_w = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -4474,25 +5265,28 @@ int32_t ism330dhcx_wkup_ths_weight_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_wkup_ths_weight_get(stmdev_ctx_t *ctx,
- ism330dhcx_wake_ths_w_t *val)
+ ism330dhcx_wake_ths_w_t *val)
{
ism330dhcx_wake_up_dur_t wake_up_dur;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
- switch (wake_up_dur.wake_ths_w){
+ switch (wake_up_dur.wake_ths_w)
+ {
case ISM330DHCX_LSb_FS_DIV_64:
*val = ISM330DHCX_LSb_FS_DIV_64;
break;
+
case ISM330DHCX_LSb_FS_DIV_256:
*val = ISM330DHCX_LSb_FS_DIV_256;
break;
+
default:
*val = ISM330DHCX_LSb_FS_DIV_64;
break;
}
+
return ret;
}
@@ -4509,14 +5303,16 @@ int32_t ism330dhcx_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_wake_up_ths_t wake_up_ths;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
- if(ret == 0){
- wake_up_ths.wk_ths= (uint8_t)val;
+ (uint8_t *)&wake_up_ths, 1);
+
+ if (ret == 0)
+ {
+ wake_up_ths.wk_ths = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
}
+
return ret;
}
@@ -4533,9 +5329,8 @@ int32_t ism330dhcx_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dhcx_wake_up_ths_t wake_up_ths;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
*val = wake_up_ths.wk_ths;
return ret;
@@ -4554,14 +5349,16 @@ int32_t ism330dhcx_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx,
{
ism330dhcx_wake_up_ths_t wake_up_ths;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
- if(ret == 0){
- wake_up_ths.usr_off_on_wu= (uint8_t)val;
+ (uint8_t *)&wake_up_ths, 1);
+
+ if (ret == 0)
+ {
+ wake_up_ths.usr_off_on_wu = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
}
+
return ret;
}
@@ -4578,9 +5375,8 @@ int32_t ism330dhcx_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx,
{
ism330dhcx_wake_up_ths_t wake_up_ths;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
*val = wake_up_ths.usr_off_on_wu;
return ret;
@@ -4598,14 +5394,16 @@ int32_t ism330dhcx_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_wake_up_dur_t wake_up_dur;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
- wake_up_dur.wake_dur= (uint8_t)val;
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ wake_up_dur.wake_dur = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -4621,9 +5419,8 @@ int32_t ism330dhcx_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dhcx_wake_up_dur_t wake_up_dur;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
*val = wake_up_dur.wake_dur;
return ret;
@@ -4654,12 +5451,16 @@ int32_t ism330dhcx_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_ctrl4_c_t ctrl4_c;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ctrl4_c.sleep_g= (uint8_t)val;
- ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ if (ret == 0)
+ {
+ ctrl4_c.sleep_g = (uint8_t)val;
+ ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -4675,8 +5476,8 @@ int32_t ism330dhcx_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dhcx_ctrl4_c_t ctrl4_c;
int32_t ret;
-
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.sleep_g;
return ret;
@@ -4693,17 +5494,20 @@ int32_t ism330dhcx_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t ism330dhcx_act_pin_notification_set(stmdev_ctx_t *ctx,
- ism330dhcx_sleep_status_on_int_t val)
+ ism330dhcx_sleep_status_on_int_t val)
{
ism330dhcx_tap_cfg0_t tap_cfg0;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0,
+ (uint8_t *)&tap_cfg0, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
- if(ret == 0){
- tap_cfg0. sleep_status_on_int= (uint8_t)val;
+ if (ret == 0)
+ {
+ tap_cfg0. sleep_status_on_int = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_TAP_CFG0,
- (uint8_t*)&tap_cfg0, 1);
+ (uint8_t *)&tap_cfg0, 1);
}
+
return ret;
}
@@ -4718,23 +5522,28 @@ int32_t ism330dhcx_act_pin_notification_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_act_pin_notification_get(stmdev_ctx_t *ctx,
- ism330dhcx_sleep_status_on_int_t *val)
+ ism330dhcx_sleep_status_on_int_t *val)
{
ism330dhcx_tap_cfg0_t tap_cfg0;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0,
+ (uint8_t *)&tap_cfg0, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
- switch (tap_cfg0. sleep_status_on_int){
+ switch (tap_cfg0. sleep_status_on_int)
+ {
case ISM330DHCX_DRIVE_SLEEP_CHG_EVENT:
*val = ISM330DHCX_DRIVE_SLEEP_CHG_EVENT;
break;
+
case ISM330DHCX_DRIVE_SLEEP_STATUS:
*val = ISM330DHCX_DRIVE_SLEEP_STATUS;
break;
+
default:
*val = ISM330DHCX_DRIVE_SLEEP_CHG_EVENT;
break;
}
+
return ret;
}
@@ -4751,13 +5560,16 @@ int32_t ism330dhcx_act_mode_set(stmdev_ctx_t *ctx,
{
ism330dhcx_tap_cfg2_t tap_cfg2;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG2,
+ (uint8_t *)&tap_cfg2, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG2, (uint8_t*)&tap_cfg2, 1);
- if(ret == 0){
- tap_cfg2.inact_en= (uint8_t)val;
+ if (ret == 0)
+ {
+ tap_cfg2.inact_en = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_TAP_CFG2,
- (uint8_t*)&tap_cfg2, 1);
+ (uint8_t *)&tap_cfg2, 1);
}
+
return ret;
}
@@ -4774,26 +5586,32 @@ int32_t ism330dhcx_act_mode_get(stmdev_ctx_t *ctx,
{
ism330dhcx_tap_cfg2_t tap_cfg2;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG2,
+ (uint8_t *)&tap_cfg2, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG2, (uint8_t*)&tap_cfg2, 1);
-
- switch (tap_cfg2.inact_en){
+ switch (tap_cfg2.inact_en)
+ {
case ISM330DHCX_XL_AND_GY_NOT_AFFECTED:
*val = ISM330DHCX_XL_AND_GY_NOT_AFFECTED;
break;
+
case ISM330DHCX_XL_12Hz5_GY_NOT_AFFECTED:
*val = ISM330DHCX_XL_12Hz5_GY_NOT_AFFECTED;
break;
+
case ISM330DHCX_XL_12Hz5_GY_SLEEP:
*val = ISM330DHCX_XL_12Hz5_GY_SLEEP;
break;
+
case ISM330DHCX_XL_12Hz5_GY_PD:
*val = ISM330DHCX_XL_12Hz5_GY_PD;
break;
+
default:
*val = ISM330DHCX_XL_AND_GY_NOT_AFFECTED;
break;
}
+
return ret;
}
@@ -4809,14 +5627,16 @@ int32_t ism330dhcx_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_wake_up_dur_t wake_up_dur;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
- wake_up_dur.sleep_dur= (uint8_t)val;
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ wake_up_dur.sleep_dur = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -4832,9 +5652,8 @@ int32_t ism330dhcx_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dhcx_wake_up_dur_t wake_up_dur;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
*val = wake_up_dur.sleep_dur;
return ret;
@@ -4861,17 +5680,21 @@ int32_t ism330dhcx_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ism330dhcx_tap_detection_on_z_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
ism330dhcx_tap_cfg0_t tap_cfg0;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0,
+ (uint8_t *)&tap_cfg0, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
- if(ret == 0){
- tap_cfg0.tap_z_en= (uint8_t)val;
+ if (ret == 0)
+ {
+ tap_cfg0.tap_z_en = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_TAP_CFG0,
- (uint8_t*)&tap_cfg0, 1);
+ (uint8_t *)&tap_cfg0, 1);
}
+
return ret;
}
@@ -4883,12 +5706,13 @@ int32_t ism330dhcx_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dhcx_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dhcx_tap_cfg0_t tap_cfg0;
int32_t ret;
-
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0,
+ (uint8_t *)&tap_cfg0, 1);
*val = tap_cfg0.tap_z_en;
return ret;
@@ -4902,17 +5726,21 @@ int32_t ism330dhcx_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ism330dhcx_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
ism330dhcx_tap_cfg0_t tap_cfg0;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0,
+ (uint8_t *)&tap_cfg0, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
- if(ret == 0){
- tap_cfg0.tap_y_en= (uint8_t)val;
+ if (ret == 0)
+ {
+ tap_cfg0.tap_y_en = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_TAP_CFG0,
- (uint8_t*)&tap_cfg0, 1);
+ (uint8_t *)&tap_cfg0, 1);
}
+
return ret;
}
@@ -4924,12 +5752,13 @@ int32_t ism330dhcx_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dhcx_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dhcx_tap_cfg0_t tap_cfg0;
int32_t ret;
-
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0,
+ (uint8_t *)&tap_cfg0, 1);
*val = tap_cfg0.tap_y_en;
return ret;
@@ -4943,17 +5772,21 @@ int32_t ism330dhcx_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ism330dhcx_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
ism330dhcx_tap_cfg0_t tap_cfg0;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0,
+ (uint8_t *)&tap_cfg0, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
- if(ret == 0){
- tap_cfg0.tap_x_en= (uint8_t)val;
+ if (ret == 0)
+ {
+ tap_cfg0.tap_x_en = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_TAP_CFG0,
- (uint8_t*)&tap_cfg0, 1);
+ (uint8_t *)&tap_cfg0, 1);
}
+
return ret;
}
@@ -4965,12 +5798,13 @@ int32_t ism330dhcx_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dhcx_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dhcx_tap_cfg0_t tap_cfg0;
int32_t ret;
-
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0,
+ (uint8_t *)&tap_cfg0, 1);
*val = tap_cfg0.tap_x_en;
return ret;
@@ -4988,13 +5822,16 @@ int32_t ism330dhcx_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_tap_cfg1_t tap_cfg1;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG1,
+ (uint8_t *)&tap_cfg1, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG1, (uint8_t*)&tap_cfg1, 1);
- if(ret == 0){
- tap_cfg1.tap_ths_x= (uint8_t)val;
+ if (ret == 0)
+ {
+ tap_cfg1.tap_ths_x = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_TAP_CFG1,
- (uint8_t*)&tap_cfg1, 1);
+ (uint8_t *)&tap_cfg1, 1);
}
+
return ret;
}
@@ -5006,12 +5843,13 @@ int32_t ism330dhcx_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dhcx_tap_threshold_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dhcx_tap_cfg1_t tap_cfg1;
int32_t ret;
-
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG1, (uint8_t*)&tap_cfg1, 1);
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG1,
+ (uint8_t *)&tap_cfg1, 1);
*val = tap_cfg1.tap_ths_x;
return ret;
@@ -5026,17 +5864,20 @@ int32_t ism330dhcx_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t ism330dhcx_tap_axis_priority_set(stmdev_ctx_t *ctx,
- ism330dhcx_tap_priority_t val)
+ ism330dhcx_tap_priority_t val)
{
ism330dhcx_tap_cfg1_t tap_cfg1;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG1,
+ (uint8_t *)&tap_cfg1, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG1, (uint8_t*)&tap_cfg1, 1);
- if(ret == 0){
- tap_cfg1.tap_priority= (uint8_t)val;
+ if (ret == 0)
+ {
+ tap_cfg1.tap_priority = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_TAP_CFG1,
- (uint8_t*)&tap_cfg1, 1);
+ (uint8_t *)&tap_cfg1, 1);
}
+
return ret;
}
@@ -5049,36 +5890,44 @@ int32_t ism330dhcx_tap_axis_priority_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_tap_axis_priority_get(stmdev_ctx_t *ctx,
- ism330dhcx_tap_priority_t *val)
+ ism330dhcx_tap_priority_t *val)
{
ism330dhcx_tap_cfg1_t tap_cfg1;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG1,
+ (uint8_t *)&tap_cfg1, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG1, (uint8_t*)&tap_cfg1, 1);
-
- switch (tap_cfg1.tap_priority){
+ switch (tap_cfg1.tap_priority)
+ {
case ISM330DHCX_XYZ:
*val = ISM330DHCX_XYZ;
break;
+
case ISM330DHCX_YXZ:
*val = ISM330DHCX_YXZ;
break;
+
case ISM330DHCX_XZY:
*val = ISM330DHCX_XZY;
break;
+
case ISM330DHCX_ZYX:
*val = ISM330DHCX_ZYX;
break;
+
case ISM330DHCX_YZX:
*val = ISM330DHCX_YZX;
break;
+
case ISM330DHCX_ZXY:
*val = ISM330DHCX_ZXY;
break;
+
default:
*val = ISM330DHCX_XYZ;
break;
}
+
return ret;
}
@@ -5094,13 +5943,16 @@ int32_t ism330dhcx_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_tap_cfg2_t tap_cfg2;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG2,
+ (uint8_t *)&tap_cfg2, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG2, (uint8_t*)&tap_cfg2, 1);
- if(ret == 0){
- tap_cfg2.tap_ths_y= (uint8_t)val;
+ if (ret == 0)
+ {
+ tap_cfg2.tap_ths_y = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_TAP_CFG2,
- (uint8_t*)&tap_cfg2, 1);
+ (uint8_t *)&tap_cfg2, 1);
}
+
return ret;
}
@@ -5112,12 +5964,13 @@ int32_t ism330dhcx_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dhcx_tap_threshold_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dhcx_tap_cfg2_t tap_cfg2;
int32_t ret;
-
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG2, (uint8_t*)&tap_cfg2, 1);
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG2,
+ (uint8_t *)&tap_cfg2, 1);
*val = tap_cfg2.tap_ths_y;
return ret;
@@ -5135,14 +5988,16 @@ int32_t ism330dhcx_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_tap_ths_6d_t tap_ths_6d;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
- if(ret == 0){
- tap_ths_6d.tap_ths_z= (uint8_t)val;
+ (uint8_t *)&tap_ths_6d, 1);
+
+ if (ret == 0)
+ {
+ tap_ths_6d.tap_ths_z = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
+ (uint8_t *)&tap_ths_6d, 1);
}
+
return ret;
}
@@ -5154,13 +6009,13 @@ int32_t ism330dhcx_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dhcx_tap_threshold_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dhcx_tap_ths_6d_t tap_ths_6d;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
+ (uint8_t *)&tap_ths_6d, 1);
*val = tap_ths_6d.tap_ths_z;
return ret;
@@ -5182,13 +6037,16 @@ int32_t ism330dhcx_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_int_dur2_t int_dur2;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_DUR2,
+ (uint8_t *)&int_dur2, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_DUR2, (uint8_t*)&int_dur2, 1);
- if(ret == 0){
- int_dur2.shock= (uint8_t)val;
+ if (ret == 0)
+ {
+ int_dur2.shock = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_INT_DUR2,
- (uint8_t*)&int_dur2, 1);
+ (uint8_t *)&int_dur2, 1);
}
+
return ret;
}
@@ -5208,8 +6066,8 @@ int32_t ism330dhcx_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dhcx_int_dur2_t int_dur2;
int32_t ret;
-
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_DUR2,
+ (uint8_t *)&int_dur2, 1);
*val = int_dur2.shock;
return ret;
@@ -5231,13 +6089,16 @@ int32_t ism330dhcx_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_int_dur2_t int_dur2;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_DUR2,
+ (uint8_t *)&int_dur2, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_DUR2, (uint8_t*)&int_dur2, 1);
- if(ret == 0){
- int_dur2.quiet= (uint8_t)val;
+ if (ret == 0)
+ {
+ int_dur2.quiet = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_INT_DUR2,
- (uint8_t*)&int_dur2, 1);
+ (uint8_t *)&int_dur2, 1);
}
+
return ret;
}
@@ -5257,8 +6118,8 @@ int32_t ism330dhcx_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dhcx_int_dur2_t int_dur2;
int32_t ret;
-
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_DUR2,
+ (uint8_t *)&int_dur2, 1);
*val = int_dur2.quiet;
return ret;
@@ -5282,13 +6143,16 @@ int32_t ism330dhcx_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_int_dur2_t int_dur2;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_DUR2,
+ (uint8_t *)&int_dur2, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_DUR2, (uint8_t*)&int_dur2, 1);
- if(ret == 0){
- int_dur2.dur= (uint8_t)val;
+ if (ret == 0)
+ {
+ int_dur2.dur = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_INT_DUR2,
- (uint8_t*)&int_dur2, 1);
+ (uint8_t *)&int_dur2, 1);
}
+
return ret;
}
@@ -5308,8 +6172,8 @@ int32_t ism330dhcx_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dhcx_int_dur2_t int_dur2;
int32_t ret;
-
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_DUR2,
+ (uint8_t *)&int_dur2, 1);
*val = int_dur2.dur;
return ret;
@@ -5324,18 +6188,20 @@ int32_t ism330dhcx_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t ism330dhcx_tap_mode_set(stmdev_ctx_t *ctx,
- ism330dhcx_single_double_tap_t val)
+ ism330dhcx_single_double_tap_t val)
{
ism330dhcx_wake_up_ths_t wake_up_ths;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
- if(ret == 0){
- wake_up_ths.single_double_tap= (uint8_t)val;
+ (uint8_t *)&wake_up_ths, 1);
+
+ if (ret == 0)
+ {
+ wake_up_ths.single_double_tap = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
}
+
return ret;
}
@@ -5348,25 +6214,28 @@ int32_t ism330dhcx_tap_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_tap_mode_get(stmdev_ctx_t *ctx,
- ism330dhcx_single_double_tap_t *val)
+ ism330dhcx_single_double_tap_t *val)
{
ism330dhcx_wake_up_ths_t wake_up_ths;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
- switch (wake_up_ths.single_double_tap){
+ switch (wake_up_ths.single_double_tap)
+ {
case ISM330DHCX_ONLY_SINGLE:
*val = ISM330DHCX_ONLY_SINGLE;
break;
+
case ISM330DHCX_BOTH_SINGLE_DOUBLE:
*val = ISM330DHCX_BOTH_SINGLE_DOUBLE;
break;
+
default:
*val = ISM330DHCX_ONLY_SINGLE;
break;
}
+
return ret;
}
@@ -5392,18 +6261,20 @@ int32_t ism330dhcx_tap_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_6d_threshold_set(stmdev_ctx_t *ctx,
- ism330dhcx_sixd_ths_t val)
+ ism330dhcx_sixd_ths_t val)
{
ism330dhcx_tap_ths_6d_t tap_ths_6d;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
- if(ret == 0){
- tap_ths_6d.sixd_ths= (uint8_t)val;
+ (uint8_t *)&tap_ths_6d, 1);
+
+ if (ret == 0)
+ {
+ tap_ths_6d.sixd_ths = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
+ (uint8_t *)&tap_ths_6d, 1);
}
+
return ret;
}
@@ -5416,31 +6287,36 @@ int32_t ism330dhcx_6d_threshold_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_6d_threshold_get(stmdev_ctx_t *ctx,
- ism330dhcx_sixd_ths_t *val)
+ ism330dhcx_sixd_ths_t *val)
{
ism330dhcx_tap_ths_6d_t tap_ths_6d;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
+ (uint8_t *)&tap_ths_6d, 1);
- switch (tap_ths_6d.sixd_ths){
+ switch (tap_ths_6d.sixd_ths)
+ {
case ISM330DHCX_DEG_80:
*val = ISM330DHCX_DEG_80;
break;
+
case ISM330DHCX_DEG_70:
*val = ISM330DHCX_DEG_70;
break;
+
case ISM330DHCX_DEG_60:
*val = ISM330DHCX_DEG_60;
break;
+
case ISM330DHCX_DEG_50:
*val = ISM330DHCX_DEG_50;
break;
+
default:
*val = ISM330DHCX_DEG_80;
break;
}
+
return ret;
}
@@ -5456,14 +6332,16 @@ int32_t ism330dhcx_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_tap_ths_6d_t tap_ths_6d;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
- if(ret == 0){
- tap_ths_6d.d4d_en= (uint8_t)val;
+ (uint8_t *)&tap_ths_6d, 1);
+
+ if (ret == 0)
+ {
+ tap_ths_6d.d4d_en = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
+ (uint8_t *)&tap_ths_6d, 1);
}
+
return ret;
}
@@ -5479,9 +6357,8 @@ int32_t ism330dhcx_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dhcx_tap_ths_6d_t tap_ths_6d;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
+ (uint8_t *)&tap_ths_6d, 1);
*val = tap_ths_6d.d4d_en;
return ret;
@@ -5509,18 +6386,20 @@ int32_t ism330dhcx_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t ism330dhcx_ff_threshold_set(stmdev_ctx_t *ctx,
- ism330dhcx_ff_ths_t val)
+ ism330dhcx_ff_ths_t val)
{
ism330dhcx_free_fall_t free_fall;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FREE_FALL,
- (uint8_t*)&free_fall, 1);
- if(ret == 0){
- free_fall.ff_ths= (uint8_t)val;
+ (uint8_t *)&free_fall, 1);
+
+ if (ret == 0)
+ {
+ free_fall.ff_ths = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FREE_FALL,
- (uint8_t*)&free_fall, 1);
+ (uint8_t *)&free_fall, 1);
}
+
return ret;
}
@@ -5533,43 +6412,52 @@ int32_t ism330dhcx_ff_threshold_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_ff_threshold_get(stmdev_ctx_t *ctx,
- ism330dhcx_ff_ths_t *val)
+ ism330dhcx_ff_ths_t *val)
{
ism330dhcx_free_fall_t free_fall;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FREE_FALL,
- (uint8_t*)&free_fall, 1);
+ (uint8_t *)&free_fall, 1);
- switch (free_fall.ff_ths){
+ switch (free_fall.ff_ths)
+ {
case ISM330DHCX_FF_TSH_156mg:
*val = ISM330DHCX_FF_TSH_156mg;
break;
+
case ISM330DHCX_FF_TSH_219mg:
*val = ISM330DHCX_FF_TSH_219mg;
break;
+
case ISM330DHCX_FF_TSH_250mg:
*val = ISM330DHCX_FF_TSH_250mg;
break;
+
case ISM330DHCX_FF_TSH_312mg:
*val = ISM330DHCX_FF_TSH_312mg;
break;
+
case ISM330DHCX_FF_TSH_344mg:
*val = ISM330DHCX_FF_TSH_344mg;
break;
+
case ISM330DHCX_FF_TSH_406mg:
*val = ISM330DHCX_FF_TSH_406mg;
break;
+
case ISM330DHCX_FF_TSH_469mg:
*val = ISM330DHCX_FF_TSH_469mg;
break;
+
case ISM330DHCX_FF_TSH_500mg:
*val = ISM330DHCX_FF_TSH_500mg;
break;
+
default:
*val = ISM330DHCX_FF_TSH_156mg;
break;
}
+
return ret;
}
@@ -5586,23 +6474,29 @@ int32_t ism330dhcx_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
ism330dhcx_wake_up_dur_t wake_up_dur;
ism330dhcx_free_fall_t free_fall;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
wake_up_dur.ff_dur = (val & 0x20U) >> 5;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FREE_FALL,
- (uint8_t*)&free_fall, 1);
+ (uint8_t *)&free_fall, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
free_fall.ff_dur = val & 0x1FU;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FREE_FALL,
- (uint8_t*)&free_fall, 1);
+ (uint8_t *)&free_fall, 1);
}
+
return ret;
}
@@ -5619,14 +6513,15 @@ int32_t ism330dhcx_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
ism330dhcx_wake_up_dur_t wake_up_dur;
ism330dhcx_free_fall_t free_fall;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FREE_FALL,
- (uint8_t*)&free_fall, 1);
+ (uint8_t *)&free_fall, 1);
}
+
*val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
return ret;
@@ -5658,19 +6553,23 @@ int32_t ism330dhcx_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
ism330dhcx_fifo_ctrl1_t fifo_ctrl1;
ism330dhcx_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl2.wtm = (uint8_t)(val / 256U) & 0x01U;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
fifo_ctrl1.wtm = (uint8_t)(val - (fifo_ctrl2.wtm * 256U));
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FIFO_CTRL1,
- (uint8_t*)&fifo_ctrl1, 1);
+ (uint8_t *)&fifo_ctrl1, 1);
}
+
return ret;
}
@@ -5682,20 +6581,24 @@ int32_t ism330dhcx_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
+int32_t ism330dhcx_fifo_watermark_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
ism330dhcx_fifo_ctrl1_t fifo_ctrl1;
ism330dhcx_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL1,
- (uint8_t*)&fifo_ctrl1, 1);
+ (uint8_t *)&fifo_ctrl1, 1);
}
+
*val = fifo_ctrl2.wtm;
*val = (*val * 256U) + fifo_ctrl1.wtm;;
+
return ret;
}
@@ -5707,24 +6610,31 @@ int32_t ism330dhcx_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_compression_algo_init_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ism330dhcx_compression_algo_init_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
ism330dhcx_emb_func_init_b_t emb_func_init_b;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_INIT_B,
- (uint8_t*)&emb_func_init_b, 1);
+ (uint8_t *)&emb_func_init_b, 1);
}
- if(ret == 0){
- emb_func_init_b.fifo_compr_init= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ emb_func_init_b.fifo_compr_init = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_INIT_B,
- (uint8_t*)&emb_func_init_b, 1);
+ (uint8_t *)&emb_func_init_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -5738,20 +6648,24 @@ int32_t ism330dhcx_compression_algo_init_set(stmdev_ctx_t *ctx, uint8_t val)
*
*/
int32_t ism330dhcx_compression_algo_init_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
ism330dhcx_emb_func_init_b_t emb_func_init_b;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_INIT_B,
- (uint8_t*)&emb_func_init_b, 1);
+ (uint8_t *)&emb_func_init_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = emb_func_init_b.fifo_compr_init;
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -5764,38 +6678,49 @@ int32_t ism330dhcx_compression_algo_init_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_compression_algo_set(stmdev_ctx_t *ctx,
- ism330dhcx_uncoptr_rate_t val)
+ ism330dhcx_uncoptr_rate_t val)
{
ism330dhcx_fifo_ctrl2_t fifo_ctrl2;
ism330dhcx_emb_func_en_b_t emb_func_en_b;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
emb_func_en_b.fifo_compr_en = ((uint8_t)val & 0x04U) >> 2;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
fifo_ctrl2.fifo_compr_rt_en = ((uint8_t)val & 0x04U) >> 2;
fifo_ctrl2.uncoptr_rate = (uint8_t)val & 0x03U;
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
+
return ret;
}
@@ -5808,34 +6733,41 @@ int32_t ism330dhcx_compression_algo_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_compression_algo_get(stmdev_ctx_t *ctx,
- ism330dhcx_uncoptr_rate_t *val)
+ ism330dhcx_uncoptr_rate_t *val)
{
ism330dhcx_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
- switch (( fifo_ctrl2.fifo_compr_rt_en << 2) + fifo_ctrl2.uncoptr_rate ){
+ switch ((fifo_ctrl2.fifo_compr_rt_en << 2) +
+ fifo_ctrl2.uncoptr_rate)
+ {
case ISM330DHCX_CMP_DISABLE:
*val = ISM330DHCX_CMP_DISABLE;
break;
+
case ISM330DHCX_CMP_ALWAYS:
*val = ISM330DHCX_CMP_ALWAYS;
break;
+
case ISM330DHCX_CMP_8_TO_1:
*val = ISM330DHCX_CMP_8_TO_1;
break;
+
case ISM330DHCX_CMP_16_TO_1:
*val = ISM330DHCX_CMP_16_TO_1;
break;
+
case ISM330DHCX_CMP_32_TO_1:
*val = ISM330DHCX_CMP_32_TO_1;
break;
+
default:
*val = ISM330DHCX_CMP_DISABLE;
break;
}
+
return ret;
}
@@ -5848,17 +6780,18 @@ int32_t ism330dhcx_compression_algo_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
- uint8_t val)
+ uint8_t val)
{
ism330dhcx_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
- fifo_ctrl2.odrchg_en= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl2.odrchg_en = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
return ret;
@@ -5873,13 +6806,12 @@ int32_t ism330dhcx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
ism330dhcx_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
*val = fifo_ctrl2.odrchg_en;
return ret;
@@ -5894,18 +6826,20 @@ int32_t ism330dhcx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_compression_algo_real_time_set(stmdev_ctx_t *ctx,
- uint8_t val)
+ uint8_t val)
{
ism330dhcx_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
- fifo_ctrl2.fifo_compr_rt_en= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl2.fifo_compr_rt_en = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
+
return ret;
}
@@ -5918,13 +6852,12 @@ int32_t ism330dhcx_compression_algo_real_time_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_compression_algo_real_time_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
ism330dhcx_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
*val = fifo_ctrl2.fifo_compr_rt_en;
return ret;
@@ -5939,18 +6872,21 @@ int32_t ism330dhcx_compression_algo_real_time_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ism330dhcx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
ism330dhcx_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
- fifo_ctrl2.stop_on_wtm= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl2.stop_on_wtm = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
+
return ret;
}
@@ -5963,13 +6899,13 @@ int32_t ism330dhcx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dhcx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dhcx_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
*val = fifo_ctrl2.stop_on_wtm;
return ret;
@@ -5985,18 +6921,20 @@ int32_t ism330dhcx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t ism330dhcx_fifo_xl_batch_set(stmdev_ctx_t *ctx,
- ism330dhcx_bdr_xl_t val)
+ ism330dhcx_bdr_xl_t val)
{
ism330dhcx_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
- if(ret == 0){
- fifo_ctrl3.bdr_xl= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl3, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl3.bdr_xl = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
+ (uint8_t *)&fifo_ctrl3, 1);
}
+
return ret;
}
@@ -6010,55 +6948,68 @@ int32_t ism330dhcx_fifo_xl_batch_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_fifo_xl_batch_get(stmdev_ctx_t *ctx,
- ism330dhcx_bdr_xl_t *val)
+ ism330dhcx_bdr_xl_t *val)
{
ism330dhcx_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
+ (uint8_t *)&fifo_ctrl3, 1);
- switch (fifo_ctrl3.bdr_xl){
+ switch (fifo_ctrl3.bdr_xl)
+ {
case ISM330DHCX_XL_NOT_BATCHED:
*val = ISM330DHCX_XL_NOT_BATCHED;
break;
+
case ISM330DHCX_XL_BATCHED_AT_12Hz5:
*val = ISM330DHCX_XL_BATCHED_AT_12Hz5;
break;
+
case ISM330DHCX_XL_BATCHED_AT_26Hz:
*val = ISM330DHCX_XL_BATCHED_AT_26Hz;
break;
+
case ISM330DHCX_XL_BATCHED_AT_52Hz:
*val = ISM330DHCX_XL_BATCHED_AT_52Hz;
break;
+
case ISM330DHCX_XL_BATCHED_AT_104Hz:
*val = ISM330DHCX_XL_BATCHED_AT_104Hz;
break;
+
case ISM330DHCX_XL_BATCHED_AT_208Hz:
*val = ISM330DHCX_XL_BATCHED_AT_208Hz;
break;
+
case ISM330DHCX_XL_BATCHED_AT_417Hz:
*val = ISM330DHCX_XL_BATCHED_AT_417Hz;
break;
+
case ISM330DHCX_XL_BATCHED_AT_833Hz:
*val = ISM330DHCX_XL_BATCHED_AT_833Hz;
break;
+
case ISM330DHCX_XL_BATCHED_AT_1667Hz:
*val = ISM330DHCX_XL_BATCHED_AT_1667Hz;
break;
+
case ISM330DHCX_XL_BATCHED_AT_3333Hz:
*val = ISM330DHCX_XL_BATCHED_AT_3333Hz;
break;
+
case ISM330DHCX_XL_BATCHED_AT_6667Hz:
*val = ISM330DHCX_XL_BATCHED_AT_6667Hz;
break;
+
case ISM330DHCX_XL_BATCHED_AT_6Hz5:
*val = ISM330DHCX_XL_BATCHED_AT_6Hz5;
break;
+
default:
*val = ISM330DHCX_XL_NOT_BATCHED;
break;
}
+
return ret;
}
@@ -6072,18 +7023,20 @@ int32_t ism330dhcx_fifo_xl_batch_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_fifo_gy_batch_set(stmdev_ctx_t *ctx,
- ism330dhcx_bdr_gy_t val)
+ ism330dhcx_bdr_gy_t val)
{
ism330dhcx_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
- if(ret == 0){
- fifo_ctrl3.bdr_gy= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl3, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl3.bdr_gy = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
+ (uint8_t *)&fifo_ctrl3, 1);
}
+
return ret;
}
@@ -6097,55 +7050,68 @@ int32_t ism330dhcx_fifo_gy_batch_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_fifo_gy_batch_get(stmdev_ctx_t *ctx,
- ism330dhcx_bdr_gy_t *val)
+ ism330dhcx_bdr_gy_t *val)
{
ism330dhcx_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
+ (uint8_t *)&fifo_ctrl3, 1);
- switch (fifo_ctrl3.bdr_gy){
+ switch (fifo_ctrl3.bdr_gy)
+ {
case ISM330DHCX_GY_NOT_BATCHED:
*val = ISM330DHCX_GY_NOT_BATCHED;
break;
+
case ISM330DHCX_GY_BATCHED_AT_12Hz5:
*val = ISM330DHCX_GY_BATCHED_AT_12Hz5;
break;
+
case ISM330DHCX_GY_BATCHED_AT_26Hz:
*val = ISM330DHCX_GY_BATCHED_AT_26Hz;
break;
+
case ISM330DHCX_GY_BATCHED_AT_52Hz:
*val = ISM330DHCX_GY_BATCHED_AT_52Hz;
break;
+
case ISM330DHCX_GY_BATCHED_AT_104Hz:
*val = ISM330DHCX_GY_BATCHED_AT_104Hz;
break;
+
case ISM330DHCX_GY_BATCHED_AT_208Hz:
*val = ISM330DHCX_GY_BATCHED_AT_208Hz;
break;
+
case ISM330DHCX_GY_BATCHED_AT_417Hz:
*val = ISM330DHCX_GY_BATCHED_AT_417Hz;
break;
+
case ISM330DHCX_GY_BATCHED_AT_833Hz:
*val = ISM330DHCX_GY_BATCHED_AT_833Hz;
break;
+
case ISM330DHCX_GY_BATCHED_AT_1667Hz:
*val = ISM330DHCX_GY_BATCHED_AT_1667Hz;
break;
+
case ISM330DHCX_GY_BATCHED_AT_3333Hz:
*val = ISM330DHCX_GY_BATCHED_AT_3333Hz;
break;
+
case ISM330DHCX_GY_BATCHED_AT_6667Hz:
*val = ISM330DHCX_GY_BATCHED_AT_6667Hz;
break;
+
case ISM330DHCX_GY_BATCHED_6Hz5:
*val = ISM330DHCX_GY_BATCHED_6Hz5;
break;
+
default:
*val = ISM330DHCX_GY_NOT_BATCHED;
break;
}
+
return ret;
}
@@ -6158,18 +7124,20 @@ int32_t ism330dhcx_fifo_gy_batch_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_fifo_mode_set(stmdev_ctx_t *ctx,
- ism330dhcx_fifo_mode_t val)
+ ism330dhcx_fifo_mode_t val)
{
ism330dhcx_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
- fifo_ctrl4.fifo_mode= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl4.fifo_mode = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -6182,37 +7150,44 @@ int32_t ism330dhcx_fifo_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_fifo_mode_get(stmdev_ctx_t *ctx,
- ism330dhcx_fifo_mode_t *val)
+ ism330dhcx_fifo_mode_t *val)
{
ism330dhcx_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
- switch (fifo_ctrl4.fifo_mode){
+ switch (fifo_ctrl4.fifo_mode)
+ {
case ISM330DHCX_BYPASS_MODE:
*val = ISM330DHCX_BYPASS_MODE;
break;
+
case ISM330DHCX_FIFO_MODE:
*val = ISM330DHCX_FIFO_MODE;
break;
+
case ISM330DHCX_STREAM_TO_FIFO_MODE:
*val = ISM330DHCX_STREAM_TO_FIFO_MODE;
break;
+
case ISM330DHCX_BYPASS_TO_STREAM_MODE:
*val = ISM330DHCX_BYPASS_TO_STREAM_MODE;
break;
+
case ISM330DHCX_STREAM_MODE:
*val = ISM330DHCX_STREAM_MODE;
break;
+
case ISM330DHCX_BYPASS_TO_FIFO_MODE:
*val = ISM330DHCX_BYPASS_TO_FIFO_MODE;
break;
+
default:
*val = ISM330DHCX_BYPASS_MODE;
break;
}
+
return ret;
}
@@ -6226,18 +7201,20 @@ int32_t ism330dhcx_fifo_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_fifo_temp_batch_set(stmdev_ctx_t *ctx,
- ism330dhcx_odr_t_batch_t val)
+ ism330dhcx_odr_t_batch_t val)
{
ism330dhcx_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
- fifo_ctrl4.odr_t_batch= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl4.odr_t_batch = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -6251,31 +7228,36 @@ int32_t ism330dhcx_fifo_temp_batch_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_fifo_temp_batch_get(stmdev_ctx_t *ctx,
- ism330dhcx_odr_t_batch_t *val)
+ ism330dhcx_odr_t_batch_t *val)
{
ism330dhcx_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
- switch (fifo_ctrl4.odr_t_batch){
+ switch (fifo_ctrl4.odr_t_batch)
+ {
case ISM330DHCX_TEMP_NOT_BATCHED:
*val = ISM330DHCX_TEMP_NOT_BATCHED;
break;
+
case ISM330DHCX_TEMP_BATCHED_AT_52Hz:
*val = ISM330DHCX_TEMP_BATCHED_AT_52Hz;
break;
+
case ISM330DHCX_TEMP_BATCHED_AT_12Hz5:
*val = ISM330DHCX_TEMP_BATCHED_AT_12Hz5;
break;
+
case ISM330DHCX_TEMP_BATCHED_AT_1Hz6:
*val = ISM330DHCX_TEMP_BATCHED_AT_1Hz6;
break;
+
default:
*val = ISM330DHCX_TEMP_NOT_BATCHED;
break;
}
+
return ret;
}
@@ -6290,18 +7272,20 @@ int32_t ism330dhcx_fifo_temp_batch_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
- ism330dhcx_odr_ts_batch_t val)
+ ism330dhcx_odr_ts_batch_t val)
{
ism330dhcx_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
- fifo_ctrl4.odr_ts_batch= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl4.odr_ts_batch = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -6317,31 +7301,36 @@ int32_t ism330dhcx_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
- ism330dhcx_odr_ts_batch_t *val)
+ ism330dhcx_odr_ts_batch_t *val)
{
ism330dhcx_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
- switch (fifo_ctrl4.odr_ts_batch){
+ switch (fifo_ctrl4.odr_ts_batch)
+ {
case ISM330DHCX_NO_DECIMATION:
*val = ISM330DHCX_NO_DECIMATION;
break;
+
case ISM330DHCX_DEC_1:
*val = ISM330DHCX_DEC_1;
break;
+
case ISM330DHCX_DEC_8:
*val = ISM330DHCX_DEC_8;
break;
+
case ISM330DHCX_DEC_32:
*val = ISM330DHCX_DEC_32;
break;
+
default:
*val = ISM330DHCX_NO_DECIMATION;
break;
}
+
return ret;
}
@@ -6356,18 +7345,20 @@ int32_t ism330dhcx_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
- ism330dhcx_trig_counter_bdr_t val)
+ ism330dhcx_trig_counter_bdr_t val)
{
ism330dhcx_counter_bdr_reg1_t counter_bdr_reg1;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if(ret == 0){
- counter_bdr_reg1.trig_counter_bdr= (uint8_t)val;
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
+ counter_bdr_reg1.trig_counter_bdr = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
}
+
return ret;
}
@@ -6382,25 +7373,28 @@ int32_t ism330dhcx_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
- ism330dhcx_trig_counter_bdr_t *val)
+ ism330dhcx_trig_counter_bdr_t *val)
{
ism330dhcx_counter_bdr_reg1_t counter_bdr_reg1;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
- switch (counter_bdr_reg1.trig_counter_bdr){
+ switch (counter_bdr_reg1.trig_counter_bdr)
+ {
case ISM330DHCX_XL_BATCH_EVENT:
*val = ISM330DHCX_XL_BATCH_EVENT;
break;
+
case ISM330DHCX_GYRO_BATCH_EVENT:
*val = ISM330DHCX_GYRO_BATCH_EVENT;
break;
+
default:
*val = ISM330DHCX_XL_BATCH_EVENT;
break;
}
+
return ret;
}
@@ -6413,18 +7407,21 @@ int32_t ism330dhcx_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ism330dhcx_rst_batch_counter_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
ism330dhcx_counter_bdr_reg1_t counter_bdr_reg1;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if(ret == 0){
- counter_bdr_reg1.rst_counter_bdr= (uint8_t)val;
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
+ counter_bdr_reg1.rst_counter_bdr = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
}
+
return ret;
}
@@ -6437,13 +7434,13 @@ int32_t ism330dhcx_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dhcx_rst_batch_counter_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dhcx_counter_bdr_reg1_t counter_bdr_reg1;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
*val = counter_bdr_reg1.rst_counter_bdr;
return ret;
@@ -6458,25 +7455,30 @@ int32_t ism330dhcx_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_batch_counter_threshold_set(stmdev_ctx_t *ctx, uint16_t val)
+int32_t ism330dhcx_batch_counter_threshold_set(stmdev_ctx_t *ctx,
+ uint16_t val)
{
ism330dhcx_counter_bdr_reg2_t counter_bdr_reg1;
ism330dhcx_counter_bdr_reg2_t counter_bdr_reg2;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if (ret == 0){
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
counter_bdr_reg1.cnt_bdr_th = (uint8_t)((val / 256U) & 0x07U);
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
}
- if (ret == 0){
+
+ if (ret == 0)
+ {
counter_bdr_reg2.cnt_bdr_th = (uint8_t)(val -
- (counter_bdr_reg1.cnt_bdr_th * 256U));
+ (counter_bdr_reg1.cnt_bdr_th * 256U));
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_COUNTER_BDR_REG2,
- (uint8_t*)&counter_bdr_reg2, 1);
+ (uint8_t *)&counter_bdr_reg2, 1);
}
+
return ret;
}
@@ -6490,21 +7492,23 @@ int32_t ism330dhcx_batch_counter_threshold_set(stmdev_ctx_t *ctx, uint16_t val)
*
*/
int32_t ism330dhcx_batch_counter_threshold_get(stmdev_ctx_t *ctx,
- uint16_t *val)
+ uint16_t *val)
{
ism330dhcx_counter_bdr_reg1_t counter_bdr_reg1;
ism330dhcx_counter_bdr_reg2_t counter_bdr_reg2;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if (ret == 0){
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_COUNTER_BDR_REG2,
- (uint8_t*)&counter_bdr_reg2, 1);
+ (uint8_t *)&counter_bdr_reg2, 1);
}
*val = counter_bdr_reg1.cnt_bdr_th;
*val = (*val * 256U) + counter_bdr_reg2.cnt_bdr_th;
+
return ret;
}
@@ -6516,21 +7520,23 @@ int32_t ism330dhcx_batch_counter_threshold_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
+int32_t ism330dhcx_fifo_data_level_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
ism330dhcx_fifo_status1_t fifo_status1;
ism330dhcx_fifo_status2_t fifo_status2;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_STATUS1,
- (uint8_t*)&fifo_status1, 1);
- if (ret == 0){
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
+ (uint8_t *)&fifo_status1, 1);
+ if (ret == 0)
+ {
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_STATUS2,
+ (uint8_t *)&fifo_status2, 1);
*val = fifo_status2.diff_fifo;
*val = (*val * 256U) + fifo_status1.diff_fifo;
}
+
return ret;
}
@@ -6543,10 +7549,12 @@ int32_t ism330dhcx_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
*
*/
int32_t ism330dhcx_fifo_status_get(stmdev_ctx_t *ctx,
- ism330dhcx_fifo_status2_t *val)
+ ism330dhcx_fifo_status2_t *val)
{
int32_t ret;
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_STATUS2, (uint8_t*)val, 1);
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_STATUS2,
+ (uint8_t *)val, 1);
+
return ret;
}
@@ -6562,9 +7570,8 @@ int32_t ism330dhcx_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dhcx_fifo_status2_t fifo_status2;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
+ (uint8_t *)&fifo_status2, 1);
*val = fifo_status2.fifo_full_ia;
return ret;
@@ -6583,9 +7590,8 @@ int32_t ism330dhcx_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dhcx_fifo_status2_t fifo_status2;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
+ (uint8_t *)&fifo_status2, 1);
*val = fifo_status2. fifo_ovr_ia;
return ret;
@@ -6603,9 +7609,8 @@ int32_t ism330dhcx_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dhcx_fifo_status2_t fifo_status2;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
+ (uint8_t *)&fifo_status2, 1);
*val = fifo_status2.fifo_wtm_ia;
return ret;
@@ -6620,85 +7625,108 @@ int32_t ism330dhcx_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t ism330dhcx_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
- ism330dhcx_fifo_tag_t *val)
+ ism330dhcx_fifo_tag_t *val)
{
ism330dhcx_fifo_data_out_tag_t fifo_data_out_tag;
int32_t ret;
-
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_DATA_OUT_TAG,
- (uint8_t*)&fifo_data_out_tag, 1);
+ (uint8_t *)&fifo_data_out_tag, 1);
- switch (fifo_data_out_tag.tag_sensor){
+ switch (fifo_data_out_tag.tag_sensor)
+ {
case ISM330DHCX_GYRO_NC_TAG:
*val = ISM330DHCX_GYRO_NC_TAG;
break;
+
case ISM330DHCX_XL_NC_TAG:
*val = ISM330DHCX_XL_NC_TAG;
break;
+
case ISM330DHCX_TEMPERATURE_TAG:
*val = ISM330DHCX_TEMPERATURE_TAG;
break;
+
case ISM330DHCX_TIMESTAMP_TAG:
*val = ISM330DHCX_TIMESTAMP_TAG;
break;
+
case ISM330DHCX_CFG_CHANGE_TAG:
*val = ISM330DHCX_CFG_CHANGE_TAG;
break;
+
case ISM330DHCX_XL_NC_T_2_TAG:
*val = ISM330DHCX_XL_NC_T_2_TAG;
break;
+
case ISM330DHCX_XL_NC_T_1_TAG:
*val = ISM330DHCX_XL_NC_T_1_TAG;
break;
+
case ISM330DHCX_XL_2XC_TAG:
*val = ISM330DHCX_XL_2XC_TAG;
break;
+
case ISM330DHCX_XL_3XC_TAG:
*val = ISM330DHCX_XL_3XC_TAG;
break;
+
case ISM330DHCX_GYRO_NC_T_2_TAG:
*val = ISM330DHCX_GYRO_NC_T_2_TAG;
break;
+
case ISM330DHCX_GYRO_NC_T_1_TAG:
*val = ISM330DHCX_GYRO_NC_T_1_TAG;
break;
+
case ISM330DHCX_GYRO_2XC_TAG:
*val = ISM330DHCX_GYRO_2XC_TAG;
break;
+
case ISM330DHCX_GYRO_3XC_TAG:
*val = ISM330DHCX_GYRO_3XC_TAG;
break;
+
case ISM330DHCX_SENSORHUB_SLAVE0_TAG:
*val = ISM330DHCX_SENSORHUB_SLAVE0_TAG;
break;
+
case ISM330DHCX_SENSORHUB_SLAVE1_TAG:
*val = ISM330DHCX_SENSORHUB_SLAVE1_TAG;
break;
+
case ISM330DHCX_SENSORHUB_SLAVE2_TAG:
*val = ISM330DHCX_SENSORHUB_SLAVE2_TAG;
break;
+
case ISM330DHCX_SENSORHUB_SLAVE3_TAG:
*val = ISM330DHCX_SENSORHUB_SLAVE3_TAG;
break;
+
case ISM330DHCX_STEP_CPUNTER_TAG:
*val = ISM330DHCX_STEP_CPUNTER_TAG;
break;
+
case ISM330DHCX_GAME_ROTATION_TAG:
*val = ISM330DHCX_GAME_ROTATION_TAG;
break;
+
case ISM330DHCX_GEOMAG_ROTATION_TAG:
*val = ISM330DHCX_GEOMAG_ROTATION_TAG;
break;
+
case ISM330DHCX_ROTATION_TAG:
*val = ISM330DHCX_ROTATION_TAG;
break;
+
case ISM330DHCX_SENSORHUB_NACK_TAG:
*val = ISM330DHCX_SENSORHUB_NACK_TAG;
break;
+
default:
*val = ISM330DHCX_SENSORHUB_NACK_TAG;
break;
}
+
return ret;
}
@@ -6715,20 +7743,26 @@ int32_t ism330dhcx_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_emb_func_fifo_cfg_t emb_func_fifo_cfg;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_FIFO_CFG,
- (uint8_t*)&emb_func_fifo_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_FIFO_CFG,
+ (uint8_t *)&emb_func_fifo_cfg, 1);
}
- if(ret == 0){
- emb_func_fifo_cfg.pedo_fifo_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ emb_func_fifo_cfg.pedo_fifo_en = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_FIFO_CFG,
- (uint8_t*)&emb_func_fifo_cfg, 1);
+ (uint8_t *)&emb_func_fifo_cfg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -6741,20 +7775,25 @@ int32_t ism330dhcx_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dhcx_fifo_pedo_batch_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dhcx_emb_func_fifo_cfg_t emb_func_fifo_cfg;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_FIFO_CFG,
- (uint8_t*)&emb_func_fifo_cfg, 1);
+ (uint8_t *)&emb_func_fifo_cfg, 1);
*val = emb_func_fifo_cfg.pedo_fifo_en;
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -6766,25 +7805,31 @@ int32_t ism330dhcx_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ism330dhcx_sh_batch_slave_0_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
ism330dhcx_slv0_config_t slv0_config;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
- slv0_config. batch_ext_sens_0_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ slv0_config. batch_ext_sens_0_en = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -6797,21 +7842,25 @@ int32_t ism330dhcx_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dhcx_sh_batch_slave_0_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dhcx_slv0_config_t slv0_config;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = slv0_config. batch_ext_sens_0_en;
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -6824,24 +7873,31 @@ int32_t ism330dhcx_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ism330dhcx_sh_batch_slave_1_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
ism330dhcx_slv1_config_t slv1_config;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SLV1_CONFIG,
- (uint8_t*)&slv1_config, 1);
+ (uint8_t *)&slv1_config, 1);
}
- if(ret == 0){
- slv1_config. batch_ext_sens_1_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ slv1_config. batch_ext_sens_1_en = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV1_CONFIG,
- (uint8_t*)&slv1_config, 1);
+ (uint8_t *)&slv1_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -6854,21 +7910,25 @@ int32_t ism330dhcx_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dhcx_sh_batch_slave_1_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dhcx_slv1_config_t slv1_config;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SLV1_CONFIG,
- (uint8_t*)&slv1_config, 1);
+ (uint8_t *)&slv1_config, 1);
*val = slv1_config. batch_ext_sens_1_en;
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -6881,25 +7941,31 @@ int32_t ism330dhcx_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ism330dhcx_sh_batch_slave_2_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
ism330dhcx_slv2_config_t slv2_config;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SLV2_CONFIG,
- (uint8_t*)&slv2_config, 1);
+ (uint8_t *)&slv2_config, 1);
}
- if(ret == 0){
- slv2_config. batch_ext_sens_2_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ slv2_config. batch_ext_sens_2_en = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV2_CONFIG,
- (uint8_t*)&slv2_config, 1);
+ (uint8_t *)&slv2_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -6912,20 +7978,25 @@ int32_t ism330dhcx_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dhcx_sh_batch_slave_2_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dhcx_slv2_config_t slv2_config;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SLV2_CONFIG,
- (uint8_t*)&slv2_config, 1);
+ (uint8_t *)&slv2_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = slv2_config. batch_ext_sens_2_en;
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -6938,24 +8009,31 @@ int32_t ism330dhcx_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ism330dhcx_sh_batch_slave_3_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
ism330dhcx_slv3_config_t slv3_config;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SLV3_CONFIG,
- (uint8_t*)&slv3_config, 1);
+ (uint8_t *)&slv3_config, 1);
}
- if(ret == 0){
- slv3_config. batch_ext_sens_3_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ slv3_config. batch_ext_sens_3_en = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV3_CONFIG,
- (uint8_t*)&slv3_config, 1);
+ (uint8_t *)&slv3_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -6968,21 +8046,25 @@ int32_t ism330dhcx_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dhcx_sh_batch_slave_3_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dhcx_slv3_config_t slv3_config;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SLV3_CONFIG,
- (uint8_t*)&slv3_config, 1);
+ (uint8_t *)&slv3_config, 1);
*val = slv3_config. batch_ext_sens_3_en;
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -7007,16 +8089,21 @@ int32_t ism330dhcx_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_den_mode_set(stmdev_ctx_t *ctx, ism330dhcx_den_mode_t val)
+int32_t ism330dhcx_den_mode_set(stmdev_ctx_t *ctx,
+ ism330dhcx_den_mode_t val)
{
ism330dhcx_ctrl6_c_t ctrl6_c;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL6_C,
+ (uint8_t *)&ctrl6_c, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
- ctrl6_c.den_mode= (uint8_t)val;
- ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ if (ret == 0)
+ {
+ ctrl6_c.den_mode = (uint8_t)val;
+ ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL6_C,
+ (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -7029,33 +8116,40 @@ int32_t ism330dhcx_den_mode_set(stmdev_ctx_t *ctx, ism330dhcx_den_mode_t val)
*
*/
int32_t ism330dhcx_den_mode_get(stmdev_ctx_t *ctx,
- ism330dhcx_den_mode_t *val)
+ ism330dhcx_den_mode_t *val)
{
ism330dhcx_ctrl6_c_t ctrl6_c;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL6_C,
+ (uint8_t *)&ctrl6_c, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
-
- switch (ctrl6_c.den_mode){
+ switch (ctrl6_c.den_mode)
+ {
case ISM330DHCX_DEN_DISABLE:
*val = ISM330DHCX_DEN_DISABLE;
break;
+
case ISM330DHCX_LEVEL_FIFO:
*val = ISM330DHCX_LEVEL_FIFO;
break;
+
case ISM330DHCX_LEVEL_LETCHED:
*val = ISM330DHCX_LEVEL_LETCHED;
break;
+
case ISM330DHCX_LEVEL_TRIGGER:
*val = ISM330DHCX_LEVEL_TRIGGER;
break;
+
case ISM330DHCX_EDGE_TRIGGER:
*val = ISM330DHCX_EDGE_TRIGGER;
break;
+
default:
*val = ISM330DHCX_DEN_DISABLE;
break;
}
+
return ret;
}
@@ -7068,17 +8162,20 @@ int32_t ism330dhcx_den_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_den_polarity_set(stmdev_ctx_t *ctx,
- ism330dhcx_den_lh_t val)
+ ism330dhcx_den_lh_t val)
{
ism330dhcx_ctrl9_xl_t ctrl9_xl;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
- ctrl9_xl.den_lh= (uint8_t)val;
+ if (ret == 0)
+ {
+ ctrl9_xl.den_lh = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
+ (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -7091,24 +8188,28 @@ int32_t ism330dhcx_den_polarity_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_den_polarity_get(stmdev_ctx_t *ctx,
- ism330dhcx_den_lh_t *val)
+ ism330dhcx_den_lh_t *val)
{
ism330dhcx_ctrl9_xl_t ctrl9_xl;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
-
- switch (ctrl9_xl.den_lh){
+ switch (ctrl9_xl.den_lh)
+ {
case ISM330DHCX_DEN_ACT_LOW:
*val = ISM330DHCX_DEN_ACT_LOW;
break;
+
case ISM330DHCX_DEN_ACT_HIGH:
*val = ISM330DHCX_DEN_ACT_HIGH;
break;
+
default:
*val = ISM330DHCX_DEN_ACT_LOW;
break;
}
+
return ret;
}
@@ -7121,17 +8222,20 @@ int32_t ism330dhcx_den_polarity_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_den_enable_set(stmdev_ctx_t *ctx,
- ism330dhcx_den_xl_g_t val)
+ ism330dhcx_den_xl_g_t val)
{
ism330dhcx_ctrl9_xl_t ctrl9_xl;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
- ctrl9_xl.den_xl_g= (uint8_t)val;
+ if (ret == 0)
+ {
+ ctrl9_xl.den_xl_g = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
+ (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -7144,27 +8248,32 @@ int32_t ism330dhcx_den_enable_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_den_enable_get(stmdev_ctx_t *ctx,
- ism330dhcx_den_xl_g_t *val)
+ ism330dhcx_den_xl_g_t *val)
{
ism330dhcx_ctrl9_xl_t ctrl9_xl;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
-
- switch (ctrl9_xl.den_xl_g){
+ switch (ctrl9_xl.den_xl_g)
+ {
case ISM330DHCX_STAMP_IN_GY_DATA:
*val = ISM330DHCX_STAMP_IN_GY_DATA;
break;
+
case ISM330DHCX_STAMP_IN_XL_DATA:
*val = ISM330DHCX_STAMP_IN_XL_DATA;
break;
+
case ISM330DHCX_STAMP_IN_GY_XL_DATA:
*val = ISM330DHCX_STAMP_IN_GY_XL_DATA;
break;
+
default:
*val = ISM330DHCX_STAMP_IN_GY_DATA;
break;
}
+
return ret;
}
@@ -7180,13 +8289,16 @@ int32_t ism330dhcx_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_ctrl9_xl_t ctrl9_xl;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
- ctrl9_xl.den_z= (uint8_t)val;
+ if (ret == 0)
+ {
+ ctrl9_xl.den_z = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
+ (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -7198,12 +8310,13 @@ int32_t ism330dhcx_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dhcx_den_mark_axis_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dhcx_ctrl9_xl_t ctrl9_xl;
int32_t ret;
-
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
*val = ctrl9_xl.den_z;
return ret;
@@ -7221,13 +8334,16 @@ int32_t ism330dhcx_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_ctrl9_xl_t ctrl9_xl;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
- ctrl9_xl.den_y= (uint8_t)val;
+ if (ret == 0)
+ {
+ ctrl9_xl.den_y = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
+ (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -7239,12 +8355,13 @@ int32_t ism330dhcx_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dhcx_den_mark_axis_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dhcx_ctrl9_xl_t ctrl9_xl;
int32_t ret;
-
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
*val = ctrl9_xl.den_y;
return ret;
@@ -7262,13 +8379,16 @@ int32_t ism330dhcx_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_ctrl9_xl_t ctrl9_xl;
int32_t ret;
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
- ctrl9_xl.den_x= (uint8_t)val;
+ if (ret == 0)
+ {
+ ctrl9_xl.den_x = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
+ (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -7280,12 +8400,13 @@ int32_t ism330dhcx_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dhcx_den_mark_axis_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dhcx_ctrl9_xl_t ctrl9_xl;
int32_t ret;
-
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
*val = ctrl9_xl.den_x;
return ret;
@@ -7315,21 +8436,26 @@ int32_t ism330dhcx_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_emb_func_en_a_t emb_func_en_a;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
+ (uint8_t *)&emb_func_en_a, 1);
}
- if(ret == 0){
- emb_func_en_a.pedo_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ emb_func_en_a.pedo_en = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
+ (uint8_t *)&emb_func_en_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -7345,17 +8471,20 @@ int32_t ism330dhcx_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dhcx_emb_func_en_a_t emb_func_en_a;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
+ (uint8_t *)&emb_func_en_a, 1);
*val = emb_func_en_a.pedo_en;
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -7367,21 +8496,25 @@ int32_t ism330dhcx_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dhcx_pedo_step_detect_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dhcx_emb_func_status_t emb_func_status;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_STATUS,
- (uint8_t*)&emb_func_status, 1);
+ (uint8_t *)&emb_func_status, 1);
*val = emb_func_status.is_step_det;
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -7393,10 +8526,13 @@ int32_t ism330dhcx_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t ism330dhcx_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
- ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_PEDO_DEB_STEPS_CONF, buff);
+ ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_PEDO_DEB_STEPS_CONF,
+ buff);
+
return ret;
}
@@ -7408,10 +8544,13 @@ int32_t ism330dhcx_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t ism330dhcx_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
- ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_PEDO_DEB_STEPS_CONF, buff);
+ ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_PEDO_DEB_STEPS_CONF,
+ buff);
+
return ret;
}
@@ -7423,19 +8562,22 @@ int32_t ism330dhcx_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_pedo_steps_period_set(stmdev_ctx_t *ctx, uint16_t val)
+int32_t ism330dhcx_pedo_steps_period_set(stmdev_ctx_t *ctx,
+ uint16_t val)
{
uint8_t buff[2];
int32_t ret;
-
- buff[1] = (uint8_t) (val / 256U);
- buff[0] = (uint8_t) (val - (buff[1] * 256U));
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_PEDO_SC_DELTAT_L,
&buff[0]);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_PEDO_SC_DELTAT_H,
- &buff[1]);
+ &buff[1]);
}
+
return ret;
}
@@ -7447,18 +8589,22 @@ int32_t ism330dhcx_pedo_steps_period_set(stmdev_ctx_t *ctx, uint16_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_pedo_steps_period_get(stmdev_ctx_t *ctx, uint16_t *val)
+int32_t ism330dhcx_pedo_steps_period_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
uint8_t buff[2];
int32_t ret;
+ ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_PEDO_SC_DELTAT_L,
+ &buff[0]);
- ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_PEDO_SC_DELTAT_L, &buff[0]);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_PEDO_SC_DELTAT_H,
&buff[1]);
*val = buff[1];
*val = (*val * 256U) + buff[0];
}
+
return ret;
}
@@ -7476,15 +8622,16 @@ int32_t ism330dhcx_pedo_int_mode_set(stmdev_ctx_t *ctx,
{
ism330dhcx_pedo_cmd_reg_t pedo_cmd_reg;
int32_t ret;
-
ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_PEDO_CMD_REG,
- (uint8_t*)&pedo_cmd_reg);
+ (uint8_t *)&pedo_cmd_reg);
- if(ret == 0){
- pedo_cmd_reg.carry_count_en= (uint8_t)val;
+ if (ret == 0)
+ {
+ pedo_cmd_reg.carry_count_en = (uint8_t)val;
ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_PEDO_CMD_REG,
- (uint8_t*)&pedo_cmd_reg);
+ (uint8_t *)&pedo_cmd_reg);
}
+
return ret;
}
@@ -7502,21 +8649,24 @@ int32_t ism330dhcx_pedo_int_mode_get(stmdev_ctx_t *ctx,
{
ism330dhcx_pedo_cmd_reg_t pedo_cmd_reg;
int32_t ret;
-
ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_PEDO_CMD_REG,
- (uint8_t*)&pedo_cmd_reg);
+ (uint8_t *)&pedo_cmd_reg);
- switch (pedo_cmd_reg.carry_count_en){
+ switch (pedo_cmd_reg.carry_count_en)
+ {
case ISM330DHCX_EVERY_STEP:
*val = ISM330DHCX_EVERY_STEP;
break;
+
case ISM330DHCX_COUNT_OVERFLOW:
*val = ISM330DHCX_COUNT_OVERFLOW;
break;
+
default:
*val = ISM330DHCX_EVERY_STEP;
break;
}
+
return ret;
}
@@ -7545,21 +8695,26 @@ int32_t ism330dhcx_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_emb_func_en_a_t emb_func_en_a;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
+ (uint8_t *)&emb_func_en_a, 1);
}
- if(ret == 0){
- emb_func_en_a.sign_motion_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ emb_func_en_a.sign_motion_en = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
+ (uint8_t *)&emb_func_en_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -7575,17 +8730,20 @@ int32_t ism330dhcx_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dhcx_emb_func_en_a_t emb_func_en_a;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
+ (uint8_t *)&emb_func_en_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = emb_func_en_a.sign_motion_en;
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -7602,16 +8760,20 @@ int32_t ism330dhcx_motion_flag_data_ready_get(stmdev_ctx_t *ctx,
{
ism330dhcx_emb_func_status_t emb_func_status;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_STATUS,
- (uint8_t*)&emb_func_status, 1);
+ (uint8_t *)&emb_func_status, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = emb_func_status.is_sigmot;
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -7640,20 +8802,26 @@ int32_t ism330dhcx_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_emb_func_en_a_t emb_func_en_a;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
+ (uint8_t *)&emb_func_en_a, 1);
}
- if(ret == 0){
- emb_func_en_a.tilt_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ emb_func_en_a.tilt_en = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
+ (uint8_t *)&emb_func_en_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -7669,16 +8837,20 @@ int32_t ism330dhcx_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dhcx_emb_func_en_a_t emb_func_en_a;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
+ (uint8_t *)&emb_func_en_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = emb_func_en_a.tilt_en;
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -7695,16 +8867,20 @@ int32_t ism330dhcx_tilt_flag_data_ready_get(stmdev_ctx_t *ctx,
{
ism330dhcx_emb_func_status_t emb_func_status;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_STATUS,
- (uint8_t*)&emb_func_status, 1);
+ (uint8_t *)&emb_func_status, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = emb_func_status.is_tilt;
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -7729,20 +8905,22 @@ int32_t ism330dhcx_tilt_flag_data_ready_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val)
+int32_t ism330dhcx_mag_sensitivity_set(stmdev_ctx_t *ctx,
+ uint16_t val)
{
uint8_t buff[2];
int32_t ret;
-
- buff[1] = (uint8_t) (val / 256U);
- buff[0] = (uint8_t) (val - (buff[1] * 256U));
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SENSITIVITY_L,
&buff[0]);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SENSITIVITY_H,
&buff[1]);
}
+
return ret;
}
@@ -7754,20 +8932,22 @@ int32_t ism330dhcx_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val)
+int32_t ism330dhcx_mag_sensitivity_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
uint8_t buff[2];
int32_t ret;
-
ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SENSITIVITY_L,
&buff[0]);
-if(ret == 0){
- ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SENSITIVITY_H,
- &buff[1]);
- *val = buff[1];
- *val = (*val * 256U) + buff[0];
-}
+ if (ret == 0)
+ {
+ ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SENSITIVITY_H,
+ &buff[1]);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
+ }
+
return ret;
}
@@ -7784,36 +8964,51 @@ int32_t ism330dhcx_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val)
uint8_t buff[6];
int32_t ret;
uint8_t i;
-
- buff[1] = (uint8_t) ((uint16_t)val[0] / 256U);
- buff[0] = (uint8_t) ((uint16_t)val[0] - (buff[1] * 256U));
- buff[3] = (uint8_t) ((uint16_t)val[1] / 256U);
- buff[2] = (uint8_t) ((uint16_t)val[1] - (buff[3] * 256U));
- buff[5] = (uint8_t) ((uint16_t)val[2] / 256U);
- buff[4] = (uint8_t) ((uint16_t)val[2] - (buff[5] * 256U));
-
+ buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
+ buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
+ buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
+ buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
+ buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
+ buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
i = 0x00U;
- ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_OFFX_L, &buff[i]);
- if(ret == 0){
+ ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_OFFX_L,
+ &buff[i]);
+
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_OFFX_H, &buff[i]);
+ ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_OFFX_H,
+ &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_OFFY_L, &buff[i]);
+ ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_OFFY_L,
+ &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_OFFY_H, &buff[i]);
+ ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_OFFY_H,
+ &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_OFFZ_L, &buff[i]);
+ ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_OFFZ_L,
+ &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_OFFZ_H, &buff[i]);
+ ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_OFFZ_H,
+ &buff[i]);
}
+
return ret;
}
@@ -7830,30 +9025,45 @@ int32_t ism330dhcx_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val)
uint8_t buff[6];
int32_t ret;
uint8_t i;
-
i = 0x00U;
- ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_OFFX_L, &buff[i]);
+ ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_OFFX_L,
+ &buff[i]);
- if(ret == 0){
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_OFFX_H, &buff[i]);
+ ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_OFFX_H,
+ &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_OFFY_L, &buff[i]);
+ ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_OFFY_L,
+ &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_OFFY_H, &buff[i]);
+ ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_OFFY_H,
+ &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_OFFZ_L, &buff[i]);
+ ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_OFFZ_L,
+ &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_OFFZ_H, &buff[i]);
+ ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_OFFZ_H,
+ &buff[i]);
}
+
val[0] = (int16_t)buff[1];
val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
@@ -7882,66 +9092,99 @@ int32_t ism330dhcx_mag_soft_iron_set(stmdev_ctx_t *ctx, uint16_t *val)
uint8_t buff[12];
int32_t ret;
uint8_t i;
-
- buff[1] = (uint8_t) (val[0] / 256U);
- buff[0] = (uint8_t) (val[0] - (buff[1] * 256U));
- buff[3] = (uint8_t) (val[1] / 256U);
- buff[2] = (uint8_t) (val[1] - (buff[3] * 256U));
- buff[5] = (uint8_t) (val[2] / 256U);
- buff[4] = (uint8_t) (val[2] - (buff[5] * 256U));
- buff[7] = (uint8_t) (val[3] / 256U);
- buff[6] = (uint8_t) (val[3] - (buff[1] * 256U));
- buff[9] = (uint8_t) (val[4] / 256U);
- buff[8] = (uint8_t) (val[4] - (buff[3] * 256U));
- buff[11] = (uint8_t) (val[5] / 256U);
- buff[10] = (uint8_t) (val[5] - (buff[5] * 256U));
-
+ buff[1] = (uint8_t)(val[0] / 256U);
+ buff[0] = (uint8_t)(val[0] - (buff[1] * 256U));
+ buff[3] = (uint8_t)(val[1] / 256U);
+ buff[2] = (uint8_t)(val[1] - (buff[3] * 256U));
+ buff[5] = (uint8_t)(val[2] / 256U);
+ buff[4] = (uint8_t)(val[2] - (buff[5] * 256U));
+ buff[7] = (uint8_t)(val[3] / 256U);
+ buff[6] = (uint8_t)(val[3] - (buff[1] * 256U));
+ buff[9] = (uint8_t)(val[4] / 256U);
+ buff[8] = (uint8_t)(val[4] - (buff[3] * 256U));
+ buff[11] = (uint8_t)(val[5] / 256U);
+ buff[10] = (uint8_t)(val[5] - (buff[5] * 256U));
i = 0x00U;
- ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_XX_L, &buff[i]);
- if(ret == 0){
+ ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_XX_L,
+ &buff[i]);
+
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_XX_H, &buff[i]);
+ ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_XX_H,
+ &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_XY_L, &buff[i]);
+ ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_XY_L,
+ &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_XY_H, &buff[i]);
+ ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_XY_H,
+ &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_XZ_L, &buff[i]);
+ ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_XZ_L,
+ &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_XZ_H, &buff[i]);
+ ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_XZ_H,
+ &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_YY_L, &buff[i]);
+ ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_YY_L,
+ &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_YY_H, &buff[i]);
+ ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_YY_H,
+ &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_YZ_L, &buff[i]);
+ ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_YZ_L,
+ &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_YZ_H, &buff[i]);
+ ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_YZ_H,
+ &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_ZZ_L, &buff[i]);
+ ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_ZZ_L,
+ &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_ZZ_H, &buff[i]);
+ ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_SI_ZZ_H,
+ &buff[i]);
}
+
return ret;
}
@@ -7963,54 +9206,87 @@ int32_t ism330dhcx_mag_soft_iron_get(stmdev_ctx_t *ctx, uint16_t *val)
uint8_t buff[12];
int32_t ret;
uint8_t i;
-
i = 0x00U;
- ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_XX_L, &buff[i]);
- if(ret == 0){
+ ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_XX_L,
+ &buff[i]);
+
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_XX_H, &buff[i]);
+ ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_XX_H,
+ &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_XY_L, &buff[i]);
+ ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_XY_L,
+ &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_XY_H, &buff[i]);
+ ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_XY_H,
+ &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_XZ_L, &buff[i]);
+ ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_XZ_L,
+ &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_XZ_H, &buff[i]);
+ ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_XZ_H,
+ &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_YY_L, &buff[i]);
+ ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_YY_L,
+ &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_YY_H, &buff[i]);
+ ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_YY_H,
+ &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_YZ_L, &buff[i]);
- }
- if(ret == 0){
+ ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_YZ_L,
+ &buff[i]);
+ }
+
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_YZ_H, &buff[i]);
- }
- if(ret == 0){
+ ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_YZ_H,
+ &buff[i]);
+ }
+
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_ZZ_L, &buff[i]);
- }
- if(ret == 0){
+ ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_ZZ_L,
+ &buff[i]);
+ }
+
+ if (ret == 0)
+ {
i++;
- ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_ZZ_H, &buff[i]);
+ ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SI_ZZ_H,
+ &buff[i]);
}
-
+
val[0] = buff[1];
val[0] = (val[0] * 256U) + buff[0];
val[1] = buff[3];
@@ -8023,7 +9299,7 @@ int32_t ism330dhcx_mag_soft_iron_get(stmdev_ctx_t *ctx, uint16_t *val)
val[4] = (val[4] * 256U) + buff[8];
val[5] = buff[11];
val[6] = (val[5] * 256U) + buff[10];
-
+
return ret;
}
@@ -8041,15 +9317,16 @@ int32_t ism330dhcx_mag_z_orient_set(stmdev_ctx_t *ctx,
{
ism330dhcx_mag_cfg_a_t mag_cfg_a;
int32_t ret;
-
ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_CFG_A,
- (uint8_t*)&mag_cfg_a);
+ (uint8_t *)&mag_cfg_a);
- if(ret == 0){
- mag_cfg_a.mag_z_axis= (uint8_t)val;
+ if (ret == 0)
+ {
+ mag_cfg_a.mag_z_axis = (uint8_t)val;
ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_CFG_A,
- (uint8_t*)&mag_cfg_a);
+ (uint8_t *)&mag_cfg_a);
}
+
return ret;
}
@@ -8068,31 +9345,39 @@ int32_t ism330dhcx_mag_z_orient_get(stmdev_ctx_t *ctx,
ism330dhcx_mag_cfg_a_t mag_cfg_a;
int32_t ret;
ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_CFG_A,
- (uint8_t*)&mag_cfg_a);
+ (uint8_t *)&mag_cfg_a);
- switch (mag_cfg_a.mag_z_axis){
+ switch (mag_cfg_a.mag_z_axis)
+ {
case ISM330DHCX_Z_EQ_Y:
*val = ISM330DHCX_Z_EQ_Y;
break;
+
case ISM330DHCX_Z_EQ_MIN_Y:
*val = ISM330DHCX_Z_EQ_MIN_Y;
break;
+
case ISM330DHCX_Z_EQ_X:
*val = ISM330DHCX_Z_EQ_X;
break;
+
case ISM330DHCX_Z_EQ_MIN_X:
*val = ISM330DHCX_Z_EQ_MIN_X;
break;
+
case ISM330DHCX_Z_EQ_MIN_Z:
*val = ISM330DHCX_Z_EQ_MIN_Z;
break;
+
case ISM330DHCX_Z_EQ_Z:
*val = ISM330DHCX_Z_EQ_Z;
break;
+
default:
*val = ISM330DHCX_Z_EQ_Y;
break;
}
+
return ret;
}
@@ -8107,18 +9392,20 @@ int32_t ism330dhcx_mag_z_orient_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_mag_y_orient_set(stmdev_ctx_t *ctx,
- ism330dhcx_mag_y_axis_t val)
+ ism330dhcx_mag_y_axis_t val)
{
ism330dhcx_mag_cfg_a_t mag_cfg_a;
int32_t ret;
-
ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_CFG_A,
- (uint8_t*)&mag_cfg_a);
- if(ret == 0){
- mag_cfg_a.mag_y_axis= (uint8_t)val;
+ (uint8_t *)&mag_cfg_a);
+
+ if (ret == 0)
+ {
+ mag_cfg_a.mag_y_axis = (uint8_t)val;
ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_CFG_A,
- (uint8_t*)&mag_cfg_a);
+ (uint8_t *)&mag_cfg_a);
}
+
return ret;
}
@@ -8132,37 +9419,44 @@ int32_t ism330dhcx_mag_y_orient_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_mag_y_orient_get(stmdev_ctx_t *ctx,
- ism330dhcx_mag_y_axis_t *val)
+ ism330dhcx_mag_y_axis_t *val)
{
ism330dhcx_mag_cfg_a_t mag_cfg_a;
int32_t ret;
-
ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_CFG_A,
- (uint8_t*)&mag_cfg_a);
+ (uint8_t *)&mag_cfg_a);
- switch (mag_cfg_a.mag_y_axis){
+ switch (mag_cfg_a.mag_y_axis)
+ {
case ISM330DHCX_Y_EQ_Y:
*val = ISM330DHCX_Y_EQ_Y;
break;
+
case ISM330DHCX_Y_EQ_MIN_Y:
*val = ISM330DHCX_Y_EQ_MIN_Y;
break;
+
case ISM330DHCX_Y_EQ_X:
*val = ISM330DHCX_Y_EQ_X;
break;
+
case ISM330DHCX_Y_EQ_MIN_X:
*val = ISM330DHCX_Y_EQ_MIN_X;
break;
+
case ISM330DHCX_Y_EQ_MIN_Z:
*val = ISM330DHCX_Y_EQ_MIN_Z;
break;
+
case ISM330DHCX_Y_EQ_Z:
*val = ISM330DHCX_Y_EQ_Z;
break;
+
default:
*val = ISM330DHCX_Y_EQ_Y;
break;
}
+
return ret;
}
@@ -8176,18 +9470,20 @@ int32_t ism330dhcx_mag_y_orient_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_mag_x_orient_set(stmdev_ctx_t *ctx,
- ism330dhcx_mag_x_axis_t val)
+ ism330dhcx_mag_x_axis_t val)
{
ism330dhcx_mag_cfg_b_t mag_cfg_b;
int32_t ret;
-
ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_CFG_B,
- (uint8_t*)&mag_cfg_b);
- if(ret == 0){
- mag_cfg_b.mag_x_axis= (uint8_t)val;
+ (uint8_t *)&mag_cfg_b);
+
+ if (ret == 0)
+ {
+ mag_cfg_b.mag_x_axis = (uint8_t)val;
ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_MAG_CFG_B,
- (uint8_t*)&mag_cfg_b);
+ (uint8_t *)&mag_cfg_b);
}
+
return ret;
}
@@ -8201,37 +9497,44 @@ int32_t ism330dhcx_mag_x_orient_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_mag_x_orient_get(stmdev_ctx_t *ctx,
- ism330dhcx_mag_x_axis_t *val)
+ ism330dhcx_mag_x_axis_t *val)
{
ism330dhcx_mag_cfg_b_t mag_cfg_b;
int32_t ret;
-
ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_CFG_B,
- (uint8_t*)&mag_cfg_b);
+ (uint8_t *)&mag_cfg_b);
- switch (mag_cfg_b.mag_x_axis){
+ switch (mag_cfg_b.mag_x_axis)
+ {
case ISM330DHCX_X_EQ_Y:
*val = ISM330DHCX_X_EQ_Y;
break;
+
case ISM330DHCX_X_EQ_MIN_Y:
*val = ISM330DHCX_X_EQ_MIN_Y;
break;
+
case ISM330DHCX_X_EQ_X:
*val = ISM330DHCX_X_EQ_X;
break;
+
case ISM330DHCX_X_EQ_MIN_X:
*val = ISM330DHCX_X_EQ_MIN_X;
break;
+
case ISM330DHCX_X_EQ_MIN_Z:
*val = ISM330DHCX_X_EQ_MIN_Z;
break;
+
case ISM330DHCX_X_EQ_Z:
*val = ISM330DHCX_X_EQ_Z;
break;
+
default:
*val = ISM330DHCX_X_EQ_Y;
break;
}
+
return ret;
}
@@ -8258,20 +9561,24 @@ int32_t ism330dhcx_mag_x_orient_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
ism330dhcx_emb_func_status_t emb_func_status;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_STATUS,
- (uint8_t*)&emb_func_status, 1);
+ (uint8_t *)&emb_func_status, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = emb_func_status.is_fsm_lc;
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -8287,21 +9594,26 @@ int32_t ism330dhcx_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val)
{
int32_t ret;
ism330dhcx_emb_func_en_b_t emb_func_en_b;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if(ret == 0){
- emb_func_en_b.fsm_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ emb_func_en_b.fsm_en = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -8317,20 +9629,26 @@ int32_t ism330dhcx_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val)
{
int32_t ret;
ism330dhcx_emb_func_en_b_t emb_func_en_b;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = emb_func_en_b.fsm_en;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -8343,54 +9661,69 @@ int32_t ism330dhcx_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t ism330dhcx_fsm_enable_set(stmdev_ctx_t *ctx,
- ism330dhcx_emb_fsm_enable_t *val)
+ ism330dhcx_emb_fsm_enable_t *val)
{
ism330dhcx_emb_func_en_b_t emb_func_en_b;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FSM_ENABLE_A,
- (uint8_t*)&val->fsm_enable_a, 1);
+ (uint8_t *)&val->fsm_enable_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FSM_ENABLE_B,
- (uint8_t*)&val->fsm_enable_b, 1);
+ (uint8_t *)&val->fsm_enable_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
- }
- if(ret == 0){
- if ( (val->fsm_enable_a.fsm1_en |
- val->fsm_enable_a.fsm2_en |
- val->fsm_enable_a.fsm3_en |
- val->fsm_enable_a.fsm4_en |
- val->fsm_enable_a.fsm5_en |
- val->fsm_enable_a.fsm6_en |
- val->fsm_enable_a.fsm7_en |
- val->fsm_enable_a.fsm8_en |
- val->fsm_enable_b.fsm9_en |
- val->fsm_enable_b.fsm10_en |
- val->fsm_enable_b.fsm11_en |
- val->fsm_enable_b.fsm12_en |
- val->fsm_enable_b.fsm13_en |
- val->fsm_enable_b.fsm14_en |
- val->fsm_enable_b.fsm15_en |
- val->fsm_enable_b.fsm16_en ) != PROPERTY_DISABLE){
+ (uint8_t *)&emb_func_en_b, 1);
+ }
+
+ if (ret == 0)
+ {
+ if ((val->fsm_enable_a.fsm1_en |
+ val->fsm_enable_a.fsm2_en |
+ val->fsm_enable_a.fsm3_en |
+ val->fsm_enable_a.fsm4_en |
+ val->fsm_enable_a.fsm5_en |
+ val->fsm_enable_a.fsm6_en |
+ val->fsm_enable_a.fsm7_en |
+ val->fsm_enable_a.fsm8_en |
+ val->fsm_enable_b.fsm9_en |
+ val->fsm_enable_b.fsm10_en |
+ val->fsm_enable_b.fsm11_en |
+ val->fsm_enable_b.fsm12_en |
+ val->fsm_enable_b.fsm13_en |
+ val->fsm_enable_b.fsm14_en |
+ val->fsm_enable_b.fsm15_en |
+ val->fsm_enable_b.fsm16_en) != PROPERTY_DISABLE)
+ {
emb_func_en_b.fsm_en = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
emb_func_en_b.fsm_en = PROPERTY_DISABLE;
}
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -8403,22 +9736,28 @@ int32_t ism330dhcx_fsm_enable_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_fsm_enable_get(stmdev_ctx_t *ctx,
- ism330dhcx_emb_fsm_enable_t *val)
+ ism330dhcx_emb_fsm_enable_t *val)
{
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FSM_ENABLE_A,
- (uint8_t*)&val->fsm_enable_a, 1);
+ (uint8_t *)&val->fsm_enable_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FSM_ENABLE_B,
- (uint8_t*)&val->fsm_enable_b, 1);
+ (uint8_t *)&val->fsm_enable_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -8435,17 +9774,21 @@ int32_t ism330dhcx_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val)
{
uint8_t buff[2];
int32_t ret;
-
- buff[1] = (uint8_t) (val / 256U);
- buff[0] = (uint8_t) (val - (buff[1] * 256U));
-
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
- ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FSM_LONG_COUNTER_L, buff, 2);
+
+ if (ret == 0)
+ {
+ ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FSM_LONG_COUNTER_L, buff,
+ 2);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -8462,16 +9805,21 @@ int32_t ism330dhcx_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val)
{
uint8_t buff[2];
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
- ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FSM_LONG_COUNTER_L, buff, 2);
+
+ if (ret == 0)
+ {
+ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FSM_LONG_COUNTER_L, buff,
+ 2);
*val = buff[1];
*val = (*val * 256U) + buff[0];
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -8485,24 +9833,30 @@ int32_t ism330dhcx_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val)
*
*/
int32_t ism330dhcx_long_clr_set(stmdev_ctx_t *ctx,
- ism330dhcx_fsm_lc_clr_t val)
+ ism330dhcx_fsm_lc_clr_t val)
{
ism330dhcx_fsm_long_counter_clear_t fsm_long_counter_clear;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FSM_LONG_COUNTER_CLEAR,
- (uint8_t*)&fsm_long_counter_clear, 1);
+ (uint8_t *)&fsm_long_counter_clear, 1);
}
- if(ret == 0){
- fsm_long_counter_clear.fsm_lc_clr= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ fsm_long_counter_clear.fsm_lc_clr = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_FSM_LONG_COUNTER_CLEAR,
- (uint8_t*)&fsm_long_counter_clear, 1);
+ (uint8_t *)&fsm_long_counter_clear, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -8515,34 +9869,42 @@ int32_t ism330dhcx_long_clr_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_long_clr_get(stmdev_ctx_t *ctx,
- ism330dhcx_fsm_lc_clr_t *val)
+ ism330dhcx_fsm_lc_clr_t *val)
{
ism330dhcx_fsm_long_counter_clear_t fsm_long_counter_clear;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FSM_LONG_COUNTER_CLEAR,
- (uint8_t*)&fsm_long_counter_clear, 1);
+ (uint8_t *)&fsm_long_counter_clear, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
- switch (fsm_long_counter_clear.fsm_lc_clr){
+
+ switch (fsm_long_counter_clear.fsm_lc_clr)
+ {
case ISM330DHCX_LC_NORMAL:
*val = ISM330DHCX_LC_NORMAL;
break;
+
case ISM330DHCX_LC_CLEAR:
*val = ISM330DHCX_LC_CLEAR;
break;
+
case ISM330DHCX_LC_CLEAR_DONE:
*val = ISM330DHCX_LC_CLEAR_DONE;
break;
+
default:
*val = ISM330DHCX_LC_NORMAL;
break;
}
+
return ret;
}
@@ -8558,16 +9920,19 @@ int32_t ism330dhcx_fsm_out_get(stmdev_ctx_t *ctx,
ism330dhcx_fsm_out_t *val)
{
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FSM_OUTS1,
- (uint8_t*)&val->fsm_outs1, 16);
+ (uint8_t *)&val->fsm_outs1, 16);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -8580,27 +9945,32 @@ int32_t ism330dhcx_fsm_out_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_fsm_data_rate_set(stmdev_ctx_t *ctx,
- ism330dhcx_fsm_odr_t val)
+ ism330dhcx_fsm_odr_t val)
{
ism330dhcx_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_ODR_CFG_B,
- (uint8_t*)&emb_func_odr_cfg_b, 1);
+ (uint8_t *)&emb_func_odr_cfg_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
emb_func_odr_cfg_b.not_used_01 = 3; /* set default values */
emb_func_odr_cfg_b.not_used_02 = 1; /* set default values */
- emb_func_odr_cfg_b.fsm_odr= (uint8_t)val;
+ emb_func_odr_cfg_b.fsm_odr = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_ODR_CFG_B,
- (uint8_t*)&emb_func_odr_cfg_b, 1);
- }
- if(ret == 0){
+ (uint8_t *)&emb_func_odr_cfg_b, 1);
+ }
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -8613,37 +9983,46 @@ int32_t ism330dhcx_fsm_data_rate_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_fsm_data_rate_get(stmdev_ctx_t *ctx,
- ism330dhcx_fsm_odr_t *val)
+ ism330dhcx_fsm_odr_t *val)
{
ism330dhcx_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_ODR_CFG_B,
- (uint8_t*)&emb_func_odr_cfg_b, 1);
+ (uint8_t *)&emb_func_odr_cfg_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
- switch (emb_func_odr_cfg_b.fsm_odr){
+
+ switch (emb_func_odr_cfg_b.fsm_odr)
+ {
case ISM330DHCX_ODR_FSM_12Hz5:
*val = ISM330DHCX_ODR_FSM_12Hz5;
break;
+
case ISM330DHCX_ODR_FSM_26Hz:
*val = ISM330DHCX_ODR_FSM_26Hz;
break;
+
case ISM330DHCX_ODR_FSM_52Hz:
*val = ISM330DHCX_ODR_FSM_52Hz;
break;
+
case ISM330DHCX_ODR_FSM_104Hz:
*val = ISM330DHCX_ODR_FSM_104Hz;
break;
+
default:
*val = ISM330DHCX_ODR_FSM_12Hz5;
break;
}
+
return ret;
}
@@ -8659,21 +10038,26 @@ int32_t ism330dhcx_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_emb_func_init_b_t emb_func_init_b;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_INIT_B,
- (uint8_t*)&emb_func_init_b, 1);
+ (uint8_t *)&emb_func_init_b, 1);
}
- if(ret == 0){
- emb_func_init_b.fsm_init= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ emb_func_init_b.fsm_init = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_INIT_B,
- (uint8_t*)&emb_func_init_b, 1);
+ (uint8_t *)&emb_func_init_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -8689,16 +10073,20 @@ int32_t ism330dhcx_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dhcx_emb_func_init_b_t emb_func_init_b;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_INIT_B,
- (uint8_t*)&emb_func_init_b, 1);
+ (uint8_t *)&emb_func_init_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = emb_func_init_b.fsm_init;
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -8713,24 +10101,25 @@ int32_t ism330dhcx_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint16_t val)
+int32_t ism330dhcx_long_cnt_int_value_set(stmdev_ctx_t *ctx,
+ uint16_t val)
{
uint8_t buff[2];
int32_t ret;
uint8_t i;
-
- buff[1] = (uint8_t) (val / 256U);
- buff[0] = (uint8_t) (val - (buff[1] * 256U));
-
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
i = 0x00U;
ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_FSM_LC_TIMEOUT_L,
&buff[i]);
- if(ret == 0){
+ if (ret == 0)
+ {
i++;
ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_FSM_LC_TIMEOUT_H,
- &buff[i]);
+ &buff[i]);
}
+
return ret;
}
@@ -8745,23 +10134,25 @@ int32_t ism330dhcx_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint16_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint16_t *val)
+int32_t ism330dhcx_long_cnt_int_value_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
uint8_t buff[2];
int32_t ret;
uint8_t i;
-
i = 0x00U;
ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_FSM_LC_TIMEOUT_L,
&buff[i]);
- if(ret == 0){
+ if (ret == 0)
+ {
i++;
ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_FSM_LC_TIMEOUT_H,
- &buff[i]);
+ &buff[i]);
*val = buff[1];
*val = (*val * 256U) + buff[0];
}
+
return ret;
}
@@ -8777,13 +10168,15 @@ int32_t ism330dhcx_fsm_number_of_programs_set(stmdev_ctx_t *ctx,
uint8_t *buff)
{
int32_t ret;
-
ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_FSM_PROGRAMS, buff);
- if(ret == 0){
- ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_FSM_PROGRAMS + 0x01U,
- buff);
+ if (ret == 0)
+ {
+ ret = ism330dhcx_ln_pg_write_byte(ctx,
+ ISM330DHCX_FSM_PROGRAMS + 0x01U,
+ buff);
}
+
return ret;
}
@@ -8796,10 +10189,9 @@ int32_t ism330dhcx_fsm_number_of_programs_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_fsm_number_of_programs_get(stmdev_ctx_t *ctx,
- uint8_t *buff)
+ uint8_t *buff)
{
int32_t ret;
-
ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_FSM_PROGRAMS, buff);
return ret;
@@ -8814,23 +10206,25 @@ int32_t ism330dhcx_fsm_number_of_programs_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val)
+int32_t ism330dhcx_fsm_start_address_set(stmdev_ctx_t *ctx,
+ uint16_t val)
{
uint8_t buff[2];
int32_t ret;
uint8_t i;
-
- buff[1] = (uint8_t) (val / 256U);
- buff[0] = (uint8_t) (val - (buff[1] * 256U));
-
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
i = 0x00U;
- ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_FSM_START_ADD_L, &buff[i]);
+ ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_FSM_START_ADD_L,
+ &buff[i]);
- if(ret == 0){
+ if (ret == 0)
+ {
i++;
ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_FSM_START_ADD_H,
&buff[i]);
}
+
return ret;
}
@@ -8843,22 +10237,25 @@ int32_t ism330dhcx_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val)
+int32_t ism330dhcx_fsm_start_address_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
uint8_t buff[2];
int32_t ret;
uint8_t i;
-
i = 0x00U;
- ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_FSM_START_ADD_L, &buff[i]);
+ ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_FSM_START_ADD_L,
+ &buff[i]);
- if(ret == 0){
+ if (ret == 0)
+ {
i++;
ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_FSM_START_ADD_H,
&buff[i]);
*val = buff[1];
*val = (*val * 256U) + buff[0];
}
+
return ret;
}
@@ -8888,29 +10285,39 @@ int32_t ism330dhcx_mlc_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_emb_func_en_b_t reg;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_EN_B,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.mlc_en = val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_EN_B,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if ((val != PROPERTY_DISABLE) && (ret == 0)){
+
+ if ((val != PROPERTY_DISABLE) && (ret == 0))
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_INIT_B,
- (uint8_t*)®, 1);
- if (ret == 0) {
+ (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.mlc_en = val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_INIT_B,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -8926,16 +10333,20 @@ int32_t ism330dhcx_mlc_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dhcx_emb_func_en_b_t reg;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_EN_B,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
*val = reg.mlc_en;
}
+
return ret;
}
@@ -8947,10 +10358,10 @@ int32_t ism330dhcx_mlc_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t ism330dhcx_mlc_status_get(stmdev_ctx_t *ctx,
- ism330dhcx_mlc_status_mainpage_t *val)
+ ism330dhcx_mlc_status_mainpage_t *val)
{
return ism330dhcx_read_reg(ctx, ISM330DHCX_MLC_STATUS_MAINPAGE,
- (uint8_t*) val, 1);
+ (uint8_t *) val, 1);
}
/**
@@ -8962,22 +10373,27 @@ int32_t ism330dhcx_mlc_status_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_mlc_data_rate_set(stmdev_ctx_t *ctx,
- ism330dhcx_mlc_odr_t val)
+ ism330dhcx_mlc_odr_t val)
{
ism330dhcx_emb_func_odr_cfg_c_t reg;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_ODR_CFG_C,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.mlc_odr = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_EMB_FUNC_ODR_CFG_C,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
@@ -8993,36 +10409,46 @@ int32_t ism330dhcx_mlc_data_rate_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_mlc_data_rate_get(stmdev_ctx_t *ctx,
- ism330dhcx_mlc_odr_t *val)
+ ism330dhcx_mlc_odr_t *val)
{
ism330dhcx_emb_func_odr_cfg_c_t reg;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_ODR_CFG_C,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
- switch (reg.mlc_odr) {
+
+ if (ret == 0)
+ {
+ switch (reg.mlc_odr)
+ {
case ISM330DHCX_ODR_PRGS_12Hz5:
*val = ISM330DHCX_ODR_PRGS_12Hz5;
break;
+
case ISM330DHCX_ODR_PRGS_26Hz:
*val = ISM330DHCX_ODR_PRGS_26Hz;
break;
+
case ISM330DHCX_ODR_PRGS_52Hz:
*val = ISM330DHCX_ODR_PRGS_52Hz;
break;
+
case ISM330DHCX_ODR_PRGS_104Hz:
*val = ISM330DHCX_ODR_PRGS_104Hz;
break;
+
default:
*val = ISM330DHCX_ODR_PRGS_12Hz5;
break;
}
+
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -9048,19 +10474,23 @@ int32_t ism330dhcx_mlc_data_rate_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_sh_read_data_raw_get(stmdev_ctx_t *ctx,
- ism330dhcx_emb_sh_read_t *val)
+ ism330dhcx_emb_sh_read_t *val,
+ uint8_t len)
{
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SENSOR_HUB_1,
- (uint8_t*)val, 18);
+ (uint8_t *)val, len);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -9077,21 +10507,26 @@ int32_t ism330dhcx_sh_slave_connected_set(stmdev_ctx_t *ctx,
{
ism330dhcx_master_config_t master_config;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- master_config.aux_sens_on= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ master_config.aux_sens_on = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -9108,33 +10543,42 @@ int32_t ism330dhcx_sh_slave_connected_get(stmdev_ctx_t *ctx,
{
ism330dhcx_master_config_t master_config;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
- switch (master_config.aux_sens_on){
+
+ switch (master_config.aux_sens_on)
+ {
case ISM330DHCX_SLV_0:
*val = ISM330DHCX_SLV_0;
break;
+
case ISM330DHCX_SLV_0_1:
*val = ISM330DHCX_SLV_0_1;
break;
+
case ISM330DHCX_SLV_0_1_2:
*val = ISM330DHCX_SLV_0_1_2;
break;
+
case ISM330DHCX_SLV_0_1_2_3:
*val = ISM330DHCX_SLV_0_1_2_3;
break;
+
default:
*val = ISM330DHCX_SLV_0;
break;
}
+
return ret;
}
@@ -9150,21 +10594,26 @@ int32_t ism330dhcx_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_master_config_t master_config;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- master_config.master_on= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ master_config.master_on = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -9180,17 +10629,20 @@ int32_t ism330dhcx_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dhcx_master_config_t master_config;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = master_config.master_on;
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -9203,25 +10655,30 @@ int32_t ism330dhcx_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t ism330dhcx_sh_pin_mode_set(stmdev_ctx_t *ctx,
- ism330dhcx_shub_pu_en_t val)
+ ism330dhcx_shub_pu_en_t val)
{
ism330dhcx_master_config_t master_config;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- master_config.shub_pu_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ master_config.shub_pu_en = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -9234,30 +10691,38 @@ int32_t ism330dhcx_sh_pin_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_sh_pin_mode_get(stmdev_ctx_t *ctx,
- ism330dhcx_shub_pu_en_t *val)
+ ism330dhcx_shub_pu_en_t *val)
{
ism330dhcx_master_config_t master_config;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
- switch (master_config.shub_pu_en){
+
+ switch (master_config.shub_pu_en)
+ {
case ISM330DHCX_EXT_PULL_UP:
*val = ISM330DHCX_EXT_PULL_UP;
break;
+
case ISM330DHCX_INTERNAL_PULL_UP:
*val = ISM330DHCX_INTERNAL_PULL_UP;
break;
+
default:
*val = ISM330DHCX_EXT_PULL_UP;
break;
}
+
return ret;
}
@@ -9273,21 +10738,26 @@ int32_t ism330dhcx_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dhcx_master_config_t master_config;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- master_config.pass_through_mode= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ master_config.pass_through_mode = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -9299,21 +10769,25 @@ int32_t ism330dhcx_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dhcx_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dhcx_sh_pass_through_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dhcx_master_config_t master_config;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = master_config.pass_through_mode;
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -9326,25 +10800,30 @@ int32_t ism330dhcx_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t ism330dhcx_sh_syncro_mode_set(stmdev_ctx_t *ctx,
- ism330dhcx_start_config_t val)
+ ism330dhcx_start_config_t val)
{
ism330dhcx_master_config_t master_config;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- master_config.start_config= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ master_config.start_config = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -9357,31 +10836,38 @@ int32_t ism330dhcx_sh_syncro_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_sh_syncro_mode_get(stmdev_ctx_t *ctx,
- ism330dhcx_start_config_t *val)
+ ism330dhcx_start_config_t *val)
{
ism330dhcx_master_config_t master_config;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
- switch (master_config.start_config){
+
+ switch (master_config.start_config)
+ {
case ISM330DHCX_EXT_ON_INT2_PIN:
*val = ISM330DHCX_EXT_ON_INT2_PIN;
break;
+
case ISM330DHCX_XL_GY_DRDY:
*val = ISM330DHCX_XL_GY_DRDY;
break;
+
default:
*val = ISM330DHCX_EXT_ON_INT2_PIN;
break;
}
+
return ret;
}
@@ -9395,25 +10881,30 @@ int32_t ism330dhcx_sh_syncro_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_sh_write_mode_set(stmdev_ctx_t *ctx,
- ism330dhcx_write_once_t val)
+ ism330dhcx_write_once_t val)
{
ism330dhcx_master_config_t master_config;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- master_config.write_once= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ master_config.write_once = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -9427,31 +10918,38 @@ int32_t ism330dhcx_sh_write_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_sh_write_mode_get(stmdev_ctx_t *ctx,
- ism330dhcx_write_once_t *val)
+ ism330dhcx_write_once_t *val)
{
ism330dhcx_master_config_t master_config;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
- switch (master_config.write_once){
+
+ switch (master_config.write_once)
+ {
case ISM330DHCX_EACH_SH_CYCLE:
*val = ISM330DHCX_EACH_SH_CYCLE;
break;
+
case ISM330DHCX_ONLY_FIRST_CYCLE:
*val = ISM330DHCX_ONLY_FIRST_CYCLE;
break;
+
default:
*val = ISM330DHCX_EACH_SH_CYCLE;
break;
}
+
return ret;
}
@@ -9466,26 +10964,33 @@ int32_t ism330dhcx_sh_reset_set(stmdev_ctx_t *ctx)
{
ism330dhcx_master_config_t master_config;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
master_config.rst_master_regs = PROPERTY_ENABLE;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
master_config.rst_master_regs = PROPERTY_DISABLE;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -9501,17 +11006,20 @@ int32_t ism330dhcx_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dhcx_master_config_t master_config;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
*val = master_config.rst_master_regs;
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -9524,25 +11032,30 @@ int32_t ism330dhcx_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t ism330dhcx_sh_data_rate_set(stmdev_ctx_t *ctx,
- ism330dhcx_shub_odr_t val)
+ ism330dhcx_shub_odr_t val)
{
ism330dhcx_slv0_config_t slv0_config;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv0_config.shub_odr = (uint8_t)val;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -9555,37 +11068,46 @@ int32_t ism330dhcx_sh_data_rate_set(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_sh_data_rate_get(stmdev_ctx_t *ctx,
- ism330dhcx_shub_odr_t *val)
+ ism330dhcx_shub_odr_t *val)
{
ism330dhcx_slv0_config_t slv0_config;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
- switch (slv0_config.shub_odr){
+
+ switch (slv0_config.shub_odr)
+ {
case ISM330DHCX_SH_ODR_104Hz:
*val = ISM330DHCX_SH_ODR_104Hz;
break;
+
case ISM330DHCX_SH_ODR_52Hz:
*val = ISM330DHCX_SH_ODR_52Hz;
break;
+
case ISM330DHCX_SH_ODR_26Hz:
*val = ISM330DHCX_SH_ODR_26Hz;
break;
+
case ISM330DHCX_SH_ODR_13Hz:
*val = ISM330DHCX_SH_ODR_13Hz;
break;
+
default:
*val = ISM330DHCX_SH_ODR_104Hz;
break;
}
+
return ret;
}
@@ -9601,30 +11123,37 @@ int32_t ism330dhcx_sh_data_rate_get(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_sh_cfg_write(stmdev_ctx_t *ctx,
- ism330dhcx_sh_cfg_write_t *val)
+ ism330dhcx_sh_cfg_write_t *val)
{
ism330dhcx_slv0_add_t slv0_add;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
- if(ret == 0){
- slv0_add.slave0 = (uint8_t) (val->slv0_add >> 1);
+ if (ret == 0)
+ {
+ slv0_add.slave0 = (uint8_t)(val->slv0_add >> 1);
slv0_add.rw_0 = 0;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV0_ADD,
- (uint8_t*)&(slv0_add), 1);
+ (uint8_t *) & (slv0_add), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV0_SUBADD,
- (uint8_t*)&(val->slv0_subadd), 1);
+ (uint8_t *) & (val->slv0_subadd), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_DATAWRITE_SLV0,
- (uint8_t*)&(val->slv0_data), 1);
+ (uint8_t *) & (val->slv0_data), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -9640,36 +11169,45 @@ int32_t ism330dhcx_sh_cfg_write(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
- ism330dhcx_sh_cfg_read_t *val)
+ ism330dhcx_sh_cfg_read_t *val)
{
ism330dhcx_slv0_config_t slv0_config;
ism330dhcx_slv0_add_t slv0_add;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
slv0_add.slave0 = (uint8_t) val->slv_add >> 1;
slv0_add.rw_0 = 1;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV0_ADD,
- (uint8_t*)&(slv0_add), 1);
+ (uint8_t *) & (slv0_add), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV0_SUBADD,
- &(val->slv_subadd), 1);
+ &(val->slv_subadd), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv0_config.slave0_numop = val->slv_len;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -9685,35 +11223,45 @@ int32_t ism330dhcx_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
- ism330dhcx_sh_cfg_read_t *val)
+ ism330dhcx_sh_cfg_read_t *val)
{
ism330dhcx_slv1_config_t slv1_config;
ism330dhcx_slv1_add_t slv1_add;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
- if(ret == 0){
- slv1_add.slave1_add = (uint8_t) (val->slv_add >> 1);
+
+ if (ret == 0)
+ {
+ slv1_add.slave1_add = (uint8_t)(val->slv_add >> 1);
slv1_add.r_1 = 1;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV1_ADD,
- (uint8_t*)&slv1_add, 1);
+ (uint8_t *)&slv1_add, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV1_SUBADD,
- &(val->slv_subadd), 1);
+ &(val->slv_subadd), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SLV1_CONFIG,
- (uint8_t*)&slv1_config, 1);
+ (uint8_t *)&slv1_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv1_config.slave1_numop = val->slv_len;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV1_CONFIG,
- (uint8_t*)&slv1_config, 1);
+ (uint8_t *)&slv1_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
-}
+ }
+
return ret;
}
@@ -9729,36 +11277,45 @@ int32_t ism330dhcx_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
- ism330dhcx_sh_cfg_read_t *val)
+ ism330dhcx_sh_cfg_read_t *val)
{
ism330dhcx_slv2_config_t slv2_config;
ism330dhcx_slv2_add_t slv2_add;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
- if(ret == 0){
- slv2_add.slave2_add = (uint8_t) (val->slv_add >> 1);
+ if (ret == 0)
+ {
+ slv2_add.slave2_add = (uint8_t)(val->slv_add >> 1);
slv2_add.r_2 = 1;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV2_ADD,
- (uint8_t*)&slv2_add, 1);
+ (uint8_t *)&slv2_add, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV2_SUBADD,
- (uint8_t*)&(val->slv_subadd), 1);
+ (uint8_t *) & (val->slv_subadd), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SLV2_CONFIG,
- (uint8_t*)&slv2_config, 1);
+ (uint8_t *)&slv2_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv2_config.slave2_numop = val->slv_len;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV2_CONFIG,
- (uint8_t*)&slv2_config, 1);
+ (uint8_t *)&slv2_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -9774,36 +11331,45 @@ int32_t ism330dhcx_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
- ism330dhcx_sh_cfg_read_t *val)
+ ism330dhcx_sh_cfg_read_t *val)
{
ism330dhcx_slv3_config_t slv3_config;
ism330dhcx_slv3_add_t slv3_add;
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
- if(ret == 0){
- slv3_add.slave3_add = (uint8_t) (val->slv_add >> 1);
+ if (ret == 0)
+ {
+ slv3_add.slave3_add = (uint8_t)(val->slv_add >> 1);
slv3_add.r_3 = 1;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV3_ADD,
- (uint8_t*)&slv3_add, 1);
+ (uint8_t *)&slv3_add, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV3_SUBADD,
- &(val->slv_subadd), 1);
+ &(val->slv_subadd), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SLV3_CONFIG,
- (uint8_t*)&slv3_config, 1);
+ (uint8_t *)&slv3_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv3_config.slave3_numop = val->slv_len;
ret = ism330dhcx_write_reg(ctx, ISM330DHCX_SLV3_CONFIG,
- (uint8_t*)&slv3_config, 1);
+ (uint8_t *)&slv3_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
@@ -9816,19 +11382,22 @@ int32_t ism330dhcx_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
*
*/
int32_t ism330dhcx_sh_status_get(stmdev_ctx_t *ctx,
- ism330dhcx_status_master_t *val)
+ ism330dhcx_status_master_t *val)
{
int32_t ret;
-
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dhcx_read_reg(ctx, ISM330DHCX_STATUS_MASTER,
- (uint8_t*)val, 1);
+ (uint8_t *)val, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK);
}
+
return ret;
}
diff --git a/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.h b/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.h
index f22624b4bfcde010f9a3148221f65cc669204b1d..8accaf1d715a64db9bd378b33a0d293cb74111b8 100644
--- a/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.h
+++ b/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.h
@@ -1,33 +1,34 @@
-/*
+/**
+ ******************************************************************************
+ * @file ism330dhcx_reg.h
+ * @author Sensor Solutions Software Team
+ * @brief This file contains all the functions prototypes for the
+ * ism330dhcx_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
******************************************************************************
- * @file ism330dhcx_reg.h
- * @author Sensor Solutions Software Team
- * @brief This file contains all the functions prototypes for the
- * ism330dhcx_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef ISM330DHCX_REGS_H
#define ISM330DHCX_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup ISM330DHCX
@@ -74,7 +75,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -107,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -131,15 +134,16 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
- * Unico / Unicleo tools available on STMicroelectronics
- * web site.
+ * You can create a sensor configuration by your own or using
+ * Unico / Unicleo tools available on STMicroelectronics
+ * web site.
*
* @{
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -174,18 +178,22 @@ typedef struct {
*/
#define ISM330DHCX_FUNC_CFG_ACCESS 0x01U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 6;
- uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */
+uint8_t reg_access :
+ 2; /* shub_reg_access + func_cfg_access */
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */
+uint8_t reg_access :
+ 2; /* shub_reg_access + func_cfg_access */
uint8_t not_used_01 : 6;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_func_cfg_access_t;
#define ISM330DHCX_PIN_CTRL 0x02U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 6;
uint8_t sdo_pu_en : 1;
@@ -198,12 +206,14 @@ typedef struct {
} ism330dhcx_pin_ctrl_t;
#define ISM330DHCX_FIFO_CTRL1 0x07U
-typedef struct {
+typedef struct
+{
uint8_t wtm : 8;
} ism330dhcx_fifo_ctrl1_t;
#define ISM330DHCX_FIFO_CTRL2 0x08U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wtm : 1;
uint8_t uncoptr_rate : 2;
@@ -224,7 +234,8 @@ typedef struct {
} ism330dhcx_fifo_ctrl2_t;
#define ISM330DHCX_FIFO_CTRL3 0x09U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bdr_xl : 4;
uint8_t bdr_gy : 4;
@@ -235,7 +246,8 @@ typedef struct {
} ism330dhcx_fifo_ctrl3_t;
#define ISM330DHCX_FIFO_CTRL4 0x0AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fifo_mode : 3;
uint8_t not_used_01 : 1;
@@ -250,7 +262,8 @@ typedef struct {
} ism330dhcx_fifo_ctrl4_t;
#define ISM330DHCX_COUNTER_BDR_REG1 0x0BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t cnt_bdr_th : 3;
uint8_t not_used_01 : 2;
@@ -267,12 +280,14 @@ typedef struct {
} ism330dhcx_counter_bdr_reg1_t;
#define ISM330DHCX_COUNTER_BDR_REG2 0x0CU
-typedef struct {
+typedef struct
+{
uint8_t cnt_bdr_th : 8;
} ism330dhcx_counter_bdr_reg2_t;
#define ISM330DHCX_INT1_CTRL 0x0DU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_drdy_xl : 1;
uint8_t int1_drdy_g : 1;
@@ -295,7 +310,8 @@ typedef struct {
} ism330dhcx_int1_ctrl_t;
#define ISM330DHCX_INT2_CTRL 0x0EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_drdy_xl : 1;
uint8_t int2_drdy_g : 1;
@@ -319,7 +335,8 @@ typedef struct {
#define ISM330DHCX_WHO_AM_I 0x0FU
#define ISM330DHCX_CTRL1_XL 0x10U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t lpf2_xl_en : 1;
@@ -334,7 +351,8 @@ typedef struct {
} ism330dhcx_ctrl1_xl_t;
#define ISM330DHCX_CTRL2_G 0x11U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fs_g : 4; /* fs_4000 + fs_125 + fs_g */
uint8_t odr_g : 4;
@@ -345,7 +363,8 @@ typedef struct {
} ism330dhcx_ctrl2_g_t;
#define ISM330DHCX_CTRL3_C 0x12U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sw_reset : 1;
uint8_t not_used_01 : 1;
@@ -368,7 +387,8 @@ typedef struct {
} ism330dhcx_ctrl3_c_t;
#define ISM330DHCX_CTRL4_C 0x13U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t lpf1_sel_g : 1;
@@ -391,7 +411,8 @@ typedef struct {
} ism330dhcx_ctrl4_c_t;
#define ISM330DHCX_CTRL5_C 0x14U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_xl : 2;
uint8_t st_g : 2;
@@ -408,14 +429,17 @@ typedef struct {
} ism330dhcx_ctrl5_c_t;
#define ISM330DHCX_CTRL6_C 0x15U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ftype : 3;
uint8_t usr_off_w : 1;
uint8_t xl_hm_mode : 1;
- uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */
+uint8_t den_mode :
+ 3; /* trig_en + lvl1_en + lvl2_en */
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */
+uint8_t den_mode :
+ 3; /* trig_en + lvl1_en + lvl2_en */
uint8_t xl_hm_mode : 1;
uint8_t usr_off_w : 1;
uint8_t ftype : 3;
@@ -423,7 +447,8 @@ typedef struct {
} ism330dhcx_ctrl6_c_t;
#define ISM330DHCX_CTRL7_G 0x16U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ois_on : 1;
uint8_t usr_off_on_out : 1;
@@ -444,7 +469,8 @@ typedef struct {
} ism330dhcx_ctrl7_g_t;
#define ISM330DHCX_CTRL8_XL 0x17U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t low_pass_on_6d : 1;
uint8_t not_used_01 : 1;
@@ -463,7 +489,8 @@ typedef struct {
} ism330dhcx_ctrl8_xl_t;
#define ISM330DHCX_CTRL9_XL 0x18U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t device_conf : 1;
@@ -484,7 +511,8 @@ typedef struct {
} ism330dhcx_ctrl9_xl_t;
#define ISM330DHCX_CTRL10_C 0x19U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 5;
uint8_t timestamp_en : 1;
@@ -497,7 +525,8 @@ typedef struct {
} ism330dhcx_ctrl10_c_t;
#define ISM330DHCX_ALL_INT_SRC 0x1AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ia : 1;
uint8_t wu_ia : 1;
@@ -520,7 +549,8 @@ typedef struct {
} ism330dhcx_all_int_src_t;
#define ISM330DHCX_WAKE_UP_SRC 0x1BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_wu : 1;
uint8_t y_wu : 1;
@@ -543,7 +573,8 @@ typedef struct {
} ism330dhcx_wake_up_src_t;
#define ISM330DHCX_TAP_SRC 0x1CU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_tap : 1;
uint8_t y_tap : 1;
@@ -566,7 +597,8 @@ typedef struct {
} ism330dhcx_tap_src_t;
#define ISM330DHCX_D6D_SRC 0x1DU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
@@ -589,7 +621,8 @@ typedef struct {
} ism330dhcx_d6d_src_t;
#define ISM330DHCX_STATUS_REG 0x1EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlda : 1;
uint8_t gda : 1;
@@ -604,7 +637,8 @@ typedef struct {
} ism330dhcx_status_reg_t;
#define ISM330DHCX_STATUS_SPIAUX 0x1EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlda : 1;
uint8_t gda : 1;
@@ -633,7 +667,8 @@ typedef struct {
#define ISM330DHCX_OUTZ_L_A 0x2CU
#define ISM330DHCX_OUTZ_H_A 0x2DU
#define ISM330DHCX_EMB_FUNC_STATUS_MAINPAGE 0x35U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t is_step_det : 1;
@@ -652,7 +687,8 @@ typedef struct {
} ism330dhcx_emb_func_status_mainpage_t;
#define ISM330DHCX_FSM_STATUS_A_MAINPAGE 0x36U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_fsm1 : 1;
uint8_t is_fsm2 : 1;
@@ -675,7 +711,8 @@ typedef struct {
} ism330dhcx_fsm_status_a_mainpage_t;
#define ISM330DHCX_FSM_STATUS_B_MAINPAGE 0x37U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_fsm9 : 1;
uint8_t is_fsm10 : 1;
@@ -698,7 +735,8 @@ typedef struct {
} ism330dhcx_fsm_status_b_mainpage_t;
#define ISM330DHCX_MLC_STATUS_MAINPAGE 0x38U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_mlc1 : 1;
uint8_t is_mlc2 : 1;
@@ -721,7 +759,8 @@ typedef struct {
} ism330dhcx_mlc_status_mainpage_t;
#define ISM330DHCX_STATUS_MASTER_MAINPAGE 0x39U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sens_hub_endop : 1;
uint8_t not_used_01 : 2;
@@ -742,12 +781,14 @@ typedef struct {
} ism330dhcx_status_master_mainpage_t;
#define ISM330DHCX_FIFO_STATUS1 0x3AU
-typedef struct {
+typedef struct
+{
uint8_t diff_fifo : 8;
} ism330dhcx_fifo_status1_t;
#define ISM330DHCX_FIFO_STATUS2 0x3BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t diff_fifo : 2;
uint8_t not_used_01 : 1;
@@ -772,7 +813,8 @@ typedef struct {
#define ISM330DHCX_TIMESTAMP2 0x42U
#define ISM330DHCX_TIMESTAMP3 0x43U
#define ISM330DHCX_TAP_CFG0 0x56U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lir : 1;
uint8_t tap_z_en : 1;
@@ -795,7 +837,8 @@ typedef struct {
} ism330dhcx_tap_cfg0_t;
#define ISM330DHCX_TAP_CFG1 0x57U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_ths_x : 5;
uint8_t tap_priority : 3;
@@ -806,7 +849,8 @@ typedef struct {
} ism330dhcx_tap_cfg1_t;
#define ISM330DHCX_TAP_CFG2 0x58U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_ths_y : 5;
uint8_t inact_en : 2;
@@ -819,7 +863,8 @@ typedef struct {
} ism330dhcx_tap_cfg2_t;
#define ISM330DHCX_TAP_THS_6D 0x59U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_ths_z : 5;
uint8_t sixd_ths : 2;
@@ -832,7 +877,8 @@ typedef struct {
} ism330dhcx_tap_ths_6d_t;
#define ISM330DHCX_INT_DUR2 0x5AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shock : 2;
uint8_t quiet : 2;
@@ -845,7 +891,8 @@ typedef struct {
} ism330dhcx_int_dur2_t;
#define ISM330DHCX_WAKE_UP_THS 0x5BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wk_ths : 6;
uint8_t usr_off_on_wu : 1;
@@ -858,7 +905,8 @@ typedef struct {
} ism330dhcx_wake_up_ths_t;
#define ISM330DHCX_WAKE_UP_DUR 0x5CU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sleep_dur : 4;
uint8_t wake_ths_w : 1;
@@ -873,7 +921,8 @@ typedef struct {
} ism330dhcx_wake_up_dur_t;
#define ISM330DHCX_FREE_FALL 0x5DU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ths : 3;
uint8_t ff_dur : 5;
@@ -884,7 +933,8 @@ typedef struct {
} ism330dhcx_free_fall_t;
#define ISM330DHCX_MD1_CFG 0x5EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_shub : 1;
uint8_t int1_emb_func : 1;
@@ -907,7 +957,8 @@ typedef struct {
} ism330dhcx_md1_cfg_t;
#define ISM330DHCX_MD2_CFG 0x5FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_timestamp : 1;
uint8_t int2_emb_func : 1;
@@ -930,12 +981,14 @@ typedef struct {
} ism330dhcx_md2_cfg_t;
#define ISM330DHCX_INTERNAL_FREQ_FINE 0x63U
-typedef struct {
+typedef struct
+{
uint8_t freq_fine : 8;
} ism330dhcx_internal_freq_fine_t;
#define ISM330DHCX_INT_OIS 0x6FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_xl_ois : 2;
uint8_t not_used_01 : 3;
@@ -952,7 +1005,8 @@ typedef struct {
} ism330dhcx_int_ois_t;
#define ISM330DHCX_CTRL1_OIS 0x70U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ois_en_spi2 : 1;
uint8_t fs_125_ois : 1;
@@ -973,7 +1027,8 @@ typedef struct {
} ism330dhcx_ctrl1_ois_t;
#define ISM330DHCX_CTRL2_OIS 0x71U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t hp_en_ois : 1;
uint8_t ftype_ois : 2;
@@ -990,7 +1045,8 @@ typedef struct {
} ism330dhcx_ctrl2_ois_t;
#define ISM330DHCX_CTRL3_OIS 0x72U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_ois_clampdis : 1;
uint8_t st_ois : 2;
@@ -1008,7 +1064,8 @@ typedef struct {
#define ISM330DHCX_Y_OFS_USR 0x74U
#define ISM330DHCX_Z_OFS_USR 0x75U
#define ISM330DHCX_FIFO_DATA_OUT_TAG 0x78U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tag_parity : 1;
uint8_t tag_cnt : 2;
@@ -1027,7 +1084,8 @@ typedef struct {
#define ISM330DHCX_FIFO_DATA_OUT_Z_L 0x7DU
#define ISM330DHCX_FIFO_DATA_OUT_Z_H 0x7EU
#define ISM330DHCX_PAGE_SEL 0x02U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 4;
uint8_t page_sel : 4;
@@ -1038,7 +1096,8 @@ typedef struct {
} ism330dhcx_page_sel_t;
#define ISM330DHCX_EMB_FUNC_EN_A 0x04U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t pedo_en : 1;
@@ -1055,7 +1114,8 @@ typedef struct {
} ism330dhcx_emb_func_en_a_t;
#define ISM330DHCX_EMB_FUNC_EN_B 0x05U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fsm_en : 1;
uint8_t not_used_01 : 2;
@@ -1072,17 +1132,20 @@ typedef struct {
} ism330dhcx_emb_func_en_b_t;
#define ISM330DHCX_PAGE_ADDRESS 0x08U
-typedef struct {
+typedef struct
+{
uint8_t page_addr : 8;
} ism330dhcx_page_address_t;
#define ISM330DHCX_PAGE_VALUE 0x09U
-typedef struct {
+typedef struct
+{
uint8_t page_value : 8;
} ism330dhcx_page_value_t;
#define ISM330DHCX_EMB_FUNC_INT1 0x0AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t int1_step_detector : 1;
@@ -1101,7 +1164,8 @@ typedef struct {
} ism330dhcx_emb_func_int1_t;
#define ISM330DHCX_FSM_INT1_A 0x0BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_fsm1 : 1;
uint8_t int1_fsm2 : 1;
@@ -1124,7 +1188,8 @@ typedef struct {
} ism330dhcx_fsm_int1_a_t;
#define ISM330DHCX_FSM_INT1_B 0x0CU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_fsm9 : 1;
uint8_t int1_fsm10 : 1;
@@ -1147,7 +1212,8 @@ typedef struct {
} ism330dhcx_fsm_int1_b_t;
#define ISM330DHCX_MLC_INT1 0x0DU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_mlc1 : 1;
uint8_t int1_mlc2 : 1;
@@ -1170,7 +1236,8 @@ typedef struct {
} ism330dhcx_mlc_int1_t;
#define ISM330DHCX_EMB_FUNC_INT2 0x0EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t int2_step_detector : 1;
@@ -1189,7 +1256,8 @@ typedef struct {
} ism330dhcx_emb_func_int2_t;
#define ISM330DHCX_FSM_INT2_A 0x0FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_fsm1 : 1;
uint8_t int2_fsm2 : 1;
@@ -1212,7 +1280,8 @@ typedef struct {
} ism330dhcx_fsm_int2_a_t;
#define ISM330DHCX_FSM_INT2_B 0x10U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_fsm9 : 1;
uint8_t int2_fsm10 : 1;
@@ -1235,7 +1304,8 @@ typedef struct {
} ism330dhcx_fsm_int2_b_t;
#define ISM330DHCX_MLC_INT2 0x11U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_mlc1 : 1;
uint8_t int2_mlc2 : 1;
@@ -1258,7 +1328,8 @@ typedef struct {
} ism330dhcx_mlc_int2_t;
#define ISM330DHCX_EMB_FUNC_STATUS 0x12U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t is_step_det : 1;
@@ -1277,7 +1348,8 @@ typedef struct {
} ism330dhcx_emb_func_status_t;
#define ISM330DHCX_FSM_STATUS_A 0x13U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_fsm1 : 1;
uint8_t is_fsm2 : 1;
@@ -1300,7 +1372,8 @@ typedef struct {
} ism330dhcx_fsm_status_a_t;
#define ISM330DHCX_FSM_STATUS_B 0x14U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_fsm9 : 1;
uint8_t is_fsm10 : 1;
@@ -1323,7 +1396,8 @@ typedef struct {
} ism330dhcx_fsm_status_b_t;
#define ISM330DHCX_MLC_STATUS 0x15U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_mlc1 : 1;
uint8_t is_mlc2 : 1;
@@ -1346,7 +1420,8 @@ typedef struct {
} ism330dhcx_mlc_status_t;
#define ISM330DHCX_PAGE_RW 0x17U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 5;
uint8_t page_rw : 2; /* page_write + page_read */
@@ -1359,7 +1434,8 @@ typedef struct {
} ism330dhcx_page_rw_t;
#define ISM330DHCX_EMB_FUNC_FIFO_CFG 0x44U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 6;
uint8_t pedo_fifo_en : 1;
@@ -1372,7 +1448,8 @@ typedef struct {
} ism330dhcx_emb_func_fifo_cfg_t;
#define ISM330DHCX_FSM_ENABLE_A 0x46U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fsm1_en : 1;
uint8_t fsm2_en : 1;
@@ -1395,7 +1472,8 @@ typedef struct {
} ism330dhcx_fsm_enable_a_t;
#define ISM330DHCX_FSM_ENABLE_B 0x47U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fsm9_en : 1;
uint8_t fsm10_en : 1;
@@ -1420,18 +1498,22 @@ typedef struct {
#define ISM330DHCX_FSM_LONG_COUNTER_L 0x48U
#define ISM330DHCX_FSM_LONG_COUNTER_H 0x49U
#define ISM330DHCX_FSM_LONG_COUNTER_CLEAR 0x4AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */
+uint8_t fsm_lc_clr :
+ 2; /* fsm_lc_cleared + fsm_lc_clear */
uint8_t not_used_01 : 6;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used_01 : 6;
- uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */
+uint8_t fsm_lc_clr :
+ 2; /* fsm_lc_cleared + fsm_lc_clear */
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_fsm_long_counter_clear_t;
#define ISM330DHCX_FSM_OUTS1 0x4CU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1454,7 +1536,8 @@ typedef struct {
} ism330dhcx_fsm_outs1_t;
#define ISM330DHCX_FSM_OUTS2 0x4DU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1477,7 +1560,8 @@ typedef struct {
} ism330dhcx_fsm_outs2_t;
#define ISM330DHCX_FSM_OUTS3 0x4EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1500,7 +1584,8 @@ typedef struct {
} ism330dhcx_fsm_outs3_t;
#define ISM330DHCX_FSM_OUTS4 0x4FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1523,7 +1608,8 @@ typedef struct {
} ism330dhcx_fsm_outs4_t;
#define ISM330DHCX_FSM_OUTS5 0x50U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1546,7 +1632,8 @@ typedef struct {
} ism330dhcx_fsm_outs5_t;
#define ISM330DHCX_FSM_OUTS6 0x51U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1569,7 +1656,8 @@ typedef struct {
} ism330dhcx_fsm_outs6_t;
#define ISM330DHCX_FSM_OUTS7 0x52U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1592,7 +1680,8 @@ typedef struct {
} ism330dhcx_fsm_outs7_t;
#define ISM330DHCX_FSM_OUTS8 0x53U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1615,7 +1704,8 @@ typedef struct {
} ism330dhcx_fsm_outs8_t;
#define ISM330DHCX_FSM_OUTS9 0x54U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1638,7 +1728,8 @@ typedef struct {
} ism330dhcx_fsm_outs9_t;
#define ISM330DHCX_FSM_OUTS10 0x55U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1661,7 +1752,8 @@ typedef struct {
} ism330dhcx_fsm_outs10_t;
#define ISM330DHCX_FSM_OUTS11 0x56U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1684,7 +1776,8 @@ typedef struct {
} ism330dhcx_fsm_outs11_t;
#define ISM330DHCX_FSM_OUTS12 0x57U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1707,7 +1800,8 @@ typedef struct {
} ism330dhcx_fsm_outs12_t;
#define ISM330DHCX_FSM_OUTS13 0x58U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1730,7 +1824,8 @@ typedef struct {
} ism330dhcx_fsm_outs13_t;
#define ISM330DHCX_FSM_OUTS14 0x59U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1753,7 +1848,8 @@ typedef struct {
} ism330dhcx_fsm_outs14_t;
#define ISM330DHCX_FSM_OUTS15 0x5AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1776,7 +1872,8 @@ typedef struct {
} ism330dhcx_fsm_outs15_t;
#define ISM330DHCX_FSM_OUTS16 0x5BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1799,7 +1896,8 @@ typedef struct {
} ism330dhcx_fsm_outs16_t;
#define ISM330DHCX_EMB_FUNC_ODR_CFG_B 0x5FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t fsm_odr : 2;
@@ -1812,7 +1910,8 @@ typedef struct {
} ism330dhcx_emb_func_odr_cfg_b_t;
#define ISM330DHCX_EMB_FUNC_ODR_CFG_C 0x60U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 4;
uint8_t mlc_odr : 2;
@@ -1827,7 +1926,8 @@ typedef struct {
#define ISM330DHCX_STEP_COUNTER_L 0x62U
#define ISM330DHCX_STEP_COUNTER_H 0x63U
#define ISM330DHCX_EMB_FUNC_SRC 0x64U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t stepcounter_bit_set : 1;
@@ -1848,7 +1948,8 @@ typedef struct {
} ism330dhcx_emb_func_src_t;
#define ISM330DHCX_EMB_FUNC_INIT_A 0x66U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t step_det_init : 1;
@@ -1865,7 +1966,8 @@ typedef struct {
} ism330dhcx_emb_func_init_a_t;
#define ISM330DHCX_EMB_FUNC_INIT_B 0x67U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fsm_init : 1;
uint8_t not_used_01 : 2;
@@ -1910,7 +2012,8 @@ typedef struct {
#define ISM330DHCX_MAG_SI_ZZ_L 0xD0U
#define ISM330DHCX_MAG_SI_ZZ_H 0xD1U
#define ISM330DHCX_MAG_CFG_A 0xD4U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t mag_z_axis : 3;
uint8_t not_used_01 : 1;
@@ -1925,7 +2028,8 @@ typedef struct {
} ism330dhcx_mag_cfg_a_t;
#define ISM330DHCX_MAG_CFG_B 0xD5U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t mag_x_axis : 3;
uint8_t not_used_01 : 5;
@@ -1941,7 +2045,8 @@ typedef struct {
#define ISM330DHCX_FSM_START_ADD_L 0x17EU
#define ISM330DHCX_FSM_START_ADD_H 0x17FU
#define ISM330DHCX_PEDO_CMD_REG 0x183U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t carry_count_en : 1;
@@ -1959,421 +2064,440 @@ typedef struct {
#define ISM330DHCX_MLC_MAG_SENSITIVITY_L 0x1E8U
#define ISM330DHCX_MLC_MAG_SENSITIVITY_H 0x1E9U
#define ISM330DHCX_SENSOR_HUB_1 0x02U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_sensor_hub_1_t;
#define ISM330DHCX_SENSOR_HUB_2 0x03U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_sensor_hub_2_t;
#define ISM330DHCX_SENSOR_HUB_3 0x04U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_sensor_hub_3_t;
#define ISM330DHCX_SENSOR_HUB_4 0x05U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_sensor_hub_4_t;
#define ISM330DHCX_SENSOR_HUB_5 0x06U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_sensor_hub_5_t;
#define ISM330DHCX_SENSOR_HUB_6 0x07U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_sensor_hub_6_t;
#define ISM330DHCX_SENSOR_HUB_7 0x08U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_sensor_hub_7_t;
#define ISM330DHCX_SENSOR_HUB_8 0x09U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_sensor_hub_8_t;
#define ISM330DHCX_SENSOR_HUB_9 0x0AU
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_sensor_hub_9_t;
#define ISM330DHCX_SENSOR_HUB_10 0x0BU
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_sensor_hub_10_t;
#define ISM330DHCX_SENSOR_HUB_11 0x0CU
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_sensor_hub_11_t;
#define ISM330DHCX_SENSOR_HUB_12 0x0DU
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_sensor_hub_12_t;
#define ISM330DHCX_SENSOR_HUB_13 0x0EU
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_sensor_hub_13_t;
#define ISM330DHCX_SENSOR_HUB_14 0x0FU
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_sensor_hub_14_t;
#define ISM330DHCX_SENSOR_HUB_15 0x10U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_sensor_hub_15_t;
#define ISM330DHCX_SENSOR_HUB_16 0x11U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_sensor_hub_16_t;
#define ISM330DHCX_SENSOR_HUB_17 0x12U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_sensor_hub_17_t;
#define ISM330DHCX_SENSOR_HUB_18 0x13U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_sensor_hub_18_t;
#define ISM330DHCX_MASTER_CONFIG 0x14U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t aux_sens_on : 2;
uint8_t master_on : 1;
@@ -2395,7 +2519,8 @@ typedef struct {
} ism330dhcx_master_config_t;
#define ISM330DHCX_SLV0_ADD 0x15U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t rw_0 : 1;
uint8_t slave0 : 7;
@@ -2407,12 +2532,14 @@ typedef struct {
} ism330dhcx_slv0_add_t;
#define ISM330DHCX_SLV0_SUBADD 0x16U
-typedef struct {
+typedef struct
+{
uint8_t slave0_reg : 8;
} ism330dhcx_slv0_subadd_t;
#define ISM330DHCX_SLV0_CONFIG 0x17U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave0_numop : 3;
uint8_t batch_ext_sens_0_en : 1;
@@ -2428,7 +2555,8 @@ typedef struct {
} ism330dhcx_slv0_config_t;
#define ISM330DHCX_SLV1_ADD 0x18U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_1 : 1;
uint8_t slave1_add : 7;
@@ -2439,12 +2567,14 @@ typedef struct {
} ism330dhcx_slv1_add_t;
#define ISM330DHCX_SLV1_SUBADD 0x19U
-typedef struct {
+typedef struct
+{
uint8_t slave1_reg : 8;
} ism330dhcx_slv1_subadd_t;
#define ISM330DHCX_SLV1_CONFIG 0x1AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave1_numop : 3;
uint8_t batch_ext_sens_1_en : 1;
@@ -2457,7 +2587,8 @@ typedef struct {
} ism330dhcx_slv1_config_t;
#define ISM330DHCX_SLV2_ADD 0x1BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_2 : 1;
uint8_t slave2_add : 7;
@@ -2468,12 +2599,14 @@ typedef struct {
} ism330dhcx_slv2_add_t;
#define ISM330DHCX_SLV2_SUBADD 0x1CU
-typedef struct {
+typedef struct
+{
uint8_t slave2_reg : 8;
} ism330dhcx_slv2_subadd_t;
#define ISM330DHCX_SLV2_CONFIG 0x1DU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave2_numop : 3;
uint8_t batch_ext_sens_2_en : 1;
@@ -2486,7 +2619,8 @@ typedef struct {
} ism330dhcx_slv2_config_t;
#define ISM330DHCX_SLV3_ADD 0x1EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_3 : 1;
uint8_t slave3_add : 7;
@@ -2497,12 +2631,14 @@ typedef struct {
} ism330dhcx_slv3_add_t;
#define ISM330DHCX_SLV3_SUBADD 0x1FU
-typedef struct {
+typedef struct
+{
uint8_t slave3_reg : 8;
} ism330dhcx_slv3_subadd_t;
#define ISM330DHCX_SLV3_CONFIG 0x20U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave3_numop : 3;
uint8_t batch_ext_sens_3_en : 1;
@@ -2515,12 +2651,14 @@ typedef struct {
} ism330dhcx_slv3_config_t;
#define ISM330DHCX_DATAWRITE_SLV0 0x21U
-typedef struct {
+typedef struct
+{
uint8_t slave0_dataw : 8;
} ism330dhcx_datawrite_slv0_t;
#define ISM330DHCX_STATUS_MASTER 0x22U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sens_hub_endop : 1;
uint8_t not_used_01 : 2;
@@ -2542,9 +2680,9 @@ typedef struct {
/**
* @defgroup ISM330DHCX_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -2552,7 +2690,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
ism330dhcx_func_cfg_access_t func_cfg_access;
ism330dhcx_pin_ctrl_t pin_ctrl;
ism330dhcx_fifo_ctrl1_t fifo_ctrl1;
@@ -2612,7 +2751,7 @@ typedef union{
ism330dhcx_fsm_status_a_t fsm_status_a;
ism330dhcx_fsm_status_b_t fsm_status_b;
ism330dhcx_page_rw_t page_rw;
- ism330dhcx_emb_func_fifo_cfg_t emb_func_fifo_cfg;
+ ism330dhcx_emb_func_fifo_cfg_t emb_func_fifo_cfg;
ism330dhcx_fsm_enable_a_t fsm_enable_a;
ism330dhcx_fsm_enable_b_t fsm_enable_b;
ism330dhcx_fsm_long_counter_clear_t fsm_long_counter_clear;
@@ -2682,36 +2821,43 @@ typedef union{
*
*/
-int32_t ism330dhcx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
- uint16_t len);
-int32_t ism330dhcx_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t ism330dhcx_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
+int32_t ism330dhcx_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len);
+
+float_t ism330dhcx_from_fs2g_to_mg(int16_t lsb);
+float_t ism330dhcx_from_fs4g_to_mg(int16_t lsb);
+float_t ism330dhcx_from_fs8g_to_mg(int16_t lsb);
+float_t ism330dhcx_from_fs16g_to_mg(int16_t lsb);
+
+float_t ism330dhcx_from_fs125dps_to_mdps(int16_t lsb);
+float_t ism330dhcx_from_fs250dps_to_mdps(int16_t lsb);
+float_t ism330dhcx_from_fs500dps_to_mdps(int16_t lsb);
+float_t ism330dhcx_from_fs1000dps_to_mdps(int16_t lsb);
+float_t ism330dhcx_from_fs2000dps_to_mdps(int16_t lsb);
+float_t ism330dhcx_from_fs4000dps_to_mdps(int16_t lsb);
+
+float_t ism330dhcx_from_lsb_to_celsius(int16_t lsb);
+
+float_t ism330dhcx_from_lsb_to_nsec(int32_t lsb);
-extern float_t ism330dhcx_from_fs2g_to_mg(int16_t lsb);
-extern float_t ism330dhcx_from_fs4g_to_mg(int16_t lsb);
-extern float_t ism330dhcx_from_fs8g_to_mg(int16_t lsb);
-extern float_t ism330dhcx_from_fs16g_to_mg(int16_t lsb);
-extern float_t ism330dhcx_from_fs125dps_to_mdps(int16_t lsb);
-extern float_t ism330dhcx_from_fs250dps_to_mdps(int16_t lsb);
-extern float_t ism330dhcx_from_fs500dps_to_mdps(int16_t lsb);
-extern float_t ism330dhcx_from_fs1000dps_to_mdps(int16_t lsb);
-extern float_t ism330dhcx_from_fs2000dps_to_mdps(int16_t lsb);
-extern float_t ism330dhcx_from_fs4000dps_to_mdps(int16_t lsb);
-extern float_t ism330dhcx_from_lsb_to_celsius(int16_t lsb);
-extern float_t ism330dhcx_from_lsb_to_nsec(int32_t lsb);
-
-typedef enum {
+typedef enum
+{
ISM330DHCX_2g = 0,
ISM330DHCX_16g = 1, /* if XL_FS_MODE = ‘1’ -> ISM330DHCX_2g */
ISM330DHCX_4g = 2,
ISM330DHCX_8g = 3,
} ism330dhcx_fs_xl_t;
int32_t ism330dhcx_xl_full_scale_set(stmdev_ctx_t *ctx,
- ism330dhcx_fs_xl_t val);
+ ism330dhcx_fs_xl_t val);
int32_t ism330dhcx_xl_full_scale_get(stmdev_ctx_t *ctx,
- ism330dhcx_fs_xl_t *val);
+ ism330dhcx_fs_xl_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_XL_ODR_OFF = 0,
ISM330DHCX_XL_ODR_12Hz5 = 1,
ISM330DHCX_XL_ODR_26Hz = 2,
@@ -2726,11 +2872,12 @@ typedef enum {
ISM330DHCX_XL_ODR_6Hz5 = 11, /* (low power only) */
} ism330dhcx_odr_xl_t;
int32_t ism330dhcx_xl_data_rate_set(stmdev_ctx_t *ctx,
- ism330dhcx_odr_xl_t val);
+ ism330dhcx_odr_xl_t val);
int32_t ism330dhcx_xl_data_rate_get(stmdev_ctx_t *ctx,
- ism330dhcx_odr_xl_t *val);
+ ism330dhcx_odr_xl_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_125dps = 2,
ISM330DHCX_250dps = 0,
ISM330DHCX_500dps = 4,
@@ -2739,11 +2886,12 @@ typedef enum {
ISM330DHCX_4000dps = 1,
} ism330dhcx_fs_g_t;
int32_t ism330dhcx_gy_full_scale_set(stmdev_ctx_t *ctx,
- ism330dhcx_fs_g_t val);
+ ism330dhcx_fs_g_t val);
int32_t ism330dhcx_gy_full_scale_get(stmdev_ctx_t *ctx,
- ism330dhcx_fs_g_t *val);
+ ism330dhcx_fs_g_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_GY_ODR_OFF = 0,
ISM330DHCX_GY_ODR_12Hz5 = 1,
ISM330DHCX_GY_ODR_26Hz = 2,
@@ -2757,41 +2905,47 @@ typedef enum {
ISM330DHCX_GY_ODR_6667Hz = 10,
} ism330dhcx_odr_g_t;
int32_t ism330dhcx_gy_data_rate_set(stmdev_ctx_t *ctx,
- ism330dhcx_odr_g_t val);
+ ism330dhcx_odr_g_t val);
int32_t ism330dhcx_gy_data_rate_get(stmdev_ctx_t *ctx,
- ism330dhcx_odr_g_t *val);
+ ism330dhcx_odr_g_t *val);
-int32_t ism330dhcx_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dhcx_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dhcx_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dhcx_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_LSb_1mg = 0,
ISM330DHCX_LSb_16mg = 1,
} ism330dhcx_usr_off_w_t;
int32_t ism330dhcx_xl_offset_weight_set(stmdev_ctx_t *ctx,
- ism330dhcx_usr_off_w_t val);
+ ism330dhcx_usr_off_w_t val);
int32_t ism330dhcx_xl_offset_weight_get(stmdev_ctx_t *ctx,
- ism330dhcx_usr_off_w_t *val);
+ ism330dhcx_usr_off_w_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_HIGH_PERFORMANCE_MD = 0,
ISM330DHCX_LOW_NORMAL_POWER_MD = 1,
} ism330dhcx_xl_hm_mode_t;
int32_t ism330dhcx_xl_power_mode_set(stmdev_ctx_t *ctx,
- ism330dhcx_xl_hm_mode_t val);
+ ism330dhcx_xl_hm_mode_t val);
int32_t ism330dhcx_xl_power_mode_get(stmdev_ctx_t *ctx,
- ism330dhcx_xl_hm_mode_t *val);
+ ism330dhcx_xl_hm_mode_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_GY_HIGH_PERFORMANCE = 0,
ISM330DHCX_GY_NORMAL = 1,
} ism330dhcx_g_hm_mode_t;
int32_t ism330dhcx_gy_power_mode_set(stmdev_ctx_t *ctx,
- ism330dhcx_g_hm_mode_t val);
+ ism330dhcx_g_hm_mode_t val);
int32_t ism330dhcx_gy_power_mode_get(stmdev_ctx_t *ctx,
- ism330dhcx_g_hm_mode_t *val);
+ ism330dhcx_g_hm_mode_t *val);
-typedef struct {
+typedef struct
+{
ism330dhcx_all_int_src_t all_int_src;
ism330dhcx_wake_up_src_t wake_up_src;
ism330dhcx_tap_src_t tap_src;
@@ -2800,12 +2954,12 @@ typedef struct {
ism330dhcx_emb_func_status_t emb_func_status;
ism330dhcx_fsm_status_a_t fsm_status_a;
ism330dhcx_fsm_status_b_t fsm_status_b;
- } ism330dhcx_all_sources_t;
+} ism330dhcx_all_sources_t;
int32_t ism330dhcx_all_sources_get(stmdev_ctx_t *ctx,
- ism330dhcx_all_sources_t *val);
+ ism330dhcx_all_sources_t *val);
int32_t ism330dhcx_status_reg_get(stmdev_ctx_t *ctx,
- ism330dhcx_status_reg_t *val);
+ ism330dhcx_status_reg_t *val);
int32_t ism330dhcx_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
uint8_t *val);
@@ -2816,14 +2970,20 @@ int32_t ism330dhcx_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
int32_t ism330dhcx_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
uint8_t *val);
-int32_t ism330dhcx_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t ism330dhcx_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t ism330dhcx_xl_usr_offset_x_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t ism330dhcx_xl_usr_offset_x_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
-int32_t ism330dhcx_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t ism330dhcx_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t ism330dhcx_xl_usr_offset_y_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t ism330dhcx_xl_usr_offset_y_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
-int32_t ism330dhcx_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t ism330dhcx_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t ism330dhcx_xl_usr_offset_z_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t ism330dhcx_xl_usr_offset_z_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
int32_t ism330dhcx_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dhcx_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -2833,37 +2993,47 @@ int32_t ism330dhcx_timestamp_rst(stmdev_ctx_t *ctx);
int32_t ism330dhcx_timestamp_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dhcx_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t ism330dhcx_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val);
+int32_t ism330dhcx_timestamp_raw_get(stmdev_ctx_t *ctx,
+ uint32_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_NO_ROUND = 0,
ISM330DHCX_ROUND_XL = 1,
ISM330DHCX_ROUND_GY = 2,
ISM330DHCX_ROUND_GY_XL = 3,
} ism330dhcx_rounding_t;
int32_t ism330dhcx_rounding_mode_set(stmdev_ctx_t *ctx,
- ism330dhcx_rounding_t val);
+ ism330dhcx_rounding_t val);
int32_t ism330dhcx_rounding_mode_get(stmdev_ctx_t *ctx,
- ism330dhcx_rounding_t *val);
+ ism330dhcx_rounding_t *val);
-int32_t ism330dhcx_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t ism330dhcx_temperature_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
-int32_t ism330dhcx_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t ism330dhcx_angular_rate_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
-int32_t ism330dhcx_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t ism330dhcx_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
int32_t ism330dhcx_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t ism330dhcx_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t ism330dhcx_device_conf_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t ism330dhcx_device_conf_get(stmdev_ctx_t *ctx, uint8_t *val);
+
int32_t ism330dhcx_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dhcx_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t ism330dhcx_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t ism330dhcx_number_of_steps_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
int32_t ism330dhcx_steps_reset(stmdev_ctx_t *ctx);
-typedef enum {
+typedef enum
+{
ISM330DHCX_USER_BANK = 0,
ISM330DHCX_SENSOR_HUB_BANK = 1,
ISM330DHCX_EMBEDDED_FUNC_BANK = 2,
@@ -2873,23 +3043,25 @@ int32_t ism330dhcx_mem_bank_set(stmdev_ctx_t *ctx,
int32_t ism330dhcx_mem_bank_get(stmdev_ctx_t *ctx,
ism330dhcx_reg_access_t *val);
-int32_t ism330dhcx_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address,
- uint8_t *val);
+int32_t ism330dhcx_ln_pg_write_byte(stmdev_ctx_t *ctx,
+ uint16_t address,
+ uint8_t *val);
int32_t ism330dhcx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address,
- uint8_t *buf, uint8_t len);
+ uint8_t *buf, uint8_t len);
int32_t ism330dhcx_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add,
- uint8_t *val);
+ uint8_t *val);
int32_t ism330dhcx_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address,
- uint8_t *val);
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_DRDY_LATCHED = 0,
ISM330DHCX_DRDY_PULSED = 1,
} ism330dhcx_dataready_pulsed_t;
int32_t ism330dhcx_data_ready_mode_set(stmdev_ctx_t *ctx,
- ism330dhcx_dataready_pulsed_t val);
+ ism330dhcx_dataready_pulsed_t val);
int32_t ism330dhcx_data_ready_mode_get(stmdev_ctx_t *ctx,
- ism330dhcx_dataready_pulsed_t *val);
+ ism330dhcx_dataready_pulsed_t *val);
int32_t ism330dhcx_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
@@ -2897,30 +3069,33 @@ int32_t ism330dhcx_reset_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dhcx_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t ism330dhcx_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dhcx_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dhcx_auto_increment_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t ism330dhcx_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dhcx_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_XL_ST_DISABLE = 0,
ISM330DHCX_XL_ST_POSITIVE = 1,
ISM330DHCX_XL_ST_NEGATIVE = 2,
} ism330dhcx_st_xl_t;
int32_t ism330dhcx_xl_self_test_set(stmdev_ctx_t *ctx,
- ism330dhcx_st_xl_t val);
+ ism330dhcx_st_xl_t val);
int32_t ism330dhcx_xl_self_test_get(stmdev_ctx_t *ctx,
- ism330dhcx_st_xl_t *val);
+ ism330dhcx_st_xl_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_GY_ST_DISABLE = 0,
ISM330DHCX_GY_ST_POSITIVE = 1,
ISM330DHCX_GY_ST_NEGATIVE = 3,
} ism330dhcx_st_g_t;
int32_t ism330dhcx_gy_self_test_set(stmdev_ctx_t *ctx,
- ism330dhcx_st_g_t val);
+ ism330dhcx_st_g_t val);
int32_t ism330dhcx_gy_self_test_get(stmdev_ctx_t *ctx,
- ism330dhcx_st_g_t *val);
+ ism330dhcx_st_g_t *val);
int32_t ism330dhcx_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dhcx_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -2929,11 +3104,12 @@ int32_t ism330dhcx_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dhcx_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t ism330dhcx_filter_settling_mask_set(stmdev_ctx_t *ctx,
- uint8_t val);
+ uint8_t val);
int32_t ism330dhcx_filter_settling_mask_get(stmdev_ctx_t *ctx,
- uint8_t *val);
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_ULTRA_LIGHT = 0,
ISM330DHCX_VERY_LIGHT = 1,
ISM330DHCX_LIGHT = 2,
@@ -2944,14 +3120,15 @@ typedef enum {
ISM330DHCX_XTREME = 7,
} ism330dhcx_ftype_t;
int32_t ism330dhcx_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
- ism330dhcx_ftype_t val);
+ ism330dhcx_ftype_t val);
int32_t ism330dhcx_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
- ism330dhcx_ftype_t *val);
+ ism330dhcx_ftype_t *val);
int32_t ism330dhcx_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dhcx_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_HP_PATH_DISABLE_ON_OUT = 0x00,
ISM330DHCX_SLOPE_ODR_DIV_4 = 0x10,
ISM330DHCX_HP_ODR_DIV_10 = 0x11,
@@ -2977,23 +3154,27 @@ typedef enum {
ISM330DHCX_LP_ODR_DIV_800 = 0x07,
} ism330dhcx_hp_slope_xl_en_t;
int32_t ism330dhcx_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
- ism330dhcx_hp_slope_xl_en_t val);
+ ism330dhcx_hp_slope_xl_en_t val);
int32_t ism330dhcx_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
- ism330dhcx_hp_slope_xl_en_t *val);
+ ism330dhcx_hp_slope_xl_en_t *val);
-int32_t ism330dhcx_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dhcx_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dhcx_xl_fast_settling_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dhcx_xl_fast_settling_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_USE_SLOPE = 0,
ISM330DHCX_USE_HPF = 1,
} ism330dhcx_slope_fds_t;
int32_t ism330dhcx_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
- ism330dhcx_slope_fds_t val);
+ ism330dhcx_slope_fds_t val);
int32_t ism330dhcx_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
- ism330dhcx_slope_fds_t *val);
+ ism330dhcx_slope_fds_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_HP_FILTER_NONE = 0x00,
ISM330DHCX_HP_FILTER_16mHz = 0x80,
ISM330DHCX_HP_FILTER_65mHz = 0x81,
@@ -3001,83 +3182,92 @@ typedef enum {
ISM330DHCX_HP_FILTER_1Hz04 = 0x83,
} ism330dhcx_hpm_g_t;
int32_t ism330dhcx_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
- ism330dhcx_hpm_g_t val);
+ ism330dhcx_hpm_g_t val);
int32_t ism330dhcx_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
- ism330dhcx_hpm_g_t *val);
+ ism330dhcx_hpm_g_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_AUX_PULL_UP_DISC = 0,
ISM330DHCX_AUX_PULL_UP_CONNECT = 1,
} ism330dhcx_ois_pu_dis_t;
int32_t ism330dhcx_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx,
- ism330dhcx_ois_pu_dis_t val);
+ ism330dhcx_ois_pu_dis_t val);
int32_t ism330dhcx_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx,
- ism330dhcx_ois_pu_dis_t *val);
+ ism330dhcx_ois_pu_dis_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_AUX_ON = 1,
ISM330DHCX_AUX_ON_BY_AUX_INTERFACE = 0,
} ism330dhcx_ois_on_t;
int32_t ism330dhcx_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx,
- ism330dhcx_ois_on_t val);
+ ism330dhcx_ois_on_t val);
int32_t ism330dhcx_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx,
- ism330dhcx_ois_on_t *val);
+ ism330dhcx_ois_on_t *val);
int32_t ism330dhcx_aux_status_reg_get(stmdev_ctx_t *ctx,
- ism330dhcx_status_spiaux_t *val);
+ ism330dhcx_status_spiaux_t *val);
int32_t ism330dhcx_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
- uint8_t *val);
+ uint8_t *val);
int32_t ism330dhcx_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
- uint8_t *val);
+ uint8_t *val);
int32_t ism330dhcx_aux_gy_flag_settling_get(stmdev_ctx_t *ctx,
uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_AUX_XL_DISABLE = 0,
ISM330DHCX_AUX_XL_POS = 1,
ISM330DHCX_AUX_XL_NEG = 2,
} ism330dhcx_st_xl_ois_t;
int32_t ism330dhcx_aux_xl_self_test_set(stmdev_ctx_t *ctx,
- ism330dhcx_st_xl_ois_t val);
+ ism330dhcx_st_xl_ois_t val);
int32_t ism330dhcx_aux_xl_self_test_get(stmdev_ctx_t *ctx,
- ism330dhcx_st_xl_ois_t *val);
+ ism330dhcx_st_xl_ois_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_AUX_DEN_ACTIVE_LOW = 0,
ISM330DHCX_AUX_DEN_ACTIVE_HIGH = 1,
} ism330dhcx_den_lh_ois_t;
int32_t ism330dhcx_aux_den_polarity_set(stmdev_ctx_t *ctx,
- ism330dhcx_den_lh_ois_t val);
+ ism330dhcx_den_lh_ois_t val);
int32_t ism330dhcx_aux_den_polarity_get(stmdev_ctx_t *ctx,
- ism330dhcx_den_lh_ois_t *val);
+ ism330dhcx_den_lh_ois_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_AUX_DEN_DISABLE = 0,
ISM330DHCX_AUX_DEN_LEVEL_LATCH = 3,
ISM330DHCX_AUX_DEN_LEVEL_TRIG = 2,
} ism330dhcx_lvl2_ois_t;
int32_t ism330dhcx_aux_den_mode_set(stmdev_ctx_t *ctx,
- ism330dhcx_lvl2_ois_t val);
+ ism330dhcx_lvl2_ois_t val);
int32_t ism330dhcx_aux_den_mode_get(stmdev_ctx_t *ctx,
- ism330dhcx_lvl2_ois_t *val);
+ ism330dhcx_lvl2_ois_t *val);
-int32_t ism330dhcx_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dhcx_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dhcx_aux_drdy_on_int2_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dhcx_aux_drdy_on_int2_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_AUX_DISABLE = 0,
ISM330DHCX_MODE_3_GY = 1,
ISM330DHCX_MODE_4_GY_XL = 3,
} ism330dhcx_ois_en_spi2_t;
int32_t ism330dhcx_aux_mode_set(stmdev_ctx_t *ctx,
- ism330dhcx_ois_en_spi2_t val);
+ ism330dhcx_ois_en_spi2_t val);
int32_t ism330dhcx_aux_mode_get(stmdev_ctx_t *ctx,
- ism330dhcx_ois_en_spi2_t *val);
+ ism330dhcx_ois_en_spi2_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_125dps_AUX = 0x04,
ISM330DHCX_250dps_AUX = 0x00,
ISM330DHCX_500dps_AUX = 0x01,
@@ -3085,31 +3275,34 @@ typedef enum {
ISM330DHCX_2000dps_AUX = 0x03,
} ism330dhcx_fs_g_ois_t;
int32_t ism330dhcx_aux_gy_full_scale_set(stmdev_ctx_t *ctx,
- ism330dhcx_fs_g_ois_t val);
+ ism330dhcx_fs_g_ois_t val);
int32_t ism330dhcx_aux_gy_full_scale_get(stmdev_ctx_t *ctx,
- ism330dhcx_fs_g_ois_t *val);
+ ism330dhcx_fs_g_ois_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_AUX_SPI_4_WIRE = 0,
ISM330DHCX_AUX_SPI_3_WIRE = 1,
} ism330dhcx_sim_ois_t;
int32_t ism330dhcx_aux_spi_mode_set(stmdev_ctx_t *ctx,
- ism330dhcx_sim_ois_t val);
+ ism330dhcx_sim_ois_t val);
int32_t ism330dhcx_aux_spi_mode_get(stmdev_ctx_t *ctx,
- ism330dhcx_sim_ois_t *val);
+ ism330dhcx_sim_ois_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_351Hz39 = 0,
ISM330DHCX_236Hz63 = 1,
ISM330DHCX_172Hz70 = 2,
ISM330DHCX_937Hz91 = 3,
} ism330dhcx_ftype_ois_t;
int32_t ism330dhcx_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
- ism330dhcx_ftype_ois_t val);
+ ism330dhcx_ftype_ois_t val);
int32_t ism330dhcx_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
- ism330dhcx_ftype_ois_t *val);
+ ism330dhcx_ftype_ois_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_AUX_HP_DISABLE = 0x00,
ISM330DHCX_AUX_HP_Hz016 = 0x10,
ISM330DHCX_AUX_HP_Hz065 = 0x11,
@@ -3117,30 +3310,33 @@ typedef enum {
ISM330DHCX_AUX_HP_1Hz040 = 0x13,
} ism330dhcx_hpm_ois_t;
int32_t ism330dhcx_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx,
- ism330dhcx_hpm_ois_t val);
+ ism330dhcx_hpm_ois_t val);
int32_t ism330dhcx_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx,
- ism330dhcx_hpm_ois_t *val);
+ ism330dhcx_hpm_ois_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_ENABLE_CLAMP = 0,
ISM330DHCX_DISABLE_CLAMP = 1,
} ism330dhcx_st_ois_clampdis_t;
int32_t ism330dhcx_aux_gy_clamp_set(stmdev_ctx_t *ctx,
- ism330dhcx_st_ois_clampdis_t val);
+ ism330dhcx_st_ois_clampdis_t val);
int32_t ism330dhcx_aux_gy_clamp_get(stmdev_ctx_t *ctx,
- ism330dhcx_st_ois_clampdis_t *val);
+ ism330dhcx_st_ois_clampdis_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_AUX_GY_DISABLE = 0,
ISM330DHCX_AUX_GY_POS = 1,
ISM330DHCX_AUX_GY_NEG = 3,
} ism330dhcx_st_ois_t;
int32_t ism330dhcx_aux_gy_self_test_set(stmdev_ctx_t *ctx,
- ism330dhcx_st_ois_t val);
+ ism330dhcx_st_ois_t val);
int32_t ism330dhcx_aux_gy_self_test_get(stmdev_ctx_t *ctx,
- ism330dhcx_st_ois_t *val);
+ ism330dhcx_st_ois_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_631Hz = 0,
ISM330DHCX_295Hz = 1,
ISM330DHCX_140Hz = 2,
@@ -3151,60 +3347,68 @@ typedef enum {
ISM330DHCX_4Hz11 = 7,
} ism330dhcx_filter_xl_conf_ois_t;
int32_t ism330dhcx_aux_xl_bandwidth_set(stmdev_ctx_t *ctx,
- ism330dhcx_filter_xl_conf_ois_t val);
+ ism330dhcx_filter_xl_conf_ois_t val);
int32_t ism330dhcx_aux_xl_bandwidth_get(stmdev_ctx_t *ctx,
- ism330dhcx_filter_xl_conf_ois_t *val);
+ ism330dhcx_filter_xl_conf_ois_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_AUX_2g = 0,
ISM330DHCX_AUX_16g = 1,
ISM330DHCX_AUX_4g = 2,
ISM330DHCX_AUX_8g = 3,
} ism330dhcx_fs_xl_ois_t;
int32_t ism330dhcx_aux_xl_full_scale_set(stmdev_ctx_t *ctx,
- ism330dhcx_fs_xl_ois_t val);
+ ism330dhcx_fs_xl_ois_t val);
int32_t ism330dhcx_aux_xl_full_scale_get(stmdev_ctx_t *ctx,
- ism330dhcx_fs_xl_ois_t *val);
+ ism330dhcx_fs_xl_ois_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_PULL_UP_DISC = 0,
ISM330DHCX_PULL_UP_CONNECT = 1,
} ism330dhcx_sdo_pu_en_t;
int32_t ism330dhcx_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
- ism330dhcx_sdo_pu_en_t val);
+ ism330dhcx_sdo_pu_en_t val);
int32_t ism330dhcx_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
- ism330dhcx_sdo_pu_en_t *val);
+ ism330dhcx_sdo_pu_en_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_SPI_4_WIRE = 0,
ISM330DHCX_SPI_3_WIRE = 1,
} ism330dhcx_sim_t;
-int32_t ism330dhcx_spi_mode_set(stmdev_ctx_t *ctx, ism330dhcx_sim_t val);
-int32_t ism330dhcx_spi_mode_get(stmdev_ctx_t *ctx, ism330dhcx_sim_t *val);
+int32_t ism330dhcx_spi_mode_set(stmdev_ctx_t *ctx,
+ ism330dhcx_sim_t val);
+int32_t ism330dhcx_spi_mode_get(stmdev_ctx_t *ctx,
+ ism330dhcx_sim_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_I2C_ENABLE = 0,
ISM330DHCX_I2C_DISABLE = 1,
} ism330dhcx_i2c_disable_t;
int32_t ism330dhcx_i2c_interface_set(stmdev_ctx_t *ctx,
- ism330dhcx_i2c_disable_t val);
+ ism330dhcx_i2c_disable_t val);
int32_t ism330dhcx_i2c_interface_get(stmdev_ctx_t *ctx,
- ism330dhcx_i2c_disable_t *val);
-
-typedef struct {
- ism330dhcx_int1_ctrl_t int1_ctrl;
- ism330dhcx_md1_cfg_t md1_cfg;
- ism330dhcx_emb_func_int1_t emb_func_int1;
- ism330dhcx_fsm_int1_a_t fsm_int1_a;
- ism330dhcx_fsm_int1_b_t fsm_int1_b;
- ism330dhcx_mlc_int1_t mlc_int1;
+ ism330dhcx_i2c_disable_t *val);
+
+typedef struct
+{
+ ism330dhcx_int1_ctrl_t int1_ctrl;
+ ism330dhcx_md1_cfg_t md1_cfg;
+ ism330dhcx_emb_func_int1_t emb_func_int1;
+ ism330dhcx_fsm_int1_a_t fsm_int1_a;
+ ism330dhcx_fsm_int1_b_t fsm_int1_b;
+ ism330dhcx_mlc_int1_t mlc_int1;
} ism330dhcx_pin_int1_route_t;
int32_t ism330dhcx_pin_int1_route_set(stmdev_ctx_t *ctx,
- ism330dhcx_pin_int1_route_t *val);
+ ism330dhcx_pin_int1_route_t *val);
int32_t ism330dhcx_pin_int1_route_get(stmdev_ctx_t *ctx,
- ism330dhcx_pin_int1_route_t *val);
+ ism330dhcx_pin_int1_route_t *val);
-typedef struct {
+typedef struct
+{
ism330dhcx_int2_ctrl_t int2_ctrl;
ism330dhcx_md2_cfg_t md2_cfg;
ism330dhcx_emb_func_int2_t emb_func_int2;
@@ -3213,11 +3417,12 @@ typedef struct {
ism330dhcx_mlc_int2_t mlc_int2;
} ism330dhcx_pin_int2_route_t;
int32_t ism330dhcx_pin_int2_route_set(stmdev_ctx_t *ctx,
- ism330dhcx_pin_int2_route_t *val);
+ ism330dhcx_pin_int2_route_t *val);
int32_t ism330dhcx_pin_int2_route_get(stmdev_ctx_t *ctx,
- ism330dhcx_pin_int2_route_t *val);
+ ism330dhcx_pin_int2_route_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_PUSH_PULL = 0,
ISM330DHCX_OPEN_DRAIN = 1,
} ism330dhcx_pp_od_t;
@@ -3226,45 +3431,49 @@ int32_t ism330dhcx_pin_mode_set(stmdev_ctx_t *ctx,
int32_t ism330dhcx_pin_mode_get(stmdev_ctx_t *ctx,
ism330dhcx_pp_od_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_ACTIVE_HIGH = 0,
ISM330DHCX_ACTIVE_LOW = 1,
} ism330dhcx_h_lactive_t;
int32_t ism330dhcx_pin_polarity_set(stmdev_ctx_t *ctx,
- ism330dhcx_h_lactive_t val);
+ ism330dhcx_h_lactive_t val);
int32_t ism330dhcx_pin_polarity_get(stmdev_ctx_t *ctx,
- ism330dhcx_h_lactive_t *val);
+ ism330dhcx_h_lactive_t *val);
int32_t ism330dhcx_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dhcx_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_ALL_INT_PULSED = 0,
ISM330DHCX_BASE_LATCHED_EMB_PULSED = 1,
ISM330DHCX_BASE_PULSED_EMB_LATCHED = 2,
ISM330DHCX_ALL_INT_LATCHED = 3,
} ism330dhcx_lir_t;
int32_t ism330dhcx_int_notification_set(stmdev_ctx_t *ctx,
- ism330dhcx_lir_t val);
+ ism330dhcx_lir_t val);
int32_t ism330dhcx_int_notification_get(stmdev_ctx_t *ctx,
- ism330dhcx_lir_t *val);
+ ism330dhcx_lir_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_LSb_FS_DIV_64 = 0,
ISM330DHCX_LSb_FS_DIV_256 = 1,
} ism330dhcx_wake_ths_w_t;
int32_t ism330dhcx_wkup_ths_weight_set(stmdev_ctx_t *ctx,
- ism330dhcx_wake_ths_w_t val);
+ ism330dhcx_wake_ths_w_t val);
int32_t ism330dhcx_wkup_ths_weight_get(stmdev_ctx_t *ctx,
- ism330dhcx_wake_ths_w_t *val);
+ ism330dhcx_wake_ths_w_t *val);
int32_t ism330dhcx_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dhcx_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dhcx_wkup_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t ism330dhcx_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx,
- uint8_t val);
+ uint8_t val);
int32_t ism330dhcx_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx,
- uint8_t *val);
+ uint8_t *val);
int32_t ism330dhcx_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dhcx_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -3272,42 +3481,53 @@ int32_t ism330dhcx_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t ism330dhcx_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dhcx_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_DRIVE_SLEEP_CHG_EVENT = 0,
ISM330DHCX_DRIVE_SLEEP_STATUS = 1,
} ism330dhcx_sleep_status_on_int_t;
int32_t ism330dhcx_act_pin_notification_set(stmdev_ctx_t *ctx,
- ism330dhcx_sleep_status_on_int_t val);
+ ism330dhcx_sleep_status_on_int_t val);
int32_t ism330dhcx_act_pin_notification_get(stmdev_ctx_t *ctx,
- ism330dhcx_sleep_status_on_int_t *val);
+ ism330dhcx_sleep_status_on_int_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_XL_AND_GY_NOT_AFFECTED = 0,
ISM330DHCX_XL_12Hz5_GY_NOT_AFFECTED = 1,
ISM330DHCX_XL_12Hz5_GY_SLEEP = 2,
ISM330DHCX_XL_12Hz5_GY_PD = 3,
} ism330dhcx_inact_en_t;
int32_t ism330dhcx_act_mode_set(stmdev_ctx_t *ctx,
- ism330dhcx_inact_en_t val);
+ ism330dhcx_inact_en_t val);
int32_t ism330dhcx_act_mode_get(stmdev_ctx_t *ctx,
- ism330dhcx_inact_en_t *val);
+ ism330dhcx_inact_en_t *val);
int32_t ism330dhcx_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dhcx_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t ism330dhcx_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dhcx_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dhcx_tap_detection_on_z_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dhcx_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t ism330dhcx_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dhcx_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dhcx_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dhcx_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t ism330dhcx_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dhcx_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dhcx_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dhcx_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t ism330dhcx_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dhcx_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dhcx_tap_threshold_x_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dhcx_tap_threshold_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_XYZ = 0,
ISM330DHCX_YXZ = 1,
ISM330DHCX_XZY = 2,
@@ -3316,15 +3536,19 @@ typedef enum {
ISM330DHCX_ZXY = 6,
} ism330dhcx_tap_priority_t;
int32_t ism330dhcx_tap_axis_priority_set(stmdev_ctx_t *ctx,
- ism330dhcx_tap_priority_t val);
+ ism330dhcx_tap_priority_t val);
int32_t ism330dhcx_tap_axis_priority_get(stmdev_ctx_t *ctx,
- ism330dhcx_tap_priority_t *val);
+ ism330dhcx_tap_priority_t *val);
-int32_t ism330dhcx_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dhcx_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dhcx_tap_threshold_y_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dhcx_tap_threshold_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t ism330dhcx_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dhcx_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dhcx_tap_threshold_z_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dhcx_tap_threshold_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t ism330dhcx_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dhcx_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -3335,30 +3559,33 @@ int32_t ism330dhcx_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t ism330dhcx_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dhcx_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_ONLY_SINGLE = 0,
ISM330DHCX_BOTH_SINGLE_DOUBLE = 1,
} ism330dhcx_single_double_tap_t;
int32_t ism330dhcx_tap_mode_set(stmdev_ctx_t *ctx,
- ism330dhcx_single_double_tap_t val);
+ ism330dhcx_single_double_tap_t val);
int32_t ism330dhcx_tap_mode_get(stmdev_ctx_t *ctx,
- ism330dhcx_single_double_tap_t *val);
+ ism330dhcx_single_double_tap_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_DEG_80 = 0,
ISM330DHCX_DEG_70 = 1,
ISM330DHCX_DEG_60 = 2,
ISM330DHCX_DEG_50 = 3,
} ism330dhcx_sixd_ths_t;
int32_t ism330dhcx_6d_threshold_set(stmdev_ctx_t *ctx,
- ism330dhcx_sixd_ths_t val);
+ ism330dhcx_sixd_ths_t val);
int32_t ism330dhcx_6d_threshold_get(stmdev_ctx_t *ctx,
- ism330dhcx_sixd_ths_t *val);
+ ism330dhcx_sixd_ths_t *val);
int32_t ism330dhcx_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dhcx_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_FF_TSH_156mg = 0,
ISM330DHCX_FF_TSH_219mg = 1,
ISM330DHCX_FF_TSH_250mg = 2,
@@ -3369,20 +3596,25 @@ typedef enum {
ISM330DHCX_FF_TSH_500mg = 7,
} ism330dhcx_ff_ths_t;
int32_t ism330dhcx_ff_threshold_set(stmdev_ctx_t *ctx,
- ism330dhcx_ff_ths_t val);
+ ism330dhcx_ff_ths_t val);
int32_t ism330dhcx_ff_threshold_get(stmdev_ctx_t *ctx,
- ism330dhcx_ff_ths_t *val);
+ ism330dhcx_ff_ths_t *val);
int32_t ism330dhcx_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dhcx_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t ism330dhcx_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val);
-int32_t ism330dhcx_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t ism330dhcx_fifo_watermark_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t ism330dhcx_fifo_watermark_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
-int32_t ism330dhcx_compression_algo_init_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dhcx_compression_algo_init_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dhcx_compression_algo_init_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dhcx_compression_algo_init_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_CMP_DISABLE = 0x00,
ISM330DHCX_CMP_ALWAYS = 0x04,
ISM330DHCX_CMP_8_TO_1 = 0x05,
@@ -3390,25 +3622,28 @@ typedef enum {
ISM330DHCX_CMP_32_TO_1 = 0x07,
} ism330dhcx_uncoptr_rate_t;
int32_t ism330dhcx_compression_algo_set(stmdev_ctx_t *ctx,
- ism330dhcx_uncoptr_rate_t val);
+ ism330dhcx_uncoptr_rate_t val);
int32_t ism330dhcx_compression_algo_get(stmdev_ctx_t *ctx,
- ism330dhcx_uncoptr_rate_t *val);
+ ism330dhcx_uncoptr_rate_t *val);
int32_t ism330dhcx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
- uint8_t val);
+ uint8_t val);
int32_t ism330dhcx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
- uint8_t *val);
+ uint8_t *val);
int32_t ism330dhcx_compression_algo_real_time_set(stmdev_ctx_t *ctx,
- uint8_t val);
+ uint8_t val);
int32_t ism330dhcx_compression_algo_real_time_get(stmdev_ctx_t *ctx,
- uint8_t *val);
+ uint8_t *val);
-int32_t ism330dhcx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dhcx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dhcx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dhcx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
- ISM330DHCX_XL_NOT_BATCHED = 0,
+typedef enum
+{
+ ISM330DHCX_XL_NOT_BATCHED = 0,
ISM330DHCX_XL_BATCHED_AT_12Hz5 = 1,
ISM330DHCX_XL_BATCHED_AT_26Hz = 2,
ISM330DHCX_XL_BATCHED_AT_52Hz = 3,
@@ -3426,7 +3661,8 @@ int32_t ism330dhcx_fifo_xl_batch_set(stmdev_ctx_t *ctx,
int32_t ism330dhcx_fifo_xl_batch_get(stmdev_ctx_t *ctx,
ism330dhcx_bdr_xl_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_GY_NOT_BATCHED = 0,
ISM330DHCX_GY_BATCHED_AT_12Hz5 = 1,
ISM330DHCX_GY_BATCHED_AT_26Hz = 2,
@@ -3445,7 +3681,8 @@ int32_t ism330dhcx_fifo_gy_batch_set(stmdev_ctx_t *ctx,
int32_t ism330dhcx_fifo_gy_batch_get(stmdev_ctx_t *ctx,
ism330dhcx_bdr_gy_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_BYPASS_MODE = 0,
ISM330DHCX_FIFO_MODE = 1,
ISM330DHCX_STREAM_TO_FIFO_MODE = 3,
@@ -3458,57 +3695,65 @@ int32_t ism330dhcx_fifo_mode_set(stmdev_ctx_t *ctx,
int32_t ism330dhcx_fifo_mode_get(stmdev_ctx_t *ctx,
ism330dhcx_fifo_mode_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_TEMP_NOT_BATCHED = 0,
ISM330DHCX_TEMP_BATCHED_AT_52Hz = 1,
ISM330DHCX_TEMP_BATCHED_AT_12Hz5 = 2,
ISM330DHCX_TEMP_BATCHED_AT_1Hz6 = 3,
} ism330dhcx_odr_t_batch_t;
int32_t ism330dhcx_fifo_temp_batch_set(stmdev_ctx_t *ctx,
- ism330dhcx_odr_t_batch_t val);
+ ism330dhcx_odr_t_batch_t val);
int32_t ism330dhcx_fifo_temp_batch_get(stmdev_ctx_t *ctx,
- ism330dhcx_odr_t_batch_t *val);
+ ism330dhcx_odr_t_batch_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_NO_DECIMATION = 0,
ISM330DHCX_DEC_1 = 1,
ISM330DHCX_DEC_8 = 2,
ISM330DHCX_DEC_32 = 3,
} ism330dhcx_odr_ts_batch_t;
int32_t ism330dhcx_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
- ism330dhcx_odr_ts_batch_t val);
+ ism330dhcx_odr_ts_batch_t val);
int32_t ism330dhcx_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
- ism330dhcx_odr_ts_batch_t *val);
+ ism330dhcx_odr_ts_batch_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_XL_BATCH_EVENT = 0,
ISM330DHCX_GYRO_BATCH_EVENT = 1,
} ism330dhcx_trig_counter_bdr_t;
int32_t ism330dhcx_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
- ism330dhcx_trig_counter_bdr_t val);
+ ism330dhcx_trig_counter_bdr_t val);
int32_t ism330dhcx_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
- ism330dhcx_trig_counter_bdr_t *val);
+ ism330dhcx_trig_counter_bdr_t *val);
-int32_t ism330dhcx_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dhcx_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dhcx_rst_batch_counter_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dhcx_rst_batch_counter_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t ism330dhcx_batch_counter_threshold_set(stmdev_ctx_t *ctx,
- uint16_t val);
+ uint16_t val);
int32_t ism330dhcx_batch_counter_threshold_get(stmdev_ctx_t *ctx,
- uint16_t *val);
+ uint16_t *val);
-int32_t ism330dhcx_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t ism330dhcx_fifo_data_level_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
int32_t ism330dhcx_fifo_status_get(stmdev_ctx_t *ctx,
- ism330dhcx_fifo_status2_t *val);
+ ism330dhcx_fifo_status2_t *val);
-int32_t ism330dhcx_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dhcx_fifo_full_flag_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t ism330dhcx_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t ism330dhcx_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_GYRO_NC_TAG = 1,
ISM330DHCX_XL_NC_TAG,
ISM330DHCX_TEMPERATURE_TAG,
@@ -3530,27 +3775,38 @@ typedef enum {
ISM330DHCX_GAME_ROTATION_TAG,
ISM330DHCX_GEOMAG_ROTATION_TAG,
ISM330DHCX_ROTATION_TAG,
- ISM330DHCX_SENSORHUB_NACK_TAG = 0x19,
+ ISM330DHCX_SENSORHUB_NACK_TAG = 0x19,
} ism330dhcx_fifo_tag_t;
int32_t ism330dhcx_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
- ism330dhcx_fifo_tag_t *val);
-
-int32_t ism330dhcx_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dhcx_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val);
-
-int32_t ism330dhcx_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dhcx_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val);
-
-int32_t ism330dhcx_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dhcx_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val);
-
-int32_t ism330dhcx_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dhcx_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val);
-
-int32_t ism330dhcx_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dhcx_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val);
-
-typedef enum {
+ ism330dhcx_fifo_tag_t *val);
+
+int32_t ism330dhcx_fifo_pedo_batch_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dhcx_fifo_pedo_batch_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t ism330dhcx_sh_batch_slave_0_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dhcx_sh_batch_slave_0_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t ism330dhcx_sh_batch_slave_1_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dhcx_sh_batch_slave_1_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t ism330dhcx_sh_batch_slave_2_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dhcx_sh_batch_slave_2_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t ism330dhcx_sh_batch_slave_3_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dhcx_sh_batch_slave_3_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+typedef enum
+{
ISM330DHCX_DEN_DISABLE = 0,
ISM330DHCX_LEVEL_FIFO = 6,
ISM330DHCX_LEVEL_LETCHED = 3,
@@ -3558,63 +3814,77 @@ typedef enum {
ISM330DHCX_EDGE_TRIGGER = 4,
} ism330dhcx_den_mode_t;
int32_t ism330dhcx_den_mode_set(stmdev_ctx_t *ctx,
- ism330dhcx_den_mode_t val);
+ ism330dhcx_den_mode_t val);
int32_t ism330dhcx_den_mode_get(stmdev_ctx_t *ctx,
- ism330dhcx_den_mode_t *val);
+ ism330dhcx_den_mode_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_DEN_ACT_LOW = 0,
ISM330DHCX_DEN_ACT_HIGH = 1,
} ism330dhcx_den_lh_t;
int32_t ism330dhcx_den_polarity_set(stmdev_ctx_t *ctx,
- ism330dhcx_den_lh_t val);
+ ism330dhcx_den_lh_t val);
int32_t ism330dhcx_den_polarity_get(stmdev_ctx_t *ctx,
- ism330dhcx_den_lh_t *val);
+ ism330dhcx_den_lh_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_STAMP_IN_GY_DATA = 0,
ISM330DHCX_STAMP_IN_XL_DATA = 1,
ISM330DHCX_STAMP_IN_GY_XL_DATA = 2,
} ism330dhcx_den_xl_g_t;
int32_t ism330dhcx_den_enable_set(stmdev_ctx_t *ctx,
- ism330dhcx_den_xl_g_t val);
+ ism330dhcx_den_xl_g_t val);
int32_t ism330dhcx_den_enable_get(stmdev_ctx_t *ctx,
- ism330dhcx_den_xl_g_t *val);
+ ism330dhcx_den_xl_g_t *val);
-int32_t ism330dhcx_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dhcx_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dhcx_den_mark_axis_x_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dhcx_den_mark_axis_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t ism330dhcx_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dhcx_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dhcx_den_mark_axis_y_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dhcx_den_mark_axis_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t ism330dhcx_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dhcx_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dhcx_den_mark_axis_z_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dhcx_den_mark_axis_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t ism330dhcx_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dhcx_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t ism330dhcx_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dhcx_pedo_step_detect_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t ism330dhcx_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t ism330dhcx_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t ism330dhcx_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t ism330dhcx_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
-int32_t ism330dhcx_pedo_steps_period_set(stmdev_ctx_t *ctx, uint16_t val);
-int32_t ism330dhcx_pedo_steps_period_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t ism330dhcx_pedo_steps_period_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t ism330dhcx_pedo_steps_period_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_EVERY_STEP = 0,
ISM330DHCX_COUNT_OVERFLOW = 1,
} ism330dhcx_carry_count_en_t;
int32_t ism330dhcx_pedo_int_mode_set(stmdev_ctx_t *ctx,
- ism330dhcx_carry_count_en_t val);
+ ism330dhcx_carry_count_en_t val);
int32_t ism330dhcx_pedo_int_mode_get(stmdev_ctx_t *ctx,
- ism330dhcx_carry_count_en_t *val);
+ ism330dhcx_carry_count_en_t *val);
int32_t ism330dhcx_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dhcx_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t ism330dhcx_motion_flag_data_ready_get(stmdev_ctx_t *ctx,
- uint8_t *val);
+ uint8_t *val);
int32_t ism330dhcx_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dhcx_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -3622,16 +3892,21 @@ int32_t ism330dhcx_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t ism330dhcx_tilt_flag_data_ready_get(stmdev_ctx_t *ctx,
uint8_t *val);
-int32_t ism330dhcx_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val);
-int32_t ism330dhcx_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t ism330dhcx_mag_sensitivity_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t ism330dhcx_mag_sensitivity_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
int32_t ism330dhcx_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val);
int32_t ism330dhcx_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val);
-int32_t ism330dhcx_mag_soft_iron_set(stmdev_ctx_t *ctx, uint16_t *val);
-int32_t ism330dhcx_mag_soft_iron_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t ism330dhcx_mag_soft_iron_set(stmdev_ctx_t *ctx,
+ uint16_t *val);
+int32_t ism330dhcx_mag_soft_iron_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_Z_EQ_Y = 0,
ISM330DHCX_Z_EQ_MIN_Y = 1,
ISM330DHCX_Z_EQ_X = 2,
@@ -3640,11 +3915,12 @@ typedef enum {
ISM330DHCX_Z_EQ_Z = 5,
} ism330dhcx_mag_z_axis_t;
int32_t ism330dhcx_mag_z_orient_set(stmdev_ctx_t *ctx,
- ism330dhcx_mag_z_axis_t val);
+ ism330dhcx_mag_z_axis_t val);
int32_t ism330dhcx_mag_z_orient_get(stmdev_ctx_t *ctx,
- ism330dhcx_mag_z_axis_t *val);
+ ism330dhcx_mag_z_axis_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_Y_EQ_Y = 0,
ISM330DHCX_Y_EQ_MIN_Y = 1,
ISM330DHCX_Y_EQ_X = 2,
@@ -3653,11 +3929,12 @@ typedef enum {
ISM330DHCX_Y_EQ_Z = 5,
} ism330dhcx_mag_y_axis_t;
int32_t ism330dhcx_mag_y_orient_set(stmdev_ctx_t *ctx,
- ism330dhcx_mag_y_axis_t val);
+ ism330dhcx_mag_y_axis_t val);
int32_t ism330dhcx_mag_y_orient_get(stmdev_ctx_t *ctx,
- ism330dhcx_mag_y_axis_t *val);
+ ism330dhcx_mag_y_axis_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_X_EQ_Y = 0,
ISM330DHCX_X_EQ_MIN_Y = 1,
ISM330DHCX_X_EQ_X = 2,
@@ -3666,83 +3943,91 @@ typedef enum {
ISM330DHCX_X_EQ_Z = 5,
} ism330dhcx_mag_x_axis_t;
int32_t ism330dhcx_mag_x_orient_set(stmdev_ctx_t *ctx,
- ism330dhcx_mag_x_axis_t val);
+ ism330dhcx_mag_x_axis_t val);
int32_t ism330dhcx_mag_x_orient_get(stmdev_ctx_t *ctx,
- ism330dhcx_mag_x_axis_t *val);
+ ism330dhcx_mag_x_axis_t *val);
int32_t ism330dhcx_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
- uint8_t *val);
+ uint8_t *val);
int32_t ism330dhcx_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dhcx_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef struct {
- ism330dhcx_fsm_enable_a_t fsm_enable_a;
- ism330dhcx_fsm_enable_b_t fsm_enable_b;
+typedef struct
+{
+ ism330dhcx_fsm_enable_a_t fsm_enable_a;
+ ism330dhcx_fsm_enable_b_t fsm_enable_b;
} ism330dhcx_emb_fsm_enable_t;
int32_t ism330dhcx_fsm_enable_set(stmdev_ctx_t *ctx,
- ism330dhcx_emb_fsm_enable_t *val);
+ ism330dhcx_emb_fsm_enable_t *val);
int32_t ism330dhcx_fsm_enable_get(stmdev_ctx_t *ctx,
- ism330dhcx_emb_fsm_enable_t *val);
+ ism330dhcx_emb_fsm_enable_t *val);
int32_t ism330dhcx_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val);
int32_t ism330dhcx_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_LC_NORMAL = 0,
ISM330DHCX_LC_CLEAR = 1,
ISM330DHCX_LC_CLEAR_DONE = 2,
} ism330dhcx_fsm_lc_clr_t;
int32_t ism330dhcx_long_clr_set(stmdev_ctx_t *ctx,
- ism330dhcx_fsm_lc_clr_t val);
+ ism330dhcx_fsm_lc_clr_t val);
int32_t ism330dhcx_long_clr_get(stmdev_ctx_t *ctx,
- ism330dhcx_fsm_lc_clr_t *val);
-
-typedef struct {
- ism330dhcx_fsm_outs1_t fsm_outs1;
- ism330dhcx_fsm_outs2_t fsm_outs2;
- ism330dhcx_fsm_outs3_t fsm_outs3;
- ism330dhcx_fsm_outs4_t fsm_outs4;
- ism330dhcx_fsm_outs5_t fsm_outs5;
- ism330dhcx_fsm_outs6_t fsm_outs6;
- ism330dhcx_fsm_outs7_t fsm_outs7;
- ism330dhcx_fsm_outs8_t fsm_outs8;
- ism330dhcx_fsm_outs9_t fsm_outs9;
- ism330dhcx_fsm_outs10_t fsm_outs10;
- ism330dhcx_fsm_outs11_t fsm_outs11;
- ism330dhcx_fsm_outs12_t fsm_outs12;
- ism330dhcx_fsm_outs13_t fsm_outs13;
- ism330dhcx_fsm_outs14_t fsm_outs14;
- ism330dhcx_fsm_outs15_t fsm_outs15;
- ism330dhcx_fsm_outs16_t fsm_outs16;
+ ism330dhcx_fsm_lc_clr_t *val);
+
+typedef struct
+{
+ ism330dhcx_fsm_outs1_t fsm_outs1;
+ ism330dhcx_fsm_outs2_t fsm_outs2;
+ ism330dhcx_fsm_outs3_t fsm_outs3;
+ ism330dhcx_fsm_outs4_t fsm_outs4;
+ ism330dhcx_fsm_outs5_t fsm_outs5;
+ ism330dhcx_fsm_outs6_t fsm_outs6;
+ ism330dhcx_fsm_outs7_t fsm_outs7;
+ ism330dhcx_fsm_outs8_t fsm_outs8;
+ ism330dhcx_fsm_outs9_t fsm_outs9;
+ ism330dhcx_fsm_outs10_t fsm_outs10;
+ ism330dhcx_fsm_outs11_t fsm_outs11;
+ ism330dhcx_fsm_outs12_t fsm_outs12;
+ ism330dhcx_fsm_outs13_t fsm_outs13;
+ ism330dhcx_fsm_outs14_t fsm_outs14;
+ ism330dhcx_fsm_outs15_t fsm_outs15;
+ ism330dhcx_fsm_outs16_t fsm_outs16;
} ism330dhcx_fsm_out_t;
int32_t ism330dhcx_fsm_out_get(stmdev_ctx_t *ctx,
ism330dhcx_fsm_out_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_ODR_FSM_12Hz5 = 0,
ISM330DHCX_ODR_FSM_26Hz = 1,
ISM330DHCX_ODR_FSM_52Hz = 2,
ISM330DHCX_ODR_FSM_104Hz = 3,
} ism330dhcx_fsm_odr_t;
int32_t ism330dhcx_fsm_data_rate_set(stmdev_ctx_t *ctx,
- ism330dhcx_fsm_odr_t val);
+ ism330dhcx_fsm_odr_t val);
int32_t ism330dhcx_fsm_data_rate_get(stmdev_ctx_t *ctx,
- ism330dhcx_fsm_odr_t *val);
+ ism330dhcx_fsm_odr_t *val);
int32_t ism330dhcx_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dhcx_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t ism330dhcx_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint16_t val);
-int32_t ism330dhcx_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t ism330dhcx_long_cnt_int_value_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t ism330dhcx_long_cnt_int_value_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
int32_t ism330dhcx_fsm_number_of_programs_set(stmdev_ctx_t *ctx,
uint8_t *buff);
int32_t ism330dhcx_fsm_number_of_programs_get(stmdev_ctx_t *ctx,
uint8_t *buff);
-int32_t ism330dhcx_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val);
-int32_t ism330dhcx_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t ism330dhcx_fsm_start_address_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t ism330dhcx_fsm_start_address_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
int32_t ism330dhcx_mlc_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dhcx_mlc_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -3750,7 +4035,8 @@ int32_t ism330dhcx_mlc_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t ism330dhcx_mlc_status_get(stmdev_ctx_t *ctx,
ism330dhcx_mlc_status_mainpage_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_ODR_PRGS_12Hz5 = 0,
ISM330DHCX_ODR_PRGS_26Hz = 1,
ISM330DHCX_ODR_PRGS_52Hz = 2,
@@ -3761,111 +4047,122 @@ int32_t ism330dhcx_mlc_data_rate_set(stmdev_ctx_t *ctx,
int32_t ism330dhcx_mlc_data_rate_get(stmdev_ctx_t *ctx,
ism330dhcx_mlc_odr_t *val);
-typedef struct {
- ism330dhcx_sensor_hub_1_t sh_byte_1;
- ism330dhcx_sensor_hub_2_t sh_byte_2;
- ism330dhcx_sensor_hub_3_t sh_byte_3;
- ism330dhcx_sensor_hub_4_t sh_byte_4;
- ism330dhcx_sensor_hub_5_t sh_byte_5;
- ism330dhcx_sensor_hub_6_t sh_byte_6;
- ism330dhcx_sensor_hub_7_t sh_byte_7;
- ism330dhcx_sensor_hub_8_t sh_byte_8;
- ism330dhcx_sensor_hub_9_t sh_byte_9;
- ism330dhcx_sensor_hub_10_t sh_byte_10;
- ism330dhcx_sensor_hub_11_t sh_byte_11;
- ism330dhcx_sensor_hub_12_t sh_byte_12;
- ism330dhcx_sensor_hub_13_t sh_byte_13;
- ism330dhcx_sensor_hub_14_t sh_byte_14;
- ism330dhcx_sensor_hub_15_t sh_byte_15;
- ism330dhcx_sensor_hub_16_t sh_byte_16;
- ism330dhcx_sensor_hub_17_t sh_byte_17;
- ism330dhcx_sensor_hub_18_t sh_byte_18;
+typedef struct
+{
+ ism330dhcx_sensor_hub_1_t sh_byte_1;
+ ism330dhcx_sensor_hub_2_t sh_byte_2;
+ ism330dhcx_sensor_hub_3_t sh_byte_3;
+ ism330dhcx_sensor_hub_4_t sh_byte_4;
+ ism330dhcx_sensor_hub_5_t sh_byte_5;
+ ism330dhcx_sensor_hub_6_t sh_byte_6;
+ ism330dhcx_sensor_hub_7_t sh_byte_7;
+ ism330dhcx_sensor_hub_8_t sh_byte_8;
+ ism330dhcx_sensor_hub_9_t sh_byte_9;
+ ism330dhcx_sensor_hub_10_t sh_byte_10;
+ ism330dhcx_sensor_hub_11_t sh_byte_11;
+ ism330dhcx_sensor_hub_12_t sh_byte_12;
+ ism330dhcx_sensor_hub_13_t sh_byte_13;
+ ism330dhcx_sensor_hub_14_t sh_byte_14;
+ ism330dhcx_sensor_hub_15_t sh_byte_15;
+ ism330dhcx_sensor_hub_16_t sh_byte_16;
+ ism330dhcx_sensor_hub_17_t sh_byte_17;
+ ism330dhcx_sensor_hub_18_t sh_byte_18;
} ism330dhcx_emb_sh_read_t;
int32_t ism330dhcx_sh_read_data_raw_get(stmdev_ctx_t *ctx,
- ism330dhcx_emb_sh_read_t *val);
+ ism330dhcx_emb_sh_read_t *val,
+ uint8_t len);
-typedef enum {
+typedef enum
+{
ISM330DHCX_SLV_0 = 0,
ISM330DHCX_SLV_0_1 = 1,
ISM330DHCX_SLV_0_1_2 = 2,
ISM330DHCX_SLV_0_1_2_3 = 3,
} ism330dhcx_aux_sens_on_t;
int32_t ism330dhcx_sh_slave_connected_set(stmdev_ctx_t *ctx,
- ism330dhcx_aux_sens_on_t val);
+ ism330dhcx_aux_sens_on_t val);
int32_t ism330dhcx_sh_slave_connected_get(stmdev_ctx_t *ctx,
- ism330dhcx_aux_sens_on_t *val);
+ ism330dhcx_aux_sens_on_t *val);
int32_t ism330dhcx_sh_master_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dhcx_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_EXT_PULL_UP = 0,
ISM330DHCX_INTERNAL_PULL_UP = 1,
} ism330dhcx_shub_pu_en_t;
int32_t ism330dhcx_sh_pin_mode_set(stmdev_ctx_t *ctx,
- ism330dhcx_shub_pu_en_t val);
+ ism330dhcx_shub_pu_en_t val);
int32_t ism330dhcx_sh_pin_mode_get(stmdev_ctx_t *ctx,
- ism330dhcx_shub_pu_en_t *val);
+ ism330dhcx_shub_pu_en_t *val);
-int32_t ism330dhcx_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dhcx_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dhcx_sh_pass_through_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dhcx_sh_pass_through_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
- ISM330DHCX_EXT_ON_INT2_PIN = 0,
- ISM330DHCX_XL_GY_DRDY = 1,
+typedef enum
+{
+ ISM330DHCX_EXT_ON_INT2_PIN = 1,
+ ISM330DHCX_XL_GY_DRDY = 0,
} ism330dhcx_start_config_t;
int32_t ism330dhcx_sh_syncro_mode_set(stmdev_ctx_t *ctx,
- ism330dhcx_start_config_t val);
+ ism330dhcx_start_config_t val);
int32_t ism330dhcx_sh_syncro_mode_get(stmdev_ctx_t *ctx,
- ism330dhcx_start_config_t *val);
+ ism330dhcx_start_config_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_EACH_SH_CYCLE = 0,
ISM330DHCX_ONLY_FIRST_CYCLE = 1,
} ism330dhcx_write_once_t;
int32_t ism330dhcx_sh_write_mode_set(stmdev_ctx_t *ctx,
- ism330dhcx_write_once_t val);
+ ism330dhcx_write_once_t val);
int32_t ism330dhcx_sh_write_mode_get(stmdev_ctx_t *ctx,
- ism330dhcx_write_once_t *val);
+ ism330dhcx_write_once_t *val);
int32_t ism330dhcx_sh_reset_set(stmdev_ctx_t *ctx);
int32_t ism330dhcx_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DHCX_SH_ODR_104Hz = 0,
ISM330DHCX_SH_ODR_52Hz = 1,
ISM330DHCX_SH_ODR_26Hz = 2,
ISM330DHCX_SH_ODR_13Hz = 3,
} ism330dhcx_shub_odr_t;
int32_t ism330dhcx_sh_data_rate_set(stmdev_ctx_t *ctx,
- ism330dhcx_shub_odr_t val);
+ ism330dhcx_shub_odr_t val);
int32_t ism330dhcx_sh_data_rate_get(stmdev_ctx_t *ctx,
- ism330dhcx_shub_odr_t *val);
+ ism330dhcx_shub_odr_t *val);
-typedef struct{
+typedef struct
+{
uint8_t slv0_add;
uint8_t slv0_subadd;
uint8_t slv0_data;
} ism330dhcx_sh_cfg_write_t;
int32_t ism330dhcx_sh_cfg_write(stmdev_ctx_t *ctx,
- ism330dhcx_sh_cfg_write_t *val);
+ ism330dhcx_sh_cfg_write_t *val);
-typedef struct{
+typedef struct
+{
uint8_t slv_add;
uint8_t slv_subadd;
uint8_t slv_len;
} ism330dhcx_sh_cfg_read_t;
int32_t ism330dhcx_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
- ism330dhcx_sh_cfg_read_t *val);
+ ism330dhcx_sh_cfg_read_t *val);
int32_t ism330dhcx_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
- ism330dhcx_sh_cfg_read_t *val);
+ ism330dhcx_sh_cfg_read_t *val);
int32_t ism330dhcx_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
- ism330dhcx_sh_cfg_read_t *val);
+ ism330dhcx_sh_cfg_read_t *val);
int32_t ism330dhcx_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
- ism330dhcx_sh_cfg_read_t *val);
+ ism330dhcx_sh_cfg_read_t *val);
int32_t ism330dhcx_sh_status_get(stmdev_ctx_t *ctx,
- ism330dhcx_status_master_t *val);
+ ism330dhcx_status_master_t *val);
/**
*@}
diff --git a/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.c b/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.c
index b5b31d6673ea133bbedbae5cd4a768bd41e0f941..7fa81752749da85eb525953ec16a45524aa70e92 100644
--- a/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.c
+++ b/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file ism330dlc_reg.c
- * @author Sensors Software Solution Team
- * @brief ISM330DLC driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file ism330dlc_reg.c
+ * @author Sensors Software Solution Team
+ * @brief ISM330DLC driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "ism330dlc_reg.h"
@@ -46,11 +46,13 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ism330dlc_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t ism330dlc_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +66,13 @@ int32_t ism330dlc_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t ism330dlc_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t ism330dlc_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -160,14 +164,16 @@ int32_t ism330dlc_xl_full_scale_set(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl1_xl_t ctrl1_xl;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
ctrl1_xl.fs_xl = (uint8_t) val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
+ (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -184,22 +190,27 @@ int32_t ism330dlc_xl_full_scale_get(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl1_xl_t ctrl1_xl;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
- switch (ctrl1_xl.fs_xl) {
+ (uint8_t *)&ctrl1_xl, 1);
+
+ switch (ctrl1_xl.fs_xl)
+ {
case ISM330DLC_2g:
*val = ISM330DLC_2g;
break;
+
case ISM330DLC_16g:
*val = ISM330DLC_16g;
break;
+
case ISM330DLC_4g:
*val = ISM330DLC_4g;
break;
+
case ISM330DLC_8g:
*val = ISM330DLC_8g;
break;
+
default:
*val = ISM330DLC_2g;
break;
@@ -221,13 +232,16 @@ int32_t ism330dlc_xl_data_rate_set(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl1_xl_t ctrl1_xl;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl1_xl.odr_xl = (uint8_t) val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
+ (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -244,45 +258,59 @@ int32_t ism330dlc_xl_data_rate_get(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl1_xl_t ctrl1_xl;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- switch (ctrl1_xl.odr_xl) {
+ switch (ctrl1_xl.odr_xl)
+ {
case ISM330DLC_XL_ODR_OFF:
*val = ISM330DLC_XL_ODR_OFF;
break;
+
case ISM330DLC_XL_ODR_12Hz5:
*val = ISM330DLC_XL_ODR_12Hz5;
break;
+
case ISM330DLC_XL_ODR_26Hz:
*val = ISM330DLC_XL_ODR_26Hz;
break;
+
case ISM330DLC_XL_ODR_52Hz:
*val = ISM330DLC_XL_ODR_52Hz;
break;
+
case ISM330DLC_XL_ODR_104Hz:
*val = ISM330DLC_XL_ODR_104Hz;
break;
+
case ISM330DLC_XL_ODR_208Hz:
*val = ISM330DLC_XL_ODR_208Hz;
break;
+
case ISM330DLC_XL_ODR_416Hz:
*val = ISM330DLC_XL_ODR_416Hz;
break;
+
case ISM330DLC_XL_ODR_833Hz:
*val = ISM330DLC_XL_ODR_833Hz;
break;
+
case ISM330DLC_XL_ODR_1k66Hz:
*val = ISM330DLC_XL_ODR_1k66Hz;
break;
+
case ISM330DLC_XL_ODR_3k33Hz:
*val = ISM330DLC_XL_ODR_3k33Hz;
break;
+
case ISM330DLC_XL_ODR_6k66Hz:
*val = ISM330DLC_XL_ODR_6k66Hz;
break;
+
case ISM330DLC_XL_ODR_1Hz6:
*val = ISM330DLC_XL_ODR_1Hz6;
break;
+
default:
*val = ISM330DLC_XL_ODR_OFF;
break;
@@ -304,12 +332,14 @@ int32_t ism330dlc_gy_full_scale_set(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl2_g_t ctrl2_g;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl2_g.fs_g = (uint8_t) val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
}
+
return ret;
}
@@ -326,24 +356,30 @@ int32_t ism330dlc_gy_full_scale_get(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl2_g_t ctrl2_g;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- switch (ctrl2_g.fs_g) {
+ switch (ctrl2_g.fs_g)
+ {
case ISM330DLC_250dps:
*val = ISM330DLC_250dps;
break;
+
case ISM330DLC_125dps:
*val = ISM330DLC_125dps;
break;
+
case ISM330DLC_500dps:
*val = ISM330DLC_500dps;
break;
+
case ISM330DLC_1000dps:
*val = ISM330DLC_1000dps;
break;
+
case ISM330DLC_2000dps:
*val = ISM330DLC_2000dps;
break;
+
default:
*val = ISM330DLC_250dps;
break;
@@ -365,12 +401,14 @@ int32_t ism330dlc_gy_data_rate_set(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl2_g_t ctrl2_g;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl2_g.odr_g = (uint8_t) val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
}
+
return ret;
}
@@ -387,42 +425,54 @@ int32_t ism330dlc_gy_data_rate_get(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl2_g_t ctrl2_g;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- switch (ctrl2_g.odr_g) {
+ switch (ctrl2_g.odr_g)
+ {
case ISM330DLC_GY_ODR_OFF:
*val = ISM330DLC_GY_ODR_OFF;
break;
+
case ISM330DLC_GY_ODR_12Hz5:
*val = ISM330DLC_GY_ODR_12Hz5;
break;
+
case ISM330DLC_GY_ODR_26Hz:
*val = ISM330DLC_GY_ODR_26Hz;
break;
+
case ISM330DLC_GY_ODR_52Hz:
*val = ISM330DLC_GY_ODR_52Hz;
break;
+
case ISM330DLC_GY_ODR_104Hz:
*val = ISM330DLC_GY_ODR_104Hz;
break;
+
case ISM330DLC_GY_ODR_208Hz:
*val = ISM330DLC_GY_ODR_208Hz;
break;
+
case ISM330DLC_GY_ODR_416Hz:
*val = ISM330DLC_GY_ODR_416Hz;
break;
+
case ISM330DLC_GY_ODR_833Hz:
*val = ISM330DLC_GY_ODR_833Hz;
break;
+
case ISM330DLC_GY_ODR_1k66Hz:
*val = ISM330DLC_GY_ODR_1k66Hz;
break;
+
case ISM330DLC_GY_ODR_3k33Hz:
*val = ISM330DLC_GY_ODR_3k33Hz;
break;
+
case ISM330DLC_GY_ODR_6k66Hz:
*val = ISM330DLC_GY_ODR_6k66Hz;
break;
+
default:
*val = ISM330DLC_GY_ODR_OFF;
break;
@@ -439,16 +489,19 @@ int32_t ism330dlc_gy_data_rate_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ism330dlc_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
ism330dlc_ctrl3_c_t ctrl3_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl3_c.bdu = val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -460,12 +513,12 @@ int32_t ism330dlc_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dlc_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dlc_ctrl3_c_t ctrl3_c;
int32_t ret;
-
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.bdu;
return ret;
@@ -485,12 +538,14 @@ int32_t ism330dlc_xl_offset_weight_set(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl6_c_t ctrl6_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl6_c.usr_off_w = (uint8_t) val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -508,15 +563,18 @@ int32_t ism330dlc_xl_offset_weight_get(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl6_c_t ctrl6_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- switch (ctrl6_c.usr_off_w) {
+ switch (ctrl6_c.usr_off_w)
+ {
case ISM330DLC_LSb_1mg:
*val = ISM330DLC_LSb_1mg;
break;
+
case ISM330DLC_LSb_16mg:
*val = ISM330DLC_LSb_16mg;
break;
+
default:
*val = ISM330DLC_LSb_1mg;
break;
@@ -538,12 +596,14 @@ int32_t ism330dlc_xl_power_mode_set(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl6_c_t ctrl6_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl6_c.xl_hm_mode = (uint8_t) val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -560,15 +620,18 @@ int32_t ism330dlc_xl_power_mode_get(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl6_c_t ctrl6_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- switch (ctrl6_c.xl_hm_mode) {
+ switch (ctrl6_c.xl_hm_mode)
+ {
case ISM330DLC_XL_HIGH_PERFORMANCE:
*val = ISM330DLC_XL_HIGH_PERFORMANCE;
break;
+
case ISM330DLC_XL_NORMAL:
*val = ISM330DLC_XL_NORMAL;
break;
+
default:
*val = ISM330DLC_XL_HIGH_PERFORMANCE;
break;
@@ -592,12 +655,14 @@ int32_t ism330dlc_rounding_on_status_set(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl7_g_t ctrl7_g;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl7_g.rounding_status = (uint8_t) val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
}
+
return ret;
}
@@ -616,15 +681,18 @@ int32_t ism330dlc_rounding_on_status_get(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl7_g_t ctrl7_g;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- switch (ctrl7_g.rounding_status) {
+ switch (ctrl7_g.rounding_status)
+ {
case ISM330DLC_STAT_RND_DISABLE:
*val = ISM330DLC_STAT_RND_DISABLE;
break;
+
case ISM330DLC_STAT_RND_ENABLE:
*val = ISM330DLC_STAT_RND_ENABLE;
break;
+
default:
*val = ISM330DLC_STAT_RND_DISABLE;
break;
@@ -646,12 +714,14 @@ int32_t ism330dlc_gy_power_mode_set(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl7_g_t ctrl7_g;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl7_g.g_hm_mode = (uint8_t) val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
}
+
return ret;
}
@@ -668,15 +738,18 @@ int32_t ism330dlc_gy_power_mode_get(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl7_g_t ctrl7_g;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- switch (ctrl7_g.g_hm_mode) {
+ switch (ctrl7_g.g_hm_mode)
+ {
case ISM330DLC_GY_HIGH_PERFORMANCE:
*val = ISM330DLC_GY_HIGH_PERFORMANCE;
break;
+
case ISM330DLC_GY_NORMAL:
*val = ISM330DLC_GY_NORMAL;
break;
+
default:
*val = ISM330DLC_GY_HIGH_PERFORMANCE;
break;
@@ -698,30 +771,41 @@ int32_t ism330dlc_all_sources_get(stmdev_ctx_t *ctx,
ism330dlc_all_sources_t *val)
{
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_SRC,
- (uint8_t*)&(val->wake_up_src), 1);
- if(ret == 0){
+ (uint8_t *) & (val->wake_up_src), 1);
+
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_SRC,
- (uint8_t*)&(val->tap_src), 1);
+ (uint8_t *) & (val->tap_src), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_D6D_SRC,
- (uint8_t*)&(val->d6d_src), 1);
+ (uint8_t *) & (val->d6d_src), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_STATUS_REG,
- (uint8_t*)&(val->status_reg), 1);
+ (uint8_t *) & (val->status_reg), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_FUNC_SRC1,
- (uint8_t*)&(val->func_src1), 1);
+ (uint8_t *) & (val->func_src1), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_FUNC_SRC2,
- (uint8_t*)&(val->func_src2), 1);
+ (uint8_t *) & (val->func_src2), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
}
@@ -739,7 +823,8 @@ int32_t ism330dlc_status_reg_get(stmdev_ctx_t *ctx,
ism330dlc_status_reg_t *val)
{
int32_t ret;
- ret = ism330dlc_read_reg(ctx, ISM330DLC_STATUS_REG, (uint8_t*) val, 1);
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_STATUS_REG, (uint8_t *) val, 1);
+
return ret;
}
@@ -751,13 +836,13 @@ int32_t ism330dlc_status_reg_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dlc_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dlc_status_reg_t status_reg;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_STATUS_REG,
- (uint8_t*)&status_reg, 1);
+ (uint8_t *)&status_reg, 1);
*val = status_reg.xlda;
return ret;
@@ -771,13 +856,13 @@ int32_t ism330dlc_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dlc_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dlc_status_reg_t status_reg;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_STATUS_REG,
- (uint8_t*)&status_reg, 1);
+ (uint8_t *)&status_reg, 1);
*val = status_reg.gda;
return ret;
@@ -791,13 +876,13 @@ int32_t ism330dlc_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dlc_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dlc_status_reg_t status_reg;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_STATUS_REG,
- (uint8_t*)&status_reg, 1);
+ (uint8_t *)&status_reg, 1);
*val = status_reg.tda;
return ret;
@@ -817,6 +902,7 @@ int32_t ism330dlc_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
ret = ism330dlc_write_reg(ctx, ISM330DLC_X_OFS_USR, buff, 3);
+
return ret;
}
@@ -834,6 +920,7 @@ int32_t ism330dlc_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
ret = ism330dlc_read_reg(ctx, ISM330DLC_X_OFS_USR, buff, 3);
+
return ret;
}
@@ -863,16 +950,21 @@ int32_t ism330dlc_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dlc_ctrl10_c_t ctrl10_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL10_C,
+ (uint8_t *)&ctrl10_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl10_c.timer_en = val;
- if ( val != 0x00U) {
+
+ if (val != 0x00U)
+ {
ctrl10_c.func_en = val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL10_C,
- (uint8_t*)&ctrl10_c, 1);
+ (uint8_t *)&ctrl10_c, 1);
}
}
+
return ret;
}
@@ -889,8 +981,8 @@ int32_t ism330dlc_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dlc_ctrl10_c_t ctrl10_c;
int32_t ret;
-
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL10_C,
+ (uint8_t *)&ctrl10_c, 1);
*val = ctrl10_c.timer_en;
return ret;
@@ -914,14 +1006,16 @@ int32_t ism330dlc_timestamp_res_set(stmdev_ctx_t *ctx,
{
ism330dlc_wake_up_dur_t wake_up_dur;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
wake_up_dur.timer_hr = (uint8_t) val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -943,16 +1037,19 @@ int32_t ism330dlc_timestamp_res_get(stmdev_ctx_t *ctx,
{
ism330dlc_wake_up_dur_t wake_up_dur;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- switch (wake_up_dur.timer_hr) {
+ (uint8_t *)&wake_up_dur, 1);
+
+ switch (wake_up_dur.timer_hr)
+ {
case ISM330DLC_LSB_6ms4:
*val = ISM330DLC_LSB_6ms4;
break;
+
case ISM330DLC_LSB_25us:
*val = ISM330DLC_LSB_25us;
break;
+
default:
*val = ISM330DLC_LSB_6ms4;
break;
@@ -987,12 +1084,14 @@ int32_t ism330dlc_rounding_mode_set(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl5_c_t ctrl5_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl5_c.rounding = (uint8_t) val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -1010,33 +1109,42 @@ int32_t ism330dlc_rounding_mode_get(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl5_c_t ctrl5_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- switch (ctrl5_c.rounding) {
+ switch (ctrl5_c.rounding)
+ {
case ISM330DLC_ROUND_DISABLE:
*val = ISM330DLC_ROUND_DISABLE;
break;
+
case ISM330DLC_ROUND_XL:
*val = ISM330DLC_ROUND_XL;
break;
+
case ISM330DLC_ROUND_GY:
*val = ISM330DLC_ROUND_GY;
break;
+
case ISM330DLC_ROUND_GY_XL:
*val = ISM330DLC_ROUND_GY_XL;
break;
+
case ISM330DLC_ROUND_SH1_TO_SH6:
*val = ISM330DLC_ROUND_SH1_TO_SH6;
break;
+
case ISM330DLC_ROUND_XL_SH1_TO_SH6:
*val = ISM330DLC_ROUND_XL_SH1_TO_SH6;
break;
+
case ISM330DLC_ROUND_GY_XL_SH1_TO_SH12:
*val = ISM330DLC_ROUND_GY_XL_SH1_TO_SH12;
break;
+
case ISM330DLC_ROUND_GY_XL_SH1_TO_SH6:
*val = ISM330DLC_ROUND_GY_XL_SH1_TO_SH6;
break;
+
default:
*val = ISM330DLC_ROUND_DISABLE;
break;
@@ -1058,10 +1166,9 @@ int32_t ism330dlc_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
uint8_t buff[2];
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_OUT_TEMP_L, buff, 2);
*val = (int16_t)buff[1];
- *val = (*val * 256) + (int16_t)buff[0];
+ *val = (*val * 256) + (int16_t)buff[0];
return ret;
}
@@ -1075,18 +1182,18 @@ int32_t ism330dlc_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
+int32_t ism330dlc_angular_rate_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
{
uint8_t buff[6];
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_OUTX_L_G, buff, 6);
val[0] = (int16_t)buff[1];
- val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
- val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
val[2] = (int16_t)buff[5];
- val[2] = (val[2] * 256) + (int16_t)buff[4];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
return ret;
}
@@ -1100,18 +1207,18 @@ int32_t ism330dlc_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
+int32_t ism330dlc_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
{
uint8_t buff[6];
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_OUTX_L_XL, buff, 6);
val[0] = (int16_t)buff[1];
- val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
- val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
val[2] = (int16_t)buff[5];
- val[2] = (val[2] * 256) + (int16_t)buff[4];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
return ret;
}
@@ -1124,18 +1231,18 @@ int32_t ism330dlc_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_mag_calibrated_raw_get(stmdev_ctx_t *ctx, int16_t *val)
+int32_t ism330dlc_mag_calibrated_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
{
uint8_t buff[6];
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_OUT_MAG_RAW_X_L, buff, 6);
val[0] = (int16_t)buff[1];
- val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
- val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
val[2] = (int16_t)buff[5];
- val[2] = (val[2] * 256) + (int16_t)buff[4];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
return ret;
}
@@ -1149,11 +1256,13 @@ int32_t ism330dlc_mag_calibrated_raw_get(stmdev_ctx_t *ctx, int16_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer,
+int32_t ism330dlc_fifo_raw_data_get(stmdev_ctx_t *ctx,
+ uint8_t *buffer,
uint8_t len)
{
int32_t ret;
ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_DATA_OUT_L, buffer, len);
+
return ret;
}
@@ -1164,7 +1273,7 @@ int32_t ism330dlc_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer,
/**
* @defgroup ISM330DLC_common
- * @brief This section groups common usefull functions.
+ * @brief This section groups common useful functions.
* @{
*
*/
@@ -1183,13 +1292,14 @@ int32_t ism330dlc_mem_bank_set(stmdev_ctx_t *ctx,
{
ism330dlc_func_cfg_access_t func_cfg_access;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
- if(ret == 0){
+ (uint8_t *)&func_cfg_access, 1);
+
+ if (ret == 0)
+ {
func_cfg_access.func_cfg_en = (uint8_t) val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
+ (uint8_t *)&func_cfg_access, 1);
}
return ret;
@@ -1209,13 +1319,15 @@ int32_t ism330dlc_mem_bank_get(stmdev_ctx_t *ctx,
{
ism330dlc_func_cfg_access_t func_cfg_access;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
- switch (func_cfg_access.func_cfg_en) {
+ (uint8_t *)&func_cfg_access, 1);
+
+ switch (func_cfg_access.func_cfg_en)
+ {
case ISM330DLC_USER_BANK:
*val = ISM330DLC_USER_BANK;
break;
+
default:
*val = ISM330DLC_USER_BANK;
break;
@@ -1237,14 +1349,16 @@ int32_t ism330dlc_data_ready_mode_set(stmdev_ctx_t *ctx,
{
ism330dlc_drdy_pulse_cfg_t drdy_pulse_cfg_g;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_DRDY_PULSE_CFG,
- (uint8_t*)&drdy_pulse_cfg_g, 1);
- if(ret == 0){
+ (uint8_t *)&drdy_pulse_cfg_g, 1);
+
+ if (ret == 0)
+ {
drdy_pulse_cfg_g.drdy_pulsed = (uint8_t) val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_DRDY_PULSE_CFG,
- (uint8_t*)&drdy_pulse_cfg_g, 1);
+ (uint8_t *)&drdy_pulse_cfg_g, 1);
}
+
return ret;
}
@@ -1261,16 +1375,19 @@ int32_t ism330dlc_data_ready_mode_get(stmdev_ctx_t *ctx,
{
ism330dlc_drdy_pulse_cfg_t drdy_pulse_cfg_g;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_DRDY_PULSE_CFG,
- (uint8_t*)&drdy_pulse_cfg_g, 1);
- switch (drdy_pulse_cfg_g.drdy_pulsed) {
+ (uint8_t *)&drdy_pulse_cfg_g, 1);
+
+ switch (drdy_pulse_cfg_g.drdy_pulsed)
+ {
case ISM330DLC_DRDY_LATCHED:
*val = ISM330DLC_DRDY_LATCHED;
break;
+
case ISM330DLC_DRDY_PULSED:
*val = ISM330DLC_DRDY_PULSED;
break;
+
default:
*val = ISM330DLC_DRDY_LATCHED;
break;
@@ -1291,6 +1408,7 @@ int32_t ism330dlc_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
ret = ism330dlc_read_reg(ctx, ISM330DLC_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -1306,12 +1424,14 @@ int32_t ism330dlc_reset_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dlc_ctrl3_c_t ctrl3_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl3_c.sw_reset = val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1327,8 +1447,7 @@ int32_t ism330dlc_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dlc_ctrl3_c_t ctrl3_c;
int32_t ret;
-
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.sw_reset;
return ret;
@@ -1342,16 +1461,19 @@ int32_t ism330dlc_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_data_format_set(stmdev_ctx_t *ctx, ism330dlc_ble_t val)
+int32_t ism330dlc_data_format_set(stmdev_ctx_t *ctx,
+ ism330dlc_ble_t val)
{
ism330dlc_ctrl3_c_t ctrl3_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl3_c.ble = (uint8_t) val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1363,19 +1485,23 @@ int32_t ism330dlc_data_format_set(stmdev_ctx_t *ctx, ism330dlc_ble_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_data_format_get(stmdev_ctx_t *ctx, ism330dlc_ble_t *val)
+int32_t ism330dlc_data_format_get(stmdev_ctx_t *ctx,
+ ism330dlc_ble_t *val)
{
ism330dlc_ctrl3_c_t ctrl3_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- switch (ctrl3_c.ble) {
+ switch (ctrl3_c.ble)
+ {
case ISM330DLC_LSB_AT_LOW_ADD:
*val = ISM330DLC_LSB_AT_LOW_ADD;
break;
+
case ISM330DLC_MSB_AT_LOW_ADD:
*val = ISM330DLC_MSB_AT_LOW_ADD;
break;
+
default:
*val = ISM330DLC_LSB_AT_LOW_ADD;
break;
@@ -1397,12 +1523,14 @@ int32_t ism330dlc_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dlc_ctrl3_c_t ctrl3_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl3_c.if_inc = val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1419,8 +1547,7 @@ int32_t ism330dlc_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dlc_ctrl3_c_t ctrl3_c;
int32_t ret;
-
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.if_inc;
return ret;
@@ -1438,12 +1565,14 @@ int32_t ism330dlc_boot_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dlc_ctrl3_c_t ctrl3_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl3_c.boot = val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1459,8 +1588,7 @@ int32_t ism330dlc_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dlc_ctrl3_c_t ctrl3_c;
int32_t ret;
-
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.boot;
return ret;
@@ -1474,16 +1602,19 @@ int32_t ism330dlc_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_xl_self_test_set(stmdev_ctx_t *ctx, ism330dlc_st_xl_t val)
+int32_t ism330dlc_xl_self_test_set(stmdev_ctx_t *ctx,
+ ism330dlc_st_xl_t val)
{
ism330dlc_ctrl5_c_t ctrl5_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl5_c.st_xl = (uint8_t) val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -1500,22 +1631,27 @@ int32_t ism330dlc_xl_self_test_get(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl5_c_t ctrl5_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- switch (ctrl5_c.st_xl) {
+ switch (ctrl5_c.st_xl)
+ {
case ISM330DLC_XL_ST_DISABLE:
*val = ISM330DLC_XL_ST_DISABLE;
break;
+
case ISM330DLC_XL_ST_POSITIVE:
*val = ISM330DLC_XL_ST_POSITIVE;
break;
+
case ISM330DLC_XL_ST_NEGATIVE:
*val = ISM330DLC_XL_ST_NEGATIVE;
break;
+
default:
*val = ISM330DLC_XL_ST_DISABLE;
break;
}
+
return ret;
}
@@ -1532,12 +1668,14 @@ int32_t ism330dlc_gy_self_test_set(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl5_c_t ctrl5_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl5_c.st_g = (uint8_t) val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -1554,18 +1692,22 @@ int32_t ism330dlc_gy_self_test_get(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl5_c_t ctrl5_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- switch (ctrl5_c.st_g) {
+ switch (ctrl5_c.st_g)
+ {
case ISM330DLC_GY_ST_DISABLE:
*val = ISM330DLC_GY_ST_DISABLE;
break;
+
case ISM330DLC_GY_ST_POSITIVE:
*val = ISM330DLC_GY_ST_POSITIVE;
break;
+
case ISM330DLC_GY_ST_NEGATIVE:
*val = ISM330DLC_GY_ST_NEGATIVE;
break;
+
default:
*val = ISM330DLC_GY_ST_DISABLE;
break;
@@ -1596,16 +1738,19 @@ int32_t ism330dlc_gy_self_test_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ism330dlc_filter_settling_mask_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
ism330dlc_ctrl4_c_t ctrl4_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl4_c.drdy_mask = val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -1618,12 +1763,12 @@ int32_t ism330dlc_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dlc_filter_settling_mask_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dlc_ctrl4_c_t ctrl4_c;
int32_t ret;
-
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.drdy_mask;
return ret;
@@ -1639,16 +1784,18 @@ int32_t ism330dlc_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t ism330dlc_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
- ism330dlc_slope_fds_t val)
+ ism330dlc_slope_fds_t val)
{
ism330dlc_tap_cfg_t tap_cfg;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
tap_cfg.slope_fds = (uint8_t) val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -1666,15 +1813,18 @@ int32_t ism330dlc_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
{
ism330dlc_tap_cfg_t tap_cfg;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- switch (tap_cfg.slope_fds) {
+ switch (tap_cfg.slope_fds)
+ {
case ISM330DLC_USE_SLOPE:
*val = ISM330DLC_USE_SLOPE;
break;
+
case ISM330DLC_USE_HPF:
*val = ISM330DLC_USE_HPF;
break;
+
default:
*val = ISM330DLC_USE_SLOPE;
break;
@@ -1710,12 +1860,16 @@ int32_t ism330dlc_xl_filter_analog_set(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl1_xl_t ctrl1_xl;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl1_xl.bw0_xl = (uint8_t) val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -1733,16 +1887,19 @@ int32_t ism330dlc_xl_filter_analog_get(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl1_xl_t ctrl1_xl;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
- switch (ctrl1_xl.bw0_xl) {
+ (uint8_t *)&ctrl1_xl, 1);
+
+ switch (ctrl1_xl.bw0_xl)
+ {
case ISM330DLC_XL_ANA_BW_1k5Hz:
*val = ISM330DLC_XL_ANA_BW_1k5Hz;
break;
+
case ISM330DLC_XL_ANA_BW_400Hz:
*val = ISM330DLC_XL_ANA_BW_400Hz;
break;
+
default:
*val = ISM330DLC_XL_ANA_BW_1k5Hz;
break;
@@ -1779,23 +1936,30 @@ int32_t ism330dlc_xl_lp1_bandwidth_set(stmdev_ctx_t *ctx,
ism330dlc_ctrl1_xl_t ctrl1_xl;
ism330dlc_ctrl8_xl_t ctrl8_xl;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl1_xl.lpf1_bw_sel = (uint8_t) val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL,
- (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
ctrl8_xl.lpf2_xl_en = 0;
ctrl8_xl.hp_slope_xl_en = 0;
ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL8_XL,
- (uint8_t*)&ctrl8_xl, 1);
+ (uint8_t *)&ctrl8_xl, 1);
}
}
}
+
return ret;
}
@@ -1814,29 +1978,39 @@ int32_t ism330dlc_xl_lp1_bandwidth_get(stmdev_ctx_t *ctx,
ism330dlc_ctrl1_xl_t ctrl1_xl;
ism330dlc_ctrl8_xl_t ctrl8_xl;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
if ((ctrl8_xl.lpf2_xl_en != 0x00U) ||
- (ctrl8_xl.hp_slope_xl_en != 0x00U)){
+ (ctrl8_xl.hp_slope_xl_en != 0x00U))
+ {
*val = ISM330DLC_XL_LP1_NA;
}
- else{
+
+ else
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
- switch ( ctrl1_xl.lpf1_bw_sel) {
+ (uint8_t *)&ctrl1_xl, 1);
+
+ switch (ctrl1_xl.lpf1_bw_sel)
+ {
case ISM330DLC_XL_LP1_ODR_DIV_2:
*val = ISM330DLC_XL_LP1_ODR_DIV_2;
break;
+
case ISM330DLC_XL_LP1_ODR_DIV_4:
*val = ISM330DLC_XL_LP1_ODR_DIV_4;
break;
+
default:
*val = ISM330DLC_XL_LP1_NA;
break;
}
}
}
+
return ret;
}
@@ -1853,16 +2027,19 @@ int32_t ism330dlc_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl8_xl_t ctrl8_xl;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
- ctrl8_xl.input_composite = ( (uint8_t) val & 0x10U ) >> 4;
+ if (ret == 0)
+ {
+ ctrl8_xl.input_composite = ((uint8_t) val & 0x10U) >> 4;
ctrl8_xl.hpcf_xl = (uint8_t) val & 0x03U;
ctrl8_xl.lpf2_xl_en = 1;
ctrl8_xl.hp_slope_xl_en = 0;
ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL8_XL,
- (uint8_t*)&ctrl8_xl, 1);
+ (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -1879,39 +2056,53 @@ int32_t ism330dlc_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl8_xl_t ctrl8_xl;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
if ((ctrl8_xl.lpf2_xl_en == 0x00U) ||
- (ctrl8_xl.hp_slope_xl_en != 0x00U)){
+ (ctrl8_xl.hp_slope_xl_en != 0x00U))
+ {
*val = ISM330DLC_XL_LP_NA;
}
- else{
- switch ((ctrl8_xl.input_composite << 4) + ctrl8_xl.hpcf_xl) {
+
+ else
+ {
+ switch ((ctrl8_xl.input_composite << 4) + ctrl8_xl.hpcf_xl)
+ {
case ISM330DLC_XL_LOW_LAT_LP_ODR_DIV_50:
*val = ISM330DLC_XL_LOW_LAT_LP_ODR_DIV_50;
break;
+
case ISM330DLC_XL_LOW_LAT_LP_ODR_DIV_100:
*val = ISM330DLC_XL_LOW_LAT_LP_ODR_DIV_100;
break;
+
case ISM330DLC_XL_LOW_LAT_LP_ODR_DIV_9:
*val = ISM330DLC_XL_LOW_LAT_LP_ODR_DIV_9;
break;
+
case ISM330DLC_XL_LOW_LAT_LP_ODR_DIV_400:
*val = ISM330DLC_XL_LOW_LAT_LP_ODR_DIV_400;
break;
+
case ISM330DLC_XL_LOW_NOISE_LP_ODR_DIV_50:
*val = ISM330DLC_XL_LOW_NOISE_LP_ODR_DIV_50;
break;
+
case ISM330DLC_XL_LOW_NOISE_LP_ODR_DIV_100:
*val = ISM330DLC_XL_LOW_NOISE_LP_ODR_DIV_100;
break;
+
case ISM330DLC_XL_LOW_NOISE_LP_ODR_DIV_9:
*val = ISM330DLC_XL_LOW_NOISE_LP_ODR_DIV_9;
break;
+
case ISM330DLC_XL_LOW_NOISE_LP_ODR_DIV_400:
*val = ISM330DLC_XL_LOW_NOISE_LP_ODR_DIV_400;
break;
+
default:
*val = ISM330DLC_XL_LP_NA;
break;
@@ -1930,16 +2121,21 @@ int32_t ism330dlc_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_xl_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ism330dlc_xl_reference_mode_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
ism330dlc_ctrl8_xl_t ctrl8_xl;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl8_xl.hp_ref_mode = val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -1951,12 +2147,13 @@ int32_t ism330dlc_xl_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_xl_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dlc_xl_reference_mode_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dlc_ctrl8_xl_t ctrl8_xl;
int32_t ret;
-
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
*val = ctrl8_xl.hp_ref_mode;
return ret;
@@ -1975,15 +2172,18 @@ int32_t ism330dlc_xl_hp_bandwidth_set(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl8_xl_t ctrl8_xl;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl8_xl.input_composite = 0;
ctrl8_xl.hpcf_xl = (uint8_t)val & 0x03U;
ctrl8_xl.hp_slope_xl_en = 1;
ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL8_XL,
- (uint8_t*)&ctrl8_xl, 1);
+ (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -2000,24 +2200,32 @@ int32_t ism330dlc_xl_hp_bandwidth_get(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl8_xl_t ctrl8_xl;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if (ctrl8_xl.hp_slope_xl_en == 0x00U){
+ if (ctrl8_xl.hp_slope_xl_en == 0x00U)
+ {
*val = ISM330DLC_XL_HP_NA;
}
- switch (ctrl8_xl.hpcf_xl) {
+
+ switch (ctrl8_xl.hpcf_xl)
+ {
case ISM330DLC_XL_HP_ODR_DIV_4:
*val = ISM330DLC_XL_HP_ODR_DIV_4;
break;
+
case ISM330DLC_XL_HP_ODR_DIV_100:
*val = ISM330DLC_XL_HP_ODR_DIV_100;
break;
+
case ISM330DLC_XL_HP_ODR_DIV_9:
*val = ISM330DLC_XL_HP_ODR_DIV_9;
break;
+
case ISM330DLC_XL_HP_ODR_DIV_400:
*val = ISM330DLC_XL_HP_ODR_DIV_400;
break;
+
default:
*val = ISM330DLC_XL_HP_NA;
break;
@@ -2055,23 +2263,29 @@ int32_t ism330dlc_xl_ui_lp1_bandwidth_set(stmdev_ctx_t *ctx,
ism330dlc_ctrl1_xl_t ctrl1_xl;
ism330dlc_ctrl8_xl_t ctrl8_xl;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
ctrl1_xl.lpf1_bw_sel = (uint8_t)val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
+ (uint8_t *)&ctrl1_xl, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL,
- (uint8_t*)&ctrl8_xl, 1);
+ (uint8_t *)&ctrl8_xl, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ctrl8_xl.hp_slope_xl_en = 0;
ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL8_XL,
- (uint8_t*)&ctrl8_xl, 1);
+ (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -2091,26 +2305,36 @@ int32_t ism330dlc_xl_ui_lp1_bandwidth_get(stmdev_ctx_t *ctx,
ism330dlc_ctrl1_xl_t ctrl1_xl;
ism330dlc_ctrl8_xl_t ctrl8_xl;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
- if (ctrl8_xl.hp_slope_xl_en == PROPERTY_DISABLE){
+ if (ret == 0)
+ {
+ if (ctrl8_xl.hp_slope_xl_en == PROPERTY_DISABLE)
+ {
*val = ISM330DLC_XL_UI_LP1_NA;
}
- else{
+
+ else
+ {
}
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
- switch (ctrl1_xl.lpf1_bw_sel ) {
- case ISM330DLC_XL_UI_LP1_ODR_DIV_2:
- *val = ISM330DLC_XL_UI_LP1_ODR_DIV_2;
- break;
- case ISM330DLC_XL_UI_LP1_ODR_DIV_4:
- *val = ISM330DLC_XL_UI_LP1_ODR_DIV_4;
- break;
- default:
- *val = ISM330DLC_XL_UI_LP1_NA;
- break;
+
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
+
+ switch (ctrl1_xl.lpf1_bw_sel)
+ {
+ case ISM330DLC_XL_UI_LP1_ODR_DIV_2:
+ *val = ISM330DLC_XL_UI_LP1_ODR_DIV_2;
+ break;
+
+ case ISM330DLC_XL_UI_LP1_ODR_DIV_4:
+ *val = ISM330DLC_XL_UI_LP1_ODR_DIV_4;
+ break;
+
+ default:
+ *val = ISM330DLC_XL_UI_LP1_NA;
+ break;
}
}
@@ -2129,12 +2353,14 @@ int32_t ism330dlc_xl_ui_slope_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dlc_ctrl8_xl_t reg;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL, (uint8_t *)®, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL, (uint8_t*)®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.hp_slope_xl_en = val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL8_XL, (uint8_t*)®, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL8_XL, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2150,8 +2376,7 @@ int32_t ism330dlc_xl_ui_slope_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dlc_ctrl8_xl_t reg;
int32_t ret;
-
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL, (uint8_t*)®, 1);
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL, (uint8_t *)®, 1);
*val = reg.hp_slope_xl_en;
return ret;
@@ -2183,12 +2408,14 @@ int32_t ism330dlc_xl_aux_lp_bandwidth_set(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl3_ois_t reg;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t*)®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.filter_xl_conf_ois = (uint8_t)val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t*)®, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2218,25 +2445,31 @@ int32_t ism330dlc_xl_aux_lp_bandwidth_get(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl3_ois_t reg;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t*)®, 1);
- switch ( reg.filter_xl_conf_ois ) {
+ switch (reg.filter_xl_conf_ois)
+ {
case ISM330DLC_AUX_LP_LIGHT:
*val = ISM330DLC_AUX_LP_LIGHT;
break;
+
case ISM330DLC_AUX_LP_NORMAL:
*val = ISM330DLC_AUX_LP_NORMAL;
break;
+
case ISM330DLC_AUX_LP_STRONG:
*val = ISM330DLC_AUX_LP_STRONG;
break;
+
case ISM330DLC_AUX_LP_AGGRESSIVE:
*val = ISM330DLC_AUX_LP_AGGRESSIVE;
break;
+
default:
*val = ISM330DLC_AUX_LP_LIGHT;
break;
}
+
return ret;
}
@@ -2269,30 +2502,40 @@ int32_t ism330dlc_gy_band_pass_set(stmdev_ctx_t *ctx,
ism330dlc_ctrl6_c_t ctrl6_c;
ism330dlc_ctrl7_g_t ctrl7_g;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
+ ctrl7_g.hpm_g = ((uint8_t)val & 0x30U) >> 4;
+ ctrl7_g.hp_en_g = ((uint8_t)val & 0x80U) >> 7;
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
- ctrl7_g.hpm_g = ( (uint8_t)val & 0x30U ) >> 4;
- ctrl7_g.hp_en_g = ( (uint8_t)val & 0x80U ) >> 7;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl6_c.ftype = (uint8_t)val & 0x03U;
ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL6_C,
- (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C,
- (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ctrl4_c.lpf1_sel_g = ( (uint8_t)val & 0x08U ) >> 3;
+ (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl4_c.lpf1_sel_g = ((uint8_t)val & 0x08U) >> 3;
ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL4_C,
- (uint8_t*)&ctrl4_c, 1);
+ (uint8_t *)&ctrl4_c, 1);
}
}
}
}
}
+
return ret;
}
@@ -2311,50 +2554,67 @@ int32_t ism330dlc_gy_band_pass_get(stmdev_ctx_t *ctx,
ism330dlc_ctrl6_c_t ctrl6_c;
ism330dlc_ctrl7_g_t ctrl7_g;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- switch ( ( ctrl7_g.hp_en_g << 7 ) + ( ctrl7_g.hpm_g << 4 ) +
- ( ctrl4_c.lpf1_sel_g << 3) + ctrl6_c.ftype ) {
+ if (ret == 0)
+ {
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ switch ((ctrl7_g.hp_en_g << 7) + (ctrl7_g.hpm_g << 4) +
+ (ctrl4_c.lpf1_sel_g << 3) + ctrl6_c.ftype)
+ {
case ISM330DLC_HP_16mHz_LP2:
*val = ISM330DLC_HP_16mHz_LP2;
break;
+
case ISM330DLC_HP_65mHz_LP2:
*val = ISM330DLC_HP_65mHz_LP2;
break;
+
case ISM330DLC_HP_260mHz_LP2:
*val = ISM330DLC_HP_260mHz_LP2;
break;
+
case ISM330DLC_HP_1Hz04_LP2:
*val = ISM330DLC_HP_1Hz04_LP2;
break;
+
case ISM330DLC_HP_DISABLE_LP1_LIGHT:
*val = ISM330DLC_HP_DISABLE_LP1_LIGHT;
break;
+
case ISM330DLC_HP_DISABLE_LP1_NORMAL:
*val = ISM330DLC_HP_DISABLE_LP1_NORMAL;
break;
+
case ISM330DLC_HP_DISABLE_LP_STRONG:
*val = ISM330DLC_HP_DISABLE_LP_STRONG;
break;
+
case ISM330DLC_HP_DISABLE_LP1_AGGRESSIVE:
*val = ISM330DLC_HP_DISABLE_LP1_AGGRESSIVE;
break;
+
case ISM330DLC_HP_16mHz_LP1_LIGHT:
*val = ISM330DLC_HP_16mHz_LP1_LIGHT;
break;
+
case ISM330DLC_HP_65mHz_LP1_NORMAL:
*val = ISM330DLC_HP_65mHz_LP1_NORMAL;
break;
+
case ISM330DLC_HP_260mHz_LP1_STRONG:
*val = ISM330DLC_HP_260mHz_LP1_STRONG;
break;
+
case ISM330DLC_HP_1Hz04_LP1_AGGRESSIVE:
*val = ISM330DLC_HP_1Hz04_LP1_AGGRESSIVE;
break;
+
default:
*val = ISM330DLC_HP_16mHz_LP2;
break;
@@ -2392,12 +2652,14 @@ int32_t ism330dlc_gy_ui_high_pass_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dlc_ctrl7_g_t reg;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)®, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t*)®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.hp_en_g = val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t*)®, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2414,9 +2676,7 @@ int32_t ism330dlc_gy_ui_high_pass_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dlc_ctrl7_g_t reg;
int32_t ret;
-
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t*)®, 1);
-
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)®, 1);
*val = reg.hp_en_g;
return ret;
@@ -2438,25 +2698,30 @@ int32_t ism330dlc_gy_aux_bandwidth_set(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl7_g_t ctrl7_g;
ism330dlc_ctrl2_ois_t ctrl2_ois;
-
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
- ctrl7_g.hp_en_g = 0;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ if (ret == 0)
+ {
+ ctrl7_g.hp_en_g = 0;
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL2_OIS,
- (uint8_t*)&ctrl2_ois, 1);
+ (uint8_t *)&ctrl2_ois, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ctrl2_ois.ftype_ois = (uint8_t)val & 0x03U;
- ctrl2_ois.hp_en_ois = ( (uint8_t)val & 0x80U ) >> 7;
- ctrl2_ois.hpm_ois = ( (uint8_t)val & 0x30U ) >> 4;
+ ctrl2_ois.hp_en_ois = ((uint8_t)val & 0x80U) >> 7;
+ ctrl2_ois.hpm_ois = ((uint8_t)val & 0x30U) >> 4;
ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL2_OIS,
- (uint8_t*)&ctrl2_ois, 1);
+ (uint8_t *)&ctrl2_ois, 1);
}
+
return ret;
}
@@ -2475,38 +2740,47 @@ int32_t ism330dlc_gy_aux_bandwidth_get(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl2_ois_t reg;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL2_OIS, (uint8_t *)®, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL2_OIS, (uint8_t*)®, 1);
-
- switch ( ( reg.hp_en_ois << 7 ) + ( reg.hpm_ois << 4) + reg.ftype_ois ) {
- case ISM330DLC_HP_DISABLE_LP_173Hz:
- *val = ISM330DLC_HP_DISABLE_LP_173Hz;
- break;
- case ISM330DLC_HP_DISABLE_LP_237Hz:
- *val = ISM330DLC_HP_DISABLE_LP_237Hz;
- break;
- case ISM330DLC_HP_DISABLE_LP_351Hz:
- *val = ISM330DLC_HP_DISABLE_LP_351Hz;
- break;
- case ISM330DLC_HP_DISABLE_LP_937Hz:
- *val = ISM330DLC_HP_DISABLE_LP_937Hz;
- break;
- case ISM330DLC_HP_16mHz_LP_173Hz:
- *val = ISM330DLC_HP_16mHz_LP_173Hz;
- break;
- case ISM330DLC_HP_65mHz_LP_237Hz:
- *val = ISM330DLC_HP_65mHz_LP_237Hz;
- break;
- case ISM330DLC_HP_260mHz_LP_351Hz:
- *val = ISM330DLC_HP_260mHz_LP_351Hz;
- break;
- case ISM330DLC_HP_1Hz04_LP_937Hz:
- *val = ISM330DLC_HP_1Hz04_LP_937Hz;
- break;
- default:
- *val = ISM330DLC_HP_DISABLE_LP_173Hz;
- break;
- }
+ switch ((reg.hp_en_ois << 7) + (reg.hpm_ois << 4) +
+ reg.ftype_ois)
+ {
+ case ISM330DLC_HP_DISABLE_LP_173Hz:
+ *val = ISM330DLC_HP_DISABLE_LP_173Hz;
+ break;
+
+ case ISM330DLC_HP_DISABLE_LP_237Hz:
+ *val = ISM330DLC_HP_DISABLE_LP_237Hz;
+ break;
+
+ case ISM330DLC_HP_DISABLE_LP_351Hz:
+ *val = ISM330DLC_HP_DISABLE_LP_351Hz;
+ break;
+
+ case ISM330DLC_HP_DISABLE_LP_937Hz:
+ *val = ISM330DLC_HP_DISABLE_LP_937Hz;
+ break;
+
+ case ISM330DLC_HP_16mHz_LP_173Hz:
+ *val = ISM330DLC_HP_16mHz_LP_173Hz;
+ break;
+
+ case ISM330DLC_HP_65mHz_LP_237Hz:
+ *val = ISM330DLC_HP_65mHz_LP_237Hz;
+ break;
+
+ case ISM330DLC_HP_260mHz_LP_351Hz:
+ *val = ISM330DLC_HP_260mHz_LP_351Hz;
+ break;
+
+ case ISM330DLC_HP_1Hz04_LP_937Hz:
+ *val = ISM330DLC_HP_1Hz04_LP_937Hz;
+ break;
+
+ default:
+ *val = ISM330DLC_HP_DISABLE_LP_173Hz;
+ break;
+ }
return ret;
}
@@ -2515,7 +2789,7 @@ int32_t ism330dlc_gy_aux_bandwidth_get(stmdev_ctx_t *ctx,
* @}
*
*/
-
+
/**
* @defgroup ISM330DLC_Auxiliary_interface
* @brief This section groups all the functions concerning
@@ -2536,7 +2810,9 @@ int32_t ism330dlc_aux_status_reg_get(stmdev_ctx_t *ctx,
ism330dlc_status_spiaux_t *val)
{
int32_t ret;
- ret = ism330dlc_read_reg(ctx, ISM330DLC_STATUS_SPIAUX, (uint8_t*) val, 1);
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_STATUS_SPIAUX,
+ (uint8_t *) val, 1);
+
return ret;
}
@@ -2553,8 +2829,8 @@ int32_t ism330dlc_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
{
ism330dlc_status_spiaux_t reg;
int32_t ret;
-
- ret = ism330dlc_read_reg(ctx, ISM330DLC_STATUS_SPIAUX, (uint8_t*)®, 1);
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_STATUS_SPIAUX,
+ (uint8_t *)®, 1);
*val = reg.xlda;
return ret;
@@ -2573,8 +2849,8 @@ int32_t ism330dlc_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
{
ism330dlc_status_spiaux_t reg;
int32_t ret;
-
- ret = ism330dlc_read_reg(ctx, ISM330DLC_STATUS_SPIAUX, (uint8_t*)®, 1);
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_STATUS_SPIAUX,
+ (uint8_t *)®, 1);
*val = reg.gda;
return ret;
@@ -2588,19 +2864,20 @@ int32_t ism330dlc_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dlc_aux_gy_flag_settling_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dlc_status_spiaux_t reg;
int32_t ret;
-
- ret = ism330dlc_read_reg(ctx, ISM330DLC_STATUS_SPIAUX, (uint8_t*)®, 1);
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_STATUS_SPIAUX,
+ (uint8_t *)®, 1);
*val = reg.gyro_settling;
return ret;
}
/**
- * @brief Configure DEN mode on the OIS chain.[set]
+ * @brief Configure DEN mode on the OIS chain.[set]
*
* @param ctx Read / write interface definitions
* @param val change the values of lvl2_ois in reg INT_OIS
@@ -2613,22 +2890,26 @@ int32_t ism330dlc_aux_den_mode_set(stmdev_ctx_t *ctx,
ism330dlc_ctrl1_ois_t ctrl1_ois;
ism330dlc_int_ois_t int_ois;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_OIS, (uint8_t *)&int_ois, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_OIS, (uint8_t*)&int_ois, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
int_ois.lvl2_ois = (uint8_t)val & 0x01U;
ret = ism330dlc_write_reg(ctx, ISM330DLC_INT_OIS,
- (uint8_t*)&int_ois, 1);
+ (uint8_t *)&int_ois, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
}
- if(ret == 0){
- ctrl1_ois.lvl1_ois = ((uint8_t)val & 0x02U) >> 1;
+ if (ret == 0)
+ {
+ ctrl1_ois.lvl1_ois = ((uint8_t)val & 0x02U) >> 1;
ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
}
return ret;
@@ -2648,31 +2929,38 @@ int32_t ism330dlc_aux_den_mode_get(stmdev_ctx_t *ctx,
ism330dlc_ctrl1_ois_t ctrl1_ois;
ism330dlc_int_ois_t int_ois;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_OIS, (uint8_t *)&int_ois, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_OIS, (uint8_t*)&int_ois, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
}
- switch ( (ctrl1_ois.lvl1_ois << 1) | int_ois.lvl2_ois) {
+
+ switch ((ctrl1_ois.lvl1_ois << 1) | int_ois.lvl2_ois)
+ {
case ISM330DLC_AUX_DEN_DISABLE:
*val = ISM330DLC_AUX_DEN_DISABLE;
break;
+
case ISM330DLC_AUX_DEN_LEVEL_LATCH:
*val = ISM330DLC_AUX_DEN_LEVEL_LATCH;
break;
+
case ISM330DLC_AUX_DEN_LEVEL_TRIG:
*val = ISM330DLC_AUX_DEN_LEVEL_TRIG;
break;
+
default:
*val = ISM330DLC_AUX_DEN_DISABLE;
break;
}
+
return ret;
}
/**
- * @brief Enables/Disable OIS chain DRDY on INT2 pin. This setting
+ * @brief Enables/Disable OIS chain DRDY on INT2 pin. This setting
* has priority over all other INT2 settings.[set]
*
* @param ctx Read / write interface definitions
@@ -2684,17 +2972,19 @@ int32_t ism330dlc_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dlc_int_ois_t reg;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_OIS, (uint8_t *)®, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_OIS, (uint8_t*)®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.int2_drdy_ois = val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_INT_OIS, (uint8_t*)®, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_INT_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
/**
- * @brief Enables/Disable OIS chain DRDY on INT2 pin. This setting
+ * @brief Enables/Disable OIS chain DRDY on INT2 pin. This setting
* has priority over all other INT2 settings.[get]
*
* @param ctx Read / write interface definitions
@@ -2702,12 +2992,12 @@ int32_t ism330dlc_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dlc_aux_drdy_on_int2_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dlc_int_ois_t reg;
int32_t ret;
-
- ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_OIS, (uint8_t*)®, 1);
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_OIS, (uint8_t *)®, 1);
*val = reg.int2_drdy_ois;
return ret;
@@ -2733,13 +3023,15 @@ int32_t ism330dlc_aux_mode_set(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl1_ois_t reg;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t *)®, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t*)®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.ois_en_spi2 = (uint8_t)val & 0x01U;
reg.mode4_en = ((uint8_t)val & 0x02U) >> 1;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t*)®, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2763,22 +3055,27 @@ int32_t ism330dlc_aux_mode_get(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl1_ois_t reg;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t *)®, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t*)®, 1);
- switch ( (reg.mode4_en << 1) + reg.ois_en_spi2 ) {
+ switch ((reg.mode4_en << 1) + reg.ois_en_spi2)
+ {
case ISM330DLC_AUX_DISABLE:
*val = ISM330DLC_AUX_DISABLE;
break;
+
case ISM330DLC_MODE_3_GY:
*val = ISM330DLC_MODE_3_GY;
break;
+
case ISM330DLC_MODE_4_GY_XL:
*val = ISM330DLC_MODE_4_GY_XL;
break;
+
default:
*val = ISM330DLC_AUX_DISABLE;
break;
}
+
return ret;
}
@@ -2795,12 +3092,14 @@ int32_t ism330dlc_aux_gy_full_scale_set(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl1_ois_t reg;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t *)®, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t*)®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.fs_g_ois = (uint8_t)val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t*)®, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2817,28 +3116,35 @@ int32_t ism330dlc_aux_gy_full_scale_get(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl1_ois_t reg;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t *)®, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t*)®, 1);
- switch ( reg.fs_g_ois ) {
+ switch (reg.fs_g_ois)
+ {
case ISM330DLC_250dps_AUX:
*val = ISM330DLC_250dps_AUX;
break;
+
case ISM330DLC_125dps_AUX:
*val = ISM330DLC_125dps_AUX;
break;
+
case ISM330DLC_500dps_AUX:
*val = ISM330DLC_500dps_AUX;
break;
+
case ISM330DLC_1000dps_AUX:
*val = ISM330DLC_1000dps_AUX;
break;
+
case ISM330DLC_2000dps_AUX:
*val = ISM330DLC_2000dps_AUX;
break;
+
default:
*val = ISM330DLC_250dps_AUX;
break;
}
+
return ret;
}
@@ -2855,12 +3161,14 @@ int32_t ism330dlc_aux_spi_mode_set(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl1_ois_t reg;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t *)®, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t*)®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.sim_ois = (uint8_t)val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t*)®, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2877,19 +3185,23 @@ int32_t ism330dlc_aux_spi_mode_get(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl1_ois_t reg;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t *)®, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t*)®, 1);
- switch ( reg.sim_ois ) {
+ switch (reg.sim_ois)
+ {
case ISM330DLC_AUX_SPI_4_WIRE:
*val = ISM330DLC_AUX_SPI_4_WIRE;
break;
+
case ISM330DLC_AUX_SPI_3_WIRE:
*val = ISM330DLC_AUX_SPI_3_WIRE;
break;
+
default:
*val = ISM330DLC_AUX_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -2906,12 +3218,14 @@ int32_t ism330dlc_aux_data_format_set(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl1_ois_t reg;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t *)®, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t*)®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.ble_ois = (uint8_t)val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t*)®, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2928,24 +3242,28 @@ int32_t ism330dlc_aux_data_format_get(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl1_ois_t reg;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t *)®, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t*)®, 1);
- switch ( reg.ble_ois ) {
+ switch (reg.ble_ois)
+ {
case ISM330DLC_AUX_LSB_AT_LOW_ADD:
*val = ISM330DLC_AUX_LSB_AT_LOW_ADD;
break;
+
case ISM330DLC_AUX_MSB_AT_LOW_ADD:
*val = ISM330DLC_AUX_MSB_AT_LOW_ADD;
break;
+
default:
*val = ISM330DLC_AUX_LSB_AT_LOW_ADD;
break;
}
+
return ret;
}
/**
- * @brief Enable / Disables OIS chain clamp. Enable: All OIS chain
+ * @brief Enable / Disables OIS chain clamp. Enable: All OIS chain
* outputs = 8000h during self-test; Disable: OIS chain
* self-test outputs dependent from the aux gyro full scale
* selected.[set]
@@ -2960,17 +3278,19 @@ int32_t ism330dlc_aux_gy_clamp_set(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl3_ois_t reg;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t*)®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.st_ois_clampdis = (uint8_t)val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t*)®, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
/**
- * @brief Enable / Disables OIS chain clamp. Enable: All OIS chain
+ * @brief Enable / Disables OIS chain clamp. Enable: All OIS chain
* outputs = 8000h during self-test; Disable: OIS chain
* self-test outputs dependent from the aux gyro full scale
* selected.[get]
@@ -2985,24 +3305,28 @@ int32_t ism330dlc_aux_gy_clamp_get(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl3_ois_t reg;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t*)®, 1);
- switch ( reg.st_ois_clampdis ) {
+ switch (reg.st_ois_clampdis)
+ {
case ISM330DLC_ENABLE_CLAMP:
*val = ISM330DLC_ENABLE_CLAMP;
break;
+
case ISM330DLC_DISABLE_CLAMP:
*val = ISM330DLC_DISABLE_CLAMP;
break;
+
default:
*val = ISM330DLC_ENABLE_CLAMP;
break;
}
+
return ret;
}
/**
- * @brief Selects gyroscope OIS chain self-test.[set]
+ * @brief Selects gyroscope OIS chain self-test.[set]
*
* @param ctx Read / write interface definitions
* @param val change the values of st_ois in reg CTRL3_OIS
@@ -3014,12 +3338,14 @@ int32_t ism330dlc_aux_gy_self_test_set(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl3_ois_t reg;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t*)®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.st_ois = (uint8_t)val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t*)®, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3036,22 +3362,27 @@ int32_t ism330dlc_aux_gy_self_test_get(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl3_ois_t reg;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t*)®, 1);
- switch ( reg.st_ois ) {
+ switch (reg.st_ois)
+ {
case ISM330DLC_AUX_GY_DISABLE:
*val = ISM330DLC_AUX_GY_DISABLE;
break;
+
case ISM330DLC_AUX_GY_POS:
*val = ISM330DLC_AUX_GY_POS;
break;
+
case ISM330DLC_AUX_GY_NEG:
*val = ISM330DLC_AUX_GY_NEG;
break;
+
default:
*val = ISM330DLC_AUX_GY_DISABLE;
break;
}
+
return ret;
}
@@ -3068,12 +3399,14 @@ int32_t ism330dlc_aux_xl_full_scale_set(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl3_ois_t reg;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t*)®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.fs_xl_ois = (uint8_t)val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t*)®, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3090,25 +3423,31 @@ int32_t ism330dlc_aux_xl_full_scale_get(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl3_ois_t reg;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t*)®, 1);
- switch ( reg.fs_xl_ois ) {
+ switch (reg.fs_xl_ois)
+ {
case ISM330DLC_AUX_2g:
*val = ISM330DLC_AUX_2g;
break;
+
case ISM330DLC_AUX_16g:
*val = ISM330DLC_AUX_16g;
break;
+
case ISM330DLC_AUX_4g:
*val = ISM330DLC_AUX_4g;
break;
+
case ISM330DLC_AUX_8g:
*val = ISM330DLC_AUX_8g;
break;
+
default:
*val = ISM330DLC_AUX_2g;
break;
}
+
return ret;
}
@@ -3125,12 +3464,14 @@ int32_t ism330dlc_aux_den_polarity_set(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl3_ois_t reg;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t*)®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.den_lh_ois = (uint8_t)val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t*)®, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3147,19 +3488,23 @@ int32_t ism330dlc_aux_den_polarity_get(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl3_ois_t reg;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t*)®, 1);
- switch ( reg.den_lh_ois ) {
+ switch (reg.den_lh_ois)
+ {
case ISM330DLC_AUX_DEN_ACTIVE_LOW:
*val = ISM330DLC_AUX_DEN_ACTIVE_LOW;
break;
+
case ISM330DLC_AUX_DEN_ACTIVE_HIGH:
*val = ISM330DLC_AUX_DEN_ACTIVE_HIGH;
break;
+
default:
*val = ISM330DLC_AUX_DEN_ACTIVE_LOW;
break;
}
+
return ret;
}
@@ -3167,7 +3512,7 @@ int32_t ism330dlc_aux_den_polarity_get(stmdev_ctx_t *ctx,
* @}
*
*/
-
+
/**
* @defgroup ISM330DLC_main_serial_interface
* @brief This section groups all the functions concerning serial
@@ -3188,12 +3533,14 @@ int32_t ism330dlc_spi_mode_set(stmdev_ctx_t *ctx, ism330dlc_sim_t val)
{
ism330dlc_ctrl3_c_t ctrl3_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl3_c.sim = (uint8_t) val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -3205,23 +3552,28 @@ int32_t ism330dlc_spi_mode_set(stmdev_ctx_t *ctx, ism330dlc_sim_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_spi_mode_get(stmdev_ctx_t *ctx, ism330dlc_sim_t *val)
+int32_t ism330dlc_spi_mode_get(stmdev_ctx_t *ctx,
+ ism330dlc_sim_t *val)
{
ism330dlc_ctrl3_c_t ctrl3_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- switch (ctrl3_c.sim) {
+ switch (ctrl3_c.sim)
+ {
case ISM330DLC_SPI_4_WIRE:
*val = ISM330DLC_SPI_4_WIRE;
break;
+
case ISM330DLC_SPI_3_WIRE:
*val = ISM330DLC_SPI_3_WIRE;
break;
+
default:
*val = ISM330DLC_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -3238,12 +3590,14 @@ int32_t ism330dlc_i2c_interface_set(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl4_c_t ctrl4_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl4_c.i2c_disable = (uint8_t)val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -3260,15 +3614,18 @@ int32_t ism330dlc_i2c_interface_get(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl4_c_t ctrl4_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- switch (ctrl4_c.i2c_disable) {
+ switch (ctrl4_c.i2c_disable)
+ {
case ISM330DLC_I2C_ENABLE:
*val = ISM330DLC_I2C_ENABLE;
break;
+
case ISM330DLC_I2C_DISABLE:
*val = ISM330DLC_I2C_DISABLE;
break;
+
default:
*val = ISM330DLC_I2C_ENABLE;
break;
@@ -3285,7 +3642,7 @@ int32_t ism330dlc_i2c_interface_get(stmdev_ctx_t *ctx,
/**
* @defgroup ISM330DLC_interrupt_pins
* @brief This section groups all the functions that manage
- * interrup pins
+ * interrupt pins
* @{
*
*/
@@ -3309,10 +3666,11 @@ int32_t ism330dlc_pin_int1_route_set(stmdev_ctx_t *ctx,
ism330dlc_ctrl4_c_t ctrl4_c;
ism330dlc_tap_cfg_t tap_cfg;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_INT1_CTRL,
- (uint8_t*)&int1_ctrl, 1);
- if(ret == 0){
+ (uint8_t *)&int1_ctrl, 1);
+
+ if (ret == 0)
+ {
int1_ctrl.int1_drdy_xl = val.int1_drdy_xl;
int1_ctrl.int1_drdy_g = val.int1_drdy_g;
int1_ctrl.int1_boot = val.int1_boot;
@@ -3320,64 +3678,87 @@ int32_t ism330dlc_pin_int1_route_set(stmdev_ctx_t *ctx,
int1_ctrl.int1_fifo_ovr = val.int1_fifo_ovr;
int1_ctrl.int1_full_flag = val.int1_full_flag;
ret = ism330dlc_write_reg(ctx, ISM330DLC_INT1_CTRL,
- (uint8_t*)&int1_ctrl, 1);
+ (uint8_t *)&int1_ctrl, 1);
}
- if(ret == 0){
- ret = ism330dlc_read_reg(ctx, ISM330DLC_MD1_CFG, (uint8_t*)&md1_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_MD1_CFG, (uint8_t *)&md1_cfg, 1);
}
- if(ret == 0){
- ret = ism330dlc_read_reg(ctx, ISM330DLC_MD2_CFG, (uint8_t*)&md2_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_MD2_CFG, (uint8_t *)&md2_cfg, 1);
}
- if(ret == 0){
- md1_cfg.int1_tilt = val.int1_tilt;
- md1_cfg.int1_6d = val.int1_6d;
- md1_cfg.int1_double_tap = val.int1_double_tap;
- md1_cfg.int1_ff = val.int1_ff;
- md1_cfg.int1_wu = val.int1_wu;
- md1_cfg.int1_single_tap = val.int1_single_tap;
- md1_cfg.int1_inact_state = val.int1_inact_state;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_MD1_CFG,
- (uint8_t*)&md1_cfg, 1);
+
+ if (ret == 0)
+ {
+ md1_cfg.int1_tilt = val.int1_tilt;
+ md1_cfg.int1_6d = val.int1_6d;
+ md1_cfg.int1_double_tap = val.int1_double_tap;
+ md1_cfg.int1_ff = val.int1_ff;
+ md1_cfg.int1_wu = val.int1_wu;
+ md1_cfg.int1_single_tap = val.int1_single_tap;
+ md1_cfg.int1_inact_state = val.int1_inact_state;
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_MD1_CFG,
+ (uint8_t *)&md1_cfg, 1);
}
- if(ret == 0){
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ctrl4_c.den_drdy_int1 = val.den_drdy_int1;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- master_config.drdy_on_int1 = val.den_drdy_int1;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+
+ if (ret == 0)
+ {
+ master_config.drdy_on_int1 = val.den_drdy_int1;
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_MASTER_CONFIG,
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
+
if ((val.int1_6d != 0x00U) ||
(val.int1_ff != 0x00U) ||
(val.int1_wu != 0x00U) ||
(val.int1_single_tap != 0x00U) ||
(val.int1_double_tap != 0x00U) ||
- (val.int1_inact_state != 0x00U)||
+ (val.int1_inact_state != 0x00U) ||
(md2_cfg.int2_6d != 0x00U) ||
(md2_cfg.int2_ff != 0x00U) ||
(md2_cfg.int2_wu != 0x00U) ||
(md2_cfg.int2_single_tap != 0x00U) ||
(md2_cfg.int2_double_tap != 0x00U) ||
- (md2_cfg.int2_inact_state!= 0x00U) ){
+ (md2_cfg.int2_inact_state != 0x00U))
+ {
tap_cfg.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
tap_cfg.interrupts_enable = PROPERTY_DISABLE;
}
}
- if(ret == 0){
- ret = ism330dlc_write_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -3397,20 +3778,22 @@ int32_t ism330dlc_pin_int1_route_get(stmdev_ctx_t *ctx,
ism330dlc_int1_ctrl_t int1_ctrl;
ism330dlc_md1_cfg_t md1_cfg;
ism330dlc_ctrl4_c_t ctrl4_c;
-
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_INT1_CTRL,
+ (uint8_t *)&int1_ctrl, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
val->int1_drdy_xl = int1_ctrl.int1_drdy_xl;
val->int1_drdy_g = int1_ctrl.int1_drdy_g;
val->int1_boot = int1_ctrl.int1_boot;
val->int1_fth = int1_ctrl.int1_fth;
val->int1_fifo_ovr = int1_ctrl.int1_fifo_ovr;
val->int1_full_flag = int1_ctrl.int1_full_flag;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_MD1_CFG, (uint8_t *)&md1_cfg, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_MD1_CFG, (uint8_t*)&md1_cfg, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
val->int1_tilt = md1_cfg.int1_tilt;
val->int1_6d = md1_cfg.int1_6d;
val->int1_double_tap = md1_cfg.int1_double_tap;
@@ -3418,16 +3801,18 @@ int32_t ism330dlc_pin_int1_route_get(stmdev_ctx_t *ctx,
val->int1_wu = md1_cfg.int1_wu;
val->int1_single_tap = md1_cfg.int1_single_tap;
val->int1_inact_state = md1_cfg.int1_inact_state;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
val->den_drdy_int1 = ctrl4_c.den_drdy_int1;
ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
val->den_drdy_int1 = master_config.drdy_on_int1;
}
}
}
+
return ret;
}
@@ -3448,11 +3833,11 @@ int32_t ism330dlc_pin_int2_route_set(stmdev_ctx_t *ctx,
ism330dlc_drdy_pulse_cfg_t drdy_pulse_cfg;
ism330dlc_tap_cfg_t tap_cfg;
int32_t ret;
-
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_INT2_CTRL,
- (uint8_t*)&int2_ctrl, 1);
- if(ret == 0){
+ (uint8_t *)&int2_ctrl, 1);
+
+ if (ret == 0)
+ {
int2_ctrl.int2_drdy_xl = val.int2_drdy_xl;
int2_ctrl.int2_drdy_g = val.int2_drdy_g;
int2_ctrl.int2_drdy_temp = val.int2_drdy_temp;
@@ -3460,17 +3845,23 @@ int32_t ism330dlc_pin_int2_route_set(stmdev_ctx_t *ctx,
int2_ctrl.int2_fifo_ovr = val.int2_fifo_ovr;
int2_ctrl.int2_full_flag = val.int2_full_flag;
ret = ism330dlc_write_reg(ctx, ISM330DLC_INT2_CTRL,
- (uint8_t*)&int2_ctrl, 1);
+ (uint8_t *)&int2_ctrl, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_MD1_CFG,
- (uint8_t*)&md1_cfg, 1);
+ (uint8_t *)&md1_cfg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_MD2_CFG,
- (uint8_t*)&md2_cfg, 1);
+ (uint8_t *)&md2_cfg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
md2_cfg.int2_iron = val.int2_iron;
md2_cfg.int2_tilt = val.int2_tilt;
md2_cfg.int2_6d = val.int2_6d;
@@ -3479,18 +3870,25 @@ int32_t ism330dlc_pin_int2_route_set(stmdev_ctx_t *ctx,
md2_cfg.int2_wu = val.int2_wu;
md2_cfg.int2_single_tap = val.int2_single_tap;
md2_cfg.int2_inact_state = val.int2_inact_state;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_MD2_CFG, (uint8_t*)&md2_cfg, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_MD2_CFG, (uint8_t *)&md2_cfg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_DRDY_PULSE_CFG,
- (uint8_t*)&drdy_pulse_cfg, 1);
+ (uint8_t *)&drdy_pulse_cfg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dlc_write_reg(ctx, ISM330DLC_DRDY_PULSE_CFG,
- (uint8_t*)&drdy_pulse_cfg, 1);
+ (uint8_t *)&drdy_pulse_cfg, 1);
}
- if(ret == 0){
- ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
+
if ((md1_cfg.int1_6d != 0x00U) ||
(md1_cfg.int1_ff != 0x00U) ||
(md1_cfg.int1_wu != 0x00U) ||
@@ -3502,16 +3900,22 @@ int32_t ism330dlc_pin_int2_route_set(stmdev_ctx_t *ctx,
(val.int2_wu != 0x00U) ||
(val.int2_single_tap != 0x00U) ||
(val.int2_double_tap != 0x00U) ||
- (val.int2_inact_state!= 0x00U) ){
+ (val.int2_inact_state != 0x00U))
+ {
tap_cfg.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
tap_cfg.interrupts_enable = PROPERTY_DISABLE;
}
}
- if(ret == 0){
- ret = ism330dlc_write_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -3528,20 +3932,22 @@ int32_t ism330dlc_pin_int2_route_get(stmdev_ctx_t *ctx,
{
ism330dlc_int2_ctrl_t int2_ctrl;
ism330dlc_md2_cfg_t md2_cfg;
-
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_INT2_CTRL,
+ (uint8_t *)&int2_ctrl, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
val->int2_drdy_xl = int2_ctrl.int2_drdy_xl;
val->int2_drdy_g = int2_ctrl.int2_drdy_g;
val->int2_drdy_temp = int2_ctrl.int2_drdy_temp;
val->int2_fth = int2_ctrl.int2_fth;
val->int2_fifo_ovr = int2_ctrl.int2_fifo_ovr;
val->int2_full_flag = int2_ctrl.int2_full_flag;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_MD2_CFG, (uint8_t *)&md2_cfg, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_MD2_CFG, (uint8_t*)&md2_cfg, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
val->int2_iron = md2_cfg.int2_iron;
val->int2_tilt = md2_cfg.int2_tilt;
val->int2_6d = md2_cfg.int2_6d;
@@ -3552,6 +3958,7 @@ int32_t ism330dlc_pin_int2_route_get(stmdev_ctx_t *ctx,
val->int2_inact_state = md2_cfg.int2_inact_state;
}
}
+
return ret;
}
@@ -3563,16 +3970,19 @@ int32_t ism330dlc_pin_int2_route_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_pin_mode_set(stmdev_ctx_t *ctx, ism330dlc_pp_od_t val)
+int32_t ism330dlc_pin_mode_set(stmdev_ctx_t *ctx,
+ ism330dlc_pp_od_t val)
{
ism330dlc_ctrl3_c_t ctrl3_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl3_c.pp_od = (uint8_t) val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -3584,19 +3994,23 @@ int32_t ism330dlc_pin_mode_set(stmdev_ctx_t *ctx, ism330dlc_pp_od_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_pin_mode_get(stmdev_ctx_t *ctx, ism330dlc_pp_od_t *val)
+int32_t ism330dlc_pin_mode_get(stmdev_ctx_t *ctx,
+ ism330dlc_pp_od_t *val)
{
ism330dlc_ctrl3_c_t ctrl3_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- switch (ctrl3_c.pp_od) {
+ switch (ctrl3_c.pp_od)
+ {
case ISM330DLC_PUSH_PULL:
*val = ISM330DLC_PUSH_PULL;
break;
+
case ISM330DLC_OPEN_DRAIN:
*val = ISM330DLC_OPEN_DRAIN;
break;
+
default:
*val = ISM330DLC_PUSH_PULL;
break;
@@ -3618,12 +4032,14 @@ int32_t ism330dlc_pin_polarity_set(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl3_c_t ctrl3_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl3_c.h_lactive = (uint8_t) val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -3640,15 +4056,18 @@ int32_t ism330dlc_pin_polarity_get(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl3_c_t ctrl3_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- switch (ctrl3_c.h_lactive) {
+ switch (ctrl3_c.h_lactive)
+ {
case ISM330DLC_ACTIVE_HIGH:
*val = ISM330DLC_ACTIVE_HIGH;
break;
+
case ISM330DLC_ACTIVE_LOW:
*val = ISM330DLC_ACTIVE_LOW;
break;
+
default:
*val = ISM330DLC_ACTIVE_HIGH;
break;
@@ -3669,12 +4088,14 @@ int32_t ism330dlc_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dlc_ctrl4_c_t ctrl4_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl4_c.int2_on_int1 = val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -3690,8 +4111,7 @@ int32_t ism330dlc_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dlc_ctrl4_c_t ctrl4_c;
int32_t ret;
-
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.int2_on_int1;
return ret;
@@ -3710,12 +4130,14 @@ int32_t ism330dlc_int_notification_set(stmdev_ctx_t *ctx,
{
ism330dlc_tap_cfg_t tap_cfg;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
tap_cfg.lir = (uint8_t) val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -3732,15 +4154,18 @@ int32_t ism330dlc_int_notification_get(stmdev_ctx_t *ctx,
{
ism330dlc_tap_cfg_t tap_cfg;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- switch (tap_cfg.lir) {
+ switch (tap_cfg.lir)
+ {
case ISM330DLC_INT_PULSED:
*val = ISM330DLC_INT_PULSED;
break;
+
case ISM330DLC_INT_LATCHED:
*val = ISM330DLC_INT_LATCHED;
break;
+
default:
*val = ISM330DLC_INT_PULSED;
break;
@@ -3774,14 +4199,16 @@ int32_t ism330dlc_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dlc_wake_up_ths_t wake_up_ths;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
- if(ret == 0){
+ (uint8_t *)&wake_up_ths, 1);
+
+ if (ret == 0)
+ {
wake_up_ths.wk_ths = val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
}
+
return ret;
}
@@ -3797,9 +4224,8 @@ int32_t ism330dlc_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dlc_wake_up_ths_t wake_up_ths;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
*val = wake_up_ths.wk_ths;
return ret;
@@ -3817,14 +4243,16 @@ int32_t ism330dlc_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dlc_wake_up_dur_t wake_up_dur;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
wake_up_dur.wake_dur = val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -3840,9 +4268,8 @@ int32_t ism330dlc_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dlc_wake_up_dur_t wake_up_dur;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
*val = wake_up_dur.wake_dur;
return ret;
@@ -3873,12 +4300,14 @@ int32_t ism330dlc_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dlc_ctrl4_c_t ctrl4_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl4_c.sleep = val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -3894,8 +4323,7 @@ int32_t ism330dlc_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dlc_ctrl4_c_t ctrl4_c;
int32_t ret;
-
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.sleep;
return ret;
@@ -3909,16 +4337,19 @@ int32_t ism330dlc_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_act_mode_set(stmdev_ctx_t *ctx, ism330dlc_inact_en_t val)
+int32_t ism330dlc_act_mode_set(stmdev_ctx_t *ctx,
+ ism330dlc_inact_en_t val)
{
ism330dlc_tap_cfg_t tap_cfg;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
tap_cfg.inact_en = (uint8_t) val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -3935,21 +4366,26 @@ int32_t ism330dlc_act_mode_get(stmdev_ctx_t *ctx,
{
ism330dlc_tap_cfg_t tap_cfg;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- switch (tap_cfg.inact_en) {
+ switch (tap_cfg.inact_en)
+ {
case ISM330DLC_PROPERTY_DISABLE:
*val = ISM330DLC_PROPERTY_DISABLE;
break;
+
case ISM330DLC_XL_12Hz5_GY_NOT_AFFECTED:
*val = ISM330DLC_XL_12Hz5_GY_NOT_AFFECTED;
break;
+
case ISM330DLC_XL_12Hz5_GY_SLEEP:
*val = ISM330DLC_XL_12Hz5_GY_SLEEP;
break;
+
case ISM330DLC_XL_12Hz5_GY_PD:
*val = ISM330DLC_XL_12Hz5_GY_PD;
break;
+
default:
*val = ISM330DLC_PROPERTY_DISABLE;
break;
@@ -3970,14 +4406,16 @@ int32_t ism330dlc_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dlc_wake_up_dur_t wake_up_dur;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
wake_up_dur.sleep_dur = val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -3993,9 +4431,8 @@ int32_t ism330dlc_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dlc_wake_up_dur_t wake_up_dur;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
*val = wake_up_dur.sleep_dur;
return ret;
@@ -4022,10 +4459,12 @@ int32_t ism330dlc_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_tap_src_get(stmdev_ctx_t *ctx, ism330dlc_tap_src_t *val)
+int32_t ism330dlc_tap_src_get(stmdev_ctx_t *ctx,
+ ism330dlc_tap_src_t *val)
{
int32_t ret;
- ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_SRC, (uint8_t*) val, 1);
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_SRC, (uint8_t *) val, 1);
+
return ret;
}
@@ -4036,16 +4475,19 @@ int32_t ism330dlc_tap_src_get(stmdev_ctx_t *ctx, ism330dlc_tap_src_t *val)
* @param val Change the values of tap_z_en in reg TAP_CFG
*
*/
-int32_t ism330dlc_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ism330dlc_tap_detection_on_z_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
ism330dlc_tap_cfg_t tap_cfg;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
tap_cfg.tap_z_en = val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -4057,12 +4499,12 @@ int32_t ism330dlc_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dlc_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dlc_tap_cfg_t tap_cfg;
int32_t ret;
-
- ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
*val = tap_cfg.tap_z_en;
return ret;
@@ -4076,16 +4518,19 @@ int32_t ism330dlc_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ism330dlc_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
ism330dlc_tap_cfg_t tap_cfg;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
tap_cfg.tap_y_en = val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -4097,12 +4542,12 @@ int32_t ism330dlc_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dlc_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dlc_tap_cfg_t tap_cfg;
int32_t ret;
-
- ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
*val = tap_cfg.tap_y_en;
return ret;
@@ -4116,16 +4561,19 @@ int32_t ism330dlc_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ism330dlc_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
ism330dlc_tap_cfg_t tap_cfg;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
tap_cfg.tap_x_en = val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -4137,12 +4585,12 @@ int32_t ism330dlc_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dlc_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dlc_tap_cfg_t tap_cfg;
int32_t ret;
-
- ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
*val = tap_cfg.tap_x_en;
return ret;
@@ -4160,14 +4608,16 @@ int32_t ism330dlc_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dlc_tap_ths_6d_t tap_ths_6d;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
- if(ret == 0){
+ (uint8_t *)&tap_ths_6d, 1);
+
+ if (ret == 0)
+ {
tap_ths_6d.tap_ths = val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
+ (uint8_t *)&tap_ths_6d, 1);
}
+
return ret;
}
@@ -4183,9 +4633,8 @@ int32_t ism330dlc_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dlc_tap_ths_6d_t tap_ths_6d;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
+ (uint8_t *)&tap_ths_6d, 1);
*val = tap_ths_6d.tap_ths;
return ret;
@@ -4208,13 +4657,16 @@ int32_t ism330dlc_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dlc_int_dur2_t int_dur2;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_DUR2,
+ (uint8_t *)&int_dur2, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_DUR2, (uint8_t*)&int_dur2, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
int_dur2.shock = val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_INT_DUR2,
- (uint8_t*)&int_dur2, 1);
+ (uint8_t *)&int_dur2, 1);
}
+
return ret;
}
@@ -4235,8 +4687,8 @@ int32_t ism330dlc_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dlc_int_dur2_t int_dur2;
int32_t ret;
-
- ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_DUR2,
+ (uint8_t *)&int_dur2, 1);
*val = int_dur2.shock;
return ret;
@@ -4259,12 +4711,16 @@ int32_t ism330dlc_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dlc_int_dur2_t int_dur2;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_DUR2,
+ (uint8_t *)&int_dur2, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_DUR2, (uint8_t*)&int_dur2, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
int_dur2.quiet = val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_INT_DUR2,
+ (uint8_t *)&int_dur2, 1);
}
+
return ret;
}
@@ -4285,8 +4741,8 @@ int32_t ism330dlc_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dlc_int_dur2_t int_dur2;
int32_t ret;
-
- ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_DUR2,
+ (uint8_t *)&int_dur2, 1);
*val = int_dur2.quiet;
return ret;
@@ -4310,12 +4766,16 @@ int32_t ism330dlc_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dlc_int_dur2_t int_dur2;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_DUR2,
+ (uint8_t *)&int_dur2, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_DUR2, (uint8_t*)&int_dur2, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
int_dur2.dur = val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_INT_DUR2,
+ (uint8_t *)&int_dur2, 1);
}
+
return ret;
}
@@ -4337,8 +4797,8 @@ int32_t ism330dlc_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dlc_int_dur2_t int_dur2;
int32_t ret;
-
- ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_DUR2,
+ (uint8_t *)&int_dur2, 1);
*val = int_dur2.dur;
return ret;
@@ -4353,18 +4813,20 @@ int32_t ism330dlc_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t ism330dlc_tap_mode_set(stmdev_ctx_t *ctx,
- ism330dlc_single_double_tap_t val)
+ ism330dlc_single_double_tap_t val)
{
ism330dlc_wake_up_ths_t wake_up_ths;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
- if(ret == 0){
+ (uint8_t *)&wake_up_ths, 1);
+
+ if (ret == 0)
+ {
wake_up_ths.single_double_tap = (uint8_t) val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
}
+
return ret;
}
@@ -4381,16 +4843,19 @@ int32_t ism330dlc_tap_mode_get(stmdev_ctx_t *ctx,
{
ism330dlc_wake_up_ths_t wake_up_ths;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_THS,
+ (uint8_t *)&wake_up_ths, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
- switch (wake_up_ths.single_double_tap) {
+ switch (wake_up_ths.single_double_tap)
+ {
case ISM330DLC_ONLY_SINGLE:
*val = ISM330DLC_ONLY_SINGLE;
break;
+
case ISM330DLC_BOTH_SINGLE_DOUBLE:
*val = ISM330DLC_BOTH_SINGLE_DOUBLE;
break;
+
default:
*val = ISM330DLC_ONLY_SINGLE;
break;
@@ -4425,13 +4890,16 @@ int32_t ism330dlc_6d_feed_data_set(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl8_xl_t ctrl8_xl;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl8_xl.low_pass_on_6d = (uint8_t) val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL8_XL,
- (uint8_t*)&ctrl8_xl, 1);
+ (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -4448,15 +4916,19 @@ int32_t ism330dlc_6d_feed_data_get(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl8_xl_t ctrl8_xl;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- switch (ctrl8_xl.low_pass_on_6d) {
+ switch (ctrl8_xl.low_pass_on_6d)
+ {
case ISM330DLC_ODR_DIV_2_FEED:
*val = ISM330DLC_ODR_DIV_2_FEED;
break;
+
case ISM330DLC_LPF2_FEED:
*val = ISM330DLC_LPF2_FEED;
break;
+
default:
*val = ISM330DLC_ODR_DIV_2_FEED;
break;
@@ -4478,14 +4950,16 @@ int32_t ism330dlc_6d_threshold_set(stmdev_ctx_t *ctx,
{
ism330dlc_tap_ths_6d_t tap_ths_6d;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
- if(ret == 0){
+ (uint8_t *)&tap_ths_6d, 1);
+
+ if (ret == 0)
+ {
tap_ths_6d.sixd_ths = (uint8_t) val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
+ (uint8_t *)&tap_ths_6d, 1);
}
+
return ret;
}
@@ -4502,22 +4976,27 @@ int32_t ism330dlc_6d_threshold_get(stmdev_ctx_t *ctx,
{
ism330dlc_tap_ths_6d_t tap_ths_6d;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
- switch (tap_ths_6d.sixd_ths) {
+ (uint8_t *)&tap_ths_6d, 1);
+
+ switch (tap_ths_6d.sixd_ths)
+ {
case ISM330DLC_DEG_80:
*val = ISM330DLC_DEG_80;
break;
+
case ISM330DLC_DEG_70:
*val = ISM330DLC_DEG_70;
break;
+
case ISM330DLC_DEG_60:
*val = ISM330DLC_DEG_60;
break;
+
case ISM330DLC_DEG_50:
*val = ISM330DLC_DEG_50;
break;
+
default:
*val = ISM330DLC_DEG_80;
break;
@@ -4538,14 +5017,16 @@ int32_t ism330dlc_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dlc_tap_ths_6d_t tap_ths_6d;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
- if(ret == 0){
+ (uint8_t *)&tap_ths_6d, 1);
+
+ if (ret == 0)
+ {
tap_ths_6d.d4d_en = val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
+ (uint8_t *)&tap_ths_6d, 1);
}
+
return ret;
}
@@ -4561,9 +5042,8 @@ int32_t ism330dlc_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dlc_tap_ths_6d_t tap_ths_6d;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
+ (uint8_t *)&tap_ths_6d, 1);
*val = tap_ths_6d.d4d_en;
return ret;
@@ -4595,22 +5075,29 @@ int32_t ism330dlc_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
ism330dlc_wake_up_dur_t wake_up_dur;
ism330dlc_free_fall_t free_fall;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_FREE_FALL,
+ (uint8_t *)&free_fall, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_FREE_FALL, (uint8_t*)&free_fall, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
free_fall.ff_dur = (val & 0x1FU);
ret = ism330dlc_write_reg(ctx, ISM330DLC_FREE_FALL,
- (uint8_t*)&free_fall, 1);
- if(ret == 0){
+ (uint8_t *)&free_fall, 1);
+
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
wake_up_dur.ff_dur = (val & 0x20U) >> 5;
ret = ism330dlc_write_reg(ctx, ISM330DLC_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
}
}
+
return ret;
}
@@ -4627,13 +5114,15 @@ int32_t ism330dlc_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
ism330dlc_wake_up_dur_t wake_up_dur;
ism330dlc_free_fall_t free_fall;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_FREE_FALL,
- (uint8_t*)&free_fall, 1);
+ (uint8_t *)&free_fall, 1);
}
+
*val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
return ret;
@@ -4652,13 +5141,16 @@ int32_t ism330dlc_ff_threshold_set(stmdev_ctx_t *ctx,
{
ism330dlc_free_fall_t free_fall;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_FREE_FALL,
+ (uint8_t *)&free_fall, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_FREE_FALL, (uint8_t*)&free_fall, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
free_fall.ff_ths = (uint8_t) val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_FREE_FALL,
- (uint8_t*)&free_fall, 1);
+ (uint8_t *)&free_fall, 1);
}
+
return ret;
}
@@ -4675,33 +5167,43 @@ int32_t ism330dlc_ff_threshold_get(stmdev_ctx_t *ctx,
{
ism330dlc_free_fall_t free_fall;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_FREE_FALL,
+ (uint8_t *)&free_fall, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_FREE_FALL, (uint8_t*)&free_fall, 1);
- switch (free_fall.ff_ths) {
+ switch (free_fall.ff_ths)
+ {
case ISM330DLC_FF_TSH_156mg:
*val = ISM330DLC_FF_TSH_156mg;
break;
+
case ISM330DLC_FF_TSH_219mg:
*val = ISM330DLC_FF_TSH_219mg;
break;
+
case ISM330DLC_FF_TSH_250mg:
*val = ISM330DLC_FF_TSH_250mg;
break;
+
case ISM330DLC_FF_TSH_312mg:
*val = ISM330DLC_FF_TSH_312mg;
break;
+
case ISM330DLC_FF_TSH_344mg:
*val = ISM330DLC_FF_TSH_344mg;
break;
+
case ISM330DLC_FF_TSH_406mg:
*val = ISM330DLC_FF_TSH_406mg;
break;
+
case ISM330DLC_FF_TSH_469mg:
*val = ISM330DLC_FF_TSH_469mg;
break;
+
case ISM330DLC_FF_TSH_500mg:
*val = ISM330DLC_FF_TSH_500mg;
break;
+
default:
*val = ISM330DLC_FF_TSH_156mg;
break;
@@ -4736,19 +5238,23 @@ int32_t ism330dlc_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
ism330dlc_fifo_ctrl1_t fifo_ctrl1;
ism330dlc_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
- fifo_ctrl2.fth = (uint8_t) (uint8_t) (val / 256U);
- fifo_ctrl1.fth = (uint8_t) (uint8_t) (val - (fifo_ctrl2.fth * 256U));
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl2.fth = (uint8_t)(uint8_t)(val / 256U);
+ fifo_ctrl1.fth = (uint8_t)(uint8_t)(val - (fifo_ctrl2.fth * 256U));
ret = ism330dlc_write_reg(ctx, ISM330DLC_FIFO_CTRL1,
- (uint8_t*)&fifo_ctrl1, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl1, 1);
+
+ if (ret == 0)
+ {
ret = ism330dlc_write_reg(ctx, ISM330DLC_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
}
+
return ret;
}
@@ -4765,13 +5271,15 @@ int32_t ism330dlc_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
ism330dlc_fifo_ctrl1_t fifo_ctrl1;
ism330dlc_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL1,
- (uint8_t*)&fifo_ctrl1, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl1, 1);
+
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
+
*val = fifo_ctrl2.fth;
*val = (*val * 256U) + fifo_ctrl1.fth;
@@ -4788,19 +5296,21 @@ int32_t ism330dlc_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
+int32_t ism330dlc_fifo_data_level_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
ism330dlc_fifo_status1_t fifo_status1;
ism330dlc_fifo_status2_t fifo_status2;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_STATUS1,
- (uint8_t*)&fifo_status1, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_status1, 1);
+
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
- *val = fifo_status2.diff_fifo;
- *val = (*val * 256U) + fifo_status1.diff_fifo;
+ (uint8_t *)&fifo_status2, 1);
+ *val = fifo_status2.diff_fifo;
+ *val = (*val * 256U) + fifo_status1.diff_fifo;
}
return ret;
@@ -4818,9 +5328,8 @@ int32_t ism330dlc_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dlc_fifo_status2_t fifo_status2;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
+ (uint8_t *)&fifo_status2, 1);
*val = fifo_status2.waterm;
return ret;
@@ -4840,15 +5349,17 @@ int32_t ism330dlc_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val)
ism330dlc_fifo_status3_t fifo_status3;
ism330dlc_fifo_status4_t fifo_status4;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_STATUS3,
- (uint8_t*)&fifo_status3, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_status3, 1);
+
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_STATUS4,
- (uint8_t*)&fifo_status4, 1);
+ (uint8_t *)&fifo_status4, 1);
*val = fifo_status4.fifo_pattern;
*val = (*val * 256U) + fifo_status3.fifo_pattern;
}
+
return ret;
}
@@ -4864,13 +5375,14 @@ int32_t ism330dlc_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dlc_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl2.fifo_temp_en = val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
return ret;
@@ -4888,9 +5400,8 @@ int32_t ism330dlc_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dlc_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
*val = fifo_ctrl2.fifo_temp_en;
return ret;
@@ -4910,14 +5421,16 @@ int32_t ism330dlc_fifo_write_trigger_set(stmdev_ctx_t *ctx,
{
ism330dlc_master_config_t master_config;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
master_config.data_valid_sel_fifo = (((uint8_t)val & 0x02U) >> 1);
ret = ism330dlc_write_reg(ctx, ISM330DLC_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
+
return ret;
}
@@ -4935,14 +5448,16 @@ int32_t ism330dlc_fifo_xl_batch_set(stmdev_ctx_t *ctx,
{
ism330dlc_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl3, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl3.dec_fifo_xl = (uint8_t)val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
+ (uint8_t *)&fifo_ctrl3, 1);
}
+
return ret;
}
@@ -4960,34 +5475,43 @@ int32_t ism330dlc_fifo_xl_batch_get(stmdev_ctx_t *ctx,
{
ism330dlc_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
- switch (fifo_ctrl3.dec_fifo_xl) {
+ (uint8_t *)&fifo_ctrl3, 1);
+
+ switch (fifo_ctrl3.dec_fifo_xl)
+ {
case ISM330DLC_FIFO_XL_DISABLE:
*val = ISM330DLC_FIFO_XL_DISABLE;
break;
+
case ISM330DLC_FIFO_XL_NO_DEC:
*val = ISM330DLC_FIFO_XL_NO_DEC;
break;
+
case ISM330DLC_FIFO_XL_DEC_2:
*val = ISM330DLC_FIFO_XL_DEC_2;
break;
+
case ISM330DLC_FIFO_XL_DEC_3:
*val = ISM330DLC_FIFO_XL_DEC_3;
break;
+
case ISM330DLC_FIFO_XL_DEC_4:
*val = ISM330DLC_FIFO_XL_DEC_4;
break;
+
case ISM330DLC_FIFO_XL_DEC_8:
*val = ISM330DLC_FIFO_XL_DEC_8;
break;
+
case ISM330DLC_FIFO_XL_DEC_16:
*val = ISM330DLC_FIFO_XL_DEC_16;
break;
+
case ISM330DLC_FIFO_XL_DEC_32:
*val = ISM330DLC_FIFO_XL_DEC_32;
break;
+
default:
*val = ISM330DLC_FIFO_XL_DISABLE;
break;
@@ -5010,14 +5534,16 @@ int32_t ism330dlc_fifo_gy_batch_set(stmdev_ctx_t *ctx,
{
ism330dlc_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl3, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl3.dec_fifo_gyro = (uint8_t)val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
+ (uint8_t *)&fifo_ctrl3, 1);
}
+
return ret;
}
@@ -5035,34 +5561,43 @@ int32_t ism330dlc_fifo_gy_batch_get(stmdev_ctx_t *ctx,
{
ism330dlc_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
- switch (fifo_ctrl3.dec_fifo_gyro) {
+ (uint8_t *)&fifo_ctrl3, 1);
+
+ switch (fifo_ctrl3.dec_fifo_gyro)
+ {
case ISM330DLC_FIFO_GY_DISABLE:
*val = ISM330DLC_FIFO_GY_DISABLE;
break;
+
case ISM330DLC_FIFO_GY_NO_DEC:
*val = ISM330DLC_FIFO_GY_NO_DEC;
break;
+
case ISM330DLC_FIFO_GY_DEC_2:
*val = ISM330DLC_FIFO_GY_DEC_2;
break;
+
case ISM330DLC_FIFO_GY_DEC_3:
*val = ISM330DLC_FIFO_GY_DEC_3;
break;
+
case ISM330DLC_FIFO_GY_DEC_4:
*val = ISM330DLC_FIFO_GY_DEC_4;
break;
+
case ISM330DLC_FIFO_GY_DEC_8:
*val = ISM330DLC_FIFO_GY_DEC_8;
break;
+
case ISM330DLC_FIFO_GY_DEC_16:
*val = ISM330DLC_FIFO_GY_DEC_16;
break;
+
case ISM330DLC_FIFO_GY_DEC_32:
*val = ISM330DLC_FIFO_GY_DEC_32;
break;
+
default:
*val = ISM330DLC_FIFO_GY_DISABLE;
break;
@@ -5085,14 +5620,16 @@ int32_t ism330dlc_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx,
{
ism330dlc_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl4.dec_ds3_fifo = (uint8_t)val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -5110,34 +5647,43 @@ int32_t ism330dlc_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx,
{
ism330dlc_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
- switch (fifo_ctrl4.dec_ds3_fifo) {
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ switch (fifo_ctrl4.dec_ds3_fifo)
+ {
case ISM330DLC_FIFO_DS3_DISABLE:
*val = ISM330DLC_FIFO_DS3_DISABLE;
break;
+
case ISM330DLC_FIFO_DS3_NO_DEC:
*val = ISM330DLC_FIFO_DS3_NO_DEC;
break;
+
case ISM330DLC_FIFO_DS3_DEC_2:
*val = ISM330DLC_FIFO_DS3_DEC_2;
break;
+
case ISM330DLC_FIFO_DS3_DEC_3:
*val = ISM330DLC_FIFO_DS3_DEC_3;
break;
+
case ISM330DLC_FIFO_DS3_DEC_4:
*val = ISM330DLC_FIFO_DS3_DEC_4;
break;
+
case ISM330DLC_FIFO_DS3_DEC_8:
*val = ISM330DLC_FIFO_DS3_DEC_8;
break;
+
case ISM330DLC_FIFO_DS3_DEC_16:
*val = ISM330DLC_FIFO_DS3_DEC_16;
break;
+
case ISM330DLC_FIFO_DS3_DEC_32:
*val = ISM330DLC_FIFO_DS3_DEC_32;
break;
+
default:
*val = ISM330DLC_FIFO_DS3_DISABLE;
break;
@@ -5160,14 +5706,16 @@ int32_t ism330dlc_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx,
{
ism330dlc_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl4.dec_ds4_fifo = (uint8_t)val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -5185,34 +5733,43 @@ int32_t ism330dlc_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx,
{
ism330dlc_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
- switch (fifo_ctrl4.dec_ds4_fifo) {
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ switch (fifo_ctrl4.dec_ds4_fifo)
+ {
case ISM330DLC_FIFO_DS4_DISABLE:
*val = ISM330DLC_FIFO_DS4_DISABLE;
break;
+
case ISM330DLC_FIFO_DS4_NO_DEC:
*val = ISM330DLC_FIFO_DS4_NO_DEC;
break;
+
case ISM330DLC_FIFO_DS4_DEC_2:
*val = ISM330DLC_FIFO_DS4_DEC_2;
break;
+
case ISM330DLC_FIFO_DS4_DEC_3:
*val = ISM330DLC_FIFO_DS4_DEC_3;
break;
+
case ISM330DLC_FIFO_DS4_DEC_4:
*val = ISM330DLC_FIFO_DS4_DEC_4;
break;
+
case ISM330DLC_FIFO_DS4_DEC_8:
*val = ISM330DLC_FIFO_DS4_DEC_8;
break;
+
case ISM330DLC_FIFO_DS4_DEC_16:
*val = ISM330DLC_FIFO_DS4_DEC_16;
break;
+
case ISM330DLC_FIFO_DS4_DEC_32:
*val = ISM330DLC_FIFO_DS4_DEC_32;
break;
+
default:
*val = ISM330DLC_FIFO_DS4_DISABLE;
break;
@@ -5234,14 +5791,16 @@ int32_t ism330dlc_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx,
{
ism330dlc_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl4.only_high_data = val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -5258,9 +5817,8 @@ int32_t ism330dlc_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx,
{
ism330dlc_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
*val = fifo_ctrl4.only_high_data;
return ret;
@@ -5279,14 +5837,16 @@ int32_t ism330dlc_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dlc_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl4.stop_on_fth = val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -5299,13 +5859,13 @@ int32_t ism330dlc_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dlc_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dlc_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
*val = fifo_ctrl4.stop_on_fth;
return ret;
@@ -5324,14 +5884,16 @@ int32_t ism330dlc_fifo_mode_set(stmdev_ctx_t *ctx,
{
ism330dlc_fifo_ctrl5_t fifo_ctrl5;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL5,
- (uint8_t*)&fifo_ctrl5, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl5, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl5.fifo_mode = (uint8_t)val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_FIFO_CTRL5,
- (uint8_t*)&fifo_ctrl5, 1);
+ (uint8_t *)&fifo_ctrl5, 1);
}
+
return ret;
}
@@ -5348,25 +5910,31 @@ int32_t ism330dlc_fifo_mode_get(stmdev_ctx_t *ctx,
{
ism330dlc_fifo_ctrl5_t fifo_ctrl5;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL5,
- (uint8_t*)&fifo_ctrl5, 1);
- switch (fifo_ctrl5.fifo_mode) {
+ (uint8_t *)&fifo_ctrl5, 1);
+
+ switch (fifo_ctrl5.fifo_mode)
+ {
case ISM330DLC_BYPASS_MODE:
*val = ISM330DLC_BYPASS_MODE;
break;
+
case ISM330DLC_FIFO_MODE:
*val = ISM330DLC_FIFO_MODE;
break;
+
case ISM330DLC_STREAM_TO_FIFO_MODE:
*val = ISM330DLC_STREAM_TO_FIFO_MODE;
break;
+
case ISM330DLC_BYPASS_TO_STREAM_MODE:
*val = ISM330DLC_BYPASS_TO_STREAM_MODE;
break;
+
case ISM330DLC_STREAM_MODE:
*val = ISM330DLC_STREAM_MODE;
break;
+
default:
*val = ISM330DLC_BYPASS_MODE;
break;
@@ -5388,14 +5956,16 @@ int32_t ism330dlc_fifo_data_rate_set(stmdev_ctx_t *ctx,
{
ism330dlc_fifo_ctrl5_t fifo_ctrl5;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL5,
- (uint8_t*)&fifo_ctrl5, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl5, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl5.odr_fifo = (uint8_t)val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_FIFO_CTRL5,
- (uint8_t*)&fifo_ctrl5, 1);
+ (uint8_t *)&fifo_ctrl5, 1);
}
+
return ret;
}
@@ -5412,43 +5982,55 @@ int32_t ism330dlc_fifo_data_rate_get(stmdev_ctx_t *ctx,
{
ism330dlc_fifo_ctrl5_t fifo_ctrl5;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL5,
- (uint8_t*)&fifo_ctrl5, 1);
- switch (fifo_ctrl5.odr_fifo) {
+ (uint8_t *)&fifo_ctrl5, 1);
+
+ switch (fifo_ctrl5.odr_fifo)
+ {
case ISM330DLC_FIFO_DISABLE:
*val = ISM330DLC_FIFO_DISABLE;
break;
+
case ISM330DLC_FIFO_12Hz5:
*val = ISM330DLC_FIFO_12Hz5;
break;
+
case ISM330DLC_FIFO_26Hz:
*val = ISM330DLC_FIFO_26Hz;
break;
+
case ISM330DLC_FIFO_52Hz:
*val = ISM330DLC_FIFO_52Hz;
break;
+
case ISM330DLC_FIFO_104Hz:
*val = ISM330DLC_FIFO_104Hz;
break;
+
case ISM330DLC_FIFO_208Hz:
*val = ISM330DLC_FIFO_208Hz;
break;
+
case ISM330DLC_FIFO_416Hz:
*val = ISM330DLC_FIFO_416Hz;
break;
+
case ISM330DLC_FIFO_833Hz:
*val = ISM330DLC_FIFO_833Hz;
break;
+
case ISM330DLC_FIFO_1k66Hz:
*val = ISM330DLC_FIFO_1k66Hz;
break;
+
case ISM330DLC_FIFO_3k33Hz:
*val = ISM330DLC_FIFO_3k33Hz;
break;
+
case ISM330DLC_FIFO_6k66Hz:
*val = ISM330DLC_FIFO_6k66Hz;
break;
+
default:
*val = ISM330DLC_FIFO_DISABLE;
break;
@@ -5478,17 +6060,19 @@ int32_t ism330dlc_fifo_data_rate_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
- int32_t ism330dlc_den_polarity_set(stmdev_ctx_t *ctx,
- ism330dlc_den_lh_t val)
+int32_t ism330dlc_den_polarity_set(stmdev_ctx_t *ctx,
+ ism330dlc_den_lh_t val)
{
ism330dlc_ctrl5_c_t ctrl5_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl5_c.den_lh = (uint8_t)val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -5505,15 +6089,18 @@ int32_t ism330dlc_den_polarity_get(stmdev_ctx_t *ctx,
{
ism330dlc_ctrl5_c_t ctrl5_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- switch (ctrl5_c.den_lh) {
+ switch (ctrl5_c.den_lh)
+ {
case ISM330DLC_DEN_ACT_LOW:
*val = ISM330DLC_DEN_ACT_LOW;
break;
+
case ISM330DLC_DEN_ACT_HIGH:
*val = ISM330DLC_DEN_ACT_HIGH;
break;
+
default:
*val = ISM330DLC_DEN_ACT_LOW;
break;
@@ -5530,16 +6117,19 @@ int32_t ism330dlc_den_polarity_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_den_mode_set(stmdev_ctx_t *ctx, ism330dlc_den_mode_t val)
+int32_t ism330dlc_den_mode_set(stmdev_ctx_t *ctx,
+ ism330dlc_den_mode_t val)
{
ism330dlc_ctrl6_c_t ctrl6_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl6_c.den_mode = (uint8_t)val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -5551,25 +6141,31 @@ int32_t ism330dlc_den_mode_set(stmdev_ctx_t *ctx, ism330dlc_den_mode_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_den_mode_get(stmdev_ctx_t *ctx, ism330dlc_den_mode_t *val)
+int32_t ism330dlc_den_mode_get(stmdev_ctx_t *ctx,
+ ism330dlc_den_mode_t *val)
{
ism330dlc_ctrl6_c_t ctrl6_c;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- switch (ctrl6_c.den_mode) {
+ switch (ctrl6_c.den_mode)
+ {
case ISM330DLC_DEN_DISABLE:
*val = ISM330DLC_DEN_DISABLE;
break;
+
case ISM330DLC_LEVEL_LETCHED:
*val = ISM330DLC_LEVEL_LETCHED;
break;
+
case ISM330DLC_LEVEL_TRIGGER:
*val = ISM330DLC_LEVEL_TRIGGER;
break;
+
case ISM330DLC_EDGE_TRIGGER:
*val = ISM330DLC_EDGE_TRIGGER;
break;
+
default:
*val = ISM330DLC_DEN_DISABLE;
break;
@@ -5593,22 +6189,29 @@ int32_t ism330dlc_den_enable_set(stmdev_ctx_t *ctx,
ism330dlc_ctrl4_c_t ctrl4_c;
ism330dlc_ctrl9_xl_t ctrl9_xl;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl9_xl.den_xl_g = (uint8_t)val & 0x01U;
ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C,
- (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
ctrl4_c.den_xl_en = (uint8_t)val & 0x02U;
ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL4_C,
- (uint8_t*)&ctrl4_c, 1);
+ (uint8_t *)&ctrl4_c, 1);
}
}
}
+
return ret;
}
@@ -5627,25 +6230,33 @@ int32_t ism330dlc_den_enable_get(stmdev_ctx_t *ctx,
ism330dlc_ctrl4_c_t ctrl4_c;
ism330dlc_ctrl9_xl_t ctrl9_xl;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- switch ( ( ctrl4_c.den_xl_en << 1) + ctrl9_xl.den_xl_g ) {
+ if (ret == 0)
+ {
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
+
+ switch ((ctrl4_c.den_xl_en << 1) + ctrl9_xl.den_xl_g)
+ {
case ISM330DLC_STAMP_IN_GY_DATA:
*val = ISM330DLC_STAMP_IN_GY_DATA;
break;
+
case ISM330DLC_STAMP_IN_XL_DATA:
*val = ISM330DLC_STAMP_IN_XL_DATA;
break;
+
case ISM330DLC_STAMP_IN_GY_XL_DATA:
*val = ISM330DLC_STAMP_IN_GY_XL_DATA;
break;
+
default:
*val = ISM330DLC_STAMP_IN_GY_DATA;
break;
}
}
+
return ret;
}
@@ -5661,13 +6272,16 @@ int32_t ism330dlc_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dlc_ctrl9_xl_t ctrl9_xl;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl9_xl.den_z = val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
+ (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -5683,8 +6297,8 @@ int32_t ism330dlc_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dlc_ctrl9_xl_t ctrl9_xl;
int32_t ret;
-
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
*val = ctrl9_xl.den_z;
return ret;
@@ -5702,13 +6316,16 @@ int32_t ism330dlc_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dlc_ctrl9_xl_t ctrl9_xl;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl9_xl.den_y = val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
+ (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -5724,8 +6341,8 @@ int32_t ism330dlc_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dlc_ctrl9_xl_t ctrl9_xl;
int32_t ret;
-
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
*val = ctrl9_xl.den_y;
return ret;
@@ -5743,12 +6360,16 @@ int32_t ism330dlc_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dlc_ctrl9_xl_t ctrl9_xl;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl9_xl.den_x = val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -5764,8 +6385,8 @@ int32_t ism330dlc_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dlc_ctrl9_xl_t ctrl9_xl;
int32_t ret;
-
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
*val = ctrl9_xl.den_x;
return ret;
@@ -5796,12 +6417,16 @@ int32_t ism330dlc_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dlc_ctrl9_xl_t ctrl9_xl;
int32_t ret;
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl9_xl.soft_en = val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -5817,8 +6442,8 @@ int32_t ism330dlc_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dlc_ctrl9_xl_t ctrl9_xl;
int32_t ret;
-
- ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
*val = ctrl9_xl.soft_en;
return ret;
@@ -5837,25 +6462,33 @@ int32_t ism330dlc_mag_hard_iron_set(stmdev_ctx_t *ctx, uint8_t val)
ism330dlc_master_config_t master_config;
ism330dlc_ctrl10_c_t ctrl10_c;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
master_config.iron_en = val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL10_C,
- (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
- if (val != 0x00U) {
+ (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
+ if (val != 0x00U)
+ {
ctrl10_c.func_en = val;
}
+
ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL10_C,
- (uint8_t*)&ctrl10_c, 1);
+ (uint8_t *)&ctrl10_c, 1);
}
}
}
+
return ret;
}
@@ -5871,9 +6504,8 @@ int32_t ism330dlc_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dlc_master_config_t master_config;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
*val = master_config.iron_en;
return ret;
@@ -5888,17 +6520,22 @@ int32_t ism330dlc_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_mag_soft_iron_mat_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t ism330dlc_mag_soft_iron_mat_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
-
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dlc_write_reg(ctx, ISM330DLC_MAG_SI_XX, buff, 9);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
}
}
+
return ret;
}
@@ -5911,17 +6548,22 @@ int32_t ism330dlc_mag_soft_iron_mat_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_mag_soft_iron_mat_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t ism330dlc_mag_soft_iron_mat_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
-
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_MAG_SI_XX, buff, 9);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
}
}
+
return ret;
}
@@ -5938,20 +6580,24 @@ int32_t ism330dlc_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val)
{
uint8_t buff[6];
int32_t ret;
-
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
- if(ret == 0){
- buff[1] = (uint8_t) ((uint16_t)val[0] / 256U);
- buff[0] = (uint8_t) ((uint16_t)val[0] - (buff[1] * 256U));
- buff[3] = (uint8_t) ((uint16_t)val[1] / 256U);
- buff[2] = (uint8_t) ((uint16_t)val[1] - (buff[3] * 256U));
- buff[5] = (uint8_t) ((uint16_t)val[2] / 256U);
- buff[4] = (uint8_t) ((uint16_t)val[2] - (buff[5] * 256U));
+
+ if (ret == 0)
+ {
+ buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
+ buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
+ buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
+ buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
+ buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
+ buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
ret = ism330dlc_write_reg(ctx, ISM330DLC_MAG_OFFX_L, buff, 6);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
}
}
+
return ret;
}
@@ -5968,9 +6614,10 @@ int32_t ism330dlc_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val)
{
uint8_t buff[6];
int32_t ret;
-
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_MAG_OFFX_L, buff, 6);
val[0] = (int16_t)buff[1];
val[0] = (val[0] * 256) + (int16_t)buff[0];
@@ -5978,10 +6625,13 @@ int32_t ism330dlc_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val)
val[1] = (val[1] * 256) + (int16_t)buff[2];
val[2] = (int16_t)buff[5];
val[2] = (val[2] * 256) + (int16_t)buff[4];
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
}
}
+
return ret;
}
@@ -6007,18 +6657,21 @@ int32_t ism330dlc_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ism330dlc_sh_sync_sens_frame_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
ism330dlc_sensor_sync_time_frame_t sensor_sync_time_frame;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_SENSOR_SYNC_TIME_FRAME,
- (uint8_t*)&sensor_sync_time_frame, 1);
- if(ret == 0){
- sensor_sync_time_frame.tph = val;
+ (uint8_t *)&sensor_sync_time_frame, 1);
+
+ if (ret == 0)
+ {
+ sensor_sync_time_frame.tph = val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_SENSOR_SYNC_TIME_FRAME,
- (uint8_t*)&sensor_sync_time_frame, 1);
+ (uint8_t *)&sensor_sync_time_frame, 1);
}
+
return ret;
}
@@ -6031,13 +6684,13 @@ int32_t ism330dlc_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dlc_sh_sync_sens_frame_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dlc_sensor_sync_time_frame_t sensor_sync_time_frame;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_SENSOR_SYNC_TIME_FRAME,
- (uint8_t*)&sensor_sync_time_frame, 1);
+ (uint8_t *)&sensor_sync_time_frame, 1);
*val = sensor_sync_time_frame.tph;
return ret;
@@ -6056,14 +6709,16 @@ int32_t ism330dlc_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx,
{
ism330dlc_sensor_sync_res_ratio_t sensor_sync_res_ratio;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_SENSOR_SYNC_RES_RATIO,
- (uint8_t*)&sensor_sync_res_ratio, 1);
- if(ret == 0){
+ (uint8_t *)&sensor_sync_res_ratio, 1);
+
+ if (ret == 0)
+ {
sensor_sync_res_ratio.rr = (uint8_t) val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_SENSOR_SYNC_RES_RATIO,
- (uint8_t*)&sensor_sync_res_ratio, 1);
+ (uint8_t *)&sensor_sync_res_ratio, 1);
}
+
return ret;
}
@@ -6080,23 +6735,27 @@ int32_t ism330dlc_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx,
{
ism330dlc_sensor_sync_res_ratio_t sensor_sync_res_ratio;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_SENSOR_SYNC_RES_RATIO,
- (uint8_t*)&sensor_sync_res_ratio, 1);
+ (uint8_t *)&sensor_sync_res_ratio, 1);
- switch ( sensor_sync_res_ratio.rr) {
+ switch (sensor_sync_res_ratio.rr)
+ {
case ISM330DLC_RES_RATIO_2_11:
*val = ISM330DLC_RES_RATIO_2_11;
break;
+
case ISM330DLC_RES_RATIO_2_12:
*val = ISM330DLC_RES_RATIO_2_12;
break;
+
case ISM330DLC_RES_RATIO_2_13:
*val = ISM330DLC_RES_RATIO_2_13;
break;
+
case ISM330DLC_RES_RATIO_2_14:
*val = ISM330DLC_RES_RATIO_2_14;
break;
+
default:
*val = ISM330DLC_RES_RATIO_2_11;
break;
@@ -6117,14 +6776,16 @@ int32_t ism330dlc_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dlc_master_config_t master_config;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
master_config.master_on = val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
+
return ret;
}
@@ -6140,9 +6801,8 @@ int32_t ism330dlc_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dlc_master_config_t master_config;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
*val = master_config.master_on;
return ret;
@@ -6160,14 +6820,16 @@ int32_t ism330dlc_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dlc_master_config_t master_config;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
master_config.pass_through_mode = val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
+
return ret;
}
@@ -6183,9 +6845,8 @@ int32_t ism330dlc_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dlc_master_config_t master_config;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
*val = master_config.pass_through_mode;
return ret;
@@ -6204,13 +6865,14 @@ int32_t ism330dlc_sh_pin_mode_set(stmdev_ctx_t *ctx,
{
ism330dlc_master_config_t master_config;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
master_config.pull_up_en = (uint8_t) val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
return ret;
@@ -6229,20 +6891,24 @@ int32_t ism330dlc_sh_pin_mode_get(stmdev_ctx_t *ctx,
{
ism330dlc_master_config_t master_config;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- switch (master_config.pull_up_en) {
+ (uint8_t *)&master_config, 1);
+
+ switch (master_config.pull_up_en)
+ {
case ISM330DLC_EXT_PULL_UP:
*val = ISM330DLC_EXT_PULL_UP;
break;
+
case ISM330DLC_INTERNAL_PULL_UP:
*val = ISM330DLC_INTERNAL_PULL_UP;
break;
+
default:
*val = ISM330DLC_EXT_PULL_UP;
break;
}
+
return ret;
}
@@ -6259,14 +6925,16 @@ int32_t ism330dlc_sh_syncro_mode_set(stmdev_ctx_t *ctx,
{
ism330dlc_master_config_t master_config;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
master_config.start_config = (uint8_t)val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
+
return ret;
}
@@ -6283,16 +6951,19 @@ int32_t ism330dlc_sh_syncro_mode_get(stmdev_ctx_t *ctx,
{
ism330dlc_master_config_t master_config;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- switch (master_config.start_config) {
+ (uint8_t *)&master_config, 1);
+
+ switch (master_config.start_config)
+ {
case ISM330DLC_XL_GY_DRDY:
*val = ISM330DLC_XL_GY_DRDY;
break;
+
case ISM330DLC_EXT_ON_INT2_PIN:
*val = ISM330DLC_EXT_ON_INT2_PIN;
break;
+
default:
*val = ISM330DLC_XL_GY_DRDY;
break;
@@ -6313,14 +6984,16 @@ int32_t ism330dlc_sh_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dlc_master_config_t master_config;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
master_config.drdy_on_int1 = val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
+
return ret;
}
@@ -6336,9 +7009,8 @@ int32_t ism330dlc_sh_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
{
ism330dlc_master_config_t master_config;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
*val = master_config.drdy_on_int1;
return ret;
@@ -6357,11 +7029,14 @@ int32_t ism330dlc_sh_read_data_raw_get(stmdev_ctx_t *ctx,
{
int32_t ret;
ret = ism330dlc_read_reg(ctx, ISM330DLC_SENSORHUB1_REG,
- (uint8_t*)&(val->sh_byte_1), 12);
- if(ret == 0){
+ (uint8_t *) & (val->sh_byte_1), 12);
+
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_SENSORHUB13_REG,
- (uint8_t*)&(val->sh_byte_13), 6);
+ (uint8_t *) & (val->sh_byte_13), 6);
}
+
return ret;
}
@@ -6378,14 +7053,16 @@ int32_t ism330dlc_sh_cmd_sens_sync_set(stmdev_ctx_t *ctx, uint8_t val)
{
ism330dlc_master_cmd_code_t master_cmd_code;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CMD_CODE,
- (uint8_t*)&master_cmd_code, 1);
- if(ret == 0){
+ (uint8_t *)&master_cmd_code, 1);
+
+ if (ret == 0)
+ {
master_cmd_code.master_cmd_code = val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_MASTER_CMD_CODE,
- (uint8_t*)&master_cmd_code, 1);
+ (uint8_t *)&master_cmd_code, 1);
}
+
return ret;
}
@@ -6398,13 +7075,13 @@ int32_t ism330dlc_sh_cmd_sens_sync_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dlc_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dlc_master_cmd_code_t master_cmd_code;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CMD_CODE,
- (uint8_t*)&master_cmd_code, 1);
+ (uint8_t *)&master_cmd_code, 1);
*val = master_cmd_code.master_cmd_code;
return ret;
@@ -6419,18 +7096,21 @@ int32_t ism330dlc_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_sh_spi_sync_error_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t ism330dlc_sh_spi_sync_error_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
ism330dlc_sens_sync_spi_error_code_t sens_sync_spi_error_code;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_SENS_SYNC_SPI_ERROR_CODE,
- (uint8_t*)&sens_sync_spi_error_code, 1);
- if(ret == 0){
+ (uint8_t *)&sens_sync_spi_error_code, 1);
+
+ if (ret == 0)
+ {
sens_sync_spi_error_code.error_code = val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_SENS_SYNC_SPI_ERROR_CODE,
- (uint8_t*)&sens_sync_spi_error_code, 1);
+ (uint8_t *)&sens_sync_spi_error_code, 1);
}
+
return ret;
}
@@ -6443,13 +7123,13 @@ int32_t ism330dlc_sh_spi_sync_error_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t ism330dlc_sh_spi_sync_error_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t ism330dlc_sh_spi_sync_error_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
ism330dlc_sens_sync_spi_error_code_t sens_sync_spi_error_code;
int32_t ret;
-
ret = ism330dlc_read_reg(ctx, ISM330DLC_SENS_SYNC_SPI_ERROR_CODE,
- (uint8_t*)&sens_sync_spi_error_code, 1);
+ (uint8_t *)&sens_sync_spi_error_code, 1);
*val = sens_sync_spi_error_code.error_code;
return ret;
@@ -6464,24 +7144,30 @@ int32_t ism330dlc_sh_spi_sync_error_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t ism330dlc_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx,
- ism330dlc_aux_sens_on_t val)
+ ism330dlc_aux_sens_on_t val)
{
ism330dlc_slave0_config_t slave0_config;
int32_t ret;
-
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave0_config, 1);
+
+ if (ret == 0)
+ {
slave0_config.aux_sens_on = (uint8_t) val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave0_config, 1);
+
+ if (ret == 0)
+ {
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
}
}
}
+
return ret;
}
@@ -6498,29 +7184,38 @@ int32_t ism330dlc_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx,
{
ism330dlc_slave0_config_t slave0_config;
int32_t ret;
-
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
- if(ret == 0){
- ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
- if(ret == 0){
- switch (slave0_config.aux_sens_on) {
+
+ if (ret == 0)
+ {
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE0_CONFIG,
+ (uint8_t *)&slave0_config, 1);
+
+ if (ret == 0)
+ {
+ switch (slave0_config.aux_sens_on)
+ {
case ISM330DLC_SLV_0:
*val = ISM330DLC_SLV_0;
break;
+
case ISM330DLC_SLV_0_1:
*val = ISM330DLC_SLV_0_1;
break;
+
case ISM330DLC_SLV_0_1_2:
*val = ISM330DLC_SLV_0_1_2;
break;
+
case ISM330DLC_SLV_0_1_2_3:
*val = ISM330DLC_SLV_0_1_2_3;
break;
+
default:
*val = ISM330DLC_SLV_0;
break;
}
+
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
}
}
@@ -6544,25 +7239,33 @@ int32_t ism330dlc_sh_cfg_write(stmdev_ctx_t *ctx,
{
ism330dlc_slv0_add_t slv0_add;
int32_t ret;
-
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv0_add.slave0_add = val->slv0_add;
slv0_add.rw_0 = 0;
ret = ism330dlc_write_reg(ctx, ISM330DLC_SLV0_ADD,
- (uint8_t*)&slv0_add, 1);
- if(ret == 0){
+ (uint8_t *)&slv0_add, 1);
+
+ if (ret == 0)
+ {
ret = ism330dlc_write_reg(ctx, ISM330DLC_SLV0_SUBADD,
&(val->slv0_subadd), 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dlc_write_reg(ctx, ISM330DLC_DATAWRITE_SRC_MODE_SUB_SLV0,
&(val->slv0_data), 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
}
}
}
}
+
return ret;
}
@@ -6583,30 +7286,40 @@ int32_t ism330dlc_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
ism330dlc_slave0_config_t slave0_config;
ism330dlc_slv0_add_t slv0_add;
int32_t ret;
-
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv0_add.slave0_add = val->slv_add;
slv0_add.rw_0 = 1;
ret = ism330dlc_write_reg(ctx, ISM330DLC_SLV0_ADD,
- (uint8_t*)&slv0_add, 1);
- if(ret == 0){
+ (uint8_t *)&slv0_add, 1);
+
+ if (ret == 0)
+ {
ret = ism330dlc_write_reg(ctx, ISM330DLC_SLV0_SUBADD,
- &(val->slv_subadd), 1);
- if(ret == 0){
+ &(val->slv_subadd), 1);
+
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
+ (uint8_t *)&slave0_config, 1);
slave0_config.slave0_numop = val->slv_len;
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave0_config, 1);
+
+ if (ret == 0)
+ {
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
}
}
}
}
}
+
return ret;
}
@@ -6627,30 +7340,40 @@ int32_t ism330dlc_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
ism330dlc_slave1_config_t slave1_config;
ism330dlc_slv1_add_t slv1_add;
int32_t ret;
-
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv1_add.slave1_add = val->slv_add;
slv1_add.r_1 = 1;
ret = ism330dlc_write_reg(ctx, ISM330DLC_SLV1_ADD,
- (uint8_t*)&slv1_add, 1);
- if(ret == 0){
+ (uint8_t *)&slv1_add, 1);
+
+ if (ret == 0)
+ {
ret = ism330dlc_write_reg(ctx, ISM330DLC_SLV1_SUBADD,
- &(val->slv_subadd), 1);
- if(ret == 0){
+ &(val->slv_subadd), 1);
+
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
+ (uint8_t *)&slave1_config, 1);
slave1_config.slave1_numop = val->slv_len;
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave1_config, 1);
+
+ if (ret == 0)
+ {
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
}
}
}
}
}
+
return ret;
}
@@ -6671,24 +7394,33 @@ int32_t ism330dlc_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
ism330dlc_slv2_add_t slv2_add;
ism330dlc_slave2_config_t slave2_config;
int32_t ret;
-
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv2_add.slave2_add = val->slv_add;
slv2_add.r_2 = 1;
ret = ism330dlc_write_reg(ctx, ISM330DLC_SLV2_ADD,
- (uint8_t*)&slv2_add, 1);
- if(ret == 0){
+ (uint8_t *)&slv2_add, 1);
+
+ if (ret == 0)
+ {
ret = ism330dlc_write_reg(ctx, ISM330DLC_SLV2_SUBADD,
&(val->slv_subadd), 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE2_CONFIG,
- (uint8_t*)&slave2_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave2_config, 1);
+
+ if (ret == 0)
+ {
slave2_config.slave2_numop = val->slv_len;
ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE2_CONFIG,
- (uint8_t*)&slave2_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave2_config, 1);
+
+ if (ret == 0)
+ {
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
}
}
@@ -6716,30 +7448,40 @@ int32_t ism330dlc_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
ism330dlc_slave3_config_t slave3_config;
ism330dlc_slv3_add_t slv3_add;
int32_t ret;
-
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv3_add.slave3_add = val->slv_add;
slv3_add.r_3 = 1;
ret = ism330dlc_write_reg(ctx, ISM330DLC_SLV3_ADD,
- (uint8_t*)&slv3_add, 1);
- if(ret == 0){
+ (uint8_t *)&slv3_add, 1);
+
+ if (ret == 0)
+ {
ret = ism330dlc_write_reg(ctx, ISM330DLC_SLV3_SUBADD,
- (uint8_t*)&(val->slv_subadd), 1);
- if(ret == 0){
+ (uint8_t *) & (val->slv_subadd), 1);
+
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE3_CONFIG,
- (uint8_t*)&slave3_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave3_config, 1);
+
+ if (ret == 0)
+ {
slave3_config.slave3_numop = val->slv_len;
ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE3_CONFIG,
- (uint8_t*)&slave3_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave3_config, 1);
+
+ if (ret == 0)
+ {
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
}
}
}
}
}
+
return ret;
}
@@ -6757,20 +7499,26 @@ int32_t ism330dlc_sh_slave_0_dec_set(stmdev_ctx_t *ctx,
{
ism330dlc_slave0_config_t slave0_config;
int32_t ret;
-
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave0_config, 1);
+
+ if (ret == 0)
+ {
slave0_config.slave0_rate = (uint8_t) val;
ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave0_config, 1);
+
+ if (ret == 0)
+ {
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
}
}
}
+
return ret;
}
@@ -6788,29 +7536,38 @@ int32_t ism330dlc_sh_slave_0_dec_get(stmdev_ctx_t *ctx,
{
ism330dlc_slave0_config_t slave0_config;
int32_t ret;
-
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
- if(ret == 0){
- ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
- if(ret == 0){
- switch (slave0_config.slave0_rate) {
+
+ if (ret == 0)
+ {
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE0_CONFIG,
+ (uint8_t *)&slave0_config, 1);
+
+ if (ret == 0)
+ {
+ switch (slave0_config.slave0_rate)
+ {
case ISM330DLC_SL0_NO_DEC:
*val = ISM330DLC_SL0_NO_DEC;
break;
+
case ISM330DLC_SL0_DEC_2:
*val = ISM330DLC_SL0_DEC_2;
break;
+
case ISM330DLC_SL0_DEC_4:
*val = ISM330DLC_SL0_DEC_4;
break;
+
case ISM330DLC_SL0_DEC_8:
*val = ISM330DLC_SL0_DEC_8;
break;
+
default:
*val = ISM330DLC_SL0_NO_DEC;
break;
}
+
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
}
}
@@ -6834,20 +7591,26 @@ int32_t ism330dlc_sh_write_mode_set(stmdev_ctx_t *ctx,
{
ism330dlc_slave1_config_t slave1_config;
int32_t ret;
-
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
+ (uint8_t *)&slave1_config, 1);
slave1_config.write_once = (uint8_t) val;
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave1_config, 1);
+
+ if (ret == 0)
+ {
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
}
}
}
+
return ret;
}
@@ -6867,23 +7630,30 @@ int32_t ism330dlc_sh_write_mode_get(stmdev_ctx_t *ctx,
{
ism330dlc_slave1_config_t slave1_config;
int32_t ret;
-
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
- if(ret == 0){
- ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
- if(ret == 0){
- switch (slave1_config.write_once) {
+
+ if (ret == 0)
+ {
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE1_CONFIG,
+ (uint8_t *)&slave1_config, 1);
+
+ if (ret == 0)
+ {
+ switch (slave1_config.write_once)
+ {
case ISM330DLC_EACH_SH_CYCLE:
*val = ISM330DLC_EACH_SH_CYCLE;
break;
+
case ISM330DLC_ONLY_FIRST_CYCLE:
*val = ISM330DLC_ONLY_FIRST_CYCLE;
break;
+
default:
*val = ISM330DLC_EACH_SH_CYCLE;
break;
}
+
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
}
}
@@ -6905,20 +7675,26 @@ int32_t ism330dlc_sh_slave_1_dec_set(stmdev_ctx_t *ctx,
{
ism330dlc_slave1_config_t slave1_config;
int32_t ret;
-
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
- if(ret == 0){
- ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE1_CONFIG,
+ (uint8_t *)&slave1_config, 1);
+
+ if (ret == 0)
+ {
slave1_config.slave1_rate = (uint8_t) val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
- if(ret == 0){
- ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE1_CONFIG,
+ (uint8_t *)&slave1_config, 1);
+
+ if (ret == 0)
+ {
+ ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
}
}
}
+
return ret;
}
@@ -6935,29 +7711,38 @@ int32_t ism330dlc_sh_slave_1_dec_get(stmdev_ctx_t *ctx,
{
ism330dlc_slave1_config_t slave1_config;
int32_t ret;
-
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
- if(ret == 0){
- ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
- if(ret == 0){
- switch (slave1_config.slave1_rate) {
+
+ if (ret == 0)
+ {
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE1_CONFIG,
+ (uint8_t *)&slave1_config, 1);
+
+ if (ret == 0)
+ {
+ switch (slave1_config.slave1_rate)
+ {
case ISM330DLC_SL1_NO_DEC:
*val = ISM330DLC_SL1_NO_DEC;
break;
+
case ISM330DLC_SL1_DEC_2:
*val = ISM330DLC_SL1_DEC_2;
break;
+
case ISM330DLC_SL1_DEC_4:
*val = ISM330DLC_SL1_DEC_4;
break;
+
case ISM330DLC_SL1_DEC_8:
*val = ISM330DLC_SL1_DEC_8;
break;
+
default:
*val = ISM330DLC_SL1_NO_DEC;
break;
}
+
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
}
}
@@ -6979,20 +7764,26 @@ int32_t ism330dlc_sh_slave_2_dec_set(stmdev_ctx_t *ctx,
{
ism330dlc_slave2_config_t slave2_config;
int32_t ret;
-
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
- if(ret == 0){
- ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE2_CONFIG,
- (uint8_t*)&slave2_config, 1);
- if(ret == 0){
- slave2_config.slave2_rate =(uint8_t) val;
- ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE2_CONFIG,
- (uint8_t*)&slave2_config, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE2_CONFIG,
+ (uint8_t *)&slave2_config, 1);
+
+ if (ret == 0)
+ {
+ slave2_config.slave2_rate = (uint8_t) val;
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE2_CONFIG,
+ (uint8_t *)&slave2_config, 1);
+
+ if (ret == 0)
+ {
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
}
}
}
+
return ret;
}
@@ -7010,29 +7801,38 @@ int32_t ism330dlc_sh_slave_2_dec_get(stmdev_ctx_t *ctx,
{
ism330dlc_slave2_config_t slave2_config;
int32_t ret;
-
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
- if(ret == 0){
- ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE2_CONFIG,
- (uint8_t*)&slave2_config, 1);
- if(ret == 0){
- switch (slave2_config.slave2_rate) {
+
+ if (ret == 0)
+ {
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE2_CONFIG,
+ (uint8_t *)&slave2_config, 1);
+
+ if (ret == 0)
+ {
+ switch (slave2_config.slave2_rate)
+ {
case ISM330DLC_SL2_NO_DEC:
*val = ISM330DLC_SL2_NO_DEC;
break;
+
case ISM330DLC_SL2_DEC_2:
*val = ISM330DLC_SL2_DEC_2;
break;
+
case ISM330DLC_SL2_DEC_4:
*val = ISM330DLC_SL2_DEC_4;
break;
+
case ISM330DLC_SL2_DEC_8:
*val = ISM330DLC_SL2_DEC_8;
break;
+
default:
*val = ISM330DLC_SL2_NO_DEC;
break;
}
+
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
}
}
@@ -7054,20 +7854,26 @@ int32_t ism330dlc_sh_slave_3_dec_set(stmdev_ctx_t *ctx,
{
ism330dlc_slave3_config_t slave3_config;
int32_t ret;
-
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
- if(ret == 0){
- ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE3_CONFIG,
- (uint8_t*)&slave3_config, 1);
+
+ if (ret == 0)
+ {
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE3_CONFIG,
+ (uint8_t *)&slave3_config, 1);
slave3_config.slave3_rate = (uint8_t)val;
- if(ret == 0){
- ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE3_CONFIG,
- (uint8_t*)&slave3_config, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
+ ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE3_CONFIG,
+ (uint8_t *)&slave3_config, 1);
+
+ if (ret == 0)
+ {
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
}
}
}
+
return ret;
}
@@ -7085,29 +7891,38 @@ int32_t ism330dlc_sh_slave_3_dec_get(stmdev_ctx_t *ctx,
{
ism330dlc_slave3_config_t slave3_config;
int32_t ret;
-
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
- if(ret == 0){
- ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE3_CONFIG,
- (uint8_t*)&slave3_config, 1);
- if(ret == 0){
- switch (slave3_config.slave3_rate) {
+
+ if (ret == 0)
+ {
+ ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE3_CONFIG,
+ (uint8_t *)&slave3_config, 1);
+
+ if (ret == 0)
+ {
+ switch (slave3_config.slave3_rate)
+ {
case ISM330DLC_SL3_NO_DEC:
*val = ISM330DLC_SL3_NO_DEC;
break;
+
case ISM330DLC_SL3_DEC_2:
*val = ISM330DLC_SL3_DEC_2;
break;
+
case ISM330DLC_SL3_DEC_4:
*val = ISM330DLC_SL3_DEC_4;
break;
+
case ISM330DLC_SL3_DEC_8:
*val = ISM330DLC_SL3_DEC_8;
break;
+
default:
*val = ISM330DLC_SL3_NO_DEC;
break;
}
+
ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
}
}
diff --git a/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.h b/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.h
index 65813f27bbeada0198775b8743a567b92fcffc66..2a2c8d8e80dc57e64685982681cb31e1c850471e 100644
--- a/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.h
+++ b/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file ism330dlc_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * ism330dlc_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file ism330dlc_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * ism330dlc_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef ISM330DLC_REGS_H
#define ISM330DLC_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup ISM330DLC
@@ -74,7 +75,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -107,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -131,7 +134,7 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
+ * You can create a sensor configuration by your own or using
* Unico / Unicleo tools available on STMicroelectronics
* web site.
*
@@ -139,7 +142,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -174,7 +178,8 @@ typedef struct {
*/
#define ISM330DLC_FUNC_CFG_ACCESS 0x01U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 7;
uint8_t func_cfg_en : 1;
@@ -185,7 +190,8 @@ typedef struct {
} ism330dlc_func_cfg_access_t;
#define ISM330DLC_SENSOR_SYNC_TIME_FRAME 0x04U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tph : 4;
uint8_t not_used_01 : 4;
@@ -196,7 +202,8 @@ typedef struct {
} ism330dlc_sensor_sync_time_frame_t;
#define ISM330DLC_SENSOR_SYNC_RES_RATIO 0x05U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t rr : 2;
uint8_t not_used_01 : 6;
@@ -207,12 +214,14 @@ typedef struct {
} ism330dlc_sensor_sync_res_ratio_t;
#define ISM330DLC_FIFO_CTRL1 0x06U
-typedef struct {
+typedef struct
+{
uint8_t fth : 8; /* + FIFO_CTRL2(fth) */
} ism330dlc_fifo_ctrl1_t;
#define ISM330DLC_FIFO_CTRL2 0x07U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fth : 3; /* + FIFO_CTRL1(fth) */
uint8_t fifo_temp_en : 1;
@@ -227,7 +236,8 @@ typedef struct {
} ism330dlc_fifo_ctrl2_t;
#define ISM330DLC_FIFO_CTRL3 0x08U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t dec_fifo_xl : 3;
uint8_t dec_fifo_gyro : 3;
@@ -240,7 +250,8 @@ typedef struct {
} ism330dlc_fifo_ctrl3_t;
#define ISM330DLC_FIFO_CTRL4 0x09U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t dec_ds3_fifo : 3;
uint8_t dec_ds4_fifo : 3;
@@ -255,7 +266,8 @@ typedef struct {
} ism330dlc_fifo_ctrl4_t;
#define ISM330DLC_FIFO_CTRL5 0x0AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fifo_mode : 3;
uint8_t odr_fifo : 4;
@@ -268,7 +280,8 @@ typedef struct {
} ism330dlc_fifo_ctrl5_t;
#define ISM330DLC_DRDY_PULSE_CFG 0x0BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 7;
uint8_t drdy_pulsed : 1;
@@ -279,7 +292,8 @@ typedef struct {
} ism330dlc_drdy_pulse_cfg_t;
#define ISM330DLC_INT1_CTRL 0x0DU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_drdy_xl : 1;
uint8_t int1_drdy_g : 1;
@@ -300,7 +314,8 @@ typedef struct {
} ism330dlc_int1_ctrl_t;
#define ISM330DLC_INT2_CTRL 0x0EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_drdy_xl : 1;
uint8_t int2_drdy_g : 1;
@@ -322,7 +337,8 @@ typedef struct {
#define ISM330DLC_WHO_AM_I 0x0FU
#define ISM330DLC_CTRL1_XL 0x10U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bw0_xl : 1;
uint8_t lpf1_bw_sel : 1;
@@ -337,7 +353,8 @@ typedef struct {
} ism330dlc_ctrl1_xl_t;
#define ISM330DLC_CTRL2_G 0x11U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t fs_g : 3; /* fs_g + fs_125 */
@@ -350,7 +367,8 @@ typedef struct {
} ism330dlc_ctrl2_g_t;
#define ISM330DLC_CTRL3_C 0x12U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sw_reset : 1;
uint8_t ble : 1;
@@ -373,7 +391,8 @@ typedef struct {
} ism330dlc_ctrl3_c_t;
#define ISM330DLC_CTRL4_C 0x13U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t lpf1_sel_g : 1;
@@ -396,7 +415,8 @@ typedef struct {
} ism330dlc_ctrl4_c_t;
#define ISM330DLC_CTRL5_C 0x14U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_xl : 2;
uint8_t st_g : 2;
@@ -411,15 +431,18 @@ typedef struct {
} ism330dlc_ctrl5_c_t;
#define ISM330DLC_CTRL6_C 0x15U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ftype : 2;
uint8_t not_used_01 : 1;
uint8_t usr_off_w : 1;
uint8_t xl_hm_mode : 1;
- uint8_t den_mode : 3; /* trig_en + lvl_en + lvl2_en */
+uint8_t den_mode :
+ 3; /* trig_en + lvl_en + lvl2_en */
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t den_mode : 3; /* trig_en + lvl_en + lvl2_en */
+uint8_t den_mode :
+ 3; /* trig_en + lvl_en + lvl2_en */
uint8_t xl_hm_mode : 1;
uint8_t usr_off_w : 1;
uint8_t not_used_01 : 1;
@@ -428,7 +451,8 @@ typedef struct {
} ism330dlc_ctrl6_c_t;
#define ISM330DLC_CTRL7_G 0x16U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t rounding_status : 1;
@@ -447,7 +471,8 @@ typedef struct {
} ism330dlc_ctrl7_g_t;
#define ISM330DLC_CTRL8_XL 0x17U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t low_pass_on_6d : 1;
uint8_t not_used_01 : 1;
@@ -468,7 +493,8 @@ typedef struct {
} ism330dlc_ctrl8_xl_t;
#define ISM330DLC_CTRL9_XL 0x18U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t soft_en : 1;
@@ -489,7 +515,8 @@ typedef struct {
} ism330dlc_ctrl9_xl_t;
#define ISM330DLC_CTRL10_C 0x19U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t func_en : 1;
@@ -508,7 +535,8 @@ typedef struct {
} ism330dlc_ctrl10_c_t;
#define ISM330DLC_MASTER_CONFIG 0x1AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t master_on : 1;
uint8_t iron_en : 1;
@@ -531,7 +559,8 @@ typedef struct {
} ism330dlc_master_config_t;
#define ISM330DLC_WAKE_UP_SRC 0x1BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_wu : 1;
uint8_t y_wu : 1;
@@ -552,7 +581,8 @@ typedef struct {
} ism330dlc_wake_up_src_t;
#define ISM330DLC_TAP_SRC 0x1CU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_tap : 1;
uint8_t y_tap : 1;
@@ -575,7 +605,8 @@ typedef struct {
} ism330dlc_tap_src_t;
#define ISM330DLC_D6D_SRC 0x1DU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
@@ -598,7 +629,8 @@ typedef struct {
} ism330dlc_d6d_src_t;
#define ISM330DLC_STATUS_REG 0x1EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlda : 1;
uint8_t gda : 1;
@@ -613,7 +645,8 @@ typedef struct {
} ism330dlc_status_reg_t;
#define ISM330DLC_STATUS_SPIAUX 0x1EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlda : 1;
uint8_t gda : 1;
@@ -642,7 +675,8 @@ typedef struct {
#define ISM330DLC_OUTZ_L_XL 0x2CU
#define ISM330DLC_OUTZ_H_XL 0x2DU
#define ISM330DLC_SENSORHUB1_REG 0x2EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -665,7 +699,8 @@ typedef struct {
} ism330dlc_sensorhub1_reg_t;
#define ISM330DLC_SENSORHUB2_REG 0x2FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -688,7 +723,8 @@ typedef struct {
} ism330dlc_sensorhub2_reg_t;
#define ISM330DLC_SENSORHUB3_REG 0x30U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -711,7 +747,8 @@ typedef struct {
} ism330dlc_sensorhub3_reg_t;
#define ISM330DLC_SENSORHUB4_REG 0x31U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -734,7 +771,8 @@ typedef struct {
} ism330dlc_sensorhub4_reg_t;
#define ISM330DLC_SENSORHUB5_REG 0x32U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -757,7 +795,8 @@ typedef struct {
} ism330dlc_sensorhub5_reg_t;
#define ISM330DLC_SENSORHUB6_REG 0x33U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -780,7 +819,8 @@ typedef struct {
} ism330dlc_sensorhub6_reg_t;
#define ISM330DLC_SENSORHUB7_REG 0x34U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -803,7 +843,8 @@ typedef struct {
} ism330dlc_sensorhub7_reg_t;
#define ISM330DLC_SENSORHUB8_REG 0x35U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -826,7 +867,8 @@ typedef struct {
} ism330dlc_sensorhub8_reg_t;
#define ISM330DLC_SENSORHUB9_REG 0x36U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -849,7 +891,8 @@ typedef struct {
} ism330dlc_sensorhub9_reg_t;
#define ISM330DLC_SENSORHUB10_REG 0x37U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -872,7 +915,8 @@ typedef struct {
} ism330dlc_sensorhub10_reg_t;
#define ISM330DLC_SENSORHUB11_REG 0x38U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -895,7 +939,8 @@ typedef struct {
} ism330dlc_sensorhub11_reg_t;
#define ISM330DLC_SENSORHUB12_REG 0x39U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -918,12 +963,14 @@ typedef struct {
} ism330dlc_sensorhub12_reg_t;
#define ISM330DLC_FIFO_STATUS1 0x3AU
-typedef struct {
+typedef struct
+{
uint8_t diff_fifo : 8; /* + FIFO_STATUS2(diff_fifo) */
} ism330dlc_fifo_status1_t;
#define ISM330DLC_FIFO_STATUS2 0x3BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t diff_fifo : 3; /* + FIFO_STATUS1(diff_fifo) */
uint8_t not_used_01 : 1;
@@ -942,18 +989,23 @@ typedef struct {
} ism330dlc_fifo_status2_t;
#define ISM330DLC_FIFO_STATUS3 0x3CU
-typedef struct {
- uint8_t fifo_pattern : 8; /* + FIFO_STATUS4(fifo_pattern) */
+typedef struct
+{
+uint8_t fifo_pattern :
+ 8; /* + FIFO_STATUS4(fifo_pattern) */
} ism330dlc_fifo_status3_t;
#define ISM330DLC_FIFO_STATUS4 0x3DU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t fifo_pattern : 2; /* + FIFO_STATUS3(fifo_pattern) */
+uint8_t fifo_pattern :
+ 2; /* + FIFO_STATUS3(fifo_pattern) */
uint8_t not_used_01 : 6;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used_01 : 6;
- uint8_t fifo_pattern : 2; /* + FIFO_STATUS3(fifo_pattern) */
+uint8_t fifo_pattern :
+ 2; /* + FIFO_STATUS3(fifo_pattern) */
#endif /* DRV_BYTE_ORDER */
} ism330dlc_fifo_status4_t;
@@ -964,7 +1016,8 @@ typedef struct {
#define ISM330DLC_TIMESTAMP2_REG 0x42
#define ISM330DLC_SENSORHUB13_REG 0x4DU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -987,7 +1040,8 @@ typedef struct {
} ism330dlc_sensorhub13_reg_t;
#define ISM330DLC_SENSORHUB14_REG 0x4EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -1010,7 +1064,8 @@ typedef struct {
} ism330dlc_sensorhub14_reg_t;
#define ISM330DLC_SENSORHUB15_REG 0x4FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -1033,7 +1088,8 @@ typedef struct {
} ism330dlc_sensorhub15_reg_t;
#define ISM330DLC_SENSORHUB16_REG 0x50U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -1056,7 +1112,8 @@ typedef struct {
} ism330dlc_sensorhub16_reg_t;
#define ISM330DLC_SENSORHUB17_REG 0x51U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -1079,7 +1136,8 @@ typedef struct {
} ism330dlc_sensorhub17_reg_t;
#define ISM330DLC_SENSORHUB18_REG 0x52U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -1102,7 +1160,8 @@ typedef struct {
} ism330dlc_sensorhub18_reg_t;
#define ISM330DLC_FUNC_SRC1 0x53U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sensorhub_end_op : 1;
uint8_t si_end_op : 1;
@@ -1121,7 +1180,8 @@ typedef struct {
} ism330dlc_func_src1_t;
#define ISM330DLC_FUNC_SRC2 0x54U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t slave0_nack : 1;
@@ -1140,7 +1200,8 @@ typedef struct {
} ism330dlc_func_src2_t;
#define ISM330DLC_TAP_CFG 0x58U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lir : 1;
uint8_t tap_z_en : 1;
@@ -1161,7 +1222,8 @@ typedef struct {
} ism330dlc_tap_cfg_t;
#define ISM330DLC_TAP_THS_6D 0x59U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_ths : 5;
uint8_t sixd_ths : 2;
@@ -1174,7 +1236,8 @@ typedef struct {
} ism330dlc_tap_ths_6d_t;
#define ISM330DLC_INT_DUR2 0x5AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shock : 2;
uint8_t quiet : 2;
@@ -1187,7 +1250,8 @@ typedef struct {
} ism330dlc_int_dur2_t;
#define ISM330DLC_WAKE_UP_THS 0x5BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wk_ths : 6;
uint8_t not_used_01 : 1;
@@ -1200,7 +1264,8 @@ typedef struct {
} ism330dlc_wake_up_ths_t;
#define ISM330DLC_WAKE_UP_DUR 0x5CU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sleep_dur : 4;
uint8_t timer_hr : 1;
@@ -1215,7 +1280,8 @@ typedef struct {
} ism330dlc_wake_up_dur_t;
#define ISM330DLC_FREE_FALL 0x5DU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ths : 3;
uint8_t ff_dur : 5;
@@ -1226,7 +1292,8 @@ typedef struct {
} ism330dlc_free_fall_t;
#define ISM330DLC_MD1_CFG 0x5EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_timer : 1;
uint8_t int1_tilt : 1;
@@ -1249,7 +1316,8 @@ typedef struct {
} ism330dlc_md1_cfg_t;
#define ISM330DLC_MD2_CFG 0x5FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_iron : 1;
uint8_t int2_tilt : 1;
@@ -1272,12 +1340,14 @@ typedef struct {
} ism330dlc_md2_cfg_t;
#define ISM330DLC_MASTER_CMD_CODE 0x60U
-typedef struct {
+typedef struct
+{
uint8_t master_cmd_code : 8;
} ism330dlc_master_cmd_code_t;
#define ISM330DLC_SENS_SYNC_SPI_ERROR_CODE 0x61U
-typedef struct {
+typedef struct
+{
uint8_t error_code : 8;
} ism330dlc_sens_sync_spi_error_code_t;
@@ -1288,7 +1358,8 @@ typedef struct {
#define ISM330DLC_OUT_MAG_RAW_Z_L 0x6AU
#define ISM330DLC_OUT_MAG_RAW_Z_H 0x6BU
#define ISM330DLC_INT_OIS 0x6FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 6;
uint8_t lvl2_ois : 1;
@@ -1301,7 +1372,8 @@ typedef struct {
} ism330dlc_int_ois_t;
#define ISM330DLC_CTRL1_OIS 0x70U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ois_en_spi2 : 1;
uint8_t fs_g_ois : 3; /* fs_g_ois + fs_125_ois */
@@ -1320,7 +1392,8 @@ typedef struct {
} ism330dlc_ctrl1_ois_t;
#define ISM330DLC_CTRL2_OIS 0x71U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t hp_en_ois : 1;
uint8_t ftype_ois : 2;
@@ -1337,7 +1410,8 @@ typedef struct {
} ism330dlc_ctrl2_ois_t;
#define ISM330DLC_CTRL3_OIS 0x72U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_ois_clampdis : 1;
uint8_t st_ois : 2;
@@ -1357,7 +1431,8 @@ typedef struct {
#define ISM330DLC_Y_OFS_USR 0x74U
#define ISM330DLC_Z_OFS_USR 0x75U
#define ISM330DLC_SLV0_ADD 0x02U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t rw_0 : 1;
uint8_t slave0_add : 7;
@@ -1368,12 +1443,14 @@ typedef struct {
} ism330dlc_slv0_add_t;
#define ISM330DLC_SLV0_SUBADD 0x03U
-typedef struct {
+typedef struct
+{
uint8_t slave0_reg : 8;
} ism330dlc_slv0_subadd_t;
#define ISM330DLC_SLAVE0_CONFIG 0x04U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave0_numop : 3;
uint8_t src_mode : 1;
@@ -1388,7 +1465,8 @@ typedef struct {
} ism330dlc_slave0_config_t;
#define ISM330DLC_SLV1_ADD 0x05U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_1 : 1;
uint8_t slave1_add : 7;
@@ -1399,12 +1477,14 @@ typedef struct {
} ism330dlc_slv1_add_t;
#define ISM330DLC_SLV1_SUBADD 0x06U
-typedef struct {
+typedef struct
+{
uint8_t slave1_reg : 8;
} ism330dlc_slv1_subadd_t;
#define ISM330DLC_SLAVE1_CONFIG 0x07U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave1_numop : 3;
uint8_t not_used_01 : 2;
@@ -1419,7 +1499,8 @@ typedef struct {
} ism330dlc_slave1_config_t;
#define ISM330DLC_SLV2_ADD 0x08U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_2 : 1;
uint8_t slave2_add : 7;
@@ -1430,12 +1511,14 @@ typedef struct {
} ism330dlc_slv2_add_t;
#define ISM330DLC_SLV2_SUBADD 0x09U
-typedef struct {
+typedef struct
+{
uint8_t slave2_reg : 8;
} ism330dlc_slv2_subadd_t;
#define ISM330DLC_SLAVE2_CONFIG 0x0AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave2_numop : 3;
uint8_t not_used_01 : 3;
@@ -1448,7 +1531,8 @@ typedef struct {
} ism330dlc_slave2_config_t;
#define ISM330DLC_SLV3_ADD 0x0BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_3 : 1;
uint8_t slave3_add : 7;
@@ -1459,12 +1543,14 @@ typedef struct {
} ism330dlc_slv3_add_t;
#define ISM330DLC_SLV3_SUBADD 0x0CU
-typedef struct {
+typedef struct
+{
uint8_t slave3_reg : 8;
} ism330dlc_slv3_subadd_t;
#define ISM330DLC_SLAVE3_CONFIG 0x0DU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave3_numop : 3;
uint8_t not_used_01 : 3;
@@ -1477,7 +1563,8 @@ typedef struct {
} ism330dlc_slave3_config_t;
#define ISM330DLC_DATAWRITE_SRC_MODE_SUB_SLV0 0x0EU
-typedef struct {
+typedef struct
+{
uint8_t slave_dataw : 8;
} ism330dlc_datawrite_src_mode_sub_slv0_t;
@@ -1499,9 +1586,9 @@ typedef struct {
/**
* @defgroup ISM330DLC_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -1509,7 +1596,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
ism330dlc_func_cfg_access_t func_cfg_access;
ism330dlc_sensor_sync_time_frame_t sensor_sync_time_frame;
ism330dlc_sensor_sync_res_ratio_t sensor_sync_res_ratio;
@@ -1587,7 +1675,8 @@ typedef union{
ism330dlc_slv3_add_t slv3_add;
ism330dlc_slv3_subadd_t slv3_subadd;
ism330dlc_slave3_config_t slave3_config;
- ism330dlc_datawrite_src_mode_sub_slv0_t datawrite_src_mode_sub_slv0;
+ ism330dlc_datawrite_src_mode_sub_slv0_t
+ datawrite_src_mode_sub_slv0;
bitwise_t bitwise;
uint8_t byte;
} ism330dlc_reg_t;
@@ -1597,10 +1686,12 @@ typedef union{
*
*/
-int32_t ism330dlc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
- uint16_t len);
-int32_t ism330dlc_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
- uint16_t len);
+int32_t ism330dlc_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len);
+int32_t ism330dlc_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len);
float_t ism330dlc_from_fs2g_to_mg(int16_t lsb);
float_t ism330dlc_from_fs4g_to_mg(int16_t lsb);
@@ -1615,17 +1706,21 @@ float_t ism330dlc_from_fs2000dps_to_mdps(int16_t lsb);
float_t ism330dlc_from_lsb_to_celsius(int16_t lsb);
-typedef enum {
+typedef enum
+{
ISM330DLC_2g = 0,
ISM330DLC_16g = 1,
ISM330DLC_4g = 2,
ISM330DLC_8g = 3,
ISM330DLC_XL_FS_ND = 4, /* ERROR CODE */
} ism330dlc_fs_xl_t;
-int32_t ism330dlc_xl_full_scale_set(stmdev_ctx_t *ctx, ism330dlc_fs_xl_t val);
-int32_t ism330dlc_xl_full_scale_get(stmdev_ctx_t *ctx, ism330dlc_fs_xl_t *val);
+int32_t ism330dlc_xl_full_scale_set(stmdev_ctx_t *ctx,
+ ism330dlc_fs_xl_t val);
+int32_t ism330dlc_xl_full_scale_get(stmdev_ctx_t *ctx,
+ ism330dlc_fs_xl_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_XL_ODR_OFF = 0,
ISM330DLC_XL_ODR_12Hz5 = 1,
ISM330DLC_XL_ODR_26Hz = 2,
@@ -1639,20 +1734,26 @@ typedef enum {
ISM330DLC_XL_ODR_6k66Hz = 10,
ISM330DLC_XL_ODR_1Hz6 = 11,
} ism330dlc_odr_xl_t;
-int32_t ism330dlc_xl_data_rate_set(stmdev_ctx_t *ctx, ism330dlc_odr_xl_t val);
-int32_t ism330dlc_xl_data_rate_get(stmdev_ctx_t *ctx, ism330dlc_odr_xl_t *val);
+int32_t ism330dlc_xl_data_rate_set(stmdev_ctx_t *ctx,
+ ism330dlc_odr_xl_t val);
+int32_t ism330dlc_xl_data_rate_get(stmdev_ctx_t *ctx,
+ ism330dlc_odr_xl_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_250dps = 0,
ISM330DLC_125dps = 1,
ISM330DLC_500dps = 2,
ISM330DLC_1000dps = 4,
ISM330DLC_2000dps = 6,
} ism330dlc_fs_g_t;
-int32_t ism330dlc_gy_full_scale_set(stmdev_ctx_t *ctx, ism330dlc_fs_g_t val);
-int32_t ism330dlc_gy_full_scale_get(stmdev_ctx_t *ctx, ism330dlc_fs_g_t *val);
+int32_t ism330dlc_gy_full_scale_set(stmdev_ctx_t *ctx,
+ ism330dlc_fs_g_t val);
+int32_t ism330dlc_gy_full_scale_get(stmdev_ctx_t *ctx,
+ ism330dlc_fs_g_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_GY_ODR_OFF = 0,
ISM330DLC_GY_ODR_12Hz5 = 1,
ISM330DLC_GY_ODR_26Hz = 2,
@@ -1665,49 +1766,58 @@ typedef enum {
ISM330DLC_GY_ODR_3k33Hz = 9,
ISM330DLC_GY_ODR_6k66Hz = 10,
} ism330dlc_odr_g_t;
-int32_t ism330dlc_gy_data_rate_set(stmdev_ctx_t *ctx, ism330dlc_odr_g_t val);
-int32_t ism330dlc_gy_data_rate_get(stmdev_ctx_t *ctx, ism330dlc_odr_g_t *val);
-
-int32_t ism330dlc_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dlc_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
-
-typedef enum {
+int32_t ism330dlc_gy_data_rate_set(stmdev_ctx_t *ctx,
+ ism330dlc_odr_g_t val);
+int32_t ism330dlc_gy_data_rate_get(stmdev_ctx_t *ctx,
+ ism330dlc_odr_g_t *val);
+
+int32_t ism330dlc_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dlc_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+typedef enum
+{
ISM330DLC_LSb_1mg = 0,
ISM330DLC_LSb_16mg = 1,
} ism330dlc_usr_off_w_t;
int32_t ism330dlc_xl_offset_weight_set(stmdev_ctx_t *ctx,
- ism330dlc_usr_off_w_t val);
+ ism330dlc_usr_off_w_t val);
int32_t ism330dlc_xl_offset_weight_get(stmdev_ctx_t *ctx,
- ism330dlc_usr_off_w_t *val);
+ ism330dlc_usr_off_w_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_XL_HIGH_PERFORMANCE = 0,
ISM330DLC_XL_NORMAL = 1,
} ism330dlc_xl_hm_mode_t;
int32_t ism330dlc_xl_power_mode_set(stmdev_ctx_t *ctx,
- ism330dlc_xl_hm_mode_t val);
+ ism330dlc_xl_hm_mode_t val);
int32_t ism330dlc_xl_power_mode_get(stmdev_ctx_t *ctx,
- ism330dlc_xl_hm_mode_t *val);
+ ism330dlc_xl_hm_mode_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_STAT_RND_DISABLE = 0,
ISM330DLC_STAT_RND_ENABLE = 1,
} ism330dlc_rounding_status_t;
int32_t ism330dlc_rounding_on_status_set(stmdev_ctx_t *ctx,
- ism330dlc_rounding_status_t val);
+ ism330dlc_rounding_status_t val);
int32_t ism330dlc_rounding_on_status_get(stmdev_ctx_t *ctx,
- ism330dlc_rounding_status_t *val);
+ ism330dlc_rounding_status_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_GY_HIGH_PERFORMANCE = 0,
ISM330DLC_GY_NORMAL = 1,
} ism330dlc_g_hm_mode_t;
int32_t ism330dlc_gy_power_mode_set(stmdev_ctx_t *ctx,
- ism330dlc_g_hm_mode_t val);
+ ism330dlc_g_hm_mode_t val);
int32_t ism330dlc_gy_power_mode_get(stmdev_ctx_t *ctx,
- ism330dlc_g_hm_mode_t *val);
+ ism330dlc_g_hm_mode_t *val);
-typedef struct {
+typedef struct
+{
ism330dlc_wake_up_src_t wake_up_src;
ism330dlc_tap_src_t tap_src;
ism330dlc_d6d_src_t d6d_src;
@@ -1716,29 +1826,37 @@ typedef struct {
ism330dlc_func_src2_t func_src2;
} ism330dlc_all_sources_t;
int32_t ism330dlc_all_sources_get(stmdev_ctx_t *ctx,
- ism330dlc_all_sources_t *val);
+ ism330dlc_all_sources_t *val);
-int32_t ism330dlc_status_reg_get(stmdev_ctx_t *ctx, ism330dlc_status_reg_t *val);
+int32_t ism330dlc_status_reg_get(stmdev_ctx_t *ctx,
+ ism330dlc_status_reg_t *val);
-int32_t ism330dlc_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dlc_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t ism330dlc_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dlc_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t ism330dlc_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dlc_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t ism330dlc_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t ism330dlc_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t ism330dlc_timestamp_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dlc_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_LSB_6ms4 = 0,
ISM330DLC_LSB_25us = 1,
} ism330dlc_timer_hr_t;
-int32_t ism330dlc_timestamp_res_set(stmdev_ctx_t *ctx, ism330dlc_timer_hr_t val);
-int32_t ism330dlc_timestamp_res_get(stmdev_ctx_t *ctx, ism330dlc_timer_hr_t *val);
+int32_t ism330dlc_timestamp_res_set(stmdev_ctx_t *ctx,
+ ism330dlc_timer_hr_t val);
+int32_t ism330dlc_timestamp_res_get(stmdev_ctx_t *ctx,
+ ism330dlc_timer_hr_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_ROUND_DISABLE = 0,
ISM330DLC_ROUND_XL = 1,
ISM330DLC_ROUND_GY = 2,
@@ -1748,46 +1866,60 @@ typedef enum {
ISM330DLC_ROUND_GY_XL_SH1_TO_SH12 = 6,
ISM330DLC_ROUND_GY_XL_SH1_TO_SH6 = 7,
} ism330dlc_rounding_t;
-int32_t ism330dlc_rounding_mode_set(stmdev_ctx_t *ctx, ism330dlc_rounding_t val);
-int32_t ism330dlc_rounding_mode_get(stmdev_ctx_t *ctx, ism330dlc_rounding_t *val);
+int32_t ism330dlc_rounding_mode_set(stmdev_ctx_t *ctx,
+ ism330dlc_rounding_t val);
+int32_t ism330dlc_rounding_mode_get(stmdev_ctx_t *ctx,
+ ism330dlc_rounding_t *val);
-int32_t ism330dlc_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t ism330dlc_temperature_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
-int32_t ism330dlc_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t ism330dlc_angular_rate_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
-int32_t ism330dlc_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t ism330dlc_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
-int32_t ism330dlc_mag_calibrated_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t ism330dlc_mag_calibrated_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
-int32_t ism330dlc_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer,
+int32_t ism330dlc_fifo_raw_data_get(stmdev_ctx_t *ctx,
+ uint8_t *buffer,
uint8_t len);
-typedef enum {
+typedef enum
+{
ISM330DLC_USER_BANK = 0,
ISM330DLC_BANK_A = 1,
} ism330dlc_func_cfg_en_t;
-int32_t ism330dlc_mem_bank_set(stmdev_ctx_t *ctx, ism330dlc_func_cfg_en_t val);
-int32_t ism330dlc_mem_bank_get(stmdev_ctx_t *ctx, ism330dlc_func_cfg_en_t *val);
+int32_t ism330dlc_mem_bank_set(stmdev_ctx_t *ctx,
+ ism330dlc_func_cfg_en_t val);
+int32_t ism330dlc_mem_bank_get(stmdev_ctx_t *ctx,
+ ism330dlc_func_cfg_en_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_DRDY_LATCHED = 0,
ISM330DLC_DRDY_PULSED = 1,
} ism330dlc_drdy_pulsed_t;
int32_t ism330dlc_data_ready_mode_set(stmdev_ctx_t *ctx,
- ism330dlc_drdy_pulsed_t val);
+ ism330dlc_drdy_pulsed_t val);
int32_t ism330dlc_data_ready_mode_get(stmdev_ctx_t *ctx,
- ism330dlc_drdy_pulsed_t *val);
+ ism330dlc_drdy_pulsed_t *val);
int32_t ism330dlc_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t ism330dlc_reset_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dlc_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_LSB_AT_LOW_ADD = 0,
ISM330DLC_MSB_AT_LOW_ADD = 1,
} ism330dlc_ble_t;
-int32_t ism330dlc_data_format_set(stmdev_ctx_t *ctx, ism330dlc_ble_t val);
-int32_t ism330dlc_data_format_get(stmdev_ctx_t *ctx, ism330dlc_ble_t *val);
+int32_t ism330dlc_data_format_set(stmdev_ctx_t *ctx,
+ ism330dlc_ble_t val);
+int32_t ism330dlc_data_format_get(stmdev_ctx_t *ctx,
+ ism330dlc_ble_t *val);
int32_t ism330dlc_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dlc_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1795,54 +1927,66 @@ int32_t ism330dlc_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t ism330dlc_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dlc_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_XL_ST_DISABLE = 0,
ISM330DLC_XL_ST_POSITIVE = 1,
ISM330DLC_XL_ST_NEGATIVE = 2,
} ism330dlc_st_xl_t;
-int32_t ism330dlc_xl_self_test_set(stmdev_ctx_t *ctx, ism330dlc_st_xl_t val);
-int32_t ism330dlc_xl_self_test_get(stmdev_ctx_t *ctx, ism330dlc_st_xl_t *val);
+int32_t ism330dlc_xl_self_test_set(stmdev_ctx_t *ctx,
+ ism330dlc_st_xl_t val);
+int32_t ism330dlc_xl_self_test_get(stmdev_ctx_t *ctx,
+ ism330dlc_st_xl_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_GY_ST_DISABLE = 0,
ISM330DLC_GY_ST_POSITIVE = 1,
ISM330DLC_GY_ST_NEGATIVE = 3,
} ism330dlc_st_g_t;
-int32_t ism330dlc_gy_self_test_set(stmdev_ctx_t *ctx, ism330dlc_st_g_t val);
-int32_t ism330dlc_gy_self_test_get(stmdev_ctx_t *ctx, ism330dlc_st_g_t *val);
-
-int32_t ism330dlc_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dlc_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dlc_gy_self_test_set(stmdev_ctx_t *ctx,
+ ism330dlc_st_g_t val);
+int32_t ism330dlc_gy_self_test_get(stmdev_ctx_t *ctx,
+ ism330dlc_st_g_t *val);
+
+int32_t ism330dlc_filter_settling_mask_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dlc_filter_settling_mask_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_USE_SLOPE = 0,
ISM330DLC_USE_HPF = 1,
} ism330dlc_slope_fds_t;
int32_t ism330dlc_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
- ism330dlc_slope_fds_t val);
+ ism330dlc_slope_fds_t val);
int32_t ism330dlc_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
- ism330dlc_slope_fds_t *val);
+ ism330dlc_slope_fds_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_XL_ANA_BW_1k5Hz = 0,
ISM330DLC_XL_ANA_BW_400Hz = 1,
} ism330dlc_bw0_xl_t;
int32_t ism330dlc_xl_filter_analog_set(stmdev_ctx_t *ctx,
- ism330dlc_bw0_xl_t val);
+ ism330dlc_bw0_xl_t val);
int32_t ism330dlc_xl_filter_analog_get(stmdev_ctx_t *ctx,
- ism330dlc_bw0_xl_t *val);
+ ism330dlc_bw0_xl_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_XL_LP1_ODR_DIV_2 = 0,
ISM330DLC_XL_LP1_ODR_DIV_4 = 1,
ISM330DLC_XL_LP1_NA = 2,
} ism330dlc_lpf1_bw_sel_t;
int32_t ism330dlc_xl_lp1_bandwidth_set(stmdev_ctx_t *ctx,
- ism330dlc_lpf1_bw_sel_t val);
+ ism330dlc_lpf1_bw_sel_t val);
int32_t ism330dlc_xl_lp1_bandwidth_get(stmdev_ctx_t *ctx,
- ism330dlc_lpf1_bw_sel_t *val);
+ ism330dlc_lpf1_bw_sel_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_XL_LOW_LAT_LP_ODR_DIV_50 = 0x00,
ISM330DLC_XL_LOW_LAT_LP_ODR_DIV_100 = 0x01,
ISM330DLC_XL_LOW_LAT_LP_ODR_DIV_9 = 0x02,
@@ -1854,14 +1998,17 @@ typedef enum {
ISM330DLC_XL_LP_NA = 0x14
} ism330dlc_input_composite_t;
int32_t ism330dlc_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx,
- ism330dlc_input_composite_t val);
+ ism330dlc_input_composite_t val);
int32_t ism330dlc_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx,
- ism330dlc_input_composite_t *val);
+ ism330dlc_input_composite_t *val);
-int32_t ism330dlc_xl_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dlc_xl_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dlc_xl_reference_mode_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dlc_xl_reference_mode_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_XL_HP_ODR_DIV_4 = 0x00, /* Slope filter */
ISM330DLC_XL_HP_ODR_DIV_100 = 0x01,
ISM330DLC_XL_HP_ODR_DIV_9 = 0x02,
@@ -1869,35 +2016,38 @@ typedef enum {
ISM330DLC_XL_HP_NA = 0x04,
} ism330dlc_hpcf_xl_t;
int32_t ism330dlc_xl_hp_bandwidth_set(stmdev_ctx_t *ctx,
- ism330dlc_hpcf_xl_t val);
+ ism330dlc_hpcf_xl_t val);
int32_t ism330dlc_xl_hp_bandwidth_get(stmdev_ctx_t *ctx,
- ism330dlc_hpcf_xl_t *val);
+ ism330dlc_hpcf_xl_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_XL_UI_LP1_ODR_DIV_2 = 0,
ISM330DLC_XL_UI_LP1_ODR_DIV_4 = 1,
ISM330DLC_XL_UI_LP1_NA = 2, /* ERROR CODE */
} ism330dlc_ui_lpf1_bw_sel_t;
int32_t ism330dlc_xl_ui_lp1_bandwidth_set(stmdev_ctx_t *ctx,
- ism330dlc_ui_lpf1_bw_sel_t val);
+ ism330dlc_ui_lpf1_bw_sel_t val);
int32_t ism330dlc_xl_ui_lp1_bandwidth_get(stmdev_ctx_t *ctx,
- ism330dlc_ui_lpf1_bw_sel_t *val);
+ ism330dlc_ui_lpf1_bw_sel_t *val);
int32_t ism330dlc_xl_ui_slope_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dlc_xl_ui_slope_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_AUX_LP_LIGHT = 2,
ISM330DLC_AUX_LP_NORMAL = 3,
ISM330DLC_AUX_LP_STRONG = 0,
ISM330DLC_AUX_LP_AGGRESSIVE = 1,
} ism330dlc_filter_xl_conf_ois_t;
int32_t ism330dlc_xl_aux_lp_bandwidth_set(stmdev_ctx_t *ctx,
- ism330dlc_filter_xl_conf_ois_t val);
+ ism330dlc_filter_xl_conf_ois_t val);
int32_t ism330dlc_xl_aux_lp_bandwidth_get(stmdev_ctx_t *ctx,
- ism330dlc_filter_xl_conf_ois_t *val);
+ ism330dlc_filter_xl_conf_ois_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_LP2_ONLY = 0x00,
ISM330DLC_HP_16mHz_LP2 = 0x80,
@@ -1916,14 +2066,16 @@ typedef enum {
ISM330DLC_HP_1Hz04_LP1_AGGRESSIVE = 0xBB,
} ism330dlc_lpf1_sel_g_t;
int32_t ism330dlc_gy_band_pass_set(stmdev_ctx_t *ctx,
- ism330dlc_lpf1_sel_g_t val);
+ ism330dlc_lpf1_sel_g_t val);
int32_t ism330dlc_gy_band_pass_get(stmdev_ctx_t *ctx,
- ism330dlc_lpf1_sel_g_t *val);
+ ism330dlc_lpf1_sel_g_t *val);
int32_t ism330dlc_gy_ui_high_pass_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dlc_gy_ui_high_pass_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dlc_gy_ui_high_pass_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_HP_DISABLE_LP_173Hz = 0x02,
ISM330DLC_HP_DISABLE_LP_237Hz = 0x01,
ISM330DLC_HP_DISABLE_LP_351Hz = 0x00,
@@ -1935,12 +2087,12 @@ typedef enum {
ISM330DLC_HP_1Hz04_LP_937Hz = 0xB3,
} ism330dlc_hp_en_ois_t;
int32_t ism330dlc_gy_aux_bandwidth_set(stmdev_ctx_t *ctx,
- ism330dlc_hp_en_ois_t val);
+ ism330dlc_hp_en_ois_t val);
int32_t ism330dlc_gy_aux_bandwidth_get(stmdev_ctx_t *ctx,
- ism330dlc_hp_en_ois_t *val);
+ ism330dlc_hp_en_ois_t *val);
int32_t ism330dlc_aux_status_reg_get(stmdev_ctx_t *ctx,
- ism330dlc_status_spiaux_t *val);
+ ism330dlc_status_spiaux_t *val);
int32_t ism330dlc_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
uint8_t *val);
@@ -1951,20 +2103,24 @@ int32_t ism330dlc_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
int32_t ism330dlc_aux_gy_flag_settling_get(stmdev_ctx_t *ctx,
uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_AUX_DEN_DISABLE = 0,
ISM330DLC_AUX_DEN_LEVEL_LATCH = 3,
ISM330DLC_AUX_DEN_LEVEL_TRIG = 2,
} ism330dlc_lvl_ois_t;
int32_t ism330dlc_aux_den_mode_set(stmdev_ctx_t *ctx,
- ism330dlc_lvl_ois_t val);
+ ism330dlc_lvl_ois_t val);
int32_t ism330dlc_aux_den_mode_get(stmdev_ctx_t *ctx,
- ism330dlc_lvl_ois_t *val);
+ ism330dlc_lvl_ois_t *val);
-int32_t ism330dlc_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dlc_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dlc_aux_drdy_on_int2_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dlc_aux_drdy_on_int2_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_AUX_DISABLE = 0,
ISM330DLC_MODE_3_GY = 1,
ISM330DLC_MODE_4_GY_XL = 3,
@@ -1974,7 +2130,8 @@ int32_t ism330dlc_aux_mode_set(stmdev_ctx_t *ctx,
int32_t ism330dlc_aux_mode_get(stmdev_ctx_t *ctx,
ism330dlc_ois_en_spi2_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_250dps_AUX = 0,
ISM330DLC_125dps_AUX = 1,
ISM330DLC_500dps_AUX = 2,
@@ -1982,11 +2139,12 @@ typedef enum {
ISM330DLC_2000dps_AUX = 6,
} ism330dlc_fs_g_ois_t;
int32_t ism330dlc_aux_gy_full_scale_set(stmdev_ctx_t *ctx,
- ism330dlc_fs_g_ois_t val);
+ ism330dlc_fs_g_ois_t val);
int32_t ism330dlc_aux_gy_full_scale_get(stmdev_ctx_t *ctx,
- ism330dlc_fs_g_ois_t *val);
+ ism330dlc_fs_g_ois_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_AUX_SPI_4_WIRE = 0,
ISM330DLC_AUX_SPI_3_WIRE = 1,
} ism330dlc_sim_ois_t;
@@ -1995,71 +2153,81 @@ int32_t ism330dlc_aux_spi_mode_set(stmdev_ctx_t *ctx,
int32_t ism330dlc_aux_spi_mode_get(stmdev_ctx_t *ctx,
ism330dlc_sim_ois_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_AUX_LSB_AT_LOW_ADD = 0,
ISM330DLC_AUX_MSB_AT_LOW_ADD = 1,
} ism330dlc_ble_ois_t;
int32_t ism330dlc_aux_data_format_set(stmdev_ctx_t *ctx,
- ism330dlc_ble_ois_t val);
+ ism330dlc_ble_ois_t val);
int32_t ism330dlc_aux_data_format_get(stmdev_ctx_t *ctx,
- ism330dlc_ble_ois_t *val);
+ ism330dlc_ble_ois_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_ENABLE_CLAMP = 0,
ISM330DLC_DISABLE_CLAMP = 1,
} ism330dlc_st_ois_clampdis_t;
int32_t ism330dlc_aux_gy_clamp_set(stmdev_ctx_t *ctx,
- ism330dlc_st_ois_clampdis_t val);
+ ism330dlc_st_ois_clampdis_t val);
int32_t ism330dlc_aux_gy_clamp_get(stmdev_ctx_t *ctx,
- ism330dlc_st_ois_clampdis_t *val);
+ ism330dlc_st_ois_clampdis_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_AUX_GY_DISABLE = 0,
ISM330DLC_AUX_GY_POS = 1,
ISM330DLC_AUX_GY_NEG = 3,
} ism330dlc_st_ois_t;
int32_t ism330dlc_aux_gy_self_test_set(stmdev_ctx_t *ctx,
- ism330dlc_st_ois_t val);
+ ism330dlc_st_ois_t val);
int32_t ism330dlc_aux_gy_self_test_get(stmdev_ctx_t *ctx,
- ism330dlc_st_ois_t *val);
+ ism330dlc_st_ois_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_AUX_2g = 0,
ISM330DLC_AUX_16g = 1,
ISM330DLC_AUX_4g = 2,
ISM330DLC_AUX_8g = 3,
} ism330dlc_fs_xl_ois_t;
int32_t ism330dlc_aux_xl_full_scale_set(stmdev_ctx_t *ctx,
- ism330dlc_fs_xl_ois_t val);
+ ism330dlc_fs_xl_ois_t val);
int32_t ism330dlc_aux_xl_full_scale_get(stmdev_ctx_t *ctx,
- ism330dlc_fs_xl_ois_t *val);
+ ism330dlc_fs_xl_ois_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_AUX_DEN_ACTIVE_LOW = 0,
ISM330DLC_AUX_DEN_ACTIVE_HIGH = 1,
} ism330dlc_den_lh_ois_t;
int32_t ism330dlc_aux_den_polarity_set(stmdev_ctx_t *ctx,
- ism330dlc_den_lh_ois_t val);
+ ism330dlc_den_lh_ois_t val);
int32_t ism330dlc_aux_den_polarity_get(stmdev_ctx_t *ctx,
- ism330dlc_den_lh_ois_t *val);
+ ism330dlc_den_lh_ois_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_SPI_4_WIRE = 0,
ISM330DLC_SPI_3_WIRE = 1,
} ism330dlc_sim_t;
-int32_t ism330dlc_spi_mode_set(stmdev_ctx_t *ctx, ism330dlc_sim_t val);
-int32_t ism330dlc_spi_mode_get(stmdev_ctx_t *ctx, ism330dlc_sim_t *val);
+int32_t ism330dlc_spi_mode_set(stmdev_ctx_t *ctx,
+ ism330dlc_sim_t val);
+int32_t ism330dlc_spi_mode_get(stmdev_ctx_t *ctx,
+ ism330dlc_sim_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_I2C_ENABLE = 0,
ISM330DLC_I2C_DISABLE = 1,
} ism330dlc_i2c_disable_t;
int32_t ism330dlc_i2c_interface_set(stmdev_ctx_t *ctx,
- ism330dlc_i2c_disable_t val);
+ ism330dlc_i2c_disable_t val);
int32_t ism330dlc_i2c_interface_get(stmdev_ctx_t *ctx,
- ism330dlc_i2c_disable_t *val);
+ ism330dlc_i2c_disable_t *val);
-typedef struct {
+typedef struct
+{
uint8_t int1_drdy_xl : 1;
uint8_t int1_drdy_g : 1;
uint8_t int1_boot : 1;
@@ -2077,11 +2245,12 @@ typedef struct {
uint8_t drdy_on_int1 : 1;
} ism330dlc_int1_route_t;
int32_t ism330dlc_pin_int1_route_set(stmdev_ctx_t *ctx,
- ism330dlc_int1_route_t val);
+ ism330dlc_int1_route_t val);
int32_t ism330dlc_pin_int1_route_get(stmdev_ctx_t *ctx,
- ism330dlc_int1_route_t *val);
+ ism330dlc_int1_route_t *val);
-typedef struct{
+typedef struct
+{
uint8_t int2_drdy_xl : 1;
uint8_t int2_drdy_g : 1;
uint8_t int2_drdy_temp : 1;
@@ -2098,33 +2267,42 @@ typedef struct{
uint8_t int2_inact_state : 1;
} ism330dlc_int2_route_t;
int32_t ism330dlc_pin_int2_route_set(stmdev_ctx_t *ctx,
- ism330dlc_int2_route_t val);
+ ism330dlc_int2_route_t val);
int32_t ism330dlc_pin_int2_route_get(stmdev_ctx_t *ctx,
- ism330dlc_int2_route_t *val);
+ ism330dlc_int2_route_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_PUSH_PULL = 0,
ISM330DLC_OPEN_DRAIN = 1,
} ism330dlc_pp_od_t;
-int32_t ism330dlc_pin_mode_set(stmdev_ctx_t *ctx, ism330dlc_pp_od_t val);
-int32_t ism330dlc_pin_mode_get(stmdev_ctx_t *ctx, ism330dlc_pp_od_t *val);
+int32_t ism330dlc_pin_mode_set(stmdev_ctx_t *ctx,
+ ism330dlc_pp_od_t val);
+int32_t ism330dlc_pin_mode_get(stmdev_ctx_t *ctx,
+ ism330dlc_pp_od_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_ACTIVE_HIGH = 0,
ISM330DLC_ACTIVE_LOW = 1,
} ism330dlc_h_lactive_t;
-int32_t ism330dlc_pin_polarity_set(stmdev_ctx_t *ctx, ism330dlc_h_lactive_t val);
-int32_t ism330dlc_pin_polarity_get(stmdev_ctx_t *ctx, ism330dlc_h_lactive_t *val);
+int32_t ism330dlc_pin_polarity_set(stmdev_ctx_t *ctx,
+ ism330dlc_h_lactive_t val);
+int32_t ism330dlc_pin_polarity_get(stmdev_ctx_t *ctx,
+ ism330dlc_h_lactive_t *val);
int32_t ism330dlc_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dlc_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_INT_PULSED = 0,
ISM330DLC_INT_LATCHED = 1,
} ism330dlc_lir_t;
-int32_t ism330dlc_int_notification_set(stmdev_ctx_t *ctx, ism330dlc_lir_t val);
-int32_t ism330dlc_int_notification_get(stmdev_ctx_t *ctx, ism330dlc_lir_t *val);
+int32_t ism330dlc_int_notification_set(stmdev_ctx_t *ctx,
+ ism330dlc_lir_t val);
+int32_t ism330dlc_int_notification_get(stmdev_ctx_t *ctx,
+ ism330dlc_lir_t *val);
int32_t ism330dlc_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dlc_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -2135,31 +2313,42 @@ int32_t ism330dlc_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t ism330dlc_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dlc_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_PROPERTY_DISABLE = 0,
ISM330DLC_XL_12Hz5_GY_NOT_AFFECTED = 1,
ISM330DLC_XL_12Hz5_GY_SLEEP = 2,
ISM330DLC_XL_12Hz5_GY_PD = 3,
} ism330dlc_inact_en_t;
-int32_t ism330dlc_act_mode_set(stmdev_ctx_t *ctx, ism330dlc_inact_en_t val);
-int32_t ism330dlc_act_mode_get(stmdev_ctx_t *ctx, ism330dlc_inact_en_t *val);
+int32_t ism330dlc_act_mode_set(stmdev_ctx_t *ctx,
+ ism330dlc_inact_en_t val);
+int32_t ism330dlc_act_mode_get(stmdev_ctx_t *ctx,
+ ism330dlc_inact_en_t *val);
int32_t ism330dlc_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dlc_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t ism330dlc_tap_src_get(stmdev_ctx_t *ctx, ism330dlc_tap_src_t *val);
+int32_t ism330dlc_tap_src_get(stmdev_ctx_t *ctx,
+ ism330dlc_tap_src_t *val);
-int32_t ism330dlc_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dlc_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dlc_tap_detection_on_z_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dlc_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t ism330dlc_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dlc_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dlc_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dlc_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t ism330dlc_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dlc_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dlc_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dlc_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t ism330dlc_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dlc_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dlc_tap_threshold_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t ism330dlc_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dlc_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -2170,32 +2359,37 @@ int32_t ism330dlc_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t ism330dlc_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dlc_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_ONLY_SINGLE = 0,
ISM330DLC_BOTH_SINGLE_DOUBLE = 1,
} ism330dlc_single_double_tap_t;
int32_t ism330dlc_tap_mode_set(stmdev_ctx_t *ctx,
- ism330dlc_single_double_tap_t val);
+ ism330dlc_single_double_tap_t val);
int32_t ism330dlc_tap_mode_get(stmdev_ctx_t *ctx,
- ism330dlc_single_double_tap_t *val);
+ ism330dlc_single_double_tap_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_ODR_DIV_2_FEED = 0,
ISM330DLC_LPF2_FEED = 1,
} ism330dlc_low_pass_on_6d_t;
int32_t ism330dlc_6d_feed_data_set(stmdev_ctx_t *ctx,
- ism330dlc_low_pass_on_6d_t val);
+ ism330dlc_low_pass_on_6d_t val);
int32_t ism330dlc_6d_feed_data_get(stmdev_ctx_t *ctx,
- ism330dlc_low_pass_on_6d_t *val);
+ ism330dlc_low_pass_on_6d_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_DEG_80 = 0,
ISM330DLC_DEG_70 = 1,
ISM330DLC_DEG_60 = 2,
ISM330DLC_DEG_50 = 3,
} ism330dlc_sixd_ths_t;
-int32_t ism330dlc_6d_threshold_set(stmdev_ctx_t *ctx, ism330dlc_sixd_ths_t val);
-int32_t ism330dlc_6d_threshold_get(stmdev_ctx_t *ctx, ism330dlc_sixd_ths_t *val);
+int32_t ism330dlc_6d_threshold_set(stmdev_ctx_t *ctx,
+ ism330dlc_sixd_ths_t val);
+int32_t ism330dlc_6d_threshold_get(stmdev_ctx_t *ctx,
+ ism330dlc_sixd_ths_t *val);
int32_t ism330dlc_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dlc_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -2203,7 +2397,8 @@ int32_t ism330dlc_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t ism330dlc_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dlc_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_FF_TSH_156mg = 0,
ISM330DLC_FF_TSH_219mg = 1,
ISM330DLC_FF_TSH_250mg = 2,
@@ -2213,31 +2408,38 @@ typedef enum {
ISM330DLC_FF_TSH_469mg = 6,
ISM330DLC_FF_TSH_500mg = 7,
} ism330dlc_ff_ths_t;
-int32_t ism330dlc_ff_threshold_set(stmdev_ctx_t *ctx, ism330dlc_ff_ths_t val);
-int32_t ism330dlc_ff_threshold_get(stmdev_ctx_t *ctx, ism330dlc_ff_ths_t *val);
+int32_t ism330dlc_ff_threshold_set(stmdev_ctx_t *ctx,
+ ism330dlc_ff_ths_t val);
+int32_t ism330dlc_ff_threshold_get(stmdev_ctx_t *ctx,
+ ism330dlc_ff_ths_t *val);
int32_t ism330dlc_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val);
-int32_t ism330dlc_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t ism330dlc_fifo_watermark_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
-int32_t ism330dlc_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t ism330dlc_fifo_data_level_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
int32_t ism330dlc_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t ism330dlc_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val);
int32_t ism330dlc_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dlc_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dlc_fifo_temp_batch_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_TRG_XL_GY_DRDY = 0,
ISM330DLC_TRG_SH_DRDY = 1,
} ism330dlc_trigger_fifo_t;
int32_t ism330dlc_fifo_write_trigger_set(stmdev_ctx_t *ctx,
- ism330dlc_trigger_fifo_t val);
+ ism330dlc_trigger_fifo_t val);
int32_t ism330dlc_fifo_write_trigger_get(stmdev_ctx_t *ctx,
- ism330dlc_trigger_fifo_t *val);
+ ism330dlc_trigger_fifo_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_FIFO_XL_DISABLE = 0,
ISM330DLC_FIFO_XL_NO_DEC = 1,
ISM330DLC_FIFO_XL_DEC_2 = 2,
@@ -2248,11 +2450,12 @@ typedef enum {
ISM330DLC_FIFO_XL_DEC_32 = 7,
} ism330dlc_dec_fifo_xl_t;
int32_t ism330dlc_fifo_xl_batch_set(stmdev_ctx_t *ctx,
- ism330dlc_dec_fifo_xl_t val);
+ ism330dlc_dec_fifo_xl_t val);
int32_t ism330dlc_fifo_xl_batch_get(stmdev_ctx_t *ctx,
- ism330dlc_dec_fifo_xl_t *val);
+ ism330dlc_dec_fifo_xl_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_FIFO_GY_DISABLE = 0,
ISM330DLC_FIFO_GY_NO_DEC = 1,
ISM330DLC_FIFO_GY_DEC_2 = 2,
@@ -2263,11 +2466,12 @@ typedef enum {
ISM330DLC_FIFO_GY_DEC_32 = 7,
} ism330dlc_dec_fifo_gyro_t;
int32_t ism330dlc_fifo_gy_batch_set(stmdev_ctx_t *ctx,
- ism330dlc_dec_fifo_gyro_t val);
+ ism330dlc_dec_fifo_gyro_t val);
int32_t ism330dlc_fifo_gy_batch_get(stmdev_ctx_t *ctx,
- ism330dlc_dec_fifo_gyro_t *val);
+ ism330dlc_dec_fifo_gyro_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_FIFO_DS3_DISABLE = 0,
ISM330DLC_FIFO_DS3_NO_DEC = 1,
ISM330DLC_FIFO_DS3_DEC_2 = 2,
@@ -2278,11 +2482,12 @@ typedef enum {
ISM330DLC_FIFO_DS3_DEC_32 = 7,
} ism330dlc_dec_ds3_fifo_t;
int32_t ism330dlc_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx,
- ism330dlc_dec_ds3_fifo_t val);
+ ism330dlc_dec_ds3_fifo_t val);
int32_t ism330dlc_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx,
- ism330dlc_dec_ds3_fifo_t *val);
+ ism330dlc_dec_ds3_fifo_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_FIFO_DS4_DISABLE = 0,
ISM330DLC_FIFO_DS4_NO_DEC = 1,
ISM330DLC_FIFO_DS4_DEC_2 = 2,
@@ -2293,27 +2498,35 @@ typedef enum {
ISM330DLC_FIFO_DS4_DEC_32 = 7,
} ism330dlc_dec_ds4_fifo_t;
int32_t ism330dlc_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx,
- ism330dlc_dec_ds4_fifo_t val);
+ ism330dlc_dec_ds4_fifo_t val);
int32_t ism330dlc_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx,
- ism330dlc_dec_ds4_fifo_t *val);
+ ism330dlc_dec_ds4_fifo_t *val);
-int32_t ism330dlc_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dlc_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dlc_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dlc_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t ism330dlc_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dlc_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dlc_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dlc_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_BYPASS_MODE = 0,
ISM330DLC_FIFO_MODE = 1,
ISM330DLC_STREAM_TO_FIFO_MODE = 3,
ISM330DLC_BYPASS_TO_STREAM_MODE = 4,
ISM330DLC_STREAM_MODE = 6,
} ism330dlc_fifo_mode_t;
-int32_t ism330dlc_fifo_mode_set(stmdev_ctx_t *ctx, ism330dlc_fifo_mode_t val);
-int32_t ism330dlc_fifo_mode_get(stmdev_ctx_t *ctx, ism330dlc_fifo_mode_t *val);
+int32_t ism330dlc_fifo_mode_set(stmdev_ctx_t *ctx,
+ ism330dlc_fifo_mode_t val);
+int32_t ism330dlc_fifo_mode_get(stmdev_ctx_t *ctx,
+ ism330dlc_fifo_mode_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_FIFO_DISABLE = 0,
ISM330DLC_FIFO_12Hz5 = 1,
ISM330DLC_FIFO_26Hz = 2,
@@ -2327,43 +2540,55 @@ typedef enum {
ISM330DLC_FIFO_6k66Hz = 10,
} ism330dlc_odr_fifo_t;
int32_t ism330dlc_fifo_data_rate_set(stmdev_ctx_t *ctx,
- ism330dlc_odr_fifo_t val);
+ ism330dlc_odr_fifo_t val);
int32_t ism330dlc_fifo_data_rate_get(stmdev_ctx_t *ctx,
- ism330dlc_odr_fifo_t *val);
+ ism330dlc_odr_fifo_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_DEN_ACT_LOW = 0,
ISM330DLC_DEN_ACT_HIGH = 1,
} ism330dlc_den_lh_t;
-int32_t ism330dlc_den_polarity_set(stmdev_ctx_t *ctx, ism330dlc_den_lh_t val);
-int32_t ism330dlc_den_polarity_get(stmdev_ctx_t *ctx, ism330dlc_den_lh_t *val);
+int32_t ism330dlc_den_polarity_set(stmdev_ctx_t *ctx,
+ ism330dlc_den_lh_t val);
+int32_t ism330dlc_den_polarity_get(stmdev_ctx_t *ctx,
+ ism330dlc_den_lh_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_DEN_DISABLE = 0,
ISM330DLC_LEVEL_FIFO = 6,
ISM330DLC_LEVEL_LETCHED = 3,
ISM330DLC_LEVEL_TRIGGER = 2,
ISM330DLC_EDGE_TRIGGER = 4,
} ism330dlc_den_mode_t;
-int32_t ism330dlc_den_mode_set(stmdev_ctx_t *ctx, ism330dlc_den_mode_t val);
-int32_t ism330dlc_den_mode_get(stmdev_ctx_t *ctx, ism330dlc_den_mode_t *val);
+int32_t ism330dlc_den_mode_set(stmdev_ctx_t *ctx,
+ ism330dlc_den_mode_t val);
+int32_t ism330dlc_den_mode_get(stmdev_ctx_t *ctx,
+ ism330dlc_den_mode_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_STAMP_IN_GY_DATA = 0,
ISM330DLC_STAMP_IN_XL_DATA = 1,
ISM330DLC_STAMP_IN_GY_XL_DATA = 2,
} ism330dlc_den_xl_en_t;
-int32_t ism330dlc_den_enable_set(stmdev_ctx_t *ctx, ism330dlc_den_xl_en_t val);
-int32_t ism330dlc_den_enable_get(stmdev_ctx_t *ctx, ism330dlc_den_xl_en_t *val);
+int32_t ism330dlc_den_enable_set(stmdev_ctx_t *ctx,
+ ism330dlc_den_xl_en_t val);
+int32_t ism330dlc_den_enable_get(stmdev_ctx_t *ctx,
+ ism330dlc_den_xl_en_t *val);
int32_t ism330dlc_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dlc_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dlc_den_mark_axis_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t ism330dlc_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dlc_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dlc_den_mark_axis_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t ism330dlc_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dlc_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dlc_den_mark_axis_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t ism330dlc_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dlc_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -2371,171 +2596,199 @@ int32_t ism330dlc_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t ism330dlc_mag_hard_iron_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dlc_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t ism330dlc_mag_soft_iron_mat_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t ism330dlc_mag_soft_iron_mat_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t ism330dlc_mag_soft_iron_mat_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t ism330dlc_mag_soft_iron_mat_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
int32_t ism330dlc_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val);
int32_t ism330dlc_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val);
-int32_t ism330dlc_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dlc_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dlc_sh_sync_sens_frame_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dlc_sh_sync_sens_frame_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_RES_RATIO_2_11 = 0,
ISM330DLC_RES_RATIO_2_12 = 1,
ISM330DLC_RES_RATIO_2_13 = 2,
ISM330DLC_RES_RATIO_2_14 = 3,
} ism330dlc_rr_t;
-int32_t ism330dlc_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx, ism330dlc_rr_t val);
-int32_t ism330dlc_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx, ism330dlc_rr_t *val);
+int32_t ism330dlc_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx,
+ ism330dlc_rr_t val);
+int32_t ism330dlc_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx,
+ ism330dlc_rr_t *val);
int32_t ism330dlc_sh_master_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t ism330dlc_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t ism330dlc_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dlc_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dlc_sh_pass_through_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_EXT_PULL_UP = 0,
ISM330DLC_INTERNAL_PULL_UP = 1,
} ism330dlc_pull_up_en_t;
-int32_t ism330dlc_sh_pin_mode_set(stmdev_ctx_t *ctx, ism330dlc_pull_up_en_t val);
-int32_t ism330dlc_sh_pin_mode_get(stmdev_ctx_t *ctx, ism330dlc_pull_up_en_t *val);
-
-typedef enum {
- ISM330DLC_XL_GY_DRDY = 0,
- ISM330DLC_EXT_ON_INT2_PIN = 1,
+int32_t ism330dlc_sh_pin_mode_set(stmdev_ctx_t *ctx,
+ ism330dlc_pull_up_en_t val);
+int32_t ism330dlc_sh_pin_mode_get(stmdev_ctx_t *ctx,
+ ism330dlc_pull_up_en_t *val);
+
+typedef enum
+{
+ ISM330DLC_XL_GY_DRDY = 1,
+ ISM330DLC_EXT_ON_INT2_PIN = 0,
} ism330dlc_start_config_t;
int32_t ism330dlc_sh_syncro_mode_set(stmdev_ctx_t *ctx,
- ism330dlc_start_config_t val);
+ ism330dlc_start_config_t val);
int32_t ism330dlc_sh_syncro_mode_get(stmdev_ctx_t *ctx,
- ism330dlc_start_config_t *val);
+ ism330dlc_start_config_t *val);
int32_t ism330dlc_sh_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dlc_sh_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
-
-typedef struct {
- ism330dlc_sensorhub1_reg_t sh_byte_1;
- ism330dlc_sensorhub2_reg_t sh_byte_2;
- ism330dlc_sensorhub3_reg_t sh_byte_3;
- ism330dlc_sensorhub4_reg_t sh_byte_4;
- ism330dlc_sensorhub5_reg_t sh_byte_5;
- ism330dlc_sensorhub6_reg_t sh_byte_6;
- ism330dlc_sensorhub7_reg_t sh_byte_7;
- ism330dlc_sensorhub8_reg_t sh_byte_8;
- ism330dlc_sensorhub9_reg_t sh_byte_9;
- ism330dlc_sensorhub10_reg_t sh_byte_10;
- ism330dlc_sensorhub11_reg_t sh_byte_11;
- ism330dlc_sensorhub12_reg_t sh_byte_12;
- ism330dlc_sensorhub13_reg_t sh_byte_13;
- ism330dlc_sensorhub14_reg_t sh_byte_14;
- ism330dlc_sensorhub15_reg_t sh_byte_15;
- ism330dlc_sensorhub16_reg_t sh_byte_16;
- ism330dlc_sensorhub17_reg_t sh_byte_17;
- ism330dlc_sensorhub18_reg_t sh_byte_18;
+int32_t ism330dlc_sh_drdy_on_int1_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+typedef struct
+{
+ ism330dlc_sensorhub1_reg_t sh_byte_1;
+ ism330dlc_sensorhub2_reg_t sh_byte_2;
+ ism330dlc_sensorhub3_reg_t sh_byte_3;
+ ism330dlc_sensorhub4_reg_t sh_byte_4;
+ ism330dlc_sensorhub5_reg_t sh_byte_5;
+ ism330dlc_sensorhub6_reg_t sh_byte_6;
+ ism330dlc_sensorhub7_reg_t sh_byte_7;
+ ism330dlc_sensorhub8_reg_t sh_byte_8;
+ ism330dlc_sensorhub9_reg_t sh_byte_9;
+ ism330dlc_sensorhub10_reg_t sh_byte_10;
+ ism330dlc_sensorhub11_reg_t sh_byte_11;
+ ism330dlc_sensorhub12_reg_t sh_byte_12;
+ ism330dlc_sensorhub13_reg_t sh_byte_13;
+ ism330dlc_sensorhub14_reg_t sh_byte_14;
+ ism330dlc_sensorhub15_reg_t sh_byte_15;
+ ism330dlc_sensorhub16_reg_t sh_byte_16;
+ ism330dlc_sensorhub17_reg_t sh_byte_17;
+ ism330dlc_sensorhub18_reg_t sh_byte_18;
} ism330dlc_emb_sh_read_t;
int32_t ism330dlc_sh_read_data_raw_get(stmdev_ctx_t *ctx,
- ism330dlc_emb_sh_read_t *val);
+ ism330dlc_emb_sh_read_t *val);
-int32_t ism330dlc_sh_cmd_sens_sync_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dlc_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dlc_sh_cmd_sens_sync_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dlc_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t ism330dlc_sh_spi_sync_error_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t ism330dlc_sh_spi_sync_error_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t ism330dlc_sh_spi_sync_error_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t ism330dlc_sh_spi_sync_error_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_NORMAL_MODE_READ = 0,
ISM330DLC_SRC_MODE_READ = 1,
} ism330dlc_src_mode_t;
int32_t ism330dlc_sh_cfg_slave_0_rd_mode_set(stmdev_ctx_t *ctx,
- ism330dlc_src_mode_t val);
+ ism330dlc_src_mode_t val);
int32_t ism330dlc_sh_cfg_slave_0_rd_mode_get(stmdev_ctx_t *ctx,
- ism330dlc_src_mode_t *val);
+ ism330dlc_src_mode_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_SLV_0 = 0,
ISM330DLC_SLV_0_1 = 1,
ISM330DLC_SLV_0_1_2 = 2,
ISM330DLC_SLV_0_1_2_3 = 3,
} ism330dlc_aux_sens_on_t;
int32_t ism330dlc_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx,
- ism330dlc_aux_sens_on_t val);
+ ism330dlc_aux_sens_on_t val);
int32_t ism330dlc_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx,
- ism330dlc_aux_sens_on_t *val);
+ ism330dlc_aux_sens_on_t *val);
-typedef struct{
+typedef struct
+{
uint8_t slv0_add;
uint8_t slv0_subadd;
uint8_t slv0_data;
} ism330dlc_sh_cfg_write_t;
-int32_t ism330dlc_sh_cfg_write(stmdev_ctx_t *ctx, ism330dlc_sh_cfg_write_t *val);
+int32_t ism330dlc_sh_cfg_write(stmdev_ctx_t *ctx,
+ ism330dlc_sh_cfg_write_t *val);
-typedef struct{
+typedef struct
+{
uint8_t slv_add;
uint8_t slv_subadd;
uint8_t slv_len;
} ism330dlc_sh_cfg_read_t;
int32_t ism330dlc_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
- ism330dlc_sh_cfg_read_t *val);
+ ism330dlc_sh_cfg_read_t *val);
int32_t ism330dlc_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
- ism330dlc_sh_cfg_read_t *val);
+ ism330dlc_sh_cfg_read_t *val);
int32_t ism330dlc_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
- ism330dlc_sh_cfg_read_t *val);
+ ism330dlc_sh_cfg_read_t *val);
int32_t ism330dlc_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
- ism330dlc_sh_cfg_read_t *val);
+ ism330dlc_sh_cfg_read_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_SL0_NO_DEC = 0,
ISM330DLC_SL0_DEC_2 = 1,
ISM330DLC_SL0_DEC_4 = 2,
ISM330DLC_SL0_DEC_8 = 3,
} ism330dlc_slave0_rate_t;
int32_t ism330dlc_sh_slave_0_dec_set(stmdev_ctx_t *ctx,
- ism330dlc_slave0_rate_t val);
+ ism330dlc_slave0_rate_t val);
int32_t ism330dlc_sh_slave_0_dec_get(stmdev_ctx_t *ctx,
- ism330dlc_slave0_rate_t *val);
+ ism330dlc_slave0_rate_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_EACH_SH_CYCLE = 0,
ISM330DLC_ONLY_FIRST_CYCLE = 1,
} ism330dlc_write_once_t;
int32_t ism330dlc_sh_write_mode_set(stmdev_ctx_t *ctx,
- ism330dlc_write_once_t val);
+ ism330dlc_write_once_t val);
int32_t ism330dlc_sh_write_mode_get(stmdev_ctx_t *ctx,
- ism330dlc_write_once_t *val);
+ ism330dlc_write_once_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_SL1_NO_DEC = 0,
ISM330DLC_SL1_DEC_2 = 1,
ISM330DLC_SL1_DEC_4 = 2,
ISM330DLC_SL1_DEC_8 = 3,
} ism330dlc_slave1_rate_t;
int32_t ism330dlc_sh_slave_1_dec_set(stmdev_ctx_t *ctx,
- ism330dlc_slave1_rate_t val);
+ ism330dlc_slave1_rate_t val);
int32_t ism330dlc_sh_slave_1_dec_get(stmdev_ctx_t *ctx,
- ism330dlc_slave1_rate_t *val);
+ ism330dlc_slave1_rate_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_SL2_NO_DEC = 0,
ISM330DLC_SL2_DEC_2 = 1,
ISM330DLC_SL2_DEC_4 = 2,
ISM330DLC_SL2_DEC_8 = 3,
} ism330dlc_slave2_rate_t;
int32_t ism330dlc_sh_slave_2_dec_set(stmdev_ctx_t *ctx,
- ism330dlc_slave2_rate_t val);
+ ism330dlc_slave2_rate_t val);
int32_t ism330dlc_sh_slave_2_dec_get(stmdev_ctx_t *ctx,
- ism330dlc_slave2_rate_t *val);
+ ism330dlc_slave2_rate_t *val);
-typedef enum {
+typedef enum
+{
ISM330DLC_SL3_NO_DEC = 0,
ISM330DLC_SL3_DEC_2 = 1,
ISM330DLC_SL3_DEC_4 = 2,
ISM330DLC_SL3_DEC_8 = 3,
} ism330dlc_slave3_rate_t;
int32_t ism330dlc_sh_slave_3_dec_set(stmdev_ctx_t *ctx,
- ism330dlc_slave3_rate_t val);
+ ism330dlc_slave3_rate_t val);
int32_t ism330dlc_sh_slave_3_dec_get(stmdev_ctx_t *ctx,
- ism330dlc_slave3_rate_t *val);
+ ism330dlc_slave3_rate_t *val);
/**
* @}
diff --git a/sensor/stmemsc/l20g20is_STdC/driver/l20g20is_reg.c b/sensor/stmemsc/l20g20is_STdC/driver/l20g20is_reg.c
index 51551a6fc6071497deb3b6de5ed325e16e80ecf4..8a3d75f3a2cf2e7c49e2007e7f171d08fd5da67a 100644
--- a/sensor/stmemsc/l20g20is_STdC/driver/l20g20is_reg.c
+++ b/sensor/stmemsc/l20g20is_STdC/driver/l20g20is_reg.c
@@ -1,21 +1,22 @@
-/*
- ******************************************************************************
- * @file l20g20is_reg.c
- * @author Sensors Software Solution Team
- * @brief L20G20IS driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file l20g20is_reg.c
+ * @author Sensors Software Solution Team
+ * @brief L20G20IS driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
#include "l20g20is_reg.h"
/**
@@ -45,11 +46,13 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t l20g20is_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t l20g20is_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -63,11 +66,13 @@ int32_t l20g20is_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t l20g20is_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t l20g20is_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -85,17 +90,17 @@ int32_t l20g20is_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
float_t l20g20is_from_fs100dps_to_mdps(int16_t lsb)
{
- return (((float_t)lsb *1000.0f)/262.0f);
+ return (((float_t)lsb * 1000.0f) / 262.0f);
}
float_t l20g20is_from_fs200dps_to_mdps(int16_t lsb)
{
- return (((float_t)lsb *1000.0f)/131.0f);
+ return (((float_t)lsb * 1000.0f) / 131.0f);
}
float_t l20g20is_from_lsb_to_celsius(int16_t lsb)
{
- return (((float_t)lsb *0.0625f)+25.0f);
+ return (((float_t)lsb * 0.0625f) + 25.0f);
}
/**
@@ -119,13 +124,13 @@ float_t l20g20is_from_lsb_to_celsius(int16_t lsb)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t l20g20is_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t l20g20is_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
l20g20is_data_status_ois_t data_status_ois;
int32_t ret;
-
ret = l20g20is_read_reg(ctx, L20G20IS_DATA_STATUS_OIS,
- (uint8_t*)&data_status_ois, 1);
+ (uint8_t *)&data_status_ois, 1);
*val = data_status_ois.xyda_ois;
return ret;
@@ -144,13 +149,16 @@ int32_t l20g20is_gy_data_rate_set(stmdev_ctx_t *ctx,
{
l20g20is_ctrl1_ois_t ctrl1_ois;
int32_t ret;
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS,
+ (uint8_t *)&ctrl1_ois, 1);
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl1_ois.pw = (uint8_t)val;
ret = l20g20is_write_reg(ctx, L20G20IS_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
}
+
return ret;
}
@@ -167,22 +175,28 @@ int32_t l20g20is_gy_data_rate_get(stmdev_ctx_t *ctx,
{
l20g20is_ctrl1_ois_t ctrl1_ois;
int32_t ret;
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS,
+ (uint8_t *)&ctrl1_ois, 1);
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
- switch (ctrl1_ois.pw){
+ switch (ctrl1_ois.pw)
+ {
case L20G20IS_GY_OFF:
*val = L20G20IS_GY_OFF;
break;
+
case L20G20IS_GY_SLEEP:
*val = L20G20IS_GY_SLEEP;
break;
+
case L20G20IS_GY_9k33Hz:
*val = L20G20IS_GY_9k33Hz;
break;
+
default:
*val = L20G20IS_GY_OFF;
break;
}
+
return ret;
}
@@ -202,19 +216,28 @@ int32_t l20g20is_gy_orient_set(stmdev_ctx_t *ctx,
l20g20is_ctrl1_ois_t ctrl1_ois;
l20g20is_ctrl2_ois_t ctrl2_ois;
int32_t ret;
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS,
+ (uint8_t *)&ctrl1_ois, 1);
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
- if(ret == 0) {
+ if (ret == 0)
+ {
ctrl1_ois.orient = val.orient;
- ret = l20g20is_write_reg(ctx, L20G20IS_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
+ ret = l20g20is_write_reg(ctx, L20G20IS_CTRL1_OIS,
+ (uint8_t *)&ctrl1_ois, 1);
}
- if(ret == 0) {
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL2_OIS, (uint8_t*)&ctrl2_ois, 1);
+
+ if (ret == 0)
+ {
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL2_OIS,
+ (uint8_t *)&ctrl2_ois, 1);
}
- if(ret == 0) {
+
+ if (ret == 0)
+ {
ctrl2_ois.signx = val.signx;
ctrl2_ois.signy = val.signy;
- ret = l20g20is_write_reg(ctx, L20G20IS_CTRL2_OIS, (uint8_t*)&ctrl2_ois, 1);
+ ret = l20g20is_write_reg(ctx, L20G20IS_CTRL2_OIS,
+ (uint8_t *)&ctrl2_ois, 1);
}
return ret;
@@ -231,19 +254,23 @@ int32_t l20g20is_gy_orient_set(stmdev_ctx_t *ctx,
*
*/
int32_t l20g20is_gy_orient_get(stmdev_ctx_t *ctx,
- l20g20is_gy_orient_t *val)
+ l20g20is_gy_orient_t *val)
{
l20g20is_ctrl1_ois_t ctrl1_ois;
l20g20is_ctrl2_ois_t ctrl2_ois;
int32_t ret;
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS,
+ (uint8_t *)&ctrl1_ois, 1);
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
- if(ret == 0) {
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL2_OIS, (uint8_t*)&ctrl2_ois, 1);
+ if (ret == 0)
+ {
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL2_OIS,
+ (uint8_t *)&ctrl2_ois, 1);
val->orient = ctrl1_ois.orient;
val->signy = ctrl2_ois.signy;
val->signy = ctrl2_ois.signy;
}
+
return ret;
}
@@ -259,13 +286,16 @@ int32_t l20g20is_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
{
l20g20is_ctrl1_ois_t ctrl1_ois;
int32_t ret;
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS,
+ (uint8_t *)&ctrl1_ois, 1);
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl1_ois.odu = (uint8_t)val;
ret = l20g20is_write_reg(ctx, L20G20IS_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
}
+
return ret;
}
@@ -277,12 +307,13 @@ int32_t l20g20is_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t l20g20is_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t l20g20is_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
l20g20is_ctrl1_ois_t ctrl1_ois;
int32_t ret;
-
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS,
+ (uint8_t *)&ctrl1_ois, 1);
*val = (uint8_t)ctrl1_ois.odu;
return ret;
@@ -303,18 +334,23 @@ int32_t l20g20is_angular_rate_offset_set(stmdev_ctx_t *ctx,
l20g20is_off_x_t off_x;
l20g20is_off_y_t off_y;
int32_t ret;
+ ret = l20g20is_read_reg(ctx, L20G20IS_OFF_X, (uint8_t *)&off_x, 1);
- ret = l20g20is_read_reg(ctx, L20G20IS_OFF_X, (uint8_t*)&off_x, 1);
- if(ret == 0) {
+ if (ret == 0)
+ {
off_x.offx = val.offx;
- ret = l20g20is_write_reg(ctx, L20G20IS_OFF_X, (uint8_t*)&off_x, 1);
+ ret = l20g20is_write_reg(ctx, L20G20IS_OFF_X, (uint8_t *)&off_x, 1);
}
- if(ret == 0) {
- ret = l20g20is_read_reg(ctx, L20G20IS_OFF_Y, (uint8_t*)&off_y, 1);
+
+ if (ret == 0)
+ {
+ ret = l20g20is_read_reg(ctx, L20G20IS_OFF_Y, (uint8_t *)&off_y, 1);
}
- if(ret == 0) {
+
+ if (ret == 0)
+ {
off_y.offy = val.offy;
- ret = l20g20is_write_reg(ctx, L20G20IS_OFF_Y, (uint8_t*)&off_y, 1);
+ ret = l20g20is_write_reg(ctx, L20G20IS_OFF_Y, (uint8_t *)&off_y, 1);
}
return ret;
@@ -330,20 +366,20 @@ int32_t l20g20is_angular_rate_offset_set(stmdev_ctx_t *ctx,
*
*/
int32_t l20g20is_angular_rate_offset_get(stmdev_ctx_t *ctx,
- l20g20is_off_t *val)
+ l20g20is_off_t *val)
{
l20g20is_off_x_t off_x;
l20g20is_off_y_t off_y;
int32_t ret;
+ ret = l20g20is_read_reg(ctx, L20G20IS_OFF_X, (uint8_t *)&off_x, 1);
- ret = l20g20is_read_reg(ctx, L20G20IS_OFF_X, (uint8_t*)&off_x, 1);
- if(ret == 0) {
- ret = l20g20is_read_reg(ctx, L20G20IS_OFF_Y, (uint8_t*)&off_y, 1);
+ if (ret == 0)
+ {
+ ret = l20g20is_read_reg(ctx, L20G20IS_OFF_Y, (uint8_t *)&off_y, 1);
val->offx = off_x.offx;
val->offy = off_y.offy;
}
-
return ret;
}
@@ -360,14 +396,16 @@ int32_t l20g20is_gy_full_scale_set(stmdev_ctx_t *ctx,
{
l20g20is_ois_cfg_reg_t ois_cfg_reg;
int32_t ret;
-
ret = l20g20is_read_reg(ctx, L20G20IS_OIS_CFG_REG,
- (uint8_t*)&ois_cfg_reg, 1);
- if(ret == 0){
+ (uint8_t *)&ois_cfg_reg, 1);
+
+ if (ret == 0)
+ {
ois_cfg_reg.fs_sel = (uint8_t)val;
ret = l20g20is_write_reg(ctx, L20G20IS_OIS_CFG_REG,
- (uint8_t*)&ois_cfg_reg, 1);
+ (uint8_t *)&ois_cfg_reg, 1);
}
+
return ret;
}
@@ -384,20 +422,24 @@ int32_t l20g20is_gy_full_scale_get(stmdev_ctx_t *ctx,
{
l20g20is_ois_cfg_reg_t ois_cfg_reg;
int32_t ret;
-
ret = l20g20is_read_reg(ctx, L20G20IS_OIS_CFG_REG,
- (uint8_t*)&ois_cfg_reg, 1);
- switch (ois_cfg_reg.fs_sel){
+ (uint8_t *)&ois_cfg_reg, 1);
+
+ switch (ois_cfg_reg.fs_sel)
+ {
case L20G20IS_100dps:
*val = L20G20IS_100dps;
break;
+
case L20G20IS_200dps:
*val = L20G20IS_200dps;
break;
+
default:
*val = L20G20IS_100dps;
break;
}
+
return ret;
}
@@ -426,10 +468,9 @@ int32_t l20g20is_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
uint8_t buff[2];
int32_t ret;
-
ret = l20g20is_read_reg(ctx, L20G20IS_TEMP_OUT_L, buff, 2);
*val = (int16_t)buff[1];
- *val = (*val * 256) + (int16_t)buff[0];
+ *val = (*val * 256) + (int16_t)buff[0];
return ret;
}
@@ -447,12 +488,11 @@ int32_t l20g20is_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
uint8_t buff[4];
int32_t ret;
-
ret = l20g20is_read_reg(ctx, L20G20IS_OUT_X_L, buff, 4);
val[0] = (int16_t)buff[1];
- val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
- val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
return ret;
}
@@ -464,7 +504,7 @@ int32_t l20g20is_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
/**
* @defgroup L20G20IS_Common
- * @brief This section groups common usefull functions.
+ * @brief This section groups common useful functions.
* @{
*
*/
@@ -481,6 +521,7 @@ int32_t l20g20is_dev_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
ret = l20g20is_read_reg(ctx, L20G20IS_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -497,9 +538,8 @@ int32_t l20g20is_dev_status_get(stmdev_ctx_t *ctx,
{
l20g20is_data_status_ois_t data_status_ois;
int32_t ret;
-
ret = l20g20is_read_reg(ctx, L20G20IS_DATA_STATUS_OIS,
- (uint8_t*)&data_status_ois, 1);
+ (uint8_t *)&data_status_ois, 1);
val->xyda_ois = data_status_ois.xyda_ois;
return ret;
@@ -518,13 +558,16 @@ int32_t l20g20is_dev_data_format_set(stmdev_ctx_t *ctx,
{
l20g20is_ctrl1_ois_t ctrl1_ois;
int32_t ret;
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS,
+ (uint8_t *)&ctrl1_ois, 1);
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl1_ois.ble = (uint8_t)val;
ret = l20g20is_write_reg(ctx, L20G20IS_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
}
+
return ret;
}
@@ -541,19 +584,24 @@ int32_t l20g20is_dev_data_format_get(stmdev_ctx_t *ctx,
{
l20g20is_ctrl1_ois_t ctrl1_ois;
int32_t ret;
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS,
+ (uint8_t *)&ctrl1_ois, 1);
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
- switch (ctrl1_ois.ble){
+ switch (ctrl1_ois.ble)
+ {
case L20G20IS_LSB_LOW_ADDRESS:
*val = L20G20IS_LSB_LOW_ADDRESS;
break;
+
case L20G20IS_MSB_LOW_ADDRESS:
*val = L20G20IS_MSB_LOW_ADDRESS;
break;
+
default:
*val = L20G20IS_LSB_LOW_ADDRESS;
break;
}
+
return ret;
}
@@ -569,12 +617,16 @@ int32_t l20g20is_dev_boot_set(stmdev_ctx_t *ctx, uint8_t val)
{
l20g20is_ctrl1_ois_t ctrl1_ois;
int32_t ret;
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS,
+ (uint8_t *)&ctrl1_ois, 1);
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl1_ois.boot = (uint8_t)val;
- ret = l20g20is_write_reg(ctx, L20G20IS_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
+ ret = l20g20is_write_reg(ctx, L20G20IS_CTRL1_OIS,
+ (uint8_t *)&ctrl1_ois, 1);
}
+
return ret;
}
@@ -590,8 +642,8 @@ int32_t l20g20is_dev_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
{
l20g20is_ctrl1_ois_t ctrl1_ois;
int32_t ret;
-
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS,
+ (uint8_t *)&ctrl1_ois, 1);
*val = (uint8_t)ctrl1_ois.boot;
return ret;
@@ -609,12 +661,16 @@ int32_t l20g20is_dev_reset_set(stmdev_ctx_t *ctx, uint8_t val)
{
l20g20is_ctrl2_ois_t ctrl2_ois;
int32_t ret;
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL2_OIS,
+ (uint8_t *)&ctrl2_ois, 1);
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL2_OIS, (uint8_t*)&ctrl2_ois, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl2_ois.sw_rst = (uint8_t)val;
- ret = l20g20is_write_reg(ctx, L20G20IS_CTRL2_OIS, (uint8_t*)&ctrl2_ois, 1);
+ ret = l20g20is_write_reg(ctx, L20G20IS_CTRL2_OIS,
+ (uint8_t *)&ctrl2_ois, 1);
}
+
return ret;
}
@@ -631,8 +687,8 @@ int32_t l20g20is_dev_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
{
l20g20is_ctrl2_ois_t ctrl2_ois;
int32_t ret;
-
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL2_OIS, (uint8_t*)&ctrl2_ois, 1);
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL2_OIS,
+ (uint8_t *)&ctrl2_ois, 1);
*val = (uint8_t)ctrl2_ois.sw_rst;
return ret;
@@ -665,21 +721,27 @@ int32_t l20g20is_gy_filter_hp_bandwidth_set(stmdev_ctx_t *ctx,
l20g20is_ctrl2_ois_t ctrl2_ois;
l20g20is_ois_cfg_reg_t ois_cfg_reg;
int32_t ret;
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL2_OIS,
+ (uint8_t *)&ctrl2_ois, 1);
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL2_OIS, (uint8_t*)&ctrl2_ois, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl2_ois.hpf = ((uint8_t)val & 0x80U) >> 4;
ret = l20g20is_write_reg(ctx, L20G20IS_CTRL2_OIS,
- (uint8_t*)&ctrl2_ois, 1);
+ (uint8_t *)&ctrl2_ois, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = l20g20is_read_reg(ctx, L20G20IS_OIS_CFG_REG,
- (uint8_t*)&ois_cfg_reg, 1);
+ (uint8_t *)&ois_cfg_reg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ois_cfg_reg.hpf_bw = (uint8_t)val & 0x03U;
ret = l20g20is_write_reg(ctx, L20G20IS_OIS_CFG_REG,
- (uint8_t*)&ois_cfg_reg, 1);
+ (uint8_t *)&ois_cfg_reg, 1);
}
return ret;
@@ -699,33 +761,42 @@ int32_t l20g20is_gy_filter_hp_bandwidth_get(stmdev_ctx_t *ctx,
l20g20is_ctrl2_ois_t ctrl2_ois;
l20g20is_ois_cfg_reg_t ois_cfg_reg;
int32_t ret;
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL2_OIS,
+ (uint8_t *)&ctrl2_ois, 1);
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL2_OIS, (uint8_t*)&ctrl2_ois, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = l20g20is_read_reg(ctx, L20G20IS_OIS_CFG_REG,
- (uint8_t*)&ois_cfg_reg, 1);
+ (uint8_t *)&ois_cfg_reg, 1);
- switch ( ( ctrl2_ois.hpf << 4 ) + ois_cfg_reg.hpf_bw){
+ switch ((ctrl2_ois.hpf << 4) + ois_cfg_reg.hpf_bw)
+ {
case L20G20IS_HPF_BYPASS:
*val = L20G20IS_HPF_BYPASS;
break;
+
case L20G20IS_HPF_BW_23mHz:
*val = L20G20IS_HPF_BW_23mHz;
break;
+
case L20G20IS_HPF_BW_91mHz:
*val = L20G20IS_HPF_BW_91mHz;
break;
+
case L20G20IS_HPF_BW_324mHz:
*val = L20G20IS_HPF_BW_324mHz;
break;
+
case L20G20IS_HPF_BW_1Hz457:
*val = L20G20IS_HPF_BW_1Hz457;
break;
+
default:
*val = L20G20IS_HPF_BYPASS;
break;
}
}
+
return ret;
}
@@ -737,16 +808,21 @@ int32_t l20g20is_gy_filter_hp_bandwidth_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t l20g20is_gy_filter_hp_reset_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t l20g20is_gy_filter_hp_reset_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
l20g20is_ctrl2_ois_t ctrl2_ois;
int32_t ret;
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL2_OIS,
+ (uint8_t *)&ctrl2_ois, 1);
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL2_OIS, (uint8_t*)&ctrl2_ois, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl2_ois.hp_rst = (uint8_t)val;
- ret = l20g20is_write_reg(ctx, L20G20IS_CTRL2_OIS, (uint8_t*)&ctrl2_ois, 1);
+ ret = l20g20is_write_reg(ctx, L20G20IS_CTRL2_OIS,
+ (uint8_t *)&ctrl2_ois, 1);
}
+
return ret;
}
@@ -758,12 +834,13 @@ int32_t l20g20is_gy_filter_hp_reset_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t l20g20is_gy_filter_hp_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t l20g20is_gy_filter_hp_reset_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
l20g20is_ctrl2_ois_t ctrl2_ois;
int32_t ret;
-
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL2_OIS, (uint8_t*)&ctrl2_ois, 1);
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL2_OIS,
+ (uint8_t *)&ctrl2_ois, 1);
*val = (uint8_t)ctrl2_ois.hp_rst;
return ret;
@@ -783,21 +860,29 @@ int32_t l20g20is_gy_filter_lp_bandwidth_set(stmdev_ctx_t *ctx,
l20g20is_ctrl2_ois_t ctrl2_ois;
l20g20is_ctrl3_ois_t ctrl3_ois;
int32_t ret;
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL2_OIS,
+ (uint8_t *)&ctrl2_ois, 1);
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL2_OIS, (uint8_t*)&ctrl2_ois, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl2_ois.lpf_bw = (uint8_t)val & 0x03U;
- ret = l20g20is_write_reg(ctx, L20G20IS_CTRL2_OIS, (uint8_t*)&ctrl2_ois, 1);
+ ret = l20g20is_write_reg(ctx, L20G20IS_CTRL2_OIS,
+ (uint8_t *)&ctrl2_ois, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = l20g20is_read_reg(ctx, L20G20IS_CTRL3_OIS,
- (uint8_t*)&ctrl3_ois, 1);
+ (uint8_t *)&ctrl3_ois, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ctrl3_ois.lpf_bw = ((uint8_t)val & 0x04U) >> 2;
ret = l20g20is_write_reg(ctx, L20G20IS_CTRL3_OIS,
- (uint8_t*)&ctrl3_ois, 1);
+ (uint8_t *)&ctrl3_ois, 1);
}
+
return ret;
}
@@ -815,31 +900,42 @@ int32_t l20g20is_gy_filter_lp_bandwidth_get(stmdev_ctx_t *ctx,
l20g20is_ctrl2_ois_t ctrl2_ois;
l20g20is_ctrl3_ois_t ctrl3_ois;
int32_t ret;
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL3_OIS,
+ (uint8_t *)&ctrl3_ois, 1);
+
+ if (ret == 0)
+ {
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL2_OIS,
+ (uint8_t *)&ctrl2_ois, 1);
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL3_OIS,(uint8_t*)&ctrl3_ois, 1);
- if(ret == 0){
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL2_OIS, (uint8_t*)&ctrl2_ois, 1);
- switch ( (ctrl3_ois.lpf_bw << 2) + ctrl2_ois.lpf_bw){
+ switch ((ctrl3_ois.lpf_bw << 2) + ctrl2_ois.lpf_bw)
+ {
case L20G20IS_LPF_BW_1150Hz:
*val = L20G20IS_LPF_BW_1150Hz;
break;
+
case L20G20IS_LPF_BW_290Hz:
*val = L20G20IS_LPF_BW_290Hz;
break;
+
case L20G20IS_LPF_BW_210Hz:
*val = L20G20IS_LPF_BW_210Hz;
break;
+
case L20G20IS_LPF_BW_160Hz:
*val = L20G20IS_LPF_BW_160Hz;
break;
+
case L20G20IS_LPF_BW_450Hz:
*val = L20G20IS_LPF_BW_450Hz;
break;
+
default:
*val = L20G20IS_LPF_BW_290Hz;
break;
}
}
+
return ret;
}
@@ -868,12 +964,16 @@ int32_t l20g20is_spi_mode_set(stmdev_ctx_t *ctx, l20g20is_sim_t val)
{
l20g20is_ctrl1_ois_t ctrl1_ois;
int32_t ret;
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS,
+ (uint8_t *)&ctrl1_ois, 1);
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl1_ois.sim = (uint8_t)val;
- ret = l20g20is_write_reg(ctx, L20G20IS_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
+ ret = l20g20is_write_reg(ctx, L20G20IS_CTRL1_OIS,
+ (uint8_t *)&ctrl1_ois, 1);
}
+
return ret;
}
@@ -889,19 +989,24 @@ int32_t l20g20is_spi_mode_get(stmdev_ctx_t *ctx, l20g20is_sim_t *val)
{
l20g20is_ctrl1_ois_t ctrl1_ois;
int32_t ret;
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS,
+ (uint8_t *)&ctrl1_ois, 1);
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
- switch (ctrl1_ois.sim){
+ switch (ctrl1_ois.sim)
+ {
case L20G20IS_SPI_4_WIRE:
*val = L20G20IS_SPI_4_WIRE;
break;
+
case L20G20IS_SPI_3_WIRE:
*val = L20G20IS_SPI_3_WIRE;
break;
+
default:
*val = L20G20IS_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -931,13 +1036,16 @@ int32_t l20g20is_pin_notification_set(stmdev_ctx_t *ctx,
{
l20g20is_ctrl1_ois_t ctrl1_ois;
int32_t ret;
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS,
+ (uint8_t *)&ctrl1_ois, 1);
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl1_ois.dr_pulsed = (uint8_t)val;
ret = l20g20is_write_reg(ctx, L20G20IS_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
}
+
return ret;
}
@@ -954,19 +1062,24 @@ int32_t l20g20is_pin_notification_get(stmdev_ctx_t *ctx,
{
l20g20is_ctrl1_ois_t ctrl1_ois;
int32_t ret;
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS,
+ (uint8_t *)&ctrl1_ois, 1);
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
- switch (ctrl1_ois.dr_pulsed){
+ switch (ctrl1_ois.dr_pulsed)
+ {
case L20G20IS_INT_LATCHED:
*val = L20G20IS_INT_LATCHED;
break;
+
case L20G20IS_INT_PULSED:
*val = L20G20IS_INT_PULSED;
break;
+
default:
*val = L20G20IS_INT_LATCHED;
break;
}
+
return ret;
}
@@ -983,13 +1096,16 @@ int32_t l20g20is_pin_polarity_set(stmdev_ctx_t *ctx,
{
l20g20is_ctrl3_ois_t ctrl3_ois;
int32_t ret;
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL3_OIS,
+ (uint8_t *)&ctrl3_ois, 1);
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl3_ois.h_l_active = (uint8_t)val;
ret = l20g20is_write_reg(ctx, L20G20IS_CTRL3_OIS,
- (uint8_t*)&ctrl3_ois, 1);
+ (uint8_t *)&ctrl3_ois, 1);
}
+
return ret;
}
@@ -1006,19 +1122,24 @@ int32_t l20g20is_pin_polarity_get(stmdev_ctx_t *ctx,
{
l20g20is_ctrl3_ois_t ctrl3_ois;
int32_t ret;
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL3_OIS,
+ (uint8_t *)&ctrl3_ois, 1);
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
- switch (ctrl3_ois.h_l_active){
+ switch (ctrl3_ois.h_l_active)
+ {
case L20G20IS_ACTIVE_HIGH:
*val = L20G20IS_ACTIVE_HIGH;
break;
+
case L20G20IS_ACTIVE_LOW:
*val = L20G20IS_ACTIVE_LOW;
break;
+
default:
*val = L20G20IS_ACTIVE_HIGH;
break;
}
+
return ret;
}
@@ -1034,12 +1155,16 @@ int32_t l20g20is_pin_mode_set(stmdev_ctx_t *ctx, l20g20is_pp_od_t val)
{
l20g20is_ctrl4_ois_t ctrl4_ois;
int32_t ret;
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL4_OIS,
+ (uint8_t *)&ctrl4_ois, 1);
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL4_OIS, (uint8_t*)&ctrl4_ois, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl4_ois.drdy_od = (uint8_t)val;
- ret = l20g20is_write_reg(ctx, L20G20IS_CTRL4_OIS, (uint8_t*)&ctrl4_ois, 1);
+ ret = l20g20is_write_reg(ctx, L20G20IS_CTRL4_OIS,
+ (uint8_t *)&ctrl4_ois, 1);
}
+
return ret;
}
@@ -1051,23 +1176,29 @@ int32_t l20g20is_pin_mode_set(stmdev_ctx_t *ctx, l20g20is_pp_od_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t l20g20is_pin_mode_get(stmdev_ctx_t *ctx, l20g20is_pp_od_t *val)
+int32_t l20g20is_pin_mode_get(stmdev_ctx_t *ctx,
+ l20g20is_pp_od_t *val)
{
l20g20is_ctrl4_ois_t ctrl4_ois;
int32_t ret;
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL4_OIS,
+ (uint8_t *)&ctrl4_ois, 1);
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL4_OIS, (uint8_t*)&ctrl4_ois, 1);
- switch (ctrl4_ois.drdy_od){
+ switch (ctrl4_ois.drdy_od)
+ {
case L20G20IS_PUSH_PULL:
*val = L20G20IS_PUSH_PULL;
break;
+
case L20G20IS_OPEN_DRAIN:
*val = L20G20IS_OPEN_DRAIN;
break;
+
default:
*val = L20G20IS_PUSH_PULL;
break;
}
+
return ret;
}
@@ -1085,13 +1216,17 @@ int32_t l20g20is_pin_drdy_route_set(stmdev_ctx_t *ctx,
{
l20g20is_ctrl4_ois_t ctrl4_ois;
int32_t ret;
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL4_OIS,
+ (uint8_t *)&ctrl4_ois, 1);
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL4_OIS, (uint8_t*)&ctrl4_ois, 1);
- if(ret == 0) {
+ if (ret == 0)
+ {
ctrl4_ois.drdy_en = val.drdy_en;
ctrl4_ois.temp_data_on_drdy = val.temp_data_on_drdy;
- ret = l20g20is_write_reg(ctx, L20G20IS_CTRL4_OIS, (uint8_t*)&ctrl4_ois, 1);
+ ret = l20g20is_write_reg(ctx, L20G20IS_CTRL4_OIS,
+ (uint8_t *)&ctrl4_ois, 1);
}
+
return ret;
}
@@ -1109,8 +1244,8 @@ int32_t l20g20is_pin_drdy_route_get(stmdev_ctx_t *ctx,
{
l20g20is_ctrl4_ois_t ctrl4_ois;
int32_t ret;
-
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL4_OIS, (uint8_t*)&ctrl4_ois, 1);
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL4_OIS,
+ (uint8_t *)&ctrl4_ois, 1);
val->temp_data_on_drdy = ctrl4_ois.temp_data_on_drdy;
val->drdy_en = ctrl4_ois.drdy_en;
@@ -1143,14 +1278,17 @@ int32_t l20g20is_gy_self_test_set(stmdev_ctx_t *ctx,
{
l20g20is_ctrl3_ois_t ctrl3_ois;
int32_t ret;
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL3_OIS,
+ (uint8_t *)&ctrl3_ois, 1);
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl3_ois.st_en = ((uint8_t)val & 0x02U) >> 1;
ctrl3_ois.st_sign = (uint8_t)val & 0x01U;
ret = l20g20is_write_reg(ctx, L20G20IS_CTRL3_OIS,
- (uint8_t*)&ctrl3_ois, 1);
+ (uint8_t *)&ctrl3_ois, 1);
}
+
return ret;
}
@@ -1167,22 +1305,28 @@ int32_t l20g20is_gy_self_test_get(stmdev_ctx_t *ctx,
{
l20g20is_ctrl3_ois_t ctrl3_ois;
int32_t ret;
+ ret = l20g20is_read_reg(ctx, L20G20IS_CTRL3_OIS,
+ (uint8_t *)&ctrl3_ois, 1);
- ret = l20g20is_read_reg(ctx, L20G20IS_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
- switch ((ctrl3_ois.st_en << 1) + ctrl3_ois.st_sign){
+ switch ((ctrl3_ois.st_en << 1) + ctrl3_ois.st_sign)
+ {
case L20G20IS_ST_DISABLE:
*val = L20G20IS_ST_DISABLE;
break;
+
case L20G20IS_ST_POSITIVE:
*val = L20G20IS_ST_POSITIVE;
break;
+
case L20G20IS_ST_NEGATIVE:
*val = L20G20IS_ST_NEGATIVE;
break;
+
default:
*val = L20G20IS_ST_DISABLE;
break;
}
+
return ret;
}
diff --git a/sensor/stmemsc/l20g20is_STdC/driver/l20g20is_reg.h b/sensor/stmemsc/l20g20is_STdC/driver/l20g20is_reg.h
index 2661e3e736580ecc836977cb952032d6c8ee60f0..d18eef6d74edb281d71bac721879f3a54c9b3daa 100644
--- a/sensor/stmemsc/l20g20is_STdC/driver/l20g20is_reg.h
+++ b/sensor/stmemsc/l20g20is_STdC/driver/l20g20is_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file l20g20is_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * l20g20is_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file l20g20is_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * l20g20is_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef L20G20IS_REGS_H
#define L20G20IS_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup L20G20IS
@@ -74,7 +75,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -107,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -131,7 +134,7 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
+ * You can create a sensor configuration by your own or using
* Unico / Unicleo tools available on STMicroelectronics
* web site.
*
@@ -139,7 +142,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -177,7 +181,8 @@ typedef struct {
#define L20G20IS_OUT_Y_L 0x05U
#define L20G20IS_OUT_Y_H 0x06U
#define L20G20IS_DATA_STATUS_OIS 0x0AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t yda_ois : 1;
@@ -200,7 +205,8 @@ typedef struct {
} l20g20is_data_status_ois_t;
#define L20G20IS_CTRL1_OIS 0x0BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t pw : 2;
uint8_t orient : 1;
@@ -221,7 +227,8 @@ typedef struct {
} l20g20is_ctrl1_ois_t;
#define L20G20IS_CTRL2_OIS 0x0CU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t hpf : 1;
uint8_t sw_rst : 1;
@@ -242,7 +249,8 @@ typedef struct {
} l20g20is_ctrl2_ois_t;
#define L20G20IS_CTRL3_OIS 0x0DU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lpf_bw : 1;
uint8_t h_l_active : 1;
@@ -261,7 +269,8 @@ typedef struct {
} l20g20is_ctrl3_ois_t;
#define L20G20IS_CTRL4_OIS 0x0EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t drdy_od : 1;
@@ -280,7 +289,8 @@ typedef struct {
} l20g20is_ctrl4_ois_t;
#define L20G20IS_OFF_X 0x0FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t offx : 7;
uint8_t not_used_01 : 1;
@@ -291,7 +301,8 @@ typedef struct {
} l20g20is_off_x_t;
#define L20G20IS_OFF_Y 0x10U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t offy : 7;
uint8_t not_used_01 : 1;
@@ -302,7 +313,8 @@ typedef struct {
} l20g20is_off_y_t;
#define L20G20IS_OIS_CFG_REG 0x1FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t hpf_bw : 2;
uint8_t not_used_01 : 1;
@@ -318,9 +330,9 @@ typedef struct {
/**
* @defgroup L20G20IS_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -329,7 +341,8 @@ typedef struct {
*
*/
-typedef union{
+typedef union
+{
l20g20is_data_status_ois_t data_status_ois;
l20g20is_ctrl1_ois_t ctrl1_ois;
l20g20is_ctrl2_ois_t ctrl2_ois;
@@ -347,9 +360,11 @@ typedef union{
*
*/
-int32_t l20g20is_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t l20g20is_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t l20g20is_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t l20g20is_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
float_t l20g20is_from_fs100dps_to_mdps(int16_t lsb);
@@ -357,9 +372,11 @@ float_t l20g20is_from_fs200dps_to_mdps(int16_t lsb);
float_t l20g20is_from_lsb_to_celsius(int16_t lsb);
-int32_t l20g20is_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t l20g20is_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
L20G20IS_GY_OFF = 0,
L20G20IS_GY_SLEEP = 2,
L20G20IS_GY_9k33Hz = 3,
@@ -369,7 +386,8 @@ int32_t l20g20is_gy_data_rate_set(stmdev_ctx_t *ctx,
int32_t l20g20is_gy_data_rate_get(stmdev_ctx_t *ctx,
l20g20is_gy_data_rate_t *val);
-typedef struct {
+typedef struct
+{
uint8_t orient : 1;
uint8_t signy : 1;
uint8_t signx : 1;
@@ -379,10 +397,13 @@ int32_t l20g20is_gy_orient_set(stmdev_ctx_t *ctx,
int32_t l20g20is_gy_orient_get(stmdev_ctx_t *ctx,
l20g20is_gy_orient_t *val);
-int32_t l20g20is_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t l20g20is_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t l20g20is_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t l20g20is_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef struct {
+typedef struct
+{
uint8_t offx : 7;
uint8_t offy : 7;
} l20g20is_off_t;
@@ -391,7 +412,8 @@ int32_t l20g20is_angular_rate_offset_set(stmdev_ctx_t *ctx,
int32_t l20g20is_angular_rate_offset_get(stmdev_ctx_t *ctx,
l20g20is_off_t *val);
-typedef enum {
+typedef enum
+{
L20G20IS_100dps = 0,
L20G20IS_200dps = 1,
} l20g20is_gy_fs_t;
@@ -402,17 +424,20 @@ int32_t l20g20is_gy_full_scale_get(stmdev_ctx_t *ctx,
int32_t l20g20is_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val);
-int32_t l20g20is_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t l20g20is_angular_rate_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
int32_t l20g20is_dev_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
-typedef struct {
+typedef struct
+{
uint8_t xyda_ois : 1;
} l20g20is_dev_status_t;
int32_t l20g20is_dev_status_get(stmdev_ctx_t *ctx,
l20g20is_dev_status_t *val);
-typedef enum {
+typedef enum
+{
L20G20IS_LSB_LOW_ADDRESS = 0,
L20G20IS_MSB_LOW_ADDRESS = 1,
} l20g20is_ble_t;
@@ -427,7 +452,8 @@ int32_t l20g20is_dev_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t l20g20is_dev_reset_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t l20g20is_dev_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
L20G20IS_HPF_BYPASS = 0x00,
L20G20IS_HPF_BW_23mHz = 0x80,
L20G20IS_HPF_BW_91mHz = 0x81,
@@ -439,10 +465,13 @@ int32_t l20g20is_gy_filter_hp_bandwidth_set(stmdev_ctx_t *ctx,
int32_t l20g20is_gy_filter_hp_bandwidth_get(stmdev_ctx_t *ctx,
l20g20is_gy_hp_bw_t *val);
-int32_t l20g20is_gy_filter_hp_reset_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t l20g20is_gy_filter_hp_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t l20g20is_gy_filter_hp_reset_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t l20g20is_gy_filter_hp_reset_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
L20G20IS_LPF_BW_290Hz = 0x00,
L20G20IS_LPF_BW_210Hz = 0x01,
L20G20IS_LPF_BW_160Hz = 0x02,
@@ -454,14 +483,16 @@ int32_t l20g20is_gy_filter_lp_bandwidth_set(stmdev_ctx_t *ctx,
int32_t l20g20is_gy_filter_lp_bandwidth_get(stmdev_ctx_t *ctx,
l20g20is_gy_lp_bw_t *val);
-typedef enum {
+typedef enum
+{
L20G20IS_SPI_4_WIRE = 0,
L20G20IS_SPI_3_WIRE = 1,
} l20g20is_sim_t;
int32_t l20g20is_spi_mode_set(stmdev_ctx_t *ctx, l20g20is_sim_t val);
int32_t l20g20is_spi_mode_get(stmdev_ctx_t *ctx, l20g20is_sim_t *val);
-typedef enum {
+typedef enum
+{
L20G20IS_INT_PULSED = 1,
L20G20IS_INT_LATCHED = 0,
} l20g20is_lir_t;
@@ -470,7 +501,8 @@ int32_t l20g20is_pin_notification_set(stmdev_ctx_t *ctx,
int32_t l20g20is_pin_notification_get(stmdev_ctx_t *ctx,
l20g20is_lir_t *val);
-typedef enum {
+typedef enum
+{
L20G20IS_ACTIVE_HIGH = 0,
L20G20IS_ACTIVE_LOW = 1,
} l20g20is_pin_pol_t;
@@ -479,14 +511,18 @@ int32_t l20g20is_pin_polarity_set(stmdev_ctx_t *ctx,
int32_t l20g20is_pin_polarity_get(stmdev_ctx_t *ctx,
l20g20is_pin_pol_t *val);
-typedef enum {
+typedef enum
+{
L20G20IS_PUSH_PULL = 0,
L20G20IS_OPEN_DRAIN = 1,
} l20g20is_pp_od_t;
-int32_t l20g20is_pin_mode_set(stmdev_ctx_t *ctx, l20g20is_pp_od_t val);
-int32_t l20g20is_pin_mode_get(stmdev_ctx_t *ctx, l20g20is_pp_od_t *val);
+int32_t l20g20is_pin_mode_set(stmdev_ctx_t *ctx,
+ l20g20is_pp_od_t val);
+int32_t l20g20is_pin_mode_get(stmdev_ctx_t *ctx,
+ l20g20is_pp_od_t *val);
-typedef struct {
+typedef struct
+{
uint8_t temp_data_on_drdy : 1;
uint8_t drdy_en : 1;
} l20g20is_pin_drdy_route_t;
@@ -495,7 +531,8 @@ int32_t l20g20is_pin_drdy_route_set(stmdev_ctx_t *ctx,
int32_t l20g20is_pin_drdy_route_get(stmdev_ctx_t *ctx,
l20g20is_pin_drdy_route_t *val);
-typedef enum {
+typedef enum
+{
L20G20IS_ST_DISABLE = 0x00,
L20G20IS_ST_POSITIVE = 0x02,
L20G20IS_ST_NEGATIVE = 0x03,
diff --git a/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.c b/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.c
index 237db284cc006cf9cefb3b9f72905b183e978e5b..19cd5ceb28f15ae1cab8e8f21781caa1f2ec5a76 100644
--- a/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.c
+++ b/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.c
@@ -1,21 +1,22 @@
-/*
- ******************************************************************************
- * @file l3gd20h_reg.c
- * @author Sensors Software Solution Team
- * @brief L3GD20H driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file l3gd20h_reg.c
+ * @author Sensors Software Solution Team
+ * @brief L3GD20H driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
#include "l3gd20h_reg.h"
/**
@@ -45,11 +46,13 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t l3gd20h_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t l3gd20h_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -63,11 +66,13 @@ int32_t l3gd20h_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t l3gd20h_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t l3gd20h_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -100,7 +105,7 @@ float_t l3gd20h_from_fs2000_to_mdps(int16_t lsb)
float_t l3gd20h_from_lsb_to_celsius(int16_t lsb)
{
- return ((float_t)lsb +25.0f);
+ return ((float_t)lsb + 25.0f);
}
/**
* @}
@@ -126,14 +131,16 @@ int32_t l3gd20h_gy_axis_set(stmdev_ctx_t *ctx, l3gd20h_gy_axis_t val)
{
l3gd20h_ctrl1_t ctrl1;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL1, (uint8_t *)&ctrl1, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL1, (uint8_t*)&ctrl1, 1);
- if(ret == 0) {
+ if (ret == 0)
+ {
ctrl1.xen = val.xen;
ctrl1.yen = val.yen;
ctrl1.zen = val.zen;
- ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL1, (uint8_t*)&ctrl1, 1);
+ ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL1, (uint8_t *)&ctrl1, 1);
}
+
return ret;
}
@@ -149,8 +156,7 @@ int32_t l3gd20h_gy_axis_get(stmdev_ctx_t *ctx, l3gd20h_gy_axis_t *val)
{
l3gd20h_ctrl1_t ctrl1;
int32_t ret;
-
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL1, (uint8_t*)&ctrl1, 1);
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL1, (uint8_t *)&ctrl1, 1);
val->xen = ctrl1.xen;
val->yen = ctrl1.yen;
val->zen = ctrl1.zen;
@@ -172,20 +178,26 @@ int32_t l3gd20h_gy_data_rate_set(stmdev_ctx_t *ctx,
l3gd20h_low_odr_t low_odr;
l3gd20h_ctrl1_t ctrl1;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL1, (uint8_t *)&ctrl1, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL1, (uint8_t*)&ctrl1, 1);
- if(ret == 0){
- ctrl1.pd = ( (uint8_t)val & 0x80U ) >> 7;
+ if (ret == 0)
+ {
+ ctrl1.pd = ((uint8_t)val & 0x80U) >> 7;
ctrl1.dr = (uint8_t)val & 0x07U;
- ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL1, (uint8_t*)&ctrl1, 1);
+ ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL1, (uint8_t *)&ctrl1, 1);
}
- if(ret == 0){
- ret = l3gd20h_read_reg(ctx, L3GD20H_LOW_ODR, (uint8_t*)&low_odr, 1);
+
+ if (ret == 0)
+ {
+ ret = l3gd20h_read_reg(ctx, L3GD20H_LOW_ODR, (uint8_t *)&low_odr, 1);
}
- if(ret == 0){
- low_odr.low_odr = ( (uint8_t)val & 0x10U ) >> 4;
- ret = l3gd20h_write_reg(ctx, L3GD20H_LOW_ODR, (uint8_t*)&low_odr, 1);
+
+ if (ret == 0)
+ {
+ low_odr.low_odr = ((uint8_t)val & 0x10U) >> 4;
+ ret = l3gd20h_write_reg(ctx, L3GD20H_LOW_ODR, (uint8_t *)&low_odr, 1);
}
+
return ret;
}
@@ -203,40 +215,52 @@ int32_t l3gd20h_gy_data_rate_get(stmdev_ctx_t *ctx,
l3gd20h_low_odr_t low_odr;
l3gd20h_ctrl1_t ctrl1;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL1, (uint8_t *)&ctrl1, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL1, (uint8_t*)&ctrl1, 1);
- if(ret == 0){
- ret = l3gd20h_read_reg(ctx, L3GD20H_LOW_ODR, (uint8_t*)&low_odr, 1);
+ if (ret == 0)
+ {
+ ret = l3gd20h_read_reg(ctx, L3GD20H_LOW_ODR, (uint8_t *)&low_odr, 1);
}
- switch ((ctrl1.pd << 7) + (low_odr.low_odr << 4) + ctrl1.dr){
+
+ switch ((ctrl1.pd << 7) + (low_odr.low_odr << 4) + ctrl1.dr)
+ {
case L3GD20H_POWER_DOWN:
*val = L3GD20H_POWER_DOWN;
break;
+
case L3GD20H_12Hz5:
*val = L3GD20H_12Hz5;
break;
+
case L3GD20H_25Hz:
*val = L3GD20H_25Hz;
break;
+
case L3GD20H_50Hz:
*val = L3GD20H_50Hz;
break;
+
case L3GD20H_100Hz:
*val = L3GD20H_100Hz;
break;
+
case L3GD20H_200Hz:
*val = L3GD20H_200Hz;
break;
+
case L3GD20H_400Hz:
*val = L3GD20H_400Hz;
break;
+
case L3GD20H_800Hz:
*val = L3GD20H_800Hz;
break;
+
default:
*val = L3GD20H_POWER_DOWN;
break;
}
+
return ret;
}
@@ -248,16 +272,19 @@ int32_t l3gd20h_gy_data_rate_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t l3gd20h_gy_full_scale_set(stmdev_ctx_t *ctx, l3gd20h_gy_fs_t val)
+int32_t l3gd20h_gy_full_scale_set(stmdev_ctx_t *ctx,
+ l3gd20h_gy_fs_t val)
{
l3gd20h_ctrl4_t ctrl4;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t*)&ctrl4, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl4.fs = (uint8_t)val;
- ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL4, (uint8_t*)&ctrl4, 1);
+ ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
}
+
return ret;
}
@@ -269,23 +296,28 @@ int32_t l3gd20h_gy_full_scale_set(stmdev_ctx_t *ctx, l3gd20h_gy_fs_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t l3gd20h_gy_full_scale_get(stmdev_ctx_t *ctx, l3gd20h_gy_fs_t *val)
+int32_t l3gd20h_gy_full_scale_get(stmdev_ctx_t *ctx,
+ l3gd20h_gy_fs_t *val)
{
l3gd20h_ctrl4_t ctrl4;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t*)&ctrl4, 1);
- switch (ctrl4.fs){
+ switch (ctrl4.fs)
+ {
case L3GD20H_245dps:
*val = L3GD20H_245dps;
break;
+
case L3GD20H_500dps:
*val = L3GD20H_500dps;
break;
+
default:
*val = L3GD20H_245dps;
break;
}
+
return ret;
}
/**
@@ -300,12 +332,14 @@ int32_t l3gd20h_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
{
l3gd20h_ctrl4_t ctrl4;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t*)&ctrl4, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl4.bdu = val;
- ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL4, (uint8_t*)&ctrl4, 1);
+ ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
}
+
return ret;
}
@@ -321,8 +355,7 @@ int32_t l3gd20h_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
{
l3gd20h_ctrl4_t ctrl4;
int32_t ret;
-
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t*)&ctrl4, 1);
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
*val = ctrl4.bdu;
return ret;
@@ -335,12 +368,12 @@ int32_t l3gd20h_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t l3gd20h_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t l3gd20h_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
l3gd20h_status_t status;
int32_t ret;
-
- ret = l3gd20h_read_reg(ctx, L3GD20H_STATUS, (uint8_t*)&status, 1);
+ ret = l3gd20h_read_reg(ctx, L3GD20H_STATUS, (uint8_t *)&status, 1);
*val = status.zyxda;
return ret;
@@ -371,6 +404,7 @@ int32_t l3gd20h_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
ret = l3gd20h_read_reg(ctx, L3GD20H_OUT_TEMP, buff, 1);
+
return ret;
}
@@ -387,14 +421,13 @@ int32_t l3gd20h_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
uint8_t buff[6];
int32_t ret;
-
ret = l3gd20h_read_reg(ctx, L3GD20H_OUT_X_L, buff, 6);
val[0] = (int16_t)buff[1];
- val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
- val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
val[2] = (int16_t)buff[5];
- val[2] = (val[2] * 256) + (int16_t)buff[4];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
return ret;
}
@@ -406,7 +439,7 @@ int32_t l3gd20h_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
/**
* @defgroup L3GD20H_Common
- * @brief This section groups common usefull functions.
+ * @brief This section groups common useful functions.
* @{
*
*/
@@ -423,6 +456,7 @@ int32_t l3gd20h_dev_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
ret = l3gd20h_read_reg(ctx, L3GD20H_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -434,16 +468,19 @@ int32_t l3gd20h_dev_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t l3gd20h_dev_data_format_set(stmdev_ctx_t *ctx, l3gd20h_ble_t val)
+int32_t l3gd20h_dev_data_format_set(stmdev_ctx_t *ctx,
+ l3gd20h_ble_t val)
{
l3gd20h_ctrl4_t ctrl4;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t*)&ctrl4, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl4.ble = (uint8_t)val;
- ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL4, (uint8_t*)&ctrl4, 1);
+ ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
}
+
return ret;
}
@@ -455,23 +492,28 @@ int32_t l3gd20h_dev_data_format_set(stmdev_ctx_t *ctx, l3gd20h_ble_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t l3gd20h_dev_data_format_get(stmdev_ctx_t *ctx, l3gd20h_ble_t *val)
+int32_t l3gd20h_dev_data_format_get(stmdev_ctx_t *ctx,
+ l3gd20h_ble_t *val)
{
l3gd20h_ctrl4_t ctrl4;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t*)&ctrl4, 1);
- switch (ctrl4.ble){
+ switch (ctrl4.ble)
+ {
case L3GD20H_LSB_LOW_ADDRESS:
*val = L3GD20H_LSB_LOW_ADDRESS;
break;
+
case L3GD20H_MSB_LOW_ADDRESS:
*val = L3GD20H_MSB_LOW_ADDRESS;
break;
+
default:
*val = L3GD20H_LSB_LOW_ADDRESS;
break;
}
+
return ret;
}
@@ -487,12 +529,14 @@ int32_t l3gd20h_dev_boot_set(stmdev_ctx_t *ctx, uint8_t val)
{
l3gd20h_ctrl5_t ctrl5;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t*)&ctrl5, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl5.boot = val;
- ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL5, (uint8_t*)&ctrl5, 1);
+ ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1);
}
+
return ret;
}
@@ -508,8 +552,7 @@ int32_t l3gd20h_dev_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
{
l3gd20h_ctrl5_t ctrl5;
int32_t ret;
-
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t*)&ctrl5, 1);
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1);
*val = ctrl5.boot;
return ret;
@@ -522,12 +565,12 @@ int32_t l3gd20h_dev_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t l3gd20h_dev_status_get(stmdev_ctx_t *ctx, l3gd20h_status_reg_t *val)
+int32_t l3gd20h_dev_status_get(stmdev_ctx_t *ctx,
+ l3gd20h_status_reg_t *val)
{
l3gd20h_status_t status;
int32_t ret;
-
- ret = l3gd20h_read_reg(ctx, L3GD20H_STATUS, (uint8_t*)&status, 1);
+ ret = l3gd20h_read_reg(ctx, L3GD20H_STATUS, (uint8_t *)&status, 1);
val->xda = status.xda;
val->yda = status.yda;
val->zda = status.zda;
@@ -552,12 +595,14 @@ int32_t l3gd20h_dev_reset_set(stmdev_ctx_t *ctx, uint8_t val)
{
l3gd20h_low_odr_t low_odr;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_LOW_ODR, (uint8_t *)&low_odr, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_LOW_ODR, (uint8_t*)&low_odr, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
low_odr.sw_res = val;
- ret = l3gd20h_write_reg(ctx, L3GD20H_LOW_ODR, (uint8_t*)&low_odr, 1);
+ ret = l3gd20h_write_reg(ctx, L3GD20H_LOW_ODR, (uint8_t *)&low_odr, 1);
}
+
return ret;
}
@@ -573,8 +618,7 @@ int32_t l3gd20h_dev_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
{
l3gd20h_low_odr_t low_odr;
int32_t ret;
-
- ret = l3gd20h_read_reg(ctx, L3GD20H_LOW_ODR, (uint8_t*)&low_odr, 1);
+ ret = l3gd20h_read_reg(ctx, L3GD20H_LOW_ODR, (uint8_t *)&low_odr, 1);
*val = low_odr.sw_res;
return ret;
@@ -606,12 +650,14 @@ int32_t l3gd20h_gy_filter_lp_bandwidth_set(stmdev_ctx_t *ctx,
{
l3gd20h_ctrl1_t ctrl1;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL1, (uint8_t *)&ctrl1, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL1, (uint8_t*)&ctrl1, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl1.bw = (uint8_t)val;
- ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL1, (uint8_t*)&ctrl1, 1);
+ ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL1, (uint8_t *)&ctrl1, 1);
}
+
return ret;
}
@@ -629,52 +675,68 @@ int32_t l3gd20h_gy_filter_lp_bandwidth_get(stmdev_ctx_t *ctx,
l3gd20h_low_odr_t low_odr;
l3gd20h_ctrl1_t ctrl1;
int32_t ret;
-
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL1, (uint8_t*)&ctrl1, 1);
- if(ret == 0){
- ret = l3gd20h_read_reg(ctx, L3GD20H_LOW_ODR, (uint8_t*)&low_odr, 1);
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL1, (uint8_t *)&ctrl1, 1);
+
+ if (ret == 0)
+ {
+ ret = l3gd20h_read_reg(ctx, L3GD20H_LOW_ODR, (uint8_t *)&low_odr, 1);
}
- switch ((low_odr.low_odr << 7) + (ctrl1.dr << 4) + ctrl1.bw){
+
+ switch ((low_odr.low_odr << 7) + (ctrl1.dr << 4) + ctrl1.bw)
+ {
case L3GD20H_16Hz6_USE_ODR_50Hz:
*val = L3GD20H_16Hz6_USE_ODR_50Hz;
break;
+
case L3GD20H_12Hz5_USE_ODR_100Hz:
*val = L3GD20H_12Hz5_USE_ODR_100Hz;
break;
+
case L3GD20H_25Hz_USE_ODR_100Hz:
*val = L3GD20H_25Hz_USE_ODR_100Hz;
break;
+
case L3GD20H_12Hz5_USE_ODR_200Hz:
*val = L3GD20H_12Hz5_USE_ODR_200Hz;
break;
+
case L3GD20H_70Hz_USE_ODR_200Hz:
*val = L3GD20H_70Hz_USE_ODR_200Hz;
break;
+
case L3GD20H_20Hz_USE_ODR_400Hz:
*val = L3GD20H_20Hz_USE_ODR_400Hz;
break;
+
case L3GD20H_25Hz_USE_ODR_400Hz:
*val = L3GD20H_25Hz_USE_ODR_400Hz;
break;
+
case L3GD20H_50Hz_USE_ODR_400Hz:
*val = L3GD20H_50Hz_USE_ODR_400Hz;
break;
+
case L3GD20H_110Hz_USE_ODR_400Hz:
*val = L3GD20H_110Hz_USE_ODR_400Hz;
break;
+
case L3GD20H_30Hz_USE_ODR_800Hz:
*val = L3GD20H_30Hz_USE_ODR_800Hz;
break;
+
case L3GD20H_35Hz_USE_ODR_800Hz:
*val = L3GD20H_35Hz_USE_ODR_800Hz;
break;
+
case L3GD20H_100Hz_USE_ODR_800Hz:
*val = L3GD20H_100Hz_USE_ODR_800Hz;
break;
+
default:
*val = L3GD20H_16Hz6_USE_ODR_50Hz;
break;
}
+
return ret;
}
@@ -687,17 +749,19 @@ int32_t l3gd20h_gy_filter_lp_bandwidth_get(stmdev_ctx_t *ctx,
*
*/
int32_t l3gd20h_gy_filter_hp_bandwidth_set(stmdev_ctx_t *ctx,
- l3gd20h_gy_hp_bw_t val)
+ l3gd20h_gy_hp_bw_t val)
{
l3gd20h_ctrl2_t ctrl2;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL2, (uint8_t *)&ctrl2, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL2, (uint8_t*)&ctrl2, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl2.hpcf = (uint8_t)val & 0x03U;
ctrl2.hpm = ((uint8_t)val & 0x30U) >> 4;
- ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL2, (uint8_t*)&ctrl2, 1);
+ ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL2, (uint8_t *)&ctrl2, 1);
}
+
return ret;
}
@@ -710,56 +774,72 @@ int32_t l3gd20h_gy_filter_hp_bandwidth_set(stmdev_ctx_t *ctx,
*
*/
int32_t l3gd20h_gy_filter_hp_bandwidth_get(stmdev_ctx_t *ctx,
- l3gd20h_gy_hp_bw_t *val)
+ l3gd20h_gy_hp_bw_t *val)
{
l3gd20h_ctrl2_t ctrl2;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL2, (uint8_t *)&ctrl2, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL2, (uint8_t*)&ctrl2, 1);
- if(ret == 0){
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL2, (uint8_t*)&ctrl2, 1);
+ if (ret == 0)
+ {
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL2, (uint8_t *)&ctrl2, 1);
}
- switch ( (ctrl2.hpm << 4) + ctrl2.hpcf){
+
+ switch ((ctrl2.hpm << 4) + ctrl2.hpcf)
+ {
case L3GD20H_NORMAL_MODE_LIGHT:
*val = L3GD20H_NORMAL_MODE_LIGHT;
break;
+
case L3GD20H_NORMAL_MODE_NORMAL:
*val = L3GD20H_NORMAL_MODE_NORMAL;
break;
+
case L3GD20H_NORMAL_MODE_STRONG:
*val = L3GD20H_NORMAL_MODE_STRONG;
break;
+
case L3GD20H_NORMAL_MODE_EXTREME:
*val = L3GD20H_NORMAL_MODE_EXTREME;
break;
+
case L3GD20H_USE_REFERENCE_LIGHT:
*val = L3GD20H_USE_REFERENCE_LIGHT;
break;
+
case L3GD20H_USE_REFERENCE_NORMAL:
*val = L3GD20H_USE_REFERENCE_NORMAL;
break;
+
case L3GD20H_USE_REFERENCE_STRONG:
*val = L3GD20H_USE_REFERENCE_STRONG;
break;
+
case L3GD20H_USE_REFERENCE_EXTREME:
*val = L3GD20H_USE_REFERENCE_EXTREME;
break;
+
case L3GD20H_AUTORESET_LIGHT:
*val = L3GD20H_AUTORESET_LIGHT;
break;
+
case L3GD20H_AUTORESET_NORMAL:
*val = L3GD20H_AUTORESET_NORMAL;
break;
+
case L3GD20H_AUTORESET_STRONG:
*val = L3GD20H_AUTORESET_STRONG;
break;
+
case L3GD20H_AUTORESET_EXTREME:
*val = L3GD20H_AUTORESET_EXTREME;
break;
+
default:
*val = L3GD20H_NORMAL_MODE_LIGHT;
break;
}
+
return ret;
}
@@ -776,13 +856,15 @@ int32_t l3gd20h_gy_filter_out_path_set(stmdev_ctx_t *ctx,
{
l3gd20h_ctrl5_t ctrl5;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t*)&ctrl5, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl5.out_sel = (uint8_t)val & 0x03U;
- ctrl5.hpen = ( (uint8_t)val & 0x10U ) >> 4;
- ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL5, (uint8_t*)&ctrl5, 1);
+ ctrl5.hpen = ((uint8_t)val & 0x10U) >> 4;
+ ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1);
}
+
return ret;
}
@@ -799,24 +881,31 @@ int32_t l3gd20h_gy_filter_out_path_get(stmdev_ctx_t *ctx,
{
l3gd20h_ctrl5_t ctrl5;
int32_t ret;
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t*)&ctrl5, 1);
- switch (( ctrl5.hpen << 4 ) + ctrl5.out_sel ){
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1);
+
+ switch ((ctrl5.hpen << 4) + ctrl5.out_sel)
+ {
case L3GD20H_LPF1_OUT:
*val = L3GD20H_LPF1_OUT;
break;
+
case L3GD20H_LPF1_HPF_OUT:
*val = L3GD20H_LPF1_HPF_OUT;
break;
+
case L3GD20H_LPF1_LPF2_OUT:
*val = L3GD20H_LPF1_LPF2_OUT;
break;
+
case L3GD20H_LPF1_HPF_LPF2_OUT:
*val = L3GD20H_LPF1_HPF_LPF2_OUT;
break;
+
default:
*val = L3GD20H_LPF1_OUT;
break;
}
+
return ret;
}
@@ -833,13 +922,15 @@ int32_t l3gd20h_gy_filter_int_path_set(stmdev_ctx_t *ctx,
{
l3gd20h_ctrl5_t ctrl5;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t*)&ctrl5, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl5.ig_sel = (uint8_t)val & 0x03U;
- ctrl5.hpen = ( (uint8_t)val & 0x10U ) >> 4;
- ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL5, (uint8_t*)&ctrl5, 1);
+ ctrl5.hpen = ((uint8_t)val & 0x10U) >> 4;
+ ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1);
}
+
return ret;
}
@@ -856,26 +947,32 @@ int32_t l3gd20h_gy_filter_int_path_get(stmdev_ctx_t *ctx,
{
l3gd20h_ctrl5_t ctrl5;
int32_t ret;
-
ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5,
- (uint8_t*)&ctrl5, 1);
- switch (( ctrl5.hpen << 4 ) + ctrl5.ig_sel ){
+ (uint8_t *)&ctrl5, 1);
+
+ switch ((ctrl5.hpen << 4) + ctrl5.ig_sel)
+ {
case L3GD20H_LPF1_INT:
*val = L3GD20H_LPF1_INT;
break;
+
case L3GD20H_LPF1_HPF_INT:
*val = L3GD20H_LPF1_HPF_INT;
break;
+
case L3GD20H_LPF1_LPF2_INT:
*val = L3GD20H_LPF1_LPF2_INT;
break;
+
case L3GD20H_LPF1_HPF_LPF2_INT:
*val = L3GD20H_LPF1_HPF_LPF2_INT;
break;
+
default:
*val = L3GD20H_LPF1_INT;
break;
}
+
return ret;
}
@@ -887,10 +984,12 @@ int32_t l3gd20h_gy_filter_int_path_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t l3gd20h_gy_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t l3gd20h_gy_filter_reference_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
ret = l3gd20h_write_reg(ctx, L3GD20H_REFERENCE, buff, 1);
+
return ret;
}
@@ -902,10 +1001,12 @@ int32_t l3gd20h_gy_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t l3gd20h_gy_filter_reference_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t l3gd20h_gy_filter_reference_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
ret = l3gd20h_read_reg(ctx, L3GD20H_REFERENCE, buff, 1);
+
return ret;
}
@@ -934,12 +1035,14 @@ int32_t l3gd20h_spi_mode_set(stmdev_ctx_t *ctx, l3gd20h_sim_t val)
{
l3gd20h_ctrl4_t ctrl4;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t*)&ctrl4, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl4.sim = (uint8_t)val;
- ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL4, (uint8_t*)&ctrl4, 1);
+ ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
}
+
return ret;
}
@@ -955,19 +1058,23 @@ int32_t l3gd20h_spi_mode_get(stmdev_ctx_t *ctx, l3gd20h_sim_t *val)
{
l3gd20h_ctrl4_t ctrl4;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t*)&ctrl4, 1);
- switch (ctrl4.sim){
+ switch (ctrl4.sim)
+ {
case L3GD20H_SPI_4_WIRE:
*val = L3GD20H_SPI_4_WIRE;
break;
+
case L3GD20H_SPI_3_WIRE:
*val = L3GD20H_SPI_3_WIRE;
break;
+
default:
*val = L3GD20H_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -979,16 +1086,19 @@ int32_t l3gd20h_spi_mode_get(stmdev_ctx_t *ctx, l3gd20h_sim_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t l3gd20h_i2c_interface_set(stmdev_ctx_t *ctx, l3gd20h_i2c_dis_t val)
+int32_t l3gd20h_i2c_interface_set(stmdev_ctx_t *ctx,
+ l3gd20h_i2c_dis_t val)
{
l3gd20h_low_odr_t low_odr;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_LOW_ODR, (uint8_t *)&low_odr, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_LOW_ODR, (uint8_t*)&low_odr, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
low_odr.i2c_dis = (uint8_t)val;
- ret = l3gd20h_write_reg(ctx, L3GD20H_LOW_ODR, (uint8_t*)&low_odr, 1);
+ ret = l3gd20h_write_reg(ctx, L3GD20H_LOW_ODR, (uint8_t *)&low_odr, 1);
}
+
return ret;
}
@@ -1000,23 +1110,28 @@ int32_t l3gd20h_i2c_interface_set(stmdev_ctx_t *ctx, l3gd20h_i2c_dis_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t l3gd20h_i2c_interface_get(stmdev_ctx_t *ctx, l3gd20h_i2c_dis_t *val)
+int32_t l3gd20h_i2c_interface_get(stmdev_ctx_t *ctx,
+ l3gd20h_i2c_dis_t *val)
{
l3gd20h_low_odr_t low_odr;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_LOW_ODR, (uint8_t *)&low_odr, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_LOW_ODR, (uint8_t*)&low_odr, 1);
- switch (low_odr.i2c_dis){
+ switch (low_odr.i2c_dis)
+ {
case L3GD20H_I2C_ENABLE:
*val = L3GD20H_I2C_ENABLE;
break;
+
case L3GD20H_I2C_DISABLE:
*val = L3GD20H_I2C_DISABLE;
break;
+
default:
*val = L3GD20H_I2C_ENABLE;
break;
}
+
return ret;
}
/**
@@ -1044,15 +1159,17 @@ int32_t l3gd20h_pin_int2_route_set(stmdev_ctx_t *ctx,
{
l3gd20h_ctrl3_t ctrl3;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL3, (uint8_t *)&ctrl3, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL3, (uint8_t*)&ctrl3, 1);
- if(ret == 0) {
+ if (ret == 0)
+ {
ctrl3.int2_empty = val.int2_empty;
ctrl3.int2_fth = val.int2_fth;
ctrl3.int2_orun = val.int2_orun;
ctrl3.int2_drdy = val.int2_drdy;
- ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL3, (uint8_t*)&ctrl3, 1);
+ ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL3, (uint8_t *)&ctrl3, 1);
}
+
return ret;
}
@@ -1069,8 +1186,7 @@ int32_t l3gd20h_pin_int2_route_get(stmdev_ctx_t *ctx,
{
l3gd20h_ctrl3_t ctrl3;
int32_t ret;
-
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL3, (uint8_t*)&ctrl3, 1);
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL3, (uint8_t *)&ctrl3, 1);
val->int2_empty = ctrl3.int2_empty;
val->int2_orun = ctrl3.int2_orun;
val->int2_fth = ctrl3.int2_fth;
@@ -1091,12 +1207,14 @@ int32_t l3gd20h_pin_mode_set(stmdev_ctx_t *ctx, l3gd20h_pp_od_t val)
{
l3gd20h_ctrl3_t ctrl3;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL3, (uint8_t *)&ctrl3, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL3, (uint8_t*)&ctrl3, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl3.pp_od = (uint8_t)val;
- ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL3, (uint8_t*)&ctrl3, 1);
+ ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL3, (uint8_t *)&ctrl3, 1);
}
+
return ret;
}
@@ -1112,19 +1230,23 @@ int32_t l3gd20h_pin_mode_get(stmdev_ctx_t *ctx, l3gd20h_pp_od_t *val)
{
l3gd20h_ctrl3_t ctrl3;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL3, (uint8_t *)&ctrl3, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL3, (uint8_t*)&ctrl3, 1);
- switch (ctrl3.pp_od){
+ switch (ctrl3.pp_od)
+ {
case L3GD20H_PUSH_PULL:
*val = L3GD20H_PUSH_PULL;
break;
+
case L3GD20H_OPEN_DRAIN:
*val = L3GD20H_OPEN_DRAIN;
break;
+
default:
*val = L3GD20H_PUSH_PULL;
break;
}
+
return ret;
}
@@ -1136,24 +1258,31 @@ int32_t l3gd20h_pin_mode_get(stmdev_ctx_t *ctx, l3gd20h_pp_od_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t l3gd20h_pin_polarity_set(stmdev_ctx_t *ctx, l3gd20h_pin_pol_t val)
+int32_t l3gd20h_pin_polarity_set(stmdev_ctx_t *ctx,
+ l3gd20h_pin_pol_t val)
{
l3gd20h_low_odr_t low_odr;
l3gd20h_ctrl3_t ctrl3;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_LOW_ODR, (uint8_t *)&low_odr, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_LOW_ODR, (uint8_t*)&low_odr, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
low_odr.drdy_hl = (uint8_t)val;
- ret = l3gd20h_write_reg(ctx, L3GD20H_LOW_ODR, (uint8_t*)&low_odr, 1);
+ ret = l3gd20h_write_reg(ctx, L3GD20H_LOW_ODR, (uint8_t *)&low_odr, 1);
}
- if(ret == 0){
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL3, (uint8_t*)&ctrl3, 1);
+
+ if (ret == 0)
+ {
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL3, (uint8_t *)&ctrl3, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ctrl3.h_lactive = (uint8_t)val;
- ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL3, (uint8_t*)&ctrl3, 1);
+ ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL3, (uint8_t *)&ctrl3, 1);
}
+
return ret;
}
@@ -1165,23 +1294,28 @@ int32_t l3gd20h_pin_polarity_set(stmdev_ctx_t *ctx, l3gd20h_pin_pol_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t l3gd20h_pin_polarity_get(stmdev_ctx_t *ctx, l3gd20h_pin_pol_t *val)
+int32_t l3gd20h_pin_polarity_get(stmdev_ctx_t *ctx,
+ l3gd20h_pin_pol_t *val)
{
l3gd20h_ctrl3_t ctrl3;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL3, (uint8_t *)&ctrl3, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL3, (uint8_t*)&ctrl3, 1);
- switch (ctrl3.h_lactive){
+ switch (ctrl3.h_lactive)
+ {
case L3GD20H_ACTIVE_HIGH:
*val = L3GD20H_ACTIVE_HIGH;
break;
+
case L3GD20H_ACTIVE_LOW:
*val = L3GD20H_ACTIVE_LOW;
break;
+
default:
*val = L3GD20H_ACTIVE_HIGH;
break;
}
+
return ret;
}
@@ -1198,13 +1332,15 @@ int32_t l3gd20h_pin_int1_route_set(stmdev_ctx_t *ctx,
{
l3gd20h_ctrl3_t ctrl3;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL3, (uint8_t *)&ctrl3, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL3, (uint8_t*)&ctrl3, 1);
- if(ret == 0) {
+ if (ret == 0)
+ {
ctrl3.int1_boot = val.int1_boot;
ctrl3.int1_ig = val.int1_ig;
- ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL3, (uint8_t*)&ctrl3, 1);
+ ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL3, (uint8_t *)&ctrl3, 1);
}
+
return ret;
}
@@ -1221,8 +1357,7 @@ int32_t l3gd20h_pin_int1_route_get(stmdev_ctx_t *ctx,
{
l3gd20h_ctrl3_t ctrl3;
int32_t ret;
-
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL3, (uint8_t*)&ctrl3, 1);
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL3, (uint8_t *)&ctrl3, 1);
val->int1_boot = ctrl3.int1_boot;
val->int1_ig = ctrl3.int1_ig;
@@ -1237,16 +1372,19 @@ int32_t l3gd20h_pin_int1_route_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t l3gd20h_pin_notification_set(stmdev_ctx_t *ctx, l3gd20h_lir_t val)
+int32_t l3gd20h_pin_notification_set(stmdev_ctx_t *ctx,
+ l3gd20h_lir_t val)
{
l3gd20h_ig_cfg_t ig_cfg;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_IG_CFG, (uint8_t *)&ig_cfg, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_IG_CFG, (uint8_t*)&ig_cfg, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ig_cfg.lir = (uint8_t)val;
- ret = l3gd20h_write_reg(ctx, L3GD20H_IG_CFG, (uint8_t*)&ig_cfg, 1);
+ ret = l3gd20h_write_reg(ctx, L3GD20H_IG_CFG, (uint8_t *)&ig_cfg, 1);
}
+
return ret;
}
@@ -1258,24 +1396,29 @@ int32_t l3gd20h_pin_notification_set(stmdev_ctx_t *ctx, l3gd20h_lir_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t l3gd20h_pin_notification_get(stmdev_ctx_t *ctx, l3gd20h_lir_t *val)
+int32_t l3gd20h_pin_notification_get(stmdev_ctx_t *ctx,
+ l3gd20h_lir_t *val)
{
l3gd20h_ig_cfg_t ig_cfg;
int32_t ret;
-
ret = l3gd20h_read_reg(ctx, L3GD20H_IG_CFG,
- (uint8_t*)&ig_cfg, 1);
- switch (ig_cfg.lir){
+ (uint8_t *)&ig_cfg, 1);
+
+ switch (ig_cfg.lir)
+ {
case L3GD20H_INT_PULSED:
*val = L3GD20H_INT_PULSED;
break;
+
case L3GD20H_INT_LATCHED:
*val = L3GD20H_INT_LATCHED;
break;
+
default:
*val = L3GD20H_INT_PULSED;
break;
}
+
return ret;
}
@@ -1287,16 +1430,19 @@ int32_t l3gd20h_pin_notification_get(stmdev_ctx_t *ctx, l3gd20h_lir_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t l3gd20h_pin_logic_set(stmdev_ctx_t *ctx, l3gd20h_pin_logic_t val)
+int32_t l3gd20h_pin_logic_set(stmdev_ctx_t *ctx,
+ l3gd20h_pin_logic_t val)
{
l3gd20h_ig_cfg_t ig_cfg;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_IG_CFG, (uint8_t *)&ig_cfg, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_IG_CFG, (uint8_t*)&ig_cfg, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ig_cfg.and_or = (uint8_t)val;
- ret = l3gd20h_write_reg(ctx, L3GD20H_IG_CFG, (uint8_t*)&ig_cfg, 1);
+ ret = l3gd20h_write_reg(ctx, L3GD20H_IG_CFG, (uint8_t *)&ig_cfg, 1);
}
+
return ret;
}
@@ -1308,23 +1454,28 @@ int32_t l3gd20h_pin_logic_set(stmdev_ctx_t *ctx, l3gd20h_pin_logic_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t l3gd20h_pin_logic_get(stmdev_ctx_t *ctx, l3gd20h_pin_logic_t *val)
+int32_t l3gd20h_pin_logic_get(stmdev_ctx_t *ctx,
+ l3gd20h_pin_logic_t *val)
{
l3gd20h_ig_cfg_t ig_cfg;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_IG_CFG, (uint8_t *)&ig_cfg, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_IG_CFG, (uint8_t*)&ig_cfg, 1);
- switch (ig_cfg.and_or){
+ switch (ig_cfg.and_or)
+ {
case L3GD20H_LOGIC_OR:
*val = L3GD20H_LOGIC_OR;
break;
+
case L3GD20H_LOGIC_AND:
*val = L3GD20H_LOGIC_AND;
break;
+
default:
*val = L3GD20H_LOGIC_OR;
break;
}
+
return ret;
}
@@ -1355,17 +1506,19 @@ int32_t l3gd20h_gy_trshld_axis_set(stmdev_ctx_t *ctx,
{
l3gd20h_ig_cfg_t ig_cfg;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_IG_CFG, (uint8_t *)&ig_cfg, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_IG_CFG, (uint8_t*)&ig_cfg, 1);
- if(ret == 0) {
+ if (ret == 0)
+ {
ig_cfg.xlie = val.xlie;
ig_cfg.xhie = val.xhie;
ig_cfg.ylie = val.ylie;
ig_cfg.yhie = val.yhie;
ig_cfg.zlie = val.zlie;
ig_cfg.zhie = val.zhie;
- ret = l3gd20h_write_reg(ctx, L3GD20H_IG_CFG, (uint8_t*)&ig_cfg, 1);
+ ret = l3gd20h_write_reg(ctx, L3GD20H_IG_CFG, (uint8_t *)&ig_cfg, 1);
}
+
return ret;
}
@@ -1383,9 +1536,8 @@ int32_t l3gd20h_gy_trshld_axis_get(stmdev_ctx_t *ctx,
{
l3gd20h_ig_cfg_t ig_cfg;
int32_t ret;
-
ret = l3gd20h_read_reg(ctx, L3GD20H_IG_CFG,
- (uint8_t*)&ig_cfg, 1);
+ (uint8_t *)&ig_cfg, 1);
val->xlie = ig_cfg.xlie;
val->xhie = ig_cfg.xhie;
val->ylie = ig_cfg.ylie;
@@ -1409,8 +1561,7 @@ int32_t l3gd20h_gy_trshld_src_get(stmdev_ctx_t *ctx,
{
l3gd20h_ig_src_t ig_src;
int32_t ret;
-
- ret = l3gd20h_read_reg(ctx, L3GD20H_IG_SRC, (uint8_t*)&ig_src, 1);
+ ret = l3gd20h_read_reg(ctx, L3GD20H_IG_SRC, (uint8_t *)&ig_src, 1);
val->xl = ig_src.xl;
val->xh = ig_src.xh;
val->yl = ig_src.yl;
@@ -1435,18 +1586,23 @@ int32_t l3gd20h_gy_trshld_x_set(stmdev_ctx_t *ctx, uint16_t val)
l3gd20h_ig_ths_xl_t ig_ths_xl;
l3gd20h_ig_ths_xh_t ig_ths_xh;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_XH, (uint8_t *)&ig_ths_xh, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_XH, (uint8_t*)&ig_ths_xh, 1);
- if(ret == 0){
- ig_ths_xh.thsx = (uint8_t)( val / 256U ) & 0x7FU;
- ret = l3gd20h_write_reg(ctx, L3GD20H_IG_THS_XH, (uint8_t*)&ig_ths_xh, 1);
+ if (ret == 0)
+ {
+ ig_ths_xh.thsx = (uint8_t)(val / 256U) & 0x7FU;
+ ret = l3gd20h_write_reg(ctx, L3GD20H_IG_THS_XH, (uint8_t *)&ig_ths_xh, 1);
}
- if(ret == 0){
- ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_XL, (uint8_t*)&ig_ths_xl, 1);
+
+ if (ret == 0)
+ {
+ ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_XL, (uint8_t *)&ig_ths_xl, 1);
}
- if(ret == 0){
- ig_ths_xl.thsx = (uint8_t) (val - (ig_ths_xh.thsx * 256U));
- ret = l3gd20h_write_reg(ctx, L3GD20H_IG_THS_XL, (uint8_t*)&ig_ths_xl, 1);
+
+ if (ret == 0)
+ {
+ ig_ths_xl.thsx = (uint8_t)(val - (ig_ths_xh.thsx * 256U));
+ ret = l3gd20h_write_reg(ctx, L3GD20H_IG_THS_XL, (uint8_t *)&ig_ths_xl, 1);
}
return ret;
@@ -1465,16 +1621,16 @@ int32_t l3gd20h_gy_trshld_x_get(stmdev_ctx_t *ctx, uint16_t *val)
l3gd20h_ig_ths_xl_t ig_ths_xl;
l3gd20h_ig_ths_xh_t ig_ths_xh;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_XL, (uint8_t *)&ig_ths_xl, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_XL, (uint8_t*)&ig_ths_xl, 1);
- if(ret == 0){
- ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_XH, (uint8_t*)&ig_ths_xh, 1);
- *val = ig_ths_xh.thsx;
- *val = *val / 256U;
- *val += ig_ths_xl.thsx;
+ if (ret == 0)
+ {
+ ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_XH, (uint8_t *)&ig_ths_xh, 1);
+ *val = ig_ths_xh.thsx;
+ *val = *val / 256U;
+ *val += ig_ths_xl.thsx;
}
-
return ret;
}
/**
@@ -1485,16 +1641,19 @@ int32_t l3gd20h_gy_trshld_x_get(stmdev_ctx_t *ctx, uint16_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t l3gd20h_gy_trshld_mode_set(stmdev_ctx_t *ctx, l3gd20h_dcrm_g_t val)
+int32_t l3gd20h_gy_trshld_mode_set(stmdev_ctx_t *ctx,
+ l3gd20h_dcrm_g_t val)
{
l3gd20h_ig_ths_xh_t ig_ths_xh;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_XH, (uint8_t *)&ig_ths_xh, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_XH, (uint8_t*)&ig_ths_xh, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ig_ths_xh.dcrm = (uint8_t)val;
- ret = l3gd20h_write_reg(ctx, L3GD20H_IG_THS_XH, (uint8_t*)&ig_ths_xh, 1);
+ ret = l3gd20h_write_reg(ctx, L3GD20H_IG_THS_XH, (uint8_t *)&ig_ths_xh, 1);
}
+
return ret;
}
@@ -1506,23 +1665,28 @@ int32_t l3gd20h_gy_trshld_mode_set(stmdev_ctx_t *ctx, l3gd20h_dcrm_g_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t l3gd20h_gy_trshld_mode_get(stmdev_ctx_t *ctx, l3gd20h_dcrm_g_t *val)
+int32_t l3gd20h_gy_trshld_mode_get(stmdev_ctx_t *ctx,
+ l3gd20h_dcrm_g_t *val)
{
l3gd20h_ig_ths_xh_t ig_ths_xh;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_XH, (uint8_t *)&ig_ths_xh, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_XH, (uint8_t*)&ig_ths_xh, 1);
- switch (ig_ths_xh.dcrm){
+ switch (ig_ths_xh.dcrm)
+ {
case L3GD20H_RESET_MODE:
*val = L3GD20H_RESET_MODE;
break;
+
case L3GD20H_DECREMENT_MODE:
*val = L3GD20H_DECREMENT_MODE;
break;
+
default:
*val = L3GD20H_RESET_MODE;
break;
}
+
return ret;
}
@@ -1539,18 +1703,23 @@ int32_t l3gd20h_gy_trshld_y_set(stmdev_ctx_t *ctx, uint16_t val)
l3gd20h_ig_ths_yh_t ig_ths_yh;
l3gd20h_ig_ths_yl_t ig_ths_yl;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_YH, (uint8_t *)&ig_ths_yh, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_YH, (uint8_t*)&ig_ths_yh, 1);
- if(ret == 0){
- ig_ths_yh.thsy = (uint8_t)( val / 256U ) & 0x7FU;
- ret = l3gd20h_write_reg(ctx, L3GD20H_IG_THS_YH, (uint8_t*)&ig_ths_yh, 1);
+ if (ret == 0)
+ {
+ ig_ths_yh.thsy = (uint8_t)(val / 256U) & 0x7FU;
+ ret = l3gd20h_write_reg(ctx, L3GD20H_IG_THS_YH, (uint8_t *)&ig_ths_yh, 1);
}
- if(ret == 0){
- ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_YL, (uint8_t*)&ig_ths_yl, 1);
+
+ if (ret == 0)
+ {
+ ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_YL, (uint8_t *)&ig_ths_yl, 1);
}
- if(ret == 0){
- ig_ths_yl.thsy = (uint8_t) (val - (ig_ths_yh.thsy * 256U));
- ret = l3gd20h_write_reg(ctx, L3GD20H_IG_THS_YL, (uint8_t*)&ig_ths_yl, 1);
+
+ if (ret == 0)
+ {
+ ig_ths_yl.thsy = (uint8_t)(val - (ig_ths_yh.thsy * 256U));
+ ret = l3gd20h_write_reg(ctx, L3GD20H_IG_THS_YL, (uint8_t *)&ig_ths_yl, 1);
}
return ret;
@@ -1569,14 +1738,16 @@ int32_t l3gd20h_gy_trshld_y_get(stmdev_ctx_t *ctx, uint16_t *val)
l3gd20h_ig_ths_yh_t ig_ths_yh;
l3gd20h_ig_ths_yl_t ig_ths_yl;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_YL, (uint8_t *)&ig_ths_yl, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_YL, (uint8_t*)&ig_ths_yl, 1);
- if(ret == 0){
- ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_YH, (uint8_t*)&ig_ths_yh, 1);
+ if (ret == 0)
+ {
+ ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_YH, (uint8_t *)&ig_ths_yh, 1);
*val = ig_ths_yh.thsy;
*val = *val / 256U;
*val += ig_ths_yl.thsy;
}
+
return ret;
}
@@ -1593,18 +1764,23 @@ int32_t l3gd20h_gy_trshld_z_set(stmdev_ctx_t *ctx, uint16_t val)
l3gd20h_ig_ths_zh_t ig_ths_zh;
l3gd20h_ig_ths_zl_t ig_ths_zl;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_ZH, (uint8_t *)&ig_ths_zh, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_ZH, (uint8_t*)&ig_ths_zh, 1);
- if(ret == 0){
- ig_ths_zh.thsz = (uint8_t)( val / 256U ) & 0x7FU;
- ret = l3gd20h_write_reg(ctx, L3GD20H_IG_THS_ZH, (uint8_t*)&ig_ths_zh, 1);
+ if (ret == 0)
+ {
+ ig_ths_zh.thsz = (uint8_t)(val / 256U) & 0x7FU;
+ ret = l3gd20h_write_reg(ctx, L3GD20H_IG_THS_ZH, (uint8_t *)&ig_ths_zh, 1);
}
- if(ret == 0){
- ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_ZL, (uint8_t*)&ig_ths_zl, 1);
+
+ if (ret == 0)
+ {
+ ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_ZL, (uint8_t *)&ig_ths_zl, 1);
}
- if(ret == 0){
- ig_ths_zl.thsz = (uint8_t) (val - (ig_ths_zh.thsz * 256U));
- ret = l3gd20h_write_reg(ctx, L3GD20H_IG_THS_ZL, (uint8_t*)&ig_ths_zl, 1);
+
+ if (ret == 0)
+ {
+ ig_ths_zl.thsz = (uint8_t)(val - (ig_ths_zh.thsz * 256U));
+ ret = l3gd20h_write_reg(ctx, L3GD20H_IG_THS_ZL, (uint8_t *)&ig_ths_zl, 1);
}
return ret;
@@ -1623,14 +1799,16 @@ int32_t l3gd20h_gy_trshld_z_get(stmdev_ctx_t *ctx, uint16_t *val)
l3gd20h_ig_ths_zh_t ig_ths_zh;
l3gd20h_ig_ths_zl_t ig_ths_zl;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_ZL, (uint8_t *)&ig_ths_zl, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_ZL, (uint8_t*)&ig_ths_zl, 1);
- if(ret == 0){
- ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_ZH, (uint8_t*)&ig_ths_zh, 1);
+ if (ret == 0)
+ {
+ ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_ZH, (uint8_t *)&ig_ths_zh, 1);
*val = ig_ths_zh.thsz;
*val = *val / 256U;
*val += ig_ths_zh.thsz;
}
+
return ret;
}
@@ -1642,23 +1820,32 @@ int32_t l3gd20h_gy_trshld_z_get(stmdev_ctx_t *ctx, uint16_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t l3gd20h_gy_trshld_min_sample_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t l3gd20h_gy_trshld_min_sample_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
l3gd20h_ig_duration_t ig_duration;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_IG_DURATION,
+ (uint8_t *)&ig_duration, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_IG_DURATION, (uint8_t*)&ig_duration, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ig_duration.d = val;
- if (val != 0x00U){
+
+ if (val != 0x00U)
+ {
ig_duration.wait = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
ig_duration.wait = PROPERTY_DISABLE;
}
+
ret = l3gd20h_write_reg(ctx, L3GD20H_IG_DURATION,
- (uint8_t*)&ig_duration, 1);
+ (uint8_t *)&ig_duration, 1);
}
+
return ret;
}
@@ -1670,12 +1857,13 @@ int32_t l3gd20h_gy_trshld_min_sample_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t l3gd20h_gy_trshld_min_sample_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t l3gd20h_gy_trshld_min_sample_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
l3gd20h_ig_duration_t ig_duration;
int32_t ret;
-
- ret = l3gd20h_read_reg(ctx, L3GD20H_IG_DURATION, (uint8_t*)&ig_duration, 1);
+ ret = l3gd20h_read_reg(ctx, L3GD20H_IG_DURATION,
+ (uint8_t *)&ig_duration, 1);
*val = ig_duration.d;
return ret;
@@ -1705,12 +1893,14 @@ int32_t l3gd20h_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
{
l3gd20h_ctrl5_t ctrl5;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t*)&ctrl5, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl5.stoponfth = val;
- ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL5, (uint8_t*)&ctrl5, 1);
+ ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1);
}
+
return ret;
}
@@ -1726,8 +1916,7 @@ int32_t l3gd20h_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
{
l3gd20h_ctrl5_t ctrl5;
int32_t ret;
-
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t*)&ctrl5, 1);
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1);
*val = ctrl5.stoponfth;
return ret;
@@ -1745,19 +1934,25 @@ int32_t l3gd20h_fifo_mode_set(stmdev_ctx_t *ctx, l3gd20h_fifo_m_t val)
l3gd20h_ctrl5_t ctrl5;
l3gd20h_fifo_ctrl_t fifo_ctrl;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
- if(ret == 0){
- fifo_ctrl.fm = ( (uint8_t)val & 0x07U );
- ret = l3gd20h_write_reg(ctx, L3GD20H_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
+ if (ret == 0)
+ {
+ fifo_ctrl.fm = ((uint8_t)val & 0x07U);
+ ret = l3gd20h_write_reg(ctx, L3GD20H_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
}
- if(ret == 0){
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t*)&ctrl5, 1);
+
+ if (ret == 0)
+ {
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1);
}
- if(ret == 0){
- ctrl5.fifo_en = ( ( (uint8_t)val & 0x10U ) >> 4);
- ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL5, (uint8_t*)&ctrl5, 1);
+
+ if (ret == 0)
+ {
+ ctrl5.fifo_en = (((uint8_t)val & 0x10U) >> 4);
+ ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1);
}
+
return ret;
}
@@ -1769,39 +1964,50 @@ int32_t l3gd20h_fifo_mode_set(stmdev_ctx_t *ctx, l3gd20h_fifo_m_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t l3gd20h_fifo_mode_get(stmdev_ctx_t *ctx, l3gd20h_fifo_m_t *val)
+int32_t l3gd20h_fifo_mode_get(stmdev_ctx_t *ctx,
+ l3gd20h_fifo_m_t *val)
{
l3gd20h_ctrl5_t ctrl5;
l3gd20h_fifo_ctrl_t fifo_ctrl;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
- if(ret == 0){
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t*)&ctrl5, 1);
+ if (ret == 0)
+ {
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1);
}
- switch ((ctrl5.fifo_en << 4) + fifo_ctrl.fm) {
+
+ switch ((ctrl5.fifo_en << 4) + fifo_ctrl.fm)
+ {
case L3GD20H_BYPASS_MODE:
*val = L3GD20H_BYPASS_MODE;
break;
+
case L3GD20H_FIFO_MODE:
*val = L3GD20H_FIFO_MODE;
break;
+
case L3GD20H_STREAM_MODE:
*val = L3GD20H_STREAM_MODE;
break;
+
case L3GD20H_STREAM_TO_FIFO_MODE:
*val = L3GD20H_STREAM_TO_FIFO_MODE;
break;
+
case L3GD20H_BYPASS_TO_STREAM_MODE:
*val = L3GD20H_BYPASS_TO_STREAM_MODE;
break;
+
case L3GD20H_BYPASS_TO_FIFO_MODE:
*val = L3GD20H_BYPASS_TO_FIFO_MODE;
break;
+
default:
*val = L3GD20H_BYPASS_MODE;
break;
}
+
return ret;
}
/**
@@ -1816,12 +2022,14 @@ int32_t l3gd20h_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
{
l3gd20h_fifo_ctrl_t fifo_ctrl;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
fifo_ctrl.fth = val;
- ret = l3gd20h_write_reg(ctx, L3GD20H_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
+ ret = l3gd20h_write_reg(ctx, L3GD20H_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
}
+
return ret;
}
@@ -1837,8 +2045,7 @@ int32_t l3gd20h_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
{
l3gd20h_fifo_ctrl_t fifo_ctrl;
int32_t ret;
-
- ret = l3gd20h_read_reg(ctx, L3GD20H_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
+ ret = l3gd20h_read_reg(ctx, L3GD20H_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
*val = fifo_ctrl.fth;
return ret;
@@ -1852,12 +2059,12 @@ int32_t l3gd20h_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t l3gd20h_fifo_src_get(stmdev_ctx_t *ctx, l3gd20h_fifo_srs_t *val)
+int32_t l3gd20h_fifo_src_get(stmdev_ctx_t *ctx,
+ l3gd20h_fifo_srs_t *val)
{
l3gd20h_fifo_src_t fifo_src;
int32_t ret;
-
- ret = l3gd20h_read_reg(ctx, L3GD20H_FIFO_SRC, (uint8_t*)&fifo_src, 1);
+ ret = l3gd20h_read_reg(ctx, L3GD20H_FIFO_SRC, (uint8_t *)&fifo_src, 1);
val->fss = fifo_src.fss;
val->empty = fifo_src.empty;
val->ovrn = fifo_src.ovrn;
@@ -1878,8 +2085,7 @@ int32_t l3gd20h_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val)
{
l3gd20h_fifo_src_t fifo_src;
int32_t ret;
-
- ret = l3gd20h_read_reg(ctx, L3GD20H_FIFO_SRC, (uint8_t*)&fifo_src, 1);
+ ret = l3gd20h_read_reg(ctx, L3GD20H_FIFO_SRC, (uint8_t *)&fifo_src, 1);
*val = fifo_src.fss;
return ret;
@@ -1897,8 +2103,7 @@ int32_t l3gd20h_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
{
l3gd20h_fifo_src_t fifo_src;
int32_t ret;
-
- ret = l3gd20h_read_reg(ctx, L3GD20H_FIFO_SRC, (uint8_t*)&fifo_src, 1);
+ ret = l3gd20h_read_reg(ctx, L3GD20H_FIFO_SRC, (uint8_t *)&fifo_src, 1);
*val = fifo_src.fss;
return ret;
@@ -1916,8 +2121,7 @@ int32_t l3gd20h_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
{
l3gd20h_fifo_src_t fifo_src;
int32_t ret;
-
- ret = l3gd20h_read_reg(ctx, L3GD20H_FIFO_SRC, (uint8_t*)&fifo_src, 1);
+ ret = l3gd20h_read_reg(ctx, L3GD20H_FIFO_SRC, (uint8_t *)&fifo_src, 1);
*val = fifo_src.fth;
return ret;
@@ -1948,20 +2152,26 @@ int32_t l3gd20h_den_mode_set(stmdev_ctx_t *ctx, l3gd20h_den_md_t val)
l3gd20h_ctrl2_t ctrl2;
l3gd20h_ctrl4_t ctrl4;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t*)&ctrl4, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl4.impen = (uint8_t)val & 0x01U;
- ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL4, (uint8_t*)&ctrl4, 1);
+ ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
}
- if(ret == 0){
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL2, (uint8_t*)&ctrl2, 1);
+
+ if (ret == 0)
+ {
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL2, (uint8_t *)&ctrl2, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ctrl2.lvlen = ((uint8_t)val & 0x04U) >> 2;
ctrl2.extren = ((uint8_t)val & 0x02U) >> 1;
- ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL2, (uint8_t*)&ctrl2, 1);
+ ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL2, (uint8_t *)&ctrl2, 1);
}
+
return ret;
}
@@ -1978,28 +2188,36 @@ int32_t l3gd20h_den_mode_get(stmdev_ctx_t *ctx, l3gd20h_den_md_t *val)
l3gd20h_ctrl2_t ctrl2;
l3gd20h_ctrl4_t ctrl4;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t*)&ctrl4, 1);
- if(ret == 0){
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL2, (uint8_t*)&ctrl2, 1);
+ if (ret == 0)
+ {
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL2, (uint8_t *)&ctrl2, 1);
}
- switch ( (ctrl2.lvlen << 2) + (ctrl2.extren << 1) + ctrl4.impen ){
+
+ switch ((ctrl2.lvlen << 2) + (ctrl2.extren << 1) + ctrl4.impen)
+ {
case L3GD20H_DEN_DISABLE:
*val = L3GD20H_DEN_DISABLE;
break;
+
case L3GD20H_DEN_ON_LEVEL_TRIGGER:
*val = L3GD20H_DEN_ON_LEVEL_TRIGGER;
break;
+
case L3GD20H_DEN_ON_EDGE_TRIGGER:
*val = L3GD20H_DEN_ON_EDGE_TRIGGER;
break;
+
case L3GD20H_DEN_IMPULSE_TRIGGER:
*val = L3GD20H_DEN_IMPULSE_TRIGGER;
break;
+
default:
*val = L3GD20H_DEN_DISABLE;
break;
}
+
return ret;
}
@@ -2028,12 +2246,14 @@ int32_t l3gd20h_gy_self_test_set(stmdev_ctx_t *ctx, l3gd20h_st_t val)
{
l3gd20h_ctrl4_t ctrl4;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t*)&ctrl4, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl4.st = (uint8_t)val;
- ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL4, (uint8_t*)&ctrl4, 1);
+ ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
}
+
return ret;
}
@@ -2049,22 +2269,27 @@ int32_t l3gd20h_gy_self_test_get(stmdev_ctx_t *ctx, l3gd20h_st_t *val)
{
l3gd20h_ctrl4_t ctrl4;
int32_t ret;
+ ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
- ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t*)&ctrl4, 1);
- switch (ctrl4.st){
+ switch (ctrl4.st)
+ {
case L3GD20H_ST_DISABLE:
*val = L3GD20H_ST_DISABLE;
break;
+
case L3GD20H_ST_POSITIVE:
*val = L3GD20H_ST_POSITIVE;
break;
+
case L3GD20H_ST_NEGATIVE:
*val = L3GD20H_ST_NEGATIVE;
break;
+
default:
*val = L3GD20H_ST_DISABLE;
break;
}
+
return ret;
}
diff --git a/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.h b/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.h
index 3fe5a387b8f95b90b50b1548ee038701ea02cd9d..6172620d079ac7a7eb4423cbbb5c57e97d74f849 100644
--- a/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.h
+++ b/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.h
@@ -1,29 +1,29 @@
-/*
- ******************************************************************************
- * @file l3gd20h_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * l3gd20h_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file l3gd20h_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * l3gd20h_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef L3GD20H_REGS_H
#define L3GD20H_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -75,7 +75,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -108,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -132,7 +134,7 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
+ * You can create a sensor configuration by your own or using
* Unico / Unicleo tools available on STMicroelectronics
* web site.
*
@@ -140,7 +142,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -176,7 +179,8 @@ typedef struct {
#define L3GD20H_WHO_AM_I 0x0FU
#define L3GD20H_CTRL1 0x20U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xen : 1;
uint8_t yen : 1;
@@ -195,7 +199,8 @@ typedef struct {
} l3gd20h_ctrl1_t;
#define L3GD20H_CTRL2 0x21U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t hpcf : 4;
uint8_t hpm : 2;
@@ -210,7 +215,8 @@ typedef struct {
} l3gd20h_ctrl2_t;
#define L3GD20H_CTRL3 0x22U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_empty : 1;
uint8_t int2_orun : 1;
@@ -233,7 +239,8 @@ typedef struct {
} l3gd20h_ctrl3_t;
#define L3GD20H_CTRL4 0x23U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t st : 2;
@@ -252,7 +259,8 @@ typedef struct {
} l3gd20h_ctrl4_t;
#define L3GD20H_CTRL5 0x24U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t out_sel : 2;
uint8_t ig_sel : 2;
@@ -273,7 +281,8 @@ typedef struct {
#define L3GD20H_REFERENCE 0x25U
#define L3GD20H_OUT_TEMP 0x26U
#define L3GD20H_STATUS 0x27U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xda : 1;
uint8_t yda : 1;
@@ -302,7 +311,8 @@ typedef struct {
#define L3GD20H_OUT_Z_L 0x2CU
#define L3GD20H_OUT_Z_H 0x2DU
#define L3GD20H_FIFO_CTRL 0x2EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fth : 5;
uint8_t fm : 3;
@@ -313,7 +323,8 @@ typedef struct {
} l3gd20h_fifo_ctrl_t;
#define L3GD20H_FIFO_SRC 0x2FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fss : 5;
uint8_t empty : 1;
@@ -328,7 +339,8 @@ typedef struct {
} l3gd20h_fifo_src_t;
#define L3GD20H_IG_CFG 0x30U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlie : 1;
uint8_t xhie : 1;
@@ -351,7 +363,8 @@ typedef struct {
} l3gd20h_ig_cfg_t;
#define L3GD20H_IG_SRC 0x31U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
@@ -374,7 +387,8 @@ typedef struct {
} l3gd20h_ig_src_t;
#define L3GD20H_IG_THS_XH 0x32U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t thsx : 7;
uint8_t dcrm : 1;
@@ -385,12 +399,14 @@ typedef struct {
} l3gd20h_ig_ths_xh_t;
#define L3GD20H_IG_THS_XL 0x33U
-typedef struct {
+typedef struct
+{
uint8_t thsx : 8;
} l3gd20h_ig_ths_xl_t;
#define L3GD20H_IG_THS_YH 0x34U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t thsy : 7;
uint8_t not_used_01 : 1;
@@ -401,12 +417,14 @@ typedef struct {
} l3gd20h_ig_ths_yh_t;
#define L3GD20H_IG_THS_YL 0x35U
-typedef struct {
+typedef struct
+{
uint8_t thsy : 8;
} l3gd20h_ig_ths_yl_t;
#define L3GD20H_IG_THS_ZH 0x36U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t thsz : 7;
uint8_t not_used_01 : 1;
@@ -417,12 +435,14 @@ typedef struct {
} l3gd20h_ig_ths_zh_t;
#define L3GD20H_IG_THS_ZL 0x37U
-typedef struct {
+typedef struct
+{
uint8_t thsz : 8;
} l3gd20h_ig_ths_zl_t;
#define L3GD20H_IG_DURATION 0x38U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d : 7;
uint8_t wait : 1;
@@ -433,7 +453,8 @@ typedef struct {
} l3gd20h_ig_duration_t;
#define L3GD20H_LOW_ODR 0x39U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t low_odr : 1;
uint8_t not_used_01 : 1;
@@ -455,9 +476,9 @@ typedef struct {
/**
* @defgroup L3GD20H_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -465,7 +486,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
l3gd20h_ctrl1_t ctrl1;
l3gd20h_ctrl2_t ctrl2;
l3gd20h_ctrl3_t ctrl3;
@@ -493,9 +515,11 @@ typedef union{
*
*/
-int32_t l3gd20h_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t l3gd20h_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t l3gd20h_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t l3gd20h_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
float_t l3gd20h_from_fs245_to_mdps(int16_t lsb);
@@ -504,15 +528,18 @@ float_t l3gd20h_from_fs2000_to_mdps(int16_t lsb);
float_t l3gd20h_from_lsb_to_celsius(int16_t lsb);
-typedef struct {
+typedef struct
+{
uint8_t xen : 1;
uint8_t yen : 1;
uint8_t zen : 1;
} l3gd20h_gy_axis_t;
int32_t l3gd20h_gy_axis_set(stmdev_ctx_t *ctx, l3gd20h_gy_axis_t val);
-int32_t l3gd20h_gy_axis_get(stmdev_ctx_t *ctx, l3gd20h_gy_axis_t *val);
+int32_t l3gd20h_gy_axis_get(stmdev_ctx_t *ctx,
+ l3gd20h_gy_axis_t *val);
-typedef enum {
+typedef enum
+{
L3GD20H_POWER_DOWN = 0x00,
L3GD20H_12Hz5 = 0x90,
L3GD20H_25Hz = 0x91,
@@ -522,24 +549,29 @@ typedef enum {
L3GD20H_400Hz = 0x82,
L3GD20H_800Hz = 0x83,
} l3gd20h_gy_data_rate_t;
-int32_t l3gd20h_gy_data_rate_set(stmdev_ctx_t *ctx,
+int32_t l3gd20h_gy_data_rate_set(stmdev_ctx_t *ctx,
l3gd20h_gy_data_rate_t val);
int32_t l3gd20h_gy_data_rate_get(stmdev_ctx_t *ctx,
l3gd20h_gy_data_rate_t *val);
-typedef enum {
+typedef enum
+{
L3GD20H_245dps = 0x00,
L3GD20H_500dps = 0x01,
L3GD20H_2000dps = 0x02,
} l3gd20h_gy_fs_t;
-int32_t l3gd20h_gy_full_scale_set(stmdev_ctx_t *ctx, l3gd20h_gy_fs_t val);
-int32_t l3gd20h_gy_full_scale_get(stmdev_ctx_t *ctx, l3gd20h_gy_fs_t *val);
+int32_t l3gd20h_gy_full_scale_set(stmdev_ctx_t *ctx,
+ l3gd20h_gy_fs_t val);
+int32_t l3gd20h_gy_full_scale_get(stmdev_ctx_t *ctx,
+ l3gd20h_gy_fs_t *val);
int32_t l3gd20h_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t l3gd20h_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t l3gd20h_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t l3gd20h_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t l3gd20h_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t l3gd20h_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
@@ -547,17 +579,21 @@ int32_t l3gd20h_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val);
int32_t l3gd20h_dev_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
-typedef enum {
+typedef enum
+{
L3GD20H_LSB_LOW_ADDRESS = 0,
L3GD20H_MSB_LOW_ADDRESS = 1,
} l3gd20h_ble_t;
-int32_t l3gd20h_dev_data_format_set(stmdev_ctx_t *ctx, l3gd20h_ble_t val);
-int32_t l3gd20h_dev_data_format_get(stmdev_ctx_t *ctx, l3gd20h_ble_t *val);
+int32_t l3gd20h_dev_data_format_set(stmdev_ctx_t *ctx,
+ l3gd20h_ble_t val);
+int32_t l3gd20h_dev_data_format_get(stmdev_ctx_t *ctx,
+ l3gd20h_ble_t *val);
int32_t l3gd20h_dev_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t l3gd20h_dev_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef struct {
+typedef struct
+{
uint8_t xda : 1;
uint8_t yda : 1;
uint8_t zda : 1;
@@ -573,7 +609,8 @@ int32_t l3gd20h_dev_status_get(stmdev_ctx_t *ctx,
int32_t l3gd20h_dev_reset_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t l3gd20h_dev_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
L3GD20H_16Hz6_USE_ODR_50Hz = 0xA0,
L3GD20H_12Hz5_USE_ODR_100Hz = 0x00,
L3GD20H_25Hz_USE_ODR_100Hz = 0x01,
@@ -592,7 +629,8 @@ int32_t l3gd20h_gy_filter_lp_bandwidth_set(stmdev_ctx_t *ctx,
int32_t l3gd20h_gy_filter_lp_bandwidth_get(stmdev_ctx_t *ctx,
l3gd20h_lpbw_t *val);
-typedef enum {
+typedef enum
+{
L3GD20H_NORMAL_MODE_LIGHT = 0x00,
L3GD20H_NORMAL_MODE_NORMAL = 0x01,
L3GD20H_NORMAL_MODE_STRONG = 0x02,
@@ -611,7 +649,8 @@ int32_t l3gd20h_gy_filter_hp_bandwidth_set(stmdev_ctx_t *ctx,
int32_t l3gd20h_gy_filter_hp_bandwidth_get(stmdev_ctx_t *ctx,
l3gd20h_gy_hp_bw_t *val);
-typedef enum {
+typedef enum
+{
L3GD20H_LPF1_OUT = 0x00,
L3GD20H_LPF1_HPF_OUT = 0x11,
L3GD20H_LPF1_LPF2_OUT = 0x02,
@@ -621,7 +660,8 @@ int32_t l3gd20h_gy_filter_out_path_set(stmdev_ctx_t *ctx,
l3gd20h_gy_out_path_t val);
int32_t l3gd20h_gy_filter_out_path_get(stmdev_ctx_t *ctx,
l3gd20h_gy_out_path_t *val);
-typedef enum {
+typedef enum
+{
L3GD20H_LPF1_INT = 0x00,
L3GD20H_LPF1_HPF_INT = 0x11,
L3GD20H_LPF1_LPF2_INT = 0x02,
@@ -632,17 +672,21 @@ int32_t l3gd20h_gy_filter_int_path_set(stmdev_ctx_t *ctx,
int32_t l3gd20h_gy_filter_int_path_get(stmdev_ctx_t *ctx,
l3gd20h_gy_int_path_t *val);
-int32_t l3gd20h_gy_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t l3gd20h_gy_filter_reference_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t l3gd20h_gy_filter_reference_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t l3gd20h_gy_filter_reference_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
-typedef enum {
+typedef enum
+{
L3GD20H_SPI_4_WIRE = 0,
L3GD20H_SPI_3_WIRE = 1,
} l3gd20h_sim_t;
int32_t l3gd20h_spi_mode_set(stmdev_ctx_t *ctx, l3gd20h_sim_t val);
int32_t l3gd20h_spi_mode_get(stmdev_ctx_t *ctx, l3gd20h_sim_t *val);
-typedef enum {
+typedef enum
+{
L3GD20H_I2C_ENABLE = 0,
L3GD20H_I2C_DISABLE = 1,
} l3gd20h_i2c_dis_t;
@@ -651,7 +695,8 @@ int32_t l3gd20h_i2c_interface_set(stmdev_ctx_t *ctx,
int32_t l3gd20h_i2c_interface_get(stmdev_ctx_t *ctx,
l3gd20h_i2c_dis_t *val);
-typedef struct {
+typedef struct
+{
uint8_t int2_empty : 1;
uint8_t int2_orun : 1;
uint8_t int2_fth : 1;
@@ -662,21 +707,26 @@ int32_t l3gd20h_pin_int2_route_set(stmdev_ctx_t *ctx,
int32_t l3gd20h_pin_int2_route_get(stmdev_ctx_t *ctx,
l3gd20h_pin_int2_rt_t *val);
-typedef enum {
+typedef enum
+{
L3GD20H_PUSH_PULL = 0,
L3GD20H_OPEN_DRAIN = 1,
} l3gd20h_pp_od_t;
int32_t l3gd20h_pin_mode_set(stmdev_ctx_t *ctx, l3gd20h_pp_od_t val);
int32_t l3gd20h_pin_mode_get(stmdev_ctx_t *ctx, l3gd20h_pp_od_t *val);
-typedef enum {
+typedef enum
+{
L3GD20H_ACTIVE_HIGH = 0,
L3GD20H_ACTIVE_LOW = 1,
} l3gd20h_pin_pol_t;
-int32_t l3gd20h_pin_polarity_set(stmdev_ctx_t *ctx, l3gd20h_pin_pol_t val);
-int32_t l3gd20h_pin_polarity_get(stmdev_ctx_t *ctx, l3gd20h_pin_pol_t *val);
+int32_t l3gd20h_pin_polarity_set(stmdev_ctx_t *ctx,
+ l3gd20h_pin_pol_t val);
+int32_t l3gd20h_pin_polarity_get(stmdev_ctx_t *ctx,
+ l3gd20h_pin_pol_t *val);
-typedef struct {
+typedef struct
+{
uint8_t int1_boot : 1;
uint8_t int1_ig : 1;
} l3gd20h_pin_int1_rt_t;
@@ -685,20 +735,27 @@ int32_t l3gd20h_pin_int1_route_set(stmdev_ctx_t *ctx,
int32_t l3gd20h_pin_int1_route_get(stmdev_ctx_t *ctx,
l3gd20h_pin_int1_rt_t *val);
-typedef enum {
+typedef enum
+{
L3GD20H_INT_PULSED = 0,
L3GD20H_INT_LATCHED = 1,
} l3gd20h_lir_t;
-int32_t l3gd20h_pin_notification_set(stmdev_ctx_t *ctx, l3gd20h_lir_t val);
-int32_t l3gd20h_pin_notification_get(stmdev_ctx_t *ctx, l3gd20h_lir_t *val);
-typedef enum {
+int32_t l3gd20h_pin_notification_set(stmdev_ctx_t *ctx,
+ l3gd20h_lir_t val);
+int32_t l3gd20h_pin_notification_get(stmdev_ctx_t *ctx,
+ l3gd20h_lir_t *val);
+typedef enum
+{
L3GD20H_LOGIC_OR = 0,
L3GD20H_LOGIC_AND = 1,
} l3gd20h_pin_logic_t;
-int32_t l3gd20h_pin_logic_set(stmdev_ctx_t *ctx, l3gd20h_pin_logic_t val);
-int32_t l3gd20h_pin_logic_get(stmdev_ctx_t *ctx, l3gd20h_pin_logic_t *val);
+int32_t l3gd20h_pin_logic_set(stmdev_ctx_t *ctx,
+ l3gd20h_pin_logic_t val);
+int32_t l3gd20h_pin_logic_get(stmdev_ctx_t *ctx,
+ l3gd20h_pin_logic_t *val);
-typedef struct {
+typedef struct
+{
uint8_t xlie : 1;
uint8_t xhie : 1;
uint8_t ylie : 1;
@@ -711,7 +768,8 @@ int32_t l3gd20h_gy_trshld_axis_set(stmdev_ctx_t *ctx,
int32_t l3gd20h_gy_trshld_axis_get(stmdev_ctx_t *ctx,
l3gd20h_gy_trshld_en_t *val);
-typedef struct {
+typedef struct
+{
uint8_t xl : 1;
uint8_t xh : 1;
uint8_t yl : 1;
@@ -726,7 +784,8 @@ int32_t l3gd20h_gy_trshld_src_get(stmdev_ctx_t *ctx,
int32_t l3gd20h_gy_trshld_x_set(stmdev_ctx_t *ctx, uint16_t val);
int32_t l3gd20h_gy_trshld_x_get(stmdev_ctx_t *ctx, uint16_t *val);
-typedef enum {
+typedef enum
+{
L3GD20H_RESET_MODE = 0x00,
L3GD20H_DECREMENT_MODE = 0x01,
} l3gd20h_dcrm_g_t;
@@ -741,13 +800,16 @@ int32_t l3gd20h_gy_trshld_y_get(stmdev_ctx_t *ctx, uint16_t *val);
int32_t l3gd20h_gy_trshld_z_set(stmdev_ctx_t *ctx, uint16_t val);
int32_t l3gd20h_gy_trshld_z_get(stmdev_ctx_t *ctx, uint16_t *val);
-int32_t l3gd20h_gy_trshld_min_sample_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t l3gd20h_gy_trshld_min_sample_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t l3gd20h_gy_trshld_min_sample_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t l3gd20h_gy_trshld_min_sample_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t l3gd20h_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t l3gd20h_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
L3GD20H_BYPASS_MODE = 0x00,
L3GD20H_FIFO_MODE = 0x11,
L3GD20H_STREAM_MODE = 0x12,
@@ -756,19 +818,23 @@ typedef enum {
L3GD20H_DYNAMIC_STREAM_MODE = 0x16,
L3GD20H_BYPASS_TO_FIFO_MODE = 0x17,
} l3gd20h_fifo_m_t;
-int32_t l3gd20h_fifo_mode_set(stmdev_ctx_t *ctx, l3gd20h_fifo_m_t val);
-int32_t l3gd20h_fifo_mode_get(stmdev_ctx_t *ctx, l3gd20h_fifo_m_t *val);
+int32_t l3gd20h_fifo_mode_set(stmdev_ctx_t *ctx,
+ l3gd20h_fifo_m_t val);
+int32_t l3gd20h_fifo_mode_get(stmdev_ctx_t *ctx,
+ l3gd20h_fifo_m_t *val);
int32_t l3gd20h_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t l3gd20h_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef struct {
+typedef struct
+{
uint8_t fss : 1;
uint8_t empty : 1;
uint8_t ovrn : 1;
uint8_t fth : 1;
} l3gd20h_fifo_srs_t;
-int32_t l3gd20h_fifo_src_get(stmdev_ctx_t *ctx, l3gd20h_fifo_srs_t *val);
+int32_t l3gd20h_fifo_src_get(stmdev_ctx_t *ctx,
+ l3gd20h_fifo_srs_t *val);
int32_t l3gd20h_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -776,22 +842,26 @@ int32_t l3gd20h_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t l3gd20h_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
L3GD20H_DEN_DISABLE = 0x00,
L3GD20H_DEN_ON_LEVEL_TRIGGER = 0x04,
L3GD20H_DEN_ON_EDGE_TRIGGER = 0x02,
L3GD20H_DEN_IMPULSE_TRIGGER = 0x05,
} l3gd20h_den_md_t;
int32_t l3gd20h_den_mode_set(stmdev_ctx_t *ctx, l3gd20h_den_md_t val);
-int32_t l3gd20h_den_mode_get(stmdev_ctx_t *ctx, l3gd20h_den_md_t *val);
+int32_t l3gd20h_den_mode_get(stmdev_ctx_t *ctx,
+ l3gd20h_den_md_t *val);
-typedef enum {
+typedef enum
+{
L3GD20H_ST_DISABLE = 0x00,
L3GD20H_ST_POSITIVE = 0x01,
L3GD20H_ST_NEGATIVE = 0x03,
} l3gd20h_st_t;
int32_t l3gd20h_gy_self_test_set(stmdev_ctx_t *ctx, l3gd20h_st_t val);
-int32_t l3gd20h_gy_self_test_get(stmdev_ctx_t *ctx, l3gd20h_st_t *val);
+int32_t l3gd20h_gy_self_test_get(stmdev_ctx_t *ctx,
+ l3gd20h_st_t *val);
/**
*@}
diff --git a/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.c b/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.c
index abd8a586705443de6ae115fcc630e1b93413e647..1e8956aabe85d01c855c8f0b0e15fd35020d705b 100644
--- a/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.c
+++ b/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file lis25ba_reg.c
- * @author Sensors Software Solution Team
- * @brief LIS25BA driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lis25ba_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LIS25BA driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lis25ba_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis25ba_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lis25ba_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t lis25ba_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis25ba_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lis25ba_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -86,7 +92,8 @@ int32_t lis25ba_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
static void bytecpy(uint8_t *target, uint8_t *source)
{
- if ( (target != NULL) && (source != NULL) ) {
+ if ((target != NULL) && (source != NULL))
+ {
*target = *source;
}
}
@@ -133,8 +140,9 @@ int32_t lis25ba_id_get(stmdev_ctx_t *ctx, lis25ba_id_t *val)
{
int32_t ret = 0;
- if (ctx != NULL){
- ret = lis25ba_read_reg(ctx, LIS25BA_WHO_AM_I, (uint8_t*)&(val->id), 1);
+ if (ctx != NULL)
+ {
+ ret = lis25ba_read_reg(ctx, LIS25BA_WHO_AM_I, (uint8_t *) & (val->id), 1);
}
return ret;
@@ -149,7 +157,8 @@ int32_t lis25ba_id_get(stmdev_ctx_t *ctx, lis25ba_id_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis25ba_bus_mode_set(stmdev_ctx_t *ctx, lis25ba_bus_mode_t *val)
+int32_t lis25ba_bus_mode_set(stmdev_ctx_t *ctx,
+ lis25ba_bus_mode_t *val)
{
lis25ba_tdm_ctrl_reg_t tdm_ctrl_reg;
lis25ba_tdm_cmax_h_t tdm_cmax_h;
@@ -158,28 +167,31 @@ int32_t lis25ba_bus_mode_set(stmdev_ctx_t *ctx, lis25ba_bus_mode_t *val)
int32_t ret;
ret = lis25ba_read_reg(ctx, LIS25BA_TDM_CTRL_REG,
- (uint8_t*)&tdm_ctrl_reg, 1);
- if (ret == 0) {
+ (uint8_t *)&tdm_ctrl_reg, 1);
+
+ if (ret == 0)
+ {
ret = lis25ba_read_reg(ctx, LIS25BA_TDM_CMAX_H, reg, 2);
- bytecpy( (uint8_t*)&tdm_cmax_h, ®[0] );
- bytecpy( (uint8_t*)&tdm_cmax_l, ®[1] );
+ bytecpy((uint8_t *)&tdm_cmax_h, ®[0]);
+ bytecpy((uint8_t *)&tdm_cmax_l, ®[1]);
+ tdm_ctrl_reg.tdm_pd = ~val->tdm.en;
+ tdm_ctrl_reg.data_valid = val->tdm.clk_pol;
+ tdm_ctrl_reg.delayed = val->tdm.clk_edge;
+ tdm_ctrl_reg.wclk_fq = val->tdm.mapping;
+ tdm_cmax_h.tdm_cmax = (uint8_t)(val->tdm.cmax / 256U);
+ tdm_cmax_l.tdm_cmax = (uint8_t)(val->tdm.cmax - tdm_cmax_h.tdm_cmax);
}
- tdm_ctrl_reg.tdm_pd = ~val->tdm.en;
- tdm_ctrl_reg.data_valid = val->tdm.clk_pol;
- tdm_ctrl_reg.delayed = val->tdm.clk_edge;
- tdm_ctrl_reg.wclk_fq = val->tdm.mapping;
-
- tdm_cmax_h.tdm_cmax = (uint8_t)(val->tdm.cmax / 256U);
- tdm_cmax_l.tdm_cmax = (uint8_t)(val->tdm.cmax - tdm_cmax_h.tdm_cmax);
-
- if ( ret == 0 ) {
+ if (ret == 0)
+ {
ret = lis25ba_write_reg(ctx, LIS25BA_TDM_CTRL_REG,
- (uint8_t*)&tdm_ctrl_reg, 1);
+ (uint8_t *)&tdm_ctrl_reg, 1);
}
- bytecpy(®[0], ( uint8_t*)&tdm_cmax_h);
- bytecpy(®[1], ( uint8_t*)&tdm_cmax_l);
- if ( ret == 0 ) {
+
+ if (ret == 0)
+ {
+ bytecpy(®[0], (uint8_t *)&tdm_cmax_h);
+ bytecpy(®[1], (uint8_t *)&tdm_cmax_l);
ret = lis25ba_write_reg(ctx, LIS25BA_TDM_CMAX_H, reg, 2);
}
@@ -195,7 +207,8 @@ int32_t lis25ba_bus_mode_set(stmdev_ctx_t *ctx, lis25ba_bus_mode_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis25ba_bus_mode_get(stmdev_ctx_t *ctx, lis25ba_bus_mode_t *val)
+int32_t lis25ba_bus_mode_get(stmdev_ctx_t *ctx,
+ lis25ba_bus_mode_t *val)
{
lis25ba_tdm_ctrl_reg_t tdm_ctrl_reg;
lis25ba_tdm_cmax_h_t tdm_cmax_h;
@@ -204,18 +217,19 @@ int32_t lis25ba_bus_mode_get(stmdev_ctx_t *ctx, lis25ba_bus_mode_t *val)
int32_t ret;
ret = lis25ba_read_reg(ctx, LIS25BA_TDM_CTRL_REG,
- (uint8_t*)&tdm_ctrl_reg, 1);
- if (ret == 0) {
+ (uint8_t *)&tdm_ctrl_reg, 1);
+
+ if (ret == 0)
+ {
ret = lis25ba_read_reg(ctx, LIS25BA_TDM_CMAX_H, reg, 2);
- bytecpy( (uint8_t*)&tdm_cmax_h, ®[0] );
- bytecpy( (uint8_t*)&tdm_cmax_l, ®[1] );
+ bytecpy((uint8_t *)&tdm_cmax_h, ®[0]);
+ bytecpy((uint8_t *)&tdm_cmax_l, ®[1]);
}
val->tdm.en = ~tdm_ctrl_reg.tdm_pd;
val->tdm.clk_pol = tdm_ctrl_reg.data_valid;
val->tdm.clk_edge = tdm_ctrl_reg.delayed;
val->tdm.mapping = tdm_ctrl_reg.wclk_fq;
-
val->tdm.cmax = tdm_cmax_h.tdm_cmax * 256U;
val->tdm.cmax += tdm_cmax_l.tdm_cmax;
@@ -240,29 +254,35 @@ int32_t lis25ba_mode_set(stmdev_ctx_t *ctx, lis25ba_md_t *val)
uint8_t reg[2];
int32_t ret;
- ret = lis25ba_read_reg(ctx, LIS25BA_CTRL_REG, (uint8_t*)&ctrl_reg, 1);
- if (ret == 0) {
+ ret = lis25ba_read_reg(ctx, LIS25BA_CTRL_REG, (uint8_t *)&ctrl_reg, 1);
+
+ if (ret == 0)
+ {
ret = lis25ba_read_reg(ctx, LIS25BA_TDM_CTRL_REG, reg, 2);
- bytecpy( (uint8_t*)&tdm_ctrl_reg, ®[0] );
- bytecpy( (uint8_t*)&axes_ctrl_reg, ®[1] );
+ bytecpy((uint8_t *)&tdm_ctrl_reg, ®[0]);
+ bytecpy((uint8_t *)&axes_ctrl_reg, ®[1]);
}
ctrl_reg.pd = (uint8_t)val->xl.odr & 0x01U;
- tdm_ctrl_reg.wclk_fq = ( (uint8_t)val->xl.odr & 0x06U ) >> 1;
- axes_ctrl_reg.odr_auto_en = ( (uint8_t)val->xl.odr & 0x10U ) >> 4;
-
+ tdm_ctrl_reg.wclk_fq = ((uint8_t)val->xl.odr & 0x06U) >> 1;
+ axes_ctrl_reg.odr_auto_en = ((uint8_t)val->xl.odr & 0x10U) >> 4;
axes_ctrl_reg.axisx_en = val->xl.axis.x;
axes_ctrl_reg.axisy_en = val->xl.axis.y;
axes_ctrl_reg.axisz_en = val->xl.axis.z;
- if ( ret == 0 ) {
- ret = lis25ba_write_reg(ctx, LIS25BA_CTRL_REG, (uint8_t*)&ctrl_reg, 1);
+ if (ret == 0)
+ {
+ ret = lis25ba_write_reg(ctx, LIS25BA_CTRL_REG, (uint8_t *)&ctrl_reg, 1);
}
+
/* writing checked configuration */
- bytecpy(®[0], ( uint8_t*)&tdm_ctrl_reg);
- bytecpy(®[1], ( uint8_t*)&axes_ctrl_reg);
- if ( ret == 0 ) {
- ret = lis25ba_write_reg(ctx, LIS25BA_TDM_CTRL_REG, (uint8_t*)®, 2);
+ bytecpy(®[0], (uint8_t *)&tdm_ctrl_reg);
+ bytecpy(®[1], (uint8_t *)&axes_ctrl_reg);
+
+ if (ret == 0)
+ {
+ ret = lis25ba_write_reg(ctx, LIS25BA_TDM_CTRL_REG, (uint8_t *)®,
+ 2);
}
return ret;
@@ -285,34 +305,43 @@ int32_t lis25ba_mode_get(stmdev_ctx_t *ctx, lis25ba_md_t *val)
uint8_t reg[2];
int32_t ret;
- ret = lis25ba_read_reg(ctx, LIS25BA_CTRL_REG, (uint8_t*)&ctrl_reg, 1);
- if (ret == 0) {
+ ret = lis25ba_read_reg(ctx, LIS25BA_CTRL_REG, (uint8_t *)&ctrl_reg, 1);
+
+ if (ret == 0)
+ {
ret = lis25ba_read_reg(ctx, LIS25BA_TDM_CTRL_REG, reg, 2);
- bytecpy( (uint8_t*)&tdm_ctrl_reg, ®[0] );
- bytecpy( (uint8_t*)&axes_ctrl_reg, ®[1] );
+ bytecpy((uint8_t *)&tdm_ctrl_reg, ®[0]);
+ bytecpy((uint8_t *)&axes_ctrl_reg, ®[1]);
}
val->xl.axis.x = axes_ctrl_reg.axisx_en;
val->xl.axis.y = axes_ctrl_reg.axisy_en;
val->xl.axis.z = axes_ctrl_reg.axisz_en;
- switch ( (axes_ctrl_reg.odr_auto_en << 4) | (tdm_ctrl_reg.wclk_fq << 1) |
- ctrl_reg.pd ) {
+ switch ((axes_ctrl_reg.odr_auto_en << 4) | (tdm_ctrl_reg.wclk_fq <<
+ 1) |
+ ctrl_reg.pd)
+ {
case LIS25BA_XL_OFF:
val->xl.odr = LIS25BA_XL_OFF;
break;
+
case LIS25BA_XL_8kHz:
val->xl.odr = LIS25BA_XL_8kHz;
break;
+
case LIS25BA_XL_16kHz:
val->xl.odr = LIS25BA_XL_16kHz;
break;
+
case LIS25BA_XL_24kHz:
val->xl.odr = LIS25BA_XL_24kHz;
break;
+
case LIS25BA_XL_HW_SEL:
val->xl.odr = LIS25BA_XL_HW_SEL;
break;
+
default:
val->xl.odr = LIS25BA_XL_OFF;
break;
@@ -337,14 +366,18 @@ int32_t lis25ba_data_get(uint16_t *tdm_stream, lis25ba_bus_mode_t *md,
uint8_t offset;
uint8_t i;
- if (md->tdm.mapping == PROPERTY_DISABLE ){
+ if (md->tdm.mapping == PROPERTY_DISABLE)
+ {
offset = 0; /* slot0-1-2 */
}
- else {
+
+ else
+ {
offset = 4; /* slot4-5-6 */
}
- for (i = 0U; i < 3U; i++) {
+ for (i = 0U; i < 3U; i++)
+ {
data->xl.raw[i] = (int16_t) tdm_stream[i + offset];
data->xl.mg[i] = lis25ba_from_raw_to_mg(data->xl.raw[i]);
}
@@ -366,11 +399,14 @@ int32_t lis25ba_self_test_set(stmdev_ctx_t *ctx, uint8_t val)
lis25ba_test_reg_t test_reg;
int32_t ret;
- ret = lis25ba_read_reg(ctx, LIS25BA_TEST_REG, (uint8_t*)&test_reg, 1);
- if (ret == 0) {
+ ret = lis25ba_read_reg(ctx, LIS25BA_TEST_REG, (uint8_t *)&test_reg, 1);
+
+ if (ret == 0)
+ {
test_reg.st = val;
- ret = lis25ba_write_reg(ctx, LIS25BA_TEST_REG, (uint8_t*)&test_reg, 1);
+ ret = lis25ba_write_reg(ctx, LIS25BA_TEST_REG, (uint8_t *)&test_reg, 1);
}
+
return ret;
}
@@ -388,7 +424,7 @@ int32_t lis25ba_self_test_get(stmdev_ctx_t *ctx, uint8_t *val)
lis25ba_test_reg_t test_reg;
int32_t ret;
- ret = lis25ba_read_reg(ctx, LIS25BA_TEST_REG, (uint8_t*)&test_reg, 1);
+ ret = lis25ba_read_reg(ctx, LIS25BA_TEST_REG, (uint8_t *)&test_reg, 1);
*val = test_reg.st;
return ret;
diff --git a/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.h b/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.h
index 067676561910f3e04985b796e997ab95a04a86e8..b4a4465f95010edd690d6fa160d671ab83ffb911 100644
--- a/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.h
+++ b/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.h
@@ -1,29 +1,29 @@
-/*
- ******************************************************************************
- * @file lis25ba_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lis25ba_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lis25ba_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lis25ba_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LIS25BA_REGS_H
#define LIS25BA_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -75,7 +75,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -108,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -140,7 +142,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -175,7 +178,8 @@ typedef struct {
*/
#define LIS25BA_TEST_REG 0x0BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t st : 1;
@@ -190,7 +194,8 @@ typedef struct {
#define LIS25BA_WHO_AM_I 0x0FU
#define LIS25BA_TDM_CMAX_H 0x24U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tdm_cmax : 4;
uint8_t not_used_01 : 4;
@@ -201,12 +206,14 @@ typedef struct {
} lis25ba_tdm_cmax_h_t;
#define LIS25BA_TDM_CMAX_L 0x25U
-typedef struct {
+typedef struct
+{
uint8_t tdm_cmax : 8;
} lis25ba_tdm_cmax_l_t;
#define LIS25BA_CTRL_REG 0x26U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 5;
uint8_t pd : 1;
@@ -219,7 +226,8 @@ typedef struct {
} lis25ba_ctrl_reg_t;
#define LIS25BA_TDM_CTRL_REG 0x2EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t wclk_fq : 2;
@@ -240,7 +248,8 @@ typedef struct {
} lis25ba_tdm_ctrl_reg_t;
#define LIS25BA_AXES_CTRL_REG 0x2FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t odr_auto_en : 1;
uint8_t not_used_01 : 4;
@@ -268,7 +277,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
lis25ba_test_reg_t test_reg;
lis25ba_tdm_cmax_h_t tdm_cmax_h;
lis25ba_tdm_cmax_l_t tdm_cmax_l;
@@ -284,20 +294,25 @@ typedef union{
*
*/
-int32_t lis25ba_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lis25ba_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t lis25ba_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lis25ba_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
extern float_t lis25ba_from_raw_to_mg(int16_t lsb);
-typedef struct {
+typedef struct
+{
uint8_t id;
} lis25ba_id_t;
int32_t lis25ba_id_get(stmdev_ctx_t *ctx, lis25ba_id_t *val);
-typedef struct {
- struct {
+typedef struct
+{
+ struct
+ {
uint8_t en : 1; /* TDM interface 1=on / 0=off) */
uint8_t clk_pol : 1; /* data valid on 0=rise/1=falling edge of BCLK */
uint8_t clk_edge : 1; /* data on 0=first / 1=second valid edge of BCLK */
@@ -305,17 +320,23 @@ typedef struct {
uint16_t cmax : 1; /* BCLK in a WCLK (unused if odr=_XL_HW_SEL) */
} tdm;
} lis25ba_bus_mode_t;
-int32_t lis25ba_bus_mode_set(stmdev_ctx_t *ctx, lis25ba_bus_mode_t *val);
-int32_t lis25ba_bus_mode_get(stmdev_ctx_t *ctx, lis25ba_bus_mode_t *val);
-
-typedef struct {
- struct {
- struct {
+int32_t lis25ba_bus_mode_set(stmdev_ctx_t *ctx,
+ lis25ba_bus_mode_t *val);
+int32_t lis25ba_bus_mode_get(stmdev_ctx_t *ctx,
+ lis25ba_bus_mode_t *val);
+
+typedef struct
+{
+ struct
+ {
+ struct
+ {
uint8_t x : 1; /* X-axis: 0=disabled / 1=enabled */
uint8_t y : 1; /* Y-axis: 0=disabled / 1=enabled */
uint8_t z : 1; /* Z-axis: 0=disabled / 1=enabled */
} axis;
- enum {
+ enum
+ {
LIS25BA_XL_OFF = 0x01, /* in power down */
LIS25BA_XL_8kHz = 0x00, /* sampling rate equal to 8 kHz */
LIS25BA_XL_16kHz = 0x02, /* sampling rate equal to 16 kHz */
@@ -327,11 +348,13 @@ typedef struct {
int32_t lis25ba_mode_set(stmdev_ctx_t *ctx, lis25ba_md_t *val);
int32_t lis25ba_mode_get(stmdev_ctx_t *ctx, lis25ba_md_t *val);
-typedef struct {
- struct {
- float mg[3];
+typedef struct
+{
+ struct
+ {
+ float_t mg[3];
int16_t raw[3];
- }xl;
+ } xl;
} lis25ba_data_t;
int32_t lis25ba_data_get(uint16_t *tdm_stream, lis25ba_bus_mode_t *md,
lis25ba_data_t *data);
diff --git a/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.c b/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.c
index 316b2fe7cf8702290ea1b533f36314eedad8e210..fc4daae2917951da27d5cc48e7e27d2dc15739f1 100644
--- a/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.c
+++ b/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file lis2de12_reg.c
- * @author Sensors Software Solution Team
- * @brief LIS2DE12 driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lis2de12_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LIS2DE12 driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lis2de12_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2de12_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lis2de12_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t lis2de12_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2de12_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lis2de12_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -77,7 +83,7 @@ int32_t lis2de12_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
*
*/
- /**
+/**
* @defgroup LIS2DE12_Sensitivity
* @brief These functions convert raw-data into engineering units.
* @{
@@ -86,27 +92,27 @@ int32_t lis2de12_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
float_t lis2de12_from_fs2_to_mg(int16_t lsb)
{
- return ( (float_t)lsb / 256.0f ) * 15.6f;
+ return ((float_t)lsb / 256.0f) * 15.6f;
}
float_t lis2de12_from_fs4_to_mg(int16_t lsb)
{
- return ( (float_t)lsb / 256.0f ) * 31.2f;
+ return ((float_t)lsb / 256.0f) * 31.2f;
}
float_t lis2de12_from_fs8_to_mg(int16_t lsb)
{
- return ( (float_t)lsb / 256.0f ) * 62.5f;
+ return ((float_t)lsb / 256.0f) * 62.5f;
}
float_t lis2de12_from_fs16_to_mg(int16_t lsb)
{
- return ( (float_t)lsb / 256.0f ) * 187.5f;
+ return ((float_t)lsb / 256.0f) * 187.5f;
}
float_t lis2de12_from_lsb_to_celsius(int16_t lsb)
{
- return ( ( (float_t)lsb / 256.0f ) * 1.0f ) + 25.0f;
+ return (((float_t)lsb / 256.0f) * 1.0f) + 25.0f;
}
/**
@@ -132,7 +138,9 @@ float_t lis2de12_from_lsb_to_celsius(int16_t lsb)
int32_t lis2de12_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis2de12_read_reg(ctx, LIS2DE12_STATUS_REG_AUX, buff, 1);
+
return ret;
}
/**
@@ -149,7 +157,7 @@ int32_t lis2de12_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lis2de12_read_reg(ctx, LIS2DE12_STATUS_REG_AUX,
- (uint8_t*)&status_reg_aux, 1);
+ (uint8_t *)&status_reg_aux, 1);
*val = status_reg_aux.tda;
return ret;
@@ -168,7 +176,7 @@ int32_t lis2de12_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lis2de12_read_reg(ctx, LIS2DE12_STATUS_REG_AUX,
- (uint8_t*)&status_reg_aux, 1);
+ (uint8_t *)&status_reg_aux, 1);
*val = status_reg_aux.tor;
return ret;
@@ -188,7 +196,7 @@ int32_t lis2de12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
ret = lis2de12_read_reg(ctx, LIS2DE12_OUT_TEMP_L, buff, 2);
*val = (int16_t)buff[1];
- *val = (*val * 256) + (int16_t)buff[0];
+ *val = (*val * 256) + (int16_t)buff[0];
return ret;
}
@@ -206,11 +214,16 @@ int32_t lis2de12_temperature_meas_set(stmdev_ctx_t *ctx,
lis2de12_temp_cfg_reg_t temp_cfg_reg;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_TEMP_CFG_REG, (uint8_t*)&temp_cfg_reg, 1);
- if (ret == 0) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_TEMP_CFG_REG,
+ (uint8_t *)&temp_cfg_reg, 1);
+
+ if (ret == 0)
+ {
temp_cfg_reg.temp_en = (uint8_t) val;
- ret = lis2de12_write_reg(ctx, LIS2DE12_TEMP_CFG_REG, (uint8_t*)&temp_cfg_reg, 1);
+ ret = lis2de12_write_reg(ctx, LIS2DE12_TEMP_CFG_REG,
+ (uint8_t *)&temp_cfg_reg, 1);
}
+
return ret;
}
@@ -228,18 +241,24 @@ int32_t lis2de12_temperature_meas_get(stmdev_ctx_t *ctx,
lis2de12_temp_cfg_reg_t temp_cfg_reg;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_TEMP_CFG_REG, (uint8_t*)&temp_cfg_reg, 1);
- switch (temp_cfg_reg.temp_en) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_TEMP_CFG_REG,
+ (uint8_t *)&temp_cfg_reg, 1);
+
+ switch (temp_cfg_reg.temp_en)
+ {
case LIS2DE12_TEMP_DISABLE:
*val = LIS2DE12_TEMP_DISABLE;
break;
+
case LIS2DE12_TEMP_ENABLE:
*val = LIS2DE12_TEMP_ENABLE;
break;
+
default:
*val = LIS2DE12_TEMP_DISABLE;
break;
}
+
return ret;
}
@@ -256,12 +275,17 @@ int32_t lis2de12_data_rate_set(stmdev_ctx_t *ctx, lis2de12_odr_t val)
lis2de12_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if (ret == 0) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.lpen = PROPERTY_ENABLE;
ctrl_reg1.odr = (uint8_t)val;
- ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -278,42 +302,56 @@ int32_t lis2de12_data_rate_get(stmdev_ctx_t *ctx, lis2de12_odr_t *val)
lis2de12_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- switch (ctrl_reg1.odr) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ switch (ctrl_reg1.odr)
+ {
case LIS2DE12_POWER_DOWN:
*val = LIS2DE12_POWER_DOWN;
break;
+
case LIS2DE12_ODR_1Hz:
*val = LIS2DE12_ODR_1Hz;
break;
+
case LIS2DE12_ODR_10Hz:
*val = LIS2DE12_ODR_10Hz;
break;
+
case LIS2DE12_ODR_25Hz:
*val = LIS2DE12_ODR_25Hz;
break;
+
case LIS2DE12_ODR_50Hz:
*val = LIS2DE12_ODR_50Hz;
break;
+
case LIS2DE12_ODR_100Hz:
*val = LIS2DE12_ODR_100Hz;
break;
+
case LIS2DE12_ODR_200Hz:
*val = LIS2DE12_ODR_200Hz;
break;
+
case LIS2DE12_ODR_400Hz:
*val = LIS2DE12_ODR_400Hz;
break;
+
case LIS2DE12_ODR_1kHz620_LP:
*val = LIS2DE12_ODR_1kHz620_LP;
break;
+
case LIS2DE12_ODR_5kHz376_LP_1kHz344_NM_HP:
*val = LIS2DE12_ODR_5kHz376_LP_1kHz344_NM_HP;
break;
+
default:
*val = LIS2DE12_POWER_DOWN;
break;
}
+
return ret;
}
@@ -326,16 +364,22 @@ int32_t lis2de12_data_rate_get(stmdev_ctx_t *ctx, lis2de12_odr_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2de12_high_pass_on_outputs_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lis2de12_high_pass_on_outputs_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lis2de12_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if (ret == 0) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.fds = val;
- ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -348,12 +392,14 @@ int32_t lis2de12_high_pass_on_outputs_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2de12_high_pass_on_outputs_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2de12_high_pass_on_outputs_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2de12_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
*val = (uint8_t)ctrl_reg2.fds;
return ret;
@@ -379,11 +425,16 @@ int32_t lis2de12_high_pass_bandwidth_set(stmdev_ctx_t *ctx,
lis2de12_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if (ret == 0) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpcf = (uint8_t)val;
- ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -407,24 +458,32 @@ int32_t lis2de12_high_pass_bandwidth_get(stmdev_ctx_t *ctx,
lis2de12_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- switch (ctrl_reg2.hpcf) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ switch (ctrl_reg2.hpcf)
+ {
case LIS2DE12_AGGRESSIVE:
*val = LIS2DE12_AGGRESSIVE;
break;
+
case LIS2DE12_STRONG:
*val = LIS2DE12_STRONG;
break;
+
case LIS2DE12_MEDIUM:
*val = LIS2DE12_MEDIUM;
break;
+
case LIS2DE12_LIGHT:
*val = LIS2DE12_LIGHT;
break;
+
default:
*val = LIS2DE12_LIGHT;
break;
}
+
return ret;
}
@@ -436,16 +495,22 @@ int32_t lis2de12_high_pass_bandwidth_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2de12_high_pass_mode_set(stmdev_ctx_t *ctx, lis2de12_hpm_t val)
+int32_t lis2de12_high_pass_mode_set(stmdev_ctx_t *ctx,
+ lis2de12_hpm_t val)
{
lis2de12_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if (ret == 0) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpm = (uint8_t)val;
- ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -457,29 +522,38 @@ int32_t lis2de12_high_pass_mode_set(stmdev_ctx_t *ctx, lis2de12_hpm_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2de12_high_pass_mode_get(stmdev_ctx_t *ctx, lis2de12_hpm_t *val)
+int32_t lis2de12_high_pass_mode_get(stmdev_ctx_t *ctx,
+ lis2de12_hpm_t *val)
{
lis2de12_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- switch (ctrl_reg2.hpm) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ switch (ctrl_reg2.hpm)
+ {
case LIS2DE12_NORMAL_WITH_RST:
*val = LIS2DE12_NORMAL_WITH_RST;
break;
+
case LIS2DE12_REFERENCE_MODE:
*val = LIS2DE12_REFERENCE_MODE;
break;
+
case LIS2DE12_NORMAL:
*val = LIS2DE12_NORMAL;
break;
+
case LIS2DE12_AUTORST_ON_INT:
*val = LIS2DE12_AUTORST_ON_INT;
break;
+
default:
*val = LIS2DE12_NORMAL_WITH_RST;
break;
}
+
return ret;
}
@@ -496,11 +570,16 @@ int32_t lis2de12_full_scale_set(stmdev_ctx_t *ctx, lis2de12_fs_t val)
lis2de12_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if (ret == 0) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.fs = (uint8_t)val;
- ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -517,24 +596,32 @@ int32_t lis2de12_full_scale_get(stmdev_ctx_t *ctx, lis2de12_fs_t *val)
lis2de12_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- switch (ctrl_reg4.fs) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ switch (ctrl_reg4.fs)
+ {
case LIS2DE12_2g:
*val = LIS2DE12_2g;
break;
+
case LIS2DE12_4g:
*val = LIS2DE12_4g;
break;
+
case LIS2DE12_8g:
*val = LIS2DE12_8g;
break;
+
case LIS2DE12_16g:
*val = LIS2DE12_16g;
break;
+
default:
*val = LIS2DE12_2g;
break;
}
+
return ret;
}
@@ -551,11 +638,16 @@ int32_t lis2de12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
lis2de12_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if (ret == 0) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.bdu = val;
- ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -567,12 +659,14 @@ int32_t lis2de12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2de12_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2de12_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2de12_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
*val = (uint8_t)ctrl_reg4.bdu;
return ret;
@@ -587,10 +681,13 @@ int32_t lis2de12_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2de12_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lis2de12_filter_reference_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
+
ret = lis2de12_write_reg(ctx, LIS2DE12_REFERENCE, buff, 1);
+
return ret;
}
@@ -603,10 +700,13 @@ int32_t lis2de12_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2de12_filter_reference_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lis2de12_filter_reference_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
+
ret = lis2de12_read_reg(ctx, LIS2DE12_REFERENCE, buff, 1);
+
return ret;
}
/**
@@ -622,7 +722,8 @@ int32_t lis2de12_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2de12_status_reg_t status_reg;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_STATUS_REG, (uint8_t*)&status_reg, 1);
+ ret = lis2de12_read_reg(ctx, LIS2DE12_STATUS_REG,
+ (uint8_t *)&status_reg, 1);
*val = status_reg.zyxda;
return ret;
@@ -640,7 +741,8 @@ int32_t lis2de12_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2de12_status_reg_t status_reg;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_STATUS_REG, (uint8_t*)&status_reg, 1);
+ ret = lis2de12_read_reg(ctx, LIS2DE12_STATUS_REG,
+ (uint8_t *)&status_reg, 1);
*val = status_reg.zyxor;
return ret;
@@ -660,11 +762,12 @@ int32_t lis2de12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_READ_START, buff, 6);
val[0] = (int16_t)buff[1];
- val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
- val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
val[2] = (int16_t)buff[5];
- val[2] = (val[2] * 256) + (int16_t)buff[4];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
/**
@@ -674,7 +777,7 @@ int32_t lis2de12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
/**
* @defgroup LIS2DE12_Common
- * @brief This section group common usefull functions
+ * @brief This section group common useful functions
* @{
*
*/
@@ -690,7 +793,9 @@ int32_t lis2de12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
int32_t lis2de12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis2de12_read_reg(ctx, LIS2DE12_WHO_AM_I, buff, 1);
+
return ret;
}
/**
@@ -706,11 +811,16 @@ int32_t lis2de12_self_test_set(stmdev_ctx_t *ctx, lis2de12_st_t val)
lis2de12_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if (ret == 0) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.st = (uint8_t)val;
- ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -727,21 +837,28 @@ int32_t lis2de12_self_test_get(stmdev_ctx_t *ctx, lis2de12_st_t *val)
lis2de12_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- switch (ctrl_reg4.st) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ switch (ctrl_reg4.st)
+ {
case LIS2DE12_ST_DISABLE:
*val = LIS2DE12_ST_DISABLE;
break;
+
case LIS2DE12_ST_POSITIVE:
*val = LIS2DE12_ST_POSITIVE;
break;
+
case LIS2DE12_ST_NEGATIVE:
*val = LIS2DE12_ST_NEGATIVE;
break;
+
default:
*val = LIS2DE12_ST_DISABLE;
break;
}
+
return ret;
}
@@ -758,11 +875,16 @@ int32_t lis2de12_boot_set(stmdev_ctx_t *ctx, uint8_t val)
lis2de12_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.boot = val;
- ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -779,7 +901,8 @@ int32_t lis2de12_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2de12_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
*val = (uint8_t)ctrl_reg5.boot;
return ret;
@@ -793,10 +916,13 @@ int32_t lis2de12_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2de12_status_get(stmdev_ctx_t *ctx, lis2de12_status_reg_t *val)
+int32_t lis2de12_status_get(stmdev_ctx_t *ctx,
+ lis2de12_status_reg_t *val)
{
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_STATUS_REG, (uint8_t*) val, 1);
+
+ ret = lis2de12_read_reg(ctx, LIS2DE12_STATUS_REG, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -824,7 +950,9 @@ int32_t lis2de12_int1_gen_conf_set(stmdev_ctx_t *ctx,
lis2de12_int1_cfg_t *val)
{
int32_t ret;
- ret = lis2de12_write_reg(ctx, LIS2DE12_INT1_CFG, (uint8_t*) val, 1);
+
+ ret = lis2de12_write_reg(ctx, LIS2DE12_INT1_CFG, (uint8_t *) val, 1);
+
return ret;
}
@@ -840,7 +968,9 @@ int32_t lis2de12_int1_gen_conf_get(stmdev_ctx_t *ctx,
lis2de12_int1_cfg_t *val)
{
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_INT1_CFG, (uint8_t*) val, 1);
+
+ ret = lis2de12_read_reg(ctx, LIS2DE12_INT1_CFG, (uint8_t *) val, 1);
+
return ret;
}
@@ -856,7 +986,9 @@ int32_t lis2de12_int1_gen_source_get(stmdev_ctx_t *ctx,
lis2de12_int1_src_t *val)
{
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_INT1_SRC, (uint8_t*) val, 1);
+
+ ret = lis2de12_read_reg(ctx, LIS2DE12_INT1_SRC, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -869,16 +1001,20 @@ int32_t lis2de12_int1_gen_source_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2de12_int1_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lis2de12_int1_gen_threshold_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lis2de12_int1_ths_t int1_ths;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_INT1_THS, (uint8_t*)&int1_ths, 1);
- if (ret == 0) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_INT1_THS, (uint8_t *)&int1_ths, 1);
+
+ if (ret == 0)
+ {
int1_ths.ths = val;
- ret = lis2de12_write_reg(ctx, LIS2DE12_INT1_THS, (uint8_t*)&int1_ths, 1);
+ ret = lis2de12_write_reg(ctx, LIS2DE12_INT1_THS, (uint8_t *)&int1_ths, 1);
}
+
return ret;
}
@@ -892,12 +1028,13 @@ int32_t lis2de12_int1_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2de12_int1_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2de12_int1_gen_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2de12_int1_ths_t int1_ths;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_INT1_THS, (uint8_t*)&int1_ths, 1);
+ ret = lis2de12_read_reg(ctx, LIS2DE12_INT1_THS, (uint8_t *)&int1_ths, 1);
*val = (uint8_t)int1_ths.ths;
return ret;
@@ -917,11 +1054,16 @@ int32_t lis2de12_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val)
lis2de12_int1_duration_t int1_duration;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_INT1_DURATION, (uint8_t*)&int1_duration, 1);
- if (ret == 0) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_INT1_DURATION,
+ (uint8_t *)&int1_duration, 1);
+
+ if (ret == 0)
+ {
int1_duration.d = val;
- ret = lis2de12_write_reg(ctx, LIS2DE12_INT1_DURATION, (uint8_t*)&int1_duration, 1);
+ ret = lis2de12_write_reg(ctx, LIS2DE12_INT1_DURATION,
+ (uint8_t *)&int1_duration, 1);
}
+
return ret;
}
@@ -934,12 +1076,14 @@ int32_t lis2de12_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2de12_int1_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2de12_int1_gen_duration_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2de12_int1_duration_t int1_duration;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_INT1_DURATION, (uint8_t*)&int1_duration, 1);
+ ret = lis2de12_read_reg(ctx, LIS2DE12_INT1_DURATION,
+ (uint8_t *)&int1_duration, 1);
*val = (uint8_t)int1_duration.d;
return ret;
@@ -970,7 +1114,9 @@ int32_t lis2de12_int2_gen_conf_set(stmdev_ctx_t *ctx,
lis2de12_int2_cfg_t *val)
{
int32_t ret;
- ret = lis2de12_write_reg(ctx, LIS2DE12_INT2_CFG, (uint8_t*) val, 1);
+
+ ret = lis2de12_write_reg(ctx, LIS2DE12_INT2_CFG, (uint8_t *) val, 1);
+
return ret;
}
@@ -986,7 +1132,9 @@ int32_t lis2de12_int2_gen_conf_get(stmdev_ctx_t *ctx,
lis2de12_int2_cfg_t *val)
{
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_INT2_CFG, (uint8_t*) val, 1);
+
+ ret = lis2de12_read_reg(ctx, LIS2DE12_INT2_CFG, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1001,7 +1149,9 @@ int32_t lis2de12_int2_gen_source_get(stmdev_ctx_t *ctx,
lis2de12_int2_src_t *val)
{
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_INT2_SRC, (uint8_t*) val, 1);
+
+ ret = lis2de12_read_reg(ctx, LIS2DE12_INT2_SRC, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1014,16 +1164,20 @@ int32_t lis2de12_int2_gen_source_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2de12_int2_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lis2de12_int2_gen_threshold_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lis2de12_int2_ths_t int2_ths;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_INT2_THS, (uint8_t*)&int2_ths, 1);
- if (ret == 0) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_INT2_THS, (uint8_t *)&int2_ths, 1);
+
+ if (ret == 0)
+ {
int2_ths.ths = val;
- ret = lis2de12_write_reg(ctx, LIS2DE12_INT2_THS, (uint8_t*)&int2_ths, 1);
+ ret = lis2de12_write_reg(ctx, LIS2DE12_INT2_THS, (uint8_t *)&int2_ths, 1);
}
+
return ret;
}
@@ -1037,12 +1191,13 @@ int32_t lis2de12_int2_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2de12_int2_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2de12_int2_gen_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2de12_int2_ths_t int2_ths;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_INT2_THS, (uint8_t*)&int2_ths, 1);
+ ret = lis2de12_read_reg(ctx, LIS2DE12_INT2_THS, (uint8_t *)&int2_ths, 1);
*val = (uint8_t)int2_ths.ths;
return ret;
@@ -1062,11 +1217,16 @@ int32_t lis2de12_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val)
lis2de12_int2_duration_t int2_duration;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_INT2_DURATION, (uint8_t*)&int2_duration, 1);
- if (ret == 0) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_INT2_DURATION,
+ (uint8_t *)&int2_duration, 1);
+
+ if (ret == 0)
+ {
int2_duration.d = val;
- ret = lis2de12_write_reg(ctx, LIS2DE12_INT2_DURATION, (uint8_t*)&int2_duration, 1);
+ ret = lis2de12_write_reg(ctx, LIS2DE12_INT2_DURATION,
+ (uint8_t *)&int2_duration, 1);
}
+
return ret;
}
@@ -1079,12 +1239,14 @@ int32_t lis2de12_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2de12_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2de12_int2_gen_duration_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2de12_int2_duration_t int2_duration;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_INT2_DURATION, (uint8_t*)&int2_duration, 1);
+ ret = lis2de12_read_reg(ctx, LIS2DE12_INT2_DURATION,
+ (uint8_t *)&int2_duration, 1);
*val = (uint8_t)int2_duration.d;
return ret;
@@ -1097,7 +1259,7 @@ int32_t lis2de12_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @defgroup LIS2DE12_Interrupt_pins
- * @brief This section group all the functions that manage interrup pins
+ * @brief This section group all the functions that manage interrupt pins
* @{
*
*/
@@ -1116,11 +1278,16 @@ int32_t lis2de12_high_pass_int_conf_set(stmdev_ctx_t *ctx,
lis2de12_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if (ret == 0) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hp = (uint8_t)val;
- ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -1138,36 +1305,48 @@ int32_t lis2de12_high_pass_int_conf_get(stmdev_ctx_t *ctx,
lis2de12_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- switch (ctrl_reg2.hp) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ switch (ctrl_reg2.hp)
+ {
case LIS2DE12_DISC_FROM_INT_GENERATOR:
*val = LIS2DE12_DISC_FROM_INT_GENERATOR;
break;
+
case LIS2DE12_ON_INT1_GEN:
*val = LIS2DE12_ON_INT1_GEN;
break;
+
case LIS2DE12_ON_INT2_GEN:
*val = LIS2DE12_ON_INT2_GEN;
break;
+
case LIS2DE12_ON_TAP_GEN:
*val = LIS2DE12_ON_TAP_GEN;
break;
+
case LIS2DE12_ON_INT1_INT2_GEN:
*val = LIS2DE12_ON_INT1_INT2_GEN;
break;
+
case LIS2DE12_ON_INT1_TAP_GEN:
*val = LIS2DE12_ON_INT1_TAP_GEN;
break;
+
case LIS2DE12_ON_INT2_TAP_GEN:
*val = LIS2DE12_ON_INT2_TAP_GEN;
break;
+
case LIS2DE12_ON_INT1_INT2_TAP_GEN:
*val = LIS2DE12_ON_INT1_INT2_TAP_GEN;
break;
+
default:
*val = LIS2DE12_DISC_FROM_INT_GENERATOR;
break;
}
+
return ret;
}
@@ -1183,7 +1362,9 @@ int32_t lis2de12_pin_int1_config_set(stmdev_ctx_t *ctx,
lis2de12_ctrl_reg3_t *val)
{
int32_t ret;
- ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG3, (uint8_t*) val, 1);
+
+ ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG3, (uint8_t *) val, 1);
+
return ret;
}
@@ -1199,7 +1380,9 @@ int32_t lis2de12_pin_int1_config_get(stmdev_ctx_t *ctx,
lis2de12_ctrl_reg3_t *val)
{
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG3, (uint8_t*) val, 1);
+
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG3, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1212,16 +1395,22 @@ int32_t lis2de12_pin_int1_config_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2de12_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lis2de12_int2_pin_detect_4d_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lis2de12_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.d4d_int2 = val;
- ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -1234,12 +1423,14 @@ int32_t lis2de12_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2de12_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2de12_int2_pin_detect_4d_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2de12_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
*val = (uint8_t)ctrl_reg5.d4d_int2;
return ret;
@@ -1261,11 +1452,16 @@ int32_t lis2de12_int2_pin_notification_mode_set(stmdev_ctx_t *ctx,
lis2de12_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.lir_int2 = (uint8_t)val;
- ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -1285,18 +1481,24 @@ int32_t lis2de12_int2_pin_notification_mode_get(stmdev_ctx_t *ctx,
lis2de12_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- switch (ctrl_reg5.lir_int2) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
+
+ switch (ctrl_reg5.lir_int2)
+ {
case LIS2DE12_INT2_PULSED:
*val = LIS2DE12_INT2_PULSED;
break;
+
case LIS2DE12_INT2_LATCHED:
*val = LIS2DE12_INT2_LATCHED;
break;
+
default:
*val = LIS2DE12_INT2_PULSED;
break;
}
+
return ret;
}
@@ -1309,16 +1511,22 @@ int32_t lis2de12_int2_pin_notification_mode_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2de12_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lis2de12_int1_pin_detect_4d_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lis2de12_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.d4d_int1 = val;
- ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -1331,12 +1539,14 @@ int32_t lis2de12_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2de12_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2de12_int1_pin_detect_4d_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2de12_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
*val = (uint8_t)ctrl_reg5.d4d_int1;
return ret;
@@ -1357,11 +1567,16 @@ int32_t lis2de12_int1_pin_notification_mode_set(stmdev_ctx_t *ctx,
lis2de12_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.lir_int1 = (uint8_t)val;
- ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -1380,18 +1595,24 @@ int32_t lis2de12_int1_pin_notification_mode_get(stmdev_ctx_t *ctx,
lis2de12_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- switch (ctrl_reg5.lir_int1) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
+
+ switch (ctrl_reg5.lir_int1)
+ {
case LIS2DE12_INT1_PULSED:
*val = LIS2DE12_INT1_PULSED;
break;
+
case LIS2DE12_INT1_LATCHED:
*val = LIS2DE12_INT1_LATCHED;
break;
+
default:
*val = LIS2DE12_INT1_PULSED;
break;
}
+
return ret;
}
@@ -1407,7 +1628,9 @@ int32_t lis2de12_pin_int2_config_set(stmdev_ctx_t *ctx,
lis2de12_ctrl_reg6_t *val)
{
int32_t ret;
- ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG6, (uint8_t*) val, 1);
+
+ ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG6, (uint8_t *) val, 1);
+
return ret;
}
@@ -1423,7 +1646,9 @@ int32_t lis2de12_pin_int2_config_get(stmdev_ctx_t *ctx,
lis2de12_ctrl_reg6_t *val)
{
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG6, (uint8_t*) val, 1);
+
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG6, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1451,11 +1676,16 @@ int32_t lis2de12_fifo_set(stmdev_ctx_t *ctx, uint8_t val)
lis2de12_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.fifo_en = val;
- ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -1472,7 +1702,8 @@ int32_t lis2de12_fifo_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2de12_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
*val = (uint8_t)ctrl_reg5.fifo_en;
return ret;
@@ -1491,11 +1722,16 @@ int32_t lis2de12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
lis2de12_fifo_ctrl_reg_t fifo_ctrl_reg;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
- if (ret == 0) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl_reg.fth = val;
- ret = lis2de12_write_reg(ctx, LIS2DE12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
+ ret = lis2de12_write_reg(ctx, LIS2DE12_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
}
+
return ret;
}
@@ -1512,7 +1748,8 @@ int32_t lis2de12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2de12_fifo_ctrl_reg_t fifo_ctrl_reg;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
+ ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
*val = (uint8_t)fifo_ctrl_reg.fth;
return ret;
@@ -1532,11 +1769,16 @@ int32_t lis2de12_fifo_trigger_event_set(stmdev_ctx_t *ctx,
lis2de12_fifo_ctrl_reg_t fifo_ctrl_reg;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
- if (ret == 0) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl_reg.tr = (uint8_t)val;
- ret = lis2de12_write_reg(ctx, LIS2DE12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
+ ret = lis2de12_write_reg(ctx, LIS2DE12_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
}
+
return ret;
}
@@ -1554,18 +1796,24 @@ int32_t lis2de12_fifo_trigger_event_get(stmdev_ctx_t *ctx,
lis2de12_fifo_ctrl_reg_t fifo_ctrl_reg;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
- switch (fifo_ctrl_reg.tr) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
+
+ switch (fifo_ctrl_reg.tr)
+ {
case LIS2DE12_INT1_GEN:
*val = LIS2DE12_INT1_GEN;
break;
+
case LIS2DE12_INT2_GEN:
*val = LIS2DE12_INT2_GEN;
break;
+
default:
*val = LIS2DE12_INT1_GEN;
break;
}
+
return ret;
}
@@ -1582,11 +1830,16 @@ int32_t lis2de12_fifo_mode_set(stmdev_ctx_t *ctx, lis2de12_fm_t val)
lis2de12_fifo_ctrl_reg_t fifo_ctrl_reg;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
- if (ret == 0) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl_reg.fm = (uint8_t)val;
- ret = lis2de12_write_reg(ctx, LIS2DE12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
+ ret = lis2de12_write_reg(ctx, LIS2DE12_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
}
+
return ret;
}
@@ -1603,24 +1856,32 @@ int32_t lis2de12_fifo_mode_get(stmdev_ctx_t *ctx, lis2de12_fm_t *val)
lis2de12_fifo_ctrl_reg_t fifo_ctrl_reg;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
- switch (fifo_ctrl_reg.fm) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
+
+ switch (fifo_ctrl_reg.fm)
+ {
case LIS2DE12_BYPASS_MODE:
*val = LIS2DE12_BYPASS_MODE;
break;
+
case LIS2DE12_FIFO_MODE:
*val = LIS2DE12_FIFO_MODE;
break;
+
case LIS2DE12_DYNAMIC_STREAM_MODE:
*val = LIS2DE12_DYNAMIC_STREAM_MODE;
break;
+
case LIS2DE12_STREAM_TO_FIFO_MODE:
*val = LIS2DE12_STREAM_TO_FIFO_MODE;
break;
+
default:
*val = LIS2DE12_BYPASS_MODE;
break;
}
+
return ret;
}
@@ -1636,7 +1897,9 @@ int32_t lis2de12_fifo_status_get(stmdev_ctx_t *ctx,
lis2de12_fifo_src_reg_t *val)
{
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_SRC_REG, (uint8_t*) val, 1);
+
+ ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_SRC_REG, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1652,7 +1915,8 @@ int32_t lis2de12_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2de12_fifo_src_reg_t fifo_src_reg;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1);
+ ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_SRC_REG,
+ (uint8_t *)&fifo_src_reg, 1);
*val = (uint8_t)fifo_src_reg.fss;
return ret;
@@ -1670,7 +1934,8 @@ int32_t lis2de12_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2de12_fifo_src_reg_t fifo_src_reg;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1);
+ ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_SRC_REG,
+ (uint8_t *)&fifo_src_reg, 1);
*val = (uint8_t)fifo_src_reg.empty;
return ret;
@@ -1688,7 +1953,8 @@ int32_t lis2de12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2de12_fifo_src_reg_t fifo_src_reg;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1);
+ ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_SRC_REG,
+ (uint8_t *)&fifo_src_reg, 1);
*val = (uint8_t)fifo_src_reg.ovrn_fifo;
return ret;
@@ -1706,7 +1972,8 @@ int32_t lis2de12_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2de12_fifo_src_reg_t fifo_src_reg;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1);
+ ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_SRC_REG,
+ (uint8_t *)&fifo_src_reg, 1);
*val = (uint8_t)fifo_src_reg.wtm;
return ret;
@@ -1732,10 +1999,13 @@ int32_t lis2de12_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2de12_tap_conf_set(stmdev_ctx_t *ctx, lis2de12_click_cfg_t *val)
+int32_t lis2de12_tap_conf_set(stmdev_ctx_t *ctx,
+ lis2de12_click_cfg_t *val)
{
int32_t ret;
- ret = lis2de12_write_reg(ctx, LIS2DE12_CLICK_CFG, (uint8_t*) val, 1);
+
+ ret = lis2de12_write_reg(ctx, LIS2DE12_CLICK_CFG, (uint8_t *) val, 1);
+
return ret;
}
@@ -1747,10 +2017,13 @@ int32_t lis2de12_tap_conf_set(stmdev_ctx_t *ctx, lis2de12_click_cfg_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2de12_tap_conf_get(stmdev_ctx_t *ctx, lis2de12_click_cfg_t *val)
+int32_t lis2de12_tap_conf_get(stmdev_ctx_t *ctx,
+ lis2de12_click_cfg_t *val)
{
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CLICK_CFG, (uint8_t*) val, 1);
+
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CLICK_CFG, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1761,10 +2034,13 @@ int32_t lis2de12_tap_conf_get(stmdev_ctx_t *ctx, lis2de12_click_cfg_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2de12_tap_source_get(stmdev_ctx_t *ctx, lis2de12_click_src_t *val)
+int32_t lis2de12_tap_source_get(stmdev_ctx_t *ctx,
+ lis2de12_click_src_t *val)
{
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CLICK_SRC, (uint8_t*) val, 1);
+
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CLICK_SRC, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1781,11 +2057,16 @@ int32_t lis2de12_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
lis2de12_click_ths_t click_ths;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CLICK_THS, (uint8_t*)&click_ths, 1);
- if (ret == 0) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CLICK_THS,
+ (uint8_t *)&click_ths, 1);
+
+ if (ret == 0)
+ {
click_ths.ths = val;
- ret = lis2de12_write_reg(ctx, LIS2DE12_CLICK_THS, (uint8_t*)&click_ths, 1);
+ ret = lis2de12_write_reg(ctx, LIS2DE12_CLICK_THS,
+ (uint8_t *)&click_ths, 1);
}
+
return ret;
}
@@ -1803,7 +2084,8 @@ int32_t lis2de12_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2de12_click_ths_t click_ths;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CLICK_THS, (uint8_t*)&click_ths, 1);
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CLICK_THS,
+ (uint8_t *)&click_ths, 1);
*val = (uint8_t)click_ths.ths;
return ret;
@@ -1826,11 +2108,16 @@ int32_t lis2de12_tap_notification_mode_set(stmdev_ctx_t *ctx,
lis2de12_click_ths_t click_ths;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CLICK_THS, (uint8_t*)&click_ths, 1);
- if (ret == 0) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CLICK_THS,
+ (uint8_t *)&click_ths, 1);
+
+ if (ret == 0)
+ {
click_ths.lir_click = (uint8_t)val;
- ret = lis2de12_write_reg(ctx, LIS2DE12_CLICK_THS, (uint8_t*)&click_ths, 1);
+ ret = lis2de12_write_reg(ctx, LIS2DE12_CLICK_THS,
+ (uint8_t *)&click_ths, 1);
}
+
return ret;
}
@@ -1851,18 +2138,24 @@ int32_t lis2de12_tap_notification_mode_get(stmdev_ctx_t *ctx,
lis2de12_click_ths_t click_ths;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CLICK_THS, (uint8_t*)&click_ths, 1);
- switch (click_ths.lir_click) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CLICK_THS,
+ (uint8_t *)&click_ths, 1);
+
+ switch (click_ths.lir_click)
+ {
case LIS2DE12_TAP_PULSED:
*val = LIS2DE12_TAP_PULSED;
break;
+
case LIS2DE12_TAP_LATCHED:
*val = LIS2DE12_TAP_LATCHED;
break;
+
default:
*val = LIS2DE12_TAP_PULSED;
break;
}
+
return ret;
}
@@ -1881,11 +2174,16 @@ int32_t lis2de12_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lis2de12_time_limit_t time_limit;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_TIME_LIMIT, (uint8_t*)&time_limit, 1);
- if (ret == 0) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_TIME_LIMIT,
+ (uint8_t *)&time_limit, 1);
+
+ if (ret == 0)
+ {
time_limit.tli = val;
- ret = lis2de12_write_reg(ctx, LIS2DE12_TIME_LIMIT, (uint8_t*)&time_limit, 1);
+ ret = lis2de12_write_reg(ctx, LIS2DE12_TIME_LIMIT,
+ (uint8_t *)&time_limit, 1);
}
+
return ret;
}
@@ -1904,7 +2202,8 @@ int32_t lis2de12_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2de12_time_limit_t time_limit;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_TIME_LIMIT, (uint8_t*)&time_limit, 1);
+ ret = lis2de12_read_reg(ctx, LIS2DE12_TIME_LIMIT,
+ (uint8_t *)&time_limit, 1);
*val = (uint8_t)time_limit.tli;
return ret;
@@ -1926,11 +2225,16 @@ int32_t lis2de12_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lis2de12_time_latency_t time_latency;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_TIME_LATENCY, (uint8_t*)&time_latency, 1);
- if (ret == 0) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_TIME_LATENCY,
+ (uint8_t *)&time_latency, 1);
+
+ if (ret == 0)
+ {
time_latency.tla = val;
- ret = lis2de12_write_reg(ctx, LIS2DE12_TIME_LATENCY, (uint8_t*)&time_latency, 1);
+ ret = lis2de12_write_reg(ctx, LIS2DE12_TIME_LATENCY,
+ (uint8_t *)&time_latency, 1);
}
+
return ret;
}
@@ -1950,7 +2254,8 @@ int32_t lis2de12_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2de12_time_latency_t time_latency;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_TIME_LATENCY, (uint8_t*)&time_latency, 1);
+ ret = lis2de12_read_reg(ctx, LIS2DE12_TIME_LATENCY,
+ (uint8_t *)&time_latency, 1);
*val = (uint8_t)time_latency.tla;
return ret;
@@ -1967,16 +2272,22 @@ int32_t lis2de12_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2de12_double_tap_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lis2de12_double_tap_timeout_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lis2de12_time_window_t time_window;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_TIME_WINDOW, (uint8_t*)&time_window, 1);
- if (ret == 0) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_TIME_WINDOW,
+ (uint8_t *)&time_window, 1);
+
+ if (ret == 0)
+ {
time_window.tw = val;
- ret = lis2de12_write_reg(ctx, LIS2DE12_TIME_WINDOW, (uint8_t*)&time_window, 1);
+ ret = lis2de12_write_reg(ctx, LIS2DE12_TIME_WINDOW,
+ (uint8_t *)&time_window, 1);
}
+
return ret;
}
@@ -1991,12 +2302,14 @@ int32_t lis2de12_double_tap_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2de12_double_tap_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2de12_double_tap_timeout_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2de12_time_window_t time_window;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_TIME_WINDOW, (uint8_t*)&time_window, 1);
+ ret = lis2de12_read_reg(ctx, LIS2DE12_TIME_WINDOW,
+ (uint8_t *)&time_window, 1);
*val = (uint8_t)time_window.tw;
return ret;
@@ -2030,11 +2343,14 @@ int32_t lis2de12_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
lis2de12_act_ths_t act_ths;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_ACT_THS, (uint8_t*)&act_ths, 1);
- if (ret == 0) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_ACT_THS, (uint8_t *)&act_ths, 1);
+
+ if (ret == 0)
+ {
act_ths.acth = val;
- ret = lis2de12_write_reg(ctx, LIS2DE12_ACT_THS, (uint8_t*)&act_ths, 1);
+ ret = lis2de12_write_reg(ctx, LIS2DE12_ACT_THS, (uint8_t *)&act_ths, 1);
}
+
return ret;
}
@@ -2053,7 +2369,7 @@ int32_t lis2de12_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2de12_act_ths_t act_ths;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_ACT_THS, (uint8_t*)&act_ths, 1);
+ ret = lis2de12_read_reg(ctx, LIS2DE12_ACT_THS, (uint8_t *)&act_ths, 1);
*val = (uint8_t)act_ths.acth;
return ret;
@@ -2073,11 +2389,14 @@ int32_t lis2de12_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
lis2de12_act_dur_t act_dur;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_ACT_DUR, (uint8_t*)&act_dur, 1);
- if (ret == 0) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_ACT_DUR, (uint8_t *)&act_dur, 1);
+
+ if (ret == 0)
+ {
act_dur.actd = val;
- ret = lis2de12_write_reg(ctx, LIS2DE12_ACT_DUR, (uint8_t*)&act_dur, 1);
+ ret = lis2de12_write_reg(ctx, LIS2DE12_ACT_DUR, (uint8_t *)&act_dur, 1);
}
+
return ret;
}
@@ -2095,7 +2414,7 @@ int32_t lis2de12_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2de12_act_dur_t act_dur;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_ACT_DUR, (uint8_t*)&act_dur, 1);
+ ret = lis2de12_read_reg(ctx, LIS2DE12_ACT_DUR, (uint8_t *)&act_dur, 1);
*val = (uint8_t)act_dur.actd;
return ret;
@@ -2128,11 +2447,16 @@ int32_t lis2de12_pin_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
lis2de12_ctrl_reg0_t ctrl_reg0;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG0, (uint8_t*)&ctrl_reg0, 1);
- if (ret == 0) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG0,
+ (uint8_t *)&ctrl_reg0, 1);
+
+ if (ret == 0)
+ {
ctrl_reg0.sdo_pu_disc = (uint8_t)val;
- ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG0, (uint8_t*)&ctrl_reg0, 1);
+ ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG0,
+ (uint8_t *)&ctrl_reg0, 1);
}
+
return ret;
}
@@ -2150,18 +2474,24 @@ int32_t lis2de12_pin_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
lis2de12_ctrl_reg0_t ctrl_reg0;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG0, (uint8_t*)&ctrl_reg0, 1);
- switch (ctrl_reg0.sdo_pu_disc) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG0,
+ (uint8_t *)&ctrl_reg0, 1);
+
+ switch (ctrl_reg0.sdo_pu_disc)
+ {
case LIS2DE12_PULL_UP_DISCONNECT:
*val = LIS2DE12_PULL_UP_DISCONNECT;
break;
+
case LIS2DE12_PULL_UP_CONNECT:
*val = LIS2DE12_PULL_UP_CONNECT;
break;
+
default:
*val = LIS2DE12_PULL_UP_DISCONNECT;
break;
}
+
return ret;
}
@@ -2178,11 +2508,16 @@ int32_t lis2de12_spi_mode_set(stmdev_ctx_t *ctx, lis2de12_sim_t val)
lis2de12_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if (ret == 0) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.sim = (uint8_t)val;
- ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -2199,18 +2534,24 @@ int32_t lis2de12_spi_mode_get(stmdev_ctx_t *ctx, lis2de12_sim_t *val)
lis2de12_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- switch (ctrl_reg4.sim) {
+ ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ switch (ctrl_reg4.sim)
+ {
case LIS2DE12_SPI_4_WIRE:
*val = LIS2DE12_SPI_4_WIRE;
break;
+
case LIS2DE12_SPI_3_WIRE:
*val = LIS2DE12_SPI_3_WIRE;
break;
+
default:
*val = LIS2DE12_SPI_4_WIRE;
break;
}
+
return ret;
}
diff --git a/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.h b/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.h
index bd7738ab93343e67eaad3c08b0f4784e3cd8dec5..d864071a40a044477079825ce73018d3a3242564 100644
--- a/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.h
+++ b/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.h
@@ -1,29 +1,29 @@
-/*
- ******************************************************************************
- * @file lis2de12_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lis2de12_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lis2de12_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lis2de12_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LIS2DE12_REGS_H
#define LIS2DE12_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -75,7 +75,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -108,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -132,7 +134,7 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
+ * You can create a sensor configuration by your own or using
* Unico / Unicleo tools available on STMicroelectronics
* web site.
*
@@ -140,7 +142,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -175,7 +178,8 @@ typedef struct {
*/
#define LIS2DE12_STATUS_REG_AUX 0x07U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t tda : 1;
@@ -196,7 +200,8 @@ typedef struct {
#define LIS2DE12_WHO_AM_I 0x0FU
#define LIS2DE12_CTRL_REG0 0x1EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 7;
uint8_t sdo_pu_disc : 1;
@@ -207,7 +212,8 @@ typedef struct {
} lis2de12_ctrl_reg0_t;
#define LIS2DE12_TEMP_CFG_REG 0x1FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 6;
uint8_t temp_en : 2;
@@ -218,7 +224,8 @@ typedef struct {
} lis2de12_temp_cfg_reg_t;
#define LIS2DE12_CTRL_REG1 0x20U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xen : 1;
uint8_t yen : 1;
@@ -235,7 +242,8 @@ typedef struct {
} lis2de12_ctrl_reg1_t;
#define LIS2DE12_CTRL_REG2 0x21U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t hp : 3; /* HPCLICK + HP_IA2 + HP_IA1 -> HP */
uint8_t fds : 1;
@@ -250,7 +258,8 @@ typedef struct {
} lis2de12_ctrl_reg2_t;
#define LIS2DE12_CTRL_REG3 0x22U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t i1_overrun : 1;
@@ -273,7 +282,8 @@ typedef struct {
} lis2de12_ctrl_reg3_t;
#define LIS2DE12_CTRL_REG4 0x23U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t st : 2;
@@ -292,7 +302,8 @@ typedef struct {
} lis2de12_ctrl_reg4_t;
#define LIS2DE12_CTRL_REG5 0x24U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d4d_int2 : 1;
uint8_t lir_int2 : 1;
@@ -313,7 +324,8 @@ typedef struct {
} lis2de12_ctrl_reg5_t;
#define LIS2DE12_CTRL_REG6 0x25U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t int_polarity : 1;
@@ -337,7 +349,8 @@ typedef struct {
#define LIS2DE12_REFERENCE 0x26U
#define LIS2DE12_STATUS_REG 0x27U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xda : 1;
uint8_t yda : 1;
@@ -364,7 +377,8 @@ typedef struct {
#define LIS2DE12_OUT_Y_H 0x2BU
#define LIS2DE12_OUT_Z_H 0x2DU
#define LIS2DE12_FIFO_CTRL_REG 0x2EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fth : 5;
uint8_t tr : 1;
@@ -377,7 +391,8 @@ typedef struct {
} lis2de12_fifo_ctrl_reg_t;
#define LIS2DE12_FIFO_SRC_REG 0x2FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fss : 5;
uint8_t empty : 1;
@@ -392,7 +407,8 @@ typedef struct {
} lis2de12_fifo_src_reg_t;
#define LIS2DE12_INT1_CFG 0x30U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlie : 1;
uint8_t xhie : 1;
@@ -415,7 +431,8 @@ typedef struct {
} lis2de12_int1_cfg_t;
#define LIS2DE12_INT1_SRC 0x31U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
@@ -438,7 +455,8 @@ typedef struct {
} lis2de12_int1_src_t;
#define LIS2DE12_INT1_THS 0x32U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t not_used_01 : 1;
@@ -449,7 +467,8 @@ typedef struct {
} lis2de12_int1_ths_t;
#define LIS2DE12_INT1_DURATION 0x33U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d : 7;
uint8_t not_used_01 : 1;
@@ -460,7 +479,8 @@ typedef struct {
} lis2de12_int1_duration_t;
#define LIS2DE12_INT2_CFG 0x34U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlie : 1;
uint8_t xhie : 1;
@@ -483,7 +503,8 @@ typedef struct {
} lis2de12_int2_cfg_t;
#define LIS2DE12_INT2_SRC 0x35U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
@@ -506,7 +527,8 @@ typedef struct {
} lis2de12_int2_src_t;
#define LIS2DE12_INT2_THS 0x36U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t not_used_01 : 1;
@@ -517,7 +539,8 @@ typedef struct {
} lis2de12_int2_ths_t;
#define LIS2DE12_INT2_DURATION 0x37U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d : 7;
uint8_t not_used_01 : 1;
@@ -528,7 +551,8 @@ typedef struct {
} lis2de12_int2_duration_t;
#define LIS2DE12_CLICK_CFG 0x38U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xs : 1;
uint8_t xd : 1;
@@ -549,7 +573,8 @@ typedef struct {
} lis2de12_click_cfg_t;
#define LIS2DE12_CLICK_SRC 0x39U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t x : 1;
uint8_t y : 1;
@@ -572,7 +597,8 @@ typedef struct {
} lis2de12_click_src_t;
#define LIS2DE12_CLICK_THS 0x3AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t lir_click : 1;
@@ -583,7 +609,8 @@ typedef struct {
} lis2de12_click_ths_t;
#define LIS2DE12_TIME_LIMIT 0x3BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tli : 7;
uint8_t not_used_01 : 1;
@@ -594,17 +621,20 @@ typedef struct {
} lis2de12_time_limit_t;
#define LIS2DE12_TIME_LATENCY 0x3CU
-typedef struct {
+typedef struct
+{
uint8_t tla : 8;
} lis2de12_time_latency_t;
#define LIS2DE12_TIME_WINDOW 0x3DU
-typedef struct {
+typedef struct
+{
uint8_t tw : 8;
} lis2de12_time_window_t;
#define LIS2DE12_ACT_THS 0x3EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t acth : 7;
uint8_t not_used_01 : 1;
@@ -615,23 +645,25 @@ typedef struct {
} lis2de12_act_ths_t;
#define LIS2DE12_ACT_DUR 0x3FU
-typedef struct {
+typedef struct
+{
uint8_t actd : 8;
} lis2de12_act_dur_t;
/**
* @defgroup LIS2DE12_Register_Union
- * @brief This union group all the registers that has a bitfield
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is usefull but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
- * REMOVING this union you are complient with:
+ * REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
*
* @{
*
*/
-typedef union{
+typedef union
+{
lis2de12_status_reg_aux_t status_reg_aux;
lis2de12_ctrl_reg0_t ctrl_reg0;
lis2de12_temp_cfg_reg_t temp_cfg_reg;
@@ -669,25 +701,30 @@ typedef union{
*
*/
-int32_t lis2de12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lis2de12_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t lis2de12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lis2de12_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
float_t lis2de12_from_fs2_to_mg(int16_t lsb);
float_t lis2de12_from_fs4_to_mg(int16_t lsb);
float_t lis2de12_from_fs8_to_mg(int16_t lsb);
float_t lis2de12_from_fs16_to_mg(int16_t lsb);
+
float_t lis2de12_from_lsb_to_celsius(int16_t lsb);
-int32_t lis2de12_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lis2de12_temp_status_reg_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
int32_t lis2de12_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2de12_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2de12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val);
-typedef enum {
+typedef enum
+{
LIS2DE12_TEMP_DISABLE = 0,
LIS2DE12_TEMP_ENABLE = 3,
} lis2de12_temp_en_t;
@@ -696,7 +733,8 @@ int32_t lis2de12_temperature_meas_set(stmdev_ctx_t *ctx,
int32_t lis2de12_temperature_meas_get(stmdev_ctx_t *ctx,
lis2de12_temp_en_t *val);
-typedef enum {
+typedef enum
+{
LIS2DE12_POWER_DOWN = 0x00,
LIS2DE12_ODR_1Hz = 0x01,
LIS2DE12_ODR_10Hz = 0x02,
@@ -709,12 +747,16 @@ typedef enum {
LIS2DE12_ODR_5kHz376_LP_1kHz344_NM_HP = 0x09,
} lis2de12_odr_t;
int32_t lis2de12_data_rate_set(stmdev_ctx_t *ctx, lis2de12_odr_t val);
-int32_t lis2de12_data_rate_get(stmdev_ctx_t *ctx, lis2de12_odr_t *val);
+int32_t lis2de12_data_rate_get(stmdev_ctx_t *ctx,
+ lis2de12_odr_t *val);
-int32_t lis2de12_high_pass_on_outputs_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2de12_high_pass_on_outputs_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2de12_high_pass_on_outputs_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2de12_high_pass_on_outputs_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DE12_AGGRESSIVE = 0,
LIS2DE12_STRONG = 1,
LIS2DE12_MEDIUM = 2,
@@ -725,39 +767,50 @@ int32_t lis2de12_high_pass_bandwidth_set(stmdev_ctx_t *ctx,
int32_t lis2de12_high_pass_bandwidth_get(stmdev_ctx_t *ctx,
lis2de12_hpcf_t *val);
-typedef enum {
+typedef enum
+{
LIS2DE12_NORMAL_WITH_RST = 0,
LIS2DE12_REFERENCE_MODE = 1,
LIS2DE12_NORMAL = 2,
LIS2DE12_AUTORST_ON_INT = 3,
} lis2de12_hpm_t;
-int32_t lis2de12_high_pass_mode_set(stmdev_ctx_t *ctx, lis2de12_hpm_t val);
-int32_t lis2de12_high_pass_mode_get(stmdev_ctx_t *ctx, lis2de12_hpm_t *val);
+int32_t lis2de12_high_pass_mode_set(stmdev_ctx_t *ctx,
+ lis2de12_hpm_t val);
+int32_t lis2de12_high_pass_mode_get(stmdev_ctx_t *ctx,
+ lis2de12_hpm_t *val);
-typedef enum {
+typedef enum
+{
LIS2DE12_2g = 0,
LIS2DE12_4g = 1,
LIS2DE12_8g = 2,
LIS2DE12_16g = 3,
} lis2de12_fs_t;
int32_t lis2de12_full_scale_set(stmdev_ctx_t *ctx, lis2de12_fs_t val);
-int32_t lis2de12_full_scale_get(stmdev_ctx_t *ctx, lis2de12_fs_t *val);
+int32_t lis2de12_full_scale_get(stmdev_ctx_t *ctx,
+ lis2de12_fs_t *val);
-int32_t lis2de12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2de12_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2de12_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2de12_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lis2de12_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lis2de12_filter_reference_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lis2de12_filter_reference_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lis2de12_filter_reference_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
int32_t lis2de12_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2de12_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lis2de12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t lis2de12_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
int32_t lis2de12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
-typedef enum {
+typedef enum
+{
LIS2DE12_ST_DISABLE = 0,
LIS2DE12_ST_POSITIVE = 1,
LIS2DE12_ST_NEGATIVE = 2,
@@ -768,7 +821,8 @@ int32_t lis2de12_self_test_get(stmdev_ctx_t *ctx, lis2de12_st_t *val);
int32_t lis2de12_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2de12_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lis2de12_status_get(stmdev_ctx_t *ctx, lis2de12_status_reg_t *val);
+int32_t lis2de12_status_get(stmdev_ctx_t *ctx,
+ lis2de12_status_reg_t *val);
int32_t lis2de12_int1_gen_conf_set(stmdev_ctx_t *ctx,
lis2de12_int1_cfg_t *val);
@@ -778,11 +832,15 @@ int32_t lis2de12_int1_gen_conf_get(stmdev_ctx_t *ctx,
int32_t lis2de12_int1_gen_source_get(stmdev_ctx_t *ctx,
lis2de12_int1_src_t *val);
-int32_t lis2de12_int1_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2de12_int1_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2de12_int1_gen_threshold_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2de12_int1_gen_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lis2de12_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2de12_int1_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2de12_int1_gen_duration_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2de12_int1_gen_duration_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lis2de12_int2_gen_conf_set(stmdev_ctx_t *ctx,
lis2de12_int2_cfg_t *val);
@@ -792,13 +850,18 @@ int32_t lis2de12_int2_gen_conf_get(stmdev_ctx_t *ctx,
int32_t lis2de12_int2_gen_source_get(stmdev_ctx_t *ctx,
lis2de12_int2_src_t *val);
-int32_t lis2de12_int2_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2de12_int2_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2de12_int2_gen_threshold_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2de12_int2_gen_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lis2de12_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2de12_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2de12_int2_gen_duration_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2de12_int2_gen_duration_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DE12_DISC_FROM_INT_GENERATOR = 0,
LIS2DE12_ON_INT1_GEN = 1,
LIS2DE12_ON_INT2_GEN = 2,
@@ -818,10 +881,13 @@ int32_t lis2de12_pin_int1_config_set(stmdev_ctx_t *ctx,
int32_t lis2de12_pin_int1_config_get(stmdev_ctx_t *ctx,
lis2de12_ctrl_reg3_t *val);
-int32_t lis2de12_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2de12_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2de12_int2_pin_detect_4d_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2de12_int2_pin_detect_4d_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DE12_INT2_PULSED = 0,
LIS2DE12_INT2_LATCHED = 1,
} lis2de12_lir_int2_t;
@@ -830,10 +896,13 @@ int32_t lis2de12_int2_pin_notification_mode_set(stmdev_ctx_t *ctx,
int32_t lis2de12_int2_pin_notification_mode_get(stmdev_ctx_t *ctx,
lis2de12_lir_int2_t *val);
-int32_t lis2de12_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2de12_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2de12_int1_pin_detect_4d_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2de12_int1_pin_detect_4d_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DE12_INT1_PULSED = 0,
LIS2DE12_INT1_LATCHED = 1,
} lis2de12_lir_int1_t;
@@ -853,7 +922,8 @@ int32_t lis2de12_fifo_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2de12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2de12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DE12_INT1_GEN = 0,
LIS2DE12_INT2_GEN = 1,
} lis2de12_tr_t;
@@ -862,7 +932,8 @@ int32_t lis2de12_fifo_trigger_event_set(stmdev_ctx_t *ctx,
int32_t lis2de12_fifo_trigger_event_get(stmdev_ctx_t *ctx,
lis2de12_tr_t *val);
-typedef enum {
+typedef enum
+{
LIS2DE12_BYPASS_MODE = 0,
LIS2DE12_FIFO_MODE = 1,
LIS2DE12_DYNAMIC_STREAM_MODE = 2,
@@ -882,8 +953,10 @@ int32_t lis2de12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2de12_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lis2de12_tap_conf_set(stmdev_ctx_t *ctx, lis2de12_click_cfg_t *val);
-int32_t lis2de12_tap_conf_get(stmdev_ctx_t *ctx, lis2de12_click_cfg_t *val);
+int32_t lis2de12_tap_conf_set(stmdev_ctx_t *ctx,
+ lis2de12_click_cfg_t *val);
+int32_t lis2de12_tap_conf_get(stmdev_ctx_t *ctx,
+ lis2de12_click_cfg_t *val);
int32_t lis2de12_tap_source_get(stmdev_ctx_t *ctx,
lis2de12_click_src_t *val);
@@ -891,7 +964,8 @@ int32_t lis2de12_tap_source_get(stmdev_ctx_t *ctx,
int32_t lis2de12_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2de12_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DE12_TAP_PULSED = 0,
LIS2DE12_TAP_LATCHED = 1,
} lis2de12_lir_click_t;
@@ -906,8 +980,10 @@ int32_t lis2de12_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2de12_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2de12_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lis2de12_double_tap_timeout_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2de12_double_tap_timeout_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2de12_double_tap_timeout_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2de12_double_tap_timeout_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lis2de12_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2de12_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -915,7 +991,8 @@ int32_t lis2de12_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2de12_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2de12_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DE12_PULL_UP_DISCONNECT = 1,
LIS2DE12_PULL_UP_CONNECT = 0,
} lis2de12_sdo_pu_disc_t;
@@ -924,7 +1001,8 @@ int32_t lis2de12_pin_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
int32_t lis2de12_pin_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
lis2de12_sdo_pu_disc_t *val);
-typedef enum {
+typedef enum
+{
LIS2DE12_SPI_4_WIRE = 0,
LIS2DE12_SPI_3_WIRE = 1,
} lis2de12_sim_t;
diff --git a/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.c b/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.c
index cffe1455c46d2dcb79679a3a6fbf2bf8d7e9247e..5cf3cb57245ae2fdd74e03c47f7ba0354b027600 100644
--- a/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.c
+++ b/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file lis2dh12_reg.c
- * @author Sensors Software Solution Team
- * @brief LIS2DH12 driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lis2dh12_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LIS2DH12 driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lis2dh12_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dh12_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lis2dh12_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t lis2dh12_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dh12_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lis2dh12_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -77,7 +83,7 @@ int32_t lis2dh12_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
*
*/
- /**
+/**
* @defgroup LIS2DH12_Sensitivity
* @brief These functions convert raw-data into engineering units.
* @{
@@ -86,77 +92,77 @@ int32_t lis2dh12_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
float_t lis2dh12_from_fs2_hr_to_mg(int16_t lsb)
{
- return ( (float_t)lsb / 16.0f ) * 1.0f;
+ return ((float_t)lsb / 16.0f) * 1.0f;
}
float_t lis2dh12_from_fs4_hr_to_mg(int16_t lsb)
{
- return ( (float_t)lsb / 16.0f ) * 2.0f;
+ return ((float_t)lsb / 16.0f) * 2.0f;
}
float_t lis2dh12_from_fs8_hr_to_mg(int16_t lsb)
{
- return ( (float_t)lsb / 16.0f ) * 4.0f;
+ return ((float_t)lsb / 16.0f) * 4.0f;
}
float_t lis2dh12_from_fs16_hr_to_mg(int16_t lsb)
{
- return ( (float_t)lsb / 16.0f ) * 12.0f;
+ return ((float_t)lsb / 16.0f) * 12.0f;
}
float_t lis2dh12_from_lsb_hr_to_celsius(int16_t lsb)
{
- return ( ( (float_t)lsb / 64.0f ) / 4.0f ) + 25.0f;
+ return (((float_t)lsb / 64.0f) / 4.0f) + 25.0f;
}
float_t lis2dh12_from_fs2_nm_to_mg(int16_t lsb)
{
- return ( (float_t)lsb / 64.0f ) * 4.0f;
+ return ((float_t)lsb / 64.0f) * 4.0f;
}
float_t lis2dh12_from_fs4_nm_to_mg(int16_t lsb)
{
- return ( (float_t)lsb / 64.0f ) * 8.0f;
+ return ((float_t)lsb / 64.0f) * 8.0f;
}
float_t lis2dh12_from_fs8_nm_to_mg(int16_t lsb)
{
- return ( (float_t)lsb / 64.0f ) * 16.0f;
+ return ((float_t)lsb / 64.0f) * 16.0f;
}
float_t lis2dh12_from_fs16_nm_to_mg(int16_t lsb)
{
- return ( (float_t)lsb / 64.0f ) * 48.0f;
+ return ((float_t)lsb / 64.0f) * 48.0f;
}
float_t lis2dh12_from_lsb_nm_to_celsius(int16_t lsb)
{
- return ( ( (float_t)lsb / 64.0f ) / 4.0f ) + 25.0f;
+ return (((float_t)lsb / 64.0f) / 4.0f) + 25.0f;
}
float_t lis2dh12_from_fs2_lp_to_mg(int16_t lsb)
{
- return ( (float_t)lsb / 256.0f ) * 16.0f;
+ return ((float_t)lsb / 256.0f) * 16.0f;
}
float_t lis2dh12_from_fs4_lp_to_mg(int16_t lsb)
{
- return ( (float_t)lsb / 256.0f ) * 32.0f;
+ return ((float_t)lsb / 256.0f) * 32.0f;
}
float_t lis2dh12_from_fs8_lp_to_mg(int16_t lsb)
{
- return ( (float_t)lsb / 256.0f ) * 64.0f;
+ return ((float_t)lsb / 256.0f) * 64.0f;
}
float_t lis2dh12_from_fs16_lp_to_mg(int16_t lsb)
{
- return ( (float_t)lsb / 256.0f ) * 192.0f;
+ return ((float_t)lsb / 256.0f) * 192.0f;
}
float_t lis2dh12_from_lsb_lp_to_celsius(int16_t lsb)
{
- return ( ( (float_t)lsb / 256.0f ) * 1.0f ) + 25.0f;
+ return (((float_t)lsb / 256.0f) * 1.0f) + 25.0f;
}
/**
@@ -182,7 +188,9 @@ float_t lis2dh12_from_lsb_lp_to_celsius(int16_t lsb)
int32_t lis2dh12_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis2dh12_read_reg(ctx, LIS2DH12_STATUS_REG_AUX, buff, 1);
+
return ret;
}
/**
@@ -199,7 +207,7 @@ int32_t lis2dh12_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lis2dh12_read_reg(ctx, LIS2DH12_STATUS_REG_AUX,
- (uint8_t*)&status_reg_aux, 1);
+ (uint8_t *)&status_reg_aux, 1);
*val = status_reg_aux.tda;
return ret;
@@ -218,7 +226,7 @@ int32_t lis2dh12_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lis2dh12_read_reg(ctx, LIS2DH12_STATUS_REG_AUX,
- (uint8_t*)&status_reg_aux, 1);
+ (uint8_t *)&status_reg_aux, 1);
*val = status_reg_aux.tor;
return ret;
@@ -238,7 +246,7 @@ int32_t lis2dh12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
ret = lis2dh12_read_reg(ctx, LIS2DH12_OUT_TEMP_L, buff, 2);
*val = (int16_t)buff[1];
- *val = (*val * 256) + (int16_t)buff[0];
+ *val = (*val * 256) + (int16_t)buff[0];
return ret;
}
@@ -256,11 +264,16 @@ int32_t lis2dh12_temperature_meas_set(stmdev_ctx_t *ctx,
lis2dh12_temp_cfg_reg_t temp_cfg_reg;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_TEMP_CFG_REG, (uint8_t*)&temp_cfg_reg, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_TEMP_CFG_REG,
+ (uint8_t *)&temp_cfg_reg, 1);
+
+ if (ret == 0)
+ {
temp_cfg_reg.temp_en = (uint8_t) val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_TEMP_CFG_REG, (uint8_t*)&temp_cfg_reg, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_TEMP_CFG_REG,
+ (uint8_t *)&temp_cfg_reg, 1);
}
+
return ret;
}
@@ -278,18 +291,24 @@ int32_t lis2dh12_temperature_meas_get(stmdev_ctx_t *ctx,
lis2dh12_temp_cfg_reg_t temp_cfg_reg;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_TEMP_CFG_REG, (uint8_t*)&temp_cfg_reg, 1);
- switch (temp_cfg_reg.temp_en) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_TEMP_CFG_REG,
+ (uint8_t *)&temp_cfg_reg, 1);
+
+ switch (temp_cfg_reg.temp_en)
+ {
case LIS2DH12_TEMP_DISABLE:
*val = LIS2DH12_TEMP_DISABLE;
break;
+
case LIS2DH12_TEMP_ENABLE:
*val = LIS2DH12_TEMP_ENABLE;
break;
+
default:
*val = LIS2DH12_TEMP_DISABLE;
break;
}
+
return ret;
}
@@ -302,36 +321,52 @@ int32_t lis2dh12_temperature_meas_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dh12_operating_mode_set(stmdev_ctx_t *ctx, lis2dh12_op_md_t val)
+int32_t lis2dh12_operating_mode_set(stmdev_ctx_t *ctx,
+ lis2dh12_op_md_t val)
{
lis2dh12_ctrl_reg1_t ctrl_reg1;
lis2dh12_ctrl_reg4_t ctrl_reg4;
int32_t ret;
ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
- if (ret == 0) {
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
- }
- if (ret == 0) {
- if ( val == LIS2DH12_HR_12bit ) {
+ (uint8_t *)&ctrl_reg4, 1);
+ }
+
+ if (ret == 0)
+ {
+ if (val == LIS2DH12_HR_12bit)
+ {
ctrl_reg1.lpen = 0;
ctrl_reg4.hr = 1;
}
- if (val == LIS2DH12_NM_10bit) {
+
+ if (val == LIS2DH12_NM_10bit)
+ {
ctrl_reg1.lpen = 0;
ctrl_reg4.hr = 0;
}
- if (val == LIS2DH12_LP_8bit) {
+
+ if (val == LIS2DH12_LP_8bit)
+ {
ctrl_reg1.lpen = 1;
ctrl_reg4.hr = 0;
}
- ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- }
- if (ret == 0) {
- ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
}
+
+ if (ret == 0)
+ {
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+ }
+
return ret;
}
@@ -343,23 +378,37 @@ int32_t lis2dh12_operating_mode_set(stmdev_ctx_t *ctx, lis2dh12_op_md_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dh12_operating_mode_get(stmdev_ctx_t *ctx, lis2dh12_op_md_t *val)
+int32_t lis2dh12_operating_mode_get(stmdev_ctx_t *ctx,
+ lis2dh12_op_md_t *val)
{
lis2dh12_ctrl_reg1_t ctrl_reg1;
lis2dh12_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if (ret == 0) {
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if ( ctrl_reg1.lpen == PROPERTY_ENABLE ) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ctrl_reg1.lpen == PROPERTY_ENABLE)
+ {
*val = LIS2DH12_LP_8bit;
- } else if (ctrl_reg4.hr == PROPERTY_ENABLE ) {
+ }
+
+ else if (ctrl_reg4.hr == PROPERTY_ENABLE)
+ {
*val = LIS2DH12_HR_12bit;
- } else {
+ }
+
+ else
+ {
*val = LIS2DH12_NM_10bit;
}
}
+
return ret;
}
@@ -376,11 +425,16 @@ int32_t lis2dh12_data_rate_set(stmdev_ctx_t *ctx, lis2dh12_odr_t val)
lis2dh12_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.odr = (uint8_t)val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -397,42 +451,56 @@ int32_t lis2dh12_data_rate_get(stmdev_ctx_t *ctx, lis2dh12_odr_t *val)
lis2dh12_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- switch (ctrl_reg1.odr) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ switch (ctrl_reg1.odr)
+ {
case LIS2DH12_POWER_DOWN:
*val = LIS2DH12_POWER_DOWN;
break;
+
case LIS2DH12_ODR_1Hz:
*val = LIS2DH12_ODR_1Hz;
break;
+
case LIS2DH12_ODR_10Hz:
*val = LIS2DH12_ODR_10Hz;
break;
+
case LIS2DH12_ODR_25Hz:
*val = LIS2DH12_ODR_25Hz;
break;
+
case LIS2DH12_ODR_50Hz:
*val = LIS2DH12_ODR_50Hz;
break;
+
case LIS2DH12_ODR_100Hz:
*val = LIS2DH12_ODR_100Hz;
break;
+
case LIS2DH12_ODR_200Hz:
*val = LIS2DH12_ODR_200Hz;
break;
+
case LIS2DH12_ODR_400Hz:
*val = LIS2DH12_ODR_400Hz;
break;
+
case LIS2DH12_ODR_1kHz620_LP:
*val = LIS2DH12_ODR_1kHz620_LP;
break;
+
case LIS2DH12_ODR_5kHz376_LP_1kHz344_NM_HP:
*val = LIS2DH12_ODR_5kHz376_LP_1kHz344_NM_HP;
break;
+
default:
*val = LIS2DH12_POWER_DOWN;
break;
}
+
return ret;
}
@@ -445,16 +513,22 @@ int32_t lis2dh12_data_rate_get(stmdev_ctx_t *ctx, lis2dh12_odr_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dh12_high_pass_on_outputs_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lis2dh12_high_pass_on_outputs_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lis2dh12_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.fds = val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -467,12 +541,14 @@ int32_t lis2dh12_high_pass_on_outputs_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dh12_high_pass_on_outputs_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2dh12_high_pass_on_outputs_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2dh12_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
*val = (uint8_t)ctrl_reg2.fds;
return ret;
@@ -498,11 +574,16 @@ int32_t lis2dh12_high_pass_bandwidth_set(stmdev_ctx_t *ctx,
lis2dh12_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpcf = (uint8_t)val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -526,24 +607,32 @@ int32_t lis2dh12_high_pass_bandwidth_get(stmdev_ctx_t *ctx,
lis2dh12_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- switch (ctrl_reg2.hpcf) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ switch (ctrl_reg2.hpcf)
+ {
case LIS2DH12_AGGRESSIVE:
*val = LIS2DH12_AGGRESSIVE;
break;
+
case LIS2DH12_STRONG:
*val = LIS2DH12_STRONG;
break;
+
case LIS2DH12_MEDIUM:
*val = LIS2DH12_MEDIUM;
break;
+
case LIS2DH12_LIGHT:
*val = LIS2DH12_LIGHT;
break;
+
default:
*val = LIS2DH12_LIGHT;
break;
}
+
return ret;
}
@@ -555,16 +644,22 @@ int32_t lis2dh12_high_pass_bandwidth_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dh12_high_pass_mode_set(stmdev_ctx_t *ctx, lis2dh12_hpm_t val)
+int32_t lis2dh12_high_pass_mode_set(stmdev_ctx_t *ctx,
+ lis2dh12_hpm_t val)
{
lis2dh12_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpm = (uint8_t)val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -576,29 +671,38 @@ int32_t lis2dh12_high_pass_mode_set(stmdev_ctx_t *ctx, lis2dh12_hpm_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dh12_high_pass_mode_get(stmdev_ctx_t *ctx, lis2dh12_hpm_t *val)
+int32_t lis2dh12_high_pass_mode_get(stmdev_ctx_t *ctx,
+ lis2dh12_hpm_t *val)
{
lis2dh12_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- switch (ctrl_reg2.hpm) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ switch (ctrl_reg2.hpm)
+ {
case LIS2DH12_NORMAL_WITH_RST:
*val = LIS2DH12_NORMAL_WITH_RST;
break;
+
case LIS2DH12_REFERENCE_MODE:
*val = LIS2DH12_REFERENCE_MODE;
break;
+
case LIS2DH12_NORMAL:
*val = LIS2DH12_NORMAL;
break;
+
case LIS2DH12_AUTORST_ON_INT:
*val = LIS2DH12_AUTORST_ON_INT;
break;
+
default:
*val = LIS2DH12_NORMAL_WITH_RST;
break;
}
+
return ret;
}
@@ -615,11 +719,16 @@ int32_t lis2dh12_full_scale_set(stmdev_ctx_t *ctx, lis2dh12_fs_t val)
lis2dh12_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.fs = (uint8_t)val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -636,24 +745,32 @@ int32_t lis2dh12_full_scale_get(stmdev_ctx_t *ctx, lis2dh12_fs_t *val)
lis2dh12_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- switch (ctrl_reg4.fs) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ switch (ctrl_reg4.fs)
+ {
case LIS2DH12_2g:
*val = LIS2DH12_2g;
break;
+
case LIS2DH12_4g:
*val = LIS2DH12_4g;
break;
+
case LIS2DH12_8g:
*val = LIS2DH12_8g;
break;
+
case LIS2DH12_16g:
*val = LIS2DH12_16g;
break;
+
default:
*val = LIS2DH12_2g;
break;
}
+
return ret;
}
@@ -670,11 +787,16 @@ int32_t lis2dh12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dh12_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.bdu = val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -686,12 +808,14 @@ int32_t lis2dh12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dh12_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2dh12_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2dh12_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
*val = (uint8_t)ctrl_reg4.bdu;
return ret;
@@ -706,10 +830,13 @@ int32_t lis2dh12_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dh12_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lis2dh12_filter_reference_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
+
ret = lis2dh12_write_reg(ctx, LIS2DH12_REFERENCE, buff, 1);
+
return ret;
}
@@ -722,10 +849,13 @@ int32_t lis2dh12_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dh12_filter_reference_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lis2dh12_filter_reference_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
+
ret = lis2dh12_read_reg(ctx, LIS2DH12_REFERENCE, buff, 1);
+
return ret;
}
/**
@@ -741,7 +871,8 @@ int32_t lis2dh12_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dh12_status_reg_t status_reg;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_STATUS_REG, (uint8_t*)&status_reg, 1);
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_STATUS_REG,
+ (uint8_t *)&status_reg, 1);
*val = status_reg.zyxda;
return ret;
@@ -759,7 +890,8 @@ int32_t lis2dh12_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dh12_status_reg_t status_reg;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_STATUS_REG, (uint8_t*)&status_reg, 1);
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_STATUS_REG,
+ (uint8_t *)&status_reg, 1);
*val = status_reg.zyxor;
return ret;
@@ -779,11 +911,11 @@ int32_t lis2dh12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
ret = lis2dh12_read_reg(ctx, LIS2DH12_OUT_X_L, buff, 6);
val[0] = (int16_t)buff[1];
- val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
- val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
val[2] = (int16_t)buff[5];
- val[2] = (val[2] * 256) + (int16_t)buff[4];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
return ret;
}
@@ -794,7 +926,7 @@ int32_t lis2dh12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
/**
* @defgroup LIS2DH12_Common
- * @brief This section group common usefull functions
+ * @brief This section group common useful functions
* @{
*
*/
@@ -810,7 +942,9 @@ int32_t lis2dh12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
int32_t lis2dh12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis2dh12_read_reg(ctx, LIS2DH12_WHO_AM_I, buff, 1);
+
return ret;
}
/**
@@ -826,11 +960,16 @@ int32_t lis2dh12_self_test_set(stmdev_ctx_t *ctx, lis2dh12_st_t val)
lis2dh12_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.st = (uint8_t)val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -847,21 +986,28 @@ int32_t lis2dh12_self_test_get(stmdev_ctx_t *ctx, lis2dh12_st_t *val)
lis2dh12_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- switch (ctrl_reg4.st) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ switch (ctrl_reg4.st)
+ {
case LIS2DH12_ST_DISABLE:
*val = LIS2DH12_ST_DISABLE;
break;
+
case LIS2DH12_ST_POSITIVE:
*val = LIS2DH12_ST_POSITIVE;
break;
+
case LIS2DH12_ST_NEGATIVE:
*val = LIS2DH12_ST_NEGATIVE;
break;
+
default:
*val = LIS2DH12_ST_DISABLE;
break;
}
+
return ret;
}
@@ -873,16 +1019,22 @@ int32_t lis2dh12_self_test_get(stmdev_ctx_t *ctx, lis2dh12_st_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dh12_data_format_set(stmdev_ctx_t *ctx, lis2dh12_ble_t val)
+int32_t lis2dh12_data_format_set(stmdev_ctx_t *ctx,
+ lis2dh12_ble_t val)
{
lis2dh12_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.ble = (uint8_t)val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -894,23 +1046,30 @@ int32_t lis2dh12_data_format_set(stmdev_ctx_t *ctx, lis2dh12_ble_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dh12_data_format_get(stmdev_ctx_t *ctx, lis2dh12_ble_t *val)
+int32_t lis2dh12_data_format_get(stmdev_ctx_t *ctx,
+ lis2dh12_ble_t *val)
{
lis2dh12_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- switch (ctrl_reg4.ble) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ switch (ctrl_reg4.ble)
+ {
case LIS2DH12_LSB_AT_LOW_ADD:
*val = LIS2DH12_LSB_AT_LOW_ADD;
break;
+
case LIS2DH12_MSB_AT_LOW_ADD:
*val = LIS2DH12_MSB_AT_LOW_ADD;
break;
+
default:
*val = LIS2DH12_LSB_AT_LOW_ADD;
break;
}
+
return ret;
}
@@ -927,11 +1086,16 @@ int32_t lis2dh12_boot_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dh12_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.boot = val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -948,7 +1112,8 @@ int32_t lis2dh12_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dh12_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
*val = (uint8_t)ctrl_reg5.boot;
return ret;
@@ -962,10 +1127,13 @@ int32_t lis2dh12_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dh12_status_get(stmdev_ctx_t *ctx, lis2dh12_status_reg_t *val)
+int32_t lis2dh12_status_get(stmdev_ctx_t *ctx,
+ lis2dh12_status_reg_t *val)
{
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_STATUS_REG, (uint8_t*) val, 1);
+
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_STATUS_REG, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -993,7 +1161,9 @@ int32_t lis2dh12_int1_gen_conf_set(stmdev_ctx_t *ctx,
lis2dh12_int1_cfg_t *val)
{
int32_t ret;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_INT1_CFG, (uint8_t*) val, 1);
+
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_INT1_CFG, (uint8_t *) val, 1);
+
return ret;
}
@@ -1009,7 +1179,9 @@ int32_t lis2dh12_int1_gen_conf_get(stmdev_ctx_t *ctx,
lis2dh12_int1_cfg_t *val)
{
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_CFG, (uint8_t*) val, 1);
+
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_CFG, (uint8_t *) val, 1);
+
return ret;
}
@@ -1025,7 +1197,9 @@ int32_t lis2dh12_int1_gen_source_get(stmdev_ctx_t *ctx,
lis2dh12_int1_src_t *val)
{
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_SRC, (uint8_t*) val, 1);
+
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_SRC, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1038,16 +1212,20 @@ int32_t lis2dh12_int1_gen_source_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dh12_int1_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lis2dh12_int1_gen_threshold_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lis2dh12_int1_ths_t int1_ths;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_THS, (uint8_t*)&int1_ths, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_THS, (uint8_t *)&int1_ths, 1);
+
+ if (ret == 0)
+ {
int1_ths.ths = val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_INT1_THS, (uint8_t*)&int1_ths, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_INT1_THS, (uint8_t *)&int1_ths, 1);
}
+
return ret;
}
@@ -1061,12 +1239,13 @@ int32_t lis2dh12_int1_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dh12_int1_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2dh12_int1_gen_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2dh12_int1_ths_t int1_ths;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_THS, (uint8_t*)&int1_ths, 1);
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_THS, (uint8_t *)&int1_ths, 1);
*val = (uint8_t)int1_ths.ths;
return ret;
@@ -1086,11 +1265,16 @@ int32_t lis2dh12_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dh12_int1_duration_t int1_duration;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_DURATION, (uint8_t*)&int1_duration, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_DURATION,
+ (uint8_t *)&int1_duration, 1);
+
+ if (ret == 0)
+ {
int1_duration.d = val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_INT1_DURATION, (uint8_t*)&int1_duration, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_INT1_DURATION,
+ (uint8_t *)&int1_duration, 1);
}
+
return ret;
}
@@ -1103,12 +1287,14 @@ int32_t lis2dh12_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dh12_int1_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2dh12_int1_gen_duration_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2dh12_int1_duration_t int1_duration;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_DURATION, (uint8_t*)&int1_duration, 1);
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_DURATION,
+ (uint8_t *)&int1_duration, 1);
*val = (uint8_t)int1_duration.d;
return ret;
@@ -1139,7 +1325,9 @@ int32_t lis2dh12_int2_gen_conf_set(stmdev_ctx_t *ctx,
lis2dh12_int2_cfg_t *val)
{
int32_t ret;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_INT2_CFG, (uint8_t*) val, 1);
+
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_INT2_CFG, (uint8_t *) val, 1);
+
return ret;
}
@@ -1155,7 +1343,9 @@ int32_t lis2dh12_int2_gen_conf_get(stmdev_ctx_t *ctx,
lis2dh12_int2_cfg_t *val)
{
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_CFG, (uint8_t*) val, 1);
+
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_CFG, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1170,7 +1360,9 @@ int32_t lis2dh12_int2_gen_source_get(stmdev_ctx_t *ctx,
lis2dh12_int2_src_t *val)
{
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_SRC, (uint8_t*) val, 1);
+
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_SRC, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1183,16 +1375,20 @@ int32_t lis2dh12_int2_gen_source_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dh12_int2_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lis2dh12_int2_gen_threshold_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lis2dh12_int2_ths_t int2_ths;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_THS, (uint8_t*)&int2_ths, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_THS, (uint8_t *)&int2_ths, 1);
+
+ if (ret == 0)
+ {
int2_ths.ths = val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_INT2_THS, (uint8_t*)&int2_ths, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_INT2_THS, (uint8_t *)&int2_ths, 1);
}
+
return ret;
}
@@ -1206,12 +1402,13 @@ int32_t lis2dh12_int2_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dh12_int2_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2dh12_int2_gen_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2dh12_int2_ths_t int2_ths;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_THS, (uint8_t*)&int2_ths, 1);
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_THS, (uint8_t *)&int2_ths, 1);
*val = (uint8_t)int2_ths.ths;
return ret;
@@ -1231,11 +1428,16 @@ int32_t lis2dh12_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dh12_int2_duration_t int2_duration;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_DURATION, (uint8_t*)&int2_duration, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_DURATION,
+ (uint8_t *)&int2_duration, 1);
+
+ if (ret == 0)
+ {
int2_duration.d = val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_INT2_DURATION, (uint8_t*)&int2_duration, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_INT2_DURATION,
+ (uint8_t *)&int2_duration, 1);
}
+
return ret;
}
@@ -1248,12 +1450,14 @@ int32_t lis2dh12_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dh12_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2dh12_int2_gen_duration_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2dh12_int2_duration_t int2_duration;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_DURATION, (uint8_t*)&int2_duration, 1);
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_DURATION,
+ (uint8_t *)&int2_duration, 1);
*val = (uint8_t)int2_duration.d;
return ret;
@@ -1266,7 +1470,7 @@ int32_t lis2dh12_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @defgroup LIS2DH12_Interrupt_pins
- * @brief This section group all the functions that manage interrup pins
+ * @brief This section group all the functions that manage interrupt pins
* @{
*
*/
@@ -1285,11 +1489,16 @@ int32_t lis2dh12_high_pass_int_conf_set(stmdev_ctx_t *ctx,
lis2dh12_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hp = (uint8_t)val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -1307,36 +1516,48 @@ int32_t lis2dh12_high_pass_int_conf_get(stmdev_ctx_t *ctx,
lis2dh12_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- switch (ctrl_reg2.hp) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ switch (ctrl_reg2.hp)
+ {
case LIS2DH12_DISC_FROM_INT_GENERATOR:
*val = LIS2DH12_DISC_FROM_INT_GENERATOR;
break;
+
case LIS2DH12_ON_INT1_GEN:
*val = LIS2DH12_ON_INT1_GEN;
break;
+
case LIS2DH12_ON_INT2_GEN:
*val = LIS2DH12_ON_INT2_GEN;
break;
+
case LIS2DH12_ON_TAP_GEN:
*val = LIS2DH12_ON_TAP_GEN;
break;
+
case LIS2DH12_ON_INT1_INT2_GEN:
*val = LIS2DH12_ON_INT1_INT2_GEN;
break;
+
case LIS2DH12_ON_INT1_TAP_GEN:
*val = LIS2DH12_ON_INT1_TAP_GEN;
break;
+
case LIS2DH12_ON_INT2_TAP_GEN:
*val = LIS2DH12_ON_INT2_TAP_GEN;
break;
+
case LIS2DH12_ON_INT1_INT2_TAP_GEN:
*val = LIS2DH12_ON_INT1_INT2_TAP_GEN;
break;
+
default:
*val = LIS2DH12_DISC_FROM_INT_GENERATOR;
break;
}
+
return ret;
}
@@ -1352,7 +1573,9 @@ int32_t lis2dh12_pin_int1_config_set(stmdev_ctx_t *ctx,
lis2dh12_ctrl_reg3_t *val)
{
int32_t ret;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG3, (uint8_t*) val, 1);
+
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG3, (uint8_t *) val, 1);
+
return ret;
}
@@ -1368,7 +1591,9 @@ int32_t lis2dh12_pin_int1_config_get(stmdev_ctx_t *ctx,
lis2dh12_ctrl_reg3_t *val)
{
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG3, (uint8_t*) val, 1);
+
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG3, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1381,16 +1606,22 @@ int32_t lis2dh12_pin_int1_config_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dh12_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lis2dh12_int2_pin_detect_4d_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lis2dh12_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.d4d_int2 = val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -1403,12 +1634,14 @@ int32_t lis2dh12_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dh12_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2dh12_int2_pin_detect_4d_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2dh12_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
*val = (uint8_t)ctrl_reg5.d4d_int2;
return ret;
@@ -1430,11 +1663,16 @@ int32_t lis2dh12_int2_pin_notification_mode_set(stmdev_ctx_t *ctx,
lis2dh12_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.lir_int2 = (uint8_t)val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -1454,18 +1692,24 @@ int32_t lis2dh12_int2_pin_notification_mode_get(stmdev_ctx_t *ctx,
lis2dh12_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- switch (ctrl_reg5.lir_int2) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
+
+ switch (ctrl_reg5.lir_int2)
+ {
case LIS2DH12_INT2_PULSED:
*val = LIS2DH12_INT2_PULSED;
break;
+
case LIS2DH12_INT2_LATCHED:
*val = LIS2DH12_INT2_LATCHED;
break;
+
default:
*val = LIS2DH12_INT2_PULSED;
break;
}
+
return ret;
}
@@ -1478,16 +1722,22 @@ int32_t lis2dh12_int2_pin_notification_mode_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dh12_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lis2dh12_int1_pin_detect_4d_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lis2dh12_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.d4d_int1 = val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -1500,12 +1750,14 @@ int32_t lis2dh12_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dh12_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2dh12_int1_pin_detect_4d_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2dh12_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
*val = (uint8_t)ctrl_reg5.d4d_int1;
return ret;
@@ -1526,11 +1778,16 @@ int32_t lis2dh12_int1_pin_notification_mode_set(stmdev_ctx_t *ctx,
lis2dh12_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.lir_int1 = (uint8_t)val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -1549,18 +1806,24 @@ int32_t lis2dh12_int1_pin_notification_mode_get(stmdev_ctx_t *ctx,
lis2dh12_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- switch (ctrl_reg5.lir_int1) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
+
+ switch (ctrl_reg5.lir_int1)
+ {
case LIS2DH12_INT1_PULSED:
*val = LIS2DH12_INT1_PULSED;
break;
+
case LIS2DH12_INT1_LATCHED:
*val = LIS2DH12_INT1_LATCHED;
break;
+
default:
*val = LIS2DH12_INT1_PULSED;
break;
}
+
return ret;
}
@@ -1576,7 +1839,9 @@ int32_t lis2dh12_pin_int2_config_set(stmdev_ctx_t *ctx,
lis2dh12_ctrl_reg6_t *val)
{
int32_t ret;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG6, (uint8_t*) val, 1);
+
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG6, (uint8_t *) val, 1);
+
return ret;
}
@@ -1592,7 +1857,9 @@ int32_t lis2dh12_pin_int2_config_get(stmdev_ctx_t *ctx,
lis2dh12_ctrl_reg6_t *val)
{
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG6, (uint8_t*) val, 1);
+
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG6, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1620,11 +1887,16 @@ int32_t lis2dh12_fifo_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dh12_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.fifo_en = val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -1641,7 +1913,8 @@ int32_t lis2dh12_fifo_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dh12_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
*val = (uint8_t)ctrl_reg5.fifo_en;
return ret;
@@ -1660,11 +1933,16 @@ int32_t lis2dh12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl_reg.fth = val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
}
+
return ret;
}
@@ -1681,7 +1959,8 @@ int32_t lis2dh12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
*val = (uint8_t)fifo_ctrl_reg.fth;
return ret;
@@ -1701,11 +1980,16 @@ int32_t lis2dh12_fifo_trigger_event_set(stmdev_ctx_t *ctx,
lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl_reg.tr = (uint8_t)val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
}
+
return ret;
}
@@ -1723,18 +2007,24 @@ int32_t lis2dh12_fifo_trigger_event_get(stmdev_ctx_t *ctx,
lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
- switch (fifo_ctrl_reg.tr) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
+
+ switch (fifo_ctrl_reg.tr)
+ {
case LIS2DH12_INT1_GEN:
*val = LIS2DH12_INT1_GEN;
break;
+
case LIS2DH12_INT2_GEN:
*val = LIS2DH12_INT2_GEN;
break;
+
default:
*val = LIS2DH12_INT1_GEN;
break;
}
+
return ret;
}
@@ -1751,11 +2041,16 @@ int32_t lis2dh12_fifo_mode_set(stmdev_ctx_t *ctx, lis2dh12_fm_t val)
lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl_reg.fm = (uint8_t)val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
}
+
return ret;
}
@@ -1772,24 +2067,32 @@ int32_t lis2dh12_fifo_mode_get(stmdev_ctx_t *ctx, lis2dh12_fm_t *val)
lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
- switch (fifo_ctrl_reg.fm) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
+
+ switch (fifo_ctrl_reg.fm)
+ {
case LIS2DH12_BYPASS_MODE:
*val = LIS2DH12_BYPASS_MODE;
break;
+
case LIS2DH12_FIFO_MODE:
*val = LIS2DH12_FIFO_MODE;
break;
+
case LIS2DH12_DYNAMIC_STREAM_MODE:
*val = LIS2DH12_DYNAMIC_STREAM_MODE;
break;
+
case LIS2DH12_STREAM_TO_FIFO_MODE:
*val = LIS2DH12_STREAM_TO_FIFO_MODE;
break;
+
default:
*val = LIS2DH12_BYPASS_MODE;
break;
}
+
return ret;
}
@@ -1805,7 +2108,9 @@ int32_t lis2dh12_fifo_status_get(stmdev_ctx_t *ctx,
lis2dh12_fifo_src_reg_t *val)
{
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_SRC_REG, (uint8_t*) val, 1);
+
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_SRC_REG, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1821,7 +2126,8 @@ int32_t lis2dh12_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dh12_fifo_src_reg_t fifo_src_reg;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1);
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_SRC_REG,
+ (uint8_t *)&fifo_src_reg, 1);
*val = (uint8_t)fifo_src_reg.fss;
return ret;
@@ -1839,7 +2145,8 @@ int32_t lis2dh12_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dh12_fifo_src_reg_t fifo_src_reg;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1);
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_SRC_REG,
+ (uint8_t *)&fifo_src_reg, 1);
*val = (uint8_t)fifo_src_reg.empty;
return ret;
@@ -1857,7 +2164,8 @@ int32_t lis2dh12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dh12_fifo_src_reg_t fifo_src_reg;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1);
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_SRC_REG,
+ (uint8_t *)&fifo_src_reg, 1);
*val = (uint8_t)fifo_src_reg.ovrn_fifo;
return ret;
@@ -1875,7 +2183,8 @@ int32_t lis2dh12_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dh12_fifo_src_reg_t fifo_src_reg;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1);
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_SRC_REG,
+ (uint8_t *)&fifo_src_reg, 1);
*val = (uint8_t)fifo_src_reg.wtm;
return ret;
@@ -1901,10 +2210,13 @@ int32_t lis2dh12_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dh12_tap_conf_set(stmdev_ctx_t *ctx, lis2dh12_click_cfg_t *val)
+int32_t lis2dh12_tap_conf_set(stmdev_ctx_t *ctx,
+ lis2dh12_click_cfg_t *val)
{
int32_t ret;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_CLICK_CFG, (uint8_t*) val, 1);
+
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_CLICK_CFG, (uint8_t *) val, 1);
+
return ret;
}
@@ -1916,10 +2228,13 @@ int32_t lis2dh12_tap_conf_set(stmdev_ctx_t *ctx, lis2dh12_click_cfg_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dh12_tap_conf_get(stmdev_ctx_t *ctx, lis2dh12_click_cfg_t *val)
+int32_t lis2dh12_tap_conf_get(stmdev_ctx_t *ctx,
+ lis2dh12_click_cfg_t *val)
{
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_CFG, (uint8_t*) val, 1);
+
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_CFG, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1930,10 +2245,13 @@ int32_t lis2dh12_tap_conf_get(stmdev_ctx_t *ctx, lis2dh12_click_cfg_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dh12_tap_source_get(stmdev_ctx_t *ctx, lis2dh12_click_src_t *val)
+int32_t lis2dh12_tap_source_get(stmdev_ctx_t *ctx,
+ lis2dh12_click_src_t *val)
{
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_SRC, (uint8_t*) val, 1);
+
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_SRC, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1950,11 +2268,16 @@ int32_t lis2dh12_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dh12_click_ths_t click_ths;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_THS, (uint8_t*)&click_ths, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_THS,
+ (uint8_t *)&click_ths, 1);
+
+ if (ret == 0)
+ {
click_ths.ths = val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_CLICK_THS, (uint8_t*)&click_ths, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_CLICK_THS,
+ (uint8_t *)&click_ths, 1);
}
+
return ret;
}
@@ -1972,7 +2295,8 @@ int32_t lis2dh12_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dh12_click_ths_t click_ths;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_THS, (uint8_t*)&click_ths, 1);
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_THS,
+ (uint8_t *)&click_ths, 1);
*val = (uint8_t)click_ths.ths;
return ret;
@@ -1995,11 +2319,16 @@ int32_t lis2dh12_tap_notification_mode_set(stmdev_ctx_t *ctx,
lis2dh12_click_ths_t click_ths;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_THS, (uint8_t*)&click_ths, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_THS,
+ (uint8_t *)&click_ths, 1);
+
+ if (ret == 0)
+ {
click_ths.lir_click = (uint8_t)val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_CLICK_THS, (uint8_t*)&click_ths, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_CLICK_THS,
+ (uint8_t *)&click_ths, 1);
}
+
return ret;
}
@@ -2020,18 +2349,24 @@ int32_t lis2dh12_tap_notification_mode_get(stmdev_ctx_t *ctx,
lis2dh12_click_ths_t click_ths;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_THS, (uint8_t*)&click_ths, 1);
- switch (click_ths.lir_click) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_THS,
+ (uint8_t *)&click_ths, 1);
+
+ switch (click_ths.lir_click)
+ {
case LIS2DH12_TAP_PULSED:
*val = LIS2DH12_TAP_PULSED;
break;
+
case LIS2DH12_TAP_LATCHED:
*val = LIS2DH12_TAP_LATCHED;
break;
+
default:
*val = LIS2DH12_TAP_PULSED;
break;
}
+
return ret;
}
@@ -2050,11 +2385,16 @@ int32_t lis2dh12_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dh12_time_limit_t time_limit;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_LIMIT, (uint8_t*)&time_limit, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_LIMIT,
+ (uint8_t *)&time_limit, 1);
+
+ if (ret == 0)
+ {
time_limit.tli = val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_TIME_LIMIT, (uint8_t*)&time_limit, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_TIME_LIMIT,
+ (uint8_t *)&time_limit, 1);
}
+
return ret;
}
@@ -2073,7 +2413,8 @@ int32_t lis2dh12_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dh12_time_limit_t time_limit;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_LIMIT, (uint8_t*)&time_limit, 1);
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_LIMIT,
+ (uint8_t *)&time_limit, 1);
*val = (uint8_t)time_limit.tli;
return ret;
@@ -2095,11 +2436,16 @@ int32_t lis2dh12_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dh12_time_latency_t time_latency;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_LATENCY, (uint8_t*)&time_latency, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_LATENCY,
+ (uint8_t *)&time_latency, 1);
+
+ if (ret == 0)
+ {
time_latency.tla = val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_TIME_LATENCY, (uint8_t*)&time_latency, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_TIME_LATENCY,
+ (uint8_t *)&time_latency, 1);
}
+
return ret;
}
@@ -2119,7 +2465,8 @@ int32_t lis2dh12_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dh12_time_latency_t time_latency;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_LATENCY, (uint8_t*)&time_latency, 1);
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_LATENCY,
+ (uint8_t *)&time_latency, 1);
*val = (uint8_t)time_latency.tla;
return ret;
@@ -2136,16 +2483,22 @@ int32_t lis2dh12_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dh12_double_tap_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lis2dh12_double_tap_timeout_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lis2dh12_time_window_t time_window;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_WINDOW, (uint8_t*)&time_window, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_WINDOW,
+ (uint8_t *)&time_window, 1);
+
+ if (ret == 0)
+ {
time_window.tw = val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_TIME_WINDOW, (uint8_t*)&time_window, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_TIME_WINDOW,
+ (uint8_t *)&time_window, 1);
}
+
return ret;
}
@@ -2160,12 +2513,14 @@ int32_t lis2dh12_double_tap_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dh12_double_tap_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2dh12_double_tap_timeout_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2dh12_time_window_t time_window;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_WINDOW, (uint8_t*)&time_window, 1);
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_WINDOW,
+ (uint8_t *)&time_window, 1);
*val = (uint8_t)time_window.tw;
return ret;
@@ -2199,11 +2554,14 @@ int32_t lis2dh12_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dh12_act_ths_t act_ths;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_ACT_THS, (uint8_t*)&act_ths, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_ACT_THS, (uint8_t *)&act_ths, 1);
+
+ if (ret == 0)
+ {
act_ths.acth = val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_ACT_THS, (uint8_t*)&act_ths, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_ACT_THS, (uint8_t *)&act_ths, 1);
}
+
return ret;
}
@@ -2222,7 +2580,7 @@ int32_t lis2dh12_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dh12_act_ths_t act_ths;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_ACT_THS, (uint8_t*)&act_ths, 1);
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_ACT_THS, (uint8_t *)&act_ths, 1);
*val = (uint8_t)act_ths.acth;
return ret;
@@ -2242,11 +2600,14 @@ int32_t lis2dh12_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dh12_act_dur_t act_dur;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_ACT_DUR, (uint8_t*)&act_dur, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_ACT_DUR, (uint8_t *)&act_dur, 1);
+
+ if (ret == 0)
+ {
act_dur.actd = val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_ACT_DUR, (uint8_t*)&act_dur, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_ACT_DUR, (uint8_t *)&act_dur, 1);
}
+
return ret;
}
@@ -2264,7 +2625,7 @@ int32_t lis2dh12_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dh12_act_dur_t act_dur;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_ACT_DUR, (uint8_t*)&act_dur, 1);
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_ACT_DUR, (uint8_t *)&act_dur, 1);
*val = (uint8_t)act_dur.actd;
return ret;
@@ -2297,11 +2658,16 @@ int32_t lis2dh12_pin_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
lis2dh12_ctrl_reg0_t ctrl_reg0;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG0, (uint8_t*)&ctrl_reg0, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG0,
+ (uint8_t *)&ctrl_reg0, 1);
+
+ if (ret == 0)
+ {
ctrl_reg0.sdo_pu_disc = (uint8_t)val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG0, (uint8_t*)&ctrl_reg0, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG0,
+ (uint8_t *)&ctrl_reg0, 1);
}
+
return ret;
}
@@ -2319,18 +2685,24 @@ int32_t lis2dh12_pin_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
lis2dh12_ctrl_reg0_t ctrl_reg0;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG0, (uint8_t*)&ctrl_reg0, 1);
- switch (ctrl_reg0.sdo_pu_disc) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG0,
+ (uint8_t *)&ctrl_reg0, 1);
+
+ switch (ctrl_reg0.sdo_pu_disc)
+ {
case LIS2DH12_PULL_UP_DISCONNECT:
*val = LIS2DH12_PULL_UP_DISCONNECT;
break;
+
case LIS2DH12_PULL_UP_CONNECT:
*val = LIS2DH12_PULL_UP_CONNECT;
break;
+
default:
*val = LIS2DH12_PULL_UP_DISCONNECT;
break;
}
+
return ret;
}
@@ -2347,11 +2719,16 @@ int32_t lis2dh12_spi_mode_set(stmdev_ctx_t *ctx, lis2dh12_sim_t val)
lis2dh12_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if (ret == 0) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.sim = (uint8_t)val;
- ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -2368,18 +2745,24 @@ int32_t lis2dh12_spi_mode_get(stmdev_ctx_t *ctx, lis2dh12_sim_t *val)
lis2dh12_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- switch (ctrl_reg4.sim) {
+ ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ switch (ctrl_reg4.sim)
+ {
case LIS2DH12_SPI_4_WIRE:
*val = LIS2DH12_SPI_4_WIRE;
break;
+
case LIS2DH12_SPI_3_WIRE:
*val = LIS2DH12_SPI_3_WIRE;
break;
+
default:
*val = LIS2DH12_SPI_4_WIRE;
break;
}
+
return ret;
}
diff --git a/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.h b/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.h
index 9b04709d73de3041587b9f44b1d163076518214d..e5567abc1b2651da92bbc70afbb40eca81882d73 100644
--- a/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.h
+++ b/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file lis2dh12_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lis2dh12_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lis2dh12_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lis2dh12_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LIS2DH12_REGS_H
#define LIS2DH12_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup LIS2DH12
@@ -65,7 +66,7 @@
* @}
*
*/
-
+
/** @defgroup STMicroelectronics sensors common types
* @{
*
@@ -74,7 +75,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -106,11 +108,11 @@ typedef struct{
* @{
*
*/
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
-
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -131,7 +133,7 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
+ * You can create a sensor configuration by your own or using
* Unico / Unicleo tools available on STMicroelectronics
* web site.
*
@@ -139,7 +141,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -174,7 +177,8 @@ typedef struct {
*/
#define LIS2DH12_STATUS_REG_AUX 0x07U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t tda : 1;
@@ -195,7 +199,8 @@ typedef struct {
#define LIS2DH12_WHO_AM_I 0x0FU
#define LIS2DH12_CTRL_REG0 0x1EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 7;
uint8_t sdo_pu_disc : 1;
@@ -206,7 +211,8 @@ typedef struct {
} lis2dh12_ctrl_reg0_t;
#define LIS2DH12_TEMP_CFG_REG 0x1FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 6;
uint8_t temp_en : 2;
@@ -217,7 +223,8 @@ typedef struct {
} lis2dh12_temp_cfg_reg_t;
#define LIS2DH12_CTRL_REG1 0x20U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xen : 1;
uint8_t yen : 1;
@@ -234,7 +241,8 @@ typedef struct {
} lis2dh12_ctrl_reg1_t;
#define LIS2DH12_CTRL_REG2 0x21U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t hp : 3; /* HPCLICK + HP_IA2 + HP_IA1 -> HP */
uint8_t fds : 1;
@@ -249,7 +257,8 @@ typedef struct {
} lis2dh12_ctrl_reg2_t;
#define LIS2DH12_CTRL_REG3 0x22U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t i1_overrun : 1;
@@ -272,7 +281,8 @@ typedef struct {
} lis2dh12_ctrl_reg3_t;
#define LIS2DH12_CTRL_REG4 0x23U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t st : 2;
@@ -291,7 +301,8 @@ typedef struct {
} lis2dh12_ctrl_reg4_t;
#define LIS2DH12_CTRL_REG5 0x24U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d4d_int2 : 1;
uint8_t lir_int2 : 1;
@@ -312,7 +323,8 @@ typedef struct {
} lis2dh12_ctrl_reg5_t;
#define LIS2DH12_CTRL_REG6 0x25U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t int_polarity : 1;
@@ -336,7 +348,8 @@ typedef struct {
#define LIS2DH12_REFERENCE 0x26U
#define LIS2DH12_STATUS_REG 0x27U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xda : 1;
uint8_t yda : 1;
@@ -365,7 +378,8 @@ typedef struct {
#define LIS2DH12_OUT_Z_L 0x2CU
#define LIS2DH12_OUT_Z_H 0x2DU
#define LIS2DH12_FIFO_CTRL_REG 0x2EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fth : 5;
uint8_t tr : 1;
@@ -378,7 +392,8 @@ typedef struct {
} lis2dh12_fifo_ctrl_reg_t;
#define LIS2DH12_FIFO_SRC_REG 0x2FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fss : 5;
uint8_t empty : 1;
@@ -393,7 +408,8 @@ typedef struct {
} lis2dh12_fifo_src_reg_t;
#define LIS2DH12_INT1_CFG 0x30U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlie : 1;
uint8_t xhie : 1;
@@ -416,7 +432,8 @@ typedef struct {
} lis2dh12_int1_cfg_t;
#define LIS2DH12_INT1_SRC 0x31U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
@@ -439,7 +456,8 @@ typedef struct {
} lis2dh12_int1_src_t;
#define LIS2DH12_INT1_THS 0x32U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t not_used_01 : 1;
@@ -450,7 +468,8 @@ typedef struct {
} lis2dh12_int1_ths_t;
#define LIS2DH12_INT1_DURATION 0x33U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d : 7;
uint8_t not_used_01 : 1;
@@ -461,7 +480,8 @@ typedef struct {
} lis2dh12_int1_duration_t;
#define LIS2DH12_INT2_CFG 0x34U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlie : 1;
uint8_t xhie : 1;
@@ -484,7 +504,8 @@ typedef struct {
} lis2dh12_int2_cfg_t;
#define LIS2DH12_INT2_SRC 0x35U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
@@ -507,7 +528,8 @@ typedef struct {
} lis2dh12_int2_src_t;
#define LIS2DH12_INT2_THS 0x36U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t not_used_01 : 1;
@@ -518,7 +540,8 @@ typedef struct {
} lis2dh12_int2_ths_t;
#define LIS2DH12_INT2_DURATION 0x37U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d : 7;
uint8_t not_used_01 : 1;
@@ -529,7 +552,8 @@ typedef struct {
} lis2dh12_int2_duration_t;
#define LIS2DH12_CLICK_CFG 0x38U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xs : 1;
uint8_t xd : 1;
@@ -550,7 +574,8 @@ typedef struct {
} lis2dh12_click_cfg_t;
#define LIS2DH12_CLICK_SRC 0x39U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t x : 1;
uint8_t y : 1;
@@ -573,7 +598,8 @@ typedef struct {
} lis2dh12_click_src_t;
#define LIS2DH12_CLICK_THS 0x3AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t lir_click : 1;
@@ -584,7 +610,8 @@ typedef struct {
} lis2dh12_click_ths_t;
#define LIS2DH12_TIME_LIMIT 0x3BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tli : 7;
uint8_t not_used_01 : 1;
@@ -595,17 +622,20 @@ typedef struct {
} lis2dh12_time_limit_t;
#define LIS2DH12_TIME_LATENCY 0x3CU
-typedef struct {
+typedef struct
+{
uint8_t tla : 8;
} lis2dh12_time_latency_t;
#define LIS2DH12_TIME_WINDOW 0x3DU
-typedef struct {
+typedef struct
+{
uint8_t tw : 8;
} lis2dh12_time_window_t;
#define LIS2DH12_ACT_THS 0x3EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t acth : 7;
uint8_t not_used_01 : 1;
@@ -616,23 +646,25 @@ typedef struct {
} lis2dh12_act_ths_t;
#define LIS2DH12_ACT_DUR 0x3FU
-typedef struct {
+typedef struct
+{
uint8_t actd : 8;
} lis2dh12_act_dur_t;
/**
* @defgroup LIS2DH12_Register_Union
- * @brief This union group all the registers that has a bitfield
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is usefull but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
- * REMOVING this union you are complient with:
+ * REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
*
* @{
*
*/
-typedef union{
+typedef union
+{
lis2dh12_status_reg_aux_t status_reg_aux;
lis2dh12_ctrl_reg0_t ctrl_reg0;
lis2dh12_temp_cfg_reg_t temp_cfg_reg;
@@ -670,9 +702,11 @@ typedef union{
*
*/
-int32_t lis2dh12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lis2dh12_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t lis2dh12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lis2dh12_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
float_t lis2dh12_from_fs2_hr_to_mg(int16_t lsb);
@@ -693,14 +727,16 @@ float_t lis2dh12_from_fs8_lp_to_mg(int16_t lsb);
float_t lis2dh12_from_fs16_lp_to_mg(int16_t lsb);
float_t lis2dh12_from_lsb_lp_to_celsius(int16_t lsb);
-int32_t lis2dh12_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lis2dh12_temp_status_reg_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
int32_t lis2dh12_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2dh12_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2dh12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val);
-typedef enum {
+typedef enum
+{
LIS2DH12_TEMP_DISABLE = 0,
LIS2DH12_TEMP_ENABLE = 3,
} lis2dh12_temp_en_t;
@@ -709,7 +745,8 @@ int32_t lis2dh12_temperature_meas_set(stmdev_ctx_t *ctx,
int32_t lis2dh12_temperature_meas_get(stmdev_ctx_t *ctx,
lis2dh12_temp_en_t *val);
-typedef enum {
+typedef enum
+{
LIS2DH12_HR_12bit = 0,
LIS2DH12_NM_10bit = 1,
LIS2DH12_LP_8bit = 2,
@@ -719,7 +756,8 @@ int32_t lis2dh12_operating_mode_set(stmdev_ctx_t *ctx,
int32_t lis2dh12_operating_mode_get(stmdev_ctx_t *ctx,
lis2dh12_op_md_t *val);
-typedef enum {
+typedef enum
+{
LIS2DH12_POWER_DOWN = 0x00,
LIS2DH12_ODR_1Hz = 0x01,
LIS2DH12_ODR_10Hz = 0x02,
@@ -732,12 +770,16 @@ typedef enum {
LIS2DH12_ODR_5kHz376_LP_1kHz344_NM_HP = 0x09,
} lis2dh12_odr_t;
int32_t lis2dh12_data_rate_set(stmdev_ctx_t *ctx, lis2dh12_odr_t val);
-int32_t lis2dh12_data_rate_get(stmdev_ctx_t *ctx, lis2dh12_odr_t *val);
+int32_t lis2dh12_data_rate_get(stmdev_ctx_t *ctx,
+ lis2dh12_odr_t *val);
-int32_t lis2dh12_high_pass_on_outputs_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2dh12_high_pass_on_outputs_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2dh12_high_pass_on_outputs_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2dh12_high_pass_on_outputs_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DH12_AGGRESSIVE = 0,
LIS2DH12_STRONG = 1,
LIS2DH12_MEDIUM = 2,
@@ -748,39 +790,50 @@ int32_t lis2dh12_high_pass_bandwidth_set(stmdev_ctx_t *ctx,
int32_t lis2dh12_high_pass_bandwidth_get(stmdev_ctx_t *ctx,
lis2dh12_hpcf_t *val);
-typedef enum {
+typedef enum
+{
LIS2DH12_NORMAL_WITH_RST = 0,
LIS2DH12_REFERENCE_MODE = 1,
LIS2DH12_NORMAL = 2,
LIS2DH12_AUTORST_ON_INT = 3,
} lis2dh12_hpm_t;
-int32_t lis2dh12_high_pass_mode_set(stmdev_ctx_t *ctx, lis2dh12_hpm_t val);
-int32_t lis2dh12_high_pass_mode_get(stmdev_ctx_t *ctx, lis2dh12_hpm_t *val);
+int32_t lis2dh12_high_pass_mode_set(stmdev_ctx_t *ctx,
+ lis2dh12_hpm_t val);
+int32_t lis2dh12_high_pass_mode_get(stmdev_ctx_t *ctx,
+ lis2dh12_hpm_t *val);
-typedef enum {
+typedef enum
+{
LIS2DH12_2g = 0,
LIS2DH12_4g = 1,
LIS2DH12_8g = 2,
LIS2DH12_16g = 3,
} lis2dh12_fs_t;
int32_t lis2dh12_full_scale_set(stmdev_ctx_t *ctx, lis2dh12_fs_t val);
-int32_t lis2dh12_full_scale_get(stmdev_ctx_t *ctx, lis2dh12_fs_t *val);
+int32_t lis2dh12_full_scale_get(stmdev_ctx_t *ctx,
+ lis2dh12_fs_t *val);
-int32_t lis2dh12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2dh12_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2dh12_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2dh12_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lis2dh12_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lis2dh12_filter_reference_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lis2dh12_filter_reference_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lis2dh12_filter_reference_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
int32_t lis2dh12_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2dh12_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lis2dh12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t lis2dh12_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
int32_t lis2dh12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
-typedef enum {
+typedef enum
+{
LIS2DH12_ST_DISABLE = 0,
LIS2DH12_ST_POSITIVE = 1,
LIS2DH12_ST_NEGATIVE = 2,
@@ -788,17 +841,21 @@ typedef enum {
int32_t lis2dh12_self_test_set(stmdev_ctx_t *ctx, lis2dh12_st_t val);
int32_t lis2dh12_self_test_get(stmdev_ctx_t *ctx, lis2dh12_st_t *val);
-typedef enum {
+typedef enum
+{
LIS2DH12_LSB_AT_LOW_ADD = 0,
LIS2DH12_MSB_AT_LOW_ADD = 1,
} lis2dh12_ble_t;
-int32_t lis2dh12_data_format_set(stmdev_ctx_t *ctx, lis2dh12_ble_t val);
-int32_t lis2dh12_data_format_get(stmdev_ctx_t *ctx, lis2dh12_ble_t *val);
+int32_t lis2dh12_data_format_set(stmdev_ctx_t *ctx,
+ lis2dh12_ble_t val);
+int32_t lis2dh12_data_format_get(stmdev_ctx_t *ctx,
+ lis2dh12_ble_t *val);
int32_t lis2dh12_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dh12_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lis2dh12_status_get(stmdev_ctx_t *ctx, lis2dh12_status_reg_t *val);
+int32_t lis2dh12_status_get(stmdev_ctx_t *ctx,
+ lis2dh12_status_reg_t *val);
int32_t lis2dh12_int1_gen_conf_set(stmdev_ctx_t *ctx,
lis2dh12_int1_cfg_t *val);
@@ -808,11 +865,15 @@ int32_t lis2dh12_int1_gen_conf_get(stmdev_ctx_t *ctx,
int32_t lis2dh12_int1_gen_source_get(stmdev_ctx_t *ctx,
lis2dh12_int1_src_t *val);
-int32_t lis2dh12_int1_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2dh12_int1_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2dh12_int1_gen_threshold_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2dh12_int1_gen_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lis2dh12_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2dh12_int1_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2dh12_int1_gen_duration_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2dh12_int1_gen_duration_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lis2dh12_int2_gen_conf_set(stmdev_ctx_t *ctx,
lis2dh12_int2_cfg_t *val);
@@ -822,13 +883,18 @@ int32_t lis2dh12_int2_gen_conf_get(stmdev_ctx_t *ctx,
int32_t lis2dh12_int2_gen_source_get(stmdev_ctx_t *ctx,
lis2dh12_int2_src_t *val);
-int32_t lis2dh12_int2_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2dh12_int2_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2dh12_int2_gen_threshold_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2dh12_int2_gen_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lis2dh12_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2dh12_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2dh12_int2_gen_duration_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2dh12_int2_gen_duration_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DH12_DISC_FROM_INT_GENERATOR = 0,
LIS2DH12_ON_INT1_GEN = 1,
LIS2DH12_ON_INT2_GEN = 2,
@@ -848,10 +914,13 @@ int32_t lis2dh12_pin_int1_config_set(stmdev_ctx_t *ctx,
int32_t lis2dh12_pin_int1_config_get(stmdev_ctx_t *ctx,
lis2dh12_ctrl_reg3_t *val);
-int32_t lis2dh12_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2dh12_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2dh12_int2_pin_detect_4d_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2dh12_int2_pin_detect_4d_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DH12_INT2_PULSED = 0,
LIS2DH12_INT2_LATCHED = 1,
} lis2dh12_lir_int2_t;
@@ -860,10 +929,13 @@ int32_t lis2dh12_int2_pin_notification_mode_set(stmdev_ctx_t *ctx,
int32_t lis2dh12_int2_pin_notification_mode_get(stmdev_ctx_t *ctx,
lis2dh12_lir_int2_t *val);
-int32_t lis2dh12_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2dh12_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2dh12_int1_pin_detect_4d_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2dh12_int1_pin_detect_4d_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DH12_INT1_PULSED = 0,
LIS2DH12_INT1_LATCHED = 1,
} lis2dh12_lir_int1_t;
@@ -883,7 +955,8 @@ int32_t lis2dh12_fifo_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2dh12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dh12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DH12_INT1_GEN = 0,
LIS2DH12_INT2_GEN = 1,
} lis2dh12_tr_t;
@@ -892,7 +965,8 @@ int32_t lis2dh12_fifo_trigger_event_set(stmdev_ctx_t *ctx,
int32_t lis2dh12_fifo_trigger_event_get(stmdev_ctx_t *ctx,
lis2dh12_tr_t *val);
-typedef enum {
+typedef enum
+{
LIS2DH12_BYPASS_MODE = 0,
LIS2DH12_FIFO_MODE = 1,
LIS2DH12_DYNAMIC_STREAM_MODE = 2,
@@ -912,8 +986,10 @@ int32_t lis2dh12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2dh12_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lis2dh12_tap_conf_set(stmdev_ctx_t *ctx, lis2dh12_click_cfg_t *val);
-int32_t lis2dh12_tap_conf_get(stmdev_ctx_t *ctx, lis2dh12_click_cfg_t *val);
+int32_t lis2dh12_tap_conf_set(stmdev_ctx_t *ctx,
+ lis2dh12_click_cfg_t *val);
+int32_t lis2dh12_tap_conf_get(stmdev_ctx_t *ctx,
+ lis2dh12_click_cfg_t *val);
int32_t lis2dh12_tap_source_get(stmdev_ctx_t *ctx,
lis2dh12_click_src_t *val);
@@ -921,7 +997,8 @@ int32_t lis2dh12_tap_source_get(stmdev_ctx_t *ctx,
int32_t lis2dh12_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dh12_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DH12_TAP_PULSED = 0,
LIS2DH12_TAP_LATCHED = 1,
} lis2dh12_lir_click_t;
@@ -936,8 +1013,10 @@ int32_t lis2dh12_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2dh12_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dh12_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lis2dh12_double_tap_timeout_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2dh12_double_tap_timeout_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2dh12_double_tap_timeout_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2dh12_double_tap_timeout_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lis2dh12_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dh12_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -945,7 +1024,8 @@ int32_t lis2dh12_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2dh12_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dh12_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DH12_PULL_UP_DISCONNECT = 0,
LIS2DH12_PULL_UP_CONNECT = 1,
} lis2dh12_sdo_pu_disc_t;
@@ -954,7 +1034,8 @@ int32_t lis2dh12_pin_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
int32_t lis2dh12_pin_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
lis2dh12_sdo_pu_disc_t *val);
-typedef enum {
+typedef enum
+{
LIS2DH12_SPI_4_WIRE = 0,
LIS2DH12_SPI_3_WIRE = 1,
} lis2dh12_sim_t;
diff --git a/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.c b/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.c
index 01c7ad35c2543c213eae64d71407a5bd081d3e5f..a49b39bcfb64ce47413c4d43ee99292aa9580b9b 100644
--- a/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.c
+++ b/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file lis2ds12_reg.c
- * @author Sensors Software Solution Team
- * @brief LIS2DS12 driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lis2ds12_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LIS2DS12 driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lis2ds12_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2ds12_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t lis2ds12_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t lis2ds12_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2ds12_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t lis2ds12_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -77,7 +83,7 @@ int32_t lis2ds12_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
*
*/
- /**
+/**
* @defgroup LIS2DS12_Sensitivity
* @brief These functions convert raw-data into engineering units.
* @{
@@ -86,22 +92,22 @@ int32_t lis2ds12_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
float_t lis2ds12_from_fs2g_to_mg(int16_t lsb)
{
- return ((float_t)lsb *0.061f);
+ return ((float_t)lsb * 0.061f);
}
float_t lis2ds12_from_fs4g_to_mg(int16_t lsb)
{
- return ((float_t)lsb *0.122f);
+ return ((float_t)lsb * 0.122f);
}
float_t lis2ds12_from_fs8g_to_mg(int16_t lsb)
{
- return ((float_t)lsb *0.244f);
+ return ((float_t)lsb * 0.244f);
}
float_t lis2ds12_from_fs16g_to_mg(int16_t lsb)
{
- return ((float_t)lsb *0.488f);
+ return ((float_t)lsb * 0.488f);
}
float_t lis2ds12_from_lsb_to_celsius(int16_t lsb)
@@ -136,31 +142,44 @@ int32_t lis2ds12_all_sources_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_SRC,
- (uint8_t*)&(val->fifo_src), 1);
- if(ret == 0){
+ (uint8_t *) & (val->fifo_src), 1);
+
+ if (ret == 0)
+ {
ret = lis2ds12_read_reg(ctx, LIS2DS12_STATUS_DUP,
- (uint8_t*)&(val->status_dup), 1);
+ (uint8_t *) & (val->status_dup), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_SRC,
- (uint8_t*)&(val->wake_up_src), 1);
+ (uint8_t *) & (val->wake_up_src), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lis2ds12_read_reg(ctx, LIS2DS12_TAP_SRC,
- (uint8_t*)&(val->tap_src), 1);
+ (uint8_t *) & (val->tap_src), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lis2ds12_read_reg(ctx, LIS2DS12_6D_SRC,
- (uint8_t*)&(val->_6d_src), 1);
+ (uint8_t *) & (val->_6d_src), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CK_GATE,
- (uint8_t*)&(val->func_ck_gate), 1);
+ (uint8_t *) & (val->func_ck_gate), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_SRC,
- (uint8_t*)&(val->func_src), 1);
+ (uint8_t *) & (val->func_src), 1);
}
+
return ret;
}
@@ -177,11 +196,14 @@ int32_t lis2ds12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
lis2ds12_ctrl1_t ctrl1;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL1, (uint8_t*)&ctrl1, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL1, (uint8_t *)&ctrl1, 1);
+
+ if (ret == 0)
+ {
ctrl1.bdu = val;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL1, (uint8_t*)&ctrl1, 1);
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL1, (uint8_t *)&ctrl1, 1);
}
+
return ret;
}
@@ -193,12 +215,13 @@ int32_t lis2ds12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2ds12_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2ds12_ctrl1_t ctrl1;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL1, (uint8_t*)&ctrl1, 1);
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL1, (uint8_t *)&ctrl1, 1);
*val = ctrl1.bdu;
return ret;
@@ -212,16 +235,20 @@ int32_t lis2ds12_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_xl_full_scale_set(stmdev_ctx_t *ctx, lis2ds12_fs_t val)
+int32_t lis2ds12_xl_full_scale_set(stmdev_ctx_t *ctx,
+ lis2ds12_fs_t val)
{
lis2ds12_ctrl1_t ctrl1;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL1, (uint8_t*)&ctrl1, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL1, (uint8_t *)&ctrl1, 1);
+
+ if (ret == 0)
+ {
ctrl1.fs = (uint8_t)val;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL1, (uint8_t*)&ctrl1, 1);
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL1, (uint8_t *)&ctrl1, 1);
}
+
return ret;
}
@@ -233,29 +260,37 @@ int32_t lis2ds12_xl_full_scale_set(stmdev_ctx_t *ctx, lis2ds12_fs_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_xl_full_scale_get(stmdev_ctx_t *ctx, lis2ds12_fs_t *val)
+int32_t lis2ds12_xl_full_scale_get(stmdev_ctx_t *ctx,
+ lis2ds12_fs_t *val)
{
lis2ds12_ctrl1_t ctrl1;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL1, (uint8_t*)&ctrl1, 1);
- switch (ctrl1.fs){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL1, (uint8_t *)&ctrl1, 1);
+
+ switch (ctrl1.fs)
+ {
case LIS2DS12_2g:
*val = LIS2DS12_2g;
break;
+
case LIS2DS12_16g:
*val = LIS2DS12_16g;
break;
+
case LIS2DS12_4g:
*val = LIS2DS12_4g;
break;
+
case LIS2DS12_8g:
*val = LIS2DS12_8g;
break;
+
default:
*val = LIS2DS12_2g;
break;
}
+
return ret;
}
@@ -267,17 +302,21 @@ int32_t lis2ds12_xl_full_scale_get(stmdev_ctx_t *ctx, lis2ds12_fs_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_xl_data_rate_set(stmdev_ctx_t *ctx, lis2ds12_odr_t val)
+int32_t lis2ds12_xl_data_rate_set(stmdev_ctx_t *ctx,
+ lis2ds12_odr_t val)
{
lis2ds12_ctrl1_t ctrl1;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL1, (uint8_t*)&ctrl1, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL1, (uint8_t *)&ctrl1, 1);
+
+ if (ret == 0)
+ {
ctrl1.odr = (uint8_t)val & 0x0FU;
ctrl1.hf_odr = ((uint8_t)val & 0x10U) >> 4;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL1, (uint8_t*)&ctrl1, 1);
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL1, (uint8_t *)&ctrl1, 1);
}
+
return ret;
}
@@ -289,74 +328,97 @@ int32_t lis2ds12_xl_data_rate_set(stmdev_ctx_t *ctx, lis2ds12_odr_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_xl_data_rate_get(stmdev_ctx_t *ctx, lis2ds12_odr_t *val)
+int32_t lis2ds12_xl_data_rate_get(stmdev_ctx_t *ctx,
+ lis2ds12_odr_t *val)
{
lis2ds12_ctrl1_t ctrl1;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL1, (uint8_t*)&ctrl1, 1);
- switch ((ctrl1.hf_odr << 4) + ctrl1.odr){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL1, (uint8_t *)&ctrl1, 1);
+
+ switch ((ctrl1.hf_odr << 4) + ctrl1.odr)
+ {
case LIS2DS12_XL_ODR_OFF:
*val = LIS2DS12_XL_ODR_OFF;
break;
+
case LIS2DS12_XL_ODR_1Hz_LP:
*val = LIS2DS12_XL_ODR_1Hz_LP;
break;
+
case LIS2DS12_XL_ODR_12Hz5_LP:
*val = LIS2DS12_XL_ODR_12Hz5_LP;
break;
+
case LIS2DS12_XL_ODR_25Hz_LP:
*val = LIS2DS12_XL_ODR_25Hz_LP;
break;
+
case LIS2DS12_XL_ODR_50Hz_LP:
*val = LIS2DS12_XL_ODR_50Hz_LP;
break;
+
case LIS2DS12_XL_ODR_100Hz_LP:
*val = LIS2DS12_XL_ODR_100Hz_LP;
break;
+
case LIS2DS12_XL_ODR_200Hz_LP:
*val = LIS2DS12_XL_ODR_200Hz_LP;
break;
+
case LIS2DS12_XL_ODR_400Hz_LP:
*val = LIS2DS12_XL_ODR_400Hz_LP;
break;
+
case LIS2DS12_XL_ODR_800Hz_LP:
*val = LIS2DS12_XL_ODR_800Hz_LP;
break;
+
case LIS2DS12_XL_ODR_12Hz5_HR:
*val = LIS2DS12_XL_ODR_12Hz5_HR;
break;
+
case LIS2DS12_XL_ODR_25Hz_HR:
*val = LIS2DS12_XL_ODR_25Hz_HR;
break;
+
case LIS2DS12_XL_ODR_50Hz_HR:
*val = LIS2DS12_XL_ODR_50Hz_HR;
break;
+
case LIS2DS12_XL_ODR_100Hz_HR:
*val = LIS2DS12_XL_ODR_100Hz_HR;
break;
+
case LIS2DS12_XL_ODR_200Hz_HR:
*val = LIS2DS12_XL_ODR_200Hz_HR;
break;
+
case LIS2DS12_XL_ODR_400Hz_HR:
*val = LIS2DS12_XL_ODR_400Hz_HR;
break;
+
case LIS2DS12_XL_ODR_800Hz_HR:
*val = LIS2DS12_XL_ODR_800Hz_HR;
break;
+
case LIS2DS12_XL_ODR_1k6Hz_HF:
*val = LIS2DS12_XL_ODR_1k6Hz_HF;
break;
+
case LIS2DS12_XL_ODR_3k2Hz_HF:
*val = LIS2DS12_XL_ODR_3k2Hz_HF;
break;
+
case LIS2DS12_XL_ODR_6k4Hz_HF:
*val = LIS2DS12_XL_ODR_6k4Hz_HF;
break;
+
default:
*val = LIS2DS12_XL_ODR_OFF;
break;
}
+
return ret;
}
@@ -368,10 +430,13 @@ int32_t lis2ds12_xl_data_rate_get(stmdev_ctx_t *ctx, lis2ds12_odr_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_status_reg_get(stmdev_ctx_t *ctx, lis2ds12_status_t *val)
+int32_t lis2ds12_status_reg_get(stmdev_ctx_t *ctx,
+ lis2ds12_status_t *val)
{
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_STATUS, (uint8_t*) val, 1);
+
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_STATUS, (uint8_t *) val, 1);
+
return ret;
}
@@ -383,12 +448,15 @@ int32_t lis2ds12_status_reg_get(stmdev_ctx_t *ctx, lis2ds12_status_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2ds12_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2ds12_status_t status;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_STATUS, (uint8_t*)&status, 1);
+
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_STATUS, (uint8_t *)&status, 1);
*val = status.drdy;
+
return ret;
}
@@ -416,7 +484,9 @@ int32_t lis2ds12_acceleration_module_raw_get(stmdev_ctx_t *ctx,
uint8_t *buff)
{
int32_t ret;
+
ret = lis2ds12_read_reg(ctx, LIS2DS12_MODULE_8BIT, buff, 1);
+
return ret;
}
@@ -432,7 +502,9 @@ int32_t lis2ds12_acceleration_module_raw_get(stmdev_ctx_t *ctx,
int32_t lis2ds12_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis2ds12_read_reg(ctx, LIS2DS12_OUT_T, buff, 1);
+
return ret;
}
@@ -452,11 +524,11 @@ int32_t lis2ds12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
ret = lis2ds12_read_reg(ctx, LIS2DS12_OUT_X_L, buff, 6);
val[0] = (int16_t)buff[1];
- val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
- val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
val[2] = (int16_t)buff[5];
- val[2] = (val[2] * 256) + (int16_t)buff[4];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
return ret;
}
@@ -476,7 +548,7 @@ int32_t lis2ds12_number_of_steps_get(stmdev_ctx_t *ctx, int16_t *val)
ret = lis2ds12_read_reg(ctx, LIS2DS12_STEP_COUNTER_L, buff, 2);
*val = (int16_t)buff[1];
- *val = (*val * 256) + (int16_t)buff[0];
+ *val = (*val * 256) + (int16_t)buff[0];
return ret;
}
@@ -488,7 +560,7 @@ int32_t lis2ds12_number_of_steps_get(stmdev_ctx_t *ctx, int16_t *val)
/**
* @defgroup Common
- * @brief This section groups common usefull functions.
+ * @brief This section groups common useful functions.
* @{
*
*/
@@ -504,7 +576,9 @@ int32_t lis2ds12_number_of_steps_get(stmdev_ctx_t *ctx, int16_t *val)
int32_t lis2ds12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis2ds12_read_reg(ctx, LIS2DS12_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -521,11 +595,15 @@ int32_t lis2ds12_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
{
lis2ds12_ctrl2_t ctrl2;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t*)&ctrl2, 1);
- if(ret == 0){
+
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
+
+ if (ret == 0)
+ {
ctrl2.if_add_inc = val;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL2, (uint8_t*)&ctrl2, 1);
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
}
+
return ret;
}
@@ -542,8 +620,10 @@ int32_t lis2ds12_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
{
lis2ds12_ctrl2_t ctrl2;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t*)&ctrl2, 1);
+
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
*val = ctrl2.if_add_inc;
+
return ret;
}
@@ -556,28 +636,38 @@ int32_t lis2ds12_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_mem_bank_set(stmdev_ctx_t *ctx, lis2ds12_func_cfg_en_t val)
+int32_t lis2ds12_mem_bank_set(stmdev_ctx_t *ctx,
+ lis2ds12_func_cfg_en_t val)
{
lis2ds12_ctrl2_t ctrl2;
lis2ds12_ctrl2_adv_t ctrl2_adv;
int32_t ret;
- if (val == LIS2DS12_ADV_BANK){
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t*)&ctrl2, 1);
- if(ret == 0){
+
+ if (val == LIS2DS12_ADV_BANK)
+ {
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
+
+ if (ret == 0)
+ {
ctrl2.func_cfg_en = (uint8_t)val;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL2, (uint8_t*)&ctrl2, 1);
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
}
}
- else {
+
+ else
+ {
ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2_ADV,
- (uint8_t*)&ctrl2_adv, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl2_adv, 1);
+
+ if (ret == 0)
+ {
ctrl2_adv.func_cfg_en = (uint8_t)val;
ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL2_ADV,
- (uint8_t*)&ctrl2_adv, 1);
+ (uint8_t *)&ctrl2_adv, 1);
}
}
+
return ret;
}
@@ -595,11 +685,14 @@ int32_t lis2ds12_reset_set(stmdev_ctx_t *ctx, uint8_t val)
lis2ds12_ctrl2_t ctrl2;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t*)&ctrl2, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
+
+ if (ret == 0)
+ {
ctrl2.soft_reset = val;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL2, (uint8_t*)&ctrl2, 1);
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
}
+
return ret;
}
@@ -616,8 +709,10 @@ int32_t lis2ds12_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
{
lis2ds12_ctrl2_t ctrl2;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t*)&ctrl2, 1);
+
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
*val = ctrl2.soft_reset;
+
return ret;
}
@@ -634,11 +729,14 @@ int32_t lis2ds12_boot_set(stmdev_ctx_t *ctx, uint8_t val)
lis2ds12_ctrl2_t ctrl2;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t*)&ctrl2, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
+
+ if (ret == 0)
+ {
ctrl2.boot = val;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL2, (uint8_t*)&ctrl2, 1);
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
}
+
return ret;
}
@@ -654,8 +752,10 @@ int32_t lis2ds12_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
{
lis2ds12_ctrl2_t ctrl2;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t*)&ctrl2, 1);
+
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
*val = ctrl2.boot;
+
return ret;
}
@@ -667,16 +767,20 @@ int32_t lis2ds12_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_xl_self_test_set(stmdev_ctx_t *ctx, lis2ds12_st_t val)
+int32_t lis2ds12_xl_self_test_set(stmdev_ctx_t *ctx,
+ lis2ds12_st_t val)
{
lis2ds12_ctrl3_t ctrl3;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t*)&ctrl3, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
+
+ if (ret == 0)
+ {
ctrl3.st = (uint8_t)val;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL3, (uint8_t*)&ctrl3, 1);
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
}
+
return ret;
}
@@ -688,22 +792,28 @@ int32_t lis2ds12_xl_self_test_set(stmdev_ctx_t *ctx, lis2ds12_st_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_xl_self_test_get(stmdev_ctx_t *ctx, lis2ds12_st_t *val)
+int32_t lis2ds12_xl_self_test_get(stmdev_ctx_t *ctx,
+ lis2ds12_st_t *val)
{
lis2ds12_ctrl3_t ctrl3;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t*)&ctrl3, 1);
- switch (ctrl3.st){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
+
+ switch (ctrl3.st)
+ {
case LIS2DS12_XL_ST_DISABLE:
*val = LIS2DS12_XL_ST_DISABLE;
break;
+
case LIS2DS12_XL_ST_POSITIVE:
*val = LIS2DS12_XL_ST_POSITIVE;
break;
+
case LIS2DS12_XL_ST_NEGATIVE:
*val = LIS2DS12_XL_ST_NEGATIVE;
break;
+
default:
*val = LIS2DS12_XL_ST_DISABLE;
break;
@@ -726,11 +836,14 @@ int32_t lis2ds12_data_ready_mode_set(stmdev_ctx_t *ctx,
lis2ds12_ctrl5_t ctrl5;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL5, (uint8_t*)&ctrl5, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL5, (uint8_t *)&ctrl5, 1);
+
+ if (ret == 0)
+ {
ctrl5.drdy_pulsed = (uint8_t)val;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL5, (uint8_t*)&ctrl5, 1);
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL5, (uint8_t *)&ctrl5, 1);
}
+
return ret;
}
@@ -748,14 +861,18 @@ int32_t lis2ds12_data_ready_mode_get(stmdev_ctx_t *ctx,
lis2ds12_ctrl5_t ctrl5;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL5, (uint8_t*)&ctrl5, 1);
- switch (ctrl5.drdy_pulsed){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL5, (uint8_t *)&ctrl5, 1);
+
+ switch (ctrl5.drdy_pulsed)
+ {
case LIS2DS12_DRDY_LATCHED:
*val = LIS2DS12_DRDY_LATCHED;
break;
+
case LIS2DS12_DRDY_PULSED:
*val = LIS2DS12_DRDY_PULSED;
break;
+
default:
*val = LIS2DS12_DRDY_LATCHED;
break;
@@ -785,16 +902,20 @@ int32_t lis2ds12_data_ready_mode_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_xl_hp_path_set(stmdev_ctx_t *ctx, lis2ds12_fds_slope_t val)
+int32_t lis2ds12_xl_hp_path_set(stmdev_ctx_t *ctx,
+ lis2ds12_fds_slope_t val)
{
lis2ds12_ctrl2_t ctrl2;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t*)&ctrl2, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
+
+ if (ret == 0)
+ {
ctrl2.fds_slope = (uint8_t)val;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL2, (uint8_t*)&ctrl2, 1);
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
}
+
return ret;
}
@@ -812,14 +933,18 @@ int32_t lis2ds12_xl_hp_path_get(stmdev_ctx_t *ctx,
lis2ds12_ctrl2_t ctrl2;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t*)&ctrl2, 1);
- switch (ctrl2.fds_slope){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
+
+ switch (ctrl2.fds_slope)
+ {
case LIS2DS12_HP_INTERNAL_ONLY:
*val = LIS2DS12_HP_INTERNAL_ONLY;
break;
+
case LIS2DS12_HP_ON_OUTPUTS:
*val = LIS2DS12_HP_ON_OUTPUTS;
break;
+
default:
*val = LIS2DS12_HP_INTERNAL_ONLY;
break;
@@ -854,11 +979,14 @@ int32_t lis2ds12_spi_mode_set(stmdev_ctx_t *ctx, lis2ds12_sim_t val)
lis2ds12_ctrl2_t ctrl2;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t*)&ctrl2, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
+
+ if (ret == 0)
+ {
ctrl2.sim = (uint8_t)val;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL2, (uint8_t*)&ctrl2, 1);
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
}
+
return ret;
}
@@ -875,14 +1003,18 @@ int32_t lis2ds12_spi_mode_get(stmdev_ctx_t *ctx, lis2ds12_sim_t *val)
lis2ds12_ctrl2_t ctrl2;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t*)&ctrl2, 1);
- switch (ctrl2.sim){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
+
+ switch (ctrl2.sim)
+ {
case LIS2DS12_SPI_4_WIRE:
*val = LIS2DS12_SPI_4_WIRE;
break;
+
case LIS2DS12_SPI_3_WIRE:
*val = LIS2DS12_SPI_3_WIRE;
break;
+
default:
*val = LIS2DS12_SPI_4_WIRE;
break;
@@ -905,11 +1037,14 @@ int32_t lis2ds12_i2c_interface_set(stmdev_ctx_t *ctx,
lis2ds12_ctrl2_t ctrl2;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t*)&ctrl2, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
+
+ if (ret == 0)
+ {
ctrl2.i2c_disable = (uint8_t)val;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL2, (uint8_t*)&ctrl2, 1);
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
}
+
return ret;
}
@@ -927,14 +1062,18 @@ int32_t lis2ds12_i2c_interface_get(stmdev_ctx_t *ctx,
lis2ds12_ctrl2_t ctrl2;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t*)&ctrl2, 1);
- switch (ctrl2.i2c_disable){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
+
+ switch (ctrl2.i2c_disable)
+ {
case LIS2DS12_I2C_ENABLE:
*val = LIS2DS12_I2C_ENABLE;
break;
+
case LIS2DS12_I2C_DISABLE:
*val = LIS2DS12_I2C_DISABLE;
break;
+
default:
*val = LIS2DS12_I2C_ENABLE;
break;
@@ -957,12 +1096,16 @@ int32_t lis2ds12_cs_mode_set(stmdev_ctx_t *ctx,
lis2ds12_fifo_ctrl_t fifo_ctrl;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_CTRL,
+ (uint8_t *)&fifo_ctrl, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl.if_cs_pu_dis = (uint8_t)val;
ret = lis2ds12_write_reg(ctx, LIS2DS12_FIFO_CTRL,
- (uint8_t*)&fifo_ctrl, 1);
+ (uint8_t *)&fifo_ctrl, 1);
}
+
return ret;
}
@@ -981,14 +1124,18 @@ int32_t lis2ds12_cs_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_CTRL,
- (uint8_t*)&fifo_ctrl, 1);
- switch (fifo_ctrl.if_cs_pu_dis){
+ (uint8_t *)&fifo_ctrl, 1);
+
+ switch (fifo_ctrl.if_cs_pu_dis)
+ {
case LIS2DS12_PULL_UP_CONNECTED:
*val = LIS2DS12_PULL_UP_CONNECTED;
break;
+
case LIS2DS12_PULL_UP_DISCONNECTED:
*val = LIS2DS12_PULL_UP_DISCONNECTED;
break;
+
default:
*val = LIS2DS12_PULL_UP_CONNECTED;
break;
@@ -1023,11 +1170,14 @@ int32_t lis2ds12_pin_mode_set(stmdev_ctx_t *ctx, lis2ds12_pp_od_t val)
lis2ds12_ctrl3_t ctrl3;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t*)&ctrl3, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
+
+ if (ret == 0)
+ {
ctrl3.pp_od = (uint8_t)val;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL3, (uint8_t*)&ctrl3, 1);
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
}
+
return ret;
}
@@ -1039,19 +1189,24 @@ int32_t lis2ds12_pin_mode_set(stmdev_ctx_t *ctx, lis2ds12_pp_od_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_pin_mode_get(stmdev_ctx_t *ctx, lis2ds12_pp_od_t *val)
+int32_t lis2ds12_pin_mode_get(stmdev_ctx_t *ctx,
+ lis2ds12_pp_od_t *val)
{
lis2ds12_ctrl3_t ctrl3;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t*)&ctrl3, 1);
- switch (ctrl3.pp_od){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
+
+ switch (ctrl3.pp_od)
+ {
case LIS2DS12_PUSH_PULL:
*val = LIS2DS12_PUSH_PULL;
break;
+
case LIS2DS12_OPEN_DRAIN:
*val = LIS2DS12_OPEN_DRAIN;
break;
+
default:
*val = LIS2DS12_PUSH_PULL;
break;
@@ -1074,11 +1229,14 @@ int32_t lis2ds12_pin_polarity_set(stmdev_ctx_t *ctx,
lis2ds12_ctrl3_t ctrl3;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t*)&ctrl3, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
+
+ if (ret == 0)
+ {
ctrl3.h_lactive = (uint8_t)val;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL3, (uint8_t*)&ctrl3, 1);
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
}
+
return ret;
}
@@ -1096,14 +1254,18 @@ int32_t lis2ds12_pin_polarity_get(stmdev_ctx_t *ctx,
lis2ds12_ctrl3_t ctrl3;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t*)&ctrl3, 1);
- switch (ctrl3.h_lactive){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
+
+ switch (ctrl3.h_lactive)
+ {
case LIS2DS12_ACTIVE_HIGH:
*val = LIS2DS12_ACTIVE_HIGH;
break;
+
case LIS2DS12_ACTIVE_LOW:
*val = LIS2DS12_ACTIVE_LOW;
break;
+
default:
*val = LIS2DS12_ACTIVE_HIGH;
break;
@@ -1126,11 +1288,14 @@ int32_t lis2ds12_int_notification_set(stmdev_ctx_t *ctx,
lis2ds12_ctrl3_t ctrl3;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t*)&ctrl3, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
+
+ if (ret == 0)
+ {
ctrl3.lir = (uint8_t)val;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL3, (uint8_t*)&ctrl3, 1);
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
}
+
return ret;
}
@@ -1148,14 +1313,18 @@ int32_t lis2ds12_int_notification_get(stmdev_ctx_t *ctx,
lis2ds12_ctrl3_t ctrl3;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t*)&ctrl3, 1);
- switch (ctrl3.lir){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
+
+ switch (ctrl3.lir)
+ {
case LIS2DS12_INT_PULSED:
*val = LIS2DS12_INT_PULSED;
break;
+
case LIS2DS12_INT_LATCHED:
*val = LIS2DS12_INT_LATCHED;
break;
+
default:
*val = LIS2DS12_INT_PULSED;
break;
@@ -1179,8 +1348,10 @@ int32_t lis2ds12_pin_int1_route_set(stmdev_ctx_t *ctx,
lis2ds12_ctrl4_t ctrl4;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL4, (uint8_t*)&ctrl4, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL4, (uint8_t *)&ctrl4, 1);
+
+ if (ret == 0)
+ {
ctrl4.int1_drdy = (uint8_t)val.int1_drdy;
ctrl4.int1_fth = (uint8_t)val.int1_fth;
ctrl4.int1_6d = (uint8_t)val.int1_6d;
@@ -1189,17 +1360,22 @@ int32_t lis2ds12_pin_int1_route_set(stmdev_ctx_t *ctx,
ctrl4.int1_wu = (uint8_t)val.int1_wu;
ctrl4.int1_s_tap = (uint8_t)val.int1_s_tap;
ctrl4.int1_master_drdy = (uint8_t)val.int1_master_drdy;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL4, (uint8_t*)&ctrl4, 1);
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL4, (uint8_t *)&ctrl4, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
wake_up_dur.int1_fss7 = (uint8_t)val.int1_fss7;
ret = lis2ds12_write_reg(ctx, LIS2DS12_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -1218,8 +1394,10 @@ int32_t lis2ds12_pin_int1_route_get(stmdev_ctx_t *ctx,
lis2ds12_ctrl4_t ctrl4;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL4, (uint8_t*)&ctrl4, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL4, (uint8_t *)&ctrl4, 1);
+
+ if (ret == 0)
+ {
val->int1_drdy = ctrl4.int1_drdy;
val->int1_fth = ctrl4.int1_fth;
val->int1_6d = ctrl4.int1_6d;
@@ -1229,9 +1407,10 @@ int32_t lis2ds12_pin_int1_route_get(stmdev_ctx_t *ctx,
val->int1_s_tap = ctrl4.int1_s_tap;
val->int1_master_drdy = ctrl4.int1_master_drdy;
ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
val->int1_fss7 = wake_up_dur.int1_fss7;
}
+
return ret;
}
@@ -1249,16 +1428,19 @@ int32_t lis2ds12_pin_int2_route_set(stmdev_ctx_t *ctx,
lis2ds12_ctrl5_t ctrl5;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL5, (uint8_t*)&ctrl5, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL5, (uint8_t *)&ctrl5, 1);
+
+ if (ret == 0)
+ {
ctrl5.int2_boot = val.int2_boot;
ctrl5.int2_tilt = val.int2_tilt;
ctrl5.int2_sig_mot = val.int2_sig_mot;
ctrl5.int2_step_det = val.int2_step_det;
ctrl5.int2_fth = val.int2_fth;
ctrl5.int2_drdy = val.int2_drdy;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL5, (uint8_t*)&ctrl5, 1);
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL5, (uint8_t *)&ctrl5, 1);
}
+
return ret;
}
@@ -1276,7 +1458,7 @@ int32_t lis2ds12_pin_int2_route_get(stmdev_ctx_t *ctx,
lis2ds12_ctrl5_t ctrl5;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL5, (uint8_t*)&ctrl5, 1);
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL5, (uint8_t *)&ctrl5, 1);
val->int2_boot = ctrl5.int2_boot;
val->int2_tilt = ctrl5.int2_tilt;
val->int2_sig_mot = ctrl5.int2_sig_mot;
@@ -1300,11 +1482,14 @@ int32_t lis2ds12_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
lis2ds12_ctrl5_t ctrl5;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL5, (uint8_t*)&ctrl5, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL5, (uint8_t *)&ctrl5, 1);
+
+ if (ret == 0)
+ {
ctrl5.int2_on_int1 = val;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL5, (uint8_t*)&ctrl5, 1);
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL5, (uint8_t *)&ctrl5, 1);
}
+
return ret;
}
@@ -1321,7 +1506,7 @@ int32_t lis2ds12_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2ds12_ctrl5_t ctrl5;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL5, (uint8_t*)&ctrl5, 1);
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL5, (uint8_t *)&ctrl5, 1);
*val = ctrl5.int2_on_int1;
return ret;
@@ -1334,12 +1519,12 @@ int32_t lis2ds12_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @defgroup Interrupt Pins
- * @brief This section groups all the functions that manage interrup pins.
+ * @brief This section groups all the functions that manage interrupt pins.
* @{
*
*/
- /**
+/**
* @brief Connect / Disconnect pull-up on auxiliary I2C line.[set]
*
* @param ctx read / write interface definitions.(ptr)
@@ -1347,16 +1532,22 @@ int32_t lis2ds12_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_sh_pin_mode_set(stmdev_ctx_t *ctx, lis2ds12_tud_en_t val)
+int32_t lis2ds12_sh_pin_mode_set(stmdev_ctx_t *ctx,
+ lis2ds12_tud_en_t val)
{
lis2ds12_func_ctrl_t func_ctrl;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL, (uint8_t*)&func_ctrl, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL,
+ (uint8_t *)&func_ctrl, 1);
+
+ if (ret == 0)
+ {
func_ctrl.tud_en = (uint8_t)val;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_FUNC_CTRL, (uint8_t*)&func_ctrl, 1);
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_FUNC_CTRL,
+ (uint8_t *)&func_ctrl, 1);
}
+
return ret;
}
@@ -1368,19 +1559,25 @@ int32_t lis2ds12_sh_pin_mode_set(stmdev_ctx_t *ctx, lis2ds12_tud_en_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_sh_pin_mode_get(stmdev_ctx_t *ctx, lis2ds12_tud_en_t *val)
+int32_t lis2ds12_sh_pin_mode_get(stmdev_ctx_t *ctx,
+ lis2ds12_tud_en_t *val)
{
lis2ds12_func_ctrl_t func_ctrl;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL, (uint8_t*)&func_ctrl, 1);
- switch (func_ctrl.tud_en){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL,
+ (uint8_t *)&func_ctrl, 1);
+
+ switch (func_ctrl.tud_en)
+ {
case LIS2DS12_EXT_PULL_UP:
*val = LIS2DS12_EXT_PULL_UP;
break;
+
case LIS2DS12_INTERNAL_PULL_UP:
*val = LIS2DS12_INTERNAL_PULL_UP;
break;
+
default:
*val = LIS2DS12_EXT_PULL_UP;
break;
@@ -1402,7 +1599,7 @@ int32_t lis2ds12_sh_pin_mode_get(stmdev_ctx_t *ctx, lis2ds12_tud_en_t *val)
*
*/
- /**
+/**
* @brief Threshold for wakeup [1 LSb = FS_XL / 64].[set]
*
* @param ctx read / write interface definitions.(ptr)
@@ -1416,12 +1613,15 @@ int32_t lis2ds12_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
- if(ret == 0){
+ (uint8_t *)&wake_up_ths, 1);
+
+ if (ret == 0)
+ {
wake_up_ths.wu_ths = val;
ret = lis2ds12_write_reg(ctx, LIS2DS12_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
}
+
return ret;
}
@@ -1439,7 +1639,7 @@ int32_t lis2ds12_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
*val = wake_up_ths.wu_ths;
return ret;
@@ -1459,12 +1659,15 @@ int32_t lis2ds12_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
wake_up_dur.wu_dur = val;
ret = lis2ds12_write_reg(ctx, LIS2DS12_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -1480,9 +1683,11 @@ int32_t lis2ds12_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
{
lis2ds12_wake_up_dur_t wake_up_dur;
int32_t ret;
+
ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
*val = wake_up_dur.wu_dur;
+
return ret;
}
@@ -1513,12 +1718,15 @@ int32_t lis2ds12_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
- if(ret == 0){
+ (uint8_t *)&wake_up_ths, 1);
+
+ if (ret == 0)
+ {
wake_up_ths.sleep_on = val;
ret = lis2ds12_write_reg(ctx, LIS2DS12_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
}
+
return ret;
}
@@ -1534,9 +1742,11 @@ int32_t lis2ds12_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
{
lis2ds12_wake_up_ths_t wake_up_ths;
int32_t ret;
+
ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
*val = wake_up_ths.sleep_on;
+
return ret;
}
@@ -1554,12 +1764,15 @@ int32_t lis2ds12_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
wake_up_dur.sleep_dur = val;
ret = lis2ds12_write_reg(ctx, LIS2DS12_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -1575,9 +1788,11 @@ int32_t lis2ds12_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
{
lis2ds12_wake_up_dur_t wake_up_dur;
int32_t ret;
+
ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
*val = wake_up_dur.sleep_dur;
+
return ret;
}
@@ -1602,16 +1817,20 @@ int32_t lis2ds12_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lis2ds12_tap_detection_on_z_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lis2ds12_ctrl3_t ctrl3;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t*)&ctrl3, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
+
+ if (ret == 0)
+ {
ctrl3.tap_z_en = val;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL3, (uint8_t*)&ctrl3, 1);
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
}
+
return ret;
}
@@ -1623,12 +1842,15 @@ int32_t lis2ds12_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2ds12_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2ds12_ctrl3_t ctrl3;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t*)&ctrl3, 1);
+
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
*val = ctrl3.tap_z_en;
+
return ret;
}
@@ -1640,16 +1862,20 @@ int32_t lis2ds12_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lis2ds12_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lis2ds12_ctrl3_t ctrl3;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t*)&ctrl3, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
+
+ if (ret == 0)
+ {
ctrl3.tap_y_en = val;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL3, (uint8_t*)&ctrl3, 1);
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
}
+
return ret;
}
@@ -1661,12 +1887,15 @@ int32_t lis2ds12_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2ds12_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2ds12_ctrl3_t ctrl3;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t*)&ctrl3, 1);
+
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
*val = ctrl3.tap_y_en;
+
return ret;
}
@@ -1678,16 +1907,20 @@ int32_t lis2ds12_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lis2ds12_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lis2ds12_ctrl3_t ctrl3;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t*)&ctrl3, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
+
+ if (ret == 0)
+ {
ctrl3.tap_x_en = val;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL3, (uint8_t*)&ctrl3, 1);
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
}
+
return ret;
}
@@ -1699,12 +1932,15 @@ int32_t lis2ds12_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2ds12_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2ds12_ctrl3_t ctrl3;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t*)&ctrl3, 1);
+
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
*val = ctrl3.tap_x_en;
+
return ret;
}
@@ -1722,12 +1958,15 @@ int32_t lis2ds12_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lis2ds12_read_reg(ctx, LIS2DS12_TAP_6D_THS,
- (uint8_t*)&tap_6d_ths, 1);
- if(ret == 0){
+ (uint8_t *)&tap_6d_ths, 1);
+
+ if (ret == 0)
+ {
tap_6d_ths.tap_ths = val;
ret = lis2ds12_write_reg(ctx, LIS2DS12_TAP_6D_THS,
- (uint8_t*)&tap_6d_ths, 1);
+ (uint8_t *)&tap_6d_ths, 1);
}
+
return ret;
}
@@ -1743,9 +1982,11 @@ int32_t lis2ds12_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
{
lis2ds12_tap_6d_ths_t tap_6d_ths;
int32_t ret;
+
ret = lis2ds12_read_reg(ctx, LIS2DS12_TAP_6D_THS,
- (uint8_t*)&tap_6d_ths, 1);
+ (uint8_t *)&tap_6d_ths, 1);
*val = tap_6d_ths.tap_ths;
+
return ret;
}
@@ -1766,11 +2007,14 @@ int32_t lis2ds12_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
lis2ds12_int_dur_t int_dur;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_INT_DUR, (uint8_t*)&int_dur, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_INT_DUR, (uint8_t *)&int_dur, 1);
+
+ if (ret == 0)
+ {
int_dur.shock = val;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_INT_DUR, (uint8_t*)&int_dur, 1);
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_INT_DUR, (uint8_t *)&int_dur, 1);
}
+
return ret;
}
@@ -1791,7 +2035,7 @@ int32_t lis2ds12_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2ds12_int_dur_t int_dur;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_INT_DUR, (uint8_t*)&int_dur, 1);
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_INT_DUR, (uint8_t *)&int_dur, 1);
*val = int_dur.shock;
return ret;
@@ -1814,11 +2058,14 @@ int32_t lis2ds12_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
lis2ds12_int_dur_t int_dur;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_INT_DUR, (uint8_t*)&int_dur, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_INT_DUR, (uint8_t *)&int_dur, 1);
+
+ if (ret == 0)
+ {
int_dur.quiet = val;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_INT_DUR, (uint8_t*)&int_dur, 1);
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_INT_DUR, (uint8_t *)&int_dur, 1);
}
+
return ret;
}
@@ -1838,8 +2085,10 @@ int32_t lis2ds12_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
{
lis2ds12_int_dur_t int_dur;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_INT_DUR, (uint8_t*)&int_dur, 1);
+
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_INT_DUR, (uint8_t *)&int_dur, 1);
*val = int_dur.quiet;
+
return ret;
}
@@ -1860,11 +2109,14 @@ int32_t lis2ds12_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lis2ds12_int_dur_t int_dur;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_INT_DUR, (uint8_t*)&int_dur, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_INT_DUR, (uint8_t *)&int_dur, 1);
+
+ if (ret == 0)
+ {
int_dur.lat = val;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_INT_DUR, (uint8_t*)&int_dur, 1);
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_INT_DUR, (uint8_t *)&int_dur, 1);
}
+
return ret;
}
@@ -1884,8 +2136,10 @@ int32_t lis2ds12_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
{
lis2ds12_int_dur_t int_dur;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_INT_DUR, (uint8_t*)&int_dur, 1);
+
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_INT_DUR, (uint8_t *)&int_dur, 1);
*val = int_dur.lat;
+
return ret;
}
@@ -1904,12 +2158,15 @@ int32_t lis2ds12_tap_mode_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
- if(ret == 0){
+ (uint8_t *)&wake_up_ths, 1);
+
+ if (ret == 0)
+ {
wake_up_ths.single_double_tap = (uint8_t)val;
ret = lis2ds12_write_reg(ctx, LIS2DS12_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
}
+
return ret;
}
@@ -1928,14 +2185,18 @@ int32_t lis2ds12_tap_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
- switch (wake_up_ths.single_double_tap){
+ (uint8_t *)&wake_up_ths, 1);
+
+ switch (wake_up_ths.single_double_tap)
+ {
case LIS2DS12_ONLY_SINGLE:
*val = LIS2DS12_ONLY_SINGLE;
break;
+
case LIS2DS12_ONLY_DOUBLE:
*val = LIS2DS12_ONLY_DOUBLE;
break;
+
default:
*val = LIS2DS12_ONLY_SINGLE;
break;
@@ -1952,10 +2213,13 @@ int32_t lis2ds12_tap_mode_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_tap_src_get(stmdev_ctx_t *ctx, lis2ds12_tap_src_t *val)
+int32_t lis2ds12_tap_src_get(stmdev_ctx_t *ctx,
+ lis2ds12_tap_src_t *val)
{
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_TAP_SRC, (uint8_t*) val, 1);
+
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_TAP_SRC, (uint8_t *) val, 1);
+
return ret;
}
@@ -1980,17 +2244,22 @@ int32_t lis2ds12_tap_src_get(stmdev_ctx_t *ctx, lis2ds12_tap_src_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_6d_threshold_set(stmdev_ctx_t *ctx, lis2ds12_6d_ths_t val)
+int32_t lis2ds12_6d_threshold_set(stmdev_ctx_t *ctx,
+ lis2ds12_6d_ths_t val)
{
lis2ds12_tap_6d_ths_t tap_6d_ths;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_TAP_6D_THS, (uint8_t*)&tap_6d_ths, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_TAP_6D_THS,
+ (uint8_t *)&tap_6d_ths, 1);
+
+ if (ret == 0)
+ {
tap_6d_ths._6d_ths = (uint8_t)val;
ret = lis2ds12_write_reg(ctx, LIS2DS12_TAP_6D_THS,
- (uint8_t*)&tap_6d_ths, 1);
+ (uint8_t *)&tap_6d_ths, 1);
}
+
return ret;
}
@@ -2002,25 +2271,33 @@ int32_t lis2ds12_6d_threshold_set(stmdev_ctx_t *ctx, lis2ds12_6d_ths_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_6d_threshold_get(stmdev_ctx_t *ctx, lis2ds12_6d_ths_t *val)
+int32_t lis2ds12_6d_threshold_get(stmdev_ctx_t *ctx,
+ lis2ds12_6d_ths_t *val)
{
lis2ds12_tap_6d_ths_t tap_6d_ths;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_TAP_6D_THS, (uint8_t*)&tap_6d_ths, 1);
- switch (tap_6d_ths._6d_ths){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_TAP_6D_THS,
+ (uint8_t *)&tap_6d_ths, 1);
+
+ switch (tap_6d_ths._6d_ths)
+ {
case LIS2DS12_DEG_80:
*val = LIS2DS12_DEG_80;
break;
+
case LIS2DS12_DEG_70:
*val = LIS2DS12_DEG_70;
break;
+
case LIS2DS12_DEG_60:
*val = LIS2DS12_DEG_60;
break;
+
case LIS2DS12_DEG_50:
*val = LIS2DS12_DEG_50;
break;
+
default:
*val = LIS2DS12_DEG_80;
break;
@@ -2043,12 +2320,15 @@ int32_t lis2ds12_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lis2ds12_read_reg(ctx, LIS2DS12_TAP_6D_THS,
- (uint8_t*)& tap_6d_ths, 1);
- if(ret == 0){
+ (uint8_t *)& tap_6d_ths, 1);
+
+ if (ret == 0)
+ {
tap_6d_ths._4d_en = val;
ret = lis2ds12_write_reg(ctx, LIS2DS12_TAP_6D_THS,
- (uint8_t*)& tap_6d_ths, 1);
+ (uint8_t *)& tap_6d_ths, 1);
}
+
return ret;
}
@@ -2064,9 +2344,11 @@ int32_t lis2ds12_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
{
lis2ds12_tap_6d_ths_t tap_6d_ths;
int32_t ret;
+
ret = lis2ds12_read_reg(ctx, LIS2DS12_TAP_6D_THS,
- (uint8_t*)&tap_6d_ths, 1);
+ (uint8_t *)&tap_6d_ths, 1);
*val = tap_6d_ths._4d_en;
+
return ret;
}
@@ -2081,7 +2363,9 @@ int32_t lis2ds12_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t lis2ds12_6d_src_get(stmdev_ctx_t *ctx, lis2ds12_6d_src_t *val)
{
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_6D_SRC, (uint8_t*) val, 1);
+
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_6D_SRC, (uint8_t *) val, 1);
+
return ret;
}
@@ -2112,21 +2396,29 @@ int32_t lis2ds12_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lis2ds12_wake_up_dur_t wake_up_dur;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_FREE_FALL, (uint8_t*)&free_fall, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_FREE_FALL,
+ (uint8_t *)&free_fall, 1);
+
+ if (ret == 0)
+ {
free_fall.ff_dur = val & 0x1FU;
ret = lis2ds12_write_reg(ctx, LIS2DS12_FREE_FALL,
- (uint8_t*)&free_fall, 1);
+ (uint8_t *)&free_fall, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
wake_up_dur.ff_dur = (val & 0x20U) >> 5;
ret = lis2ds12_write_reg(ctx, LIS2DS12_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -2144,12 +2436,16 @@ int32_t lis2ds12_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2ds12_wake_up_dur_t wake_up_dur;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_FREE_FALL, (uint8_t*)&free_fall, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_FREE_FALL,
+ (uint8_t *)&free_fall, 1);
+
+ if (ret == 0)
+ {
ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
*val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
}
+
return ret;
}
@@ -2166,11 +2462,16 @@ int32_t lis2ds12_ff_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
lis2ds12_free_fall_t free_fall;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_FREE_FALL, (uint8_t*)&free_fall, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_FREE_FALL,
+ (uint8_t *)&free_fall, 1);
+
+ if (ret == 0)
+ {
free_fall.ff_ths = val;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_FREE_FALL, (uint8_t*)&free_fall, 1);
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_FREE_FALL,
+ (uint8_t *)&free_fall, 1);
}
+
return ret;
}
@@ -2186,8 +2487,11 @@ int32_t lis2ds12_ff_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
{
lis2ds12_free_fall_t free_fall;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_FREE_FALL, (uint8_t*)&free_fall, 1);
+
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_FREE_FALL,
+ (uint8_t *)&free_fall, 1);
*val = free_fall.ff_ths;
+
return ret;
}
@@ -2212,17 +2516,22 @@ int32_t lis2ds12_ff_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_fifo_xl_module_batch_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lis2ds12_fifo_xl_module_batch_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lis2ds12_fifo_ctrl_t fifo_ctrl;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_CTRL,
+ (uint8_t *)&fifo_ctrl, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl.module_to_fifo = val;
ret = lis2ds12_write_reg(ctx, LIS2DS12_FIFO_CTRL,
- (uint8_t*)&fifo_ctrl, 1);
+ (uint8_t *)&fifo_ctrl, 1);
}
+
return ret;
}
@@ -2235,12 +2544,16 @@ int32_t lis2ds12_fifo_xl_module_batch_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_fifo_xl_module_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2ds12_fifo_xl_module_batch_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2ds12_fifo_ctrl_t fifo_ctrl;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
+
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_CTRL,
+ (uint8_t *)&fifo_ctrl, 1);
*val = fifo_ctrl.module_to_fifo;
+
return ret;
}
@@ -2252,17 +2565,22 @@ int32_t lis2ds12_fifo_xl_module_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_fifo_mode_set(stmdev_ctx_t *ctx, lis2ds12_fmode_t val)
+int32_t lis2ds12_fifo_mode_set(stmdev_ctx_t *ctx,
+ lis2ds12_fmode_t val)
{
lis2ds12_fifo_ctrl_t fifo_ctrl;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_CTRL,
+ (uint8_t *)&fifo_ctrl, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl.fmode = (uint8_t)val;
ret = lis2ds12_write_reg(ctx, LIS2DS12_FIFO_CTRL,
- (uint8_t*)&fifo_ctrl, 1);
+ (uint8_t *)&fifo_ctrl, 1);
}
+
return ret;
}
@@ -2274,22 +2592,29 @@ int32_t lis2ds12_fifo_mode_set(stmdev_ctx_t *ctx, lis2ds12_fmode_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_fifo_mode_get(stmdev_ctx_t *ctx, lis2ds12_fmode_t *val)
+int32_t lis2ds12_fifo_mode_get(stmdev_ctx_t *ctx,
+ lis2ds12_fmode_t *val)
{
lis2ds12_fifo_ctrl_t fifo_ctrl;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
- switch (fifo_ctrl.fmode){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_CTRL,
+ (uint8_t *)&fifo_ctrl, 1);
+
+ switch (fifo_ctrl.fmode)
+ {
case LIS2DS12_BYPASS_MODE:
*val = LIS2DS12_BYPASS_MODE;
break;
+
case LIS2DS12_FIFO_MODE:
*val = LIS2DS12_FIFO_MODE;
break;
+
case LIS2DS12_STREAM_TO_FIFO_MODE:
*val = LIS2DS12_STREAM_TO_FIFO_MODE;
break;
+
case LIS2DS12_BYPASS_TO_STREAM_MODE:
*val = LIS2DS12_BYPASS_TO_STREAM_MODE;
break;
@@ -2297,6 +2622,7 @@ int32_t lis2ds12_fifo_mode_get(stmdev_ctx_t *ctx, lis2ds12_fmode_t *val)
case LIS2DS12_STREAM_MODE:
*val = LIS2DS12_STREAM_MODE;
break;
+
default:
*val = LIS2DS12_BYPASS_MODE;
break;
@@ -2316,7 +2642,9 @@ int32_t lis2ds12_fifo_mode_get(stmdev_ctx_t *ctx, lis2ds12_fmode_t *val)
int32_t lis2ds12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
{
int32_t ret;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_FIFO_THS, (uint8_t*)&val, 1);
+
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_FIFO_THS, (uint8_t *)&val, 1);
+
return ret;
}
@@ -2331,7 +2659,9 @@ int32_t lis2ds12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t lis2ds12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
{
int32_t ret;
+
ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_THS, val, 1);
+
return ret;
}
@@ -2347,8 +2677,10 @@ int32_t lis2ds12_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
{
lis2ds12_fifo_src_t fifo_src;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_SRC, (uint8_t*)&fifo_src, 1);
+
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_SRC, (uint8_t *)&fifo_src, 1);
*val = fifo_src.diff;
+
return ret;
}
@@ -2364,8 +2696,10 @@ int32_t lis2ds12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
{
lis2ds12_fifo_src_t fifo_src;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_SRC, (uint8_t*)&fifo_src, 1);
+
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_SRC, (uint8_t *)&fifo_src, 1);
*val = fifo_src.fifo_ovr;
+
return ret;
}
@@ -2381,8 +2715,10 @@ int32_t lis2ds12_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
{
lis2ds12_fifo_src_t fifo_src;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_SRC, (uint8_t*)&fifo_src, 1);
+
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_SRC, (uint8_t *)&fifo_src, 1);
*val = fifo_src.fth;
+
return ret;
}
@@ -2400,12 +2736,15 @@ int32_t lis2ds12_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
lis2ds12_fifo_src_t fifo_src;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_THS, (uint8_t*)&fifo_ths, 1);
- if(ret == 0){
- ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_SRC, (uint8_t*)&fifo_src, 1);
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_THS, (uint8_t *)&fifo_ths, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_SRC, (uint8_t *)&fifo_src, 1);
*val = fifo_src.diff;
*val = (*val * 256U) + fifo_ths.fth;
}
+
return ret;
}
@@ -2417,10 +2756,13 @@ int32_t lis2ds12_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_fifo_src_get(stmdev_ctx_t *ctx, lis2ds12_fifo_src_t *val)
+int32_t lis2ds12_fifo_src_get(stmdev_ctx_t *ctx,
+ lis2ds12_fifo_src_t *val)
{
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_SRC, (uint8_t*) val, 1);
+
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_SRC, (uint8_t *) val, 1);
+
return ret;
}
@@ -2450,12 +2792,15 @@ int32_t lis2ds12_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lis2ds12_read_reg(ctx, LIS2DS12_STEP_COUNTER_MINTHS,
- (uint8_t*)&step_counter_minths, 1);
- if(ret == 0){
+ (uint8_t *)&step_counter_minths, 1);
+
+ if (ret == 0)
+ {
step_counter_minths.sc_mths = val;
ret = lis2ds12_write_reg(ctx, LIS2DS12_STEP_COUNTER_MINTHS,
- (uint8_t*)&step_counter_minths, 1);
+ (uint8_t *)&step_counter_minths, 1);
}
+
return ret;
}
@@ -2471,9 +2816,11 @@ int32_t lis2ds12_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
{
lis2ds12_step_counter_minths_t step_counter_minths;
int32_t ret;
+
ret = lis2ds12_read_reg(ctx, LIS2DS12_STEP_COUNTER_MINTHS,
- (uint8_t*)&step_counter_minths, 1);
+ (uint8_t *)&step_counter_minths, 1);
*val = step_counter_minths.sc_mths;
+
return ret;
}
@@ -2492,12 +2839,15 @@ int32_t lis2ds12_pedo_full_scale_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lis2ds12_read_reg(ctx, LIS2DS12_STEP_COUNTER_MINTHS,
- (uint8_t*)&step_counter_minths, 1);
- if(ret == 0){
+ (uint8_t *)&step_counter_minths, 1);
+
+ if (ret == 0)
+ {
step_counter_minths.pedo4g = (uint8_t)val;
ret = lis2ds12_write_reg(ctx, LIS2DS12_STEP_COUNTER_MINTHS,
- (uint8_t*)&step_counter_minths, 1);
+ (uint8_t *)&step_counter_minths, 1);
}
+
return ret;
}
@@ -2516,14 +2866,18 @@ int32_t lis2ds12_pedo_full_scale_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lis2ds12_read_reg(ctx, LIS2DS12_STEP_COUNTER_MINTHS,
- (uint8_t*)&step_counter_minths, 1);
- switch (step_counter_minths.pedo4g){
+ (uint8_t *)&step_counter_minths, 1);
+
+ switch (step_counter_minths.pedo4g)
+ {
case LIS2DS12_PEDO_AT_2g:
*val = LIS2DS12_PEDO_AT_2g;
break;
+
case LIS2DS12_PEDO_AT_4g:
*val = LIS2DS12_PEDO_AT_4g;
break;
+
default:
*val = LIS2DS12_PEDO_AT_2g;
break;
@@ -2546,12 +2900,15 @@ int32_t lis2ds12_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lis2ds12_read_reg(ctx, LIS2DS12_STEP_COUNTER_MINTHS,
- (uint8_t*)&step_counter_minths, 1);
- if(ret == 0){
+ (uint8_t *)&step_counter_minths, 1);
+
+ if (ret == 0)
+ {
step_counter_minths.rst_nstep = val;
ret = lis2ds12_write_reg(ctx, LIS2DS12_STEP_COUNTER_MINTHS,
- (uint8_t*)&step_counter_minths, 1);
+ (uint8_t *)&step_counter_minths, 1);
}
+
return ret;
}
@@ -2567,9 +2924,11 @@ int32_t lis2ds12_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
{
lis2ds12_step_counter_minths_t step_counter_minths;
int32_t ret;
+
ret = lis2ds12_read_reg(ctx, LIS2DS12_STEP_COUNTER_MINTHS,
- (uint8_t*)&step_counter_minths, 1);
+ (uint8_t *)&step_counter_minths, 1);
*val = step_counter_minths.rst_nstep;
+
return ret;
}
@@ -2581,13 +2940,16 @@ int32_t lis2ds12_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_pedo_step_detect_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2ds12_pedo_step_detect_flag_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2ds12_func_ck_gate_t func_ck_gate;
int32_t ret;
+
ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CK_GATE,
- (uint8_t*)&func_ck_gate, 1);
+ (uint8_t *)&func_ck_gate, 1);
*val = func_ck_gate.step_detect;
+
return ret;
}
@@ -2604,12 +2966,16 @@ int32_t lis2ds12_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val)
lis2ds12_func_ctrl_t func_ctrl;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL, (uint8_t*)&func_ctrl, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL,
+ (uint8_t *)&func_ctrl, 1);
+
+ if (ret == 0)
+ {
func_ctrl.step_cnt_on = val;
ret = lis2ds12_write_reg(ctx, LIS2DS12_FUNC_CTRL,
- (uint8_t*)&func_ctrl, 1);
+ (uint8_t *)&func_ctrl, 1);
}
+
return ret;
}
@@ -2625,8 +2991,11 @@ int32_t lis2ds12_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
{
lis2ds12_func_ctrl_t func_ctrl;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL, (uint8_t*)&func_ctrl, 1);
+
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL,
+ (uint8_t *)&func_ctrl, 1);
*val = func_ctrl.step_cnt_on;
+
return ret;
}
@@ -2638,24 +3007,32 @@ int32_t lis2ds12_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lis2ds12_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lis2ds12_pedo_deb_reg_t pedo_deb_reg;
int32_t ret;
ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_ADV_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lis2ds12_read_reg(ctx, LIS2DS12_PEDO_DEB_REG,
- (uint8_t*)&pedo_deb_reg, 1);
+ (uint8_t *)&pedo_deb_reg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
pedo_deb_reg.deb_step = val;
ret = lis2ds12_write_reg(ctx, LIS2DS12_PEDO_DEB_REG,
- (uint8_t*)&pedo_deb_reg, 1);
+ (uint8_t *)&pedo_deb_reg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK);
}
+
return ret;
}
@@ -2667,20 +3044,26 @@ int32_t lis2ds12_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2ds12_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2ds12_pedo_deb_reg_t pedo_deb_reg;
int32_t ret;
ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_ADV_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lis2ds12_read_reg(ctx, LIS2DS12_PEDO_DEB_REG,
- (uint8_t*)&pedo_deb_reg, 1);
+ (uint8_t *)&pedo_deb_reg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = pedo_deb_reg.deb_step;
ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK);
}
+
return ret;
}
@@ -2700,18 +3083,25 @@ int32_t lis2ds12_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_ADV_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lis2ds12_read_reg(ctx, LIS2DS12_PEDO_DEB_REG,
- (uint8_t*)&pedo_deb_reg, 1);
+ (uint8_t *)&pedo_deb_reg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
pedo_deb_reg.deb_time = val;
ret = lis2ds12_write_reg(ctx, LIS2DS12_PEDO_DEB_REG,
- (uint8_t*)&pedo_deb_reg, 1);
+ (uint8_t *)&pedo_deb_reg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK);
}
+
return ret;
}
@@ -2731,14 +3121,19 @@ int32_t lis2ds12_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_ADV_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lis2ds12_read_reg(ctx, LIS2DS12_PEDO_DEB_REG,
- (uint8_t*)&pedo_deb_reg, 1);
+ (uint8_t *)&pedo_deb_reg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = pedo_deb_reg.deb_time;
ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK);
}
+
return ret;
}
@@ -2751,17 +3146,23 @@ int32_t lis2ds12_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_pedo_steps_period_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lis2ds12_pedo_steps_period_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_ADV_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lis2ds12_write_reg(ctx, LIS2DS12_STEP_COUNT_DELTA, buff, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK);
}
+
return ret;
}
@@ -2774,17 +3175,23 @@ int32_t lis2ds12_pedo_steps_period_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_pedo_steps_period_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lis2ds12_pedo_steps_period_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_ADV_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lis2ds12_read_reg(ctx, LIS2DS12_STEP_COUNT_DELTA, buff, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK);
}
+
return ret;
}
@@ -2809,13 +3216,16 @@ int32_t lis2ds12_pedo_steps_period_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_motion_data_ready_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2ds12_motion_data_ready_flag_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2ds12_func_ck_gate_t func_ck_gate;
int32_t ret;
+
ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CK_GATE,
- (uint8_t*)&func_ck_gate, 1);
+ (uint8_t *)&func_ck_gate, 1);
*val = func_ck_gate.sig_mot_detect;
+
return ret;
}
@@ -2832,12 +3242,16 @@ int32_t lis2ds12_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val)
lis2ds12_func_ctrl_t func_ctrl;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL, (uint8_t*)&func_ctrl, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL,
+ (uint8_t *)&func_ctrl, 1);
+
+ if (ret == 0)
+ {
func_ctrl.sign_mot_on = val;
ret = lis2ds12_write_reg(ctx, LIS2DS12_FUNC_CTRL,
- (uint8_t*)&func_ctrl, 1);
+ (uint8_t *)&func_ctrl, 1);
}
+
return ret;
}
@@ -2853,8 +3267,11 @@ int32_t lis2ds12_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
{
lis2ds12_func_ctrl_t func_ctrl;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL, (uint8_t*)&func_ctrl, 1);
+
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL,
+ (uint8_t *)&func_ctrl, 1);
*val = func_ctrl.sign_mot_on;
+
return ret;
}
@@ -2876,16 +3293,23 @@ int32_t lis2ds12_motion_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_ADV_BANK);
- if(ret == 0){
- ret = lis2ds12_read_reg(ctx, LIS2DS12_SM_THS, (uint8_t*)&sm_ths, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_SM_THS, (uint8_t *)&sm_ths, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
sm_ths.sm_ths = val;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_SM_THS, (uint8_t*)&sm_ths, 1);
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_SM_THS, (uint8_t *)&sm_ths, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK);
}
+
return ret;
}
@@ -2907,13 +3331,18 @@ int32_t lis2ds12_motion_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_ADV_BANK);
- if(ret == 0){
- ret = lis2ds12_read_reg(ctx, LIS2DS12_SM_THS, (uint8_t*)&sm_ths, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_SM_THS, (uint8_t *)&sm_ths, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = sm_ths.sm_ths;
ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK);
}
+
return ret;
}
@@ -2938,13 +3367,16 @@ int32_t lis2ds12_motion_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2ds12_tilt_data_ready_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2ds12_tilt_data_ready_flag_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2ds12_func_ck_gate_t func_ck_gate;
int32_t ret;
+
ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CK_GATE,
- (uint8_t*)&func_ck_gate, 1);
+ (uint8_t *)&func_ck_gate, 1);
*val = func_ck_gate.tilt_int;
+
return ret;
}
@@ -2961,11 +3393,16 @@ int32_t lis2ds12_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val)
lis2ds12_func_ctrl_t func_ctrl;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL, (uint8_t*)&func_ctrl, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL,
+ (uint8_t *)&func_ctrl, 1);
+
+ if (ret == 0)
+ {
func_ctrl.tilt_on = val;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_FUNC_CTRL, (uint8_t*)&func_ctrl, 1);
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_FUNC_CTRL,
+ (uint8_t *)&func_ctrl, 1);
}
+
return ret;
}
@@ -2981,8 +3418,11 @@ int32_t lis2ds12_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
{
lis2ds12_func_ctrl_t func_ctrl;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL, (uint8_t*)&func_ctrl, 1);
+
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL,
+ (uint8_t *)&func_ctrl, 1);
*val = func_ctrl.tilt_on;
+
return ret;
}
@@ -3012,11 +3452,16 @@ int32_t lis2ds12_module_sens_set(stmdev_ctx_t *ctx, uint8_t val)
lis2ds12_func_ctrl_t func_ctrl;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL, (uint8_t*)&func_ctrl, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL,
+ (uint8_t *)&func_ctrl, 1);
+
+ if (ret == 0)
+ {
func_ctrl.module_on = val;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_FUNC_CTRL, (uint8_t*)&func_ctrl, 1);
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_FUNC_CTRL,
+ (uint8_t *)&func_ctrl, 1);
}
+
return ret;
}
@@ -3032,8 +3477,11 @@ int32_t lis2ds12_module_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
{
lis2ds12_func_ctrl_t func_ctrl;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL, (uint8_t*)&func_ctrl, 1);
+
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL,
+ (uint8_t *)&func_ctrl, 1);
*val = func_ctrl.module_on;
+
return ret;
}
@@ -3062,7 +3510,10 @@ int32_t lis2ds12_sh_read_data_raw_get(stmdev_ctx_t *ctx,
lis2ds12_sh_read_data_raw_t *val)
{
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_SENSORHUB1_REG, (uint8_t*) val, 6);
+
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_SENSORHUB1_REG, (uint8_t *) val,
+ 6);
+
return ret;
}
@@ -3079,11 +3530,16 @@ int32_t lis2ds12_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
lis2ds12_func_ctrl_t func_ctrl;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL, (uint8_t*)&func_ctrl, 1);
- if(ret == 0){
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL,
+ (uint8_t *)&func_ctrl, 1);
+
+ if (ret == 0)
+ {
func_ctrl.master_on = val;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_FUNC_CTRL, (uint8_t*)&func_ctrl, 1);
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_FUNC_CTRL,
+ (uint8_t *)&func_ctrl, 1);
}
+
return ret;
}
@@ -3099,8 +3555,11 @@ int32_t lis2ds12_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
{
lis2ds12_func_ctrl_t func_ctrl;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL, (uint8_t*)&func_ctrl, 1);
+
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL,
+ (uint8_t *)&func_ctrl, 1);
*val = func_ctrl.master_on;
+
return ret;
}
@@ -3122,23 +3581,32 @@ int32_t lis2ds12_sh_cfg_write(stmdev_ctx_t *ctx,
int32_t ret;
ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_ADV_BANK);
- if(ret == 0){
- slv0_add.slave0_add = (val->slv_add & 0xFEU) >> 1;
+
+ if (ret == 0)
+ {
+ slv0_add.slave0_add = (val->slv_add & 0xFEU) >> 1;
slv0_add.rw_0 = 0;
ret = lis2ds12_write_reg(ctx, LIS2DS12_SLV0_ADD,
- (uint8_t*)&slv0_add, 1);
+ (uint8_t *)&slv0_add, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lis2ds12_write_reg(ctx, LIS2DS12_SLV0_SUBADD,
- &(val->slv_subadd), 1);
+ &(val->slv_subadd), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lis2ds12_write_reg(ctx, LIS2DS12_DATAWRITE_SLV0,
- &(val->slv_data), 1);
+ &(val->slv_data), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK);
}
+
return ret;
}
@@ -3158,32 +3626,42 @@ int32_t lis2ds12_sh_slv_cfg_read(stmdev_ctx_t *ctx,
{
lis2ds12_slv0_add_t slv0_add;
lis2ds12_slv0_config_t slv0_config;
-
int32_t ret;
ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_ADV_BANK);
- if(ret == 0){
- slv0_add.slave0_add = (val->slv_add & 0xFEU) >> 1;
+
+ if (ret == 0)
+ {
+ slv0_add.slave0_add = (val->slv_add & 0xFEU) >> 1;
slv0_add.rw_0 = 1;
- ret = lis2ds12_write_reg(ctx, LIS2DS12_SLV0_ADD,
- (uint8_t*)&slv0_add, 1);
+ ret = lis2ds12_write_reg(ctx, LIS2DS12_SLV0_ADD,
+ (uint8_t *)&slv0_add, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lis2ds12_write_reg(ctx, LIS2DS12_SLV0_SUBADD,
&(val->slv_subadd), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lis2ds12_read_reg(ctx, LIS2DS12_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv0_config.slave0_numop = val->slv_len;
ret = lis2ds12_write_reg(ctx, LIS2DS12_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK);
}
+
return ret;
}
@@ -3199,8 +3677,10 @@ int32_t lis2ds12_sh_end_op_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
{
lis2ds12_func_src_t func_src;
int32_t ret;
- ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_SRC, (uint8_t*)&func_src, 1);
+
+ ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_SRC, (uint8_t *)&func_src, 1);
*val = func_src.sensorhub_end_op;
+
return ret;
}
diff --git a/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.h b/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.h
index 17a972ac06f7db5166172d51b4270344ec52a0c9..b95500d69e5646f1ff2cb09f1734c0421394344d 100644
--- a/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.h
+++ b/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file lis2ds12_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lis2ds12_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lis2ds12_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lis2ds12_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LIS2DS12_REGS_H
#define LIS2DS12_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup LIS2DS12
@@ -74,7 +75,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -107,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -131,7 +134,7 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
+ * You can create a sensor configuration by your own or using
* Unico / Unicleo tools available on STMicroelectronics
* web site.
*
@@ -139,7 +142,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -161,7 +165,7 @@ typedef struct {
*
*/
- /** I2C Device Address 8 bit format if SA0=0 -> 0x3D if SA0=1 -> 0x3B **/
+/** I2C Device Address 8 bit format if SA0=0 -> 0x3D if SA0=1 -> 0x3B **/
#define LIS2DS12_I2C_ADD_L 0x3DU
#define LIS2DS12_I2C_ADD_H 0x3BU
@@ -174,7 +178,8 @@ typedef struct {
*/
#define LIS2DS12_SENSORHUB1_REG 0x06U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -197,7 +202,8 @@ typedef struct {
} lis2ds12_sensorhub1_reg_t;
#define LIS2DS12_SENSORHUB2_REG 0x07U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -220,7 +226,8 @@ typedef struct {
} lis2ds12_sensorhub2_reg_t;
#define LIS2DS12_SENSORHUB3_REG 0x08U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -243,7 +250,8 @@ typedef struct {
} lis2ds12_sensorhub3_reg_t;
#define LIS2DS12_SENSORHUB4_REG 0x09U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -266,7 +274,8 @@ typedef struct {
} lis2ds12_sensorhub4_reg_t;
#define LIS2DS12_SENSORHUB5_REG 0x0AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -289,7 +298,8 @@ typedef struct {
} lis2ds12_sensorhub5_reg_t;
#define LIS2DS12_SENSORHUB6_REG 0x0BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -314,7 +324,8 @@ typedef struct {
#define LIS2DS12_MODULE_8BIT 0x0CU
#define LIS2DS12_WHO_AM_I 0x0FU
#define LIS2DS12_CTRL1 0x20U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bdu : 1;
uint8_t hf_odr : 1;
@@ -330,7 +341,8 @@ typedef struct {
} lis2ds12_ctrl1_t;
#define LIS2DS12_CTRL2 0x21U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t i2c_disable : 1;
@@ -354,7 +366,8 @@ typedef struct {
} lis2ds12_ctrl2_t;
#define LIS2DS12_CTRL3 0x22U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t pp_od : 1;
uint8_t h_lactive : 1;
@@ -376,7 +389,8 @@ typedef struct {
} lis2ds12_ctrl3_t;
#define LIS2DS12_CTRL4 0x23U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_drdy : 1;
uint8_t int1_fth : 1;
@@ -399,7 +413,8 @@ typedef struct {
} lis2ds12_ctrl4_t;
#define LIS2DS12_CTRL5 0x24U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_drdy : 1;
uint8_t int2_fth : 1;
@@ -422,7 +437,8 @@ typedef struct {
} lis2ds12_ctrl5_t;
#define LIS2DS12_FIFO_CTRL 0x25U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t if_cs_pu_dis : 1;
uint8_t not_used_01 : 2;
@@ -440,7 +456,8 @@ typedef struct {
#define LIS2DS12_OUT_T 0x26U
#define LIS2DS12_STATUS 0x27U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t drdy : 1;
uint8_t ff_ia : 1;
@@ -469,12 +486,14 @@ typedef struct {
#define LIS2DS12_OUT_Z_L 0x2CU
#define LIS2DS12_OUT_Z_H 0x2DU
#define LIS2DS12_FIFO_THS 0x2EU
-typedef struct {
+typedef struct
+{
uint8_t fth : 8;
} lis2ds12_fifo_ths_t;
#define LIS2DS12_FIFO_SRC 0x2FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 5;
uint8_t diff : 1;
@@ -490,7 +509,8 @@ typedef struct {
#define LIS2DS12_FIFO_SAMPLES 0x30U
#define LIS2DS12_TAP_6D_THS 0x31U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_ths : 5;
uint8_t _6d_ths : 2;
@@ -503,7 +523,8 @@ typedef struct {
} lis2ds12_tap_6d_ths_t;
#define LIS2DS12_INT_DUR 0x32U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shock : 2;
uint8_t quiet : 2;
@@ -516,7 +537,8 @@ typedef struct {
} lis2ds12_int_dur_t;
#define LIS2DS12_WAKE_UP_THS 0x33U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wu_ths : 6;
uint8_t sleep_on : 1;
@@ -529,7 +551,8 @@ typedef struct {
} lis2ds12_wake_up_ths_t;
#define LIS2DS12_WAKE_UP_DUR 0x34U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sleep_dur : 4;
uint8_t int1_fss7 : 1;
@@ -544,7 +567,8 @@ typedef struct {
} lis2ds12_wake_up_dur_t;
#define LIS2DS12_FREE_FALL 0x35U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ths : 3;
uint8_t ff_dur : 5;
@@ -555,7 +579,8 @@ typedef struct {
} lis2ds12_free_fall_t;
#define LIS2DS12_STATUS_DUP 0x36U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t drdy : 1;
uint8_t ff_ia : 1;
@@ -578,7 +603,8 @@ typedef struct {
} lis2ds12_status_dup_t;
#define LIS2DS12_WAKE_UP_SRC 0x37U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_wu : 1;
uint8_t y_wu : 1;
@@ -599,7 +625,8 @@ typedef struct {
} lis2ds12_wake_up_src_t;
#define LIS2DS12_TAP_SRC 0x38U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_tap : 1;
uint8_t y_tap : 1;
@@ -622,7 +649,8 @@ typedef struct {
} lis2ds12_tap_src_t;
#define LIS2DS12_6D_SRC 0x39U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
@@ -645,7 +673,8 @@ typedef struct {
} lis2ds12_6d_src_t;
#define LIS2DS12_STEP_COUNTER_MINTHS 0x3AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sc_mths : 6;
uint8_t pedo4g : 1;
@@ -660,7 +689,8 @@ typedef struct {
#define LIS2DS12_STEP_COUNTER_L 0x3BU
#define LIS2DS12_STEP_COUNTER_H 0x3CU
#define LIS2DS12_FUNC_CK_GATE 0x3DU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ck_gate_func : 1;
uint8_t step_detect : 1;
@@ -681,7 +711,8 @@ typedef struct {
} lis2ds12_func_ck_gate_t;
#define LIS2DS12_FUNC_SRC 0x3EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sensorhub_end_op : 1;
uint8_t module_ready : 1;
@@ -696,7 +727,8 @@ typedef struct {
} lis2ds12_func_src_t;
#define LIS2DS12_FUNC_CTRL 0x3FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t step_cnt_on : 1;
uint8_t sign_mot_on : 1;
@@ -717,7 +749,8 @@ typedef struct {
} lis2ds12_func_ctrl_t;
#define LIS2DS12_PEDO_DEB_REG 0x2BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t deb_step : 3;
uint8_t deb_time : 5;
@@ -728,7 +761,8 @@ typedef struct {
} lis2ds12_pedo_deb_reg_t;
#define LIS2DS12_SLV0_ADD 0x30U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t rw_0 : 1;
uint8_t slave0_add : 7;
@@ -739,12 +773,14 @@ typedef struct {
} lis2ds12_slv0_add_t;
#define LIS2DS12_SLV0_SUBADD 0x31U
-typedef struct {
+typedef struct
+{
uint8_t slave0_reg : 8;
} lis2ds12_slv0_subadd_t;
#define LIS2DS12_SLV0_CONFIG 0x32U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave0_numop : 3;
uint8_t not_used_01 : 5;
@@ -755,22 +791,26 @@ typedef struct {
} lis2ds12_slv0_config_t;
#define LIS2DS12_DATAWRITE_SLV0 0x33U
-typedef struct {
+typedef struct
+{
uint8_t slave_dataw : 8;
} lis2ds12_datawrite_slv0_t;
#define LIS2DS12_SM_THS 0x34U
-typedef struct {
+typedef struct
+{
uint8_t sm_ths : 8;
} lis2ds12_sm_ths_t;
#define LIS2DS12_STEP_COUNT_DELTA 0x3AU
-typedef struct {
+typedef struct
+{
uint8_t step_count_d : 8;
} lis2ds12_step_count_delta_t;
#define LIS2DS12_CTRL2_ADV 0x3FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t i2c_disable : 1;
@@ -794,9 +834,9 @@ typedef struct {
/**
* @defgroup LIS2DS12_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -804,7 +844,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
lis2ds12_sensorhub1_reg_t sensorhub1_reg;
lis2ds12_sensorhub2_reg_t sensorhub2_reg;
lis2ds12_sensorhub3_reg_t sensorhub3_reg;
@@ -849,9 +890,11 @@ typedef union{
*
*/
-int32_t lis2ds12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lis2ds12_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t lis2ds12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lis2ds12_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
float_t lis2ds12_from_fs2g_to_mg(int16_t lsb);
@@ -861,7 +904,8 @@ float_t lis2ds12_from_fs16g_to_mg(int16_t lsb);
float_t lis2ds12_from_lsb_to_celsius(int16_t lsb);
-typedef struct {
+typedef struct
+{
lis2ds12_fifo_src_t fifo_src;
lis2ds12_status_dup_t status_dup;
lis2ds12_wake_up_src_t wake_up_src;
@@ -869,23 +913,29 @@ typedef struct {
lis2ds12_6d_src_t _6d_src;
lis2ds12_func_ck_gate_t func_ck_gate;
lis2ds12_func_src_t func_src;
- } lis2ds12_all_sources_t;
+} lis2ds12_all_sources_t;
int32_t lis2ds12_all_sources_get(stmdev_ctx_t *ctx,
lis2ds12_all_sources_t *val);
-int32_t lis2ds12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2ds12_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2ds12_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2ds12_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DS12_2g = 0,
LIS2DS12_16g = 1,
LIS2DS12_4g = 2,
LIS2DS12_8g = 3,
} lis2ds12_fs_t;
-int32_t lis2ds12_xl_full_scale_set(stmdev_ctx_t *ctx, lis2ds12_fs_t val);
-int32_t lis2ds12_xl_full_scale_get(stmdev_ctx_t *ctx, lis2ds12_fs_t *val);
+int32_t lis2ds12_xl_full_scale_set(stmdev_ctx_t *ctx,
+ lis2ds12_fs_t val);
+int32_t lis2ds12_xl_full_scale_get(stmdev_ctx_t *ctx,
+ lis2ds12_fs_t *val);
-typedef enum {
+typedef enum
+{
LIS2DS12_XL_ODR_OFF = 0x00,
LIS2DS12_XL_ODR_1Hz_LP = 0x08,
LIS2DS12_XL_ODR_12Hz5_LP = 0x09,
@@ -906,19 +956,25 @@ typedef enum {
LIS2DS12_XL_ODR_3k2Hz_HF = 0x16,
LIS2DS12_XL_ODR_6k4Hz_HF = 0x17,
} lis2ds12_odr_t;
-int32_t lis2ds12_xl_data_rate_set(stmdev_ctx_t *ctx, lis2ds12_odr_t val);
-int32_t lis2ds12_xl_data_rate_get(stmdev_ctx_t *ctx, lis2ds12_odr_t *val);
+int32_t lis2ds12_xl_data_rate_set(stmdev_ctx_t *ctx,
+ lis2ds12_odr_t val);
+int32_t lis2ds12_xl_data_rate_get(stmdev_ctx_t *ctx,
+ lis2ds12_odr_t *val);
-int32_t lis2ds12_status_reg_get(stmdev_ctx_t *ctx, lis2ds12_status_t *val);
+int32_t lis2ds12_status_reg_get(stmdev_ctx_t *ctx,
+ lis2ds12_status_t *val);
-int32_t lis2ds12_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2ds12_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lis2ds12_acceleration_module_raw_get(stmdev_ctx_t *ctx,
uint8_t *buff);
-int32_t lis2ds12_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lis2ds12_temperature_raw_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
-int32_t lis2ds12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t lis2ds12_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
int32_t lis2ds12_number_of_steps_get(stmdev_ctx_t *ctx, int16_t *val);
@@ -927,7 +983,8 @@ int32_t lis2ds12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t lis2ds12_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2ds12_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DS12_USER_BANK = 0,
LIS2DS12_ADV_BANK = 1,
} lis2ds12_func_cfg_en_t;
@@ -940,15 +997,19 @@ int32_t lis2ds12_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2ds12_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2ds12_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DS12_XL_ST_DISABLE = 0,
LIS2DS12_XL_ST_POSITIVE = 1,
LIS2DS12_XL_ST_NEGATIVE = 2,
} lis2ds12_st_t;
-int32_t lis2ds12_xl_self_test_set(stmdev_ctx_t *ctx, lis2ds12_st_t val);
-int32_t lis2ds12_xl_self_test_get(stmdev_ctx_t *ctx, lis2ds12_st_t *val);
+int32_t lis2ds12_xl_self_test_set(stmdev_ctx_t *ctx,
+ lis2ds12_st_t val);
+int32_t lis2ds12_xl_self_test_get(stmdev_ctx_t *ctx,
+ lis2ds12_st_t *val);
-typedef enum {
+typedef enum
+{
LIS2DS12_DRDY_LATCHED = 0,
LIS2DS12_DRDY_PULSED = 1,
} lis2ds12_drdy_pulsed_t;
@@ -957,7 +1018,8 @@ int32_t lis2ds12_data_ready_mode_set(stmdev_ctx_t *ctx,
int32_t lis2ds12_data_ready_mode_get(stmdev_ctx_t *ctx,
lis2ds12_drdy_pulsed_t *val);
-typedef enum {
+typedef enum
+{
LIS2DS12_HP_INTERNAL_ONLY = 0,
LIS2DS12_HP_ON_OUTPUTS = 1,
} lis2ds12_fds_slope_t;
@@ -966,14 +1028,16 @@ int32_t lis2ds12_xl_hp_path_set(stmdev_ctx_t *ctx,
int32_t lis2ds12_xl_hp_path_get(stmdev_ctx_t *ctx,
lis2ds12_fds_slope_t *val);
-typedef enum {
+typedef enum
+{
LIS2DS12_SPI_4_WIRE = 0,
LIS2DS12_SPI_3_WIRE = 1,
} lis2ds12_sim_t;
int32_t lis2ds12_spi_mode_set(stmdev_ctx_t *ctx, lis2ds12_sim_t val);
int32_t lis2ds12_spi_mode_get(stmdev_ctx_t *ctx, lis2ds12_sim_t *val);
-typedef enum {
+typedef enum
+{
LIS2DS12_I2C_ENABLE = 0,
LIS2DS12_I2C_DISABLE = 1,
} lis2ds12_i2c_disable_t;
@@ -982,7 +1046,8 @@ int32_t lis2ds12_i2c_interface_set(stmdev_ctx_t *ctx,
int32_t lis2ds12_i2c_interface_get(stmdev_ctx_t *ctx,
lis2ds12_i2c_disable_t *val);
-typedef enum {
+typedef enum
+{
LIS2DS12_PULL_UP_CONNECTED = 0,
LIS2DS12_PULL_UP_DISCONNECTED = 1,
} lis2ds12_if_cs_pu_dis_t;
@@ -991,14 +1056,18 @@ int32_t lis2ds12_cs_mode_set(stmdev_ctx_t *ctx,
int32_t lis2ds12_cs_mode_get(stmdev_ctx_t *ctx,
lis2ds12_if_cs_pu_dis_t *val);
-typedef enum {
+typedef enum
+{
LIS2DS12_PUSH_PULL = 0,
LIS2DS12_OPEN_DRAIN = 1,
} lis2ds12_pp_od_t;
-int32_t lis2ds12_pin_mode_set(stmdev_ctx_t *ctx, lis2ds12_pp_od_t val);
-int32_t lis2ds12_pin_mode_get(stmdev_ctx_t *ctx, lis2ds12_pp_od_t *val);
+int32_t lis2ds12_pin_mode_set(stmdev_ctx_t *ctx,
+ lis2ds12_pp_od_t val);
+int32_t lis2ds12_pin_mode_get(stmdev_ctx_t *ctx,
+ lis2ds12_pp_od_t *val);
-typedef enum {
+typedef enum
+{
LIS2DS12_ACTIVE_HIGH = 0,
LIS2DS12_ACTIVE_LOW = 1,
} lis2ds12_h_lactive_t;
@@ -1007,7 +1076,8 @@ int32_t lis2ds12_pin_polarity_set(stmdev_ctx_t *ctx,
int32_t lis2ds12_pin_polarity_get(stmdev_ctx_t *ctx,
lis2ds12_h_lactive_t *val);
-typedef enum {
+typedef enum
+{
LIS2DS12_INT_PULSED = 0,
LIS2DS12_INT_LATCHED = 1,
} lis2ds12_lir_t;
@@ -1016,7 +1086,8 @@ int32_t lis2ds12_int_notification_set(stmdev_ctx_t *ctx,
int32_t lis2ds12_int_notification_get(stmdev_ctx_t *ctx,
lis2ds12_lir_t *val);
-typedef struct{
+typedef struct
+{
uint8_t int1_drdy : 1;
uint8_t int1_fth : 1;
uint8_t int1_6d : 1;
@@ -1032,7 +1103,8 @@ int32_t lis2ds12_pin_int1_route_set(stmdev_ctx_t *ctx,
int32_t lis2ds12_pin_int1_route_get(stmdev_ctx_t *ctx,
lis2ds12_pin_int1_route_t *val);
-typedef struct{
+typedef struct
+{
uint8_t int2_boot : 1;
uint8_t int2_tilt : 1;
uint8_t int2_sig_mot : 1;
@@ -1060,14 +1132,20 @@ int32_t lis2ds12_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2ds12_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2ds12_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lis2ds12_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2ds12_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2ds12_tap_detection_on_z_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2ds12_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lis2ds12_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2ds12_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2ds12_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2ds12_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lis2ds12_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2ds12_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2ds12_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2ds12_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lis2ds12_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2ds12_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1081,7 +1159,8 @@ int32_t lis2ds12_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2ds12_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2ds12_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DS12_ONLY_SINGLE = 0,
LIS2DS12_ONLY_DOUBLE = 1,
} lis2ds12_single_double_tap_t;
@@ -1090,21 +1169,26 @@ int32_t lis2ds12_tap_mode_set(stmdev_ctx_t *ctx,
int32_t lis2ds12_tap_mode_get(stmdev_ctx_t *ctx,
lis2ds12_single_double_tap_t *val);
-int32_t lis2ds12_tap_src_get(stmdev_ctx_t *ctx, lis2ds12_tap_src_t *val);
+int32_t lis2ds12_tap_src_get(stmdev_ctx_t *ctx,
+ lis2ds12_tap_src_t *val);
-typedef enum {
+typedef enum
+{
LIS2DS12_DEG_80 = 0,
LIS2DS12_DEG_70 = 1,
LIS2DS12_DEG_60 = 2,
LIS2DS12_DEG_50 = 3,
} lis2ds12_6d_ths_t;
-int32_t lis2ds12_6d_threshold_set(stmdev_ctx_t *ctx, lis2ds12_6d_ths_t val);
-int32_t lis2ds12_6d_threshold_get(stmdev_ctx_t *ctx, lis2ds12_6d_ths_t *val);
+int32_t lis2ds12_6d_threshold_set(stmdev_ctx_t *ctx,
+ lis2ds12_6d_ths_t val);
+int32_t lis2ds12_6d_threshold_get(stmdev_ctx_t *ctx,
+ lis2ds12_6d_ths_t *val);
int32_t lis2ds12_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2ds12_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lis2ds12_6d_src_get(stmdev_ctx_t *ctx, lis2ds12_6d_src_t *val);
+int32_t lis2ds12_6d_src_get(stmdev_ctx_t *ctx,
+ lis2ds12_6d_src_t *val);
int32_t lis2ds12_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2ds12_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1112,18 +1196,23 @@ int32_t lis2ds12_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2ds12_ff_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2ds12_ff_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lis2ds12_fifo_xl_module_batch_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2ds12_fifo_xl_module_batch_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2ds12_fifo_xl_module_batch_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2ds12_fifo_xl_module_batch_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DS12_BYPASS_MODE = 0,
LIS2DS12_FIFO_MODE = 1,
LIS2DS12_STREAM_TO_FIFO_MODE = 3,
LIS2DS12_BYPASS_TO_STREAM_MODE = 4,
LIS2DS12_STREAM_MODE = 6,
} lis2ds12_fmode_t;
-int32_t lis2ds12_fifo_mode_set(stmdev_ctx_t *ctx, lis2ds12_fmode_t val);
-int32_t lis2ds12_fifo_mode_get(stmdev_ctx_t *ctx, lis2ds12_fmode_t *val);
+int32_t lis2ds12_fifo_mode_set(stmdev_ctx_t *ctx,
+ lis2ds12_fmode_t val);
+int32_t lis2ds12_fifo_mode_get(stmdev_ctx_t *ctx,
+ lis2ds12_fmode_t *val);
int32_t lis2ds12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2ds12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1134,14 +1223,17 @@ int32_t lis2ds12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2ds12_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lis2ds12_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t lis2ds12_fifo_data_level_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
-int32_t lis2ds12_fifo_src_get(stmdev_ctx_t *ctx, lis2ds12_fifo_src_t *val);
+int32_t lis2ds12_fifo_src_get(stmdev_ctx_t *ctx,
+ lis2ds12_fifo_src_t *val);
int32_t lis2ds12_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2ds12_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DS12_PEDO_AT_2g = 0,
LIS2DS12_PEDO_AT_4g = 1,
} lis2ds12_pedo4g_t;
@@ -1153,28 +1245,36 @@ int32_t lis2ds12_pedo_full_scale_get(stmdev_ctx_t *ctx,
int32_t lis2ds12_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2ds12_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lis2ds12_pedo_step_detect_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2ds12_pedo_step_detect_flag_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lis2ds12_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2ds12_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lis2ds12_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2ds12_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2ds12_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2ds12_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lis2ds12_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2ds12_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lis2ds12_pedo_steps_period_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lis2ds12_pedo_steps_period_get(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lis2ds12_motion_data_ready_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2ds12_pedo_steps_period_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lis2ds12_pedo_steps_period_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lis2ds12_motion_data_ready_flag_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lis2ds12_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2ds12_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2ds12_motion_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2ds12_motion_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2ds12_motion_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lis2ds12_tilt_data_ready_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2ds12_tilt_data_ready_flag_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lis2ds12_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2ds12_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1182,13 +1282,14 @@ int32_t lis2ds12_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2ds12_module_sens_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2ds12_module_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef struct {
- lis2ds12_sensorhub1_reg_t sensorhub1_reg;
- lis2ds12_sensorhub2_reg_t sensorhub2_reg;
- lis2ds12_sensorhub3_reg_t sensorhub3_reg;
- lis2ds12_sensorhub4_reg_t sensorhub4_reg;
- lis2ds12_sensorhub5_reg_t sensorhub5_reg;
- lis2ds12_sensorhub6_reg_t sensorhub6_reg;
+typedef struct
+{
+ lis2ds12_sensorhub1_reg_t sensorhub1_reg;
+ lis2ds12_sensorhub2_reg_t sensorhub2_reg;
+ lis2ds12_sensorhub3_reg_t sensorhub3_reg;
+ lis2ds12_sensorhub4_reg_t sensorhub4_reg;
+ lis2ds12_sensorhub5_reg_t sensorhub5_reg;
+ lis2ds12_sensorhub6_reg_t sensorhub6_reg;
} lis2ds12_sh_read_data_raw_t;
int32_t lis2ds12_sh_read_data_raw_get(stmdev_ctx_t *ctx,
lis2ds12_sh_read_data_raw_t *val);
@@ -1196,14 +1297,18 @@ int32_t lis2ds12_sh_read_data_raw_get(stmdev_ctx_t *ctx,
int32_t lis2ds12_sh_master_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2ds12_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DS12_EXT_PULL_UP = 0,
LIS2DS12_INTERNAL_PULL_UP = 1,
} lis2ds12_tud_en_t;
-int32_t lis2ds12_sh_pin_mode_set(stmdev_ctx_t *ctx, lis2ds12_tud_en_t val);
-int32_t lis2ds12_sh_pin_mode_get(stmdev_ctx_t *ctx, lis2ds12_tud_en_t *val);
+int32_t lis2ds12_sh_pin_mode_set(stmdev_ctx_t *ctx,
+ lis2ds12_tud_en_t val);
+int32_t lis2ds12_sh_pin_mode_get(stmdev_ctx_t *ctx,
+ lis2ds12_tud_en_t *val);
-typedef struct{
+typedef struct
+{
uint8_t slv_add;
uint8_t slv_subadd;
uint8_t slv_data;
@@ -1211,7 +1316,8 @@ typedef struct{
int32_t lis2ds12_sh_cfg_write(stmdev_ctx_t *ctx,
lis2ds12_sh_cfg_write_t *val);
-typedef struct{
+typedef struct
+{
uint8_t slv_add;
uint8_t slv_subadd;
uint8_t slv_len;
@@ -1220,7 +1326,8 @@ int32_t lis2ds12_sh_slv_cfg_read(stmdev_ctx_t *ctx,
lis2ds12_sh_cfg_read_t *val);
int32_t lis2ds12_sh_slv0_cfg_read_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2ds12_sh_slv0_cfg_read_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2ds12_sh_slv0_cfg_read_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lis2ds12_sh_end_op_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
diff --git a/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.c b/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.c
index 2fccd3eedb5f6615d3310c21ec650cf4185d8ae6..e85c1e9a9bacbd95c393a125eb510a185d331b20 100644
--- a/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.c
+++ b/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file lis2dtw12_reg.c
- * @author Sensors Software Solution Team
- * @brief LIS2DTW12 driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lis2dtw12_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LIS2DTW12 driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lis2dtw12_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lis2dtw12_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t lis2dtw12_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lis2dtw12_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -101,7 +107,7 @@ float_t lis2dtw12_from_fs8_to_mg(int16_t lsb)
float_t lis2dtw12_from_fs16_to_mg(int16_t lsb)
{
- return ((float_t)lsb) *0.488f;
+ return ((float_t)lsb) * 0.488f;
}
float_t lis2dtw12_from_fs2_lp1_to_mg(int16_t lsb)
@@ -151,25 +157,33 @@ float_t lis2dtw12_from_lsb_to_celsius(int16_t lsb)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_power_mode_set(stmdev_ctx_t *ctx, lis2dtw12_mode_t val)
+int32_t lis2dtw12_power_mode_set(stmdev_ctx_t *ctx,
+ lis2dtw12_mode_t val)
{
lis2dtw12_ctrl1_t ctrl1;
lis2dtw12_ctrl6_t ctrl6;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL1,(uint8_t*) &ctrl1, 1);
- if (ret == 0) {
- ctrl1.mode = ( (uint8_t) val & 0x0CU ) >> 2;
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL1, (uint8_t *) &ctrl1, 1);
+
+ if (ret == 0)
+ {
+ ctrl1.mode = ((uint8_t) val & 0x0CU) >> 2;
ctrl1.lp_mode = (uint8_t) val & 0x03U ;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL1,(uint8_t*) &ctrl1, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL1, (uint8_t *) &ctrl1, 1);
}
- if (ret == 0) {
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL6,(uint8_t*) &ctrl6, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL6, (uint8_t *) &ctrl6, 1);
}
- if (ret == 0) {
- ctrl6.low_noise = ( (uint8_t) val & 0x10U ) >> 4;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL6,(uint8_t*) &ctrl6, 1);
+
+ if (ret == 0)
+ {
+ ctrl6.low_noise = ((uint8_t) val & 0x10U) >> 4;
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL6, (uint8_t *) &ctrl6, 1);
}
+
return ret;
}
@@ -182,77 +196,100 @@ int32_t lis2dtw12_power_mode_set(stmdev_ctx_t *ctx, lis2dtw12_mode_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_power_mode_get(stmdev_ctx_t *ctx, lis2dtw12_mode_t *val)
+int32_t lis2dtw12_power_mode_get(stmdev_ctx_t *ctx,
+ lis2dtw12_mode_t *val)
{
lis2dtw12_ctrl1_t ctrl1;
lis2dtw12_ctrl6_t ctrl6;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL1,(uint8_t*) &ctrl1, 1);
- if (ret == 0) {
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL6,(uint8_t*) &ctrl6, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL1, (uint8_t *) &ctrl1, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL6, (uint8_t *) &ctrl6, 1);
switch (((ctrl6.low_noise << 4) + (ctrl1.mode << 2) +
- ctrl1.lp_mode)) {
+ ctrl1.lp_mode))
+ {
case LIS2DTW12_HIGH_PERFORMANCE:
*val = LIS2DTW12_HIGH_PERFORMANCE;
break;
+
case LIS2DTW12_CONT_LOW_PWR_4:
*val = LIS2DTW12_CONT_LOW_PWR_4;
break;
+
case LIS2DTW12_CONT_LOW_PWR_3:
*val = LIS2DTW12_CONT_LOW_PWR_3;
break;
+
case LIS2DTW12_CONT_LOW_PWR_2:
*val = LIS2DTW12_CONT_LOW_PWR_2;
break;
+
case LIS2DTW12_CONT_LOW_PWR_12bit:
*val = LIS2DTW12_CONT_LOW_PWR_12bit;
break;
+
case LIS2DTW12_SINGLE_LOW_PWR_4:
*val = LIS2DTW12_SINGLE_LOW_PWR_4;
break;
+
case LIS2DTW12_SINGLE_LOW_PWR_3:
*val = LIS2DTW12_SINGLE_LOW_PWR_3;
break;
+
case LIS2DTW12_SINGLE_LOW_PWR_2:
*val = LIS2DTW12_SINGLE_LOW_PWR_2;
break;
+
case LIS2DTW12_SINGLE_LOW_PWR_12bit:
*val = LIS2DTW12_SINGLE_LOW_PWR_12bit;
break;
+
case LIS2DTW12_HIGH_PERFORMANCE_LOW_NOISE:
*val = LIS2DTW12_HIGH_PERFORMANCE_LOW_NOISE;
break;
+
case LIS2DTW12_CONT_LOW_PWR_LOW_NOISE_4:
*val = LIS2DTW12_CONT_LOW_PWR_LOW_NOISE_4;
break;
+
case LIS2DTW12_CONT_LOW_PWR_LOW_NOISE_3:
*val = LIS2DTW12_CONT_LOW_PWR_LOW_NOISE_3;
break;
+
case LIS2DTW12_CONT_LOW_PWR_LOW_NOISE_2:
*val = LIS2DTW12_CONT_LOW_PWR_LOW_NOISE_2;
break;
+
case LIS2DTW12_CONT_LOW_PWR_LOW_NOISE_12bit:
*val = LIS2DTW12_CONT_LOW_PWR_LOW_NOISE_12bit;
break;
+
case LIS2DTW12_SINGLE_LOW_PWR_LOW_NOISE_4:
*val = LIS2DTW12_SINGLE_LOW_PWR_LOW_NOISE_4;
break;
+
case LIS2DTW12_SINGLE_LOW_PWR_LOW_NOISE_3:
*val = LIS2DTW12_SINGLE_LOW_PWR_LOW_NOISE_3;
break;
+
case LIS2DTW12_SINGLE_LOW_PWR_LOW_NOISE_2:
*val = LIS2DTW12_SINGLE_LOW_PWR_LOW_NOISE_2;
break;
+
case LIS2DTW12_SINGLE_LOW_LOW_NOISE_PWR_12bit:
*val = LIS2DTW12_SINGLE_LOW_LOW_NOISE_PWR_12bit;
break;
+
default:
*val = LIS2DTW12_HIGH_PERFORMANCE;
break;
}
}
+
return ret;
}
@@ -264,24 +301,32 @@ int32_t lis2dtw12_power_mode_get(stmdev_ctx_t *ctx, lis2dtw12_mode_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_data_rate_set(stmdev_ctx_t *ctx, lis2dtw12_odr_t val)
+int32_t lis2dtw12_data_rate_set(stmdev_ctx_t *ctx,
+ lis2dtw12_odr_t val)
{
lis2dtw12_ctrl1_t ctrl1;
lis2dtw12_ctrl3_t ctrl3;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL1,(uint8_t*) &ctrl1, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL1, (uint8_t *) &ctrl1, 1);
+
+ if (ret == 0)
+ {
ctrl1.odr = (uint8_t) val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL1,(uint8_t*) &ctrl1, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL1, (uint8_t *) &ctrl1, 1);
}
- if (ret == 0) {
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3,(uint8_t*) &ctrl3, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) &ctrl3, 1);
}
- if (ret == 0) {
- ctrl3.slp_mode = ( (uint8_t) val & 0x30U ) >> 4;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL3,(uint8_t*) &ctrl3, 1);
+
+ if (ret == 0)
+ {
+ ctrl3.slp_mode = ((uint8_t) val & 0x30U) >> 4;
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) &ctrl3, 1);
}
+
return ret;
}
@@ -293,58 +338,75 @@ int32_t lis2dtw12_data_rate_set(stmdev_ctx_t *ctx, lis2dtw12_odr_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_data_rate_get(stmdev_ctx_t *ctx, lis2dtw12_odr_t *val)
+int32_t lis2dtw12_data_rate_get(stmdev_ctx_t *ctx,
+ lis2dtw12_odr_t *val)
{
lis2dtw12_ctrl1_t ctrl1;
lis2dtw12_ctrl3_t ctrl3;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL1,(uint8_t*) &ctrl1, 1);
- if (ret == 0) {
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3,(uint8_t*) &ctrl3, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL1, (uint8_t *) &ctrl1, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) &ctrl3, 1);
- switch ((ctrl3.slp_mode << 4) + ctrl1.odr) {
+ switch ((ctrl3.slp_mode << 4) + ctrl1.odr)
+ {
case LIS2DTW12_XL_ODR_OFF:
*val = LIS2DTW12_XL_ODR_OFF;
break;
+
case LIS2DTW12_XL_ODR_1Hz6_LP_ONLY:
*val = LIS2DTW12_XL_ODR_1Hz6_LP_ONLY;
break;
+
case LIS2DTW12_XL_ODR_12Hz5:
*val = LIS2DTW12_XL_ODR_12Hz5;
break;
+
case LIS2DTW12_XL_ODR_25Hz:
*val = LIS2DTW12_XL_ODR_25Hz;
break;
- case LIS2DTW12_XL_ODR_50Hz:
+
+ case LIS2DTW12_XL_ODR_50Hz:
*val = LIS2DTW12_XL_ODR_50Hz;
break;
+
case LIS2DTW12_XL_ODR_100Hz:
*val = LIS2DTW12_XL_ODR_100Hz;
break;
+
case LIS2DTW12_XL_ODR_200Hz:
*val = LIS2DTW12_XL_ODR_200Hz;
break;
+
case LIS2DTW12_XL_ODR_400Hz:
*val = LIS2DTW12_XL_ODR_400Hz;
break;
- case LIS2DTW12_XL_ODR_800Hz:
+
+ case LIS2DTW12_XL_ODR_800Hz:
*val = LIS2DTW12_XL_ODR_800Hz;
break;
+
case LIS2DTW12_XL_ODR_1k6Hz:
*val = LIS2DTW12_XL_ODR_1k6Hz;
break;
+
case LIS2DTW12_XL_SET_SW_TRIG:
*val = LIS2DTW12_XL_SET_SW_TRIG;
break;
+
case LIS2DTW12_XL_SET_PIN_TRIG:
*val = LIS2DTW12_XL_SET_PIN_TRIG;
break;
+
default:
*val = LIS2DTW12_XL_ODR_OFF;
break;
}
}
+
return ret;
}
@@ -356,16 +418,20 @@ int32_t lis2dtw12_data_rate_get(stmdev_ctx_t *ctx, lis2dtw12_odr_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lis2dtw12_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lis2dtw12_ctrl2_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.bdu = val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL2,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -377,12 +443,13 @@ int32_t lis2dtw12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2dtw12_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2dtw12_ctrl2_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
*val = reg.bdu;
return ret;
@@ -396,16 +463,20 @@ int32_t lis2dtw12_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_full_scale_set(stmdev_ctx_t *ctx, lis2dtw12_fs_t val)
+int32_t lis2dtw12_full_scale_set(stmdev_ctx_t *ctx,
+ lis2dtw12_fs_t val)
{
lis2dtw12_ctrl6_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL6,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL6, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.fs = (uint8_t) val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL6,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL6, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -417,30 +488,37 @@ int32_t lis2dtw12_full_scale_set(stmdev_ctx_t *ctx, lis2dtw12_fs_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_full_scale_get(stmdev_ctx_t *ctx, lis2dtw12_fs_t *val)
+int32_t lis2dtw12_full_scale_get(stmdev_ctx_t *ctx,
+ lis2dtw12_fs_t *val)
{
lis2dtw12_ctrl6_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL6,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL6, (uint8_t *) ®, 1);
- switch (reg.fs) {
+ switch (reg.fs)
+ {
case LIS2DTW12_2g:
*val = LIS2DTW12_2g;
break;
+
case LIS2DTW12_4g:
*val = LIS2DTW12_4g;
break;
+
case LIS2DTW12_8g:
*val = LIS2DTW12_8g;
break;
+
case LIS2DTW12_16g:
*val = LIS2DTW12_16g;
break;
+
default:
*val = LIS2DTW12_2g;
break;
}
+
return ret;
}
@@ -452,10 +530,13 @@ int32_t lis2dtw12_full_scale_get(stmdev_ctx_t *ctx, lis2dtw12_fs_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_status_reg_get(stmdev_ctx_t *ctx, lis2dtw12_status_t *val)
+int32_t lis2dtw12_status_reg_get(stmdev_ctx_t *ctx,
+ lis2dtw12_status_t *val)
{
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_STATUS, (uint8_t*) val, 1);
+
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_STATUS, (uint8_t *) val, 1);
+
return ret;
}
@@ -472,7 +553,7 @@ int32_t lis2dtw12_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dtw12_status_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_STATUS,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_STATUS, (uint8_t *) ®, 1);
*val = reg.drdy;
return ret;
@@ -490,7 +571,10 @@ int32_t lis2dtw12_all_sources_get(stmdev_ctx_t *ctx,
lis2dtw12_all_sources_t *val)
{
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_STATUS_DUP, (uint8_t*) val, 5);
+
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_STATUS_DUP, (uint8_t *) val,
+ 5);
+
return ret;
}
@@ -507,7 +591,9 @@ int32_t lis2dtw12_all_sources_get(stmdev_ctx_t *ctx,
int32_t lis2dtw12_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis2dtw12_write_reg(ctx, LIS2DTW12_X_OFS_USR, buff, 1);
+
return ret;
}
@@ -524,7 +610,9 @@ int32_t lis2dtw12_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lis2dtw12_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis2dtw12_read_reg(ctx, LIS2DTW12_X_OFS_USR, buff, 1);
+
return ret;
}
@@ -541,7 +629,9 @@ int32_t lis2dtw12_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lis2dtw12_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis2dtw12_write_reg(ctx, LIS2DTW12_Y_OFS_USR, buff, 1);
+
return ret;
}
@@ -558,7 +648,9 @@ int32_t lis2dtw12_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lis2dtw12_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis2dtw12_read_reg(ctx, LIS2DTW12_Y_OFS_USR, buff, 1);
+
return ret;
}
@@ -575,7 +667,9 @@ int32_t lis2dtw12_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lis2dtw12_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis2dtw12_write_reg(ctx, LIS2DTW12_Z_OFS_USR, buff, 1);
+
return ret;
}
@@ -592,7 +686,9 @@ int32_t lis2dtw12_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lis2dtw12_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis2dtw12_read_reg(ctx, LIS2DTW12_Z_OFS_USR, buff, 1);
+
return ret;
}
@@ -607,16 +703,19 @@ int32_t lis2dtw12_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
*/
int32_t lis2dtw12_offset_weight_set(stmdev_ctx_t *ctx,
- lis2dtw12_usr_off_w_t val)
+ lis2dtw12_usr_off_w_t val)
{
lis2dtw12_ctrl_reg7_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.usr_off_w = (uint8_t) val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL_REG7,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -630,23 +729,28 @@ int32_t lis2dtw12_offset_weight_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis2dtw12_offset_weight_get(stmdev_ctx_t *ctx,
- lis2dtw12_usr_off_w_t *val)
+ lis2dtw12_usr_off_w_t *val)
{
lis2dtw12_ctrl_reg7_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7,(uint8_t*) ®, 1);
- switch (reg.usr_off_w) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
+
+ switch (reg.usr_off_w)
+ {
case LIS2DTW12_LSb_977ug:
*val = LIS2DTW12_LSb_977ug;
break;
+
case LIS2DTW12_LSb_15mg6:
*val = LIS2DTW12_LSb_15mg6;
break;
+
default:
*val = LIS2DTW12_LSb_977ug;
break;
}
+
return ret;
}
@@ -678,7 +782,7 @@ int32_t lis2dtw12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
ret = lis2dtw12_read_reg(ctx, LIS2DTW12_OUT_T_L, buff, 2);
*val = (int16_t)buff[1];
- *val = (*val * 256) + (int16_t)buff[0];
+ *val = (*val * 256) + (int16_t)buff[0];
return ret;
}
@@ -692,18 +796,19 @@ int32_t lis2dtw12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
+int32_t lis2dtw12_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
{
uint8_t buff[6];
int32_t ret;
ret = lis2dtw12_read_reg(ctx, LIS2DTW12_OUT_X_L, buff, 6);
val[0] = (int16_t)buff[1];
- val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
- val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
val[2] = (int16_t)buff[5];
- val[2] = (val[2] * 256) + (int16_t)buff[4];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
return ret;
}
@@ -731,7 +836,9 @@ int32_t lis2dtw12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
int32_t lis2dtw12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -749,11 +856,14 @@ int32_t lis2dtw12_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dtw12_ctrl2_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.if_add_inc = val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL2,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -771,7 +881,7 @@ int32_t lis2dtw12_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dtw12_ctrl2_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
*val = reg.if_add_inc;
return ret;
@@ -790,10 +900,12 @@ int32_t lis2dtw12_reset_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dtw12_ctrl2_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.soft_reset = val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL2,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
}
return ret;
@@ -812,7 +924,7 @@ int32_t lis2dtw12_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dtw12_ctrl2_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
*val = reg.soft_reset;
return ret;
@@ -831,11 +943,14 @@ int32_t lis2dtw12_boot_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dtw12_ctrl2_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.boot = val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL2,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -852,7 +967,7 @@ int32_t lis2dtw12_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dtw12_ctrl2_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
*val = reg.boot;
return ret;
@@ -871,10 +986,12 @@ int32_t lis2dtw12_self_test_set(stmdev_ctx_t *ctx, lis2dtw12_st_t val)
lis2dtw12_ctrl3_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.st = (uint8_t) val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL3,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) ®, 1);
}
return ret;
@@ -888,27 +1005,33 @@ int32_t lis2dtw12_self_test_set(stmdev_ctx_t *ctx, lis2dtw12_st_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_self_test_get(stmdev_ctx_t *ctx, lis2dtw12_st_t *val)
+int32_t lis2dtw12_self_test_get(stmdev_ctx_t *ctx,
+ lis2dtw12_st_t *val)
{
lis2dtw12_ctrl3_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) ®, 1);
- switch (reg.st) {
+ switch (reg.st)
+ {
case LIS2DTW12_XL_ST_DISABLE:
*val = LIS2DTW12_XL_ST_DISABLE;
break;
+
case LIS2DTW12_XL_ST_POSITIVE:
*val = LIS2DTW12_XL_ST_POSITIVE;
break;
+
case LIS2DTW12_XL_ST_NEGATIVE:
*val = LIS2DTW12_XL_ST_NEGATIVE;
break;
+
default:
*val = LIS2DTW12_XL_ST_DISABLE;
break;
}
+
return ret;
}
@@ -921,15 +1044,17 @@ int32_t lis2dtw12_self_test_get(stmdev_ctx_t *ctx, lis2dtw12_st_t *val)
*
*/
int32_t lis2dtw12_data_ready_mode_set(stmdev_ctx_t *ctx,
- lis2dtw12_drdy_pulsed_t val)
+ lis2dtw12_drdy_pulsed_t val)
{
lis2dtw12_ctrl_reg7_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.drdy_pulsed = (uint8_t) val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL_REG7,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
}
return ret;
@@ -944,24 +1069,28 @@ int32_t lis2dtw12_data_ready_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis2dtw12_data_ready_mode_get(stmdev_ctx_t *ctx,
- lis2dtw12_drdy_pulsed_t *val)
+ lis2dtw12_drdy_pulsed_t *val)
{
lis2dtw12_ctrl_reg7_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
- switch (reg.drdy_pulsed) {
+ switch (reg.drdy_pulsed)
+ {
case LIS2DTW12_DRDY_LATCHED:
*val = LIS2DTW12_DRDY_LATCHED;
break;
+
case LIS2DTW12_DRDY_PULSED:
*val = LIS2DTW12_DRDY_PULSED;
break;
+
default:
*val = LIS2DTW12_DRDY_LATCHED;
break;
}
+
return ret;
}
@@ -986,23 +1115,32 @@ int32_t lis2dtw12_data_ready_mode_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_filter_path_set(stmdev_ctx_t *ctx, lis2dtw12_fds_t val)
+int32_t lis2dtw12_filter_path_set(stmdev_ctx_t *ctx,
+ lis2dtw12_fds_t val)
{
lis2dtw12_ctrl6_t ctrl6;
lis2dtw12_ctrl_reg7_t ctrl_reg7;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL6,(uint8_t*) &ctrl6, 1);
- if (ret == 0) {
- ctrl6.fds = ( (uint8_t) val & 0x10U ) >> 4;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL6,(uint8_t*) &ctrl6, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL6, (uint8_t *) &ctrl6, 1);
+
+ if (ret == 0)
+ {
+ ctrl6.fds = ((uint8_t) val & 0x10U) >> 4;
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL6, (uint8_t *) &ctrl6, 1);
}
- if (ret == 0) {
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7,(uint8_t*) &ctrl_reg7, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7,
+ (uint8_t *) &ctrl_reg7, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ctrl_reg7.usr_off_on_out = (uint8_t) val & 0x01U;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL_REG7,(uint8_t*) &ctrl_reg7, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL_REG7,
+ (uint8_t *) &ctrl_reg7, 1);
}
return ret;
@@ -1016,31 +1154,40 @@ int32_t lis2dtw12_filter_path_set(stmdev_ctx_t *ctx, lis2dtw12_fds_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_filter_path_get(stmdev_ctx_t *ctx, lis2dtw12_fds_t *val)
+int32_t lis2dtw12_filter_path_get(stmdev_ctx_t *ctx,
+ lis2dtw12_fds_t *val)
{
lis2dtw12_ctrl6_t ctrl6;
lis2dtw12_ctrl_reg7_t ctrl_reg7;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL6,(uint8_t*) &ctrl6, 1);
- if (ret == 0) {
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7,(uint8_t*) &ctrl_reg7, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL6, (uint8_t *) &ctrl6, 1);
- switch ((ctrl6.fds << 4 ) + ctrl_reg7.usr_off_on_out) {
+ if (ret == 0)
+ {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7,
+ (uint8_t *) &ctrl_reg7, 1);
+
+ switch ((ctrl6.fds << 4) + ctrl_reg7.usr_off_on_out)
+ {
case LIS2DTW12_LPF_ON_OUT:
*val = LIS2DTW12_LPF_ON_OUT;
break;
+
case LIS2DTW12_USER_OFFSET_ON_OUT:
*val = LIS2DTW12_USER_OFFSET_ON_OUT;
break;
+
case LIS2DTW12_HIGH_PASS_ON_OUT:
*val = LIS2DTW12_HIGH_PASS_ON_OUT;
break;
+
default:
*val = LIS2DTW12_LPF_ON_OUT;
break;
}
}
+
return ret;
}
@@ -1054,15 +1201,17 @@ int32_t lis2dtw12_filter_path_get(stmdev_ctx_t *ctx, lis2dtw12_fds_t *val)
*
*/
int32_t lis2dtw12_filter_bandwidth_set(stmdev_ctx_t *ctx,
- lis2dtw12_bw_filt_t val)
+ lis2dtw12_bw_filt_t val)
{
lis2dtw12_ctrl6_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL6,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL6, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.bw_filt = (uint8_t) val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL6,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL6, (uint8_t *) ®, 1);
}
return ret;
@@ -1078,30 +1227,36 @@ int32_t lis2dtw12_filter_bandwidth_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis2dtw12_filter_bandwidth_get(stmdev_ctx_t *ctx,
- lis2dtw12_bw_filt_t *val)
+ lis2dtw12_bw_filt_t *val)
{
lis2dtw12_ctrl6_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL6,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL6, (uint8_t *) ®, 1);
- switch (reg.bw_filt) {
+ switch (reg.bw_filt)
+ {
case LIS2DTW12_ODR_DIV_2:
*val = LIS2DTW12_ODR_DIV_2;
break;
+
case LIS2DTW12_ODR_DIV_4:
*val = LIS2DTW12_ODR_DIV_4;
break;
+
case LIS2DTW12_ODR_DIV_10:
*val = LIS2DTW12_ODR_DIV_10;
break;
+
case LIS2DTW12_ODR_DIV_20:
*val = LIS2DTW12_ODR_DIV_20;
break;
+
default:
*val = LIS2DTW12_ODR_DIV_2;
break;
}
+
return ret;
}
@@ -1118,11 +1273,14 @@ int32_t lis2dtw12_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dtw12_ctrl_reg7_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.hp_ref_mode = val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL_REG7,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1139,7 +1297,7 @@ int32_t lis2dtw12_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dtw12_ctrl_reg7_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
*val = reg.hp_ref_mode;
return ret;
@@ -1171,11 +1329,14 @@ int32_t lis2dtw12_spi_mode_set(stmdev_ctx_t *ctx, lis2dtw12_sim_t val)
lis2dtw12_ctrl2_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.sim = (uint8_t) val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL2,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1187,24 +1348,29 @@ int32_t lis2dtw12_spi_mode_set(stmdev_ctx_t *ctx, lis2dtw12_sim_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_spi_mode_get(stmdev_ctx_t *ctx, lis2dtw12_sim_t *val)
+int32_t lis2dtw12_spi_mode_get(stmdev_ctx_t *ctx,
+ lis2dtw12_sim_t *val)
{
lis2dtw12_ctrl2_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
- switch (reg.sim) {
+ switch (reg.sim)
+ {
case LIS2DTW12_SPI_4_WIRE:
*val = LIS2DTW12_SPI_4_WIRE;
break;
+
case LIS2DTW12_SPI_3_WIRE:
*val = LIS2DTW12_SPI_3_WIRE;
break;
+
default:
*val = LIS2DTW12_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -1218,16 +1384,19 @@ int32_t lis2dtw12_spi_mode_get(stmdev_ctx_t *ctx, lis2dtw12_sim_t *val)
*
*/
int32_t lis2dtw12_i2c_interface_set(stmdev_ctx_t *ctx,
- lis2dtw12_i2c_disable_t val)
+ lis2dtw12_i2c_disable_t val)
{
lis2dtw12_ctrl2_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.i2c_disable = (uint8_t) val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL2,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1240,24 +1409,28 @@ int32_t lis2dtw12_i2c_interface_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis2dtw12_i2c_interface_get(stmdev_ctx_t *ctx,
- lis2dtw12_i2c_disable_t *val)
+ lis2dtw12_i2c_disable_t *val)
{
lis2dtw12_ctrl2_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
- switch (reg.i2c_disable) {
+ switch (reg.i2c_disable)
+ {
case LIS2DTW12_I2C_ENABLE:
*val = LIS2DTW12_I2C_ENABLE;
break;
+
case LIS2DTW12_I2C_DISABLE:
*val = LIS2DTW12_I2C_DISABLE;
break;
+
default:
*val = LIS2DTW12_I2C_ENABLE;
break;
}
+
return ret;
}
@@ -1269,16 +1442,20 @@ int32_t lis2dtw12_i2c_interface_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_cs_mode_set(stmdev_ctx_t *ctx, lis2dtw12_cs_pu_disc_t val)
+int32_t lis2dtw12_cs_mode_set(stmdev_ctx_t *ctx,
+ lis2dtw12_cs_pu_disc_t val)
{
lis2dtw12_ctrl2_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.cs_pu_disc = (uint8_t) val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL2,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1290,24 +1467,29 @@ int32_t lis2dtw12_cs_mode_set(stmdev_ctx_t *ctx, lis2dtw12_cs_pu_disc_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_cs_mode_get(stmdev_ctx_t *ctx, lis2dtw12_cs_pu_disc_t *val)
+int32_t lis2dtw12_cs_mode_get(stmdev_ctx_t *ctx,
+ lis2dtw12_cs_pu_disc_t *val)
{
lis2dtw12_ctrl2_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
- switch (reg.cs_pu_disc) {
+ switch (reg.cs_pu_disc)
+ {
case LIS2DTW12_PULL_UP_CONNECT:
*val = LIS2DTW12_PULL_UP_CONNECT;
break;
+
case LIS2DTW12_PULL_UP_DISCONNECT:
*val = LIS2DTW12_PULL_UP_DISCONNECT;
break;
+
default:
*val = LIS2DTW12_PULL_UP_CONNECT;
break;
}
+
return ret;
}
@@ -1332,16 +1514,19 @@ int32_t lis2dtw12_cs_mode_get(stmdev_ctx_t *ctx, lis2dtw12_cs_pu_disc_t *val)
*
*/
int32_t lis2dtw12_pin_polarity_set(stmdev_ctx_t *ctx,
- lis2dtw12_h_lactive_t val)
+ lis2dtw12_h_lactive_t val)
{
lis2dtw12_ctrl3_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.h_lactive = (uint8_t) val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL3,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1354,24 +1539,28 @@ int32_t lis2dtw12_pin_polarity_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis2dtw12_pin_polarity_get(stmdev_ctx_t *ctx,
- lis2dtw12_h_lactive_t *val)
+ lis2dtw12_h_lactive_t *val)
{
lis2dtw12_ctrl3_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) ®, 1);
- switch (reg.h_lactive) {
+ switch (reg.h_lactive)
+ {
case LIS2DTW12_ACTIVE_HIGH:
*val = LIS2DTW12_ACTIVE_HIGH;
break;
+
case LIS2DTW12_ACTIVE_LOW:
*val = LIS2DTW12_ACTIVE_LOW;
break;
+
default:
*val = LIS2DTW12_ACTIVE_HIGH;
break;
}
+
return ret;
}
@@ -1384,16 +1573,19 @@ int32_t lis2dtw12_pin_polarity_get(stmdev_ctx_t *ctx,
*
*/
int32_t lis2dtw12_int_notification_set(stmdev_ctx_t *ctx,
- lis2dtw12_lir_t val)
+ lis2dtw12_lir_t val)
{
lis2dtw12_ctrl3_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.lir = (uint8_t) val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL3,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1406,24 +1598,28 @@ int32_t lis2dtw12_int_notification_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis2dtw12_int_notification_get(stmdev_ctx_t *ctx,
- lis2dtw12_lir_t *val)
+ lis2dtw12_lir_t *val)
{
lis2dtw12_ctrl3_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) ®, 1);
- switch (reg.lir) {
+ switch (reg.lir)
+ {
case LIS2DTW12_INT_PULSED:
*val = LIS2DTW12_INT_PULSED;
break;
+
case LIS2DTW12_INT_LATCHED:
*val = LIS2DTW12_INT_LATCHED;
break;
+
default:
*val = LIS2DTW12_INT_PULSED;
break;
}
+
return ret;
}
@@ -1435,16 +1631,20 @@ int32_t lis2dtw12_int_notification_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_pin_mode_set(stmdev_ctx_t *ctx, lis2dtw12_pp_od_t val)
+int32_t lis2dtw12_pin_mode_set(stmdev_ctx_t *ctx,
+ lis2dtw12_pp_od_t val)
{
lis2dtw12_ctrl3_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.pp_od = (uint8_t) val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL3,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1456,24 +1656,29 @@ int32_t lis2dtw12_pin_mode_set(stmdev_ctx_t *ctx, lis2dtw12_pp_od_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_pin_mode_get(stmdev_ctx_t *ctx, lis2dtw12_pp_od_t *val)
+int32_t lis2dtw12_pin_mode_get(stmdev_ctx_t *ctx,
+ lis2dtw12_pp_od_t *val)
{
lis2dtw12_ctrl3_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) ®, 1);
- switch (reg.pp_od) {
+ switch (reg.pp_od)
+ {
case LIS2DTW12_PUSH_PULL:
*val = LIS2DTW12_PUSH_PULL;
break;
+
case LIS2DTW12_OPEN_DRAIN:
*val = LIS2DTW12_OPEN_DRAIN;
break;
+
default:
*val = LIS2DTW12_PUSH_PULL;
break;
}
+
return ret;
}
@@ -1486,26 +1691,36 @@ int32_t lis2dtw12_pin_mode_get(stmdev_ctx_t *ctx, lis2dtw12_pp_od_t *val)
*
*/
int32_t lis2dtw12_pin_int1_route_set(stmdev_ctx_t *ctx,
- lis2dtw12_ctrl4_int1_pad_ctrl_t *val)
+ lis2dtw12_ctrl4_int1_pad_ctrl_t *val)
{
lis2dtw12_ctrl_reg7_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7,(uint8_t*) ®, 1);
- if (ret == 0) {
- if ((val->int1_tap | val->int1_ff | val->int1_wu | val->int1_single_tap |
- val->int1_6d) != PROPERTY_DISABLE){
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ if ((val->int1_tap | val->int1_ff | val->int1_wu |
+ val->int1_single_tap |
+ val->int1_6d) != PROPERTY_DISABLE)
+ {
reg.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
reg.interrupts_enable = PROPERTY_DISABLE;
}
ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL4_INT1_PAD_CTRL,
- (uint8_t*) val, 1);
- } if (ret == 0) {
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL_REG7,(uint8_t*) ®, 1);
+ (uint8_t *) val, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1518,11 +1733,13 @@ int32_t lis2dtw12_pin_int1_route_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis2dtw12_pin_int1_route_get(stmdev_ctx_t *ctx,
- lis2dtw12_ctrl4_int1_pad_ctrl_t *val)
+ lis2dtw12_ctrl4_int1_pad_ctrl_t *val)
{
int32_t ret;
+
ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL4_INT1_PAD_CTRL,
- (uint8_t*) val, 1);
+ (uint8_t *) val, 1);
+
return ret;
}
@@ -1535,25 +1752,33 @@ int32_t lis2dtw12_pin_int1_route_get(stmdev_ctx_t *ctx,
*
*/
int32_t lis2dtw12_pin_int2_route_set(stmdev_ctx_t *ctx,
- lis2dtw12_ctrl5_int2_pad_ctrl_t *val)
+ lis2dtw12_ctrl5_int2_pad_ctrl_t *val)
{
lis2dtw12_ctrl_reg7_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7,(uint8_t*) ®, 1);
- if (ret == 0) {
- if ((val->int2_sleep_state | val->int2_sleep_chg ) != PROPERTY_DISABLE) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ if ((val->int2_sleep_state | val->int2_sleep_chg) !=
+ PROPERTY_DISABLE)
+ {
reg.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
reg.interrupts_enable = PROPERTY_DISABLE;
}
ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL5_INT2_PAD_CTRL,
- (uint8_t*) val, 1);
+ (uint8_t *) val, 1);
}
- if (ret == 0) {
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL_REG7,(uint8_t*) ®, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
}
return ret;
@@ -1568,11 +1793,13 @@ int32_t lis2dtw12_pin_int2_route_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis2dtw12_pin_int2_route_get(stmdev_ctx_t *ctx,
- lis2dtw12_ctrl5_int2_pad_ctrl_t *val)
+ lis2dtw12_ctrl5_int2_pad_ctrl_t *val)
{
int32_t ret;
+
ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL5_INT2_PAD_CTRL,
- (uint8_t*) val, 1);
+ (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1588,11 +1815,14 @@ int32_t lis2dtw12_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dtw12_ctrl_reg7_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.int2_on_int1 = val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL_REG7,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1609,7 +1839,7 @@ int32_t lis2dtw12_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dtw12_ctrl_reg7_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
*val = reg.int2_on_int1;
return ret;
@@ -1641,11 +1871,15 @@ int32_t lis2dtw12_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dtw12_wake_up_ths_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_THS,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_THS, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.wk_ths = val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_WAKE_UP_THS,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_WAKE_UP_THS,
+ (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1662,7 +1896,7 @@ int32_t lis2dtw12_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dtw12_wake_up_ths_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_THS,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_THS, (uint8_t *) ®, 1);
*val = reg.wk_ths;
return ret;
@@ -1681,11 +1915,15 @@ int32_t lis2dtw12_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dtw12_wake_up_dur_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_DUR,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.wake_dur = val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_WAKE_UP_DUR,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_WAKE_UP_DUR,
+ (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1702,7 +1940,7 @@ int32_t lis2dtw12_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dtw12_wake_up_dur_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_DUR,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
*val = reg.wake_dur;
return ret;
@@ -1717,16 +1955,19 @@ int32_t lis2dtw12_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lis2dtw12_wkup_feed_data_set(stmdev_ctx_t *ctx,
- lis2dtw12_usr_off_on_wu_t val)
+ lis2dtw12_usr_off_on_wu_t val)
{
lis2dtw12_ctrl_reg7_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.usr_off_on_wu = (uint8_t) val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL_REG7,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1739,24 +1980,28 @@ int32_t lis2dtw12_wkup_feed_data_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis2dtw12_wkup_feed_data_get(stmdev_ctx_t *ctx,
- lis2dtw12_usr_off_on_wu_t *val)
+ lis2dtw12_usr_off_on_wu_t *val)
{
lis2dtw12_ctrl_reg7_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
- switch (reg.usr_off_on_wu) {
+ switch (reg.usr_off_on_wu)
+ {
case LIS2DTW12_HP_FEED:
*val = LIS2DTW12_HP_FEED;
break;
+
case LIS2DTW12_USER_OFFSET_FEED:
*val = LIS2DTW12_USER_OFFSET_FEED;
break;
+
default:
*val = LIS2DTW12_HP_FEED;
break;
}
+
return ret;
}
@@ -1783,23 +2028,34 @@ int32_t lis2dtw12_wkup_feed_data_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_act_mode_set(stmdev_ctx_t *ctx, lis2dtw12_sleep_on_t val)
+int32_t lis2dtw12_act_mode_set(stmdev_ctx_t *ctx,
+ lis2dtw12_sleep_on_t val)
{
lis2dtw12_wake_up_ths_t wake_up_ths;
lis2dtw12_wake_up_dur_t wake_up_dur;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_THS,(uint8_t*) &wake_up_ths, 1);
- if (ret == 0) {
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_THS,
+ (uint8_t *) &wake_up_ths, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_DUR,
+ (uint8_t *) &wake_up_dur, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
wake_up_ths.sleep_on = (uint8_t) val & 0x01U;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_WAKE_UP_THS,(uint8_t*) &wake_up_ths, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_WAKE_UP_THS,
+ (uint8_t *) &wake_up_ths, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
wake_up_dur.stationary = ((uint8_t)val & 0x02U) >> 1;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_WAKE_UP_DUR,
+ (uint8_t *) &wake_up_dur, 1);
}
return ret;
@@ -1814,31 +2070,41 @@ int32_t lis2dtw12_act_mode_set(stmdev_ctx_t *ctx, lis2dtw12_sleep_on_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_act_mode_get(stmdev_ctx_t *ctx, lis2dtw12_sleep_on_t *val)
+int32_t lis2dtw12_act_mode_get(stmdev_ctx_t *ctx,
+ lis2dtw12_sleep_on_t *val)
{
lis2dtw12_wake_up_ths_t wake_up_ths;
lis2dtw12_wake_up_dur_t wake_up_dur;;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_THS,(uint8_t*) &wake_up_ths, 1);
- if (ret == 0) {
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_THS,
+ (uint8_t *) &wake_up_ths, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_DUR,
+ (uint8_t *) &wake_up_dur, 1);
- switch ((wake_up_dur.stationary << 1) + wake_up_ths.sleep_on){
+ switch ((wake_up_dur.stationary << 1) + wake_up_ths.sleep_on)
+ {
case LIS2DTW12_NO_DETECTION:
*val = LIS2DTW12_NO_DETECTION;
break;
+
case LIS2DTW12_DETECT_ACT_INACT:
*val = LIS2DTW12_DETECT_ACT_INACT;
break;
+
case LIS2DTW12_DETECT_STAT_MOTION:
*val = LIS2DTW12_DETECT_STAT_MOTION;
break;
+
default:
*val = LIS2DTW12_NO_DETECTION;
break;
}
}
+
return ret;
}
@@ -1855,11 +2121,15 @@ int32_t lis2dtw12_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dtw12_wake_up_dur_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_DUR,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.sleep_dur = val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_WAKE_UP_DUR,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_WAKE_UP_DUR,
+ (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1876,7 +2146,7 @@ int32_t lis2dtw12_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dtw12_wake_up_dur_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_DUR,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
*val = reg.sleep_dur;
return ret;
@@ -1908,11 +2178,14 @@ int32_t lis2dtw12_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dtw12_tap_ths_x_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_X,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_X, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.tap_thsx = val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_TAP_THS_X,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_TAP_THS_X, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1929,7 +2202,7 @@ int32_t lis2dtw12_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dtw12_tap_ths_x_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_X,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_X, (uint8_t *) ®, 1);
*val = reg.tap_thsx;
return ret;
@@ -1948,11 +2221,14 @@ int32_t lis2dtw12_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dtw12_tap_ths_y_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Y,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Y, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.tap_thsy = val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_TAP_THS_Y,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_TAP_THS_Y, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1969,7 +2245,7 @@ int32_t lis2dtw12_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dtw12_tap_ths_y_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Y,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Y, (uint8_t *) ®, 1);
*val = reg.tap_thsy;
return ret;
@@ -1984,16 +2260,19 @@ int32_t lis2dtw12_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lis2dtw12_tap_axis_priority_set(stmdev_ctx_t *ctx,
- lis2dtw12_tap_prior_t val)
+ lis2dtw12_tap_prior_t val)
{
lis2dtw12_tap_ths_y_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Y,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Y, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.tap_prior = (uint8_t) val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_TAP_THS_Y,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_TAP_THS_Y, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -2006,36 +2285,44 @@ int32_t lis2dtw12_tap_axis_priority_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis2dtw12_tap_axis_priority_get(stmdev_ctx_t *ctx,
- lis2dtw12_tap_prior_t *val)
+ lis2dtw12_tap_prior_t *val)
{
lis2dtw12_tap_ths_y_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Y,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Y, (uint8_t *) ®, 1);
- switch (reg.tap_prior) {
+ switch (reg.tap_prior)
+ {
case LIS2DTW12_XYZ:
*val = LIS2DTW12_XYZ;
break;
+
case LIS2DTW12_YXZ:
*val = LIS2DTW12_YXZ;
break;
+
case LIS2DTW12_XZY:
*val = LIS2DTW12_XZY;
break;
+
case LIS2DTW12_ZYX:
*val = LIS2DTW12_ZYX;
break;
+
case LIS2DTW12_YZX:
*val = LIS2DTW12_YZX;
break;
+
case LIS2DTW12_ZXY:
*val = LIS2DTW12_ZXY;
break;
+
default:
*val = LIS2DTW12_XYZ;
break;
}
+
return ret;
}
@@ -2052,10 +2339,12 @@ int32_t lis2dtw12_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dtw12_tap_ths_z_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Z,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Z, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.tap_thsz = val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_TAP_THS_Z,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_TAP_THS_Z, (uint8_t *) ®, 1);
}
return ret;
@@ -2074,7 +2363,7 @@ int32_t lis2dtw12_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dtw12_tap_ths_z_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Z,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Z, (uint8_t *) ®, 1);
*val = reg.tap_thsz;
return ret;
@@ -2088,16 +2377,20 @@ int32_t lis2dtw12_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lis2dtw12_tap_detection_on_z_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lis2dtw12_tap_ths_z_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Z,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Z, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.tap_z_en = val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_TAP_THS_Z,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_TAP_THS_Z, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -2109,12 +2402,13 @@ int32_t lis2dtw12_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2dtw12_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2dtw12_tap_ths_z_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Z,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Z, (uint8_t *) ®, 1);
*val = reg.tap_z_en;
return ret;
@@ -2128,16 +2422,20 @@ int32_t lis2dtw12_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lis2dtw12_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lis2dtw12_tap_ths_z_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Z,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Z, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.tap_y_en = val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_TAP_THS_Z,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_TAP_THS_Z, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -2149,12 +2447,13 @@ int32_t lis2dtw12_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2dtw12_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2dtw12_tap_ths_z_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Z,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Z, (uint8_t *) ®, 1);
*val = reg.tap_y_en;
return ret;
@@ -2168,16 +2467,20 @@ int32_t lis2dtw12_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lis2dtw12_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lis2dtw12_tap_ths_z_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Z,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Z, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.tap_x_en = val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_TAP_THS_Z,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_TAP_THS_Z, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -2189,12 +2492,13 @@ int32_t lis2dtw12_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2dtw12_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2dtw12_tap_ths_z_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Z,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Z, (uint8_t *) ®, 1);
*val = reg.tap_x_en;
return ret;
@@ -2217,10 +2521,12 @@ int32_t lis2dtw12_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dtw12_int_dur_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_INT_DUR,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_INT_DUR, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.shock = val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_INT_DUR,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_INT_DUR, (uint8_t *) ®, 1);
}
return ret;
@@ -2243,7 +2549,7 @@ int32_t lis2dtw12_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dtw12_int_dur_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_INT_DUR,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_INT_DUR, (uint8_t *) ®, 1);
*val = reg.shock;
return ret;
@@ -2266,11 +2572,14 @@ int32_t lis2dtw12_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dtw12_int_dur_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_INT_DUR,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_INT_DUR, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.quiet = val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_INT_DUR,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_INT_DUR, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -2291,7 +2600,7 @@ int32_t lis2dtw12_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dtw12_int_dur_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_INT_DUR,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_INT_DUR, (uint8_t *) ®, 1);
*val = reg.quiet;
return ret;
@@ -2315,11 +2624,14 @@ int32_t lis2dtw12_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dtw12_int_dur_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_INT_DUR,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_INT_DUR, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.latency = val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_INT_DUR,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_INT_DUR, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -2341,7 +2653,7 @@ int32_t lis2dtw12_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dtw12_int_dur_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_INT_DUR,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_INT_DUR, (uint8_t *) ®, 1);
*val = reg.latency;
return ret;
@@ -2356,16 +2668,20 @@ int32_t lis2dtw12_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lis2dtw12_tap_mode_set(stmdev_ctx_t *ctx,
- lis2dtw12_single_double_tap_t val)
+ lis2dtw12_single_double_tap_t val)
{
lis2dtw12_wake_up_ths_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_THS,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_THS, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.single_double_tap = (uint8_t) val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_WAKE_UP_THS,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_WAKE_UP_THS,
+ (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -2378,20 +2694,23 @@ int32_t lis2dtw12_tap_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis2dtw12_tap_mode_get(stmdev_ctx_t *ctx,
- lis2dtw12_single_double_tap_t *val)
+ lis2dtw12_single_double_tap_t *val)
{
lis2dtw12_wake_up_ths_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_THS,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_THS, (uint8_t *) ®, 1);
- switch (reg.single_double_tap) {
+ switch (reg.single_double_tap)
+ {
case LIS2DTW12_ONLY_SINGLE:
*val = LIS2DTW12_ONLY_SINGLE;
break;
+
case LIS2DTW12_BOTH_SINGLE_DOUBLE:
*val = LIS2DTW12_BOTH_SINGLE_DOUBLE;
break;
+
default:
*val = LIS2DTW12_ONLY_SINGLE;
break;
@@ -2408,10 +2727,13 @@ int32_t lis2dtw12_tap_mode_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_tap_src_get(stmdev_ctx_t *ctx, lis2dtw12_tap_src_t *val)
+int32_t lis2dtw12_tap_src_get(stmdev_ctx_t *ctx,
+ lis2dtw12_tap_src_t *val)
{
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_SRC, (uint8_t*) val, 1);
+
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_SRC, (uint8_t *) val, 1);
+
return ret;
}
@@ -2441,11 +2763,14 @@ int32_t lis2dtw12_6d_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dtw12_tap_ths_x_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_X,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_X, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg._6d_ths = val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_TAP_THS_X,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_TAP_THS_X, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -2462,7 +2787,7 @@ int32_t lis2dtw12_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dtw12_tap_ths_x_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_X,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_X, (uint8_t *) ®, 1);
*val = reg._6d_ths;
return ret;
@@ -2481,10 +2806,12 @@ int32_t lis2dtw12_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dtw12_tap_ths_x_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_X,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_X, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg._4d_en = val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_TAP_THS_X,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_TAP_THS_X, (uint8_t *) ®, 1);
}
return ret;
@@ -2503,7 +2830,7 @@ int32_t lis2dtw12_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dtw12_tap_ths_x_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_X,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_X, (uint8_t *) ®, 1);
*val = reg._4d_en;
return ret;
@@ -2517,10 +2844,13 @@ int32_t lis2dtw12_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_6d_src_get(stmdev_ctx_t *ctx, lis2dtw12_sixd_src_t *val)
+int32_t lis2dtw12_6d_src_get(stmdev_ctx_t *ctx,
+ lis2dtw12_sixd_src_t *val)
{
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_SIXD_SRC, (uint8_t*) val, 1);
+
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_SIXD_SRC, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -2532,16 +2862,19 @@ int32_t lis2dtw12_6d_src_get(stmdev_ctx_t *ctx, lis2dtw12_sixd_src_t *val)
*
*/
int32_t lis2dtw12_6d_feed_data_set(stmdev_ctx_t *ctx,
- lis2dtw12_lpass_on6d_t val)
+ lis2dtw12_lpass_on6d_t val)
{
lis2dtw12_ctrl_reg7_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.lpass_on6d = (uint8_t) val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL_REG7,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -2554,24 +2887,28 @@ int32_t lis2dtw12_6d_feed_data_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis2dtw12_6d_feed_data_get(stmdev_ctx_t *ctx,
- lis2dtw12_lpass_on6d_t *val)
+ lis2dtw12_lpass_on6d_t *val)
{
lis2dtw12_ctrl_reg7_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
- switch (reg.lpass_on6d) {
+ switch (reg.lpass_on6d)
+ {
case LIS2DTW12_ODR_DIV_2_FEED:
*val = LIS2DTW12_ODR_DIV_2_FEED;
break;
+
case LIS2DTW12_LPF2_FEED:
*val = LIS2DTW12_LPF2_FEED;
break;
+
default:
*val = LIS2DTW12_ODR_DIV_2_FEED;
break;
}
+
return ret;
}
@@ -2603,17 +2940,27 @@ int32_t lis2dtw12_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dtw12_free_fall_t free_fall;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
- if (ret == 0) {
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FREE_FALL,(uint8_t*) &free_fall, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_DUR,
+ (uint8_t *) &wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FREE_FALL,
+ (uint8_t *) &free_fall, 1);
}
- if(ret == 0) {
- wake_up_dur.ff_dur = ( (uint8_t) val & 0x20U) >> 5;
+
+ if (ret == 0)
+ {
+ wake_up_dur.ff_dur = ((uint8_t) val & 0x20U) >> 5;
free_fall.ff_dur = (uint8_t) val & 0x1FU;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_WAKE_UP_DUR,
+ (uint8_t *) &wake_up_dur, 1);
}
- if(ret == 0) {
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_FREE_FALL,(uint8_t*) &free_fall, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_FREE_FALL,
+ (uint8_t *) &free_fall, 1);
}
return ret;
@@ -2634,11 +2981,16 @@ int32_t lis2dtw12_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dtw12_free_fall_t free_fall;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
- if (ret == 0) {
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FREE_FALL,(uint8_t*) &free_fall, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_DUR,
+ (uint8_t *) &wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FREE_FALL,
+ (uint8_t *) &free_fall, 1);
*val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
}
+
return ret;
}
@@ -2650,15 +3002,18 @@ int32_t lis2dtw12_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_ff_threshold_set(stmdev_ctx_t *ctx, lis2dtw12_ff_ths_t val)
+int32_t lis2dtw12_ff_threshold_set(stmdev_ctx_t *ctx,
+ lis2dtw12_ff_ths_t val)
{
lis2dtw12_free_fall_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FREE_FALL,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FREE_FALL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.ff_ths = (uint8_t) val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_FREE_FALL,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_FREE_FALL, (uint8_t *) ®, 1);
}
return ret;
@@ -2673,42 +3028,52 @@ int32_t lis2dtw12_ff_threshold_set(stmdev_ctx_t *ctx, lis2dtw12_ff_ths_t val)
*
*/
int32_t lis2dtw12_ff_threshold_get(stmdev_ctx_t *ctx,
- lis2dtw12_ff_ths_t *val)
+ lis2dtw12_ff_ths_t *val)
{
lis2dtw12_free_fall_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FREE_FALL,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FREE_FALL, (uint8_t *) ®, 1);
- switch (reg.ff_ths) {
+ switch (reg.ff_ths)
+ {
case LIS2DTW12_FF_TSH_5LSb_FS2g:
*val = LIS2DTW12_FF_TSH_5LSb_FS2g;
break;
+
case LIS2DTW12_FF_TSH_7LSb_FS2g:
*val = LIS2DTW12_FF_TSH_7LSb_FS2g;
break;
+
case LIS2DTW12_FF_TSH_8LSb_FS2g:
*val = LIS2DTW12_FF_TSH_8LSb_FS2g;
break;
+
case LIS2DTW12_FF_TSH_10LSb_FS2g:
*val = LIS2DTW12_FF_TSH_10LSb_FS2g;
break;
+
case LIS2DTW12_FF_TSH_11LSb_FS2g:
*val = LIS2DTW12_FF_TSH_11LSb_FS2g;
break;
+
case LIS2DTW12_FF_TSH_13LSb_FS2g:
*val = LIS2DTW12_FF_TSH_13LSb_FS2g;
break;
+
case LIS2DTW12_FF_TSH_15LSb_FS2g:
*val = LIS2DTW12_FF_TSH_15LSb_FS2g;
break;
+
case LIS2DTW12_FF_TSH_16LSb_FS2g:
*val = LIS2DTW12_FF_TSH_16LSb_FS2g;
break;
+
default:
*val = LIS2DTW12_FF_TSH_5LSb_FS2g;
break;
}
+
return ret;
}
@@ -2737,10 +3102,12 @@ int32_t lis2dtw12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dtw12_fifo_ctrl_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FIFO_CTRL,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FIFO_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.fth = val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_FIFO_CTRL,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_FIFO_CTRL, (uint8_t *) ®, 1);
}
return ret;
@@ -2759,7 +3126,7 @@ int32_t lis2dtw12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dtw12_fifo_ctrl_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FIFO_CTRL,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FIFO_CTRL, (uint8_t *) ®, 1);
*val = reg.fth;
return ret;
@@ -2773,16 +3140,20 @@ int32_t lis2dtw12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_fifo_mode_set(stmdev_ctx_t *ctx, lis2dtw12_fmode_t val)
+int32_t lis2dtw12_fifo_mode_set(stmdev_ctx_t *ctx,
+ lis2dtw12_fmode_t val)
{
lis2dtw12_fifo_ctrl_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FIFO_CTRL,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FIFO_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.fmode = (uint8_t) val;
- ret = lis2dtw12_write_reg(ctx, LIS2DTW12_FIFO_CTRL,(uint8_t*) ®, 1);
+ ret = lis2dtw12_write_reg(ctx, LIS2DTW12_FIFO_CTRL, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -2794,33 +3165,41 @@ int32_t lis2dtw12_fifo_mode_set(stmdev_ctx_t *ctx, lis2dtw12_fmode_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dtw12_fifo_mode_get(stmdev_ctx_t *ctx, lis2dtw12_fmode_t *val)
+int32_t lis2dtw12_fifo_mode_get(stmdev_ctx_t *ctx,
+ lis2dtw12_fmode_t *val)
{
lis2dtw12_fifo_ctrl_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FIFO_CTRL,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FIFO_CTRL, (uint8_t *) ®, 1);
- switch (reg.fmode) {
+ switch (reg.fmode)
+ {
case LIS2DTW12_BYPASS_MODE:
*val = LIS2DTW12_BYPASS_MODE;
break;
+
case LIS2DTW12_FIFO_MODE:
*val = LIS2DTW12_FIFO_MODE;
break;
+
case LIS2DTW12_STREAM_TO_FIFO_MODE:
*val = LIS2DTW12_STREAM_TO_FIFO_MODE;
break;
+
case LIS2DTW12_BYPASS_TO_STREAM_MODE:
*val = LIS2DTW12_BYPASS_TO_STREAM_MODE;
break;
+
case LIS2DTW12_STREAM_MODE:
*val = LIS2DTW12_STREAM_MODE;
break;
+
default:
*val = LIS2DTW12_BYPASS_MODE;
break;
}
+
return ret;
}
@@ -2837,7 +3216,8 @@ int32_t lis2dtw12_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dtw12_fifo_samples_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FIFO_SAMPLES,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FIFO_SAMPLES,
+ (uint8_t *) ®, 1);
*val = reg.diff;
return ret;
@@ -2855,7 +3235,8 @@ int32_t lis2dtw12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dtw12_fifo_samples_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FIFO_SAMPLES,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FIFO_SAMPLES,
+ (uint8_t *) ®, 1);
*val = reg.fifo_ovr;
return ret;
@@ -2873,7 +3254,8 @@ int32_t lis2dtw12_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dtw12_fifo_samples_t reg;
int32_t ret;
- ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FIFO_SAMPLES,(uint8_t*) ®, 1);
+ ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FIFO_SAMPLES,
+ (uint8_t *) ®, 1);
*val = reg.fifo_fth;
return ret;
diff --git a/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.h b/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.h
index 553effb2cc6310fe5659fba3f79611f7150f5818..4cf96b71f9362b9763930a942d488797ea10421a 100644
--- a/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.h
+++ b/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file lis2dtw12_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lis2dtw12_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lis2dtw12_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lis2dtw12_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LIS2DTW12_REGS_H
#define LIS2DTW12_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup LIS2DTW12
@@ -74,7 +75,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -107,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -131,15 +134,16 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
- * Unico / Unicleo tools available on STMicroelectronics
- * web site.
+ * You can create a sensor configuration by your own or using
+ * Unico / Unicleo tools available on STMicroelectronics
+ * web site.
*
* @{
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -177,7 +181,8 @@ typedef struct {
#define LIS2DTW12_OUT_T_H 0x0EU
#define LIS2DTW12_WHO_AM_I 0x0FU
#define LIS2DTW12_CTRL1 0x20U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lp_mode : 2;
uint8_t mode : 2;
@@ -190,7 +195,8 @@ typedef struct {
} lis2dtw12_ctrl1_t;
#define LIS2DTW12_CTRL2 0x21U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t i2c_disable : 1;
@@ -213,9 +219,11 @@ typedef struct {
} lis2dtw12_ctrl2_t;
#define LIS2DTW12_CTRL3 0x22U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t slp_mode : 2; /* slp_mode_sel + slp_mode_1 */
+uint8_t slp_mode :
+ 2; /* slp_mode_sel + slp_mode_1 */
uint8_t not_used_01 : 1;
uint8_t h_lactive : 1;
uint8_t lir : 1;
@@ -227,12 +235,14 @@ typedef struct {
uint8_t lir : 1;
uint8_t h_lactive : 1;
uint8_t not_used_01 : 1;
- uint8_t slp_mode : 2; /* slp_mode_sel + slp_mode_1 */
+uint8_t slp_mode :
+ 2; /* slp_mode_sel + slp_mode_1 */
#endif /* DRV_BYTE_ORDER */
} lis2dtw12_ctrl3_t;
#define LIS2DTW12_CTRL4_INT1_PAD_CTRL 0x23U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_drdy : 1;
uint8_t int1_fth : 1;
@@ -256,7 +266,8 @@ typedef struct {
} lis2dtw12_ctrl4_int1_pad_ctrl_t;
#define LIS2DTW12_CTRL5_INT2_PAD_CTRL 0x24U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_drdy : 1;
uint8_t int2_fth : 1;
@@ -280,7 +291,8 @@ typedef struct {
} lis2dtw12_ctrl5_int2_pad_ctrl_t;
#define LIS2DTW12_CTRL6 0x25U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t low_noise : 1;
@@ -298,7 +310,8 @@ typedef struct {
} lis2dtw12_ctrl6_t;
#define LIS2DTW12_STATUS 0x27U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t drdy : 1;
uint8_t ff_ia : 1;
@@ -327,7 +340,8 @@ typedef struct {
#define LIS2DTW12_OUT_Z_L 0x2CU
#define LIS2DTW12_OUT_Z_H 0x2DU
#define LIS2DTW12_FIFO_CTRL 0x2EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fth : 5;
uint8_t fmode : 3;
@@ -338,7 +352,8 @@ typedef struct {
} lis2dtw12_fifo_ctrl_t;
#define LIS2DTW12_FIFO_SAMPLES 0x2FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t diff : 6;
uint8_t fifo_ovr : 1;
@@ -351,7 +366,8 @@ typedef struct {
} lis2dtw12_fifo_samples_t;
#define LIS2DTW12_TAP_THS_X 0x30U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_thsx : 5;
uint8_t _6d_ths : 2;
@@ -364,7 +380,8 @@ typedef struct {
} lis2dtw12_tap_ths_x_t;
#define LIS2DTW12_TAP_THS_Y 0x31U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_thsy : 5;
uint8_t tap_prior : 3;
@@ -375,7 +392,8 @@ typedef struct {
} lis2dtw12_tap_ths_y_t;
#define LIS2DTW12_TAP_THS_Z 0x32U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_thsz : 5;
uint8_t tap_z_en : 1;
@@ -390,7 +408,8 @@ typedef struct {
} lis2dtw12_tap_ths_z_t;
#define LIS2DTW12_INT_DUR 0x33U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shock : 2;
uint8_t quiet : 2;
@@ -403,7 +422,8 @@ typedef struct {
} lis2dtw12_int_dur_t;
#define LIS2DTW12_WAKE_UP_THS 0x34U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wk_ths : 6;
uint8_t sleep_on : 1;
@@ -416,7 +436,8 @@ typedef struct {
} lis2dtw12_wake_up_ths_t;
#define LIS2DTW12_WAKE_UP_DUR 0x35U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sleep_dur : 4;
uint8_t stationary : 1;
@@ -431,7 +452,8 @@ typedef struct {
} lis2dtw12_wake_up_dur_t;
#define LIS2DTW12_FREE_FALL 0x36U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ths : 3;
uint8_t ff_dur : 5;
@@ -442,7 +464,8 @@ typedef struct {
} lis2dtw12_free_fall_t;
#define LIS2DTW12_STATUS_DUP 0x37U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t drdy : 1;
uint8_t ff_ia : 1;
@@ -465,7 +488,8 @@ typedef struct {
} lis2dtw12_status_dup_t;
#define LIS2DTW12_WAKE_UP_SRC 0x38U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_wu : 1;
uint8_t y_wu : 1;
@@ -486,7 +510,8 @@ typedef struct {
} lis2dtw12_wake_up_src_t;
#define LIS2DTW12_TAP_SRC 0x39U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_tap : 1;
uint8_t y_tap : 1;
@@ -509,7 +534,8 @@ typedef struct {
} lis2dtw12_tap_src_t;
#define LIS2DTW12_SIXD_SRC 0x3AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
@@ -532,7 +558,8 @@ typedef struct {
} lis2dtw12_sixd_src_t;
#define LIS2DTW12_ALL_INT_SRC 0x3BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ia : 1;
uint8_t wu_ia : 1;
@@ -556,7 +583,8 @@ typedef struct {
#define LIS2DTW12_Y_OFS_USR 0x3DU
#define LIS2DTW12_Z_OFS_USR 0x3EU
#define LIS2DTW12_CTRL_REG7 0x3FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lpass_on6d : 1;
uint8_t hp_ref_mode : 1;
@@ -580,9 +608,9 @@ typedef struct {
/**
* @defgroup LIS2DTW12_Register_Union
- * @brief This union group all the registers that has a bitfield
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -590,7 +618,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
lis2dtw12_ctrl1_t ctrl1;
lis2dtw12_ctrl2_t ctrl2;
lis2dtw12_ctrl3_t ctrl3;
@@ -622,22 +651,27 @@ typedef union{
*
*/
-int32_t lis2dtw12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
- uint16_t len);
-int32_t lis2dtw12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lis2dtw12_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
+int32_t lis2dtw12_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len);
-extern float_t lis2dtw12_from_fs2_to_mg(int16_t lsb);
-extern float_t lis2dtw12_from_fs4_to_mg(int16_t lsb);
-extern float_t lis2dtw12_from_fs8_to_mg(int16_t lsb);
-extern float_t lis2dtw12_from_fs16_to_mg(int16_t lsb);
-extern float_t lis2dtw12_from_fs2_lp1_to_mg(int16_t lsb);
-extern float_t lis2dtw12_from_fs4_lp1_to_mg(int16_t lsb);
-extern float_t lis2dtw12_from_fs8_lp1_to_mg(int16_t lsb);
-extern float_t lis2dtw12_from_fs16_lp1_to_mg(int16_t lsb);
-extern float_t lis2dtw12_from_lsb_to_celsius(int16_t lsb);
-
-typedef enum {
+float_t lis2dtw12_from_fs2_to_mg(int16_t lsb);
+float_t lis2dtw12_from_fs4_to_mg(int16_t lsb);
+float_t lis2dtw12_from_fs8_to_mg(int16_t lsb);
+float_t lis2dtw12_from_fs16_to_mg(int16_t lsb);
+
+float_t lis2dtw12_from_fs2_lp1_to_mg(int16_t lsb);
+float_t lis2dtw12_from_fs4_lp1_to_mg(int16_t lsb);
+float_t lis2dtw12_from_fs8_lp1_to_mg(int16_t lsb);
+float_t lis2dtw12_from_fs16_lp1_to_mg(int16_t lsb);
+
+float_t lis2dtw12_from_lsb_to_celsius(int16_t lsb);
+
+typedef enum
+{
LIS2DTW12_HIGH_PERFORMANCE = 0x04,
LIS2DTW12_CONT_LOW_PWR_4 = 0x03,
LIS2DTW12_CONT_LOW_PWR_3 = 0x02,
@@ -657,10 +691,13 @@ typedef enum {
LIS2DTW12_SINGLE_LOW_PWR_LOW_NOISE_2 = 0x19,
LIS2DTW12_SINGLE_LOW_LOW_NOISE_PWR_12bit = 0x18,
} lis2dtw12_mode_t;
-int32_t lis2dtw12_power_mode_set(stmdev_ctx_t *ctx, lis2dtw12_mode_t val);
-int32_t lis2dtw12_power_mode_get(stmdev_ctx_t *ctx, lis2dtw12_mode_t *val);
+int32_t lis2dtw12_power_mode_set(stmdev_ctx_t *ctx,
+ lis2dtw12_mode_t val);
+int32_t lis2dtw12_power_mode_get(stmdev_ctx_t *ctx,
+ lis2dtw12_mode_t *val);
-typedef enum {
+typedef enum
+{
LIS2DTW12_XL_ODR_OFF = 0x00,
LIS2DTW12_XL_ODR_1Hz6_LP_ONLY = 0x01,
LIS2DTW12_XL_ODR_12Hz5 = 0x02,
@@ -674,26 +711,36 @@ typedef enum {
LIS2DTW12_XL_SET_SW_TRIG = 0x12, /* Use this only in SINGLE mode */
LIS2DTW12_XL_SET_PIN_TRIG = 0x22, /* Use this only in SINGLE mode */
} lis2dtw12_odr_t;
-int32_t lis2dtw12_data_rate_set(stmdev_ctx_t *ctx, lis2dtw12_odr_t val);
-int32_t lis2dtw12_data_rate_get(stmdev_ctx_t *ctx, lis2dtw12_odr_t *val);
-
-int32_t lis2dtw12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2dtw12_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
-
-typedef enum {
+int32_t lis2dtw12_data_rate_set(stmdev_ctx_t *ctx,
+ lis2dtw12_odr_t val);
+int32_t lis2dtw12_data_rate_get(stmdev_ctx_t *ctx,
+ lis2dtw12_odr_t *val);
+
+int32_t lis2dtw12_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2dtw12_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+typedef enum
+{
LIS2DTW12_2g = 0,
LIS2DTW12_4g = 1,
LIS2DTW12_8g = 2,
LIS2DTW12_16g = 3,
} lis2dtw12_fs_t;
-int32_t lis2dtw12_full_scale_set(stmdev_ctx_t *ctx, lis2dtw12_fs_t val);
-int32_t lis2dtw12_full_scale_get(stmdev_ctx_t *ctx, lis2dtw12_fs_t *val);
+int32_t lis2dtw12_full_scale_set(stmdev_ctx_t *ctx,
+ lis2dtw12_fs_t val);
+int32_t lis2dtw12_full_scale_get(stmdev_ctx_t *ctx,
+ lis2dtw12_fs_t *val);
-int32_t lis2dtw12_status_reg_get(stmdev_ctx_t *ctx, lis2dtw12_status_t *val);
+int32_t lis2dtw12_status_reg_get(stmdev_ctx_t *ctx,
+ lis2dtw12_status_t *val);
-int32_t lis2dtw12_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2dtw12_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef struct{
+typedef struct
+{
lis2dtw12_status_dup_t status_dup;
lis2dtw12_wake_up_src_t wake_up_src;
lis2dtw12_tap_src_t tap_src;
@@ -701,7 +748,7 @@ typedef struct{
lis2dtw12_all_int_src_t all_int_src;
} lis2dtw12_all_sources_t;
int32_t lis2dtw12_all_sources_get(stmdev_ctx_t *ctx,
- lis2dtw12_all_sources_t *val);
+ lis2dtw12_all_sources_t *val);
int32_t lis2dtw12_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t lis2dtw12_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff);
@@ -712,18 +759,21 @@ int32_t lis2dtw12_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t lis2dtw12_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t lis2dtw12_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff);
-typedef enum {
+typedef enum
+{
LIS2DTW12_LSb_977ug = 0,
LIS2DTW12_LSb_15mg6 = 1,
} lis2dtw12_usr_off_w_t;
int32_t lis2dtw12_offset_weight_set(stmdev_ctx_t *ctx,
- lis2dtw12_usr_off_w_t val);
+ lis2dtw12_usr_off_w_t val);
int32_t lis2dtw12_offset_weight_get(stmdev_ctx_t *ctx,
- lis2dtw12_usr_off_w_t *val);
+ lis2dtw12_usr_off_w_t *val);
-int32_t lis2dtw12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t lis2dtw12_temperature_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
-int32_t lis2dtw12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t lis2dtw12_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
int32_t lis2dtw12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
@@ -736,102 +786,122 @@ int32_t lis2dtw12_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2dtw12_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dtw12_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DTW12_XL_ST_DISABLE = 0,
LIS2DTW12_XL_ST_POSITIVE = 1,
LIS2DTW12_XL_ST_NEGATIVE = 2,
} lis2dtw12_st_t;
-int32_t lis2dtw12_self_test_set(stmdev_ctx_t *ctx, lis2dtw12_st_t val);
-int32_t lis2dtw12_self_test_get(stmdev_ctx_t *ctx, lis2dtw12_st_t *val);
+int32_t lis2dtw12_self_test_set(stmdev_ctx_t *ctx,
+ lis2dtw12_st_t val);
+int32_t lis2dtw12_self_test_get(stmdev_ctx_t *ctx,
+ lis2dtw12_st_t *val);
-typedef enum {
+typedef enum
+{
LIS2DTW12_DRDY_LATCHED = 0,
LIS2DTW12_DRDY_PULSED = 1,
} lis2dtw12_drdy_pulsed_t;
int32_t lis2dtw12_data_ready_mode_set(stmdev_ctx_t *ctx,
- lis2dtw12_drdy_pulsed_t val);
+ lis2dtw12_drdy_pulsed_t val);
int32_t lis2dtw12_data_ready_mode_get(stmdev_ctx_t *ctx,
- lis2dtw12_drdy_pulsed_t *val);
+ lis2dtw12_drdy_pulsed_t *val);
-typedef enum {
+typedef enum
+{
LIS2DTW12_LPF_ON_OUT = 0x00,
LIS2DTW12_USER_OFFSET_ON_OUT = 0x01,
LIS2DTW12_HIGH_PASS_ON_OUT = 0x10,
} lis2dtw12_fds_t;
-int32_t lis2dtw12_filter_path_set(stmdev_ctx_t *ctx, lis2dtw12_fds_t val);
-int32_t lis2dtw12_filter_path_get(stmdev_ctx_t *ctx, lis2dtw12_fds_t *val);
+int32_t lis2dtw12_filter_path_set(stmdev_ctx_t *ctx,
+ lis2dtw12_fds_t val);
+int32_t lis2dtw12_filter_path_get(stmdev_ctx_t *ctx,
+ lis2dtw12_fds_t *val);
-typedef enum {
+typedef enum
+{
LIS2DTW12_ODR_DIV_2 = 0,
LIS2DTW12_ODR_DIV_4 = 1,
LIS2DTW12_ODR_DIV_10 = 2,
LIS2DTW12_ODR_DIV_20 = 3,
} lis2dtw12_bw_filt_t;
int32_t lis2dtw12_filter_bandwidth_set(stmdev_ctx_t *ctx,
- lis2dtw12_bw_filt_t val);
+ lis2dtw12_bw_filt_t val);
int32_t lis2dtw12_filter_bandwidth_get(stmdev_ctx_t *ctx,
- lis2dtw12_bw_filt_t *val);
+ lis2dtw12_bw_filt_t *val);
int32_t lis2dtw12_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dtw12_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DTW12_SPI_4_WIRE = 0,
LIS2DTW12_SPI_3_WIRE = 1,
} lis2dtw12_sim_t;
-int32_t lis2dtw12_spi_mode_set(stmdev_ctx_t *ctx, lis2dtw12_sim_t val);
-int32_t lis2dtw12_spi_mode_get(stmdev_ctx_t *ctx, lis2dtw12_sim_t *val);
+int32_t lis2dtw12_spi_mode_set(stmdev_ctx_t *ctx,
+ lis2dtw12_sim_t val);
+int32_t lis2dtw12_spi_mode_get(stmdev_ctx_t *ctx,
+ lis2dtw12_sim_t *val);
-typedef enum {
+typedef enum
+{
LIS2DTW12_I2C_ENABLE = 0,
LIS2DTW12_I2C_DISABLE = 1,
} lis2dtw12_i2c_disable_t;
int32_t lis2dtw12_i2c_interface_set(stmdev_ctx_t *ctx,
- lis2dtw12_i2c_disable_t val);
+ lis2dtw12_i2c_disable_t val);
int32_t lis2dtw12_i2c_interface_get(stmdev_ctx_t *ctx,
- lis2dtw12_i2c_disable_t *val);
+ lis2dtw12_i2c_disable_t *val);
-typedef enum {
+typedef enum
+{
LIS2DTW12_PULL_UP_CONNECT = 0,
LIS2DTW12_PULL_UP_DISCONNECT = 1,
} lis2dtw12_cs_pu_disc_t;
-int32_t lis2dtw12_cs_mode_set(stmdev_ctx_t *ctx, lis2dtw12_cs_pu_disc_t val);
-int32_t lis2dtw12_cs_mode_get(stmdev_ctx_t *ctx, lis2dtw12_cs_pu_disc_t *val);
+int32_t lis2dtw12_cs_mode_set(stmdev_ctx_t *ctx,
+ lis2dtw12_cs_pu_disc_t val);
+int32_t lis2dtw12_cs_mode_get(stmdev_ctx_t *ctx,
+ lis2dtw12_cs_pu_disc_t *val);
-typedef enum {
+typedef enum
+{
LIS2DTW12_ACTIVE_HIGH = 0,
LIS2DTW12_ACTIVE_LOW = 1,
} lis2dtw12_h_lactive_t;
int32_t lis2dtw12_pin_polarity_set(stmdev_ctx_t *ctx,
- lis2dtw12_h_lactive_t val);
+ lis2dtw12_h_lactive_t val);
int32_t lis2dtw12_pin_polarity_get(stmdev_ctx_t *ctx,
- lis2dtw12_h_lactive_t *val);
+ lis2dtw12_h_lactive_t *val);
-typedef enum {
+typedef enum
+{
LIS2DTW12_INT_PULSED = 0,
LIS2DTW12_INT_LATCHED = 1,
} lis2dtw12_lir_t;
int32_t lis2dtw12_int_notification_set(stmdev_ctx_t *ctx,
- lis2dtw12_lir_t val);
+ lis2dtw12_lir_t val);
int32_t lis2dtw12_int_notification_get(stmdev_ctx_t *ctx,
- lis2dtw12_lir_t *val);
+ lis2dtw12_lir_t *val);
-typedef enum {
+typedef enum
+{
LIS2DTW12_PUSH_PULL = 0,
LIS2DTW12_OPEN_DRAIN = 1,
} lis2dtw12_pp_od_t;
-int32_t lis2dtw12_pin_mode_set(stmdev_ctx_t *ctx, lis2dtw12_pp_od_t val);
-int32_t lis2dtw12_pin_mode_get(stmdev_ctx_t *ctx, lis2dtw12_pp_od_t *val);
+int32_t lis2dtw12_pin_mode_set(stmdev_ctx_t *ctx,
+ lis2dtw12_pp_od_t val);
+int32_t lis2dtw12_pin_mode_get(stmdev_ctx_t *ctx,
+ lis2dtw12_pp_od_t *val);
int32_t lis2dtw12_pin_int1_route_set(stmdev_ctx_t *ctx,
- lis2dtw12_ctrl4_int1_pad_ctrl_t *val);
+ lis2dtw12_ctrl4_int1_pad_ctrl_t *val);
int32_t lis2dtw12_pin_int1_route_get(stmdev_ctx_t *ctx,
- lis2dtw12_ctrl4_int1_pad_ctrl_t *val);
+ lis2dtw12_ctrl4_int1_pad_ctrl_t *val);
int32_t lis2dtw12_pin_int2_route_set(stmdev_ctx_t *ctx,
- lis2dtw12_ctrl5_int2_pad_ctrl_t *val);
+ lis2dtw12_ctrl5_int2_pad_ctrl_t *val);
int32_t lis2dtw12_pin_int2_route_get(stmdev_ctx_t *ctx,
- lis2dtw12_ctrl5_int2_pad_ctrl_t *val);
+ lis2dtw12_ctrl5_int2_pad_ctrl_t *val);
int32_t lis2dtw12_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dtw12_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -842,33 +912,40 @@ int32_t lis2dtw12_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2dtw12_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dtw12_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DTW12_HP_FEED = 0,
LIS2DTW12_USER_OFFSET_FEED = 1,
} lis2dtw12_usr_off_on_wu_t;
int32_t lis2dtw12_wkup_feed_data_set(stmdev_ctx_t *ctx,
- lis2dtw12_usr_off_on_wu_t val);
+ lis2dtw12_usr_off_on_wu_t val);
int32_t lis2dtw12_wkup_feed_data_get(stmdev_ctx_t *ctx,
- lis2dtw12_usr_off_on_wu_t *val);
+ lis2dtw12_usr_off_on_wu_t *val);
-typedef enum {
+typedef enum
+{
LIS2DTW12_NO_DETECTION = 0,
LIS2DTW12_DETECT_ACT_INACT = 1,
LIS2DTW12_DETECT_STAT_MOTION = 3,
} lis2dtw12_sleep_on_t;
-int32_t lis2dtw12_act_mode_set(stmdev_ctx_t *ctx, lis2dtw12_sleep_on_t val);
-int32_t lis2dtw12_act_mode_get(stmdev_ctx_t *ctx, lis2dtw12_sleep_on_t *val);
+int32_t lis2dtw12_act_mode_set(stmdev_ctx_t *ctx,
+ lis2dtw12_sleep_on_t val);
+int32_t lis2dtw12_act_mode_get(stmdev_ctx_t *ctx,
+ lis2dtw12_sleep_on_t *val);
int32_t lis2dtw12_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dtw12_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2dtw12_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2dtw12_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2dtw12_tap_threshold_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lis2dtw12_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2dtw12_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2dtw12_tap_threshold_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DTW12_XYZ = 0,
LIS2DTW12_YXZ = 1,
LIS2DTW12_XZY = 2,
@@ -877,21 +954,28 @@ typedef enum {
LIS2DTW12_ZXY = 6,
} lis2dtw12_tap_prior_t;
int32_t lis2dtw12_tap_axis_priority_set(stmdev_ctx_t *ctx,
- lis2dtw12_tap_prior_t val);
+ lis2dtw12_tap_prior_t val);
int32_t lis2dtw12_tap_axis_priority_get(stmdev_ctx_t *ctx,
- lis2dtw12_tap_prior_t *val);
+ lis2dtw12_tap_prior_t *val);
int32_t lis2dtw12_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2dtw12_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2dtw12_tap_threshold_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lis2dtw12_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2dtw12_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2dtw12_tap_detection_on_z_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2dtw12_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lis2dtw12_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2dtw12_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2dtw12_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2dtw12_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lis2dtw12_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2dtw12_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2dtw12_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2dtw12_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lis2dtw12_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dtw12_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -902,16 +986,18 @@ int32_t lis2dtw12_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2dtw12_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dtw12_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DTW12_ONLY_SINGLE = 0,
LIS2DTW12_BOTH_SINGLE_DOUBLE = 1,
} lis2dtw12_single_double_tap_t;
int32_t lis2dtw12_tap_mode_set(stmdev_ctx_t *ctx,
- lis2dtw12_single_double_tap_t val);
+ lis2dtw12_single_double_tap_t val);
int32_t lis2dtw12_tap_mode_get(stmdev_ctx_t *ctx,
- lis2dtw12_single_double_tap_t *val);
+ lis2dtw12_single_double_tap_t *val);
-int32_t lis2dtw12_tap_src_get(stmdev_ctx_t *ctx, lis2dtw12_tap_src_t *val);
+int32_t lis2dtw12_tap_src_get(stmdev_ctx_t *ctx,
+ lis2dtw12_tap_src_t *val);
int32_t lis2dtw12_6d_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dtw12_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -919,21 +1005,24 @@ int32_t lis2dtw12_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2dtw12_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dtw12_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lis2dtw12_6d_src_get(stmdev_ctx_t *ctx, lis2dtw12_sixd_src_t *val);
+int32_t lis2dtw12_6d_src_get(stmdev_ctx_t *ctx,
+ lis2dtw12_sixd_src_t *val);
-typedef enum {
+typedef enum
+{
LIS2DTW12_ODR_DIV_2_FEED = 0,
LIS2DTW12_LPF2_FEED = 1,
} lis2dtw12_lpass_on6d_t;
int32_t lis2dtw12_6d_feed_data_set(stmdev_ctx_t *ctx,
- lis2dtw12_lpass_on6d_t val);
+ lis2dtw12_lpass_on6d_t val);
int32_t lis2dtw12_6d_feed_data_get(stmdev_ctx_t *ctx,
- lis2dtw12_lpass_on6d_t *val);
+ lis2dtw12_lpass_on6d_t *val);
int32_t lis2dtw12_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dtw12_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DTW12_FF_TSH_5LSb_FS2g = 0,
LIS2DTW12_FF_TSH_7LSb_FS2g = 1,
LIS2DTW12_FF_TSH_8LSb_FS2g = 2,
@@ -944,24 +1033,28 @@ typedef enum {
LIS2DTW12_FF_TSH_16LSb_FS2g = 7,
} lis2dtw12_ff_ths_t;
int32_t lis2dtw12_ff_threshold_set(stmdev_ctx_t *ctx,
- lis2dtw12_ff_ths_t val);
+ lis2dtw12_ff_ths_t val);
int32_t lis2dtw12_ff_threshold_get(stmdev_ctx_t *ctx,
- lis2dtw12_ff_ths_t *val);
+ lis2dtw12_ff_ths_t *val);
int32_t lis2dtw12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dtw12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DTW12_BYPASS_MODE = 0,
LIS2DTW12_FIFO_MODE = 1,
LIS2DTW12_STREAM_TO_FIFO_MODE = 3,
LIS2DTW12_BYPASS_TO_STREAM_MODE = 4,
LIS2DTW12_STREAM_MODE = 6,
} lis2dtw12_fmode_t;
-int32_t lis2dtw12_fifo_mode_set(stmdev_ctx_t *ctx, lis2dtw12_fmode_t val);
-int32_t lis2dtw12_fifo_mode_get(stmdev_ctx_t *ctx, lis2dtw12_fmode_t *val);
+int32_t lis2dtw12_fifo_mode_set(stmdev_ctx_t *ctx,
+ lis2dtw12_fmode_t val);
+int32_t lis2dtw12_fifo_mode_get(stmdev_ctx_t *ctx,
+ lis2dtw12_fmode_t *val);
-int32_t lis2dtw12_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2dtw12_fifo_data_level_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lis2dtw12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
diff --git a/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.c b/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.c
index d9736296e361ab598740425ced39bfdedffbd7a8..dbbc03088c1e3c3b92d1649cf87197a331e78186 100644
--- a/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.c
+++ b/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file lis2dw12_reg.c
- * @author Sensors Software Solution Team
- * @brief LIS2DW12 driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lis2dw12_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LIS2DW12 driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lis2dw12_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dw12_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lis2dw12_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t lis2dw12_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dw12_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lis2dw12_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -101,7 +107,7 @@ float_t lis2dw12_from_fs8_to_mg(int16_t lsb)
float_t lis2dw12_from_fs16_to_mg(int16_t lsb)
{
- return ((float_t)lsb) *0.488f;
+ return ((float_t)lsb) * 0.488f;
}
float_t lis2dw12_from_fs2_lp1_to_mg(int16_t lsb)
@@ -151,25 +157,33 @@ float_t lis2dw12_from_lsb_to_celsius(int16_t lsb)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dw12_power_mode_set(stmdev_ctx_t *ctx, lis2dw12_mode_t val)
+int32_t lis2dw12_power_mode_set(stmdev_ctx_t *ctx,
+ lis2dw12_mode_t val)
{
lis2dw12_ctrl1_t ctrl1;
lis2dw12_ctrl6_t ctrl6;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1,(uint8_t*) &ctrl1, 1);
- if (ret == 0) {
- ctrl1.mode = ( (uint8_t) val & 0x0CU ) >> 2;
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1);
+
+ if (ret == 0)
+ {
+ ctrl1.mode = ((uint8_t) val & 0x0CU) >> 2;
ctrl1.lp_mode = (uint8_t) val & 0x03U ;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL1,(uint8_t*) &ctrl1, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1);
}
- if (ret == 0) {
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) &ctrl6, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1);
}
- if (ret == 0) {
- ctrl6.low_noise = ( (uint8_t) val & 0x10U ) >> 4;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) &ctrl6, 1);
+
+ if (ret == 0)
+ {
+ ctrl6.low_noise = ((uint8_t) val & 0x10U) >> 4;
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1);
}
+
return ret;
}
@@ -182,77 +196,100 @@ int32_t lis2dw12_power_mode_set(stmdev_ctx_t *ctx, lis2dw12_mode_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dw12_power_mode_get(stmdev_ctx_t *ctx, lis2dw12_mode_t *val)
+int32_t lis2dw12_power_mode_get(stmdev_ctx_t *ctx,
+ lis2dw12_mode_t *val)
{
lis2dw12_ctrl1_t ctrl1;
lis2dw12_ctrl6_t ctrl6;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1,(uint8_t*) &ctrl1, 1);
- if (ret == 0) {
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) &ctrl6, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1);
switch (((ctrl6.low_noise << 4) + (ctrl1.mode << 2) +
- ctrl1.lp_mode)) {
+ ctrl1.lp_mode))
+ {
case LIS2DW12_HIGH_PERFORMANCE:
*val = LIS2DW12_HIGH_PERFORMANCE;
break;
+
case LIS2DW12_CONT_LOW_PWR_4:
*val = LIS2DW12_CONT_LOW_PWR_4;
break;
+
case LIS2DW12_CONT_LOW_PWR_3:
*val = LIS2DW12_CONT_LOW_PWR_3;
break;
+
case LIS2DW12_CONT_LOW_PWR_2:
*val = LIS2DW12_CONT_LOW_PWR_2;
break;
+
case LIS2DW12_CONT_LOW_PWR_12bit:
*val = LIS2DW12_CONT_LOW_PWR_12bit;
break;
+
case LIS2DW12_SINGLE_LOW_PWR_4:
*val = LIS2DW12_SINGLE_LOW_PWR_4;
break;
+
case LIS2DW12_SINGLE_LOW_PWR_3:
*val = LIS2DW12_SINGLE_LOW_PWR_3;
break;
+
case LIS2DW12_SINGLE_LOW_PWR_2:
*val = LIS2DW12_SINGLE_LOW_PWR_2;
break;
+
case LIS2DW12_SINGLE_LOW_PWR_12bit:
*val = LIS2DW12_SINGLE_LOW_PWR_12bit;
break;
+
case LIS2DW12_HIGH_PERFORMANCE_LOW_NOISE:
*val = LIS2DW12_HIGH_PERFORMANCE_LOW_NOISE;
break;
+
case LIS2DW12_CONT_LOW_PWR_LOW_NOISE_4:
*val = LIS2DW12_CONT_LOW_PWR_LOW_NOISE_4;
break;
+
case LIS2DW12_CONT_LOW_PWR_LOW_NOISE_3:
*val = LIS2DW12_CONT_LOW_PWR_LOW_NOISE_3;
break;
+
case LIS2DW12_CONT_LOW_PWR_LOW_NOISE_2:
*val = LIS2DW12_CONT_LOW_PWR_LOW_NOISE_2;
break;
+
case LIS2DW12_CONT_LOW_PWR_LOW_NOISE_12bit:
*val = LIS2DW12_CONT_LOW_PWR_LOW_NOISE_12bit;
break;
+
case LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_4:
*val = LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_4;
break;
+
case LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_3:
*val = LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_3;
break;
+
case LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_2:
*val = LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_2;
break;
+
case LIS2DW12_SINGLE_LOW_LOW_NOISE_PWR_12bit:
*val = LIS2DW12_SINGLE_LOW_LOW_NOISE_PWR_12bit;
break;
+
default:
*val = LIS2DW12_HIGH_PERFORMANCE;
break;
}
}
+
return ret;
}
@@ -270,18 +307,25 @@ int32_t lis2dw12_data_rate_set(stmdev_ctx_t *ctx, lis2dw12_odr_t val)
lis2dw12_ctrl3_t ctrl3;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1,(uint8_t*) &ctrl1, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1);
+
+ if (ret == 0)
+ {
ctrl1.odr = (uint8_t) val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL1,(uint8_t*) &ctrl1, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1);
}
- if (ret == 0) {
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) &ctrl3, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) &ctrl3, 1);
}
- if (ret == 0) {
- ctrl3.slp_mode = ( (uint8_t) val & 0x30U ) >> 4;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) &ctrl3, 1);
+
+ if (ret == 0)
+ {
+ ctrl3.slp_mode = ((uint8_t) val & 0x30U) >> 4;
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) &ctrl3, 1);
}
+
return ret;
}
@@ -299,52 +343,68 @@ int32_t lis2dw12_data_rate_get(stmdev_ctx_t *ctx, lis2dw12_odr_t *val)
lis2dw12_ctrl3_t ctrl3;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1,(uint8_t*) &ctrl1, 1);
- if (ret == 0) {
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) &ctrl3, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) &ctrl3, 1);
- switch ((ctrl3.slp_mode << 4) + ctrl1.odr) {
+ switch ((ctrl3.slp_mode << 4) + ctrl1.odr)
+ {
case LIS2DW12_XL_ODR_OFF:
*val = LIS2DW12_XL_ODR_OFF;
break;
+
case LIS2DW12_XL_ODR_1Hz6_LP_ONLY:
*val = LIS2DW12_XL_ODR_1Hz6_LP_ONLY;
break;
+
case LIS2DW12_XL_ODR_12Hz5:
*val = LIS2DW12_XL_ODR_12Hz5;
break;
+
case LIS2DW12_XL_ODR_25Hz:
*val = LIS2DW12_XL_ODR_25Hz;
break;
- case LIS2DW12_XL_ODR_50Hz:
+
+ case LIS2DW12_XL_ODR_50Hz:
*val = LIS2DW12_XL_ODR_50Hz;
break;
+
case LIS2DW12_XL_ODR_100Hz:
*val = LIS2DW12_XL_ODR_100Hz;
break;
+
case LIS2DW12_XL_ODR_200Hz:
*val = LIS2DW12_XL_ODR_200Hz;
break;
+
case LIS2DW12_XL_ODR_400Hz:
*val = LIS2DW12_XL_ODR_400Hz;
break;
- case LIS2DW12_XL_ODR_800Hz:
+
+ case LIS2DW12_XL_ODR_800Hz:
*val = LIS2DW12_XL_ODR_800Hz;
break;
+
case LIS2DW12_XL_ODR_1k6Hz:
*val = LIS2DW12_XL_ODR_1k6Hz;
break;
+
case LIS2DW12_XL_SET_SW_TRIG:
*val = LIS2DW12_XL_SET_SW_TRIG;
break;
+
case LIS2DW12_XL_SET_PIN_TRIG:
*val = LIS2DW12_XL_SET_PIN_TRIG;
break;
+
default:
*val = LIS2DW12_XL_ODR_OFF;
break;
}
}
+
return ret;
}
@@ -361,11 +421,14 @@ int32_t lis2dw12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dw12_ctrl2_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.bdu = val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -377,12 +440,13 @@ int32_t lis2dw12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dw12_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2dw12_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2dw12_ctrl2_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
*val = reg.bdu;
return ret;
@@ -401,11 +465,14 @@ int32_t lis2dw12_full_scale_set(stmdev_ctx_t *ctx, lis2dw12_fs_t val)
lis2dw12_ctrl6_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.fs = (uint8_t) val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -422,25 +489,31 @@ int32_t lis2dw12_full_scale_get(stmdev_ctx_t *ctx, lis2dw12_fs_t *val)
lis2dw12_ctrl6_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) ®, 1);
- switch (reg.fs) {
+ switch (reg.fs)
+ {
case LIS2DW12_2g:
*val = LIS2DW12_2g;
break;
+
case LIS2DW12_4g:
*val = LIS2DW12_4g;
break;
+
case LIS2DW12_8g:
*val = LIS2DW12_8g;
break;
+
case LIS2DW12_16g:
*val = LIS2DW12_16g;
break;
+
default:
*val = LIS2DW12_2g;
break;
}
+
return ret;
}
@@ -452,10 +525,13 @@ int32_t lis2dw12_full_scale_get(stmdev_ctx_t *ctx, lis2dw12_fs_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dw12_status_reg_get(stmdev_ctx_t *ctx, lis2dw12_status_t *val)
+int32_t lis2dw12_status_reg_get(stmdev_ctx_t *ctx,
+ lis2dw12_status_t *val)
{
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_STATUS, (uint8_t*) val, 1);
+
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_STATUS, (uint8_t *) val, 1);
+
return ret;
}
@@ -472,7 +548,7 @@ int32_t lis2dw12_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dw12_status_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_STATUS,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_STATUS, (uint8_t *) ®, 1);
*val = reg.drdy;
return ret;
@@ -490,7 +566,9 @@ int32_t lis2dw12_all_sources_get(stmdev_ctx_t *ctx,
lis2dw12_all_sources_t *val)
{
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_STATUS_DUP, (uint8_t*) val, 5);
+
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_STATUS_DUP, (uint8_t *) val, 5);
+
return ret;
}
@@ -507,7 +585,9 @@ int32_t lis2dw12_all_sources_get(stmdev_ctx_t *ctx,
int32_t lis2dw12_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis2dw12_write_reg(ctx, LIS2DW12_X_OFS_USR, buff, 1);
+
return ret;
}
@@ -524,7 +604,9 @@ int32_t lis2dw12_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lis2dw12_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis2dw12_read_reg(ctx, LIS2DW12_X_OFS_USR, buff, 1);
+
return ret;
}
@@ -541,7 +623,9 @@ int32_t lis2dw12_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lis2dw12_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis2dw12_write_reg(ctx, LIS2DW12_Y_OFS_USR, buff, 1);
+
return ret;
}
@@ -558,7 +642,9 @@ int32_t lis2dw12_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lis2dw12_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis2dw12_read_reg(ctx, LIS2DW12_Y_OFS_USR, buff, 1);
+
return ret;
}
@@ -575,7 +661,9 @@ int32_t lis2dw12_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lis2dw12_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis2dw12_write_reg(ctx, LIS2DW12_Z_OFS_USR, buff, 1);
+
return ret;
}
@@ -592,7 +680,9 @@ int32_t lis2dw12_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lis2dw12_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis2dw12_read_reg(ctx, LIS2DW12_Z_OFS_USR, buff, 1);
+
return ret;
}
@@ -612,11 +702,14 @@ int32_t lis2dw12_offset_weight_set(stmdev_ctx_t *ctx,
lis2dw12_ctrl_reg7_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.usr_off_w = (uint8_t) val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -635,18 +728,23 @@ int32_t lis2dw12_offset_weight_get(stmdev_ctx_t *ctx,
lis2dw12_ctrl_reg7_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1);
- switch (reg.usr_off_w) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
+
+ switch (reg.usr_off_w)
+ {
case LIS2DW12_LSb_977ug:
*val = LIS2DW12_LSb_977ug;
break;
+
case LIS2DW12_LSb_15mg6:
*val = LIS2DW12_LSb_15mg6;
break;
+
default:
*val = LIS2DW12_LSb_977ug;
break;
}
+
return ret;
}
@@ -678,7 +776,7 @@ int32_t lis2dw12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
ret = lis2dw12_read_reg(ctx, LIS2DW12_OUT_T_L, buff, 2);
*val = (int16_t)buff[1];
- *val = (*val * 256) + (int16_t)buff[0];
+ *val = (*val * 256) + (int16_t)buff[0];
return ret;
}
@@ -699,11 +797,11 @@ int32_t lis2dw12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
ret = lis2dw12_read_reg(ctx, LIS2DW12_OUT_X_L, buff, 6);
val[0] = (int16_t)buff[1];
- val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
- val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
val[2] = (int16_t)buff[5];
- val[2] = (val[2] * 256) + (int16_t)buff[4];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
return ret;
}
@@ -731,7 +829,9 @@ int32_t lis2dw12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
int32_t lis2dw12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis2dw12_read_reg(ctx, LIS2DW12_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -749,11 +849,14 @@ int32_t lis2dw12_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dw12_ctrl2_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.if_add_inc = val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -771,7 +874,7 @@ int32_t lis2dw12_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dw12_ctrl2_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
*val = reg.if_add_inc;
return ret;
@@ -790,10 +893,12 @@ int32_t lis2dw12_reset_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dw12_ctrl2_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.soft_reset = val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
}
return ret;
@@ -812,7 +917,7 @@ int32_t lis2dw12_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dw12_ctrl2_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
*val = reg.soft_reset;
return ret;
@@ -831,11 +936,14 @@ int32_t lis2dw12_boot_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dw12_ctrl2_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.boot = val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -852,7 +960,7 @@ int32_t lis2dw12_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dw12_ctrl2_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
*val = reg.boot;
return ret;
@@ -871,10 +979,12 @@ int32_t lis2dw12_self_test_set(stmdev_ctx_t *ctx, lis2dw12_st_t val)
lis2dw12_ctrl3_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.st = (uint8_t) val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1);
}
return ret;
@@ -893,22 +1003,27 @@ int32_t lis2dw12_self_test_get(stmdev_ctx_t *ctx, lis2dw12_st_t *val)
lis2dw12_ctrl3_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1);
- switch (reg.st) {
+ switch (reg.st)
+ {
case LIS2DW12_XL_ST_DISABLE:
*val = LIS2DW12_XL_ST_DISABLE;
break;
+
case LIS2DW12_XL_ST_POSITIVE:
*val = LIS2DW12_XL_ST_POSITIVE;
break;
+
case LIS2DW12_XL_ST_NEGATIVE:
*val = LIS2DW12_XL_ST_NEGATIVE;
break;
+
default:
*val = LIS2DW12_XL_ST_DISABLE;
break;
}
+
return ret;
}
@@ -926,10 +1041,12 @@ int32_t lis2dw12_data_ready_mode_set(stmdev_ctx_t *ctx,
lis2dw12_ctrl_reg7_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.drdy_pulsed = (uint8_t) val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
}
return ret;
@@ -949,19 +1066,23 @@ int32_t lis2dw12_data_ready_mode_get(stmdev_ctx_t *ctx,
lis2dw12_ctrl_reg7_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
- switch (reg.drdy_pulsed) {
+ switch (reg.drdy_pulsed)
+ {
case LIS2DW12_DRDY_LATCHED:
*val = LIS2DW12_DRDY_LATCHED;
break;
+
case LIS2DW12_DRDY_PULSED:
*val = LIS2DW12_DRDY_PULSED;
break;
+
default:
*val = LIS2DW12_DRDY_LATCHED;
break;
}
+
return ret;
}
@@ -986,23 +1107,32 @@ int32_t lis2dw12_data_ready_mode_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dw12_filter_path_set(stmdev_ctx_t *ctx, lis2dw12_fds_t val)
+int32_t lis2dw12_filter_path_set(stmdev_ctx_t *ctx,
+ lis2dw12_fds_t val)
{
lis2dw12_ctrl6_t ctrl6;
lis2dw12_ctrl_reg7_t ctrl_reg7;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) &ctrl6, 1);
- if (ret == 0) {
- ctrl6.fds = ( (uint8_t) val & 0x10U ) >> 4;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) &ctrl6, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1);
+
+ if (ret == 0)
+ {
+ ctrl6.fds = ((uint8_t) val & 0x10U) >> 4;
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1);
}
- if (ret == 0) {
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) &ctrl_reg7, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,
+ (uint8_t *) &ctrl_reg7, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ctrl_reg7.usr_off_on_out = (uint8_t) val & 0x01U;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) &ctrl_reg7, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7,
+ (uint8_t *) &ctrl_reg7, 1);
}
return ret;
@@ -1016,31 +1146,40 @@ int32_t lis2dw12_filter_path_set(stmdev_ctx_t *ctx, lis2dw12_fds_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dw12_filter_path_get(stmdev_ctx_t *ctx, lis2dw12_fds_t *val)
+int32_t lis2dw12_filter_path_get(stmdev_ctx_t *ctx,
+ lis2dw12_fds_t *val)
{
lis2dw12_ctrl6_t ctrl6;
lis2dw12_ctrl_reg7_t ctrl_reg7;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) &ctrl6, 1);
- if (ret == 0) {
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) &ctrl_reg7, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1);
- switch ((ctrl6.fds << 4 ) + ctrl_reg7.usr_off_on_out) {
+ if (ret == 0)
+ {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,
+ (uint8_t *) &ctrl_reg7, 1);
+
+ switch ((ctrl6.fds << 4) + ctrl_reg7.usr_off_on_out)
+ {
case LIS2DW12_LPF_ON_OUT:
*val = LIS2DW12_LPF_ON_OUT;
break;
+
case LIS2DW12_USER_OFFSET_ON_OUT:
*val = LIS2DW12_USER_OFFSET_ON_OUT;
break;
+
case LIS2DW12_HIGH_PASS_ON_OUT:
*val = LIS2DW12_HIGH_PASS_ON_OUT;
break;
+
default:
*val = LIS2DW12_LPF_ON_OUT;
break;
}
}
+
return ret;
}
@@ -1054,15 +1193,17 @@ int32_t lis2dw12_filter_path_get(stmdev_ctx_t *ctx, lis2dw12_fds_t *val)
*
*/
int32_t lis2dw12_filter_bandwidth_set(stmdev_ctx_t *ctx,
- lis2dw12_bw_filt_t val)
+ lis2dw12_bw_filt_t val)
{
lis2dw12_ctrl6_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.bw_filt = (uint8_t) val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) ®, 1);
}
return ret;
@@ -1078,30 +1219,36 @@ int32_t lis2dw12_filter_bandwidth_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis2dw12_filter_bandwidth_get(stmdev_ctx_t *ctx,
- lis2dw12_bw_filt_t *val)
+ lis2dw12_bw_filt_t *val)
{
lis2dw12_ctrl6_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) ®, 1);
- switch (reg.bw_filt) {
+ switch (reg.bw_filt)
+ {
case LIS2DW12_ODR_DIV_2:
*val = LIS2DW12_ODR_DIV_2;
break;
+
case LIS2DW12_ODR_DIV_4:
*val = LIS2DW12_ODR_DIV_4;
break;
+
case LIS2DW12_ODR_DIV_10:
*val = LIS2DW12_ODR_DIV_10;
break;
+
case LIS2DW12_ODR_DIV_20:
*val = LIS2DW12_ODR_DIV_20;
break;
+
default:
*val = LIS2DW12_ODR_DIV_2;
break;
}
+
return ret;
}
@@ -1118,11 +1265,14 @@ int32_t lis2dw12_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dw12_ctrl_reg7_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.hp_ref_mode = val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1139,7 +1289,7 @@ int32_t lis2dw12_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dw12_ctrl_reg7_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
*val = reg.hp_ref_mode;
return ret;
@@ -1171,11 +1321,14 @@ int32_t lis2dw12_spi_mode_set(stmdev_ctx_t *ctx, lis2dw12_sim_t val)
lis2dw12_ctrl2_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.sim = (uint8_t) val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1192,19 +1345,23 @@ int32_t lis2dw12_spi_mode_get(stmdev_ctx_t *ctx, lis2dw12_sim_t *val)
lis2dw12_ctrl2_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
- switch (reg.sim) {
+ switch (reg.sim)
+ {
case LIS2DW12_SPI_4_WIRE:
*val = LIS2DW12_SPI_4_WIRE;
break;
+
case LIS2DW12_SPI_3_WIRE:
*val = LIS2DW12_SPI_3_WIRE;
break;
+
default:
*val = LIS2DW12_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -1223,11 +1380,14 @@ int32_t lis2dw12_i2c_interface_set(stmdev_ctx_t *ctx,
lis2dw12_ctrl2_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.i2c_disable = (uint8_t) val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1245,19 +1405,23 @@ int32_t lis2dw12_i2c_interface_get(stmdev_ctx_t *ctx,
lis2dw12_ctrl2_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
- switch (reg.i2c_disable) {
+ switch (reg.i2c_disable)
+ {
case LIS2DW12_I2C_ENABLE:
*val = LIS2DW12_I2C_ENABLE;
break;
+
case LIS2DW12_I2C_DISABLE:
*val = LIS2DW12_I2C_DISABLE;
break;
+
default:
*val = LIS2DW12_I2C_ENABLE;
break;
}
+
return ret;
}
@@ -1269,16 +1433,20 @@ int32_t lis2dw12_i2c_interface_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dw12_cs_mode_set(stmdev_ctx_t *ctx, lis2dw12_cs_pu_disc_t val)
+int32_t lis2dw12_cs_mode_set(stmdev_ctx_t *ctx,
+ lis2dw12_cs_pu_disc_t val)
{
lis2dw12_ctrl2_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.cs_pu_disc = (uint8_t) val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1290,24 +1458,29 @@ int32_t lis2dw12_cs_mode_set(stmdev_ctx_t *ctx, lis2dw12_cs_pu_disc_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dw12_cs_mode_get(stmdev_ctx_t *ctx, lis2dw12_cs_pu_disc_t *val)
+int32_t lis2dw12_cs_mode_get(stmdev_ctx_t *ctx,
+ lis2dw12_cs_pu_disc_t *val)
{
lis2dw12_ctrl2_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
- switch (reg.cs_pu_disc) {
+ switch (reg.cs_pu_disc)
+ {
case LIS2DW12_PULL_UP_CONNECT:
*val = LIS2DW12_PULL_UP_CONNECT;
break;
+
case LIS2DW12_PULL_UP_DISCONNECT:
*val = LIS2DW12_PULL_UP_DISCONNECT;
break;
+
default:
*val = LIS2DW12_PULL_UP_CONNECT;
break;
}
+
return ret;
}
@@ -1337,11 +1510,14 @@ int32_t lis2dw12_pin_polarity_set(stmdev_ctx_t *ctx,
lis2dw12_ctrl3_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.h_lactive = (uint8_t) val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1359,19 +1535,23 @@ int32_t lis2dw12_pin_polarity_get(stmdev_ctx_t *ctx,
lis2dw12_ctrl3_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1);
- switch (reg.h_lactive) {
+ switch (reg.h_lactive)
+ {
case LIS2DW12_ACTIVE_HIGH:
*val = LIS2DW12_ACTIVE_HIGH;
break;
+
case LIS2DW12_ACTIVE_LOW:
*val = LIS2DW12_ACTIVE_LOW;
break;
+
default:
*val = LIS2DW12_ACTIVE_HIGH;
break;
}
+
return ret;
}
@@ -1389,11 +1569,14 @@ int32_t lis2dw12_int_notification_set(stmdev_ctx_t *ctx,
lis2dw12_ctrl3_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.lir = (uint8_t) val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1411,19 +1594,23 @@ int32_t lis2dw12_int_notification_get(stmdev_ctx_t *ctx,
lis2dw12_ctrl3_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1);
- switch (reg.lir) {
+ switch (reg.lir)
+ {
case LIS2DW12_INT_PULSED:
*val = LIS2DW12_INT_PULSED;
break;
+
case LIS2DW12_INT_LATCHED:
*val = LIS2DW12_INT_LATCHED;
break;
+
default:
*val = LIS2DW12_INT_PULSED;
break;
}
+
return ret;
}
@@ -1440,11 +1627,14 @@ int32_t lis2dw12_pin_mode_set(stmdev_ctx_t *ctx, lis2dw12_pp_od_t val)
lis2dw12_ctrl3_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.pp_od = (uint8_t) val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1456,24 +1646,29 @@ int32_t lis2dw12_pin_mode_set(stmdev_ctx_t *ctx, lis2dw12_pp_od_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dw12_pin_mode_get(stmdev_ctx_t *ctx, lis2dw12_pp_od_t *val)
+int32_t lis2dw12_pin_mode_get(stmdev_ctx_t *ctx,
+ lis2dw12_pp_od_t *val)
{
lis2dw12_ctrl3_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1);
- switch (reg.pp_od) {
+ switch (reg.pp_od)
+ {
case LIS2DW12_PUSH_PULL:
*val = LIS2DW12_PUSH_PULL;
break;
+
case LIS2DW12_OPEN_DRAIN:
*val = LIS2DW12_OPEN_DRAIN;
break;
+
default:
*val = LIS2DW12_PUSH_PULL;
break;
}
+
return ret;
}
@@ -1493,30 +1688,40 @@ int32_t lis2dw12_pin_int1_route_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL5_INT2_PAD_CTRL,
- (uint8_t*)&ctrl5_int2_pad_ctrl, 1);
+ (uint8_t *)&ctrl5_int2_pad_ctrl, 1);
- if (ret == 0) {
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1);
+ if (ret == 0)
+ {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
if ((val->int1_tap |
val->int1_ff |
val->int1_wu |
val->int1_single_tap |
val->int1_6d |
ctrl5_int2_pad_ctrl.int2_sleep_state |
- ctrl5_int2_pad_ctrl.int2_sleep_chg ) != PROPERTY_DISABLE){
+ ctrl5_int2_pad_ctrl.int2_sleep_chg) != PROPERTY_DISABLE)
+ {
reg.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
reg.interrupts_enable = PROPERTY_DISABLE;
}
ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL4_INT1_PAD_CTRL,
- (uint8_t*) val, 1);
- } if (ret == 0) {
- ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1);
+ (uint8_t *) val, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1532,8 +1737,10 @@ int32_t lis2dw12_pin_int1_route_get(stmdev_ctx_t *ctx,
lis2dw12_ctrl4_int1_pad_ctrl_t *val)
{
int32_t ret;
+
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL4_INT1_PAD_CTRL,
- (uint8_t*) val, 1);
+ (uint8_t *) val, 1);
+
return ret;
}
@@ -1553,29 +1760,37 @@ int32_t lis2dw12_pin_int2_route_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL4_INT1_PAD_CTRL,
- (uint8_t*) &ctrl4_int1_pad_ctrl, 1);
+ (uint8_t *) &ctrl4_int1_pad_ctrl, 1);
- if (ret == 0) {
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1);
+ if (ret == 0)
+ {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
if ((ctrl4_int1_pad_ctrl.int1_tap |
ctrl4_int1_pad_ctrl.int1_ff |
ctrl4_int1_pad_ctrl.int1_wu |
ctrl4_int1_pad_ctrl.int1_single_tap |
ctrl4_int1_pad_ctrl.int1_6d |
- val->int2_sleep_state | val->int2_sleep_chg ) != PROPERTY_DISABLE) {
- reg.interrupts_enable = PROPERTY_ENABLE;
+ val->int2_sleep_state | val->int2_sleep_chg) != PROPERTY_DISABLE)
+ {
+ reg.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
reg.interrupts_enable = PROPERTY_DISABLE;
}
ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL5_INT2_PAD_CTRL,
- (uint8_t*) val, 1);
+ (uint8_t *) val, 1);
}
- if (ret == 0) {
- ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
}
return ret;
@@ -1593,8 +1808,10 @@ int32_t lis2dw12_pin_int2_route_get(stmdev_ctx_t *ctx,
lis2dw12_ctrl5_int2_pad_ctrl_t *val)
{
int32_t ret;
+
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL5_INT2_PAD_CTRL,
- (uint8_t*) val, 1);
+ (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1610,11 +1827,14 @@ int32_t lis2dw12_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dw12_ctrl_reg7_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.int2_on_int1 = val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1631,7 +1851,7 @@ int32_t lis2dw12_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dw12_ctrl_reg7_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
*val = reg.int2_on_int1;
return ret;
@@ -1663,11 +1883,14 @@ int32_t lis2dw12_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dw12_wake_up_ths_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.wk_ths = val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_THS,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_THS, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1684,7 +1907,7 @@ int32_t lis2dw12_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dw12_wake_up_ths_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS, (uint8_t *) ®, 1);
*val = reg.wk_ths;
return ret;
@@ -1703,11 +1926,14 @@ int32_t lis2dw12_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dw12_wake_up_dur_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.wake_dur = val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1724,7 +1950,7 @@ int32_t lis2dw12_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dw12_wake_up_dur_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
*val = reg.wake_dur;
return ret;
@@ -1744,11 +1970,14 @@ int32_t lis2dw12_wkup_feed_data_set(stmdev_ctx_t *ctx,
lis2dw12_ctrl_reg7_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.usr_off_on_wu = (uint8_t) val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1766,19 +1995,23 @@ int32_t lis2dw12_wkup_feed_data_get(stmdev_ctx_t *ctx,
lis2dw12_ctrl_reg7_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
- switch (reg.usr_off_on_wu) {
+ switch (reg.usr_off_on_wu)
+ {
case LIS2DW12_HP_FEED:
*val = LIS2DW12_HP_FEED;
break;
+
case LIS2DW12_USER_OFFSET_FEED:
*val = LIS2DW12_USER_OFFSET_FEED;
break;
+
default:
*val = LIS2DW12_HP_FEED;
break;
}
+
return ret;
}
@@ -1805,23 +2038,34 @@ int32_t lis2dw12_wkup_feed_data_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dw12_act_mode_set(stmdev_ctx_t *ctx, lis2dw12_sleep_on_t val)
+int32_t lis2dw12_act_mode_set(stmdev_ctx_t *ctx,
+ lis2dw12_sleep_on_t val)
{
lis2dw12_wake_up_ths_t wake_up_ths;
lis2dw12_wake_up_dur_t wake_up_dur;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS,(uint8_t*) &wake_up_ths, 1);
- if (ret == 0) {
- ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS,
+ (uint8_t *) &wake_up_ths, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,
+ (uint8_t *) &wake_up_dur, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
wake_up_ths.sleep_on = (uint8_t) val & 0x01U;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_THS,(uint8_t*) &wake_up_ths, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_THS,
+ (uint8_t *) &wake_up_ths, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
wake_up_dur.stationary = ((uint8_t)val & 0x02U) >> 1;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_DUR,
+ (uint8_t *) &wake_up_dur, 1);
}
return ret;
@@ -1836,31 +2080,41 @@ int32_t lis2dw12_act_mode_set(stmdev_ctx_t *ctx, lis2dw12_sleep_on_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dw12_act_mode_get(stmdev_ctx_t *ctx, lis2dw12_sleep_on_t *val)
+int32_t lis2dw12_act_mode_get(stmdev_ctx_t *ctx,
+ lis2dw12_sleep_on_t *val)
{
lis2dw12_wake_up_ths_t wake_up_ths;
lis2dw12_wake_up_dur_t wake_up_dur;;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS,(uint8_t*) &wake_up_ths, 1);
- if (ret == 0) {
- ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS,
+ (uint8_t *) &wake_up_ths, 1);
- switch ((wake_up_dur.stationary << 1) + wake_up_ths.sleep_on){
+ if (ret == 0)
+ {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,
+ (uint8_t *) &wake_up_dur, 1);
+
+ switch ((wake_up_dur.stationary << 1) + wake_up_ths.sleep_on)
+ {
case LIS2DW12_NO_DETECTION:
*val = LIS2DW12_NO_DETECTION;
break;
+
case LIS2DW12_DETECT_ACT_INACT:
*val = LIS2DW12_DETECT_ACT_INACT;
break;
+
case LIS2DW12_DETECT_STAT_MOTION:
*val = LIS2DW12_DETECT_STAT_MOTION;
break;
+
default:
*val = LIS2DW12_NO_DETECTION;
break;
}
}
+
return ret;
}
@@ -1877,11 +2131,14 @@ int32_t lis2dw12_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dw12_wake_up_dur_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.sleep_dur = val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1898,7 +2155,7 @@ int32_t lis2dw12_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dw12_wake_up_dur_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
*val = reg.sleep_dur;
return ret;
@@ -1930,11 +2187,14 @@ int32_t lis2dw12_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dw12_tap_ths_x_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.tap_thsx = val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_X,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1951,7 +2211,7 @@ int32_t lis2dw12_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dw12_tap_ths_x_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) ®, 1);
*val = reg.tap_thsx;
return ret;
@@ -1970,11 +2230,14 @@ int32_t lis2dw12_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dw12_tap_ths_y_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.tap_thsy = val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Y,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Y, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1991,7 +2254,7 @@ int32_t lis2dw12_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dw12_tap_ths_y_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y, (uint8_t *) ®, 1);
*val = reg.tap_thsy;
return ret;
@@ -2011,11 +2274,14 @@ int32_t lis2dw12_tap_axis_priority_set(stmdev_ctx_t *ctx,
lis2dw12_tap_ths_y_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.tap_prior = (uint8_t) val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Y,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Y, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -2033,31 +2299,39 @@ int32_t lis2dw12_tap_axis_priority_get(stmdev_ctx_t *ctx,
lis2dw12_tap_ths_y_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y, (uint8_t *) ®, 1);
- switch (reg.tap_prior) {
+ switch (reg.tap_prior)
+ {
case LIS2DW12_XYZ:
*val = LIS2DW12_XYZ;
break;
+
case LIS2DW12_YXZ:
*val = LIS2DW12_YXZ;
break;
+
case LIS2DW12_XZY:
*val = LIS2DW12_XZY;
break;
+
case LIS2DW12_ZYX:
*val = LIS2DW12_ZYX;
break;
+
case LIS2DW12_YZX:
*val = LIS2DW12_YZX;
break;
+
case LIS2DW12_ZXY:
*val = LIS2DW12_ZXY;
break;
+
default:
*val = LIS2DW12_XYZ;
break;
}
+
return ret;
}
@@ -2074,10 +2348,12 @@ int32_t lis2dw12_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dw12_tap_ths_z_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.tap_thsz = val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1);
}
return ret;
@@ -2096,7 +2372,7 @@ int32_t lis2dw12_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dw12_tap_ths_z_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1);
*val = reg.tap_thsz;
return ret;
@@ -2110,16 +2386,20 @@ int32_t lis2dw12_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dw12_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lis2dw12_tap_detection_on_z_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lis2dw12_tap_ths_z_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.tap_z_en = val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -2131,12 +2411,13 @@ int32_t lis2dw12_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dw12_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2dw12_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2dw12_tap_ths_z_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1);
*val = reg.tap_z_en;
return ret;
@@ -2150,16 +2431,20 @@ int32_t lis2dw12_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dw12_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lis2dw12_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lis2dw12_tap_ths_z_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.tap_y_en = val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -2171,12 +2456,13 @@ int32_t lis2dw12_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dw12_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2dw12_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2dw12_tap_ths_z_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1);
*val = reg.tap_y_en;
return ret;
@@ -2190,16 +2476,20 @@ int32_t lis2dw12_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dw12_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lis2dw12_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lis2dw12_tap_ths_z_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.tap_x_en = val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -2211,12 +2501,13 @@ int32_t lis2dw12_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dw12_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2dw12_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2dw12_tap_ths_z_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1);
*val = reg.tap_x_en;
return ret;
@@ -2239,10 +2530,12 @@ int32_t lis2dw12_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dw12_int_dur_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.shock = val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_INT_DUR,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) ®, 1);
}
return ret;
@@ -2265,7 +2558,7 @@ int32_t lis2dw12_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dw12_int_dur_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) ®, 1);
*val = reg.shock;
return ret;
@@ -2288,11 +2581,14 @@ int32_t lis2dw12_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dw12_int_dur_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.quiet = val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_INT_DUR,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -2313,7 +2609,7 @@ int32_t lis2dw12_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dw12_int_dur_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) ®, 1);
*val = reg.quiet;
return ret;
@@ -2337,11 +2633,14 @@ int32_t lis2dw12_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dw12_int_dur_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.latency = val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_INT_DUR,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -2363,7 +2662,7 @@ int32_t lis2dw12_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dw12_int_dur_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) ®, 1);
*val = reg.latency;
return ret;
@@ -2383,11 +2682,14 @@ int32_t lis2dw12_tap_mode_set(stmdev_ctx_t *ctx,
lis2dw12_wake_up_ths_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.single_double_tap = (uint8_t) val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_THS,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_THS, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -2405,15 +2707,18 @@ int32_t lis2dw12_tap_mode_get(stmdev_ctx_t *ctx,
lis2dw12_wake_up_ths_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS, (uint8_t *) ®, 1);
- switch (reg.single_double_tap) {
+ switch (reg.single_double_tap)
+ {
case LIS2DW12_ONLY_SINGLE:
*val = LIS2DW12_ONLY_SINGLE;
break;
+
case LIS2DW12_BOTH_SINGLE_DOUBLE:
*val = LIS2DW12_BOTH_SINGLE_DOUBLE;
break;
+
default:
*val = LIS2DW12_ONLY_SINGLE;
break;
@@ -2430,10 +2735,13 @@ int32_t lis2dw12_tap_mode_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dw12_tap_src_get(stmdev_ctx_t *ctx, lis2dw12_tap_src_t *val)
+int32_t lis2dw12_tap_src_get(stmdev_ctx_t *ctx,
+ lis2dw12_tap_src_t *val)
{
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_SRC, (uint8_t*) val, 1);
+
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_SRC, (uint8_t *) val, 1);
+
return ret;
}
@@ -2463,11 +2771,14 @@ int32_t lis2dw12_6d_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dw12_tap_ths_x_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg._6d_ths = val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_X,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -2484,7 +2795,7 @@ int32_t lis2dw12_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dw12_tap_ths_x_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) ®, 1);
*val = reg._6d_ths;
return ret;
@@ -2503,10 +2814,12 @@ int32_t lis2dw12_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dw12_tap_ths_x_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg._4d_en = val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_X,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) ®, 1);
}
return ret;
@@ -2525,7 +2838,7 @@ int32_t lis2dw12_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dw12_tap_ths_x_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) ®, 1);
*val = reg._4d_en;
return ret;
@@ -2539,10 +2852,13 @@ int32_t lis2dw12_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dw12_6d_src_get(stmdev_ctx_t *ctx, lis2dw12_sixd_src_t *val)
+int32_t lis2dw12_6d_src_get(stmdev_ctx_t *ctx,
+ lis2dw12_sixd_src_t *val)
{
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_SIXD_SRC, (uint8_t*) val, 1);
+
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_SIXD_SRC, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -2559,11 +2875,14 @@ int32_t lis2dw12_6d_feed_data_set(stmdev_ctx_t *ctx,
lis2dw12_ctrl_reg7_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.lpass_on6d = (uint8_t) val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -2581,19 +2900,23 @@ int32_t lis2dw12_6d_feed_data_get(stmdev_ctx_t *ctx,
lis2dw12_ctrl_reg7_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
- switch (reg.lpass_on6d) {
+ switch (reg.lpass_on6d)
+ {
case LIS2DW12_ODR_DIV_2_FEED:
*val = LIS2DW12_ODR_DIV_2_FEED;
break;
+
case LIS2DW12_LPF2_FEED:
*val = LIS2DW12_LPF2_FEED;
break;
+
default:
*val = LIS2DW12_ODR_DIV_2_FEED;
break;
}
+
return ret;
}
@@ -2625,17 +2948,27 @@ int32_t lis2dw12_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dw12_free_fall_t free_fall;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
- if (ret == 0) {
- ret = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL,(uint8_t*) &free_fall, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,
+ (uint8_t *) &wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL,
+ (uint8_t *) &free_fall, 1);
}
- if(ret == 0) {
- wake_up_dur.ff_dur = ( (uint8_t) val & 0x20U) >> 5;
+
+ if (ret == 0)
+ {
+ wake_up_dur.ff_dur = ((uint8_t) val & 0x20U) >> 5;
free_fall.ff_dur = (uint8_t) val & 0x1FU;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_DUR,
+ (uint8_t *) &wake_up_dur, 1);
}
- if(ret == 0) {
- ret = lis2dw12_write_reg(ctx, LIS2DW12_FREE_FALL,(uint8_t*) &free_fall, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_FREE_FALL,
+ (uint8_t *) &free_fall, 1);
}
return ret;
@@ -2656,11 +2989,16 @@ int32_t lis2dw12_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dw12_free_fall_t free_fall;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
- if (ret == 0) {
- ret = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL,(uint8_t*) &free_fall, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,
+ (uint8_t *) &wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL,
+ (uint8_t *) &free_fall, 1);
*val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
}
+
return ret;
}
@@ -2672,15 +3010,18 @@ int32_t lis2dw12_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dw12_ff_threshold_set(stmdev_ctx_t *ctx, lis2dw12_ff_ths_t val)
+int32_t lis2dw12_ff_threshold_set(stmdev_ctx_t *ctx,
+ lis2dw12_ff_ths_t val)
{
lis2dw12_free_fall_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.ff_ths = (uint8_t) val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_FREE_FALL,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_FREE_FALL, (uint8_t *) ®, 1);
}
return ret;
@@ -2700,37 +3041,47 @@ int32_t lis2dw12_ff_threshold_get(stmdev_ctx_t *ctx,
lis2dw12_free_fall_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL, (uint8_t *) ®, 1);
- switch (reg.ff_ths) {
+ switch (reg.ff_ths)
+ {
case LIS2DW12_FF_TSH_5LSb_FS2g:
*val = LIS2DW12_FF_TSH_5LSb_FS2g;
break;
+
case LIS2DW12_FF_TSH_7LSb_FS2g:
*val = LIS2DW12_FF_TSH_7LSb_FS2g;
break;
+
case LIS2DW12_FF_TSH_8LSb_FS2g:
*val = LIS2DW12_FF_TSH_8LSb_FS2g;
break;
+
case LIS2DW12_FF_TSH_10LSb_FS2g:
*val = LIS2DW12_FF_TSH_10LSb_FS2g;
break;
+
case LIS2DW12_FF_TSH_11LSb_FS2g:
*val = LIS2DW12_FF_TSH_11LSb_FS2g;
break;
+
case LIS2DW12_FF_TSH_13LSb_FS2g:
*val = LIS2DW12_FF_TSH_13LSb_FS2g;
break;
+
case LIS2DW12_FF_TSH_15LSb_FS2g:
*val = LIS2DW12_FF_TSH_15LSb_FS2g;
break;
+
case LIS2DW12_FF_TSH_16LSb_FS2g:
*val = LIS2DW12_FF_TSH_16LSb_FS2g;
break;
+
default:
*val = LIS2DW12_FF_TSH_5LSb_FS2g;
break;
}
+
return ret;
}
@@ -2759,10 +3110,12 @@ int32_t lis2dw12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
lis2dw12_fifo_ctrl_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.fth = val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_FIFO_CTRL,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1);
}
return ret;
@@ -2781,7 +3134,7 @@ int32_t lis2dw12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dw12_fifo_ctrl_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1);
*val = reg.fth;
return ret;
@@ -2795,16 +3148,20 @@ int32_t lis2dw12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dw12_fifo_mode_set(stmdev_ctx_t *ctx, lis2dw12_fmode_t val)
+int32_t lis2dw12_fifo_mode_set(stmdev_ctx_t *ctx,
+ lis2dw12_fmode_t val)
{
lis2dw12_fifo_ctrl_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.fmode = (uint8_t) val;
- ret = lis2dw12_write_reg(ctx, LIS2DW12_FIFO_CTRL,(uint8_t*) ®, 1);
+ ret = lis2dw12_write_reg(ctx, LIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -2816,33 +3173,41 @@ int32_t lis2dw12_fifo_mode_set(stmdev_ctx_t *ctx, lis2dw12_fmode_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2dw12_fifo_mode_get(stmdev_ctx_t *ctx, lis2dw12_fmode_t *val)
+int32_t lis2dw12_fifo_mode_get(stmdev_ctx_t *ctx,
+ lis2dw12_fmode_t *val)
{
lis2dw12_fifo_ctrl_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1);
- switch (reg.fmode) {
+ switch (reg.fmode)
+ {
case LIS2DW12_BYPASS_MODE:
*val = LIS2DW12_BYPASS_MODE;
break;
+
case LIS2DW12_FIFO_MODE:
*val = LIS2DW12_FIFO_MODE;
break;
+
case LIS2DW12_STREAM_TO_FIFO_MODE:
*val = LIS2DW12_STREAM_TO_FIFO_MODE;
break;
+
case LIS2DW12_BYPASS_TO_STREAM_MODE:
*val = LIS2DW12_BYPASS_TO_STREAM_MODE;
break;
+
case LIS2DW12_STREAM_MODE:
*val = LIS2DW12_STREAM_MODE;
break;
+
default:
*val = LIS2DW12_BYPASS_MODE;
break;
}
+
return ret;
}
@@ -2859,7 +3224,7 @@ int32_t lis2dw12_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dw12_fifo_samples_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_SAMPLES,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_SAMPLES, (uint8_t *) ®, 1);
*val = reg.diff;
return ret;
@@ -2877,7 +3242,7 @@ int32_t lis2dw12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dw12_fifo_samples_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_SAMPLES,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_SAMPLES, (uint8_t *) ®, 1);
*val = reg.fifo_ovr;
return ret;
@@ -2895,7 +3260,7 @@ int32_t lis2dw12_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2dw12_fifo_samples_t reg;
int32_t ret;
- ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_SAMPLES,(uint8_t*) ®, 1);
+ ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_SAMPLES, (uint8_t *) ®, 1);
*val = reg.fifo_fth;
return ret;
diff --git a/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.h b/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.h
index a12807d1c326598a83f95e038d4c8677539f432f..21e2185574580d635027837248166e65921d2dcf 100644
--- a/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.h
+++ b/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file lis2dw12_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lis2dw12_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lis2dw12_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lis2dw12_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LIS2DW12_REGS_H
#define LIS2DW12_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup LIS2DW12
@@ -74,7 +75,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -107,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -131,15 +134,16 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
- * Unico / Unicleo tools available on STMicroelectronics
- * web site.
+ * You can create a sensor configuration by your own or using
+ * Unico / Unicleo tools available on STMicroelectronics
+ * web site.
*
* @{
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -177,7 +181,8 @@ typedef struct {
#define LIS2DW12_OUT_T_H 0x0EU
#define LIS2DW12_WHO_AM_I 0x0FU
#define LIS2DW12_CTRL1 0x20U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lp_mode : 2;
uint8_t mode : 2;
@@ -191,7 +196,8 @@ typedef struct {
} lis2dw12_ctrl1_t;
#define LIS2DW12_CTRL2 0x21U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t i2c_disable : 1;
@@ -215,9 +221,11 @@ typedef struct {
} lis2dw12_ctrl2_t;
#define LIS2DW12_CTRL3 0x22U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t slp_mode : 2; /* slp_mode_sel + slp_mode_1 */
+uint8_t slp_mode :
+ 2; /* slp_mode_sel + slp_mode_1 */
uint8_t not_used_01 : 1;
uint8_t h_lactive : 1;
uint8_t lir : 1;
@@ -229,13 +237,15 @@ typedef struct {
uint8_t lir : 1;
uint8_t h_lactive : 1;
uint8_t not_used_01 : 1;
- uint8_t slp_mode : 2; /* slp_mode_sel + slp_mode_1 */
+uint8_t slp_mode :
+ 2; /* slp_mode_sel + slp_mode_1 */
#endif /* DRV_BYTE_ORDER */
} lis2dw12_ctrl3_t;
#define LIS2DW12_CTRL4_INT1_PAD_CTRL 0x23U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_drdy : 1;
uint8_t int1_fth : 1;
@@ -258,7 +268,8 @@ typedef struct {
} lis2dw12_ctrl4_int1_pad_ctrl_t;
#define LIS2DW12_CTRL5_INT2_PAD_CTRL 0x24U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_drdy : 1;
uint8_t int2_fth : 1;
@@ -281,7 +292,8 @@ typedef struct {
} lis2dw12_ctrl5_int2_pad_ctrl_t;
#define LIS2DW12_CTRL6 0x25U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t low_noise : 1;
@@ -299,7 +311,8 @@ typedef struct {
#define LIS2DW12_OUT_T 0x26U
#define LIS2DW12_STATUS 0x27U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t drdy : 1;
uint8_t ff_ia : 1;
@@ -328,7 +341,8 @@ typedef struct {
#define LIS2DW12_OUT_Z_L 0x2CU
#define LIS2DW12_OUT_Z_H 0x2DU
#define LIS2DW12_FIFO_CTRL 0x2EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fth : 5;
uint8_t fmode : 3;
@@ -339,7 +353,8 @@ typedef struct {
} lis2dw12_fifo_ctrl_t;
#define LIS2DW12_FIFO_SAMPLES 0x2FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t diff : 6;
uint8_t fifo_ovr : 1;
@@ -352,7 +367,8 @@ typedef struct {
} lis2dw12_fifo_samples_t;
#define LIS2DW12_TAP_THS_X 0x30U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_thsx : 5;
uint8_t _6d_ths : 2;
@@ -365,7 +381,8 @@ typedef struct {
} lis2dw12_tap_ths_x_t;
#define LIS2DW12_TAP_THS_Y 0x31U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_thsy : 5;
uint8_t tap_prior : 3;
@@ -376,7 +393,8 @@ typedef struct {
} lis2dw12_tap_ths_y_t;
#define LIS2DW12_TAP_THS_Z 0x32U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_thsz : 5;
uint8_t tap_z_en : 1;
@@ -391,7 +409,8 @@ typedef struct {
} lis2dw12_tap_ths_z_t;
#define LIS2DW12_INT_DUR 0x33U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shock : 2;
uint8_t quiet : 2;
@@ -404,7 +423,8 @@ typedef struct {
} lis2dw12_int_dur_t;
#define LIS2DW12_WAKE_UP_THS 0x34U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wk_ths : 6;
uint8_t sleep_on : 1;
@@ -417,7 +437,8 @@ typedef struct {
} lis2dw12_wake_up_ths_t;
#define LIS2DW12_WAKE_UP_DUR 0x35U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sleep_dur : 4;
uint8_t stationary : 1;
@@ -432,7 +453,8 @@ typedef struct {
} lis2dw12_wake_up_dur_t;
#define LIS2DW12_FREE_FALL 0x36U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ths : 3;
uint8_t ff_dur : 5;
@@ -443,7 +465,8 @@ typedef struct {
} lis2dw12_free_fall_t;
#define LIS2DW12_STATUS_DUP 0x37U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t drdy : 1;
uint8_t ff_ia : 1;
@@ -466,7 +489,8 @@ typedef struct {
} lis2dw12_status_dup_t;
#define LIS2DW12_WAKE_UP_SRC 0x38U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_wu : 1;
uint8_t y_wu : 1;
@@ -487,7 +511,8 @@ typedef struct {
} lis2dw12_wake_up_src_t;
#define LIS2DW12_TAP_SRC 0x39U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_tap : 1;
uint8_t y_tap : 1;
@@ -510,7 +535,8 @@ typedef struct {
} lis2dw12_tap_src_t;
#define LIS2DW12_SIXD_SRC 0x3AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
@@ -534,7 +560,8 @@ typedef struct {
} lis2dw12_sixd_src_t;
#define LIS2DW12_ALL_INT_SRC 0x3BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ia : 1;
uint8_t wu_ia : 1;
@@ -558,7 +585,8 @@ typedef struct {
#define LIS2DW12_Y_OFS_USR 0x3DU
#define LIS2DW12_Z_OFS_USR 0x3EU
#define LIS2DW12_CTRL_REG7 0x3FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lpass_on6d : 1;
uint8_t hp_ref_mode : 1;
@@ -582,9 +610,9 @@ typedef struct {
/**
* @defgroup LIS2DW12_Register_Union
- * @brief This union group all the registers that has a bitfield
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -592,7 +620,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
lis2dw12_ctrl1_t ctrl1;
lis2dw12_ctrl2_t ctrl2;
lis2dw12_ctrl3_t ctrl3;
@@ -624,22 +653,27 @@ typedef union{
*
*/
-int32_t lis2dw12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lis2dw12_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t lis2dw12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lis2dw12_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
float_t lis2dw12_from_fs2_to_mg(int16_t lsb);
float_t lis2dw12_from_fs4_to_mg(int16_t lsb);
float_t lis2dw12_from_fs8_to_mg(int16_t lsb);
float_t lis2dw12_from_fs16_to_mg(int16_t lsb);
+
float_t lis2dw12_from_fs2_lp1_to_mg(int16_t lsb);
float_t lis2dw12_from_fs4_lp1_to_mg(int16_t lsb);
float_t lis2dw12_from_fs8_lp1_to_mg(int16_t lsb);
float_t lis2dw12_from_fs16_lp1_to_mg(int16_t lsb);
+
float_t lis2dw12_from_lsb_to_celsius(int16_t lsb);
-typedef enum {
+typedef enum
+{
LIS2DW12_HIGH_PERFORMANCE = 0x04,
LIS2DW12_CONT_LOW_PWR_4 = 0x03,
LIS2DW12_CONT_LOW_PWR_3 = 0x02,
@@ -659,10 +693,13 @@ typedef enum {
LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_2 = 0x19,
LIS2DW12_SINGLE_LOW_LOW_NOISE_PWR_12bit = 0x18,
} lis2dw12_mode_t;
-int32_t lis2dw12_power_mode_set(stmdev_ctx_t *ctx, lis2dw12_mode_t val);
-int32_t lis2dw12_power_mode_get(stmdev_ctx_t *ctx, lis2dw12_mode_t *val);
+int32_t lis2dw12_power_mode_set(stmdev_ctx_t *ctx,
+ lis2dw12_mode_t val);
+int32_t lis2dw12_power_mode_get(stmdev_ctx_t *ctx,
+ lis2dw12_mode_t *val);
-typedef enum {
+typedef enum
+{
LIS2DW12_XL_ODR_OFF = 0x00,
LIS2DW12_XL_ODR_1Hz6_LP_ONLY = 0x01,
LIS2DW12_XL_ODR_12Hz5 = 0x02,
@@ -677,25 +714,32 @@ typedef enum {
LIS2DW12_XL_SET_PIN_TRIG = 0x12, /* Use this only in SINGLE mode */
} lis2dw12_odr_t;
int32_t lis2dw12_data_rate_set(stmdev_ctx_t *ctx, lis2dw12_odr_t val);
-int32_t lis2dw12_data_rate_get(stmdev_ctx_t *ctx, lis2dw12_odr_t *val);
+int32_t lis2dw12_data_rate_get(stmdev_ctx_t *ctx,
+ lis2dw12_odr_t *val);
-int32_t lis2dw12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2dw12_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2dw12_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2dw12_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DW12_2g = 0,
LIS2DW12_4g = 1,
LIS2DW12_8g = 2,
LIS2DW12_16g = 3,
} lis2dw12_fs_t;
int32_t lis2dw12_full_scale_set(stmdev_ctx_t *ctx, lis2dw12_fs_t val);
-int32_t lis2dw12_full_scale_get(stmdev_ctx_t *ctx, lis2dw12_fs_t *val);
+int32_t lis2dw12_full_scale_get(stmdev_ctx_t *ctx,
+ lis2dw12_fs_t *val);
-int32_t lis2dw12_status_reg_get(stmdev_ctx_t *ctx, lis2dw12_status_t *val);
+int32_t lis2dw12_status_reg_get(stmdev_ctx_t *ctx,
+ lis2dw12_status_t *val);
int32_t lis2dw12_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef struct{
+typedef struct
+{
lis2dw12_status_dup_t status_dup;
lis2dw12_wake_up_src_t wake_up_src;
lis2dw12_tap_src_t tap_src;
@@ -714,18 +758,20 @@ int32_t lis2dw12_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t lis2dw12_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t lis2dw12_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff);
-typedef enum {
+typedef enum
+{
LIS2DW12_LSb_977ug = 0,
LIS2DW12_LSb_15mg6 = 1,
} lis2dw12_usr_off_w_t;
int32_t lis2dw12_offset_weight_set(stmdev_ctx_t *ctx,
- lis2dw12_usr_off_w_t val);
+ lis2dw12_usr_off_w_t val);
int32_t lis2dw12_offset_weight_get(stmdev_ctx_t *ctx,
- lis2dw12_usr_off_w_t *val);
+ lis2dw12_usr_off_w_t *val);
int32_t lis2dw12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val);
-int32_t lis2dw12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t lis2dw12_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
int32_t lis2dw12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
@@ -738,7 +784,8 @@ int32_t lis2dw12_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2dw12_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dw12_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DW12_XL_ST_DISABLE = 0,
LIS2DW12_XL_ST_POSITIVE = 1,
LIS2DW12_XL_ST_NEGATIVE = 2,
@@ -746,7 +793,8 @@ typedef enum {
int32_t lis2dw12_self_test_set(stmdev_ctx_t *ctx, lis2dw12_st_t val);
int32_t lis2dw12_self_test_get(stmdev_ctx_t *ctx, lis2dw12_st_t *val);
-typedef enum {
+typedef enum
+{
LIS2DW12_DRDY_LATCHED = 0,
LIS2DW12_DRDY_PULSED = 1,
} lis2dw12_drdy_pulsed_t;
@@ -755,36 +803,42 @@ int32_t lis2dw12_data_ready_mode_set(stmdev_ctx_t *ctx,
int32_t lis2dw12_data_ready_mode_get(stmdev_ctx_t *ctx,
lis2dw12_drdy_pulsed_t *val);
-typedef enum {
+typedef enum
+{
LIS2DW12_LPF_ON_OUT = 0x00,
LIS2DW12_USER_OFFSET_ON_OUT = 0x01,
LIS2DW12_HIGH_PASS_ON_OUT = 0x10,
} lis2dw12_fds_t;
-int32_t lis2dw12_filter_path_set(stmdev_ctx_t *ctx, lis2dw12_fds_t val);
-int32_t lis2dw12_filter_path_get(stmdev_ctx_t *ctx, lis2dw12_fds_t *val);
+int32_t lis2dw12_filter_path_set(stmdev_ctx_t *ctx,
+ lis2dw12_fds_t val);
+int32_t lis2dw12_filter_path_get(stmdev_ctx_t *ctx,
+ lis2dw12_fds_t *val);
-typedef enum {
+typedef enum
+{
LIS2DW12_ODR_DIV_2 = 0,
LIS2DW12_ODR_DIV_4 = 1,
LIS2DW12_ODR_DIV_10 = 2,
LIS2DW12_ODR_DIV_20 = 3,
} lis2dw12_bw_filt_t;
int32_t lis2dw12_filter_bandwidth_set(stmdev_ctx_t *ctx,
- lis2dw12_bw_filt_t val);
+ lis2dw12_bw_filt_t val);
int32_t lis2dw12_filter_bandwidth_get(stmdev_ctx_t *ctx,
- lis2dw12_bw_filt_t *val);
+ lis2dw12_bw_filt_t *val);
int32_t lis2dw12_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dw12_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DW12_SPI_4_WIRE = 0,
LIS2DW12_SPI_3_WIRE = 1,
} lis2dw12_sim_t;
int32_t lis2dw12_spi_mode_set(stmdev_ctx_t *ctx, lis2dw12_sim_t val);
int32_t lis2dw12_spi_mode_get(stmdev_ctx_t *ctx, lis2dw12_sim_t *val);
-typedef enum {
+typedef enum
+{
LIS2DW12_I2C_ENABLE = 0,
LIS2DW12_I2C_DISABLE = 1,
} lis2dw12_i2c_disable_t;
@@ -793,14 +847,18 @@ int32_t lis2dw12_i2c_interface_set(stmdev_ctx_t *ctx,
int32_t lis2dw12_i2c_interface_get(stmdev_ctx_t *ctx,
lis2dw12_i2c_disable_t *val);
-typedef enum {
+typedef enum
+{
LIS2DW12_PULL_UP_CONNECT = 0,
LIS2DW12_PULL_UP_DISCONNECT = 1,
} lis2dw12_cs_pu_disc_t;
-int32_t lis2dw12_cs_mode_set(stmdev_ctx_t *ctx, lis2dw12_cs_pu_disc_t val);
-int32_t lis2dw12_cs_mode_get(stmdev_ctx_t *ctx, lis2dw12_cs_pu_disc_t *val);
+int32_t lis2dw12_cs_mode_set(stmdev_ctx_t *ctx,
+ lis2dw12_cs_pu_disc_t val);
+int32_t lis2dw12_cs_mode_get(stmdev_ctx_t *ctx,
+ lis2dw12_cs_pu_disc_t *val);
-typedef enum {
+typedef enum
+{
LIS2DW12_ACTIVE_HIGH = 0,
LIS2DW12_ACTIVE_LOW = 1,
} lis2dw12_h_lactive_t;
@@ -809,7 +867,8 @@ int32_t lis2dw12_pin_polarity_set(stmdev_ctx_t *ctx,
int32_t lis2dw12_pin_polarity_get(stmdev_ctx_t *ctx,
lis2dw12_h_lactive_t *val);
-typedef enum {
+typedef enum
+{
LIS2DW12_INT_PULSED = 0,
LIS2DW12_INT_LATCHED = 1,
} lis2dw12_lir_t;
@@ -818,12 +877,15 @@ int32_t lis2dw12_int_notification_set(stmdev_ctx_t *ctx,
int32_t lis2dw12_int_notification_get(stmdev_ctx_t *ctx,
lis2dw12_lir_t *val);
-typedef enum {
+typedef enum
+{
LIS2DW12_PUSH_PULL = 0,
LIS2DW12_OPEN_DRAIN = 1,
} lis2dw12_pp_od_t;
-int32_t lis2dw12_pin_mode_set(stmdev_ctx_t *ctx, lis2dw12_pp_od_t val);
-int32_t lis2dw12_pin_mode_get(stmdev_ctx_t *ctx, lis2dw12_pp_od_t *val);
+int32_t lis2dw12_pin_mode_set(stmdev_ctx_t *ctx,
+ lis2dw12_pp_od_t val);
+int32_t lis2dw12_pin_mode_get(stmdev_ctx_t *ctx,
+ lis2dw12_pp_od_t *val);
int32_t lis2dw12_pin_int1_route_set(stmdev_ctx_t *ctx,
lis2dw12_ctrl4_int1_pad_ctrl_t *val);
@@ -844,7 +906,8 @@ int32_t lis2dw12_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2dw12_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dw12_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DW12_HP_FEED = 0,
LIS2DW12_USER_OFFSET_FEED = 1,
} lis2dw12_usr_off_on_wu_t;
@@ -853,13 +916,16 @@ int32_t lis2dw12_wkup_feed_data_set(stmdev_ctx_t *ctx,
int32_t lis2dw12_wkup_feed_data_get(stmdev_ctx_t *ctx,
lis2dw12_usr_off_on_wu_t *val);
-typedef enum {
+typedef enum
+{
LIS2DW12_NO_DETECTION = 0,
LIS2DW12_DETECT_ACT_INACT = 1,
LIS2DW12_DETECT_STAT_MOTION = 3,
} lis2dw12_sleep_on_t;
-int32_t lis2dw12_act_mode_set(stmdev_ctx_t *ctx, lis2dw12_sleep_on_t val);
-int32_t lis2dw12_act_mode_get(stmdev_ctx_t *ctx, lis2dw12_sleep_on_t *val);
+int32_t lis2dw12_act_mode_set(stmdev_ctx_t *ctx,
+ lis2dw12_sleep_on_t val);
+int32_t lis2dw12_act_mode_get(stmdev_ctx_t *ctx,
+ lis2dw12_sleep_on_t *val);
int32_t lis2dw12_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dw12_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -870,7 +936,8 @@ int32_t lis2dw12_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2dw12_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dw12_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DW12_XYZ = 0,
LIS2DW12_YXZ = 1,
LIS2DW12_XZY = 2,
@@ -886,14 +953,20 @@ int32_t lis2dw12_tap_axis_priority_get(stmdev_ctx_t *ctx,
int32_t lis2dw12_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dw12_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lis2dw12_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2dw12_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2dw12_tap_detection_on_z_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2dw12_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lis2dw12_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2dw12_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2dw12_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2dw12_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lis2dw12_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2dw12_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2dw12_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2dw12_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lis2dw12_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dw12_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -904,7 +977,8 @@ int32_t lis2dw12_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2dw12_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dw12_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DW12_ONLY_SINGLE = 0,
LIS2DW12_BOTH_SINGLE_DOUBLE = 1,
} lis2dw12_single_double_tap_t;
@@ -913,7 +987,8 @@ int32_t lis2dw12_tap_mode_set(stmdev_ctx_t *ctx,
int32_t lis2dw12_tap_mode_get(stmdev_ctx_t *ctx,
lis2dw12_single_double_tap_t *val);
-int32_t lis2dw12_tap_src_get(stmdev_ctx_t *ctx, lis2dw12_tap_src_t *val);
+int32_t lis2dw12_tap_src_get(stmdev_ctx_t *ctx,
+ lis2dw12_tap_src_t *val);
int32_t lis2dw12_6d_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dw12_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -921,9 +996,11 @@ int32_t lis2dw12_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2dw12_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dw12_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lis2dw12_6d_src_get(stmdev_ctx_t *ctx, lis2dw12_sixd_src_t *val);
+int32_t lis2dw12_6d_src_get(stmdev_ctx_t *ctx,
+ lis2dw12_sixd_src_t *val);
-typedef enum {
+typedef enum
+{
LIS2DW12_ODR_DIV_2_FEED = 0,
LIS2DW12_LPF2_FEED = 1,
} lis2dw12_lpass_on6d_t;
@@ -935,7 +1012,8 @@ int32_t lis2dw12_6d_feed_data_get(stmdev_ctx_t *ctx,
int32_t lis2dw12_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dw12_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DW12_FF_TSH_5LSb_FS2g = 0,
LIS2DW12_FF_TSH_7LSb_FS2g = 1,
LIS2DW12_FF_TSH_8LSb_FS2g = 2,
@@ -953,15 +1031,18 @@ int32_t lis2dw12_ff_threshold_get(stmdev_ctx_t *ctx,
int32_t lis2dw12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dw12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2DW12_BYPASS_MODE = 0,
LIS2DW12_FIFO_MODE = 1,
LIS2DW12_STREAM_TO_FIFO_MODE = 3,
LIS2DW12_BYPASS_TO_STREAM_MODE = 4,
LIS2DW12_STREAM_MODE = 6,
} lis2dw12_fmode_t;
-int32_t lis2dw12_fifo_mode_set(stmdev_ctx_t *ctx, lis2dw12_fmode_t val);
-int32_t lis2dw12_fifo_mode_get(stmdev_ctx_t *ctx, lis2dw12_fmode_t *val);
+int32_t lis2dw12_fifo_mode_set(stmdev_ctx_t *ctx,
+ lis2dw12_fmode_t val);
+int32_t lis2dw12_fifo_mode_get(stmdev_ctx_t *ctx,
+ lis2dw12_fmode_t *val);
int32_t lis2dw12_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val);
diff --git a/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.c b/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.c
index 926d0cdae8d62aae9bfdd0ba5e9c67bb19787147..c08ea0c0bdb896147929682f2f1ed850002ec55b 100644
--- a/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.c
+++ b/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file lis2hh12_reg.c
- * @author Sensors Software Solution Team
- * @brief LIS2HH12 driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lis2hh12_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LIS2HH12 driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lis2hh12_reg.h"
/**
@@ -45,11 +45,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2hh12_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t lis2hh12_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -63,11 +66,14 @@ int32_t lis2hh12_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2hh12_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lis2hh12_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -85,17 +91,17 @@ int32_t lis2hh12_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
float_t lis2hh12_from_fs2g_to_mg(int16_t lsb)
{
- return ((float_t)lsb *0.061f);
+ return ((float_t)lsb * 0.061f);
}
float_t lis2hh12_from_fs4g_to_mg(int16_t lsb)
{
- return ((float_t)lsb *0.122f);
+ return ((float_t)lsb * 0.122f);
}
float_t lis2hh12_from_fs8g_to_mg(int16_t lsb)
{
- return ((float_t)lsb *0.244f);
+ return ((float_t)lsb * 0.244f);
}
float_t lis2hh12_from_lsb_to_celsius(int16_t lsb)
@@ -124,18 +130,22 @@ float_t lis2hh12_from_lsb_to_celsius(int16_t lsb)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2hh12_xl_axis_set(stmdev_ctx_t *ctx, lis2hh12_xl_axis_t val)
+int32_t lis2hh12_xl_axis_set(stmdev_ctx_t *ctx,
+ lis2hh12_xl_axis_t val)
{
lis2hh12_ctrl1_t ctrl1;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL1, (uint8_t*)&ctrl1, 1);
- if(ret == 0) {
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL1, (uint8_t *)&ctrl1, 1);
+
+ if (ret == 0)
+ {
ctrl1.xen = val.xen;
ctrl1.yen = val.yen;
ctrl1.zen = val.zen;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL1, (uint8_t*)&ctrl1, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL1, (uint8_t *)&ctrl1, 1);
}
+
return ret;
}
@@ -147,12 +157,13 @@ int32_t lis2hh12_xl_axis_set(stmdev_ctx_t *ctx, lis2hh12_xl_axis_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2hh12_xl_axis_get(stmdev_ctx_t *ctx, lis2hh12_xl_axis_t *val)
+int32_t lis2hh12_xl_axis_get(stmdev_ctx_t *ctx,
+ lis2hh12_xl_axis_t *val)
{
lis2hh12_ctrl1_t ctrl1;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL1, (uint8_t*)&ctrl1, 1);
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL1, (uint8_t *)&ctrl1, 1);
val->xen = ctrl1.xen;
val->yen = ctrl1.yen;
val->zen = ctrl1.zen;
@@ -173,11 +184,14 @@ int32_t lis2hh12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
lis2hh12_ctrl1_t ctrl1;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL1, (uint8_t*)&ctrl1, 1);
- if(ret == 0){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL1, (uint8_t *)&ctrl1, 1);
+
+ if (ret == 0)
+ {
ctrl1.bdu = (uint8_t)val;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL1, (uint8_t*)&ctrl1, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL1, (uint8_t *)&ctrl1, 1);
}
+
return ret;
}
@@ -189,12 +203,13 @@ int32_t lis2hh12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2hh12_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2hh12_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2hh12_ctrl1_t ctrl1;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL1, (uint8_t*)&ctrl1, 1);
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL1, (uint8_t *)&ctrl1, 1);
*val = (uint8_t)ctrl1.bdu;
return ret;
@@ -214,11 +229,14 @@ int32_t lis2hh12_xl_data_rate_set(stmdev_ctx_t *ctx,
lis2hh12_ctrl1_t ctrl1;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL1, (uint8_t*)&ctrl1, 1);
- if(ret == 0){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL1, (uint8_t *)&ctrl1, 1);
+
+ if (ret == 0)
+ {
ctrl1.odr = (uint8_t)val;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL1, (uint8_t*)&ctrl1, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL1, (uint8_t *)&ctrl1, 1);
}
+
return ret;
}
@@ -236,33 +254,43 @@ int32_t lis2hh12_xl_data_rate_get(stmdev_ctx_t *ctx,
lis2hh12_ctrl1_t ctrl1;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL1, (uint8_t*)&ctrl1, 1);
- switch (ctrl1.odr){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL1, (uint8_t *)&ctrl1, 1);
+
+ switch (ctrl1.odr)
+ {
case LIS2HH12_XL_ODR_OFF:
*val = LIS2HH12_XL_ODR_OFF;
break;
+
case LIS2HH12_XL_ODR_10Hz:
*val = LIS2HH12_XL_ODR_10Hz;
break;
+
case LIS2HH12_XL_ODR_50Hz:
*val = LIS2HH12_XL_ODR_50Hz;
break;
+
case LIS2HH12_XL_ODR_100Hz:
*val = LIS2HH12_XL_ODR_100Hz;
break;
+
case LIS2HH12_XL_ODR_200Hz:
*val = LIS2HH12_XL_ODR_200Hz;
break;
+
case LIS2HH12_XL_ODR_400Hz:
*val = LIS2HH12_XL_ODR_400Hz;
break;
+
case LIS2HH12_XL_ODR_800Hz:
*val = LIS2HH12_XL_ODR_800Hz;
break;
+
default:
*val = LIS2HH12_XL_ODR_OFF;
break;
}
+
return ret;
}
@@ -280,11 +308,14 @@ int32_t lis2hh12_xl_full_scale_set(stmdev_ctx_t *ctx,
lis2hh12_ctrl4_t ctrl4;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t*)&ctrl4, 1);
- if(ret == 0){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1);
+
+ if (ret == 0)
+ {
ctrl4.fs = (uint8_t)val;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL4, (uint8_t*)&ctrl4, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1);
}
+
return ret;
}
@@ -302,21 +333,27 @@ int32_t lis2hh12_xl_full_scale_get(stmdev_ctx_t *ctx,
lis2hh12_ctrl4_t ctrl4;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t*)&ctrl4, 1);
- switch (ctrl4.fs){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1);
+
+ switch (ctrl4.fs)
+ {
case LIS2HH12_2g:
*val = LIS2HH12_2g;
break;
+
case LIS2HH12_4g:
*val = LIS2HH12_4g;
break;
+
case LIS2HH12_8g:
*val = LIS2HH12_8g;
break;
+
default:
*val = LIS2HH12_2g;
break;
}
+
return ret;
}
@@ -328,16 +365,20 @@ int32_t lis2hh12_xl_full_scale_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2hh12_xl_decimation_set(stmdev_ctx_t *ctx, lis2hh12_dec_t val)
+int32_t lis2hh12_xl_decimation_set(stmdev_ctx_t *ctx,
+ lis2hh12_dec_t val)
{
lis2hh12_ctrl5_t ctrl5;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t*)&ctrl5, 1);
- if(ret == 0){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1);
+
+ if (ret == 0)
+ {
ctrl5.dec = (uint8_t)val;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL5, (uint8_t*)&ctrl5, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1);
}
+
return ret;
}
@@ -349,29 +390,37 @@ int32_t lis2hh12_xl_decimation_set(stmdev_ctx_t *ctx, lis2hh12_dec_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2hh12_xl_decimation_get(stmdev_ctx_t *ctx, lis2hh12_dec_t *val)
+int32_t lis2hh12_xl_decimation_get(stmdev_ctx_t *ctx,
+ lis2hh12_dec_t *val)
{
lis2hh12_ctrl5_t ctrl5;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t*)&ctrl5, 1);
- switch (ctrl5.dec){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1);
+
+ switch (ctrl5.dec)
+ {
case LIS2HH12_NO_DECIMATION:
*val = LIS2HH12_NO_DECIMATION;
break;
+
case LIS2HH12_EVERY_2_SAMPLES:
*val = LIS2HH12_EVERY_2_SAMPLES;
break;
+
case LIS2HH12_EVERY_4_SAMPLES:
*val = LIS2HH12_EVERY_4_SAMPLES;
break;
+
case LIS2HH12_EVERY_8_SAMPLES:
*val = LIS2HH12_EVERY_8_SAMPLES;
break;
+
default:
*val = LIS2HH12_NO_DECIMATION;
break;
}
+
return ret;
}
@@ -383,12 +432,13 @@ int32_t lis2hh12_xl_decimation_get(stmdev_ctx_t *ctx, lis2hh12_dec_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2hh12_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2hh12_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2hh12_status_t status;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_STATUS, (uint8_t*)&status, 1);
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_STATUS, (uint8_t *)&status, 1);
*val = status.zyxda;
return ret;
@@ -422,7 +472,7 @@ int32_t lis2hh12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
ret = lis2hh12_read_reg(ctx, LIS2HH12_TEMP_L, buff, 2);
*val = (int16_t)buff[1];
- *val = (*val * 256) + (int16_t)buff[0];
+ *val = (*val * 256) + (int16_t)buff[0];
return ret;
}
@@ -443,11 +493,11 @@ int32_t lis2hh12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
ret = lis2hh12_read_reg(ctx, LIS2HH12_OUT_X_L, buff, 6);
val[0] = (int16_t)buff[1];
- val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
- val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
val[2] = (int16_t)buff[5];
- val[2] = (val[2] * 256) + (int16_t)buff[4];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
return ret;
}
@@ -459,7 +509,7 @@ int32_t lis2hh12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
/**
* @defgroup LIS2HH12_Common
- * @brief This section groups common usefull functions.
+ * @brief This section groups common useful functions.
* @{
*
*/
@@ -475,7 +525,9 @@ int32_t lis2hh12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
int32_t lis2hh12_dev_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis2hh12_read_reg(ctx, LIS2HH12_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -493,11 +545,14 @@ int32_t lis2hh12_dev_reset_set(stmdev_ctx_t *ctx, uint8_t val)
lis2hh12_ctrl5_t ctrl5;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t*)&ctrl5, 1);
- if(ret == 0){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1);
+
+ if (ret == 0)
+ {
ctrl5.soft_reset = (uint8_t)val;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL5, (uint8_t*)&ctrl5, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1);
}
+
return ret;
}
@@ -515,7 +570,7 @@ int32_t lis2hh12_dev_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2hh12_ctrl5_t ctrl5;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t*)&ctrl5, 1);
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1);
*val = (uint8_t)ctrl5.soft_reset;
return ret;
@@ -534,11 +589,14 @@ int32_t lis2hh12_dev_boot_set(stmdev_ctx_t *ctx, uint8_t val)
lis2hh12_ctrl6_t ctrl6;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL6, (uint8_t*)&ctrl6, 1);
- if(ret == 0){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL6, (uint8_t *)&ctrl6, 1);
+
+ if (ret == 0)
+ {
ctrl6.boot = (uint8_t)val;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL6, (uint8_t*)&ctrl6, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL6, (uint8_t *)&ctrl6, 1);
}
+
return ret;
}
@@ -555,7 +613,7 @@ int32_t lis2hh12_dev_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2hh12_ctrl6_t ctrl6;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL6, (uint8_t*)&ctrl6, 1);
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL6, (uint8_t *)&ctrl6, 1);
*val = (uint8_t)ctrl6.boot;
return ret;
@@ -575,7 +633,7 @@ int32_t lis2hh12_dev_status_get(stmdev_ctx_t *ctx,
lis2hh12_status_t status;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_STATUS, (uint8_t*)&status, 1);
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_STATUS, (uint8_t *)&status, 1);
val->xda = status.xda;
val->yda = status.yda;
val->zda = status.zda;
@@ -615,11 +673,14 @@ int32_t lis2hh12_xl_filter_int_path_set(stmdev_ctx_t *ctx,
lis2hh12_ctrl2_t ctrl2;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL2, (uint8_t*)&ctrl2, 1);
- if(ret == 0){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL2, (uint8_t *)&ctrl2, 1);
+
+ if (ret == 0)
+ {
ctrl2.hpis = (uint8_t)val;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL2, (uint8_t*)&ctrl2, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL2, (uint8_t *)&ctrl2, 1);
}
+
return ret;
}
@@ -637,21 +698,27 @@ int32_t lis2hh12_xl_filter_int_path_get(stmdev_ctx_t *ctx,
lis2hh12_ctrl2_t ctrl2;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL2, (uint8_t*)&ctrl2, 1);
- switch (ctrl2.hpis){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL2, (uint8_t *)&ctrl2, 1);
+
+ switch (ctrl2.hpis)
+ {
case LIS2HH12_HP_DISABLE:
*val = LIS2HH12_HP_DISABLE;
break;
+
case LIS2HH12_HP_ON_INT_GEN_1:
*val = LIS2HH12_HP_ON_INT_GEN_1;
break;
+
case LIS2HH12_HP_ON_INT_GEN_2:
*val = LIS2HH12_HP_ON_INT_GEN_2;
break;
+
default:
*val = LIS2HH12_HP_DISABLE;
break;
}
+
return ret;
}
@@ -668,22 +735,27 @@ int32_t lis2hh12_xl_filter_out_path_set(stmdev_ctx_t *ctx,
{
lis2hh12_ctrl1_t ctrl1;
lis2hh12_ctrl2_t ctrl2;
-
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL1, (uint8_t*)&ctrl1, 1);
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL1, (uint8_t *)&ctrl1, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl1.hr = (uint8_t)val;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL1, (uint8_t*)&ctrl1, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL1, (uint8_t *)&ctrl1, 1);
}
- if(ret == 0){
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL2, (uint8_t*)&ctrl2, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL2, (uint8_t *)&ctrl2, 1);
}
- if(ret == 0){
- ctrl2.fds = ( (uint8_t) val & 0x02U ) >> 1;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL2, (uint8_t*)&ctrl2, 1);
+
+ if (ret == 0)
+ {
+ ctrl2.fds = ((uint8_t) val & 0x02U) >> 1;
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL2, (uint8_t *)&ctrl2, 1);
}
+
return ret;
}
@@ -702,26 +774,32 @@ int32_t lis2hh12_xl_filter_out_path_get(stmdev_ctx_t *ctx,
lis2hh12_ctrl2_t ctrl2;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL1, (uint8_t*)&ctrl1, 1);
- if(ret == 0){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL1, (uint8_t *)&ctrl1, 1);
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL2, (uint8_t*)&ctrl2, 1);
+ if (ret == 0)
+ {
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL2, (uint8_t *)&ctrl2, 1);
- switch ((ctrl2.fds << 1) | ctrl1.hr){
+ switch ((ctrl2.fds << 1) | ctrl1.hr)
+ {
case LIS2HH12_BYPASSED:
*val = LIS2HH12_BYPASSED;
break;
+
case LIS2HH12_FILT_HP:
*val = LIS2HH12_FILT_HP;
break;
+
case LIS2HH12_FILT_LP:
*val = LIS2HH12_FILT_LP;
break;
+
default:
*val = LIS2HH12_BYPASSED;
break;
}
}
+
return ret;
}
@@ -740,12 +818,15 @@ int32_t lis2hh12_xl_filter_hp_bandwidth_set(stmdev_ctx_t *ctx,
lis2hh12_ctrl2_t ctrl2;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL2, (uint8_t*)&ctrl2, 1);
- if(ret == 0){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL2, (uint8_t *)&ctrl2, 1);
+
+ if (ret == 0)
+ {
ctrl2.hpm = (uint8_t) val & 0x01U;
- ctrl2.dfc = (((uint8_t) val & 0x30U )>> 4);
- ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL2, (uint8_t*)&ctrl2, 1);
+ ctrl2.dfc = (((uint8_t) val & 0x30U) >> 4);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL2, (uint8_t *)&ctrl2, 1);
}
+
return ret;
}
@@ -764,36 +845,47 @@ int32_t lis2hh12_xl_filter_hp_bandwidth_get(stmdev_ctx_t *ctx,
lis2hh12_ctrl2_t ctrl2;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL2, (uint8_t*)&ctrl2, 1);
- switch ((ctrl2.dfc << 4) | ctrl2.hpm){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL2, (uint8_t *)&ctrl2, 1);
+
+ switch ((ctrl2.dfc << 4) | ctrl2.hpm)
+ {
case LIS2HH12_HP_ODR_DIV_50:
*val = LIS2HH12_HP_ODR_DIV_50;
break;
+
case LIS2HH12_HP_ODR_DIV_100:
*val = LIS2HH12_HP_ODR_DIV_100;
break;
+
case LIS2HH12_HP_ODR_DIV_9:
*val = LIS2HH12_HP_ODR_DIV_9;
break;
+
case LIS2HH12_HP_ODR_DIV_400:
*val = LIS2HH12_HP_ODR_DIV_400;
break;
+
case LIS2HH12_HP_ODR_DIV_50_REF_MD:
*val = LIS2HH12_HP_ODR_DIV_50_REF_MD;
break;
+
case LIS2HH12_HP_ODR_DIV_100_REF_MD:
*val = LIS2HH12_HP_ODR_DIV_100_REF_MD;
break;
+
case LIS2HH12_HP_ODR_DIV_9_REF_MD:
*val = LIS2HH12_HP_ODR_DIV_9_REF_MD;
break;
+
case LIS2HH12_HP_ODR_DIV_400_REF_MD:
*val = LIS2HH12_HP_ODR_DIV_400_REF_MD;
break;
+
default:
*val = LIS2HH12_HP_ODR_DIV_50;
break;
}
+
return ret;
}
@@ -812,11 +904,14 @@ int32_t lis2hh12_xl_filter_low_bandwidth_set(stmdev_ctx_t *ctx,
lis2hh12_ctrl2_t ctrl2;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL2, (uint8_t*)&ctrl2, 1);
- if(ret == 0){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL2, (uint8_t *)&ctrl2, 1);
+
+ if (ret == 0)
+ {
ctrl2.dfc = (uint8_t)val;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL2, (uint8_t*)&ctrl2, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL2, (uint8_t *)&ctrl2, 1);
}
+
return ret;
}
@@ -835,24 +930,31 @@ int32_t lis2hh12_xl_filter_low_bandwidth_get(stmdev_ctx_t *ctx,
lis2hh12_ctrl2_t ctrl2;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL2, (uint8_t*)&ctrl2, 1);
- switch (ctrl2.dfc){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL2, (uint8_t *)&ctrl2, 1);
+
+ switch (ctrl2.dfc)
+ {
case LIS2HH12_LP_ODR_DIV_50:
*val = LIS2HH12_LP_ODR_DIV_50;
break;
+
case LIS2HH12_LP_ODR_DIV_100:
*val = LIS2HH12_LP_ODR_DIV_100;
break;
+
case LIS2HH12_LP_ODR_DIV_9:
*val = LIS2HH12_LP_ODR_DIV_9;
break;
+
case LIS2HH12_LP_ODR_DIV_400:
*val = LIS2HH12_LP_ODR_DIV_400;
break;
+
default:
*val = LIS2HH12_LP_ODR_DIV_50;
break;
}
+
return ret;
}
@@ -870,12 +972,15 @@ int32_t lis2hh12_xl_filter_aalias_bandwidth_set(stmdev_ctx_t *ctx,
lis2hh12_ctrl4_t ctrl4;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t*)&ctrl4, 1);
- if(ret == 0){
- ctrl4.bw_scale_odr = ((( uint8_t) val & 0x10U ) >> 4);
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1);
+
+ if (ret == 0)
+ {
+ ctrl4.bw_scale_odr = (((uint8_t) val & 0x10U) >> 4);
ctrl4.bw = (uint8_t)val;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL4, (uint8_t*)&ctrl4, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1);
}
+
return ret;
}
@@ -893,27 +998,35 @@ int32_t lis2hh12_xl_filter_aalias_bandwidth_get(stmdev_ctx_t *ctx,
lis2hh12_ctrl4_t ctrl4;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t*)&ctrl4, 1);
- switch ( (ctrl4.bw_scale_odr << 4) | ctrl4.bw){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1);
+
+ switch ((ctrl4.bw_scale_odr << 4) | ctrl4.bw)
+ {
case LIS2HH12_AUTO:
*val = LIS2HH12_AUTO;
break;
+
case LIS2HH12_408Hz:
*val = LIS2HH12_408Hz;
break;
+
case LIS2HH12_211Hz:
*val = LIS2HH12_211Hz;
break;
+
case LIS2HH12_105Hz:
*val = LIS2HH12_105Hz;
break;
+
case LIS2HH12_50Hz:
*val = LIS2HH12_50Hz;
- break;
+ break;
+
default:
*val = LIS2HH12_AUTO;
break;
}
+
return ret;
}
@@ -925,17 +1038,18 @@ int32_t lis2hh12_xl_filter_aalias_bandwidth_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2hh12_xl_filter_reference_set(stmdev_ctx_t *ctx, int16_t *val)
+int32_t lis2hh12_xl_filter_reference_set(stmdev_ctx_t *ctx,
+ int16_t *val)
{
uint8_t buff[6];
int32_t ret;
- buff[1] = (uint8_t) ((uint16_t)val[0] / 256U);
- buff[0] = (uint8_t) ((uint16_t)val[0] - (buff[1] * 256U));
- buff[3] = (uint8_t) ((uint16_t)val[1] / 256U);
- buff[2] = (uint8_t) ((uint16_t)val[1] - (buff[3] * 256U));
- buff[5] = (uint8_t) ((uint16_t)val[2] / 256U);
- buff[4] = (uint8_t) ((uint16_t)val[2] - (buff[5] * 256U));
+ buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
+ buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
+ buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
+ buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
+ buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
+ buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
ret = lis2hh12_write_reg(ctx, LIS2HH12_XL_REFERENCE, buff, 6);
return ret;
@@ -949,18 +1063,19 @@ int32_t lis2hh12_xl_filter_reference_set(stmdev_ctx_t *ctx, int16_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2hh12_xl_filter_reference_get(stmdev_ctx_t *ctx, int16_t *val)
+int32_t lis2hh12_xl_filter_reference_get(stmdev_ctx_t *ctx,
+ int16_t *val)
{
uint8_t buff[6];
int32_t ret;
ret = lis2hh12_read_reg(ctx, LIS2HH12_XL_REFERENCE, buff, 6);
val[0] = (int16_t)buff[1];
- val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
- val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
val[2] = (int16_t)buff[5];
- val[2] = (val[2] * 256) + (int16_t)buff[4];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
return ret;
}
@@ -991,11 +1106,14 @@ int32_t lis2hh12_spi_mode_set(stmdev_ctx_t *ctx, lis2hh12_sim_t val)
lis2hh12_ctrl4_t ctrl4;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t*)&ctrl4, 1);
- if(ret == 0){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1);
+
+ if (ret == 0)
+ {
ctrl4.sim = (uint8_t)val;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL4, (uint8_t*)&ctrl4, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1);
}
+
return ret;
}
@@ -1012,18 +1130,23 @@ int32_t lis2hh12_spi_mode_get(stmdev_ctx_t *ctx, lis2hh12_sim_t *val)
lis2hh12_ctrl4_t ctrl4;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t*)&ctrl4, 1);
- switch (ctrl4.sim){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1);
+
+ switch (ctrl4.sim)
+ {
case LIS2HH12_SPI_4_WIRE:
*val = LIS2HH12_SPI_4_WIRE;
break;
+
case LIS2HH12_SPI_3_WIRE:
*val = LIS2HH12_SPI_3_WIRE;
break;
+
default:
*val = LIS2HH12_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -1041,11 +1164,14 @@ int32_t lis2hh12_i2c_interface_set(stmdev_ctx_t *ctx,
lis2hh12_ctrl4_t ctrl4;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t*)&ctrl4, 1);
- if(ret == 0){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1);
+
+ if (ret == 0)
+ {
ctrl4.i2c_disable = (uint8_t)val;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL4, (uint8_t*)&ctrl4, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1);
}
+
return ret;
}
@@ -1063,18 +1189,23 @@ int32_t lis2hh12_i2c_interface_get(stmdev_ctx_t *ctx,
lis2hh12_ctrl4_t ctrl4;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t*)&ctrl4, 1);
- switch (ctrl4.i2c_disable){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1);
+
+ switch (ctrl4.i2c_disable)
+ {
case LIS2HH12_I2C_ENABLE:
*val = LIS2HH12_I2C_ENABLE;
break;
+
case LIS2HH12_I2C_DISABLE:
*val = LIS2HH12_I2C_DISABLE;
break;
+
default:
*val = LIS2HH12_I2C_ENABLE;
break;
}
+
return ret;
}
@@ -1093,11 +1224,14 @@ int32_t lis2hh12_auto_increment_set(stmdev_ctx_t *ctx,
lis2hh12_ctrl4_t ctrl4;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t*)&ctrl4, 1);
- if(ret == 0){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1);
+
+ if (ret == 0)
+ {
ctrl4.if_add_inc = (uint8_t)val;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL4, (uint8_t*)&ctrl4, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1);
}
+
return ret;
}
@@ -1116,18 +1250,23 @@ int32_t lis2hh12_auto_increment_get(stmdev_ctx_t *ctx,
lis2hh12_ctrl4_t ctrl4;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t*)&ctrl4, 1);
- switch (ctrl4.if_add_inc){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1);
+
+ switch (ctrl4.if_add_inc)
+ {
case LIS2HH12_DISABLE:
*val = LIS2HH12_DISABLE;
break;
+
case LIS2HH12_ENABLE:
*val = LIS2HH12_ENABLE;
break;
+
default:
*val = LIS2HH12_DISABLE;
break;
}
+
return ret;
}
@@ -1158,16 +1297,19 @@ int32_t lis2hh12_pin_int1_route_set(stmdev_ctx_t *ctx,
lis2hh12_ctrl3_t ctrl3;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL3, (uint8_t*)&ctrl3, 1);
- if(ret == 0) {
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL3, (uint8_t *)&ctrl3, 1);
+
+ if (ret == 0)
+ {
ctrl3.int1_drdy = val.int1_drdy;
ctrl3.int1_fth = val.int1_fth;
ctrl3.int1_ovr = val.int1_ovr;
ctrl3.int1_ig1 = val.int1_ig1;
ctrl3.int1_ig2 = val.int1_ig2;
ctrl3.int1_inact = val.int1_inact;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL3, (uint8_t*)&ctrl3, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL3, (uint8_t *)&ctrl3, 1);
}
+
return ret;
}
@@ -1185,7 +1327,7 @@ int32_t lis2hh12_pin_int1_route_get(stmdev_ctx_t *ctx,
lis2hh12_ctrl3_t ctrl3;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL3, (uint8_t*)&ctrl3, 1);
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL3, (uint8_t *)&ctrl3, 1);
val->int1_drdy = ctrl3.int1_drdy;
val->int1_fth = ctrl3.int1_fth;
val->int1_ovr = ctrl3.int1_ovr;
@@ -1209,11 +1351,14 @@ int32_t lis2hh12_pin_mode_set(stmdev_ctx_t *ctx, lis2hh12_pp_od_t val)
lis2hh12_ctrl5_t ctrl5;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t*)&ctrl5, 1);
- if(ret == 0){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1);
+
+ if (ret == 0)
+ {
ctrl5.pp_od = (uint8_t)val;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL5, (uint8_t*)&ctrl5, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1);
}
+
return ret;
}
@@ -1225,23 +1370,29 @@ int32_t lis2hh12_pin_mode_set(stmdev_ctx_t *ctx, lis2hh12_pp_od_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2hh12_pin_mode_get(stmdev_ctx_t *ctx, lis2hh12_pp_od_t *val)
+int32_t lis2hh12_pin_mode_get(stmdev_ctx_t *ctx,
+ lis2hh12_pp_od_t *val)
{
lis2hh12_ctrl5_t ctrl5;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t*)&ctrl5, 1);
- switch (ctrl5.pp_od){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1);
+
+ switch (ctrl5.pp_od)
+ {
case LIS2HH12_PUSH_PULL:
*val = LIS2HH12_PUSH_PULL;
break;
+
case LIS2HH12_OPEN_DRAIN:
*val = LIS2HH12_OPEN_DRAIN;
break;
+
default:
*val = LIS2HH12_PUSH_PULL;
break;
}
+
return ret;
}
@@ -1259,11 +1410,14 @@ int32_t lis2hh12_pin_polarity_set(stmdev_ctx_t *ctx,
lis2hh12_ctrl5_t ctrl5;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t*)&ctrl5, 1);
- if(ret == 0){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1);
+
+ if (ret == 0)
+ {
ctrl5.h_lactive = (uint8_t)val;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL5, (uint8_t*)&ctrl5, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1);
}
+
return ret;
}
@@ -1281,18 +1435,23 @@ int32_t lis2hh12_pin_polarity_get(stmdev_ctx_t *ctx,
lis2hh12_ctrl5_t ctrl5;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t*)&ctrl5, 1);
- switch (ctrl5.h_lactive){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1);
+
+ switch (ctrl5.h_lactive)
+ {
case LIS2HH12_ACTIVE_HIGH:
*val = LIS2HH12_ACTIVE_HIGH;
break;
+
case LIS2HH12_ACTIVE_LOW:
*val = LIS2HH12_ACTIVE_LOW;
break;
+
default:
*val = LIS2HH12_ACTIVE_HIGH;
break;
}
+
return ret;
}
@@ -1310,16 +1469,19 @@ int32_t lis2hh12_pin_int2_route_set(stmdev_ctx_t *ctx,
lis2hh12_ctrl6_t ctrl6;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL6, (uint8_t*)&ctrl6, 1);
- if(ret == 0) {
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL6, (uint8_t *)&ctrl6, 1);
+
+ if (ret == 0)
+ {
ctrl6.int2_drdy = val.int2_drdy;
ctrl6.int2_fth = val.int2_fth;
ctrl6.int2_empty = val.int2_empty;
ctrl6.int2_ig1 = val.int2_ig1;
ctrl6.int2_ig2 = val.int2_ig2;
ctrl6.int2_boot = val.int2_boot;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL6, (uint8_t*)&ctrl6, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL6, (uint8_t *)&ctrl6, 1);
}
+
return ret;
}
@@ -1337,13 +1499,14 @@ int32_t lis2hh12_pin_int2_route_get(stmdev_ctx_t *ctx,
lis2hh12_ctrl6_t ctrl6;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL6, (uint8_t*)&ctrl6, 1);
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL6, (uint8_t *)&ctrl6, 1);
val->int2_drdy = ctrl6.int2_drdy;
val->int2_fth = ctrl6.int2_fth;
val->int2_empty = ctrl6.int2_empty;
val->int2_ig1 = ctrl6.int2_ig1;
val->int2_ig2 = ctrl6.int2_ig2;
val->int2_boot = ctrl6.int2_boot;
+
return ret;
}
@@ -1361,11 +1524,14 @@ int32_t lis2hh12_pin_notification_set(stmdev_ctx_t *ctx,
lis2hh12_ctrl7_t ctrl7;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL7, (uint8_t*)&ctrl7, 1);
- if(ret == 0){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL7, (uint8_t *)&ctrl7, 1);
+
+ if (ret == 0)
+ {
ctrl7.lir = (uint8_t)val;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL7, (uint8_t*)&ctrl7, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL7, (uint8_t *)&ctrl7, 1);
}
+
return ret;
}
@@ -1383,18 +1549,23 @@ int32_t lis2hh12_pin_notification_get(stmdev_ctx_t *ctx,
lis2hh12_ctrl7_t ctrl7;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL7, (uint8_t*)&ctrl7, 1);
- switch (ctrl7.lir){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL7, (uint8_t *)&ctrl7, 1);
+
+ switch (ctrl7.lir)
+ {
case LIS2HH12_INT_PULSED:
*val = LIS2HH12_INT_PULSED;
break;
+
case LIS2HH12_INT_LATCHED:
*val = LIS2HH12_INT_LATCHED;
break;
+
default:
*val = LIS2HH12_INT_PULSED;
break;
}
+
return ret;
}
@@ -1413,17 +1584,23 @@ int32_t lis2hh12_pin_logic_set(stmdev_ctx_t *ctx,
lis2hh12_ig_cfg2_t ig_cfg2;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t*)&ig_cfg1, 1);
- if(ret == 0){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t *)&ig_cfg1, 1);
+
+ if (ret == 0)
+ {
ig_cfg1.aoi = (uint8_t)val;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t*)&ig_cfg1, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t *)&ig_cfg1, 1);
}
- if(ret == 0){
- ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t*)&ig_cfg2, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t *)&ig_cfg2, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ig_cfg2.aoi = (((uint8_t) val & 0x02U) >> 1);
- ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t*)&ig_cfg2, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t *)&ig_cfg2, 1);
}
return ret;
@@ -1444,28 +1621,36 @@ int32_t lis2hh12_pin_logic_get(stmdev_ctx_t *ctx,
lis2hh12_ig_cfg2_t ig_cfg2;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t*)&ig_cfg1, 1);
- if(ret == 0){
- ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t*)&ig_cfg2, 1);
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t *)&ig_cfg1, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t *)&ig_cfg2, 1);
}
- switch ( (ig_cfg2.aoi << 1) | ig_cfg1.aoi){
+ switch ((ig_cfg2.aoi << 1) | ig_cfg1.aoi)
+ {
case LIS2HH12_IG1_OR_IG2_OR:
*val = LIS2HH12_IG1_OR_IG2_OR;
break;
+
case LIS2HH12_IG1_AND_IG2_OR:
*val = LIS2HH12_IG1_AND_IG2_OR;
break;
+
case LIS2HH12_IG1_OR_IG2_AND:
*val = LIS2HH12_IG1_OR_IG2_AND;
break;
+
case LIS2HH12_IG1_AND_IG2_AND:
*val = LIS2HH12_IG1_AND_IG2_AND;
break;
+
default:
*val = LIS2HH12_IG1_OR_IG2_OR;
break;
}
+
return ret;
}
@@ -1496,11 +1681,14 @@ int32_t lis2hh12_xl_trshld_mode_set(stmdev_ctx_t *ctx,
lis2hh12_ctrl7_t ctrl7;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL7, (uint8_t*)&ctrl7, 1);
- if(ret == 0){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL7, (uint8_t *)&ctrl7, 1);
+
+ if (ret == 0)
+ {
ctrl7.dcrm = (uint8_t)val;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL7, (uint8_t*)&ctrl7, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL7, (uint8_t *)&ctrl7, 1);
}
+
return ret;
}
@@ -1518,18 +1706,23 @@ int32_t lis2hh12_xl_trshld_mode_get(stmdev_ctx_t *ctx,
lis2hh12_ctrl7_t ctrl7;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL7, (uint8_t*)&ctrl7, 1);
- switch (ctrl7.dcrm){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL7, (uint8_t *)&ctrl7, 1);
+
+ switch (ctrl7.dcrm)
+ {
case LIS2HH12_RESET_MODE:
*val = LIS2HH12_RESET_MODE;
break;
+
case LIS2HH12_DECREMENT_MODE:
*val = LIS2HH12_DECREMENT_MODE;
break;
+
default:
*val = LIS2HH12_RESET_MODE;
break;
}
+
return ret;
}
@@ -1549,28 +1742,35 @@ int32_t lis2hh12_xl_trshld_axis_set(stmdev_ctx_t *ctx,
lis2hh12_ig_cfg2_t ig_cfg2;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t*)&ig_cfg1, 1);
- if(ret == 0) {
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t *)&ig_cfg1, 1);
+
+ if (ret == 0)
+ {
ig_cfg1.xlie = (uint8_t)val.ig1_xlie;
ig_cfg1.xhie = (uint8_t)val.ig1_xhie;
ig_cfg1.ylie = (uint8_t)val.ig1_ylie;
ig_cfg1.yhie = (uint8_t)val.ig1_yhie;
ig_cfg1.zlie = (uint8_t)val.ig1_zlie;
ig_cfg1.zhie = (uint8_t)val.ig1_zhie;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t*)&ig_cfg1, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t *)&ig_cfg1, 1);
}
- if(ret == 0) {
- ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t*)&ig_cfg2, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t *)&ig_cfg2, 1);
}
- if(ret == 0) {
+
+ if (ret == 0)
+ {
ig_cfg2.xlie = (uint8_t)val.ig2_xlie;
ig_cfg2.xhie = (uint8_t)val.ig2_xhie;
ig_cfg2.ylie = (uint8_t)val.ig2_ylie;
ig_cfg2.yhie = (uint8_t)val.ig2_yhie;
ig_cfg2.zlie = (uint8_t)val.ig2_zlie;
ig_cfg2.zhie = (uint8_t)val.ig2_zhie;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t*)&ig_cfg2, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t *)&ig_cfg2, 1);
}
+
return ret;
}
@@ -1590,24 +1790,26 @@ int32_t lis2hh12_xl_trshld_axis_get(stmdev_ctx_t *ctx,
lis2hh12_ig_cfg2_t ig_cfg2;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG1,(uint8_t*)&ig_cfg1, 1);
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t *)&ig_cfg1, 1);
- if(ret == 0) {
- ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t*)&ig_cfg2, 1);
+ if (ret == 0)
+ {
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t *)&ig_cfg2, 1);
}
+
val->ig1_xlie = ig_cfg1.xlie;
val->ig1_xhie = ig_cfg1.xhie;
val->ig1_ylie = ig_cfg1.ylie;
val->ig1_yhie = ig_cfg1.yhie;
val->ig1_zlie = ig_cfg1.zlie;
val->ig1_zhie = ig_cfg1.zhie;
-
val->ig2_xlie = ig_cfg2.xlie;
val->ig2_xhie = ig_cfg2.xhie;
val->ig2_ylie = ig_cfg2.ylie;
val->ig2_yhie = ig_cfg2.yhie;
val->ig2_zlie = ig_cfg2.zlie;
val->ig2_zhie = ig_cfg2.zhie;
+
return ret;
}
@@ -1626,10 +1828,13 @@ int32_t lis2hh12_xl_trshld_src_get(stmdev_ctx_t *ctx,
lis2hh12_ig_src2_t ig_src2;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_SRC1, (uint8_t*)&ig_src1, 1);
- if(ret == 0) {
- ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_SRC2, (uint8_t*)&ig_src2, 1);
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_SRC1, (uint8_t *)&ig_src1, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_SRC2, (uint8_t *)&ig_src2, 1);
}
+
val->ig1_xl = ig_src1.xl;
val->ig1_xh = ig_src1.xh;
val->ig1_yl = ig_src1.yl;
@@ -1663,13 +1868,19 @@ int32_t lis2hh12_xl_trshld_set(stmdev_ctx_t *ctx, uint8_t ig1_x,
int32_t ret;
ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_THS_X1, &ig1_x, 1);
- if(ret == 0) {
+
+ if (ret == 0)
+ {
ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_THS_Y1, &ig1_y, 1);
}
- if(ret == 0) {
+
+ if (ret == 0)
+ {
ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_THS_Z1, &ig1_z, 1);
}
- if(ret == 0) {
+
+ if (ret == 0)
+ {
ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_THS2, &ig2_xyz, 1);
}
@@ -1691,13 +1902,19 @@ int32_t lis2hh12_xl_trshld_get(stmdev_ctx_t *ctx, uint8_t *ig1_x,
int32_t ret;
ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_THS_X1, ig1_x, 1);
- if(ret == 0) {
+
+ if (ret == 0)
+ {
ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_THS_Y1, ig1_y, 1);
}
- if(ret == 0) {
+
+ if (ret == 0)
+ {
ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_THS_Z1, ig1_z, 1);
}
- if(ret == 0) {
+
+ if (ret == 0)
+ {
ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_THS2, ig2_xyz, 1);
}
@@ -1719,29 +1936,43 @@ int32_t lis2hh12_xl_trshld_min_sample_set(stmdev_ctx_t *ctx,
lis2hh12_ig_dur2_t ig_dur2;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_DUR1, (uint8_t*)&ig_dur1, 1);
- if(ret == 0){
- if (ig1_sam == 0x00U){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_DUR1, (uint8_t *)&ig_dur1, 1);
+
+ if (ret == 0)
+ {
+ if (ig1_sam == 0x00U)
+ {
ig_dur1.wait1 = PROPERTY_DISABLE;
}
- else{
+
+ else
+ {
ig_dur1.wait1 = PROPERTY_ENABLE;
}
+
ig_dur1.dur1 = ig1_sam;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_DUR1, (uint8_t*)&ig_dur1, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_DUR1, (uint8_t *)&ig_dur1, 1);
}
- if(ret == 0){
- ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_DUR2, (uint8_t*)&ig_dur2, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_DUR2, (uint8_t *)&ig_dur2, 1);
}
- if(ret == 0){
- if (ig2_sam == 0x00U){
+
+ if (ret == 0)
+ {
+ if (ig2_sam == 0x00U)
+ {
ig_dur2.wait2 = PROPERTY_DISABLE;
}
- else{
+
+ else
+ {
ig_dur2.wait2 = PROPERTY_ENABLE;
}
+
ig_dur2.dur2 = ig2_sam;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_DUR2, (uint8_t*)&ig_dur2, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_DUR2, (uint8_t *)&ig_dur2, 1);
}
return ret;
@@ -1762,11 +1993,12 @@ int32_t lis2hh12_xl_trshld_min_sample_get(stmdev_ctx_t *ctx,
lis2hh12_ig_dur2_t ig_dur2;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_DUR1, (uint8_t*)&ig_dur1, 1);
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_DUR1, (uint8_t *)&ig_dur1, 1);
*ig1_sam = (uint8_t)ig_dur1.dur1;
- if(ret == 0){
- ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_DUR2, (uint8_t*)&ig_dur2, 1);
+ if (ret == 0)
+ {
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_DUR2, (uint8_t *)&ig_dur2, 1);
*ig2_sam = (uint8_t)ig_dur2.dur2;
}
@@ -1799,11 +2031,14 @@ int32_t lis2hh12_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
lis2hh12_act_ths_t act_ths;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_ACT_THS, (uint8_t*)&act_ths, 1);
- if(ret == 0){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_ACT_THS, (uint8_t *)&act_ths, 1);
+
+ if (ret == 0)
+ {
act_ths.ths = (uint8_t)val;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_ACT_THS, (uint8_t*)&act_ths, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_ACT_THS, (uint8_t *)&act_ths, 1);
}
+
return ret;
}
@@ -1820,7 +2055,7 @@ int32_t lis2hh12_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2hh12_act_ths_t act_ths;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_ACT_THS, (uint8_t*)&act_ths, 1);
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_ACT_THS, (uint8_t *)&act_ths, 1);
*val = (uint8_t)act_ths.ths;
return ret;
@@ -1839,11 +2074,14 @@ int32_t lis2hh12_act_duration_set(stmdev_ctx_t *ctx, uint8_t val)
lis2hh12_act_dur_t act_dur;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_ACT_DUR, (uint8_t*)&act_dur, 1);
- if(ret == 0){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_ACT_DUR, (uint8_t *)&act_dur, 1);
+
+ if (ret == 0)
+ {
act_dur.dur = (uint8_t)val;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_ACT_DUR, (uint8_t*)&act_dur, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_ACT_DUR, (uint8_t *)&act_dur, 1);
}
+
return ret;
}
@@ -1860,7 +2098,7 @@ int32_t lis2hh12_act_duration_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2hh12_act_dur_t act_dur;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_ACT_DUR, (uint8_t*)&act_dur, 1);
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_ACT_DUR, (uint8_t *)&act_dur, 1);
*val = (uint8_t)act_dur.dur;
return ret;
@@ -1887,31 +2125,42 @@ int32_t lis2hh12_act_duration_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2hh12_6d_mode_set(stmdev_ctx_t *ctx, lis2hh12_6d_mode_t val)
+int32_t lis2hh12_6d_mode_set(stmdev_ctx_t *ctx,
+ lis2hh12_6d_mode_t val)
{
lis2hh12_ig_cfg1_t ig_cfg1;
lis2hh12_ig_cfg2_t ig_cfg2;
lis2hh12_ctrl7_t ctrl7;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL7, (uint8_t*)&ctrl7, 1);
- if(ret == 0){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL7, (uint8_t *)&ctrl7, 1);
+
+ if (ret == 0)
+ {
ctrl7._4d_ig = ((uint8_t)val & 0x10U) >> 4;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL7, (uint8_t*)&ctrl7, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL7, (uint8_t *)&ctrl7, 1);
}
- if(ret == 0){
- ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t*)&ig_cfg2, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t *)&ig_cfg2, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ig_cfg2._6d = ((uint8_t)val & 0x02U) >> 1;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t*)&ig_cfg2, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t *)&ig_cfg2, 1);
}
- if(ret == 0){
- ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t*)&ig_cfg1, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t *)&ig_cfg1, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ig_cfg1._6d = (uint8_t)val & 0x01U;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t*)&ig_cfg1, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t *)&ig_cfg1, 1);
}
return ret;
@@ -1925,37 +2174,48 @@ int32_t lis2hh12_6d_mode_set(stmdev_ctx_t *ctx, lis2hh12_6d_mode_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2hh12_6d_mode_get(stmdev_ctx_t *ctx, lis2hh12_6d_mode_t *val)
+int32_t lis2hh12_6d_mode_get(stmdev_ctx_t *ctx,
+ lis2hh12_6d_mode_t *val)
{
lis2hh12_ig_cfg1_t ig_cfg1;
lis2hh12_ig_cfg2_t ig_cfg2;
lis2hh12_ctrl7_t ctrl7;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL7, (uint8_t*)&ctrl7, 1);
- if(ret == 0){
- ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t*)&ig_cfg2, 1);
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL7, (uint8_t *)&ctrl7, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t *)&ig_cfg2, 1);
}
- if(ret == 0){
- ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t*)&ig_cfg1, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t *)&ig_cfg1, 1);
}
- switch ( (ctrl7._4d_ig << 4) | (ig_cfg2._6d << 1) | ig_cfg1._6d){
+ switch ((ctrl7._4d_ig << 4) | (ig_cfg2._6d << 1) | ig_cfg1._6d)
+ {
case LIS2HH12_6D_4D_DISABLE:
*val = LIS2HH12_6D_4D_DISABLE;
break;
+
case LIS2HH12_ENABLE_ON_IG1_6D:
*val = LIS2HH12_ENABLE_ON_IG1_6D;
break;
+
case LIS2HH12_ENABLE_ON_IG2_6D:
*val = LIS2HH12_ENABLE_ON_IG2_6D;
break;
+
case LIS2HH12_ENABLE_ON_IG1_4D:
*val = LIS2HH12_ENABLE_ON_IG1_4D;
break;
+
case LIS2HH12_ENABLE_ON_IG2_4D:
*val = LIS2HH12_ENABLE_ON_IG2_4D;
break;
+
default:
*val = LIS2HH12_6D_4D_DISABLE;
break;
@@ -1991,21 +2251,28 @@ int32_t lis2hh12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
lis2hh12_ctrl3_t ctrl3;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL3, (uint8_t*)&ctrl3, 1);
- if(ret == 0){
- ret = lis2hh12_read_reg(ctx, LIS2HH12_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL3, (uint8_t *)&ctrl3, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_FIFO_CTRL,
+ (uint8_t *)&fifo_ctrl, 1);
}
- if(ret == 0){
- if (val == 0x00U){
+ if (ret == 0)
+ {
+ if (val == 0x00U)
+ {
ctrl3.stop_fth = PROPERTY_DISABLE;
}
- else{
- ctrl3.stop_fth = PROPERTY_ENABLE;
+ else
+ {
+ ctrl3.stop_fth = PROPERTY_ENABLE;
}
+
fifo_ctrl.fth = val;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL3, (uint8_t*)&ctrl3, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL3, (uint8_t *)&ctrl3, 1);
}
return ret;
@@ -2021,11 +2288,11 @@ int32_t lis2hh12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
*/
int32_t lis2hh12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
{
-
lis2hh12_fifo_ctrl_t fifo_ctrl;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_FIFO_CTRL,
+ (uint8_t *)&fifo_ctrl, 1);
*val = (uint8_t)fifo_ctrl.fth;
return ret;
@@ -2039,24 +2306,34 @@ int32_t lis2hh12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2hh12_fifo_mode_set(stmdev_ctx_t *ctx, lis2hh12_fifo_md_t val)
+int32_t lis2hh12_fifo_mode_set(stmdev_ctx_t *ctx,
+ lis2hh12_fifo_md_t val)
{
lis2hh12_fifo_ctrl_t fifo_ctrl;
lis2hh12_ctrl3_t ctrl3;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL3, (uint8_t*)&ctrl3, 1);
- if(ret == 0){
- ctrl3.fifo_en = (( (uint8_t) val & 0x10U) >> 4);
- ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL3, (uint8_t*)&ctrl3, 1);
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL3, (uint8_t *)&ctrl3, 1);
+
+ if (ret == 0)
+ {
+ ctrl3.fifo_en = (((uint8_t) val & 0x10U) >> 4);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL3, (uint8_t *)&ctrl3, 1);
}
- if(ret == 0){
- ret = lis2hh12_read_reg(ctx, LIS2HH12_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_FIFO_CTRL,
+ (uint8_t *)&fifo_ctrl, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
fifo_ctrl.fmode = ((uint8_t)val & 0x0FU);
- ret = lis2hh12_write_reg(ctx, LIS2HH12_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_FIFO_CTRL,
+ (uint8_t *)&fifo_ctrl, 1);
}
+
return ret;
}
@@ -2068,43 +2345,56 @@ int32_t lis2hh12_fifo_mode_set(stmdev_ctx_t *ctx, lis2hh12_fifo_md_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis2hh12_fifo_mode_get(stmdev_ctx_t *ctx, lis2hh12_fifo_md_t *val)
+int32_t lis2hh12_fifo_mode_get(stmdev_ctx_t *ctx,
+ lis2hh12_fifo_md_t *val)
{
lis2hh12_fifo_ctrl_t fifo_ctrl;
lis2hh12_ctrl3_t ctrl3;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL3, (uint8_t*)&ctrl3, 1);
- if(ret == 0){
- ret = lis2hh12_read_reg(ctx, LIS2HH12_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL3, (uint8_t *)&ctrl3, 1);
+
+ if (ret == 0)
+ {
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_FIFO_CTRL,
+ (uint8_t *)&fifo_ctrl, 1);
}
- switch ( (ctrl3.fifo_en << 4) | fifo_ctrl.fmode ){
+ switch ((ctrl3.fifo_en << 4) | fifo_ctrl.fmode)
+ {
case LIS2HH12_FIFO_OFF:
*val = LIS2HH12_FIFO_OFF;
break;
+
case LIS2HH12_BYPASS_MODE:
*val = LIS2HH12_BYPASS_MODE;
break;
+
case LIS2HH12_FIFO_MODE:
*val = LIS2HH12_FIFO_MODE;
break;
+
case LIS2HH12_STREAM_MODE:
*val = LIS2HH12_STREAM_MODE;
break;
+
case LIS2HH12_STREAM_TO_FIFO_MODE:
*val = LIS2HH12_STREAM_TO_FIFO_MODE;
break;
+
case LIS2HH12_BYPASS_TO_STREAM_MODE:
*val = LIS2HH12_BYPASS_TO_STREAM_MODE;
break;
+
case LIS2HH12_BYPASS_TO_FIFO_MODE:
*val = LIS2HH12_BYPASS_TO_FIFO_MODE;
break;
+
default:
*val = LIS2HH12_FIFO_OFF;
break;
}
+
return ret;
}
@@ -2122,7 +2412,7 @@ int32_t lis2hh12_fifo_status_get(stmdev_ctx_t *ctx,
lis2hh12_fifo_src_t fifo_src;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_FIFO_SRC, (uint8_t*)&fifo_src, 1);
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_FIFO_SRC, (uint8_t *)&fifo_src, 1);
val->fss = fifo_src.fss;
val->empty = fifo_src.empty;
val->ovr = fifo_src.ovr;
@@ -2157,11 +2447,14 @@ int32_t lis2hh12_xl_self_test_set(stmdev_ctx_t *ctx,
lis2hh12_ctrl5_t ctrl5;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t*)&ctrl5, 1);
- if(ret == 0){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1);
+
+ if (ret == 0)
+ {
ctrl5.st = (uint8_t)val;
- ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL5, (uint8_t*)&ctrl5, 1);
+ ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1);
}
+
return ret;
}
@@ -2179,21 +2472,27 @@ int32_t lis2hh12_xl_self_test_get(stmdev_ctx_t *ctx,
lis2hh12_ctrl5_t ctrl5;
int32_t ret;
- ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t*)&ctrl5, 1);
- switch (ctrl5.st){
+ ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1);
+
+ switch (ctrl5.st)
+ {
case LIS2HH12_ST_DISABLE:
*val = LIS2HH12_ST_DISABLE;
break;
+
case LIS2HH12_ST_POSITIVE:
*val = LIS2HH12_ST_POSITIVE;
break;
+
case LIS2HH12_ST_NEGATIVE:
*val = LIS2HH12_ST_NEGATIVE;
break;
+
default:
*val = LIS2HH12_ST_DISABLE;
break;
}
+
return ret;
}
diff --git a/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.h b/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.h
index e46773ea7fe1fcff0d04c92d4d3ad1a5896573f0..8409639a8e1b6fb191cc38ee8cad25313a2d0bb0 100644
--- a/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.h
+++ b/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file lis2hh12_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lis2hh12_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lis2hh12_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lis2hh12_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LIS2HH12_REGS_H
#define LIS2HH12_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup LIS2HH12
@@ -74,7 +75,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -107,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -131,7 +134,7 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
+ * You can create a sensor configuration by your own or using
* Unico / Unicleo tools available on STMicroelectronics
* web site.
*
@@ -139,7 +142,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -176,7 +180,8 @@ typedef struct {
#define LIS2HH12_TEMP_H 0x0CU
#define LIS2HH12_WHO_AM_I 0x0FU
#define LIS2HH12_ACT_THS 0x1EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t not_used_01 : 1;
@@ -187,12 +192,14 @@ typedef struct {
} lis2hh12_act_ths_t;
#define LIS2HH12_ACT_DUR 0x1FU
-typedef struct {
+typedef struct
+{
uint8_t dur : 8;
} lis2hh12_act_dur_t;
#define LIS2HH12_CTRL1 0x20U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xen : 1;
uint8_t yen : 1;
@@ -211,7 +218,8 @@ typedef struct {
} lis2hh12_ctrl1_t;
#define LIS2HH12_CTRL2 0x21U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t hpis : 2;
uint8_t fds : 1;
@@ -228,7 +236,8 @@ typedef struct {
} lis2hh12_ctrl2_t;
#define LIS2HH12_CTRL3 0x22U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_drdy : 1;
uint8_t int1_fth : 1;
@@ -251,7 +260,8 @@ typedef struct {
} lis2hh12_ctrl3_t;
#define LIS2HH12_CTRL4 0x23U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t i2c_disable : 1;
@@ -270,7 +280,8 @@ typedef struct {
} lis2hh12_ctrl4_t;
#define LIS2HH12_CTRL5 0x24U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t pp_od : 1;
uint8_t h_lactive : 1;
@@ -289,7 +300,8 @@ typedef struct {
} lis2hh12_ctrl5_t;
#define LIS2HH12_CTRL6 0x25U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_drdy : 1;
uint8_t int2_fth : 1;
@@ -312,7 +324,8 @@ typedef struct {
} lis2hh12_ctrl6_t;
#define LIS2HH12_CTRL7 0x26U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t _4d_ig : 2;
uint8_t lir : 2;
@@ -327,7 +340,8 @@ typedef struct {
} lis2hh12_ctrl7_t;
#define LIS2HH12_STATUS 0x27U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xda : 1;
uint8_t yda : 1;
@@ -356,7 +370,8 @@ typedef struct {
#define LIS2HH12_OUT_Z_L 0x2CU
#define LIS2HH12_OUT_Z_H 0x2DU
#define LIS2HH12_FIFO_CTRL 0x2EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fth : 5;
uint8_t fmode : 3;
@@ -367,7 +382,8 @@ typedef struct {
} lis2hh12_fifo_ctrl_t;
#define LIS2HH12_FIFO_SRC 0x2FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fss : 5;
uint8_t empty : 1;
@@ -382,7 +398,8 @@ typedef struct {
} lis2hh12_fifo_src_t;
#define LIS2HH12_IG_CFG1 0x30U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlie : 1;
uint8_t xhie : 1;
@@ -405,7 +422,8 @@ typedef struct {
} lis2hh12_ig_cfg1_t;
#define LIS2HH12_IG_SRC1 0x31U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
@@ -431,7 +449,8 @@ typedef struct {
#define LIS2HH12_IG_THS_Y1 0x33U
#define LIS2HH12_IG_THS_Z1 0x34U
#define LIS2HH12_IG_DUR1 0x35U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t dur1 : 7;
uint8_t wait1 : 1;
@@ -442,7 +461,8 @@ typedef struct {
} lis2hh12_ig_dur1_t;
#define LIS2HH12_IG_CFG2 0x36U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlie : 1;
uint8_t xhie : 1;
@@ -465,7 +485,8 @@ typedef struct {
} lis2hh12_ig_cfg2_t;
#define LIS2HH12_IG_SRC2 0x37U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
@@ -489,7 +510,8 @@ typedef struct {
#define LIS2HH12_IG_THS2 0x38U
#define LIS2HH12_IG_DUR2 0x39U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t dur2 : 7;
uint8_t wait2 : 1;
@@ -508,9 +530,9 @@ typedef struct {
/**
* @defgroup LIS2HH12_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -518,7 +540,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
lis2hh12_act_ths_t act_ths;
lis2hh12_act_dur_t act_dur;
lis2hh12_ctrl1_t ctrl1;
@@ -546,28 +569,37 @@ typedef union{
*
*/
-int32_t lis2hh12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lis2hh12_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t lis2hh12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lis2hh12_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
float_t lis2hh12_from_fs2g_to_mg(int16_t lsb);
float_t lis2hh12_from_fs4g_to_mg(int16_t lsb);
float_t lis2hh12_from_fs8g_to_mg(int16_t lsb);
+
float_t lis2hh12_from_lsb_to_celsius(int16_t lsb);
-typedef struct {
+typedef struct
+{
uint8_t xen : 1;
uint8_t yen : 1;
uint8_t zen : 1;
} lis2hh12_xl_axis_t;
-int32_t lis2hh12_xl_axis_set(stmdev_ctx_t *ctx, lis2hh12_xl_axis_t val);
-int32_t lis2hh12_xl_axis_get(stmdev_ctx_t *ctx, lis2hh12_xl_axis_t *val);
-
-int32_t lis2hh12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2hh12_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
-
-typedef enum {
+int32_t lis2hh12_xl_axis_set(stmdev_ctx_t *ctx,
+ lis2hh12_xl_axis_t val);
+int32_t lis2hh12_xl_axis_get(stmdev_ctx_t *ctx,
+ lis2hh12_xl_axis_t *val);
+
+int32_t lis2hh12_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis2hh12_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+typedef enum
+{
LIS2HH12_XL_ODR_OFF = 0x00,
LIS2HH12_XL_ODR_10Hz = 0x01,
LIS2HH12_XL_ODR_50Hz = 0x02,
@@ -581,7 +613,8 @@ int32_t lis2hh12_xl_data_rate_set(stmdev_ctx_t *ctx,
int32_t lis2hh12_xl_data_rate_get(stmdev_ctx_t *ctx,
lis2hh12_xl_data_rate_t *val);
-typedef enum {
+typedef enum
+{
LIS2HH12_2g = 0x00,
LIS2HH12_16g = 0x01,
LIS2HH12_4g = 0x02,
@@ -592,20 +625,25 @@ int32_t lis2hh12_xl_full_scale_set(stmdev_ctx_t *ctx,
int32_t lis2hh12_xl_full_scale_get(stmdev_ctx_t *ctx,
lis2hh12_xl_fs_t *val);
-typedef enum {
+typedef enum
+{
LIS2HH12_NO_DECIMATION = 0x00,
LIS2HH12_EVERY_2_SAMPLES = 0x01,
LIS2HH12_EVERY_4_SAMPLES = 0x02,
LIS2HH12_EVERY_8_SAMPLES = 0x03,
} lis2hh12_dec_t;
-int32_t lis2hh12_xl_decimation_set(stmdev_ctx_t *ctx, lis2hh12_dec_t val);
-int32_t lis2hh12_xl_decimation_get(stmdev_ctx_t *ctx, lis2hh12_dec_t *val);
+int32_t lis2hh12_xl_decimation_set(stmdev_ctx_t *ctx,
+ lis2hh12_dec_t val);
+int32_t lis2hh12_xl_decimation_get(stmdev_ctx_t *ctx,
+ lis2hh12_dec_t *val);
-int32_t lis2hh12_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2hh12_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lis2hh12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val);
-int32_t lis2hh12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t lis2hh12_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
int32_t lis2hh12_dev_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
@@ -615,7 +653,8 @@ int32_t lis2hh12_dev_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2hh12_dev_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2hh12_dev_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef struct {
+typedef struct
+{
uint8_t xda : 1;
uint8_t yda : 1;
uint8_t zda : 1;
@@ -628,7 +667,8 @@ typedef struct {
int32_t lis2hh12_dev_status_get(stmdev_ctx_t *ctx,
lis2hh12_status_reg_t *val);
-typedef enum {
+typedef enum
+{
LIS2HH12_HP_DISABLE = 0x00,
LIS2HH12_HP_ON_INT_GEN_1 = 0x02,
LIS2HH12_HP_ON_INT_GEN_2 = 0x01,
@@ -639,7 +679,8 @@ int32_t lis2hh12_xl_filter_int_path_set(stmdev_ctx_t *ctx,
int32_t lis2hh12_xl_filter_int_path_get(stmdev_ctx_t *ctx,
lis2hh12_xl_hp_path_t *val);
-typedef enum {
+typedef enum
+{
LIS2HH12_BYPASSED = 0x00,
LIS2HH12_FILT_HP = 0x02,
LIS2HH12_FILT_LP = 0x01,
@@ -649,7 +690,8 @@ int32_t lis2hh12_xl_filter_out_path_set(stmdev_ctx_t *ctx,
int32_t lis2hh12_xl_filter_out_path_get(stmdev_ctx_t *ctx,
lis2hh12_xl_out_path_t *val);
-typedef enum {
+typedef enum
+{
LIS2HH12_HP_ODR_DIV_50 = 0x00,
LIS2HH12_HP_ODR_DIV_100 = 0x10,
LIS2HH12_HP_ODR_DIV_9 = 0x20,
@@ -664,7 +706,8 @@ int32_t lis2hh12_xl_filter_hp_bandwidth_set(stmdev_ctx_t *ctx,
int32_t lis2hh12_xl_filter_hp_bandwidth_get(stmdev_ctx_t *ctx,
lis2hh12_xl_hp_bw_t *val);
-typedef enum {
+typedef enum
+{
LIS2HH12_LP_ODR_DIV_50 = 0,
LIS2HH12_LP_ODR_DIV_100 = 1,
LIS2HH12_LP_ODR_DIV_9 = 2,
@@ -675,7 +718,8 @@ int32_t lis2hh12_xl_filter_low_bandwidth_set(stmdev_ctx_t *ctx,
int32_t lis2hh12_xl_filter_low_bandwidth_get(stmdev_ctx_t *ctx,
lis2hh12_xl_lp_bw_t *val);
-typedef enum {
+typedef enum
+{
LIS2HH12_AUTO = 0x00,
LIS2HH12_408Hz = 0x10,
LIS2HH12_211Hz = 0x11,
@@ -687,17 +731,21 @@ int32_t lis2hh12_xl_filter_aalias_bandwidth_set(stmdev_ctx_t *ctx,
int32_t lis2hh12_xl_filter_aalias_bandwidth_get(stmdev_ctx_t *ctx,
lis2hh12_xl_filt_aa_bw_t *val);
-int32_t lis2hh12_xl_filter_reference_set(stmdev_ctx_t *ctx, int16_t *val);
-int32_t lis2hh12_xl_filter_reference_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t lis2hh12_xl_filter_reference_set(stmdev_ctx_t *ctx,
+ int16_t *val);
+int32_t lis2hh12_xl_filter_reference_get(stmdev_ctx_t *ctx,
+ int16_t *val);
-typedef enum {
+typedef enum
+{
LIS2HH12_SPI_4_WIRE = 0x00,
LIS2HH12_SPI_3_WIRE = 0x01,
} lis2hh12_sim_t;
int32_t lis2hh12_spi_mode_set(stmdev_ctx_t *ctx, lis2hh12_sim_t val);
int32_t lis2hh12_spi_mode_get(stmdev_ctx_t *ctx, lis2hh12_sim_t *val);
-typedef enum {
+typedef enum
+{
LIS2HH12_I2C_ENABLE = 0x00,
LIS2HH12_I2C_DISABLE = 0x01,
} lis2hh12_i2c_dis_t;
@@ -706,7 +754,8 @@ int32_t lis2hh12_i2c_interface_set(stmdev_ctx_t *ctx,
int32_t lis2hh12_i2c_interface_get(stmdev_ctx_t *ctx,
lis2hh12_i2c_dis_t *val);
-typedef enum {
+typedef enum
+{
LIS2HH12_DISABLE = 0x00,
LIS2HH12_ENABLE = 0x01,
} lis2hh12_auto_inc_t;
@@ -715,7 +764,8 @@ int32_t lis2hh12_auto_increment_set(stmdev_ctx_t *ctx,
int32_t lis2hh12_auto_increment_get(stmdev_ctx_t *ctx,
lis2hh12_auto_inc_t *val);
-typedef struct {
+typedef struct
+{
uint8_t int1_drdy : 1;
uint8_t int1_fth : 1;
uint8_t int1_ovr : 1;
@@ -728,14 +778,18 @@ int32_t lis2hh12_pin_int1_route_set(stmdev_ctx_t *ctx,
int32_t lis2hh12_pin_int1_route_get(stmdev_ctx_t *ctx,
lis2hh12_pin_int1_route_t *val);
-typedef enum {
+typedef enum
+{
LIS2HH12_PUSH_PULL = 0x00,
LIS2HH12_OPEN_DRAIN = 0x01,
} lis2hh12_pp_od_t;
-int32_t lis2hh12_pin_mode_set(stmdev_ctx_t *ctx, lis2hh12_pp_od_t val);
-int32_t lis2hh12_pin_mode_get(stmdev_ctx_t *ctx, lis2hh12_pp_od_t *val);
+int32_t lis2hh12_pin_mode_set(stmdev_ctx_t *ctx,
+ lis2hh12_pp_od_t val);
+int32_t lis2hh12_pin_mode_get(stmdev_ctx_t *ctx,
+ lis2hh12_pp_od_t *val);
-typedef enum {
+typedef enum
+{
LIS2HH12_ACTIVE_HIGH = 0x00,
LIS2HH12_ACTIVE_LOW = 0x01,
} lis2hh12_pin_pol_t;
@@ -744,7 +798,8 @@ int32_t lis2hh12_pin_polarity_set(stmdev_ctx_t *ctx,
int32_t lis2hh12_pin_polarity_get(stmdev_ctx_t *ctx,
lis2hh12_pin_pol_t *val);
-typedef struct {
+typedef struct
+{
uint8_t int2_drdy : 1;
uint8_t int2_fth : 1;
uint8_t int2_empty : 1;
@@ -757,7 +812,8 @@ int32_t lis2hh12_pin_int2_route_set(stmdev_ctx_t *ctx,
int32_t lis2hh12_pin_int2_route_get(stmdev_ctx_t *ctx,
lis2hh12_pin_int2_route_t *val);
-typedef enum {
+typedef enum
+{
LIS2HH12_INT_PULSED = 0x00,
LIS2HH12_INT_LATCHED = 0x01,
} lis2hh12_lir_t;
@@ -765,7 +821,8 @@ int32_t lis2hh12_pin_notification_set(stmdev_ctx_t *ctx,
lis2hh12_lir_t val);
int32_t lis2hh12_pin_notification_get(stmdev_ctx_t *ctx,
lis2hh12_lir_t *val);
-typedef enum {
+typedef enum
+{
LIS2HH12_IG1_OR_IG2_OR = 0x00,
LIS2HH12_IG1_AND_IG2_OR = 0x01,
LIS2HH12_IG1_OR_IG2_AND = 0x10,
@@ -776,7 +833,8 @@ int32_t lis2hh12_pin_logic_set(stmdev_ctx_t *ctx,
int32_t lis2hh12_pin_logic_get(stmdev_ctx_t *ctx,
lis2hh12_pin_logic_t *val);
-typedef enum {
+typedef enum
+{
LIS2HH12_RESET_MODE = 0x00,
LIS2HH12_DECREMENT_MODE = 0x01,
} lis2hh12_dcrm_t;
@@ -785,7 +843,8 @@ int32_t lis2hh12_xl_trshld_mode_set(stmdev_ctx_t *ctx,
int32_t lis2hh12_xl_trshld_mode_get(stmdev_ctx_t *ctx,
lis2hh12_dcrm_t *val);
-typedef struct {
+typedef struct
+{
uint16_t ig1_xlie : 1;
uint16_t ig1_xhie : 1;
uint16_t ig1_ylie : 1;
@@ -804,7 +863,8 @@ int32_t lis2hh12_xl_trshld_axis_set(stmdev_ctx_t *ctx,
int32_t lis2hh12_xl_trshld_axis_get(stmdev_ctx_t *ctx,
lis2hh12_xl_trshld_en_t *val);
-typedef struct {
+typedef struct
+{
uint16_t ig1_xl : 1;
uint16_t ig1_xh : 1;
uint16_t ig1_yl : 1;
@@ -841,20 +901,24 @@ int32_t lis2hh12_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2hh12_act_duration_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2hh12_act_duration_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2HH12_6D_4D_DISABLE = 0x00,
LIS2HH12_ENABLE_ON_IG1_6D = 0x01,
LIS2HH12_ENABLE_ON_IG2_6D = 0x02,
LIS2HH12_ENABLE_ON_IG1_4D = 0x11,
LIS2HH12_ENABLE_ON_IG2_4D = 0x12,
} lis2hh12_6d_mode_t;
-int32_t lis2hh12_6d_mode_set(stmdev_ctx_t *ctx, lis2hh12_6d_mode_t val);
-int32_t lis2hh12_6d_mode_get(stmdev_ctx_t *ctx, lis2hh12_6d_mode_t *val);
+int32_t lis2hh12_6d_mode_set(stmdev_ctx_t *ctx,
+ lis2hh12_6d_mode_t val);
+int32_t lis2hh12_6d_mode_get(stmdev_ctx_t *ctx,
+ lis2hh12_6d_mode_t *val);
int32_t lis2hh12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2hh12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2HH12_FIFO_OFF = 0x00,
LIS2HH12_BYPASS_MODE = 0x10,
LIS2HH12_FIFO_MODE = 0x11,
@@ -863,10 +927,13 @@ typedef enum {
LIS2HH12_BYPASS_TO_STREAM_MODE = 0x14,
LIS2HH12_BYPASS_TO_FIFO_MODE = 0x17,
} lis2hh12_fifo_md_t;
-int32_t lis2hh12_fifo_mode_set(stmdev_ctx_t *ctx, lis2hh12_fifo_md_t val);
-int32_t lis2hh12_fifo_mode_get(stmdev_ctx_t *ctx, lis2hh12_fifo_md_t *val);
+int32_t lis2hh12_fifo_mode_set(stmdev_ctx_t *ctx,
+ lis2hh12_fifo_md_t val);
+int32_t lis2hh12_fifo_mode_get(stmdev_ctx_t *ctx,
+ lis2hh12_fifo_md_t *val);
-typedef struct {
+typedef struct
+{
uint8_t fss : 1;
uint8_t empty : 1;
uint8_t ovr : 1;
@@ -874,7 +941,8 @@ typedef struct {
int32_t lis2hh12_fifo_status_get(stmdev_ctx_t *ctx,
lis2hh12_fifo_stat_t *val);
-typedef enum {
+typedef enum
+{
LIS2HH12_ST_DISABLE = 0x00,
LIS2HH12_ST_POSITIVE = 0x01,
LIS2HH12_ST_NEGATIVE = 0x02,
diff --git a/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.c b/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.c
index a6f55814d1cc9173c5d66927ce7bdd59517def6f..a6dd9d69345e2058d89c91ec605bba1cebe44e0d 100644
--- a/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.c
+++ b/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file lis2mdl_reg.c
- * @author Sensors Software Solution Team
- * @brief LIS2MDL driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lis2mdl_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LIS2MDL driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lis2mdl_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2mdl_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lis2mdl_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t lis2mdl_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2mdl_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lis2mdl_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -77,7 +83,7 @@ int32_t lis2mdl_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
*
*/
- /**
+/**
* @defgroup LIS2MDL_Sensitivity
* @brief These functions convert raw-data into engineering units.
* @{
@@ -123,12 +129,12 @@ int32_t lis2mdl_mag_user_offset_set(stmdev_ctx_t *ctx, int16_t *val)
uint8_t buff[6];
int32_t ret;
- buff[1] = (uint8_t) ( (uint8_t)val[0] / 256U);
- buff[0] = (uint8_t) ( (uint8_t)val[0] - (buff[1] * 256U));
- buff[3] = (uint8_t) ( (uint8_t)val[1] / 256U);
- buff[2] = (uint8_t) ( (uint8_t)val[1] - (buff[1] * 256U));
- buff[5] = (uint8_t) ( (uint8_t)val[2] / 256U);
- buff[4] = (uint8_t) ( (uint8_t)val[2] - (buff[1] * 256U));
+ buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
+ buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
+ buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
+ buff[2] = (uint8_t)((uint16_t)val[1] - (buff[1] * 256U));
+ buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
+ buff[4] = (uint8_t)((uint16_t)val[2] - (buff[1] * 256U));
ret = lis2mdl_write_reg(ctx, LIS2MDL_OFFSET_X_REG_L, buff, 6);
return ret;
@@ -153,11 +159,11 @@ int32_t lis2mdl_mag_user_offset_get(stmdev_ctx_t *ctx, int16_t *val)
ret = lis2mdl_read_reg(ctx, LIS2MDL_OFFSET_X_REG_L, buff, 6);
val[0] = (int16_t)buff[1];
- val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
- val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
val[2] = (int16_t)buff[5];
- val[2] = (val[2] * 256) + (int16_t)buff[4];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
return ret;
}
@@ -170,16 +176,18 @@ int32_t lis2mdl_mag_user_offset_get(stmdev_ctx_t *ctx, int16_t *val)
* @retval interface status.(MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2mdl_operating_mode_set(stmdev_ctx_t *ctx, lis2mdl_md_t val)
+int32_t lis2mdl_operating_mode_set(stmdev_ctx_t *ctx,
+ lis2mdl_md_t val)
{
lis2mdl_cfg_reg_a_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t*)®, 1);
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.md = (uint8_t)val;
- ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t*)®, 1);
+ ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
}
return ret;
@@ -193,22 +201,28 @@ int32_t lis2mdl_operating_mode_set(stmdev_ctx_t *ctx, lis2mdl_md_t val)
* @retval interface status.(MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2mdl_operating_mode_get(stmdev_ctx_t *ctx, lis2mdl_md_t *val)
+int32_t lis2mdl_operating_mode_get(stmdev_ctx_t *ctx,
+ lis2mdl_md_t *val)
{
lis2mdl_cfg_reg_a_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t*)®, 1);
- switch (reg.md){
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
+
+ switch (reg.md)
+ {
case LIS2MDL_POWER_DOWN:
*val = LIS2MDL_POWER_DOWN;
break;
+
case LIS2MDL_CONTINUOUS_MODE:
*val = LIS2MDL_CONTINUOUS_MODE;
break;
+
case LIS2MDL_SINGLE_TRIGGER:
*val = LIS2MDL_SINGLE_TRIGGER;
break;
+
default:
*val = LIS2MDL_POWER_DOWN;
break;
@@ -230,11 +244,12 @@ int32_t lis2mdl_data_rate_set(stmdev_ctx_t *ctx, lis2mdl_odr_t val)
lis2mdl_cfg_reg_a_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t*)®, 1);
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.odr = (uint8_t)val;
- ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t*)®, 1);
+ ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
}
return ret;
@@ -253,24 +268,31 @@ int32_t lis2mdl_data_rate_get(stmdev_ctx_t *ctx, lis2mdl_odr_t *val)
lis2mdl_cfg_reg_a_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t*)®, 1);
- switch (reg.odr){
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
+
+ switch (reg.odr)
+ {
case LIS2MDL_ODR_10Hz:
*val = LIS2MDL_ODR_10Hz;
break;
+
case LIS2MDL_ODR_20Hz:
*val = LIS2MDL_ODR_20Hz;
break;
+
case LIS2MDL_ODR_50Hz:
*val = LIS2MDL_ODR_50Hz;
break;
+
case LIS2MDL_ODR_100Hz:
*val = LIS2MDL_ODR_100Hz;
break;
+
default:
*val = LIS2MDL_ODR_10Hz;
break;
}
+
return ret;
}
@@ -287,11 +309,12 @@ int32_t lis2mdl_power_mode_set(stmdev_ctx_t *ctx, lis2mdl_lp_t val)
lis2mdl_cfg_reg_a_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t*)®, 1);
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.lp = (uint8_t)val;
- ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t*)®, 1);
+ ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
}
return ret;
@@ -310,18 +333,23 @@ int32_t lis2mdl_power_mode_get(stmdev_ctx_t *ctx, lis2mdl_lp_t *val)
lis2mdl_cfg_reg_a_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t*)®, 1);
- switch (reg.lp){
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
+
+ switch (reg.lp)
+ {
case LIS2MDL_HIGH_RESOLUTION:
*val = LIS2MDL_HIGH_RESOLUTION;
break;
+
case LIS2MDL_LOW_POWER:
*val = LIS2MDL_LOW_POWER;
break;
+
default:
*val = LIS2MDL_HIGH_RESOLUTION;
break;
}
+
return ret;
}
@@ -338,11 +366,12 @@ int32_t lis2mdl_offset_temp_comp_set(stmdev_ctx_t *ctx, uint8_t val)
lis2mdl_cfg_reg_a_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t*)®, 1);
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.comp_temp_en = val;
- ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t*)®, 1);
+ ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
}
return ret;
@@ -361,7 +390,7 @@ int32_t lis2mdl_offset_temp_comp_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2mdl_cfg_reg_a_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t*)®, 1);
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
*val = reg.comp_temp_en;
return ret;
@@ -381,11 +410,12 @@ int32_t lis2mdl_low_pass_bandwidth_set(stmdev_ctx_t *ctx,
lis2mdl_cfg_reg_b_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t*)®, 1);
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.lpf = (uint8_t)val;
- ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t*)®, 1);
+ ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
}
return ret;
@@ -405,18 +435,23 @@ int32_t lis2mdl_low_pass_bandwidth_get(stmdev_ctx_t *ctx,
lis2mdl_cfg_reg_b_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t*)®, 1);
- switch (reg.lpf){
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
+
+ switch (reg.lpf)
+ {
case LIS2MDL_ODR_DIV_2:
*val = LIS2MDL_ODR_DIV_2;
break;
+
case LIS2MDL_ODR_DIV_4:
*val = LIS2MDL_ODR_DIV_4;
break;
+
default:
*val = LIS2MDL_ODR_DIV_2;
break;
}
+
return ret;
}
@@ -428,16 +463,18 @@ int32_t lis2mdl_low_pass_bandwidth_get(stmdev_ctx_t *ctx,
* @retval interface status.(MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2mdl_set_rst_mode_set(stmdev_ctx_t *ctx, lis2mdl_set_rst_t val)
+int32_t lis2mdl_set_rst_mode_set(stmdev_ctx_t *ctx,
+ lis2mdl_set_rst_t val)
{
lis2mdl_cfg_reg_b_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t*)®, 1);
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.set_rst = (uint8_t)val;
- ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t*)®, 1);
+ ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
}
return ret;
@@ -451,26 +488,33 @@ int32_t lis2mdl_set_rst_mode_set(stmdev_ctx_t *ctx, lis2mdl_set_rst_t val)
* @retval interface status.(MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2mdl_set_rst_mode_get(stmdev_ctx_t *ctx, lis2mdl_set_rst_t *val)
+int32_t lis2mdl_set_rst_mode_get(stmdev_ctx_t *ctx,
+ lis2mdl_set_rst_t *val)
{
lis2mdl_cfg_reg_b_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t*)®, 1);
- switch (reg.set_rst){
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
+
+ switch (reg.set_rst)
+ {
case LIS2MDL_SET_SENS_ODR_DIV_63:
*val = LIS2MDL_SET_SENS_ODR_DIV_63;
break;
+
case LIS2MDL_SENS_OFF_CANC_EVERY_ODR:
*val = LIS2MDL_SENS_OFF_CANC_EVERY_ODR;
break;
+
case LIS2MDL_SET_SENS_ONLY_AT_POWER_ON:
*val = LIS2MDL_SET_SENS_ONLY_AT_POWER_ON;
break;
+
default:
*val = LIS2MDL_SET_SENS_ODR_DIV_63;
break;
}
+
return ret;
}
@@ -486,16 +530,18 @@ int32_t lis2mdl_set_rst_mode_get(stmdev_ctx_t *ctx, lis2mdl_set_rst_t *val)
* @retval interface status.(MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2mdl_set_rst_sensor_single_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lis2mdl_set_rst_sensor_single_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lis2mdl_cfg_reg_b_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t*)®, 1);
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.off_canc_one_shot = val;
- ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t*)®, 1);
+ ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
}
return ret;
@@ -513,12 +559,13 @@ int32_t lis2mdl_set_rst_sensor_single_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status.(MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2mdl_set_rst_sensor_single_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis2mdl_set_rst_sensor_single_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis2mdl_cfg_reg_b_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t*)®, 1);
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
*val = reg.off_canc_one_shot;
return ret;
@@ -537,11 +584,12 @@ int32_t lis2mdl_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
lis2mdl_cfg_reg_c_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t*)®, 1);
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.bdu = val;
- ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t*)®, 1);
+ ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
}
return ret;
@@ -560,7 +608,7 @@ int32_t lis2mdl_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2mdl_cfg_reg_c_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t*)®, 1);
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
*val = reg.bdu;
return ret;
@@ -579,7 +627,7 @@ int32_t lis2mdl_mag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2mdl_status_reg_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_STATUS_REG, (uint8_t*)®, 1);
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_STATUS_REG, (uint8_t *)®, 1);
*val = reg.zyxda;
return ret;
@@ -598,7 +646,7 @@ int32_t lis2mdl_mag_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2mdl_status_reg_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_STATUS_REG, (uint8_t*)®, 1);
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_STATUS_REG, (uint8_t *)®, 1);
*val = reg.zyxor;
return ret;
@@ -619,11 +667,11 @@ int32_t lis2mdl_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val)
ret = lis2mdl_read_reg(ctx, LIS2MDL_OUTX_L_REG, buff, 6);
val[0] = (int16_t)buff[1];
- val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
- val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
val[2] = (int16_t)buff[5];
- val[2] = (val[2] * 256) + (int16_t)buff[4];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
return ret;
}
@@ -643,7 +691,7 @@ int32_t lis2mdl_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
ret = lis2mdl_read_reg(ctx, LIS2MDL_TEMP_OUT_L_REG, buff, 2);
*val = (int16_t)buff[1];
- *val = (*val * 256) + (int16_t)buff[0];
+ *val = (*val * 256) + (int16_t)buff[0];
return ret;
}
@@ -655,7 +703,7 @@ int32_t lis2mdl_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
/**
* @defgroup LIS2MDL_common
- * @brief This section group common usefull functions
+ * @brief This section group common useful functions
* @{
*
*/
@@ -671,7 +719,9 @@ int32_t lis2mdl_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
int32_t lis2mdl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis2mdl_read_reg(ctx, LIS2MDL_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -688,11 +738,12 @@ int32_t lis2mdl_reset_set(stmdev_ctx_t *ctx, uint8_t val)
lis2mdl_cfg_reg_a_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t*)®, 1);
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.soft_rst = val;
- ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t*)®, 1);
+ ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
}
return ret;
@@ -711,7 +762,7 @@ int32_t lis2mdl_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2mdl_cfg_reg_a_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t*)®, 1);
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
*val = reg.soft_rst;
return ret;
@@ -730,11 +781,12 @@ int32_t lis2mdl_boot_set(stmdev_ctx_t *ctx, uint8_t val)
lis2mdl_cfg_reg_a_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t*)®, 1);
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.reboot = val;
- ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t*)®, 1);
+ ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
}
return ret;
@@ -753,7 +805,7 @@ int32_t lis2mdl_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2mdl_cfg_reg_a_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t*)®, 1);
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
*val = reg.reboot;
return ret;
@@ -772,11 +824,12 @@ int32_t lis2mdl_self_test_set(stmdev_ctx_t *ctx, uint8_t val)
lis2mdl_cfg_reg_c_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t*)®, 1);
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.self_test = val;
- ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t*)®, 1);
+ ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
}
return ret;
@@ -795,7 +848,7 @@ int32_t lis2mdl_self_test_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2mdl_cfg_reg_c_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t*)®, 1);
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
*val = reg.self_test;
return ret;
@@ -814,11 +867,12 @@ int32_t lis2mdl_data_format_set(stmdev_ctx_t *ctx, lis2mdl_ble_t val)
lis2mdl_cfg_reg_c_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t*)®, 1);
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.ble = (uint8_t)val;
- ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t*)®, 1);
+ ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
}
return ret;
@@ -837,18 +891,23 @@ int32_t lis2mdl_data_format_get(stmdev_ctx_t *ctx, lis2mdl_ble_t *val)
lis2mdl_cfg_reg_c_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t*)®, 1);
- switch (reg.ble){
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
+
+ switch (reg.ble)
+ {
case LIS2MDL_LSB_AT_LOW_ADD:
*val = LIS2MDL_LSB_AT_LOW_ADD;
break;
+
case LIS2MDL_MSB_AT_LOW_ADD:
*val = LIS2MDL_MSB_AT_LOW_ADD;
break;
+
default:
*val = LIS2MDL_LSB_AT_LOW_ADD;
break;
}
+
return ret;
}
@@ -860,10 +919,13 @@ int32_t lis2mdl_data_format_get(stmdev_ctx_t *ctx, lis2mdl_ble_t *val)
* @retval interface status.(MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2mdl_status_get(stmdev_ctx_t *ctx, lis2mdl_status_reg_t *val)
+int32_t lis2mdl_status_get(stmdev_ctx_t *ctx,
+ lis2mdl_status_reg_t *val)
{
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_STATUS_REG, (uint8_t*) val, 1);
+
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_STATUS_REG, (uint8_t *) val, 1);
+
return ret;
}
@@ -894,11 +956,12 @@ int32_t lis2mdl_offset_int_conf_set(stmdev_ctx_t *ctx,
lis2mdl_cfg_reg_b_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t*)®, 1);
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.int_on_dataoff = (uint8_t)val;
- ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t*)®, 1);
+ ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
}
return ret;
@@ -919,18 +982,23 @@ int32_t lis2mdl_offset_int_conf_get(stmdev_ctx_t *ctx,
lis2mdl_cfg_reg_b_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t*)®, 1);
- switch (reg.int_on_dataoff){
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
+
+ switch (reg.int_on_dataoff)
+ {
case LIS2MDL_CHECK_BEFORE:
*val = LIS2MDL_CHECK_BEFORE;
break;
+
case LIS2MDL_CHECK_AFTER:
*val = LIS2MDL_CHECK_AFTER;
break;
+
default:
*val = LIS2MDL_CHECK_BEFORE;
break;
}
+
return ret;
}
@@ -947,11 +1015,12 @@ int32_t lis2mdl_drdy_on_pin_set(stmdev_ctx_t *ctx, uint8_t val)
lis2mdl_cfg_reg_c_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t*)®, 1);
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.drdy_on_pin = val;
- ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t*)®, 1);
+ ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
}
return ret;
@@ -970,7 +1039,7 @@ int32_t lis2mdl_drdy_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2mdl_cfg_reg_c_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t*)®, 1);
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
*val = reg.drdy_on_pin;
return ret;
@@ -989,11 +1058,12 @@ int32_t lis2mdl_int_on_pin_set(stmdev_ctx_t *ctx, uint8_t val)
lis2mdl_cfg_reg_c_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t*)®, 1);
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.int_on_pin = val;
- ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t*)®, 1);
+ ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
}
return ret;
@@ -1012,7 +1082,7 @@ int32_t lis2mdl_int_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val)
lis2mdl_cfg_reg_c_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t*)®, 1);
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
*val = reg.int_on_pin;
return ret;
@@ -1030,7 +1100,9 @@ int32_t lis2mdl_int_gen_conf_set(stmdev_ctx_t *ctx,
lis2mdl_int_crtl_reg_t *val)
{
int32_t ret;
- ret = lis2mdl_write_reg(ctx, LIS2MDL_INT_CRTL_REG, (uint8_t*) val, 1);
+
+ ret = lis2mdl_write_reg(ctx, LIS2MDL_INT_CRTL_REG, (uint8_t *) val, 1);
+
return ret;
}
@@ -1046,7 +1118,9 @@ int32_t lis2mdl_int_gen_conf_get(stmdev_ctx_t *ctx,
lis2mdl_int_crtl_reg_t *val)
{
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_INT_CRTL_REG, (uint8_t*) val, 1);
+
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_INT_CRTL_REG, (uint8_t *) val, 1);
+
return ret;
}
@@ -1062,7 +1136,9 @@ int32_t lis2mdl_int_gen_source_get(stmdev_ctx_t *ctx,
lis2mdl_int_source_reg_t *val)
{
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_INT_SOURCE_REG, (uint8_t*) val, 1);
+
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_INT_SOURCE_REG, (uint8_t *) val, 1);
+
return ret;
}
@@ -1081,8 +1157,8 @@ int32_t lis2mdl_int_gen_treshold_set(stmdev_ctx_t *ctx, uint16_t val)
uint8_t buff[2];
int32_t ret;
- buff[1] = (uint8_t) (val / 256U);
- buff[0] = (uint8_t) (val - (buff[1] * 256U));
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
ret = lis2mdl_write_reg(ctx, LIS2MDL_INT_THS_L_REG, buff, 2);
return ret;
@@ -1136,11 +1212,12 @@ int32_t lis2mdl_spi_mode_set(stmdev_ctx_t *ctx, lis2mdl_sim_t val)
lis2mdl_cfg_reg_c_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t*)®, 1);
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg._4wspi = (uint8_t)val;
- ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t*)®, 1);
+ ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
}
return ret;
@@ -1159,18 +1236,23 @@ int32_t lis2mdl_spi_mode_get(stmdev_ctx_t *ctx, lis2mdl_sim_t *val)
lis2mdl_cfg_reg_c_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t*)®, 1);
- switch (reg._4wspi){
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
+
+ switch (reg._4wspi)
+ {
case LIS2MDL_SPI_4_WIRE:
*val = LIS2MDL_SPI_4_WIRE;
break;
+
case LIS2MDL_SPI_3_WIRE:
*val = LIS2MDL_SPI_3_WIRE;
break;
+
default:
*val = LIS2MDL_SPI_3_WIRE;
break;
}
+
return ret;
}
@@ -1182,16 +1264,18 @@ int32_t lis2mdl_spi_mode_get(stmdev_ctx_t *ctx, lis2mdl_sim_t *val)
* @retval interface status.(MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2mdl_i2c_interface_set(stmdev_ctx_t *ctx, lis2mdl_i2c_dis_t val)
+int32_t lis2mdl_i2c_interface_set(stmdev_ctx_t *ctx,
+ lis2mdl_i2c_dis_t val)
{
lis2mdl_cfg_reg_c_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t*)®, 1);
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
reg.i2c_dis = (uint8_t)val;
- ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t*)®, 1);
+ ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
}
return ret;
@@ -1205,23 +1289,29 @@ int32_t lis2mdl_i2c_interface_set(stmdev_ctx_t *ctx, lis2mdl_i2c_dis_t val)
* @retval interface status.(MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis2mdl_i2c_interface_get(stmdev_ctx_t *ctx, lis2mdl_i2c_dis_t *val)
+int32_t lis2mdl_i2c_interface_get(stmdev_ctx_t *ctx,
+ lis2mdl_i2c_dis_t *val)
{
lis2mdl_cfg_reg_c_t reg;
int32_t ret;
- ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t*)®, 1);
- switch (reg.i2c_dis){
+ ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
+
+ switch (reg.i2c_dis)
+ {
case LIS2MDL_I2C_ENABLE:
*val = LIS2MDL_I2C_ENABLE;
break;
+
case LIS2MDL_I2C_DISABLE:
*val = LIS2MDL_I2C_DISABLE;
break;
+
default:
*val = LIS2MDL_I2C_ENABLE;
break;
}
+
return ret;
}
diff --git a/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.h b/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.h
index 965cc6be73d21c9eee3e1d86425741a561c4f663..c50307dcdb7e23f89f9f062aa2f3994fe2ceacda 100644
--- a/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.h
+++ b/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.h
@@ -1,29 +1,29 @@
-/*
- ******************************************************************************
- * @file lis2mdl_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lis2mdl_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lis2mdl_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lis2mdl_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LIS2MDL_REGS_H
#define LIS2MDL_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -75,7 +75,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -108,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -132,7 +134,7 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
+ * You can create a sensor configuration by your own or using
* Unico / Unicleo tools available on STMicroelectronics
* web site.
*
@@ -140,7 +142,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -162,7 +165,7 @@ typedef struct {
*
*/
- /** I2C Device Address 8 bit format **/
+/** I2C Device Address 8 bit format **/
#define LIS2MDL_I2C_ADD 0x3DU
/** Device Identification (Who am I) **/
@@ -181,7 +184,8 @@ typedef struct {
#define LIS2MDL_OFFSET_Z_REG_H 0x4AU
#define LIS2MDL_WHO_AM_I 0x4FU
#define LIS2MDL_CFG_REG_A 0x60U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t md : 2;
uint8_t odr : 2;
@@ -200,7 +204,8 @@ typedef struct {
} lis2mdl_cfg_reg_a_t;
#define LIS2MDL_CFG_REG_B 0x61U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lpf : 1;
uint8_t set_rst : 2; /* OFF_CANC + Set_FREQ */
@@ -217,7 +222,8 @@ typedef struct {
} lis2mdl_cfg_reg_b_t;
#define LIS2MDL_CFG_REG_C 0x62U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t drdy_on_pin : 1;
uint8_t self_test : 1;
@@ -240,7 +246,8 @@ typedef struct {
} lis2mdl_cfg_reg_c_t;
#define LIS2MDL_INT_CRTL_REG 0x63U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ien : 1;
uint8_t iel : 1;
@@ -261,7 +268,8 @@ typedef struct {
} lis2mdl_int_crtl_reg_t;
#define LIS2MDL_INT_SOURCE_REG 0x64U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t _int : 1;
uint8_t mroi : 1;
@@ -286,7 +294,8 @@ typedef struct {
#define LIS2MDL_INT_THS_L_REG 0x65U
#define LIS2MDL_INT_THS_H_REG 0x66U
#define LIS2MDL_STATUS_REG 0x67U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xda : 1;
uint8_t yda : 1;
@@ -319,9 +328,9 @@ typedef struct {
/**
* @defgroup LIS2MDL_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -329,7 +338,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
lis2mdl_cfg_reg_a_t cfg_reg_a;
lis2mdl_cfg_reg_b_t cfg_reg_b;
lis2mdl_cfg_reg_c_t cfg_reg_c;
@@ -345,26 +355,33 @@ typedef union{
*
*/
-int32_t lis2mdl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lis2mdl_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t lis2mdl_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lis2mdl_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-
+
float_t lis2mdl_from_lsb_to_mgauss(int16_t lsb);
+
float_t lis2mdl_from_lsb_to_celsius(int16_t lsb);
int32_t lis2mdl_mag_user_offset_set(stmdev_ctx_t *ctx, int16_t *val);
int32_t lis2mdl_mag_user_offset_get(stmdev_ctx_t *ctx, int16_t *val);
-typedef enum {
+typedef enum
+{
LIS2MDL_CONTINUOUS_MODE = 0,
LIS2MDL_SINGLE_TRIGGER = 1,
LIS2MDL_POWER_DOWN = 2,
} lis2mdl_md_t;
-int32_t lis2mdl_operating_mode_set(stmdev_ctx_t *ctx, lis2mdl_md_t val);
-int32_t lis2mdl_operating_mode_get(stmdev_ctx_t *ctx, lis2mdl_md_t *val);
+int32_t lis2mdl_operating_mode_set(stmdev_ctx_t *ctx,
+ lis2mdl_md_t val);
+int32_t lis2mdl_operating_mode_get(stmdev_ctx_t *ctx,
+ lis2mdl_md_t *val);
-typedef enum {
+typedef enum
+{
LIS2MDL_ODR_10Hz = 0,
LIS2MDL_ODR_20Hz = 1,
LIS2MDL_ODR_50Hz = 2,
@@ -373,7 +390,8 @@ typedef enum {
int32_t lis2mdl_data_rate_set(stmdev_ctx_t *ctx, lis2mdl_odr_t val);
int32_t lis2mdl_data_rate_get(stmdev_ctx_t *ctx, lis2mdl_odr_t *val);
-typedef enum {
+typedef enum
+{
LIS2MDL_HIGH_RESOLUTION = 0,
LIS2MDL_LOW_POWER = 1,
} lis2mdl_lp_t;
@@ -383,7 +401,8 @@ int32_t lis2mdl_power_mode_get(stmdev_ctx_t *ctx, lis2mdl_lp_t *val);
int32_t lis2mdl_offset_temp_comp_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2mdl_offset_temp_comp_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2MDL_ODR_DIV_2 = 0,
LIS2MDL_ODR_DIV_4 = 1,
} lis2mdl_lpf_t;
@@ -392,7 +411,8 @@ int32_t lis2mdl_low_pass_bandwidth_set(stmdev_ctx_t *ctx,
int32_t lis2mdl_low_pass_bandwidth_get(stmdev_ctx_t *ctx,
lis2mdl_lpf_t *val);
-typedef enum {
+typedef enum
+{
LIS2MDL_SET_SENS_ODR_DIV_63 = 0,
LIS2MDL_SENS_OFF_CANC_EVERY_ODR = 1,
LIS2MDL_SET_SENS_ONLY_AT_POWER_ON = 2,
@@ -408,7 +428,8 @@ int32_t lis2mdl_set_rst_sensor_single_get(stmdev_ctx_t *ctx,
uint8_t *val);
int32_t lis2mdl_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis2mdl_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis2mdl_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lis2mdl_mag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -429,16 +450,20 @@ int32_t lis2mdl_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2mdl_self_test_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2mdl_self_test_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS2MDL_LSB_AT_LOW_ADD = 0,
LIS2MDL_MSB_AT_LOW_ADD = 1,
} lis2mdl_ble_t;
int32_t lis2mdl_data_format_set(stmdev_ctx_t *ctx, lis2mdl_ble_t val);
-int32_t lis2mdl_data_format_get(stmdev_ctx_t *ctx, lis2mdl_ble_t *val);
+int32_t lis2mdl_data_format_get(stmdev_ctx_t *ctx,
+ lis2mdl_ble_t *val);
-int32_t lis2mdl_status_get(stmdev_ctx_t *ctx, lis2mdl_status_reg_t *val);
+int32_t lis2mdl_status_get(stmdev_ctx_t *ctx,
+ lis2mdl_status_reg_t *val);
-typedef enum {
+typedef enum
+{
LIS2MDL_CHECK_BEFORE = 0,
LIS2MDL_CHECK_AFTER = 1,
} lis2mdl_int_on_dataoff_t;
@@ -462,16 +487,19 @@ int32_t lis2mdl_int_gen_source_get(stmdev_ctx_t *ctx,
lis2mdl_int_source_reg_t *val);
int32_t lis2mdl_int_gen_treshold_set(stmdev_ctx_t *ctx, uint16_t val);
-int32_t lis2mdl_int_gen_treshold_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t lis2mdl_int_gen_treshold_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
-typedef enum {
+typedef enum
+{
LIS2MDL_SPI_4_WIRE = 1,
LIS2MDL_SPI_3_WIRE = 0,
} lis2mdl_sim_t;
int32_t lis2mdl_spi_mode_set(stmdev_ctx_t *ctx, lis2mdl_sim_t val);
int32_t lis2mdl_spi_mode_get(stmdev_ctx_t *ctx, lis2mdl_sim_t *val);
-typedef enum {
+typedef enum
+{
LIS2MDL_I2C_ENABLE = 0,
LIS2MDL_I2C_DISABLE = 1,
} lis2mdl_i2c_dis_t;
diff --git a/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.c b/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.c
index 2a7d719e5529d2abf85aa3d39ac239203055bb28..cd4e5aa74cb0e8a3739fd28d575d444aef9bcf2c 100644
--- a/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.c
+++ b/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file lis331dlh_reg.c
- * @author Sensors Software Solution Team
- * @brief LIS331DLH driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lis331dlh_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LIS331DLH driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lis331dlh_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis331dlh_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lis331dlh_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t lis331dlh_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis331dlh_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lis331dlh_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -77,26 +83,26 @@ int32_t lis331dlh_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
*
*/
- /**
+/**
* @defgroup LIS331DLH_Sensitivity
* @brief These functions convert raw-data into engineering units.
* @{
*
*/
-float lis331dlh_from_fs2_to_mg(int16_t lsb)
+float_t lis331dlh_from_fs2_to_mg(int16_t lsb)
{
- return ((float)lsb / 16.0f);
+ return ((float_t)lsb / 16.0f);
}
-float lis331dlh_from_fs4_to_mg(int16_t lsb)
+float_t lis331dlh_from_fs4_to_mg(int16_t lsb)
{
- return ((float)lsb * 2.0f / 16.0f);
+ return ((float_t)lsb * 2.0f / 16.0f);
}
-float lis331dlh_from_fs8_to_mg(int16_t lsb)
+float_t lis331dlh_from_fs8_to_mg(int16_t lsb)
{
- return ((float)lsb * 3.9f / 16.0f);
+ return ((float_t)lsb * 3.9f / 16.0f);
}
/**
@@ -117,6 +123,7 @@ float lis331dlh_from_fs8_to_mg(int16_t lsb)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of xen in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -124,12 +131,16 @@ int32_t lis331dlh_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val)
lis331dlh_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0) {
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.xen = val;
ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -138,6 +149,7 @@ int32_t lis331dlh_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of xen in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -145,7 +157,8 @@ int32_t lis331dlh_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val)
lis331dlh_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
*val = ctrl_reg1.xen;
return ret;
@@ -156,6 +169,7 @@ int32_t lis331dlh_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of yen in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -163,12 +177,16 @@ int32_t lis331dlh_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val)
lis331dlh_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0) {
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.yen = val;
ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -177,6 +195,7 @@ int32_t lis331dlh_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of yen in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -184,7 +203,8 @@ int32_t lis331dlh_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val)
lis331dlh_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
*val = ctrl_reg1.yen;
return ret;
@@ -195,6 +215,7 @@ int32_t lis331dlh_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of zen in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -202,12 +223,16 @@ int32_t lis331dlh_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val)
lis331dlh_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0) {
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.zen = val;
ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -216,6 +241,7 @@ int32_t lis331dlh_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of zen in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -223,7 +249,8 @@ int32_t lis331dlh_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val)
lis331dlh_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
*val = ctrl_reg1.zen;
return ret;
@@ -234,6 +261,7 @@ int32_t lis331dlh_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of dr in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_data_rate_set(stmdev_ctx_t *ctx, lis331dlh_dr_t val)
@@ -242,13 +270,16 @@ int32_t lis331dlh_data_rate_set(stmdev_ctx_t *ctx, lis331dlh_dr_t val)
int32_t ret;
ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0) {
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.pm = (uint8_t)val & 0x07U;
- ctrl_reg1.dr = ( (uint8_t)val & 0x30U ) >> 4;
+ ctrl_reg1.dr = ((uint8_t)val & 0x30U) >> 4;
ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -257,48 +288,60 @@ int32_t lis331dlh_data_rate_set(stmdev_ctx_t *ctx, lis331dlh_dr_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of dr in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis331dlh_data_rate_get(stmdev_ctx_t *ctx, lis331dlh_dr_t *val)
+int32_t lis331dlh_data_rate_get(stmdev_ctx_t *ctx,
+ lis331dlh_dr_t *val)
{
lis331dlh_ctrl_reg1_t ctrl_reg1;
int32_t ret;
ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
+ (uint8_t *)&ctrl_reg1, 1);
switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pm)
{
case LIS331DLH_ODR_OFF:
*val = LIS331DLH_ODR_OFF;
break;
+
case LIS331DLH_ODR_Hz5:
*val = LIS331DLH_ODR_Hz5;
break;
+
case LIS331DLH_ODR_1Hz:
*val = LIS331DLH_ODR_1Hz;
break;
+
case LIS331DLH_ODR_2Hz:
*val = LIS331DLH_ODR_2Hz;
break;
+
case LIS331DLH_ODR_5Hz:
*val = LIS331DLH_ODR_5Hz;
break;
+
case LIS331DLH_ODR_10Hz:
*val = LIS331DLH_ODR_10Hz;
break;
+
case LIS331DLH_ODR_50Hz:
*val = LIS331DLH_ODR_50Hz;
break;
+
case LIS331DLH_ODR_100Hz:
*val = LIS331DLH_ODR_100Hz;
break;
+
case LIS331DLH_ODR_400Hz:
*val = LIS331DLH_ODR_400Hz;
break;
+
case LIS331DLH_ODR_1kHz:
*val = LIS331DLH_ODR_1kHz;
break;
+
default:
*val = LIS331DLH_ODR_OFF;
break;
@@ -312,6 +355,7 @@ int32_t lis331dlh_data_rate_get(stmdev_ctx_t *ctx, lis331dlh_dr_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of hpm in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_reference_mode_set(stmdev_ctx_t *ctx,
@@ -320,12 +364,16 @@ int32_t lis331dlh_reference_mode_set(stmdev_ctx_t *ctx,
lis331dlh_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0) {
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpm = (uint8_t)val;
ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -334,6 +382,7 @@ int32_t lis331dlh_reference_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of hpm in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_reference_mode_get(stmdev_ctx_t *ctx,
@@ -343,20 +392,23 @@ int32_t lis331dlh_reference_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
switch (ctrl_reg2.hpm)
{
case LIS331DLH_NORMAL_MODE:
*val = LIS331DLH_NORMAL_MODE;
break;
+
case LIS331DLH_REF_MODE_ENABLE:
*val = LIS331DLH_REF_MODE_ENABLE;
break;
+
default:
*val = LIS331DLH_NORMAL_MODE;
break;
}
+
return ret;
}
@@ -365,19 +417,25 @@ int32_t lis331dlh_reference_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of fs in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis331dlh_full_scale_set(stmdev_ctx_t *ctx, lis331dlh_fs_t val)
+int32_t lis331dlh_full_scale_set(stmdev_ctx_t *ctx,
+ lis331dlh_fs_t val)
{
lis331dlh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0) {
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.fs = (uint8_t)val;
ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -386,26 +444,32 @@ int32_t lis331dlh_full_scale_set(stmdev_ctx_t *ctx, lis331dlh_fs_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of fs in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis331dlh_full_scale_get(stmdev_ctx_t *ctx, lis331dlh_fs_t *val)
+int32_t lis331dlh_full_scale_get(stmdev_ctx_t *ctx,
+ lis331dlh_fs_t *val)
{
lis331dlh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
switch (ctrl_reg4.fs)
{
case LIS331DLH_2g:
*val = LIS331DLH_2g;
break;
+
case LIS331DLH_4g:
*val = LIS331DLH_4g;
break;
+
case LIS331DLH_8g:
*val = LIS331DLH_8g;
break;
+
default:
*val = LIS331DLH_2g;
break;
@@ -419,19 +483,25 @@ int32_t lis331dlh_full_scale_get(stmdev_ctx_t *ctx, lis331dlh_fs_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of bdu in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis331dlh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lis331dlh_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lis331dlh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0) {
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.bdu = val;
ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -440,14 +510,17 @@ int32_t lis331dlh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of bdu in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis331dlh_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis331dlh_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis331dlh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
*val = ctrl_reg4.bdu;
return ret;
@@ -458,13 +531,16 @@ int32_t lis331dlh_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val registers STATUS_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_status_reg_get(stmdev_ctx_t *ctx,
lis331dlh_status_reg_t *val)
{
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_STATUS_REG, (uint8_t*) val, 1);
+
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_STATUS_REG, (uint8_t *) val, 1);
+
return ret;
}
@@ -473,6 +549,7 @@ int32_t lis331dlh_status_reg_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of zyxda in reg STATUS_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -481,7 +558,7 @@ int32_t lis331dlh_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lis331dlh_read_reg(ctx, LIS331DLH_STATUS_REG,
- (uint8_t*)&status_reg, 1);
+ (uint8_t *)&status_reg, 1);
*val = status_reg.zyxda;
return ret;
@@ -505,12 +582,23 @@ int32_t lis331dlh_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis331dlh_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lis331dlh_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lis331dlh_read_reg(ctx, LIS331DLH_OUT_X_L, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -531,12 +619,15 @@ int32_t lis331dlh_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions(ptr)
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis331dlh_read_reg(ctx, LIS331DLH_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -545,6 +636,7 @@ int32_t lis331dlh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of boot in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_boot_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -552,12 +644,16 @@ int32_t lis331dlh_boot_set(stmdev_ctx_t *ctx, uint8_t val)
lis331dlh_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0) {
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.boot = val;
ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -566,6 +662,7 @@ int32_t lis331dlh_boot_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of boot in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -573,7 +670,8 @@ int32_t lis331dlh_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
lis331dlh_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
*val = ctrl_reg2.boot;
return ret;
@@ -584,6 +682,7 @@ int32_t lis331dlh_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of st in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_self_test_set(stmdev_ctx_t *ctx, lis331dlh_st_t val)
@@ -591,12 +690,16 @@ int32_t lis331dlh_self_test_set(stmdev_ctx_t *ctx, lis331dlh_st_t val)
lis331dlh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0) {
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.st = (uint8_t)val;
ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -605,26 +708,32 @@ int32_t lis331dlh_self_test_set(stmdev_ctx_t *ctx, lis331dlh_st_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of st in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis331dlh_self_test_get(stmdev_ctx_t *ctx, lis331dlh_st_t *val)
+int32_t lis331dlh_self_test_get(stmdev_ctx_t *ctx,
+ lis331dlh_st_t *val)
{
lis331dlh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
switch (ctrl_reg4.st)
{
case LIS331DLH_ST_DISABLE:
*val = LIS331DLH_ST_DISABLE;
break;
+
case LIS331DLH_ST_POSITIVE:
*val = LIS331DLH_ST_POSITIVE;
break;
+
case LIS331DLH_ST_NEGATIVE:
*val = LIS331DLH_ST_NEGATIVE;
break;
+
default:
*val = LIS331DLH_ST_DISABLE;
break;
@@ -638,19 +747,25 @@ int32_t lis331dlh_self_test_get(stmdev_ctx_t *ctx, lis331dlh_st_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ble in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis331dlh_data_format_set(stmdev_ctx_t *ctx, lis331dlh_ble_t val)
+int32_t lis331dlh_data_format_set(stmdev_ctx_t *ctx,
+ lis331dlh_ble_t val)
{
lis331dlh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0) {
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.ble = (uint8_t)val;
ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -659,23 +774,28 @@ int32_t lis331dlh_data_format_set(stmdev_ctx_t *ctx, lis331dlh_ble_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of ble in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis331dlh_data_format_get(stmdev_ctx_t *ctx, lis331dlh_ble_t *val)
+int32_t lis331dlh_data_format_get(stmdev_ctx_t *ctx,
+ lis331dlh_ble_t *val)
{
lis331dlh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
switch (ctrl_reg4.ble)
{
case LIS331DLH_LSB_AT_LOW_ADD:
*val = LIS331DLH_LSB_AT_LOW_ADD;
break;
+
case LIS331DLH_MSB_AT_LOW_ADD:
*val = LIS331DLH_MSB_AT_LOW_ADD;
break;
+
default:
*val = LIS331DLH_LSB_AT_LOW_ADD;
break;
@@ -702,19 +822,25 @@ int32_t lis331dlh_data_format_get(stmdev_ctx_t *ctx, lis331dlh_ble_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of hpcf in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis331dlh_hp_bandwidth_set(stmdev_ctx_t *ctx, lis331dlh_hpcf_t val)
+int32_t lis331dlh_hp_bandwidth_set(stmdev_ctx_t *ctx,
+ lis331dlh_hpcf_t val)
{
lis331dlh_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0) {
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpcf = (uint8_t)val;
ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -723,6 +849,7 @@ int32_t lis331dlh_hp_bandwidth_set(stmdev_ctx_t *ctx, lis331dlh_hpcf_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of hpcf in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_hp_bandwidth_get(stmdev_ctx_t *ctx,
@@ -731,22 +858,27 @@ int32_t lis331dlh_hp_bandwidth_get(stmdev_ctx_t *ctx,
lis331dlh_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
switch (ctrl_reg2.hpcf)
{
case LIS331DLH_CUT_OFF_8Hz:
*val = LIS331DLH_CUT_OFF_8Hz;
break;
+
case LIS331DLH_CUT_OFF_16Hz:
*val = LIS331DLH_CUT_OFF_16Hz;
break;
+
case LIS331DLH_CUT_OFF_32Hz:
*val = LIS331DLH_CUT_OFF_32Hz;
break;
+
case LIS331DLH_CUT_OFF_64Hz:
*val = LIS331DLH_CUT_OFF_64Hz;
break;
+
default:
*val = LIS331DLH_CUT_OFF_8Hz;
break;
@@ -760,6 +892,7 @@ int32_t lis331dlh_hp_bandwidth_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of hpen in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_hp_path_set(stmdev_ctx_t *ctx, lis331dlh_hpen_t val)
@@ -767,13 +900,17 @@ int32_t lis331dlh_hp_path_set(stmdev_ctx_t *ctx, lis331dlh_hpen_t val)
lis331dlh_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0) {
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpen = (uint8_t)val & 0x03U;
ctrl_reg2.fds = ((uint8_t)val & 0x04U) >> 2;
ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG2,
- (uint8_t*)&ctrl_reg2, 1);
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -782,45 +919,57 @@ int32_t lis331dlh_hp_path_set(stmdev_ctx_t *ctx, lis331dlh_hpen_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of hpen in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis331dlh_hp_path_get(stmdev_ctx_t *ctx, lis331dlh_hpen_t *val)
+int32_t lis331dlh_hp_path_get(stmdev_ctx_t *ctx,
+ lis331dlh_hpen_t *val)
{
lis331dlh_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
- switch ( (ctrl_reg2.fds << 2) + ctrl_reg2.hpen )
+ switch ((ctrl_reg2.fds << 2) + ctrl_reg2.hpen)
{
case LIS331DLH_HP_DISABLE:
*val = LIS331DLH_HP_DISABLE;
break;
+
case LIS331DLH_HP_ON_OUT:
*val = LIS331DLH_HP_ON_OUT;
break;
+
case LIS331DLH_HP_ON_INT1:
*val = LIS331DLH_HP_ON_INT1;
break;
+
case LIS331DLH_HP_ON_INT2:
*val = LIS331DLH_HP_ON_INT2;
break;
+
case LIS331DLH_HP_ON_INT1_INT2:
*val = LIS331DLH_HP_ON_INT1_INT2;
break;
+
case LIS331DLH_HP_ON_INT1_INT2_OUT:
*val = LIS331DLH_HP_ON_INT1_INT2_OUT;
break;
+
case LIS331DLH_HP_ON_INT2_OUT:
*val = LIS331DLH_HP_ON_INT2_OUT;
break;
+
case LIS331DLH_HP_ON_INT1_OUT:
*val = LIS331DLH_HP_ON_INT1_OUT;
break;
+
default:
*val = LIS331DLH_HP_DISABLE;
break;
}
+
return ret;
}
@@ -833,14 +982,17 @@ int32_t lis331dlh_hp_path_get(stmdev_ctx_t *ctx, lis331dlh_hpen_t *val)
* filter.[get]
*
* @param ctx read / write interface definitions(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_hp_reset_get(stmdev_ctx_t *ctx)
{
uint8_t dummy;
int32_t ret;
+
ret = lis331dlh_read_reg(ctx, LIS331DLH_HP_FILTER_RESET,
- (uint8_t*)&dummy, 1);
+ (uint8_t *)&dummy, 1);
+
return ret;
}
@@ -849,12 +1001,16 @@ int32_t lis331dlh_hp_reset_get(stmdev_ctx_t *ctx)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ref in reg REFERENCE
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis331dlh_hp_reference_value_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lis331dlh_hp_reference_value_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
int32_t ret;
- ret = lis331dlh_write_reg(ctx, LIS331DLH_REFERENCE, (uint8_t*)&val, 1);
+
+ ret = lis331dlh_write_reg(ctx, LIS331DLH_REFERENCE, (uint8_t *)&val, 1);
+
return ret;
}
@@ -863,12 +1019,16 @@ int32_t lis331dlh_hp_reference_value_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ref in reg REFERENCE
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis331dlh_hp_reference_value_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis331dlh_hp_reference_value_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
int32_t ret;
+
ret = lis331dlh_read_reg(ctx, LIS331DLH_REFERENCE, val, 1);
+
return ret;
}
@@ -890,6 +1050,7 @@ int32_t lis331dlh_hp_reference_value_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of sim in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_spi_mode_set(stmdev_ctx_t *ctx, lis331dlh_sim_t val)
@@ -897,12 +1058,16 @@ int32_t lis331dlh_spi_mode_set(stmdev_ctx_t *ctx, lis331dlh_sim_t val)
lis331dlh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0) {
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.sim = (uint8_t)val;
ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -911,23 +1076,28 @@ int32_t lis331dlh_spi_mode_set(stmdev_ctx_t *ctx, lis331dlh_sim_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of sim in reg CTRL_REG4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis331dlh_spi_mode_get(stmdev_ctx_t *ctx, lis331dlh_sim_t *val)
+int32_t lis331dlh_spi_mode_get(stmdev_ctx_t *ctx,
+ lis331dlh_sim_t *val)
{
lis331dlh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4,
+ (uint8_t *)&ctrl_reg4, 1);
- switch ( ctrl_reg4.sim )
+ switch (ctrl_reg4.sim)
{
case LIS331DLH_SPI_4_WIRE:
*val = LIS331DLH_SPI_4_WIRE;
break;
+
case LIS331DLH_SPI_3_WIRE:
*val = LIS331DLH_SPI_3_WIRE;
break;
+
default:
*val = LIS331DLH_SPI_4_WIRE;
break;
@@ -954,6 +1124,7 @@ int32_t lis331dlh_spi_mode_get(stmdev_ctx_t *ctx, lis331dlh_sim_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of i1_cfg in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_pin_int1_route_set(stmdev_ctx_t *ctx,
@@ -962,12 +1133,16 @@ int32_t lis331dlh_pin_int1_route_set(stmdev_ctx_t *ctx,
lis331dlh_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.i1_cfg = (uint8_t)val;
ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -976,6 +1151,7 @@ int32_t lis331dlh_pin_int1_route_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of i1_cfg in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_pin_int1_route_get(stmdev_ctx_t *ctx,
@@ -984,22 +1160,27 @@ int32_t lis331dlh_pin_int1_route_get(stmdev_ctx_t *ctx,
lis331dlh_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.i1_cfg )
+ switch (ctrl_reg3.i1_cfg)
{
case LIS331DLH_PAD1_INT1_SRC:
*val = LIS331DLH_PAD1_INT1_SRC;
break;
+
case LIS331DLH_PAD1_INT1_OR_INT2_SRC:
*val = LIS331DLH_PAD1_INT1_OR_INT2_SRC;
break;
+
case LIS331DLH_PAD1_DRDY:
*val = LIS331DLH_PAD1_DRDY;
break;
+
case LIS331DLH_PAD1_BOOT:
*val = LIS331DLH_PAD1_BOOT;
break;
+
default:
*val = LIS331DLH_PAD1_INT1_SRC;
break;
@@ -1014,6 +1195,7 @@ int32_t lis331dlh_pin_int1_route_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of lir1 in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_int1_notification_set(stmdev_ctx_t *ctx,
@@ -1022,12 +1204,16 @@ int32_t lis331dlh_int1_notification_set(stmdev_ctx_t *ctx,
lis331dlh_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.lir1 = (uint8_t)val;
ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1037,6 +1223,7 @@ int32_t lis331dlh_int1_notification_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of lir1 in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_int1_notification_get(stmdev_ctx_t *ctx,
@@ -1045,16 +1232,19 @@ int32_t lis331dlh_int1_notification_get(stmdev_ctx_t *ctx,
lis331dlh_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.lir1 )
+ switch (ctrl_reg3.lir1)
{
case LIS331DLH_INT1_PULSED:
*val = LIS331DLH_INT1_PULSED;
break;
+
case LIS331DLH_INT1_LATCHED:
*val = LIS331DLH_INT1_LATCHED;
break;
+
default:
*val = LIS331DLH_INT1_PULSED;
break;
@@ -1068,6 +1258,7 @@ int32_t lis331dlh_int1_notification_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of i2_cfg in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_pin_int2_route_set(stmdev_ctx_t *ctx,
@@ -1076,12 +1267,16 @@ int32_t lis331dlh_pin_int2_route_set(stmdev_ctx_t *ctx,
lis331dlh_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.i2_cfg = (uint8_t)val;
ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1090,6 +1285,7 @@ int32_t lis331dlh_pin_int2_route_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of i2_cfg in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_pin_int2_route_get(stmdev_ctx_t *ctx,
@@ -1098,22 +1294,27 @@ int32_t lis331dlh_pin_int2_route_get(stmdev_ctx_t *ctx,
lis331dlh_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.i2_cfg )
+ switch (ctrl_reg3.i2_cfg)
{
case LIS331DLH_PAD2_INT2_SRC:
*val = LIS331DLH_PAD2_INT2_SRC;
break;
+
case LIS331DLH_PAD2_INT1_OR_INT2_SRC:
*val = LIS331DLH_PAD2_INT1_OR_INT2_SRC;
break;
+
case LIS331DLH_PAD2_DRDY:
*val = LIS331DLH_PAD2_DRDY;
break;
+
case LIS331DLH_PAD2_BOOT:
*val = LIS331DLH_PAD2_BOOT;
break;
+
default:
*val = LIS331DLH_PAD2_INT2_SRC;
break;
@@ -1128,6 +1329,7 @@ int32_t lis331dlh_pin_int2_route_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of lir2 in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_int2_notification_set(stmdev_ctx_t *ctx,
@@ -1136,12 +1338,16 @@ int32_t lis331dlh_int2_notification_set(stmdev_ctx_t *ctx,
lis331dlh_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.lir2 = (uint8_t)val;
ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1151,6 +1357,7 @@ int32_t lis331dlh_int2_notification_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of lir2 in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_int2_notification_get(stmdev_ctx_t *ctx,
@@ -1159,16 +1366,19 @@ int32_t lis331dlh_int2_notification_get(stmdev_ctx_t *ctx,
lis331dlh_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.lir2 )
+ switch (ctrl_reg3.lir2)
{
case LIS331DLH_INT2_PULSED:
*val = LIS331DLH_INT2_PULSED;
break;
+
case LIS331DLH_INT2_LATCHED:
*val = LIS331DLH_INT2_LATCHED;
break;
+
default:
*val = LIS331DLH_INT2_PULSED;
break;
@@ -1182,19 +1392,25 @@ int32_t lis331dlh_int2_notification_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of pp_od in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis331dlh_pin_mode_set(stmdev_ctx_t *ctx, lis331dlh_pp_od_t val)
+int32_t lis331dlh_pin_mode_set(stmdev_ctx_t *ctx,
+ lis331dlh_pp_od_t val)
{
lis331dlh_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.pp_od = (uint8_t)val;
ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1203,23 +1419,28 @@ int32_t lis331dlh_pin_mode_set(stmdev_ctx_t *ctx, lis331dlh_pp_od_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of pp_od in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis331dlh_pin_mode_get(stmdev_ctx_t *ctx, lis331dlh_pp_od_t *val)
+int32_t lis331dlh_pin_mode_get(stmdev_ctx_t *ctx,
+ lis331dlh_pp_od_t *val)
{
lis331dlh_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.pp_od )
+ switch (ctrl_reg3.pp_od)
{
case LIS331DLH_PUSH_PULL:
*val = LIS331DLH_PUSH_PULL;
break;
+
case LIS331DLH_OPEN_DRAIN:
*val = LIS331DLH_OPEN_DRAIN;
break;
+
default:
*val = LIS331DLH_PUSH_PULL;
break;
@@ -1233,19 +1454,25 @@ int32_t lis331dlh_pin_mode_get(stmdev_ctx_t *ctx, lis331dlh_pp_od_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ihl in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis331dlh_pin_polarity_set(stmdev_ctx_t *ctx, lis331dlh_ihl_t val)
+int32_t lis331dlh_pin_polarity_set(stmdev_ctx_t *ctx,
+ lis331dlh_ihl_t val)
{
lis331dlh_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0) {
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.ihl = (uint8_t)val;
ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG3,
- (uint8_t*)&ctrl_reg3, 1);
+ (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1254,23 +1481,28 @@ int32_t lis331dlh_pin_polarity_set(stmdev_ctx_t *ctx, lis331dlh_ihl_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of ihl in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis331dlh_pin_polarity_get(stmdev_ctx_t *ctx, lis331dlh_ihl_t *val)
+int32_t lis331dlh_pin_polarity_get(stmdev_ctx_t *ctx,
+ lis331dlh_ihl_t *val)
{
lis331dlh_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
+ (uint8_t *)&ctrl_reg3, 1);
- switch ( ctrl_reg3.ihl )
+ switch (ctrl_reg3.ihl)
{
case LIS331DLH_ACTIVE_HIGH:
*val = LIS331DLH_ACTIVE_HIGH;
break;
+
case LIS331DLH_ACTIVE_LOW:
*val = LIS331DLH_ACTIVE_LOW;
break;
+
default:
*val = LIS331DLH_ACTIVE_HIGH;
break;
@@ -1297,16 +1529,20 @@ int32_t lis331dlh_pin_polarity_get(stmdev_ctx_t *ctx, lis331dlh_ihl_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val enable sign and axis for interrupt on threshold
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_int1_on_threshold_conf_set(stmdev_ctx_t *ctx,
- int1_on_th_conf_t val)
+ int1_on_th_conf_t val)
{
lis331dlh_int1_cfg_t int1_cfg;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_CFG, (uint8_t*)&int1_cfg, 1);
- if(ret == 0) {
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_CFG,
+ (uint8_t *)&int1_cfg, 1);
+
+ if (ret == 0)
+ {
int1_cfg.xlie = val.int1_xlie;
int1_cfg.xhie = val.int1_xhie;
int1_cfg.ylie = val.int1_ylie;
@@ -1314,8 +1550,9 @@ int32_t lis331dlh_int1_on_threshold_conf_set(stmdev_ctx_t *ctx,
int1_cfg.zlie = val.int1_zlie;
int1_cfg.zhie = val.int1_zhie;
ret = lis331dlh_write_reg(ctx, LIS331DLH_INT1_CFG,
- (uint8_t*)&int1_cfg, 1);
+ (uint8_t *)&int1_cfg, 1);
}
+
return ret;
}
@@ -1324,6 +1561,7 @@ int32_t lis331dlh_int1_on_threshold_conf_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val enable sign and axis for interrupt on threshold
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_int1_on_threshold_conf_get(stmdev_ctx_t *ctx,
@@ -1332,7 +1570,8 @@ int32_t lis331dlh_int1_on_threshold_conf_get(stmdev_ctx_t *ctx,
lis331dlh_int1_cfg_t int1_cfg;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_CFG, (uint8_t*)&int1_cfg, 1);
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_CFG,
+ (uint8_t *)&int1_cfg, 1);
val->int1_xlie = int1_cfg.xlie;
val->int1_xhie = int1_cfg.xhie;
val->int1_ylie = int1_cfg.ylie;
@@ -1348,6 +1587,7 @@ int32_t lis331dlh_int1_on_threshold_conf_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of aoi in reg INT1_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_int1_on_threshold_mode_set(stmdev_ctx_t *ctx,
@@ -1356,12 +1596,16 @@ int32_t lis331dlh_int1_on_threshold_mode_set(stmdev_ctx_t *ctx,
lis331dlh_int1_cfg_t int1_cfg;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_CFG, (uint8_t*)&int1_cfg, 1);
- if(ret == 0) {
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_CFG,
+ (uint8_t *)&int1_cfg, 1);
+
+ if (ret == 0)
+ {
int1_cfg.aoi = (uint8_t) val;
ret = lis331dlh_write_reg(ctx, LIS331DLH_INT1_CFG,
- (uint8_t*)&int1_cfg, 1);
+ (uint8_t *)&int1_cfg, 1);
}
+
return ret;
}
@@ -1370,6 +1614,7 @@ int32_t lis331dlh_int1_on_threshold_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of aoi in reg INT1_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_int1_on_threshold_mode_get(stmdev_ctx_t *ctx,
@@ -1378,16 +1623,19 @@ int32_t lis331dlh_int1_on_threshold_mode_get(stmdev_ctx_t *ctx,
lis331dlh_int1_cfg_t int1_cfg;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_CFG, (uint8_t*)&int1_cfg, 1);
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_CFG,
+ (uint8_t *)&int1_cfg, 1);
- switch ( int1_cfg.aoi )
+ switch (int1_cfg.aoi)
{
case LIS331DLH_INT1_ON_THRESHOLD_OR:
*val = LIS331DLH_INT1_ON_THRESHOLD_OR;
break;
+
case LIS331DLH_INT1_ON_THRESHOLD_AND:
*val = LIS331DLH_INT1_ON_THRESHOLD_AND;
break;
+
default:
*val = LIS331DLH_INT1_ON_THRESHOLD_OR;
break;
@@ -1401,13 +1649,16 @@ int32_t lis331dlh_int1_on_threshold_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val registers INT1_SRC
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_int1_src_get(stmdev_ctx_t *ctx,
lis331dlh_int1_src_t *val)
{
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_SRC, (uint8_t*) val, 1);
+
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_SRC, (uint8_t *) val, 1);
+
return ret;
}
@@ -1416,6 +1667,7 @@ int32_t lis331dlh_int1_src_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ths in reg INT1_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1423,12 +1675,16 @@ int32_t lis331dlh_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
lis331dlh_int1_ths_t int1_ths;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_THS, (uint8_t*)&int1_ths, 1);
- if(ret == 0) {
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_THS,
+ (uint8_t *)&int1_ths, 1);
+
+ if (ret == 0)
+ {
int1_ths.ths = val;
ret = lis331dlh_write_reg(ctx, LIS331DLH_INT1_THS,
- (uint8_t*)&int1_ths, 1);
+ (uint8_t *)&int1_ths, 1);
}
+
return ret;
}
@@ -1437,6 +1693,7 @@ int32_t lis331dlh_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ths in reg INT1_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1444,7 +1701,8 @@ int32_t lis331dlh_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
lis331dlh_int1_ths_t int1_ths;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_THS, (uint8_t*)&int1_ths, 1);
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_THS,
+ (uint8_t *)&int1_ths, 1);
*val = int1_ths.ths;
return ret;
@@ -1455,6 +1713,7 @@ int32_t lis331dlh_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of d in reg INT1_DURATION
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1463,12 +1722,15 @@ int32_t lis331dlh_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_DURATION,
- (uint8_t*)&int1_duration, 1);
- if(ret == 0) {
+ (uint8_t *)&int1_duration, 1);
+
+ if (ret == 0)
+ {
int1_duration.d = val;
ret = lis331dlh_write_reg(ctx, LIS331DLH_INT1_DURATION,
- (uint8_t*)&int1_duration, 1);
+ (uint8_t *)&int1_duration, 1);
}
+
return ret;
}
@@ -1477,6 +1739,7 @@ int32_t lis331dlh_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of d in reg INT1_DURATION
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1485,7 +1748,7 @@ int32_t lis331dlh_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_DURATION,
- (uint8_t*)&int1_duration, 1);
+ (uint8_t *)&int1_duration, 1);
*val = int1_duration.d;
return ret;
@@ -1496,17 +1759,20 @@ int32_t lis331dlh_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val enable sign and axis for interrupt on threshold
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_int2_on_threshold_conf_set(stmdev_ctx_t *ctx,
- int2_on_th_conf_t val)
+ int2_on_th_conf_t val)
{
lis331dlh_int2_cfg_t int2_cfg;
int32_t ret;
ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_CFG,
- (uint8_t*)&int2_cfg, 1);
- if(ret == 0) {
+ (uint8_t *)&int2_cfg, 1);
+
+ if (ret == 0)
+ {
int2_cfg.xlie = val.int2_xlie;
int2_cfg.xhie = val.int2_xhie;
int2_cfg.ylie = val.int2_ylie;
@@ -1514,8 +1780,9 @@ int32_t lis331dlh_int2_on_threshold_conf_set(stmdev_ctx_t *ctx,
int2_cfg.zlie = val.int2_zlie;
int2_cfg.zhie = val.int2_zhie;
ret = lis331dlh_write_reg(ctx, LIS331DLH_INT2_CFG,
- (uint8_t*)&int2_cfg, 1);
+ (uint8_t *)&int2_cfg, 1);
}
+
return ret;
}
@@ -1524,15 +1791,17 @@ int32_t lis331dlh_int2_on_threshold_conf_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val enable sign and axis for interrupt on threshold
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_int2_on_threshold_conf_get(stmdev_ctx_t *ctx,
- int2_on_th_conf_t *val)
+ int2_on_th_conf_t *val)
{
lis331dlh_int2_cfg_t int2_cfg;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_CFG, (uint8_t*)&int2_cfg, 1);
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_CFG,
+ (uint8_t *)&int2_cfg, 1);
val->int2_xlie = int2_cfg.xlie;
val->int2_xhie = int2_cfg.xhie;
val->int2_ylie = int2_cfg.ylie;
@@ -1548,6 +1817,7 @@ int32_t lis331dlh_int2_on_threshold_conf_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of aoi in reg INT2_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_int2_on_threshold_mode_set(stmdev_ctx_t *ctx,
@@ -1556,12 +1826,16 @@ int32_t lis331dlh_int2_on_threshold_mode_set(stmdev_ctx_t *ctx,
lis331dlh_int2_cfg_t int2_cfg;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_CFG, (uint8_t*)&int2_cfg, 1);
- if(ret == 0) {
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_CFG,
+ (uint8_t *)&int2_cfg, 1);
+
+ if (ret == 0)
+ {
int2_cfg.aoi = (uint8_t) val;
ret = lis331dlh_write_reg(ctx, LIS331DLH_INT2_CFG,
- (uint8_t*)&int2_cfg, 1);
+ (uint8_t *)&int2_cfg, 1);
}
+
return ret;
}
@@ -1570,6 +1844,7 @@ int32_t lis331dlh_int2_on_threshold_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of aoi in reg INT2_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_int2_on_threshold_mode_get(stmdev_ctx_t *ctx,
@@ -1578,16 +1853,19 @@ int32_t lis331dlh_int2_on_threshold_mode_get(stmdev_ctx_t *ctx,
lis331dlh_int2_cfg_t int2_cfg;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_CFG, (uint8_t*)&int2_cfg, 1);
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_CFG,
+ (uint8_t *)&int2_cfg, 1);
- switch ( int2_cfg.aoi )
+ switch (int2_cfg.aoi)
{
case LIS331DLH_INT2_ON_THRESHOLD_OR:
*val = LIS331DLH_INT2_ON_THRESHOLD_OR;
break;
+
case LIS331DLH_INT2_ON_THRESHOLD_AND:
*val = LIS331DLH_INT2_ON_THRESHOLD_AND;
break;
+
default:
*val = LIS331DLH_INT2_ON_THRESHOLD_OR;
break;
@@ -1601,13 +1879,16 @@ int32_t lis331dlh_int2_on_threshold_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val registers INT2_SRC
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_int2_src_get(stmdev_ctx_t *ctx,
lis331dlh_int2_src_t *val)
{
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_SRC, (uint8_t*) val, 1);
+
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_SRC, (uint8_t *) val, 1);
+
return ret;
}
@@ -1616,6 +1897,7 @@ int32_t lis331dlh_int2_src_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ths in reg INT2_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1623,12 +1905,16 @@ int32_t lis331dlh_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
lis331dlh_int2_ths_t int2_ths;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_THS, (uint8_t*)&int2_ths, 1);
- if(ret == 0) {
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_THS,
+ (uint8_t *)&int2_ths, 1);
+
+ if (ret == 0)
+ {
int2_ths.ths = val;
ret = lis331dlh_write_reg(ctx, LIS331DLH_INT2_THS,
- (uint8_t*)&int2_ths, 1);
+ (uint8_t *)&int2_ths, 1);
}
+
return ret;
}
@@ -1637,6 +1923,7 @@ int32_t lis331dlh_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ths in reg INT2_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1644,7 +1931,8 @@ int32_t lis331dlh_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
lis331dlh_int2_ths_t int2_ths;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_THS, (uint8_t*)&int2_ths, 1);
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_THS,
+ (uint8_t *)&int2_ths, 1);
*val = int2_ths.ths;
return ret;
@@ -1655,6 +1943,7 @@ int32_t lis331dlh_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of d in reg INT2_DURATION
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1663,12 +1952,15 @@ int32_t lis331dlh_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_DURATION,
- (uint8_t*)&int2_duration, 1);
- if(ret == 0) {
+ (uint8_t *)&int2_duration, 1);
+
+ if (ret == 0)
+ {
int2_duration.d = val;
ret = lis331dlh_write_reg(ctx, LIS331DLH_INT2_DURATION,
- (uint8_t*)&int2_duration, 1);
+ (uint8_t *)&int2_duration, 1);
}
+
return ret;
}
@@ -1677,6 +1969,7 @@ int32_t lis331dlh_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of d in reg INT2_DURATION
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1685,7 +1978,7 @@ int32_t lis331dlh_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_DURATION,
- (uint8_t*)&int2_duration, 1);
+ (uint8_t *)&int2_duration, 1);
*val = int2_duration.d;
return ret;
@@ -1709,6 +2002,7 @@ int32_t lis331dlh_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of turnon in reg CTRL_REG5
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1716,12 +2010,16 @@ int32_t lis331dlh_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val)
lis331dlh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if(ret == 0) {
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.turnon = val;
ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG5,
- (uint8_t*)&ctrl_reg5, 1);
+ (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -1730,6 +2028,7 @@ int32_t lis331dlh_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of turnon in reg CTRL_REG5
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1737,7 +2036,8 @@ int32_t lis331dlh_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val)
lis331dlh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG5,
+ (uint8_t *)&ctrl_reg5, 1);
*val = ctrl_reg5.turnon;
return ret;
@@ -1761,6 +2061,7 @@ int32_t lis331dlh_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of 6d in reg INT1_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_int1_6d_mode_set(stmdev_ctx_t *ctx,
@@ -1769,12 +2070,17 @@ int32_t lis331dlh_int1_6d_mode_set(stmdev_ctx_t *ctx,
lis331dlh_int1_cfg_t int1_cfg;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_CFG, (uint8_t*)&int1_cfg, 1);
- if(ret == 0) {
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_CFG,
+ (uint8_t *)&int1_cfg, 1);
+
+ if (ret == 0)
+ {
int1_cfg._6d = (uint8_t)val & 0x01U;
int1_cfg.aoi = ((uint8_t)val & 0x02U) >> 1;
- ret = lis331dlh_write_reg(ctx, LIS331DLH_INT1_CFG, (uint8_t*)&int1_cfg, 1);
+ ret = lis331dlh_write_reg(ctx, LIS331DLH_INT1_CFG,
+ (uint8_t *)&int1_cfg, 1);
}
+
return ret;
}
@@ -1783,6 +2089,7 @@ int32_t lis331dlh_int1_6d_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of 6d in reg INT1_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_int1_6d_mode_get(stmdev_ctx_t *ctx,
@@ -1791,19 +2098,23 @@ int32_t lis331dlh_int1_6d_mode_get(stmdev_ctx_t *ctx,
lis331dlh_int1_cfg_t int1_cfg;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_CFG, (uint8_t*)&int1_cfg, 1);
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_CFG,
+ (uint8_t *)&int1_cfg, 1);
switch ((int1_cfg.aoi << 1) + int1_cfg._6d)
{
case LIS331DLH_6D_INT1_DISABLE:
*val = LIS331DLH_6D_INT1_DISABLE;
break;
+
case LIS331DLH_6D_INT1_MOVEMENT:
*val = LIS331DLH_6D_INT1_MOVEMENT;
break;
- case LIS331DLH_6D_INT1_POSITION:
+
+ case LIS331DLH_6D_INT1_POSITION:
*val = LIS331DLH_6D_INT1_POSITION;
break;
+
default:
*val = LIS331DLH_6D_INT1_DISABLE;
break;
@@ -1817,13 +2128,16 @@ int32_t lis331dlh_int1_6d_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val registers INT1_SRC
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_int1_6d_src_get(stmdev_ctx_t *ctx,
lis331dlh_int1_src_t *val)
{
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_SRC, (uint8_t*) val, 1);
+
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_SRC, (uint8_t *) val, 1);
+
return ret;
}
@@ -1832,6 +2146,7 @@ int32_t lis331dlh_int1_6d_src_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ths in reg INT1_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_int1_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1839,11 +2154,16 @@ int32_t lis331dlh_int1_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
lis331dlh_int1_ths_t int1_ths;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_THS, (uint8_t*)&int1_ths, 1);
- if(ret == 0) {
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_THS,
+ (uint8_t *)&int1_ths, 1);
+
+ if (ret == 0)
+ {
int1_ths.ths = val;
- ret = lis331dlh_write_reg(ctx, LIS331DLH_INT1_THS, (uint8_t*)&int1_ths, 1);
+ ret = lis331dlh_write_reg(ctx, LIS331DLH_INT1_THS,
+ (uint8_t *)&int1_ths, 1);
}
+
return ret;
}
@@ -1852,14 +2172,17 @@ int32_t lis331dlh_int1_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ths in reg INT1_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis331dlh_int1_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis331dlh_int1_6d_treshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis331dlh_int1_ths_t int1_ths;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_THS, (uint8_t*)&int1_ths, 1);
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_THS,
+ (uint8_t *)&int1_ths, 1);
*val = int1_ths.ths;
return ret;
@@ -1870,6 +2193,7 @@ int32_t lis331dlh_int1_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of 6d in reg INT2_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_int2_6d_mode_set(stmdev_ctx_t *ctx,
@@ -1878,13 +2202,17 @@ int32_t lis331dlh_int2_6d_mode_set(stmdev_ctx_t *ctx,
lis331dlh_int2_cfg_t int2_cfg;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_CFG, (uint8_t*)&int2_cfg, 1);
- if(ret == 0) {
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_CFG,
+ (uint8_t *)&int2_cfg, 1);
+
+ if (ret == 0)
+ {
int2_cfg._6d = (uint8_t)val & 0x01U;
int2_cfg.aoi = ((uint8_t)val & 0x02U) >> 1;
ret = lis331dlh_write_reg(ctx, LIS331DLH_INT2_CFG,
- (uint8_t*)&int2_cfg, 1);
+ (uint8_t *)&int2_cfg, 1);
}
+
return ret;
}
@@ -1893,6 +2221,7 @@ int32_t lis331dlh_int2_6d_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Get the values of 6d in reg INT2_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_int2_6d_mode_get(stmdev_ctx_t *ctx,
@@ -1901,19 +2230,23 @@ int32_t lis331dlh_int2_6d_mode_get(stmdev_ctx_t *ctx,
lis331dlh_int2_cfg_t int2_cfg;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_CFG, (uint8_t*)&int2_cfg, 1);
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_CFG,
+ (uint8_t *)&int2_cfg, 1);
switch ((int2_cfg.aoi << 1) + int2_cfg._6d)
{
case LIS331DLH_6D_INT2_DISABLE:
*val = LIS331DLH_6D_INT2_DISABLE;
break;
+
case LIS331DLH_6D_INT2_MOVEMENT:
*val = LIS331DLH_6D_INT2_MOVEMENT;
break;
- case LIS331DLH_6D_INT2_POSITION:
+
+ case LIS331DLH_6D_INT2_POSITION:
*val = LIS331DLH_6D_INT2_POSITION;
break;
+
default:
*val = LIS331DLH_6D_INT2_DISABLE;
break;
@@ -1927,13 +2260,16 @@ int32_t lis331dlh_int2_6d_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val registers INT2_SRC
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_int2_6d_src_get(stmdev_ctx_t *ctx,
lis331dlh_int2_src_t *val)
{
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_SRC, (uint8_t*) val, 1);
+
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_SRC, (uint8_t *) val, 1);
+
return ret;
}
@@ -1942,6 +2278,7 @@ int32_t lis331dlh_int2_6d_src_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ths in reg INT2_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis331dlh_int2_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1949,12 +2286,16 @@ int32_t lis331dlh_int2_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
lis331dlh_int2_ths_t int2_ths;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_THS, (uint8_t*)&int2_ths, 1);
- if(ret == 0) {
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_THS,
+ (uint8_t *)&int2_ths, 1);
+
+ if (ret == 0)
+ {
int2_ths.ths = val;
ret = lis331dlh_write_reg(ctx, LIS331DLH_INT2_THS,
- (uint8_t*)&int2_ths, 1);
+ (uint8_t *)&int2_ths, 1);
}
+
return ret;
}
@@ -1963,14 +2304,17 @@ int32_t lis331dlh_int2_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val change the values of ths in reg INT2_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis331dlh_int2_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis331dlh_int2_6d_treshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis331dlh_int2_ths_t int2_ths;
int32_t ret;
- ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_THS, (uint8_t*)&int2_ths, 1);
+ ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_THS,
+ (uint8_t *)&int2_ths, 1);
*val = int2_ths.ths;
return ret;
diff --git a/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.h b/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.h
index 8c82e8f1d3c553b169452ae34d67d729d796657f..18d4e6516fa86e689efc1e655a717dd3000b7d1a 100644
--- a/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.h
+++ b/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file lis331dlh_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lis331dlh_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lis331dlh_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lis331dlh_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LIS331DLH_REGS_H
#define LIS331DLH_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup LIS331DLH
@@ -35,6 +36,37 @@
*
*/
+/** @defgroup Endianness definitions
+ * @{
+ *
+ */
+
+#ifndef DRV_BYTE_ORDER
+#ifndef __BYTE_ORDER__
+
+#define DRV_LITTLE_ENDIAN 1234
+#define DRV_BIG_ENDIAN 4321
+
+/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
+ * by uncommenting the define which fits your platform endianness
+ */
+//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
+#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
+
+#else /* defined __BYTE_ORDER__ */
+
+#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
+#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
+#define DRV_BYTE_ORDER __BYTE_ORDER__
+
+#endif /* __BYTE_ORDER__*/
+#endif /* DRV_BYTE_ORDER */
+
+/**
+ * @}
+ *
+ */
+
/** @defgroup STMicroelectronics sensors common types
* @{
*
@@ -43,7 +75,9 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -52,6 +86,16 @@ typedef struct{
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} bitwise_t;
#define PROPERTY_DISABLE (0U)
@@ -65,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -89,15 +134,16 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
- * Unico / Unicleo tools available on STMicroelectronics
- * web site.
+ * You can create a sensor configuration by your own or using
+ * Unico / Unicleo tools available on STMicroelectronics
+ * web site.
*
* @{
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -127,30 +173,6 @@ typedef struct {
/** Device Identification (Who am I) **/
#define LIS331DLH_ID 0x32U
-/**
- * @}
- *
- */
-
-/**
- * @addtogroup LIS331DLH_Sensitivity
- * @brief These macro are maintained for back compatibility.
- * in order to convert data into engineering units please
- * use functions:
- * -> _from_fs2_to_mg(int16_t lsb);
- * -> _from_fs4_to_mg(int16_t lsb);
- * -> _from_fs8_to_mg(int16_t lsb);
- *
- * REMOVING the MACRO you are compliant with:
- * MISRA-C 2012 [Dir 4.9] -> " avoid function-like macros "
- * @{
- *
- */
-
-#define LIS331DLH_FROM_FS_2g_TO_mg(lsb) (float)( (lsb >> 4 ) * 1.0f )
-#define LIS331DLH_FROM_FS_4g_TO_mg(lsb) (float)( (lsb >> 4 ) * 2.0f )
-#define LIS331DLH_FROM_FS_8g_TO_mg(lsb) (float)( (lsb >> 4 ) * 3.9f )
-
/**
* @}
*
@@ -158,52 +180,97 @@ typedef struct {
#define LIS331DLH_WHO_AM_I 0x0FU
#define LIS331DLH_CTRL_REG1 0x20U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xen : 1;
uint8_t yen : 1;
uint8_t zen : 1;
uint8_t dr : 2;
uint8_t pm : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t pm : 3;
+ uint8_t dr : 2;
+ uint8_t zen : 1;
+ uint8_t yen : 1;
+ uint8_t xen : 1;
+#endif /* DRV_BYTE_ORDER */
} lis331dlh_ctrl_reg1_t;
#define LIS331DLH_CTRL_REG2 0x21U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t hpcf : 2;
uint8_t hpen : 2;
uint8_t fds : 1;
uint8_t hpm : 2;
uint8_t boot : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t boot : 1;
+ uint8_t hpm : 2;
+ uint8_t fds : 1;
+ uint8_t hpen : 2;
+ uint8_t hpcf : 2;
+#endif /* DRV_BYTE_ORDER */
} lis331dlh_ctrl_reg2_t;
#define LIS331DLH_CTRL_REG3 0x22U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t i1_cfg : 2;
uint8_t lir1 : 1;
uint8_t i2_cfg : 2;
uint8_t lir2 : 1;
uint8_t pp_od : 1;
uint8_t ihl : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t ihl : 1;
+ uint8_t pp_od : 1;
+ uint8_t lir2 : 1;
+ uint8_t i2_cfg : 2;
+ uint8_t lir1 : 1;
+ uint8_t i1_cfg : 2;
+#endif /* DRV_BYTE_ORDER */
} lis331dlh_ctrl_reg3_t;
#define LIS331DLH_CTRL_REG4 0x23U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t st : 3; /* STsign + ST */
uint8_t fs : 2;
uint8_t ble : 1;
uint8_t bdu : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bdu : 1;
+ uint8_t ble : 1;
+ uint8_t fs : 2;
+ uint8_t st : 3; /* STsign + ST */
+ uint8_t sim : 1;
+#endif /* DRV_BYTE_ORDER */
} lis331dlh_ctrl_reg4_t;
#define LIS331DLH_CTRL_REG5 0x24U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t turnon : 2;
uint8_t not_used_01 : 6;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 6;
+ uint8_t turnon : 2;
+#endif /* DRV_BYTE_ORDER */
} lis331dlh_ctrl_reg5_t;
#define LIS331DLH_HP_FILTER_RESET 0x25U
#define LIS331DLH_REFERENCE 0x26U
#define LIS331DLH_STATUS_REG 0x27U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xda : 1;
uint8_t yda : 1;
uint8_t zda : 1;
@@ -212,6 +279,16 @@ typedef struct {
uint8_t yor : 1;
uint8_t zor : 1;
uint8_t zyxor : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t zyxor : 1;
+ uint8_t zor : 1;
+ uint8_t yor : 1;
+ uint8_t _xor : 1;
+ uint8_t zyxda : 1;
+ uint8_t zda : 1;
+ uint8_t yda : 1;
+ uint8_t xda : 1;
+#endif /* DRV_BYTE_ORDER */
} lis331dlh_status_reg_t;
#define LIS331DLH_OUT_X_L 0x28U
@@ -221,7 +298,9 @@ typedef struct {
#define LIS331DLH_OUT_Z_L 0x2CU
#define LIS331DLH_OUT_Z_H 0x2DU
#define LIS331DLH_INT1_CFG 0x30U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlie : 1;
uint8_t xhie : 1;
uint8_t ylie : 1;
@@ -230,10 +309,22 @@ typedef struct {
uint8_t zhie : 1;
uint8_t _6d : 1;
uint8_t aoi : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t aoi : 1;
+ uint8_t _6d : 1;
+ uint8_t zhie : 1;
+ uint8_t zlie : 1;
+ uint8_t yhie : 1;
+ uint8_t ylie : 1;
+ uint8_t xhie : 1;
+ uint8_t xlie : 1;
+#endif /* DRV_BYTE_ORDER */
} lis331dlh_int1_cfg_t;
#define LIS331DLH_INT1_SRC 0x31U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
uint8_t yl : 1;
@@ -242,22 +333,47 @@ typedef struct {
uint8_t zh : 1;
uint8_t ia : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t ia : 1;
+ uint8_t zh : 1;
+ uint8_t zl : 1;
+ uint8_t yh : 1;
+ uint8_t yl : 1;
+ uint8_t xh : 1;
+ uint8_t xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lis331dlh_int1_src_t;
#define LIS331DLH_INT1_THS 0x32U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t ths : 7;
+#endif /* DRV_BYTE_ORDER */
} lis331dlh_int1_ths_t;
#define LIS331DLH_INT1_DURATION 0x33U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d : 7;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t d : 7;
+#endif /* DRV_BYTE_ORDER */
+
} lis331dlh_int1_duration_t;
#define LIS331DLH_INT2_CFG 0x34U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlie : 1;
uint8_t xhie : 1;
uint8_t ylie : 1;
@@ -266,10 +382,23 @@ typedef struct {
uint8_t zhie : 1;
uint8_t _6d : 1;
uint8_t aoi : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t aoi : 1;
+ uint8_t _6d : 1;
+ uint8_t zhie : 1;
+ uint8_t zlie : 1;
+ uint8_t yhie : 1;
+ uint8_t ylie : 1;
+ uint8_t xhie : 1;
+ uint8_t xlie : 1;
+#endif /* DRV_BYTE_ORDER */
+
} lis331dlh_int2_cfg_t;
#define LIS331DLH_INT2_SRC 0x35U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
uint8_t yl : 1;
@@ -278,25 +407,48 @@ typedef struct {
uint8_t zh : 1;
uint8_t ia : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t ia : 1;
+ uint8_t zh : 1;
+ uint8_t zl : 1;
+ uint8_t yh : 1;
+ uint8_t yl : 1;
+ uint8_t xh : 1;
+ uint8_t xl : 1;
+#endif /* DRV_BYTE_ORDER */
+
} lis331dlh_int2_src_t;
#define LIS331DLH_INT2_THS 0x36U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t ths : 7;
+#endif /* DRV_BYTE_ORDER */
} lis331dlh_int2_ths_t;
#define LIS331DLH_INT2_DURATION 0x37U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d : 7;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t d : 7;
+#endif /* DRV_BYTE_ORDER */
} lis331dlh_int2_duration_t;
/**
* @defgroup LIS331DLH_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -304,7 +456,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
lis331dlh_ctrl_reg1_t ctrl_reg1;
lis331dlh_ctrl_reg2_t ctrl_reg2;
lis331dlh_ctrl_reg3_t ctrl_reg3;
@@ -328,14 +481,16 @@ typedef union{
*
*/
-int32_t lis331dlh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lis331dlh_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t lis331dlh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lis331dlh_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-extern float lis331dlh_from_fs2_to_mg(int16_t lsb);
-extern float lis331dlh_from_fs4_to_mg(int16_t lsb);
-extern float lis331dlh_from_fs8_to_mg(int16_t lsb);
+float_t lis331dlh_from_fs2_to_mg(int16_t lsb);
+float_t lis331dlh_from_fs4_to_mg(int16_t lsb);
+float_t lis331dlh_from_fs8_to_mg(int16_t lsb);
int32_t lis331dlh_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis331dlh_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -346,7 +501,8 @@ int32_t lis331dlh_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis331dlh_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis331dlh_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS331DLH_ODR_OFF = 0x00,
LIS331DLH_ODR_Hz5 = 0x02,
LIS331DLH_ODR_1Hz = 0x03,
@@ -358,10 +514,13 @@ typedef enum {
LIS331DLH_ODR_400Hz = 0x21,
LIS331DLH_ODR_1kHz = 0x31,
} lis331dlh_dr_t;
-int32_t lis331dlh_data_rate_set(stmdev_ctx_t *ctx, lis331dlh_dr_t val);
-int32_t lis331dlh_data_rate_get(stmdev_ctx_t *ctx, lis331dlh_dr_t *val);
+int32_t lis331dlh_data_rate_set(stmdev_ctx_t *ctx,
+ lis331dlh_dr_t val);
+int32_t lis331dlh_data_rate_get(stmdev_ctx_t *ctx,
+ lis331dlh_dr_t *val);
-typedef enum {
+typedef enum
+{
LIS331DLH_NORMAL_MODE = 0,
LIS331DLH_REF_MODE_ENABLE = 1,
} lis331dlh_hpm_t;
@@ -370,16 +529,21 @@ int32_t lis331dlh_reference_mode_set(stmdev_ctx_t *ctx,
int32_t lis331dlh_reference_mode_get(stmdev_ctx_t *ctx,
lis331dlh_hpm_t *val);
-typedef enum {
+typedef enum
+{
LIS331DLH_2g = 0,
LIS331DLH_4g = 1,
LIS331DLH_8g = 3,
} lis331dlh_fs_t;
-int32_t lis331dlh_full_scale_set(stmdev_ctx_t *ctx, lis331dlh_fs_t val);
-int32_t lis331dlh_full_scale_get(stmdev_ctx_t *ctx, lis331dlh_fs_t *val);
+int32_t lis331dlh_full_scale_set(stmdev_ctx_t *ctx,
+ lis331dlh_fs_t val);
+int32_t lis331dlh_full_scale_get(stmdev_ctx_t *ctx,
+ lis331dlh_fs_t *val);
-int32_t lis331dlh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis331dlh_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis331dlh_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis331dlh_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lis331dlh_status_reg_get(stmdev_ctx_t *ctx,
lis331dlh_status_reg_t *val);
@@ -387,29 +551,37 @@ int32_t lis331dlh_status_reg_get(stmdev_ctx_t *ctx,
int32_t lis331dlh_flag_data_ready_get(stmdev_ctx_t *ctx,
uint8_t *val);
-int32_t lis331dlh_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lis331dlh_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
int32_t lis331dlh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t lis331dlh_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis331dlh_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS331DLH_ST_DISABLE = 0,
LIS331DLH_ST_POSITIVE = 1,
LIS331DLH_ST_NEGATIVE = 5,
} lis331dlh_st_t;
-int32_t lis331dlh_self_test_set(stmdev_ctx_t *ctx, lis331dlh_st_t val);
-int32_t lis331dlh_self_test_get(stmdev_ctx_t *ctx, lis331dlh_st_t *val);
+int32_t lis331dlh_self_test_set(stmdev_ctx_t *ctx,
+ lis331dlh_st_t val);
+int32_t lis331dlh_self_test_get(stmdev_ctx_t *ctx,
+ lis331dlh_st_t *val);
-typedef enum {
+typedef enum
+{
LIS331DLH_LSB_AT_LOW_ADD = 0,
LIS331DLH_MSB_AT_LOW_ADD = 1,
} lis331dlh_ble_t;
-int32_t lis331dlh_data_format_set(stmdev_ctx_t *ctx, lis331dlh_ble_t val);
-int32_t lis331dlh_data_format_get(stmdev_ctx_t *ctx, lis331dlh_ble_t *val);
+int32_t lis331dlh_data_format_set(stmdev_ctx_t *ctx,
+ lis331dlh_ble_t val);
+int32_t lis331dlh_data_format_get(stmdev_ctx_t *ctx,
+ lis331dlh_ble_t *val);
-typedef enum {
+typedef enum
+{
LIS331DLH_CUT_OFF_8Hz = 0,
LIS331DLH_CUT_OFF_16Hz = 1,
LIS331DLH_CUT_OFF_32Hz = 2,
@@ -420,7 +592,8 @@ int32_t lis331dlh_hp_bandwidth_set(stmdev_ctx_t *ctx,
int32_t lis331dlh_hp_bandwidth_get(stmdev_ctx_t *ctx,
lis331dlh_hpcf_t *val);
-typedef enum {
+typedef enum
+{
LIS331DLH_HP_DISABLE = 0,
LIS331DLH_HP_ON_OUT = 4,
LIS331DLH_HP_ON_INT1 = 1,
@@ -430,22 +603,30 @@ typedef enum {
LIS331DLH_HP_ON_INT2_OUT = 6,
LIS331DLH_HP_ON_INT1_OUT = 5,
} lis331dlh_hpen_t;
-int32_t lis331dlh_hp_path_set(stmdev_ctx_t *ctx, lis331dlh_hpen_t val);
-int32_t lis331dlh_hp_path_get(stmdev_ctx_t *ctx, lis331dlh_hpen_t *val);
+int32_t lis331dlh_hp_path_set(stmdev_ctx_t *ctx,
+ lis331dlh_hpen_t val);
+int32_t lis331dlh_hp_path_get(stmdev_ctx_t *ctx,
+ lis331dlh_hpen_t *val);
int32_t lis331dlh_hp_reset_get(stmdev_ctx_t *ctx);
-int32_t lis331dlh_hp_reference_value_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis331dlh_hp_reference_value_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis331dlh_hp_reference_value_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis331dlh_hp_reference_value_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS331DLH_SPI_4_WIRE = 0,
LIS331DLH_SPI_3_WIRE = 1,
} lis331dlh_sim_t;
-int32_t lis331dlh_spi_mode_set(stmdev_ctx_t *ctx, lis331dlh_sim_t val);
-int32_t lis331dlh_spi_mode_get(stmdev_ctx_t *ctx, lis331dlh_sim_t *val);
+int32_t lis331dlh_spi_mode_set(stmdev_ctx_t *ctx,
+ lis331dlh_sim_t val);
+int32_t lis331dlh_spi_mode_get(stmdev_ctx_t *ctx,
+ lis331dlh_sim_t *val);
-typedef enum {
+typedef enum
+{
LIS331DLH_PAD1_INT1_SRC = 0,
LIS331DLH_PAD1_INT1_OR_INT2_SRC = 1,
LIS331DLH_PAD1_DRDY = 2,
@@ -456,7 +637,8 @@ int32_t lis331dlh_pin_int1_route_set(stmdev_ctx_t *ctx,
int32_t lis331dlh_pin_int1_route_get(stmdev_ctx_t *ctx,
lis331dlh_i1_cfg_t *val);
-typedef enum {
+typedef enum
+{
LIS331DLH_INT1_PULSED = 0,
LIS331DLH_INT1_LATCHED = 1,
} lis331dlh_lir1_t;
@@ -465,7 +647,8 @@ int32_t lis331dlh_int1_notification_set(stmdev_ctx_t *ctx,
int32_t lis331dlh_int1_notification_get(stmdev_ctx_t *ctx,
lis331dlh_lir1_t *val);
-typedef enum {
+typedef enum
+{
LIS331DLH_PAD2_INT2_SRC = 0,
LIS331DLH_PAD2_INT1_OR_INT2_SRC = 1,
LIS331DLH_PAD2_DRDY = 2,
@@ -476,7 +659,8 @@ int32_t lis331dlh_pin_int2_route_set(stmdev_ctx_t *ctx,
int32_t lis331dlh_pin_int2_route_get(stmdev_ctx_t *ctx,
lis331dlh_i2_cfg_t *val);
-typedef enum {
+typedef enum
+{
LIS331DLH_INT2_PULSED = 0,
LIS331DLH_INT2_LATCHED = 1,
} lis331dlh_lir2_t;
@@ -485,14 +669,18 @@ int32_t lis331dlh_int2_notification_set(stmdev_ctx_t *ctx,
int32_t lis331dlh_int2_notification_get(stmdev_ctx_t *ctx,
lis331dlh_lir2_t *val);
-typedef enum {
+typedef enum
+{
LIS331DLH_PUSH_PULL = 0,
LIS331DLH_OPEN_DRAIN = 1,
} lis331dlh_pp_od_t;
-int32_t lis331dlh_pin_mode_set(stmdev_ctx_t *ctx, lis331dlh_pp_od_t val);
-int32_t lis331dlh_pin_mode_get(stmdev_ctx_t *ctx, lis331dlh_pp_od_t *val);
+int32_t lis331dlh_pin_mode_set(stmdev_ctx_t *ctx,
+ lis331dlh_pp_od_t val);
+int32_t lis331dlh_pin_mode_get(stmdev_ctx_t *ctx,
+ lis331dlh_pp_od_t *val);
-typedef enum {
+typedef enum
+{
LIS331DLH_ACTIVE_HIGH = 0,
LIS331DLH_ACTIVE_LOW = 1,
} lis331dlh_ihl_t;
@@ -501,7 +689,8 @@ int32_t lis331dlh_pin_polarity_set(stmdev_ctx_t *ctx,
int32_t lis331dlh_pin_polarity_get(stmdev_ctx_t *ctx,
lis331dlh_ihl_t *val);
-typedef struct {
+typedef struct
+{
uint8_t int1_xlie : 1;
uint8_t int1_xhie : 1;
uint8_t int1_ylie : 1;
@@ -514,7 +703,8 @@ int32_t lis331dlh_int1_on_threshold_conf_set(stmdev_ctx_t *ctx,
int32_t lis331dlh_int1_on_threshold_conf_get(stmdev_ctx_t *ctx,
int1_on_th_conf_t *val);
-typedef enum {
+typedef enum
+{
LIS331DLH_INT1_ON_THRESHOLD_OR = 0,
LIS331DLH_INT1_ON_THRESHOLD_AND = 1,
} lis331dlh_int1_aoi_t;
@@ -532,7 +722,8 @@ int32_t lis331dlh_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis331dlh_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis331dlh_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef struct {
+typedef struct
+{
uint8_t int2_xlie : 1;
uint8_t int2_xhie : 1;
uint8_t int2_ylie : 1;
@@ -545,7 +736,8 @@ int32_t lis331dlh_int2_on_threshold_conf_set(stmdev_ctx_t *ctx,
int32_t lis331dlh_int2_on_threshold_conf_get(stmdev_ctx_t *ctx,
int2_on_th_conf_t *val);
-typedef enum {
+typedef enum
+{
LIS331DLH_INT2_ON_THRESHOLD_OR = 0,
LIS331DLH_INT2_ON_THRESHOLD_AND = 1,
} lis331dlh_int2_aoi_t;
@@ -566,7 +758,8 @@ int32_t lis331dlh_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis331dlh_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis331dlh_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS331DLH_6D_INT1_DISABLE = 0,
LIS331DLH_6D_INT1_MOVEMENT = 1,
LIS331DLH_6D_INT1_POSITION = 3,
@@ -579,10 +772,13 @@ int32_t lis331dlh_int1_6d_mode_get(stmdev_ctx_t *ctx,
int32_t lis331dlh_int1_6d_src_get(stmdev_ctx_t *ctx,
lis331dlh_int1_src_t *val);
-int32_t lis331dlh_int1_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis331dlh_int1_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis331dlh_int1_6d_treshold_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis331dlh_int1_6d_treshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS331DLH_6D_INT2_DISABLE = 0,
LIS331DLH_6D_INT2_MOVEMENT = 1,
LIS331DLH_6D_INT2_POSITION = 3,
@@ -595,8 +791,10 @@ int32_t lis331dlh_int2_6d_mode_get(stmdev_ctx_t *ctx,
int32_t lis331dlh_int2_6d_src_get(stmdev_ctx_t *ctx,
lis331dlh_int2_src_t *val);
-int32_t lis331dlh_int2_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis331dlh_int2_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis331dlh_int2_6d_treshold_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis331dlh_int2_6d_treshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
/**
*@}
diff --git a/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.c b/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.c
index 39a8174c69e0485429537d776fc4809331107ce5..8a64723cf747499ece1784482913339a1a50b979 100644
--- a/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.c
+++ b/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file lis3de_reg.c
- * @author Sensors Software Solution Team
- * @brief LIS3DE driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lis3de_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LIS3DE driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lis3de_reg.h"
@@ -46,11 +46,13 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3de_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t lis3de_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +66,14 @@ int32_t lis3de_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3de_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t lis3de_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -77,36 +82,36 @@ int32_t lis3de_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
*
*/
- /**
+/**
* @defgroup LIS3DE_Sensitivity
* @brief These functions convert raw-data into engineering units.
* @{
*
*/
-float lis3de_from_fs2_to_mg(int16_t lsb)
+float_t lis3de_from_fs2_to_mg(int16_t lsb)
{
- return ( (float)lsb ) * 15.6f;
+ return ((float_t)lsb) * 15.6f;
}
-float lis3de_from_fs4_to_mg(int16_t lsb)
+float_t lis3de_from_fs4_to_mg(int16_t lsb)
{
- return ( (float)lsb ) * 31.2f;
+ return ((float_t)lsb) * 31.2f;
}
-float lis3de_from_fs8_to_mg(int16_t lsb)
+float_t lis3de_from_fs8_to_mg(int16_t lsb)
{
- return ( (float)lsb ) * 62.5f;
+ return ((float_t)lsb) * 62.5f;
}
-float lis3de_from_fs16_to_mg(int16_t lsb)
+float_t lis3de_from_fs16_to_mg(int16_t lsb)
{
- return ( (float)lsb ) * 187.5f;
+ return ((float_t)lsb) * 187.5f;
}
-float lis3de_from_lsb_to_celsius(int16_t lsb)
+float_t lis3de_from_lsb_to_celsius(int16_t lsb)
{
- return ( ( (float)lsb ) * 1.0f ) + 25.0f;
+ return (((float_t)lsb) * 1.0f) + 25.0f;
}
/**
@@ -132,7 +137,9 @@ float lis3de_from_lsb_to_celsius(int16_t lsb)
int32_t lis3de_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis3de_read_reg(ctx, LIS3DE_STATUS_REG_AUX, buff, 1);
+
return ret;
}
/**
@@ -149,7 +156,7 @@ int32_t lis3de_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lis3de_read_reg(ctx, LIS3DE_STATUS_REG_AUX,
- (uint8_t*)&status_reg_aux, 1);
+ (uint8_t *)&status_reg_aux, 1);
*val = status_reg_aux._3da;
return ret;
@@ -168,7 +175,7 @@ int32_t lis3de_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lis3de_read_reg(ctx, LIS3DE_STATUS_REG_AUX,
- (uint8_t*)&status_reg_aux, 1);
+ (uint8_t *)&status_reg_aux, 1);
*val = status_reg_aux._3or;
return ret;
@@ -184,7 +191,9 @@ int32_t lis3de_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t lis3de_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis3de_read_reg(ctx, LIS3DE_OUT_ADC1_H, buff, 1);
+
return ret;
}
@@ -208,10 +217,19 @@ int32_t lis3de_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3de_adc_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lis3de_adc_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lis3de_read_reg(ctx, LIS3DE_OUT_ADC1_L, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -228,19 +246,26 @@ int32_t lis3de_aux_adc_set(stmdev_ctx_t *ctx, lis3de_temp_en_t val)
lis3de_temp_cfg_reg_t temp_cfg_reg;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_TEMP_CFG_REG, (uint8_t*)&temp_cfg_reg, 1);
- if (ret == 0) {
- if (val != LIS3DE_AUX_DISABLE){
+ ret = lis3de_read_reg(ctx, LIS3DE_TEMP_CFG_REG,
+ (uint8_t *)&temp_cfg_reg, 1);
+
+ if (ret == 0)
+ {
+ if (val != LIS3DE_AUX_DISABLE)
+ {
/* Required in order to use auxiliary adc */
ret = lis3de_block_data_update_set(ctx, PROPERTY_ENABLE);
}
- }
- if (ret == 0) {
- temp_cfg_reg.temp_en = ( (uint8_t) val & 0x02U) >> 1;
+ }
+
+ if (ret == 0)
+ {
+ temp_cfg_reg.temp_en = ((uint8_t) val & 0x02U) >> 1;
temp_cfg_reg.adc_pd = (uint8_t) val & 0x01U;
ret = lis3de_write_reg(ctx, LIS3DE_TEMP_CFG_REG,
- (uint8_t*)&temp_cfg_reg, 1);
+ (uint8_t *)&temp_cfg_reg, 1);
}
+
return ret;
}
@@ -257,16 +282,26 @@ int32_t lis3de_aux_adc_get(stmdev_ctx_t *ctx, lis3de_temp_en_t *val)
lis3de_temp_cfg_reg_t temp_cfg_reg;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_TEMP_CFG_REG, (uint8_t*)&temp_cfg_reg, 1);
- if ( ( temp_cfg_reg.temp_en & temp_cfg_reg.adc_pd ) == PROPERTY_ENABLE ){
+ ret = lis3de_read_reg(ctx, LIS3DE_TEMP_CFG_REG,
+ (uint8_t *)&temp_cfg_reg, 1);
+
+ if ((temp_cfg_reg.temp_en & temp_cfg_reg.adc_pd) ==
+ PROPERTY_ENABLE)
+ {
*val = LIS3DE_AUX_ON_TEMPERATURE;
- }
- if ( ( temp_cfg_reg.temp_en == PROPERTY_DISABLE ) &&
- ( temp_cfg_reg.adc_pd == PROPERTY_ENABLE ) ) {
+ }
+
+ if ((temp_cfg_reg.temp_en == PROPERTY_DISABLE) &&
+ (temp_cfg_reg.adc_pd == PROPERTY_ENABLE))
+ {
*val = LIS3DE_AUX_ON_PADS;
- } else {
+ }
+
+ else
+ {
*val = LIS3DE_AUX_DISABLE;
}
+
return ret;
}
@@ -278,16 +313,20 @@ int32_t lis3de_aux_adc_get(stmdev_ctx_t *ctx, lis3de_temp_en_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3de_operating_mode_set(stmdev_ctx_t *ctx, lis3de_op_md_t val)
+int32_t lis3de_operating_mode_set(stmdev_ctx_t *ctx,
+ lis3de_op_md_t val)
{
lis3de_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if (ret == 0) {
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.lpen = (uint8_t) val;
- ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -299,21 +338,27 @@ int32_t lis3de_operating_mode_set(stmdev_ctx_t *ctx, lis3de_op_md_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3de_operating_mode_get(stmdev_ctx_t *ctx, lis3de_op_md_t *val)
+int32_t lis3de_operating_mode_get(stmdev_ctx_t *ctx,
+ lis3de_op_md_t *val)
{
lis3de_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if (ret == 0) {
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
- if ( ctrl_reg1.lpen == PROPERTY_ENABLE ) {
+ if (ret == 0)
+ {
+ if (ctrl_reg1.lpen == PROPERTY_ENABLE)
+ {
*val = LIS3DE_LP;
}
- else {
+
+ else
+ {
*val = LIS3DE_NM;
}
}
+
return ret;
}
@@ -330,11 +375,14 @@ int32_t lis3de_data_rate_set(stmdev_ctx_t *ctx, lis3de_odr_t val)
lis3de_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if (ret == 0) {
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.odr = (uint8_t)val;
- ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -351,42 +399,55 @@ int32_t lis3de_data_rate_get(stmdev_ctx_t *ctx, lis3de_odr_t *val)
lis3de_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- switch (ctrl_reg1.odr) {
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ switch (ctrl_reg1.odr)
+ {
case LIS3DE_POWER_DOWN:
*val = LIS3DE_POWER_DOWN;
break;
+
case LIS3DE_ODR_1Hz:
*val = LIS3DE_ODR_1Hz;
break;
+
case LIS3DE_ODR_10Hz:
*val = LIS3DE_ODR_10Hz;
break;
+
case LIS3DE_ODR_25Hz:
*val = LIS3DE_ODR_25Hz;
break;
+
case LIS3DE_ODR_50Hz:
*val = LIS3DE_ODR_50Hz;
break;
+
case LIS3DE_ODR_100Hz:
*val = LIS3DE_ODR_100Hz;
break;
+
case LIS3DE_ODR_200Hz:
*val = LIS3DE_ODR_200Hz;
break;
+
case LIS3DE_ODR_400Hz:
*val = LIS3DE_ODR_400Hz;
break;
+
case LIS3DE_ODR_1kHz6:
*val = LIS3DE_ODR_1kHz6;
break;
+
case LIS3DE_ODR_5kHz376_LP_1kHz344_NM:
*val = LIS3DE_ODR_5kHz376_LP_1kHz344_NM;
break;
+
default:
*val = LIS3DE_POWER_DOWN;
break;
}
+
return ret;
}
@@ -399,16 +460,20 @@ int32_t lis3de_data_rate_get(stmdev_ctx_t *ctx, lis3de_odr_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3de_high_pass_on_outputs_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lis3de_high_pass_on_outputs_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lis3de_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if (ret == 0) {
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.fds = val;
- ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -421,12 +486,13 @@ int32_t lis3de_high_pass_on_outputs_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3de_high_pass_on_outputs_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis3de_high_pass_on_outputs_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis3de_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
*val = (uint8_t)ctrl_reg2.fds;
return ret;
@@ -447,16 +513,19 @@ int32_t lis3de_high_pass_on_outputs_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lis3de_high_pass_bandwidth_set(stmdev_ctx_t *ctx,
- lis3de_hpcf_t val)
+ lis3de_hpcf_t val)
{
lis3de_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if (ret == 0) {
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpcf = (uint8_t)val;
- ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -475,29 +544,36 @@ int32_t lis3de_high_pass_bandwidth_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis3de_high_pass_bandwidth_get(stmdev_ctx_t *ctx,
- lis3de_hpcf_t *val)
+ lis3de_hpcf_t *val)
{
lis3de_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- switch (ctrl_reg2.hpcf) {
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ switch (ctrl_reg2.hpcf)
+ {
case LIS3DE_AGGRESSIVE:
*val = LIS3DE_AGGRESSIVE;
break;
+
case LIS3DE_STRONG:
*val = LIS3DE_STRONG;
break;
+
case LIS3DE_MEDIUM:
*val = LIS3DE_MEDIUM;
break;
+
case LIS3DE_LIGHT:
*val = LIS3DE_LIGHT;
break;
+
default:
*val = LIS3DE_LIGHT;
break;
}
+
return ret;
}
@@ -514,11 +590,14 @@ int32_t lis3de_high_pass_mode_set(stmdev_ctx_t *ctx, lis3de_hpm_t val)
lis3de_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if (ret == 0) {
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpm = (uint8_t)val;
- ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -530,29 +609,37 @@ int32_t lis3de_high_pass_mode_set(stmdev_ctx_t *ctx, lis3de_hpm_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3de_high_pass_mode_get(stmdev_ctx_t *ctx, lis3de_hpm_t *val)
+int32_t lis3de_high_pass_mode_get(stmdev_ctx_t *ctx,
+ lis3de_hpm_t *val)
{
lis3de_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- switch (ctrl_reg2.hpm) {
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ switch (ctrl_reg2.hpm)
+ {
case LIS3DE_NORMAL_WITH_RST:
*val = LIS3DE_NORMAL_WITH_RST;
break;
+
case LIS3DE_REFERENCE_MODE:
*val = LIS3DE_REFERENCE_MODE;
break;
+
case LIS3DE_NORMAL:
*val = LIS3DE_NORMAL;
break;
+
case LIS3DE_AUTORST_ON_INT:
*val = LIS3DE_AUTORST_ON_INT;
break;
+
default:
*val = LIS3DE_NORMAL_WITH_RST;
break;
}
+
return ret;
}
@@ -569,11 +656,14 @@ int32_t lis3de_full_scale_set(stmdev_ctx_t *ctx, lis3de_fs_t val)
lis3de_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if (ret == 0) {
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.fs = (uint8_t)val;
- ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -590,24 +680,31 @@ int32_t lis3de_full_scale_get(stmdev_ctx_t *ctx, lis3de_fs_t *val)
lis3de_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- switch (ctrl_reg4.fs) {
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ switch (ctrl_reg4.fs)
+ {
case LIS3DE_2g:
*val = LIS3DE_2g;
break;
+
case LIS3DE_4g:
*val = LIS3DE_4g;
break;
+
case LIS3DE_8g:
*val = LIS3DE_8g;
break;
+
case LIS3DE_16g:
*val = LIS3DE_16g;
break;
+
default:
*val = LIS3DE_2g;
break;
}
+
return ret;
}
@@ -624,11 +721,14 @@ int32_t lis3de_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
lis3de_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if (ret == 0) {
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.bdu = val;
- ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -645,7 +745,7 @@ int32_t lis3de_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3de_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
*val = (uint8_t)ctrl_reg4.bdu;
return ret;
@@ -663,7 +763,9 @@ int32_t lis3de_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t lis3de_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis3de_write_reg(ctx, LIS3DE_REFERENCE, buff, 1);
+
return ret;
}
@@ -679,7 +781,9 @@ int32_t lis3de_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lis3de_filter_reference_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis3de_read_reg(ctx, LIS3DE_REFERENCE, buff, 1);
+
return ret;
}
/**
@@ -695,7 +799,7 @@ int32_t lis3de_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3de_status_reg_t status_reg;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_STATUS_REG, (uint8_t*)&status_reg, 1);
+ ret = lis3de_read_reg(ctx, LIS3DE_STATUS_REG, (uint8_t *)&status_reg, 1);
*val = status_reg.zyxda;
return ret;
@@ -713,7 +817,7 @@ int32_t lis3de_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3de_status_reg_t status_reg;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_STATUS_REG, (uint8_t*)&status_reg, 1);
+ ret = lis3de_read_reg(ctx, LIS3DE_STATUS_REG, (uint8_t *)&status_reg, 1);
*val = status_reg.zyxor;
return ret;
@@ -729,17 +833,23 @@ int32_t lis3de_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t lis3de_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *buff)
{
int32_t ret;
+
int8_t dummy;
- ret = lis3de_read_reg(ctx, LIS3DE_OUT_X, (uint8_t*)&dummy , 1);
+ ret = lis3de_read_reg(ctx, LIS3DE_OUT_X, (uint8_t *)&dummy, 1);
buff[0] = dummy;
- if (ret == 0) {
- ret = lis3de_read_reg(ctx, LIS3DE_OUT_Y, (uint8_t*)&dummy, 1);
+
+ if (ret == 0)
+ {
+ ret = lis3de_read_reg(ctx, LIS3DE_OUT_Y, (uint8_t *)&dummy, 1);
buff[1] = dummy;
- }
- if (ret == 0) {
- ret = lis3de_read_reg(ctx, LIS3DE_OUT_Z, (uint8_t*)&dummy, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lis3de_read_reg(ctx, LIS3DE_OUT_Z, (uint8_t *)&dummy, 1);
buff[2] = dummy;
}
+
return ret;
}
@@ -750,7 +860,7 @@ int32_t lis3de_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *buff)
/**
* @defgroup LIS3DE_Common
- * @brief This section group common usefull functions
+ * @brief This section group common useful functions
* @{
*
*/
@@ -766,7 +876,9 @@ int32_t lis3de_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *buff)
int32_t lis3de_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis3de_read_reg(ctx, LIS3DE_WHO_AM_I, buff, 1);
+
return ret;
}
/**
@@ -782,11 +894,14 @@ int32_t lis3de_self_test_set(stmdev_ctx_t *ctx, lis3de_st_t val)
lis3de_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if (ret == 0) {
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.st = (uint8_t)val;
- ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -803,21 +918,27 @@ int32_t lis3de_self_test_get(stmdev_ctx_t *ctx, lis3de_st_t *val)
lis3de_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- switch (ctrl_reg4.st) {
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ switch (ctrl_reg4.st)
+ {
case LIS3DE_ST_DISABLE:
*val = LIS3DE_ST_DISABLE;
break;
+
case LIS3DE_ST_POSITIVE:
*val = LIS3DE_ST_POSITIVE;
break;
+
case LIS3DE_ST_NEGATIVE:
*val = LIS3DE_ST_NEGATIVE;
break;
+
default:
*val = LIS3DE_ST_DISABLE;
break;
}
+
return ret;
}
@@ -834,11 +955,14 @@ int32_t lis3de_boot_set(stmdev_ctx_t *ctx, uint8_t val)
lis3de_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.boot = val;
- ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -855,7 +979,7 @@ int32_t lis3de_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3de_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
*val = (uint8_t)ctrl_reg5.boot;
return ret;
@@ -872,7 +996,9 @@ int32_t lis3de_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t lis3de_status_get(stmdev_ctx_t *ctx, lis3de_status_reg_t *val)
{
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_STATUS_REG, (uint8_t*) val, 1);
+
+ ret = lis3de_read_reg(ctx, LIS3DE_STATUS_REG, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -897,10 +1023,12 @@ int32_t lis3de_status_get(stmdev_ctx_t *ctx, lis3de_status_reg_t *val)
*
*/
int32_t lis3de_int1_gen_conf_set(stmdev_ctx_t *ctx,
- lis3de_ig1_cfg_t *val)
+ lis3de_ig1_cfg_t *val)
{
int32_t ret;
- ret = lis3de_write_reg(ctx, LIS3DE_IG1_CFG, (uint8_t*) val, 1);
+
+ ret = lis3de_write_reg(ctx, LIS3DE_IG1_CFG, (uint8_t *) val, 1);
+
return ret;
}
@@ -913,10 +1041,12 @@ int32_t lis3de_int1_gen_conf_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis3de_int1_gen_conf_get(stmdev_ctx_t *ctx,
- lis3de_ig1_cfg_t *val)
+ lis3de_ig1_cfg_t *val)
{
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_IG1_CFG, (uint8_t*) val, 1);
+
+ ret = lis3de_read_reg(ctx, LIS3DE_IG1_CFG, (uint8_t *) val, 1);
+
return ret;
}
@@ -929,10 +1059,12 @@ int32_t lis3de_int1_gen_conf_get(stmdev_ctx_t *ctx,
*
*/
int32_t lis3de_int1_gen_source_get(stmdev_ctx_t *ctx,
- lis3de_ig1_source_t *val)
+ lis3de_ig1_source_t *val)
{
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_IG1_SOURCE, (uint8_t*) val, 1);
+
+ ret = lis3de_read_reg(ctx, LIS3DE_IG1_SOURCE, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -950,11 +1082,14 @@ int32_t lis3de_int1_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
lis3de_ig1_ths_t int1_ths;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_IG1_THS, (uint8_t*)&int1_ths, 1);
- if (ret == 0) {
+ ret = lis3de_read_reg(ctx, LIS3DE_IG1_THS, (uint8_t *)&int1_ths, 1);
+
+ if (ret == 0)
+ {
int1_ths.ths = val;
- ret = lis3de_write_reg(ctx, LIS3DE_IG1_THS, (uint8_t*)&int1_ths, 1);
+ ret = lis3de_write_reg(ctx, LIS3DE_IG1_THS, (uint8_t *)&int1_ths, 1);
}
+
return ret;
}
@@ -973,7 +1108,7 @@ int32_t lis3de_int1_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3de_ig1_ths_t int1_ths;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_IG1_THS, (uint8_t*)&int1_ths, 1);
+ ret = lis3de_read_reg(ctx, LIS3DE_IG1_THS, (uint8_t *)&int1_ths, 1);
*val = (uint8_t)int1_ths.ths;
return ret;
@@ -993,11 +1128,16 @@ int32_t lis3de_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val)
lis3de_ig1_duration_t int1_duration;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_IG1_DURATION, (uint8_t*)&int1_duration, 1);
- if (ret == 0) {
+ ret = lis3de_read_reg(ctx, LIS3DE_IG1_DURATION,
+ (uint8_t *)&int1_duration, 1);
+
+ if (ret == 0)
+ {
int1_duration.d = val;
- ret = lis3de_write_reg(ctx, LIS3DE_IG1_DURATION, (uint8_t*)&int1_duration, 1);
+ ret = lis3de_write_reg(ctx, LIS3DE_IG1_DURATION,
+ (uint8_t *)&int1_duration, 1);
}
+
return ret;
}
@@ -1015,7 +1155,8 @@ int32_t lis3de_int1_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3de_ig1_duration_t int1_duration;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_IG1_DURATION, (uint8_t*)&int1_duration, 1);
+ ret = lis3de_read_reg(ctx, LIS3DE_IG1_DURATION,
+ (uint8_t *)&int1_duration, 1);
*val = (uint8_t)int1_duration.d;
return ret;
@@ -1043,10 +1184,12 @@ int32_t lis3de_int1_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lis3de_int2_gen_conf_set(stmdev_ctx_t *ctx,
- lis3de_ig2_cfg_t *val)
+ lis3de_ig2_cfg_t *val)
{
int32_t ret;
- ret = lis3de_write_reg(ctx, LIS3DE_IG2_CFG, (uint8_t*) val, 1);
+
+ ret = lis3de_write_reg(ctx, LIS3DE_IG2_CFG, (uint8_t *) val, 1);
+
return ret;
}
@@ -1059,10 +1202,12 @@ int32_t lis3de_int2_gen_conf_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis3de_int2_gen_conf_get(stmdev_ctx_t *ctx,
- lis3de_ig2_cfg_t *val)
+ lis3de_ig2_cfg_t *val)
{
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_IG2_CFG, (uint8_t*) val, 1);
+
+ ret = lis3de_read_reg(ctx, LIS3DE_IG2_CFG, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1074,10 +1219,12 @@ int32_t lis3de_int2_gen_conf_get(stmdev_ctx_t *ctx,
*
*/
int32_t lis3de_int2_gen_source_get(stmdev_ctx_t *ctx,
- lis3de_ig2_source_t *val)
+ lis3de_ig2_source_t *val)
{
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_IG2_SOURCE, (uint8_t*) val, 1);
+
+ ret = lis3de_read_reg(ctx, LIS3DE_IG2_SOURCE, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1095,11 +1242,14 @@ int32_t lis3de_int2_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
lis3de_ig2_ths_t int2_ths;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_IG2_THS, (uint8_t*)&int2_ths, 1);
- if (ret == 0) {
+ ret = lis3de_read_reg(ctx, LIS3DE_IG2_THS, (uint8_t *)&int2_ths, 1);
+
+ if (ret == 0)
+ {
int2_ths.ths = val;
- ret = lis3de_write_reg(ctx, LIS3DE_IG2_THS, (uint8_t*)&int2_ths, 1);
+ ret = lis3de_write_reg(ctx, LIS3DE_IG2_THS, (uint8_t *)&int2_ths, 1);
}
+
return ret;
}
@@ -1118,7 +1268,7 @@ int32_t lis3de_int2_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3de_ig2_ths_t int2_ths;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_IG2_THS, (uint8_t*)&int2_ths, 1);
+ ret = lis3de_read_reg(ctx, LIS3DE_IG2_THS, (uint8_t *)&int2_ths, 1);
*val = (uint8_t)int2_ths.ths;
return ret;
@@ -1138,11 +1288,16 @@ int32_t lis3de_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val)
lis3de_ig2_duration_t int2_duration;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_IG2_DURATION, (uint8_t*)&int2_duration, 1);
- if (ret == 0) {
+ ret = lis3de_read_reg(ctx, LIS3DE_IG2_DURATION,
+ (uint8_t *)&int2_duration, 1);
+
+ if (ret == 0)
+ {
int2_duration.d = val;
- ret = lis3de_write_reg(ctx, LIS3DE_IG2_DURATION, (uint8_t*)&int2_duration, 1);
+ ret = lis3de_write_reg(ctx, LIS3DE_IG2_DURATION,
+ (uint8_t *)&int2_duration, 1);
}
+
return ret;
}
@@ -1160,7 +1315,8 @@ int32_t lis3de_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3de_ig2_duration_t int2_duration;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_IG2_DURATION, (uint8_t*)&int2_duration, 1);
+ ret = lis3de_read_reg(ctx, LIS3DE_IG2_DURATION,
+ (uint8_t *)&int2_duration, 1);
*val = (uint8_t)int2_duration.d;
return ret;
@@ -1173,7 +1329,7 @@ int32_t lis3de_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @defgroup LIS3DE_Interrupt_pins
- * @brief This section group all the functions that manage interrup pins
+ * @brief This section group all the functions that manage interrupt pins
* @{
*
*/
@@ -1187,16 +1343,19 @@ int32_t lis3de_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lis3de_high_pass_int_conf_set(stmdev_ctx_t *ctx,
- lis3de_hp_t val)
+ lis3de_hp_t val)
{
lis3de_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if (ret == 0) {
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hp = (uint8_t)val;
- ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -1209,41 +1368,52 @@ int32_t lis3de_high_pass_int_conf_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis3de_high_pass_int_conf_get(stmdev_ctx_t *ctx,
- lis3de_hp_t *val)
+ lis3de_hp_t *val)
{
lis3de_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- switch (ctrl_reg2.hp) {
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ switch (ctrl_reg2.hp)
+ {
case LIS3DE_DISC_FROM_INT_GENERATOR:
*val = LIS3DE_DISC_FROM_INT_GENERATOR;
break;
+
case LIS3DE_ON_INT1_GEN:
*val = LIS3DE_ON_INT1_GEN;
break;
+
case LIS3DE_ON_INT2_GEN:
*val = LIS3DE_ON_INT2_GEN;
break;
+
case LIS3DE_ON_TAP_GEN:
*val = LIS3DE_ON_TAP_GEN;
break;
+
case LIS3DE_ON_INT1_INT2_GEN:
*val = LIS3DE_ON_INT1_INT2_GEN;
break;
+
case LIS3DE_ON_INT1_TAP_GEN:
*val = LIS3DE_ON_INT1_TAP_GEN;
break;
+
case LIS3DE_ON_INT2_TAP_GEN:
*val = LIS3DE_ON_INT2_TAP_GEN;
break;
+
case LIS3DE_ON_INT1_INT2_TAP_GEN:
*val = LIS3DE_ON_INT1_INT2_TAP_GEN;
break;
+
default:
*val = LIS3DE_DISC_FROM_INT_GENERATOR;
break;
}
+
return ret;
}
@@ -1256,10 +1426,12 @@ int32_t lis3de_high_pass_int_conf_get(stmdev_ctx_t *ctx,
*
*/
int32_t lis3de_pin_int1_config_set(stmdev_ctx_t *ctx,
- lis3de_ctrl_reg3_t *val)
+ lis3de_ctrl_reg3_t *val)
{
int32_t ret;
- ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG3, (uint8_t*) val, 1);
+
+ ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG3, (uint8_t *) val, 1);
+
return ret;
}
@@ -1272,10 +1444,12 @@ int32_t lis3de_pin_int1_config_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis3de_pin_int1_config_get(stmdev_ctx_t *ctx,
- lis3de_ctrl_reg3_t *val)
+ lis3de_ctrl_reg3_t *val)
{
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG3, (uint8_t*) val, 1);
+
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG3, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1293,11 +1467,14 @@ int32_t lis3de_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val)
lis3de_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.d4d_ig2 = val;
- ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -1315,7 +1492,7 @@ int32_t lis3de_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3de_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
*val = (uint8_t)ctrl_reg5.d4d_ig2;
return ret;
@@ -1332,16 +1509,19 @@ int32_t lis3de_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lis3de_int2_pin_notification_mode_set(stmdev_ctx_t *ctx,
- lis3de_lir_int2_t val)
+ lis3de_lir_int2_t val)
{
lis3de_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.lir_ig2 = (uint8_t)val;
- ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -1356,23 +1536,28 @@ int32_t lis3de_int2_pin_notification_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis3de_int2_pin_notification_mode_get(stmdev_ctx_t *ctx,
- lis3de_lir_int2_t *val)
+ lis3de_lir_int2_t *val)
{
lis3de_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- switch (ctrl_reg5.lir_ig2) {
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
+
+ switch (ctrl_reg5.lir_ig2)
+ {
case LIS3DE_INT2_PULSED:
*val = LIS3DE_INT2_PULSED;
break;
+
case LIS3DE_INT2_LATCHED:
*val = LIS3DE_INT2_LATCHED;
break;
+
default:
*val = LIS3DE_INT2_PULSED;
break;
}
+
return ret;
}
@@ -1390,11 +1575,14 @@ int32_t lis3de_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val)
lis3de_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.d4d_ig1 = val;
- ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -1412,7 +1600,7 @@ int32_t lis3de_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3de_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
*val = (uint8_t)ctrl_reg5.d4d_ig1;
return ret;
@@ -1428,16 +1616,19 @@ int32_t lis3de_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lis3de_int1_pin_notification_mode_set(stmdev_ctx_t *ctx,
- lis3de_lir_int1_t val)
+ lis3de_lir_int1_t val)
{
lis3de_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.lir_ig1 = (uint8_t)val;
- ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -1451,23 +1642,28 @@ int32_t lis3de_int1_pin_notification_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis3de_int1_pin_notification_mode_get(stmdev_ctx_t *ctx,
- lis3de_lir_int1_t *val)
+ lis3de_lir_int1_t *val)
{
lis3de_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- switch (ctrl_reg5.lir_ig1) {
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
+
+ switch (ctrl_reg5.lir_ig1)
+ {
case LIS3DE_INT1_PULSED:
*val = LIS3DE_INT1_PULSED;
break;
+
case LIS3DE_INT1_LATCHED:
*val = LIS3DE_INT1_LATCHED;
break;
+
default:
*val = LIS3DE_INT1_PULSED;
break;
}
+
return ret;
}
@@ -1480,10 +1676,12 @@ int32_t lis3de_int1_pin_notification_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t lis3de_pin_int2_config_set(stmdev_ctx_t *ctx,
- lis3de_ctrl_reg6_t *val)
+ lis3de_ctrl_reg6_t *val)
{
int32_t ret;
- ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG6, (uint8_t*) val, 1);
+
+ ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG6, (uint8_t *) val, 1);
+
return ret;
}
@@ -1496,10 +1694,12 @@ int32_t lis3de_pin_int2_config_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis3de_pin_int2_config_get(stmdev_ctx_t *ctx,
- lis3de_ctrl_reg6_t *val)
+ lis3de_ctrl_reg6_t *val)
{
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG6, (uint8_t*) val, 1);
+
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG6, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1527,11 +1727,14 @@ int32_t lis3de_fifo_set(stmdev_ctx_t *ctx, uint8_t val)
lis3de_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.fifo_en = val;
- ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -1548,7 +1751,7 @@ int32_t lis3de_fifo_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3de_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
*val = (uint8_t)ctrl_reg5.fifo_en;
return ret;
@@ -1567,11 +1770,16 @@ int32_t lis3de_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
lis3de_fifo_ctrl_reg_t fifo_ctrl_reg;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
- if (ret == 0) {
+ ret = lis3de_read_reg(ctx, LIS3DE_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl_reg.fth = val;
- ret = lis3de_write_reg(ctx, LIS3DE_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
+ ret = lis3de_write_reg(ctx, LIS3DE_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
}
+
return ret;
}
@@ -1588,7 +1796,8 @@ int32_t lis3de_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3de_fifo_ctrl_reg_t fifo_ctrl_reg;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
+ ret = lis3de_read_reg(ctx, LIS3DE_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
*val = (uint8_t)fifo_ctrl_reg.fth;
return ret;
@@ -1603,16 +1812,21 @@ int32_t lis3de_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lis3de_fifo_trigger_event_set(stmdev_ctx_t *ctx,
- lis3de_tr_t val)
+ lis3de_tr_t val)
{
lis3de_fifo_ctrl_reg_t fifo_ctrl_reg;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
- if (ret == 0) {
+ ret = lis3de_read_reg(ctx, LIS3DE_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl_reg.tr = (uint8_t)val;
- ret = lis3de_write_reg(ctx, LIS3DE_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
+ ret = lis3de_write_reg(ctx, LIS3DE_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
}
+
return ret;
}
@@ -1625,23 +1839,29 @@ int32_t lis3de_fifo_trigger_event_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis3de_fifo_trigger_event_get(stmdev_ctx_t *ctx,
- lis3de_tr_t *val)
+ lis3de_tr_t *val)
{
lis3de_fifo_ctrl_reg_t fifo_ctrl_reg;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
- switch (fifo_ctrl_reg.tr) {
+ ret = lis3de_read_reg(ctx, LIS3DE_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
+
+ switch (fifo_ctrl_reg.tr)
+ {
case LIS3DE_INT1_GEN:
*val = LIS3DE_INT1_GEN;
break;
+
case LIS3DE_INT2_GEN:
*val = LIS3DE_INT2_GEN;
break;
+
default:
*val = LIS3DE_INT1_GEN;
break;
}
+
return ret;
}
@@ -1658,11 +1878,16 @@ int32_t lis3de_fifo_mode_set(stmdev_ctx_t *ctx, lis3de_fm_t val)
lis3de_fifo_ctrl_reg_t fifo_ctrl_reg;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
- if (ret == 0) {
+ ret = lis3de_read_reg(ctx, LIS3DE_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl_reg.fm = (uint8_t)val;
- ret = lis3de_write_reg(ctx, LIS3DE_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
+ ret = lis3de_write_reg(ctx, LIS3DE_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
}
+
return ret;
}
@@ -1679,24 +1904,32 @@ int32_t lis3de_fifo_mode_get(stmdev_ctx_t *ctx, lis3de_fm_t *val)
lis3de_fifo_ctrl_reg_t fifo_ctrl_reg;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
- switch (fifo_ctrl_reg.fm) {
+ ret = lis3de_read_reg(ctx, LIS3DE_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
+
+ switch (fifo_ctrl_reg.fm)
+ {
case LIS3DE_BYPASS_MODE:
*val = LIS3DE_BYPASS_MODE;
break;
+
case LIS3DE_FIFO_MODE:
*val = LIS3DE_FIFO_MODE;
break;
+
case LIS3DE_DYNAMIC_STREAM_MODE:
*val = LIS3DE_DYNAMIC_STREAM_MODE;
break;
+
case LIS3DE_STREAM_TO_FIFO_MODE:
*val = LIS3DE_STREAM_TO_FIFO_MODE;
break;
+
default:
*val = LIS3DE_BYPASS_MODE;
break;
}
+
return ret;
}
@@ -1709,10 +1942,12 @@ int32_t lis3de_fifo_mode_get(stmdev_ctx_t *ctx, lis3de_fm_t *val)
*
*/
int32_t lis3de_fifo_status_get(stmdev_ctx_t *ctx,
- lis3de_fifo_src_reg_t *val)
+ lis3de_fifo_src_reg_t *val)
{
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_FIFO_SRC_REG, (uint8_t*) val, 1);
+
+ ret = lis3de_read_reg(ctx, LIS3DE_FIFO_SRC_REG, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1728,7 +1963,8 @@ int32_t lis3de_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3de_fifo_src_reg_t fifo_src_reg;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1);
+ ret = lis3de_read_reg(ctx, LIS3DE_FIFO_SRC_REG,
+ (uint8_t *)&fifo_src_reg, 1);
*val = (uint8_t)fifo_src_reg.fss;
return ret;
@@ -1746,7 +1982,8 @@ int32_t lis3de_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3de_fifo_src_reg_t fifo_src_reg;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1);
+ ret = lis3de_read_reg(ctx, LIS3DE_FIFO_SRC_REG,
+ (uint8_t *)&fifo_src_reg, 1);
*val = (uint8_t)fifo_src_reg.empty;
return ret;
@@ -1764,7 +2001,8 @@ int32_t lis3de_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3de_fifo_src_reg_t fifo_src_reg;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1);
+ ret = lis3de_read_reg(ctx, LIS3DE_FIFO_SRC_REG,
+ (uint8_t *)&fifo_src_reg, 1);
*val = (uint8_t)fifo_src_reg.ovrn_fifo;
return ret;
@@ -1782,7 +2020,8 @@ int32_t lis3de_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3de_fifo_src_reg_t fifo_src_reg;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1);
+ ret = lis3de_read_reg(ctx, LIS3DE_FIFO_SRC_REG,
+ (uint8_t *)&fifo_src_reg, 1);
*val = (uint8_t)fifo_src_reg.wtm;
return ret;
@@ -1808,10 +2047,13 @@ int32_t lis3de_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3de_tap_conf_set(stmdev_ctx_t *ctx, lis3de_click_cfg_t *val)
+int32_t lis3de_tap_conf_set(stmdev_ctx_t *ctx,
+ lis3de_click_cfg_t *val)
{
int32_t ret;
- ret = lis3de_write_reg(ctx, LIS3DE_CLICK_CFG, (uint8_t*) val, 1);
+
+ ret = lis3de_write_reg(ctx, LIS3DE_CLICK_CFG, (uint8_t *) val, 1);
+
return ret;
}
@@ -1823,10 +2065,13 @@ int32_t lis3de_tap_conf_set(stmdev_ctx_t *ctx, lis3de_click_cfg_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3de_tap_conf_get(stmdev_ctx_t *ctx, lis3de_click_cfg_t *val)
+int32_t lis3de_tap_conf_get(stmdev_ctx_t *ctx,
+ lis3de_click_cfg_t *val)
{
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CLICK_CFG, (uint8_t*) val, 1);
+
+ ret = lis3de_read_reg(ctx, LIS3DE_CLICK_CFG, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1837,10 +2082,13 @@ int32_t lis3de_tap_conf_get(stmdev_ctx_t *ctx, lis3de_click_cfg_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3de_tap_source_get(stmdev_ctx_t *ctx, lis3de_click_src_t *val)
+int32_t lis3de_tap_source_get(stmdev_ctx_t *ctx,
+ lis3de_click_src_t *val)
{
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CLICK_SRC, (uint8_t*) val, 1);
+
+ ret = lis3de_read_reg(ctx, LIS3DE_CLICK_SRC, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1857,11 +2105,14 @@ int32_t lis3de_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
lis3de_click_ths_t click_ths;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CLICK_THS, (uint8_t*)&click_ths, 1);
- if (ret == 0) {
+ ret = lis3de_read_reg(ctx, LIS3DE_CLICK_THS, (uint8_t *)&click_ths, 1);
+
+ if (ret == 0)
+ {
click_ths.ths = val;
- ret = lis3de_write_reg(ctx, LIS3DE_CLICK_THS, (uint8_t*)&click_ths, 1);
+ ret = lis3de_write_reg(ctx, LIS3DE_CLICK_THS, (uint8_t *)&click_ths, 1);
}
+
return ret;
}
@@ -1879,7 +2130,7 @@ int32_t lis3de_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3de_click_ths_t click_ths;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CLICK_THS, (uint8_t*)&click_ths, 1);
+ ret = lis3de_read_reg(ctx, LIS3DE_CLICK_THS, (uint8_t *)&click_ths, 1);
*val = (uint8_t)click_ths.ths;
return ret;
@@ -1897,16 +2148,19 @@ int32_t lis3de_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lis3de_tap_notification_mode_set(stmdev_ctx_t *ctx,
- lis3de_lir_t val)
+ lis3de_lir_t val)
{
lis3de_click_ths_t click_ths;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CLICK_THS, (uint8_t*)&click_ths, 1);
- if (ret == 0) {
+ ret = lis3de_read_reg(ctx, LIS3DE_CLICK_THS, (uint8_t *)&click_ths, 1);
+
+ if (ret == 0)
+ {
click_ths.lir = (uint8_t)val;
- ret = lis3de_write_reg(ctx, LIS3DE_CLICK_THS, (uint8_t*)&click_ths, 1);
+ ret = lis3de_write_reg(ctx, LIS3DE_CLICK_THS, (uint8_t *)&click_ths, 1);
}
+
return ret;
}
@@ -1922,23 +2176,28 @@ int32_t lis3de_tap_notification_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis3de_tap_notification_mode_get(stmdev_ctx_t *ctx,
- lis3de_lir_t *val)
+ lis3de_lir_t *val)
{
lis3de_click_ths_t click_ths;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CLICK_THS, (uint8_t*)&click_ths, 1);
- switch (click_ths.lir) {
+ ret = lis3de_read_reg(ctx, LIS3DE_CLICK_THS, (uint8_t *)&click_ths, 1);
+
+ switch (click_ths.lir)
+ {
case LIS3DE_TAP_PULSED:
*val = LIS3DE_TAP_PULSED;
break;
+
case LIS3DE_TAP_LATCHED:
*val = LIS3DE_TAP_LATCHED;
break;
+
default:
*val = LIS3DE_TAP_PULSED;
break;
}
+
return ret;
}
@@ -1957,11 +2216,14 @@ int32_t lis3de_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lis3de_time_limit_t time_limit;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_TIME_LIMIT, (uint8_t*)&time_limit, 1);
- if (ret == 0) {
+ ret = lis3de_read_reg(ctx, LIS3DE_TIME_LIMIT, (uint8_t *)&time_limit, 1);
+
+ if (ret == 0)
+ {
time_limit.tli = val;
- ret = lis3de_write_reg(ctx, LIS3DE_TIME_LIMIT, (uint8_t*)&time_limit, 1);
+ ret = lis3de_write_reg(ctx, LIS3DE_TIME_LIMIT, (uint8_t *)&time_limit, 1);
}
+
return ret;
}
@@ -1980,7 +2242,7 @@ int32_t lis3de_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3de_time_limit_t time_limit;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_TIME_LIMIT, (uint8_t*)&time_limit, 1);
+ ret = lis3de_read_reg(ctx, LIS3DE_TIME_LIMIT, (uint8_t *)&time_limit, 1);
*val = (uint8_t)time_limit.tli;
return ret;
@@ -2002,11 +2264,16 @@ int32_t lis3de_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lis3de_time_latency_t time_latency;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_TIME_LATENCY, (uint8_t*)&time_latency, 1);
- if (ret == 0) {
+ ret = lis3de_read_reg(ctx, LIS3DE_TIME_LATENCY,
+ (uint8_t *)&time_latency, 1);
+
+ if (ret == 0)
+ {
time_latency.tla = val;
- ret = lis3de_write_reg(ctx, LIS3DE_TIME_LATENCY, (uint8_t*)&time_latency, 1);
+ ret = lis3de_write_reg(ctx, LIS3DE_TIME_LATENCY,
+ (uint8_t *)&time_latency, 1);
}
+
return ret;
}
@@ -2026,7 +2293,8 @@ int32_t lis3de_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3de_time_latency_t time_latency;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_TIME_LATENCY, (uint8_t*)&time_latency, 1);
+ ret = lis3de_read_reg(ctx, LIS3DE_TIME_LATENCY,
+ (uint8_t *)&time_latency, 1);
*val = (uint8_t)time_latency.tla;
return ret;
@@ -2048,11 +2316,16 @@ int32_t lis3de_double_tap_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
lis3de_time_window_t time_window;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_TIME_WINDOW, (uint8_t*)&time_window, 1);
- if (ret == 0) {
+ ret = lis3de_read_reg(ctx, LIS3DE_TIME_WINDOW,
+ (uint8_t *)&time_window, 1);
+
+ if (ret == 0)
+ {
time_window.tw = val;
- ret = lis3de_write_reg(ctx, LIS3DE_TIME_WINDOW, (uint8_t*)&time_window, 1);
+ ret = lis3de_write_reg(ctx, LIS3DE_TIME_WINDOW,
+ (uint8_t *)&time_window, 1);
}
+
return ret;
}
@@ -2072,7 +2345,8 @@ int32_t lis3de_double_tap_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3de_time_window_t time_window;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_TIME_WINDOW, (uint8_t*)&time_window, 1);
+ ret = lis3de_read_reg(ctx, LIS3DE_TIME_WINDOW,
+ (uint8_t *)&time_window, 1);
*val = (uint8_t)time_window.tw;
return ret;
@@ -2106,11 +2380,14 @@ int32_t lis3de_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
lis3de_act_ths_t act_ths;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_ACT_THS, (uint8_t*)&act_ths, 1);
- if (ret == 0) {
+ ret = lis3de_read_reg(ctx, LIS3DE_ACT_THS, (uint8_t *)&act_ths, 1);
+
+ if (ret == 0)
+ {
act_ths.acth = val;
- ret = lis3de_write_reg(ctx, LIS3DE_ACT_THS, (uint8_t*)&act_ths, 1);
+ ret = lis3de_write_reg(ctx, LIS3DE_ACT_THS, (uint8_t *)&act_ths, 1);
}
+
return ret;
}
@@ -2129,7 +2406,7 @@ int32_t lis3de_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3de_act_ths_t act_ths;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_ACT_THS, (uint8_t*)&act_ths, 1);
+ ret = lis3de_read_reg(ctx, LIS3DE_ACT_THS, (uint8_t *)&act_ths, 1);
*val = (uint8_t)act_ths.acth;
return ret;
@@ -2149,11 +2426,14 @@ int32_t lis3de_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
lis3de_act_dur_t act_dur;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_ACT_DUR, (uint8_t*)&act_dur, 1);
- if (ret == 0) {
+ ret = lis3de_read_reg(ctx, LIS3DE_ACT_DUR, (uint8_t *)&act_dur, 1);
+
+ if (ret == 0)
+ {
act_dur.actd = val;
- ret = lis3de_write_reg(ctx, LIS3DE_ACT_DUR, (uint8_t*)&act_dur, 1);
+ ret = lis3de_write_reg(ctx, LIS3DE_ACT_DUR, (uint8_t *)&act_dur, 1);
}
+
return ret;
}
@@ -2171,7 +2451,7 @@ int32_t lis3de_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3de_act_dur_t act_dur;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_ACT_DUR, (uint8_t*)&act_dur, 1);
+ ret = lis3de_read_reg(ctx, LIS3DE_ACT_DUR, (uint8_t *)&act_dur, 1);
*val = (uint8_t)act_dur.actd;
return ret;
@@ -2203,11 +2483,14 @@ int32_t lis3de_spi_mode_set(stmdev_ctx_t *ctx, lis3de_sim_t val)
lis3de_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if (ret == 0) {
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.sim = (uint8_t)val;
- ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis3de_write_reg(ctx, LIS3DE_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -2224,18 +2507,23 @@ int32_t lis3de_spi_mode_get(stmdev_ctx_t *ctx, lis3de_sim_t *val)
lis3de_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- switch (ctrl_reg4.sim) {
+ ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ switch (ctrl_reg4.sim)
+ {
case LIS3DE_SPI_4_WIRE:
*val = LIS3DE_SPI_4_WIRE;
break;
+
case LIS3DE_SPI_3_WIRE:
*val = LIS3DE_SPI_3_WIRE;
break;
+
default:
*val = LIS3DE_SPI_4_WIRE;
break;
}
+
return ret;
}
diff --git a/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.h b/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.h
index 11dc3ef8f216e32c9b98132fc5fb3bad3d895d36..8966d95819e7458ad98ec6e6e3470abf6af4ba54 100644
--- a/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.h
+++ b/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file lis3de_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lis3de_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lis3de_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lis3de_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LIS3DE_REGS_H
#define LIS3DE_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup LIS3DE
@@ -35,6 +36,37 @@
*
*/
+/** @defgroup Endianness definitions
+ * @{
+ *
+ */
+
+#ifndef DRV_BYTE_ORDER
+#ifndef __BYTE_ORDER__
+
+#define DRV_LITTLE_ENDIAN 1234
+#define DRV_BIG_ENDIAN 4321
+
+/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
+ * by uncommenting the define which fits your platform endianness
+ */
+//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
+#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
+
+#else /* defined __BYTE_ORDER__ */
+
+#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
+#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
+#define DRV_BYTE_ORDER __BYTE_ORDER__
+
+#endif /* __BYTE_ORDER__*/
+#endif /* DRV_BYTE_ORDER */
+
+/**
+ * @}
+ *
+ */
+
/** @defgroup STMicroelectronics sensors common types
* @{
*
@@ -43,7 +75,9 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -52,6 +86,16 @@ typedef struct{
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} bitwise_t;
#define PROPERTY_DISABLE (0U)
@@ -65,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -89,15 +134,16 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
- * Unico / Unicleo tools available on STMicroelectronics
- * web site.
+ * You can create a sensor configuration by your own or using
+ * Unico / Unicleo tools available on STMicroelectronics
+ * web site.
*
* @{
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -132,7 +178,9 @@ typedef struct {
*/
#define LIS3DE_STATUS_REG_AUX 0x07U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t _1da : 1;
uint8_t _2da : 1;
uint8_t _3da : 1;
@@ -141,6 +189,16 @@ typedef struct {
uint8_t _2or : 1;
uint8_t _3or : 1;
uint8_t _321or : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t _321or : 1;
+ uint8_t _3or : 1;
+ uint8_t _2or : 1;
+ uint8_t _1or : 1;
+ uint8_t _321da : 1;
+ uint8_t _3da : 1;
+ uint8_t _2da : 1;
+ uint8_t _1da : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3de_status_reg_aux_t;
#define LIS3DE_OUT_ADC1_L 0x08U
@@ -153,31 +211,57 @@ typedef struct {
#define LIS3DE_WHO_AM_I 0x0FU
#define LIS3DE_TEMP_CFG_REG 0x1FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 6;
uint8_t adc_pd : 1;
uint8_t temp_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t temp_en : 1;
+ uint8_t adc_pd : 1;
+ uint8_t not_used_01 : 6;
+#endif /* DRV_BYTE_ORDER */
} lis3de_temp_cfg_reg_t;
#define LIS3DE_CTRL_REG1 0x20U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xen : 1;
uint8_t yen : 1;
uint8_t zen : 1;
uint8_t lpen : 1;
uint8_t odr : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr : 4;
+ uint8_t lpen : 1;
+ uint8_t zen : 1;
+ uint8_t yen : 1;
+ uint8_t xen : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3de_ctrl_reg1_t;
#define LIS3DE_CTRL_REG2 0x21U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t hp : 3; /* HPCLICK + HP_IA2 + HP_IA1 -> HP */
uint8_t fds : 1;
uint8_t hpcf : 2;
uint8_t hpm : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t hpm : 2;
+ uint8_t hpcf : 2;
+ uint8_t fds : 1;
+ uint8_t hp : 3; /* HPCLICK + HP_IA2 + HP_IA1 -> HP */
+#endif /* DRV_BYTE_ORDER */
} lis3de_ctrl_reg2_t;
#define LIS3DE_CTRL_REG3 0x22U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t int1_overrun : 1;
uint8_t int1_wtm : 1;
@@ -186,20 +270,42 @@ typedef struct {
uint8_t int1_ig2 : 1;
uint8_t int1_ig1 : 1;
uint8_t int1_click : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_click : 1;
+ uint8_t int1_ig1 : 1;
+ uint8_t int1_ig2 : 1;
+ uint8_t int1_drdy1 : 1;
+ uint8_t int1_drdy2 : 1;
+ uint8_t int1_wtm : 1;
+ uint8_t int1_overrun : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3de_ctrl_reg3_t;
#define LIS3DE_CTRL_REG4 0x23U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t st : 2;
uint8_t not_used_01 : 1;
uint8_t fs : 2;
uint8_t not_used_02 : 1;
uint8_t bdu : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bdu : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t fs : 2;
+ uint8_t not_used_01 : 1;
+ uint8_t st : 2;
+ uint8_t sim : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3de_ctrl_reg4_t;
#define LIS3DE_CTRL_REG5 0x24U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d4d_ig2 : 1;
uint8_t lir_ig2 : 1;
uint8_t d4d_ig1 : 1;
@@ -207,10 +313,21 @@ typedef struct {
uint8_t not_used_01 : 2;
uint8_t fifo_en : 1;
uint8_t boot : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t boot : 1;
+ uint8_t fifo_en : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t lir_ig1 : 1;
+ uint8_t d4d_ig1 : 1;
+ uint8_t lir_ig2 : 1;
+ uint8_t d4d_ig2 : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3de_ctrl_reg5_t;
#define LIS3DE_CTRL_REG6 0x25U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t h_lactive : 1;
uint8_t not_used_02 : 1;
@@ -219,11 +336,23 @@ typedef struct {
uint8_t int2_ig2 : 1;
uint8_t int2_ig1 : 1;
uint8_t int2_click : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_click : 1;
+ uint8_t int2_ig1 : 1;
+ uint8_t int2_ig2 : 1;
+ uint8_t int2_boot : 1;
+ uint8_t int2_act : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t h_lactive : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3de_ctrl_reg6_t;
#define LIS3DE_REFERENCE 0x26U
#define LIS3DE_STATUS_REG 0x27U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xda : 1;
uint8_t yda : 1;
uint8_t zda : 1;
@@ -232,28 +361,55 @@ typedef struct {
uint8_t yor : 1;
uint8_t zor : 1;
uint8_t zyxor : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t zyxor : 1;
+ uint8_t zor : 1;
+ uint8_t yor : 1;
+ uint8_t _xor : 1;
+ uint8_t zyxda : 1;
+ uint8_t zda : 1;
+ uint8_t yda : 1;
+ uint8_t xda : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3de_status_reg_t;
#define LIS3DE_OUT_X 0x29U
#define LIS3DE_OUT_Y 0x2BU
#define LIS3DE_OUT_Z 0x2DU
#define LIS3DE_FIFO_CTRL_REG 0x2EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fth : 5;
uint8_t tr : 1;
uint8_t fm : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fm : 2;
+ uint8_t tr : 1;
+ uint8_t fth : 5;
+#endif /* DRV_BYTE_ORDER */
} lis3de_fifo_ctrl_reg_t;
#define LIS3DE_FIFO_SRC_REG 0x2FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fss : 5;
uint8_t empty : 1;
uint8_t ovrn_fifo : 1;
uint8_t wtm : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t wtm : 1;
+ uint8_t ovrn_fifo : 1;
+ uint8_t empty : 1;
+ uint8_t fss : 5;
+#endif /* DRV_BYTE_ORDER */
} lis3de_fifo_src_reg_t;
#define LIS3DE_IG1_CFG 0x30U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlie : 1;
uint8_t xhie : 1;
uint8_t ylie : 1;
@@ -262,10 +418,22 @@ typedef struct {
uint8_t zhie : 1;
uint8_t _6d : 1;
uint8_t aoi : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t aoi : 1;
+ uint8_t _6d : 1;
+ uint8_t zhie : 1;
+ uint8_t zlie : 1;
+ uint8_t yhie : 1;
+ uint8_t ylie : 1;
+ uint8_t xhie : 1;
+ uint8_t xlie : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3de_ig1_cfg_t;
#define LIS3DE_IG1_SOURCE 0x31U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
uint8_t yl : 1;
@@ -274,22 +442,46 @@ typedef struct {
uint8_t zh : 1;
uint8_t ia : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t ia : 1;
+ uint8_t zh : 1;
+ uint8_t zl : 1;
+ uint8_t yh : 1;
+ uint8_t yl : 1;
+ uint8_t xh : 1;
+ uint8_t xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3de_ig1_source_t;
#define LIS3DE_IG1_THS 0x32U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t ths : 7;
+#endif /* DRV_BYTE_ORDER */
} lis3de_ig1_ths_t;
#define LIS3DE_IG1_DURATION 0x33U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d : 7;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t d : 7;
+#endif /* DRV_BYTE_ORDER */
} lis3de_ig1_duration_t;
#define LIS3DE_IG2_CFG 0x34U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlie : 1;
uint8_t xhie : 1;
uint8_t ylie : 1;
@@ -298,10 +490,22 @@ typedef struct {
uint8_t zhie : 1;
uint8_t _6d : 1;
uint8_t aoi : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t aoi : 1;
+ uint8_t _6d : 1;
+ uint8_t zhie : 1;
+ uint8_t zlie : 1;
+ uint8_t yhie : 1;
+ uint8_t ylie : 1;
+ uint8_t xhie : 1;
+ uint8_t xlie : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3de_ig2_cfg_t;
#define LIS3DE_IG2_SOURCE 0x35U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
uint8_t yl : 1;
@@ -310,22 +514,46 @@ typedef struct {
uint8_t zh : 1;
uint8_t ia : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t ia : 1;
+ uint8_t zh : 1;
+ uint8_t zl : 1;
+ uint8_t yh : 1;
+ uint8_t yl : 1;
+ uint8_t xh : 1;
+ uint8_t xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3de_ig2_source_t;
#define LIS3DE_IG2_THS 0x36U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t ths : 7;
+#endif /* DRV_BYTE_ORDER */
} lis3de_ig2_ths_t;
#define LIS3DE_IG2_DURATION 0x37U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d : 7;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t d : 7;
+#endif /* DRV_BYTE_ORDER */
} lis3de_ig2_duration_t;
#define LIS3DE_CLICK_CFG 0x38U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xs : 1;
uint8_t xd : 1;
uint8_t ys : 1;
@@ -333,10 +561,21 @@ typedef struct {
uint8_t zs : 1;
uint8_t zd : 1;
uint8_t not_used_01 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 2;
+ uint8_t zd : 1;
+ uint8_t zs : 1;
+ uint8_t yd : 1;
+ uint8_t ys : 1;
+ uint8_t xd : 1;
+ uint8_t xs : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3de_click_cfg_t;
#define LIS3DE_CLICK_SRC 0x39U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t x : 1;
uint8_t y : 1;
uint8_t z : 1;
@@ -345,54 +584,86 @@ typedef struct {
uint8_t dclick : 1;
uint8_t ia : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t ia : 1;
+ uint8_t dclick : 1;
+ uint8_t sclick : 1;
+ uint8_t sign : 1;
+ uint8_t z : 1;
+ uint8_t y : 1;
+ uint8_t x : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3de_click_src_t;
#define LIS3DE_CLICK_THS 0x3AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t lir : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t lir : 1;
+ uint8_t ths : 7;
+#endif /* DRV_BYTE_ORDER */
} lis3de_click_ths_t;
#define LIS3DE_TIME_LIMIT 0x3BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tli : 7;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t tli : 7;
+#endif /* DRV_BYTE_ORDER */
} lis3de_time_limit_t;
#define LIS3DE_TIME_LATENCY 0x3CU
-typedef struct {
+typedef struct
+{
uint8_t tla : 8;
} lis3de_time_latency_t;
#define LIS3DE_TIME_WINDOW 0x3DU
-typedef struct {
+typedef struct
+{
uint8_t tw : 8;
} lis3de_time_window_t;
#define LIS3DE_ACT_THS 0x3EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t acth : 7;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t acth : 7;
+#endif /* DRV_BYTE_ORDER */
} lis3de_act_ths_t;
#define LIS3DE_ACT_DUR 0x3FU
-typedef struct {
+typedef struct
+{
uint8_t actd : 8;
} lis3de_act_dur_t;
/**
* @defgroup LIS3DE_Register_Union
- * @brief This union group all the registers that has a bitfield
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is usefull but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
- * REMOVING this union you are complient with:
+ * REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
*
* @{
*
*/
-typedef union{
+typedef union
+{
lis3de_status_reg_aux_t status_reg_aux;
lis3de_temp_cfg_reg_t temp_cfg_reg;
lis3de_ctrl_reg1_t ctrl_reg1;
@@ -429,16 +700,18 @@ typedef union{
*
*/
-int32_t lis3de_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
- uint16_t len);
-int32_t lis3de_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
- uint16_t len);
+int32_t lis3de_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
+ uint16_t len);
+int32_t lis3de_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len);
+
+float_t lis3de_from_fs2_to_mg(int16_t lsb);
+float_t lis3de_from_fs4_to_mg(int16_t lsb);
+float_t lis3de_from_fs8_to_mg(int16_t lsb);
+float_t lis3de_from_fs16_to_mg(int16_t lsb);
-extern float lis3de_from_fs2_to_mg(int16_t lsb);
-extern float lis3de_from_fs4_to_mg(int16_t lsb);
-extern float lis3de_from_fs8_to_mg(int16_t lsb);
-extern float lis3de_from_fs16_to_mg(int16_t lsb);
-extern float lis3de_from_lsb_to_celsius(int16_t lsb);
+float_t lis3de_from_lsb_to_celsius(int16_t lsb);
int32_t lis3de_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t lis3de_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -446,9 +719,10 @@ int32_t lis3de_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis3de_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis3de_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lis3de_adc_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lis3de_adc_raw_get(stmdev_ctx_t *ctx, int16_t *val);
-typedef enum {
+typedef enum
+{
LIS3DE_AUX_DISABLE = 0,
LIS3DE_AUX_ON_TEMPERATURE = 3,
LIS3DE_AUX_ON_PADS = 1,
@@ -456,14 +730,18 @@ typedef enum {
int32_t lis3de_aux_adc_set(stmdev_ctx_t *ctx, lis3de_temp_en_t val);
int32_t lis3de_aux_adc_get(stmdev_ctx_t *ctx, lis3de_temp_en_t *val);
-typedef enum {
+typedef enum
+{
LIS3DE_NM = 0,
LIS3DE_LP = 1,
} lis3de_op_md_t;
-int32_t lis3de_operating_mode_set(stmdev_ctx_t *ctx, lis3de_op_md_t val);
-int32_t lis3de_operating_mode_get(stmdev_ctx_t *ctx, lis3de_op_md_t *val);
+int32_t lis3de_operating_mode_set(stmdev_ctx_t *ctx,
+ lis3de_op_md_t val);
+int32_t lis3de_operating_mode_get(stmdev_ctx_t *ctx,
+ lis3de_op_md_t *val);
-typedef enum {
+typedef enum
+{
LIS3DE_POWER_DOWN = 0x00,
LIS3DE_ODR_1Hz = 0x01,
LIS3DE_ODR_10Hz = 0x02,
@@ -478,30 +756,37 @@ typedef enum {
int32_t lis3de_data_rate_set(stmdev_ctx_t *ctx, lis3de_odr_t val);
int32_t lis3de_data_rate_get(stmdev_ctx_t *ctx, lis3de_odr_t *val);
-int32_t lis3de_high_pass_on_outputs_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis3de_high_pass_on_outputs_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis3de_high_pass_on_outputs_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis3de_high_pass_on_outputs_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS3DE_AGGRESSIVE = 0,
LIS3DE_STRONG = 1,
LIS3DE_MEDIUM = 2,
LIS3DE_LIGHT = 3,
} lis3de_hpcf_t;
int32_t lis3de_high_pass_bandwidth_set(stmdev_ctx_t *ctx,
- lis3de_hpcf_t val);
+ lis3de_hpcf_t val);
int32_t lis3de_high_pass_bandwidth_get(stmdev_ctx_t *ctx,
- lis3de_hpcf_t *val);
+ lis3de_hpcf_t *val);
-typedef enum {
+typedef enum
+{
LIS3DE_NORMAL_WITH_RST = 0,
LIS3DE_REFERENCE_MODE = 1,
LIS3DE_NORMAL = 2,
LIS3DE_AUTORST_ON_INT = 3,
} lis3de_hpm_t;
-int32_t lis3de_high_pass_mode_set(stmdev_ctx_t *ctx, lis3de_hpm_t val);
-int32_t lis3de_high_pass_mode_get(stmdev_ctx_t *ctx, lis3de_hpm_t *val);
+int32_t lis3de_high_pass_mode_set(stmdev_ctx_t *ctx,
+ lis3de_hpm_t val);
+int32_t lis3de_high_pass_mode_get(stmdev_ctx_t *ctx,
+ lis3de_hpm_t *val);
-typedef enum {
+typedef enum
+{
LIS3DE_2g = 0,
LIS3DE_4g = 1,
LIS3DE_8g = 2,
@@ -524,7 +809,8 @@ int32_t lis3de_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *buff);
int32_t lis3de_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
-typedef enum {
+typedef enum
+{
LIS3DE_ST_DISABLE = 0,
LIS3DE_ST_POSITIVE = 1,
LIS3DE_ST_NEGATIVE = 2,
@@ -535,37 +821,41 @@ int32_t lis3de_self_test_get(stmdev_ctx_t *ctx, lis3de_st_t *val);
int32_t lis3de_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3de_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lis3de_status_get(stmdev_ctx_t *ctx, lis3de_status_reg_t *val);
+int32_t lis3de_status_get(stmdev_ctx_t *ctx,
+ lis3de_status_reg_t *val);
int32_t lis3de_int1_gen_conf_set(stmdev_ctx_t *ctx,
- lis3de_ig1_cfg_t *val);
+ lis3de_ig1_cfg_t *val);
int32_t lis3de_int1_gen_conf_get(stmdev_ctx_t *ctx,
- lis3de_ig1_cfg_t *val);
+ lis3de_ig1_cfg_t *val);
int32_t lis3de_int1_gen_source_get(stmdev_ctx_t *ctx,
- lis3de_ig1_source_t *val);
+ lis3de_ig1_source_t *val);
int32_t lis3de_int1_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis3de_int1_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis3de_int1_gen_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lis3de_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3de_int1_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis3de_int2_gen_conf_set(stmdev_ctx_t *ctx,
- lis3de_ig2_cfg_t *val);
+ lis3de_ig2_cfg_t *val);
int32_t lis3de_int2_gen_conf_get(stmdev_ctx_t *ctx,
- lis3de_ig2_cfg_t *val);
+ lis3de_ig2_cfg_t *val);
int32_t lis3de_int2_gen_source_get(stmdev_ctx_t *ctx,
- lis3de_ig2_source_t *val);
+ lis3de_ig2_source_t *val);
int32_t lis3de_int2_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis3de_int2_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis3de_int2_gen_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lis3de_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3de_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS3DE_DISC_FROM_INT_GENERATOR = 0,
LIS3DE_ON_INT1_GEN = 1,
LIS3DE_ON_INT2_GEN = 2,
@@ -576,43 +866,47 @@ typedef enum {
LIS3DE_ON_INT1_INT2_TAP_GEN = 7,
} lis3de_hp_t;
int32_t lis3de_high_pass_int_conf_set(stmdev_ctx_t *ctx,
- lis3de_hp_t val);
+ lis3de_hp_t val);
int32_t lis3de_high_pass_int_conf_get(stmdev_ctx_t *ctx,
- lis3de_hp_t *val);
+ lis3de_hp_t *val);
int32_t lis3de_pin_int1_config_set(stmdev_ctx_t *ctx,
- lis3de_ctrl_reg3_t *val);
+ lis3de_ctrl_reg3_t *val);
int32_t lis3de_pin_int1_config_get(stmdev_ctx_t *ctx,
- lis3de_ctrl_reg3_t *val);
+ lis3de_ctrl_reg3_t *val);
int32_t lis3de_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis3de_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis3de_int2_pin_detect_4d_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS3DE_INT2_PULSED = 0,
LIS3DE_INT2_LATCHED = 1,
} lis3de_lir_int2_t;
int32_t lis3de_int2_pin_notification_mode_set(stmdev_ctx_t *ctx,
- lis3de_lir_int2_t val);
+ lis3de_lir_int2_t val);
int32_t lis3de_int2_pin_notification_mode_get(stmdev_ctx_t *ctx,
- lis3de_lir_int2_t *val);
+ lis3de_lir_int2_t *val);
int32_t lis3de_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis3de_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis3de_int1_pin_detect_4d_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS3DE_INT1_PULSED = 0,
LIS3DE_INT1_LATCHED = 1,
} lis3de_lir_int1_t;
int32_t lis3de_int1_pin_notification_mode_set(stmdev_ctx_t *ctx,
- lis3de_lir_int1_t val);
+ lis3de_lir_int1_t val);
int32_t lis3de_int1_pin_notification_mode_get(stmdev_ctx_t *ctx,
- lis3de_lir_int1_t *val);
+ lis3de_lir_int1_t *val);
int32_t lis3de_pin_int2_config_set(stmdev_ctx_t *ctx,
- lis3de_ctrl_reg6_t *val);
+ lis3de_ctrl_reg6_t *val);
int32_t lis3de_pin_int2_config_get(stmdev_ctx_t *ctx,
- lis3de_ctrl_reg6_t *val);
+ lis3de_ctrl_reg6_t *val);
int32_t lis3de_fifo_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3de_fifo_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -620,16 +914,18 @@ int32_t lis3de_fifo_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis3de_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3de_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS3DE_INT1_GEN = 0,
LIS3DE_INT2_GEN = 1,
} lis3de_tr_t;
int32_t lis3de_fifo_trigger_event_set(stmdev_ctx_t *ctx,
- lis3de_tr_t val);
+ lis3de_tr_t val);
int32_t lis3de_fifo_trigger_event_get(stmdev_ctx_t *ctx,
- lis3de_tr_t *val);
+ lis3de_tr_t *val);
-typedef enum {
+typedef enum
+{
LIS3DE_BYPASS_MODE = 0,
LIS3DE_FIFO_MODE = 1,
LIS3DE_DYNAMIC_STREAM_MODE = 2,
@@ -639,7 +935,7 @@ int32_t lis3de_fifo_mode_set(stmdev_ctx_t *ctx, lis3de_fm_t val);
int32_t lis3de_fifo_mode_get(stmdev_ctx_t *ctx, lis3de_fm_t *val);
int32_t lis3de_fifo_status_get(stmdev_ctx_t *ctx,
- lis3de_fifo_src_reg_t *val);
+ lis3de_fifo_src_reg_t *val);
int32_t lis3de_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -649,23 +945,26 @@ int32_t lis3de_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis3de_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lis3de_tap_conf_set(stmdev_ctx_t *ctx, lis3de_click_cfg_t *val);
-int32_t lis3de_tap_conf_get(stmdev_ctx_t *ctx, lis3de_click_cfg_t *val);
+int32_t lis3de_tap_conf_set(stmdev_ctx_t *ctx,
+ lis3de_click_cfg_t *val);
+int32_t lis3de_tap_conf_get(stmdev_ctx_t *ctx,
+ lis3de_click_cfg_t *val);
int32_t lis3de_tap_source_get(stmdev_ctx_t *ctx,
- lis3de_click_src_t *val);
+ lis3de_click_src_t *val);
int32_t lis3de_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3de_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS3DE_TAP_PULSED = 0,
LIS3DE_TAP_LATCHED = 1,
} lis3de_lir_t;
int32_t lis3de_tap_notification_mode_set(stmdev_ctx_t *ctx,
- lis3de_lir_t val);
+ lis3de_lir_t val);
int32_t lis3de_tap_notification_mode_get(stmdev_ctx_t *ctx,
- lis3de_lir_t *val);
+ lis3de_lir_t *val);
int32_t lis3de_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3de_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -674,7 +973,8 @@ int32_t lis3de_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3de_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis3de_double_tap_timeout_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis3de_double_tap_timeout_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis3de_double_tap_timeout_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lis3de_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3de_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -682,7 +982,8 @@ int32_t lis3de_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis3de_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3de_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS3DE_SPI_4_WIRE = 0,
LIS3DE_SPI_3_WIRE = 1,
} lis3de_sim_t;
diff --git a/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.c b/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.c
index edb5e1cfcac3b163aab7f3afe4c986194a091586..c2a6ce9140bcddc6d5ae49778d5decfc0d23ac62 100644
--- a/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.c
+++ b/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file lis3dh_reg.c
- * @author Sensors Software Solution Team
- * @brief LIS3DH driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lis3dh_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LIS3DH driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lis3dh_reg.h"
@@ -46,11 +46,13 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3dh_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t lis3dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +66,14 @@ int32_t lis3dh_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3dh_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t lis3dh_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -77,86 +82,86 @@ int32_t lis3dh_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
*
*/
- /**
+/**
* @defgroup LIS3DH_Sensitivity
* @brief These functions convert raw-data into engineering units.
* @{
*
*/
-float lis3dh_from_fs2_hr_to_mg(int16_t lsb)
+float_t lis3dh_from_fs2_hr_to_mg(int16_t lsb)
{
- return ( (float)lsb / 16.0f ) * 1.0f;
+ return ((float_t)lsb / 16.0f) * 1.0f;
}
-float lis3dh_from_fs4_hr_to_mg(int16_t lsb)
+float_t lis3dh_from_fs4_hr_to_mg(int16_t lsb)
{
- return ( (float)lsb / 16.0f ) * 2.0f;
+ return ((float_t)lsb / 16.0f) * 2.0f;
}
-float lis3dh_from_fs8_hr_to_mg(int16_t lsb)
+float_t lis3dh_from_fs8_hr_to_mg(int16_t lsb)
{
- return ( (float)lsb / 16.0f ) * 4.0f;
+ return ((float_t)lsb / 16.0f) * 4.0f;
}
-float lis3dh_from_fs16_hr_to_mg(int16_t lsb)
+float_t lis3dh_from_fs16_hr_to_mg(int16_t lsb)
{
- return ( (float)lsb / 16.0f ) * 12.0f;
+ return ((float_t)lsb / 16.0f) * 12.0f;
}
-float lis3dh_from_lsb_hr_to_celsius(int16_t lsb)
+float_t lis3dh_from_lsb_hr_to_celsius(int16_t lsb)
{
- return ( ( (float)lsb / 64.0f ) / 4.0f ) + 25.0f;
+ return (((float_t)lsb / 64.0f) / 4.0f) + 25.0f;
}
-float lis3dh_from_fs2_nm_to_mg(int16_t lsb)
+float_t lis3dh_from_fs2_nm_to_mg(int16_t lsb)
{
- return ( (float)lsb / 64.0f ) * 4.0f;
+ return ((float_t)lsb / 64.0f) * 4.0f;
}
-float lis3dh_from_fs4_nm_to_mg(int16_t lsb)
+float_t lis3dh_from_fs4_nm_to_mg(int16_t lsb)
{
- return ( (float)lsb / 64.0f ) * 8.0f;
+ return ((float_t)lsb / 64.0f) * 8.0f;
}
-float lis3dh_from_fs8_nm_to_mg(int16_t lsb)
+float_t lis3dh_from_fs8_nm_to_mg(int16_t lsb)
{
- return ( (float)lsb / 64.0f ) * 16.0f;
+ return ((float_t)lsb / 64.0f) * 16.0f;
}
-float lis3dh_from_fs16_nm_to_mg(int16_t lsb)
+float_t lis3dh_from_fs16_nm_to_mg(int16_t lsb)
{
- return ( (float)lsb / 64.0f ) * 48.0f;
+ return ((float_t)lsb / 64.0f) * 48.0f;
}
-float lis3dh_from_lsb_nm_to_celsius(int16_t lsb)
+float_t lis3dh_from_lsb_nm_to_celsius(int16_t lsb)
{
- return ( ( (float)lsb / 64.0f ) / 4.0f ) + 25.0f;
+ return (((float_t)lsb / 64.0f) / 4.0f) + 25.0f;
}
-float lis3dh_from_fs2_lp_to_mg(int16_t lsb)
+float_t lis3dh_from_fs2_lp_to_mg(int16_t lsb)
{
- return ( (float)lsb / 256.0f ) * 16.0f;
+ return ((float_t)lsb / 256.0f) * 16.0f;
}
-float lis3dh_from_fs4_lp_to_mg(int16_t lsb)
+float_t lis3dh_from_fs4_lp_to_mg(int16_t lsb)
{
- return ( (float)lsb / 256.0f ) * 32.0f;
+ return ((float_t)lsb / 256.0f) * 32.0f;
}
-float lis3dh_from_fs8_lp_to_mg(int16_t lsb)
+float_t lis3dh_from_fs8_lp_to_mg(int16_t lsb)
{
- return ( (float)lsb / 256.0f ) * 64.0f;
+ return ((float_t)lsb / 256.0f) * 64.0f;
}
-float lis3dh_from_fs16_lp_to_mg(int16_t lsb)
+float_t lis3dh_from_fs16_lp_to_mg(int16_t lsb)
{
- return ( (float)lsb / 256.0f ) * 192.0f;
+ return ((float_t)lsb / 256.0f) * 192.0f;
}
-float lis3dh_from_lsb_lp_to_celsius(int16_t lsb)
+float_t lis3dh_from_lsb_lp_to_celsius(int16_t lsb)
{
- return ( ( (float)lsb / 256.0f ) * 1.0f ) + 25.0f;
+ return (((float_t)lsb / 256.0f) * 1.0f) + 25.0f;
}
/**
@@ -182,7 +187,9 @@ float lis3dh_from_lsb_lp_to_celsius(int16_t lsb)
int32_t lis3dh_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis3dh_read_reg(ctx, LIS3DH_STATUS_REG_AUX, buff, 1);
+
return ret;
}
/**
@@ -199,7 +206,7 @@ int32_t lis3dh_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lis3dh_read_reg(ctx, LIS3DH_STATUS_REG_AUX,
- (uint8_t*)&status_reg_aux, 1);
+ (uint8_t *)&status_reg_aux, 1);
*val = status_reg_aux._3da;
return ret;
@@ -218,7 +225,7 @@ int32_t lis3dh_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lis3dh_read_reg(ctx, LIS3DH_STATUS_REG_AUX,
- (uint8_t*)&status_reg_aux, 1);
+ (uint8_t *)&status_reg_aux, 1);
*val = status_reg_aux._3or;
return ret;
@@ -231,14 +238,15 @@ int32_t lis3dh_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3dh_temperature_raw_get(stmdev_ctx_t *ctx, uint16_t *buff)
+int32_t lis3dh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
- uint8_t dummy[2];
- ret = lis3dh_read_reg(ctx, LIS3DH_OUT_ADC3_L, dummy, 2);
- *buff = dummy[1];
- *buff = *buff * 256;
- *buff += dummy[0];
+
+ ret = lis3dh_read_reg(ctx, LIS3DH_OUT_ADC3_L, buff, 2);
+ *val = (int16_t)buff[1];
+ *val = (*val * 256) + (int16_t)buff[0];
+
return ret;
}
@@ -262,10 +270,19 @@ int32_t lis3dh_temperature_raw_get(stmdev_ctx_t *ctx, uint16_t *buff)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3dh_adc_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lis3dh_adc_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lis3dh_read_reg(ctx, LIS3DH_OUT_ADC1_L, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -282,19 +299,26 @@ int32_t lis3dh_aux_adc_set(stmdev_ctx_t *ctx, lis3dh_temp_en_t val)
lis3dh_temp_cfg_reg_t temp_cfg_reg;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_TEMP_CFG_REG, (uint8_t*)&temp_cfg_reg, 1);
- if (ret == 0) {
- if (val != LIS3DH_AUX_DISABLE){
+ ret = lis3dh_read_reg(ctx, LIS3DH_TEMP_CFG_REG,
+ (uint8_t *)&temp_cfg_reg, 1);
+
+ if (ret == 0)
+ {
+ if (val != LIS3DH_AUX_DISABLE)
+ {
/* Required in order to use auxiliary adc */
ret = lis3dh_block_data_update_set(ctx, PROPERTY_ENABLE);
}
- }
- if (ret == 0) {
- temp_cfg_reg.temp_en = ( (uint8_t) val & 0x02U) >> 1;
+ }
+
+ if (ret == 0)
+ {
+ temp_cfg_reg.temp_en = ((uint8_t) val & 0x02U) >> 1;
temp_cfg_reg.adc_pd = (uint8_t) val & 0x01U;
ret = lis3dh_write_reg(ctx, LIS3DH_TEMP_CFG_REG,
- (uint8_t*)&temp_cfg_reg, 1);
+ (uint8_t *)&temp_cfg_reg, 1);
}
+
return ret;
}
@@ -311,16 +335,26 @@ int32_t lis3dh_aux_adc_get(stmdev_ctx_t *ctx, lis3dh_temp_en_t *val)
lis3dh_temp_cfg_reg_t temp_cfg_reg;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_TEMP_CFG_REG, (uint8_t*)&temp_cfg_reg, 1);
- if ( ( temp_cfg_reg.temp_en & temp_cfg_reg.adc_pd ) == PROPERTY_ENABLE ){
+ ret = lis3dh_read_reg(ctx, LIS3DH_TEMP_CFG_REG,
+ (uint8_t *)&temp_cfg_reg, 1);
+
+ if ((temp_cfg_reg.temp_en & temp_cfg_reg.adc_pd) ==
+ PROPERTY_ENABLE)
+ {
*val = LIS3DH_AUX_ON_TEMPERATURE;
- }
- if ( ( temp_cfg_reg.temp_en == PROPERTY_DISABLE ) &&
- ( temp_cfg_reg.adc_pd == PROPERTY_ENABLE ) ) {
+ }
+
+ if ((temp_cfg_reg.temp_en == PROPERTY_DISABLE) &&
+ (temp_cfg_reg.adc_pd == PROPERTY_ENABLE))
+ {
*val = LIS3DH_AUX_ON_PADS;
- } else {
+ }
+
+ else
+ {
*val = LIS3DH_AUX_DISABLE;
}
+
return ret;
}
@@ -333,36 +367,50 @@ int32_t lis3dh_aux_adc_get(stmdev_ctx_t *ctx, lis3dh_temp_en_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3dh_operating_mode_set(stmdev_ctx_t *ctx, lis3dh_op_md_t val)
+int32_t lis3dh_operating_mode_set(stmdev_ctx_t *ctx,
+ lis3dh_op_md_t val)
{
lis3dh_ctrl_reg1_t ctrl_reg1;
lis3dh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG1,
- (uint8_t*)&ctrl_reg1, 1);
- if (ret == 0) {
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
- }
- if (ret == 0) {
- if ( val == LIS3DH_HR_12bit ) {
+ (uint8_t *)&ctrl_reg4, 1);
+ }
+
+ if (ret == 0)
+ {
+ if (val == LIS3DH_HR_12bit)
+ {
ctrl_reg1.lpen = 0;
ctrl_reg4.hr = 1;
}
- if (val == LIS3DH_NM_10bit) {
+
+ if (val == LIS3DH_NM_10bit)
+ {
ctrl_reg1.lpen = 0;
ctrl_reg4.hr = 0;
}
- if (val == LIS3DH_LP_8bit) {
+
+ if (val == LIS3DH_LP_8bit)
+ {
ctrl_reg1.lpen = 1;
ctrl_reg4.hr = 0;
}
- ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- }
- if (ret == 0) {
- ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+
+ ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
}
+
+ if (ret == 0)
+ {
+ ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+ }
+
return ret;
}
@@ -374,23 +422,35 @@ int32_t lis3dh_operating_mode_set(stmdev_ctx_t *ctx, lis3dh_op_md_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3dh_operating_mode_get(stmdev_ctx_t *ctx, lis3dh_op_md_t *val)
+int32_t lis3dh_operating_mode_get(stmdev_ctx_t *ctx,
+ lis3dh_op_md_t *val)
{
lis3dh_ctrl_reg1_t ctrl_reg1;
lis3dh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if (ret == 0) {
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if ( ctrl_reg1.lpen == PROPERTY_ENABLE ) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ if (ctrl_reg1.lpen == PROPERTY_ENABLE)
+ {
*val = LIS3DH_LP_8bit;
- } else if (ctrl_reg4.hr == PROPERTY_ENABLE ) {
+ }
+
+ else if (ctrl_reg4.hr == PROPERTY_ENABLE)
+ {
*val = LIS3DH_HR_12bit;
- } else {
+ }
+
+ else
+ {
*val = LIS3DH_NM_10bit;
}
}
+
return ret;
}
@@ -407,11 +467,14 @@ int32_t lis3dh_data_rate_set(stmdev_ctx_t *ctx, lis3dh_odr_t val)
lis3dh_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if (ret == 0) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.odr = (uint8_t)val;
- ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -428,42 +491,55 @@ int32_t lis3dh_data_rate_get(stmdev_ctx_t *ctx, lis3dh_odr_t *val)
lis3dh_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- switch (ctrl_reg1.odr) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ switch (ctrl_reg1.odr)
+ {
case LIS3DH_POWER_DOWN:
*val = LIS3DH_POWER_DOWN;
break;
+
case LIS3DH_ODR_1Hz:
*val = LIS3DH_ODR_1Hz;
break;
+
case LIS3DH_ODR_10Hz:
*val = LIS3DH_ODR_10Hz;
break;
+
case LIS3DH_ODR_25Hz:
*val = LIS3DH_ODR_25Hz;
break;
+
case LIS3DH_ODR_50Hz:
*val = LIS3DH_ODR_50Hz;
break;
+
case LIS3DH_ODR_100Hz:
*val = LIS3DH_ODR_100Hz;
break;
+
case LIS3DH_ODR_200Hz:
*val = LIS3DH_ODR_200Hz;
break;
+
case LIS3DH_ODR_400Hz:
*val = LIS3DH_ODR_400Hz;
break;
+
case LIS3DH_ODR_1kHz620_LP:
*val = LIS3DH_ODR_1kHz620_LP;
break;
+
case LIS3DH_ODR_5kHz376_LP_1kHz344_NM_HP:
*val = LIS3DH_ODR_5kHz376_LP_1kHz344_NM_HP;
break;
+
default:
*val = LIS3DH_POWER_DOWN;
break;
}
+
return ret;
}
@@ -476,16 +552,20 @@ int32_t lis3dh_data_rate_get(stmdev_ctx_t *ctx, lis3dh_odr_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3dh_high_pass_on_outputs_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lis3dh_high_pass_on_outputs_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lis3dh_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if (ret == 0) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.fds = val;
- ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -498,12 +578,13 @@ int32_t lis3dh_high_pass_on_outputs_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3dh_high_pass_on_outputs_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis3dh_high_pass_on_outputs_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis3dh_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
*val = (uint8_t)ctrl_reg2.fds;
return ret;
@@ -524,16 +605,19 @@ int32_t lis3dh_high_pass_on_outputs_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lis3dh_high_pass_bandwidth_set(stmdev_ctx_t *ctx,
- lis3dh_hpcf_t val)
+ lis3dh_hpcf_t val)
{
lis3dh_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if (ret == 0) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpcf = (uint8_t)val;
- ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -552,29 +636,36 @@ int32_t lis3dh_high_pass_bandwidth_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis3dh_high_pass_bandwidth_get(stmdev_ctx_t *ctx,
- lis3dh_hpcf_t *val)
+ lis3dh_hpcf_t *val)
{
lis3dh_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- switch (ctrl_reg2.hpcf) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ switch (ctrl_reg2.hpcf)
+ {
case LIS3DH_AGGRESSIVE:
*val = LIS3DH_AGGRESSIVE;
break;
+
case LIS3DH_STRONG:
*val = LIS3DH_STRONG;
break;
+
case LIS3DH_MEDIUM:
*val = LIS3DH_MEDIUM;
break;
+
case LIS3DH_LIGHT:
*val = LIS3DH_LIGHT;
break;
+
default:
*val = LIS3DH_LIGHT;
break;
}
+
return ret;
}
@@ -591,11 +682,14 @@ int32_t lis3dh_high_pass_mode_set(stmdev_ctx_t *ctx, lis3dh_hpm_t val)
lis3dh_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if (ret == 0) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hpm = (uint8_t)val;
- ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -607,29 +701,37 @@ int32_t lis3dh_high_pass_mode_set(stmdev_ctx_t *ctx, lis3dh_hpm_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3dh_high_pass_mode_get(stmdev_ctx_t *ctx, lis3dh_hpm_t *val)
+int32_t lis3dh_high_pass_mode_get(stmdev_ctx_t *ctx,
+ lis3dh_hpm_t *val)
{
lis3dh_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- switch (ctrl_reg2.hpm) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ switch (ctrl_reg2.hpm)
+ {
case LIS3DH_NORMAL_WITH_RST:
*val = LIS3DH_NORMAL_WITH_RST;
break;
+
case LIS3DH_REFERENCE_MODE:
*val = LIS3DH_REFERENCE_MODE;
break;
+
case LIS3DH_NORMAL:
*val = LIS3DH_NORMAL;
break;
+
case LIS3DH_AUTORST_ON_INT:
*val = LIS3DH_AUTORST_ON_INT;
break;
+
default:
*val = LIS3DH_NORMAL_WITH_RST;
break;
}
+
return ret;
}
@@ -646,11 +748,14 @@ int32_t lis3dh_full_scale_set(stmdev_ctx_t *ctx, lis3dh_fs_t val)
lis3dh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if (ret == 0) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.fs = (uint8_t)val;
- ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -667,24 +772,31 @@ int32_t lis3dh_full_scale_get(stmdev_ctx_t *ctx, lis3dh_fs_t *val)
lis3dh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- switch (ctrl_reg4.fs) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ switch (ctrl_reg4.fs)
+ {
case LIS3DH_2g:
*val = LIS3DH_2g;
break;
+
case LIS3DH_4g:
*val = LIS3DH_4g;
break;
+
case LIS3DH_8g:
*val = LIS3DH_8g;
break;
+
case LIS3DH_16g:
*val = LIS3DH_16g;
break;
+
default:
*val = LIS3DH_2g;
break;
}
+
return ret;
}
@@ -701,11 +813,14 @@ int32_t lis3dh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
lis3dh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if (ret == 0) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.bdu = val;
- ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -722,7 +837,7 @@ int32_t lis3dh_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
*val = (uint8_t)ctrl_reg4.bdu;
return ret;
@@ -740,7 +855,9 @@ int32_t lis3dh_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t lis3dh_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis3dh_write_reg(ctx, LIS3DH_REFERENCE, buff, 1);
+
return ret;
}
@@ -756,7 +873,9 @@ int32_t lis3dh_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lis3dh_filter_reference_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis3dh_read_reg(ctx, LIS3DH_REFERENCE, buff, 1);
+
return ret;
}
/**
@@ -772,7 +891,7 @@ int32_t lis3dh_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dh_status_reg_t status_reg;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_STATUS_REG, (uint8_t*)&status_reg, 1);
+ ret = lis3dh_read_reg(ctx, LIS3DH_STATUS_REG, (uint8_t *)&status_reg, 1);
*val = status_reg.zyxda;
return ret;
@@ -790,7 +909,7 @@ int32_t lis3dh_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dh_status_reg_t status_reg;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_STATUS_REG, (uint8_t*)&status_reg, 1);
+ ret = lis3dh_read_reg(ctx, LIS3DH_STATUS_REG, (uint8_t *)&status_reg, 1);
*val = status_reg.zyxor;
return ret;
@@ -803,10 +922,19 @@ int32_t lis3dh_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3dh_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lis3dh_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lis3dh_read_reg(ctx, LIS3DH_OUT_X_L, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
/**
@@ -816,7 +944,7 @@ int32_t lis3dh_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
/**
* @defgroup LIS3DH_Common
- * @brief This section group common usefull functions
+ * @brief This section group common useful functions
* @{
*
*/
@@ -832,7 +960,9 @@ int32_t lis3dh_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lis3dh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis3dh_read_reg(ctx, LIS3DH_WHO_AM_I, buff, 1);
+
return ret;
}
/**
@@ -848,11 +978,14 @@ int32_t lis3dh_self_test_set(stmdev_ctx_t *ctx, lis3dh_st_t val)
lis3dh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if (ret == 0) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.st = (uint8_t)val;
- ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -869,21 +1002,27 @@ int32_t lis3dh_self_test_get(stmdev_ctx_t *ctx, lis3dh_st_t *val)
lis3dh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- switch (ctrl_reg4.st) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ switch (ctrl_reg4.st)
+ {
case LIS3DH_ST_DISABLE:
*val = LIS3DH_ST_DISABLE;
break;
+
case LIS3DH_ST_POSITIVE:
*val = LIS3DH_ST_POSITIVE;
break;
+
case LIS3DH_ST_NEGATIVE:
*val = LIS3DH_ST_NEGATIVE;
break;
+
default:
*val = LIS3DH_ST_DISABLE;
break;
}
+
return ret;
}
@@ -900,11 +1039,14 @@ int32_t lis3dh_data_format_set(stmdev_ctx_t *ctx, lis3dh_ble_t val)
lis3dh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if (ret == 0) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.ble = (uint8_t)val;
- ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -921,18 +1063,23 @@ int32_t lis3dh_data_format_get(stmdev_ctx_t *ctx, lis3dh_ble_t *val)
lis3dh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- switch (ctrl_reg4.ble) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ switch (ctrl_reg4.ble)
+ {
case LIS3DH_LSB_AT_LOW_ADD:
*val = LIS3DH_LSB_AT_LOW_ADD;
break;
+
case LIS3DH_MSB_AT_LOW_ADD:
*val = LIS3DH_MSB_AT_LOW_ADD;
break;
+
default:
*val = LIS3DH_LSB_AT_LOW_ADD;
break;
}
+
return ret;
}
@@ -949,11 +1096,14 @@ int32_t lis3dh_boot_set(stmdev_ctx_t *ctx, uint8_t val)
lis3dh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.boot = val;
- ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -970,7 +1120,7 @@ int32_t lis3dh_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
*val = (uint8_t)ctrl_reg5.boot;
return ret;
@@ -987,7 +1137,9 @@ int32_t lis3dh_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t lis3dh_status_get(stmdev_ctx_t *ctx, lis3dh_status_reg_t *val)
{
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_STATUS_REG, (uint8_t*) val, 1);
+
+ ret = lis3dh_read_reg(ctx, LIS3DH_STATUS_REG, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1012,10 +1164,12 @@ int32_t lis3dh_status_get(stmdev_ctx_t *ctx, lis3dh_status_reg_t *val)
*
*/
int32_t lis3dh_int1_gen_conf_set(stmdev_ctx_t *ctx,
- lis3dh_int1_cfg_t *val)
+ lis3dh_int1_cfg_t *val)
{
int32_t ret;
- ret = lis3dh_write_reg(ctx, LIS3DH_INT1_CFG, (uint8_t*) val, 1);
+
+ ret = lis3dh_write_reg(ctx, LIS3DH_INT1_CFG, (uint8_t *) val, 1);
+
return ret;
}
@@ -1028,10 +1182,12 @@ int32_t lis3dh_int1_gen_conf_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis3dh_int1_gen_conf_get(stmdev_ctx_t *ctx,
- lis3dh_int1_cfg_t *val)
+ lis3dh_int1_cfg_t *val)
{
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_INT1_CFG, (uint8_t*) val, 1);
+
+ ret = lis3dh_read_reg(ctx, LIS3DH_INT1_CFG, (uint8_t *) val, 1);
+
return ret;
}
@@ -1044,10 +1200,12 @@ int32_t lis3dh_int1_gen_conf_get(stmdev_ctx_t *ctx,
*
*/
int32_t lis3dh_int1_gen_source_get(stmdev_ctx_t *ctx,
- lis3dh_int1_src_t *val)
+ lis3dh_int1_src_t *val)
{
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_INT1_SRC, (uint8_t*) val, 1);
+
+ ret = lis3dh_read_reg(ctx, LIS3DH_INT1_SRC, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1065,11 +1223,14 @@ int32_t lis3dh_int1_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
lis3dh_int1_ths_t int1_ths;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_INT1_THS, (uint8_t*)&int1_ths, 1);
- if (ret == 0) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_INT1_THS, (uint8_t *)&int1_ths, 1);
+
+ if (ret == 0)
+ {
int1_ths.ths = val;
- ret = lis3dh_write_reg(ctx, LIS3DH_INT1_THS, (uint8_t*)&int1_ths, 1);
+ ret = lis3dh_write_reg(ctx, LIS3DH_INT1_THS, (uint8_t *)&int1_ths, 1);
}
+
return ret;
}
@@ -1088,7 +1249,7 @@ int32_t lis3dh_int1_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dh_int1_ths_t int1_ths;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_INT1_THS, (uint8_t*)&int1_ths, 1);
+ ret = lis3dh_read_reg(ctx, LIS3DH_INT1_THS, (uint8_t *)&int1_ths, 1);
*val = (uint8_t)int1_ths.ths;
return ret;
@@ -1108,11 +1269,16 @@ int32_t lis3dh_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val)
lis3dh_int1_duration_t int1_duration;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_INT1_DURATION, (uint8_t*)&int1_duration, 1);
- if (ret == 0) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_INT1_DURATION,
+ (uint8_t *)&int1_duration, 1);
+
+ if (ret == 0)
+ {
int1_duration.d = val;
- ret = lis3dh_write_reg(ctx, LIS3DH_INT1_DURATION, (uint8_t*)&int1_duration, 1);
+ ret = lis3dh_write_reg(ctx, LIS3DH_INT1_DURATION,
+ (uint8_t *)&int1_duration, 1);
}
+
return ret;
}
@@ -1130,7 +1296,8 @@ int32_t lis3dh_int1_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dh_int1_duration_t int1_duration;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_INT1_DURATION, (uint8_t*)&int1_duration, 1);
+ ret = lis3dh_read_reg(ctx, LIS3DH_INT1_DURATION,
+ (uint8_t *)&int1_duration, 1);
*val = (uint8_t)int1_duration.d;
return ret;
@@ -1158,10 +1325,12 @@ int32_t lis3dh_int1_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lis3dh_int2_gen_conf_set(stmdev_ctx_t *ctx,
- lis3dh_int2_cfg_t *val)
+ lis3dh_int2_cfg_t *val)
{
int32_t ret;
- ret = lis3dh_write_reg(ctx, LIS3DH_INT2_CFG, (uint8_t*) val, 1);
+
+ ret = lis3dh_write_reg(ctx, LIS3DH_INT2_CFG, (uint8_t *) val, 1);
+
return ret;
}
@@ -1174,10 +1343,12 @@ int32_t lis3dh_int2_gen_conf_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis3dh_int2_gen_conf_get(stmdev_ctx_t *ctx,
- lis3dh_int2_cfg_t *val)
+ lis3dh_int2_cfg_t *val)
{
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_INT2_CFG, (uint8_t*) val, 1);
+
+ ret = lis3dh_read_reg(ctx, LIS3DH_INT2_CFG, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1189,10 +1360,12 @@ int32_t lis3dh_int2_gen_conf_get(stmdev_ctx_t *ctx,
*
*/
int32_t lis3dh_int2_gen_source_get(stmdev_ctx_t *ctx,
- lis3dh_int2_src_t *val)
+ lis3dh_int2_src_t *val)
{
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_INT2_SRC, (uint8_t*) val, 1);
+
+ ret = lis3dh_read_reg(ctx, LIS3DH_INT2_SRC, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1210,11 +1383,14 @@ int32_t lis3dh_int2_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
lis3dh_int2_ths_t int2_ths;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_INT2_THS, (uint8_t*)&int2_ths, 1);
- if (ret == 0) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_INT2_THS, (uint8_t *)&int2_ths, 1);
+
+ if (ret == 0)
+ {
int2_ths.ths = val;
- ret = lis3dh_write_reg(ctx, LIS3DH_INT2_THS, (uint8_t*)&int2_ths, 1);
+ ret = lis3dh_write_reg(ctx, LIS3DH_INT2_THS, (uint8_t *)&int2_ths, 1);
}
+
return ret;
}
@@ -1233,7 +1409,7 @@ int32_t lis3dh_int2_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dh_int2_ths_t int2_ths;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_INT2_THS, (uint8_t*)&int2_ths, 1);
+ ret = lis3dh_read_reg(ctx, LIS3DH_INT2_THS, (uint8_t *)&int2_ths, 1);
*val = (uint8_t)int2_ths.ths;
return ret;
@@ -1253,11 +1429,16 @@ int32_t lis3dh_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val)
lis3dh_int2_duration_t int2_duration;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_INT2_DURATION, (uint8_t*)&int2_duration, 1);
- if (ret == 0) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_INT2_DURATION,
+ (uint8_t *)&int2_duration, 1);
+
+ if (ret == 0)
+ {
int2_duration.d = val;
- ret = lis3dh_write_reg(ctx, LIS3DH_INT2_DURATION, (uint8_t*)&int2_duration, 1);
+ ret = lis3dh_write_reg(ctx, LIS3DH_INT2_DURATION,
+ (uint8_t *)&int2_duration, 1);
}
+
return ret;
}
@@ -1275,7 +1456,8 @@ int32_t lis3dh_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dh_int2_duration_t int2_duration;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_INT2_DURATION, (uint8_t*)&int2_duration, 1);
+ ret = lis3dh_read_reg(ctx, LIS3DH_INT2_DURATION,
+ (uint8_t *)&int2_duration, 1);
*val = (uint8_t)int2_duration.d;
return ret;
@@ -1288,7 +1470,7 @@ int32_t lis3dh_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @defgroup LIS3DH_Interrupt_pins
- * @brief This section group all the functions that manage interrup pins
+ * @brief This section group all the functions that manage interrupt pins
* @{
*
*/
@@ -1302,16 +1484,19 @@ int32_t lis3dh_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lis3dh_high_pass_int_conf_set(stmdev_ctx_t *ctx,
- lis3dh_hp_t val)
+ lis3dh_hp_t val)
{
lis3dh_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if (ret == 0) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.hp = (uint8_t)val;
- ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -1324,41 +1509,52 @@ int32_t lis3dh_high_pass_int_conf_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis3dh_high_pass_int_conf_get(stmdev_ctx_t *ctx,
- lis3dh_hp_t *val)
+ lis3dh_hp_t *val)
{
lis3dh_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- switch (ctrl_reg2.hp) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ switch (ctrl_reg2.hp)
+ {
case LIS3DH_DISC_FROM_INT_GENERATOR:
*val = LIS3DH_DISC_FROM_INT_GENERATOR;
break;
+
case LIS3DH_ON_INT1_GEN:
*val = LIS3DH_ON_INT1_GEN;
break;
+
case LIS3DH_ON_INT2_GEN:
*val = LIS3DH_ON_INT2_GEN;
break;
+
case LIS3DH_ON_TAP_GEN:
*val = LIS3DH_ON_TAP_GEN;
break;
+
case LIS3DH_ON_INT1_INT2_GEN:
*val = LIS3DH_ON_INT1_INT2_GEN;
break;
+
case LIS3DH_ON_INT1_TAP_GEN:
*val = LIS3DH_ON_INT1_TAP_GEN;
break;
+
case LIS3DH_ON_INT2_TAP_GEN:
*val = LIS3DH_ON_INT2_TAP_GEN;
break;
+
case LIS3DH_ON_INT1_INT2_TAP_GEN:
*val = LIS3DH_ON_INT1_INT2_TAP_GEN;
break;
+
default:
*val = LIS3DH_DISC_FROM_INT_GENERATOR;
break;
}
+
return ret;
}
@@ -1371,10 +1567,12 @@ int32_t lis3dh_high_pass_int_conf_get(stmdev_ctx_t *ctx,
*
*/
int32_t lis3dh_pin_int1_config_set(stmdev_ctx_t *ctx,
- lis3dh_ctrl_reg3_t *val)
+ lis3dh_ctrl_reg3_t *val)
{
int32_t ret;
- ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG3, (uint8_t*) val, 1);
+
+ ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG3, (uint8_t *) val, 1);
+
return ret;
}
@@ -1387,10 +1585,12 @@ int32_t lis3dh_pin_int1_config_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis3dh_pin_int1_config_get(stmdev_ctx_t *ctx,
- lis3dh_ctrl_reg3_t *val)
+ lis3dh_ctrl_reg3_t *val)
{
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG3, (uint8_t*) val, 1);
+
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG3, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1408,11 +1608,14 @@ int32_t lis3dh_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val)
lis3dh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.d4d_int2 = val;
- ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -1430,7 +1633,7 @@ int32_t lis3dh_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
*val = (uint8_t)ctrl_reg5.d4d_int2;
return ret;
@@ -1447,16 +1650,19 @@ int32_t lis3dh_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lis3dh_int2_pin_notification_mode_set(stmdev_ctx_t *ctx,
- lis3dh_lir_int2_t val)
+ lis3dh_lir_int2_t val)
{
lis3dh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.lir_int2 = (uint8_t)val;
- ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -1471,23 +1677,28 @@ int32_t lis3dh_int2_pin_notification_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis3dh_int2_pin_notification_mode_get(stmdev_ctx_t *ctx,
- lis3dh_lir_int2_t *val)
+ lis3dh_lir_int2_t *val)
{
lis3dh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- switch (ctrl_reg5.lir_int2) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
+
+ switch (ctrl_reg5.lir_int2)
+ {
case LIS3DH_INT2_PULSED:
*val = LIS3DH_INT2_PULSED;
break;
+
case LIS3DH_INT2_LATCHED:
*val = LIS3DH_INT2_LATCHED;
break;
+
default:
*val = LIS3DH_INT2_PULSED;
break;
}
+
return ret;
}
@@ -1505,11 +1716,14 @@ int32_t lis3dh_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val)
lis3dh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.d4d_int1 = val;
- ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -1527,7 +1741,7 @@ int32_t lis3dh_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
*val = (uint8_t)ctrl_reg5.d4d_int1;
return ret;
@@ -1543,16 +1757,19 @@ int32_t lis3dh_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lis3dh_int1_pin_notification_mode_set(stmdev_ctx_t *ctx,
- lis3dh_lir_int1_t val)
+ lis3dh_lir_int1_t val)
{
lis3dh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.lir_int1 = (uint8_t)val;
- ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -1566,23 +1783,28 @@ int32_t lis3dh_int1_pin_notification_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis3dh_int1_pin_notification_mode_get(stmdev_ctx_t *ctx,
- lis3dh_lir_int1_t *val)
+ lis3dh_lir_int1_t *val)
{
lis3dh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- switch (ctrl_reg5.lir_int1) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
+
+ switch (ctrl_reg5.lir_int1)
+ {
case LIS3DH_INT1_PULSED:
*val = LIS3DH_INT1_PULSED;
break;
+
case LIS3DH_INT1_LATCHED:
*val = LIS3DH_INT1_LATCHED;
break;
+
default:
*val = LIS3DH_INT1_PULSED;
break;
}
+
return ret;
}
@@ -1595,10 +1817,12 @@ int32_t lis3dh_int1_pin_notification_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t lis3dh_pin_int2_config_set(stmdev_ctx_t *ctx,
- lis3dh_ctrl_reg6_t *val)
+ lis3dh_ctrl_reg6_t *val)
{
int32_t ret;
- ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG6, (uint8_t*) val, 1);
+
+ ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG6, (uint8_t *) val, 1);
+
return ret;
}
@@ -1611,10 +1835,12 @@ int32_t lis3dh_pin_int2_config_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis3dh_pin_int2_config_get(stmdev_ctx_t *ctx,
- lis3dh_ctrl_reg6_t *val)
+ lis3dh_ctrl_reg6_t *val)
{
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG6, (uint8_t*) val, 1);
+
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG6, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1642,11 +1868,14 @@ int32_t lis3dh_fifo_set(stmdev_ctx_t *ctx, uint8_t val)
lis3dh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.fifo_en = val;
- ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -1663,7 +1892,7 @@ int32_t lis3dh_fifo_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
*val = (uint8_t)ctrl_reg5.fifo_en;
return ret;
@@ -1682,11 +1911,16 @@ int32_t lis3dh_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
- if (ret == 0) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl_reg.fth = val;
- ret = lis3dh_write_reg(ctx, LIS3DH_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
+ ret = lis3dh_write_reg(ctx, LIS3DH_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
}
+
return ret;
}
@@ -1703,7 +1937,8 @@ int32_t lis3dh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
+ ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
*val = (uint8_t)fifo_ctrl_reg.fth;
return ret;
@@ -1718,16 +1953,21 @@ int32_t lis3dh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lis3dh_fifo_trigger_event_set(stmdev_ctx_t *ctx,
- lis3dh_tr_t val)
+ lis3dh_tr_t val)
{
lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
- if (ret == 0) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl_reg.tr = (uint8_t)val;
- ret = lis3dh_write_reg(ctx, LIS3DH_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
+ ret = lis3dh_write_reg(ctx, LIS3DH_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
}
+
return ret;
}
@@ -1740,23 +1980,29 @@ int32_t lis3dh_fifo_trigger_event_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis3dh_fifo_trigger_event_get(stmdev_ctx_t *ctx,
- lis3dh_tr_t *val)
+ lis3dh_tr_t *val)
{
lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
- switch (fifo_ctrl_reg.tr) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
+
+ switch (fifo_ctrl_reg.tr)
+ {
case LIS3DH_INT1_GEN:
*val = LIS3DH_INT1_GEN;
break;
+
case LIS3DH_INT2_GEN:
*val = LIS3DH_INT2_GEN;
break;
+
default:
*val = LIS3DH_INT1_GEN;
break;
}
+
return ret;
}
@@ -1773,11 +2019,16 @@ int32_t lis3dh_fifo_mode_set(stmdev_ctx_t *ctx, lis3dh_fm_t val)
lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
- if (ret == 0) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl_reg.fm = (uint8_t)val;
- ret = lis3dh_write_reg(ctx, LIS3DH_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
+ ret = lis3dh_write_reg(ctx, LIS3DH_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
}
+
return ret;
}
@@ -1794,24 +2045,32 @@ int32_t lis3dh_fifo_mode_get(stmdev_ctx_t *ctx, lis3dh_fm_t *val)
lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
- switch (fifo_ctrl_reg.fm) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG,
+ (uint8_t *)&fifo_ctrl_reg, 1);
+
+ switch (fifo_ctrl_reg.fm)
+ {
case LIS3DH_BYPASS_MODE:
*val = LIS3DH_BYPASS_MODE;
break;
+
case LIS3DH_FIFO_MODE:
*val = LIS3DH_FIFO_MODE;
break;
+
case LIS3DH_DYNAMIC_STREAM_MODE:
*val = LIS3DH_DYNAMIC_STREAM_MODE;
break;
+
case LIS3DH_STREAM_TO_FIFO_MODE:
*val = LIS3DH_STREAM_TO_FIFO_MODE;
break;
+
default:
*val = LIS3DH_BYPASS_MODE;
break;
}
+
return ret;
}
@@ -1824,10 +2083,12 @@ int32_t lis3dh_fifo_mode_get(stmdev_ctx_t *ctx, lis3dh_fm_t *val)
*
*/
int32_t lis3dh_fifo_status_get(stmdev_ctx_t *ctx,
- lis3dh_fifo_src_reg_t *val)
+ lis3dh_fifo_src_reg_t *val)
{
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_SRC_REG, (uint8_t*) val, 1);
+
+ ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_SRC_REG, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1843,7 +2104,8 @@ int32_t lis3dh_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dh_fifo_src_reg_t fifo_src_reg;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1);
+ ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_SRC_REG,
+ (uint8_t *)&fifo_src_reg, 1);
*val = (uint8_t)fifo_src_reg.fss;
return ret;
@@ -1861,7 +2123,8 @@ int32_t lis3dh_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dh_fifo_src_reg_t fifo_src_reg;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1);
+ ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_SRC_REG,
+ (uint8_t *)&fifo_src_reg, 1);
*val = (uint8_t)fifo_src_reg.empty;
return ret;
@@ -1879,7 +2142,8 @@ int32_t lis3dh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dh_fifo_src_reg_t fifo_src_reg;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1);
+ ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_SRC_REG,
+ (uint8_t *)&fifo_src_reg, 1);
*val = (uint8_t)fifo_src_reg.ovrn_fifo;
return ret;
@@ -1897,7 +2161,8 @@ int32_t lis3dh_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dh_fifo_src_reg_t fifo_src_reg;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1);
+ ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_SRC_REG,
+ (uint8_t *)&fifo_src_reg, 1);
*val = (uint8_t)fifo_src_reg.wtm;
return ret;
@@ -1923,10 +2188,13 @@ int32_t lis3dh_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3dh_tap_conf_set(stmdev_ctx_t *ctx, lis3dh_click_cfg_t *val)
+int32_t lis3dh_tap_conf_set(stmdev_ctx_t *ctx,
+ lis3dh_click_cfg_t *val)
{
int32_t ret;
- ret = lis3dh_write_reg(ctx, LIS3DH_CLICK_CFG, (uint8_t*) val, 1);
+
+ ret = lis3dh_write_reg(ctx, LIS3DH_CLICK_CFG, (uint8_t *) val, 1);
+
return ret;
}
@@ -1938,10 +2206,13 @@ int32_t lis3dh_tap_conf_set(stmdev_ctx_t *ctx, lis3dh_click_cfg_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3dh_tap_conf_get(stmdev_ctx_t *ctx, lis3dh_click_cfg_t *val)
+int32_t lis3dh_tap_conf_get(stmdev_ctx_t *ctx,
+ lis3dh_click_cfg_t *val)
{
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_CFG, (uint8_t*) val, 1);
+
+ ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_CFG, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1952,10 +2223,13 @@ int32_t lis3dh_tap_conf_get(stmdev_ctx_t *ctx, lis3dh_click_cfg_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3dh_tap_source_get(stmdev_ctx_t *ctx, lis3dh_click_src_t *val)
+int32_t lis3dh_tap_source_get(stmdev_ctx_t *ctx,
+ lis3dh_click_src_t *val)
{
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_SRC, (uint8_t*) val, 1);
+
+ ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_SRC, (uint8_t *) val, 1);
+
return ret;
}
/**
@@ -1972,11 +2246,14 @@ int32_t lis3dh_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
lis3dh_click_ths_t click_ths;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_THS, (uint8_t*)&click_ths, 1);
- if (ret == 0) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_THS, (uint8_t *)&click_ths, 1);
+
+ if (ret == 0)
+ {
click_ths.ths = val;
- ret = lis3dh_write_reg(ctx, LIS3DH_CLICK_THS, (uint8_t*)&click_ths, 1);
+ ret = lis3dh_write_reg(ctx, LIS3DH_CLICK_THS, (uint8_t *)&click_ths, 1);
}
+
return ret;
}
@@ -1994,7 +2271,7 @@ int32_t lis3dh_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dh_click_ths_t click_ths;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_THS, (uint8_t*)&click_ths, 1);
+ ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_THS, (uint8_t *)&click_ths, 1);
*val = (uint8_t)click_ths.ths;
return ret;
@@ -2012,16 +2289,19 @@ int32_t lis3dh_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lis3dh_tap_notification_mode_set(stmdev_ctx_t *ctx,
- lis3dh_lir_click_t val)
+ lis3dh_lir_click_t val)
{
lis3dh_click_ths_t click_ths;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_THS, (uint8_t*)&click_ths, 1);
- if (ret == 0) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_THS, (uint8_t *)&click_ths, 1);
+
+ if (ret == 0)
+ {
click_ths.lir_click = (uint8_t)val;
- ret = lis3dh_write_reg(ctx, LIS3DH_CLICK_THS, (uint8_t*)&click_ths, 1);
+ ret = lis3dh_write_reg(ctx, LIS3DH_CLICK_THS, (uint8_t *)&click_ths, 1);
}
+
return ret;
}
@@ -2037,23 +2317,28 @@ int32_t lis3dh_tap_notification_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis3dh_tap_notification_mode_get(stmdev_ctx_t *ctx,
- lis3dh_lir_click_t *val)
+ lis3dh_lir_click_t *val)
{
lis3dh_click_ths_t click_ths;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_THS, (uint8_t*)&click_ths, 1);
- switch (click_ths.lir_click) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_THS, (uint8_t *)&click_ths, 1);
+
+ switch (click_ths.lir_click)
+ {
case LIS3DH_TAP_PULSED:
*val = LIS3DH_TAP_PULSED;
break;
+
case LIS3DH_TAP_LATCHED:
*val = LIS3DH_TAP_LATCHED;
break;
+
default:
*val = LIS3DH_TAP_PULSED;
break;
}
+
return ret;
}
@@ -2072,11 +2357,14 @@ int32_t lis3dh_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lis3dh_time_limit_t time_limit;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_TIME_LIMIT, (uint8_t*)&time_limit, 1);
- if (ret == 0) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_TIME_LIMIT, (uint8_t *)&time_limit, 1);
+
+ if (ret == 0)
+ {
time_limit.tli = val;
- ret = lis3dh_write_reg(ctx, LIS3DH_TIME_LIMIT, (uint8_t*)&time_limit, 1);
+ ret = lis3dh_write_reg(ctx, LIS3DH_TIME_LIMIT, (uint8_t *)&time_limit, 1);
}
+
return ret;
}
@@ -2095,7 +2383,7 @@ int32_t lis3dh_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dh_time_limit_t time_limit;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_TIME_LIMIT, (uint8_t*)&time_limit, 1);
+ ret = lis3dh_read_reg(ctx, LIS3DH_TIME_LIMIT, (uint8_t *)&time_limit, 1);
*val = (uint8_t)time_limit.tli;
return ret;
@@ -2117,11 +2405,16 @@ int32_t lis3dh_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lis3dh_time_latency_t time_latency;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_TIME_LATENCY, (uint8_t*)&time_latency, 1);
- if (ret == 0) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_TIME_LATENCY,
+ (uint8_t *)&time_latency, 1);
+
+ if (ret == 0)
+ {
time_latency.tla = val;
- ret = lis3dh_write_reg(ctx, LIS3DH_TIME_LATENCY, (uint8_t*)&time_latency, 1);
+ ret = lis3dh_write_reg(ctx, LIS3DH_TIME_LATENCY,
+ (uint8_t *)&time_latency, 1);
}
+
return ret;
}
@@ -2141,7 +2434,8 @@ int32_t lis3dh_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dh_time_latency_t time_latency;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_TIME_LATENCY, (uint8_t*)&time_latency, 1);
+ ret = lis3dh_read_reg(ctx, LIS3DH_TIME_LATENCY,
+ (uint8_t *)&time_latency, 1);
*val = (uint8_t)time_latency.tla;
return ret;
@@ -2163,11 +2457,16 @@ int32_t lis3dh_double_tap_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
lis3dh_time_window_t time_window;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_TIME_WINDOW, (uint8_t*)&time_window, 1);
- if (ret == 0) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_TIME_WINDOW,
+ (uint8_t *)&time_window, 1);
+
+ if (ret == 0)
+ {
time_window.tw = val;
- ret = lis3dh_write_reg(ctx, LIS3DH_TIME_WINDOW, (uint8_t*)&time_window, 1);
+ ret = lis3dh_write_reg(ctx, LIS3DH_TIME_WINDOW,
+ (uint8_t *)&time_window, 1);
}
+
return ret;
}
@@ -2187,7 +2486,8 @@ int32_t lis3dh_double_tap_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dh_time_window_t time_window;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_TIME_WINDOW, (uint8_t*)&time_window, 1);
+ ret = lis3dh_read_reg(ctx, LIS3DH_TIME_WINDOW,
+ (uint8_t *)&time_window, 1);
*val = (uint8_t)time_window.tw;
return ret;
@@ -2221,11 +2521,14 @@ int32_t lis3dh_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
lis3dh_act_ths_t act_ths;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_ACT_THS, (uint8_t*)&act_ths, 1);
- if (ret == 0) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_ACT_THS, (uint8_t *)&act_ths, 1);
+
+ if (ret == 0)
+ {
act_ths.acth = val;
- ret = lis3dh_write_reg(ctx, LIS3DH_ACT_THS, (uint8_t*)&act_ths, 1);
+ ret = lis3dh_write_reg(ctx, LIS3DH_ACT_THS, (uint8_t *)&act_ths, 1);
}
+
return ret;
}
@@ -2244,7 +2547,7 @@ int32_t lis3dh_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dh_act_ths_t act_ths;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_ACT_THS, (uint8_t*)&act_ths, 1);
+ ret = lis3dh_read_reg(ctx, LIS3DH_ACT_THS, (uint8_t *)&act_ths, 1);
*val = (uint8_t)act_ths.acth;
return ret;
@@ -2264,11 +2567,14 @@ int32_t lis3dh_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
lis3dh_act_dur_t act_dur;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_ACT_DUR, (uint8_t*)&act_dur, 1);
- if (ret == 0) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_ACT_DUR, (uint8_t *)&act_dur, 1);
+
+ if (ret == 0)
+ {
act_dur.actd = val;
- ret = lis3dh_write_reg(ctx, LIS3DH_ACT_DUR, (uint8_t*)&act_dur, 1);
+ ret = lis3dh_write_reg(ctx, LIS3DH_ACT_DUR, (uint8_t *)&act_dur, 1);
}
+
return ret;
}
@@ -2286,7 +2592,7 @@ int32_t lis3dh_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dh_act_dur_t act_dur;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_ACT_DUR, (uint8_t*)&act_dur, 1);
+ ret = lis3dh_read_reg(ctx, LIS3DH_ACT_DUR, (uint8_t *)&act_dur, 1);
*val = (uint8_t)act_dur.actd;
return ret;
@@ -2314,16 +2620,19 @@ int32_t lis3dh_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lis3dh_pin_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
- lis3dh_sdo_pu_disc_t val)
+ lis3dh_sdo_pu_disc_t val)
{
lis3dh_ctrl_reg0_t ctrl_reg0;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG0, (uint8_t*)&ctrl_reg0, 1);
- if (ret == 0) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG0, (uint8_t *)&ctrl_reg0, 1);
+
+ if (ret == 0)
+ {
ctrl_reg0.sdo_pu_disc = (uint8_t)val;
- ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG0, (uint8_t*)&ctrl_reg0, 1);
+ ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG0, (uint8_t *)&ctrl_reg0, 1);
}
+
return ret;
}
@@ -2336,23 +2645,28 @@ int32_t lis3dh_pin_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis3dh_pin_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
- lis3dh_sdo_pu_disc_t *val)
+ lis3dh_sdo_pu_disc_t *val)
{
lis3dh_ctrl_reg0_t ctrl_reg0;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG0, (uint8_t*)&ctrl_reg0, 1);
- switch (ctrl_reg0.sdo_pu_disc) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG0, (uint8_t *)&ctrl_reg0, 1);
+
+ switch (ctrl_reg0.sdo_pu_disc)
+ {
case LIS3DH_PULL_UP_DISCONNECT:
*val = LIS3DH_PULL_UP_DISCONNECT;
break;
+
case LIS3DH_PULL_UP_CONNECT:
*val = LIS3DH_PULL_UP_CONNECT;
break;
+
default:
*val = LIS3DH_PULL_UP_DISCONNECT;
break;
}
+
return ret;
}
@@ -2369,11 +2683,14 @@ int32_t lis3dh_spi_mode_set(stmdev_ctx_t *ctx, lis3dh_sim_t val)
lis3dh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if (ret == 0) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.sim = (uint8_t)val;
- ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -2390,18 +2707,23 @@ int32_t lis3dh_spi_mode_get(stmdev_ctx_t *ctx, lis3dh_sim_t *val)
lis3dh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- switch (ctrl_reg4.sim) {
+ ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ switch (ctrl_reg4.sim)
+ {
case LIS3DH_SPI_4_WIRE:
*val = LIS3DH_SPI_4_WIRE;
break;
+
case LIS3DH_SPI_3_WIRE:
*val = LIS3DH_SPI_3_WIRE;
break;
+
default:
*val = LIS3DH_SPI_4_WIRE;
break;
}
+
return ret;
}
diff --git a/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.h b/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.h
index 736bad8afa62b4e08f240f1c81f948d14cebca65..f8b35575e976a4fb05593c8886dcfe2a69282514 100644
--- a/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.h
+++ b/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file lis3dh_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lis3dh_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lis3dh_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lis3dh_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LIS3DH_REGS_H
#define LIS3DH_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup LIS3DH
@@ -35,6 +36,37 @@
*
*/
+/** @defgroup Endianness definitions
+ * @{
+ *
+ */
+
+#ifndef DRV_BYTE_ORDER
+#ifndef __BYTE_ORDER__
+
+#define DRV_LITTLE_ENDIAN 1234
+#define DRV_BIG_ENDIAN 4321
+
+/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
+ * by uncommenting the define which fits your platform endianness
+ */
+//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
+#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
+
+#else /* defined __BYTE_ORDER__ */
+
+#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
+#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
+#define DRV_BYTE_ORDER __BYTE_ORDER__
+
+#endif /* __BYTE_ORDER__*/
+#endif /* DRV_BYTE_ORDER */
+
+/**
+ * @}
+ *
+ */
+
/** @defgroup STMicroelectronics sensors common types
* @{
*
@@ -43,7 +75,9 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -52,6 +86,16 @@ typedef struct{
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} bitwise_t;
#define PROPERTY_DISABLE (0U)
@@ -65,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -89,15 +134,16 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
- * Unico / Unicleo tools available on STMicroelectronics
- * web site.
+ * You can create a sensor configuration by your own or using
+ * Unico / Unicleo tools available on STMicroelectronics
+ * web site.
*
* @{
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -132,7 +178,9 @@ typedef struct {
*/
#define LIS3DH_STATUS_REG_AUX 0x07U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t _1da : 1;
uint8_t _2da : 1;
uint8_t _3da : 1;
@@ -141,6 +189,16 @@ typedef struct {
uint8_t _2or : 1;
uint8_t _3or : 1;
uint8_t _321or : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t _321or : 1;
+ uint8_t _3or : 1;
+ uint8_t _2or : 1;
+ uint8_t _1or : 1;
+ uint8_t _321da : 1;
+ uint8_t _3da : 1;
+ uint8_t _2da : 1;
+ uint8_t _1da : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dh_status_reg_aux_t;
#define LIS3DH_OUT_ADC1_L 0x08U
@@ -152,37 +210,69 @@ typedef struct {
#define LIS3DH_WHO_AM_I 0x0FU
#define LIS3DH_CTRL_REG0 0x1EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 7;
uint8_t sdo_pu_disc : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t sdo_pu_disc : 1;
+ uint8_t not_used_01 : 7;
+#endif /* DRV_BYTE_ORDER */
} lis3dh_ctrl_reg0_t;
#define LIS3DH_TEMP_CFG_REG 0x1FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 6;
uint8_t adc_pd : 1;
uint8_t temp_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t temp_en : 1;
+ uint8_t adc_pd : 1;
+ uint8_t not_used_01 : 6;
+#endif /* DRV_BYTE_ORDER */
} lis3dh_temp_cfg_reg_t;
#define LIS3DH_CTRL_REG1 0x20U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xen : 1;
uint8_t yen : 1;
uint8_t zen : 1;
uint8_t lpen : 1;
uint8_t odr : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr : 4;
+ uint8_t lpen : 1;
+ uint8_t zen : 1;
+ uint8_t yen : 1;
+ uint8_t xen : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dh_ctrl_reg1_t;
#define LIS3DH_CTRL_REG2 0x21U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t hp : 3; /* HPCLICK + HP_IA2 + HP_IA1 -> HP */
uint8_t fds : 1;
uint8_t hpcf : 2;
uint8_t hpm : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t hpm : 2;
+ uint8_t hpcf : 2;
+ uint8_t fds : 1;
+ uint8_t hp : 3; /* HPCLICK + HP_IA2 + HP_IA1 -> HP */
+#endif /* DRV_BYTE_ORDER */
} lis3dh_ctrl_reg2_t;
#define LIS3DH_CTRL_REG3 0x22U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t i1_overrun : 1;
uint8_t i1_wtm : 1;
@@ -191,20 +281,42 @@ typedef struct {
uint8_t i1_ia2 : 1;
uint8_t i1_ia1 : 1;
uint8_t i1_click : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t i1_click : 1;
+ uint8_t i1_ia1 : 1;
+ uint8_t i1_ia2 : 1;
+ uint8_t i1_zyxda : 1;
+ uint8_t i1_321da : 1;
+ uint8_t i1_wtm : 1;
+ uint8_t i1_overrun : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dh_ctrl_reg3_t;
#define LIS3DH_CTRL_REG4 0x23U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t st : 2;
uint8_t hr : 1;
uint8_t fs : 2;
uint8_t ble : 1;
uint8_t bdu : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bdu : 1;
+ uint8_t ble : 1;
+ uint8_t fs : 2;
+ uint8_t hr : 1;
+ uint8_t st : 2;
+ uint8_t sim : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dh_ctrl_reg4_t;
#define LIS3DH_CTRL_REG5 0x24U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d4d_int2 : 1;
uint8_t lir_int2 : 1;
uint8_t d4d_int1 : 1;
@@ -212,10 +324,21 @@ typedef struct {
uint8_t not_used_01 : 2;
uint8_t fifo_en : 1;
uint8_t boot : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t boot : 1;
+ uint8_t fifo_en : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t lir_int1 : 1;
+ uint8_t d4d_int1 : 1;
+ uint8_t lir_int2 : 1;
+ uint8_t d4d_int2 : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dh_ctrl_reg5_t;
#define LIS3DH_CTRL_REG6 0x25U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t int_polarity : 1;
uint8_t not_used_02 : 1;
@@ -224,11 +347,23 @@ typedef struct {
uint8_t i2_ia2 : 1;
uint8_t i2_ia1 : 1;
uint8_t i2_click : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t i2_click : 1;
+ uint8_t i2_ia1 : 1;
+ uint8_t i2_ia2 : 1;
+ uint8_t i2_boot : 1;
+ uint8_t i2_act : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t int_polarity : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dh_ctrl_reg6_t;
#define LIS3DH_REFERENCE 0x26U
#define LIS3DH_STATUS_REG 0x27U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xda : 1;
uint8_t yda : 1;
uint8_t zda : 1;
@@ -237,6 +372,16 @@ typedef struct {
uint8_t yor : 1;
uint8_t zor : 1;
uint8_t zyxor : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t zyxor : 1;
+ uint8_t zor : 1;
+ uint8_t yor : 1;
+ uint8_t _xor : 1;
+ uint8_t zyxda : 1;
+ uint8_t zda : 1;
+ uint8_t yda : 1;
+ uint8_t xda : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dh_status_reg_t;
#define LIS3DH_OUT_X_L 0x28U
@@ -246,22 +391,39 @@ typedef struct {
#define LIS3DH_OUT_Z_L 0x2CU
#define LIS3DH_OUT_Z_H 0x2DU
#define LIS3DH_FIFO_CTRL_REG 0x2EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fth : 5;
uint8_t tr : 1;
uint8_t fm : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fm : 2;
+ uint8_t tr : 1;
+ uint8_t fth : 5;
+#endif /* DRV_BYTE_ORDER */
} lis3dh_fifo_ctrl_reg_t;
#define LIS3DH_FIFO_SRC_REG 0x2FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fss : 5;
uint8_t empty : 1;
uint8_t ovrn_fifo : 1;
uint8_t wtm : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t wtm : 1;
+ uint8_t ovrn_fifo : 1;
+ uint8_t empty : 1;
+ uint8_t fss : 5;
+#endif /* DRV_BYTE_ORDER */
} lis3dh_fifo_src_reg_t;
#define LIS3DH_INT1_CFG 0x30U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlie : 1;
uint8_t xhie : 1;
uint8_t ylie : 1;
@@ -270,10 +432,22 @@ typedef struct {
uint8_t zhie : 1;
uint8_t _6d : 1;
uint8_t aoi : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t aoi : 1;
+ uint8_t _6d : 1;
+ uint8_t zhie : 1;
+ uint8_t zlie : 1;
+ uint8_t yhie : 1;
+ uint8_t ylie : 1;
+ uint8_t xhie : 1;
+ uint8_t xlie : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dh_int1_cfg_t;
#define LIS3DH_INT1_SRC 0x31U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
uint8_t yl : 1;
@@ -282,22 +456,46 @@ typedef struct {
uint8_t zh : 1;
uint8_t ia : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t ia : 1;
+ uint8_t zh : 1;
+ uint8_t zl : 1;
+ uint8_t yh : 1;
+ uint8_t yl : 1;
+ uint8_t xh : 1;
+ uint8_t xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dh_int1_src_t;
#define LIS3DH_INT1_THS 0x32U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t ths : 7;
+#endif /* DRV_BYTE_ORDER */
} lis3dh_int1_ths_t;
#define LIS3DH_INT1_DURATION 0x33U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d : 7;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t d : 7;
+#endif /* DRV_BYTE_ORDER */
} lis3dh_int1_duration_t;
#define LIS3DH_INT2_CFG 0x34U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlie : 1;
uint8_t xhie : 1;
uint8_t ylie : 1;
@@ -306,10 +504,22 @@ typedef struct {
uint8_t zhie : 1;
uint8_t _6d : 1;
uint8_t aoi : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t aoi : 1;
+ uint8_t _6d : 1;
+ uint8_t zhie : 1;
+ uint8_t zlie : 1;
+ uint8_t yhie : 1;
+ uint8_t ylie : 1;
+ uint8_t xhie : 1;
+ uint8_t xlie : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dh_int2_cfg_t;
#define LIS3DH_INT2_SRC 0x35U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
uint8_t yl : 1;
@@ -318,22 +528,46 @@ typedef struct {
uint8_t zh : 1;
uint8_t ia : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t ia : 1;
+ uint8_t zh : 1;
+ uint8_t zl : 1;
+ uint8_t yh : 1;
+ uint8_t yl : 1;
+ uint8_t xh : 1;
+ uint8_t xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dh_int2_src_t;
#define LIS3DH_INT2_THS 0x36U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t ths : 7;
+#endif /* DRV_BYTE_ORDER */
} lis3dh_int2_ths_t;
#define LIS3DH_INT2_DURATION 0x37U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d : 7;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t d : 7;
+#endif /* DRV_BYTE_ORDER */
} lis3dh_int2_duration_t;
#define LIS3DH_CLICK_CFG 0x38U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xs : 1;
uint8_t xd : 1;
uint8_t ys : 1;
@@ -341,10 +575,21 @@ typedef struct {
uint8_t zs : 1;
uint8_t zd : 1;
uint8_t not_used_01 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 2;
+ uint8_t zd : 1;
+ uint8_t zs : 1;
+ uint8_t yd : 1;
+ uint8_t ys : 1;
+ uint8_t xd : 1;
+ uint8_t xs : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dh_click_cfg_t;
#define LIS3DH_CLICK_SRC 0x39U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t x : 1;
uint8_t y : 1;
uint8_t z : 1;
@@ -353,54 +598,86 @@ typedef struct {
uint8_t dclick : 1;
uint8_t ia : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t ia : 1;
+ uint8_t dclick : 1;
+ uint8_t sclick : 1;
+ uint8_t sign : 1;
+ uint8_t z : 1;
+ uint8_t y : 1;
+ uint8_t x : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dh_click_src_t;
#define LIS3DH_CLICK_THS 0x3AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t lir_click : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t lir_click : 1;
+ uint8_t ths : 7;
+#endif /* DRV_BYTE_ORDER */
} lis3dh_click_ths_t;
#define LIS3DH_TIME_LIMIT 0x3BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tli : 7;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t tli : 7;
+#endif /* DRV_BYTE_ORDER */
} lis3dh_time_limit_t;
#define LIS3DH_TIME_LATENCY 0x3CU
-typedef struct {
+typedef struct
+{
uint8_t tla : 8;
} lis3dh_time_latency_t;
#define LIS3DH_TIME_WINDOW 0x3DU
-typedef struct {
+typedef struct
+{
uint8_t tw : 8;
} lis3dh_time_window_t;
#define LIS3DH_ACT_THS 0x3EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t acth : 7;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t acth : 7;
+#endif /* DRV_BYTE_ORDER */
} lis3dh_act_ths_t;
#define LIS3DH_ACT_DUR 0x3FU
-typedef struct {
+typedef struct
+{
uint8_t actd : 8;
} lis3dh_act_dur_t;
/**
* @defgroup LIS3DH_Register_Union
- * @brief This union group all the registers that has a bitfield
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is usefull but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
- * REMOVING this union you are complient with:
+ * REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
*
* @{
*
*/
-typedef union{
+typedef union
+{
lis3dh_status_reg_aux_t status_reg_aux;
lis3dh_ctrl_reg0_t ctrl_reg0;
lis3dh_temp_cfg_reg_t temp_cfg_reg;
@@ -438,39 +715,41 @@ typedef union{
*
*/
-int32_t lis3dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
- uint16_t len);
-int32_t lis3dh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
- uint16_t len);
-
-extern float lis3dh_from_fs2_hr_to_mg(int16_t lsb);
-extern float lis3dh_from_fs4_hr_to_mg(int16_t lsb);
-extern float lis3dh_from_fs8_hr_to_mg(int16_t lsb);
-extern float lis3dh_from_fs16_hr_to_mg(int16_t lsb);
-extern float lis3dh_from_lsb_hr_to_celsius(int16_t lsb);
-
-extern float lis3dh_from_fs2_nm_to_mg(int16_t lsb);
-extern float lis3dh_from_fs4_nm_to_mg(int16_t lsb);
-extern float lis3dh_from_fs8_nm_to_mg(int16_t lsb);
-extern float lis3dh_from_fs16_nm_to_mg(int16_t lsb);
-extern float lis3dh_from_lsb_nm_to_celsius(int16_t lsb);
-
-extern float lis3dh_from_fs2_lp_to_mg(int16_t lsb);
-extern float lis3dh_from_fs4_lp_to_mg(int16_t lsb);
-extern float lis3dh_from_fs8_lp_to_mg(int16_t lsb);
-extern float lis3dh_from_fs16_lp_to_mg(int16_t lsb);
-extern float lis3dh_from_lsb_lp_to_celsius(int16_t lsb);
+int32_t lis3dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
+ uint16_t len);
+int32_t lis3dh_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len);
+
+float_t lis3dh_from_fs2_hr_to_mg(int16_t lsb);
+float_t lis3dh_from_fs4_hr_to_mg(int16_t lsb);
+float_t lis3dh_from_fs8_hr_to_mg(int16_t lsb);
+float_t lis3dh_from_fs16_hr_to_mg(int16_t lsb);
+float_t lis3dh_from_lsb_hr_to_celsius(int16_t lsb);
+
+float_t lis3dh_from_fs2_nm_to_mg(int16_t lsb);
+float_t lis3dh_from_fs4_nm_to_mg(int16_t lsb);
+float_t lis3dh_from_fs8_nm_to_mg(int16_t lsb);
+float_t lis3dh_from_fs16_nm_to_mg(int16_t lsb);
+float_t lis3dh_from_lsb_nm_to_celsius(int16_t lsb);
+
+float_t lis3dh_from_fs2_lp_to_mg(int16_t lsb);
+float_t lis3dh_from_fs4_lp_to_mg(int16_t lsb);
+float_t lis3dh_from_fs8_lp_to_mg(int16_t lsb);
+float_t lis3dh_from_fs16_lp_to_mg(int16_t lsb);
+float_t lis3dh_from_lsb_lp_to_celsius(int16_t lsb);
int32_t lis3dh_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t lis3dh_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis3dh_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lis3dh_temperature_raw_get(stmdev_ctx_t *ctx, uint16_t *buff);
+int32_t lis3dh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val);
-int32_t lis3dh_adc_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lis3dh_adc_raw_get(stmdev_ctx_t *ctx, int16_t *buff);
-typedef enum {
+typedef enum
+{
LIS3DH_AUX_DISABLE = 0,
LIS3DH_AUX_ON_TEMPERATURE = 3,
LIS3DH_AUX_ON_PADS = 1,
@@ -478,17 +757,19 @@ typedef enum {
int32_t lis3dh_aux_adc_set(stmdev_ctx_t *ctx, lis3dh_temp_en_t val);
int32_t lis3dh_aux_adc_get(stmdev_ctx_t *ctx, lis3dh_temp_en_t *val);
-typedef enum {
+typedef enum
+{
LIS3DH_HR_12bit = 0,
LIS3DH_NM_10bit = 1,
LIS3DH_LP_8bit = 2,
} lis3dh_op_md_t;
int32_t lis3dh_operating_mode_set(stmdev_ctx_t *ctx,
- lis3dh_op_md_t val);
+ lis3dh_op_md_t val);
int32_t lis3dh_operating_mode_get(stmdev_ctx_t *ctx,
- lis3dh_op_md_t *val);
+ lis3dh_op_md_t *val);
-typedef enum {
+typedef enum
+{
LIS3DH_POWER_DOWN = 0x00,
LIS3DH_ODR_1Hz = 0x01,
LIS3DH_ODR_10Hz = 0x02,
@@ -503,30 +784,37 @@ typedef enum {
int32_t lis3dh_data_rate_set(stmdev_ctx_t *ctx, lis3dh_odr_t val);
int32_t lis3dh_data_rate_get(stmdev_ctx_t *ctx, lis3dh_odr_t *val);
-int32_t lis3dh_high_pass_on_outputs_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis3dh_high_pass_on_outputs_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis3dh_high_pass_on_outputs_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis3dh_high_pass_on_outputs_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS3DH_AGGRESSIVE = 0,
LIS3DH_STRONG = 1,
LIS3DH_MEDIUM = 2,
LIS3DH_LIGHT = 3,
} lis3dh_hpcf_t;
int32_t lis3dh_high_pass_bandwidth_set(stmdev_ctx_t *ctx,
- lis3dh_hpcf_t val);
+ lis3dh_hpcf_t val);
int32_t lis3dh_high_pass_bandwidth_get(stmdev_ctx_t *ctx,
- lis3dh_hpcf_t *val);
+ lis3dh_hpcf_t *val);
-typedef enum {
+typedef enum
+{
LIS3DH_NORMAL_WITH_RST = 0,
LIS3DH_REFERENCE_MODE = 1,
LIS3DH_NORMAL = 2,
LIS3DH_AUTORST_ON_INT = 3,
} lis3dh_hpm_t;
-int32_t lis3dh_high_pass_mode_set(stmdev_ctx_t *ctx, lis3dh_hpm_t val);
-int32_t lis3dh_high_pass_mode_get(stmdev_ctx_t *ctx, lis3dh_hpm_t *val);
+int32_t lis3dh_high_pass_mode_set(stmdev_ctx_t *ctx,
+ lis3dh_hpm_t val);
+int32_t lis3dh_high_pass_mode_get(stmdev_ctx_t *ctx,
+ lis3dh_hpm_t *val);
-typedef enum {
+typedef enum
+{
LIS3DH_2g = 0,
LIS3DH_4g = 1,
LIS3DH_8g = 2,
@@ -545,11 +833,12 @@ int32_t lis3dh_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis3dh_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lis3dh_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lis3dh_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val);
int32_t lis3dh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
-typedef enum {
+typedef enum
+{
LIS3DH_ST_DISABLE = 0,
LIS3DH_ST_POSITIVE = 1,
LIS3DH_ST_NEGATIVE = 2,
@@ -557,7 +846,8 @@ typedef enum {
int32_t lis3dh_self_test_set(stmdev_ctx_t *ctx, lis3dh_st_t val);
int32_t lis3dh_self_test_get(stmdev_ctx_t *ctx, lis3dh_st_t *val);
-typedef enum {
+typedef enum
+{
LIS3DH_LSB_AT_LOW_ADD = 0,
LIS3DH_MSB_AT_LOW_ADD = 1,
} lis3dh_ble_t;
@@ -567,37 +857,41 @@ int32_t lis3dh_data_format_get(stmdev_ctx_t *ctx, lis3dh_ble_t *val);
int32_t lis3dh_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3dh_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lis3dh_status_get(stmdev_ctx_t *ctx, lis3dh_status_reg_t *val);
+int32_t lis3dh_status_get(stmdev_ctx_t *ctx,
+ lis3dh_status_reg_t *val);
int32_t lis3dh_int1_gen_conf_set(stmdev_ctx_t *ctx,
- lis3dh_int1_cfg_t *val);
+ lis3dh_int1_cfg_t *val);
int32_t lis3dh_int1_gen_conf_get(stmdev_ctx_t *ctx,
- lis3dh_int1_cfg_t *val);
+ lis3dh_int1_cfg_t *val);
int32_t lis3dh_int1_gen_source_get(stmdev_ctx_t *ctx,
- lis3dh_int1_src_t *val);
+ lis3dh_int1_src_t *val);
int32_t lis3dh_int1_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis3dh_int1_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis3dh_int1_gen_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lis3dh_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3dh_int1_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis3dh_int2_gen_conf_set(stmdev_ctx_t *ctx,
- lis3dh_int2_cfg_t *val);
+ lis3dh_int2_cfg_t *val);
int32_t lis3dh_int2_gen_conf_get(stmdev_ctx_t *ctx,
- lis3dh_int2_cfg_t *val);
+ lis3dh_int2_cfg_t *val);
int32_t lis3dh_int2_gen_source_get(stmdev_ctx_t *ctx,
- lis3dh_int2_src_t *val);
+ lis3dh_int2_src_t *val);
int32_t lis3dh_int2_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis3dh_int2_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis3dh_int2_gen_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lis3dh_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3dh_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS3DH_DISC_FROM_INT_GENERATOR = 0,
LIS3DH_ON_INT1_GEN = 1,
LIS3DH_ON_INT2_GEN = 2,
@@ -608,43 +902,47 @@ typedef enum {
LIS3DH_ON_INT1_INT2_TAP_GEN = 7,
} lis3dh_hp_t;
int32_t lis3dh_high_pass_int_conf_set(stmdev_ctx_t *ctx,
- lis3dh_hp_t val);
+ lis3dh_hp_t val);
int32_t lis3dh_high_pass_int_conf_get(stmdev_ctx_t *ctx,
- lis3dh_hp_t *val);
+ lis3dh_hp_t *val);
int32_t lis3dh_pin_int1_config_set(stmdev_ctx_t *ctx,
- lis3dh_ctrl_reg3_t *val);
+ lis3dh_ctrl_reg3_t *val);
int32_t lis3dh_pin_int1_config_get(stmdev_ctx_t *ctx,
- lis3dh_ctrl_reg3_t *val);
+ lis3dh_ctrl_reg3_t *val);
int32_t lis3dh_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis3dh_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis3dh_int2_pin_detect_4d_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS3DH_INT2_PULSED = 0,
LIS3DH_INT2_LATCHED = 1,
} lis3dh_lir_int2_t;
int32_t lis3dh_int2_pin_notification_mode_set(stmdev_ctx_t *ctx,
- lis3dh_lir_int2_t val);
+ lis3dh_lir_int2_t val);
int32_t lis3dh_int2_pin_notification_mode_get(stmdev_ctx_t *ctx,
- lis3dh_lir_int2_t *val);
+ lis3dh_lir_int2_t *val);
int32_t lis3dh_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis3dh_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis3dh_int1_pin_detect_4d_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS3DH_INT1_PULSED = 0,
LIS3DH_INT1_LATCHED = 1,
} lis3dh_lir_int1_t;
int32_t lis3dh_int1_pin_notification_mode_set(stmdev_ctx_t *ctx,
- lis3dh_lir_int1_t val);
+ lis3dh_lir_int1_t val);
int32_t lis3dh_int1_pin_notification_mode_get(stmdev_ctx_t *ctx,
- lis3dh_lir_int1_t *val);
+ lis3dh_lir_int1_t *val);
int32_t lis3dh_pin_int2_config_set(stmdev_ctx_t *ctx,
- lis3dh_ctrl_reg6_t *val);
+ lis3dh_ctrl_reg6_t *val);
int32_t lis3dh_pin_int2_config_get(stmdev_ctx_t *ctx,
- lis3dh_ctrl_reg6_t *val);
+ lis3dh_ctrl_reg6_t *val);
int32_t lis3dh_fifo_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3dh_fifo_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -652,16 +950,18 @@ int32_t lis3dh_fifo_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis3dh_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3dh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS3DH_INT1_GEN = 0,
LIS3DH_INT2_GEN = 1,
} lis3dh_tr_t;
int32_t lis3dh_fifo_trigger_event_set(stmdev_ctx_t *ctx,
- lis3dh_tr_t val);
+ lis3dh_tr_t val);
int32_t lis3dh_fifo_trigger_event_get(stmdev_ctx_t *ctx,
- lis3dh_tr_t *val);
+ lis3dh_tr_t *val);
-typedef enum {
+typedef enum
+{
LIS3DH_BYPASS_MODE = 0,
LIS3DH_FIFO_MODE = 1,
LIS3DH_DYNAMIC_STREAM_MODE = 2,
@@ -671,7 +971,7 @@ int32_t lis3dh_fifo_mode_set(stmdev_ctx_t *ctx, lis3dh_fm_t val);
int32_t lis3dh_fifo_mode_get(stmdev_ctx_t *ctx, lis3dh_fm_t *val);
int32_t lis3dh_fifo_status_get(stmdev_ctx_t *ctx,
- lis3dh_fifo_src_reg_t *val);
+ lis3dh_fifo_src_reg_t *val);
int32_t lis3dh_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -681,23 +981,26 @@ int32_t lis3dh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis3dh_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lis3dh_tap_conf_set(stmdev_ctx_t *ctx, lis3dh_click_cfg_t *val);
-int32_t lis3dh_tap_conf_get(stmdev_ctx_t *ctx, lis3dh_click_cfg_t *val);
+int32_t lis3dh_tap_conf_set(stmdev_ctx_t *ctx,
+ lis3dh_click_cfg_t *val);
+int32_t lis3dh_tap_conf_get(stmdev_ctx_t *ctx,
+ lis3dh_click_cfg_t *val);
int32_t lis3dh_tap_source_get(stmdev_ctx_t *ctx,
- lis3dh_click_src_t *val);
+ lis3dh_click_src_t *val);
int32_t lis3dh_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3dh_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS3DH_TAP_PULSED = 0,
LIS3DH_TAP_LATCHED = 1,
} lis3dh_lir_click_t;
int32_t lis3dh_tap_notification_mode_set(stmdev_ctx_t *ctx,
- lis3dh_lir_click_t val);
+ lis3dh_lir_click_t val);
int32_t lis3dh_tap_notification_mode_get(stmdev_ctx_t *ctx,
- lis3dh_lir_click_t *val);
+ lis3dh_lir_click_t *val);
int32_t lis3dh_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3dh_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -706,7 +1009,8 @@ int32_t lis3dh_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3dh_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis3dh_double_tap_timeout_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis3dh_double_tap_timeout_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis3dh_double_tap_timeout_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lis3dh_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3dh_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -714,16 +1018,18 @@ int32_t lis3dh_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis3dh_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3dh_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS3DH_PULL_UP_DISCONNECT = 0,
LIS3DH_PULL_UP_CONNECT = 1,
} lis3dh_sdo_pu_disc_t;
int32_t lis3dh_pin_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
- lis3dh_sdo_pu_disc_t val);
+ lis3dh_sdo_pu_disc_t val);
int32_t lis3dh_pin_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
- lis3dh_sdo_pu_disc_t *val);
+ lis3dh_sdo_pu_disc_t *val);
-typedef enum {
+typedef enum
+{
LIS3DH_SPI_4_WIRE = 0,
LIS3DH_SPI_3_WIRE = 1,
} lis3dh_sim_t;
diff --git a/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.c b/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.c
index c89a86ec75079a777ae0f883b5295fbc04edff39..85427b5636ca90e3715bceeaa775ba297e2e2bed 100644
--- a/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.c
+++ b/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file lis3dhh_reg.c
- * @author Sensors Software Solution Team
- * @brief LIS3DHH driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lis3dhh_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LIS3DHH driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lis3dhh_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3dhh_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lis3dhh_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t lis3dhh_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3dhh_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lis3dhh_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -77,7 +83,7 @@ int32_t lis3dhh_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
*
*/
- /**
+/**
* @defgroup LIS3DHH_Sensitivity
* @brief These functions convert raw-data into engineering units.
* @{
@@ -86,7 +92,7 @@ int32_t lis3dhh_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
float_t lis3dhh_from_lsb_to_mg(int16_t lsb)
{
- return ((float_t)lsb *0.076f);
+ return ((float_t)lsb * 0.076f);
}
float_t lis3dhh_from_lsb_to_celsius(int16_t lsb)
@@ -120,10 +126,12 @@ int32_t lis3dhh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
lis3dhh_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0){
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.bdu = val;
- ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
}
return ret;
@@ -142,7 +150,7 @@ int32_t lis3dhh_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dhh_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
*val = ctrl_reg1.bdu;
return ret;
@@ -156,15 +164,18 @@ int32_t lis3dhh_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis3dhh_data_rate_set(stmdev_ctx_t *ctx, lis3dhh_norm_mod_en_t val)
+int32_t lis3dhh_data_rate_set(stmdev_ctx_t *ctx,
+ lis3dhh_norm_mod_en_t val)
{
lis3dhh_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0){
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.norm_mod_en = (uint8_t)val;
- ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
}
return ret;
@@ -178,20 +189,24 @@ int32_t lis3dhh_data_rate_set(stmdev_ctx_t *ctx, lis3dhh_norm_mod_en_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis3dhh_data_rate_get(stmdev_ctx_t *ctx, lis3dhh_norm_mod_en_t *val)
+int32_t lis3dhh_data_rate_get(stmdev_ctx_t *ctx,
+ lis3dhh_norm_mod_en_t *val)
{
lis3dhh_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
- switch (ctrl_reg1.norm_mod_en){
+ switch (ctrl_reg1.norm_mod_en)
+ {
case LIS3DHH_POWER_DOWN:
*val = LIS3DHH_POWER_DOWN;
break;
+
case LIS3DHH_1kHz1:
*val = LIS3DHH_1kHz1;
break;
+
default:
*val = LIS3DHH_POWER_DOWN;
break;
@@ -208,10 +223,15 @@ int32_t lis3dhh_data_rate_get(stmdev_ctx_t *ctx, lis3dhh_norm_mod_en_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis3dhh_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lis3dhh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
+
ret = lis3dhh_read_reg(ctx, LIS3DHH_OUT_TEMP_L, buff, 2);
+ *val = (int16_t)buff[1];
+ *val = (*val * 256) + (int16_t)buff[0];
+
return ret;
}
@@ -223,10 +243,19 @@ int32_t lis3dhh_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis3dhh_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lis3dhh_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lis3dhh_read_reg(ctx, LIS3DHH_OUT_X_L_XL, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -243,7 +272,7 @@ int32_t lis3dhh_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dhh_status_t status;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_STATUS, (uint8_t*)&status, 1);
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_STATUS, (uint8_t *)&status, 1);
*val = status.zyxda;
return ret;
@@ -262,7 +291,7 @@ int32_t lis3dhh_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dhh_status_t status;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_STATUS, (uint8_t*)&status, 1);
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_STATUS, (uint8_t *)&status, 1);
*val = status.zyxor;
return ret;
@@ -291,7 +320,9 @@ int32_t lis3dhh_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t lis3dhh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lis3dhh_read_reg(ctx, LIS3DHH_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -308,10 +339,12 @@ int32_t lis3dhh_reset_set(stmdev_ctx_t *ctx, uint8_t val)
lis3dhh_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0){
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.sw_reset = val;
- ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
}
return ret;
@@ -330,7 +363,7 @@ int32_t lis3dhh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dhh_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
*val = ctrl_reg1.sw_reset;
return ret;
@@ -349,10 +382,12 @@ int32_t lis3dhh_boot_set(stmdev_ctx_t *ctx, uint8_t val)
lis3dhh_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0){
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.boot = val;
- ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
}
return ret;
@@ -371,7 +406,7 @@ int32_t lis3dhh_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dhh_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
*val = ctrl_reg1.boot;
return ret;
@@ -390,10 +425,12 @@ int32_t lis3dhh_self_test_set(stmdev_ctx_t *ctx, lis3dhh_st_t val)
lis3dhh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0){
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.st = (uint8_t)val;
- ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
}
return ret;
@@ -412,18 +449,22 @@ int32_t lis3dhh_self_test_get(stmdev_ctx_t *ctx, lis3dhh_st_t *val)
lis3dhh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
- switch (ctrl_reg4.st){
+ switch (ctrl_reg4.st)
+ {
case LIS3DHH_ST_DISABLE:
*val = LIS3DHH_ST_DISABLE;
break;
+
case LIS3DHH_ST_POSITIVE:
*val = LIS3DHH_ST_POSITIVE;
break;
+
case LIS3DHH_ST_NEGATIVE:
*val = LIS3DHH_ST_NEGATIVE;
break;
+
default:
*val = LIS3DHH_ST_DISABLE;
break;
@@ -440,15 +481,18 @@ int32_t lis3dhh_self_test_get(stmdev_ctx_t *ctx, lis3dhh_st_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis3dhh_filter_config_set(stmdev_ctx_t *ctx, lis3dhh_dsp_t val)
+int32_t lis3dhh_filter_config_set(stmdev_ctx_t *ctx,
+ lis3dhh_dsp_t val)
{
lis3dhh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0){
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.dsp = (uint8_t)val;
- ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
}
return ret;
@@ -462,26 +506,32 @@ int32_t lis3dhh_filter_config_set(stmdev_ctx_t *ctx, lis3dhh_dsp_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis3dhh_filter_config_get(stmdev_ctx_t *ctx, lis3dhh_dsp_t *val)
+int32_t lis3dhh_filter_config_get(stmdev_ctx_t *ctx,
+ lis3dhh_dsp_t *val)
{
lis3dhh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
- switch (ctrl_reg4.dsp){
+ switch (ctrl_reg4.dsp)
+ {
case LIS3DHH_LINEAR_PHASE_440Hz:
*val = LIS3DHH_LINEAR_PHASE_440Hz;
break;
+
case LIS3DHH_LINEAR_PHASE_235Hz:
*val = LIS3DHH_LINEAR_PHASE_235Hz;
break;
+
case LIS3DHH_NO_LINEAR_PHASE_440Hz:
*val = LIS3DHH_NO_LINEAR_PHASE_440Hz;
break;
+
case LIS3DHH_NO_LINEAR_PHASE_235Hz:
*val = LIS3DHH_NO_LINEAR_PHASE_235Hz;
break;
+
default:
*val = LIS3DHH_LINEAR_PHASE_440Hz;
break;
@@ -501,7 +551,9 @@ int32_t lis3dhh_filter_config_get(stmdev_ctx_t *ctx, lis3dhh_dsp_t *val)
int32_t lis3dhh_status_get(stmdev_ctx_t *ctx, lis3dhh_status_t *val)
{
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_STATUS, (uint8_t*) val, 1);
+
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_STATUS, (uint8_t *) val, 1);
+
return ret;
}
@@ -526,15 +578,17 @@ int32_t lis3dhh_status_get(stmdev_ctx_t *ctx, lis3dhh_status_t *val)
*
*/
int32_t lis3dhh_drdy_notification_mode_set(stmdev_ctx_t *ctx,
- lis3dhh_drdy_pulse_t val)
+ lis3dhh_drdy_pulse_t val)
{
lis3dhh_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0){
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.drdy_pulse = (uint8_t)val;
- ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
}
return ret;
@@ -549,20 +603,23 @@ int32_t lis3dhh_drdy_notification_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis3dhh_drdy_notification_mode_get(stmdev_ctx_t *ctx,
- lis3dhh_drdy_pulse_t *val)
+ lis3dhh_drdy_pulse_t *val)
{
lis3dhh_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
- switch (ctrl_reg1.drdy_pulse){
+ switch (ctrl_reg1.drdy_pulse)
+ {
case LIS3DHH_LATCHED:
*val = LIS3DHH_LATCHED;
break;
+
case LIS3DHH_PULSED:
*val = LIS3DHH_PULSED;
break;
+
default:
*val = LIS3DHH_LATCHED;
break;
@@ -580,15 +637,18 @@ int32_t lis3dhh_drdy_notification_mode_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis3dhh_int1_mode_set(stmdev_ctx_t *ctx, lis3dhh_int1_ext_t val)
+int32_t lis3dhh_int1_mode_set(stmdev_ctx_t *ctx,
+ lis3dhh_int1_ext_t val)
{
lis3dhh_int1_ctrl_t int1_ctrl;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
- if(ret == 0){
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
+
+ if (ret == 0)
+ {
int1_ctrl.int1_ext = (uint8_t)val;
- ret = lis3dhh_write_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
+ ret = lis3dhh_write_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
}
return ret;
@@ -603,20 +663,24 @@ int32_t lis3dhh_int1_mode_set(stmdev_ctx_t *ctx, lis3dhh_int1_ext_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis3dhh_int1_mode_get(stmdev_ctx_t *ctx, lis3dhh_int1_ext_t *val)
+int32_t lis3dhh_int1_mode_get(stmdev_ctx_t *ctx,
+ lis3dhh_int1_ext_t *val)
{
lis3dhh_int1_ctrl_t int1_ctrl;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
- switch (int1_ctrl.int1_ext){
+ switch (int1_ctrl.int1_ext)
+ {
case LIS3DHH_PIN_AS_INTERRUPT:
*val = LIS3DHH_PIN_AS_INTERRUPT;
break;
+
case LIS3DHH_PIN_AS_TRIGGER:
*val = LIS3DHH_PIN_AS_TRIGGER;
break;
+
default:
*val = LIS3DHH_PIN_AS_INTERRUPT;
break;
@@ -639,10 +703,12 @@ int32_t lis3dhh_fifo_threshold_on_int1_set(stmdev_ctx_t *ctx,
lis3dhh_int1_ctrl_t int1_ctrl;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
- if(ret == 0){
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
+
+ if (ret == 0)
+ {
int1_ctrl.int1_fth = val;
- ret = lis3dhh_write_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
+ ret = lis3dhh_write_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
}
return ret;
@@ -656,12 +722,13 @@ int32_t lis3dhh_fifo_threshold_on_int1_set(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis3dhh_fifo_threshold_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis3dhh_fifo_threshold_on_int1_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis3dhh_int1_ctrl_t int1_ctrl;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
*val = int1_ctrl.int1_fth;
return ret;
@@ -680,10 +747,12 @@ int32_t lis3dhh_fifo_full_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
lis3dhh_int1_ctrl_t int1_ctrl;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
- if(ret == 0){
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
+
+ if (ret == 0)
+ {
int1_ctrl.int1_fss5 = val;
- ret = lis3dhh_write_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
+ ret = lis3dhh_write_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
}
return ret;
@@ -702,7 +771,7 @@ int32_t lis3dhh_fifo_full_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dhh_int1_ctrl_t int1_ctrl;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
*val = int1_ctrl.int1_fss5;
return ret;
@@ -721,10 +790,12 @@ int32_t lis3dhh_fifo_ovr_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
lis3dhh_int1_ctrl_t int1_ctrl;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
- if(ret == 0){
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
+
+ if (ret == 0)
+ {
int1_ctrl.int1_ovr = val;
- ret = lis3dhh_write_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
+ ret = lis3dhh_write_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
}
return ret;
@@ -743,7 +814,7 @@ int32_t lis3dhh_fifo_ovr_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dhh_int1_ctrl_t int1_ctrl;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
*val = int1_ctrl.int1_ovr;
return ret;
@@ -762,10 +833,12 @@ int32_t lis3dhh_boot_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
lis3dhh_int1_ctrl_t int1_ctrl;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
- if(ret == 0){
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
+
+ if (ret == 0)
+ {
int1_ctrl.int1_boot = val;
- ret = lis3dhh_write_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
+ ret = lis3dhh_write_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
}
return ret;
@@ -784,7 +857,7 @@ int32_t lis3dhh_boot_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dhh_int1_ctrl_t int1_ctrl;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
*val = int1_ctrl.int1_boot;
return ret;
@@ -803,10 +876,12 @@ int32_t lis3dhh_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
lis3dhh_int1_ctrl_t int1_ctrl;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
- if(ret == 0){
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
+
+ if (ret == 0)
+ {
int1_ctrl.int1_drdy = val;
- ret = lis3dhh_write_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
+ ret = lis3dhh_write_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
}
return ret;
@@ -825,7 +900,7 @@ int32_t lis3dhh_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dhh_int1_ctrl_t int1_ctrl;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
*val = int1_ctrl.int1_drdy;
return ret;
@@ -839,15 +914,18 @@ int32_t lis3dhh_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis3dhh_fifo_threshold_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lis3dhh_fifo_threshold_on_int2_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lis3dhh_int2_ctrl_t int2_ctrl;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
- if(ret == 0){
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
+
+ if (ret == 0)
+ {
int2_ctrl.int2_fth = val;
- ret = lis3dhh_write_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+ ret = lis3dhh_write_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
}
return ret;
@@ -861,12 +939,13 @@ int32_t lis3dhh_fifo_threshold_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis3dhh_fifo_threshold_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis3dhh_fifo_threshold_on_int2_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis3dhh_int2_ctrl_t int2_ctrl;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
*val = int2_ctrl.int2_fth;
return ret;
@@ -885,10 +964,12 @@ int32_t lis3dhh_fifo_full_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
lis3dhh_int2_ctrl_t int2_ctrl;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
- if(ret == 0){
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
+
+ if (ret == 0)
+ {
int2_ctrl.int2_fss5 = val;
- ret = lis3dhh_write_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+ ret = lis3dhh_write_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
}
return ret;
@@ -907,7 +988,7 @@ int32_t lis3dhh_fifo_full_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dhh_int2_ctrl_t int2_ctrl;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
*val = int2_ctrl.int2_fss5;
return ret;
@@ -926,10 +1007,12 @@ int32_t lis3dhh_fifo_ovr_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
lis3dhh_int2_ctrl_t int2_ctrl;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
- if(ret == 0){
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
+
+ if (ret == 0)
+ {
int2_ctrl.int2_ovr = val;
- ret = lis3dhh_write_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+ ret = lis3dhh_write_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
}
return ret;
@@ -948,7 +1031,7 @@ int32_t lis3dhh_fifo_ovr_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dhh_int2_ctrl_t int2_ctrl;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
*val = int2_ctrl.int2_ovr;
return ret;
@@ -967,10 +1050,12 @@ int32_t lis3dhh_boot_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
lis3dhh_int2_ctrl_t int2_ctrl;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
- if(ret == 0){
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
+
+ if (ret == 0)
+ {
int2_ctrl.int2_boot = val;
- ret = lis3dhh_write_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+ ret = lis3dhh_write_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
}
return ret;
@@ -989,7 +1074,7 @@ int32_t lis3dhh_boot_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dhh_int2_ctrl_t int2_ctrl;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
*val = int2_ctrl.int2_boot;
return ret;
@@ -1008,10 +1093,12 @@ int32_t lis3dhh_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
lis3dhh_int2_ctrl_t int2_ctrl;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
- if(ret == 0){
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
+
+ if (ret == 0)
+ {
int2_ctrl.int2_drdy = val;
- ret = lis3dhh_write_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+ ret = lis3dhh_write_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
}
return ret;
@@ -1030,7 +1117,7 @@ int32_t lis3dhh_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dhh_int2_ctrl_t int2_ctrl;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
*val = int2_ctrl.int2_drdy;
return ret;
@@ -1049,10 +1136,12 @@ int32_t lis3dhh_pin_mode_set(stmdev_ctx_t *ctx, lis3dhh_pp_od_t val)
lis3dhh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0){
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.pp_od = (uint8_t)val;
- ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
}
return ret;
@@ -1071,21 +1160,26 @@ int32_t lis3dhh_pin_mode_get(stmdev_ctx_t *ctx, lis3dhh_pp_od_t *val)
lis3dhh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
- switch (ctrl_reg4.pp_od){
+ switch (ctrl_reg4.pp_od)
+ {
case LIS3DHH_ALL_PUSH_PULL:
*val = LIS3DHH_ALL_PUSH_PULL;
break;
+
case LIS3DHH_INT1_OD_INT2_PP:
*val = LIS3DHH_INT1_OD_INT2_PP;
break;
+
case LIS3DHH_INT1_PP_INT2_OD:
*val = LIS3DHH_INT1_PP_INT2_OD;
break;
+
case LIS3DHH_ALL_OPEN_DRAIN:
*val = LIS3DHH_ALL_OPEN_DRAIN;
break;
+
default:
*val = LIS3DHH_ALL_PUSH_PULL;
break;
@@ -1120,10 +1214,12 @@ int32_t lis3dhh_fifo_set(stmdev_ctx_t *ctx, uint8_t val)
lis3dhh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0){
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.fifo_en = val;
- ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
}
return ret;
@@ -1142,7 +1238,7 @@ int32_t lis3dhh_fifo_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dhh_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
*val = ctrl_reg4.fifo_en;
return ret;
@@ -1164,10 +1260,12 @@ int32_t lis3dhh_fifo_block_spi_hs_set(stmdev_ctx_t *ctx, uint8_t val)
lis3dhh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if(ret == 0){
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.fifo_spi_hs_on = val;
- ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
}
return ret;
@@ -1189,7 +1287,7 @@ int32_t lis3dhh_fifo_block_spi_hs_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dhh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
*val = ctrl_reg5.fifo_spi_hs_on;
return ret;
@@ -1208,10 +1306,12 @@ int32_t lis3dhh_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
lis3dhh_fifo_ctrl_t fifo_ctrl;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
- if(ret == 0){
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl.fth = val;
- ret = lis3dhh_write_reg(ctx, LIS3DHH_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
+ ret = lis3dhh_write_reg(ctx, LIS3DHH_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
}
return ret;
@@ -1230,7 +1330,7 @@ int32_t lis3dhh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dhh_fifo_ctrl_t fifo_ctrl;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
*val = fifo_ctrl.fth;
return ret;
@@ -1249,10 +1349,12 @@ int32_t lis3dhh_fifo_mode_set(stmdev_ctx_t *ctx, lis3dhh_fmode_t val)
lis3dhh_fifo_ctrl_t fifo_ctrl;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
- if(ret == 0){
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl.fmode = (uint8_t)val;
- ret = lis3dhh_write_reg(ctx, LIS3DHH_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
+ ret = lis3dhh_write_reg(ctx, LIS3DHH_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
}
return ret;
@@ -1271,24 +1373,30 @@ int32_t lis3dhh_fifo_mode_get(stmdev_ctx_t *ctx, lis3dhh_fmode_t *val)
lis3dhh_fifo_ctrl_t fifo_ctrl;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
- switch (fifo_ctrl.fmode){
+ switch (fifo_ctrl.fmode)
+ {
case LIS3DHH_BYPASS_MODE:
*val = LIS3DHH_BYPASS_MODE;
break;
+
case LIS3DHH_FIFO_MODE:
*val = LIS3DHH_FIFO_MODE;
break;
+
case LIS3DHH_STREAM_TO_FIFO_MODE:
*val = LIS3DHH_STREAM_TO_FIFO_MODE;
break;
+
case LIS3DHH_BYPASS_TO_STREAM_MODE:
*val = LIS3DHH_BYPASS_TO_STREAM_MODE;
break;
+
case LIS3DHH_DYNAMIC_STREAM_MODE:
*val = LIS3DHH_DYNAMIC_STREAM_MODE;
break;
+
default:
*val = LIS3DHH_BYPASS_MODE;
break;
@@ -1305,10 +1413,13 @@ int32_t lis3dhh_fifo_mode_get(stmdev_ctx_t *ctx, lis3dhh_fmode_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lis3dhh_fifo_status_get(stmdev_ctx_t *ctx, lis3dhh_fifo_src_t *val)
+int32_t lis3dhh_fifo_status_get(stmdev_ctx_t *ctx,
+ lis3dhh_fifo_src_t *val)
{
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_FIFO_SRC, (uint8_t*) val, 1);
+
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_FIFO_SRC, (uint8_t *) val, 1);
+
return ret;
}
@@ -1325,7 +1436,7 @@ int32_t lis3dhh_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dhh_fifo_src_t fifo_src;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_FIFO_SRC, (uint8_t*)&fifo_src, 1);
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_FIFO_SRC, (uint8_t *)&fifo_src, 1);
*val = fifo_src.fss;
return ret;
@@ -1344,7 +1455,7 @@ int32_t lis3dhh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dhh_fifo_src_t fifo_src;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_FIFO_SRC, (uint8_t*)&fifo_src, 1);
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_FIFO_SRC, (uint8_t *)&fifo_src, 1);
*val = fifo_src.ovrn;
return ret;
@@ -1363,7 +1474,7 @@ int32_t lis3dhh_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dhh_fifo_src_t fifo_src;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_FIFO_SRC, (uint8_t*)&fifo_src, 1);
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_FIFO_SRC, (uint8_t *)&fifo_src, 1);
*val = fifo_src.fth;
return ret;
@@ -1396,10 +1507,12 @@ int32_t lis3dhh_auto_add_inc_set(stmdev_ctx_t *ctx, uint8_t val)
lis3dhh_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0){
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.if_add_inc = val;
- ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
}
return ret;
@@ -1419,7 +1532,7 @@ int32_t lis3dhh_auto_add_inc_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3dhh_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
*val = ctrl_reg1.if_add_inc;
return ret;
diff --git a/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.h b/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.h
index dfe4d3b7203682d336cdc2c2cd9c91e97c141ebf..ef9efa4876f08773d50dda1bcdcbd831931b63fd 100644
--- a/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.h
+++ b/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file lis3dhh_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lis3dhh_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lis3dhh_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lis3dhh_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LIS3DHH_REGS_H
#define LIS3DHH_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup LIS3DHH
@@ -35,6 +36,37 @@
*
*/
+/** @defgroup Endianness definitions
+ * @{
+ *
+ */
+
+#ifndef DRV_BYTE_ORDER
+#ifndef __BYTE_ORDER__
+
+#define DRV_LITTLE_ENDIAN 1234
+#define DRV_BIG_ENDIAN 4321
+
+/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
+ * by uncommenting the define which fits your platform endianness
+ */
+//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
+#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
+
+#else /* defined __BYTE_ORDER__ */
+
+#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
+#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
+#define DRV_BYTE_ORDER __BYTE_ORDER__
+
+#endif /* __BYTE_ORDER__*/
+#endif /* DRV_BYTE_ORDER */
+
+/**
+ * @}
+ *
+ */
+
/** @defgroup STMicroelectronics sensors common types
* @{
*
@@ -43,7 +75,9 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -52,6 +86,16 @@ typedef struct{
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} bitwise_t;
#define PROPERTY_DISABLE (0U)
@@ -65,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -89,15 +134,16 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
- * Unico / Unicleo tools available on STMicroelectronics
- * web site.
+ * You can create a sensor configuration by your own or using
+ * Unico / Unicleo tools available on STMicroelectronics
+ * web site.
*
* @{
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -129,7 +175,9 @@ typedef struct {
#define LIS3DHH_WHO_AM_I 0x0FU
#define LIS3DHH_CTRL_REG1 0x20U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bdu : 1;
uint8_t drdy_pulse : 1;
uint8_t sw_reset : 1;
@@ -137,10 +185,21 @@ typedef struct {
uint8_t not_used_01 : 2;
uint8_t if_add_inc : 1;
uint8_t norm_mod_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t norm_mod_en : 1;
+ uint8_t if_add_inc : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t boot : 1;
+ uint8_t sw_reset : 1;
+ uint8_t drdy_pulse : 1;
+ uint8_t bdu : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dhh_ctrl_reg1_t;
#define LIS3DHH_INT1_CTRL 0x21U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t int1_ext : 1;
uint8_t int1_fth : 1;
@@ -148,37 +207,73 @@ typedef struct {
uint8_t int1_ovr : 1;
uint8_t int1_boot : 1;
uint8_t int1_drdy : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_drdy : 1;
+ uint8_t int1_boot : 1;
+ uint8_t int1_ovr : 1;
+ uint8_t int1_fss5 : 1;
+ uint8_t int1_fth : 1;
+ uint8_t int1_ext : 1;
+ uint8_t not_used_01 : 2;
+#endif /* DRV_BYTE_ORDER */
} lis3dhh_int1_ctrl_t;
#define LIS3DHH_INT2_CTRL 0x22U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t int2_fth : 1;
uint8_t int2_fss5 : 1;
uint8_t int2_ovr : 1;
uint8_t int2_boot : 1;
uint8_t int2_drdy : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_drdy : 1;
+ uint8_t int2_boot : 1;
+ uint8_t int2_ovr : 1;
+ uint8_t int2_fss5 : 1;
+ uint8_t int2_fth : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
} lis3dhh_int2_ctrl_t;
#define LIS3DHH_CTRL_REG4 0x23U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t fifo_en : 1;
uint8_t pp_od : 2;
uint8_t st : 2;
uint8_t dsp : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t dsp : 2;
+ uint8_t st : 2;
+ uint8_t pp_od : 2;
+ uint8_t fifo_en : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dhh_ctrl_reg4_t;
#define LIS3DHH_CTRL_REG5 0x24U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fifo_spi_hs_on : 1;
uint8_t not_used_01 : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 7;
+ uint8_t fifo_spi_hs_on : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dhh_ctrl_reg5_t;
#define LIS3DHH_OUT_TEMP_L 0x25U
#define LIS3DHH_OUT_TEMP_H 0x26U
#define LIS3DHH_STATUS 0x27U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xda : 1;
uint8_t yda : 1;
uint8_t zda : 1;
@@ -187,6 +282,16 @@ typedef struct {
uint8_t yor : 1;
uint8_t zor : 1;
uint8_t zyxor : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t zyxor : 1;
+ uint8_t zor : 1;
+ uint8_t yor : 1;
+ uint8_t _xor : 1;
+ uint8_t zyxda : 1;
+ uint8_t zda : 1;
+ uint8_t yda : 1;
+ uint8_t xda : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dhh_status_t;
#define LIS3DHH_OUT_X_L_XL 0x28U
@@ -196,23 +301,36 @@ typedef struct {
#define LIS3DHH_OUT_Z_L_XL 0x2CU
#define LIS3DHH_OUT_Z_H_XL 0x2DU
#define LIS3DHH_FIFO_CTRL 0x2EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fth : 5;
uint8_t fmode : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fmode : 3;
+ uint8_t fth : 5;
+#endif /* DRV_BYTE_ORDER */
} lis3dhh_fifo_ctrl_t;
#define LIS3DHH_FIFO_SRC 0x2FU
-typedef struct {
- uint8_t fss : 6;
- uint8_t ovrn : 1;
- uint8_t fth : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t fss : 6;
+ uint8_t ovrn : 1;
+ uint8_t fth : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fth : 1;
+ uint8_t ovrn : 1;
+ uint8_t fss : 6;
+#endif /* DRV_BYTE_ORDER */
} lis3dhh_fifo_src_t;
/**
* @defgroup LIS3DHH_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -220,7 +338,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
lis3dhh_ctrl_reg1_t ctrl_reg1;
lis3dhh_int1_ctrl_t int1_ctrl;
lis3dhh_int2_ctrl_t int2_ctrl;
@@ -238,26 +357,32 @@ typedef union{
*
*/
-int32_t lis3dhh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lis3dhh_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t lis3dhh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lis3dhh_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-extern float_t lis3dhh_from_lsb_to_mg(int16_t lsb);
-extern float_t lis3dhh_from_lsb_to_celsius(int16_t lsb);
+float_t lis3dhh_from_lsb_to_mg(int16_t lsb);
+float_t lis3dhh_from_lsb_to_celsius(int16_t lsb);
int32_t lis3dhh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis3dhh_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis3dhh_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS3DHH_POWER_DOWN = 0,
LIS3DHH_1kHz1 = 1,
} lis3dhh_norm_mod_en_t;
-int32_t lis3dhh_data_rate_set(stmdev_ctx_t *ctx, lis3dhh_norm_mod_en_t val);
-int32_t lis3dhh_data_rate_get(stmdev_ctx_t *ctx, lis3dhh_norm_mod_en_t *val);
+int32_t lis3dhh_data_rate_set(stmdev_ctx_t *ctx,
+ lis3dhh_norm_mod_en_t val);
+int32_t lis3dhh_data_rate_get(stmdev_ctx_t *ctx,
+ lis3dhh_norm_mod_en_t *val);
-int32_t lis3dhh_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lis3dhh_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lis3dhh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t lis3dhh_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val);
int32_t lis3dhh_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -271,7 +396,8 @@ int32_t lis3dhh_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis3dhh_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3dhh_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS3DHH_ST_DISABLE = 0,
LIS3DHH_ST_POSITIVE = 1,
LIS3DHH_ST_NEGATIVE = 2,
@@ -279,18 +405,22 @@ typedef enum {
int32_t lis3dhh_self_test_set(stmdev_ctx_t *ctx, lis3dhh_st_t val);
int32_t lis3dhh_self_test_get(stmdev_ctx_t *ctx, lis3dhh_st_t *val);
-typedef enum {
+typedef enum
+{
LIS3DHH_LINEAR_PHASE_440Hz = 0,
LIS3DHH_LINEAR_PHASE_235Hz = 1,
LIS3DHH_NO_LINEAR_PHASE_440Hz = 2,
LIS3DHH_NO_LINEAR_PHASE_235Hz = 3,
} lis3dhh_dsp_t;
-int32_t lis3dhh_filter_config_set(stmdev_ctx_t *ctx, lis3dhh_dsp_t val);
-int32_t lis3dhh_filter_config_get(stmdev_ctx_t *ctx, lis3dhh_dsp_t *val);
+int32_t lis3dhh_filter_config_set(stmdev_ctx_t *ctx,
+ lis3dhh_dsp_t val);
+int32_t lis3dhh_filter_config_get(stmdev_ctx_t *ctx,
+ lis3dhh_dsp_t *val);
int32_t lis3dhh_status_get(stmdev_ctx_t *ctx, lis3dhh_status_t *val);
-typedef enum {
+typedef enum
+{
LIS3DHH_LATCHED = 0,
LIS3DHH_PULSED = 1,
} lis3dhh_drdy_pulse_t;
@@ -300,19 +430,25 @@ int32_t lis3dhh_drdy_notification_mode_get(stmdev_ctx_t *ctx,
lis3dhh_drdy_pulse_t *val);
-typedef enum {
+typedef enum
+{
LIS3DHH_PIN_AS_INTERRUPT = 0,
LIS3DHH_PIN_AS_TRIGGER = 1,
} lis3dhh_int1_ext_t;
-int32_t lis3dhh_int1_mode_set(stmdev_ctx_t *ctx, lis3dhh_int1_ext_t val);
-int32_t lis3dhh_int1_mode_get(stmdev_ctx_t *ctx, lis3dhh_int1_ext_t *val);
+int32_t lis3dhh_int1_mode_set(stmdev_ctx_t *ctx,
+ lis3dhh_int1_ext_t val);
+int32_t lis3dhh_int1_mode_get(stmdev_ctx_t *ctx,
+ lis3dhh_int1_ext_t *val);
-int32_t lis3dhh_fifo_threshold_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis3dhh_fifo_threshold_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis3dhh_fifo_threshold_on_int1_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis3dhh_fifo_threshold_on_int1_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lis3dhh_fifo_full_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis3dhh_fifo_full_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis3dhh_fifo_full_on_int1_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lis3dhh_fifo_ovr_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3dhh_fifo_ovr_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -323,11 +459,14 @@ int32_t lis3dhh_boot_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis3dhh_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3dhh_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lis3dhh_fifo_threshold_on_int2_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis3dhh_fifo_threshold_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis3dhh_fifo_threshold_on_int2_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lis3dhh_fifo_threshold_on_int2_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lis3dhh_fifo_full_on_int2_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis3dhh_fifo_full_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis3dhh_fifo_full_on_int2_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lis3dhh_fifo_ovr_on_int2_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3dhh_fifo_ovr_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -338,7 +477,8 @@ int32_t lis3dhh_boot_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis3dhh_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3dhh_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS3DHH_ALL_PUSH_PULL = 0,
LIS3DHH_INT1_OD_INT2_PP = 1,
LIS3DHH_INT1_PP_INT2_OD = 2,
@@ -351,12 +491,14 @@ int32_t lis3dhh_fifo_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3dhh_fifo_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis3dhh_fifo_block_spi_hs_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis3dhh_fifo_block_spi_hs_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis3dhh_fifo_block_spi_hs_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lis3dhh_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3dhh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LIS3DHH_BYPASS_MODE = 0,
LIS3DHH_FIFO_MODE = 1,
LIS3DHH_STREAM_TO_FIFO_MODE = 3,
@@ -364,9 +506,11 @@ typedef enum {
LIS3DHH_DYNAMIC_STREAM_MODE = 6,
} lis3dhh_fmode_t;
int32_t lis3dhh_fifo_mode_set(stmdev_ctx_t *ctx, lis3dhh_fmode_t val);
-int32_t lis3dhh_fifo_mode_get(stmdev_ctx_t *ctx, lis3dhh_fmode_t *val);
+int32_t lis3dhh_fifo_mode_get(stmdev_ctx_t *ctx,
+ lis3dhh_fmode_t *val);
-int32_t lis3dhh_fifo_status_get(stmdev_ctx_t *ctx, lis3dhh_fifo_src_t *val);
+int32_t lis3dhh_fifo_status_get(stmdev_ctx_t *ctx,
+ lis3dhh_fifo_src_t *val);
int32_t lis3dhh_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
diff --git a/sensor/stmemsc/lis3dsh_STdC/driver/lis3dsh_reg.c b/sensor/stmemsc/lis3dsh_STdC/driver/lis3dsh_reg.c
index f0a65c306ac1c226221b1a8734127c89d6039755..9bd96a671798c0cd85b822a2631dc8f427a78f6c 100644
--- a/sensor/stmemsc/lis3dsh_STdC/driver/lis3dsh_reg.c
+++ b/sensor/stmemsc/lis3dsh_STdC/driver/lis3dsh_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file lis3dsh_reg.c
- * @author Sensors Software Solution Team
- * @brief LIS3DSH driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lis3dsh_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LIS3DSH driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lis3dsh_reg.h"
@@ -43,14 +43,17 @@
* @param reg first register address to read.
* @param data buffer for data read.(ptr)
* @param len number of consecutive register to read.
- * @retval interface status (MANDATORY: return 0 -> no Error).
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3dsh_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t lis3dsh_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -61,14 +64,17 @@ int32_t lis3dsh_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @param reg first register address to write.
* @param data the buffer contains data to be written.(ptr)
* @param len number of consecutive register to write.
- * @retval interface status (MANDATORY: return 0 -> no Error).
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3dsh_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t lis3dsh_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -86,7 +92,8 @@ int32_t lis3dsh_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
static void bytecpy(uint8_t *target, uint8_t *source)
{
- if ( (target != NULL) && (source != NULL) ) {
+ if ((target != NULL) && (source != NULL))
+ {
*target = *source;
}
}
@@ -129,7 +136,7 @@ float_t lis3dsh_from_fs16_to_mg(int16_t lsb)
float_t lis3dsh_from_lsb_to_celsius(int8_t lsb)
{
- return (((float_t)lsb / 256.0f) + 25.0f);
+ return ((float_t)lsb + 25.0f);
}
/**
@@ -148,65 +155,75 @@ float_t lis3dsh_from_lsb_to_celsius(int8_t lsb)
/**
* @brief Device "Who am I".[get]
*
- * @param ctx communication interface handler.(ptr)
- * @param val ID values.(ptr)
+ * @param ctx communication interface handler.(ptr)
+ * @param val ID values.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis3dsh_id_get(stmdev_ctx_t *ctx, lis3dsh_id_t *val)
{
uint8_t reg[3];
int32_t ret;
-
- ret = lis3dsh_read_reg(ctx, LIS3DSH_INFO1,reg, 3);
+
+ ret = lis3dsh_read_reg(ctx, LIS3DSH_INFO1, reg, 3);
val->info1 = reg[0];
val->info2 = reg[1];
val->whoami = reg[2];
-
+
return ret;
}
/**
* @brief Configures the bus operating mode.[set]
*
- * @param ctx communication interface handler.(ptr)
- * @param val configures the bus operating mode.(ptr)
+ * @param ctx communication interface handler.(ptr)
+ * @param val configures the bus operating mode.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3dsh_bus_mode_set(stmdev_ctx_t *ctx, lis3dsh_bus_mode_t *val)
+int32_t lis3dsh_bus_mode_set(stmdev_ctx_t *ctx,
+ lis3dsh_bus_mode_t *val)
{
lis3dsh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
- ctrl_reg5.sim = (uint8_t)*val;
- ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
+ ctrl_reg5.sim = (uint8_t) * val;
+ ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
}
return ret;
-
}
/**
* @brief Get the bus operating mode.[get]
*
- * @param ctx communication interface handler.(ptr)
- * @param val retrieves the bus operating.(ptr)
+ * @param ctx communication interface handler.(ptr)
+ * @param val retrieves the bus operating.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3dsh_bus_mode_get(stmdev_ctx_t *ctx, lis3dsh_bus_mode_t *val)
+int32_t lis3dsh_bus_mode_get(stmdev_ctx_t *ctx,
+ lis3dsh_bus_mode_t *val)
{
lis3dsh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- switch ( ctrl_reg5.sim ) {
+ ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
+
+ switch (ctrl_reg5.sim)
+ {
case LIS3DSH_SEL_BY_HW:
*val = LIS3DSH_SEL_BY_HW;
break;
+
case LIS3DSH_SPI_3W:
*val = LIS3DSH_SPI_3W;
break;
+
default:
*val = LIS3DSH_SEL_BY_HW;
break;
@@ -218,11 +235,12 @@ int32_t lis3dsh_bus_mode_get(stmdev_ctx_t *ctx, lis3dsh_bus_mode_t *val)
/**
* @brief Re-initialize the device.[set]
*
- * @param ctx communication interface handler.(ptr)
- * @param val re-initialization mode. Refer to datasheet
+ * @param ctx communication interface handler.(ptr)
+ * @param val re-initialization mode. Refer to datasheet
* and application note for more information
- * about differencies beetween boot and sw_reset
+ * about differencies between boot and sw_reset
* procedure.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis3dsh_init_set(stmdev_ctx_t *ctx, lis3dsh_init_t val)
@@ -230,57 +248,72 @@ int32_t lis3dsh_init_set(stmdev_ctx_t *ctx, lis3dsh_init_t val)
lis3dsh_ctrl_reg3_t ctrl_reg3;
lis3dsh_ctrl_reg4_t ctrl_reg4;
lis3dsh_ctrl_reg6_t ctrl_reg6;
-
int32_t ret;
- switch ( val ) {
+
+ switch (val)
+ {
case LIS3DSH_BOOT:
ctrl_reg6.boot = (uint8_t)val & (uint8_t)LIS3DSH_BOOT;
- ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
break;
+
case LIS3DSH_RESET:
- ctrl_reg3.strt = ( (uint8_t)val & (uint8_t)LIS3DSH_RESET) >> 1;
- ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG6, (uint8_t*)&ctrl_reg6, 1);
+ ctrl_reg3.strt = ((uint8_t)val & (uint8_t)LIS3DSH_RESET) >> 1;
+ ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG6, (uint8_t *)&ctrl_reg6, 1);
break;
+
case LIS3DSH_DRV_RDY:
ctrl_reg4.xen = PROPERTY_ENABLE;
ctrl_reg4.yen = PROPERTY_ENABLE;
ctrl_reg4.zen = PROPERTY_ENABLE;
ctrl_reg4.bdu = PROPERTY_ENABLE;
ctrl_reg6.add_inc = PROPERTY_ENABLE;
- ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if (ret == 0) {
- ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG6, (uint8_t*)&ctrl_reg6, 1);
+ ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
+ ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG6,
+ (uint8_t *)&ctrl_reg6, 1);
}
+
break;
+
default:
- ctrl_reg3.strt = ( (uint8_t)val & (uint8_t)LIS3DSH_RESET) >> 1;
- ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG6, (uint8_t*)&ctrl_reg6, 1);
+ ctrl_reg3.strt = ((uint8_t)val & (uint8_t)LIS3DSH_RESET) >> 1;
+ ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG6, (uint8_t *)&ctrl_reg6, 1);
break;
}
+
return ret;
}
/**
* @brief Get the status of the device.[get]
*
- * @param ctx communication interface handler.(ptr)
- * @param val the status of the device.(ptr)
+ * @param ctx communication interface handler.(ptr)
+ * @param val the status of the device.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3dsh_status_get(stmdev_ctx_t *ctx, lis3dsh_status_var_t *val)
+int32_t lis3dsh_status_get(stmdev_ctx_t *ctx,
+ lis3dsh_status_var_t *val)
{
lis3dsh_ctrl_reg3_t ctrl_reg3;
lis3dsh_ctrl_reg6_t ctrl_reg6;
lis3dsh_stat_t stat;
int32_t ret;
- ret = lis3dsh_read_reg(ctx, LIS3DSH_STAT, (uint8_t*)&stat, 1);
- if (ret == 0) {
- ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lis3dsh_read_reg(ctx, LIS3DSH_STAT, (uint8_t *)&stat, 1);
+
+ if (ret == 0)
+ {
+ ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
}
- if (ret == 0) {
- ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG6, (uint8_t*)&ctrl_reg6, 1);
+
+ if (ret == 0)
+ {
+ ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG6, (uint8_t *)&ctrl_reg6, 1);
}
val->sw_reset = ctrl_reg3.strt;
@@ -294,20 +327,24 @@ int32_t lis3dsh_status_get(stmdev_ctx_t *ctx, lis3dsh_status_var_t *val)
/**
* @brief Interrupt pins hardware signal configuration.[set]
*
- * @param ctx communication interface handler.(ptr)
- * @param val the pins hardware signal settings.(ptr)
+ * @param ctx communication interface handler.(ptr)
+ * @param val the pins hardware signal settings.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3dsh_interrupt_mode_set(stmdev_ctx_t *ctx, lis3dsh_int_mode_t *val)
+int32_t lis3dsh_interrupt_mode_set(stmdev_ctx_t *ctx,
+ lis3dsh_int_mode_t *val)
{
lis3dsh_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if (ret == 0) {
+ ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.iel = ~(val->latched);
ctrl_reg3.iea = ~(val->active_low);
- ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
}
return ret;
@@ -316,16 +353,18 @@ int32_t lis3dsh_interrupt_mode_set(stmdev_ctx_t *ctx, lis3dsh_int_mode_t *val)
/**
* @brief Interrupt pins hardware signal configuration.[get]
*
- * @param ctx communication interface handler.(ptr)
- * @param val the pins hardware signal settings.(ptr)
+ * @param ctx communication interface handler.(ptr)
+ * @param val the pins hardware signal settings.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3dsh_interrupt_mode_get(stmdev_ctx_t *ctx, lis3dsh_int_mode_t *val)
+int32_t lis3dsh_interrupt_mode_get(stmdev_ctx_t *ctx,
+ lis3dsh_int_mode_t *val)
{
lis3dsh_ctrl_reg3_t ctrl_reg3;
int32_t ret;
-
- ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+
+ ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
val->latched = ~(ctrl_reg3.iel);
val->active_low = ~(ctrl_reg3.iea);
@@ -335,8 +374,9 @@ int32_t lis3dsh_interrupt_mode_get(stmdev_ctx_t *ctx, lis3dsh_int_mode_t *val)
/**
* @brief Route interrupt signals on int1 pin.[set]
*
- * @param ctx communication interface handler.(ptr)
- * @param val the signals to route on int1 pin.(ptr)
+ * @param ctx communication interface handler.(ptr)
+ * @param val the signals to route on int1 pin.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis3dsh_pin_int1_route_set(stmdev_ctx_t *ctx,
@@ -349,12 +389,11 @@ int32_t lis3dsh_pin_int1_route_set(stmdev_ctx_t *ctx,
uint8_t reg[5];
int32_t ret;
- ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG1, (uint8_t*)®, 5);
- bytecpy(( uint8_t*)&ctrl_reg1, ®[0]);
- bytecpy(( uint8_t*)&ctrl_reg2, ®[1]);
- bytecpy(( uint8_t*)&ctrl_reg3, ®[2]);
- bytecpy(( uint8_t*)&ctrl_reg6, ®[4]);
-
+ ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG1, (uint8_t *)®, 5);
+ bytecpy((uint8_t *)&ctrl_reg1, ®[0]);
+ bytecpy((uint8_t *)&ctrl_reg2, ®[1]);
+ bytecpy((uint8_t *)&ctrl_reg3, ®[2]);
+ bytecpy((uint8_t *)&ctrl_reg6, ®[4]);
ctrl_reg1.sm1_pin = ~(val->fsm1);
ctrl_reg2.sm2_pin = ~(val->fsm2);
ctrl_reg3.dr_en = val->drdy_xl;
@@ -362,30 +401,37 @@ int32_t lis3dsh_pin_int1_route_set(stmdev_ctx_t *ctx,
ctrl_reg6.p1_empty = val->fifo_empty;
ctrl_reg6.p1_overrun = val->fifo_full;
- if ( (val->fsm1 | val->fsm2 | val->drdy_xl |
- val->fifo_empty | val->fifo_th |
- val->fifo_full) == PROPERTY_ENABLE ){
+ if ((val->fsm1 | val->fsm2 | val->drdy_xl |
+ val->fifo_empty | val->fifo_th |
+ val->fifo_full) == PROPERTY_ENABLE)
+ {
ctrl_reg3.int1_en = PROPERTY_ENABLE;
}
- else {
+
+ else
+ {
ctrl_reg3.int1_en = PROPERTY_DISABLE;
}
- bytecpy(®[0], ( uint8_t*)&ctrl_reg1);
- bytecpy(®[1], ( uint8_t*)&ctrl_reg2);
- bytecpy(®[2], ( uint8_t*)&ctrl_reg3);
- bytecpy(®[4], ( uint8_t*)&ctrl_reg6);
- if (ret == 0) {
- ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG1, (uint8_t*)®, 5);
+ bytecpy(®[0], (uint8_t *)&ctrl_reg1);
+ bytecpy(®[1], (uint8_t *)&ctrl_reg2);
+ bytecpy(®[2], (uint8_t *)&ctrl_reg3);
+ bytecpy(®[4], (uint8_t *)&ctrl_reg6);
+
+ if (ret == 0)
+ {
+ ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG1, (uint8_t *)®, 5);
}
+
return ret;
}
/**
* @brief Route interrupt signals on int1 pin.[get]
*
- * @param ctx communication interface handler.(ptr)
- * @param val the signals that are routed on int1 pin.(ptr)
+ * @param ctx communication interface handler.(ptr)
+ * @param val the signals that are routed on int1 pin.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis3dsh_pin_int1_route_get(stmdev_ctx_t *ctx,
@@ -398,21 +444,24 @@ int32_t lis3dsh_pin_int1_route_get(stmdev_ctx_t *ctx,
uint8_t reg[5];
int32_t ret;
- ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG1, (uint8_t*)®, 5);
- bytecpy(( uint8_t*)&ctrl_reg1, ®[0]);
- bytecpy(( uint8_t*)&ctrl_reg2, ®[1]);
- bytecpy(( uint8_t*)&ctrl_reg3, ®[2]);
- bytecpy(( uint8_t*)&ctrl_reg6, ®[4]);
+ ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG1, (uint8_t *)®, 5);
+ bytecpy((uint8_t *)&ctrl_reg1, ®[0]);
+ bytecpy((uint8_t *)&ctrl_reg2, ®[1]);
+ bytecpy((uint8_t *)&ctrl_reg3, ®[2]);
+ bytecpy((uint8_t *)&ctrl_reg6, ®[4]);
- if ( ctrl_reg3.int1_en == PROPERTY_ENABLE ){
- val->fsm1 = ~(ctrl_reg1.sm1_pin);
- val->fsm2 = ~(ctrl_reg2.sm2_pin);
- val->drdy_xl = ctrl_reg3.dr_en;
+ if (ctrl_reg3.int1_en == PROPERTY_ENABLE)
+ {
+ val->fsm1 = ~(ctrl_reg1.sm1_pin);
+ val->fsm2 = ~(ctrl_reg2.sm2_pin);
+ val->drdy_xl = ctrl_reg3.dr_en;
val->fifo_th = ctrl_reg6.p1_wtm;
val->fifo_empty = ctrl_reg6.p1_empty;
val->fifo_full = ctrl_reg6.p1_overrun;
}
- else {
+
+ else
+ {
val->fsm1 = PROPERTY_DISABLE;
val->fsm2 = PROPERTY_DISABLE;
val->drdy_xl = PROPERTY_DISABLE;
@@ -427,11 +476,12 @@ int32_t lis3dsh_pin_int1_route_get(stmdev_ctx_t *ctx,
/**
* @brief Route interrupt signals on int2 pin.[set]
*
- * @param ctx communication interface handler.(ptr)
- * @param val the signals to route on int2 pin.(ptr)
+ * @param ctx communication interface handler.(ptr)
+ * @param val the signals to route on int2 pin.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3dsh_pin_int2_route_set(stmdev_ctx_t *ctx,
+int32_t lis3dsh_pin_int2_route_set(stmdev_ctx_t *ctx,
lis3dsh_pin_int2_route_t *val)
{
lis3dsh_ctrl_reg1_t ctrl_reg1;
@@ -441,45 +491,51 @@ int32_t lis3dsh_pin_int2_route_set(stmdev_ctx_t *ctx,
uint8_t reg[5];
int32_t ret;
- ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG1, (uint8_t*)®, 5);
- bytecpy(( uint8_t*)&ctrl_reg1, ®[0]);
- bytecpy(( uint8_t*)&ctrl_reg2, ®[1]);
- bytecpy(( uint8_t*)&ctrl_reg3, ®[2]);
- bytecpy(( uint8_t*)&ctrl_reg6, ®[4]);
-
+ ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG1, (uint8_t *)®, 5);
+ bytecpy((uint8_t *)&ctrl_reg1, ®[0]);
+ bytecpy((uint8_t *)&ctrl_reg2, ®[1]);
+ bytecpy((uint8_t *)&ctrl_reg3, ®[2]);
+ bytecpy((uint8_t *)&ctrl_reg6, ®[4]);
ctrl_reg1.sm1_pin = val->fsm1;
ctrl_reg2.sm2_pin = val->fsm2;
ctrl_reg6.p2_boot = val->boot;
- if ( (val->fsm1 | val->fsm2 | val->boot) == PROPERTY_ENABLE){
+ if ((val->fsm1 | val->fsm2 | val->boot) == PROPERTY_ENABLE)
+ {
ctrl_reg3.int1_en = PROPERTY_ENABLE;
}
- else {
+
+ else
+ {
ctrl_reg3.int1_en = PROPERTY_DISABLE;
}
- bytecpy(®[0], (uint8_t*)&ctrl_reg1);
- bytecpy(®[1], (uint8_t*)&ctrl_reg2);
- bytecpy(®[2], (uint8_t*)&ctrl_reg3);
- bytecpy(®[4], (uint8_t*)&ctrl_reg6);
- if (ret == 0) {
- ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG1, (uint8_t*)®, 5);
+ bytecpy(®[0], (uint8_t *)&ctrl_reg1);
+ bytecpy(®[1], (uint8_t *)&ctrl_reg2);
+ bytecpy(®[2], (uint8_t *)&ctrl_reg3);
+ bytecpy(®[4], (uint8_t *)&ctrl_reg6);
+
+ if (ret == 0)
+ {
+ ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG1, (uint8_t *)®, 5);
}
+
return ret;
}
/**
* @brief Route interrupt signals on int2 pin.[get]
*
- * @param ctx communication interface handler. Use NULL to ingnore
+ * @param ctx communication interface handler. Use NULL to ignore
* this interface.(ptr)
* @param aux_ctx auxiliary communication interface handler. Use NULL
- * to ingnore this interface.(ptr)
- * @param val the signals that are routed on int2 pin.(ptr)
+ * to ignore this interface.(ptr)
+ * @param val the signals that are routed on int2 pin.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis3dsh_pin_int2_route_get(stmdev_ctx_t *ctx,
- lis3dsh_pin_int2_route_t *val)
+ lis3dsh_pin_int2_route_t *val)
{
lis3dsh_ctrl_reg1_t ctrl_reg1;
lis3dsh_ctrl_reg2_t ctrl_reg2;
@@ -488,22 +544,24 @@ int32_t lis3dsh_pin_int2_route_get(stmdev_ctx_t *ctx,
uint8_t reg[5];
int32_t ret;
- ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG1, (uint8_t*)®, 5);
- bytecpy(( uint8_t*)&ctrl_reg1, ®[0]);
- bytecpy(( uint8_t*)&ctrl_reg2, ®[1]);
- bytecpy(( uint8_t*)&ctrl_reg3, ®[2]);
- bytecpy(( uint8_t*)&ctrl_reg6, ®[4]);
-
- if ( ctrl_reg3.int1_en == PROPERTY_ENABLE ){
- val->fsm1 = ctrl_reg1.sm1_pin;
- val->fsm2 = ctrl_reg2.sm2_pin;
- val->boot = ctrl_reg6.p2_boot;
+ ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG1, (uint8_t *)®, 5);
+ bytecpy((uint8_t *)&ctrl_reg1, ®[0]);
+ bytecpy((uint8_t *)&ctrl_reg2, ®[1]);
+ bytecpy((uint8_t *)&ctrl_reg3, ®[2]);
+ bytecpy((uint8_t *)&ctrl_reg6, ®[4]);
+ if (ctrl_reg3.int1_en == PROPERTY_ENABLE)
+ {
+ val->fsm1 = ctrl_reg1.sm1_pin;
+ val->fsm2 = ctrl_reg2.sm2_pin;
+ val->boot = ctrl_reg6.p2_boot;
}
- else {
+
+ else
+ {
val->fsm1 = PROPERTY_DISABLE;
val->fsm2 = PROPERTY_DISABLE;
- val->boot = PROPERTY_DISABLE;
+ val->boot = PROPERTY_DISABLE;
}
return ret;
@@ -512,30 +570,33 @@ int32_t lis3dsh_pin_int2_route_get(stmdev_ctx_t *ctx,
/**
* @brief Get the status of all the interrupt sources.[get]
*
- * @param ctx communication interface handler.(ptr)
- * @param val the status of all the interrupt sources.(ptr)
+ * @param ctx communication interface handler.(ptr)
+ * @param val the status of all the interrupt sources.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3dsh_all_sources_get(stmdev_ctx_t *ctx, lis3dsh_all_sources_t *val)
+int32_t lis3dsh_all_sources_get(stmdev_ctx_t *ctx,
+ lis3dsh_all_sources_t *val)
{
-
lis3dsh_fifo_src_t fifo_src;
lis3dsh_stat_t stat;
int32_t ret;
- ret = lis3dsh_read_reg(ctx, LIS3DSH_STAT, (uint8_t*)&stat, 1);
- if (ret == 0) {
- ret = lis3dsh_read_reg(ctx, LIS3DSH_FIFO_SRC, (uint8_t*)&fifo_src, 1);
+ ret = lis3dsh_read_reg(ctx, LIS3DSH_STAT, (uint8_t *)&stat, 1);
+
+ if (ret == 0)
+ {
+ ret = lis3dsh_read_reg(ctx, LIS3DSH_FIFO_SRC, (uint8_t *)&fifo_src, 1);
}
-
- val->drdy_xl = stat.drdy;
- val->ovrn_xl = stat.dor;
- val->fsm_lc = stat.l_count;
- val->fsm_ext_sync = stat.syncw;
- val->fsm1_wait_fsm2 = stat.sync1;
- val->fsm2_wait_fsm1 = stat.sync2;
- val->fsm1 = stat.int_sm1;
- val->fsm2 = stat.int_sm2;
+
+ val->drdy_xl = stat.drdy;
+ val->ovrn_xl = stat.dor;
+ val->fsm_lc = stat.l_count;
+ val->fsm_ext_sync = stat.syncw;
+ val->fsm1_wait_fsm2 = stat.sync1;
+ val->fsm2_wait_fsm1 = stat.sync2;
+ val->fsm1 = stat.int_sm1;
+ val->fsm2 = stat.int_sm2;
val->fifo_ovr = fifo_src.ovrn_fifo;
val->fifo_empty = fifo_src.empty;
val->fifo_full = fifo_src.ovrn_fifo;
@@ -547,9 +608,10 @@ int32_t lis3dsh_all_sources_get(stmdev_ctx_t *ctx, lis3dsh_all_sources_t *val)
/**
* @brief Sensor conversion parameters selection.[set]
*
- * @param ctx communication interface handler.(ptr)
- * @param val set the sensor conversion parameters by checking
+ * @param ctx communication interface handler.(ptr)
+ * @param val set the sensor conversion parameters by checking
* the constraints of the device.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis3dsh_mode_set(stmdev_ctx_t *ctx, lis3dsh_md_t *val)
@@ -558,19 +620,24 @@ int32_t lis3dsh_mode_set(stmdev_ctx_t *ctx, lis3dsh_md_t *val)
lis3dsh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if (ret == 0) {
- ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
+ ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
}
ctrl_reg4.odr = (uint8_t)val->odr;
ctrl_reg5.fscale = (uint8_t)val->fs;
- if (ret == 0) {
- ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ if (ret == 0)
+ {
+ ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
}
- if (ret == 0) {
- ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
+ ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
}
return ret;
@@ -579,74 +646,93 @@ int32_t lis3dsh_mode_set(stmdev_ctx_t *ctx, lis3dsh_md_t *val)
/**
* @brief Sensor conversion parameters selection.[get]
*
- * @param ctx communication interface handler.(ptr)
- * @param val get the sensor conversion parameters.(ptr)
+ * @param ctx communication interface handler.(ptr)
+ * @param val get the sensor conversion parameters.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis3dsh_mode_get(stmdev_ctx_t *ctx, lis3dsh_md_t *val)
{
-
lis3dsh_ctrl_reg4_t ctrl_reg4;
lis3dsh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if (ret == 0) {
- ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
+ ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
}
- switch (ctrl_reg4.odr) {
+ switch (ctrl_reg4.odr)
+ {
case LIS3DSH_OFF:
val->odr = LIS3DSH_OFF;
break;
+
case LIS3DSH_3Hz125:
val->odr = LIS3DSH_3Hz125;
break;
+
case LIS3DSH_6Hz25:
val->odr = LIS3DSH_6Hz25;
break;
+
case LIS3DSH_12Hz5:
val->odr = LIS3DSH_12Hz5;
break;
+
case LIS3DSH_25Hz:
val->odr = LIS3DSH_25Hz;
break;
+
case LIS3DSH_50Hz:
val->odr = LIS3DSH_50Hz;
break;
+
case LIS3DSH_100Hz:
val->odr = LIS3DSH_100Hz;
break;
+
case LIS3DSH_400Hz:
val->odr = LIS3DSH_400Hz;
break;
+
case LIS3DSH_800Hz:
val->odr = LIS3DSH_800Hz;
break;
+
case LIS3DSH_1kHz6:
val->odr = LIS3DSH_1kHz6;
break;
+
default:
val->odr = LIS3DSH_OFF;
break;
}
- switch (ctrl_reg5.fscale) {
+ switch (ctrl_reg5.fscale)
+ {
case LIS3DSH_2g:
val->fs = LIS3DSH_2g;
break;
+
case LIS3DSH_4g:
val->fs = LIS3DSH_4g;
break;
+
case LIS3DSH_6g:
val->fs = LIS3DSH_6g;
break;
+
case LIS3DSH_8g:
val->fs = LIS3DSH_8g;
break;
+
case LIS3DSH_16g:
val->fs = LIS3DSH_16g;
break;
+
default:
val->fs = LIS3DSH_2g;
break;
@@ -660,6 +746,7 @@ int32_t lis3dsh_mode_get(stmdev_ctx_t *ctx, lis3dsh_md_t *val)
*
* @param ctx communication interface handler.(ptr)
* @param md the sensor conversion parameters.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis3dsh_data_get(stmdev_ctx_t *ctx, lis3dsh_md_t *md,
@@ -667,40 +754,49 @@ int32_t lis3dsh_data_get(stmdev_ctx_t *ctx, lis3dsh_md_t *md,
{
uint8_t buff[6];
int32_t ret;
+
uint8_t i;
uint8_t j;
-
- ret = lis3dsh_read_reg(ctx, LIS3DSH_OUT_T, (uint8_t*)&data->heat.raw, 1);
- if (ret == 0) {
- ret = lis3dsh_read_reg(ctx, LIS3DSH_OUT_X_L, (uint8_t*)&buff, 6);
+ ret = lis3dsh_read_reg(ctx, LIS3DSH_OUT_T, (uint8_t *)&data->heat.raw, 1);
+
+ if (ret == 0)
+ {
+ ret = lis3dsh_read_reg(ctx, LIS3DSH_OUT_X_L, (uint8_t *)&buff, 6);
}
-
/* temperature conversion */
data->heat.deg_c = lis3dsh_from_lsb_to_celsius(data->heat.raw);
-
/* acceleration conversion */
j = 0U;
- for (i = 0U; i < 3U; i++) {
- data->xl.raw[i] = (int16_t)buff[j+1U];
+
+ for (i = 0U; i < 3U; i++)
+ {
+ data->xl.raw[i] = (int16_t)buff[j + 1U];
data->xl.raw[i] = (data->xl.raw[i] * 256) + (int16_t) buff[j];
- j+=2U;
- switch ( md->fs ) {
+ j += 2U;
+
+ switch (md->fs)
+ {
case LIS3DSH_2g:
- data->xl.mg[i] =lis3dsh_from_fs2_to_mg(data->xl.raw[i]);
+ data->xl.mg[i] = lis3dsh_from_fs2_to_mg(data->xl.raw[i]);
break;
+
case LIS3DSH_4g:
- data->xl.mg[i] =lis3dsh_from_fs4_to_mg(data->xl.raw[i]);
+ data->xl.mg[i] = lis3dsh_from_fs4_to_mg(data->xl.raw[i]);
break;
+
case LIS3DSH_6g:
- data->xl.mg[i] =lis3dsh_from_fs6_to_mg(data->xl.raw[i]);
+ data->xl.mg[i] = lis3dsh_from_fs6_to_mg(data->xl.raw[i]);
break;
+
case LIS3DSH_8g:
- data->xl.mg[i] =lis3dsh_from_fs8_to_mg(data->xl.raw[i]);
+ data->xl.mg[i] = lis3dsh_from_fs8_to_mg(data->xl.raw[i]);
break;
+
case LIS3DSH_16g:
- data->xl.mg[i] =lis3dsh_from_fs16_to_mg(data->xl.raw[i]);
+ data->xl.mg[i] = lis3dsh_from_fs16_to_mg(data->xl.raw[i]);
break;
+
default:
data->xl.mg[i] = 0.0f;
break;
@@ -719,8 +815,9 @@ int32_t lis3dsh_data_get(stmdev_ctx_t *ctx, lis3dsh_md_t *md,
/**
* @brief Configures the self test.[set]
*
- * @param ctx communication interface handler.(ptr)
- * @param val Self test mode mode.(ptr)
+ * @param ctx communication interface handler.(ptr)
+ * @param val Self test mode mode.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis3dsh_self_test_set(stmdev_ctx_t *ctx, lis3dsh_st_t val)
@@ -728,19 +825,23 @@ int32_t lis3dsh_self_test_set(stmdev_ctx_t *ctx, lis3dsh_st_t val)
lis3dsh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if (ret == 0) {
+ ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5.st = (uint8_t) val;
- ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
/**
* @brief Get self test configuration.[set]
*
- * @param ctx communication interface handler.(ptr)
- * @param val Self test mode mode.(ptr)
+ * @param ctx communication interface handler.(ptr)
+ * @param val Self test mode mode.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis3dsh_self_test_get(stmdev_ctx_t *ctx, lis3dsh_st_t *val)
@@ -748,19 +849,22 @@ int32_t lis3dsh_self_test_get(stmdev_ctx_t *ctx, lis3dsh_st_t *val)
lis3dsh_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
switch (ctrl_reg5.st)
{
case LIS3DSH_ST_DISABLE:
*val = LIS3DSH_ST_DISABLE;
break;
+
case LIS3DSH_ST_POSITIVE:
*val = LIS3DSH_ST_POSITIVE;
break;
+
case LIS3DSH_ST_NEGATIVE:
*val = LIS3DSH_ST_NEGATIVE;
break;
+
default:
*val = LIS3DSH_ST_DISABLE;
break;
diff --git a/sensor/stmemsc/lis3dsh_STdC/driver/lis3dsh_reg.h b/sensor/stmemsc/lis3dsh_STdC/driver/lis3dsh_reg.h
index 8a0311b0665fb767c7e3034d3edb4d18481f1e4b..56e1ae913416f3ed990bcee45a5c9b06522ecf3f 100644
--- a/sensor/stmemsc/lis3dsh_STdC/driver/lis3dsh_reg.h
+++ b/sensor/stmemsc/lis3dsh_STdC/driver/lis3dsh_reg.h
@@ -1,29 +1,29 @@
-/*
- ******************************************************************************
- * @file lis3dsh_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lis3dsh_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lis3dsh_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lis3dsh_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LIS3DSH_REGS_H
#define LIS3DSH_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -36,6 +36,37 @@
*
*/
+/** @defgroup Endianness definitions
+ * @{
+ *
+ */
+
+#ifndef DRV_BYTE_ORDER
+#ifndef __BYTE_ORDER__
+
+#define DRV_LITTLE_ENDIAN 1234
+#define DRV_BIG_ENDIAN 4321
+
+/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
+ * by uncommenting the define which fits your platform endianness
+ */
+//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
+#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
+
+#else /* defined __BYTE_ORDER__ */
+
+#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
+#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
+#define DRV_BYTE_ORDER __BYTE_ORDER__
+
+#endif /* __BYTE_ORDER__*/
+#endif /* DRV_BYTE_ORDER */
+
+/**
+ * @}
+ *
+ */
+
/** @defgroup STMicroelectronics sensors common types
* @{
*
@@ -44,7 +75,9 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -53,8 +86,23 @@ typedef struct{
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} bitwise_t;
+/**
+ * @}
+ *
+ */
+
#define PROPERTY_DISABLE (0U)
#define PROPERTY_ENABLE (1U)
@@ -66,10 +114,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -98,7 +147,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -149,7 +199,9 @@ typedef struct {
#define LIS3DSH_LC_H 0x17U
#define LIS3DSH_STAT 0x18U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t drdy : 1;
uint8_t dor : 1;
uint8_t int_sm2 : 1;
@@ -158,6 +210,16 @@ typedef struct {
uint8_t sync2 : 1;
uint8_t syncw : 1;
uint8_t l_count : 1; //alias LONG
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t l_count : 1; //alias LONG
+ uint8_t syncw : 1;
+ uint8_t sync2 : 1;
+ uint8_t sync1 : 1;
+ uint8_t int_sm1 : 1;
+ uint8_t int_sm2 : 1;
+ uint8_t dor : 1;
+ uint8_t drdy : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dsh_stat_t;
#define LIS3DSH_PEAK1 0x19U
@@ -170,34 +232,63 @@ typedef struct {
#define LIS3DSH_THRS3 0x1FU
#define LIS3DSH_CTRL_REG4 0x20U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xen : 1;
uint8_t yen : 1;
uint8_t zen : 1;
uint8_t bdu : 1;
uint8_t odr : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr : 4;
+ uint8_t bdu : 1;
+ uint8_t zen : 1;
+ uint8_t yen : 1;
+ uint8_t xen : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dsh_ctrl_reg4_t;
#define LIS3DSH_CTRL_REG1 0x21U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sm1_en : 1;
uint8_t not_used_01 : 2;
uint8_t sm1_pin : 1;
uint8_t not_used_02 : 1;
uint8_t hyst_1 : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t hyst_1 : 3;
+ uint8_t not_used_02 : 1;
+ uint8_t sm1_pin : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t sm1_en : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dsh_ctrl_reg1_t;
#define LIS3DSH_CTRL_REG2 0x22U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sm2_en : 1;
uint8_t not_used_01 : 2;
uint8_t sm2_pin : 1;
uint8_t not_used_02 : 1;
uint8_t hyst_2 : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t hyst_2 : 3;
+ uint8_t not_used_02 : 1;
+ uint8_t sm2_pin : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t sm2_en : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dsh_ctrl_reg2_t;
#define LIS3DSH_CTRL_REG3 0x23U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t strt : 1;
uint8_t not_used_01 : 1;
uint8_t vfilt : 1;
@@ -206,18 +297,38 @@ typedef struct {
uint8_t iel : 1;
uint8_t iea : 1;
uint8_t dr_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t dr_en : 1;
+ uint8_t iea : 1;
+ uint8_t iel : 1;
+ uint8_t int2_en : 1;
+ uint8_t int1_en : 1;
+ uint8_t vfilt : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t strt : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dsh_ctrl_reg3_t;
#define LIS3DSH_CTRL_REG5 0x24U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t st : 2;
uint8_t fscale : 3;
uint8_t bw : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bw : 2;
+ uint8_t fscale : 3;
+ uint8_t st : 2;
+ uint8_t sim : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dsh_ctrl_reg5_t;
#define LIS3DSH_CTRL_REG6 0x25U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t p2_boot : 1;
uint8_t p1_overrun : 1;
uint8_t p1_wtm : 1;
@@ -226,10 +337,22 @@ typedef struct {
uint8_t wtm_en : 1;
uint8_t fifo_en : 1;
uint8_t boot : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t boot : 1;
+ uint8_t fifo_en : 1;
+ uint8_t wtm_en : 1;
+ uint8_t add_inc : 1;
+ uint8_t p1_empty : 1;
+ uint8_t p1_wtm : 1;
+ uint8_t p1_overrun : 1;
+ uint8_t p2_boot : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dsh_ctrl_reg6_t;
#define LIS3DSH_STATUS 0x27U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xda : 1;
uint8_t yda : 1;
uint8_t zda : 1;
@@ -238,6 +361,16 @@ typedef struct {
uint8_t yor : 1;
uint8_t zor : 1;
uint8_t zyxor : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t zyxor : 1;
+ uint8_t zor : 1;
+ uint8_t yor : 1;
+ uint8_t _xor : 1;
+ uint8_t zyxda : 1;
+ uint8_t zda : 1;
+ uint8_t yda : 1;
+ uint8_t xda : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dsh_status_t;
#define LIS3DSH_OUT_X_L 0x28U
@@ -247,17 +380,31 @@ typedef struct {
#define LIS3DSH_OUT_Z_L 0x2CU
#define LIS3DSH_OUT_Z_H 0x2DU
#define LIS3DSH_FIFO_CTRL 0X2EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wtmp : 5;
uint8_t fmode : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fmode : 3;
+ uint8_t wtmp : 5;
+#endif /* DRV_BYTE_ORDER */
} lis3dsh_fifo_ctrl_t;
#define LIS3DSH_FIFO_SRC 0x2FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fss : 5;
uint8_t empty : 1;
uint8_t ovrn_fifo : 1;
uint8_t wtm : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t wtm : 1;
+ uint8_t ovrn_fifo : 1;
+ uint8_t empty : 1;
+ uint8_t fss : 5;
+#endif /* DRV_BYTE_ORDER */
} lis3dsh_fifo_src_t;
/* State Machine 1 */
@@ -287,7 +434,9 @@ typedef struct {
#define LIS3DSH_THRS2_1 0x56U
#define LIS3DSH_THRS1_1 0x57U
#define LIS3DSH_MASK1_B 0x59U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -296,10 +445,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dsh_mask1_b_t;
#define LIS3DSH_MASK1_A 0x5AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -308,10 +469,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dsh_mask1_a_t;
#define LIS3DSH_SETT1 0x5BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sitr : 1;
uint8_t r_tam : 1;
uint8_t thr3_ma : 1;
@@ -319,18 +492,35 @@ typedef struct {
uint8_t abs : 1;
uint8_t thr3_sa : 1;
uint8_t p_det : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_det : 1;
+ uint8_t thr3_sa : 1;
+ uint8_t abs : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t thr3_ma : 1;
+ uint8_t r_tam : 1;
+ uint8_t sitr : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dsh_sett1_t;
#define LIS3DSH_PR1 0x5CU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t pp : 4;
uint8_t rp : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t rp : 4;
+ uint8_t pp : 4;
+#endif /* DRV_BYTE_ORDER */
} lis3dsh_pr1_t;
#define LIS3DSH_TC1_L 0x5DU
#define LIS3DSH_TC1_H 0x5EU
#define LIS3DSH_OUTS1 0x5FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -339,6 +529,16 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dsh_outs1_t;
/* State Machine 2 */
@@ -369,7 +569,9 @@ typedef struct {
#define LIS3DSH_THRS1_2 0x77U
#define LIS3DSH_DES2 0x78U
#define LIS3DSH_MASK2_B 0x79U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -378,10 +580,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dsh_mask2_b_t;
#define LIS3DSH_MASK2_A 0x7AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -390,10 +604,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dsh_mask2_a_t;
#define LIS3DSH_SETT2 0x7BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sitr : 1;
uint8_t r_tam : 1;
uint8_t thr3_ma : 1;
@@ -402,18 +628,36 @@ typedef struct {
uint8_t abs : 1;
uint8_t thr3_sa : 1;
uint8_t p_det : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_det : 1;
+ uint8_t thr3_sa : 1;
+ uint8_t abs : 1;
+ uint8_t radi : 1;
+ uint8_t d_cs : 1;
+ uint8_t thr3_ma : 1;
+ uint8_t r_tam : 1;
+ uint8_t sitr : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dsh_sett2_t;
#define LIS3DSH_PR2 0x7CU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t pp : 4;
uint8_t rp : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t rp : 4;
+ uint8_t pp : 4;
+#endif /* DRV_BYTE_ORDER */
} lis3dsh_pr2_t;
#define LIS3DSH_TC2_L 0x7DU
#define LIS3DSH_TC2_H 0x7EU
#define LIS3DSH_OUTS2 0x7FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -422,13 +666,23 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3dsh_outs2_t;
/**
* @defgroup LIS3DSH_Register_Union
- * @brief This union group all the registers that has a bitfield
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -436,7 +690,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
lis3dsh_stat_t stat;
lis3dsh_ctrl_reg4_t ctrl_reg4;
lis3dsh_ctrl_reg1_t ctrl_reg1;
@@ -466,57 +721,69 @@ typedef union{
*
*/
-int32_t lis3dsh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lis3dsh_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t lis3dsh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lis3dsh_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-extern float_t lis3dsh_from_fs2_to_mg(int16_t lsb);
-extern float_t lis3dsh_from_fs4_to_mg(int16_t lsb);
-extern float_t lis3dsh_from_fs6_to_mg(int16_t lsb);
-extern float_t lis3dsh_from_fs8_to_mg(int16_t lsb);
-extern float_t lis3dsh_from_fs16_to_mg(int16_t lsb);
-extern float_t lis3dsh_from_lsb_to_celsius(int8_t lsb);
+float_t lis3dsh_from_fs2_to_mg(int16_t lsb);
+float_t lis3dsh_from_fs4_to_mg(int16_t lsb);
+float_t lis3dsh_from_fs6_to_mg(int16_t lsb);
+float_t lis3dsh_from_fs8_to_mg(int16_t lsb);
+float_t lis3dsh_from_fs16_to_mg(int16_t lsb);
+float_t lis3dsh_from_lsb_to_celsius(int8_t lsb);
-typedef struct {
+typedef struct
+{
uint8_t whoami;
uint8_t info1;
uint8_t info2;
} lis3dsh_id_t;
int32_t lis3dsh_id_get(stmdev_ctx_t *ctx, lis3dsh_id_t *val);
-typedef enum {
+typedef enum
+{
LIS3DSH_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */
LIS3DSH_SPI_3W = 0x01, /* SDO / SDI share the same pin */
} lis3dsh_bus_mode_t;
-int32_t lis3dsh_bus_mode_set(stmdev_ctx_t *ctx, lis3dsh_bus_mode_t *val);
-int32_t lis3dsh_bus_mode_get(stmdev_ctx_t *ctx, lis3dsh_bus_mode_t *val);
+int32_t lis3dsh_bus_mode_set(stmdev_ctx_t *ctx,
+ lis3dsh_bus_mode_t *val);
+int32_t lis3dsh_bus_mode_get(stmdev_ctx_t *ctx,
+ lis3dsh_bus_mode_t *val);
-typedef enum {
+typedef enum
+{
LIS3DSH_DRV_RDY = 0x00, /* Initialize the device for driver usage */
LIS3DSH_BOOT = 0x01, /* Restore calib. param. ( it takes 10ms ) */
LIS3DSH_RESET = 0x02, /* Reset configuration registers */
} lis3dsh_init_t;
int32_t lis3dsh_init_set(stmdev_ctx_t *ctx, lis3dsh_init_t val);
-typedef struct {
- uint8_t sw_reset : 1; /* Restoring configuration registers */
+typedef struct
+{
+uint8_t sw_reset :
+ 1; /* Restoring configuration registers */
uint8_t boot : 1; /* Restoring calibration parameters */
uint8_t drdy_xl : 1; /* Accelerometer data ready */
uint8_t ovrn_xl : 1; /* Accelerometer data overrun */
} lis3dsh_status_var_t;
-int32_t lis3dsh_status_get(stmdev_ctx_t *ctx, lis3dsh_status_var_t *val);
+int32_t lis3dsh_status_get(stmdev_ctx_t *ctx,
+ lis3dsh_status_var_t *val);
-typedef struct {
+typedef struct
+{
uint8_t active_low : 1; /* 1 = active low / 0 = active high */
uint8_t latched : 1; /* Signals 1 = latched / 0 = pulsed */
} lis3dsh_int_mode_t;
int32_t lis3dsh_interrupt_mode_set(stmdev_ctx_t *ctx,
- lis3dsh_int_mode_t *val);
+ lis3dsh_int_mode_t *val);
int32_t lis3dsh_interrupt_mode_get(stmdev_ctx_t *ctx,
- lis3dsh_int_mode_t *val);
+ lis3dsh_int_mode_t *val);
-typedef struct {
+typedef struct
+{
uint8_t drdy_xl : 1; /* Accelerometer data ready. */
uint8_t fifo_empty : 1; /* FIFO empty indication. */
uint8_t fifo_th : 1; /* FIFO threshold reached */
@@ -529,21 +796,24 @@ int32_t lis3dsh_pin_int1_route_set(stmdev_ctx_t *ctx,
int32_t lis3dsh_pin_int1_route_get(stmdev_ctx_t *ctx,
lis3dsh_pin_int1_route_t *val);
-typedef struct {
+typedef struct
+{
uint8_t fsm1 : 1; /* State machine 1 interrupt event */
uint8_t fsm2 : 1; /* State machine 2 interrupt event */
uint8_t boot : 1; /* Restoring calibration parameters */
} lis3dsh_pin_int2_route_t;
-int32_t lis3dsh_pin_int2_route_set(stmdev_ctx_t *ctx,
+int32_t lis3dsh_pin_int2_route_set(stmdev_ctx_t *ctx,
lis3dsh_pin_int2_route_t *val);
int32_t lis3dsh_pin_int2_route_get(stmdev_ctx_t *ctx,
lis3dsh_pin_int2_route_t *val);
-typedef struct {
+typedef struct
+{
uint8_t drdy_xl : 1; /* Accelerometer data ready */
uint8_t ovrn_xl : 1; /* Accelerometer data overrun */
uint8_t fsm_lc : 1; /* long counter flag (for both SM) */
- uint8_t fsm_ext_sync : 1; /* Synchronization with ext-host requested */
+uint8_t fsm_ext_sync :
+ 1; /* Synchronization with ext-host requested */
uint8_t fsm1_wait_fsm2 : 1; /* fsm1 wait fsm2 */
uint8_t fsm2_wait_fsm1 : 1; /* fsm2 wait fsm1 */
uint8_t fsm1 : 1; /* fsm 1 interrupt event */
@@ -556,8 +826,10 @@ typedef struct {
int32_t lis3dsh_all_sources_get(stmdev_ctx_t *ctx,
lis3dsh_all_sources_t *val);
-typedef struct {
- enum {
+typedef struct
+{
+ enum
+ {
LIS3DSH_OFF = 0x00, /* in power down */
LIS3DSH_3Hz125 = 0x01, /* Data rate @3.125 Hz */
LIS3DSH_6Hz25 = 0x02, /* Data rate @6.25 Hz */
@@ -569,7 +841,8 @@ typedef struct {
LIS3DSH_800Hz = 0x08, /* Data rate @800 Hz */
LIS3DSH_1kHz6 = 0x09, /* Data rate @1600 Hz */
} odr;
- enum {
+ enum
+ {
LIS3DSH_2g = 0,
LIS3DSH_4g = 1,
LIS3DSH_6g = 2,
@@ -580,20 +853,24 @@ typedef struct {
int32_t lis3dsh_mode_set(stmdev_ctx_t *ctx, lis3dsh_md_t *val);
int32_t lis3dsh_mode_get(stmdev_ctx_t *ctx, lis3dsh_md_t *val);
-typedef struct {
- struct {
- float mg[3];
+typedef struct
+{
+ struct
+ {
+ float_t mg[3];
int16_t raw[3];
- }xl;
- struct {
- float deg_c;
+ } xl;
+ struct
+ {
+ float_t deg_c;
int8_t raw;
- }heat;
+ } heat;
} lis3dsh_data_t;
int32_t lis3dsh_data_get(stmdev_ctx_t *ctx, lis3dsh_md_t *md,
lis3dsh_data_t *data);
-typedef enum {
+typedef enum
+{
LIS3DSH_ST_DISABLE = 0,
LIS3DSH_ST_POSITIVE = 1,
LIS3DSH_ST_NEGATIVE = 2,
diff --git a/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.c b/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.c
index 94b7c6688c53013d2c0594f11b0cd7ba0f3dd68a..9344a8b2388203d3e98d7daa05e6193777a0e838 100644
--- a/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.c
+++ b/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file lis3mdl_reg.c
- * @author Sensors Software Solution Team
- * @brief LIS3MDL driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lis3mdl_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LIS3MDL driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lis3mdl_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3mdl_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lis3mdl_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t lis3mdl_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3mdl_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lis3mdl_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -84,29 +90,29 @@ int32_t lis3mdl_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
*
*/
-float lis3mdl_from_fs4_to_gauss(int16_t lsb)
+float_t lis3mdl_from_fs4_to_gauss(int16_t lsb)
{
- return ((float)lsb / 6842.0f);
+ return ((float_t)lsb / 6842.0f);
}
-float lis3mdl_from_fs8_to_gauss(int16_t lsb)
+float_t lis3mdl_from_fs8_to_gauss(int16_t lsb)
{
- return ((float)lsb / 3421.0f);
+ return ((float_t)lsb / 3421.0f);
}
-float lis3mdl_from_fs12_to_gauss(int16_t lsb)
+float_t lis3mdl_from_fs12_to_gauss(int16_t lsb)
{
- return ((float)lsb / 2281.0f);
+ return ((float_t)lsb / 2281.0f);
}
-float lis3mdl_from_fs16_to_gauss(int16_t lsb)
+float_t lis3mdl_from_fs16_to_gauss(int16_t lsb)
{
- return ((float)lsb / 1711.0f);
+ return ((float_t)lsb / 1711.0f);
}
-float lis3mdl_from_lsb_to_celsius(int16_t lsb)
+float_t lis3mdl_from_lsb_to_celsius(int16_t lsb)
{
- return ((float)lsb / 8.0f ) + ( 25.0f );
+ return ((float_t)lsb / 8.0f) + (25.0f);
}
/**
@@ -136,24 +142,25 @@ int32_t lis3mdl_data_rate_set(stmdev_ctx_t *ctx, lis3mdl_om_t val)
lis3mdl_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
if (ret == 0)
{
ctrl_reg1.om = (uint8_t)val;
- ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
}
-
+
if (ret == 0)
{
/* set mode also for z axis, ctrl_reg4 -> omz */
- ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
}
-
+
if (ret == 0)
{
ctrl_reg4.omz = (uint8_t)(((uint8_t) val >> 4) & 0x03U);
ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
}
return ret;
@@ -173,108 +180,142 @@ int32_t lis3mdl_data_rate_get(stmdev_ctx_t *ctx, lis3mdl_om_t *val)
int32_t ret;
/* z axis, ctrl_reg4 -> omz is aligned with x/y axis ctrl_reg1 -> om*/
- ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
switch (ctrl_reg1.om)
{
case LIS3MDL_LP_Hz625:
*val = LIS3MDL_LP_Hz625;
break;
+
case LIS3MDL_LP_1kHz:
*val = LIS3MDL_LP_1kHz;
break;
+
case LIS3MDL_MP_560Hz:
*val = LIS3MDL_MP_560Hz;
break;
+
case LIS3MDL_HP_300Hz:
*val = LIS3MDL_HP_300Hz;
break;
+
case LIS3MDL_UHP_155Hz:
*val = LIS3MDL_UHP_155Hz;
break;
+
case LIS3MDL_LP_1Hz25:
*val = LIS3MDL_LP_1Hz25;
break;
+
case LIS3MDL_LP_2Hz5:
*val = LIS3MDL_LP_2Hz5;
break;
+
case LIS3MDL_LP_5Hz:
*val = LIS3MDL_LP_5Hz;
break;
+
case LIS3MDL_LP_10Hz:
*val = LIS3MDL_LP_10Hz;
break;
+
case LIS3MDL_LP_20Hz:
*val = LIS3MDL_LP_20Hz;
break;
+
case LIS3MDL_LP_40Hz:
*val = LIS3MDL_LP_40Hz;
break;
+
case LIS3MDL_LP_80Hz:
*val = LIS3MDL_LP_80Hz;
break;
+
case LIS3MDL_MP_1Hz25:
*val = LIS3MDL_MP_1Hz25;
break;
+
case LIS3MDL_MP_2Hz5:
*val = LIS3MDL_MP_2Hz5;
break;
+
case LIS3MDL_MP_5Hz:
*val = LIS3MDL_MP_5Hz;
break;
+
case LIS3MDL_MP_10Hz:
*val = LIS3MDL_MP_10Hz;
break;
+
case LIS3MDL_MP_20Hz:
*val = LIS3MDL_MP_20Hz;
break;
+
case LIS3MDL_MP_40Hz:
*val = LIS3MDL_MP_40Hz;
break;
+
case LIS3MDL_MP_80Hz:
*val = LIS3MDL_MP_80Hz;
break;
+
case LIS3MDL_HP_1Hz25:
*val = LIS3MDL_HP_1Hz25;
break;
+
case LIS3MDL_HP_2Hz5:
*val = LIS3MDL_HP_2Hz5;
break;
+
case LIS3MDL_HP_5Hz:
*val = LIS3MDL_HP_5Hz;
break;
+
case LIS3MDL_HP_10Hz:
*val = LIS3MDL_HP_10Hz;
break;
+
case LIS3MDL_HP_20Hz:
*val = LIS3MDL_HP_20Hz;
break;
+
case LIS3MDL_HP_40Hz:
*val = LIS3MDL_HP_40Hz;
break;
+
case LIS3MDL_HP_80Hz:
*val = LIS3MDL_HP_80Hz;
break;
+
case LIS3MDL_UHP_1Hz25:
*val = LIS3MDL_UHP_1Hz25;
break;
+
case LIS3MDL_UHP_2Hz5:
*val = LIS3MDL_UHP_2Hz5;
break;
+
case LIS3MDL_UHP_5Hz:
*val = LIS3MDL_UHP_5Hz;
break;
+
case LIS3MDL_UHP_10Hz:
*val = LIS3MDL_UHP_10Hz;
break;
+
case LIS3MDL_UHP_20Hz:
*val = LIS3MDL_UHP_20Hz;
break;
+
case LIS3MDL_UHP_40Hz:
*val = LIS3MDL_UHP_40Hz;
break;
+
case LIS3MDL_UHP_80Hz:
*val = LIS3MDL_UHP_80Hz;
break;
+
default:
*val = LIS3MDL_UHP_80Hz;
break;
@@ -296,12 +337,14 @@ int32_t lis3mdl_temperature_meas_set(stmdev_ctx_t *ctx, uint8_t val)
lis3mdl_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0)
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
{
ctrl_reg1.temp_en = val;
- ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -318,7 +361,7 @@ int32_t lis3mdl_temperature_meas_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3mdl_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
*val = (uint8_t)ctrl_reg1.temp_en;
return ret;
@@ -337,12 +380,14 @@ int32_t lis3mdl_full_scale_set(stmdev_ctx_t *ctx, lis3mdl_fs_t val)
lis3mdl_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0)
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
{
ctrl_reg2.fs = (uint8_t)val;
- ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -359,21 +404,26 @@ int32_t lis3mdl_full_scale_get(stmdev_ctx_t *ctx, lis3mdl_fs_t *val)
lis3mdl_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
switch (ctrl_reg2.fs)
{
case LIS3MDL_4_GAUSS:
*val = LIS3MDL_4_GAUSS;
break;
+
case LIS3MDL_8_GAUSS:
*val = LIS3MDL_8_GAUSS;
break;
+
case LIS3MDL_12_GAUSS:
*val = LIS3MDL_12_GAUSS;
break;
+
case LIS3MDL_16_GAUSS:
*val = LIS3MDL_16_GAUSS;
break;
+
default:
*val = LIS3MDL_4_GAUSS;
break;
@@ -390,16 +440,18 @@ int32_t lis3mdl_full_scale_get(stmdev_ctx_t *ctx, lis3mdl_fs_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3mdl_operating_mode_set(stmdev_ctx_t *ctx, lis3mdl_md_t val)
+int32_t lis3mdl_operating_mode_set(stmdev_ctx_t *ctx,
+ lis3mdl_md_t val)
{
lis3mdl_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0)
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
{
ctrl_reg3.md = (uint8_t)val;
- ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
}
return ret;
@@ -413,27 +465,33 @@ int32_t lis3mdl_operating_mode_set(stmdev_ctx_t *ctx, lis3mdl_md_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3mdl_operating_mode_get(stmdev_ctx_t *ctx, lis3mdl_md_t *val)
+int32_t lis3mdl_operating_mode_get(stmdev_ctx_t *ctx,
+ lis3mdl_md_t *val)
{
lis3mdl_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
switch (ctrl_reg3.md)
{
case LIS3MDL_CONTINUOUS_MODE:
*val = LIS3MDL_CONTINUOUS_MODE;
break;
+
case LIS3MDL_SINGLE_TRIGGER:
*val = LIS3MDL_SINGLE_TRIGGER;
break;
+
case LIS3MDL_POWER_DOWN:
*val = LIS3MDL_POWER_DOWN;
break;
+
default:
*val = LIS3MDL_POWER_DOWN;
break;
}
+
return ret;
}
@@ -450,12 +508,14 @@ int32_t lis3mdl_fast_low_power_set(stmdev_ctx_t *ctx, uint8_t val)
lis3mdl_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0)
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
{
ctrl_reg3.lp = val;
- ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -472,7 +532,7 @@ int32_t lis3mdl_fast_low_power_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3mdl_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
*val = (uint8_t)ctrl_reg3.lp;
return ret;
@@ -491,12 +551,14 @@ int32_t lis3mdl_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
lis3mdl_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if(ret == 0)
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
{
ctrl_reg5.bdu = val;
- ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
}
+
return ret;
}
@@ -513,7 +575,7 @@ int32_t lis3mdl_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3mdl_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
*val = (uint8_t)ctrl_reg5.bdu;
return ret;
@@ -533,11 +595,12 @@ int32_t lis3mdl_high_part_cycle_set(stmdev_ctx_t *ctx, uint8_t val)
lis3mdl_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
- if(ret == 0)
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
+
+ if (ret == 0)
{
ctrl_reg5.fast_read = val;
- ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
}
return ret;
@@ -557,7 +620,7 @@ int32_t lis3mdl_high_part_cycle_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3mdl_ctrl_reg5_t ctrl_reg5;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
*val = (uint8_t)ctrl_reg5.fast_read;
return ret;
@@ -576,7 +639,8 @@ int32_t lis3mdl_mag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3mdl_status_reg_t status_reg;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_STATUS_REG, (uint8_t*)&status_reg, 1);
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_STATUS_REG,
+ (uint8_t *)&status_reg, 1);
*val = (uint8_t)status_reg.zyxda;
return ret;
@@ -595,7 +659,8 @@ int32_t lis3mdl_mag_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3mdl_status_reg_t status_reg;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_STATUS_REG, (uint8_t*)&status_reg, 1);
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_STATUS_REG,
+ (uint8_t *)&status_reg, 1);
*val = (uint8_t)status_reg.zyxor;
return ret;
@@ -608,10 +673,19 @@ int32_t lis3mdl_mag_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3mdl_magnetic_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lis3mdl_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_OUT_X_L, (uint8_t*) buff, 6);
+
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_OUT_X_L, (uint8_t *) buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
/**
@@ -622,12 +696,18 @@ int32_t lis3mdl_magnetic_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3mdl_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lis3mdl_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
- int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_TEMP_OUT_L, (uint8_t*) buff, 2);
+ uint8_t buff[2];
+ int32_t ret;
+
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_TEMP_OUT_L, (uint8_t *) buff, 2);
+ *val = (int16_t)buff[1];
+ *val = (*val * 256) + (int16_t)buff[0];
+
return ret;
}
+
/**
* @}
*
@@ -635,7 +715,7 @@ int32_t lis3mdl_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
/**
* @defgroup LIS3MDL_Common
- * @brief This section group common usefull functions
+ * @brief This section group common useful functions
* @{
*
*/
@@ -650,8 +730,10 @@ int32_t lis3mdl_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
*/
int32_t lis3mdl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
- int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_WHO_AM_I, (uint8_t*) buff, 1);
+ int32_t ret;
+
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_WHO_AM_I, (uint8_t *) buff, 1);
+
return ret;
}
/**
@@ -667,12 +749,14 @@ int32_t lis3mdl_self_test_set(stmdev_ctx_t *ctx, uint8_t val)
lis3mdl_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0)
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
{
ctrl_reg1.st = (uint8_t)val;
- ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -689,7 +773,7 @@ int32_t lis3mdl_self_test_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3mdl_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
*val = (uint8_t)ctrl_reg1.st;
return ret;
@@ -708,12 +792,14 @@ int32_t lis3mdl_reset_set(stmdev_ctx_t *ctx, uint8_t val)
lis3mdl_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0)
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
{
ctrl_reg2.soft_rst = val;
- ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -730,7 +816,7 @@ int32_t lis3mdl_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3mdl_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
*val = (uint8_t)ctrl_reg2.soft_rst;
return ret;
@@ -749,11 +835,12 @@ int32_t lis3mdl_boot_set(stmdev_ctx_t *ctx, uint8_t val)
lis3mdl_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0)
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
{
ctrl_reg2.reboot = val;
- ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
return ret;
@@ -772,7 +859,7 @@ int32_t lis3mdl_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3mdl_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
*val = (uint8_t)ctrl_reg2.reboot;
return ret;
@@ -791,12 +878,14 @@ int32_t lis3mdl_data_format_set(stmdev_ctx_t *ctx, lis3mdl_ble_t val)
lis3mdl_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0)
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
{
ctrl_reg4.ble = (uint8_t)val;
- ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -813,19 +902,23 @@ int32_t lis3mdl_data_format_get(stmdev_ctx_t *ctx, lis3mdl_ble_t *val)
lis3mdl_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
switch (ctrl_reg4.ble)
{
case LIS3MDL_LSB_AT_LOW_ADD:
*val = LIS3MDL_LSB_AT_LOW_ADD;
break;
+
case LIS3MDL_MSB_AT_LOW_ADD:
*val = LIS3MDL_MSB_AT_LOW_ADD;
break;
+
default:
*val = LIS3MDL_LSB_AT_LOW_ADD;
break;
}
+
return ret;
}
@@ -837,9 +930,10 @@ int32_t lis3mdl_data_format_get(stmdev_ctx_t *ctx, lis3mdl_ble_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3mdl_status_get(stmdev_ctx_t *ctx, lis3mdl_status_reg_t *val)
+int32_t lis3mdl_status_get(stmdev_ctx_t *ctx,
+ lis3mdl_status_reg_t *val)
{
- return lis3mdl_read_reg(ctx, LIS3MDL_STATUS_REG, (uint8_t*) val, 1);
+ return lis3mdl_read_reg(ctx, LIS3MDL_STATUS_REG, (uint8_t *) val, 1);
}
/**
* @}
@@ -861,9 +955,10 @@ int32_t lis3mdl_status_get(stmdev_ctx_t *ctx, lis3mdl_status_reg_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3mdl_int_config_set(stmdev_ctx_t *ctx, lis3mdl_int_cfg_t *val)
+int32_t lis3mdl_int_config_set(stmdev_ctx_t *ctx,
+ lis3mdl_int_cfg_t *val)
{
- return lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t*) val, 1);
+ return lis3mdl_write_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *) val, 1);
}
/**
@@ -874,9 +969,10 @@ int32_t lis3mdl_int_config_set(stmdev_ctx_t *ctx, lis3mdl_int_cfg_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3mdl_int_config_get(stmdev_ctx_t *ctx, lis3mdl_int_cfg_t *val)
+int32_t lis3mdl_int_config_get(stmdev_ctx_t *ctx,
+ lis3mdl_int_cfg_t *val)
{
- return lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t*) val, 1);
+ return lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *) val, 1);
}
/**
* @brief Interrupt enable on INT pin[set]
@@ -891,11 +987,12 @@ int32_t lis3mdl_int_generation_set(stmdev_ctx_t *ctx, uint8_t val)
lis3mdl_int_cfg_t int_cfg;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t*)&int_cfg, 1);
- if(ret == 0)
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
+
+ if (ret == 0)
{
int_cfg.ien = val;
- ret = lis3mdl_write_reg(ctx, LIS3MDL_INT_CFG, (uint8_t*)&int_cfg, 1);
+ ret = lis3mdl_write_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
}
return ret;
@@ -914,7 +1011,7 @@ int32_t lis3mdl_int_generation_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3mdl_int_cfg_t int_cfg;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t*)&int_cfg, 1);
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
*val = (uint8_t)int_cfg.ien;
return ret;
@@ -930,17 +1027,19 @@ int32_t lis3mdl_int_generation_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lis3mdl_int_notification_mode_set(stmdev_ctx_t *ctx,
- lis3mdl_lir_t val)
+ lis3mdl_lir_t val)
{
lis3mdl_int_cfg_t int_cfg;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t*)&int_cfg, 1);
- if(ret == 0)
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
+
+ if (ret == 0)
{
int_cfg.lir = (uint8_t)val;
- ret = lis3mdl_write_reg(ctx, LIS3MDL_INT_CFG, (uint8_t*)&int_cfg, 1);
+ ret = lis3mdl_write_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
}
+
return ret;
}
@@ -954,20 +1053,23 @@ int32_t lis3mdl_int_notification_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lis3mdl_int_notification_mode_get(stmdev_ctx_t *ctx,
- lis3mdl_lir_t *val)
+ lis3mdl_lir_t *val)
{
lis3mdl_int_cfg_t int_cfg;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t*)&int_cfg, 1);
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
+
switch (int_cfg.lir)
{
case LIS3MDL_INT_PULSED:
*val = LIS3MDL_INT_PULSED;
break;
+
case LIS3MDL_INT_LATCHED:
*val = LIS3MDL_INT_LATCHED;
break;
+
default:
*val = LIS3MDL_INT_PULSED;
break;
@@ -989,11 +1091,12 @@ int32_t lis3mdl_int_polarity_set(stmdev_ctx_t *ctx, lis3mdl_iea_t val)
lis3mdl_int_cfg_t int_cfg;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t*)&int_cfg, 1);
- if(ret == 0)
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
+
+ if (ret == 0)
{
int_cfg.iea = (uint8_t)val;
- ret = lis3mdl_write_reg(ctx, LIS3MDL_INT_CFG, (uint8_t*)&int_cfg, 1);
+ ret = lis3mdl_write_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
}
return ret;
@@ -1007,24 +1110,29 @@ int32_t lis3mdl_int_polarity_set(stmdev_ctx_t *ctx, lis3mdl_iea_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3mdl_int_polarity_get(stmdev_ctx_t *ctx, lis3mdl_iea_t *val)
+int32_t lis3mdl_int_polarity_get(stmdev_ctx_t *ctx,
+ lis3mdl_iea_t *val)
{
lis3mdl_int_cfg_t int_cfg;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t*)&int_cfg, 1);
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
+
switch (int_cfg.iea)
{
case LIS3MDL_ACTIVE_HIGH:
*val = LIS3MDL_ACTIVE_HIGH;
break;
+
case LIS3MDL_ACTIVE_LOW:
*val = LIS3MDL_ACTIVE_LOW;
break;
+
default:
*val = LIS3MDL_ACTIVE_HIGH;
break;
}
+
return ret;
}
@@ -1041,12 +1149,14 @@ int32_t lis3mdl_int_on_z_ax_set(stmdev_ctx_t *ctx, uint8_t val)
lis3mdl_int_cfg_t int_cfg;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t*)&int_cfg, 1);
- if(ret == 0)
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
+
+ if (ret == 0)
{
int_cfg.zien = val;
- ret = lis3mdl_write_reg(ctx, LIS3MDL_INT_CFG, (uint8_t*)&int_cfg, 1);
+ ret = lis3mdl_write_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
}
+
return ret;
}
@@ -1063,7 +1173,7 @@ int32_t lis3mdl_int_on_z_ax_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3mdl_int_cfg_t int_cfg;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t*)&int_cfg, 1);
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
*val = (uint8_t)int_cfg.zien;
return ret;
@@ -1082,12 +1192,14 @@ int32_t lis3mdl_int_on_y_ax_set(stmdev_ctx_t *ctx, uint8_t val)
lis3mdl_int_cfg_t int_cfg;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t*)&int_cfg, 1);
- if(ret == 0)
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
+
+ if (ret == 0)
{
int_cfg.yien = val;
- ret = lis3mdl_write_reg(ctx, LIS3MDL_INT_CFG, (uint8_t*)&int_cfg, 1);
+ ret = lis3mdl_write_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
}
+
return ret;
}
@@ -1104,7 +1216,7 @@ int32_t lis3mdl_int_on_y_ax_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3mdl_int_cfg_t int_cfg;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t*)&int_cfg, 1);
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
*val = (uint8_t)int_cfg.yien;
return ret;
@@ -1123,11 +1235,12 @@ int32_t lis3mdl_int_on_x_ax_set(stmdev_ctx_t *ctx, uint8_t val)
lis3mdl_int_cfg_t int_cfg;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t*)&int_cfg, 1);
- if(ret == 0)
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
+
+ if (ret == 0)
{
int_cfg.xien = val;
- ret = lis3mdl_write_reg(ctx, LIS3MDL_INT_CFG, (uint8_t*)&int_cfg, 1);
+ ret = lis3mdl_write_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
}
return ret;
@@ -1146,7 +1259,7 @@ int32_t lis3mdl_int_on_x_ax_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3mdl_int_cfg_t int_cfg;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t*)&int_cfg, 1);
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1);
*val = (uint8_t)int_cfg.xien;
return ret;
@@ -1160,9 +1273,10 @@ int32_t lis3mdl_int_on_x_ax_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3mdl_int_source_get(stmdev_ctx_t *ctx, lis3mdl_int_src_t *val)
+int32_t lis3mdl_int_source_get(stmdev_ctx_t *ctx,
+ lis3mdl_int_src_t *val)
{
- return lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t*) val, 1);
+ return lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t *) val, 1);
}
/**
@@ -1173,12 +1287,13 @@ int32_t lis3mdl_int_source_get(stmdev_ctx_t *ctx, lis3mdl_int_src_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3mdl_interrupt_event_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis3mdl_interrupt_event_flag_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis3mdl_int_src_t int_src;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t*)&int_src, 1);
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t *)&int_src, 1);
*val = (uint8_t)int_src.int_;
return ret;
@@ -1192,12 +1307,13 @@ int32_t lis3mdl_interrupt_event_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3mdl_int_mag_over_range_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lis3mdl_int_mag_over_range_flag_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lis3mdl_int_src_t int_src;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t*)&int_src, 1);
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t *)&int_src, 1);
*val = (uint8_t)int_src.mroi;
return ret;
@@ -1216,7 +1332,7 @@ int32_t lis3mdl_int_neg_z_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3mdl_int_src_t int_src;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t*)&int_src, 1);
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t *)&int_src, 1);
*val = (uint8_t)int_src.nth_z;
return ret;
@@ -1235,7 +1351,7 @@ int32_t lis3mdl_int_neg_y_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3mdl_int_src_t int_src;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t*)&int_src, 1);
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t *)&int_src, 1);
*val = (uint8_t)int_src.nth_y;
return ret;
@@ -1253,7 +1369,7 @@ int32_t lis3mdl_int_neg_x_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3mdl_int_src_t int_src;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t*)&int_src, 1);
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t *)&int_src, 1);
*val = (uint8_t)int_src.nth_x;
return ret;
@@ -1271,7 +1387,7 @@ int32_t lis3mdl_int_pos_z_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3mdl_int_src_t int_src;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t*)&int_src, 1);
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t *)&int_src, 1);
*val = (uint8_t)int_src.pth_z;
return ret;
@@ -1289,7 +1405,7 @@ int32_t lis3mdl_int_pos_y_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3mdl_int_src_t int_src;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t*)&int_src, 1);
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t *)&int_src, 1);
*val = (uint8_t)int_src.pth_y;
return ret;
@@ -1307,7 +1423,7 @@ int32_t lis3mdl_int_pos_x_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lis3mdl_int_src_t int_src;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t*)&int_src, 1);
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t *)&int_src, 1);
*val = (uint8_t)int_src.pth_x;
return ret;
@@ -1320,9 +1436,16 @@ int32_t lis3mdl_int_pos_x_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3mdl_int_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lis3mdl_int_threshold_set(stmdev_ctx_t *ctx, uint16_t val)
{
- return lis3mdl_read_reg(ctx, LIS3MDL_INT_THS_L, buff, 2);
+ uint8_t buff[2];
+ int32_t ret;
+
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
+ ret = lis3mdl_write_reg(ctx, LIS3MDL_INT_THS_L, buff, 2);
+
+ return ret;
}
/**
@@ -1333,10 +1456,18 @@ int32_t lis3mdl_int_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lis3mdl_int_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lis3mdl_int_threshold_get(stmdev_ctx_t *ctx, uint16_t *val)
{
- return lis3mdl_read_reg(ctx, LIS3MDL_INT_THS_L, buff, 2);
+ uint8_t buff[2];
+ int32_t ret;
+
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_THS_L, buff, 2);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
+
+ return ret;
}
+
/**
* @}
*
@@ -1363,12 +1494,14 @@ int32_t lis3mdl_spi_mode_set(stmdev_ctx_t *ctx, lis3mdl_sim_t val)
lis3mdl_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0)
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
{
ctrl_reg3.sim = (uint8_t)val;
- ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1385,19 +1518,23 @@ int32_t lis3mdl_spi_mode_get(stmdev_ctx_t *ctx, lis3mdl_sim_t *val)
lis3mdl_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
switch (ctrl_reg3.sim)
{
case LIS3MDL_SPI_4_WIRE:
*val = LIS3MDL_SPI_4_WIRE;
break;
+
case LIS3MDL_SPI_3_WIRE:
*val = LIS3MDL_SPI_3_WIRE;
break;
+
default:
*val = LIS3MDL_SPI_4_WIRE;
break;
}
+
return ret;
}
diff --git a/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.h b/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.h
index fac64195b2279629e20422ce826505e3a5f3c28e..621a209ecc3bedc7cf4ef0754c406f9e960f13d4 100644
--- a/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.h
+++ b/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file lis3mdl_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lis3mdl_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lis3mdl_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lis3mdl_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LIS3MDL_REGS_H
#define LIS3MDL_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup LIS3MDL
@@ -35,6 +36,37 @@
*
*/
+/** @defgroup Endianness definitions
+ * @{
+ *
+ */
+
+#ifndef DRV_BYTE_ORDER
+#ifndef __BYTE_ORDER__
+
+#define DRV_LITTLE_ENDIAN 1234
+#define DRV_BIG_ENDIAN 4321
+
+/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
+ * by uncommenting the define which fits your platform endianness
+ */
+//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
+#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
+
+#else /* defined __BYTE_ORDER__ */
+
+#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
+#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
+#define DRV_BYTE_ORDER __BYTE_ORDER__
+
+#endif /* __BYTE_ORDER__*/
+#endif /* DRV_BYTE_ORDER */
+
+/**
+ * @}
+ *
+ */
+
/** @defgroup STMicroelectronics sensors common types
* @{
*
@@ -43,7 +75,9 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -52,6 +86,16 @@ typedef struct{
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} bitwise_t;
#define PROPERTY_DISABLE (0U)
@@ -65,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -89,15 +134,16 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
- * Unico / Unicleo tools available on STMicroelectronics
- * web site.
+ * You can create a sensor configuration by your own or using
+ * Unico / Unicleo tools available on STMicroelectronics
+ * web site.
*
* @{
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -126,35 +172,6 @@ typedef struct {
/** Device Identification (Who am I) **/
#define LIS3MDL_ID 0x3DU
-/**
- * @}
- *
- */
-
-/**
- * @addtogroup LIS3MDL_Sensitivity
- * @brief These macro are maintained for back compatibility.
- * in order to convert data into engineering units please
- * use functions:
- * -> _from_fs4_to_gauss(int16_t lsb);
- * -> _from_fs8_to_gauss(int16_t lsb);
- * -> _from_fs12_to_gauss(int16_t lsb);
- * -> _from_fs16_to_gauss(int16_t lsb);
- * -> _from_lsb_to_celsius(int16_t lsb);
- *
- * REMOVING the MACRO you are compliant with:
- * MISRA-C 2012 [Dir 4.9] -> " avoid function-like macros "
- * @{
- *
- */
-
-#define LIS3MDL_FROM_FS_4G_TO_G(lsb) (float)( lsb / 6842.0f )
-#define LIS3MDL_FROM_FS_8G_TO_G(lsb) (float)( lsb / 3421.0f )
-#define LIS3MDL_FROM_FS_12G_TO_G(lsb) (float)( lsb / 2281.0f )
-#define LIS3MDL_FROM_FS_16G_TO_G(lsb) (float)( lsb / 1711.0f )
-
-#define LIS3MDL_FROM_LSB_TO_degC(lsb) (float)(lsb / 8.0f ) + ( 25.0f )
-
/**
* @}
*
@@ -162,49 +179,91 @@ typedef struct {
#define LIS3MDL_WHO_AM_I 0x0FU
#define LIS3MDL_CTRL_REG1 0x20U
-typedef struct{
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st : 1;
uint8_t om : 6; /* om + do + fast_odr -> om */
uint8_t temp_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t temp_en : 1;
+ uint8_t om : 6; /* om + do + fast_odr -> om */
+ uint8_t st : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3mdl_ctrl_reg1_t;
#define LIS3MDL_CTRL_REG2 0x21U
typedef struct
{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t soft_rst : 1;
uint8_t reboot : 1;
uint8_t not_used_02 : 1;
uint8_t fs : 2;
uint8_t not_used_03 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_03 : 1;
+ uint8_t fs : 2;
+ uint8_t not_used_02 : 1;
+ uint8_t reboot : 1;
+ uint8_t soft_rst : 1;
+ uint8_t not_used_01 : 2;
+#endif /* DRV_BYTE_ORDER */
} lis3mdl_ctrl_reg2_t;
#define LIS3MDL_CTRL_REG3 0x22U
-typedef struct{
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t md : 2;
uint8_t sim : 1;
uint8_t not_used_01 : 2;
uint8_t lp : 1;
uint8_t not_used_02 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 2;
+ uint8_t lp : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t sim : 1;
+ uint8_t md : 2;
+#endif /* DRV_BYTE_ORDER */
} lis3mdl_ctrl_reg3_t;
#define LIS3MDL_CTRL_REG4 0x23U
-typedef struct{
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t ble : 1;
uint8_t omz : 2;
uint8_t not_used_02 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 4;
+ uint8_t omz : 2;
+ uint8_t ble : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3mdl_ctrl_reg4_t;
#define LIS3MDL_CTRL_REG5 0x24U
-typedef struct{
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 6;
uint8_t bdu : 1;
uint8_t fast_read : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fast_read : 1;
+ uint8_t bdu : 1;
+ uint8_t not_used_01 : 6;
+#endif /* DRV_BYTE_ORDER */
} lis3mdl_ctrl_reg5_t;
#define LIS3MDL_STATUS_REG 0x27U
-typedef struct{
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xda : 1;
uint8_t yda : 1;
uint8_t zda : 1;
@@ -213,6 +272,16 @@ typedef struct{
uint8_t yor : 1;
uint8_t zor : 1;
uint8_t zyxor : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t zyxor : 1;
+ uint8_t zor : 1;
+ uint8_t yor : 1;
+ uint8_t _xor : 1;
+ uint8_t zyxda : 1;
+ uint8_t zda : 1;
+ uint8_t yda : 1;
+ uint8_t xda : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3mdl_status_reg_t;
#define LIS3MDL_OUT_X_L 0x28U
@@ -224,7 +293,9 @@ typedef struct{
#define LIS3MDL_TEMP_OUT_L 0x2EU
#define LIS3MDL_TEMP_OUT_H 0x2FU
#define LIS3MDL_INT_CFG 0x30U
-typedef struct{
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ien : 1;
uint8_t lir : 1;
uint8_t iea : 1;
@@ -232,10 +303,21 @@ typedef struct{
uint8_t zien : 1;
uint8_t yien : 1;
uint8_t xien : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t xien : 1;
+ uint8_t yien : 1;
+ uint8_t zien : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t iea : 1;
+ uint8_t lir : 1;
+ uint8_t ien : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3mdl_int_cfg_t;
#define LIS3MDL_INT_SRC 0x31U
-typedef struct{
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int_ : 1;
uint8_t mroi : 1;
uint8_t nth_z : 1;
@@ -244,6 +326,16 @@ typedef struct{
uint8_t pth_z : 1;
uint8_t pth_y : 1;
uint8_t pth_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t pth_x : 1;
+ uint8_t pth_y : 1;
+ uint8_t pth_z : 1;
+ uint8_t nth_x : 1;
+ uint8_t nth_y : 1;
+ uint8_t nth_z : 1;
+ uint8_t mroi : 1;
+ uint8_t int_ : 1;
+#endif /* DRV_BYTE_ORDER */
} lis3mdl_int_src_t;
#define LIS3MDL_INT_THS_L 0x32U
@@ -251,9 +343,9 @@ typedef struct{
/**
* @defgroup LIS3MDL_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -261,7 +353,8 @@ typedef struct{
* @{
*
*/
-typedef union{
+typedef union
+{
lis3mdl_ctrl_reg1_t ctrl_reg1;
lis3mdl_ctrl_reg2_t ctrl_reg2;
lis3mdl_ctrl_reg3_t ctrl_reg3;
@@ -279,18 +372,22 @@ typedef union{
*
*/
-int32_t lis3mdl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lis3mdl_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t lis3mdl_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lis3mdl_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-extern float lis3mdl_from_fs4_to_gauss(int16_t lsb);
-extern float lis3mdl_from_fs8_to_gauss(int16_t lsb);
-extern float lis3mdl_from_fs12_to_gauss(int16_t lsb);
-extern float lis3mdl_from_fs16_to_gauss(int16_t lsb);
-extern float lis3mdl_from_lsb_to_celsius(int16_t lsb);
+float_t lis3mdl_from_fs4_to_gauss(int16_t lsb);
+float_t lis3mdl_from_fs8_to_gauss(int16_t lsb);
+float_t lis3mdl_from_fs12_to_gauss(int16_t lsb);
+float_t lis3mdl_from_fs16_to_gauss(int16_t lsb);
+
+float_t lis3mdl_from_lsb_to_celsius(int16_t lsb);
-typedef enum{
+typedef enum
+{
LIS3MDL_LP_Hz625 = 0x00,
LIS3MDL_LP_1kHz = 0x01,
LIS3MDL_MP_560Hz = 0x11,
@@ -336,7 +433,8 @@ int32_t lis3mdl_data_rate_get(stmdev_ctx_t *ctx, lis3mdl_om_t *val);
int32_t lis3mdl_temperature_meas_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3mdl_temperature_meas_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum{
+typedef enum
+{
LIS3MDL_4_GAUSS = 0,
LIS3MDL_8_GAUSS = 1,
LIS3MDL_12_GAUSS = 2,
@@ -345,19 +443,23 @@ typedef enum{
int32_t lis3mdl_full_scale_set(stmdev_ctx_t *ctx, lis3mdl_fs_t val);
int32_t lis3mdl_full_scale_get(stmdev_ctx_t *ctx, lis3mdl_fs_t *val);
-typedef enum{
+typedef enum
+{
LIS3MDL_CONTINUOUS_MODE = 0,
LIS3MDL_SINGLE_TRIGGER = 1,
LIS3MDL_POWER_DOWN = 2,
} lis3mdl_md_t;
-int32_t lis3mdl_operating_mode_set(stmdev_ctx_t *ctx, lis3mdl_md_t val);
-int32_t lis3mdl_operating_mode_get(stmdev_ctx_t *ctx, lis3mdl_md_t *val);
+int32_t lis3mdl_operating_mode_set(stmdev_ctx_t *ctx,
+ lis3mdl_md_t val);
+int32_t lis3mdl_operating_mode_get(stmdev_ctx_t *ctx,
+ lis3mdl_md_t *val);
int32_t lis3mdl_fast_low_power_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3mdl_fast_low_power_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis3mdl_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lis3mdl_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lis3mdl_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lis3mdl_high_part_cycle_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3mdl_high_part_cycle_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -366,9 +468,9 @@ int32_t lis3mdl_mag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis3mdl_mag_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lis3mdl_magnetic_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lis3mdl_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val);
-int32_t lis3mdl_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lis3mdl_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val);
int32_t lis3mdl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
@@ -381,22 +483,28 @@ int32_t lis3mdl_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis3mdl_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3mdl_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum{
+typedef enum
+{
LIS3MDL_LSB_AT_LOW_ADD = 0,
LIS3MDL_MSB_AT_LOW_ADD = 1,
} lis3mdl_ble_t;
int32_t lis3mdl_data_format_set(stmdev_ctx_t *ctx, lis3mdl_ble_t val);
-int32_t lis3mdl_data_format_get(stmdev_ctx_t *ctx, lis3mdl_ble_t *val);
+int32_t lis3mdl_data_format_get(stmdev_ctx_t *ctx,
+ lis3mdl_ble_t *val);
-int32_t lis3mdl_status_get(stmdev_ctx_t *ctx, lis3mdl_status_reg_t *val);
+int32_t lis3mdl_status_get(stmdev_ctx_t *ctx,
+ lis3mdl_status_reg_t *val);
-int32_t lis3mdl_int_config_set(stmdev_ctx_t *ctx, lis3mdl_int_cfg_t *val);
-int32_t lis3mdl_int_config_get(stmdev_ctx_t *ctx, lis3mdl_int_cfg_t *val);
+int32_t lis3mdl_int_config_set(stmdev_ctx_t *ctx,
+ lis3mdl_int_cfg_t *val);
+int32_t lis3mdl_int_config_get(stmdev_ctx_t *ctx,
+ lis3mdl_int_cfg_t *val);
int32_t lis3mdl_int_generation_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3mdl_int_generation_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum{
+typedef enum
+{
LIS3MDL_INT_PULSED = 0,
LIS3MDL_INT_LATCHED = 1,
} lis3mdl_lir_t;
@@ -405,12 +513,15 @@ int32_t lis3mdl_int_notification_mode_set(stmdev_ctx_t *ctx,
int32_t lis3mdl_int_notification_mode_get(stmdev_ctx_t *ctx,
lis3mdl_lir_t *val);
-typedef enum{
+typedef enum
+{
LIS3MDL_ACTIVE_HIGH = 0,
LIS3MDL_ACTIVE_LOW = 1,
} lis3mdl_iea_t;
-int32_t lis3mdl_int_polarity_set(stmdev_ctx_t *ctx, lis3mdl_iea_t val);
-int32_t lis3mdl_int_polarity_get(stmdev_ctx_t *ctx, lis3mdl_iea_t *val);
+int32_t lis3mdl_int_polarity_set(stmdev_ctx_t *ctx,
+ lis3mdl_iea_t val);
+int32_t lis3mdl_int_polarity_get(stmdev_ctx_t *ctx,
+ lis3mdl_iea_t *val);
int32_t lis3mdl_int_on_z_ax_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3mdl_int_on_z_ax_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -421,13 +532,14 @@ int32_t lis3mdl_int_on_y_ax_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis3mdl_int_on_x_ax_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lis3mdl_int_on_x_ax_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lis3mdl_int_source_get(stmdev_ctx_t *ctx, lis3mdl_int_src_t *val);
+int32_t lis3mdl_int_source_get(stmdev_ctx_t *ctx,
+ lis3mdl_int_src_t *val);
int32_t lis3mdl_interrupt_event_flag_get(stmdev_ctx_t *ctx,
- uint8_t *val);
+ uint8_t *val);
int32_t lis3mdl_int_mag_over_range_flag_get(stmdev_ctx_t *ctx,
- uint8_t *val);
+ uint8_t *val);
int32_t lis3mdl_int_neg_z_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -441,10 +553,11 @@ int32_t lis3mdl_int_pos_y_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis3mdl_int_pos_x_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lis3mdl_int_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lis3mdl_int_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lis3mdl_int_threshold_set(stmdev_ctx_t *ctx, uint16_t val);
+int32_t lis3mdl_int_threshold_get(stmdev_ctx_t *ctx, uint16_t *val);
-typedef enum{
+typedef enum
+{
LIS3MDL_SPI_4_WIRE = 0,
LIS3MDL_SPI_3_WIRE = 1,
} lis3mdl_sim_t;
diff --git a/sensor/stmemsc/lps22ch_STdC/driver/lps22ch_reg.c b/sensor/stmemsc/lps22ch_STdC/driver/lps22ch_reg.c
new file mode 100644
index 0000000000000000000000000000000000000000..ece25095ffecaa22bf0601d932f9554223910fcf
--- /dev/null
+++ b/sensor/stmemsc/lps22ch_STdC/driver/lps22ch_reg.c
@@ -0,0 +1,2066 @@
+/**
+ ******************************************************************************
+ * @file lps22ch_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LPS22CH driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+#include "lps22ch_reg.h"
+
+/**
+ * @defgroup LPS22CH
+ * @brief This file provides a set of functions needed to drive the
+ * lps22ch enhanced inertial module.
+ * @{
+ *
+ */
+
+/**
+ * @defgroup LPS22CH_Interfaces_Functions
+ * @brief This section provide a set of functions used to read and
+ * write a generic register of the device.
+ * MANDATORY: return 0 -> no Error.
+ * @{
+ *
+ */
+
+/**
+ * @brief Read generic device register
+ *
+ * @param ctx read / write interface definitions(ptr)
+ * @param reg register to read
+ * @param data pointer to buffer that store the data read(ptr)
+ * @param len number of consecutive register to read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
+{
+ int32_t ret;
+
+ ret = ctx->read_reg(ctx->handle, reg, data, len);
+
+ return ret;
+}
+
+/**
+ * @brief Write generic device register
+ *
+ * @param ctx read / write interface definitions(ptr)
+ * @param reg register to write
+ * @param data pointer to data to write in register reg(ptr)
+ * @param len number of consecutive register to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
+{
+ int32_t ret;
+
+ ret = ctx->write_reg(ctx->handle, reg, data, len);
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LPS22CH_Sensitivity
+ * @brief These functions convert raw-data into engineering units.
+ * @{
+ *
+ */
+float_t lps22ch_from_lsb_to_hpa(uint32_t lsb)
+{
+ return ((float_t) lsb / 1048576.0f);
+}
+
+float_t lps22ch_from_lsb_to_celsius(int16_t lsb)
+{
+ return ((float_t) lsb / 100.0f);
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LPS22CH_Data_Generation
+ * @brief This section groups all the functions concerning
+ * data generation.
+ * @{
+ *
+ */
+
+/**
+ * @brief Reset Autozero function.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of reset_az in reg INTERRUPT_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lps22ch_interrupt_cfg_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.reset_az = val;
+ ret = lps22ch_write_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Reset Autozero function.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of reset_az in reg INTERRUPT_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lps22ch_interrupt_cfg_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
+ *val = reg.reset_az;
+
+ return ret;
+}
+
+/**
+ * @brief Enable Autozero function.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of autozero in reg INTERRUPT_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_autozero_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lps22ch_interrupt_cfg_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.autozero = val;
+ ret = lps22ch_write_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable Autozero function.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of autozero in reg INTERRUPT_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_autozero_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lps22ch_interrupt_cfg_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
+ *val = reg.autozero;
+
+ return ret;
+}
+
+/**
+ * @brief Reset AutoRifP function.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of reset_arp in reg INTERRUPT_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_pressure_snap_rst_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lps22ch_interrupt_cfg_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.reset_arp = val;
+ ret = lps22ch_write_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Reset AutoRifP function.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of reset_arp in reg INTERRUPT_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_pressure_snap_rst_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lps22ch_interrupt_cfg_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
+ *val = reg.reset_arp;
+
+ return ret;
+}
+
+/**
+ * @brief Enable AutoRefP function.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of autorefp in reg INTERRUPT_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lps22ch_interrupt_cfg_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.autorefp = val;
+ ret = lps22ch_write_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable AutoRefP function.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of autorefp in reg INTERRUPT_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lps22ch_interrupt_cfg_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
+ *val = reg.autorefp;
+
+ return ret;
+}
+
+/**
+ * @brief Block Data Update.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of bdu in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lps22ch_ctrl_reg1_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG1, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.bdu = val;
+ ret = lps22ch_write_reg(ctx, LPS22CH_CTRL_REG1, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Block Data Update.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of bdu in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lps22ch_ctrl_reg1_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG1, (uint8_t *) ®, 1);
+ *val = reg.bdu;
+
+ return ret;
+}
+
+/**
+ * @brief Output data rate selection.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of odr in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_data_rate_set(stmdev_ctx_t *ctx, lps22ch_odr_t val)
+{
+ lps22ch_ctrl_reg1_t ctrl_reg1;
+ lps22ch_ctrl_reg2_t ctrl_reg2;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
+ ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+ }
+
+ if (ret == 0)
+ {
+ ctrl_reg1.odr = (uint8_t)val & 0x07U;
+ ret = lps22ch_write_reg(ctx, LPS22CH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+ }
+
+ if (ret == 0)
+ {
+ ctrl_reg2.low_noise_en = ((uint8_t)val & 0x10U) >> 4;
+ ctrl_reg2.one_shot = ((uint8_t)val & 0x08U) >> 3;
+ ret = lps22ch_write_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Output data rate selection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of odr in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_data_rate_get(stmdev_ctx_t *ctx, lps22ch_odr_t *val)
+{
+ lps22ch_ctrl_reg1_t ctrl_reg1;
+ lps22ch_ctrl_reg2_t ctrl_reg2;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
+ ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ switch (((ctrl_reg2.low_noise_en << 4) + (ctrl_reg2.one_shot << 3) +
+ ctrl_reg1.odr))
+ {
+ case LPS22CH_POWER_DOWN:
+ *val = LPS22CH_POWER_DOWN;
+ break;
+
+ case LPS22CH_ONE_SHOOT:
+ *val = LPS22CH_ONE_SHOOT;
+ break;
+
+ case LPS22CH_1_Hz:
+ *val = LPS22CH_1_Hz;
+ break;
+
+ case LPS22CH_10_Hz:
+ *val = LPS22CH_10_Hz;
+ break;
+
+ case LPS22CH_25_Hz:
+ *val = LPS22CH_25_Hz;
+ break;
+
+ case LPS22CH_50_Hz:
+ *val = LPS22CH_50_Hz;
+ break;
+
+ case LPS22CH_75_Hz:
+ *val = LPS22CH_75_Hz;
+ break;
+
+ case LPS22CH_1_Hz_LOW_NOISE:
+ *val = LPS22CH_1_Hz_LOW_NOISE;
+ break;
+
+ case LPS22CH_10_Hz_LOW_NOISE:
+ *val = LPS22CH_10_Hz_LOW_NOISE;
+ break;
+
+ case LPS22CH_25_Hz_LOW_NOISE:
+ *val = LPS22CH_25_Hz_LOW_NOISE;
+ break;
+
+ case LPS22CH_50_Hz_LOW_NOISE:
+ *val = LPS22CH_50_Hz_LOW_NOISE;
+ break;
+
+ case LPS22CH_75_Hz_LOW_NOISE:
+ *val = LPS22CH_75_Hz_LOW_NOISE;
+ break;
+
+ case LPS22CH_100_Hz:
+ *val = LPS22CH_100_Hz;
+ break;
+
+ case LPS22CH_200_Hz:
+ *val = LPS22CH_200_Hz;
+ break;
+
+ default:
+ *val = LPS22CH_POWER_DOWN;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief The Reference pressure value is a 16-bit data
+ * expressed as 2’s complement. The value is used
+ * when AUTOZERO or AUTORIFP function is enabled.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_pressure_ref_set(stmdev_ctx_t *ctx, int16_t val)
+{
+ uint8_t buff[2];
+ int32_t ret;
+
+ buff[1] = (uint8_t)((uint16_t)val / 256U);
+ buff[0] = (uint8_t)((uint16_t)val - (buff[1] * 256U));
+ ret = lps22ch_write_reg(ctx, LPS22CH_REF_P_L, buff, 2);
+
+ return ret;
+}
+
+/**
+ * @brief The Reference pressure value is a 16-bit
+ * data expressed as 2’s complement.
+ * The value is used when AUTOZERO or AUTORIFP
+ * function is enabled.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_pressure_ref_get(stmdev_ctx_t *ctx, int16_t *val)
+{
+ uint8_t buff[2];
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_REF_P_L, buff, 2);
+ *val = (int16_t)buff[1];
+ *val = (*val * 256) + (int16_t)buff[0];
+
+ return ret;
+}
+
+/**
+ * @brief The pressure offset value is 16-bit data
+ * that can be used to implement one-point
+ * calibration (OPC) after soldering.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val)
+{
+ uint8_t buff[2];
+ int32_t ret;
+
+ buff[1] = (uint8_t)((uint16_t)val / 256U);
+ buff[0] = (uint8_t)((uint16_t)val - (buff[1] * 256U));
+ ret = lps22ch_write_reg(ctx, LPS22CH_RPDS_L, buff, 2);
+
+ return ret;
+}
+
+/**
+ * @brief The pressure offset value is 16-bit
+ * data that can be used to implement
+ * one-point calibration (OPC) after
+ * soldering.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val)
+{
+ uint8_t buff[2];
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_RPDS_L, buff, 2);
+ *val = (int16_t)buff[1];
+ *val = (*val * 256) + (int16_t)buff[0];
+
+ return ret;
+}
+
+/**
+ * @brief Read all the interrupt/status flag of the device.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val registers STATUS,FIFO_STATUS2,INT_SOURCE
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_all_sources_get(stmdev_ctx_t *ctx,
+ lps22ch_all_sources_t *val)
+{
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_INT_SOURCE,
+ (uint8_t *) & (val->int_source), 1);
+
+ if (ret == 0)
+ {
+ ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_STATUS2,
+ (uint8_t *) & (val->fifo_status2), 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lps22ch_read_reg(ctx, LPS22CH_STATUS,
+ (uint8_t *) & (val->status), 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief The STATUS_REG register is read by the primary interface.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val structure of registers from STATUS to STATUS_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_status_reg_get(stmdev_ctx_t *ctx,
+ lps22ch_status_t *val)
+{
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_STATUS, (uint8_t *) val, 1);
+
+ return ret;
+}
+
+/**
+ * @brief Pressure new data available.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of p_da in reg STATUS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_press_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lps22ch_status_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_STATUS, (uint8_t *) ®, 1);
+ *val = reg.p_da;
+
+ return ret;
+}
+
+/**
+ * @brief Temperature data available.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of t_da in reg STATUS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lps22ch_status_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_STATUS, (uint8_t *) ®, 1);
+ *val = reg.t_da;
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LPS22CH_Data_Output
+ * @brief This section groups all the data output functions.
+ * @{
+ *
+ */
+
+/**
+ * @brief Pressure output value.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff)
+{
+ int32_t ret;
+
+ uint8_t reg[3];
+ ret = lps22ch_read_reg(ctx, LPS22CH_PRESS_OUT_XL, reg, 3);
+ *buff = reg[2];
+ *buff = (*buff * 256) + reg[1];
+ *buff = (*buff * 256) + reg[0];
+ *buff *= 256;
+
+ return ret;
+}
+
+/**
+ * @brief Temperature output value.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff)
+{
+ int32_t ret;
+
+ uint8_t reg[2];
+ ret = lps22ch_read_reg(ctx, LPS22CH_TEMP_OUT_L, reg, 2);
+ *buff = reg[1];
+ *buff = (*buff * 256) + reg[0];
+
+ return ret;
+}
+
+/**
+ * @brief Pressure output from FIFO value.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_fifo_pressure_raw_get(stmdev_ctx_t *ctx,
+ uint32_t *buff)
+{
+ int32_t ret;
+
+ uint8_t reg[3];
+ ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_DATA_OUT_PRESS_XL, reg, 3);
+ *buff = reg[2];
+ *buff = (*buff * 256) + reg[1];
+ *buff = (*buff * 256) + reg[0];
+ *buff *= 256;
+
+ return ret;
+}
+
+/**
+ * @brief Temperature output from FIFO value.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_fifo_temperature_raw_get(stmdev_ctx_t *ctx,
+ int16_t *buff)
+{
+ int32_t ret;
+
+ uint8_t reg[2];
+ ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_DATA_OUT_TEMP_L, reg, 2);
+ *buff = reg[1];
+ *buff = (*buff * 256) + reg[0];
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LPS22CH_Common
+ * @brief This section groups common useful functions.
+ * @{
+ *
+ */
+
+/**
+ * @brief DeviceWhoamI.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
+{
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_WHO_AM_I, buff, 1);
+
+ return ret;
+}
+
+/**
+ * @brief Software reset. Restore the default values
+ * in user registers.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of swreset in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_reset_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lps22ch_ctrl_reg2_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.swreset = val;
+ ret = lps22ch_write_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Software reset. Restore the default values
+ * in user registers.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of swreset in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lps22ch_ctrl_reg2_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1);
+ *val = reg.swreset;
+
+ return ret;
+}
+
+/**
+ * @brief Register address automatically
+ * incremented during a multiple byte access
+ * with a serial interface.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of if_add_inc in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lps22ch_ctrl_reg2_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.if_add_inc = val;
+ ret = lps22ch_write_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Register address automatically
+ * incremented during a multiple byte
+ * access with a serial interface.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of if_add_inc in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lps22ch_ctrl_reg2_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1);
+ *val = reg.if_add_inc;
+
+ return ret;
+}
+
+/**
+ * @brief Reboot memory content. Reload the calibration
+ * parameters.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of boot in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_boot_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lps22ch_ctrl_reg2_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.boot = val;
+ ret = lps22ch_write_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Reboot memory content. Reload the calibration
+ * parameters.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of boot in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lps22ch_ctrl_reg2_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1);
+ *val = reg.boot;
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LPS22CH_Filters
+ * @brief This section group all the functions concerning the
+ * filters configuration.
+ * @{
+ *
+ */
+
+/**
+ * @brief Low-pass bandwidth selection.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of lpfp_cfg in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_lp_bandwidth_set(stmdev_ctx_t *ctx,
+ lps22ch_lpfp_cfg_t val)
+{
+ lps22ch_ctrl_reg1_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG1, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.lpfp_cfg = (uint8_t)val;
+ ret = lps22ch_write_reg(ctx, LPS22CH_CTRL_REG1, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Low-pass bandwidth selection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of lpfp_cfg in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_lp_bandwidth_get(stmdev_ctx_t *ctx,
+ lps22ch_lpfp_cfg_t *val)
+{
+ lps22ch_ctrl_reg1_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG1, (uint8_t *) ®, 1);
+
+ switch (reg.lpfp_cfg)
+ {
+ case LPS22CH_LPF_ODR_DIV_2:
+ *val = LPS22CH_LPF_ODR_DIV_2;
+ break;
+
+ case LPS22CH_LPF_ODR_DIV_9:
+ *val = LPS22CH_LPF_ODR_DIV_9;
+ break;
+
+ case LPS22CH_LPF_ODR_DIV_20:
+ *val = LPS22CH_LPF_ODR_DIV_20;
+ break;
+
+ default:
+ *val = LPS22CH_LPF_ODR_DIV_2;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LPS22CH_Serial_Interface
+ * @brief This section groups all the functions concerning serial
+ * interface management
+ * @{
+ *
+ */
+
+/**
+ * @brief Enable/Disable I2C interface.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of i2c_disable in reg IF_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_i2c_interface_set(stmdev_ctx_t *ctx,
+ lps22ch_i2c_disable_t val)
+{
+ lps22ch_if_ctrl_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_IF_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.i2c_disable = (uint8_t)val;
+ ret = lps22ch_write_reg(ctx, LPS22CH_IF_CTRL, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable/Disable I2C interface.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of i2c_disable in reg IF_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_i2c_interface_get(stmdev_ctx_t *ctx,
+ lps22ch_i2c_disable_t *val)
+{
+ lps22ch_if_ctrl_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_IF_CTRL, (uint8_t *) ®, 1);
+
+ switch (reg.i2c_disable)
+ {
+ case LPS22CH_I2C_ENABLE:
+ *val = LPS22CH_I2C_ENABLE;
+ break;
+
+ case LPS22CH_I2C_DISABLE:
+ *val = LPS22CH_I2C_DISABLE;
+ break;
+
+ default:
+ *val = LPS22CH_I2C_ENABLE;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable/Disable I3C interface.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of i2c_disable in reg IF_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_i3c_interface_set(stmdev_ctx_t *ctx,
+ lps22ch_i3c_disable_t val)
+{
+ lps22ch_if_ctrl_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_IF_CTRL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.i3c_disable = (uint8_t)val;
+ reg.int_en_i3c = (uint8_t)~val;
+ ret = lps22ch_write_reg(ctx, LPS22CH_IF_CTRL, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable/Disable I3C interface.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of i2c_disable in reg IF_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_i3c_interface_get(stmdev_ctx_t *ctx,
+ lps22ch_i3c_disable_t *val)
+{
+ lps22ch_if_ctrl_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_IF_CTRL, (uint8_t *)®, 1);
+
+ switch (reg.i3c_disable)
+ {
+ case LPS22CH_I3C_ENABLE:
+ *val = LPS22CH_I3C_ENABLE;
+ break;
+
+ case LPS22CH_I3C_DISABLE:
+ *val = LPS22CH_I3C_DISABLE;
+ break;
+
+ default:
+ *val = LPS22CH_I3C_ENABLE;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable/Disable pull-up on SDO pin.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of sdo_pu_en in reg IF_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
+ lps22ch_pu_en_t val)
+{
+ lps22ch_if_ctrl_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_IF_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.sdo_pu_en = (uint8_t)val;
+ ret = lps22ch_write_reg(ctx, LPS22CH_IF_CTRL, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable/Disable pull-up on SDO pin.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of sdo_pu_en in reg IF_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
+ lps22ch_pu_en_t *val)
+{
+ lps22ch_if_ctrl_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_IF_CTRL, (uint8_t *) ®, 1);
+
+ switch (reg.sdo_pu_en)
+ {
+ case LPS22CH_PULL_UP_DISCONNECT:
+ *val = LPS22CH_PULL_UP_DISCONNECT;
+ break;
+
+ case LPS22CH_PULL_UP_CONNECT:
+ *val = LPS22CH_PULL_UP_CONNECT;
+ break;
+
+ default:
+ *val = LPS22CH_PULL_UP_DISCONNECT;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of sda_pu_en in reg IF_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_sda_mode_set(stmdev_ctx_t *ctx, lps22ch_pu_en_t val)
+{
+ lps22ch_if_ctrl_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_IF_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.sda_pu_en = (uint8_t)val;
+ ret = lps22ch_write_reg(ctx, LPS22CH_IF_CTRL, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of sda_pu_en in reg IF_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_sda_mode_get(stmdev_ctx_t *ctx, lps22ch_pu_en_t *val)
+{
+ lps22ch_if_ctrl_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_IF_CTRL, (uint8_t *) ®, 1);
+
+ switch (reg.sda_pu_en)
+ {
+ case LPS22CH_PULL_UP_DISCONNECT:
+ *val = LPS22CH_PULL_UP_DISCONNECT;
+ break;
+
+ case LPS22CH_PULL_UP_CONNECT:
+ *val = LPS22CH_PULL_UP_CONNECT;
+ break;
+
+ default:
+ *val = LPS22CH_PULL_UP_DISCONNECT;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief SPI Serial Interface Mode selection.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of sim in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_spi_mode_set(stmdev_ctx_t *ctx, lps22ch_sim_t val)
+{
+ lps22ch_ctrl_reg1_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG1, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.sim = (uint8_t)val;
+ ret = lps22ch_write_reg(ctx, LPS22CH_CTRL_REG1, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief SPI Serial Interface Mode selection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of sim in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_spi_mode_get(stmdev_ctx_t *ctx, lps22ch_sim_t *val)
+{
+ lps22ch_ctrl_reg1_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG1, (uint8_t *) ®, 1);
+
+ switch (reg.sim)
+ {
+ case LPS22CH_SPI_4_WIRE:
+ *val = LPS22CH_SPI_4_WIRE;
+ break;
+
+ case LPS22CH_SPI_3_WIRE:
+ *val = LPS22CH_SPI_3_WIRE;
+ break;
+
+ default:
+ *val = LPS22CH_SPI_4_WIRE;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LPS22CH_Interrupt_Pins
+ * @brief This section groups all the functions that manage
+ * interrupt pins.
+ * @{
+ *
+ */
+
+/**
+ * @brief Latch interrupt request to the INT_SOURCE (24h) register.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of lir in reg INTERRUPT_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_int_notification_set(stmdev_ctx_t *ctx,
+ lps22ch_lir_t val)
+{
+ lps22ch_interrupt_cfg_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.lir = (uint8_t)val;
+ ret = lps22ch_write_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Latch interrupt request to the INT_SOURCE (24h) register.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of lir in reg INTERRUPT_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_int_notification_get(stmdev_ctx_t *ctx,
+ lps22ch_lir_t *val)
+{
+ lps22ch_interrupt_cfg_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
+
+ switch (reg.lir)
+ {
+ case LPS22CH_INT_PULSED:
+ *val = LPS22CH_INT_PULSED;
+ break;
+
+ case LPS22CH_INT_LATCHED:
+ *val = LPS22CH_INT_LATCHED;
+ break;
+
+ default:
+ *val = LPS22CH_INT_PULSED;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Push-pull/open drain selection on interrupt pads.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of pp_od in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_pin_mode_set(stmdev_ctx_t *ctx, lps22ch_pp_od_t val)
+{
+ lps22ch_ctrl_reg2_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.pp_od = (uint8_t)val;
+ ret = lps22ch_write_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Push-pull/open drain selection on interrupt pads.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of pp_od in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_pin_mode_get(stmdev_ctx_t *ctx, lps22ch_pp_od_t *val)
+{
+ lps22ch_ctrl_reg2_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1);
+
+ switch (reg.pp_od)
+ {
+ case LPS22CH_PUSH_PULL:
+ *val = LPS22CH_PUSH_PULL;
+ break;
+
+ case LPS22CH_OPEN_DRAIN:
+ *val = LPS22CH_OPEN_DRAIN;
+ break;
+
+ default:
+ *val = LPS22CH_PUSH_PULL;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Interrupt active-high/low.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of int_h_l in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_pin_polarity_set(stmdev_ctx_t *ctx,
+ lps22ch_int_h_l_t val)
+{
+ lps22ch_ctrl_reg2_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.int_h_l = (uint8_t)val;
+ ret = lps22ch_write_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Interrupt active-high/low.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of int_h_l in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_pin_polarity_get(stmdev_ctx_t *ctx,
+ lps22ch_int_h_l_t *val)
+{
+ lps22ch_ctrl_reg2_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1);
+
+ switch (reg.int_h_l)
+ {
+ case LPS22CH_ACTIVE_HIGH:
+ *val = LPS22CH_ACTIVE_HIGH;
+ break;
+
+ case LPS22CH_ACTIVE_LOW:
+ *val = LPS22CH_ACTIVE_LOW;
+ break;
+
+ default:
+ *val = LPS22CH_ACTIVE_HIGH;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Select the signal that need to route on int pad.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val registers CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_pin_int_route_set(stmdev_ctx_t *ctx,
+ lps22ch_ctrl_reg3_t *val)
+{
+ int32_t ret;
+
+ ret = lps22ch_write_reg(ctx, LPS22CH_CTRL_REG3, (uint8_t *) val, 1);
+
+ return ret;
+}
+
+/**
+ * @brief Select the signal that need to route on int pad.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val registers CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_pin_int_route_get(stmdev_ctx_t *ctx,
+ lps22ch_ctrl_reg3_t *val)
+{
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG3, (uint8_t *) val, 1);
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LPS22CH_Interrupt_on_Threshold
+ * @brief This section groups all the functions that manage the
+ * interrupt on threshold event generation.
+ * @{
+ *
+ */
+
+/**
+ * @brief Enable interrupt generation on pressure low/high event.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of pe in reg INTERRUPT_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_int_on_threshold_set(stmdev_ctx_t *ctx,
+ lps22ch_pe_t val)
+{
+ lps22ch_interrupt_cfg_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.pe = (uint8_t)val;
+
+ if (val == LPS22CH_NO_THRESHOLD)
+ {
+ reg.diff_en = PROPERTY_DISABLE;
+ }
+
+ else
+ {
+ reg.diff_en = PROPERTY_ENABLE;
+ }
+
+ ret = lps22ch_write_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable interrupt generation on pressure low/high event.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of pe in reg INTERRUPT_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_int_on_threshold_get(stmdev_ctx_t *ctx,
+ lps22ch_pe_t *val)
+{
+ lps22ch_interrupt_cfg_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
+
+ switch (reg.pe)
+ {
+ case LPS22CH_NO_THRESHOLD:
+ *val = LPS22CH_NO_THRESHOLD;
+ break;
+
+ case LPS22CH_POSITIVE:
+ *val = LPS22CH_POSITIVE;
+ break;
+
+ case LPS22CH_NEGATIVE:
+ *val = LPS22CH_NEGATIVE;
+ break;
+
+ case LPS22CH_BOTH:
+ *val = LPS22CH_BOTH;
+ break;
+
+ default:
+ *val = LPS22CH_NO_THRESHOLD;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief User-defined threshold value for pressure interrupt event.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_int_treshold_set(stmdev_ctx_t *ctx, uint16_t buff)
+{
+ int32_t ret;
+
+ lps22ch_ths_p_l_t ths_p_l;
+ lps22ch_ths_p_h_t ths_p_h;
+ ths_p_h.ths = (uint8_t)(buff / 256U);
+ ths_p_l.ths = (uint8_t)(buff - (ths_p_h.ths * 256U));
+ ret = lps22ch_write_reg(ctx, LPS22CH_THS_P_L,
+ (uint8_t *)&ths_p_l, 1);
+
+ if (ret == 0)
+ {
+ ret = lps22ch_write_reg(ctx, LPS22CH_THS_P_H,
+ (uint8_t *)&ths_p_h, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief User-defined threshold value for pressure interrupt event.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_int_treshold_get(stmdev_ctx_t *ctx, uint16_t *buff)
+{
+ int32_t ret;
+
+ lps22ch_ths_p_l_t ths_p_l;
+ lps22ch_ths_p_h_t ths_p_h;
+ ret = lps22ch_read_reg(ctx, LPS22CH_THS_P_L,
+ (uint8_t *)&ths_p_l, 1);
+
+ if (ret == 0)
+ {
+ ret = lps22ch_read_reg(ctx, LPS22CH_THS_P_H,
+ (uint8_t *)&ths_p_h, 1);
+ *buff = (uint16_t)ths_p_h.ths;
+ *buff = (*buff * 256U) + (uint16_t)ths_p_l.ths;
+ }
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LPS22CH_Fifo
+ * @brief This section group all the functions concerning the fifo usage.
+ * @{
+ *
+ */
+
+/**
+ * @brief Fifo Mode selection.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of f_mode in reg FIFO_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_fifo_mode_set(stmdev_ctx_t *ctx, lps22ch_f_mode_t val)
+{
+ lps22ch_fifo_ctrl_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.f_mode = (uint8_t)val;
+ ret = lps22ch_write_reg(ctx, LPS22CH_FIFO_CTRL, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Fifo Mode selection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of f_mode in reg FIFO_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_fifo_mode_get(stmdev_ctx_t *ctx,
+ lps22ch_f_mode_t *val)
+{
+ lps22ch_fifo_ctrl_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_CTRL, (uint8_t *) ®, 1);
+
+ switch (reg.f_mode)
+ {
+ case LPS22CH_BYPASS_MODE:
+ *val = LPS22CH_BYPASS_MODE;
+ break;
+
+ case LPS22CH_FIFO_MODE:
+ *val = LPS22CH_FIFO_MODE;
+ break;
+
+ case LPS22CH_STREAM_MODE:
+ *val = LPS22CH_STREAM_MODE;
+ break;
+
+ case LPS22CH_DYNAMIC_STREAM_MODE:
+ *val = LPS22CH_DYNAMIC_STREAM_MODE;
+ break;
+
+ case LPS22CH_BYPASS_TO_FIFO_MODE:
+ *val = LPS22CH_BYPASS_TO_FIFO_MODE;
+ break;
+
+ case LPS22CH_BYPASS_TO_STREAM_MODE:
+ *val = LPS22CH_BYPASS_TO_STREAM_MODE;
+ break;
+
+ case LPS22CH_STREAM_TO_FIFO_MODE:
+ *val = LPS22CH_STREAM_TO_FIFO_MODE;
+ break;
+
+ default:
+ *val = LPS22CH_BYPASS_MODE;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Sensing chain FIFO stop values memorization at
+ * threshold level.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of stop_on_wtm in reg FIFO_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lps22ch_fifo_ctrl_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.stop_on_wtm = val;
+ ret = lps22ch_write_reg(ctx, LPS22CH_FIFO_CTRL, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Sensing chain FIFO stop values memorization at threshold
+ * level.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of stop_on_wtm in reg FIFO_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lps22ch_fifo_ctrl_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_CTRL, (uint8_t *) ®, 1);
+ *val = reg.stop_on_wtm;
+
+ return ret;
+}
+
+/**
+ * @brief FIFO watermark level selection.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of wtm in reg FIFO_WTM
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lps22ch_fifo_wtm_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_WTM, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.wtm = val;
+ ret = lps22ch_write_reg(ctx, LPS22CH_FIFO_WTM, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief FIFO watermark level selection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of wtm in reg FIFO_WTM
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lps22ch_fifo_wtm_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_WTM, (uint8_t *) ®, 1);
+ *val = reg.wtm;
+
+ return ret;
+}
+
+/**
+ * @brief FIFO stored data level.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *buff)
+{
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_STATUS1, buff, 1);
+
+ return ret;
+}
+
+/**
+ * @brief Read all the FIFO status flag of the device.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val registers FIFO_STATUS2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_fifo_src_get(stmdev_ctx_t *ctx,
+ lps22ch_fifo_status2_t *val)
+{
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_STATUS2, (uint8_t *) val, 1);
+
+ return ret;
+}
+
+/**
+ * @brief Smart FIFO full status.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of fifo_full_ia in reg FIFO_STATUS2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lps22ch_fifo_status2_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_STATUS2, (uint8_t *) ®, 1);
+ *val = reg.fifo_full_ia;
+
+ return ret;
+}
+
+/**
+ * @brief FIFO overrun status.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of fifo_ovr_ia in reg FIFO_STATUS2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lps22ch_fifo_status2_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_STATUS2, (uint8_t *) ®, 1);
+ *val = reg.fifo_ovr_ia;
+
+ return ret;
+}
+
+/**
+ * @brief FIFO watermark status.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of fifo_wtm_ia in reg FIFO_STATUS2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lps22ch_fifo_status2_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_STATUS2, (uint8_t *)®, 1);
+ *val = reg.fifo_wtm_ia;
+
+ return ret;
+}
+
+/**
+ * @brief FIFO overrun interrupt on INT_DRDY pin.[set]
+ *
+ * @param stmdev_ctx_t *ctx: read / write interface definitions
+ * @param uint8_t val: change the values of f_ovr in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lps22ch_ctrl_reg3_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG3, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.int_f_ovr = val;
+ ret = lps22ch_write_reg(ctx, LPS22CH_CTRL_REG3, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief FIFO overrun interrupt on INT_DRDY pin.[get]
+ *
+ * @param stmdev_ctx_t *ctx: read / write interface definitions
+ * @param uint8_t: change the values of f_ovr in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lps22ch_ctrl_reg3_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG3, (uint8_t *)®, 1);
+ *val = reg.int_f_ovr;
+
+ return ret;
+}
+
+/**
+ * @brief FIFO watermark status on INT_DRDY pin.[set]
+ *
+ * @param stmdev_ctx_t *ctx: read / write interface definitions
+ * @param uint8_t val: change the values of f_fth in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_fifo_threshold_on_int_set(stmdev_ctx_t *ctx,
+ uint8_t val)
+{
+ lps22ch_ctrl_reg3_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG3, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.int_f_wtm = val;
+ ret = lps22ch_write_reg(ctx, LPS22CH_CTRL_REG3, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief FIFO watermark status on INT_DRDY pin.[get]
+ *
+ * @param lps22hb_ctx_t *ctx: read / write interface definitions
+ * @param uint8_t: change the values of f_fth in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_fifo_threshold_on_int_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lps22ch_ctrl_reg3_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG3, (uint8_t *)®, 1);
+ *val = reg.int_f_wtm;
+
+ return ret;
+}
+
+/**
+ * @brief FIFO full flag on INT_DRDY pin.[set]
+ *
+ * @param stmdev_ctx_t *ctx: read / write interface definitions
+ * @param uint8_t val: change the values of f_fss5 in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lps22ch_ctrl_reg3_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG3, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.int_f_full = val;
+ ret = lps22ch_write_reg(ctx, LPS22CH_CTRL_REG3, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief FIFO full flag on INT_DRDY pin.[get]
+ *
+ * @param stmdev_ctx_t *ctx: read / write interface definitions
+ * @param uint8_t: change the values of f_fss5 in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps22ch_fifo_full_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lps22ch_ctrl_reg3_t reg;
+ int32_t ret;
+
+ ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG3, (uint8_t *)®, 1);
+ *val = reg.int_f_full;
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @}
+ *
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/sensor/stmemsc/lps22ch_STdC/driver/lps22ch_reg.h b/sensor/stmemsc/lps22ch_STdC/driver/lps22ch_reg.h
new file mode 100644
index 0000000000000000000000000000000000000000..07ebdb322b705439e6901f558bdb4d9bd75bcaee
--- /dev/null
+++ b/sensor/stmemsc/lps22ch_STdC/driver/lps22ch_reg.h
@@ -0,0 +1,682 @@
+/**
+ ******************************************************************************
+ * @file lps22ch_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lps22ch_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef LPS22CH_REGS_H
+#define LPS22CH_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include
+#include
+#include
+
+/** @addtogroup LPS22CH
+ * @{
+ *
+ */
+
+/** @defgroup Endianness definitions
+ * @{
+ *
+ */
+
+#ifndef DRV_BYTE_ORDER
+#ifndef __BYTE_ORDER__
+
+#define DRV_LITTLE_ENDIAN 1234
+#define DRV_BIG_ENDIAN 4321
+
+/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
+ * by uncommenting the define which fits your platform endianness
+ */
+//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
+#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
+
+#else /* defined __BYTE_ORDER__ */
+
+#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
+#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
+#define DRV_BYTE_ORDER __BYTE_ORDER__
+
+#endif /* __BYTE_ORDER__*/
+#endif /* DRV_BYTE_ORDER */
+
+/**
+ * @}
+ *
+ */
+
+/** @defgroup STMicroelectronics sensors common types
+ * @{
+ *
+ */
+
+#ifndef MEMS_SHARED_TYPES
+#define MEMS_SHARED_TYPES
+
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
+} bitwise_t;
+
+#define PROPERTY_DISABLE (0U)
+#define PROPERTY_ENABLE (1U)
+
+/** @addtogroup Interfaces_Functions
+ * @brief This section provide a set of functions used to read and
+ * write a generic register of the device.
+ * MANDATORY: return 0 -> no Error.
+ * @{
+ *
+ */
+
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
+
+typedef struct
+{
+ /** Component mandatory fields **/
+ stmdev_write_ptr write_reg;
+ stmdev_read_ptr read_reg;
+ /** Customizable optional pointer **/
+ void *handle;
+} stmdev_ctx_t;
+
+/**
+ * @}
+ *
+ */
+
+#endif /* MEMS_SHARED_TYPES */
+
+#ifndef MEMS_UCF_SHARED_TYPES
+#define MEMS_UCF_SHARED_TYPES
+
+/** @defgroup Generic address-data structure definition
+ * @brief This structure is useful to load a predefined configuration
+ * of a sensor.
+ * You can create a sensor configuration by your own or using
+ * Unico / Unicleo tools available on STMicroelectronics
+ * web site.
+ *
+ * @{
+ *
+ */
+
+typedef struct
+{
+ uint8_t address;
+ uint8_t data;
+} ucf_line_t;
+
+/**
+ * @}
+ *
+ */
+
+#endif /* MEMS_UCF_SHARED_TYPES */
+
+/**
+ * @}
+ *
+ */
+
+/** @defgroup LPS22CH_Infos
+ * @{
+ *
+ */
+
+/** I2C Device Address 8 bit format if SA0=0 -> B9 if SA0=1 -> BB **/
+#define LPS22CH_I2C_ADD_H 0xBBU
+#define LPS22CH_I2C_ADD_L 0xB9U
+
+/** Device Identification (Who am I) **/
+#define LPS22CH_ID 0xB3U
+
+/**
+ * @}
+ *
+ */
+
+#define LPS22CH_INTERRUPT_CFG 0x0BU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t pe : 2; /* ple + phe */
+ uint8_t lir : 1;
+ uint8_t diff_en : 1;
+ uint8_t reset_az : 1;
+ uint8_t autozero : 1;
+ uint8_t reset_arp : 1;
+ uint8_t autorefp : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t autorefp : 1;
+ uint8_t reset_arp : 1;
+ uint8_t autozero : 1;
+ uint8_t reset_az : 1;
+ uint8_t diff_en : 1;
+ uint8_t lir : 1;
+ uint8_t pe : 2; /* ple + phe */
+#endif /* DRV_BYTE_ORDER */
+} lps22ch_interrupt_cfg_t;
+
+#define LPS22CH_THS_P_L 0x0CU
+typedef struct
+{
+ uint8_t ths : 8;
+} lps22ch_ths_p_l_t;
+
+#define LPS22CH_THS_P_H 0x0DU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t ths : 7;
+ uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t ths : 7;
+#endif /* DRV_BYTE_ORDER */
+} lps22ch_ths_p_h_t;
+
+#define LPS22CH_IF_CTRL 0x0EU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t i2c_disable : 1;
+ uint8_t i3c_disable : 1;
+ uint8_t pd_dis_int1 : 1;
+ uint8_t sdo_pu_en : 1;
+ uint8_t sda_pu_en : 1;
+ uint8_t not_used : 2;
+ uint8_t int_en_i3c : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int_en_i3c : 1;
+ uint8_t not_used : 2;
+ uint8_t sda_pu_en : 1;
+ uint8_t sdo_pu_en : 1;
+ uint8_t pd_dis_int1 : 1;
+ uint8_t i3c_disable : 1;
+ uint8_t i2c_disable : 1;
+#endif /* DRV_BYTE_ORDER */
+} lps22ch_if_ctrl_t;
+
+#define LPS22CH_WHO_AM_I 0x0FU
+#define LPS22CH_CTRL_REG1 0x10U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t sim : 1;
+ uint8_t bdu : 1;
+ uint8_t lpfp_cfg : 2; /* en_lpfp + lpfp_cfg */
+ uint8_t odr : 3;
+ uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t odr : 3;
+ uint8_t lpfp_cfg : 2; /* en_lpfp + lpfp_cfg */
+ uint8_t bdu : 1;
+ uint8_t sim : 1;
+#endif /* DRV_BYTE_ORDER */
+} lps22ch_ctrl_reg1_t;
+
+#define LPS22CH_CTRL_REG2 0x11U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t one_shot : 1;
+ uint8_t low_noise_en : 1;
+ uint8_t swreset : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t if_add_inc : 1;
+ uint8_t pp_od : 1;
+ uint8_t int_h_l : 1;
+ uint8_t boot : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t boot : 1;
+ uint8_t int_h_l : 1;
+ uint8_t pp_od : 1;
+ uint8_t if_add_inc : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t swreset : 1;
+ uint8_t low_noise_en : 1;
+ uint8_t one_shot : 1;
+#endif /* DRV_BYTE_ORDER */
+} lps22ch_ctrl_reg2_t;
+
+#define LPS22CH_CTRL_REG3 0x12U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t int_s : 2;
+ uint8_t drdy : 1;
+ uint8_t int_f_ovr : 1;
+ uint8_t int_f_wtm : 1;
+ uint8_t int_f_full : 1;
+ uint8_t not_used_01 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 2;
+ uint8_t int_f_full : 1;
+ uint8_t int_f_wtm : 1;
+ uint8_t int_f_ovr : 1;
+ uint8_t drdy : 1;
+ uint8_t int_s : 2;
+#endif /* DRV_BYTE_ORDER */
+} lps22ch_ctrl_reg3_t;
+
+#define LPS22CH_FIFO_CTRL 0x13U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+uint8_t f_mode :
+ 3; /* f_mode + trig_modes */
+ uint8_t stop_on_wtm : 1;
+ uint8_t not_used_01 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 4;
+ uint8_t stop_on_wtm : 1;
+uint8_t f_mode :
+ 3; /* f_mode + trig_modes */
+#endif /* DRV_BYTE_ORDER */
+} lps22ch_fifo_ctrl_t;
+
+#define LPS22CH_FIFO_WTM 0x14U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t wtm : 7;
+ uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t wtm : 7;
+#endif /* DRV_BYTE_ORDER */
+} lps22ch_fifo_wtm_t;
+
+#define LPS22CH_REF_P_L 0x15U
+#define LPS22CH_REF_P_H 0x16U
+#define LPS22CH_RPDS_L 0x18U
+#define LPS22CH_RPDS_H 0x19U
+#define LPS22CH_INT_SOURCE 0x24U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t ph : 1;
+ uint8_t pl : 1;
+ uint8_t ia : 1;
+ uint8_t not_used_01 : 4;
+ uint8_t boot_on : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t boot_on : 1;
+ uint8_t not_used_01 : 4;
+ uint8_t ia : 1;
+ uint8_t pl : 1;
+ uint8_t ph : 1;
+#endif /* DRV_BYTE_ORDER */
+} lps22ch_int_source_t;
+
+#define LPS22CH_FIFO_STATUS1 0x25U
+#define LPS22CH_FIFO_STATUS2 0x26U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t not_used_01 : 5;
+ uint8_t fifo_full_ia : 1;
+ uint8_t fifo_ovr_ia : 1;
+ uint8_t fifo_wtm_ia : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fifo_wtm_ia : 1;
+ uint8_t fifo_ovr_ia : 1;
+ uint8_t fifo_full_ia : 1;
+ uint8_t not_used_01 : 5;
+#endif /* DRV_BYTE_ORDER */
+} lps22ch_fifo_status2_t;
+
+#define LPS22CH_STATUS 0x27U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t p_da : 1;
+ uint8_t t_da : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t p_or : 1;
+ uint8_t t_or : 1;
+ uint8_t not_used_02 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 2;
+ uint8_t t_or : 1;
+ uint8_t p_or : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t t_da : 1;
+ uint8_t p_da : 1;
+#endif /* DRV_BYTE_ORDER */
+} lps22ch_status_t;
+
+#define LPS22CH_PRESS_OUT_XL 0x28U
+#define LPS22CH_PRESS_OUT_L 0x29U
+#define LPS22CH_PRESS_OUT_H 0x2AU
+#define LPS22CH_TEMP_OUT_L 0x2BU
+#define LPS22CH_TEMP_OUT_H 0x2CU
+#define LPS22CH_FIFO_DATA_OUT_PRESS_XL 0x78U
+#define LPS22CH_FIFO_DATA_OUT_PRESS_L 0x79U
+#define LPS22CH_FIFO_DATA_OUT_PRESS_H 0x7AU
+#define LPS22CH_FIFO_DATA_OUT_TEMP_L 0x7BU
+#define LPS22CH_FIFO_DATA_OUT_TEMP_H 0x7CU
+
+/**
+ * @defgroup LPS22CH_Register_Union
+ * @brief This union group all the registers having a bit-field
+ * description.
+ * This union is useful but it's not needed by the driver.
+ *
+ * REMOVING this union you are compliant with:
+ * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
+ *
+ * @{
+ *
+ */
+typedef union
+{
+ lps22ch_interrupt_cfg_t interrupt_cfg;
+ lps22ch_if_ctrl_t if_ctrl;
+ lps22ch_ctrl_reg1_t ctrl_reg1;
+ lps22ch_ctrl_reg2_t ctrl_reg2;
+ lps22ch_ctrl_reg3_t ctrl_reg3;
+ lps22ch_fifo_ctrl_t fifo_ctrl;
+ lps22ch_fifo_wtm_t fifo_wtm;
+ lps22ch_int_source_t int_source;
+ lps22ch_fifo_status2_t fifo_status2;
+ lps22ch_status_t status;
+ bitwise_t bitwise;
+ uint8_t byte;
+} lps22ch_reg_t;
+
+/**
+ * @}
+ *
+ */
+
+int32_t lps22ch_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len);
+int32_t lps22ch_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len);
+
+float_t lps22ch_from_lsb_to_hpa(uint32_t lsb);
+
+float_t lps22ch_from_lsb_to_celsius(int16_t lsb);
+
+int32_t lps22ch_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lps22ch_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lps22ch_autozero_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lps22ch_autozero_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lps22ch_pressure_snap_rst_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lps22ch_pressure_snap_rst_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lps22ch_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lps22ch_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lps22ch_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lps22ch_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+typedef enum
+{
+ LPS22CH_POWER_DOWN = 0x00,
+ LPS22CH_ONE_SHOOT = 0x08,
+ LPS22CH_1_Hz = 0x01,
+ LPS22CH_10_Hz = 0x02,
+ LPS22CH_25_Hz = 0x03,
+ LPS22CH_50_Hz = 0x04,
+ LPS22CH_75_Hz = 0x05,
+ LPS22CH_1_Hz_LOW_NOISE = 0x11,
+ LPS22CH_10_Hz_LOW_NOISE = 0x12,
+ LPS22CH_25_Hz_LOW_NOISE = 0x13,
+ LPS22CH_50_Hz_LOW_NOISE = 0x14,
+ LPS22CH_75_Hz_LOW_NOISE = 0x15,
+ LPS22CH_100_Hz = 0x06,
+ LPS22CH_200_Hz = 0x07,
+} lps22ch_odr_t;
+int32_t lps22ch_data_rate_set(stmdev_ctx_t *ctx, lps22ch_odr_t val);
+int32_t lps22ch_data_rate_get(stmdev_ctx_t *ctx, lps22ch_odr_t *val);
+
+int32_t lps22ch_pressure_ref_set(stmdev_ctx_t *ctx, int16_t val);
+int32_t lps22ch_pressure_ref_get(stmdev_ctx_t *ctx, int16_t *val);
+
+int32_t lps22ch_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val);
+int32_t lps22ch_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val);
+
+typedef struct
+{
+ lps22ch_int_source_t int_source;
+ lps22ch_fifo_status2_t fifo_status2;
+ lps22ch_status_t status;
+} lps22ch_all_sources_t;
+int32_t lps22ch_all_sources_get(stmdev_ctx_t *ctx,
+ lps22ch_all_sources_t *val);
+
+int32_t lps22ch_status_reg_get(stmdev_ctx_t *ctx,
+ lps22ch_status_t *val);
+
+int32_t lps22ch_press_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lps22ch_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lps22ch_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff);
+
+int32_t lps22ch_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff);
+
+int32_t lps22ch_fifo_pressure_raw_get(stmdev_ctx_t *ctx,
+ uint32_t *buff);
+
+int32_t lps22ch_fifo_temperature_raw_get(stmdev_ctx_t *ctx,
+ int16_t *buff);
+
+int32_t lps22ch_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
+
+int32_t lps22ch_reset_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lps22ch_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lps22ch_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lps22ch_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lps22ch_boot_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lps22ch_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+ LPS22CH_LPF_ODR_DIV_2 = 0,
+ LPS22CH_LPF_ODR_DIV_9 = 2,
+ LPS22CH_LPF_ODR_DIV_20 = 3,
+} lps22ch_lpfp_cfg_t;
+int32_t lps22ch_lp_bandwidth_set(stmdev_ctx_t *ctx,
+ lps22ch_lpfp_cfg_t val);
+int32_t lps22ch_lp_bandwidth_get(stmdev_ctx_t *ctx,
+ lps22ch_lpfp_cfg_t *val);
+
+typedef enum
+{
+ LPS22CH_I2C_ENABLE = 0,
+ LPS22CH_I2C_DISABLE = 1,
+} lps22ch_i2c_disable_t;
+int32_t lps22ch_i2c_interface_set(stmdev_ctx_t *ctx,
+ lps22ch_i2c_disable_t val);
+int32_t lps22ch_i2c_interface_get(stmdev_ctx_t *ctx,
+ lps22ch_i2c_disable_t *val);
+
+typedef enum
+{
+ LPS22CH_I3C_ENABLE = 0,
+ LPS22CH_I3C_DISABLE = 1,
+} lps22ch_i3c_disable_t;
+int32_t lps22ch_i3c_interface_set(stmdev_ctx_t *ctx,
+ lps22ch_i3c_disable_t val);
+int32_t lps22ch_i3c_interface_get(stmdev_ctx_t *ctx,
+ lps22ch_i3c_disable_t *val);
+
+typedef enum
+{
+ LPS22CH_PULL_UP_DISCONNECT = 0,
+ LPS22CH_PULL_UP_CONNECT = 1,
+} lps22ch_pu_en_t;
+int32_t lps22ch_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
+ lps22ch_pu_en_t val);
+int32_t lps22ch_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
+ lps22ch_pu_en_t *val);
+int32_t lps22ch_sda_mode_set(stmdev_ctx_t *ctx, lps22ch_pu_en_t val);
+int32_t lps22ch_sda_mode_get(stmdev_ctx_t *ctx, lps22ch_pu_en_t *val);
+
+typedef enum
+{
+ LPS22CH_SPI_4_WIRE = 0,
+ LPS22CH_SPI_3_WIRE = 1,
+} lps22ch_sim_t;
+int32_t lps22ch_spi_mode_set(stmdev_ctx_t *ctx, lps22ch_sim_t val);
+int32_t lps22ch_spi_mode_get(stmdev_ctx_t *ctx, lps22ch_sim_t *val);
+
+typedef enum
+{
+ LPS22CH_INT_PULSED = 0,
+ LPS22CH_INT_LATCHED = 1,
+} lps22ch_lir_t;
+int32_t lps22ch_int_notification_set(stmdev_ctx_t *ctx,
+ lps22ch_lir_t val);
+int32_t lps22ch_int_notification_get(stmdev_ctx_t *ctx,
+ lps22ch_lir_t *val);
+
+typedef enum
+{
+ LPS22CH_PUSH_PULL = 0,
+ LPS22CH_OPEN_DRAIN = 1,
+} lps22ch_pp_od_t;
+int32_t lps22ch_pin_mode_set(stmdev_ctx_t *ctx, lps22ch_pp_od_t val);
+int32_t lps22ch_pin_mode_get(stmdev_ctx_t *ctx, lps22ch_pp_od_t *val);
+
+typedef enum
+{
+ LPS22CH_ACTIVE_HIGH = 0,
+ LPS22CH_ACTIVE_LOW = 1,
+} lps22ch_int_h_l_t;
+int32_t lps22ch_pin_polarity_set(stmdev_ctx_t *ctx,
+ lps22ch_int_h_l_t val);
+int32_t lps22ch_pin_polarity_get(stmdev_ctx_t *ctx,
+ lps22ch_int_h_l_t *val);
+
+int32_t lps22ch_pin_int_route_set(stmdev_ctx_t *ctx,
+ lps22ch_ctrl_reg3_t *val);
+int32_t lps22ch_pin_int_route_get(stmdev_ctx_t *ctx,
+ lps22ch_ctrl_reg3_t *val);
+
+typedef enum
+{
+ LPS22CH_NO_THRESHOLD = 0,
+ LPS22CH_POSITIVE = 1,
+ LPS22CH_NEGATIVE = 2,
+ LPS22CH_BOTH = 3,
+} lps22ch_pe_t;
+int32_t lps22ch_int_on_threshold_set(stmdev_ctx_t *ctx,
+ lps22ch_pe_t val);
+int32_t lps22ch_int_on_threshold_get(stmdev_ctx_t *ctx,
+ lps22ch_pe_t *val);
+
+int32_t lps22ch_int_treshold_set(stmdev_ctx_t *ctx, uint16_t buff);
+int32_t lps22ch_int_treshold_get(stmdev_ctx_t *ctx, uint16_t *buff);
+
+typedef enum
+{
+ LPS22CH_BYPASS_MODE = 0,
+ LPS22CH_FIFO_MODE = 1,
+ LPS22CH_STREAM_MODE = 2,
+ LPS22CH_DYNAMIC_STREAM_MODE = 3,
+ LPS22CH_BYPASS_TO_FIFO_MODE = 5,
+ LPS22CH_BYPASS_TO_STREAM_MODE = 6,
+ LPS22CH_STREAM_TO_FIFO_MODE = 7,
+} lps22ch_f_mode_t;
+int32_t lps22ch_fifo_mode_set(stmdev_ctx_t *ctx,
+ lps22ch_f_mode_t val);
+int32_t lps22ch_fifo_mode_get(stmdev_ctx_t *ctx,
+ lps22ch_f_mode_t *val);
+
+int32_t lps22ch_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lps22ch_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lps22ch_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lps22ch_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lps22ch_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *buff);
+
+int32_t lps22ch_fifo_src_get(stmdev_ctx_t *ctx,
+ lps22ch_fifo_status2_t *val);
+
+int32_t lps22ch_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lps22ch_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lps22ch_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lps22ch_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lps22ch_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lps22ch_fifo_threshold_on_int_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lps22ch_fifo_threshold_on_int_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lps22ch_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lps22ch_fifo_full_on_int_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+/**
+ * @}
+ *
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*LPS22CH_REGS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.c b/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.c
index 5dddc74f149d8ffe315453f91ed88720eb37abcb..842a88ee772df88f7e89ccf6f1788f5412a501cd 100644
--- a/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.c
+++ b/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file lps22hb_reg.c
- * @author Sensors Software Solution Team
- * @brief LPS22HB driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lps22hb_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LPS22HB driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lps22hb_reg.h"
@@ -27,7 +27,7 @@
*
*/
-/**
+/**
* @defgroup LPS22HB_Interfaces_functions
* @brief This section provide a set of functions used to read and
* write a generic register of the device.
@@ -45,11 +45,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps22hb_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lps22hb_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -63,11 +66,14 @@ int32_t lps22hb_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps22hb_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lps22hb_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -85,12 +91,12 @@ int32_t lps22hb_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
float_t lps22hb_from_lsb_to_hpa(int32_t lsb)
{
- return ( (float_t)lsb / 4096.0f );
+ return ((float_t)lsb / 1048576.0f);
}
float_t lps22hb_from_lsb_to_degc(int16_t lsb)
{
- return ( (float_t)lsb / 100.0f );
+ return ((float_t)lsb / 100.0f);
}
/**
@@ -122,17 +128,20 @@ int32_t lps22hb_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lps22hb_read_reg(ctx, LPS22HB_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
- if(ret == 0){
+ (uint8_t *)&interrupt_cfg, 1);
+
+ if (ret == 0)
+ {
interrupt_cfg.reset_az = val;
ret = lps22hb_write_reg(ctx, LPS22HB_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
}
+
return ret;
}
/**
- * @brief Reset Autozero function.[get]
+ * @brief Reset Autozero function.[get]
*
* @param ctx Read / write interface definitions
* @param val Change the values of reset_az in reg INTERRUPT_CFG
@@ -145,7 +154,7 @@ int32_t lps22hb_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lps22hb_read_reg(ctx, LPS22HB_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
*val = interrupt_cfg.reset_az;
return ret;
@@ -164,13 +173,16 @@ int32_t lps22hb_autozero_set(stmdev_ctx_t *ctx, uint8_t val)
lps22hb_interrupt_cfg_t interrupt_cfg;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
- if(ret == 0){
+ ret = lps22hb_read_reg(ctx, LPS22HB_INTERRUPT_CFG,
+ (uint8_t *)&interrupt_cfg, 1);
+
+ if (ret == 0)
+ {
interrupt_cfg.autozero = val;
ret = lps22hb_write_reg(ctx, LPS22HB_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
}
+
return ret;
}
@@ -188,14 +200,14 @@ int32_t lps22hb_autozero_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lps22hb_read_reg(ctx, LPS22HB_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
*val = interrupt_cfg.autozero;
return ret;
}
/**
- * @brief Reset AutoRifP function.[set]
+ * @brief Reset AutoRifP function.[set]
*
* @param ctx Read / write interface definitions
* @param val Change the values of reset_arp in reg INTERRUPT_CFG
@@ -208,12 +220,15 @@ int32_t lps22hb_pressure_snap_rst_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lps22hb_read_reg(ctx, LPS22HB_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
- if(ret == 0){
+ (uint8_t *)&interrupt_cfg, 1);
+
+ if (ret == 0)
+ {
interrupt_cfg.reset_arp = val;
ret = lps22hb_write_reg(ctx, LPS22HB_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
}
+
return ret;
}
@@ -231,7 +246,7 @@ int32_t lps22hb_pressure_snap_rst_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lps22hb_read_reg(ctx, LPS22HB_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
*val = interrupt_cfg.reset_arp;
return ret;
@@ -251,12 +266,15 @@ int32_t lps22hb_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lps22hb_read_reg(ctx, LPS22HB_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
- if(ret == 0){
+ (uint8_t *)&interrupt_cfg, 1);
+
+ if (ret == 0)
+ {
interrupt_cfg.autorifp = val;
ret = lps22hb_write_reg(ctx, LPS22HB_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
}
+
return ret;
}
@@ -274,7 +292,7 @@ int32_t lps22hb_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lps22hb_read_reg(ctx, LPS22HB_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
*val = interrupt_cfg.autorifp;
return ret;
@@ -293,11 +311,14 @@ int32_t lps22hb_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
lps22hb_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0){
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.bdu = val;
- ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -314,7 +335,7 @@ int32_t lps22hb_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hb_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
*val = ctrl_reg1.bdu;
return ret;
@@ -329,21 +350,24 @@ int32_t lps22hb_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lps22hb_low_pass_filter_mode_set(stmdev_ctx_t *ctx,
- lps22hb_lpfp_t val)
+ lps22hb_lpfp_t val)
{
lps22hb_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0){
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.lpfp = (uint8_t)val;
- ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
/**
- * @brief Low-pass bandwidth selection.[get]
+ * @brief Low-pass bandwidth selection.[get]
*
* @param ctx Read / write interface definitions
* @param val Get the values of lpfp in reg CTRL_REG1
@@ -356,21 +380,27 @@ int32_t lps22hb_low_pass_filter_mode_get(stmdev_ctx_t *ctx,
lps22hb_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- switch (ctrl_reg1.lpfp){
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ switch (ctrl_reg1.lpfp)
+ {
case LPS22HB_LPF_ODR_DIV_2:
*val = LPS22HB_LPF_ODR_DIV_2;
break;
+
case LPS22HB_LPF_ODR_DIV_9:
*val = LPS22HB_LPF_ODR_DIV_9;
break;
+
case LPS22HB_LPF_ODR_DIV_20:
*val = LPS22HB_LPF_ODR_DIV_20;
break;
+
default:
*val = LPS22HB_LPF_ODR_DIV_2;
break;
}
+
return ret;
}
@@ -387,11 +417,14 @@ int32_t lps22hb_data_rate_set(stmdev_ctx_t *ctx, lps22hb_odr_t val)
lps22hb_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0){
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.odr = (uint8_t)val;
- ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -408,26 +441,34 @@ int32_t lps22hb_data_rate_get(stmdev_ctx_t *ctx, lps22hb_odr_t *val)
lps22hb_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- switch (ctrl_reg1.odr){
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ switch (ctrl_reg1.odr)
+ {
case LPS22HB_POWER_DOWN:
*val = LPS22HB_POWER_DOWN;
break;
+
case LPS22HB_ODR_1_Hz:
*val = LPS22HB_ODR_1_Hz;
break;
+
case LPS22HB_ODR_10_Hz:
*val = LPS22HB_ODR_10_Hz;
break;
+
case LPS22HB_ODR_25_Hz:
*val = LPS22HB_ODR_25_Hz;
break;
+
case LPS22HB_ODR_50_Hz:
*val = LPS22HB_ODR_50_Hz;
break;
+
case LPS22HB_ODR_75_Hz:
*val = LPS22HB_ODR_75_Hz;
break;
+
default:
*val = LPS22HB_ODR_1_Hz;
break;
@@ -437,7 +478,7 @@ int32_t lps22hb_data_rate_get(stmdev_ctx_t *ctx, lps22hb_odr_t *val)
}
/**
- * @brief One-shot mode. Device perform a single measure.[set]
+ * @brief One-shot mode. Device perform a single measure.[set]
*
* @param ctx Read / write interface definitions
* @param val Change the values of one_shot in reg CTRL_REG2
@@ -449,11 +490,14 @@ int32_t lps22hb_one_shoot_trigger_set(stmdev_ctx_t *ctx, uint8_t val)
lps22hb_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0){
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.one_shot = val;
- ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -470,7 +514,7 @@ int32_t lps22hb_one_shoot_trigger_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hb_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
*val = ctrl_reg2.one_shot;
return ret;
@@ -486,10 +530,17 @@ int32_t lps22hb_one_shoot_trigger_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps22hb_pressure_ref_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps22hb_pressure_ref_set(stmdev_ctx_t *ctx, int32_t val)
{
+ uint8_t buff[3];
int32_t ret;
+
+ buff[2] = (uint8_t)((uint32_t)val / 65536U);
+ buff[1] = (uint8_t)((uint32_t)val - (buff[2] * 65536U)) / 256U;
+ buff[0] = (uint8_t)((uint32_t)val - (buff[2] * 65536U) -
+ (buff[1] * 256U));
ret = lps22hb_write_reg(ctx, LPS22HB_REF_P_XL, buff, 3);
+
return ret;
}
@@ -503,10 +554,16 @@ int32_t lps22hb_pressure_ref_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps22hb_pressure_ref_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps22hb_pressure_ref_get(stmdev_ctx_t *ctx, int32_t *val)
{
+ uint8_t buff[3];
int32_t ret;
+
ret = lps22hb_read_reg(ctx, LPS22HB_REF_P_XL, buff, 3);
+ *val = (int32_t)buff[2];
+ *val = (*val * 256) + (int32_t)buff[1];
+ *val = (*val * 256) + (int32_t)buff[0];
+
return ret;
}
@@ -519,10 +576,15 @@ int32_t lps22hb_pressure_ref_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps22hb_pressure_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps22hb_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val)
{
+ uint8_t buff[2];
int32_t ret;
+
+ buff[1] = (uint8_t)((uint16_t)val / 256U);
+ buff[0] = (uint8_t)((uint16_t)val - (buff[1] * 256U));
ret = lps22hb_write_reg(ctx, LPS22HB_RPDS_L, buff, 2);
+
return ret;
}
@@ -535,10 +597,15 @@ int32_t lps22hb_pressure_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps22hb_pressure_offset_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps22hb_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
+
ret = lps22hb_read_reg(ctx, LPS22HB_RPDS_L, buff, 2);
+ *val = (int16_t)buff[1];
+ *val = (*val * 256) + (int16_t)buff[0];
+
return ret;
}
@@ -555,7 +622,7 @@ int32_t lps22hb_press_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hb_status_t status;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_STATUS, (uint8_t*)&status, 1);
+ ret = lps22hb_read_reg(ctx, LPS22HB_STATUS, (uint8_t *)&status, 1);
*val = status.p_da;
return ret;
@@ -574,7 +641,7 @@ int32_t lps22hb_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hb_status_t status;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_STATUS, (uint8_t*)&status, 1);
+ ret = lps22hb_read_reg(ctx, LPS22HB_STATUS, (uint8_t *)&status, 1);
*val = status.t_da;
return ret;
@@ -593,7 +660,7 @@ int32_t lps22hb_press_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hb_status_t status;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_STATUS, (uint8_t*)&status, 1);
+ ret = lps22hb_read_reg(ctx, LPS22HB_STATUS, (uint8_t *)&status, 1);
*val = status.p_or;
return ret;
@@ -612,7 +679,7 @@ int32_t lps22hb_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hb_status_t status;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_STATUS, (uint8_t*)&status, 1);
+ ret = lps22hb_read_reg(ctx, LPS22HB_STATUS, (uint8_t *)&status, 1);
*val = status.t_or;
return ret;
@@ -626,10 +693,17 @@ int32_t lps22hb_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps22hb_pressure_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps22hb_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff)
{
+ uint8_t reg[3];
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_PRESS_OUT_XL, buff, 3);
+
+ ret = lps22hb_read_reg(ctx, LPS22HB_PRESS_OUT_XL, reg, 3);
+ *buff = reg[2];
+ *buff = (*buff * 256) + reg[1];
+ *buff = (*buff * 256) + reg[0];
+ *buff *= 256;
+
return ret;
}
@@ -641,10 +715,15 @@ int32_t lps22hb_pressure_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps22hb_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps22hb_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff)
{
+ uint8_t reg[2];
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_TEMP_OUT_L, (uint8_t*) buff, 2);
+
+ ret = lps22hb_read_reg(ctx, LPS22HB_TEMP_OUT_L, (uint8_t *) reg, 2);
+ *buff = reg[1];
+ *buff = (*buff * 256) + reg[0];
+
return ret;
}
@@ -662,7 +741,9 @@ int32_t lps22hb_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lps22hb_low_pass_rst_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_LPFP_RES, (uint8_t*) buff, 1);
+
+ ret = lps22hb_read_reg(ctx, LPS22HB_LPFP_RES, (uint8_t *) buff, 1);
+
return ret;
}
@@ -673,7 +754,7 @@ int32_t lps22hb_low_pass_rst_get(stmdev_ctx_t *ctx, uint8_t *buff)
/**
* @defgroup LPS22HB_common
- * @brief This section group common usefull functions
+ * @brief This section group common useful functions
* @{
*
*/
@@ -689,7 +770,9 @@ int32_t lps22hb_low_pass_rst_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lps22hb_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_WHO_AM_I, (uint8_t*) buff, 1);
+
+ ret = lps22hb_read_reg(ctx, LPS22HB_WHO_AM_I, (uint8_t *) buff, 1);
+
return ret;
}
@@ -706,11 +789,14 @@ int32_t lps22hb_reset_set(stmdev_ctx_t *ctx, uint8_t val)
lps22hb_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0){
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.swreset = val;
- ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -727,7 +813,7 @@ int32_t lps22hb_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hb_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
*val = ctrl_reg2.swreset;
return ret;
@@ -746,11 +832,14 @@ int32_t lps22hb_boot_set(stmdev_ctx_t *ctx, uint8_t val)
lps22hb_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0){
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.boot = val;
- ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -767,7 +856,7 @@ int32_t lps22hb_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hb_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
*val = ctrl_reg2.boot;
return ret;
@@ -786,11 +875,14 @@ int32_t lps22hb_low_power_set(stmdev_ctx_t *ctx, uint8_t val)
lps22hb_res_conf_t res_conf;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_RES_CONF, (uint8_t*)&res_conf, 1);
- if(ret == 0){
+ ret = lps22hb_read_reg(ctx, LPS22HB_RES_CONF, (uint8_t *)&res_conf, 1);
+
+ if (ret == 0)
+ {
res_conf.lc_en = val;
- ret = lps22hb_write_reg(ctx, LPS22HB_RES_CONF, (uint8_t*)&res_conf, 1);
+ ret = lps22hb_write_reg(ctx, LPS22HB_RES_CONF, (uint8_t *)&res_conf, 1);
}
+
return ret;
}
@@ -807,7 +899,7 @@ int32_t lps22hb_low_power_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hb_res_conf_t res_conf;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_RES_CONF, (uint8_t*)&res_conf, 1);
+ ret = lps22hb_read_reg(ctx, LPS22HB_RES_CONF, (uint8_t *)&res_conf, 1);
*val = res_conf.lc_en;
return ret;
@@ -826,7 +918,8 @@ int32_t lps22hb_boot_status_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hb_int_source_t int_source;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_INT_SOURCE, (uint8_t*)&int_source, 1);
+ ret = lps22hb_read_reg(ctx, LPS22HB_INT_SOURCE,
+ (uint8_t *)&int_source, 1);
*val = int_source.boot_status;
return ret;
@@ -840,10 +933,13 @@ int32_t lps22hb_boot_status_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps22hb_dev_status_get(stmdev_ctx_t *ctx, lps22hb_dev_stat_t *val)
+int32_t lps22hb_dev_status_get(stmdev_ctx_t *ctx,
+ lps22hb_dev_stat_t *val)
{
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_FIFO_STATUS, (uint8_t*) val, 2);
+
+ ret = lps22hb_read_reg(ctx, LPS22HB_FIFO_STATUS, (uint8_t *) val, 2);
+
return ret;
}
@@ -868,18 +964,21 @@ int32_t lps22hb_dev_status_get(stmdev_ctx_t *ctx, lps22hb_dev_stat_t *val)
*
*/
int32_t lps22hb_sign_of_int_threshold_set(stmdev_ctx_t *ctx,
- lps22hb_pe_t val)
+ lps22hb_pe_t val)
{
lps22hb_interrupt_cfg_t interrupt_cfg;
int32_t ret;
ret = lps22hb_read_reg(ctx, LPS22HB_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
- if(ret == 0){
+ (uint8_t *)&interrupt_cfg, 1);
+
+ if (ret == 0)
+ {
interrupt_cfg.pe = (uint8_t)val;
ret = lps22hb_write_reg(ctx, LPS22HB_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
}
+
return ret;
}
@@ -892,30 +991,37 @@ int32_t lps22hb_sign_of_int_threshold_set(stmdev_ctx_t *ctx,
*
*/
int32_t lps22hb_sign_of_int_threshold_get(stmdev_ctx_t *ctx,
- lps22hb_pe_t *val)
+ lps22hb_pe_t *val)
{
lps22hb_interrupt_cfg_t interrupt_cfg;
int32_t ret;
ret = lps22hb_read_reg(ctx, LPS22HB_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
- switch (interrupt_cfg.pe){
+ (uint8_t *)&interrupt_cfg, 1);
+
+ switch (interrupt_cfg.pe)
+ {
case LPS22HB_NO_THRESHOLD:
*val = LPS22HB_NO_THRESHOLD;
break;
+
case LPS22HB_POSITIVE:
*val = LPS22HB_POSITIVE;
break;
+
case LPS22HB_NEGATIVE:
*val = LPS22HB_NEGATIVE;
break;
+
case LPS22HB_BOTH:
*val = LPS22HB_BOTH;
break;
+
default:
*val = LPS22HB_NO_THRESHOLD;
break;
}
+
return ret;
}
@@ -929,18 +1035,21 @@ int32_t lps22hb_sign_of_int_threshold_get(stmdev_ctx_t *ctx,
*
*/
int32_t lps22hb_int_notification_mode_set(stmdev_ctx_t *ctx,
- lps22hb_lir_t val)
+ lps22hb_lir_t val)
{
lps22hb_interrupt_cfg_t interrupt_cfg;
int32_t ret;
ret = lps22hb_read_reg(ctx, LPS22HB_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
- if(ret == 0){
+ (uint8_t *)&interrupt_cfg, 1);
+
+ if (ret == 0)
+ {
interrupt_cfg.lir = (uint8_t)val;
ret = lps22hb_write_reg(ctx, LPS22HB_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
}
+
return ret;
}
@@ -960,18 +1069,23 @@ int32_t lps22hb_int_notification_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lps22hb_read_reg(ctx, LPS22HB_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
- switch (interrupt_cfg.lir){
+ (uint8_t *)&interrupt_cfg, 1);
+
+ switch (interrupt_cfg.lir)
+ {
case LPS22HB_INT_PULSED:
*val = LPS22HB_INT_PULSED;
break;
+
case LPS22HB_INT_LATCHED:
*val = LPS22HB_INT_LATCHED;
break;
+
default:
*val = LPS22HB_INT_PULSED;
break;
}
+
return ret;
}
@@ -989,12 +1103,15 @@ int32_t lps22hb_int_generation_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lps22hb_read_reg(ctx, LPS22HB_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
- if(ret == 0){
+ (uint8_t *)&interrupt_cfg, 1);
+
+ if (ret == 0)
+ {
interrupt_cfg.diff_en = val;
ret = lps22hb_write_reg(ctx, LPS22HB_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
}
+
return ret;
}
@@ -1012,7 +1129,7 @@ int32_t lps22hb_int_generation_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lps22hb_read_reg(ctx, LPS22HB_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
*val = interrupt_cfg.diff_en;
return ret;
@@ -1026,10 +1143,15 @@ int32_t lps22hb_int_generation_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps22hb_int_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps22hb_int_threshold_set(stmdev_ctx_t *ctx, uint16_t val)
{
+ uint8_t buff[2];
int32_t ret;
- ret = lps22hb_write_reg(ctx, LPS22HB_THS_P_L, (uint8_t*) buff, 2);
+
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
+ ret = lps22hb_write_reg(ctx, LPS22HB_THS_P_L, (uint8_t *) buff, 2);
+
return ret;
}
@@ -1041,10 +1163,15 @@ int32_t lps22hb_int_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps22hb_int_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps22hb_int_threshold_get(stmdev_ctx_t *ctx, uint16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_THS_P_L, (uint8_t*) buff, 2);
+
+ ret = lps22hb_read_reg(ctx, LPS22HB_THS_P_L, (uint8_t *) buff, 2);
+ *val = buff[1];
+ *val = (*val * 256) + buff[0];
+
return ret;
}
@@ -1056,16 +1183,20 @@ int32_t lps22hb_int_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps22hb_int_pin_mode_set(stmdev_ctx_t *ctx, lps22hb_int_s_t val)
+int32_t lps22hb_int_pin_mode_set(stmdev_ctx_t *ctx,
+ lps22hb_int_s_t val)
{
lps22hb_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0){
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.int_s = (uint8_t)val;
- ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1077,29 +1208,37 @@ int32_t lps22hb_int_pin_mode_set(stmdev_ctx_t *ctx, lps22hb_int_s_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps22hb_int_pin_mode_get(stmdev_ctx_t *ctx, lps22hb_int_s_t *val)
+int32_t lps22hb_int_pin_mode_get(stmdev_ctx_t *ctx,
+ lps22hb_int_s_t *val)
{
lps22hb_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- switch (ctrl_reg3.int_s){
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ switch (ctrl_reg3.int_s)
+ {
case LPS22HB_DRDY_OR_FIFO_FLAGS:
*val = LPS22HB_DRDY_OR_FIFO_FLAGS;
break;
+
case LPS22HB_HIGH_PRES_INT:
*val = LPS22HB_HIGH_PRES_INT;
break;
+
case LPS22HB_LOW_PRES_INT:
*val = LPS22HB_LOW_PRES_INT;
break;
+
case LPS22HB_EVERY_PRES_INT:
*val = LPS22HB_EVERY_PRES_INT;
break;
+
default:
*val = LPS22HB_DRDY_OR_FIFO_FLAGS;
break;
}
+
return ret;
}
@@ -1116,11 +1255,14 @@ int32_t lps22hb_drdy_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
lps22hb_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0){
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.drdy = val;
- ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1137,7 +1279,7 @@ int32_t lps22hb_drdy_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hb_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
*val = ctrl_reg3.drdy;
return ret;
@@ -1156,11 +1298,14 @@ int32_t lps22hb_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
lps22hb_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0){
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.f_ovr = val;
- ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1177,7 +1322,7 @@ int32_t lps22hb_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hb_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
*val = ctrl_reg3.f_ovr;
return ret;
@@ -1191,16 +1336,20 @@ int32_t lps22hb_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps22hb_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lps22hb_fifo_threshold_on_int_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lps22hb_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0){
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.f_fth = val;
- ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1212,12 +1361,13 @@ int32_t lps22hb_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps22hb_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lps22hb_fifo_threshold_on_int_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lps22hb_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
*val = ctrl_reg3.f_fth;
return ret;
@@ -1236,11 +1386,14 @@ int32_t lps22hb_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
lps22hb_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0){
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.f_fss5 = val;
- ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1257,7 +1410,7 @@ int32_t lps22hb_fifo_full_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hb_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
*val = ctrl_reg3.f_fss5;
return ret;
@@ -1276,11 +1429,14 @@ int32_t lps22hb_pin_mode_set(stmdev_ctx_t *ctx, lps22hb_pp_od_t val)
lps22hb_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0){
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.pp_od = (uint8_t)val;
- ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1297,18 +1453,23 @@ int32_t lps22hb_pin_mode_get(stmdev_ctx_t *ctx, lps22hb_pp_od_t *val)
lps22hb_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- switch (ctrl_reg3.pp_od){
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ switch (ctrl_reg3.pp_od)
+ {
case LPS22HB_PUSH_PULL:
*val = LPS22HB_PUSH_PULL;
break;
+
case LPS22HB_OPEN_DRAIN:
*val = LPS22HB_OPEN_DRAIN;
break;
+
default:
*val = LPS22HB_PUSH_PULL;
break;
}
+
return ret;
}
@@ -1320,16 +1481,20 @@ int32_t lps22hb_pin_mode_get(stmdev_ctx_t *ctx, lps22hb_pp_od_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps22hb_int_polarity_set(stmdev_ctx_t *ctx, lps22hb_int_h_l_t val)
+int32_t lps22hb_int_polarity_set(stmdev_ctx_t *ctx,
+ lps22hb_int_h_l_t val)
{
lps22hb_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0){
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.int_h_l = (uint8_t)val;
- ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1341,23 +1506,29 @@ int32_t lps22hb_int_polarity_set(stmdev_ctx_t *ctx, lps22hb_int_h_l_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps22hb_int_polarity_get(stmdev_ctx_t *ctx, lps22hb_int_h_l_t *val)
+int32_t lps22hb_int_polarity_get(stmdev_ctx_t *ctx,
+ lps22hb_int_h_l_t *val)
{
lps22hb_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- switch (ctrl_reg3.int_h_l){
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ switch (ctrl_reg3.int_h_l)
+ {
case LPS22HB_ACTIVE_HIGH:
*val = LPS22HB_ACTIVE_HIGH;
break;
+
case LPS22HB_ACTIVE_LOW:
*val = LPS22HB_ACTIVE_LOW;
break;
+
default:
*val = LPS22HB_ACTIVE_HIGH;
break;
}
+
return ret;
}
@@ -1369,10 +1540,13 @@ int32_t lps22hb_int_polarity_get(stmdev_ctx_t *ctx, lps22hb_int_h_l_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps22hb_int_source_get(stmdev_ctx_t *ctx, lps22hb_int_source_t *val)
+int32_t lps22hb_int_source_get(stmdev_ctx_t *ctx,
+ lps22hb_int_source_t *val)
{
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_INT_SOURCE, (uint8_t*) val, 1);
+
+ ret = lps22hb_read_reg(ctx, LPS22HB_INT_SOURCE, (uint8_t *) val, 1);
+
return ret;
}
@@ -1389,7 +1563,8 @@ int32_t lps22hb_int_on_press_high_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hb_int_source_t int_source;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_INT_SOURCE, (uint8_t*)&int_source, 1);
+ ret = lps22hb_read_reg(ctx, LPS22HB_INT_SOURCE,
+ (uint8_t *)&int_source, 1);
*val = int_source.ph;
return ret;
@@ -1408,7 +1583,8 @@ int32_t lps22hb_int_on_press_low_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hb_int_source_t int_source;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_INT_SOURCE, (uint8_t*)&int_source, 1);
+ ret = lps22hb_read_reg(ctx, LPS22HB_INT_SOURCE,
+ (uint8_t *)&int_source, 1);
*val = int_source.pl;
return ret;
@@ -1427,7 +1603,8 @@ int32_t lps22hb_interrupt_event_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hb_int_source_t int_source;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_INT_SOURCE, (uint8_t*)&int_source, 1);
+ ret = lps22hb_read_reg(ctx, LPS22HB_INT_SOURCE,
+ (uint8_t *)&int_source, 1);
*val = int_source.ia;
return ret;
@@ -1454,16 +1631,20 @@ int32_t lps22hb_interrupt_event_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps22hb_stop_on_fifo_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lps22hb_stop_on_fifo_threshold_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lps22hb_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0){
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.stop_on_fth = val;
- ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -1475,12 +1656,13 @@ int32_t lps22hb_stop_on_fifo_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps22hb_stop_on_fifo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lps22hb_stop_on_fifo_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lps22hb_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
*val = ctrl_reg2.stop_on_fth;
return ret;
@@ -1499,11 +1681,14 @@ int32_t lps22hb_fifo_set(stmdev_ctx_t *ctx, uint8_t val)
lps22hb_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0){
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.fifo_en = val;
- ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -1520,7 +1705,7 @@ int32_t lps22hb_fifo_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hb_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
*val = ctrl_reg2.fifo_en;
return ret;
@@ -1539,11 +1724,14 @@ int32_t lps22hb_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
lps22hb_fifo_ctrl_t fifo_ctrl;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
- if(ret == 0){
+ ret = lps22hb_read_reg(ctx, LPS22HB_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl.wtm = val;
- ret = lps22hb_write_reg(ctx, LPS22HB_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
+ ret = lps22hb_write_reg(ctx, LPS22HB_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
}
+
return ret;
}
@@ -1560,7 +1748,7 @@ int32_t lps22hb_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hb_fifo_ctrl_t fifo_ctrl;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
+ ret = lps22hb_read_reg(ctx, LPS22HB_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
*val = fifo_ctrl.wtm;
return ret;
@@ -1579,11 +1767,14 @@ int32_t lps22hb_fifo_mode_set(stmdev_ctx_t *ctx, lps22hb_f_mode_t val)
lps22hb_fifo_ctrl_t fifo_ctrl;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
- if(ret == 0){
+ ret = lps22hb_read_reg(ctx, LPS22HB_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl.f_mode = (uint8_t)val;
- ret = lps22hb_write_reg(ctx, LPS22HB_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
+ ret = lps22hb_write_reg(ctx, LPS22HB_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
}
+
return ret;
}
@@ -1595,38 +1786,49 @@ int32_t lps22hb_fifo_mode_set(stmdev_ctx_t *ctx, lps22hb_f_mode_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps22hb_fifo_mode_get(stmdev_ctx_t *ctx, lps22hb_f_mode_t *val)
+int32_t lps22hb_fifo_mode_get(stmdev_ctx_t *ctx,
+ lps22hb_f_mode_t *val)
{
lps22hb_fifo_ctrl_t fifo_ctrl;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
- switch (fifo_ctrl.f_mode){
+ ret = lps22hb_read_reg(ctx, LPS22HB_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
+
+ switch (fifo_ctrl.f_mode)
+ {
case LPS22HB_BYPASS_MODE:
*val = LPS22HB_BYPASS_MODE;
break;
+
case LPS22HB_FIFO_MODE:
*val = LPS22HB_FIFO_MODE;
break;
+
case LPS22HB_STREAM_MODE:
*val = LPS22HB_STREAM_MODE;
break;
+
case LPS22HB_STREAM_TO_FIFO_MODE:
*val = LPS22HB_STREAM_TO_FIFO_MODE;
break;
+
case LPS22HB_BYPASS_TO_STREAM_MODE:
*val = LPS22HB_BYPASS_TO_STREAM_MODE;
break;
+
case LPS22HB_DYNAMIC_STREAM_MODE:
*val = LPS22HB_DYNAMIC_STREAM_MODE;
break;
+
case LPS22HB_BYPASS_TO_FIFO_MODE:
*val = LPS22HB_BYPASS_TO_FIFO_MODE;
break;
+
default:
*val = LPS22HB_BYPASS_MODE;
break;
}
+
return ret;
}
@@ -1643,7 +1845,8 @@ int32_t lps22hb_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hb_fifo_status_t fifo_status;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_FIFO_STATUS, (uint8_t*)&fifo_status, 1);
+ ret = lps22hb_read_reg(ctx, LPS22HB_FIFO_STATUS,
+ (uint8_t *)&fifo_status, 1);
*val = fifo_status.fss;
return ret;
@@ -1662,7 +1865,8 @@ int32_t lps22hb_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hb_fifo_status_t fifo_status;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_FIFO_STATUS, (uint8_t*)&fifo_status, 1);
+ ret = lps22hb_read_reg(ctx, LPS22HB_FIFO_STATUS,
+ (uint8_t *)&fifo_status, 1);
*val = fifo_status.ovr;
return ret;
@@ -1681,7 +1885,8 @@ int32_t lps22hb_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hb_fifo_status_t fifo_status;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_FIFO_STATUS, (uint8_t*)&fifo_status, 1);
+ ret = lps22hb_read_reg(ctx, LPS22HB_FIFO_STATUS,
+ (uint8_t *)&fifo_status, 1);
*val = fifo_status.fth_fifo;
return ret;
@@ -1713,11 +1918,14 @@ int32_t lps22hb_spi_mode_set(stmdev_ctx_t *ctx, lps22hb_sim_t val)
lps22hb_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0){
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.sim = (uint8_t)val;
- ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -1734,18 +1942,23 @@ int32_t lps22hb_spi_mode_get(stmdev_ctx_t *ctx, lps22hb_sim_t *val)
lps22hb_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- switch (ctrl_reg1.sim){
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ switch (ctrl_reg1.sim)
+ {
case LPS22HB_SPI_4_WIRE:
*val = LPS22HB_SPI_4_WIRE;
break;
+
case LPS22HB_SPI_3_WIRE:
*val = LPS22HB_SPI_3_WIRE;
break;
+
default:
*val = LPS22HB_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -1757,16 +1970,20 @@ int32_t lps22hb_spi_mode_get(stmdev_ctx_t *ctx, lps22hb_sim_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps22hb_i2c_interface_set(stmdev_ctx_t *ctx, lps22hb_i2c_dis_t val)
+int32_t lps22hb_i2c_interface_set(stmdev_ctx_t *ctx,
+ lps22hb_i2c_dis_t val)
{
lps22hb_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0){
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.i2c_dis = (uint8_t)val;
- ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -1778,23 +1995,29 @@ int32_t lps22hb_i2c_interface_set(stmdev_ctx_t *ctx, lps22hb_i2c_dis_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps22hb_i2c_interface_get(stmdev_ctx_t *ctx, lps22hb_i2c_dis_t *val)
+int32_t lps22hb_i2c_interface_get(stmdev_ctx_t *ctx,
+ lps22hb_i2c_dis_t *val)
{
lps22hb_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- switch (ctrl_reg2.i2c_dis){
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ switch (ctrl_reg2.i2c_dis)
+ {
case LPS22HB_I2C_ENABLE:
*val = LPS22HB_I2C_ENABLE;
break;
+
case LPS22HB_I2C_DISABLE:
*val = LPS22HB_I2C_DISABLE;
break;
+
default:
*val = LPS22HB_I2C_ENABLE;
break;
}
+
return ret;
}
@@ -1812,11 +2035,14 @@ int32_t lps22hb_auto_add_inc_set(stmdev_ctx_t *ctx, uint8_t val)
lps22hb_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0){
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.if_add_inc = val;
- ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps22hb_write_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -1834,7 +2060,7 @@ int32_t lps22hb_auto_add_inc_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hb_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
*val = ctrl_reg2.if_add_inc;
return ret;
diff --git a/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.h b/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.h
index 9d3fc6ee5e4c690922f379f8161b81a49599caac..4a7f08ab4c77c4cc9b61c201f49abfa660da8662 100644
--- a/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.h
+++ b/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file lps22hb_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lps22hb_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lps22hb_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lps22hb_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LPS22HB_REGS_H
#define LPS22HB_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup LPS22HB
@@ -35,6 +36,37 @@
*
*/
+/** @defgroup Endianness definitions
+ * @{
+ *
+ */
+
+#ifndef DRV_BYTE_ORDER
+#ifndef __BYTE_ORDER__
+
+#define DRV_LITTLE_ENDIAN 1234
+#define DRV_BIG_ENDIAN 4321
+
+/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
+ * by uncommenting the define which fits your platform endianness
+ */
+//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
+#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
+
+#else /* defined __BYTE_ORDER__ */
+
+#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
+#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
+#define DRV_BYTE_ORDER __BYTE_ORDER__
+
+#endif /* __BYTE_ORDER__*/
+#endif /* DRV_BYTE_ORDER */
+
+/**
+ * @}
+ *
+ */
+
/** @defgroup STMicroelectronics sensors common types
* @{
*
@@ -43,7 +75,9 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -52,6 +86,16 @@ typedef struct{
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BIG_ENDIAN */
} bitwise_t;
#define PROPERTY_DISABLE (0U)
@@ -65,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -89,15 +134,16 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
- * Unico / Unicleo tools available on STMicroelectronics
- * web site.
+ * You can create a sensor configuration by your own or using
+ * Unico / Unicleo tools available on STMicroelectronics
+ * web site.
*
* @{
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -115,12 +161,12 @@ typedef struct {
*/
-/** @defgroup LSM9DS1_Infos
+/** @defgroup LPS22HB_Infos
* @{
*
*/
- /** I2C Device Address 8 bit format: if SA0=0 -> 0xB9 if SA0=1 -> 0xBB **/
+/** I2C Device Address 8 bit format: if SA0=0 -> 0xB9 if SA0=1 -> 0xBB **/
#define LPS22HB_I2C_ADD_H 0xBBU
#define LPS22HB_I2C_ADD_L 0xB9U
@@ -133,7 +179,9 @@ typedef struct {
*/
#define LPS22HB_INTERRUPT_CFG 0x0BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t pe : 2; /* ple + phe -> pe */
uint8_t lir : 1;
uint8_t diff_en : 1;
@@ -141,22 +189,42 @@ typedef struct {
uint8_t autozero : 1;
uint8_t reset_arp : 1;
uint8_t autorifp : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t autorifp : 1;
+ uint8_t reset_arp : 1;
+ uint8_t autozero : 1;
+ uint8_t reset_az : 1;
+ uint8_t diff_en : 1;
+ uint8_t lir : 1;
+ uint8_t pe : 2; /* ple + phe -> pe */
+#endif /* DRV_BIG_ENDIAN */
} lps22hb_interrupt_cfg_t;
#define LPS22HB_THS_P_L 0x0CU
#define LPS22HB_THS_P_H 0x0DU
#define LPS22HB_WHO_AM_I 0x0FU
#define LPS22HB_CTRL_REG1 0x10U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t bdu : 1;
uint8_t lpfp : 2; /* en_lpfp + lpfp_cfg -> lpfp */
uint8_t odr : 3;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t odr : 3;
+ uint8_t lpfp : 2; /* en_lpfp + lpfp_cfg -> lpfp */
+ uint8_t bdu : 1;
+ uint8_t sim : 1;
+#endif /* DRV_BIG_ENDIAN */
} lps22hb_ctrl_reg1_t;
#define LPS22HB_CTRL_REG2 0x11U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t one_shot : 1;
uint8_t not_used_01 : 1;
uint8_t swreset : 1;
@@ -165,10 +233,22 @@ typedef struct {
uint8_t stop_on_fth : 1;
uint8_t fifo_en : 1;
uint8_t boot : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t boot : 1;
+ uint8_t fifo_en : 1;
+ uint8_t stop_on_fth : 1;
+ uint8_t if_add_inc : 1;
+ uint8_t i2c_dis : 1;
+ uint8_t swreset : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t one_shot : 1;
+#endif /* DRV_BIG_ENDIAN */
} lps22hb_ctrl_reg2_t;
#define LPS22HB_CTRL_REG3 0x12U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int_s : 2;
uint8_t drdy : 1;
uint8_t f_ovr : 1;
@@ -176,13 +256,30 @@ typedef struct {
uint8_t f_fss5 : 1;
uint8_t pp_od : 1;
uint8_t int_h_l : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int_h_l : 1;
+ uint8_t pp_od : 1;
+ uint8_t f_fss5 : 1;
+ uint8_t f_fth : 1;
+ uint8_t f_ovr : 1;
+ uint8_t drdy : 1;
+ uint8_t int_s : 2;
+#endif /* DRV_BIG_ENDIAN */
+
} lps22hb_ctrl_reg3_t;
#define LPS22HB_FIFO_CTRL 0x14U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wtm : 5;
uint8_t f_mode : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t f_mode : 3;
+ uint8_t wtm : 5;
+#endif /* DRV_BIG_ENDIAN */
+
} lps22hb_fifo_ctrl_t;
#define LPS22HB_REF_P_XL 0x15U
@@ -192,35 +289,68 @@ typedef struct {
#define LPS22HB_RPDS_H 0x19U
#define LPS22HB_RES_CONF 0x1AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lc_en : 1;
uint8_t not_used_01 : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 7;
+ uint8_t lc_en : 1;
+#endif /* DRV_BIG_ENDIAN */
+
} lps22hb_res_conf_t;
#define LPS22HB_INT_SOURCE 0x25U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ph : 1;
uint8_t pl : 1;
uint8_t ia : 1;
uint8_t not_used_01 : 4;
uint8_t boot_status : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t boot_status : 1;
+ uint8_t not_used_01 : 4;
+ uint8_t ia : 1;
+ uint8_t pl : 1;
+ uint8_t ph : 1;
+#endif /* DRV_BIG_ENDIAN */
} lps22hb_int_source_t;
#define LPS22HB_FIFO_STATUS 0x26U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fss : 6;
uint8_t ovr : 1;
uint8_t fth_fifo : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fth_fifo : 1;
+ uint8_t ovr : 1;
+ uint8_t fss : 6;
+#endif /* DRV_BIG_ENDIAN */
} lps22hb_fifo_status_t;
#define LPS22HB_STATUS 0x27U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t p_da : 1;
uint8_t t_da : 1;
uint8_t not_used_02 : 2;
uint8_t p_or : 1;
uint8_t t_or : 1;
uint8_t not_used_01 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 2;
+ uint8_t t_or : 1;
+ uint8_t p_or : 1;
+ uint8_t not_used_02 : 2;
+ uint8_t t_da : 1;
+ uint8_t p_da : 1;
+#endif /* DRV_BIG_ENDIAN */
} lps22hb_status_t;
#define LPS22HB_PRESS_OUT_XL 0x28U
@@ -232,9 +362,9 @@ typedef struct {
/**
* @defgroup LPS22HB_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -243,7 +373,8 @@ typedef struct {
*
*/
-typedef union{
+typedef union
+{
lps22hb_interrupt_cfg_t interrupt_cfg;
lps22hb_ctrl_reg1_t ctrl_reg1;
lps22hb_ctrl_reg2_t ctrl_reg2;
@@ -262,13 +393,16 @@ typedef union{
*
*/
-int32_t lps22hb_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lps22hb_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t lps22hb_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lps22hb_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-extern float_t lps22hb_from_lsb_to_hpa(int32_t lsb);
-extern float_t lps22hb_from_lsb_to_degc(int16_t lsb);
+float_t lps22hb_from_lsb_to_hpa(int32_t lsb);
+
+float_t lps22hb_from_lsb_to_degc(int16_t lsb);
int32_t lps22hb_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps22hb_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -277,15 +411,18 @@ int32_t lps22hb_autozero_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps22hb_autozero_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps22hb_pressure_snap_rst_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lps22hb_pressure_snap_rst_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps22hb_pressure_snap_rst_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lps22hb_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps22hb_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps22hb_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lps22hb_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps22hb_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LPS22HB_LPF_ODR_DIV_2 = 0,
LPS22HB_LPF_ODR_DIV_9 = 2,
LPS22HB_LPF_ODR_DIV_20 = 3,
@@ -295,7 +432,8 @@ int32_t lps22hb_low_pass_filter_mode_set(stmdev_ctx_t *ctx,
int32_t lps22hb_low_pass_filter_mode_get(stmdev_ctx_t *ctx,
lps22hb_lpfp_t *val);
-typedef enum {
+typedef enum
+{
LPS22HB_POWER_DOWN = 0,
LPS22HB_ODR_1_Hz = 1,
LPS22HB_ODR_10_Hz = 2,
@@ -307,13 +445,14 @@ int32_t lps22hb_data_rate_set(stmdev_ctx_t *ctx, lps22hb_odr_t val);
int32_t lps22hb_data_rate_get(stmdev_ctx_t *ctx, lps22hb_odr_t *val);
int32_t lps22hb_one_shoot_trigger_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lps22hb_one_shoot_trigger_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps22hb_one_shoot_trigger_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lps22hb_pressure_ref_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lps22hb_pressure_ref_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lps22hb_pressure_ref_set(stmdev_ctx_t *ctx, int32_t val);
+int32_t lps22hb_pressure_ref_get(stmdev_ctx_t *ctx, int32_t *val);
-int32_t lps22hb_pressure_offset_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lps22hb_pressure_offset_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lps22hb_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val);
+int32_t lps22hb_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val);
int32_t lps22hb_press_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -323,9 +462,9 @@ int32_t lps22hb_press_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps22hb_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lps22hb_pressure_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lps22hb_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff);
-int32_t lps22hb_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lps22hb_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff);
int32_t lps22hb_low_pass_rst_get(stmdev_ctx_t *ctx, uint8_t *buff);
@@ -342,13 +481,16 @@ int32_t lps22hb_low_power_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps22hb_boot_status_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef struct{
+typedef struct
+{
lps22hb_fifo_status_t fifo_status;
lps22hb_status_t status;
} lps22hb_dev_stat_t;
-int32_t lps22hb_dev_status_get(stmdev_ctx_t *ctx, lps22hb_dev_stat_t *val);
+int32_t lps22hb_dev_status_get(stmdev_ctx_t *ctx,
+ lps22hb_dev_stat_t *val);
-typedef enum {
+typedef enum
+{
LPS22HB_NO_THRESHOLD = 0,
LPS22HB_POSITIVE = 1,
LPS22HB_NEGATIVE = 2,
@@ -359,7 +501,8 @@ int32_t lps22hb_sign_of_int_threshold_set(stmdev_ctx_t *ctx,
int32_t lps22hb_sign_of_int_threshold_get(stmdev_ctx_t *ctx,
lps22hb_pe_t *val);
-typedef enum {
+typedef enum
+{
LPS22HB_INT_PULSED = 0,
LPS22HB_INT_LATCHED = 1,
} lps22hb_lir_t;
@@ -371,17 +514,20 @@ int32_t lps22hb_int_notification_mode_get(stmdev_ctx_t *ctx,
int32_t lps22hb_int_generation_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps22hb_int_generation_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lps22hb_int_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lps22hb_int_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lps22hb_int_threshold_set(stmdev_ctx_t *ctx, uint16_t val);
+int32_t lps22hb_int_threshold_get(stmdev_ctx_t *ctx, uint16_t *val);
-typedef enum {
+typedef enum
+{
LPS22HB_DRDY_OR_FIFO_FLAGS = 0,
LPS22HB_HIGH_PRES_INT = 1,
LPS22HB_LOW_PRES_INT = 2,
LPS22HB_EVERY_PRES_INT = 3,
} lps22hb_int_s_t;
-int32_t lps22hb_int_pin_mode_set(stmdev_ctx_t *ctx, lps22hb_int_s_t val);
-int32_t lps22hb_int_pin_mode_get(stmdev_ctx_t *ctx, lps22hb_int_s_t *val);
+int32_t lps22hb_int_pin_mode_set(stmdev_ctx_t *ctx,
+ lps22hb_int_s_t val);
+int32_t lps22hb_int_pin_mode_get(stmdev_ctx_t *ctx,
+ lps22hb_int_s_t *val);
int32_t lps22hb_drdy_on_int_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps22hb_drdy_on_int_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -389,36 +535,46 @@ int32_t lps22hb_drdy_on_int_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps22hb_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps22hb_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lps22hb_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lps22hb_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps22hb_fifo_threshold_on_int_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lps22hb_fifo_threshold_on_int_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lps22hb_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps22hb_fifo_full_on_int_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LPS22HB_PUSH_PULL = 0,
LPS22HB_OPEN_DRAIN = 1,
} lps22hb_pp_od_t;
int32_t lps22hb_pin_mode_set(stmdev_ctx_t *ctx, lps22hb_pp_od_t val);
int32_t lps22hb_pin_mode_get(stmdev_ctx_t *ctx, lps22hb_pp_od_t *val);
-typedef enum {
+typedef enum
+{
LPS22HB_ACTIVE_HIGH = 0,
LPS22HB_ACTIVE_LOW = 1,
} lps22hb_int_h_l_t;
-int32_t lps22hb_int_polarity_set(stmdev_ctx_t *ctx, lps22hb_int_h_l_t val);
-int32_t lps22hb_int_polarity_get(stmdev_ctx_t *ctx, lps22hb_int_h_l_t *val);
+int32_t lps22hb_int_polarity_set(stmdev_ctx_t *ctx,
+ lps22hb_int_h_l_t val);
+int32_t lps22hb_int_polarity_get(stmdev_ctx_t *ctx,
+ lps22hb_int_h_l_t *val);
-int32_t lps22hb_int_source_get(stmdev_ctx_t *ctx, lps22hb_int_source_t *val);
+int32_t lps22hb_int_source_get(stmdev_ctx_t *ctx,
+ lps22hb_int_source_t *val);
-int32_t lps22hb_int_on_press_high_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps22hb_int_on_press_high_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lps22hb_int_on_press_low_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps22hb_interrupt_event_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lps22hb_stop_on_fifo_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lps22hb_stop_on_fifo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps22hb_stop_on_fifo_threshold_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lps22hb_stop_on_fifo_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lps22hb_fifo_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps22hb_fifo_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -426,7 +582,8 @@ int32_t lps22hb_fifo_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps22hb_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps22hb_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LPS22HB_BYPASS_MODE = 0,
LPS22HB_FIFO_MODE = 1,
LPS22HB_STREAM_MODE = 2,
@@ -435,8 +592,10 @@ typedef enum {
LPS22HB_DYNAMIC_STREAM_MODE = 6,
LPS22HB_BYPASS_TO_FIFO_MODE = 7,
} lps22hb_f_mode_t;
-int32_t lps22hb_fifo_mode_set(stmdev_ctx_t *ctx, lps22hb_f_mode_t val);
-int32_t lps22hb_fifo_mode_get(stmdev_ctx_t *ctx, lps22hb_f_mode_t *val);
+int32_t lps22hb_fifo_mode_set(stmdev_ctx_t *ctx,
+ lps22hb_f_mode_t val);
+int32_t lps22hb_fifo_mode_get(stmdev_ctx_t *ctx,
+ lps22hb_f_mode_t *val);
int32_t lps22hb_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -444,19 +603,23 @@ int32_t lps22hb_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps22hb_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LPS22HB_SPI_4_WIRE = 0,
LPS22HB_SPI_3_WIRE = 1,
} lps22hb_sim_t;
int32_t lps22hb_spi_mode_set(stmdev_ctx_t *ctx, lps22hb_sim_t val);
int32_t lps22hb_spi_mode_get(stmdev_ctx_t *ctx, lps22hb_sim_t *val);
-typedef enum {
+typedef enum
+{
LPS22HB_I2C_ENABLE = 0,
LPS22HB_I2C_DISABLE = 1,
} lps22hb_i2c_dis_t;
-int32_t lps22hb_i2c_interface_set(stmdev_ctx_t *ctx, lps22hb_i2c_dis_t val);
-int32_t lps22hb_i2c_interface_get(stmdev_ctx_t *ctx, lps22hb_i2c_dis_t *val);
+int32_t lps22hb_i2c_interface_set(stmdev_ctx_t *ctx,
+ lps22hb_i2c_dis_t val);
+int32_t lps22hb_i2c_interface_get(stmdev_ctx_t *ctx,
+ lps22hb_i2c_dis_t *val);
int32_t lps22hb_auto_add_inc_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps22hb_auto_add_inc_get(stmdev_ctx_t *ctx, uint8_t *val);
diff --git a/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.c b/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.c
index 1545489da159113401292032040431aac8975a70..97c8a1cc8e6474f1a4dd55bc78383a5621d86c11 100644
--- a/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.c
+++ b/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file lps22hh_reg.c
- * @author Sensors Software Solution Team
- * @brief LPS22HH driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lps22hh_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LPS22HH driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lps22hh_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps22hh_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lps22hh_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t lps22hh_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps22hh_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t lps22hh_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -85,12 +91,12 @@ int32_t lps22hh_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
*/
float_t lps22hh_from_lsb_to_hpa(uint32_t lsb)
{
- return ( (float_t) lsb / 1048576.0f );
+ return ((float_t) lsb / 1048576.0f);
}
float_t lps22hh_from_lsb_to_celsius(int16_t lsb)
{
- return ( (float_t) lsb / 100.0f );
+ return ((float_t) lsb / 100.0f);
}
/**
@@ -119,11 +125,14 @@ int32_t lps22hh_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val)
lps22hh_interrupt_cfg_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.reset_az = val;
- ret = lps22hh_write_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t*) ®, 1);
+ ret = lps22hh_write_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -140,7 +149,7 @@ int32_t lps22hh_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hh_interrupt_cfg_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t*) ®, 1);
+ ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
*val = reg.reset_az;
return ret;
@@ -159,11 +168,14 @@ int32_t lps22hh_autozero_set(stmdev_ctx_t *ctx, uint8_t val)
lps22hh_interrupt_cfg_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.autozero = val;
- ret = lps22hh_write_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t*) ®, 1);
+ ret = lps22hh_write_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -180,7 +192,7 @@ int32_t lps22hh_autozero_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hh_interrupt_cfg_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t*) ®, 1);
+ ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
*val = reg.autozero;
return ret;
@@ -199,11 +211,14 @@ int32_t lps22hh_pressure_snap_rst_set(stmdev_ctx_t *ctx, uint8_t val)
lps22hh_interrupt_cfg_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.reset_arp = val;
- ret = lps22hh_write_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t*) ®, 1);
+ ret = lps22hh_write_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -220,7 +235,7 @@ int32_t lps22hh_pressure_snap_rst_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hh_interrupt_cfg_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t*) ®, 1);
+ ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
*val = reg.reset_arp;
return ret;
@@ -239,11 +254,14 @@ int32_t lps22hh_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val)
lps22hh_interrupt_cfg_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.autorefp = val;
- ret = lps22hh_write_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t*) ®, 1);
+ ret = lps22hh_write_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -260,7 +278,7 @@ int32_t lps22hh_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hh_interrupt_cfg_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t*) ®, 1);
+ ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
*val = reg.autorefp;
return ret;
@@ -279,11 +297,14 @@ int32_t lps22hh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
lps22hh_ctrl_reg1_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.bdu = val;
- ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t*) ®, 1);
+ ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -300,7 +321,7 @@ int32_t lps22hh_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hh_ctrl_reg1_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t*) ®, 1);
+ ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *) ®, 1);
*val = reg.bdu;
return ret;
@@ -320,19 +341,26 @@ int32_t lps22hh_data_rate_set(stmdev_ctx_t *ctx, lps22hh_odr_t val)
lps22hh_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if (ret == 0) {
- ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
+ ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ctrl_reg1.odr = (uint8_t)val & 0x07U;
- ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ctrl_reg2.low_noise_en = ((uint8_t)val & 0x10U) >> 4;
ctrl_reg2.one_shot = ((uint8_t)val & 0x08U) >> 3;
- ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -350,61 +378,82 @@ int32_t lps22hh_data_rate_get(stmdev_ctx_t *ctx, lps22hh_odr_t *val)
lps22hh_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if (ret == 0) {
- ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
+ ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
- if (ret == 0) {
- ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
+ ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
switch (((ctrl_reg2.low_noise_en << 4) + (ctrl_reg2.one_shot << 3) +
- ctrl_reg1.odr )) {
+ ctrl_reg1.odr))
+ {
case LPS22HH_POWER_DOWN:
*val = LPS22HH_POWER_DOWN;
break;
+
case LPS22HH_ONE_SHOOT:
*val = LPS22HH_ONE_SHOOT;
break;
+
case LPS22HH_1_Hz:
*val = LPS22HH_1_Hz;
break;
+
case LPS22HH_10_Hz:
*val = LPS22HH_10_Hz;
break;
+
case LPS22HH_25_Hz:
*val = LPS22HH_25_Hz;
break;
+
case LPS22HH_50_Hz:
*val = LPS22HH_50_Hz;
break;
+
case LPS22HH_75_Hz:
*val = LPS22HH_75_Hz;
break;
+
case LPS22HH_1_Hz_LOW_NOISE:
*val = LPS22HH_1_Hz_LOW_NOISE;
break;
+
case LPS22HH_10_Hz_LOW_NOISE:
*val = LPS22HH_10_Hz_LOW_NOISE;
break;
+
case LPS22HH_25_Hz_LOW_NOISE:
*val = LPS22HH_25_Hz_LOW_NOISE;
break;
+
case LPS22HH_50_Hz_LOW_NOISE:
*val = LPS22HH_50_Hz_LOW_NOISE;
break;
+
case LPS22HH_75_Hz_LOW_NOISE:
*val = LPS22HH_75_Hz_LOW_NOISE;
break;
+
case LPS22HH_100_Hz:
*val = LPS22HH_100_Hz;
break;
+
case LPS22HH_200_Hz:
*val = LPS22HH_200_Hz;
break;
+
default:
*val = LPS22HH_POWER_DOWN;
break;
}
}
+
return ret;
}
@@ -423,8 +472,8 @@ int32_t lps22hh_pressure_ref_set(stmdev_ctx_t *ctx, int16_t val)
uint8_t buff[2];
int32_t ret;
- buff[1] = (uint8_t) ((uint16_t)val / 256U);
- buff[0] = (uint8_t) ((uint16_t)val - (buff[1] * 256U));
+ buff[1] = (uint8_t)((uint16_t)val / 256U);
+ buff[0] = (uint8_t)((uint16_t)val - (buff[1] * 256U));
ret = lps22hh_write_reg(ctx, LPS22HH_REF_P_L, buff, 2);
return ret;
@@ -468,8 +517,8 @@ int32_t lps22hh_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val)
uint8_t buff[2];
int32_t ret;
- buff[1] = (uint8_t) ((uint16_t)val / 256U);
- buff[0] = (uint8_t) ((uint16_t)val - (buff[1] * 256U));
+ buff[1] = (uint8_t)((uint16_t)val / 256U);
+ buff[0] = (uint8_t)((uint16_t)val - (buff[1] * 256U));
ret = lps22hh_write_reg(ctx, LPS22HH_RPDS_L, buff, 2);
return ret;
@@ -506,20 +555,26 @@ int32_t lps22hh_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps22hh_all_sources_get(stmdev_ctx_t *ctx, lps22hh_all_sources_t *val)
+int32_t lps22hh_all_sources_get(stmdev_ctx_t *ctx,
+ lps22hh_all_sources_t *val)
{
int32_t ret;
ret = lps22hh_read_reg(ctx, LPS22HH_INT_SOURCE,
- (uint8_t*) &(val->int_source), 1);
- if (ret == 0) {
+ (uint8_t *) & (val->int_source), 1);
+
+ if (ret == 0)
+ {
ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS2,
- (uint8_t*) &(val->fifo_status2), 1);
+ (uint8_t *) & (val->fifo_status2), 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lps22hh_read_reg(ctx, LPS22HH_STATUS,
- (uint8_t*) &(val->status), 1);
+ (uint8_t *) & (val->status), 1);
}
+
return ret;
}
@@ -531,10 +586,13 @@ int32_t lps22hh_all_sources_get(stmdev_ctx_t *ctx, lps22hh_all_sources_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps22hh_status_reg_get(stmdev_ctx_t *ctx, lps22hh_status_t *val)
+int32_t lps22hh_status_reg_get(stmdev_ctx_t *ctx,
+ lps22hh_status_t *val)
{
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_STATUS, (uint8_t*) val, 1);
+
+ ret = lps22hh_read_reg(ctx, LPS22HH_STATUS, (uint8_t *) val, 1);
+
return ret;
}
@@ -546,12 +604,13 @@ int32_t lps22hh_status_reg_get(stmdev_ctx_t *ctx, lps22hh_status_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps22hh_press_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lps22hh_press_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lps22hh_status_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_STATUS, (uint8_t*) ®, 1);
+ ret = lps22hh_read_reg(ctx, LPS22HH_STATUS, (uint8_t *) ®, 1);
*val = reg.p_da;
return ret;
@@ -565,12 +624,13 @@ int32_t lps22hh_press_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps22hh_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lps22hh_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lps22hh_status_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_STATUS, (uint8_t*) ®, 1);
+ ret = lps22hh_read_reg(ctx, LPS22HH_STATUS, (uint8_t *) ®, 1);
*val = reg.t_da;
return ret;
@@ -599,8 +659,8 @@ int32_t lps22hh_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t lps22hh_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff)
{
int32_t ret;
- uint8_t reg[3];
+ uint8_t reg[3];
ret = lps22hh_read_reg(ctx, LPS22HH_PRESS_OUT_XL, reg, 3);
*buff = reg[2];
*buff = (*buff * 256) + reg[1];
@@ -621,8 +681,8 @@ int32_t lps22hh_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff)
int32_t lps22hh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff)
{
int32_t ret;
- uint8_t reg[2];
+ uint8_t reg[2];
ret = lps22hh_read_reg(ctx, LPS22HH_TEMP_OUT_L, reg, 2);
*buff = reg[1];
*buff = (*buff * 256) + reg[0];
@@ -638,11 +698,12 @@ int32_t lps22hh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps22hh_fifo_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff)
+int32_t lps22hh_fifo_pressure_raw_get(stmdev_ctx_t *ctx,
+ uint32_t *buff)
{
int32_t ret;
- uint8_t reg[3];
+ uint8_t reg[3];
ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_DATA_OUT_PRESS_XL, reg, 3);
*buff = reg[2];
*buff = (*buff * 256) + reg[1];
@@ -660,11 +721,12 @@ int32_t lps22hh_fifo_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps22hh_fifo_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff)
+int32_t lps22hh_fifo_temperature_raw_get(stmdev_ctx_t *ctx,
+ int16_t *buff)
{
int32_t ret;
- uint8_t reg[2];
+ uint8_t reg[2];
ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_DATA_OUT_TEMP_L, reg, 2);
*buff = reg[1];
*buff = (*buff * 256) + reg[0];
@@ -695,7 +757,9 @@ int32_t lps22hh_fifo_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff)
int32_t lps22hh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lps22hh_read_reg(ctx, LPS22HH_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -713,11 +777,14 @@ int32_t lps22hh_reset_set(stmdev_ctx_t *ctx, uint8_t val)
lps22hh_ctrl_reg2_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.swreset = val;
- ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t*) ®, 1);
+ ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -735,7 +802,7 @@ int32_t lps22hh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hh_ctrl_reg2_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t*) ®, 1);
+ ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1);
*val = reg.swreset;
return ret;
@@ -756,11 +823,14 @@ int32_t lps22hh_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
lps22hh_ctrl_reg2_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.if_add_inc = val;
- ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t*) ®, 1);
+ ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -779,7 +849,7 @@ int32_t lps22hh_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hh_ctrl_reg2_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t*) ®, 1);
+ ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1);
*val = reg.if_add_inc;
return ret;
@@ -799,11 +869,14 @@ int32_t lps22hh_boot_set(stmdev_ctx_t *ctx, uint8_t val)
lps22hh_ctrl_reg2_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.boot = val;
- ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t*) ®, 1);
+ ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -821,7 +894,7 @@ int32_t lps22hh_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hh_ctrl_reg2_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t*) ®, 1);
+ ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1);
*val = reg.boot;
return ret;
@@ -848,16 +921,20 @@ int32_t lps22hh_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps22hh_lp_bandwidth_set(stmdev_ctx_t *ctx, lps22hh_lpfp_cfg_t val)
+int32_t lps22hh_lp_bandwidth_set(stmdev_ctx_t *ctx,
+ lps22hh_lpfp_cfg_t val)
{
lps22hh_ctrl_reg1_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.lpfp_cfg = (uint8_t)val;
- ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t*) ®, 1);
+ ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -869,26 +946,32 @@ int32_t lps22hh_lp_bandwidth_set(stmdev_ctx_t *ctx, lps22hh_lpfp_cfg_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps22hh_lp_bandwidth_get(stmdev_ctx_t *ctx, lps22hh_lpfp_cfg_t *val)
+int32_t lps22hh_lp_bandwidth_get(stmdev_ctx_t *ctx,
+ lps22hh_lpfp_cfg_t *val)
{
lps22hh_ctrl_reg1_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t*) ®, 1);
- switch (reg.lpfp_cfg) {
- case LPS22HH_LPF_ODR_DIV_2:
- *val = LPS22HH_LPF_ODR_DIV_2;
- break;
- case LPS22HH_LPF_ODR_DIV_9:
- *val = LPS22HH_LPF_ODR_DIV_9;
- break;
- case LPS22HH_LPF_ODR_DIV_20:
- *val = LPS22HH_LPF_ODR_DIV_20;
- break;
- default:
- *val = LPS22HH_LPF_ODR_DIV_2;
- break;
- }
+ ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *) ®, 1);
+
+ switch (reg.lpfp_cfg)
+ {
+ case LPS22HH_LPF_ODR_DIV_2:
+ *val = LPS22HH_LPF_ODR_DIV_2;
+ break;
+
+ case LPS22HH_LPF_ODR_DIV_9:
+ *val = LPS22HH_LPF_ODR_DIV_9;
+ break;
+
+ case LPS22HH_LPF_ODR_DIV_20:
+ *val = LPS22HH_LPF_ODR_DIV_20;
+ break;
+
+ default:
+ *val = LPS22HH_LPF_ODR_DIV_2;
+ break;
+ }
return ret;
}
@@ -920,11 +1003,14 @@ int32_t lps22hh_i2c_interface_set(stmdev_ctx_t *ctx,
lps22hh_if_ctrl_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.i2c_disable = (uint8_t)val;
- ret = lps22hh_write_reg(ctx, LPS22HH_IF_CTRL, (uint8_t*) ®, 1);
+ ret = lps22hh_write_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -942,18 +1028,22 @@ int32_t lps22hh_i2c_interface_get(stmdev_ctx_t *ctx,
lps22hh_if_ctrl_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t*) ®, 1);
- switch (reg.i2c_disable) {
- case LPS22HH_I2C_ENABLE:
- *val = LPS22HH_I2C_ENABLE;
- break;
- case LPS22HH_I2C_DISABLE:
- *val = LPS22HH_I2C_DISABLE;
- break;
- default:
- *val = LPS22HH_I2C_ENABLE;
- break;
- }
+ ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1);
+
+ switch (reg.i2c_disable)
+ {
+ case LPS22HH_I2C_ENABLE:
+ *val = LPS22HH_I2C_ENABLE;
+ break;
+
+ case LPS22HH_I2C_DISABLE:
+ *val = LPS22HH_I2C_DISABLE;
+ break;
+
+ default:
+ *val = LPS22HH_I2C_ENABLE;
+ break;
+ }
return ret;
}
@@ -972,12 +1062,15 @@ int32_t lps22hh_i3c_interface_set(stmdev_ctx_t *ctx,
lps22hh_if_ctrl_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.i3c_disable = ((uint8_t)val & 0x01u);
reg.int_en_i3c = ((uint8_t)val & 0x10U) >> 4;
- ret = lps22hh_write_reg(ctx, LPS22HH_IF_CTRL, (uint8_t*) ®, 1);
+ ret = lps22hh_write_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -995,22 +1088,27 @@ int32_t lps22hh_i3c_interface_get(stmdev_ctx_t *ctx,
lps22hh_if_ctrl_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t*) ®, 1);
+ ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1);
- switch ((reg.int_en_i3c << 4) + reg.int_en_i3c) {
+ switch ((reg.int_en_i3c << 4) + reg.int_en_i3c)
+ {
case LPS22HH_I3C_ENABLE:
*val = LPS22HH_I3C_ENABLE;
break;
+
case LPS22HH_I3C_ENABLE_INT_PIN_ENABLE:
*val = LPS22HH_I3C_ENABLE_INT_PIN_ENABLE;
break;
+
case LPS22HH_I3C_DISABLE:
*val = LPS22HH_I3C_DISABLE;
break;
+
default:
*val = LPS22HH_I3C_ENABLE;
break;
}
+
return ret;
}
@@ -1022,16 +1120,20 @@ int32_t lps22hh_i3c_interface_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps22hh_sdo_sa0_mode_set(stmdev_ctx_t *ctx, lps22hh_pu_en_t val)
+int32_t lps22hh_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
+ lps22hh_pu_en_t val)
{
lps22hh_if_ctrl_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.sdo_pu_en = (uint8_t)val;
- ret = lps22hh_write_reg(ctx, LPS22HH_IF_CTRL, (uint8_t*) ®, 1);
+ ret = lps22hh_write_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1043,19 +1145,24 @@ int32_t lps22hh_sdo_sa0_mode_set(stmdev_ctx_t *ctx, lps22hh_pu_en_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps22hh_sdo_sa0_mode_get(stmdev_ctx_t *ctx, lps22hh_pu_en_t *val)
+int32_t lps22hh_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
+ lps22hh_pu_en_t *val)
{
lps22hh_if_ctrl_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t*) ®, 1);
- switch (reg.sdo_pu_en) {
+ ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1);
+
+ switch (reg.sdo_pu_en)
+ {
case LPS22HH_PULL_UP_DISCONNECT:
*val = LPS22HH_PULL_UP_DISCONNECT;
break;
+
case LPS22HH_PULL_UP_CONNECT:
*val = LPS22HH_PULL_UP_CONNECT;
break;
+
default:
*val = LPS22HH_PULL_UP_DISCONNECT;
break;
@@ -1077,11 +1184,14 @@ int32_t lps22hh_sda_mode_set(stmdev_ctx_t *ctx, lps22hh_pu_en_t val)
lps22hh_if_ctrl_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.sda_pu_en = (uint8_t)val;
- ret = lps22hh_write_reg(ctx, LPS22HH_IF_CTRL, (uint8_t*) ®, 1);
+ ret = lps22hh_write_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1098,18 +1208,23 @@ int32_t lps22hh_sda_mode_get(stmdev_ctx_t *ctx, lps22hh_pu_en_t *val)
lps22hh_if_ctrl_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t*) ®, 1);
- switch (reg.sda_pu_en) {
+ ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1);
+
+ switch (reg.sda_pu_en)
+ {
case LPS22HH_PULL_UP_DISCONNECT:
*val = LPS22HH_PULL_UP_DISCONNECT;
break;
+
case LPS22HH_PULL_UP_CONNECT:
*val = LPS22HH_PULL_UP_CONNECT;
break;
+
default:
*val = LPS22HH_PULL_UP_DISCONNECT;
break;
}
+
return ret;
}
@@ -1126,11 +1241,14 @@ int32_t lps22hh_spi_mode_set(stmdev_ctx_t *ctx, lps22hh_sim_t val)
lps22hh_ctrl_reg1_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.sim = (uint8_t)val;
- ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t*) ®, 1);
+ ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1147,18 +1265,23 @@ int32_t lps22hh_spi_mode_get(stmdev_ctx_t *ctx, lps22hh_sim_t *val)
lps22hh_ctrl_reg1_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t*) ®, 1);
- switch (reg.sim) {
+ ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *) ®, 1);
+
+ switch (reg.sim)
+ {
case LPS22HH_SPI_4_WIRE:
*val = LPS22HH_SPI_4_WIRE;
break;
+
case LPS22HH_SPI_3_WIRE:
*val = LPS22HH_SPI_3_WIRE;
break;
+
default:
*val = LPS22HH_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -1183,16 +1306,20 @@ int32_t lps22hh_spi_mode_get(stmdev_ctx_t *ctx, lps22hh_sim_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps22hh_int_notification_set(stmdev_ctx_t *ctx, lps22hh_lir_t val)
+int32_t lps22hh_int_notification_set(stmdev_ctx_t *ctx,
+ lps22hh_lir_t val)
{
lps22hh_interrupt_cfg_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.lir = (uint8_t)val;
- ret = lps22hh_write_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t*) ®, 1);
+ ret = lps22hh_write_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1204,24 +1331,29 @@ int32_t lps22hh_int_notification_set(stmdev_ctx_t *ctx, lps22hh_lir_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps22hh_int_notification_get(stmdev_ctx_t *ctx, lps22hh_lir_t *val)
+int32_t lps22hh_int_notification_get(stmdev_ctx_t *ctx,
+ lps22hh_lir_t *val)
{
lps22hh_interrupt_cfg_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t*) ®, 1);
+ ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
- switch (reg.lir) {
+ switch (reg.lir)
+ {
case LPS22HH_INT_PULSED:
*val = LPS22HH_INT_PULSED;
break;
+
case LPS22HH_INT_LATCHED:
*val = LPS22HH_INT_LATCHED;
break;
+
default:
*val = LPS22HH_INT_PULSED;
break;
}
+
return ret;
}
@@ -1238,10 +1370,12 @@ int32_t lps22hh_pin_mode_set(stmdev_ctx_t *ctx, lps22hh_pp_od_t val)
lps22hh_ctrl_reg2_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.pp_od = (uint8_t)val;
- ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t*) ®, 1);
+ ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1);
}
return ret;
@@ -1260,16 +1394,18 @@ int32_t lps22hh_pin_mode_get(stmdev_ctx_t *ctx, lps22hh_pp_od_t *val)
lps22hh_ctrl_reg2_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t*) ®, 1);
+ ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1);
-
- switch (reg.pp_od) {
+ switch (reg.pp_od)
+ {
case LPS22HH_PUSH_PULL:
*val = LPS22HH_PUSH_PULL;
break;
+
case LPS22HH_OPEN_DRAIN:
*val = LPS22HH_OPEN_DRAIN;
break;
+
default:
*val = LPS22HH_PUSH_PULL;
break;
@@ -1286,15 +1422,18 @@ int32_t lps22hh_pin_mode_get(stmdev_ctx_t *ctx, lps22hh_pp_od_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps22hh_pin_polarity_set(stmdev_ctx_t *ctx, lps22hh_int_h_l_t val)
+int32_t lps22hh_pin_polarity_set(stmdev_ctx_t *ctx,
+ lps22hh_int_h_l_t val)
{
lps22hh_ctrl_reg2_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.int_h_l = (uint8_t)val;
- ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t*) ®, 1);
+ ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1);
}
return ret;
@@ -1308,20 +1447,24 @@ int32_t lps22hh_pin_polarity_set(stmdev_ctx_t *ctx, lps22hh_int_h_l_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps22hh_pin_polarity_get(stmdev_ctx_t *ctx, lps22hh_int_h_l_t *val)
+int32_t lps22hh_pin_polarity_get(stmdev_ctx_t *ctx,
+ lps22hh_int_h_l_t *val)
{
lps22hh_ctrl_reg2_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t*) ®, 1);
+ ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1);
- switch (reg.int_h_l) {
+ switch (reg.int_h_l)
+ {
case LPS22HH_ACTIVE_HIGH:
*val = LPS22HH_ACTIVE_HIGH;
break;
+
case LPS22HH_ACTIVE_LOW:
*val = LPS22HH_ACTIVE_LOW;
break;
+
default:
*val = LPS22HH_ACTIVE_HIGH;
break;
@@ -1342,7 +1485,9 @@ int32_t lps22hh_pin_int_route_set(stmdev_ctx_t *ctx,
lps22hh_ctrl_reg3_t *val)
{
int32_t ret;
- ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t*) val, 1);
+
+ ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t *) val, 1);
+
return ret;
}
@@ -1358,7 +1503,9 @@ int32_t lps22hh_pin_int_route_get(stmdev_ctx_t *ctx,
lps22hh_ctrl_reg3_t *val)
{
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t*) val, 1);
+
+ ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t *) val, 1);
+
return ret;
}
@@ -1383,23 +1530,31 @@ int32_t lps22hh_pin_int_route_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps22hh_int_on_threshold_set(stmdev_ctx_t *ctx, lps22hh_pe_t val)
+int32_t lps22hh_int_on_threshold_set(stmdev_ctx_t *ctx,
+ lps22hh_pe_t val)
{
lps22hh_interrupt_cfg_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.pe = (uint8_t)val;
- if (val == LPS22HH_NO_THRESHOLD){
+ if (val == LPS22HH_NO_THRESHOLD)
+ {
reg.diff_en = PROPERTY_DISABLE;
}
- else{
+
+ else
+ {
reg.diff_en = PROPERTY_ENABLE;
}
- ret = lps22hh_write_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t*) ®, 1);
+
+ ret = lps22hh_write_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1411,26 +1566,32 @@ int32_t lps22hh_int_on_threshold_set(stmdev_ctx_t *ctx, lps22hh_pe_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps22hh_int_on_threshold_get(stmdev_ctx_t *ctx, lps22hh_pe_t *val)
+int32_t lps22hh_int_on_threshold_get(stmdev_ctx_t *ctx,
+ lps22hh_pe_t *val)
{
lps22hh_interrupt_cfg_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t*) ®, 1);
+ ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
- switch (reg.pe) {
+ switch (reg.pe)
+ {
case LPS22HH_NO_THRESHOLD:
*val = LPS22HH_NO_THRESHOLD;
break;
+
case LPS22HH_POSITIVE:
*val = LPS22HH_POSITIVE;
break;
+
case LPS22HH_NEGATIVE:
*val = LPS22HH_NEGATIVE;
break;
+
case LPS22HH_BOTH:
*val = LPS22HH_BOTH;
break;
+
default:
*val = LPS22HH_NO_THRESHOLD;
break;
@@ -1450,18 +1611,20 @@ int32_t lps22hh_int_on_threshold_get(stmdev_ctx_t *ctx, lps22hh_pe_t *val)
int32_t lps22hh_int_treshold_set(stmdev_ctx_t *ctx, uint16_t buff)
{
int32_t ret;
+
lps22hh_ths_p_l_t ths_p_l;
lps22hh_ths_p_h_t ths_p_h;
-
- ths_p_h.ths = (uint8_t) (buff / 256U);
- ths_p_l.ths = (uint8_t) (buff - (ths_p_h.ths * 256U));
-
+ ths_p_h.ths = (uint8_t)(buff / 256U);
+ ths_p_l.ths = (uint8_t)(buff - (ths_p_h.ths * 256U));
ret = lps22hh_write_reg(ctx, LPS22HH_THS_P_L,
- (uint8_t*)&ths_p_l, 1);
- if (ret == 0) {
- ret = lps22hh_write_reg(ctx, LPS22HH_THS_P_H,
- (uint8_t*)&ths_p_h, 1);
+ (uint8_t *)&ths_p_l, 1);
+
+ if (ret == 0)
+ {
+ ret = lps22hh_write_reg(ctx, LPS22HH_THS_P_H,
+ (uint8_t *)&ths_p_h, 1);
}
+
return ret;
}
@@ -1476,17 +1639,20 @@ int32_t lps22hh_int_treshold_set(stmdev_ctx_t *ctx, uint16_t buff)
int32_t lps22hh_int_treshold_get(stmdev_ctx_t *ctx, uint16_t *buff)
{
int32_t ret;
+
lps22hh_ths_p_l_t ths_p_l;
lps22hh_ths_p_h_t ths_p_h;
-
ret = lps22hh_read_reg(ctx, LPS22HH_THS_P_L,
- (uint8_t*)&ths_p_l, 1);
- if (ret == 0) {
- ret = lps22hh_read_reg(ctx, LPS22HH_THS_P_H,
- (uint8_t*)&ths_p_h, 1);
- *buff = (uint16_t)ths_p_h.ths;
- *buff = (*buff * 256U) + (uint16_t)ths_p_l.ths;
- }
+ (uint8_t *)&ths_p_l, 1);
+
+ if (ret == 0)
+ {
+ ret = lps22hh_read_reg(ctx, LPS22HH_THS_P_H,
+ (uint8_t *)&ths_p_h, 1);
+ *buff = (uint16_t)ths_p_h.ths;
+ *buff = (*buff * 256U) + (uint16_t)ths_p_l.ths;
+ }
+
return ret;
}
@@ -1515,11 +1681,14 @@ int32_t lps22hh_fifo_mode_set(stmdev_ctx_t *ctx, lps22hh_f_mode_t val)
lps22hh_fifo_ctrl_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_CTRL, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.f_mode = (uint8_t)val;
- ret = lps22hh_write_reg(ctx, LPS22HH_FIFO_CTRL, (uint8_t*) ®, 1);
+ ret = lps22hh_write_reg(ctx, LPS22HH_FIFO_CTRL, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1531,35 +1700,44 @@ int32_t lps22hh_fifo_mode_set(stmdev_ctx_t *ctx, lps22hh_f_mode_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps22hh_fifo_mode_get(stmdev_ctx_t *ctx, lps22hh_f_mode_t *val)
+int32_t lps22hh_fifo_mode_get(stmdev_ctx_t *ctx,
+ lps22hh_f_mode_t *val)
{
lps22hh_fifo_ctrl_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_CTRL, (uint8_t*) ®, 1);
+ ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_CTRL, (uint8_t *) ®, 1);
- switch (reg.f_mode) {
+ switch (reg.f_mode)
+ {
case LPS22HH_BYPASS_MODE:
*val = LPS22HH_BYPASS_MODE;
break;
+
case LPS22HH_FIFO_MODE:
*val = LPS22HH_FIFO_MODE;
break;
+
case LPS22HH_STREAM_MODE:
*val = LPS22HH_STREAM_MODE;
break;
+
case LPS22HH_DYNAMIC_STREAM_MODE:
*val = LPS22HH_DYNAMIC_STREAM_MODE;
break;
+
case LPS22HH_BYPASS_TO_FIFO_MODE:
*val = LPS22HH_BYPASS_TO_FIFO_MODE;
break;
+
case LPS22HH_BYPASS_TO_STREAM_MODE:
*val = LPS22HH_BYPASS_TO_STREAM_MODE;
break;
+
case LPS22HH_STREAM_TO_FIFO_MODE:
*val = LPS22HH_STREAM_TO_FIFO_MODE;
break;
+
default:
*val = LPS22HH_BYPASS_MODE;
break;
@@ -1582,11 +1760,14 @@ int32_t lps22hh_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
lps22hh_fifo_ctrl_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_CTRL, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.stop_on_wtm = val;
- ret = lps22hh_write_reg(ctx, LPS22HH_FIFO_CTRL, (uint8_t*) ®, 1);
+ ret = lps22hh_write_reg(ctx, LPS22HH_FIFO_CTRL, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1604,7 +1785,7 @@ int32_t lps22hh_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hh_fifo_ctrl_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_CTRL, (uint8_t*) ®, 1);
+ ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_CTRL, (uint8_t *) ®, 1);
*val = reg.stop_on_wtm;
return ret;
@@ -1623,11 +1804,14 @@ int32_t lps22hh_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
lps22hh_fifo_wtm_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_WTM, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_WTM, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.wtm = val;
- ret = lps22hh_write_reg(ctx, LPS22HH_FIFO_WTM, (uint8_t*) ®, 1);
+ ret = lps22hh_write_reg(ctx, LPS22HH_FIFO_WTM, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1644,7 +1828,7 @@ int32_t lps22hh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hh_fifo_wtm_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_WTM, (uint8_t*) ®, 1);
+ ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_WTM, (uint8_t *) ®, 1);
*val = reg.wtm;
return ret;
@@ -1661,7 +1845,9 @@ int32_t lps22hh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t lps22hh_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS1, buff, 1);
+
return ret;
}
@@ -1673,10 +1859,13 @@ int32_t lps22hh_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps22hh_fifo_src_get(stmdev_ctx_t *ctx, lps22hh_fifo_status2_t *val)
+int32_t lps22hh_fifo_src_get(stmdev_ctx_t *ctx,
+ lps22hh_fifo_status2_t *val)
{
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS2, (uint8_t*) val, 1);
+
+ ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS2, (uint8_t *) val, 1);
+
return ret;
}
@@ -1693,7 +1882,7 @@ int32_t lps22hh_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hh_fifo_status2_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS2, (uint8_t*) ®, 1);
+ ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS2, (uint8_t *) ®, 1);
*val = reg.fifo_full_ia;
return ret;
@@ -1712,7 +1901,7 @@ int32_t lps22hh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hh_fifo_status2_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS2, (uint8_t*) ®, 1);
+ ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS2, (uint8_t *) ®, 1);
*val = reg.fifo_ovr_ia;
return ret;
@@ -1731,7 +1920,7 @@ int32_t lps22hh_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hh_fifo_status2_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS2, (uint8_t*)®, 1);
+ ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS2, (uint8_t *)®, 1);
*val = reg.fifo_wtm_ia;
return ret;
@@ -1742,6 +1931,7 @@ int32_t lps22hh_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param stmdev_ctx_t *ctx: read / write interface definitions
* @param uint8_t val: change the values of f_ovr in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lps22hh_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1749,11 +1939,14 @@ int32_t lps22hh_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
lps22hh_ctrl_reg3_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.int_f_ovr = val;
- ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t*)®, 1);
+ ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1762,6 +1955,7 @@ int32_t lps22hh_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param stmdev_ctx_t *ctx: read / write interface definitions
* @param uint8_t: change the values of f_ovr in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lps22hh_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1769,7 +1963,7 @@ int32_t lps22hh_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hh_ctrl_reg3_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t*)®, 1);
+ ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t *)®, 1);
*val = reg.int_f_ovr;
return ret;
@@ -1780,18 +1974,23 @@ int32_t lps22hh_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param stmdev_ctx_t *ctx: read / write interface definitions
* @param uint8_t val: change the values of f_fth in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps22hh_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lps22hh_fifo_threshold_on_int_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lps22hh_ctrl_reg3_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.int_f_wtm = val;
- ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t*)®, 1);
+ ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1800,14 +1999,16 @@ int32_t lps22hh_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param lps22hb_ctx_t *ctx: read / write interface definitions
* @param uint8_t: change the values of f_fth in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps22hh_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lps22hh_fifo_threshold_on_int_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lps22hh_ctrl_reg3_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t*)®, 1);
+ ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t *)®, 1);
*val = reg.int_f_wtm;
return ret;
@@ -1818,6 +2019,7 @@ int32_t lps22hh_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param stmdev_ctx_t *ctx: read / write interface definitions
* @param uint8_t val: change the values of f_fss5 in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lps22hh_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1825,11 +2027,14 @@ int32_t lps22hh_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
lps22hh_ctrl_reg3_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.int_f_full = val;
- ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t*)®, 1);
+ ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1838,6 +2043,7 @@ int32_t lps22hh_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param stmdev_ctx_t *ctx: read / write interface definitions
* @param uint8_t: change the values of f_fss5 in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lps22hh_fifo_full_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1845,7 +2051,7 @@ int32_t lps22hh_fifo_full_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
lps22hh_ctrl_reg3_t reg;
int32_t ret;
- ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t*)®, 1);
+ ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t *)®, 1);
*val = reg.int_f_full;
return ret;
diff --git a/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.h b/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.h
index 5e7a2088a5e225a914923e477fc351b63ee8ed0b..dfc2a9a5f094e9021195f66439305754da54abef 100644
--- a/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.h
+++ b/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file lps22hh_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lps22hh_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lps22hh_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lps22hh_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LPS22HH_REGS_H
#define LPS22HH_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup LPS22HH
@@ -74,7 +75,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -107,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -131,7 +134,7 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
+ * You can create a sensor configuration by your own or using
* Unico / Unicleo tools available on STMicroelectronics
* web site.
*
@@ -139,7 +142,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -174,7 +178,8 @@ typedef struct {
*/
#define LPS22HH_INTERRUPT_CFG 0x0BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t pe : 2; /* ple + phe */
uint8_t lir : 1;
@@ -195,12 +200,14 @@ typedef struct {
} lps22hh_interrupt_cfg_t;
#define LPS22HH_THS_P_L 0x0CU
-typedef struct {
+typedef struct
+{
uint8_t ths : 8;
} lps22hh_ths_p_l_t;
#define LPS22HH_THS_P_H 0x0DU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t not_used_01 : 1;
@@ -211,7 +218,8 @@ typedef struct {
} lps22hh_ths_p_h_t;
#define LPS22HH_IF_CTRL 0x0EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t i2c_disable : 1;
uint8_t i3c_disable : 1;
@@ -233,7 +241,8 @@ typedef struct {
#define LPS22HH_WHO_AM_I 0x0FU
#define LPS22HH_CTRL_REG1 0x10U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t bdu : 1;
@@ -250,7 +259,8 @@ typedef struct {
} lps22hh_ctrl_reg1_t;
#define LPS22HH_CTRL_REG2 0x11U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t one_shot : 1;
uint8_t low_noise_en : 1;
@@ -273,7 +283,8 @@ typedef struct {
} lps22hh_ctrl_reg2_t;
#define LPS22HH_CTRL_REG3 0x12U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int_s : 2;
uint8_t drdy : 1;
@@ -292,20 +303,24 @@ typedef struct {
} lps22hh_ctrl_reg3_t;
#define LPS22HH_FIFO_CTRL 0x13U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t f_mode : 3; /* f_mode + trig_modes */
+uint8_t f_mode :
+ 3; /* f_mode + trig_modes */
uint8_t stop_on_wtm : 1;
uint8_t not_used_01 : 4;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used_01 : 4;
uint8_t stop_on_wtm : 1;
- uint8_t f_mode : 3; /* f_mode + trig_modes */
+uint8_t f_mode :
+ 3; /* f_mode + trig_modes */
#endif /* DRV_BYTE_ORDER */
} lps22hh_fifo_ctrl_t;
#define LPS22HH_FIFO_WTM 0x14U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wtm : 7;
uint8_t not_used_01 : 1;
@@ -320,7 +335,8 @@ typedef struct {
#define LPS22HH_RPDS_L 0x18U
#define LPS22HH_RPDS_H 0x19U
#define LPS22HH_INT_SOURCE 0x24U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ph : 1;
uint8_t pl : 1;
@@ -338,7 +354,8 @@ typedef struct {
#define LPS22HH_FIFO_STATUS1 0x25U
#define LPS22HH_FIFO_STATUS2 0x26U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 5;
uint8_t fifo_full_ia : 1;
@@ -353,7 +370,8 @@ typedef struct {
} lps22hh_fifo_status2_t;
#define LPS22HH_STATUS 0x27U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t p_da : 1;
uint8_t t_da : 1;
@@ -384,9 +402,9 @@ typedef struct {
/**
* @defgroup LPS22HH_Register_Union
- * @brief This union group all the registers that has a bitfield
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -394,7 +412,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
lps22hh_interrupt_cfg_t interrupt_cfg;
lps22hh_if_ctrl_t if_ctrl;
lps22hh_ctrl_reg1_t ctrl_reg1;
@@ -414,12 +433,15 @@ typedef union{
*
*/
-int32_t lps22hh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lps22hh_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t lps22hh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lps22hh_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
float_t lps22hh_from_lsb_to_hpa(uint32_t lsb);
+
float_t lps22hh_from_lsb_to_celsius(int16_t lsb);
int32_t lps22hh_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val);
@@ -429,15 +451,18 @@ int32_t lps22hh_autozero_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps22hh_autozero_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps22hh_pressure_snap_rst_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lps22hh_pressure_snap_rst_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps22hh_pressure_snap_rst_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lps22hh_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps22hh_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps22hh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lps22hh_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps22hh_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LPS22HH_POWER_DOWN = 0x00,
LPS22HH_ONE_SHOOT = 0x08,
LPS22HH_1_Hz = 0x01,
@@ -462,7 +487,8 @@ int32_t lps22hh_pressure_ref_get(stmdev_ctx_t *ctx, int16_t *val);
int32_t lps22hh_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val);
int32_t lps22hh_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val);
-typedef struct{
+typedef struct
+{
lps22hh_int_source_t int_source;
lps22hh_fifo_status2_t fifo_status2;
lps22hh_status_t status;
@@ -470,19 +496,24 @@ typedef struct{
int32_t lps22hh_all_sources_get(stmdev_ctx_t *ctx,
lps22hh_all_sources_t *val);
-int32_t lps22hh_status_reg_get(stmdev_ctx_t *ctx, lps22hh_status_t *val);
+int32_t lps22hh_status_reg_get(stmdev_ctx_t *ctx,
+ lps22hh_status_t *val);
-int32_t lps22hh_press_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps22hh_press_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lps22hh_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps22hh_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lps22hh_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff);
int32_t lps22hh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff);
-int32_t lps22hh_fifo_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff);
+int32_t lps22hh_fifo_pressure_raw_get(stmdev_ctx_t *ctx,
+ uint32_t *buff);
-int32_t lps22hh_fifo_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff);
+int32_t lps22hh_fifo_temperature_raw_get(stmdev_ctx_t *ctx,
+ int16_t *buff);
int32_t lps22hh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
@@ -495,15 +526,19 @@ int32_t lps22hh_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps22hh_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps22hh_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LPS22HH_LPF_ODR_DIV_2 = 0,
LPS22HH_LPF_ODR_DIV_9 = 2,
LPS22HH_LPF_ODR_DIV_20 = 3,
} lps22hh_lpfp_cfg_t;
-int32_t lps22hh_lp_bandwidth_set(stmdev_ctx_t *ctx, lps22hh_lpfp_cfg_t val);
-int32_t lps22hh_lp_bandwidth_get(stmdev_ctx_t *ctx, lps22hh_lpfp_cfg_t *val);
+int32_t lps22hh_lp_bandwidth_set(stmdev_ctx_t *ctx,
+ lps22hh_lpfp_cfg_t val);
+int32_t lps22hh_lp_bandwidth_get(stmdev_ctx_t *ctx,
+ lps22hh_lpfp_cfg_t *val);
-typedef enum {
+typedef enum
+{
LPS22HH_I2C_ENABLE = 0,
LPS22HH_I2C_DISABLE = 1,
} lps22hh_i2c_disable_t;
@@ -512,7 +547,8 @@ int32_t lps22hh_i2c_interface_set(stmdev_ctx_t *ctx,
int32_t lps22hh_i2c_interface_get(stmdev_ctx_t *ctx,
lps22hh_i2c_disable_t *val);
-typedef enum {
+typedef enum
+{
LPS22HH_I3C_ENABLE = 0x00,
LPS22HH_I3C_ENABLE_INT_PIN_ENABLE = 0x10,
LPS22HH_I3C_DISABLE = 0x11,
@@ -522,61 +558,76 @@ int32_t lps22hh_i3c_interface_set(stmdev_ctx_t *ctx,
int32_t lps22hh_i3c_interface_get(stmdev_ctx_t *ctx,
lps22hh_i3c_disable_t *val);
-typedef enum {
+typedef enum
+{
LPS22HH_PULL_UP_DISCONNECT = 0,
LPS22HH_PULL_UP_CONNECT = 1,
} lps22hh_pu_en_t;
-int32_t lps22hh_sdo_sa0_mode_set(stmdev_ctx_t *ctx, lps22hh_pu_en_t val);
-int32_t lps22hh_sdo_sa0_mode_get(stmdev_ctx_t *ctx, lps22hh_pu_en_t *val);
+int32_t lps22hh_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
+ lps22hh_pu_en_t val);
+int32_t lps22hh_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
+ lps22hh_pu_en_t *val);
int32_t lps22hh_sda_mode_set(stmdev_ctx_t *ctx, lps22hh_pu_en_t val);
int32_t lps22hh_sda_mode_get(stmdev_ctx_t *ctx, lps22hh_pu_en_t *val);
-typedef enum {
+typedef enum
+{
LPS22HH_SPI_4_WIRE = 0,
LPS22HH_SPI_3_WIRE = 1,
} lps22hh_sim_t;
int32_t lps22hh_spi_mode_set(stmdev_ctx_t *ctx, lps22hh_sim_t val);
int32_t lps22hh_spi_mode_get(stmdev_ctx_t *ctx, lps22hh_sim_t *val);
-typedef enum {
+typedef enum
+{
LPS22HH_INT_PULSED = 0,
LPS22HH_INT_LATCHED = 1,
} lps22hh_lir_t;
-int32_t lps22hh_int_notification_set(stmdev_ctx_t *ctx, lps22hh_lir_t val);
-int32_t lps22hh_int_notification_get(stmdev_ctx_t *ctx, lps22hh_lir_t *val);
+int32_t lps22hh_int_notification_set(stmdev_ctx_t *ctx,
+ lps22hh_lir_t val);
+int32_t lps22hh_int_notification_get(stmdev_ctx_t *ctx,
+ lps22hh_lir_t *val);
-typedef enum {
+typedef enum
+{
LPS22HH_PUSH_PULL = 0,
LPS22HH_OPEN_DRAIN = 1,
} lps22hh_pp_od_t;
int32_t lps22hh_pin_mode_set(stmdev_ctx_t *ctx, lps22hh_pp_od_t val);
int32_t lps22hh_pin_mode_get(stmdev_ctx_t *ctx, lps22hh_pp_od_t *val);
-typedef enum {
+typedef enum
+{
LPS22HH_ACTIVE_HIGH = 0,
LPS22HH_ACTIVE_LOW = 1,
} lps22hh_int_h_l_t;
-int32_t lps22hh_pin_polarity_set(stmdev_ctx_t *ctx, lps22hh_int_h_l_t val);
-int32_t lps22hh_pin_polarity_get(stmdev_ctx_t *ctx, lps22hh_int_h_l_t *val);
+int32_t lps22hh_pin_polarity_set(stmdev_ctx_t *ctx,
+ lps22hh_int_h_l_t val);
+int32_t lps22hh_pin_polarity_get(stmdev_ctx_t *ctx,
+ lps22hh_int_h_l_t *val);
int32_t lps22hh_pin_int_route_set(stmdev_ctx_t *ctx,
lps22hh_ctrl_reg3_t *val);
int32_t lps22hh_pin_int_route_get(stmdev_ctx_t *ctx,
lps22hh_ctrl_reg3_t *val);
-typedef enum {
+typedef enum
+{
LPS22HH_NO_THRESHOLD = 0,
LPS22HH_POSITIVE = 1,
LPS22HH_NEGATIVE = 2,
LPS22HH_BOTH = 3,
} lps22hh_pe_t;
-int32_t lps22hh_int_on_threshold_set(stmdev_ctx_t *ctx, lps22hh_pe_t val);
-int32_t lps22hh_int_on_threshold_get(stmdev_ctx_t *ctx, lps22hh_pe_t *val);
+int32_t lps22hh_int_on_threshold_set(stmdev_ctx_t *ctx,
+ lps22hh_pe_t val);
+int32_t lps22hh_int_on_threshold_get(stmdev_ctx_t *ctx,
+ lps22hh_pe_t *val);
int32_t lps22hh_int_treshold_set(stmdev_ctx_t *ctx, uint16_t buff);
int32_t lps22hh_int_treshold_get(stmdev_ctx_t *ctx, uint16_t *buff);
-typedef enum {
+typedef enum
+{
LPS22HH_BYPASS_MODE = 0,
LPS22HH_FIFO_MODE = 1,
LPS22HH_STREAM_MODE = 2,
@@ -585,8 +636,10 @@ typedef enum {
LPS22HH_BYPASS_TO_STREAM_MODE = 6,
LPS22HH_STREAM_TO_FIFO_MODE = 7,
} lps22hh_f_mode_t;
-int32_t lps22hh_fifo_mode_set(stmdev_ctx_t *ctx, lps22hh_f_mode_t val);
-int32_t lps22hh_fifo_mode_get(stmdev_ctx_t *ctx, lps22hh_f_mode_t *val);
+int32_t lps22hh_fifo_mode_set(stmdev_ctx_t *ctx,
+ lps22hh_f_mode_t val);
+int32_t lps22hh_fifo_mode_get(stmdev_ctx_t *ctx,
+ lps22hh_f_mode_t *val);
int32_t lps22hh_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps22hh_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -596,7 +649,8 @@ int32_t lps22hh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps22hh_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lps22hh_fifo_src_get(stmdev_ctx_t *ctx, lps22hh_fifo_status2_t *val);
+int32_t lps22hh_fifo_src_get(stmdev_ctx_t *ctx,
+ lps22hh_fifo_status2_t *val);
int32_t lps22hh_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -607,8 +661,10 @@ int32_t lps22hh_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps22hh_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps22hh_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lps22hh_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lps22hh_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps22hh_fifo_threshold_on_int_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lps22hh_fifo_threshold_on_int_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lps22hh_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps22hh_fifo_full_on_int_get(stmdev_ctx_t *ctx, uint8_t *val);
diff --git a/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.c b/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.c
index f962e1ceb633455c0c9915e4ddfa0c7845b213d7..de9f8b854d62c909efa190aeb50bdb72a6741de9 100644
--- a/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.c
+++ b/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file lps25hb_reg.c
- * @author Sensors Software Solution Team
- * @brief LPS25HB driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lps25hb_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LPS25HB driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lps25hb_reg.h"
@@ -45,11 +45,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps25hb_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lps25hb_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -63,11 +66,14 @@ int32_t lps25hb_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps25hb_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lps25hb_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -85,12 +91,12 @@ int32_t lps25hb_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
float_t lps25hb_from_lsb_to_hpa(uint32_t lsb)
{
- return ( (float_t)lsb / 4096.0f );
+ return ((float_t)lsb / 4096.0f);
}
float_t lps25hb_from_lsb_to_degc(int16_t lsb)
{
- return ( (float_t)lsb / 480.0f ) + 42.5f ;
+ return ((float_t)lsb / 480.0f) + 42.5f ;
}
/**
@@ -115,10 +121,17 @@ float_t lps25hb_from_lsb_to_degc(int16_t lsb)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps25hb_pressure_ref_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps25hb_pressure_ref_set(stmdev_ctx_t *ctx, int32_t val)
{
+ uint8_t buff[3];
int32_t ret;
+
+ buff[2] = (uint8_t)((uint32_t)val / 65536U);
+ buff[1] = (uint8_t)((uint32_t)val - (buff[2] * 65536U)) / 256U;
+ buff[0] = (uint8_t)((uint32_t)val - (buff[2] * 65536U) -
+ (buff[1] * 256U));
ret = lps25hb_read_reg(ctx, LPS25HB_REF_P_XL, buff, 3);
+
return ret;
}
@@ -132,10 +145,16 @@ int32_t lps25hb_pressure_ref_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps25hb_pressure_ref_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps25hb_pressure_ref_get(stmdev_ctx_t *ctx, int32_t *val)
{
+ uint8_t buff[3];
int32_t ret;
+
ret = lps25hb_read_reg(ctx, LPS25HB_REF_P_XL, buff, 3);
+ *val = (int32_t)buff[2];
+ *val = (*val * 256) + (int32_t)buff[1];
+ *val = (*val * 256) + (int32_t)buff[0];
+
return ret;
}
@@ -147,16 +166,20 @@ int32_t lps25hb_pressure_ref_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps25hb_pressure_avg_set(stmdev_ctx_t *ctx, lps25hb_avgp_t val)
+int32_t lps25hb_pressure_avg_set(stmdev_ctx_t *ctx,
+ lps25hb_avgp_t val)
{
lps25hb_res_conf_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_RES_CONF, (uint8_t*)®, 1);
- if(ret == 0){
+ ret = lps25hb_read_reg(ctx, LPS25HB_RES_CONF, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.avgp = (uint8_t)val;
- ret = lps25hb_write_reg(ctx, LPS25HB_RES_CONF, (uint8_t*)®, 1);
+ ret = lps25hb_write_reg(ctx, LPS25HB_RES_CONF, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -168,29 +191,37 @@ int32_t lps25hb_pressure_avg_set(stmdev_ctx_t *ctx, lps25hb_avgp_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps25hb_pressure_avg_get(stmdev_ctx_t *ctx, lps25hb_avgp_t *val)
+int32_t lps25hb_pressure_avg_get(stmdev_ctx_t *ctx,
+ lps25hb_avgp_t *val)
{
lps25hb_res_conf_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_RES_CONF, (uint8_t*)®, 1);
- switch (reg.avgp){
+ ret = lps25hb_read_reg(ctx, LPS25HB_RES_CONF, (uint8_t *)®, 1);
+
+ switch (reg.avgp)
+ {
case LPS25HB_P_AVG_8:
*val = LPS25HB_P_AVG_8;
break;
+
case LPS25HB_P_AVG_16:
*val = LPS25HB_P_AVG_16;
break;
+
case LPS25HB_P_AVG_32:
*val = LPS25HB_P_AVG_32;
break;
+
case LPS25HB_P_AVG_64:
*val = LPS25HB_P_AVG_64;
break;
+
default:
*val = LPS25HB_P_AVG_8;
break;
}
+
return ret;
}
@@ -202,16 +233,20 @@ int32_t lps25hb_pressure_avg_get(stmdev_ctx_t *ctx, lps25hb_avgp_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps25hb_temperature_avg_set(stmdev_ctx_t *ctx, lps25hb_avgt_t val)
+int32_t lps25hb_temperature_avg_set(stmdev_ctx_t *ctx,
+ lps25hb_avgt_t val)
{
lps25hb_res_conf_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_RES_CONF, (uint8_t*)®, 1);
- if(ret == 0){
+ ret = lps25hb_read_reg(ctx, LPS25HB_RES_CONF, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.avgt = (uint8_t)val;
- ret = lps25hb_write_reg(ctx, LPS25HB_RES_CONF, (uint8_t*)®, 1);
+ ret = lps25hb_write_reg(ctx, LPS25HB_RES_CONF, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -223,29 +258,37 @@ int32_t lps25hb_temperature_avg_set(stmdev_ctx_t *ctx, lps25hb_avgt_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps25hb_temperature_avg_get(stmdev_ctx_t *ctx, lps25hb_avgt_t *val)
+int32_t lps25hb_temperature_avg_get(stmdev_ctx_t *ctx,
+ lps25hb_avgt_t *val)
{
lps25hb_res_conf_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_RES_CONF, (uint8_t*)®, 1);
- switch (reg.avgt){
+ ret = lps25hb_read_reg(ctx, LPS25HB_RES_CONF, (uint8_t *)®, 1);
+
+ switch (reg.avgt)
+ {
case LPS25HB_T_AVG_8:
*val = LPS25HB_T_AVG_8;
break;
+
case LPS25HB_T_AVG_16:
*val = LPS25HB_T_AVG_16;
break;
+
case LPS25HB_T_AVG_32:
*val = LPS25HB_T_AVG_32;
break;
+
case LPS25HB_T_AVG_64:
*val = LPS25HB_T_AVG_64;
break;
+
default:
*val = LPS25HB_T_AVG_8;
break;
}
+
return ret;
}
@@ -262,11 +305,14 @@ int32_t lps25hb_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val)
lps25hb_ctrl_reg1_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t*)®, 1);
- if(ret == 0){
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.reset_az = val;
- ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t*)®, 1);
+ ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -283,7 +329,7 @@ int32_t lps25hb_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val)
lps25hb_ctrl_reg1_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t*)®, 1);
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t *)®, 1);
*val = reg.reset_az;
return ret;
@@ -302,11 +348,14 @@ int32_t lps25hb_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
lps25hb_ctrl_reg1_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t*)®, 1);
- if(ret == 0){
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.bdu = val;
- ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t*)®, 1);
+ ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -323,7 +372,7 @@ int32_t lps25hb_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
lps25hb_ctrl_reg1_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t*)®, 1);
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t *)®, 1);
*val = reg.bdu;
return ret;
@@ -342,11 +391,14 @@ int32_t lps25hb_data_rate_set(stmdev_ctx_t *ctx, lps25hb_odr_t val)
lps25hb_ctrl_reg1_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t*)®, 1);
- if(ret == 0){
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.odr = (uint8_t)val;
- ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t*)®, 1);
+ ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -363,30 +415,39 @@ int32_t lps25hb_data_rate_get(stmdev_ctx_t *ctx, lps25hb_odr_t *val)
lps25hb_ctrl_reg1_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t*)®, 1);
- switch (reg.odr){
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t *)®, 1);
+
+ switch (reg.odr)
+ {
case LPS25HB_POWER_DOWN:
*val = LPS25HB_POWER_DOWN;
break;
+
case LPS25HB_ODR_1Hz:
*val = LPS25HB_ODR_1Hz;
break;
+
case LPS25HB_ODR_7Hz:
*val = LPS25HB_ODR_7Hz;
break;
+
case LPS25HB_ODR_12Hz5:
*val = LPS25HB_ODR_12Hz5;
break;
+
case LPS25HB_ODR_25Hz:
*val = LPS25HB_ODR_25Hz;
break;
+
case LPS25HB_ONE_SHOT:
*val = LPS25HB_ONE_SHOT;
break;
+
default:
*val = LPS25HB_POWER_DOWN;
break;
}
+
return ret;
}
@@ -403,11 +464,14 @@ int32_t lps25hb_one_shoot_trigger_set(stmdev_ctx_t *ctx, uint8_t val)
lps25hb_ctrl_reg2_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t*)®, 1);
- if(ret == 0){
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.one_shot = val;
- ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t*)®, 1);
+ ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -424,7 +488,7 @@ int32_t lps25hb_one_shoot_trigger_get(stmdev_ctx_t *ctx, uint8_t *val)
lps25hb_ctrl_reg2_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t*)®, 1);
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1);
*val = reg.one_shot;
return ret;
@@ -443,11 +507,14 @@ int32_t lps25hb_autozero_set(stmdev_ctx_t *ctx, uint8_t val)
lps25hb_ctrl_reg2_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t*)®, 1);
- if(ret == 0){
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.autozero = val;
- ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t*)®, 1);
+ ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -464,7 +531,7 @@ int32_t lps25hb_autozero_get(stmdev_ctx_t *ctx, uint8_t *val)
lps25hb_ctrl_reg2_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t*)®, 1);
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1);
*val = reg.autozero;
return ret;
@@ -479,16 +546,20 @@ int32_t lps25hb_autozero_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps25hb_fifo_mean_decimator_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lps25hb_fifo_mean_decimator_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lps25hb_ctrl_reg2_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t*)®, 1);
- if(ret == 0){
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.fifo_mean_dec = val;
- ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t*)®, 1);
+ ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -501,12 +572,13 @@ int32_t lps25hb_fifo_mean_decimator_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps25hb_fifo_mean_decimator_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lps25hb_fifo_mean_decimator_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lps25hb_ctrl_reg2_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t*)®, 1);
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1);
*val = reg.fifo_mean_dec;
return ret;
@@ -525,7 +597,7 @@ int32_t lps25hb_press_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
lps25hb_status_reg_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_STATUS_REG, (uint8_t*)®, 1);
+ ret = lps25hb_read_reg(ctx, LPS25HB_STATUS_REG, (uint8_t *)®, 1);
*val = reg.p_da;
return ret;
@@ -544,7 +616,7 @@ int32_t lps25hb_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
lps25hb_status_reg_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_STATUS_REG, (uint8_t*)®, 1);
+ ret = lps25hb_read_reg(ctx, LPS25HB_STATUS_REG, (uint8_t *)®, 1);
*val = reg.t_da;
return ret;
@@ -563,7 +635,7 @@ int32_t lps25hb_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
lps25hb_status_reg_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_STATUS_REG, (uint8_t*)®, 1);
+ ret = lps25hb_read_reg(ctx, LPS25HB_STATUS_REG, (uint8_t *)®, 1);
*val = reg.t_or;
return ret;
@@ -582,7 +654,7 @@ int32_t lps25hb_press_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
lps25hb_status_reg_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_STATUS_REG, (uint8_t*)®, 1);
+ ret = lps25hb_read_reg(ctx, LPS25HB_STATUS_REG, (uint8_t *)®, 1);
*val = reg.p_or;
return ret;
@@ -596,10 +668,17 @@ int32_t lps25hb_press_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps25hb_pressure_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps25hb_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff)
{
+ uint8_t reg[3];
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_PRESS_OUT_XL, buff, 3);
+
+ ret = lps25hb_read_reg(ctx, LPS25HB_PRESS_OUT_XL, reg, 3);
+ *buff = reg[2];
+ *buff = (*buff * 256) + reg[1];
+ *buff = (*buff * 256) + reg[0];
+ *buff *= 256;
+
return ret;
}
@@ -611,10 +690,15 @@ int32_t lps25hb_pressure_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps25hb_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps25hb_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff)
{
+ uint8_t reg[2];
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_TEMP_OUT_L, buff, 2);
+
+ ret = lps25hb_read_reg(ctx, LPS25HB_TEMP_OUT_L, reg, 2);
+ *buff = reg[1];
+ *buff = (*buff * 256) + reg[0];
+
return ret;
}
@@ -627,10 +711,15 @@ int32_t lps25hb_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps25hb_pressure_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps25hb_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val)
{
+ uint8_t buff[2];
int32_t ret;
+
+ buff[1] = (uint8_t)((uint16_t)val / 256U);
+ buff[0] = (uint8_t)((uint16_t)val - (buff[1] * 256U));
ret = lps25hb_read_reg(ctx, LPS25HB_RPDS_L, buff, 2);
+
return ret;
}
@@ -643,10 +732,15 @@ int32_t lps25hb_pressure_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps25hb_pressure_offset_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps25hb_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
+
ret = lps25hb_read_reg(ctx, LPS25HB_RPDS_L, buff, 2);
+ *val = (int16_t)buff[1];
+ *val = (*val * 256) + (int16_t)buff[0];
+
return ret;
}
@@ -657,7 +751,7 @@ int32_t lps25hb_pressure_offset_get(stmdev_ctx_t *ctx, uint8_t *buff)
/**
* @defgroup LPS25HB_common
- * @brief This section group common usefull functions
+ * @brief This section group common useful functions
* @{
*
*/
@@ -673,7 +767,9 @@ int32_t lps25hb_pressure_offset_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lps25hb_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lps25hb_read_reg(ctx, LPS25HB_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -690,11 +786,14 @@ int32_t lps25hb_reset_set(stmdev_ctx_t *ctx, uint8_t val)
lps25hb_ctrl_reg2_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t*)®, 1);
- if(ret == 0){
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.swreset = val;
- ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t*)®, 1);
+ ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -711,7 +810,7 @@ int32_t lps25hb_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
lps25hb_ctrl_reg2_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t*)®, 1);
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1);
*val = reg.swreset;
return ret;
@@ -730,11 +829,14 @@ int32_t lps25hb_boot_set(stmdev_ctx_t *ctx, uint8_t val)
lps25hb_ctrl_reg2_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t*)®, 1);
- if(ret == 0){
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.boot = val;
- ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t*)®, 1);
+ ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -751,7 +853,7 @@ int32_t lps25hb_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
lps25hb_ctrl_reg2_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t*)®, 1);
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1);
*val = reg.boot;
return ret;
@@ -765,10 +867,13 @@ int32_t lps25hb_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps25hb_status_get(stmdev_ctx_t *ctx, lps25hb_status_reg_t *val)
+int32_t lps25hb_status_get(stmdev_ctx_t *ctx,
+ lps25hb_status_reg_t *val)
{
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_STATUS_REG, (uint8_t*) val, 1);
+
+ ret = lps25hb_read_reg(ctx, LPS25HB_STATUS_REG, (uint8_t *) val, 1);
+
return ret;
}
@@ -797,11 +902,14 @@ int32_t lps25hb_int_generation_set(stmdev_ctx_t *ctx, uint8_t val)
lps25hb_ctrl_reg1_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t*)®, 1);
- if(ret == 0){
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.diff_en = val;
- ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t*)®, 1);
+ ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -818,7 +926,7 @@ int32_t lps25hb_int_generation_get(stmdev_ctx_t *ctx, uint8_t *val)
lps25hb_ctrl_reg1_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t*)®, 1);
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t *)®, 1);
*val = reg.diff_en;
return ret;
@@ -832,16 +940,20 @@ int32_t lps25hb_int_generation_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps25hb_int_pin_mode_set(stmdev_ctx_t *ctx, lps25hb_int_s_t val)
+int32_t lps25hb_int_pin_mode_set(stmdev_ctx_t *ctx,
+ lps25hb_int_s_t val)
{
lps25hb_ctrl_reg3_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG3, (uint8_t*)®, 1);
- if(ret == 0){
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG3, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.int_s = (uint8_t)val;
- ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG3, (uint8_t*)®, 1);
+ ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG3, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -853,29 +965,37 @@ int32_t lps25hb_int_pin_mode_set(stmdev_ctx_t *ctx, lps25hb_int_s_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps25hb_int_pin_mode_get(stmdev_ctx_t *ctx, lps25hb_int_s_t *val)
+int32_t lps25hb_int_pin_mode_get(stmdev_ctx_t *ctx,
+ lps25hb_int_s_t *val)
{
lps25hb_ctrl_reg3_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG3, (uint8_t*)®, 1);
- switch (reg.int_s){
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG3, (uint8_t *)®, 1);
+
+ switch (reg.int_s)
+ {
case LPS25HB_DRDY_OR_FIFO_FLAGS:
*val = LPS25HB_DRDY_OR_FIFO_FLAGS;
break;
+
case LPS25HB_HIGH_PRES_INT:
*val = LPS25HB_HIGH_PRES_INT;
break;
+
case LPS25HB_LOW_PRES_INT:
*val = LPS25HB_LOW_PRES_INT;
break;
+
case LPS25HB_EVERY_PRES_INT:
*val = LPS25HB_EVERY_PRES_INT;
break;
+
default:
*val = LPS25HB_DRDY_OR_FIFO_FLAGS;
break;
}
+
return ret;
}
@@ -892,11 +1012,14 @@ int32_t lps25hb_pin_mode_set(stmdev_ctx_t *ctx, lps25hb_pp_od_t val)
lps25hb_ctrl_reg3_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG3, (uint8_t*)®, 1);
- if(ret == 0){
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG3, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.pp_od = (uint8_t)val;
- ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG3, (uint8_t*)®, 1);
+ ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG3, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -913,18 +1036,23 @@ int32_t lps25hb_pin_mode_get(stmdev_ctx_t *ctx, lps25hb_pp_od_t *val)
lps25hb_ctrl_reg3_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG3, (uint8_t*)®, 1);
- switch (reg.pp_od){
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG3, (uint8_t *)®, 1);
+
+ switch (reg.pp_od)
+ {
case LPS25HB_PUSH_PULL:
*val = LPS25HB_PUSH_PULL;
break;
+
case LPS25HB_OPEN_DRAIN:
*val = LPS25HB_OPEN_DRAIN;
break;
+
default:
*val = LPS25HB_PUSH_PULL;
break;
}
+
return ret;
}
@@ -936,16 +1064,20 @@ int32_t lps25hb_pin_mode_get(stmdev_ctx_t *ctx, lps25hb_pp_od_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps25hb_int_polarity_set(stmdev_ctx_t *ctx, lps25hb_int_h_l_t val)
+int32_t lps25hb_int_polarity_set(stmdev_ctx_t *ctx,
+ lps25hb_int_h_l_t val)
{
lps25hb_ctrl_reg3_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG3, (uint8_t*)®, 1);
- if(ret == 0){
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG3, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.int_h_l = (uint8_t)val;
- ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG3, (uint8_t*)®, 1);
+ ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG3, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -957,23 +1089,29 @@ int32_t lps25hb_int_polarity_set(stmdev_ctx_t *ctx, lps25hb_int_h_l_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps25hb_int_polarity_get(stmdev_ctx_t *ctx, lps25hb_int_h_l_t *val)
+int32_t lps25hb_int_polarity_get(stmdev_ctx_t *ctx,
+ lps25hb_int_h_l_t *val)
{
lps25hb_ctrl_reg3_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG3, (uint8_t*)®, 1);
- switch (reg.int_h_l){
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG3, (uint8_t *)®, 1);
+
+ switch (reg.int_h_l)
+ {
case LPS25HB_ACTIVE_HIGH:
*val = LPS25HB_ACTIVE_HIGH;
break;
+
case LPS25HB_ACTIVE_LOW:
*val = LPS25HB_ACTIVE_LOW;
break;
+
default:
*val = LPS25HB_ACTIVE_HIGH;
break;
}
+
return ret;
}
@@ -990,11 +1128,14 @@ int32_t lps25hb_drdy_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
lps25hb_ctrl_reg4_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG4, (uint8_t*)®, 1);
- if(ret == 0){
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG4, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.drdy = val;
- ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG4, (uint8_t*)®, 1);
+ ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG4, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1011,7 +1152,7 @@ int32_t lps25hb_drdy_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
lps25hb_ctrl_reg4_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG4, (uint8_t*)®, 1);
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG4, (uint8_t *)®, 1);
*val = reg.drdy;
return ret;
@@ -1030,11 +1171,14 @@ int32_t lps25hb_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
lps25hb_ctrl_reg4_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG4, (uint8_t*)®, 1);
- if(ret == 0){
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG4, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.f_ovr = val;
- ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG4, (uint8_t*)®, 1);
+ ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG4, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1051,7 +1195,7 @@ int32_t lps25hb_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
lps25hb_ctrl_reg4_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG4, (uint8_t*)®, 1);
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG4, (uint8_t *)®, 1);
*val = reg.f_ovr;
return ret;
@@ -1065,16 +1209,20 @@ int32_t lps25hb_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps25hb_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lps25hb_fifo_threshold_on_int_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lps25hb_ctrl_reg4_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG4, (uint8_t*)®, 1);
- if(ret == 0){
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG4, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.f_fth = val;
- ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG4, (uint8_t*)®, 1);
+ ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG4, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1086,12 +1234,13 @@ int32_t lps25hb_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps25hb_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lps25hb_fifo_threshold_on_int_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lps25hb_ctrl_reg4_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG4, (uint8_t*)®, 1);
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG4, (uint8_t *)®, 1);
*val = reg.f_fth;
return ret;
@@ -1110,11 +1259,14 @@ int32_t lps25hb_fifo_empty_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
lps25hb_ctrl_reg4_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG4, (uint8_t*)®, 1);
- if(ret == 0){
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG4, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.f_empty = val;
- ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG4, (uint8_t*)®, 1);
+ ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG4, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1131,7 +1283,7 @@ int32_t lps25hb_fifo_empty_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
lps25hb_ctrl_reg4_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG4, (uint8_t*)®, 1);
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG4, (uint8_t *)®, 1);
*val = reg.f_empty;
return ret;
@@ -1151,11 +1303,14 @@ int32_t lps25hb_sign_of_int_threshold_set(stmdev_ctx_t *ctx,
lps25hb_interrupt_cfg_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_INTERRUPT_CFG, (uint8_t*)®, 1);
- if(ret == 0){
+ ret = lps25hb_read_reg(ctx, LPS25HB_INTERRUPT_CFG, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.pe = (uint8_t)val;
- ret = lps25hb_write_reg(ctx, LPS25HB_INTERRUPT_CFG, (uint8_t*)®, 1);
+ ret = lps25hb_write_reg(ctx, LPS25HB_INTERRUPT_CFG, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1173,24 +1328,31 @@ int32_t lps25hb_sign_of_int_threshold_get(stmdev_ctx_t *ctx,
lps25hb_interrupt_cfg_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_INTERRUPT_CFG, (uint8_t*)®, 1);
- switch (reg.pe){
+ ret = lps25hb_read_reg(ctx, LPS25HB_INTERRUPT_CFG, (uint8_t *)®, 1);
+
+ switch (reg.pe)
+ {
case LPS25HB_NO_THRESHOLD:
*val = LPS25HB_NO_THRESHOLD;
break;
+
case LPS25HB_POSITIVE:
*val = LPS25HB_POSITIVE;
break;
+
case LPS25HB_NEGATIVE:
*val = LPS25HB_NEGATIVE;
break;
+
case LPS25HB_BOTH:
*val = LPS25HB_BOTH;
break;
+
default:
*val = LPS25HB_NO_THRESHOLD;
break;
}
+
return ret;
}
@@ -1208,11 +1370,14 @@ int32_t lps25hb_int_notification_mode_set(stmdev_ctx_t *ctx,
lps25hb_interrupt_cfg_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_INTERRUPT_CFG, (uint8_t*)®, 1);
- if(ret == 0){
+ ret = lps25hb_read_reg(ctx, LPS25HB_INTERRUPT_CFG, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.lir = (uint8_t)val;
- ret = lps25hb_write_reg(ctx, LPS25HB_INTERRUPT_CFG, (uint8_t*)®, 1);
+ ret = lps25hb_write_reg(ctx, LPS25HB_INTERRUPT_CFG, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1230,18 +1395,23 @@ int32_t lps25hb_int_notification_mode_get(stmdev_ctx_t *ctx,
lps25hb_interrupt_cfg_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_INTERRUPT_CFG, (uint8_t*)®, 1);
- switch (reg.lir){
+ ret = lps25hb_read_reg(ctx, LPS25HB_INTERRUPT_CFG, (uint8_t *)®, 1);
+
+ switch (reg.lir)
+ {
case LPS25HB_INT_PULSED:
*val = LPS25HB_INT_PULSED;
break;
+
case LPS25HB_INT_LATCHED:
*val = LPS25HB_INT_LATCHED;
break;
+
default:
*val = LPS25HB_INT_PULSED;
break;
}
+
return ret;
}
@@ -1253,10 +1423,13 @@ int32_t lps25hb_int_notification_mode_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps25hb_int_source_get(stmdev_ctx_t *ctx, lps25hb_int_source_t *val)
+int32_t lps25hb_int_source_get(stmdev_ctx_t *ctx,
+ lps25hb_int_source_t *val)
{
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_INT_SOURCE, (uint8_t*) val, 1);
+
+ ret = lps25hb_read_reg(ctx, LPS25HB_INT_SOURCE, (uint8_t *) val, 1);
+
return ret;
}
@@ -1273,7 +1446,7 @@ int32_t lps25hb_int_on_press_high_get(stmdev_ctx_t *ctx, uint8_t *val)
lps25hb_int_source_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_INT_SOURCE, (uint8_t*)®, 1);
+ ret = lps25hb_read_reg(ctx, LPS25HB_INT_SOURCE, (uint8_t *)®, 1);
*val = reg.ph;
return ret;
@@ -1292,7 +1465,7 @@ int32_t lps25hb_int_on_press_low_get(stmdev_ctx_t *ctx, uint8_t *val)
lps25hb_int_source_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_INT_SOURCE, (uint8_t*)®, 1);
+ ret = lps25hb_read_reg(ctx, LPS25HB_INT_SOURCE, (uint8_t *)®, 1);
*val = reg.pl;
return ret;
@@ -1311,7 +1484,7 @@ int32_t lps25hb_interrupt_event_get(stmdev_ctx_t *ctx, uint8_t *val)
lps25hb_int_source_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_INT_SOURCE, (uint8_t*)®, 1);
+ ret = lps25hb_read_reg(ctx, LPS25HB_INT_SOURCE, (uint8_t *)®, 1);
*val = reg.ia;
return ret;
@@ -1325,10 +1498,15 @@ int32_t lps25hb_interrupt_event_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps25hb_int_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps25hb_int_threshold_set(stmdev_ctx_t *ctx, uint16_t val)
{
+ uint8_t buff[2];
int32_t ret;
+
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
ret = lps25hb_read_reg(ctx, LPS25HB_THS_P_L, buff, 2);
+
return ret;
}
@@ -1340,10 +1518,15 @@ int32_t lps25hb_int_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps25hb_int_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps25hb_int_threshold_get(stmdev_ctx_t *ctx, uint16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
+
ret = lps25hb_read_reg(ctx, LPS25HB_THS_P_L, buff, 2);
+ *val = buff[1];
+ *val = (*val * 256) + buff[0];
+
return ret;
}
@@ -1367,16 +1550,20 @@ int32_t lps25hb_int_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps25hb_stop_on_fifo_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lps25hb_stop_on_fifo_threshold_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lps25hb_ctrl_reg2_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t*)®, 1);
- if(ret == 0){
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.stop_on_fth = val;
- ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t*)®, 1);
+ ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1388,12 +1575,13 @@ int32_t lps25hb_stop_on_fifo_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps25hb_stop_on_fifo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lps25hb_stop_on_fifo_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lps25hb_ctrl_reg2_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t*)®, 1);
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1);
*val = reg.stop_on_fth;
return ret;
@@ -1412,11 +1600,14 @@ int32_t lps25hb_fifo_set(stmdev_ctx_t *ctx, uint8_t val)
lps25hb_ctrl_reg2_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t*)®, 1);
- if(ret == 0){
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.fifo_en = val;
- ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t*)®, 1);
+ ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1433,7 +1624,7 @@ int32_t lps25hb_fifo_get(stmdev_ctx_t *ctx, uint8_t *val)
lps25hb_ctrl_reg2_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t*)®, 1);
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1);
*val = reg.fifo_en;
return ret;
@@ -1452,11 +1643,14 @@ int32_t lps25hb_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
lps25hb_fifo_ctrl_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_FIFO_CTRL, (uint8_t*)®, 1);
- if(ret == 0){
+ ret = lps25hb_read_reg(ctx, LPS25HB_FIFO_CTRL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.wtm_point = val;
- ret = lps25hb_write_reg(ctx, LPS25HB_FIFO_CTRL, (uint8_t*)®, 1);
+ ret = lps25hb_write_reg(ctx, LPS25HB_FIFO_CTRL, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1473,7 +1667,7 @@ int32_t lps25hb_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
lps25hb_fifo_ctrl_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_FIFO_CTRL, (uint8_t*)®, 1);
+ ret = lps25hb_read_reg(ctx, LPS25HB_FIFO_CTRL, (uint8_t *)®, 1);
*val = reg.wtm_point;
return ret;
@@ -1492,11 +1686,14 @@ int32_t lps25hb_fifo_mode_set(stmdev_ctx_t *ctx, lps25hb_f_mode_t val)
lps25hb_fifo_ctrl_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_FIFO_CTRL, (uint8_t*)®, 1);
- if(ret == 0){
+ ret = lps25hb_read_reg(ctx, LPS25HB_FIFO_CTRL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.f_mode = (uint8_t)val;
- ret = lps25hb_write_reg(ctx, LPS25HB_FIFO_CTRL, (uint8_t*)®, 1);
+ ret = lps25hb_write_reg(ctx, LPS25HB_FIFO_CTRL, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1508,38 +1705,49 @@ int32_t lps25hb_fifo_mode_set(stmdev_ctx_t *ctx, lps25hb_f_mode_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps25hb_fifo_mode_get(stmdev_ctx_t *ctx, lps25hb_f_mode_t *val)
+int32_t lps25hb_fifo_mode_get(stmdev_ctx_t *ctx,
+ lps25hb_f_mode_t *val)
{
lps25hb_fifo_ctrl_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_FIFO_CTRL, (uint8_t*)®, 1);
- switch (reg.f_mode){
+ ret = lps25hb_read_reg(ctx, LPS25HB_FIFO_CTRL, (uint8_t *)®, 1);
+
+ switch (reg.f_mode)
+ {
case LPS25HB_BYPASS_MODE:
*val = LPS25HB_BYPASS_MODE;
break;
+
case LPS25HB_FIFO_MODE:
*val = LPS25HB_FIFO_MODE;
break;
+
case LPS25HB_STREAM_MODE:
*val = LPS25HB_STREAM_MODE;
break;
+
case LPS25HB_Stream_to_FIFO_mode:
*val = LPS25HB_Stream_to_FIFO_mode;
break;
+
case LPS25HB_BYPASS_TO_STREAM_MODE:
*val = LPS25HB_BYPASS_TO_STREAM_MODE;
break;
+
case LPS25HB_MEAN_MODE:
*val = LPS25HB_MEAN_MODE;
break;
+
case LPS25HB_BYPASS_TO_FIFO_MODE:
*val = LPS25HB_BYPASS_TO_FIFO_MODE;
break;
+
default:
*val = LPS25HB_BYPASS_MODE;
break;
}
+
return ret;
}
@@ -1555,7 +1763,9 @@ int32_t lps25hb_fifo_status_get(stmdev_ctx_t *ctx,
lps25hb_fifo_status_t *val)
{
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_FIFO_STATUS, (uint8_t*) val, 1);
+
+ ret = lps25hb_read_reg(ctx, LPS25HB_FIFO_STATUS, (uint8_t *) val, 1);
+
return ret;
}
@@ -1572,7 +1782,7 @@ int32_t lps25hb_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val)
lps25hb_fifo_status_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_FIFO_STATUS, (uint8_t*)®, 1);
+ ret = lps25hb_read_reg(ctx, LPS25HB_FIFO_STATUS, (uint8_t *)®, 1);
*val = reg.fss;
return ret;
@@ -1591,7 +1801,7 @@ int32_t lps25hb_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lps25hb_fifo_status_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_FIFO_STATUS, (uint8_t*)®, 1);
+ ret = lps25hb_read_reg(ctx, LPS25HB_FIFO_STATUS, (uint8_t *)®, 1);
*val = reg.empty_fifo;
return ret;
@@ -1610,7 +1820,7 @@ int32_t lps25hb_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lps25hb_fifo_status_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_FIFO_STATUS, (uint8_t*)®, 1);
+ ret = lps25hb_read_reg(ctx, LPS25HB_FIFO_STATUS, (uint8_t *)®, 1);
*val = reg.ovr;
return ret;
@@ -1629,7 +1839,7 @@ int32_t lps25hb_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lps25hb_fifo_status_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_FIFO_STATUS, (uint8_t*)®, 1);
+ ret = lps25hb_read_reg(ctx, LPS25HB_FIFO_STATUS, (uint8_t *)®, 1);
*val = reg.fth_fifo;
return ret;
@@ -1661,11 +1871,14 @@ int32_t lps25hb_spi_mode_set(stmdev_ctx_t *ctx, lps25hb_sim_t val)
lps25hb_ctrl_reg1_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t*)®, 1);
- if(ret == 0){
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.sim = (uint8_t)val;
- ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t*)®, 1);
+ ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1682,18 +1895,23 @@ int32_t lps25hb_spi_mode_get(stmdev_ctx_t *ctx, lps25hb_sim_t *val)
lps25hb_ctrl_reg1_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t*)®, 1);
- switch (reg.sim){
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t *)®, 1);
+
+ switch (reg.sim)
+ {
case LPS25HB_SPI_4_WIRE:
*val = LPS25HB_SPI_4_WIRE;
break;
+
case LPS25HB_SPI_3_WIRE:
*val = LPS25HB_SPI_3_WIRE;
break;
+
default:
*val = LPS25HB_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -1705,16 +1923,20 @@ int32_t lps25hb_spi_mode_get(stmdev_ctx_t *ctx, lps25hb_sim_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps25hb_i2c_interface_set(stmdev_ctx_t *ctx, lps25hb_i2c_dis_t val)
+int32_t lps25hb_i2c_interface_set(stmdev_ctx_t *ctx,
+ lps25hb_i2c_dis_t val)
{
lps25hb_ctrl_reg2_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t*)®, 1);
- if(ret == 0){
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.i2c_dis = (uint8_t)val;
- ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t*)®, 1);
+ ret = lps25hb_write_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1726,23 +1948,29 @@ int32_t lps25hb_i2c_interface_set(stmdev_ctx_t *ctx, lps25hb_i2c_dis_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps25hb_i2c_interface_get(stmdev_ctx_t *ctx, lps25hb_i2c_dis_t *val)
+int32_t lps25hb_i2c_interface_get(stmdev_ctx_t *ctx,
+ lps25hb_i2c_dis_t *val)
{
lps25hb_ctrl_reg2_t reg;
int32_t ret;
- ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t*)®, 1);
- switch (reg.i2c_dis){
+ ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1);
+
+ switch (reg.i2c_dis)
+ {
case LPS25HB_I2C_ENABLE:
*val = LPS25HB_I2C_ENABLE;
break;
+
case LPS25HB_I2C_DISABLE:
*val = LPS25HB_I2C_DISABLE;
break;
+
default:
*val = LPS25HB_I2C_ENABLE;
break;
}
+
return ret;
}
diff --git a/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.h b/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.h
index 8fc12400061c681cbce89d0595d514467a84129f..2cd69cd010fe0d1e81dc40eccce37070fcab6d05 100644
--- a/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.h
+++ b/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file lps25hb_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lps25hb_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lps25hb_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lps25hb_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LPS25HB_REGS_H
#define LPS25HB_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup LPS25HB
@@ -35,6 +36,38 @@
*
*/
+/** @defgroup Endianness definitions
+ * @{
+ *
+ */
+
+#ifndef DRV_BYTE_ORDER
+#ifndef __BYTE_ORDER__
+
+#define DRV_LITTLE_ENDIAN 1234
+#define DRV_BIG_ENDIAN 4321
+
+/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
+ * by uncommenting the define which fits your platform endianness
+ */
+//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
+#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
+
+#else /* defined __BYTE_ORDER__ */
+
+#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
+#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
+#define DRV_BYTE_ORDER __BYTE_ORDER__
+
+#endif /* __BYTE_ORDER__*/
+#endif /* DRV_BYTE_ORDER */
+
+/**
+ * @}
+ *
+ */
+
+
/** @defgroup STMicroelectronics sensors common types
* @{
*
@@ -43,7 +76,9 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -52,6 +87,16 @@ typedef struct{
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} bitwise_t;
#define PROPERTY_DISABLE (0U)
@@ -65,10 +110,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -89,15 +135,16 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
- * Unico / Unicleo tools available on STMicroelectronics
- * web site.
+ * You can create a sensor configuration by your own or using
+ * Unico / Unicleo tools available on STMicroelectronics
+ * web site.
*
* @{
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -136,23 +183,41 @@ typedef struct {
#define LPS25HB_REF_P_H 0x0AU
#define LPS25HB_WHO_AM_I 0x0FU
#define LPS25HB_RES_CONF 0x10U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t avgp : 2;
uint8_t avgt : 2;
uint8_t not_used_01 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 4;
+ uint8_t avgt : 2;
+ uint8_t avgp : 2;
+#endif /* DRV_BYTE_ORDER */
} lps25hb_res_conf_t;
#define LPS25HB_CTRL_REG1 0x20U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t reset_az : 1;
uint8_t bdu : 1;
uint8_t diff_en : 1;
uint8_t odr : 4; /* pd + odr -> odr */
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr : 4; /* pd + odr -> odr */
+ uint8_t diff_en : 1;
+ uint8_t bdu : 1;
+ uint8_t reset_az : 1;
+ uint8_t sim : 1;
+#endif /* DRV_BYTE_ORDER */
} lps25hb_ctrl_reg1_t;
#define LPS25HB_CTRL_REG2 0x21U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t one_shot : 1;
uint8_t autozero : 1;
uint8_t swreset : 1;
@@ -161,48 +226,100 @@ typedef struct {
uint8_t stop_on_fth : 1;
uint8_t fifo_en : 1;
uint8_t boot : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t boot : 1;
+ uint8_t fifo_en : 1;
+ uint8_t stop_on_fth : 1;
+ uint8_t fifo_mean_dec : 1;
+ uint8_t i2c_dis : 1;
+ uint8_t swreset : 1;
+ uint8_t autozero : 1;
+ uint8_t one_shot : 1;
+#endif /* DRV_BYTE_ORDER */
} lps25hb_ctrl_reg2_t;
#define LPS25HB_CTRL_REG3 0x22U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int_s : 2;
uint8_t not_used_01 : 4;
uint8_t pp_od : 1;
uint8_t int_h_l : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int_h_l : 1;
+ uint8_t pp_od : 1;
+ uint8_t not_used_01 : 4;
+ uint8_t int_s : 2;
+#endif /* DRV_BYTE_ORDER */
} lps25hb_ctrl_reg3_t;
#define LPS25HB_CTRL_REG4 0x23U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t drdy : 1;
uint8_t f_ovr : 1;
uint8_t f_fth : 1;
uint8_t f_empty : 1;
uint8_t not_used_01 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 4;
+ uint8_t f_empty : 1;
+ uint8_t f_fth : 1;
+ uint8_t f_ovr : 1;
+ uint8_t drdy : 1;
+#endif /* DRV_BYTE_ORDER */
} lps25hb_ctrl_reg4_t;
#define LPS25HB_INTERRUPT_CFG 0x24U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t pe : 2; /* pl_e + ph_e -> pe */
uint8_t lir : 1;
uint8_t not_used_01 : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 5;
+ uint8_t lir : 1;
+ uint8_t pe : 2; /* pl_e + ph_e -> pe */
+#endif /* DRV_BYTE_ORDER */
} lps25hb_interrupt_cfg_t;
#define LPS25HB_INT_SOURCE 0x25U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ph : 1;
uint8_t pl : 1;
uint8_t ia : 1;
uint8_t not_used_01 : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 5;
+ uint8_t ia : 1;
+ uint8_t pl : 1;
+ uint8_t ph : 1;
+#endif /* DRV_BYTE_ORDER */
} lps25hb_int_source_t;
#define LPS25HB_STATUS_REG 0x27U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t t_da : 1;
uint8_t p_da : 1;
uint8_t not_used_01 : 2;
uint8_t t_or : 1;
uint8_t p_or : 1;
uint8_t not_used_02 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 2;
+ uint8_t p_or : 1;
+ uint8_t t_or : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t p_da : 1;
+ uint8_t t_da : 1;
+#endif /* DRV_BYTE_ORDER */
} lps25hb_status_reg_t;
#define LPS25HB_PRESS_OUT_XL 0x28U
@@ -211,17 +328,31 @@ typedef struct {
#define LPS25HB_TEMP_OUT_L 0x2BU
#define LPS25HB_TEMP_OUT_H 0x2CU
#define LPS25HB_FIFO_CTRL 0x2EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wtm_point : 5;
uint8_t f_mode : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t f_mode : 3;
+ uint8_t wtm_point : 5;
+#endif /* DRV_BYTE_ORDER */
} lps25hb_fifo_ctrl_t;
#define LPS25HB_FIFO_STATUS 0x2FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fss : 5;
uint8_t empty_fifo : 1;
uint8_t ovr : 1;
uint8_t fth_fifo : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fth_fifo : 1;
+ uint8_t ovr : 1;
+ uint8_t empty_fifo : 1;
+ uint8_t fss : 5;
+#endif /* DRV_BYTE_ORDER */
} lps25hb_fifo_status_t;
#define LPS25HB_THS_P_L 0x30U
@@ -231,9 +362,9 @@ typedef struct {
/**
* @defgroup LPS25HB_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -241,7 +372,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
lps25hb_res_conf_t res_conf;
lps25hb_ctrl_reg1_t ctrl_reg1;
lps25hb_ctrl_reg2_t ctrl_reg2;
@@ -261,42 +393,53 @@ typedef union{
*
*/
-int32_t lps25hb_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lps25hb_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t lps25hb_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lps25hb_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-extern float_t lps25hb_from_lsb_to_hpa(uint32_t lsb);
-extern float_t lps25hb_from_lsb_to_degc(int16_t lsb);
+float_t lps25hb_from_lsb_to_hpa(uint32_t lsb);
+
+float_t lps25hb_from_lsb_to_degc(int16_t lsb);
-int32_t lps25hb_pressure_ref_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lps25hb_pressure_ref_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lps25hb_pressure_ref_set(stmdev_ctx_t *ctx, int32_t val);
+int32_t lps25hb_pressure_ref_get(stmdev_ctx_t *ctx, int32_t *val);
-typedef enum {
+typedef enum
+{
LPS25HB_P_AVG_8 = 0,
LPS25HB_P_AVG_16 = 1,
LPS25HB_P_AVG_32 = 2,
LPS25HB_P_AVG_64 = 3,
} lps25hb_avgp_t;
-int32_t lps25hb_pressure_avg_set(stmdev_ctx_t *ctx, lps25hb_avgp_t val);
-int32_t lps25hb_pressure_avg_get(stmdev_ctx_t *ctx, lps25hb_avgp_t *val);
+int32_t lps25hb_pressure_avg_set(stmdev_ctx_t *ctx,
+ lps25hb_avgp_t val);
+int32_t lps25hb_pressure_avg_get(stmdev_ctx_t *ctx,
+ lps25hb_avgp_t *val);
-typedef enum {
+typedef enum
+{
LPS25HB_T_AVG_8 = 0,
LPS25HB_T_AVG_16 = 1,
LPS25HB_T_AVG_32 = 2,
LPS25HB_T_AVG_64 = 3,
} lps25hb_avgt_t;
-int32_t lps25hb_temperature_avg_set(stmdev_ctx_t *ctx, lps25hb_avgt_t val);
-int32_t lps25hb_temperature_avg_get(stmdev_ctx_t *ctx, lps25hb_avgt_t *val);
+int32_t lps25hb_temperature_avg_set(stmdev_ctx_t *ctx,
+ lps25hb_avgt_t val);
+int32_t lps25hb_temperature_avg_get(stmdev_ctx_t *ctx,
+ lps25hb_avgt_t *val);
int32_t lps25hb_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps25hb_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps25hb_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lps25hb_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps25hb_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LPS25HB_POWER_DOWN = 0,
LPS25HB_ODR_1Hz = 9,
LPS25HB_ODR_7Hz = 10,
@@ -308,13 +451,16 @@ int32_t lps25hb_data_rate_set(stmdev_ctx_t *ctx, lps25hb_odr_t val);
int32_t lps25hb_data_rate_get(stmdev_ctx_t *ctx, lps25hb_odr_t *val);
int32_t lps25hb_one_shoot_trigger_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lps25hb_one_shoot_trigger_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps25hb_one_shoot_trigger_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lps25hb_autozero_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps25hb_autozero_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lps25hb_fifo_mean_decimator_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lps25hb_fifo_mean_decimator_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps25hb_fifo_mean_decimator_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lps25hb_fifo_mean_decimator_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lps25hb_press_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -324,12 +470,12 @@ int32_t lps25hb_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps25hb_press_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lps25hb_pressure_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lps25hb_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff);
-int32_t lps25hb_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lps25hb_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff);
-int32_t lps25hb_pressure_offset_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lps25hb_pressure_offset_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lps25hb_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val);
+int32_t lps25hb_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val);
int32_t lps25hb_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
@@ -339,33 +485,41 @@ int32_t lps25hb_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps25hb_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps25hb_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lps25hb_status_get(stmdev_ctx_t *ctx, lps25hb_status_reg_t *val);
+int32_t lps25hb_status_get(stmdev_ctx_t *ctx,
+ lps25hb_status_reg_t *val);
int32_t lps25hb_int_generation_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps25hb_int_generation_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LPS25HB_DRDY_OR_FIFO_FLAGS = 0,
LPS25HB_HIGH_PRES_INT = 1,
LPS25HB_LOW_PRES_INT = 2,
LPS25HB_EVERY_PRES_INT = 3,
} lps25hb_int_s_t;
-int32_t lps25hb_int_pin_mode_set(stmdev_ctx_t *ctx, lps25hb_int_s_t val);
-int32_t lps25hb_int_pin_mode_get(stmdev_ctx_t *ctx, lps25hb_int_s_t *val);
+int32_t lps25hb_int_pin_mode_set(stmdev_ctx_t *ctx,
+ lps25hb_int_s_t val);
+int32_t lps25hb_int_pin_mode_get(stmdev_ctx_t *ctx,
+ lps25hb_int_s_t *val);
-typedef enum {
+typedef enum
+{
LPS25HB_PUSH_PULL = 0,
LPS25HB_OPEN_DRAIN = 1,
} lps25hb_pp_od_t;
int32_t lps25hb_pin_mode_set(stmdev_ctx_t *ctx, lps25hb_pp_od_t val);
int32_t lps25hb_pin_mode_get(stmdev_ctx_t *ctx, lps25hb_pp_od_t *val);
-typedef enum {
+typedef enum
+{
LPS25HB_ACTIVE_HIGH = 0,
LPS25HB_ACTIVE_LOW = 1,
} lps25hb_int_h_l_t;
-int32_t lps25hb_int_polarity_set(stmdev_ctx_t *ctx, lps25hb_int_h_l_t val);
-int32_t lps25hb_int_polarity_get(stmdev_ctx_t *ctx, lps25hb_int_h_l_t *val);
+int32_t lps25hb_int_polarity_set(stmdev_ctx_t *ctx,
+ lps25hb_int_h_l_t val);
+int32_t lps25hb_int_polarity_get(stmdev_ctx_t *ctx,
+ lps25hb_int_h_l_t *val);
int32_t lps25hb_drdy_on_int_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps25hb_drdy_on_int_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -373,13 +527,17 @@ int32_t lps25hb_drdy_on_int_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps25hb_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps25hb_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lps25hb_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lps25hb_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps25hb_fifo_threshold_on_int_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lps25hb_fifo_threshold_on_int_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lps25hb_fifo_empty_on_int_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lps25hb_fifo_empty_on_int_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps25hb_fifo_empty_on_int_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LPS25HB_NO_THRESHOLD = 0,
LPS25HB_POSITIVE = 1,
LPS25HB_NEGATIVE = 2,
@@ -390,7 +548,8 @@ int32_t lps25hb_sign_of_int_threshold_set(stmdev_ctx_t *ctx,
int32_t lps25hb_sign_of_int_threshold_get(stmdev_ctx_t *ctx,
lps25hb_pe_t *val);
-typedef enum {
+typedef enum
+{
LPS25HB_INT_PULSED = 0,
LPS25HB_INT_LATCHED = 1,
} lps25hb_lir_t;
@@ -399,19 +558,23 @@ int32_t lps25hb_int_notification_mode_set(stmdev_ctx_t *ctx,
int32_t lps25hb_int_notification_mode_get(stmdev_ctx_t *ctx,
lps25hb_lir_t *val);
-int32_t lps25hb_int_source_get(stmdev_ctx_t *ctx, lps25hb_int_source_t *val);
+int32_t lps25hb_int_source_get(stmdev_ctx_t *ctx,
+ lps25hb_int_source_t *val);
-int32_t lps25hb_int_on_press_high_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps25hb_int_on_press_high_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lps25hb_int_on_press_low_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps25hb_interrupt_event_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lps25hb_int_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lps25hb_int_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lps25hb_int_threshold_set(stmdev_ctx_t *ctx, uint16_t val);
+int32_t lps25hb_int_threshold_get(stmdev_ctx_t *ctx, uint16_t *val);
-int32_t lps25hb_stop_on_fifo_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lps25hb_stop_on_fifo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps25hb_stop_on_fifo_threshold_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lps25hb_stop_on_fifo_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lps25hb_fifo_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps25hb_fifo_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -419,7 +582,8 @@ int32_t lps25hb_fifo_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps25hb_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps25hb_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LPS25HB_BYPASS_MODE = 0,
LPS25HB_FIFO_MODE = 1,
LPS25HB_STREAM_MODE = 2,
@@ -428,8 +592,10 @@ typedef enum {
LPS25HB_MEAN_MODE = 6,
LPS25HB_BYPASS_TO_FIFO_MODE = 7,
} lps25hb_f_mode_t;
-int32_t lps25hb_fifo_mode_set(stmdev_ctx_t *ctx, lps25hb_f_mode_t val);
-int32_t lps25hb_fifo_mode_get(stmdev_ctx_t *ctx, lps25hb_f_mode_t *val);
+int32_t lps25hb_fifo_mode_set(stmdev_ctx_t *ctx,
+ lps25hb_f_mode_t val);
+int32_t lps25hb_fifo_mode_get(stmdev_ctx_t *ctx,
+ lps25hb_f_mode_t *val);
int32_t lps25hb_fifo_status_get(stmdev_ctx_t *ctx,
lps25hb_fifo_status_t *val);
@@ -442,19 +608,23 @@ int32_t lps25hb_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps25hb_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LPS25HB_SPI_4_WIRE = 0,
LPS25HB_SPI_3_WIRE = 1,
} lps25hb_sim_t;
int32_t lps25hb_spi_mode_set(stmdev_ctx_t *ctx, lps25hb_sim_t val);
int32_t lps25hb_spi_mode_get(stmdev_ctx_t *ctx, lps25hb_sim_t *val);
-typedef enum {
+typedef enum
+{
LPS25HB_I2C_ENABLE = 0,
LPS25HB_I2C_DISABLE = 1,
} lps25hb_i2c_dis_t;
-int32_t lps25hb_i2c_interface_set(stmdev_ctx_t *ctx, lps25hb_i2c_dis_t val);
-int32_t lps25hb_i2c_interface_get(stmdev_ctx_t *ctx, lps25hb_i2c_dis_t *val);
+int32_t lps25hb_i2c_interface_set(stmdev_ctx_t *ctx,
+ lps25hb_i2c_dis_t val);
+int32_t lps25hb_i2c_interface_get(stmdev_ctx_t *ctx,
+ lps25hb_i2c_dis_t *val);
/**
*@}
diff --git a/sensor/stmemsc/lps27hhtw_STdC/driver/lps27hhtw_reg.c b/sensor/stmemsc/lps27hhtw_STdC/driver/lps27hhtw_reg.c
new file mode 100644
index 0000000000000000000000000000000000000000..d3ee18bc4da489970b1b3ed3c797387317db31bc
--- /dev/null
+++ b/sensor/stmemsc/lps27hhtw_STdC/driver/lps27hhtw_reg.c
@@ -0,0 +1,2116 @@
+/**
+ ******************************************************************************
+ * @file lps27hhtw_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LPS27HHTW driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+#include "lps27hhtw_reg.h"
+
+/**
+ * @defgroup LPS27HHTW
+ * @brief This file provides a set of functions needed to drive the
+ * lps27hhtw enhanced inertial module.
+ * @{
+ *
+ */
+
+/**
+ * @defgroup LPS27HHTW_Interfaces_Functions
+ * @brief This section provide a set of functions used to read and
+ * write a generic register of the device.
+ * MANDATORY: return 0 -> no Error.
+ * @{
+ *
+ */
+
+/**
+ * @brief Read generic device register
+ *
+ * @param ctx read / write interface definitions(ptr)
+ * @param reg register to read
+ * @param data pointer to buffer that store the data read(ptr)
+ * @param len number of consecutive register to read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
+{
+ int32_t ret;
+
+ ret = ctx->read_reg(ctx->handle, reg, data, len);
+
+ return ret;
+}
+
+/**
+ * @brief Write generic device register
+ *
+ * @param ctx read / write interface definitions(ptr)
+ * @param reg register to write
+ * @param data pointer to data to write in register reg(ptr)
+ * @param len number of consecutive register to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
+{
+ int32_t ret;
+
+ ret = ctx->write_reg(ctx->handle, reg, data, len);
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LPS27HHTW_Sensitivity
+ * @brief These functions convert raw-data into engineering units.
+ * @{
+ *
+ */
+float_t lps27hhtw_from_lsb_to_hpa(int32_t lsb)
+{
+ return ((float_t) lsb / 1048576.0f);
+}
+
+float_t lps27hhtw_from_lsb_to_celsius(int16_t lsb)
+{
+ return ((float_t) lsb / 100.0f);
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LPS27HHTW_Data_Generation
+ * @brief This section groups all the functions concerning
+ * data generation.
+ * @{
+ *
+ */
+
+/**
+ * @brief Reset Autozero function.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of reset_az in reg INTERRUPT_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lps27hhtw_interrupt_cfg_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
+ (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.reset_az = val;
+ ret = lps27hhtw_write_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
+ (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Reset Autozero function.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of reset_az in reg INTERRUPT_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lps27hhtw_interrupt_cfg_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
+ (uint8_t *) ®, 1);
+ *val = reg.reset_az;
+
+ return ret;
+}
+
+/**
+ * @brief Enable Autozero function.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of autozero in reg INTERRUPT_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_autozero_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lps27hhtw_interrupt_cfg_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
+ (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.autozero = val;
+ ret = lps27hhtw_write_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
+ (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable Autozero function.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of autozero in reg INTERRUPT_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_autozero_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lps27hhtw_interrupt_cfg_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
+ (uint8_t *) ®, 1);
+ *val = reg.autozero;
+
+ return ret;
+}
+
+/**
+ * @brief Reset AutoRifP function.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of reset_arp in reg INTERRUPT_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_pressure_snap_rst_set(stmdev_ctx_t *ctx,
+ uint8_t val)
+{
+ lps27hhtw_interrupt_cfg_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
+ (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.reset_arp = val;
+ ret = lps27hhtw_write_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
+ (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Reset AutoRifP function.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of reset_arp in reg INTERRUPT_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_pressure_snap_rst_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lps27hhtw_interrupt_cfg_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
+ (uint8_t *) ®, 1);
+ *val = reg.reset_arp;
+
+ return ret;
+}
+
+/**
+ * @brief Enable AutoRefP function.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of autorefp in reg INTERRUPT_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lps27hhtw_interrupt_cfg_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
+ (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.autorefp = val;
+ ret = lps27hhtw_write_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
+ (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable AutoRefP function.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of autorefp in reg INTERRUPT_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lps27hhtw_interrupt_cfg_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
+ (uint8_t *) ®, 1);
+ *val = reg.autorefp;
+
+ return ret;
+}
+
+/**
+ * @brief Block Data Update.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of bdu in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val)
+{
+ lps27hhtw_ctrl_reg1_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG1, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.bdu = val;
+ ret = lps27hhtw_write_reg(ctx, LPS27HHTW_CTRL_REG1, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Block Data Update.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of bdu in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lps27hhtw_ctrl_reg1_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG1, (uint8_t *) ®, 1);
+ *val = reg.bdu;
+
+ return ret;
+}
+
+/**
+ * @brief Output data rate selection.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of odr in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_data_rate_set(stmdev_ctx_t *ctx,
+ lps27hhtw_odr_t val)
+{
+ lps27hhtw_ctrl_reg1_t ctrl_reg1;
+ lps27hhtw_ctrl_reg2_t ctrl_reg2;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+ }
+
+ if (ret == 0)
+ {
+ ctrl_reg1.odr = (uint8_t)val & 0x07U;
+ ret = lps27hhtw_write_reg(ctx, LPS27HHTW_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+ }
+
+ if (ret == 0)
+ {
+ ctrl_reg2.low_noise_en = ((uint8_t)val & 0x10U) >> 4;
+ ctrl_reg2.one_shot = ((uint8_t)val & 0x08U) >> 3;
+ ret = lps27hhtw_write_reg(ctx, LPS27HHTW_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Output data rate selection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of odr in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_data_rate_get(stmdev_ctx_t *ctx,
+ lps27hhtw_odr_t *val)
+{
+ lps27hhtw_ctrl_reg1_t ctrl_reg1;
+ lps27hhtw_ctrl_reg2_t ctrl_reg2;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
+ switch (((ctrl_reg2.low_noise_en << 4) + (ctrl_reg2.one_shot << 3) +
+ ctrl_reg1.odr))
+ {
+ case LPS27HHTW_POWER_DOWN:
+ *val = LPS27HHTW_POWER_DOWN;
+ break;
+
+ case LPS27HHTW_ONE_SHOOT:
+ *val = LPS27HHTW_ONE_SHOOT;
+ break;
+
+ case LPS27HHTW_1_Hz:
+ *val = LPS27HHTW_1_Hz;
+ break;
+
+ case LPS27HHTW_10_Hz:
+ *val = LPS27HHTW_10_Hz;
+ break;
+
+ case LPS27HHTW_25_Hz:
+ *val = LPS27HHTW_25_Hz;
+ break;
+
+ case LPS27HHTW_50_Hz:
+ *val = LPS27HHTW_50_Hz;
+ break;
+
+ case LPS27HHTW_75_Hz:
+ *val = LPS27HHTW_75_Hz;
+ break;
+
+ case LPS27HHTW_1_Hz_LOW_NOISE:
+ *val = LPS27HHTW_1_Hz_LOW_NOISE;
+ break;
+
+ case LPS27HHTW_10_Hz_LOW_NOISE:
+ *val = LPS27HHTW_10_Hz_LOW_NOISE;
+ break;
+
+ case LPS27HHTW_25_Hz_LOW_NOISE:
+ *val = LPS27HHTW_25_Hz_LOW_NOISE;
+ break;
+
+ case LPS27HHTW_50_Hz_LOW_NOISE:
+ *val = LPS27HHTW_50_Hz_LOW_NOISE;
+ break;
+
+ case LPS27HHTW_75_Hz_LOW_NOISE:
+ *val = LPS27HHTW_75_Hz_LOW_NOISE;
+ break;
+
+ case LPS27HHTW_100_Hz:
+ *val = LPS27HHTW_100_Hz;
+ break;
+
+ case LPS27HHTW_200_Hz:
+ *val = LPS27HHTW_200_Hz;
+ break;
+
+ default:
+ *val = LPS27HHTW_POWER_DOWN;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief The Reference pressure value is a 16-bit data
+ * expressed as 2’s complement. The value is used
+ * when AUTOZERO or AUTORIFP function is enabled.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_pressure_ref_set(stmdev_ctx_t *ctx, int16_t val)
+{
+ uint8_t buff[2];
+ int32_t ret;
+
+ buff[1] = (uint8_t)((uint16_t)val / 256U);
+ buff[0] = (uint8_t)((uint16_t)val - (buff[1] * 256U));
+ ret = lps27hhtw_write_reg(ctx, LPS27HHTW_REF_P_L, buff, 2);
+
+ return ret;
+}
+
+/**
+ * @brief The Reference pressure value is a 16-bit
+ * data expressed as 2’s complement.
+ * The value is used when AUTOZERO or AUTORIFP
+ * function is enabled.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_pressure_ref_get(stmdev_ctx_t *ctx, int16_t *val)
+{
+ uint8_t buff[2];
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_REF_P_L, buff, 2);
+ *val = (int16_t)buff[1];
+ *val = (*val * 256) + (int16_t)buff[0];
+
+ return ret;
+}
+
+/**
+ * @brief The pressure offset value is 16-bit data
+ * that can be used to implement one-point
+ * calibration (OPC) after soldering.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val)
+{
+ uint8_t buff[2];
+ int32_t ret;
+
+ buff[1] = (uint8_t)((uint16_t)val / 256U);
+ buff[0] = (uint8_t)((uint16_t)val - (buff[1] * 256U));
+ ret = lps27hhtw_write_reg(ctx, LPS27HHTW_RPDS_L, buff, 2);
+
+ return ret;
+}
+
+/**
+ * @brief The pressure offset value is 16-bit
+ * data that can be used to implement
+ * one-point calibration (OPC) after
+ * soldering.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val)
+{
+ uint8_t buff[2];
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_RPDS_L, buff, 2);
+ *val = (int16_t)buff[1];
+ *val = (*val * 256) + (int16_t)buff[0];
+
+ return ret;
+}
+
+/**
+ * @brief Read all the interrupt/status flag of the device.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val registers STATUS,FIFO_STATUS2,INT_SOURCE
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_all_sources_get(stmdev_ctx_t *ctx,
+ lps27hhtw_all_sources_t *val)
+{
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INT_SOURCE,
+ (uint8_t *) & (val->int_source), 1);
+
+ if (ret == 0)
+ {
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_STATUS2,
+ (uint8_t *) & (val->fifo_status2), 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_STATUS,
+ (uint8_t *) & (val->status), 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief The STATUS_REG register is read by the primary interface.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val structure of registers from STATUS to STATUS_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_status_reg_get(stmdev_ctx_t *ctx,
+ lps27hhtw_status_t *val)
+{
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_STATUS, (uint8_t *) val, 1);
+
+ return ret;
+}
+
+/**
+ * @brief Pressure new data available.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of p_da in reg STATUS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_press_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lps27hhtw_status_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_STATUS, (uint8_t *) ®, 1);
+ *val = reg.p_da;
+
+ return ret;
+}
+
+/**
+ * @brief Temperature data available.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of t_da in reg STATUS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lps27hhtw_status_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_STATUS, (uint8_t *) ®, 1);
+ *val = reg.t_da;
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LPS27HHTW_Data_Output
+ * @brief This section groups all the data output functions.
+ * @{
+ *
+ */
+
+/**
+ * @brief Pressure output value.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff)
+{
+ uint8_t reg[3];
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_PRESS_OUT_XL, reg, 3);
+ *buff = reg[2];
+ *buff = (*buff * 256) + reg[1];
+ *buff = (*buff * 256) + reg[0];
+ *buff *= 256;
+
+ return ret;
+}
+
+/**
+ * @brief Temperature output value.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_temperature_raw_get(stmdev_ctx_t *ctx,
+ int16_t *buff)
+{
+ uint8_t reg[2];
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_TEMP_OUT_L, reg, 2);
+ *buff = reg[1];
+ *buff = (*buff * 256) + reg[0];
+
+ return ret;
+}
+
+/**
+ * @brief Pressure output from FIFO value.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_fifo_pressure_raw_get(stmdev_ctx_t *ctx,
+ uint32_t *buff)
+{
+ uint8_t reg[3];
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_DATA_OUT_PRESS_XL, reg,
+ 3);
+ *buff = reg[2];
+ *buff = (*buff * 256) + reg[1];
+ *buff = (*buff * 256) + reg[0];
+ *buff *= 256;
+
+ return ret;
+}
+
+/**
+ * @brief Temperature output from FIFO value.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_fifo_temperature_raw_get(stmdev_ctx_t *ctx,
+ int16_t *buff)
+{
+ uint8_t reg[2];
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_DATA_OUT_TEMP_L, reg,
+ 2);
+ *buff = reg[1];
+ *buff = (*buff * 256) + reg[0];
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LPS27HHTW_Common
+ * @brief This section groups common useful functions.
+ * @{
+ *
+ */
+
+/**
+ * @brief DeviceWhoamI[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
+{
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_WHO_AM_I, buff, 1);
+
+ return ret;
+}
+
+/**
+ * @brief Software reset. Restore the default values
+ * in user registers.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of swreset in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_reset_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lps27hhtw_ctrl_reg2_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.swreset = val;
+ ret = lps27hhtw_write_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Software reset. Restore the default values
+ * in user registers.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of swreset in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lps27hhtw_ctrl_reg2_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1);
+ *val = reg.swreset;
+
+ return ret;
+}
+
+/**
+ * @brief Register address automatically
+ * incremented during a multiple byte access
+ * with a serial interface.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of if_add_inc in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lps27hhtw_ctrl_reg2_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.if_add_inc = val;
+ ret = lps27hhtw_write_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Register address automatically
+ * incremented during a multiple byte
+ * access with a serial interface.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of if_add_inc in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lps27hhtw_ctrl_reg2_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1);
+ *val = reg.if_add_inc;
+
+ return ret;
+}
+
+/**
+ * @brief Reboot memory content. Reload the calibration
+ * parameters.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of boot in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_boot_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lps27hhtw_ctrl_reg2_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.boot = val;
+ ret = lps27hhtw_write_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Reboot memory content. Reload the calibration
+ * parameters.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of boot in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lps27hhtw_ctrl_reg2_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1);
+ *val = reg.boot;
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LPS27HHTW_Filters
+ * @brief This section group all the functions concerning the
+ * filters configuration.
+ * @{
+ *
+ */
+
+/**
+ * @brief Low-pass bandwidth selection.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of lpfp_cfg in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_lp_bandwidth_set(stmdev_ctx_t *ctx,
+ lps27hhtw_lpfp_cfg_t val)
+{
+ lps27hhtw_ctrl_reg1_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG1, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.lpfp_cfg = (uint8_t)val;
+ ret = lps27hhtw_write_reg(ctx, LPS27HHTW_CTRL_REG1, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Low-pass bandwidth selection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of lpfp_cfg in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_lp_bandwidth_get(stmdev_ctx_t *ctx,
+ lps27hhtw_lpfp_cfg_t *val)
+{
+ lps27hhtw_ctrl_reg1_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG1, (uint8_t *) ®, 1);
+
+ switch (reg.lpfp_cfg)
+ {
+ case LPS27HHTW_LPF_ODR_DIV_2:
+ *val = LPS27HHTW_LPF_ODR_DIV_2;
+ break;
+
+ case LPS27HHTW_LPF_ODR_DIV_9:
+ *val = LPS27HHTW_LPF_ODR_DIV_9;
+ break;
+
+ case LPS27HHTW_LPF_ODR_DIV_20:
+ *val = LPS27HHTW_LPF_ODR_DIV_20;
+ break;
+
+ default:
+ *val = LPS27HHTW_LPF_ODR_DIV_2;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LPS27HHTW_Serial_Interface
+ * @brief This section groups all the functions concerning serial
+ * interface management
+ * @{
+ *
+ */
+
+/**
+ * @brief Enable/Disable I2C interface.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of i2c_disable in reg IF_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_i2c_interface_set(stmdev_ctx_t *ctx,
+ lps27hhtw_i2c_disable_t val)
+{
+ lps27hhtw_if_ctrl_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_IF_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.i2c_disable = (uint8_t)val;
+ ret = lps27hhtw_write_reg(ctx, LPS27HHTW_IF_CTRL, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable/Disable I2C interface.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of i2c_disable in reg IF_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_i2c_interface_get(stmdev_ctx_t *ctx,
+ lps27hhtw_i2c_disable_t *val)
+{
+ lps27hhtw_if_ctrl_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_IF_CTRL, (uint8_t *) ®, 1);
+
+ switch (reg.i2c_disable)
+ {
+ case LPS27HHTW_I2C_ENABLE:
+ *val = LPS27HHTW_I2C_ENABLE;
+ break;
+
+ case LPS27HHTW_I2C_DISABLE:
+ *val = LPS27HHTW_I2C_DISABLE;
+ break;
+
+ default:
+ *val = LPS27HHTW_I2C_ENABLE;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief I3C Enable/Disable communication protocol.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of int_en_i3c in reg IF_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_i3c_interface_set(stmdev_ctx_t *ctx,
+ lps27hhtw_i3c_disable_t val)
+{
+ lps27hhtw_if_ctrl_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_IF_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.i3c_disable = ((uint8_t)val & 0x01u);
+ reg.int_en_i3c = ((uint8_t)val & 0x10U) >> 4;
+ ret = lps27hhtw_write_reg(ctx, LPS27HHTW_IF_CTRL, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief I3C Enable/Disable communication protocol.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of int_en_i3c in reg IF_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_i3c_interface_get(stmdev_ctx_t *ctx,
+ lps27hhtw_i3c_disable_t *val)
+{
+ lps27hhtw_if_ctrl_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_IF_CTRL, (uint8_t *) ®, 1);
+
+ switch ((reg.int_en_i3c << 4) + reg.int_en_i3c)
+ {
+ case LPS27HHTW_I3C_ENABLE:
+ *val = LPS27HHTW_I3C_ENABLE;
+ break;
+
+ case LPS27HHTW_I3C_ENABLE_INT_PIN_ENABLE:
+ *val = LPS27HHTW_I3C_ENABLE_INT_PIN_ENABLE;
+ break;
+
+ case LPS27HHTW_I3C_DISABLE:
+ *val = LPS27HHTW_I3C_DISABLE;
+ break;
+
+ default:
+ *val = LPS27HHTW_I3C_ENABLE;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable/Disable pull-up on SDO pin.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of sdo_pu_en in reg IF_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
+ lps27hhtw_pu_en_t val)
+{
+ lps27hhtw_if_ctrl_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_IF_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.sdo_pu_en = (uint8_t)val;
+ ret = lps27hhtw_write_reg(ctx, LPS27HHTW_IF_CTRL, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable/Disable pull-up on SDO pin.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of sdo_pu_en in reg IF_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
+ lps27hhtw_pu_en_t *val)
+{
+ lps27hhtw_if_ctrl_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_IF_CTRL, (uint8_t *) ®, 1);
+
+ switch (reg.sdo_pu_en)
+ {
+ case LPS27HHTW_PULL_UP_DISCONNECT:
+ *val = LPS27HHTW_PULL_UP_DISCONNECT;
+ break;
+
+ case LPS27HHTW_PULL_UP_CONNECT:
+ *val = LPS27HHTW_PULL_UP_CONNECT;
+ break;
+
+ default:
+ *val = LPS27HHTW_PULL_UP_DISCONNECT;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of sda_pu_en in reg IF_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_sda_mode_set(stmdev_ctx_t *ctx,
+ lps27hhtw_pu_en_t val)
+{
+ lps27hhtw_if_ctrl_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_IF_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.sda_pu_en = (uint8_t)val;
+ ret = lps27hhtw_write_reg(ctx, LPS27HHTW_IF_CTRL, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of sda_pu_en in reg IF_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_sda_mode_get(stmdev_ctx_t *ctx,
+ lps27hhtw_pu_en_t *val)
+{
+ lps27hhtw_if_ctrl_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_IF_CTRL, (uint8_t *) ®, 1);
+
+ switch (reg.sda_pu_en)
+ {
+ case LPS27HHTW_PULL_UP_DISCONNECT:
+ *val = LPS27HHTW_PULL_UP_DISCONNECT;
+ break;
+
+ case LPS27HHTW_PULL_UP_CONNECT:
+ *val = LPS27HHTW_PULL_UP_CONNECT;
+ break;
+
+ default:
+ *val = LPS27HHTW_PULL_UP_DISCONNECT;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief SPI Serial Interface Mode selection.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of sim in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_spi_mode_set(stmdev_ctx_t *ctx, lps27hhtw_sim_t val)
+{
+ lps27hhtw_ctrl_reg1_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG1, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.sim = (uint8_t)val;
+ ret = lps27hhtw_write_reg(ctx, LPS27HHTW_CTRL_REG1, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief SPI Serial Interface Mode selection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of sim in reg CTRL_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_spi_mode_get(stmdev_ctx_t *ctx,
+ lps27hhtw_sim_t *val)
+{
+ lps27hhtw_ctrl_reg1_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG1, (uint8_t *) ®, 1);
+
+ switch (reg.sim)
+ {
+ case LPS27HHTW_SPI_4_WIRE:
+ *val = LPS27HHTW_SPI_4_WIRE;
+ break;
+
+ case LPS27HHTW_SPI_3_WIRE:
+ *val = LPS27HHTW_SPI_3_WIRE;
+ break;
+
+ default:
+ *val = LPS27HHTW_SPI_4_WIRE;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LPS27HHTW_Interrupt_Pins
+ * @brief This section groups all the functions that manage
+ * interrupt pins.
+ * @{
+ *
+ */
+
+/**
+ * @brief Latch interrupt request to the INT_SOURCE (24h) register.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of lir in reg INTERRUPT_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_int_notification_set(stmdev_ctx_t *ctx,
+ lps27hhtw_lir_t val)
+{
+ lps27hhtw_interrupt_cfg_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
+ (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.lir = (uint8_t)val;
+ ret = lps27hhtw_write_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
+ (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Latch interrupt request to the INT_SOURCE (24h) register.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of lir in reg INTERRUPT_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_int_notification_get(stmdev_ctx_t *ctx,
+ lps27hhtw_lir_t *val)
+{
+ lps27hhtw_interrupt_cfg_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
+ (uint8_t *) ®, 1);
+
+ switch (reg.lir)
+ {
+ case LPS27HHTW_INT_PULSED:
+ *val = LPS27HHTW_INT_PULSED;
+ break;
+
+ case LPS27HHTW_INT_LATCHED:
+ *val = LPS27HHTW_INT_LATCHED;
+ break;
+
+ default:
+ *val = LPS27HHTW_INT_PULSED;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Push-pull/open drain selection on interrupt pads.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of pp_od in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_pin_mode_set(stmdev_ctx_t *ctx,
+ lps27hhtw_pp_od_t val)
+{
+ lps27hhtw_ctrl_reg2_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.pp_od = (uint8_t)val;
+ ret = lps27hhtw_write_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Push-pull/open drain selection on interrupt pads.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of pp_od in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_pin_mode_get(stmdev_ctx_t *ctx,
+ lps27hhtw_pp_od_t *val)
+{
+ lps27hhtw_ctrl_reg2_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1);
+
+ switch (reg.pp_od)
+ {
+ case LPS27HHTW_PUSH_PULL:
+ *val = LPS27HHTW_PUSH_PULL;
+ break;
+
+ case LPS27HHTW_OPEN_DRAIN:
+ *val = LPS27HHTW_OPEN_DRAIN;
+ break;
+
+ default:
+ *val = LPS27HHTW_PUSH_PULL;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Interrupt active-high/low.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of int_h_l in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_pin_polarity_set(stmdev_ctx_t *ctx,
+ lps27hhtw_int_h_l_t val)
+{
+ lps27hhtw_ctrl_reg2_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.int_h_l = (uint8_t)val;
+ ret = lps27hhtw_write_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Interrupt active-high/low.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of int_h_l in reg CTRL_REG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_pin_polarity_get(stmdev_ctx_t *ctx,
+ lps27hhtw_int_h_l_t *val)
+{
+ lps27hhtw_ctrl_reg2_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1);
+
+ switch (reg.int_h_l)
+ {
+ case LPS27HHTW_ACTIVE_HIGH:
+ *val = LPS27HHTW_ACTIVE_HIGH;
+ break;
+
+ case LPS27HHTW_ACTIVE_LOW:
+ *val = LPS27HHTW_ACTIVE_LOW;
+ break;
+
+ default:
+ *val = LPS27HHTW_ACTIVE_HIGH;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Select the signal that need to route on int pad.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val registers CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_pin_int_route_set(stmdev_ctx_t *ctx,
+ lps27hhtw_ctrl_reg3_t *val)
+{
+ int32_t ret;
+
+ ret = lps27hhtw_write_reg(ctx, LPS27HHTW_CTRL_REG3, (uint8_t *) val, 1);
+
+ return ret;
+}
+
+/**
+ * @brief Select the signal that need to route on int pad.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val registers CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_pin_int_route_get(stmdev_ctx_t *ctx,
+ lps27hhtw_ctrl_reg3_t *val)
+{
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG3, (uint8_t *) val, 1);
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LPS27HHTW_Interrupt_on_Threshold
+ * @brief This section groups all the functions that manage the
+ * interrupt on threshold event generation.
+ * @{
+ *
+ */
+
+/**
+ * @brief Enable interrupt generation on pressure low/high event.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of pe in reg INTERRUPT_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_int_on_threshold_set(stmdev_ctx_t *ctx,
+ lps27hhtw_pe_t val)
+{
+ lps27hhtw_interrupt_cfg_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
+ (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.pe = (uint8_t)val;
+
+ if (val == LPS27HHTW_NO_THRESHOLD)
+ {
+ reg.diff_en = PROPERTY_DISABLE;
+ }
+
+ else
+ {
+ reg.diff_en = PROPERTY_ENABLE;
+ }
+
+ ret = lps27hhtw_write_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
+ (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable interrupt generation on pressure low/high event.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of pe in reg INTERRUPT_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_int_on_threshold_get(stmdev_ctx_t *ctx,
+ lps27hhtw_pe_t *val)
+{
+ lps27hhtw_interrupt_cfg_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
+ (uint8_t *) ®, 1);
+
+ switch (reg.pe)
+ {
+ case LPS27HHTW_NO_THRESHOLD:
+ *val = LPS27HHTW_NO_THRESHOLD;
+ break;
+
+ case LPS27HHTW_POSITIVE:
+ *val = LPS27HHTW_POSITIVE;
+ break;
+
+ case LPS27HHTW_NEGATIVE:
+ *val = LPS27HHTW_NEGATIVE;
+ break;
+
+ case LPS27HHTW_BOTH:
+ *val = LPS27HHTW_BOTH;
+ break;
+
+ default:
+ *val = LPS27HHTW_NO_THRESHOLD;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief User-defined threshold value for pressure interrupt event.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_int_treshold_set(stmdev_ctx_t *ctx, uint16_t buff)
+{
+ int32_t ret;
+
+ lps27hhtw_ths_p_l_t ths_p_l;
+ lps27hhtw_ths_p_h_t ths_p_h;
+ ths_p_l.ths = (uint8_t)(buff & 0x00FFU);
+ ths_p_h.ths = (uint8_t)((buff & 0x7F00U) >> 8);
+ ret = lps27hhtw_write_reg(ctx, LPS27HHTW_THS_P_L,
+ (uint8_t *)&ths_p_l, 1);
+
+ if (ret == 0)
+ {
+ ret = lps27hhtw_write_reg(ctx, LPS27HHTW_THS_P_H,
+ (uint8_t *)&ths_p_h, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief User-defined threshold value for pressure interrupt event.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_int_treshold_get(stmdev_ctx_t *ctx, uint16_t *buff)
+{
+ int32_t ret;
+
+ lps27hhtw_ths_p_l_t ths_p_l;
+ lps27hhtw_ths_p_h_t ths_p_h;
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_THS_P_L,
+ (uint8_t *)&ths_p_l, 1);
+
+ if (ret == 0)
+ {
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_THS_P_H,
+ (uint8_t *)&ths_p_h, 1);
+ *buff = (uint16_t)ths_p_h.ths << 8;
+ *buff |= (uint16_t)ths_p_l.ths;
+ }
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LPS27HHTW_Fifo
+ * @brief This section group all the functions concerning the fifo usage.
+ * @{
+ *
+ */
+
+/**
+ * @brief Fifo Mode selection.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of f_mode in reg FIFO_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_fifo_mode_set(stmdev_ctx_t *ctx,
+ lps27hhtw_f_mode_t val)
+{
+ lps27hhtw_fifo_ctrl_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.f_mode = (uint8_t)val;
+ ret = lps27hhtw_write_reg(ctx, LPS27HHTW_FIFO_CTRL, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Fifo Mode selection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of f_mode in reg FIFO_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_fifo_mode_get(stmdev_ctx_t *ctx,
+ lps27hhtw_f_mode_t *val)
+{
+ lps27hhtw_fifo_ctrl_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_CTRL, (uint8_t *) ®, 1);
+
+ switch (reg.f_mode)
+ {
+ case LPS27HHTW_BYPASS_MODE:
+ *val = LPS27HHTW_BYPASS_MODE;
+ break;
+
+ case LPS27HHTW_FIFO_MODE:
+ *val = LPS27HHTW_FIFO_MODE;
+ break;
+
+ case LPS27HHTW_STREAM_MODE:
+ *val = LPS27HHTW_STREAM_MODE;
+ break;
+
+ case LPS27HHTW_DYNAMIC_STREAM_MODE:
+ *val = LPS27HHTW_DYNAMIC_STREAM_MODE;
+ break;
+
+ case LPS27HHTW_BYPASS_TO_FIFO_MODE:
+ *val = LPS27HHTW_BYPASS_TO_FIFO_MODE;
+ break;
+
+ case LPS27HHTW_BYPASS_TO_STREAM_MODE:
+ *val = LPS27HHTW_BYPASS_TO_STREAM_MODE;
+ break;
+
+ case LPS27HHTW_STREAM_TO_FIFO_MODE:
+ *val = LPS27HHTW_STREAM_TO_FIFO_MODE;
+ break;
+
+ default:
+ *val = LPS27HHTW_BYPASS_MODE;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Sensing chain FIFO stop values memorization at
+ * threshold level.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of stop_on_wtm in reg FIFO_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lps27hhtw_fifo_ctrl_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.stop_on_wtm = val;
+ ret = lps27hhtw_write_reg(ctx, LPS27HHTW_FIFO_CTRL, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Sensing chain FIFO stop values memorization at threshold
+ * level.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of stop_on_wtm in reg FIFO_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lps27hhtw_fifo_ctrl_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_CTRL, (uint8_t *) ®, 1);
+ *val = reg.stop_on_wtm;
+
+ return ret;
+}
+
+/**
+ * @brief FIFO watermark level selection.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of wtm in reg FIFO_WTM
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lps27hhtw_fifo_wtm_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_WTM, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
+ reg.wtm = val;
+ ret = lps27hhtw_write_reg(ctx, LPS27HHTW_FIFO_WTM, (uint8_t *) ®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief FIFO watermark level selection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of wtm in reg FIFO_WTM
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lps27hhtw_fifo_wtm_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_WTM, (uint8_t *) ®, 1);
+ *val = reg.wtm;
+
+ return ret;
+}
+
+/**
+ * @brief FIFO stored data level.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_fifo_data_level_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
+{
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_STATUS1, buff, 1);
+
+ return ret;
+}
+
+/**
+ * @brief Read all the FIFO status flag of the device.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val registers FIFO_STATUS2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_fifo_src_get(stmdev_ctx_t *ctx,
+ lps27hhtw_fifo_status2_t *val)
+{
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_STATUS2,
+ (uint8_t *) val, 1);
+
+ return ret;
+}
+
+/**
+ * @brief Smart FIFO full status.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of fifo_full_ia in reg FIFO_STATUS2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lps27hhtw_fifo_status2_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_STATUS2,
+ (uint8_t *) ®, 1);
+ *val = reg.fifo_full_ia;
+
+ return ret;
+}
+
+/**
+ * @brief FIFO overrun status.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of fifo_ovr_ia in reg FIFO_STATUS2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lps27hhtw_fifo_status2_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_STATUS2,
+ (uint8_t *) ®, 1);
+ *val = reg.fifo_ovr_ia;
+
+ return ret;
+}
+
+/**
+ * @brief FIFO watermark status.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of fifo_wtm_ia in reg FIFO_STATUS2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lps27hhtw_fifo_status2_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_STATUS2, (uint8_t *)®, 1);
+ *val = reg.fifo_wtm_ia;
+
+ return ret;
+}
+
+/**
+ * @brief FIFO overrun interrupt on INT_DRDY pin.[set]
+ *
+ * @param stmdev_ctx_t *ctx: read / write interface definitions
+ * @param uint8_t val: change the values of f_ovr in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lps27hhtw_ctrl_reg3_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG3, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.int_f_ovr = val;
+ ret = lps27hhtw_write_reg(ctx, LPS27HHTW_CTRL_REG3, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief FIFO overrun interrupt on INT_DRDY pin.[get]
+ *
+ * @param stmdev_ctx_t *ctx: read / write interface definitions
+ * @param uint8_t: change the values of f_ovr in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lps27hhtw_ctrl_reg3_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG3, (uint8_t *)®, 1);
+ *val = reg.int_f_ovr;
+
+ return ret;
+}
+
+/**
+ * @brief FIFO watermark status on INT_DRDY pin.[set]
+ *
+ * @param stmdev_ctx_t *ctx: read / write interface definitions
+ * @param uint8_t val: change the values of f_fth in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_fifo_threshold_on_int_set(stmdev_ctx_t *ctx,
+ uint8_t val)
+{
+ lps27hhtw_ctrl_reg3_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG3, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.int_f_wtm = val;
+ ret = lps27hhtw_write_reg(ctx, LPS27HHTW_CTRL_REG3, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief FIFO watermark status on INT_DRDY pin.[get]
+ *
+ * @param lps22hb_ctx_t *ctx: read / write interface definitions
+ * @param uint8_t: change the values of f_fth in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_fifo_threshold_on_int_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lps27hhtw_ctrl_reg3_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG3, (uint8_t *)®, 1);
+ *val = reg.int_f_wtm;
+
+ return ret;
+}
+
+/**
+ * @brief FIFO full flag on INT_DRDY pin.[set]
+ *
+ * @param stmdev_ctx_t *ctx: read / write interface definitions
+ * @param uint8_t val: change the values of f_fss5 in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lps27hhtw_ctrl_reg3_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG3, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.int_f_full = val;
+ ret = lps27hhtw_write_reg(ctx, LPS27HHTW_CTRL_REG3, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief FIFO full flag on INT_DRDY pin.[get]
+ *
+ * @param stmdev_ctx_t *ctx: read / write interface definitions
+ * @param uint8_t: change the values of f_fss5 in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lps27hhtw_fifo_full_on_int_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lps27hhtw_ctrl_reg3_t reg;
+ int32_t ret;
+
+ ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG3, (uint8_t *)®, 1);
+ *val = reg.int_f_full;
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @}
+ *
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/sensor/stmemsc/lps27hhtw_STdC/driver/lps27hhtw_reg.h b/sensor/stmemsc/lps27hhtw_STdC/driver/lps27hhtw_reg.h
new file mode 100644
index 0000000000000000000000000000000000000000..0cfab74b6aa01aebfb839c3b534a926c2a23ea40
--- /dev/null
+++ b/sensor/stmemsc/lps27hhtw_STdC/driver/lps27hhtw_reg.h
@@ -0,0 +1,703 @@
+/**
+ ******************************************************************************
+ * @file lps27hhtw_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lps27hhtw_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef LPS27HHTW_DRIVER_H
+#define LPS27HHTW_DRIVER_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include
+#include
+#include
+
+/** @addtogroup LPS27HHTW
+ * @{
+ *
+ */
+
+/** @defgroup Endianness definitions
+ * @{
+ *
+ */
+
+#ifndef DRV_BYTE_ORDER
+#ifndef __BYTE_ORDER__
+
+#define DRV_LITTLE_ENDIAN 1234
+#define DRV_BIG_ENDIAN 4321
+
+/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
+ * by uncommenting the define which fits your platform endianness
+ */
+//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
+#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
+
+#else /* defined __BYTE_ORDER__ */
+
+#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
+#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
+#define DRV_BYTE_ORDER __BYTE_ORDER__
+
+#endif /* __BYTE_ORDER__*/
+#endif /* DRV_BYTE_ORDER */
+
+/**
+ * @}
+ *
+ */
+
+/** @defgroup STMicroelectronics sensors common types
+ * @{
+ *
+ */
+
+#ifndef MEMS_SHARED_TYPES
+#define MEMS_SHARED_TYPES
+
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
+} bitwise_t;
+
+#define PROPERTY_DISABLE (0U)
+#define PROPERTY_ENABLE (1U)
+
+/** @addtogroup Interfaces_Functions
+ * @brief This section provide a set of functions used to read and
+ * write a generic register of the device.
+ * MANDATORY: return 0 -> no Error.
+ * @{
+ *
+ */
+
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
+
+typedef struct
+{
+ /** Component mandatory fields **/
+ stmdev_write_ptr write_reg;
+ stmdev_read_ptr read_reg;
+ /** Customizable optional pointer **/
+ void *handle;
+} stmdev_ctx_t;
+
+/**
+ * @}
+ *
+ */
+
+#endif /* MEMS_SHARED_TYPES */
+
+#ifndef MEMS_UCF_SHARED_TYPES
+#define MEMS_UCF_SHARED_TYPES
+
+/** @defgroup Generic address-data structure definition
+ * @brief This structure is useful to load a predefined configuration
+ * of a sensor.
+ * You can create a sensor configuration by your own or using
+ * Unico / Unicleo tools available on STMicroelectronics
+ * web site.
+ *
+ * @{
+ *
+ */
+
+typedef struct
+{
+ uint8_t address;
+ uint8_t data;
+} ucf_line_t;
+
+/**
+ * @}
+ *
+ */
+
+#endif /* MEMS_UCF_SHARED_TYPES */
+
+/**
+ * @}
+ *
+ */
+
+/** @defgroup LPS27HHTW_Infos
+ * @{
+ *
+ */
+
+/** I2C Device Address 8 bit format if SA0=0 -> B9 if SA0=1 -> BB **/
+#define LPS27HHTW_I2C_ADD_H 0xBBU
+#define LPS27HHTW_I2C_ADD_L 0xB9U
+
+/** Device Identification (Who am I) **/
+#define LPS27HHTW_ID 0xB3U
+
+/**
+ * @}
+ *
+ */
+
+#define LPS27HHTW_INTERRUPT_CFG 0x0BU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t pe : 2; /* ple + phe */
+ uint8_t lir : 1;
+ uint8_t diff_en : 1;
+ uint8_t reset_az : 1;
+ uint8_t autozero : 1;
+ uint8_t reset_arp : 1;
+ uint8_t autorefp : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t autorefp : 1;
+ uint8_t reset_arp : 1;
+ uint8_t autozero : 1;
+ uint8_t reset_az : 1;
+ uint8_t diff_en : 1;
+ uint8_t lir : 1;
+ uint8_t pe : 2; /* ple + phe */
+#endif /* DRV_BYTE_ORDER */
+} lps27hhtw_interrupt_cfg_t;
+
+#define LPS27HHTW_THS_P_L 0x0CU
+typedef struct
+{
+ uint8_t ths : 8;
+} lps27hhtw_ths_p_l_t;
+
+#define LPS27HHTW_THS_P_H 0x0DU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t ths : 7;
+ uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t ths : 7;
+#endif /* DRV_BYTE_ORDER */
+} lps27hhtw_ths_p_h_t;
+
+#define LPS27HHTW_IF_CTRL 0x0EU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t i2c_disable : 1;
+ uint8_t i3c_disable : 1;
+ uint8_t pd_dis_int1 : 1;
+ uint8_t sdo_pu_en : 1;
+ uint8_t sda_pu_en : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t int_en_i3c : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int_en_i3c : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t sda_pu_en : 1;
+ uint8_t sdo_pu_en : 1;
+ uint8_t pd_dis_int1 : 1;
+ uint8_t i3c_disable : 1;
+ uint8_t i2c_disable : 1;
+#endif /* DRV_BYTE_ORDER */
+} lps27hhtw_if_ctrl_t;
+
+#define LPS27HHTW_WHO_AM_I 0x0FU
+#define LPS27HHTW_CTRL_REG1 0x10U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t sim : 1;
+ uint8_t bdu : 1;
+ uint8_t lpfp_cfg : 2; /* en_lpfp + lpfp_cfg */
+ uint8_t odr : 3;
+ uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t odr : 3;
+ uint8_t lpfp_cfg : 2; /* en_lpfp + lpfp_cfg */
+ uint8_t bdu : 1;
+ uint8_t sim : 1;
+#endif /* DRV_BYTE_ORDER */
+
+} lps27hhtw_ctrl_reg1_t;
+
+#define LPS27HHTW_CTRL_REG2 0x11U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t one_shot : 1;
+ uint8_t low_noise_en : 1;
+ uint8_t swreset : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t if_add_inc : 1;
+ uint8_t pp_od : 1;
+ uint8_t int_h_l : 1;
+ uint8_t boot : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t boot : 1;
+ uint8_t int_h_l : 1;
+ uint8_t pp_od : 1;
+ uint8_t if_add_inc : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t swreset : 1;
+ uint8_t low_noise_en : 1;
+ uint8_t one_shot : 1;
+#endif /* DRV_BYTE_ORDER */
+
+} lps27hhtw_ctrl_reg2_t;
+
+#define LPS27HHTW_CTRL_REG3 0x12U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t int_s : 2;
+ uint8_t drdy : 1;
+ uint8_t int_f_ovr : 1;
+ uint8_t int_f_wtm : 1;
+ uint8_t int_f_full : 1;
+ uint8_t not_used_01 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 2;
+ uint8_t int_f_full : 1;
+ uint8_t int_f_wtm : 1;
+ uint8_t int_f_ovr : 1;
+ uint8_t drdy : 1;
+ uint8_t int_s : 2;
+#endif /* DRV_BYTE_ORDER */
+} lps27hhtw_ctrl_reg3_t;
+
+#define LPS27HHTW_FIFO_CTRL 0x13U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+uint8_t f_mode :
+ 3; /* f_mode + trig_modes */
+ uint8_t stop_on_wtm : 1;
+ uint8_t not_used_01 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 4;
+ uint8_t stop_on_wtm : 1;
+uint8_t f_mode :
+ 3; /* f_mode + trig_modes */
+#endif /* DRV_BYTE_ORDER */
+} lps27hhtw_fifo_ctrl_t;
+
+#define LPS27HHTW_FIFO_WTM 0x14U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t wtm : 7;
+ uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t wtm : 7;
+#endif /* DRV_BYTE_ORDER */
+} lps27hhtw_fifo_wtm_t;
+
+#define LPS27HHTW_REF_P_L 0x15U
+#define LPS27HHTW_REF_P_H 0x16U
+#define LPS27HHTW_RPDS_L 0x18U
+#define LPS27HHTW_RPDS_H 0x19U
+#define LPS27HHTW_INT_SOURCE 0x24U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t ph : 1;
+ uint8_t pl : 1;
+ uint8_t ia : 1;
+ uint8_t not_used_01 : 4;
+ uint8_t boot_on : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t boot_on : 1;
+ uint8_t not_used_01 : 4;
+ uint8_t ia : 1;
+ uint8_t pl : 1;
+ uint8_t ph : 1;
+#endif /* DRV_BYTE_ORDER */
+} lps27hhtw_int_source_t;
+
+#define LPS27HHTW_FIFO_STATUS1 0x25U
+#define LPS27HHTW_FIFO_STATUS2 0x26U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t not_used_01 : 5;
+ uint8_t fifo_full_ia : 1;
+ uint8_t fifo_ovr_ia : 1;
+ uint8_t fifo_wtm_ia : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fifo_wtm_ia : 1;
+ uint8_t fifo_ovr_ia : 1;
+ uint8_t fifo_full_ia : 1;
+ uint8_t not_used_01 : 5;
+#endif /* DRV_BYTE_ORDER */
+} lps27hhtw_fifo_status2_t;
+
+#define LPS27HHTW_STATUS 0x27U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t p_da : 1;
+ uint8_t t_da : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t p_or : 1;
+ uint8_t t_or : 1;
+ uint8_t not_used_02 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 2;
+ uint8_t t_or : 1;
+ uint8_t p_or : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t t_da : 1;
+ uint8_t p_da : 1;
+#endif /* DRV_BYTE_ORDER */
+} lps27hhtw_status_t;
+
+#define LPS27HHTW_PRESS_OUT_XL 0x28U
+#define LPS27HHTW_PRESS_OUT_L 0x29U
+#define LPS27HHTW_PRESS_OUT_H 0x2AU
+#define LPS27HHTW_TEMP_OUT_L 0x2BU
+#define LPS27HHTW_TEMP_OUT_H 0x2CU
+#define LPS27HHTW_FIFO_DATA_OUT_PRESS_XL 0x78U
+#define LPS27HHTW_FIFO_DATA_OUT_PRESS_L 0x79U
+#define LPS27HHTW_FIFO_DATA_OUT_PRESS_H 0x7AU
+#define LPS27HHTW_FIFO_DATA_OUT_TEMP_L 0x7BU
+#define LPS27HHTW_FIFO_DATA_OUT_TEMP_H 0x7CU
+
+/**
+ * @defgroup LPS27HHTW_Register_Union
+ * @brief This union group all the registers having a bit-field
+ * description.
+ * This union is useful but it's not needed by the driver.
+ *
+ * REMOVING this union you are compliant with:
+ * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
+ *
+ * @{
+ *
+ */
+typedef union
+{
+ lps27hhtw_interrupt_cfg_t interrupt_cfg;
+ lps27hhtw_if_ctrl_t if_ctrl;
+ lps27hhtw_ctrl_reg1_t ctrl_reg1;
+ lps27hhtw_ctrl_reg2_t ctrl_reg2;
+ lps27hhtw_ctrl_reg3_t ctrl_reg3;
+ lps27hhtw_fifo_ctrl_t fifo_ctrl;
+ lps27hhtw_fifo_wtm_t fifo_wtm;
+ lps27hhtw_int_source_t int_source;
+ lps27hhtw_fifo_status2_t fifo_status2;
+ lps27hhtw_status_t status;
+ bitwise_t bitwise;
+ uint8_t byte;
+} lps27hhtw_reg_t;
+
+/**
+ * @}
+ *
+ */
+
+int32_t lps27hhtw_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len);
+int32_t lps27hhtw_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len);
+
+float_t lps27hhtw_from_lsb_to_hpa(int32_t lsb);
+
+float_t lps27hhtw_from_lsb_to_celsius(int16_t lsb);
+
+int32_t lps27hhtw_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lps27hhtw_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lps27hhtw_autozero_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lps27hhtw_autozero_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lps27hhtw_pressure_snap_rst_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lps27hhtw_pressure_snap_rst_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lps27hhtw_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lps27hhtw_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lps27hhtw_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lps27hhtw_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+typedef enum
+{
+ LPS27HHTW_POWER_DOWN = 0x00,
+ LPS27HHTW_ONE_SHOOT = 0x08,
+ LPS27HHTW_1_Hz = 0x01,
+ LPS27HHTW_10_Hz = 0x02,
+ LPS27HHTW_25_Hz = 0x03,
+ LPS27HHTW_50_Hz = 0x04,
+ LPS27HHTW_75_Hz = 0x05,
+ LPS27HHTW_1_Hz_LOW_NOISE = 0x11,
+ LPS27HHTW_10_Hz_LOW_NOISE = 0x12,
+ LPS27HHTW_25_Hz_LOW_NOISE = 0x13,
+ LPS27HHTW_50_Hz_LOW_NOISE = 0x14,
+ LPS27HHTW_75_Hz_LOW_NOISE = 0x15,
+ LPS27HHTW_100_Hz = 0x06,
+ LPS27HHTW_200_Hz = 0x07,
+} lps27hhtw_odr_t;
+int32_t lps27hhtw_data_rate_set(stmdev_ctx_t *ctx,
+ lps27hhtw_odr_t val);
+int32_t lps27hhtw_data_rate_get(stmdev_ctx_t *ctx,
+ lps27hhtw_odr_t *val);
+
+int32_t lps27hhtw_pressure_ref_set(stmdev_ctx_t *ctx, int16_t val);
+int32_t lps27hhtw_pressure_ref_get(stmdev_ctx_t *ctx, int16_t *val);
+
+int32_t lps27hhtw_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val);
+int32_t lps27hhtw_pressure_offset_get(stmdev_ctx_t *ctx,
+ int16_t *val);
+
+typedef struct
+{
+ lps27hhtw_int_source_t int_source;
+ lps27hhtw_fifo_status2_t fifo_status2;
+ lps27hhtw_status_t status;
+} lps27hhtw_all_sources_t;
+int32_t lps27hhtw_all_sources_get(stmdev_ctx_t *ctx,
+ lps27hhtw_all_sources_t *val);
+
+int32_t lps27hhtw_status_reg_get(stmdev_ctx_t *ctx,
+ lps27hhtw_status_t *val);
+
+int32_t lps27hhtw_press_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lps27hhtw_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lps27hhtw_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff);
+
+int32_t lps27hhtw_temperature_raw_get(stmdev_ctx_t *ctx,
+ int16_t *buff);
+
+int32_t lps27hhtw_fifo_pressure_raw_get(stmdev_ctx_t *ctx,
+ uint32_t *buff);
+
+int32_t lps27hhtw_fifo_temperature_raw_get(stmdev_ctx_t *ctx,
+ int16_t *buff);
+
+int32_t lps27hhtw_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
+
+int32_t lps27hhtw_reset_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lps27hhtw_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lps27hhtw_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lps27hhtw_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lps27hhtw_boot_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lps27hhtw_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+ LPS27HHTW_LPF_ODR_DIV_2 = 0,
+ LPS27HHTW_LPF_ODR_DIV_9 = 2,
+ LPS27HHTW_LPF_ODR_DIV_20 = 3,
+} lps27hhtw_lpfp_cfg_t;
+int32_t lps27hhtw_lp_bandwidth_set(stmdev_ctx_t *ctx,
+ lps27hhtw_lpfp_cfg_t val);
+int32_t lps27hhtw_lp_bandwidth_get(stmdev_ctx_t *ctx,
+ lps27hhtw_lpfp_cfg_t *val);
+
+typedef enum
+{
+ LPS27HHTW_I2C_ENABLE = 0,
+ LPS27HHTW_I2C_DISABLE = 1,
+} lps27hhtw_i2c_disable_t;
+int32_t lps27hhtw_i2c_interface_set(stmdev_ctx_t *ctx,
+ lps27hhtw_i2c_disable_t val);
+int32_t lps27hhtw_i2c_interface_get(stmdev_ctx_t *ctx,
+ lps27hhtw_i2c_disable_t *val);
+
+typedef enum
+{
+ LPS27HHTW_I3C_ENABLE = 0x00,
+ LPS27HHTW_I3C_ENABLE_INT_PIN_ENABLE = 0x10,
+ LPS27HHTW_I3C_DISABLE = 0x11,
+} lps27hhtw_i3c_disable_t;
+int32_t lps27hhtw_i3c_interface_set(stmdev_ctx_t *ctx,
+ lps27hhtw_i3c_disable_t val);
+int32_t lps27hhtw_i3c_interface_get(stmdev_ctx_t *ctx,
+ lps27hhtw_i3c_disable_t *val);
+
+typedef enum
+{
+ LPS27HHTW_PULL_UP_DISCONNECT = 0,
+ LPS27HHTW_PULL_UP_CONNECT = 1,
+} lps27hhtw_pu_en_t;
+int32_t lps27hhtw_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
+ lps27hhtw_pu_en_t val);
+int32_t lps27hhtw_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
+ lps27hhtw_pu_en_t *val);
+int32_t lps27hhtw_sda_mode_set(stmdev_ctx_t *ctx,
+ lps27hhtw_pu_en_t val);
+int32_t lps27hhtw_sda_mode_get(stmdev_ctx_t *ctx,
+ lps27hhtw_pu_en_t *val);
+
+typedef enum
+{
+ LPS27HHTW_SPI_4_WIRE = 0,
+ LPS27HHTW_SPI_3_WIRE = 1,
+} lps27hhtw_sim_t;
+int32_t lps27hhtw_spi_mode_set(stmdev_ctx_t *ctx,
+ lps27hhtw_sim_t val);
+int32_t lps27hhtw_spi_mode_get(stmdev_ctx_t *ctx,
+ lps27hhtw_sim_t *val);
+
+typedef enum
+{
+ LPS27HHTW_INT_PULSED = 0,
+ LPS27HHTW_INT_LATCHED = 1,
+} lps27hhtw_lir_t;
+int32_t lps27hhtw_int_notification_set(stmdev_ctx_t *ctx,
+ lps27hhtw_lir_t val);
+int32_t lps27hhtw_int_notification_get(stmdev_ctx_t *ctx,
+ lps27hhtw_lir_t *val);
+
+typedef enum
+{
+ LPS27HHTW_PUSH_PULL = 0,
+ LPS27HHTW_OPEN_DRAIN = 1,
+} lps27hhtw_pp_od_t;
+int32_t lps27hhtw_pin_mode_set(stmdev_ctx_t *ctx,
+ lps27hhtw_pp_od_t val);
+int32_t lps27hhtw_pin_mode_get(stmdev_ctx_t *ctx,
+ lps27hhtw_pp_od_t *val);
+
+typedef enum
+{
+ LPS27HHTW_ACTIVE_HIGH = 0,
+ LPS27HHTW_ACTIVE_LOW = 1,
+} lps27hhtw_int_h_l_t;
+int32_t lps27hhtw_pin_polarity_set(stmdev_ctx_t *ctx,
+ lps27hhtw_int_h_l_t val);
+int32_t lps27hhtw_pin_polarity_get(stmdev_ctx_t *ctx,
+ lps27hhtw_int_h_l_t *val);
+
+int32_t lps27hhtw_pin_int_route_set(stmdev_ctx_t *ctx,
+ lps27hhtw_ctrl_reg3_t *val);
+int32_t lps27hhtw_pin_int_route_get(stmdev_ctx_t *ctx,
+ lps27hhtw_ctrl_reg3_t *val);
+
+typedef enum
+{
+ LPS27HHTW_NO_THRESHOLD = 0,
+ LPS27HHTW_POSITIVE = 1,
+ LPS27HHTW_NEGATIVE = 2,
+ LPS27HHTW_BOTH = 3,
+} lps27hhtw_pe_t;
+int32_t lps27hhtw_int_on_threshold_set(stmdev_ctx_t *ctx,
+ lps27hhtw_pe_t val);
+int32_t lps27hhtw_int_on_threshold_get(stmdev_ctx_t *ctx,
+ lps27hhtw_pe_t *val);
+
+int32_t lps27hhtw_int_treshold_set(stmdev_ctx_t *ctx, uint16_t buff);
+int32_t lps27hhtw_int_treshold_get(stmdev_ctx_t *ctx, uint16_t *buff);
+
+typedef enum
+{
+ LPS27HHTW_BYPASS_MODE = 0,
+ LPS27HHTW_FIFO_MODE = 1,
+ LPS27HHTW_STREAM_MODE = 2,
+ LPS27HHTW_DYNAMIC_STREAM_MODE = 3,
+ LPS27HHTW_BYPASS_TO_FIFO_MODE = 5,
+ LPS27HHTW_BYPASS_TO_STREAM_MODE = 6,
+ LPS27HHTW_STREAM_TO_FIFO_MODE = 7,
+} lps27hhtw_f_mode_t;
+int32_t lps27hhtw_fifo_mode_set(stmdev_ctx_t *ctx,
+ lps27hhtw_f_mode_t val);
+int32_t lps27hhtw_fifo_mode_get(stmdev_ctx_t *ctx,
+ lps27hhtw_f_mode_t *val);
+
+int32_t lps27hhtw_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lps27hhtw_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lps27hhtw_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lps27hhtw_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lps27hhtw_fifo_data_level_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+
+int32_t lps27hhtw_fifo_src_get(stmdev_ctx_t *ctx,
+ lps27hhtw_fifo_status2_t *val);
+
+int32_t lps27hhtw_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lps27hhtw_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lps27hhtw_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lps27hhtw_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lps27hhtw_fifo_ovr_on_int_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lps27hhtw_fifo_threshold_on_int_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lps27hhtw_fifo_threshold_on_int_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lps27hhtw_fifo_full_on_int_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lps27hhtw_fifo_full_on_int_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+/**
+ * @}
+ *
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*LPS27HHTW_REGS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.c b/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.c
index fcdd1ceabb9e70b94eead0de244e809ef3ccf4ad..e11508ddeb759655845cc3f2a78a41fc23c839d0 100644
--- a/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.c
+++ b/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file lps27hhw_reg.c
- * @author Sensors Software Solution Team
- * @brief LPS27HHW driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lps27hhw_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LPS27HHW driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lps27hhw_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps27hhw_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t lps27hhw_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t lps27hhw_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps27hhw_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lps27hhw_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -85,12 +91,12 @@ int32_t lps27hhw_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
*/
float_t lps27hhw_from_lsb_to_hpa(int32_t lsb)
{
- return ( (float_t) lsb / 4096.0f );
+ return ((float_t) lsb / 4096.0f);
}
float_t lps27hhw_from_lsb_to_celsius(int16_t lsb)
{
- return ( (float_t) lsb / 100.0f );
+ return ((float_t) lsb / 100.0f);
}
/**
@@ -119,11 +125,15 @@ int32_t lps27hhw_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val)
lps27hhw_interrupt_cfg_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.reset_az = val;
- ret = lps27hhw_write_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t*) ®, 1);
+ ret = lps27hhw_write_reg(ctx, LPS27HHW_INTERRUPT_CFG,
+ (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -140,7 +150,7 @@ int32_t lps27hhw_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val)
lps27hhw_interrupt_cfg_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t*) ®, 1);
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t *) ®, 1);
*val = reg.reset_az;
return ret;
@@ -159,11 +169,15 @@ int32_t lps27hhw_autozero_set(stmdev_ctx_t *ctx, uint8_t val)
lps27hhw_interrupt_cfg_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.autozero = val;
- ret = lps27hhw_write_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t*) ®, 1);
+ ret = lps27hhw_write_reg(ctx, LPS27HHW_INTERRUPT_CFG,
+ (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -180,7 +194,7 @@ int32_t lps27hhw_autozero_get(stmdev_ctx_t *ctx, uint8_t *val)
lps27hhw_interrupt_cfg_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t*) ®, 1);
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t *) ®, 1);
*val = reg.autozero;
return ret;
@@ -199,11 +213,15 @@ int32_t lps27hhw_pressure_snap_rst_set(stmdev_ctx_t *ctx, uint8_t val)
lps27hhw_interrupt_cfg_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.reset_arp = val;
- ret = lps27hhw_write_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t*) ®, 1);
+ ret = lps27hhw_write_reg(ctx, LPS27HHW_INTERRUPT_CFG,
+ (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -215,12 +233,13 @@ int32_t lps27hhw_pressure_snap_rst_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps27hhw_pressure_snap_rst_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lps27hhw_pressure_snap_rst_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lps27hhw_interrupt_cfg_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t*) ®, 1);
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t *) ®, 1);
*val = reg.reset_arp;
return ret;
@@ -239,11 +258,15 @@ int32_t lps27hhw_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val)
lps27hhw_interrupt_cfg_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.autorefp = val;
- ret = lps27hhw_write_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t*) ®, 1);
+ ret = lps27hhw_write_reg(ctx, LPS27HHW_INTERRUPT_CFG,
+ (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -260,7 +283,7 @@ int32_t lps27hhw_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val)
lps27hhw_interrupt_cfg_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t*) ®, 1);
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t *) ®, 1);
*val = reg.autorefp;
return ret;
@@ -279,11 +302,14 @@ int32_t lps27hhw_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
lps27hhw_ctrl_reg1_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.bdu = val;
- ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t*) ®, 1);
+ ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -295,12 +321,13 @@ int32_t lps27hhw_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps27hhw_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lps27hhw_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lps27hhw_ctrl_reg1_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t*) ®, 1);
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t *) ®, 1);
*val = reg.bdu;
return ret;
@@ -320,19 +347,30 @@ int32_t lps27hhw_data_rate_set(stmdev_ctx_t *ctx, lps27hhw_odr_t val)
lps27hhw_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if (ret == 0) {
- ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ctrl_reg1.odr = (uint8_t)val & 0x07U;
- ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ctrl_reg2.low_noise_en = ((uint8_t)val & 0x10U) >> 4;
ctrl_reg2.one_shot = ((uint8_t)val & 0x08U) >> 3;
- ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -350,61 +388,85 @@ int32_t lps27hhw_data_rate_get(stmdev_ctx_t *ctx, lps27hhw_odr_t *val)
lps27hhw_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if (ret == 0) {
- ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG1,
+ (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
}
- if (ret == 0) {
- ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2,
+ (uint8_t *)&ctrl_reg2, 1);
+
switch (((ctrl_reg2.low_noise_en << 4) + (ctrl_reg2.one_shot << 3) +
- ctrl_reg1.odr )) {
+ ctrl_reg1.odr))
+ {
case LPS27HHW_POWER_DOWN:
*val = LPS27HHW_POWER_DOWN;
break;
+
case LPS27HHW_ONE_SHOOT:
*val = LPS27HHW_ONE_SHOOT;
break;
+
case LPS27HHW_1_Hz:
*val = LPS27HHW_1_Hz;
break;
+
case LPS27HHW_10_Hz:
*val = LPS27HHW_10_Hz;
break;
+
case LPS27HHW_25_Hz:
*val = LPS27HHW_25_Hz;
break;
+
case LPS27HHW_50_Hz:
*val = LPS27HHW_50_Hz;
break;
+
case LPS27HHW_75_Hz:
*val = LPS27HHW_75_Hz;
break;
+
case LPS27HHW_1_Hz_LOW_NOISE:
*val = LPS27HHW_1_Hz_LOW_NOISE;
break;
+
case LPS27HHW_10_Hz_LOW_NOISE:
*val = LPS27HHW_10_Hz_LOW_NOISE;
break;
+
case LPS27HHW_25_Hz_LOW_NOISE:
*val = LPS27HHW_25_Hz_LOW_NOISE;
break;
+
case LPS27HHW_50_Hz_LOW_NOISE:
*val = LPS27HHW_50_Hz_LOW_NOISE;
break;
+
case LPS27HHW_75_Hz_LOW_NOISE:
*val = LPS27HHW_75_Hz_LOW_NOISE;
break;
+
case LPS27HHW_100_Hz:
*val = LPS27HHW_100_Hz;
break;
+
case LPS27HHW_200_Hz:
*val = LPS27HHW_200_Hz;
break;
+
default:
*val = LPS27HHW_POWER_DOWN;
break;
}
}
+
return ret;
}
@@ -423,8 +485,8 @@ int32_t lps27hhw_pressure_ref_set(stmdev_ctx_t *ctx, int16_t val)
uint8_t buff[2];
int32_t ret;
- buff[1] = (uint8_t) ((uint16_t)val / 256U);
- buff[0] = (uint8_t) ((uint16_t)val - (buff[1] * 256U));
+ buff[1] = (uint8_t)((uint16_t)val / 256U);
+ buff[0] = (uint8_t)((uint16_t)val - (buff[1] * 256U));
ret = lps27hhw_write_reg(ctx, LPS27HHW_REF_P_L, buff, 2);
return ret;
@@ -468,8 +530,8 @@ int32_t lps27hhw_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val)
uint8_t buff[2];
int32_t ret;
- buff[1] = (uint8_t) ((uint16_t)val / 256U);
- buff[0] = (uint8_t) ((uint16_t)val - (buff[1] * 256U));
+ buff[1] = (uint8_t)((uint16_t)val / 256U);
+ buff[0] = (uint8_t)((uint16_t)val - (buff[1] * 256U));
ret = lps27hhw_write_reg(ctx, LPS27HHW_RPDS_L, buff, 2);
return ret;
@@ -506,20 +568,26 @@ int32_t lps27hhw_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps27hhw_all_sources_get(stmdev_ctx_t *ctx, lps27hhw_all_sources_t *val)
+int32_t lps27hhw_all_sources_get(stmdev_ctx_t *ctx,
+ lps27hhw_all_sources_t *val)
{
int32_t ret;
ret = lps27hhw_read_reg(ctx, LPS27HHW_INT_SOURCE,
- (uint8_t*) &(val->int_source), 1);
- if (ret == 0) {
+ (uint8_t *) & (val->int_source), 1);
+
+ if (ret == 0)
+ {
ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_STATUS2,
- (uint8_t*) &(val->fifo_status2), 1);
+ (uint8_t *) & (val->fifo_status2), 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lps27hhw_read_reg(ctx, LPS27HHW_STATUS,
- (uint8_t*) &(val->status), 1);
+ (uint8_t *) & (val->status), 1);
}
+
return ret;
}
@@ -531,10 +599,13 @@ int32_t lps27hhw_all_sources_get(stmdev_ctx_t *ctx, lps27hhw_all_sources_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps27hhw_status_reg_get(stmdev_ctx_t *ctx, lps27hhw_status_t *val)
+int32_t lps27hhw_status_reg_get(stmdev_ctx_t *ctx,
+ lps27hhw_status_t *val)
{
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_STATUS, (uint8_t*) val, 1);
+
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_STATUS, (uint8_t *) val, 1);
+
return ret;
}
@@ -546,12 +617,13 @@ int32_t lps27hhw_status_reg_get(stmdev_ctx_t *ctx, lps27hhw_status_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps27hhw_press_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lps27hhw_press_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lps27hhw_status_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_STATUS, (uint8_t*) ®, 1);
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_STATUS, (uint8_t *) ®, 1);
*val = reg.p_da;
return ret;
@@ -565,12 +637,13 @@ int32_t lps27hhw_press_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps27hhw_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lps27hhw_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lps27hhw_status_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_STATUS, (uint8_t*) ®, 1);
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_STATUS, (uint8_t *) ®, 1);
*val = reg.t_da;
return ret;
@@ -638,12 +711,14 @@ int32_t lps27hhw_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps27hhw_fifo_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff)
+int32_t lps27hhw_fifo_pressure_raw_get(stmdev_ctx_t *ctx,
+ uint32_t *buff)
{
uint8_t reg[3];
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_DATA_OUT_PRESS_XL, reg, 3);
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_DATA_OUT_PRESS_XL, reg,
+ 3);
*buff = reg[2];
*buff = (*buff * 256) + reg[1];
*buff = (*buff * 256) + reg[0];
@@ -660,7 +735,8 @@ int32_t lps27hhw_fifo_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps27hhw_fifo_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff)
+int32_t lps27hhw_fifo_temperature_raw_get(stmdev_ctx_t *ctx,
+ int16_t *buff)
{
uint8_t reg[2];
int32_t ret;
@@ -695,7 +771,9 @@ int32_t lps27hhw_fifo_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff)
int32_t lps27hhw_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lps27hhw_read_reg(ctx, LPS27HHW_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -713,11 +791,14 @@ int32_t lps27hhw_reset_set(stmdev_ctx_t *ctx, uint8_t val)
lps27hhw_ctrl_reg2_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.swreset = val;
- ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t*) ®, 1);
+ ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -735,7 +816,7 @@ int32_t lps27hhw_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
lps27hhw_ctrl_reg2_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t*) ®, 1);
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1);
*val = reg.swreset;
return ret;
@@ -756,11 +837,14 @@ int32_t lps27hhw_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
lps27hhw_ctrl_reg2_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.if_add_inc = val;
- ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t*) ®, 1);
+ ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -779,7 +863,7 @@ int32_t lps27hhw_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
lps27hhw_ctrl_reg2_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t*) ®, 1);
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1);
*val = reg.if_add_inc;
return ret;
@@ -799,11 +883,14 @@ int32_t lps27hhw_boot_set(stmdev_ctx_t *ctx, uint8_t val)
lps27hhw_ctrl_reg2_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.boot = val;
- ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t*) ®, 1);
+ ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -821,7 +908,7 @@ int32_t lps27hhw_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
lps27hhw_ctrl_reg2_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t*) ®, 1);
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1);
*val = reg.boot;
return ret;
@@ -848,16 +935,20 @@ int32_t lps27hhw_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps27hhw_lp_bandwidth_set(stmdev_ctx_t *ctx, lps27hhw_lpfp_cfg_t val)
+int32_t lps27hhw_lp_bandwidth_set(stmdev_ctx_t *ctx,
+ lps27hhw_lpfp_cfg_t val)
{
lps27hhw_ctrl_reg1_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.lpfp_cfg = (uint8_t)val;
- ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t*) ®, 1);
+ ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -869,26 +960,32 @@ int32_t lps27hhw_lp_bandwidth_set(stmdev_ctx_t *ctx, lps27hhw_lpfp_cfg_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps27hhw_lp_bandwidth_get(stmdev_ctx_t *ctx, lps27hhw_lpfp_cfg_t *val)
+int32_t lps27hhw_lp_bandwidth_get(stmdev_ctx_t *ctx,
+ lps27hhw_lpfp_cfg_t *val)
{
lps27hhw_ctrl_reg1_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t*) ®, 1);
- switch (reg.lpfp_cfg) {
- case LPS27HHW_LPF_ODR_DIV_2:
- *val = LPS27HHW_LPF_ODR_DIV_2;
- break;
- case LPS27HHW_LPF_ODR_DIV_9:
- *val = LPS27HHW_LPF_ODR_DIV_9;
- break;
- case LPS27HHW_LPF_ODR_DIV_20:
- *val = LPS27HHW_LPF_ODR_DIV_20;
- break;
- default:
- *val = LPS27HHW_LPF_ODR_DIV_2;
- break;
- }
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t *) ®, 1);
+
+ switch (reg.lpfp_cfg)
+ {
+ case LPS27HHW_LPF_ODR_DIV_2:
+ *val = LPS27HHW_LPF_ODR_DIV_2;
+ break;
+
+ case LPS27HHW_LPF_ODR_DIV_9:
+ *val = LPS27HHW_LPF_ODR_DIV_9;
+ break;
+
+ case LPS27HHW_LPF_ODR_DIV_20:
+ *val = LPS27HHW_LPF_ODR_DIV_20;
+ break;
+
+ default:
+ *val = LPS27HHW_LPF_ODR_DIV_2;
+ break;
+ }
return ret;
}
@@ -915,16 +1012,19 @@ int32_t lps27hhw_lp_bandwidth_get(stmdev_ctx_t *ctx, lps27hhw_lpfp_cfg_t *val)
*
*/
int32_t lps27hhw_i2c_interface_set(stmdev_ctx_t *ctx,
- lps27hhw_i2c_disable_t val)
+ lps27hhw_i2c_disable_t val)
{
lps27hhw_if_ctrl_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.i2c_disable = (uint8_t)val;
- ret = lps27hhw_write_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t*) ®, 1);
+ ret = lps27hhw_write_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -937,23 +1037,27 @@ int32_t lps27hhw_i2c_interface_set(stmdev_ctx_t *ctx,
*
*/
int32_t lps27hhw_i2c_interface_get(stmdev_ctx_t *ctx,
- lps27hhw_i2c_disable_t *val)
+ lps27hhw_i2c_disable_t *val)
{
lps27hhw_if_ctrl_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t*) ®, 1);
- switch (reg.i2c_disable) {
- case LPS27HHW_I2C_ENABLE:
- *val = LPS27HHW_I2C_ENABLE;
- break;
- case LPS27HHW_I2C_DISABLE:
- *val = LPS27HHW_I2C_DISABLE;
- break;
- default:
- *val = LPS27HHW_I2C_ENABLE;
- break;
- }
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t *) ®, 1);
+
+ switch (reg.i2c_disable)
+ {
+ case LPS27HHW_I2C_ENABLE:
+ *val = LPS27HHW_I2C_ENABLE;
+ break;
+
+ case LPS27HHW_I2C_DISABLE:
+ *val = LPS27HHW_I2C_DISABLE;
+ break;
+
+ default:
+ *val = LPS27HHW_I2C_ENABLE;
+ break;
+ }
return ret;
}
@@ -967,17 +1071,20 @@ int32_t lps27hhw_i2c_interface_get(stmdev_ctx_t *ctx,
*
*/
int32_t lps27hhw_i3c_interface_set(stmdev_ctx_t *ctx,
- lps27hhw_i3c_disable_t val)
+ lps27hhw_i3c_disable_t val)
{
lps27hhw_if_ctrl_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.i3c_disable = ((uint8_t)val & 0x01u);
reg.int_en_i3c = ((uint8_t)val & 0x10U) >> 4;
- ret = lps27hhw_write_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t*) ®, 1);
+ ret = lps27hhw_write_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -990,27 +1097,32 @@ int32_t lps27hhw_i3c_interface_set(stmdev_ctx_t *ctx,
*
*/
int32_t lps27hhw_i3c_interface_get(stmdev_ctx_t *ctx,
- lps27hhw_i3c_disable_t *val)
+ lps27hhw_i3c_disable_t *val)
{
lps27hhw_if_ctrl_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t*) ®, 1);
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t *) ®, 1);
- switch ((reg.int_en_i3c << 4) + reg.int_en_i3c) {
+ switch ((reg.int_en_i3c << 4) + reg.int_en_i3c)
+ {
case LPS27HHW_I3C_ENABLE:
*val = LPS27HHW_I3C_ENABLE;
break;
+
case LPS27HHW_I3C_ENABLE_INT_PIN_ENABLE:
*val = LPS27HHW_I3C_ENABLE_INT_PIN_ENABLE;
break;
+
case LPS27HHW_I3C_DISABLE:
*val = LPS27HHW_I3C_DISABLE;
break;
+
default:
*val = LPS27HHW_I3C_ENABLE;
break;
}
+
return ret;
}
@@ -1022,16 +1134,20 @@ int32_t lps27hhw_i3c_interface_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps27hhw_sdo_sa0_mode_set(stmdev_ctx_t *ctx, lps27hhw_pu_en_t val)
+int32_t lps27hhw_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
+ lps27hhw_pu_en_t val)
{
lps27hhw_if_ctrl_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.sdo_pu_en = (uint8_t)val;
- ret = lps27hhw_write_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t*) ®, 1);
+ ret = lps27hhw_write_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1043,19 +1159,24 @@ int32_t lps27hhw_sdo_sa0_mode_set(stmdev_ctx_t *ctx, lps27hhw_pu_en_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps27hhw_sdo_sa0_mode_get(stmdev_ctx_t *ctx, lps27hhw_pu_en_t *val)
+int32_t lps27hhw_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
+ lps27hhw_pu_en_t *val)
{
lps27hhw_if_ctrl_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t*) ®, 1);
- switch (reg.sdo_pu_en) {
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t *) ®, 1);
+
+ switch (reg.sdo_pu_en)
+ {
case LPS27HHW_PULL_UP_DISCONNECT:
*val = LPS27HHW_PULL_UP_DISCONNECT;
break;
+
case LPS27HHW_PULL_UP_CONNECT:
*val = LPS27HHW_PULL_UP_CONNECT;
break;
+
default:
*val = LPS27HHW_PULL_UP_DISCONNECT;
break;
@@ -1077,11 +1198,14 @@ int32_t lps27hhw_sda_mode_set(stmdev_ctx_t *ctx, lps27hhw_pu_en_t val)
lps27hhw_if_ctrl_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.sda_pu_en = (uint8_t)val;
- ret = lps27hhw_write_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t*) ®, 1);
+ ret = lps27hhw_write_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1093,23 +1217,29 @@ int32_t lps27hhw_sda_mode_set(stmdev_ctx_t *ctx, lps27hhw_pu_en_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps27hhw_sda_mode_get(stmdev_ctx_t *ctx, lps27hhw_pu_en_t *val)
+int32_t lps27hhw_sda_mode_get(stmdev_ctx_t *ctx,
+ lps27hhw_pu_en_t *val)
{
lps27hhw_if_ctrl_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t*) ®, 1);
- switch (reg.sda_pu_en) {
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t *) ®, 1);
+
+ switch (reg.sda_pu_en)
+ {
case LPS27HHW_PULL_UP_DISCONNECT:
*val = LPS27HHW_PULL_UP_DISCONNECT;
break;
+
case LPS27HHW_PULL_UP_CONNECT:
*val = LPS27HHW_PULL_UP_CONNECT;
break;
+
default:
*val = LPS27HHW_PULL_UP_DISCONNECT;
break;
}
+
return ret;
}
@@ -1126,11 +1256,14 @@ int32_t lps27hhw_spi_mode_set(stmdev_ctx_t *ctx, lps27hhw_sim_t val)
lps27hhw_ctrl_reg1_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.sim = (uint8_t)val;
- ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t*) ®, 1);
+ ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1147,18 +1280,23 @@ int32_t lps27hhw_spi_mode_get(stmdev_ctx_t *ctx, lps27hhw_sim_t *val)
lps27hhw_ctrl_reg1_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t*) ®, 1);
- switch (reg.sim) {
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t *) ®, 1);
+
+ switch (reg.sim)
+ {
case LPS27HHW_SPI_4_WIRE:
*val = LPS27HHW_SPI_4_WIRE;
break;
+
case LPS27HHW_SPI_3_WIRE:
*val = LPS27HHW_SPI_3_WIRE;
break;
+
default:
*val = LPS27HHW_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -1183,16 +1321,21 @@ int32_t lps27hhw_spi_mode_get(stmdev_ctx_t *ctx, lps27hhw_sim_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps27hhw_int_notification_set(stmdev_ctx_t *ctx, lps27hhw_lir_t val)
+int32_t lps27hhw_int_notification_set(stmdev_ctx_t *ctx,
+ lps27hhw_lir_t val)
{
lps27hhw_interrupt_cfg_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.lir = (uint8_t)val;
- ret = lps27hhw_write_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t*) ®, 1);
+ ret = lps27hhw_write_reg(ctx, LPS27HHW_INTERRUPT_CFG,
+ (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1204,24 +1347,29 @@ int32_t lps27hhw_int_notification_set(stmdev_ctx_t *ctx, lps27hhw_lir_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps27hhw_int_notification_get(stmdev_ctx_t *ctx, lps27hhw_lir_t *val)
+int32_t lps27hhw_int_notification_get(stmdev_ctx_t *ctx,
+ lps27hhw_lir_t *val)
{
lps27hhw_interrupt_cfg_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t*) ®, 1);
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t *) ®, 1);
- switch (reg.lir) {
+ switch (reg.lir)
+ {
case LPS27HHW_INT_PULSED:
*val = LPS27HHW_INT_PULSED;
break;
+
case LPS27HHW_INT_LATCHED:
*val = LPS27HHW_INT_LATCHED;
break;
+
default:
*val = LPS27HHW_INT_PULSED;
break;
}
+
return ret;
}
@@ -1238,10 +1386,12 @@ int32_t lps27hhw_pin_mode_set(stmdev_ctx_t *ctx, lps27hhw_pp_od_t val)
lps27hhw_ctrl_reg2_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.pp_od = (uint8_t)val;
- ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t*) ®, 1);
+ ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1);
}
return ret;
@@ -1255,21 +1405,24 @@ int32_t lps27hhw_pin_mode_set(stmdev_ctx_t *ctx, lps27hhw_pp_od_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps27hhw_pin_mode_get(stmdev_ctx_t *ctx, lps27hhw_pp_od_t *val)
+int32_t lps27hhw_pin_mode_get(stmdev_ctx_t *ctx,
+ lps27hhw_pp_od_t *val)
{
lps27hhw_ctrl_reg2_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t*) ®, 1);
-
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1);
- switch (reg.pp_od) {
+ switch (reg.pp_od)
+ {
case LPS27HHW_PUSH_PULL:
*val = LPS27HHW_PUSH_PULL;
break;
+
case LPS27HHW_OPEN_DRAIN:
*val = LPS27HHW_OPEN_DRAIN;
break;
+
default:
*val = LPS27HHW_PUSH_PULL;
break;
@@ -1286,15 +1439,18 @@ int32_t lps27hhw_pin_mode_get(stmdev_ctx_t *ctx, lps27hhw_pp_od_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps27hhw_pin_polarity_set(stmdev_ctx_t *ctx, lps27hhw_int_h_l_t val)
+int32_t lps27hhw_pin_polarity_set(stmdev_ctx_t *ctx,
+ lps27hhw_int_h_l_t val)
{
lps27hhw_ctrl_reg2_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.int_h_l = (uint8_t)val;
- ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t*) ®, 1);
+ ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1);
}
return ret;
@@ -1308,20 +1464,24 @@ int32_t lps27hhw_pin_polarity_set(stmdev_ctx_t *ctx, lps27hhw_int_h_l_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps27hhw_pin_polarity_get(stmdev_ctx_t *ctx, lps27hhw_int_h_l_t *val)
+int32_t lps27hhw_pin_polarity_get(stmdev_ctx_t *ctx,
+ lps27hhw_int_h_l_t *val)
{
lps27hhw_ctrl_reg2_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t*) ®, 1);
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1);
- switch (reg.int_h_l) {
+ switch (reg.int_h_l)
+ {
case LPS27HHW_ACTIVE_HIGH:
*val = LPS27HHW_ACTIVE_HIGH;
break;
+
case LPS27HHW_ACTIVE_LOW:
*val = LPS27HHW_ACTIVE_LOW;
break;
+
default:
*val = LPS27HHW_ACTIVE_HIGH;
break;
@@ -1339,10 +1499,12 @@ int32_t lps27hhw_pin_polarity_get(stmdev_ctx_t *ctx, lps27hhw_int_h_l_t *val)
*
*/
int32_t lps27hhw_pin_int_route_set(stmdev_ctx_t *ctx,
- lps27hhw_ctrl_reg3_t *val)
+ lps27hhw_ctrl_reg3_t *val)
{
int32_t ret;
- ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t*) val, 1);
+
+ ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t *) val, 1);
+
return ret;
}
@@ -1355,10 +1517,12 @@ int32_t lps27hhw_pin_int_route_set(stmdev_ctx_t *ctx,
*
*/
int32_t lps27hhw_pin_int_route_get(stmdev_ctx_t *ctx,
- lps27hhw_ctrl_reg3_t *val)
+ lps27hhw_ctrl_reg3_t *val)
{
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t*) val, 1);
+
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t *) val, 1);
+
return ret;
}
@@ -1383,23 +1547,32 @@ int32_t lps27hhw_pin_int_route_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps27hhw_int_on_threshold_set(stmdev_ctx_t *ctx, lps27hhw_pe_t val)
+int32_t lps27hhw_int_on_threshold_set(stmdev_ctx_t *ctx,
+ lps27hhw_pe_t val)
{
lps27hhw_interrupt_cfg_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.pe = (uint8_t)val;
- if (val == LPS27HHW_NO_THRESHOLD){
+ if (val == LPS27HHW_NO_THRESHOLD)
+ {
reg.diff_en = PROPERTY_DISABLE;
}
- else{
+
+ else
+ {
reg.diff_en = PROPERTY_ENABLE;
}
- ret = lps27hhw_write_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t*) ®, 1);
+
+ ret = lps27hhw_write_reg(ctx, LPS27HHW_INTERRUPT_CFG,
+ (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1411,26 +1584,32 @@ int32_t lps27hhw_int_on_threshold_set(stmdev_ctx_t *ctx, lps27hhw_pe_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps27hhw_int_on_threshold_get(stmdev_ctx_t *ctx, lps27hhw_pe_t *val)
+int32_t lps27hhw_int_on_threshold_get(stmdev_ctx_t *ctx,
+ lps27hhw_pe_t *val)
{
lps27hhw_interrupt_cfg_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t*) ®, 1);
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t *) ®, 1);
- switch (reg.pe) {
+ switch (reg.pe)
+ {
case LPS27HHW_NO_THRESHOLD:
*val = LPS27HHW_NO_THRESHOLD;
break;
+
case LPS27HHW_POSITIVE:
*val = LPS27HHW_POSITIVE;
break;
+
case LPS27HHW_NEGATIVE:
*val = LPS27HHW_NEGATIVE;
break;
+
case LPS27HHW_BOTH:
*val = LPS27HHW_BOTH;
break;
+
default:
*val = LPS27HHW_NO_THRESHOLD;
break;
@@ -1450,16 +1629,20 @@ int32_t lps27hhw_int_on_threshold_get(stmdev_ctx_t *ctx, lps27hhw_pe_t *val)
int32_t lps27hhw_int_treshold_set(stmdev_ctx_t *ctx, uint16_t buff)
{
int32_t ret;
+
lps27hhw_ths_p_l_t ths_p_l;
lps27hhw_ths_p_h_t ths_p_h;
ths_p_l.ths = (uint8_t)(buff & 0x00FFU);
ths_p_h.ths = (uint8_t)((buff & 0x7F00U) >> 8);
ret = lps27hhw_write_reg(ctx, LPS27HHW_THS_P_L,
- (uint8_t*)&ths_p_l, 1);
- if (ret == 0) {
- ret = lps27hhw_write_reg(ctx, LPS27HHW_THS_P_H,
- (uint8_t*)&ths_p_h, 1);
+ (uint8_t *)&ths_p_l, 1);
+
+ if (ret == 0)
+ {
+ ret = lps27hhw_write_reg(ctx, LPS27HHW_THS_P_H,
+ (uint8_t *)&ths_p_h, 1);
}
+
return ret;
}
@@ -1474,16 +1657,20 @@ int32_t lps27hhw_int_treshold_set(stmdev_ctx_t *ctx, uint16_t buff)
int32_t lps27hhw_int_treshold_get(stmdev_ctx_t *ctx, uint16_t *buff)
{
int32_t ret;
+
lps27hhw_ths_p_l_t ths_p_l;
lps27hhw_ths_p_h_t ths_p_h;
ret = lps27hhw_read_reg(ctx, LPS27HHW_THS_P_L,
- (uint8_t*)&ths_p_l, 1);
- if (ret == 0) {
- ret = lps27hhw_read_reg(ctx, LPS27HHW_THS_P_H,
- (uint8_t*)&ths_p_h, 1);
- *buff = (uint16_t)ths_p_h.ths << 8;
- *buff |= (uint16_t)ths_p_l.ths;
- }
+ (uint8_t *)&ths_p_l, 1);
+
+ if (ret == 0)
+ {
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_THS_P_H,
+ (uint8_t *)&ths_p_h, 1);
+ *buff = (uint16_t)ths_p_h.ths << 8;
+ *buff |= (uint16_t)ths_p_l.ths;
+ }
+
return ret;
}
@@ -1507,16 +1694,20 @@ int32_t lps27hhw_int_treshold_get(stmdev_ctx_t *ctx, uint16_t *buff)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps27hhw_fifo_mode_set(stmdev_ctx_t *ctx, lps27hhw_f_mode_t val)
+int32_t lps27hhw_fifo_mode_set(stmdev_ctx_t *ctx,
+ lps27hhw_f_mode_t val)
{
lps27hhw_fifo_ctrl_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_CTRL, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.f_mode = (uint8_t)val;
- ret = lps27hhw_write_reg(ctx, LPS27HHW_FIFO_CTRL, (uint8_t*) ®, 1);
+ ret = lps27hhw_write_reg(ctx, LPS27HHW_FIFO_CTRL, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1528,35 +1719,44 @@ int32_t lps27hhw_fifo_mode_set(stmdev_ctx_t *ctx, lps27hhw_f_mode_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps27hhw_fifo_mode_get(stmdev_ctx_t *ctx, lps27hhw_f_mode_t *val)
+int32_t lps27hhw_fifo_mode_get(stmdev_ctx_t *ctx,
+ lps27hhw_f_mode_t *val)
{
lps27hhw_fifo_ctrl_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_CTRL, (uint8_t*) ®, 1);
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_CTRL, (uint8_t *) ®, 1);
- switch (reg.f_mode) {
+ switch (reg.f_mode)
+ {
case LPS27HHW_BYPASS_MODE:
*val = LPS27HHW_BYPASS_MODE;
break;
+
case LPS27HHW_FIFO_MODE:
*val = LPS27HHW_FIFO_MODE;
break;
+
case LPS27HHW_STREAM_MODE:
*val = LPS27HHW_STREAM_MODE;
break;
+
case LPS27HHW_DYNAMIC_STREAM_MODE:
*val = LPS27HHW_DYNAMIC_STREAM_MODE;
break;
+
case LPS27HHW_BYPASS_TO_FIFO_MODE:
*val = LPS27HHW_BYPASS_TO_FIFO_MODE;
break;
+
case LPS27HHW_BYPASS_TO_STREAM_MODE:
*val = LPS27HHW_BYPASS_TO_STREAM_MODE;
break;
+
case LPS27HHW_STREAM_TO_FIFO_MODE:
*val = LPS27HHW_STREAM_TO_FIFO_MODE;
break;
+
default:
*val = LPS27HHW_BYPASS_MODE;
break;
@@ -1579,11 +1779,14 @@ int32_t lps27hhw_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
lps27hhw_fifo_ctrl_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_CTRL, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_CTRL, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.stop_on_wtm = val;
- ret = lps27hhw_write_reg(ctx, LPS27HHW_FIFO_CTRL, (uint8_t*) ®, 1);
+ ret = lps27hhw_write_reg(ctx, LPS27HHW_FIFO_CTRL, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1601,7 +1804,7 @@ int32_t lps27hhw_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
lps27hhw_fifo_ctrl_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_CTRL, (uint8_t*) ®, 1);
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_CTRL, (uint8_t *) ®, 1);
*val = reg.stop_on_wtm;
return ret;
@@ -1620,11 +1823,14 @@ int32_t lps27hhw_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
lps27hhw_fifo_wtm_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_WTM, (uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_WTM, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.wtm = val;
- ret = lps27hhw_write_reg(ctx, LPS27HHW_FIFO_WTM, (uint8_t*) ®, 1);
+ ret = lps27hhw_write_reg(ctx, LPS27HHW_FIFO_WTM, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -1641,7 +1847,7 @@ int32_t lps27hhw_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
lps27hhw_fifo_wtm_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_WTM, (uint8_t*) ®, 1);
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_WTM, (uint8_t *) ®, 1);
*val = reg.wtm;
return ret;
@@ -1658,7 +1864,9 @@ int32_t lps27hhw_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t lps27hhw_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_STATUS1, buff, 1);
+
return ret;
}
@@ -1670,10 +1878,13 @@ int32_t lps27hhw_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps27hhw_fifo_src_get(stmdev_ctx_t *ctx, lps27hhw_fifo_status2_t *val)
+int32_t lps27hhw_fifo_src_get(stmdev_ctx_t *ctx,
+ lps27hhw_fifo_status2_t *val)
{
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_STATUS2, (uint8_t*) val, 1);
+
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_STATUS2, (uint8_t *) val, 1);
+
return ret;
}
@@ -1690,7 +1901,7 @@ int32_t lps27hhw_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lps27hhw_fifo_status2_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_STATUS2, (uint8_t*) ®, 1);
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_STATUS2, (uint8_t *) ®, 1);
*val = reg.fifo_full_ia;
return ret;
@@ -1709,7 +1920,7 @@ int32_t lps27hhw_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lps27hhw_fifo_status2_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_STATUS2, (uint8_t*) ®, 1);
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_STATUS2, (uint8_t *) ®, 1);
*val = reg.fifo_ovr_ia;
return ret;
@@ -1728,7 +1939,7 @@ int32_t lps27hhw_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lps27hhw_fifo_status2_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_STATUS2, (uint8_t*)®, 1);
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_STATUS2, (uint8_t *)®, 1);
*val = reg.fifo_wtm_ia;
return ret;
@@ -1739,6 +1950,7 @@ int32_t lps27hhw_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param stmdev_ctx_t *ctx: read / write interface definitions
* @param uint8_t val: change the values of f_ovr in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lps27hhw_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1746,11 +1958,14 @@ int32_t lps27hhw_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
lps27hhw_ctrl_reg3_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.int_f_ovr = val;
- ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t*)®, 1);
+ ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1759,6 +1974,7 @@ int32_t lps27hhw_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param stmdev_ctx_t *ctx: read / write interface definitions
* @param uint8_t: change the values of f_ovr in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lps27hhw_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1766,7 +1982,7 @@ int32_t lps27hhw_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
lps27hhw_ctrl_reg3_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t*)®, 1);
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t *)®, 1);
*val = reg.int_f_ovr;
return ret;
@@ -1777,18 +1993,23 @@ int32_t lps27hhw_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param stmdev_ctx_t *ctx: read / write interface definitions
* @param uint8_t val: change the values of f_fth in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps27hhw_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lps27hhw_fifo_threshold_on_int_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lps27hhw_ctrl_reg3_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.int_f_wtm = val;
- ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t*)®, 1);
+ ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1797,14 +2018,16 @@ int32_t lps27hhw_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param lps22hb_ctx_t *ctx: read / write interface definitions
* @param uint8_t: change the values of f_fth in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps27hhw_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lps27hhw_fifo_threshold_on_int_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lps27hhw_ctrl_reg3_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t*)®, 1);
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t *)®, 1);
*val = reg.int_f_wtm;
return ret;
@@ -1815,6 +2038,7 @@ int32_t lps27hhw_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param stmdev_ctx_t *ctx: read / write interface definitions
* @param uint8_t val: change the values of f_fss5 in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lps27hhw_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1822,11 +2046,14 @@ int32_t lps27hhw_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
lps27hhw_ctrl_reg3_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.int_f_full = val;
- ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t*)®, 1);
+ ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1835,6 +2062,7 @@ int32_t lps27hhw_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param stmdev_ctx_t *ctx: read / write interface definitions
* @param uint8_t: change the values of f_fss5 in reg CTRL_REG3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lps27hhw_fifo_full_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1842,7 +2070,7 @@ int32_t lps27hhw_fifo_full_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
lps27hhw_ctrl_reg3_t reg;
int32_t ret;
- ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t*)®, 1);
+ ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t *)®, 1);
*val = reg.int_f_full;
return ret;
diff --git a/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.h b/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.h
index 9fad2ba252e94c138b544278ac15d589d42aeb89..1433d820c737a681e0158e2e7b77013a872e1804 100644
--- a/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.h
+++ b/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file lps27hhw_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lps27hhw_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lps27hhw_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lps27hhw_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LPS27HHW_DRIVER_H
#define LPS27HHW_DRIVER_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup LPS27HHW
@@ -74,7 +75,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -107,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -139,7 +142,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -174,7 +178,8 @@ typedef struct {
*/
#define LPS27HHW_INTERRUPT_CFG 0x0BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t pe : 2; /* ple + phe */
uint8_t lir : 1;
@@ -195,12 +200,14 @@ typedef struct {
} lps27hhw_interrupt_cfg_t;
#define LPS27HHW_THS_P_L 0x0CU
-typedef struct {
+typedef struct
+{
uint8_t ths : 8;
} lps27hhw_ths_p_l_t;
#define LPS27HHW_THS_P_H 0x0DU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t not_used_01 : 1;
@@ -211,7 +218,8 @@ typedef struct {
} lps27hhw_ths_p_h_t;
#define LPS27HHW_IF_CTRL 0x0EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t i2c_disable : 1;
uint8_t i3c_disable : 1;
@@ -233,7 +241,8 @@ typedef struct {
#define LPS27HHW_WHO_AM_I 0x0FU
#define LPS27HHW_CTRL_REG1 0x10U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t bdu : 1;
@@ -251,7 +260,8 @@ typedef struct {
} lps27hhw_ctrl_reg1_t;
#define LPS27HHW_CTRL_REG2 0x11U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t one_shot : 1;
uint8_t low_noise_en : 1;
@@ -275,7 +285,8 @@ typedef struct {
} lps27hhw_ctrl_reg2_t;
#define LPS27HHW_CTRL_REG3 0x12U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int_s : 2;
uint8_t drdy : 1;
@@ -294,20 +305,24 @@ typedef struct {
} lps27hhw_ctrl_reg3_t;
#define LPS27HHW_FIFO_CTRL 0x13U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t f_mode : 3; /* f_mode + trig_modes */
+uint8_t f_mode :
+ 3; /* f_mode + trig_modes */
uint8_t stop_on_wtm : 1;
uint8_t not_used_01 : 4;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used_01 : 4;
uint8_t stop_on_wtm : 1;
- uint8_t f_mode : 3; /* f_mode + trig_modes */
+uint8_t f_mode :
+ 3; /* f_mode + trig_modes */
#endif /* DRV_BYTE_ORDER */
} lps27hhw_fifo_ctrl_t;
#define LPS27HHW_FIFO_WTM 0x14U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wtm : 7;
uint8_t not_used_01 : 1;
@@ -322,7 +337,8 @@ typedef struct {
#define LPS27HHW_RPDS_L 0x18U
#define LPS27HHW_RPDS_H 0x19U
#define LPS27HHW_INT_SOURCE 0x24U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ph : 1;
uint8_t pl : 1;
@@ -340,7 +356,8 @@ typedef struct {
#define LPS27HHW_FIFO_STATUS1 0x25U
#define LPS27HHW_FIFO_STATUS2 0x26U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 5;
uint8_t fifo_full_ia : 1;
@@ -355,7 +372,8 @@ typedef struct {
} lps27hhw_fifo_status2_t;
#define LPS27HHW_STATUS 0x27U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t p_da : 1;
uint8_t t_da : 1;
@@ -386,9 +404,9 @@ typedef struct {
/**
* @defgroup LPS27HHW_Register_Union
- * @brief This union group all the registers that has a bitfield
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -396,7 +414,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
lps27hhw_interrupt_cfg_t interrupt_cfg;
lps27hhw_if_ctrl_t if_ctrl;
lps27hhw_ctrl_reg1_t ctrl_reg1;
@@ -416,12 +435,15 @@ typedef union{
*
*/
-int32_t lps27hhw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
- uint16_t len);
-int32_t lps27hhw_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lps27hhw_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
+int32_t lps27hhw_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len);
float_t lps27hhw_from_lsb_to_hpa(int32_t lsb);
+
float_t lps27hhw_from_lsb_to_celsius(int16_t lsb);
int32_t lps27hhw_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val);
@@ -430,16 +452,21 @@ int32_t lps27hhw_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps27hhw_autozero_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps27hhw_autozero_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lps27hhw_pressure_snap_rst_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lps27hhw_pressure_snap_rst_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps27hhw_pressure_snap_rst_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lps27hhw_pressure_snap_rst_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lps27hhw_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps27hhw_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lps27hhw_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lps27hhw_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps27hhw_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lps27hhw_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LPS27HHW_POWER_DOWN = 0x00,
LPS27HHW_ONE_SHOOT = 0x08,
LPS27HHW_1_Hz = 0x01,
@@ -456,7 +483,8 @@ typedef enum {
LPS27HHW_200_Hz = 0x07,
} lps27hhw_odr_t;
int32_t lps27hhw_data_rate_set(stmdev_ctx_t *ctx, lps27hhw_odr_t val);
-int32_t lps27hhw_data_rate_get(stmdev_ctx_t *ctx, lps27hhw_odr_t *val);
+int32_t lps27hhw_data_rate_get(stmdev_ctx_t *ctx,
+ lps27hhw_odr_t *val);
int32_t lps27hhw_pressure_ref_set(stmdev_ctx_t *ctx, int16_t val);
int32_t lps27hhw_pressure_ref_get(stmdev_ctx_t *ctx, int16_t *val);
@@ -464,27 +492,34 @@ int32_t lps27hhw_pressure_ref_get(stmdev_ctx_t *ctx, int16_t *val);
int32_t lps27hhw_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val);
int32_t lps27hhw_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val);
-typedef struct{
+typedef struct
+{
lps27hhw_int_source_t int_source;
lps27hhw_fifo_status2_t fifo_status2;
lps27hhw_status_t status;
} lps27hhw_all_sources_t;
int32_t lps27hhw_all_sources_get(stmdev_ctx_t *ctx,
- lps27hhw_all_sources_t *val);
+ lps27hhw_all_sources_t *val);
-int32_t lps27hhw_status_reg_get(stmdev_ctx_t *ctx, lps27hhw_status_t *val);
+int32_t lps27hhw_status_reg_get(stmdev_ctx_t *ctx,
+ lps27hhw_status_t *val);
-int32_t lps27hhw_press_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps27hhw_press_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lps27hhw_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps27hhw_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lps27hhw_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff);
-int32_t lps27hhw_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff);
+int32_t lps27hhw_temperature_raw_get(stmdev_ctx_t *ctx,
+ int16_t *buff);
-int32_t lps27hhw_fifo_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff);
+int32_t lps27hhw_fifo_pressure_raw_get(stmdev_ctx_t *ctx,
+ uint32_t *buff);
-int32_t lps27hhw_fifo_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff);
+int32_t lps27hhw_fifo_temperature_raw_get(stmdev_ctx_t *ctx,
+ int16_t *buff);
int32_t lps27hhw_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
@@ -497,88 +532,112 @@ int32_t lps27hhw_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps27hhw_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps27hhw_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LPS27HHW_LPF_ODR_DIV_2 = 0,
LPS27HHW_LPF_ODR_DIV_9 = 2,
LPS27HHW_LPF_ODR_DIV_20 = 3,
} lps27hhw_lpfp_cfg_t;
-int32_t lps27hhw_lp_bandwidth_set(stmdev_ctx_t *ctx, lps27hhw_lpfp_cfg_t val);
-int32_t lps27hhw_lp_bandwidth_get(stmdev_ctx_t *ctx, lps27hhw_lpfp_cfg_t *val);
+int32_t lps27hhw_lp_bandwidth_set(stmdev_ctx_t *ctx,
+ lps27hhw_lpfp_cfg_t val);
+int32_t lps27hhw_lp_bandwidth_get(stmdev_ctx_t *ctx,
+ lps27hhw_lpfp_cfg_t *val);
-typedef enum {
+typedef enum
+{
LPS27HHW_I2C_ENABLE = 0,
LPS27HHW_I2C_DISABLE = 1,
} lps27hhw_i2c_disable_t;
int32_t lps27hhw_i2c_interface_set(stmdev_ctx_t *ctx,
- lps27hhw_i2c_disable_t val);
+ lps27hhw_i2c_disable_t val);
int32_t lps27hhw_i2c_interface_get(stmdev_ctx_t *ctx,
- lps27hhw_i2c_disable_t *val);
+ lps27hhw_i2c_disable_t *val);
-typedef enum {
+typedef enum
+{
LPS27HHW_I3C_ENABLE = 0x00,
LPS27HHW_I3C_ENABLE_INT_PIN_ENABLE = 0x10,
LPS27HHW_I3C_DISABLE = 0x11,
} lps27hhw_i3c_disable_t;
int32_t lps27hhw_i3c_interface_set(stmdev_ctx_t *ctx,
- lps27hhw_i3c_disable_t val);
+ lps27hhw_i3c_disable_t val);
int32_t lps27hhw_i3c_interface_get(stmdev_ctx_t *ctx,
- lps27hhw_i3c_disable_t *val);
+ lps27hhw_i3c_disable_t *val);
-typedef enum {
+typedef enum
+{
LPS27HHW_PULL_UP_DISCONNECT = 0,
LPS27HHW_PULL_UP_CONNECT = 1,
} lps27hhw_pu_en_t;
-int32_t lps27hhw_sdo_sa0_mode_set(stmdev_ctx_t *ctx, lps27hhw_pu_en_t val);
-int32_t lps27hhw_sdo_sa0_mode_get(stmdev_ctx_t *ctx, lps27hhw_pu_en_t *val);
-int32_t lps27hhw_sda_mode_set(stmdev_ctx_t *ctx, lps27hhw_pu_en_t val);
-int32_t lps27hhw_sda_mode_get(stmdev_ctx_t *ctx, lps27hhw_pu_en_t *val);
-
-typedef enum {
+int32_t lps27hhw_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
+ lps27hhw_pu_en_t val);
+int32_t lps27hhw_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
+ lps27hhw_pu_en_t *val);
+int32_t lps27hhw_sda_mode_set(stmdev_ctx_t *ctx,
+ lps27hhw_pu_en_t val);
+int32_t lps27hhw_sda_mode_get(stmdev_ctx_t *ctx,
+ lps27hhw_pu_en_t *val);
+
+typedef enum
+{
LPS27HHW_SPI_4_WIRE = 0,
LPS27HHW_SPI_3_WIRE = 1,
} lps27hhw_sim_t;
int32_t lps27hhw_spi_mode_set(stmdev_ctx_t *ctx, lps27hhw_sim_t val);
int32_t lps27hhw_spi_mode_get(stmdev_ctx_t *ctx, lps27hhw_sim_t *val);
-typedef enum {
+typedef enum
+{
LPS27HHW_INT_PULSED = 0,
LPS27HHW_INT_LATCHED = 1,
} lps27hhw_lir_t;
-int32_t lps27hhw_int_notification_set(stmdev_ctx_t *ctx, lps27hhw_lir_t val);
-int32_t lps27hhw_int_notification_get(stmdev_ctx_t *ctx, lps27hhw_lir_t *val);
+int32_t lps27hhw_int_notification_set(stmdev_ctx_t *ctx,
+ lps27hhw_lir_t val);
+int32_t lps27hhw_int_notification_get(stmdev_ctx_t *ctx,
+ lps27hhw_lir_t *val);
-typedef enum {
+typedef enum
+{
LPS27HHW_PUSH_PULL = 0,
LPS27HHW_OPEN_DRAIN = 1,
} lps27hhw_pp_od_t;
-int32_t lps27hhw_pin_mode_set(stmdev_ctx_t *ctx, lps27hhw_pp_od_t val);
-int32_t lps27hhw_pin_mode_get(stmdev_ctx_t *ctx, lps27hhw_pp_od_t *val);
+int32_t lps27hhw_pin_mode_set(stmdev_ctx_t *ctx,
+ lps27hhw_pp_od_t val);
+int32_t lps27hhw_pin_mode_get(stmdev_ctx_t *ctx,
+ lps27hhw_pp_od_t *val);
-typedef enum {
+typedef enum
+{
LPS27HHW_ACTIVE_HIGH = 0,
LPS27HHW_ACTIVE_LOW = 1,
} lps27hhw_int_h_l_t;
-int32_t lps27hhw_pin_polarity_set(stmdev_ctx_t *ctx, lps27hhw_int_h_l_t val);
-int32_t lps27hhw_pin_polarity_get(stmdev_ctx_t *ctx, lps27hhw_int_h_l_t *val);
+int32_t lps27hhw_pin_polarity_set(stmdev_ctx_t *ctx,
+ lps27hhw_int_h_l_t val);
+int32_t lps27hhw_pin_polarity_get(stmdev_ctx_t *ctx,
+ lps27hhw_int_h_l_t *val);
int32_t lps27hhw_pin_int_route_set(stmdev_ctx_t *ctx,
- lps27hhw_ctrl_reg3_t *val);
+ lps27hhw_ctrl_reg3_t *val);
int32_t lps27hhw_pin_int_route_get(stmdev_ctx_t *ctx,
- lps27hhw_ctrl_reg3_t *val);
+ lps27hhw_ctrl_reg3_t *val);
-typedef enum {
+typedef enum
+{
LPS27HHW_NO_THRESHOLD = 0,
LPS27HHW_POSITIVE = 1,
LPS27HHW_NEGATIVE = 2,
LPS27HHW_BOTH = 3,
} lps27hhw_pe_t;
-int32_t lps27hhw_int_on_threshold_set(stmdev_ctx_t *ctx, lps27hhw_pe_t val);
-int32_t lps27hhw_int_on_threshold_get(stmdev_ctx_t *ctx, lps27hhw_pe_t *val);
+int32_t lps27hhw_int_on_threshold_set(stmdev_ctx_t *ctx,
+ lps27hhw_pe_t val);
+int32_t lps27hhw_int_on_threshold_get(stmdev_ctx_t *ctx,
+ lps27hhw_pe_t *val);
int32_t lps27hhw_int_treshold_set(stmdev_ctx_t *ctx, uint16_t buff);
int32_t lps27hhw_int_treshold_get(stmdev_ctx_t *ctx, uint16_t *buff);
-typedef enum {
+typedef enum
+{
LPS27HHW_BYPASS_MODE = 0,
LPS27HHW_FIFO_MODE = 1,
LPS27HHW_STREAM_MODE = 2,
@@ -587,18 +646,23 @@ typedef enum {
LPS27HHW_BYPASS_TO_STREAM_MODE = 6,
LPS27HHW_STREAM_TO_FIFO_MODE = 7,
} lps27hhw_f_mode_t;
-int32_t lps27hhw_fifo_mode_set(stmdev_ctx_t *ctx, lps27hhw_f_mode_t val);
-int32_t lps27hhw_fifo_mode_get(stmdev_ctx_t *ctx, lps27hhw_f_mode_t *val);
+int32_t lps27hhw_fifo_mode_set(stmdev_ctx_t *ctx,
+ lps27hhw_f_mode_t val);
+int32_t lps27hhw_fifo_mode_get(stmdev_ctx_t *ctx,
+ lps27hhw_f_mode_t *val);
int32_t lps27hhw_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lps27hhw_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps27hhw_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lps27hhw_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps27hhw_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lps27hhw_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lps27hhw_fifo_data_level_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
-int32_t lps27hhw_fifo_src_get(stmdev_ctx_t *ctx, lps27hhw_fifo_status2_t *val);
+int32_t lps27hhw_fifo_src_get(stmdev_ctx_t *ctx,
+ lps27hhw_fifo_status2_t *val);
int32_t lps27hhw_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -609,11 +673,14 @@ int32_t lps27hhw_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps27hhw_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps27hhw_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lps27hhw_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lps27hhw_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps27hhw_fifo_threshold_on_int_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lps27hhw_fifo_threshold_on_int_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lps27hhw_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lps27hhw_fifo_full_on_int_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps27hhw_fifo_full_on_int_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
/**
* @}
diff --git a/sensor/stmemsc/lps33hw_STdC/driver/lps33hw_reg.c b/sensor/stmemsc/lps33hw_STdC/driver/lps33hw_reg.c
index b612e73588d06dceb6143930b8beccbb104244c3..4f135bbcc27d02674c1914bbbbe20e7f76606c43 100644
--- a/sensor/stmemsc/lps33hw_STdC/driver/lps33hw_reg.c
+++ b/sensor/stmemsc/lps33hw_STdC/driver/lps33hw_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file lps33hw_reg.c
- * @author Sensors Software Solution Team
- * @brief LPS33HW driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lps33hw_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LPS33HW driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lps33hw_reg.h"
@@ -27,7 +27,7 @@
*
*/
-/**
+/**
* @defgroup LPS33HW_Interfaces_functions
* @brief This section provide a set of functions used to read and
* write a generic register of the device.
@@ -45,11 +45,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps33hw_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lps33hw_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -63,11 +66,14 @@ int32_t lps33hw_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps33hw_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lps33hw_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -85,12 +91,12 @@ int32_t lps33hw_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
float_t lps33hw_from_lsb_to_hpa(int32_t lsb)
{
- return ( (float_t)lsb / 4096.0f );
+ return ((float_t)lsb / 4096.0f);
}
float_t lps33hw_from_lsb_to_degc(int16_t lsb)
{
- return ( (float_t)lsb / 100.0f );
+ return ((float_t)lsb / 100.0f);
}
/**
@@ -122,17 +128,20 @@ int32_t lps33hw_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lps33hw_read_reg(ctx, LPS33HW_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
- if(ret == 0){
+ (uint8_t *)&interrupt_cfg, 1);
+
+ if (ret == 0)
+ {
interrupt_cfg.reset_az = val;
ret = lps33hw_write_reg(ctx, LPS33HW_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
}
+
return ret;
}
/**
- * @brief Reset Autozero function.[get]
+ * @brief Reset Autozero function.[get]
*
* @param ctx Read / write interface definitions
* @param val Change the values of reset_az in reg INTERRUPT_CFG
@@ -145,7 +154,7 @@ int32_t lps33hw_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lps33hw_read_reg(ctx, LPS33HW_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
*val = interrupt_cfg.reset_az;
return ret;
@@ -164,13 +173,16 @@ int32_t lps33hw_autozero_set(stmdev_ctx_t *ctx, uint8_t val)
lps33hw_interrupt_cfg_t interrupt_cfg;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
- if(ret == 0){
+ ret = lps33hw_read_reg(ctx, LPS33HW_INTERRUPT_CFG,
+ (uint8_t *)&interrupt_cfg, 1);
+
+ if (ret == 0)
+ {
interrupt_cfg.autozero = val;
ret = lps33hw_write_reg(ctx, LPS33HW_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
}
+
return ret;
}
@@ -188,14 +200,14 @@ int32_t lps33hw_autozero_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lps33hw_read_reg(ctx, LPS33HW_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
*val = interrupt_cfg.autozero;
return ret;
}
/**
- * @brief Reset AutoRifP function.[set]
+ * @brief Reset AutoRifP function.[set]
*
* @param ctx Read / write interface definitions
* @param val Change the values of reset_arp in reg INTERRUPT_CFG
@@ -208,12 +220,15 @@ int32_t lps33hw_pressure_snap_rst_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lps33hw_read_reg(ctx, LPS33HW_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
- if(ret == 0){
+ (uint8_t *)&interrupt_cfg, 1);
+
+ if (ret == 0)
+ {
interrupt_cfg.reset_arp = val;
ret = lps33hw_write_reg(ctx, LPS33HW_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
}
+
return ret;
}
@@ -231,7 +246,7 @@ int32_t lps33hw_pressure_snap_rst_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lps33hw_read_reg(ctx, LPS33HW_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
*val = interrupt_cfg.reset_arp;
return ret;
@@ -251,12 +266,15 @@ int32_t lps33hw_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lps33hw_read_reg(ctx, LPS33HW_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
- if(ret == 0){
+ (uint8_t *)&interrupt_cfg, 1);
+
+ if (ret == 0)
+ {
interrupt_cfg.autorifp = val;
ret = lps33hw_write_reg(ctx, LPS33HW_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
}
+
return ret;
}
@@ -274,7 +292,7 @@ int32_t lps33hw_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lps33hw_read_reg(ctx, LPS33HW_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
*val = interrupt_cfg.autorifp;
return ret;
@@ -293,11 +311,14 @@ int32_t lps33hw_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
lps33hw_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0){
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.bdu = val;
- ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -314,7 +335,7 @@ int32_t lps33hw_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33hw_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
*val = ctrl_reg1.bdu;
return ret;
@@ -329,21 +350,24 @@ int32_t lps33hw_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lps33hw_low_pass_filter_mode_set(stmdev_ctx_t *ctx,
- lps33hw_lpfp_t val)
+ lps33hw_lpfp_t val)
{
lps33hw_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0){
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.lpfp = (uint8_t)val;
- ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
/**
- * @brief Low-pass bandwidth selection.[get]
+ * @brief Low-pass bandwidth selection.[get]
*
* @param ctx Read / write interface definitions
* @param val Get the values of lpfp in reg CTRL_REG1
@@ -356,21 +380,27 @@ int32_t lps33hw_low_pass_filter_mode_get(stmdev_ctx_t *ctx,
lps33hw_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- switch (ctrl_reg1.lpfp){
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ switch (ctrl_reg1.lpfp)
+ {
case LPS33HW_LPF_ODR_DIV_2:
*val = LPS33HW_LPF_ODR_DIV_2;
break;
+
case LPS33HW_LPF_ODR_DIV_9:
*val = LPS33HW_LPF_ODR_DIV_9;
break;
+
case LPS33HW_LPF_ODR_DIV_20:
*val = LPS33HW_LPF_ODR_DIV_20;
break;
+
default:
*val = LPS33HW_LPF_ODR_DIV_2;
break;
}
+
return ret;
}
@@ -387,11 +417,14 @@ int32_t lps33hw_data_rate_set(stmdev_ctx_t *ctx, lps33hw_odr_t val)
lps33hw_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0){
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.odr = (uint8_t)val;
- ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -408,26 +441,34 @@ int32_t lps33hw_data_rate_get(stmdev_ctx_t *ctx, lps33hw_odr_t *val)
lps33hw_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- switch (ctrl_reg1.odr){
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ switch (ctrl_reg1.odr)
+ {
case LPS33HW_POWER_DOWN:
*val = LPS33HW_POWER_DOWN;
break;
+
case LPS33HW_ODR_1_Hz:
*val = LPS33HW_ODR_1_Hz;
break;
+
case LPS33HW_ODR_10_Hz:
*val = LPS33HW_ODR_10_Hz;
break;
+
case LPS33HW_ODR_25_Hz:
*val = LPS33HW_ODR_25_Hz;
break;
+
case LPS33HW_ODR_50_Hz:
*val = LPS33HW_ODR_50_Hz;
break;
+
case LPS33HW_ODR_75_Hz:
*val = LPS33HW_ODR_75_Hz;
break;
+
default:
*val = LPS33HW_ODR_1_Hz;
break;
@@ -437,7 +478,7 @@ int32_t lps33hw_data_rate_get(stmdev_ctx_t *ctx, lps33hw_odr_t *val)
}
/**
- * @brief One-shot mode. Device perform a single measure.[set]
+ * @brief One-shot mode. Device perform a single measure.[set]
*
* @param ctx Read / write interface definitions
* @param val Change the values of one_shot in reg CTRL_REG2
@@ -449,11 +490,14 @@ int32_t lps33hw_one_shoot_trigger_set(stmdev_ctx_t *ctx, uint8_t val)
lps33hw_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0){
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.one_shot = val;
- ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -470,7 +514,7 @@ int32_t lps33hw_one_shoot_trigger_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33hw_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
*val = ctrl_reg2.one_shot;
return ret;
@@ -486,10 +530,17 @@ int32_t lps33hw_one_shoot_trigger_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33hw_pressure_ref_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps33hw_pressure_ref_set(stmdev_ctx_t *ctx, int32_t val)
{
+ uint8_t buff[3];
int32_t ret;
+
+ buff[2] = (uint8_t)((uint32_t)val / 65536U);
+ buff[1] = (uint8_t)((uint32_t)val - (buff[2] * 65536U)) / 256U;
+ buff[0] = (uint8_t)((uint32_t)val - (buff[2] * 65536U) -
+ (buff[1] * 256U));
ret = lps33hw_write_reg(ctx, LPS33HW_REF_P_XL, buff, 3);
+
return ret;
}
@@ -503,10 +554,16 @@ int32_t lps33hw_pressure_ref_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33hw_pressure_ref_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps33hw_pressure_ref_get(stmdev_ctx_t *ctx, int32_t *val)
{
+ uint8_t buff[3];
int32_t ret;
+
ret = lps33hw_read_reg(ctx, LPS33HW_REF_P_XL, buff, 3);
+ *val = (int32_t)buff[2];
+ *val = (*val * 256) + (int32_t)buff[1];
+ *val = (*val * 256) + (int32_t)buff[0];
+
return ret;
}
@@ -519,10 +576,15 @@ int32_t lps33hw_pressure_ref_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33hw_pressure_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps33hw_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val)
{
+ uint8_t buff[2];
int32_t ret;
+
+ buff[1] = (uint8_t)((uint16_t)val / 256U);
+ buff[0] = (uint8_t)((uint16_t)val - (buff[1] * 256U));
ret = lps33hw_write_reg(ctx, LPS33HW_RPDS_L, buff, 2);
+
return ret;
}
@@ -535,10 +597,15 @@ int32_t lps33hw_pressure_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33hw_pressure_offset_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps33hw_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
+
ret = lps33hw_read_reg(ctx, LPS33HW_RPDS_L, buff, 2);
+ *val = (int16_t)buff[1];
+ *val = (*val * 256) + (int16_t)buff[0];
+
return ret;
}
@@ -555,7 +622,7 @@ int32_t lps33hw_press_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33hw_status_t status;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_STATUS, (uint8_t*)&status, 1);
+ ret = lps33hw_read_reg(ctx, LPS33HW_STATUS, (uint8_t *)&status, 1);
*val = status.p_da;
return ret;
@@ -574,7 +641,7 @@ int32_t lps33hw_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33hw_status_t status;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_STATUS, (uint8_t*)&status, 1);
+ ret = lps33hw_read_reg(ctx, LPS33HW_STATUS, (uint8_t *)&status, 1);
*val = status.t_da;
return ret;
@@ -593,7 +660,7 @@ int32_t lps33hw_press_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33hw_status_t status;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_STATUS, (uint8_t*)&status, 1);
+ ret = lps33hw_read_reg(ctx, LPS33HW_STATUS, (uint8_t *)&status, 1);
*val = status.p_or;
return ret;
@@ -612,7 +679,7 @@ int32_t lps33hw_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33hw_status_t status;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_STATUS, (uint8_t*)&status, 1);
+ ret = lps33hw_read_reg(ctx, LPS33HW_STATUS, (uint8_t *)&status, 1);
*val = status.t_or;
return ret;
@@ -626,10 +693,17 @@ int32_t lps33hw_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33hw_pressure_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps33hw_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff)
{
+ uint8_t reg[3];
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_PRESS_OUT_XL, buff, 3);
+
+ ret = lps33hw_read_reg(ctx, LPS33HW_PRESS_OUT_XL, reg, 3);
+ *buff = reg[2];
+ *buff = (*buff * 256) + reg[1];
+ *buff = (*buff * 256) + reg[0];
+ *buff *= 256;
+
return ret;
}
@@ -641,10 +715,15 @@ int32_t lps33hw_pressure_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33hw_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps33hw_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff)
{
+ uint8_t reg[2];
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_TEMP_OUT_L, (uint8_t*) buff, 2);
+
+ ret = lps33hw_read_reg(ctx, LPS33HW_TEMP_OUT_L, (uint8_t *) reg, 2);
+ *buff = reg[1];
+ *buff = (*buff * 256) + reg[0];
+
return ret;
}
@@ -662,7 +741,9 @@ int32_t lps33hw_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lps33hw_low_pass_rst_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_LPFP_RES, (uint8_t*) buff, 1);
+
+ ret = lps33hw_read_reg(ctx, LPS33HW_LPFP_RES, (uint8_t *) buff, 1);
+
return ret;
}
@@ -673,7 +754,7 @@ int32_t lps33hw_low_pass_rst_get(stmdev_ctx_t *ctx, uint8_t *buff)
/**
* @defgroup LPS33HW_common
- * @brief This section group common usefull functions
+ * @brief This section group common useful functions
* @{
*
*/
@@ -689,7 +770,9 @@ int32_t lps33hw_low_pass_rst_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lps33hw_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_WHO_AM_I, (uint8_t*) buff, 1);
+
+ ret = lps33hw_read_reg(ctx, LPS33HW_WHO_AM_I, (uint8_t *) buff, 1);
+
return ret;
}
@@ -706,11 +789,14 @@ int32_t lps33hw_reset_set(stmdev_ctx_t *ctx, uint8_t val)
lps33hw_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0){
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.swreset = val;
- ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -727,7 +813,7 @@ int32_t lps33hw_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33hw_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
*val = ctrl_reg2.swreset;
return ret;
@@ -746,11 +832,14 @@ int32_t lps33hw_boot_set(stmdev_ctx_t *ctx, uint8_t val)
lps33hw_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0){
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.boot = val;
- ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -767,7 +856,7 @@ int32_t lps33hw_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33hw_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
*val = ctrl_reg2.boot;
return ret;
@@ -786,11 +875,14 @@ int32_t lps33hw_low_power_set(stmdev_ctx_t *ctx, uint8_t val)
lps33hw_res_conf_t res_conf;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_RES_CONF, (uint8_t*)&res_conf, 1);
- if(ret == 0){
+ ret = lps33hw_read_reg(ctx, LPS33HW_RES_CONF, (uint8_t *)&res_conf, 1);
+
+ if (ret == 0)
+ {
res_conf.lc_en = val;
- ret = lps33hw_write_reg(ctx, LPS33HW_RES_CONF, (uint8_t*)&res_conf, 1);
+ ret = lps33hw_write_reg(ctx, LPS33HW_RES_CONF, (uint8_t *)&res_conf, 1);
}
+
return ret;
}
@@ -807,7 +899,7 @@ int32_t lps33hw_low_power_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33hw_res_conf_t res_conf;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_RES_CONF, (uint8_t*)&res_conf, 1);
+ ret = lps33hw_read_reg(ctx, LPS33HW_RES_CONF, (uint8_t *)&res_conf, 1);
*val = res_conf.lc_en;
return ret;
@@ -826,7 +918,8 @@ int32_t lps33hw_boot_status_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33hw_int_source_t int_source;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_INT_SOURCE, (uint8_t*)&int_source, 1);
+ ret = lps33hw_read_reg(ctx, LPS33HW_INT_SOURCE,
+ (uint8_t *)&int_source, 1);
*val = int_source.boot_status;
return ret;
@@ -840,10 +933,13 @@ int32_t lps33hw_boot_status_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33hw_dev_status_get(stmdev_ctx_t *ctx, lps33hw_dev_stat_t *val)
+int32_t lps33hw_dev_status_get(stmdev_ctx_t *ctx,
+ lps33hw_dev_stat_t *val)
{
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_FIFO_STATUS, (uint8_t*) val, 2);
+
+ ret = lps33hw_read_reg(ctx, LPS33HW_FIFO_STATUS, (uint8_t *) val, 2);
+
return ret;
}
@@ -868,18 +964,21 @@ int32_t lps33hw_dev_status_get(stmdev_ctx_t *ctx, lps33hw_dev_stat_t *val)
*
*/
int32_t lps33hw_sign_of_int_threshold_set(stmdev_ctx_t *ctx,
- lps33hw_pe_t val)
+ lps33hw_pe_t val)
{
lps33hw_interrupt_cfg_t interrupt_cfg;
int32_t ret;
ret = lps33hw_read_reg(ctx, LPS33HW_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
- if(ret == 0){
+ (uint8_t *)&interrupt_cfg, 1);
+
+ if (ret == 0)
+ {
interrupt_cfg.pe = (uint8_t)val;
ret = lps33hw_write_reg(ctx, LPS33HW_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
}
+
return ret;
}
@@ -892,30 +991,37 @@ int32_t lps33hw_sign_of_int_threshold_set(stmdev_ctx_t *ctx,
*
*/
int32_t lps33hw_sign_of_int_threshold_get(stmdev_ctx_t *ctx,
- lps33hw_pe_t *val)
+ lps33hw_pe_t *val)
{
lps33hw_interrupt_cfg_t interrupt_cfg;
int32_t ret;
ret = lps33hw_read_reg(ctx, LPS33HW_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
- switch (interrupt_cfg.pe){
+ (uint8_t *)&interrupt_cfg, 1);
+
+ switch (interrupt_cfg.pe)
+ {
case LPS33HW_NO_THRESHOLD:
*val = LPS33HW_NO_THRESHOLD;
break;
+
case LPS33HW_POSITIVE:
*val = LPS33HW_POSITIVE;
break;
+
case LPS33HW_NEGATIVE:
*val = LPS33HW_NEGATIVE;
break;
+
case LPS33HW_BOTH:
*val = LPS33HW_BOTH;
break;
+
default:
*val = LPS33HW_NO_THRESHOLD;
break;
}
+
return ret;
}
@@ -929,18 +1035,21 @@ int32_t lps33hw_sign_of_int_threshold_get(stmdev_ctx_t *ctx,
*
*/
int32_t lps33hw_int_notification_mode_set(stmdev_ctx_t *ctx,
- lps33hw_lir_t val)
+ lps33hw_lir_t val)
{
lps33hw_interrupt_cfg_t interrupt_cfg;
int32_t ret;
ret = lps33hw_read_reg(ctx, LPS33HW_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
- if(ret == 0){
+ (uint8_t *)&interrupt_cfg, 1);
+
+ if (ret == 0)
+ {
interrupt_cfg.lir = (uint8_t)val;
ret = lps33hw_write_reg(ctx, LPS33HW_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
}
+
return ret;
}
@@ -960,18 +1069,23 @@ int32_t lps33hw_int_notification_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lps33hw_read_reg(ctx, LPS33HW_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
- switch (interrupt_cfg.lir){
+ (uint8_t *)&interrupt_cfg, 1);
+
+ switch (interrupt_cfg.lir)
+ {
case LPS33HW_INT_PULSED:
*val = LPS33HW_INT_PULSED;
break;
+
case LPS33HW_INT_LATCHED:
*val = LPS33HW_INT_LATCHED;
break;
+
default:
*val = LPS33HW_INT_PULSED;
break;
}
+
return ret;
}
@@ -989,12 +1103,15 @@ int32_t lps33hw_int_generation_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lps33hw_read_reg(ctx, LPS33HW_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
- if(ret == 0){
+ (uint8_t *)&interrupt_cfg, 1);
+
+ if (ret == 0)
+ {
interrupt_cfg.diff_en = val;
ret = lps33hw_write_reg(ctx, LPS33HW_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
}
+
return ret;
}
@@ -1012,7 +1129,7 @@ int32_t lps33hw_int_generation_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lps33hw_read_reg(ctx, LPS33HW_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
*val = interrupt_cfg.diff_en;
return ret;
@@ -1026,10 +1143,15 @@ int32_t lps33hw_int_generation_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33hw_int_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps33hw_int_threshold_set(stmdev_ctx_t *ctx, uint16_t val)
{
+ uint8_t buff[2];
int32_t ret;
- ret = lps33hw_write_reg(ctx, LPS33HW_THS_P_L, (uint8_t*) buff, 2);
+
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
+ ret = lps33hw_write_reg(ctx, LPS33HW_THS_P_L, (uint8_t *) buff, 2);
+
return ret;
}
@@ -1041,10 +1163,15 @@ int32_t lps33hw_int_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33hw_int_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps33hw_int_threshold_get(stmdev_ctx_t *ctx, uint16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_THS_P_L, (uint8_t*) buff, 2);
+
+ ret = lps33hw_read_reg(ctx, LPS33HW_THS_P_L, (uint8_t *) buff, 2);
+ *val = buff[1];
+ *val = (*val * 256) + buff[0];
+
return ret;
}
@@ -1056,16 +1183,20 @@ int32_t lps33hw_int_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33hw_int_pin_mode_set(stmdev_ctx_t *ctx, lps33hw_int_s_t val)
+int32_t lps33hw_int_pin_mode_set(stmdev_ctx_t *ctx,
+ lps33hw_int_s_t val)
{
lps33hw_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0){
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.int_s = (uint8_t)val;
- ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1077,29 +1208,37 @@ int32_t lps33hw_int_pin_mode_set(stmdev_ctx_t *ctx, lps33hw_int_s_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33hw_int_pin_mode_get(stmdev_ctx_t *ctx, lps33hw_int_s_t *val)
+int32_t lps33hw_int_pin_mode_get(stmdev_ctx_t *ctx,
+ lps33hw_int_s_t *val)
{
lps33hw_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- switch (ctrl_reg3.int_s){
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ switch (ctrl_reg3.int_s)
+ {
case LPS33HW_DRDY_OR_FIFO_FLAGS:
*val = LPS33HW_DRDY_OR_FIFO_FLAGS;
break;
+
case LPS33HW_HIGH_PRES_INT:
*val = LPS33HW_HIGH_PRES_INT;
break;
+
case LPS33HW_LOW_PRES_INT:
*val = LPS33HW_LOW_PRES_INT;
break;
+
case LPS33HW_EVERY_PRES_INT:
*val = LPS33HW_EVERY_PRES_INT;
break;
+
default:
*val = LPS33HW_DRDY_OR_FIFO_FLAGS;
break;
}
+
return ret;
}
@@ -1116,11 +1255,14 @@ int32_t lps33hw_drdy_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
lps33hw_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0){
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.drdy = val;
- ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1137,7 +1279,7 @@ int32_t lps33hw_drdy_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33hw_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
*val = ctrl_reg3.drdy;
return ret;
@@ -1156,11 +1298,14 @@ int32_t lps33hw_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
lps33hw_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0){
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.f_ovr = val;
- ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1177,7 +1322,7 @@ int32_t lps33hw_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33hw_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
*val = ctrl_reg3.f_ovr;
return ret;
@@ -1191,16 +1336,20 @@ int32_t lps33hw_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33hw_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lps33hw_fifo_threshold_on_int_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lps33hw_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0){
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.f_fth = val;
- ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1212,12 +1361,13 @@ int32_t lps33hw_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33hw_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lps33hw_fifo_threshold_on_int_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lps33hw_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
*val = ctrl_reg3.f_fth;
return ret;
@@ -1236,11 +1386,14 @@ int32_t lps33hw_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
lps33hw_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0){
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.f_fss5 = val;
- ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1257,7 +1410,7 @@ int32_t lps33hw_fifo_full_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33hw_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
*val = ctrl_reg3.f_fss5;
return ret;
@@ -1276,11 +1429,14 @@ int32_t lps33hw_pin_mode_set(stmdev_ctx_t *ctx, lps33hw_pp_od_t val)
lps33hw_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0){
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.pp_od = (uint8_t)val;
- ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1297,18 +1453,23 @@ int32_t lps33hw_pin_mode_get(stmdev_ctx_t *ctx, lps33hw_pp_od_t *val)
lps33hw_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- switch (ctrl_reg3.pp_od){
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ switch (ctrl_reg3.pp_od)
+ {
case LPS33HW_PUSH_PULL:
*val = LPS33HW_PUSH_PULL;
break;
+
case LPS33HW_OPEN_DRAIN:
*val = LPS33HW_OPEN_DRAIN;
break;
+
default:
*val = LPS33HW_PUSH_PULL;
break;
}
+
return ret;
}
@@ -1320,16 +1481,20 @@ int32_t lps33hw_pin_mode_get(stmdev_ctx_t *ctx, lps33hw_pp_od_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33hw_int_polarity_set(stmdev_ctx_t *ctx, lps33hw_int_h_l_t val)
+int32_t lps33hw_int_polarity_set(stmdev_ctx_t *ctx,
+ lps33hw_int_h_l_t val)
{
lps33hw_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0){
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.int_h_l = (uint8_t)val;
- ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1341,23 +1506,29 @@ int32_t lps33hw_int_polarity_set(stmdev_ctx_t *ctx, lps33hw_int_h_l_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33hw_int_polarity_get(stmdev_ctx_t *ctx, lps33hw_int_h_l_t *val)
+int32_t lps33hw_int_polarity_get(stmdev_ctx_t *ctx,
+ lps33hw_int_h_l_t *val)
{
lps33hw_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- switch (ctrl_reg3.int_h_l){
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ switch (ctrl_reg3.int_h_l)
+ {
case LPS33HW_ACTIVE_HIGH:
*val = LPS33HW_ACTIVE_HIGH;
break;
+
case LPS33HW_ACTIVE_LOW:
*val = LPS33HW_ACTIVE_LOW;
break;
+
default:
*val = LPS33HW_ACTIVE_HIGH;
break;
}
+
return ret;
}
@@ -1369,10 +1540,13 @@ int32_t lps33hw_int_polarity_get(stmdev_ctx_t *ctx, lps33hw_int_h_l_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33hw_int_source_get(stmdev_ctx_t *ctx, lps33hw_int_source_t *val)
+int32_t lps33hw_int_source_get(stmdev_ctx_t *ctx,
+ lps33hw_int_source_t *val)
{
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_INT_SOURCE, (uint8_t*) val, 1);
+
+ ret = lps33hw_read_reg(ctx, LPS33HW_INT_SOURCE, (uint8_t *) val, 1);
+
return ret;
}
@@ -1389,7 +1563,8 @@ int32_t lps33hw_int_on_press_high_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33hw_int_source_t int_source;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_INT_SOURCE, (uint8_t*)&int_source, 1);
+ ret = lps33hw_read_reg(ctx, LPS33HW_INT_SOURCE,
+ (uint8_t *)&int_source, 1);
*val = int_source.ph;
return ret;
@@ -1408,7 +1583,8 @@ int32_t lps33hw_int_on_press_low_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33hw_int_source_t int_source;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_INT_SOURCE, (uint8_t*)&int_source, 1);
+ ret = lps33hw_read_reg(ctx, LPS33HW_INT_SOURCE,
+ (uint8_t *)&int_source, 1);
*val = int_source.pl;
return ret;
@@ -1427,7 +1603,8 @@ int32_t lps33hw_interrupt_event_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33hw_int_source_t int_source;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_INT_SOURCE, (uint8_t*)&int_source, 1);
+ ret = lps33hw_read_reg(ctx, LPS33HW_INT_SOURCE,
+ (uint8_t *)&int_source, 1);
*val = int_source.ia;
return ret;
@@ -1454,16 +1631,20 @@ int32_t lps33hw_interrupt_event_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33hw_stop_on_fifo_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lps33hw_stop_on_fifo_threshold_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lps33hw_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0){
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.stop_on_fth = val;
- ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -1475,12 +1656,13 @@ int32_t lps33hw_stop_on_fifo_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33hw_stop_on_fifo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lps33hw_stop_on_fifo_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lps33hw_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
*val = ctrl_reg2.stop_on_fth;
return ret;
@@ -1499,11 +1681,14 @@ int32_t lps33hw_fifo_set(stmdev_ctx_t *ctx, uint8_t val)
lps33hw_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0){
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.fifo_en = val;
- ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -1520,7 +1705,7 @@ int32_t lps33hw_fifo_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33hw_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
*val = ctrl_reg2.fifo_en;
return ret;
@@ -1539,11 +1724,14 @@ int32_t lps33hw_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
lps33hw_fifo_ctrl_t fifo_ctrl;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
- if(ret == 0){
+ ret = lps33hw_read_reg(ctx, LPS33HW_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl.wtm = val;
- ret = lps33hw_write_reg(ctx, LPS33HW_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
+ ret = lps33hw_write_reg(ctx, LPS33HW_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
}
+
return ret;
}
@@ -1560,7 +1748,7 @@ int32_t lps33hw_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33hw_fifo_ctrl_t fifo_ctrl;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
+ ret = lps33hw_read_reg(ctx, LPS33HW_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
*val = fifo_ctrl.wtm;
return ret;
@@ -1579,11 +1767,14 @@ int32_t lps33hw_fifo_mode_set(stmdev_ctx_t *ctx, lps33hw_f_mode_t val)
lps33hw_fifo_ctrl_t fifo_ctrl;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
- if(ret == 0){
+ ret = lps33hw_read_reg(ctx, LPS33HW_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl.f_mode = (uint8_t)val;
- ret = lps33hw_write_reg(ctx, LPS33HW_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
+ ret = lps33hw_write_reg(ctx, LPS33HW_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
}
+
return ret;
}
@@ -1595,38 +1786,49 @@ int32_t lps33hw_fifo_mode_set(stmdev_ctx_t *ctx, lps33hw_f_mode_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33hw_fifo_mode_get(stmdev_ctx_t *ctx, lps33hw_f_mode_t *val)
+int32_t lps33hw_fifo_mode_get(stmdev_ctx_t *ctx,
+ lps33hw_f_mode_t *val)
{
lps33hw_fifo_ctrl_t fifo_ctrl;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
- switch (fifo_ctrl.f_mode){
+ ret = lps33hw_read_reg(ctx, LPS33HW_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
+
+ switch (fifo_ctrl.f_mode)
+ {
case LPS33HW_BYPASS_MODE:
*val = LPS33HW_BYPASS_MODE;
break;
+
case LPS33HW_FIFO_MODE:
*val = LPS33HW_FIFO_MODE;
break;
+
case LPS33HW_STREAM_MODE:
*val = LPS33HW_STREAM_MODE;
break;
+
case LPS33HW_STREAM_TO_FIFO_MODE:
*val = LPS33HW_STREAM_TO_FIFO_MODE;
break;
+
case LPS33HW_BYPASS_TO_STREAM_MODE:
*val = LPS33HW_BYPASS_TO_STREAM_MODE;
break;
+
case LPS33HW_DYNAMIC_STREAM_MODE:
*val = LPS33HW_DYNAMIC_STREAM_MODE;
break;
+
case LPS33HW_BYPASS_TO_FIFO_MODE:
*val = LPS33HW_BYPASS_TO_FIFO_MODE;
break;
+
default:
*val = LPS33HW_BYPASS_MODE;
break;
}
+
return ret;
}
@@ -1643,7 +1845,8 @@ int32_t lps33hw_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33hw_fifo_status_t fifo_status;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_FIFO_STATUS, (uint8_t*)&fifo_status, 1);
+ ret = lps33hw_read_reg(ctx, LPS33HW_FIFO_STATUS,
+ (uint8_t *)&fifo_status, 1);
*val = fifo_status.fss;
return ret;
@@ -1662,7 +1865,8 @@ int32_t lps33hw_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33hw_fifo_status_t fifo_status;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_FIFO_STATUS, (uint8_t*)&fifo_status, 1);
+ ret = lps33hw_read_reg(ctx, LPS33HW_FIFO_STATUS,
+ (uint8_t *)&fifo_status, 1);
*val = fifo_status.ovr;
return ret;
@@ -1681,7 +1885,8 @@ int32_t lps33hw_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33hw_fifo_status_t fifo_status;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_FIFO_STATUS, (uint8_t*)&fifo_status, 1);
+ ret = lps33hw_read_reg(ctx, LPS33HW_FIFO_STATUS,
+ (uint8_t *)&fifo_status, 1);
*val = fifo_status.fth_fifo;
return ret;
@@ -1713,11 +1918,14 @@ int32_t lps33hw_spi_mode_set(stmdev_ctx_t *ctx, lps33hw_sim_t val)
lps33hw_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0){
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.sim = (uint8_t)val;
- ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -1734,18 +1942,23 @@ int32_t lps33hw_spi_mode_get(stmdev_ctx_t *ctx, lps33hw_sim_t *val)
lps33hw_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- switch (ctrl_reg1.sim){
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ switch (ctrl_reg1.sim)
+ {
case LPS33HW_SPI_4_WIRE:
*val = LPS33HW_SPI_4_WIRE;
break;
+
case LPS33HW_SPI_3_WIRE:
*val = LPS33HW_SPI_3_WIRE;
break;
+
default:
*val = LPS33HW_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -1757,16 +1970,20 @@ int32_t lps33hw_spi_mode_get(stmdev_ctx_t *ctx, lps33hw_sim_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33hw_i2c_interface_set(stmdev_ctx_t *ctx, lps33hw_i2c_dis_t val)
+int32_t lps33hw_i2c_interface_set(stmdev_ctx_t *ctx,
+ lps33hw_i2c_dis_t val)
{
lps33hw_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0){
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.i2c_dis = (uint8_t)val;
- ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -1778,23 +1995,29 @@ int32_t lps33hw_i2c_interface_set(stmdev_ctx_t *ctx, lps33hw_i2c_dis_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33hw_i2c_interface_get(stmdev_ctx_t *ctx, lps33hw_i2c_dis_t *val)
+int32_t lps33hw_i2c_interface_get(stmdev_ctx_t *ctx,
+ lps33hw_i2c_dis_t *val)
{
lps33hw_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- switch (ctrl_reg2.i2c_dis){
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ switch (ctrl_reg2.i2c_dis)
+ {
case LPS33HW_I2C_ENABLE:
*val = LPS33HW_I2C_ENABLE;
break;
+
case LPS33HW_I2C_DISABLE:
*val = LPS33HW_I2C_DISABLE;
break;
+
default:
*val = LPS33HW_I2C_ENABLE;
break;
}
+
return ret;
}
@@ -1812,11 +2035,14 @@ int32_t lps33hw_auto_add_inc_set(stmdev_ctx_t *ctx, uint8_t val)
lps33hw_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0){
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.if_add_inc = val;
- ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -1834,7 +2060,7 @@ int32_t lps33hw_auto_add_inc_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33hw_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
*val = ctrl_reg2.if_add_inc;
return ret;
diff --git a/sensor/stmemsc/lps33hw_STdC/driver/lps33hw_reg.h b/sensor/stmemsc/lps33hw_STdC/driver/lps33hw_reg.h
index b53d45f25250e332f723f114851387a1ef5eab63..993ff9a0962de7c3000e0d8eef418f1c4421f346 100644
--- a/sensor/stmemsc/lps33hw_STdC/driver/lps33hw_reg.h
+++ b/sensor/stmemsc/lps33hw_STdC/driver/lps33hw_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file lps33hw_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lps33hw_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lps33hw_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lps33hw_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LPS33HW_REGS_H
#define LPS33HW_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup LPS33HW
@@ -35,6 +36,37 @@
*
*/
+/** @defgroup Endianness definitions
+ * @{
+ *
+ */
+
+#ifndef DRV_BYTE_ORDER
+#ifndef __BYTE_ORDER__
+
+#define DRV_LITTLE_ENDIAN 1234
+#define DRV_BIG_ENDIAN 4321
+
+/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
+ * by uncommenting the define which fits your platform endianness
+ */
+//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
+#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
+
+#else /* defined __BYTE_ORDER__ */
+
+#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
+#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
+#define DRV_BYTE_ORDER __BYTE_ORDER__
+
+#endif /* __BYTE_ORDER__*/
+#endif /* DRV_BYTE_ORDER */
+
+/**
+ * @}
+ *
+ */
+
/** @defgroup STMicroelectronics sensors common types
* @{
*
@@ -43,7 +75,9 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -52,6 +86,16 @@ typedef struct{
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BIG_ENDIAN */
} bitwise_t;
#define PROPERTY_DISABLE (0U)
@@ -65,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -89,15 +134,16 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
- * Unico / Unicleo tools available on STMicroelectronics
- * web site.
+ * You can create a sensor configuration by your own or using
+ * Unico / Unicleo tools available on STMicroelectronics
+ * web site.
*
* @{
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -115,12 +161,12 @@ typedef struct {
*/
-/** @defgroup LSM9DS1_Infos
+/** @defgroup LPS33HW_Infos
* @{
*
*/
- /** I2C Device Address 8 bit format: if SA0=0 -> 0xB9 if SA0=1 -> 0xBB **/
+/** I2C Device Address 8 bit format: if SA0=0 -> 0xB9 if SA0=1 -> 0xBB **/
#define LPS33HW_I2C_ADD_H 0xBBU
#define LPS33HW_I2C_ADD_L 0xB9U
@@ -133,7 +179,9 @@ typedef struct {
*/
#define LPS33HW_INTERRUPT_CFG 0x0BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t pe : 2; /* ple + phe -> pe */
uint8_t lir : 1;
uint8_t diff_en : 1;
@@ -141,22 +189,42 @@ typedef struct {
uint8_t autozero : 1;
uint8_t reset_arp : 1;
uint8_t autorifp : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t autorifp : 1;
+ uint8_t reset_arp : 1;
+ uint8_t autozero : 1;
+ uint8_t reset_az : 1;
+ uint8_t diff_en : 1;
+ uint8_t lir : 1;
+ uint8_t pe : 2; /* ple + phe -> pe */
+#endif /* DRV_BIG_ENDIAN */
} lps33hw_interrupt_cfg_t;
#define LPS33HW_THS_P_L 0x0CU
#define LPS33HW_THS_P_H 0x0DU
#define LPS33HW_WHO_AM_I 0x0FU
#define LPS33HW_CTRL_REG1 0x10U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t bdu : 1;
uint8_t lpfp : 2; /* en_lpfp + lpfp_cfg -> lpfp */
uint8_t odr : 3;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t odr : 3;
+ uint8_t lpfp : 2; /* en_lpfp + lpfp_cfg -> lpfp */
+ uint8_t bdu : 1;
+ uint8_t sim : 1;
+#endif /* DRV_BIG_ENDIAN */
} lps33hw_ctrl_reg1_t;
#define LPS33HW_CTRL_REG2 0x11U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t one_shot : 1;
uint8_t not_used_01 : 1;
uint8_t swreset : 1;
@@ -165,10 +233,22 @@ typedef struct {
uint8_t stop_on_fth : 1;
uint8_t fifo_en : 1;
uint8_t boot : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t boot : 1;
+ uint8_t fifo_en : 1;
+ uint8_t stop_on_fth : 1;
+ uint8_t if_add_inc : 1;
+ uint8_t i2c_dis : 1;
+ uint8_t swreset : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t one_shot : 1;
+#endif /* DRV_BIG_ENDIAN */
} lps33hw_ctrl_reg2_t;
#define LPS33HW_CTRL_REG3 0x12U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int_s : 2;
uint8_t drdy : 1;
uint8_t f_ovr : 1;
@@ -176,13 +256,28 @@ typedef struct {
uint8_t f_fss5 : 1;
uint8_t pp_od : 1;
uint8_t int_h_l : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int_h_l : 1;
+ uint8_t pp_od : 1;
+ uint8_t f_fss5 : 1;
+ uint8_t f_fth : 1;
+ uint8_t f_ovr : 1;
+ uint8_t drdy : 1;
+ uint8_t int_s : 2;
+#endif /* DRV_BIG_ENDIAN */
} lps33hw_ctrl_reg3_t;
#define LPS33HW_FIFO_CTRL 0x14U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wtm : 5;
uint8_t f_mode : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t f_mode : 3;
+ uint8_t wtm : 5;
+#endif /* DRV_BIG_ENDIAN */
} lps33hw_fifo_ctrl_t;
#define LPS33HW_REF_P_XL 0x15U
@@ -192,35 +287,67 @@ typedef struct {
#define LPS33HW_RPDS_H 0x19U
#define LPS33HW_RES_CONF 0x1AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lc_en : 1;
uint8_t not_used_01 : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 7;
+ uint8_t lc_en : 1;
+#endif /* DRV_BIG_ENDIAN */
} lps33hw_res_conf_t;
#define LPS33HW_INT_SOURCE 0x25U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ph : 1;
uint8_t pl : 1;
uint8_t ia : 1;
uint8_t not_used_01 : 4;
uint8_t boot_status : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t boot_status : 1;
+ uint8_t not_used_01 : 4;
+ uint8_t ia : 1;
+ uint8_t pl : 1;
+ uint8_t ph : 1;
+#endif /* DRV_BIG_ENDIAN */
} lps33hw_int_source_t;
#define LPS33HW_FIFO_STATUS 0x26U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fss : 6;
uint8_t ovr : 1;
uint8_t fth_fifo : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fth_fifo : 1;
+ uint8_t ovr : 1;
+ uint8_t fss : 6;
+#endif /* DRV_BIG_ENDIAN */
} lps33hw_fifo_status_t;
#define LPS33HW_STATUS 0x27U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t p_da : 1;
uint8_t t_da : 1;
uint8_t not_used_02 : 2;
uint8_t p_or : 1;
uint8_t t_or : 1;
uint8_t not_used_01 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 2;
+ uint8_t t_or : 1;
+ uint8_t p_or : 1;
+ uint8_t not_used_02 : 2;
+ uint8_t t_da : 1;
+ uint8_t p_da : 1;
+#endif /* DRV_BIG_ENDIAN */
} lps33hw_status_t;
#define LPS33HW_PRESS_OUT_XL 0x28U
@@ -232,9 +359,9 @@ typedef struct {
/**
* @defgroup LPS33HW_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -243,7 +370,8 @@ typedef struct {
*
*/
-typedef union{
+typedef union
+{
lps33hw_interrupt_cfg_t interrupt_cfg;
lps33hw_ctrl_reg1_t ctrl_reg1;
lps33hw_ctrl_reg2_t ctrl_reg2;
@@ -262,13 +390,16 @@ typedef union{
*
*/
-int32_t lps33hw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lps33hw_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t lps33hw_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lps33hw_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-extern float_t lps33hw_from_lsb_to_hpa(int32_t lsb);
-extern float_t lps33hw_from_lsb_to_degc(int16_t lsb);
+float_t lps33hw_from_lsb_to_hpa(int32_t lsb);
+
+float_t lps33hw_from_lsb_to_degc(int16_t lsb);
int32_t lps33hw_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps33hw_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -277,15 +408,18 @@ int32_t lps33hw_autozero_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps33hw_autozero_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps33hw_pressure_snap_rst_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lps33hw_pressure_snap_rst_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps33hw_pressure_snap_rst_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lps33hw_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps33hw_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps33hw_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lps33hw_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps33hw_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LPS33HW_LPF_ODR_DIV_2 = 0,
LPS33HW_LPF_ODR_DIV_9 = 2,
LPS33HW_LPF_ODR_DIV_20 = 3,
@@ -295,7 +429,8 @@ int32_t lps33hw_low_pass_filter_mode_set(stmdev_ctx_t *ctx,
int32_t lps33hw_low_pass_filter_mode_get(stmdev_ctx_t *ctx,
lps33hw_lpfp_t *val);
-typedef enum {
+typedef enum
+{
LPS33HW_POWER_DOWN = 0,
LPS33HW_ODR_1_Hz = 1,
LPS33HW_ODR_10_Hz = 2,
@@ -307,13 +442,14 @@ int32_t lps33hw_data_rate_set(stmdev_ctx_t *ctx, lps33hw_odr_t val);
int32_t lps33hw_data_rate_get(stmdev_ctx_t *ctx, lps33hw_odr_t *val);
int32_t lps33hw_one_shoot_trigger_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lps33hw_one_shoot_trigger_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps33hw_one_shoot_trigger_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lps33hw_pressure_ref_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lps33hw_pressure_ref_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lps33hw_pressure_ref_set(stmdev_ctx_t *ctx, int32_t val);
+int32_t lps33hw_pressure_ref_get(stmdev_ctx_t *ctx, int32_t *val);
-int32_t lps33hw_pressure_offset_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lps33hw_pressure_offset_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lps33hw_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val);
+int32_t lps33hw_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val);
int32_t lps33hw_press_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -323,9 +459,9 @@ int32_t lps33hw_press_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps33hw_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lps33hw_pressure_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lps33hw_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff);
-int32_t lps33hw_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lps33hw_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff);
int32_t lps33hw_low_pass_rst_get(stmdev_ctx_t *ctx, uint8_t *buff);
@@ -342,13 +478,16 @@ int32_t lps33hw_low_power_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps33hw_boot_status_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef struct{
+typedef struct
+{
lps33hw_fifo_status_t fifo_status;
lps33hw_status_t status;
} lps33hw_dev_stat_t;
-int32_t lps33hw_dev_status_get(stmdev_ctx_t *ctx, lps33hw_dev_stat_t *val);
+int32_t lps33hw_dev_status_get(stmdev_ctx_t *ctx,
+ lps33hw_dev_stat_t *val);
-typedef enum {
+typedef enum
+{
LPS33HW_NO_THRESHOLD = 0,
LPS33HW_POSITIVE = 1,
LPS33HW_NEGATIVE = 2,
@@ -359,7 +498,8 @@ int32_t lps33hw_sign_of_int_threshold_set(stmdev_ctx_t *ctx,
int32_t lps33hw_sign_of_int_threshold_get(stmdev_ctx_t *ctx,
lps33hw_pe_t *val);
-typedef enum {
+typedef enum
+{
LPS33HW_INT_PULSED = 0,
LPS33HW_INT_LATCHED = 1,
} lps33hw_lir_t;
@@ -371,17 +511,20 @@ int32_t lps33hw_int_notification_mode_get(stmdev_ctx_t *ctx,
int32_t lps33hw_int_generation_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps33hw_int_generation_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lps33hw_int_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lps33hw_int_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lps33hw_int_threshold_set(stmdev_ctx_t *ctx, uint16_t val);
+int32_t lps33hw_int_threshold_get(stmdev_ctx_t *ctx, uint16_t *val);
-typedef enum {
+typedef enum
+{
LPS33HW_DRDY_OR_FIFO_FLAGS = 0,
LPS33HW_HIGH_PRES_INT = 1,
LPS33HW_LOW_PRES_INT = 2,
LPS33HW_EVERY_PRES_INT = 3,
} lps33hw_int_s_t;
-int32_t lps33hw_int_pin_mode_set(stmdev_ctx_t *ctx, lps33hw_int_s_t val);
-int32_t lps33hw_int_pin_mode_get(stmdev_ctx_t *ctx, lps33hw_int_s_t *val);
+int32_t lps33hw_int_pin_mode_set(stmdev_ctx_t *ctx,
+ lps33hw_int_s_t val);
+int32_t lps33hw_int_pin_mode_get(stmdev_ctx_t *ctx,
+ lps33hw_int_s_t *val);
int32_t lps33hw_drdy_on_int_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps33hw_drdy_on_int_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -389,36 +532,46 @@ int32_t lps33hw_drdy_on_int_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps33hw_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps33hw_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lps33hw_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lps33hw_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps33hw_fifo_threshold_on_int_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lps33hw_fifo_threshold_on_int_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lps33hw_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps33hw_fifo_full_on_int_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LPS33HW_PUSH_PULL = 0,
LPS33HW_OPEN_DRAIN = 1,
} lps33hw_pp_od_t;
int32_t lps33hw_pin_mode_set(stmdev_ctx_t *ctx, lps33hw_pp_od_t val);
int32_t lps33hw_pin_mode_get(stmdev_ctx_t *ctx, lps33hw_pp_od_t *val);
-typedef enum {
+typedef enum
+{
LPS33HW_ACTIVE_HIGH = 0,
LPS33HW_ACTIVE_LOW = 1,
} lps33hw_int_h_l_t;
-int32_t lps33hw_int_polarity_set(stmdev_ctx_t *ctx, lps33hw_int_h_l_t val);
-int32_t lps33hw_int_polarity_get(stmdev_ctx_t *ctx, lps33hw_int_h_l_t *val);
+int32_t lps33hw_int_polarity_set(stmdev_ctx_t *ctx,
+ lps33hw_int_h_l_t val);
+int32_t lps33hw_int_polarity_get(stmdev_ctx_t *ctx,
+ lps33hw_int_h_l_t *val);
-int32_t lps33hw_int_source_get(stmdev_ctx_t *ctx, lps33hw_int_source_t *val);
+int32_t lps33hw_int_source_get(stmdev_ctx_t *ctx,
+ lps33hw_int_source_t *val);
-int32_t lps33hw_int_on_press_high_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps33hw_int_on_press_high_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lps33hw_int_on_press_low_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps33hw_interrupt_event_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lps33hw_stop_on_fifo_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lps33hw_stop_on_fifo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps33hw_stop_on_fifo_threshold_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lps33hw_stop_on_fifo_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lps33hw_fifo_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps33hw_fifo_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -426,7 +579,8 @@ int32_t lps33hw_fifo_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps33hw_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps33hw_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LPS33HW_BYPASS_MODE = 0,
LPS33HW_FIFO_MODE = 1,
LPS33HW_STREAM_MODE = 2,
@@ -435,8 +589,10 @@ typedef enum {
LPS33HW_DYNAMIC_STREAM_MODE = 6,
LPS33HW_BYPASS_TO_FIFO_MODE = 7,
} lps33hw_f_mode_t;
-int32_t lps33hw_fifo_mode_set(stmdev_ctx_t *ctx, lps33hw_f_mode_t val);
-int32_t lps33hw_fifo_mode_get(stmdev_ctx_t *ctx, lps33hw_f_mode_t *val);
+int32_t lps33hw_fifo_mode_set(stmdev_ctx_t *ctx,
+ lps33hw_f_mode_t val);
+int32_t lps33hw_fifo_mode_get(stmdev_ctx_t *ctx,
+ lps33hw_f_mode_t *val);
int32_t lps33hw_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -444,19 +600,23 @@ int32_t lps33hw_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps33hw_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LPS33HW_SPI_4_WIRE = 0,
LPS33HW_SPI_3_WIRE = 1,
} lps33hw_sim_t;
int32_t lps33hw_spi_mode_set(stmdev_ctx_t *ctx, lps33hw_sim_t val);
int32_t lps33hw_spi_mode_get(stmdev_ctx_t *ctx, lps33hw_sim_t *val);
-typedef enum {
+typedef enum
+{
LPS33HW_I2C_ENABLE = 0,
LPS33HW_I2C_DISABLE = 1,
} lps33hw_i2c_dis_t;
-int32_t lps33hw_i2c_interface_set(stmdev_ctx_t *ctx, lps33hw_i2c_dis_t val);
-int32_t lps33hw_i2c_interface_get(stmdev_ctx_t *ctx, lps33hw_i2c_dis_t *val);
+int32_t lps33hw_i2c_interface_set(stmdev_ctx_t *ctx,
+ lps33hw_i2c_dis_t val);
+int32_t lps33hw_i2c_interface_get(stmdev_ctx_t *ctx,
+ lps33hw_i2c_dis_t *val);
int32_t lps33hw_auto_add_inc_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps33hw_auto_add_inc_get(stmdev_ctx_t *ctx, uint8_t *val);
diff --git a/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.c b/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.c
index 2510d820fda18bfbc49bde8b2d8e60ef32df60fd..cf2af66f840aa5050164ff7c4e5fcbf49a4245c3 100644
--- a/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.c
+++ b/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file lps33k_reg.c
- * @author Sensors Software Solution Team
- * @brief LPS33K driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lps33k_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LPS33K driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lps33k_reg.h"
@@ -27,7 +27,7 @@
*
*/
-/**
+/**
* @defgroup LPS33K_Interfaces_functions
* @brief This section provide a set of functions used to read and
* write a generic register of the device.
@@ -45,11 +45,13 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps33k_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t lps33k_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -63,11 +65,14 @@ int32_t lps33k_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps33k_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t lps33k_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -85,12 +90,12 @@ int32_t lps33k_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
float_t lps33k_from_lsb_to_hpa(int32_t lsb)
{
- return ( (float_t)lsb / 4096.0f );
+ return ((float_t)lsb / 4096.0f);
}
float_t lps33k_from_lsb_to_degc(int16_t lsb)
{
- return ( (float_t)lsb / 100.0f );
+ return ((float_t)lsb / 100.0f);
}
/**
@@ -119,11 +124,14 @@ int32_t lps33k_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
lps33k_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0){
+ ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.bdu = val;
- ret = lps33k_write_reg(ctx, LPS33K_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lps33k_write_reg(ctx, LPS33K_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -140,7 +148,7 @@ int32_t lps33k_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33k_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
*val = ctrl_reg1.bdu;
return ret;
@@ -155,21 +163,24 @@ int32_t lps33k_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lps33k_low_pass_filter_mode_set(stmdev_ctx_t *ctx,
- lps33k_lpfp_t val)
+ lps33k_lpfp_t val)
{
lps33k_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0){
+ ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.lpfp = (uint8_t)val;
- ret = lps33k_write_reg(ctx, LPS33K_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lps33k_write_reg(ctx, LPS33K_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
/**
- * @brief Low-pass bandwidth selection.[get]
+ * @brief Low-pass bandwidth selection.[get]
*
* @param ctx Read / write interface definitions
* @param val Get the values of lpfp in reg CTRL_REG1
@@ -177,26 +188,32 @@ int32_t lps33k_low_pass_filter_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lps33k_low_pass_filter_mode_get(stmdev_ctx_t *ctx,
- lps33k_lpfp_t *val)
+ lps33k_lpfp_t *val)
{
lps33k_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- switch (ctrl_reg1.lpfp){
+ ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ switch (ctrl_reg1.lpfp)
+ {
case LPS33K_LPF_ODR_DIV_2:
*val = LPS33K_LPF_ODR_DIV_2;
break;
+
case LPS33K_LPF_ODR_DIV_9:
*val = LPS33K_LPF_ODR_DIV_9;
break;
+
case LPS33K_LPF_ODR_DIV_20:
*val = LPS33K_LPF_ODR_DIV_20;
break;
+
default:
*val = LPS33K_LPF_ODR_DIV_2;
break;
}
+
return ret;
}
@@ -213,11 +230,14 @@ int32_t lps33k_data_rate_set(stmdev_ctx_t *ctx, lps33k_odr_t val)
lps33k_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0){
+ ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.odr = (uint8_t)val;
- ret = lps33k_write_reg(ctx, LPS33K_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lps33k_write_reg(ctx, LPS33K_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -234,26 +254,34 @@ int32_t lps33k_data_rate_get(stmdev_ctx_t *ctx, lps33k_odr_t *val)
lps33k_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- switch (ctrl_reg1.odr){
+ ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ switch (ctrl_reg1.odr)
+ {
case LPS33K_POWER_DOWN:
*val = LPS33K_POWER_DOWN;
break;
+
case LPS33K_ODR_1_Hz:
*val = LPS33K_ODR_1_Hz;
break;
+
case LPS33K_ODR_10_Hz:
*val = LPS33K_ODR_10_Hz;
break;
+
case LPS33K_ODR_25_Hz:
*val = LPS33K_ODR_25_Hz;
break;
+
case LPS33K_ODR_50_Hz:
*val = LPS33K_ODR_50_Hz;
break;
+
case LPS33K_ODR_75_Hz:
*val = LPS33K_ODR_75_Hz;
break;
+
default:
*val = LPS33K_ODR_1_Hz;
break;
@@ -263,7 +291,7 @@ int32_t lps33k_data_rate_get(stmdev_ctx_t *ctx, lps33k_odr_t *val)
}
/**
- * @brief One-shot mode. Device perform a single measure.[set]
+ * @brief One-shot mode. Device perform a single measure.[set]
*
* @param ctx Read / write interface definitions
* @param val Change the values of one_shot in reg CTRL_REG2
@@ -275,11 +303,14 @@ int32_t lps33k_one_shoot_trigger_set(stmdev_ctx_t *ctx, uint8_t val)
lps33k_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0){
+ ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.one_shot = val;
- ret = lps33k_write_reg(ctx, LPS33K_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33k_write_reg(ctx, LPS33K_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -296,7 +327,7 @@ int32_t lps33k_one_shoot_trigger_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33k_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
*val = ctrl_reg2.one_shot;
return ret;
@@ -311,10 +342,15 @@ int32_t lps33k_one_shoot_trigger_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33k_pressure_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps33k_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val)
{
+ uint8_t buff[2];
int32_t ret;
+
+ buff[1] = (uint8_t)((uint16_t)val / 256U);
+ buff[0] = (uint8_t)((uint16_t)val - (buff[1] * 256U));
ret = lps33k_write_reg(ctx, LPS33K_RPDS_L, buff, 2);
+
return ret;
}
@@ -327,10 +363,15 @@ int32_t lps33k_pressure_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33k_pressure_offset_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps33k_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
+
ret = lps33k_read_reg(ctx, LPS33K_RPDS_L, buff, 2);
+ *val = (int16_t)buff[1];
+ *val = (*val * 256) + (int16_t)buff[0];
+
return ret;
}
@@ -347,7 +388,7 @@ int32_t lps33k_press_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33k_status_t status;
int32_t ret;
- ret = lps33k_read_reg(ctx, LPS33K_STATUS, (uint8_t*)&status, 1);
+ ret = lps33k_read_reg(ctx, LPS33K_STATUS, (uint8_t *)&status, 1);
*val = status.p_da;
return ret;
@@ -366,7 +407,7 @@ int32_t lps33k_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33k_status_t status;
int32_t ret;
- ret = lps33k_read_reg(ctx, LPS33K_STATUS, (uint8_t*)&status, 1);
+ ret = lps33k_read_reg(ctx, LPS33K_STATUS, (uint8_t *)&status, 1);
*val = status.t_da;
return ret;
@@ -385,7 +426,7 @@ int32_t lps33k_press_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33k_status_t status;
int32_t ret;
- ret = lps33k_read_reg(ctx, LPS33K_STATUS, (uint8_t*)&status, 1);
+ ret = lps33k_read_reg(ctx, LPS33K_STATUS, (uint8_t *)&status, 1);
*val = status.p_or;
return ret;
@@ -404,7 +445,7 @@ int32_t lps33k_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33k_status_t status;
int32_t ret;
- ret = lps33k_read_reg(ctx, LPS33K_STATUS, (uint8_t*)&status, 1);
+ ret = lps33k_read_reg(ctx, LPS33K_STATUS, (uint8_t *)&status, 1);
*val = status.t_or;
return ret;
@@ -418,10 +459,17 @@ int32_t lps33k_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33k_pressure_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps33k_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff)
{
+ uint8_t reg[3];
int32_t ret;
- ret = lps33k_read_reg(ctx, LPS33K_PRESS_OUT_XL, buff, 3);
+
+ ret = lps33k_read_reg(ctx, LPS33K_PRESS_OUT_XL, reg, 3);
+ *buff = reg[2];
+ *buff = (*buff * 256) + reg[1];
+ *buff = (*buff * 256) + reg[0];
+ *buff *= 256;
+
return ret;
}
@@ -433,10 +481,15 @@ int32_t lps33k_pressure_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33k_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps33k_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff)
{
+ uint8_t reg[2];
int32_t ret;
- ret = lps33k_read_reg(ctx, LPS33K_TEMP_OUT_L, (uint8_t*) buff, 2);
+
+ ret = lps33k_read_reg(ctx, LPS33K_TEMP_OUT_L, (uint8_t *) reg, 2);
+ *buff = reg[1];
+ *buff = (*buff * 256) + reg[0];
+
return ret;
}
@@ -454,7 +507,9 @@ int32_t lps33k_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lps33k_low_pass_rst_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
- ret = lps33k_read_reg(ctx, LPS33K_LPFP_RES, (uint8_t*) buff, 1);
+
+ ret = lps33k_read_reg(ctx, LPS33K_LPFP_RES, (uint8_t *) buff, 1);
+
return ret;
}
@@ -465,7 +520,7 @@ int32_t lps33k_low_pass_rst_get(stmdev_ctx_t *ctx, uint8_t *buff)
/**
* @defgroup LPS33K_common
- * @brief This section group common usefull functions
+ * @brief This section group common useful functions
* @{
*
*/
@@ -481,7 +536,9 @@ int32_t lps33k_low_pass_rst_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lps33k_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
- ret = lps33k_read_reg(ctx, LPS33K_WHO_AM_I, (uint8_t*) buff, 1);
+
+ ret = lps33k_read_reg(ctx, LPS33K_WHO_AM_I, (uint8_t *) buff, 1);
+
return ret;
}
@@ -498,11 +555,14 @@ int32_t lps33k_reset_set(stmdev_ctx_t *ctx, uint8_t val)
lps33k_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0){
+ ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.swreset = val;
- ret = lps33k_write_reg(ctx, LPS33K_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33k_write_reg(ctx, LPS33K_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -519,7 +579,7 @@ int32_t lps33k_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33k_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
*val = ctrl_reg2.swreset;
return ret;
@@ -538,11 +598,14 @@ int32_t lps33k_boot_set(stmdev_ctx_t *ctx, uint8_t val)
lps33k_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0){
+ ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.boot = val;
- ret = lps33k_write_reg(ctx, LPS33K_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33k_write_reg(ctx, LPS33K_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -559,7 +622,7 @@ int32_t lps33k_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33k_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
*val = ctrl_reg2.boot;
return ret;
@@ -578,11 +641,14 @@ int32_t lps33k_low_power_set(stmdev_ctx_t *ctx, uint8_t val)
lps33k_res_conf_t res_conf;
int32_t ret;
- ret = lps33k_read_reg(ctx, LPS33K_RES_CONF, (uint8_t*)&res_conf, 1);
- if(ret == 0){
+ ret = lps33k_read_reg(ctx, LPS33K_RES_CONF, (uint8_t *)&res_conf, 1);
+
+ if (ret == 0)
+ {
res_conf.lc_en = val;
- ret = lps33k_write_reg(ctx, LPS33K_RES_CONF, (uint8_t*)&res_conf, 1);
+ ret = lps33k_write_reg(ctx, LPS33K_RES_CONF, (uint8_t *)&res_conf, 1);
}
+
return ret;
}
@@ -599,7 +665,7 @@ int32_t lps33k_low_power_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33k_res_conf_t res_conf;
int32_t ret;
- ret = lps33k_read_reg(ctx, LPS33K_RES_CONF, (uint8_t*)&res_conf, 1);
+ ret = lps33k_read_reg(ctx, LPS33K_RES_CONF, (uint8_t *)&res_conf, 1);
*val = res_conf.lc_en;
return ret;
@@ -632,11 +698,14 @@ int32_t lps33k_auto_add_inc_set(stmdev_ctx_t *ctx, uint8_t val)
lps33k_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0){
+ ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.if_add_inc = val;
- ret = lps33k_write_reg(ctx, LPS33K_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33k_write_reg(ctx, LPS33K_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -654,7 +723,7 @@ int32_t lps33k_auto_add_inc_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33k_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
*val = ctrl_reg2.if_add_inc;
return ret;
diff --git a/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.h b/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.h
index 6c3f0c0569e669edd347a4ce194b2cc099bd5071..c569658fb57024f54ddb4cd6410ba2c818c35ac8 100644
--- a/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.h
+++ b/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file lps33k_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lps33k_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lps33k_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lps33k_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LPS33K_REGS_H
#define LPS33K_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup LPS33K
@@ -35,6 +36,37 @@
*
*/
+/** @defgroup Endianness definitions
+ * @{
+ *
+ */
+
+#ifndef DRV_BYTE_ORDER
+#ifndef __BYTE_ORDER__
+
+#define DRV_LITTLE_ENDIAN 1234
+#define DRV_BIG_ENDIAN 4321
+
+/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
+ * by uncommenting the define which fits your platform endianness
+ */
+//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
+#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
+
+#else /* defined __BYTE_ORDER__ */
+
+#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
+#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
+#define DRV_BYTE_ORDER __BYTE_ORDER__
+
+#endif /* __BYTE_ORDER__*/
+#endif /* DRV_BYTE_ORDER */
+
+/**
+ * @}
+ *
+ */
+
/** @defgroup STMicroelectronics sensors common types
* @{
*
@@ -43,7 +75,9 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -52,6 +86,16 @@ typedef struct{
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} bitwise_t;
#define PROPERTY_DISABLE (0U)
@@ -65,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -89,15 +134,16 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
- * Unico / Unicleo tools available on STMicroelectronics
- * web site.
+ * You can create a sensor configuration by your own or using
+ * Unico / Unicleo tools available on STMicroelectronics
+ * web site.
*
* @{
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -115,12 +161,12 @@ typedef struct {
*/
-/** @defgroup LSM9DS1_Infos
+/** @defgroup LPS22HB_Infos
* @{
*
*/
- /** I2C Device Address 8 bit format. **/
+/** I2C Device Address 8 bit format. **/
#define LPS33K_I2C_ADD 0xBBU
/** Device Identification (Who am I) **/
@@ -133,16 +179,27 @@ typedef struct {
#define LPS33K_WHO_AM_I 0x0FU
#define LPS33K_CTRL_REG1 0x10U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t bdu : 1;
uint8_t lpfp : 2; /* en_lpfp + lpfp_cfg -> lpfp */
uint8_t odr : 3;
uint8_t not_used_02 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 1;
+ uint8_t odr : 3;
+ uint8_t lpfp : 2; /* en_lpfp + lpfp_cfg -> lpfp */
+ uint8_t bdu : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lps33k_ctrl_reg1_t;
#define LPS33K_CTRL_REG2 0x11U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t one_shot : 1;
uint8_t not_used_01 : 1;
uint8_t swreset : 1;
@@ -150,25 +207,50 @@ typedef struct {
uint8_t if_add_inc : 1;
uint8_t not_used_03 : 2;
uint8_t boot : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t boot : 1;
+ uint8_t not_used_03 : 2;
+ uint8_t if_add_inc : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t swreset : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t one_shot : 1;
+#endif /* DRV_BYTE_ORDER */
} lps33k_ctrl_reg2_t;
#define LPS33K_RPDS_L 0x18U
#define LPS33K_RPDS_H 0x19U
#define LPS33K_RES_CONF 0x1AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lc_en : 1;
uint8_t not_used_01 : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 7;
+ uint8_t lc_en : 1;
+#endif /* DRV_BYTE_ORDER */
} lps33k_res_conf_t;
#define LPS33K_STATUS 0x27U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t p_da : 1;
uint8_t t_da : 1;
uint8_t not_used_02 : 2;
uint8_t p_or : 1;
uint8_t t_or : 1;
uint8_t not_used_01 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 2;
+ uint8_t t_or : 1;
+ uint8_t p_or : 1;
+ uint8_t not_used_02 : 2;
+ uint8_t t_da : 1;
+ uint8_t p_da : 1;
+#endif /* DRV_BYTE_ORDER */
} lps33k_status_t;
#define LPS33K_PRESS_OUT_XL 0x28U
@@ -180,9 +262,9 @@ typedef struct {
/**
* @defgroup LPS33K_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -191,7 +273,8 @@ typedef struct {
*
*/
-typedef union{
+typedef union
+{
lps33k_ctrl_reg1_t ctrl_reg1;
lps33k_ctrl_reg2_t ctrl_reg2;
lps33k_res_conf_t res_conf;
@@ -205,28 +288,32 @@ typedef union{
*
*/
-int32_t lps33k_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lps33k_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
+ uint16_t len);
+int32_t lps33k_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t lps33k_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
- uint16_t len);
-extern float_t lps33k_from_lsb_to_hpa(int32_t lsb);
-extern float_t lps33k_from_lsb_to_degc(int16_t lsb);
+float_t lps33k_from_lsb_to_hpa(int32_t lsb);
+
+float_t lps33k_from_lsb_to_degc(int16_t lsb);
int32_t lps33k_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps33k_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LPS33K_LPF_ODR_DIV_2 = 0,
LPS33K_LPF_ODR_DIV_9 = 2,
LPS33K_LPF_ODR_DIV_20 = 3,
} lps33k_lpfp_t;
int32_t lps33k_low_pass_filter_mode_set(stmdev_ctx_t *ctx,
- lps33k_lpfp_t val);
+ lps33k_lpfp_t val);
int32_t lps33k_low_pass_filter_mode_get(stmdev_ctx_t *ctx,
- lps33k_lpfp_t *val);
+ lps33k_lpfp_t *val);
-typedef enum {
+typedef enum
+{
LPS33K_POWER_DOWN = 0,
LPS33K_ODR_1_Hz = 1,
LPS33K_ODR_10_Hz = 2,
@@ -240,8 +327,8 @@ int32_t lps33k_data_rate_get(stmdev_ctx_t *ctx, lps33k_odr_t *val);
int32_t lps33k_one_shoot_trigger_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps33k_one_shoot_trigger_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lps33k_pressure_offset_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lps33k_pressure_offset_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lps33k_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val);
+int32_t lps33k_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val);
int32_t lps33k_press_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -251,9 +338,9 @@ int32_t lps33k_press_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps33k_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lps33k_pressure_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lps33k_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff);
-int32_t lps33k_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lps33k_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff);
int32_t lps33k_low_pass_rst_get(stmdev_ctx_t *ctx, uint8_t *buff);
diff --git a/sensor/stmemsc/lps33w_STdC/driver/lps33w_reg.c b/sensor/stmemsc/lps33w_STdC/driver/lps33w_reg.c
index 85166abf69f305bc69691083c8c0292836f77d0d..400e6a623e9bbebcd18ee027885699414b06ffc2 100644
--- a/sensor/stmemsc/lps33w_STdC/driver/lps33w_reg.c
+++ b/sensor/stmemsc/lps33w_STdC/driver/lps33w_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file lps33w_reg.c
- * @author Sensors Software Solution Team
- * @brief LPS33W driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lps33w_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LPS33W driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lps33w_reg.h"
@@ -27,7 +27,7 @@
*
*/
-/**
+/**
* @defgroup LPS33W_Interfaces_functions
* @brief This section provide a set of functions used to read and
* write a generic register of the device.
@@ -45,11 +45,13 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps33w_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lps33w_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -63,11 +65,14 @@ int32_t lps33w_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lps33w_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lps33w_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -85,12 +90,12 @@ int32_t lps33w_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
float_t lps33w_from_lsb_to_hpa(uint32_t lsb)
{
- return ( (float_t)lsb / 4096.0f );
+ return ((float_t)lsb / 4096.0f);
}
float_t lps33w_from_lsb_to_degc(int16_t lsb)
{
- return ( (float_t)lsb / 100.0f );
+ return ((float_t)lsb / 100.0f);
}
/**
@@ -121,17 +126,20 @@ int32_t lps33w_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lps33w_read_reg(ctx, LPS33W_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
- if(ret == 0){
+ (uint8_t *)&interrupt_cfg, 1);
+
+ if (ret == 0)
+ {
interrupt_cfg.reset_az = val;
ret = lps33w_write_reg(ctx, LPS33W_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
}
+
return ret;
}
/**
- * @brief Reset Autozero function.[get]
+ * @brief Reset Autozero function.[get]
*
* @param ctx Read / write interface definitions
* @param val Change the values of reset_az in reg INTERRUPT_CFG
@@ -144,7 +152,7 @@ int32_t lps33w_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lps33w_read_reg(ctx, LPS33W_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
*val = interrupt_cfg.reset_az;
return ret;
@@ -163,13 +171,16 @@ int32_t lps33w_autozero_set(stmdev_ctx_t *ctx, uint8_t val)
lps33w_interrupt_cfg_t interrupt_cfg;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
- if(ret == 0){
+ ret = lps33w_read_reg(ctx, LPS33W_INTERRUPT_CFG,
+ (uint8_t *)&interrupt_cfg, 1);
+
+ if (ret == 0)
+ {
interrupt_cfg.autozero = val;
ret = lps33w_write_reg(ctx, LPS33W_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
}
+
return ret;
}
@@ -187,14 +198,14 @@ int32_t lps33w_autozero_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lps33w_read_reg(ctx, LPS33W_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
*val = interrupt_cfg.autozero;
return ret;
}
/**
- * @brief Reset AutoRifP function.[set]
+ * @brief Reset AutoRifP function.[set]
*
* @param ctx Read / write interface definitions
* @param val Change the values of reset_arp in reg INTERRUPT_CFG
@@ -207,12 +218,15 @@ int32_t lps33w_pressure_snap_rst_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lps33w_read_reg(ctx, LPS33W_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
- if(ret == 0){
+ (uint8_t *)&interrupt_cfg, 1);
+
+ if (ret == 0)
+ {
interrupt_cfg.reset_arp = val;
ret = lps33w_write_reg(ctx, LPS33W_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
}
+
return ret;
}
@@ -230,7 +244,7 @@ int32_t lps33w_pressure_snap_rst_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lps33w_read_reg(ctx, LPS33W_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
*val = interrupt_cfg.reset_arp;
return ret;
@@ -250,12 +264,15 @@ int32_t lps33w_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lps33w_read_reg(ctx, LPS33W_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
- if(ret == 0){
+ (uint8_t *)&interrupt_cfg, 1);
+
+ if (ret == 0)
+ {
interrupt_cfg.autorifp = val;
ret = lps33w_write_reg(ctx, LPS33W_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
}
+
return ret;
}
@@ -273,7 +290,7 @@ int32_t lps33w_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lps33w_read_reg(ctx, LPS33W_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
*val = interrupt_cfg.autorifp;
return ret;
@@ -292,11 +309,14 @@ int32_t lps33w_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
lps33w_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0){
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.bdu = val;
- ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -313,7 +333,7 @@ int32_t lps33w_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33w_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
*val = ctrl_reg1.bdu;
return ret;
@@ -327,47 +347,58 @@ int32_t lps33w_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33w_low_pass_filter_mode_set(stmdev_ctx_t *ctx, lps33w_lpfp_t val)
+int32_t lps33w_low_pass_filter_mode_set(stmdev_ctx_t *ctx,
+ lps33w_lpfp_t val)
{
lps33w_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0){
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.lpfp = (uint8_t)val;
- ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
/**
- * @brief Low-pass bandwidth selection.[get]
+ * @brief Low-pass bandwidth selection.[get]
*
* @param ctx Read / write interface definitions
* @param val Get the values of lpfp in reg CTRL_REG1
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33w_low_pass_filter_mode_get(stmdev_ctx_t *ctx, lps33w_lpfp_t *val)
+int32_t lps33w_low_pass_filter_mode_get(stmdev_ctx_t *ctx,
+ lps33w_lpfp_t *val)
{
lps33w_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- switch (ctrl_reg1.lpfp){
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ switch (ctrl_reg1.lpfp)
+ {
case LPS33W_LPF_ODR_DIV_2:
*val = LPS33W_LPF_ODR_DIV_2;
break;
+
case LPS33W_LPF_ODR_DIV_9:
*val = LPS33W_LPF_ODR_DIV_9;
break;
+
case LPS33W_LPF_ODR_DIV_20:
*val = LPS33W_LPF_ODR_DIV_20;
break;
+
default:
*val = LPS33W_LPF_ODR_DIV_2;
break;
}
+
return ret;
}
@@ -384,11 +415,14 @@ int32_t lps33w_data_rate_set(stmdev_ctx_t *ctx, lps33w_odr_t val)
lps33w_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0){
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.odr = (uint8_t)val;
- ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -405,26 +439,34 @@ int32_t lps33w_data_rate_get(stmdev_ctx_t *ctx, lps33w_odr_t *val)
lps33w_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- switch (ctrl_reg1.odr){
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ switch (ctrl_reg1.odr)
+ {
case LPS33W_POWER_DOWN:
*val = LPS33W_POWER_DOWN;
break;
+
case LPS33W_ODR_1_Hz:
*val = LPS33W_ODR_1_Hz;
break;
+
case LPS33W_ODR_10_Hz:
*val = LPS33W_ODR_10_Hz;
break;
+
case LPS33W_ODR_25_Hz:
*val = LPS33W_ODR_25_Hz;
break;
+
case LPS33W_ODR_50_Hz:
*val = LPS33W_ODR_50_Hz;
break;
+
case LPS33W_ODR_75_Hz:
*val = LPS33W_ODR_75_Hz;
break;
+
default:
*val = LPS33W_ODR_1_Hz;
break;
@@ -434,7 +476,7 @@ int32_t lps33w_data_rate_get(stmdev_ctx_t *ctx, lps33w_odr_t *val)
}
/**
- * @brief One-shot mode. Device perform a single measure.[set]
+ * @brief One-shot mode. Device perform a single measure.[set]
*
* @param ctx Read / write interface definitions
* @param val Change the values of one_shot in reg CTRL_REG2
@@ -446,11 +488,14 @@ int32_t lps33w_one_shoot_trigger_set(stmdev_ctx_t *ctx, uint8_t val)
lps33w_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0){
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.one_shot = val;
- ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -467,7 +512,7 @@ int32_t lps33w_one_shoot_trigger_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33w_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
*val = ctrl_reg2.one_shot;
return ret;
@@ -483,10 +528,17 @@ int32_t lps33w_one_shoot_trigger_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33w_pressure_ref_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps33w_pressure_ref_set(stmdev_ctx_t *ctx, int32_t val)
{
+ uint8_t buff[3];
int32_t ret;
+
+ buff[2] = (uint8_t)((uint32_t)val / 65536U);
+ buff[1] = (uint8_t)((uint32_t)val - (buff[2] * 65536U)) / 256U;
+ buff[0] = (uint8_t)((uint32_t)val - (buff[2] * 65536U) -
+ (buff[1] * 256U));
ret = lps33w_write_reg(ctx, LPS33W_REF_P_XL, buff, 3);
+
return ret;
}
@@ -500,10 +552,16 @@ int32_t lps33w_pressure_ref_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33w_pressure_ref_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps33w_pressure_ref_get(stmdev_ctx_t *ctx, int32_t *val)
{
+ uint8_t buff[3];
int32_t ret;
+
ret = lps33w_read_reg(ctx, LPS33W_REF_P_XL, buff, 3);
+ *val = (int32_t)buff[2];
+ *val = (*val * 256) + (int32_t)buff[1];
+ *val = (*val * 256) + (int32_t)buff[0];
+
return ret;
}
@@ -516,10 +574,15 @@ int32_t lps33w_pressure_ref_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33w_pressure_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps33w_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val)
{
+ uint8_t buff[2];
int32_t ret;
+
+ buff[1] = (uint8_t)((uint16_t)val / 256U);
+ buff[0] = (uint8_t)((uint16_t)val - (buff[1] * 256U));
ret = lps33w_write_reg(ctx, LPS33W_RPDS_L, buff, 2);
+
return ret;
}
@@ -532,10 +595,15 @@ int32_t lps33w_pressure_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33w_pressure_offset_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps33w_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
+
ret = lps33w_read_reg(ctx, LPS33W_RPDS_L, buff, 2);
+ *val = (int16_t)buff[1];
+ *val = (*val * 256) + (int16_t)buff[0];
+
return ret;
}
@@ -552,7 +620,7 @@ int32_t lps33w_press_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33w_status_t status;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_STATUS, (uint8_t*)&status, 1);
+ ret = lps33w_read_reg(ctx, LPS33W_STATUS, (uint8_t *)&status, 1);
*val = status.p_da;
return ret;
@@ -571,7 +639,7 @@ int32_t lps33w_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33w_status_t status;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_STATUS, (uint8_t*)&status, 1);
+ ret = lps33w_read_reg(ctx, LPS33W_STATUS, (uint8_t *)&status, 1);
*val = status.t_da;
return ret;
@@ -590,7 +658,7 @@ int32_t lps33w_press_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33w_status_t status;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_STATUS, (uint8_t*)&status, 1);
+ ret = lps33w_read_reg(ctx, LPS33W_STATUS, (uint8_t *)&status, 1);
*val = status.p_or;
return ret;
@@ -609,7 +677,7 @@ int32_t lps33w_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33w_status_t status;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_STATUS, (uint8_t*)&status, 1);
+ ret = lps33w_read_reg(ctx, LPS33W_STATUS, (uint8_t *)&status, 1);
*val = status.t_or;
return ret;
@@ -623,10 +691,17 @@ int32_t lps33w_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33w_pressure_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps33w_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff)
{
+ uint8_t reg[3];
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_PRESS_OUT_XL, buff, 3);
+
+ ret = lps33w_read_reg(ctx, LPS33W_PRESS_OUT_XL, reg, 3);
+ *buff = reg[2];
+ *buff = (*buff * 256) + reg[1];
+ *buff = (*buff * 256) + reg[0];
+ *buff *= 256;
+
return ret;
}
@@ -638,10 +713,15 @@ int32_t lps33w_pressure_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33w_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps33w_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff)
{
+ uint8_t reg[2];
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_TEMP_OUT_L, (uint8_t*) buff, 2);
+
+ ret = lps33w_read_reg(ctx, LPS33W_TEMP_OUT_L, (uint8_t *) reg, 2);
+ *buff = reg[1];
+ *buff = (*buff * 256) + reg[0];
+
return ret;
}
@@ -659,7 +739,9 @@ int32_t lps33w_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lps33w_low_pass_rst_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_LPFP_RES, (uint8_t*) buff, 1);
+
+ ret = lps33w_read_reg(ctx, LPS33W_LPFP_RES, (uint8_t *) buff, 1);
+
return ret;
}
@@ -670,7 +752,7 @@ int32_t lps33w_low_pass_rst_get(stmdev_ctx_t *ctx, uint8_t *buff)
/**
* @defgroup LPS33W_common
- * @brief This section group common usefull functions
+ * @brief This section group common useful functions
* @{
*
*/
@@ -686,7 +768,9 @@ int32_t lps33w_low_pass_rst_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lps33w_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_WHO_AM_I, (uint8_t*) buff, 1);
+
+ ret = lps33w_read_reg(ctx, LPS33W_WHO_AM_I, (uint8_t *) buff, 1);
+
return ret;
}
@@ -703,11 +787,14 @@ int32_t lps33w_reset_set(stmdev_ctx_t *ctx, uint8_t val)
lps33w_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0){
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.swreset = val;
- ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -724,7 +811,7 @@ int32_t lps33w_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33w_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
*val = ctrl_reg2.swreset;
return ret;
@@ -743,11 +830,14 @@ int32_t lps33w_boot_set(stmdev_ctx_t *ctx, uint8_t val)
lps33w_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0){
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.boot = val;
- ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -764,7 +854,7 @@ int32_t lps33w_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33w_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
*val = ctrl_reg2.boot;
return ret;
@@ -783,11 +873,14 @@ int32_t lps33w_low_power_set(stmdev_ctx_t *ctx, uint8_t val)
lps33w_res_conf_t res_conf;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_RES_CONF, (uint8_t*)&res_conf, 1);
- if(ret == 0){
+ ret = lps33w_read_reg(ctx, LPS33W_RES_CONF, (uint8_t *)&res_conf, 1);
+
+ if (ret == 0)
+ {
res_conf.lc_en = val;
- ret = lps33w_write_reg(ctx, LPS33W_RES_CONF, (uint8_t*)&res_conf, 1);
+ ret = lps33w_write_reg(ctx, LPS33W_RES_CONF, (uint8_t *)&res_conf, 1);
}
+
return ret;
}
@@ -804,7 +897,7 @@ int32_t lps33w_low_power_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33w_res_conf_t res_conf;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_RES_CONF, (uint8_t*)&res_conf, 1);
+ ret = lps33w_read_reg(ctx, LPS33W_RES_CONF, (uint8_t *)&res_conf, 1);
*val = res_conf.lc_en;
return ret;
@@ -823,7 +916,7 @@ int32_t lps33w_boot_status_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33w_int_source_t int_source;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_INT_SOURCE, (uint8_t*)&int_source, 1);
+ ret = lps33w_read_reg(ctx, LPS33W_INT_SOURCE, (uint8_t *)&int_source, 1);
*val = int_source.boot_status;
return ret;
@@ -837,10 +930,13 @@ int32_t lps33w_boot_status_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33w_dev_status_get(stmdev_ctx_t *ctx, lps33w_dev_stat_t *val)
+int32_t lps33w_dev_status_get(stmdev_ctx_t *ctx,
+ lps33w_dev_stat_t *val)
{
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_FIFO_STATUS, (uint8_t*) val, 2);
+
+ ret = lps33w_read_reg(ctx, LPS33W_FIFO_STATUS, (uint8_t *) val, 2);
+
return ret;
}
@@ -864,18 +960,22 @@ int32_t lps33w_dev_status_get(stmdev_ctx_t *ctx, lps33w_dev_stat_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33w_sign_of_int_threshold_set(stmdev_ctx_t *ctx, lps33w_pe_t val)
+int32_t lps33w_sign_of_int_threshold_set(stmdev_ctx_t *ctx,
+ lps33w_pe_t val)
{
lps33w_interrupt_cfg_t interrupt_cfg;
int32_t ret;
ret = lps33w_read_reg(ctx, LPS33W_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
- if(ret == 0){
+ (uint8_t *)&interrupt_cfg, 1);
+
+ if (ret == 0)
+ {
interrupt_cfg.pe = (uint8_t)val;
ret = lps33w_write_reg(ctx, LPS33W_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
}
+
return ret;
}
@@ -887,30 +987,38 @@ int32_t lps33w_sign_of_int_threshold_set(stmdev_ctx_t *ctx, lps33w_pe_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33w_sign_of_int_threshold_get(stmdev_ctx_t *ctx, lps33w_pe_t *val)
+int32_t lps33w_sign_of_int_threshold_get(stmdev_ctx_t *ctx,
+ lps33w_pe_t *val)
{
lps33w_interrupt_cfg_t interrupt_cfg;
int32_t ret;
ret = lps33w_read_reg(ctx, LPS33W_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
- switch (interrupt_cfg.pe){
+ (uint8_t *)&interrupt_cfg, 1);
+
+ switch (interrupt_cfg.pe)
+ {
case LPS33W_NO_THRESHOLD:
*val = LPS33W_NO_THRESHOLD;
break;
+
case LPS33W_POSITIVE:
*val = LPS33W_POSITIVE;
break;
+
case LPS33W_NEGATIVE:
*val = LPS33W_NEGATIVE;
break;
+
case LPS33W_BOTH:
*val = LPS33W_BOTH;
break;
+
default:
*val = LPS33W_NO_THRESHOLD;
break;
}
+
return ret;
}
@@ -923,18 +1031,22 @@ int32_t lps33w_sign_of_int_threshold_get(stmdev_ctx_t *ctx, lps33w_pe_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33w_int_notification_mode_set(stmdev_ctx_t *ctx, lps33w_lir_t val)
+int32_t lps33w_int_notification_mode_set(stmdev_ctx_t *ctx,
+ lps33w_lir_t val)
{
lps33w_interrupt_cfg_t interrupt_cfg;
int32_t ret;
ret = lps33w_read_reg(ctx, LPS33W_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
- if(ret == 0){
+ (uint8_t *)&interrupt_cfg, 1);
+
+ if (ret == 0)
+ {
interrupt_cfg.lir = (uint8_t)val;
ret = lps33w_write_reg(ctx, LPS33W_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
}
+
return ret;
}
@@ -947,24 +1059,30 @@ int32_t lps33w_int_notification_mode_set(stmdev_ctx_t *ctx, lps33w_lir_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33w_int_notification_mode_get(stmdev_ctx_t *ctx, lps33w_lir_t *val)
+int32_t lps33w_int_notification_mode_get(stmdev_ctx_t *ctx,
+ lps33w_lir_t *val)
{
lps33w_interrupt_cfg_t interrupt_cfg;
int32_t ret;
ret = lps33w_read_reg(ctx, LPS33W_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
- switch (interrupt_cfg.lir){
+ (uint8_t *)&interrupt_cfg, 1);
+
+ switch (interrupt_cfg.lir)
+ {
case LPS33W_INT_PULSED:
*val = LPS33W_INT_PULSED;
break;
+
case LPS33W_INT_LATCHED:
*val = LPS33W_INT_LATCHED;
break;
+
default:
*val = LPS33W_INT_PULSED;
break;
}
+
return ret;
}
@@ -982,12 +1100,15 @@ int32_t lps33w_int_generation_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lps33w_read_reg(ctx, LPS33W_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
- if(ret == 0){
+ (uint8_t *)&interrupt_cfg, 1);
+
+ if (ret == 0)
+ {
interrupt_cfg.diff_en = val;
ret = lps33w_write_reg(ctx, LPS33W_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
}
+
return ret;
}
@@ -1005,7 +1126,7 @@ int32_t lps33w_int_generation_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lps33w_read_reg(ctx, LPS33W_INTERRUPT_CFG,
- (uint8_t*)&interrupt_cfg, 1);
+ (uint8_t *)&interrupt_cfg, 1);
*val = interrupt_cfg.diff_en;
return ret;
@@ -1019,10 +1140,15 @@ int32_t lps33w_int_generation_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33w_int_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps33w_int_threshold_set(stmdev_ctx_t *ctx, uint16_t val)
{
+ uint8_t buff[2];
int32_t ret;
- ret = lps33w_write_reg(ctx, LPS33W_THS_P_L, (uint8_t*) buff, 2);
+
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
+ ret = lps33w_write_reg(ctx, LPS33W_THS_P_L, (uint8_t *) buff, 2);
+
return ret;
}
@@ -1034,10 +1160,15 @@ int32_t lps33w_int_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33w_int_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lps33w_int_threshold_get(stmdev_ctx_t *ctx, uint16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_THS_P_L, (uint8_t*) buff, 2);
+
+ ret = lps33w_read_reg(ctx, LPS33W_THS_P_L, (uint8_t *) buff, 2);
+ *val = buff[1];
+ *val = (*val * 256) + buff[0];
+
return ret;
}
@@ -1054,11 +1185,14 @@ int32_t lps33w_int_pin_mode_set(stmdev_ctx_t *ctx, lps33w_int_s_t val)
lps33w_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0){
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.int_s = (uint8_t)val;
- ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1070,29 +1204,37 @@ int32_t lps33w_int_pin_mode_set(stmdev_ctx_t *ctx, lps33w_int_s_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33w_int_pin_mode_get(stmdev_ctx_t *ctx, lps33w_int_s_t *val)
+int32_t lps33w_int_pin_mode_get(stmdev_ctx_t *ctx,
+ lps33w_int_s_t *val)
{
lps33w_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- switch (ctrl_reg3.int_s){
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ switch (ctrl_reg3.int_s)
+ {
case LPS33W_DRDY_OR_FIFO_FLAGS:
*val = LPS33W_DRDY_OR_FIFO_FLAGS;
break;
+
case LPS33W_HIGH_PRES_INT:
*val = LPS33W_HIGH_PRES_INT;
break;
+
case LPS33W_LOW_PRES_INT:
*val = LPS33W_LOW_PRES_INT;
break;
+
case LPS33W_EVERY_PRES_INT:
*val = LPS33W_EVERY_PRES_INT;
break;
+
default:
*val = LPS33W_DRDY_OR_FIFO_FLAGS;
break;
}
+
return ret;
}
@@ -1109,11 +1251,14 @@ int32_t lps33w_drdy_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
lps33w_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0){
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.drdy = val;
- ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1130,7 +1275,7 @@ int32_t lps33w_drdy_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33w_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
*val = ctrl_reg3.drdy;
return ret;
@@ -1149,11 +1294,14 @@ int32_t lps33w_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
lps33w_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0){
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.f_ovr = val;
- ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1170,7 +1318,7 @@ int32_t lps33w_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33w_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
*val = ctrl_reg3.f_ovr;
return ret;
@@ -1184,16 +1332,20 @@ int32_t lps33w_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33w_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lps33w_fifo_threshold_on_int_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lps33w_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0){
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.f_fth = val;
- ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1205,12 +1357,13 @@ int32_t lps33w_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33w_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lps33w_fifo_threshold_on_int_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lps33w_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
*val = ctrl_reg3.f_fth;
return ret;
@@ -1229,11 +1382,14 @@ int32_t lps33w_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val)
lps33w_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0){
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.f_fss5 = val;
- ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1250,7 +1406,7 @@ int32_t lps33w_fifo_full_on_int_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33w_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
*val = ctrl_reg3.f_fss5;
return ret;
@@ -1269,11 +1425,14 @@ int32_t lps33w_pin_mode_set(stmdev_ctx_t *ctx, lps33w_pp_od_t val)
lps33w_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0){
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.pp_od = (uint8_t)val;
- ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1290,18 +1449,23 @@ int32_t lps33w_pin_mode_get(stmdev_ctx_t *ctx, lps33w_pp_od_t *val)
lps33w_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- switch (ctrl_reg3.pp_od){
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ switch (ctrl_reg3.pp_od)
+ {
case LPS33W_PUSH_PULL:
*val = LPS33W_PUSH_PULL;
break;
+
case LPS33W_OPEN_DRAIN:
*val = LPS33W_OPEN_DRAIN;
break;
+
default:
*val = LPS33W_PUSH_PULL;
break;
}
+
return ret;
}
@@ -1313,16 +1477,20 @@ int32_t lps33w_pin_mode_get(stmdev_ctx_t *ctx, lps33w_pp_od_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33w_int_polarity_set(stmdev_ctx_t *ctx, lps33w_int_h_l_t val)
+int32_t lps33w_int_polarity_set(stmdev_ctx_t *ctx,
+ lps33w_int_h_l_t val)
{
lps33w_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- if(ret == 0){
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3.int_h_l = (uint8_t)val;
- ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
+ ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
}
+
return ret;
}
@@ -1334,23 +1502,29 @@ int32_t lps33w_int_polarity_set(stmdev_ctx_t *ctx, lps33w_int_h_l_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33w_int_polarity_get(stmdev_ctx_t *ctx, lps33w_int_h_l_t *val)
+int32_t lps33w_int_polarity_get(stmdev_ctx_t *ctx,
+ lps33w_int_h_l_t *val)
{
lps33w_ctrl_reg3_t ctrl_reg3;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);
- switch (ctrl_reg3.int_h_l){
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
+
+ switch (ctrl_reg3.int_h_l)
+ {
case LPS33W_ACTIVE_HIGH:
*val = LPS33W_ACTIVE_HIGH;
break;
+
case LPS33W_ACTIVE_LOW:
*val = LPS33W_ACTIVE_LOW;
break;
+
default:
*val = LPS33W_ACTIVE_HIGH;
break;
}
+
return ret;
}
@@ -1362,10 +1536,13 @@ int32_t lps33w_int_polarity_get(stmdev_ctx_t *ctx, lps33w_int_h_l_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33w_int_source_get(stmdev_ctx_t *ctx, lps33w_int_source_t *val)
+int32_t lps33w_int_source_get(stmdev_ctx_t *ctx,
+ lps33w_int_source_t *val)
{
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_INT_SOURCE, (uint8_t*) val, 1);
+
+ ret = lps33w_read_reg(ctx, LPS33W_INT_SOURCE, (uint8_t *) val, 1);
+
return ret;
}
@@ -1382,7 +1559,7 @@ int32_t lps33w_int_on_press_high_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33w_int_source_t int_source;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_INT_SOURCE, (uint8_t*)&int_source, 1);
+ ret = lps33w_read_reg(ctx, LPS33W_INT_SOURCE, (uint8_t *)&int_source, 1);
*val = int_source.ph;
return ret;
@@ -1401,7 +1578,7 @@ int32_t lps33w_int_on_press_low_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33w_int_source_t int_source;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_INT_SOURCE, (uint8_t*)&int_source, 1);
+ ret = lps33w_read_reg(ctx, LPS33W_INT_SOURCE, (uint8_t *)&int_source, 1);
*val = int_source.pl;
return ret;
@@ -1420,7 +1597,7 @@ int32_t lps33w_interrupt_event_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33w_int_source_t int_source;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_INT_SOURCE, (uint8_t*)&int_source, 1);
+ ret = lps33w_read_reg(ctx, LPS33W_INT_SOURCE, (uint8_t *)&int_source, 1);
*val = int_source.ia;
return ret;
@@ -1447,16 +1624,20 @@ int32_t lps33w_interrupt_event_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33w_stop_on_fifo_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lps33w_stop_on_fifo_threshold_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lps33w_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0){
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.stop_on_fth = val;
- ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -1468,12 +1649,13 @@ int32_t lps33w_stop_on_fifo_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33w_stop_on_fifo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lps33w_stop_on_fifo_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lps33w_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
*val = ctrl_reg2.stop_on_fth;
return ret;
@@ -1492,11 +1674,14 @@ int32_t lps33w_fifo_set(stmdev_ctx_t *ctx, uint8_t val)
lps33w_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0){
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.fifo_en = val;
- ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -1513,7 +1698,7 @@ int32_t lps33w_fifo_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33w_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
*val = ctrl_reg2.fifo_en;
return ret;
@@ -1532,11 +1717,14 @@ int32_t lps33w_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
lps33w_fifo_ctrl_t fifo_ctrl;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
- if(ret == 0){
+ ret = lps33w_read_reg(ctx, LPS33W_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl.wtm = val;
- ret = lps33w_write_reg(ctx, LPS33W_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
+ ret = lps33w_write_reg(ctx, LPS33W_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
}
+
return ret;
}
@@ -1553,7 +1741,7 @@ int32_t lps33w_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33w_fifo_ctrl_t fifo_ctrl;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
+ ret = lps33w_read_reg(ctx, LPS33W_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
*val = fifo_ctrl.wtm;
return ret;
@@ -1572,11 +1760,14 @@ int32_t lps33w_fifo_mode_set(stmdev_ctx_t *ctx, lps33w_f_mode_t val)
lps33w_fifo_ctrl_t fifo_ctrl;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
- if(ret == 0){
+ ret = lps33w_read_reg(ctx, LPS33W_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl.f_mode = (uint8_t)val;
- ret = lps33w_write_reg(ctx, LPS33W_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
+ ret = lps33w_write_reg(ctx, LPS33W_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
}
+
return ret;
}
@@ -1593,33 +1784,43 @@ int32_t lps33w_fifo_mode_get(stmdev_ctx_t *ctx, lps33w_f_mode_t *val)
lps33w_fifo_ctrl_t fifo_ctrl;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
- switch (fifo_ctrl.f_mode){
+ ret = lps33w_read_reg(ctx, LPS33W_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
+
+ switch (fifo_ctrl.f_mode)
+ {
case LPS33W_BYPASS_MODE:
*val = LPS33W_BYPASS_MODE;
break;
+
case LPS33W_FIFO_MODE:
*val = LPS33W_FIFO_MODE;
break;
+
case LPS33W_STREAM_MODE:
*val = LPS33W_STREAM_MODE;
break;
+
case LPS33W_STREAM_TO_FIFO_MODE:
*val = LPS33W_STREAM_TO_FIFO_MODE;
break;
+
case LPS33W_BYPASS_TO_STREAM_MODE:
*val = LPS33W_BYPASS_TO_STREAM_MODE;
break;
+
case LPS33W_DYNAMIC_STREAM_MODE:
*val = LPS33W_DYNAMIC_STREAM_MODE;
break;
+
case LPS33W_BYPASS_TO_FIFO_MODE:
*val = LPS33W_BYPASS_TO_FIFO_MODE;
break;
+
default:
*val = LPS33W_BYPASS_MODE;
break;
}
+
return ret;
}
@@ -1636,7 +1837,8 @@ int32_t lps33w_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33w_fifo_status_t fifo_status;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_FIFO_STATUS, (uint8_t*)&fifo_status, 1);
+ ret = lps33w_read_reg(ctx, LPS33W_FIFO_STATUS,
+ (uint8_t *)&fifo_status, 1);
*val = fifo_status.fss;
return ret;
@@ -1655,7 +1857,8 @@ int32_t lps33w_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33w_fifo_status_t fifo_status;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_FIFO_STATUS, (uint8_t*)&fifo_status, 1);
+ ret = lps33w_read_reg(ctx, LPS33W_FIFO_STATUS,
+ (uint8_t *)&fifo_status, 1);
*val = fifo_status.ovr;
return ret;
@@ -1674,7 +1877,8 @@ int32_t lps33w_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33w_fifo_status_t fifo_status;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_FIFO_STATUS, (uint8_t*)&fifo_status, 1);
+ ret = lps33w_read_reg(ctx, LPS33W_FIFO_STATUS,
+ (uint8_t *)&fifo_status, 1);
*val = fifo_status.fth_fifo;
return ret;
@@ -1706,11 +1910,14 @@ int32_t lps33w_spi_mode_set(stmdev_ctx_t *ctx, lps33w_sim_t val)
lps33w_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- if(ret == 0){
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1.sim = (uint8_t)val;
- ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
+ ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
}
+
return ret;
}
@@ -1727,18 +1934,23 @@ int32_t lps33w_spi_mode_get(stmdev_ctx_t *ctx, lps33w_sim_t *val)
lps33w_ctrl_reg1_t ctrl_reg1;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
- switch (ctrl_reg1.sim){
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
+
+ switch (ctrl_reg1.sim)
+ {
case LPS33W_SPI_4_WIRE:
*val = LPS33W_SPI_4_WIRE;
break;
+
case LPS33W_SPI_3_WIRE:
*val = LPS33W_SPI_3_WIRE;
break;
+
default:
*val = LPS33W_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -1750,16 +1962,20 @@ int32_t lps33w_spi_mode_get(stmdev_ctx_t *ctx, lps33w_sim_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33w_i2c_interface_set(stmdev_ctx_t *ctx, lps33w_i2c_dis_t val)
+int32_t lps33w_i2c_interface_set(stmdev_ctx_t *ctx,
+ lps33w_i2c_dis_t val)
{
lps33w_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0){
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.i2c_dis = (uint8_t)val;
- ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -1771,23 +1987,29 @@ int32_t lps33w_i2c_interface_set(stmdev_ctx_t *ctx, lps33w_i2c_dis_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lps33w_i2c_interface_get(stmdev_ctx_t *ctx, lps33w_i2c_dis_t *val)
+int32_t lps33w_i2c_interface_get(stmdev_ctx_t *ctx,
+ lps33w_i2c_dis_t *val)
{
lps33w_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- switch (ctrl_reg2.i2c_dis){
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ switch (ctrl_reg2.i2c_dis)
+ {
case LPS33W_I2C_ENABLE:
*val = LPS33W_I2C_ENABLE;
break;
+
case LPS33W_I2C_DISABLE:
*val = LPS33W_I2C_DISABLE;
break;
+
default:
*val = LPS33W_I2C_ENABLE;
break;
}
+
return ret;
}
@@ -1805,11 +2027,14 @@ int32_t lps33w_auto_add_inc_set(stmdev_ctx_t *ctx, uint8_t val)
lps33w_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
- if(ret == 0){
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2.if_add_inc = val;
- ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
}
+
return ret;
}
@@ -1827,7 +2052,7 @@ int32_t lps33w_auto_add_inc_get(stmdev_ctx_t *ctx, uint8_t *val)
lps33w_ctrl_reg2_t ctrl_reg2;
int32_t ret;
- ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
+ ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
*val = ctrl_reg2.if_add_inc;
return ret;
diff --git a/sensor/stmemsc/lps33w_STdC/driver/lps33w_reg.h b/sensor/stmemsc/lps33w_STdC/driver/lps33w_reg.h
index be98d2d512ef46a406b6d09daed14433644aafc7..7801b5d1e55d200831078d6599f0ad35ee7915bd 100644
--- a/sensor/stmemsc/lps33w_STdC/driver/lps33w_reg.h
+++ b/sensor/stmemsc/lps33w_STdC/driver/lps33w_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file lps33w_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lps33w_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lps33w_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lps33w_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LPS33W_REGS_H
#define LPS33W_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup LPS33W
@@ -35,6 +36,37 @@
*
*/
+/** @defgroup Endianness definitions
+ * @{
+ *
+ */
+
+#ifndef DRV_BYTE_ORDER
+#ifndef __BYTE_ORDER__
+
+#define DRV_LITTLE_ENDIAN 1234
+#define DRV_BIG_ENDIAN 4321
+
+/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
+ * by uncommenting the define which fits your platform endianness
+ */
+//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
+#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
+
+#else /* defined __BYTE_ORDER__ */
+
+#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
+#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
+#define DRV_BYTE_ORDER __BYTE_ORDER__
+
+#endif /* __BYTE_ORDER__*/
+#endif /* DRV_BYTE_ORDER */
+
+/**
+ * @}
+ *
+ */
+
/** @defgroup STMicroelectronics sensors common types
* @{
*
@@ -43,7 +75,9 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -52,6 +86,16 @@ typedef struct{
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} bitwise_t;
#define PROPERTY_DISABLE (0U)
@@ -65,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -89,15 +134,16 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
- * Unico / Unicleo tools available on STMicroelectronics
- * web site.
+ * You can create a sensor configuration by your own or using
+ * Unico / Unicleo tools available on STMicroelectronics
+ * web site.
*
* @{
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -120,7 +166,7 @@ typedef struct {
*
*/
- /** I2C Device Address 8 bit format: if SA0=0 -> 0xB9 if SA0=1 -> 0xBB **/
+/** I2C Device Address 8 bit format: if SA0=0 -> 0xB9 if SA0=1 -> 0xBB **/
#define LPS33W_I2C_ADD_H 0xBBU
#define LPS33W_I2C_ADD_L 0xB9U
@@ -133,7 +179,9 @@ typedef struct {
*/
#define LPS33W_INTERRUPT_CFG 0x0BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t pe : 2; /* ple + phe -> pe */
uint8_t lir : 1;
uint8_t diff_en : 1;
@@ -141,22 +189,42 @@ typedef struct {
uint8_t autozero : 1;
uint8_t reset_arp : 1;
uint8_t autorifp : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t autorifp : 1;
+ uint8_t reset_arp : 1;
+ uint8_t autozero : 1;
+ uint8_t reset_az : 1;
+ uint8_t diff_en : 1;
+ uint8_t lir : 1;
+ uint8_t pe : 2; /* ple + phe -> pe */
+#endif /* DRV_BYTE_ORDER */
} lps33w_interrupt_cfg_t;
#define LPS33W_THS_P_L 0x0CU
#define LPS33W_THS_P_H 0x0DU
#define LPS33W_WHO_AM_I 0x0FU
#define LPS33W_CTRL_REG1 0x10U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t bdu : 1;
uint8_t lpfp : 2; /* en_lpfp + lpfp_cfg -> lpfp */
uint8_t odr : 3;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t odr : 3;
+ uint8_t lpfp : 2; /* en_lpfp + lpfp_cfg -> lpfp */
+ uint8_t bdu : 1;
+ uint8_t sim : 1;
+#endif /* DRV_BYTE_ORDER */
} lps33w_ctrl_reg1_t;
#define LPS33W_CTRL_REG2 0x11U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t one_shot : 1;
uint8_t not_used_01 : 1;
uint8_t swreset : 1;
@@ -165,10 +233,22 @@ typedef struct {
uint8_t stop_on_fth : 1;
uint8_t fifo_en : 1;
uint8_t boot : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t boot : 1;
+ uint8_t fifo_en : 1;
+ uint8_t stop_on_fth : 1;
+ uint8_t if_add_inc : 1;
+ uint8_t i2c_dis : 1;
+ uint8_t swreset : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t one_shot : 1;
+#endif /* DRV_BYTE_ORDER */
} lps33w_ctrl_reg2_t;
#define LPS33W_CTRL_REG3 0x12U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int_s : 2;
uint8_t drdy : 1;
uint8_t f_ovr : 1;
@@ -176,13 +256,28 @@ typedef struct {
uint8_t f_fss5 : 1;
uint8_t pp_od : 1;
uint8_t int_h_l : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int_h_l : 1;
+ uint8_t pp_od : 1;
+ uint8_t f_fss5 : 1;
+ uint8_t f_fth : 1;
+ uint8_t f_ovr : 1;
+ uint8_t drdy : 1;
+ uint8_t int_s : 2;
+#endif /* DRV_BYTE_ORDER */
} lps33w_ctrl_reg3_t;
#define LPS33W_FIFO_CTRL 0x14U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wtm : 5;
uint8_t f_mode : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t f_mode : 3;
+ uint8_t wtm : 5;
+#endif /* DRV_BYTE_ORDER */
} lps33w_fifo_ctrl_t;
#define LPS33W_REF_P_XL 0x15U
@@ -192,35 +287,67 @@ typedef struct {
#define LPS33W_RPDS_H 0x19U
#define LPS33W_RES_CONF 0x1AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lc_en : 1;
uint8_t not_used_01 : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 7;
+ uint8_t lc_en : 1;
+#endif /* DRV_BYTE_ORDER */
} lps33w_res_conf_t;
#define LPS33W_INT_SOURCE 0x25U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ph : 1;
uint8_t pl : 1;
uint8_t ia : 1;
uint8_t not_used_01 : 4;
uint8_t boot_status : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t boot_status : 1;
+ uint8_t not_used_01 : 4;
+ uint8_t ia : 1;
+ uint8_t pl : 1;
+ uint8_t ph : 1;
+#endif /* DRV_BYTE_ORDER */
} lps33w_int_source_t;
#define LPS33W_FIFO_STATUS 0x26U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fss : 6;
uint8_t ovr : 1;
uint8_t fth_fifo : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fth_fifo : 1;
+ uint8_t ovr : 1;
+ uint8_t fss : 6;
+#endif /* DRV_BYTE_ORDER */
} lps33w_fifo_status_t;
#define LPS33W_STATUS 0x27U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t p_da : 1;
uint8_t t_da : 1;
uint8_t not_used_02 : 2;
uint8_t p_or : 1;
uint8_t t_or : 1;
uint8_t not_used_01 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 2;
+ uint8_t t_or : 1;
+ uint8_t p_or : 1;
+ uint8_t not_used_02 : 2;
+ uint8_t t_da : 1;
+ uint8_t p_da : 1;
+#endif /* DRV_BYTE_ORDER */
} lps33w_status_t;
#define LPS33W_PRESS_OUT_XL 0x28U
@@ -232,9 +359,9 @@ typedef struct {
/**
* @defgroup LPS33W_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -243,7 +370,8 @@ typedef struct {
*
*/
-typedef union{
+typedef union
+{
lps33w_interrupt_cfg_t interrupt_cfg;
lps33w_ctrl_reg1_t ctrl_reg1;
lps33w_ctrl_reg2_t ctrl_reg2;
@@ -262,13 +390,15 @@ typedef union{
*
*/
-int32_t lps33w_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lps33w_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
+ uint16_t len);
+int32_t lps33w_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t lps33w_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
- uint16_t len);
-extern float_t lps33w_from_lsb_to_hpa(uint32_t lsb);
-extern float_t lps33w_from_lsb_to_degc(int16_t lsb);
+float_t lps33w_from_lsb_to_hpa(uint32_t lsb);
+
+float_t lps33w_from_lsb_to_degc(int16_t lsb);
int32_t lps33w_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps33w_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -285,15 +415,19 @@ int32_t lps33w_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps33w_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps33w_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LPS33W_LPF_ODR_DIV_2 = 0,
LPS33W_LPF_ODR_DIV_9 = 2,
LPS33W_LPF_ODR_DIV_20 = 3,
} lps33w_lpfp_t;
-int32_t lps33w_low_pass_filter_mode_set(stmdev_ctx_t *ctx, lps33w_lpfp_t val);
-int32_t lps33w_low_pass_filter_mode_get(stmdev_ctx_t *ctx, lps33w_lpfp_t *val);
+int32_t lps33w_low_pass_filter_mode_set(stmdev_ctx_t *ctx,
+ lps33w_lpfp_t val);
+int32_t lps33w_low_pass_filter_mode_get(stmdev_ctx_t *ctx,
+ lps33w_lpfp_t *val);
-typedef enum {
+typedef enum
+{
LPS33W_POWER_DOWN = 0,
LPS33W_ODR_1_Hz = 1,
LPS33W_ODR_10_Hz = 2,
@@ -307,11 +441,11 @@ int32_t lps33w_data_rate_get(stmdev_ctx_t *ctx, lps33w_odr_t *val);
int32_t lps33w_one_shoot_trigger_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps33w_one_shoot_trigger_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lps33w_pressure_ref_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lps33w_pressure_ref_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lps33w_pressure_ref_set(stmdev_ctx_t *ctx, int32_t val);
+int32_t lps33w_pressure_ref_get(stmdev_ctx_t *ctx, int32_t *val);
-int32_t lps33w_pressure_offset_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lps33w_pressure_offset_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lps33w_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val);
+int32_t lps33w_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val);
int32_t lps33w_press_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -321,9 +455,9 @@ int32_t lps33w_press_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps33w_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lps33w_pressure_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lps33w_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *val);
-int32_t lps33w_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lps33w_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val);
int32_t lps33w_low_pass_rst_get(stmdev_ctx_t *ctx, uint8_t *buff);
@@ -340,42 +474,53 @@ int32_t lps33w_low_power_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps33w_boot_status_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef struct{
+typedef struct
+{
lps33w_fifo_status_t fifo_status;
lps33w_status_t status;
} lps33w_dev_stat_t;
-int32_t lps33w_dev_status_get(stmdev_ctx_t *ctx, lps33w_dev_stat_t *val);
+int32_t lps33w_dev_status_get(stmdev_ctx_t *ctx,
+ lps33w_dev_stat_t *val);
-typedef enum {
+typedef enum
+{
LPS33W_NO_THRESHOLD = 0,
LPS33W_POSITIVE = 1,
LPS33W_NEGATIVE = 2,
LPS33W_BOTH = 3,
} lps33w_pe_t;
-int32_t lps33w_sign_of_int_threshold_set(stmdev_ctx_t *ctx, lps33w_pe_t val);
-int32_t lps33w_sign_of_int_threshold_get(stmdev_ctx_t *ctx, lps33w_pe_t *val);
+int32_t lps33w_sign_of_int_threshold_set(stmdev_ctx_t *ctx,
+ lps33w_pe_t val);
+int32_t lps33w_sign_of_int_threshold_get(stmdev_ctx_t *ctx,
+ lps33w_pe_t *val);
-typedef enum {
+typedef enum
+{
LPS33W_INT_PULSED = 0,
LPS33W_INT_LATCHED = 1,
} lps33w_lir_t;
-int32_t lps33w_int_notification_mode_set(stmdev_ctx_t *ctx, lps33w_lir_t val);
-int32_t lps33w_int_notification_mode_get(stmdev_ctx_t *ctx, lps33w_lir_t *val);
+int32_t lps33w_int_notification_mode_set(stmdev_ctx_t *ctx,
+ lps33w_lir_t val);
+int32_t lps33w_int_notification_mode_get(stmdev_ctx_t *ctx,
+ lps33w_lir_t *val);
int32_t lps33w_int_generation_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps33w_int_generation_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lps33w_int_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lps33w_int_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lps33w_int_threshold_set(stmdev_ctx_t *ctx, uint16_t val);
+int32_t lps33w_int_threshold_get(stmdev_ctx_t *ctx, uint16_t *val);
-typedef enum {
+typedef enum
+{
LPS33W_DRDY_OR_FIFO_FLAGS = 0,
LPS33W_HIGH_PRES_INT = 1,
LPS33W_LOW_PRES_INT = 2,
LPS33W_EVERY_PRES_INT = 3,
} lps33w_int_s_t;
-int32_t lps33w_int_pin_mode_set(stmdev_ctx_t *ctx, lps33w_int_s_t val);
-int32_t lps33w_int_pin_mode_get(stmdev_ctx_t *ctx, lps33w_int_s_t *val);
+int32_t lps33w_int_pin_mode_set(stmdev_ctx_t *ctx,
+ lps33w_int_s_t val);
+int32_t lps33w_int_pin_mode_get(stmdev_ctx_t *ctx,
+ lps33w_int_s_t *val);
int32_t lps33w_drdy_on_int_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps33w_drdy_on_int_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -383,27 +528,34 @@ int32_t lps33w_drdy_on_int_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps33w_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps33w_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lps33w_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lps33w_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps33w_fifo_threshold_on_int_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lps33w_fifo_threshold_on_int_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lps33w_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps33w_fifo_full_on_int_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LPS33W_PUSH_PULL = 0,
LPS33W_OPEN_DRAIN = 1,
} lps33w_pp_od_t;
int32_t lps33w_pin_mode_set(stmdev_ctx_t *ctx, lps33w_pp_od_t val);
int32_t lps33w_pin_mode_get(stmdev_ctx_t *ctx, lps33w_pp_od_t *val);
-typedef enum {
+typedef enum
+{
LPS33W_ACTIVE_HIGH = 0,
LPS33W_ACTIVE_LOW = 1,
} lps33w_int_h_l_t;
-int32_t lps33w_int_polarity_set(stmdev_ctx_t *ctx, lps33w_int_h_l_t val);
-int32_t lps33w_int_polarity_get(stmdev_ctx_t *ctx, lps33w_int_h_l_t *val);
+int32_t lps33w_int_polarity_set(stmdev_ctx_t *ctx,
+ lps33w_int_h_l_t val);
+int32_t lps33w_int_polarity_get(stmdev_ctx_t *ctx,
+ lps33w_int_h_l_t *val);
-int32_t lps33w_int_source_get(stmdev_ctx_t *ctx, lps33w_int_source_t *val);
+int32_t lps33w_int_source_get(stmdev_ctx_t *ctx,
+ lps33w_int_source_t *val);
int32_t lps33w_int_on_press_high_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -411,8 +563,10 @@ int32_t lps33w_int_on_press_low_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps33w_interrupt_event_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lps33w_stop_on_fifo_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lps33w_stop_on_fifo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lps33w_stop_on_fifo_threshold_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lps33w_stop_on_fifo_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lps33w_fifo_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps33w_fifo_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -420,7 +574,8 @@ int32_t lps33w_fifo_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps33w_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps33w_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LPS33W_BYPASS_MODE = 0,
LPS33W_FIFO_MODE = 1,
LPS33W_STREAM_MODE = 2,
@@ -438,19 +593,23 @@ int32_t lps33w_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lps33w_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LPS33W_SPI_4_WIRE = 0,
LPS33W_SPI_3_WIRE = 1,
} lps33w_sim_t;
int32_t lps33w_spi_mode_set(stmdev_ctx_t *ctx, lps33w_sim_t val);
int32_t lps33w_spi_mode_get(stmdev_ctx_t *ctx, lps33w_sim_t *val);
-typedef enum {
+typedef enum
+{
LPS33W_I2C_ENABLE = 0,
LPS33W_I2C_DISABLE = 1,
} lps33w_i2c_dis_t;
-int32_t lps33w_i2c_interface_set(stmdev_ctx_t *ctx, lps33w_i2c_dis_t val);
-int32_t lps33w_i2c_interface_get(stmdev_ctx_t *ctx, lps33w_i2c_dis_t *val);
+int32_t lps33w_i2c_interface_set(stmdev_ctx_t *ctx,
+ lps33w_i2c_dis_t val);
+int32_t lps33w_i2c_interface_get(stmdev_ctx_t *ctx,
+ lps33w_i2c_dis_t *val);
int32_t lps33w_auto_add_inc_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lps33w_auto_add_inc_get(stmdev_ctx_t *ctx, uint8_t *val);
diff --git a/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.c b/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.c
index 5727200f16e769efd4378404e1b3a5d1c26b29db..cf484e5f03cdd3d6fb85d51b9f961c9f84b92321 100644
--- a/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.c
+++ b/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file lsm303agr_reg.c
- * @author Sensors Software Solution Team
- * @brief LSM303AGR driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lsm303agr_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LSM303AGR driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lsm303agr_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm303agr_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t lsm303agr_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t lsm303agr_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm303agr_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t lsm303agr_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -86,77 +92,77 @@ int32_t lsm303agr_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
float_t lsm303agr_from_fs_2g_hr_to_mg(int16_t lsb)
{
- return ((float_t)lsb / 16.0f ) * 0.98f;
+ return ((float_t)lsb / 16.0f) * 0.98f;
}
float_t lsm303agr_from_fs_4g_hr_to_mg(int16_t lsb)
{
- return ((float_t)lsb / 16.0f ) * 1.95f;
+ return ((float_t)lsb / 16.0f) * 1.95f;
}
float_t lsm303agr_from_fs_8g_hr_to_mg(int16_t lsb)
{
- return ((float_t)lsb / 16.0f ) * 3.9f;
+ return ((float_t)lsb / 16.0f) * 3.9f;
}
float_t lsm303agr_from_fs_16g_hr_to_mg(int16_t lsb)
{
- return ((float_t)lsb / 16.0f ) * 11.72f;
+ return ((float_t)lsb / 16.0f) * 11.72f;
}
float_t lsm303agr_from_lsb_hr_to_celsius(int16_t lsb)
{
- return ( ( (float_t)lsb / 64.0f ) / 4.0f ) + 25.0f;
+ return (((float_t)lsb / 64.0f) / 4.0f) + 25.0f;
}
float_t lsm303agr_from_fs_2g_nm_to_mg(int16_t lsb)
{
- return ((float_t)lsb / 64.0f ) * 3.9f;
+ return ((float_t)lsb / 64.0f) * 3.9f;
}
float_t lsm303agr_from_fs_4g_nm_to_mg(int16_t lsb)
{
- return ((float_t)lsb / 64.0f ) * 7.82f;
+ return ((float_t)lsb / 64.0f) * 7.82f;
}
float_t lsm303agr_from_fs_8g_nm_to_mg(int16_t lsb)
{
- return ((float_t)lsb / 64.0f ) * 15.63f;
+ return ((float_t)lsb / 64.0f) * 15.63f;
}
float_t lsm303agr_from_fs_16g_nm_to_mg(int16_t lsb)
{
- return ((float_t)lsb / 64.0f ) * 46.9f;
+ return ((float_t)lsb / 64.0f) * 46.9f;
}
float_t lsm303agr_from_lsb_nm_to_celsius(int16_t lsb)
{
- return ( ( (float_t)lsb / 64.0f ) / 4.0f ) + 25.0f;
+ return (((float_t)lsb / 64.0f) / 4.0f) + 25.0f;
}
float_t lsm303agr_from_fs_2g_lp_to_mg(int16_t lsb)
{
- return ((float_t)lsb / 256.0f ) * 15.63f;
+ return ((float_t)lsb / 256.0f) * 15.63f;
}
float_t lsm303agr_from_fs_4g_lp_to_mg(int16_t lsb)
{
- return ((float_t)lsb / 256.0f ) * 31.26f;
+ return ((float_t)lsb / 256.0f) * 31.26f;
}
float_t lsm303agr_from_fs_8g_lp_to_mg(int16_t lsb)
{
- return ((float_t)lsb / 256.0f ) * 62.52f;
+ return ((float_t)lsb / 256.0f) * 62.52f;
}
float_t lsm303agr_from_fs_16g_lp_to_mg(int16_t lsb)
{
- return ((float_t)lsb / 256.0f ) * 187.58f;
+ return ((float_t)lsb / 256.0f) * 187.58f;
}
float_t lsm303agr_from_lsb_lp_to_celsius(int16_t lsb)
{
- return ( ( (float_t)lsb / 256.0f ) * 1.0f ) + 25.0f;
+ return (((float_t)lsb / 256.0f) * 1.0f) + 25.0f;
}
float_t lsm303agr_from_lsb_to_mgauss(int16_t lsb)
@@ -184,10 +190,13 @@ float_t lsm303agr_from_lsb_to_mgauss(int16_t lsb)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303agr_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm303agr_temp_status_reg_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
+
ret = lsm303agr_read_reg(ctx, LSM303AGR_STATUS_REG_AUX_A, buff, 1);
+
return ret;
}
@@ -205,7 +214,7 @@ int32_t lsm303agr_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_STATUS_REG_AUX_A,
- (uint8_t*)&status_reg_aux_a, 1);
+ (uint8_t *)&status_reg_aux_a, 1);
*val = status_reg_aux_a.tda;
return ret;
@@ -225,7 +234,7 @@ int32_t lsm303agr_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_STATUS_REG_AUX_A,
- (uint8_t*)&status_reg_aux_a, 1);
+ (uint8_t *)&status_reg_aux_a, 1);
*val = status_reg_aux_a.tor;
return ret;
@@ -239,10 +248,15 @@ int32_t lsm303agr_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303agr_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm303agr_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
+
ret = lsm303agr_read_reg(ctx, LSM303AGR_OUT_TEMP_L_A, buff, 2);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+
return ret;
}
@@ -261,11 +275,13 @@ int32_t lsm303agr_temperature_meas_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_TEMP_CFG_REG_A,
- (uint8_t*)&temp_cfg_reg_a, 1);
- if(ret == 0){
+ (uint8_t *)&temp_cfg_reg_a, 1);
+
+ if (ret == 0)
+ {
temp_cfg_reg_a.temp_en = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_TEMP_CFG_REG_A,
- (uint8_t*)&temp_cfg_reg_a, 1);
+ (uint8_t *)&temp_cfg_reg_a, 1);
}
return ret;
@@ -280,20 +296,24 @@ int32_t lsm303agr_temperature_meas_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm303agr_temperature_meas_get(stmdev_ctx_t *ctx,
- lsm303agr_temp_en_a_t *val)
+ lsm303agr_temp_en_a_t *val)
{
lsm303agr_temp_cfg_reg_a_t temp_cfg_reg_a;
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_TEMP_CFG_REG_A,
- (uint8_t*)&temp_cfg_reg_a, 1);
- switch (temp_cfg_reg_a.temp_en){
+ (uint8_t *)&temp_cfg_reg_a, 1);
+
+ switch (temp_cfg_reg_a.temp_en)
+ {
case LSM303AGR_TEMP_DISABLE:
*val = LSM303AGR_TEMP_DISABLE;
break;
+
case LSM303AGR_TEMP_ENABLE:
*val = LSM303AGR_TEMP_ENABLE;
break;
+
default:
*val = LSM303AGR_TEMP_DISABLE;
break;
@@ -317,34 +337,48 @@ int32_t lsm303agr_xl_operating_mode_set(stmdev_ctx_t *ctx,
lsm303agr_ctrl_reg1_a_t ctrl_reg1_a;
lsm303agr_ctrl_reg4_a_t ctrl_reg4_a;
int32_t ret;
+
uint8_t lpen, hr;
- if ( val == LSM303AGR_HR_12bit ){
+ if (val == LSM303AGR_HR_12bit)
+ {
lpen = 0;
hr = 1;
- } else if (val == LSM303AGR_NM_10bit) {
+ }
+
+ else if (val == LSM303AGR_NM_10bit)
+ {
lpen = 0;
hr = 0;
- } else {
+ }
+
+ else
+ {
lpen = 1;
hr = 0;
}
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG1_A,
- (uint8_t*)&ctrl_reg1_a, 1);
+ (uint8_t *)&ctrl_reg1_a, 1);
ctrl_reg1_a.lpen = (uint8_t)lpen;
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG1_A,
- (uint8_t*)&ctrl_reg1_a, 1);
+ (uint8_t *)&ctrl_reg1_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG4_A,
- (uint8_t*)&ctrl_reg4_a, 1);
+ (uint8_t *)&ctrl_reg4_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ctrl_reg4_a.hr = hr;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG4_A,
- (uint8_t*)&ctrl_reg4_a, 1);
+ (uint8_t *)&ctrl_reg4_a, 1);
}
return ret;
@@ -365,19 +399,28 @@ int32_t lsm303agr_xl_operating_mode_get(stmdev_ctx_t *ctx,
lsm303agr_ctrl_reg4_a_t ctrl_reg4_a;
lsm303agr_ctrl_reg1_a_t ctrl_reg1_a;
int32_t ret;
-
+
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG1_A,
- (uint8_t*)&ctrl_reg1_a, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg1_a, 1);
+
+ if (ret == 0)
+ {
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG4_A,
- (uint8_t*)&ctrl_reg4_a, 1);
+ (uint8_t *)&ctrl_reg4_a, 1);
}
- if ( ctrl_reg1_a.lpen != PROPERTY_DISABLE ){
+ if (ctrl_reg1_a.lpen != PROPERTY_DISABLE)
+ {
*val = LSM303AGR_LP_8bit;
- } else if (ctrl_reg4_a.hr != PROPERTY_DISABLE ) {
+ }
+
+ else if (ctrl_reg4_a.hr != PROPERTY_DISABLE)
+ {
*val = LSM303AGR_HR_12bit;
- } else{
+ }
+
+ else
+ {
*val = LSM303AGR_NM_10bit;
}
@@ -399,11 +442,13 @@ int32_t lsm303agr_xl_data_rate_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG1_A,
- (uint8_t*)&ctrl_reg1_a, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg1_a, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1_a.odr = (uint8_t)val;
- ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG1_A,
- (uint8_t*)&ctrl_reg1_a, 1);
+ ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG1_A,
+ (uint8_t *)&ctrl_reg1_a, 1);
}
return ret;
@@ -424,39 +469,50 @@ int32_t lsm303agr_xl_data_rate_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG1_A,
- (uint8_t*)&ctrl_reg1_a, 1);
+ (uint8_t *)&ctrl_reg1_a, 1);
- switch (ctrl_reg1_a.odr){
+ switch (ctrl_reg1_a.odr)
+ {
case LSM303AGR_XL_POWER_DOWN:
*val = LSM303AGR_XL_POWER_DOWN;
break;
+
case LSM303AGR_XL_ODR_1Hz:
*val = LSM303AGR_XL_ODR_1Hz;
break;
+
case LSM303AGR_XL_ODR_10Hz:
*val = LSM303AGR_XL_ODR_10Hz;
break;
+
case LSM303AGR_XL_ODR_25Hz:
*val = LSM303AGR_XL_ODR_25Hz;
break;
+
case LSM303AGR_XL_ODR_50Hz:
*val = LSM303AGR_XL_ODR_50Hz;
break;
+
case LSM303AGR_XL_ODR_100Hz:
*val = LSM303AGR_XL_ODR_100Hz;
break;
+
case LSM303AGR_XL_ODR_200Hz:
*val = LSM303AGR_XL_ODR_200Hz;
break;
+
case LSM303AGR_XL_ODR_400Hz:
*val = LSM303AGR_XL_ODR_400Hz;
break;
+
case LSM303AGR_XL_ODR_1kHz620_LP:
*val = LSM303AGR_XL_ODR_1kHz620_LP;
break;
+
case LSM303AGR_XL_ODR_1kHz344_NM_HP_5kHz376_LP:
*val = LSM303AGR_XL_ODR_1kHz344_NM_HP_5kHz376_LP;
break;
+
default:
*val = LSM303AGR_XL_POWER_DOWN;
break;
@@ -480,11 +536,13 @@ int32_t lsm303agr_xl_high_pass_on_outputs_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG2_A,
- (uint8_t*)&ctrl_reg2_a, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg2_a, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2_a.fds = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG2_A,
- (uint8_t*)&ctrl_reg2_a, 1);
+ (uint8_t *)&ctrl_reg2_a, 1);
}
return ret;
@@ -506,7 +564,7 @@ int32_t lsm303agr_xl_high_pass_on_outputs_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG2_A,
- (uint8_t*)&ctrl_reg2_a, 1);
+ (uint8_t *)&ctrl_reg2_a, 1);
*val = ctrl_reg2_a.fds;
return ret;
@@ -534,11 +592,13 @@ int32_t lsm303agr_xl_high_pass_bandwidth_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG2_A,
- (uint8_t*)&ctrl_reg2_a, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg2_a, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2_a.hpcf = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG2_A,
- (uint8_t*)&ctrl_reg2_a, 1);
+ (uint8_t *)&ctrl_reg2_a, 1);
}
return ret;
@@ -566,25 +626,31 @@ int32_t lsm303agr_xl_high_pass_bandwidth_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG2_A,
- (uint8_t*)&ctrl_reg2_a, 1);
+ (uint8_t *)&ctrl_reg2_a, 1);
- switch (ctrl_reg2_a.hpcf){
+ switch (ctrl_reg2_a.hpcf)
+ {
case LSM303AGR_AGGRESSIVE:
*val = LSM303AGR_AGGRESSIVE;
break;
+
case LSM303AGR_STRONG:
*val = LSM303AGR_STRONG;
break;
+
case LSM303AGR_MEDIUM:
*val = LSM303AGR_MEDIUM;
break;
+
case LSM303AGR_LIGHT:
*val = LSM303AGR_LIGHT;
break;
+
default:
*val = LSM303AGR_AGGRESSIVE;
break;
}
+
return ret;
}
@@ -603,11 +669,13 @@ int32_t lsm303agr_xl_high_pass_mode_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG2_A,
- (uint8_t*)&ctrl_reg2_a, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg2_a, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2_a.hpm = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG2_A,
- (uint8_t*)&ctrl_reg2_a, 1);
+ (uint8_t *)&ctrl_reg2_a, 1);
}
return ret;
@@ -628,25 +696,31 @@ int32_t lsm303agr_xl_high_pass_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG2_A,
- (uint8_t*)&ctrl_reg2_a, 1);
+ (uint8_t *)&ctrl_reg2_a, 1);
- switch (ctrl_reg2_a.hpm){
+ switch (ctrl_reg2_a.hpm)
+ {
case LSM303AGR_NORMAL_WITH_RST:
*val = LSM303AGR_NORMAL_WITH_RST;
break;
+
case LSM303AGR_REFERENCE_MODE:
*val = LSM303AGR_REFERENCE_MODE;
break;
+
case LSM303AGR_NORMAL:
*val = LSM303AGR_NORMAL;
break;
+
case LSM303AGR_AUTORST_ON_INT:
*val = LSM303AGR_AUTORST_ON_INT;
break;
+
default:
*val = LSM303AGR_NORMAL_WITH_RST;
break;
}
+
return ret;
}
@@ -665,11 +739,13 @@ int32_t lsm303agr_xl_full_scale_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG4_A,
- (uint8_t*)&ctrl_reg4_a, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg4_a, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4_a.fs = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG4_A,
- (uint8_t*)&ctrl_reg4_a, 1);
+ (uint8_t *)&ctrl_reg4_a, 1);
}
return ret;
@@ -690,25 +766,31 @@ int32_t lsm303agr_xl_full_scale_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG4_A,
- (uint8_t*)&ctrl_reg4_a, 1);
+ (uint8_t *)&ctrl_reg4_a, 1);
- switch (ctrl_reg4_a.fs){
+ switch (ctrl_reg4_a.fs)
+ {
case LSM303AGR_2g:
*val = LSM303AGR_2g;
break;
+
case LSM303AGR_4g:
*val = LSM303AGR_4g;
break;
+
case LSM303AGR_8g:
*val = LSM303AGR_8g;
break;
+
case LSM303AGR_16g:
*val = LSM303AGR_16g;
break;
+
default:
*val = LSM303AGR_2g;
break;
}
+
return ret;
}
@@ -727,11 +809,13 @@ int32_t lsm303agr_xl_block_data_update_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG4_A,
- (uint8_t*)&ctrl_reg4_a, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg4_a, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4_a.bdu = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG4_A,
- (uint8_t*)&ctrl_reg4_a, 1);
+ (uint8_t *)&ctrl_reg4_a, 1);
}
return ret;
@@ -752,7 +836,7 @@ int32_t lsm303agr_xl_block_data_update_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG4_A,
- (uint8_t*)&ctrl_reg4_a, 1);
+ (uint8_t *)&ctrl_reg4_a, 1);
*val = ctrl_reg4_a.bdu;
return ret;
@@ -771,7 +855,9 @@ int32_t lsm303agr_xl_filter_reference_set(stmdev_ctx_t *ctx,
uint8_t *buff)
{
int32_t ret;
+
ret = lsm303agr_write_reg(ctx, LSM303AGR_REFERENCE_A, buff, 1);
+
return ret;
}
@@ -788,7 +874,9 @@ int32_t lsm303agr_xl_filter_reference_get(stmdev_ctx_t *ctx,
uint8_t *buff)
{
int32_t ret;
+
ret = lsm303agr_read_reg(ctx, LSM303AGR_REFERENCE_A, buff, 1);
+
return ret;
}
@@ -806,7 +894,7 @@ int32_t lsm303agr_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_STATUS_REG_A,
- (uint8_t*)&status_reg_a, 1);
+ (uint8_t *)&status_reg_a, 1);
*val = status_reg_a.zyxda;
return ret;
@@ -826,7 +914,7 @@ int32_t lsm303agr_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_STATUS_REG_A,
- (uint8_t*)&status_reg_a, 1);
+ (uint8_t *)&status_reg_a, 1);
*val = status_reg_a.zyxor;
return ret;
@@ -840,10 +928,20 @@ int32_t lsm303agr_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303agr_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm303agr_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lsm303agr_read_reg(ctx, LSM303AGR_OUT_X_L_A, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -862,10 +960,19 @@ int32_t lsm303agr_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303agr_mag_user_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm303agr_mag_user_offset_set(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
+ buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
+ buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
+ buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
+ buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
+ buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
+ buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
ret = lsm303agr_write_reg(ctx, LSM303AGR_OFFSET_X_REG_L_M, buff, 6);
+
return ret;
}
@@ -884,10 +991,19 @@ int32_t lsm303agr_mag_user_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303agr_mag_user_offset_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm303agr_mag_user_offset_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lsm303agr_read_reg(ctx, LSM303AGR_OFFSET_X_REG_L_M, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -906,11 +1022,13 @@ int32_t lsm303agr_mag_operating_mode_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_a_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_a_m.md = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
+ (uint8_t *)&cfg_reg_a_m, 1);
}
return ret;
@@ -931,22 +1049,27 @@ int32_t lsm303agr_mag_operating_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
+ (uint8_t *)&cfg_reg_a_m, 1);
- switch (cfg_reg_a_m.md){
+ switch (cfg_reg_a_m.md)
+ {
case LSM303AGR_CONTINUOUS_MODE:
*val = LSM303AGR_CONTINUOUS_MODE;
break;
+
case LSM303AGR_SINGLE_TRIGGER:
*val = LSM303AGR_SINGLE_TRIGGER;
break;
+
case LSM303AGR_POWER_DOWN:
*val = LSM303AGR_POWER_DOWN;
break;
+
default:
*val = LSM303AGR_CONTINUOUS_MODE;
break;
}
+
return ret;
}
@@ -965,11 +1088,13 @@ int32_t lsm303agr_mag_data_rate_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_a_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_a_m.odr = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
+ (uint8_t *)&cfg_reg_a_m, 1);
}
return ret;
@@ -990,25 +1115,31 @@ int32_t lsm303agr_mag_data_rate_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
+ (uint8_t *)&cfg_reg_a_m, 1);
- switch (cfg_reg_a_m.odr){
+ switch (cfg_reg_a_m.odr)
+ {
case LSM303AGR_MG_ODR_10Hz:
*val = LSM303AGR_MG_ODR_10Hz;
break;
+
case LSM303AGR_MG_ODR_20Hz:
*val = LSM303AGR_MG_ODR_20Hz;
break;
+
case LSM303AGR_MG_ODR_50Hz:
*val = LSM303AGR_MG_ODR_50Hz;
break;
+
case LSM303AGR_MG_ODR_100Hz:
*val = LSM303AGR_MG_ODR_100Hz;
break;
+
default:
*val = LSM303AGR_MG_ODR_10Hz;
break;
}
+
return ret;
}
@@ -1027,11 +1158,13 @@ int32_t lsm303agr_mag_power_mode_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_a_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_a_m.lp = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
+ (uint8_t *)&cfg_reg_a_m, 1);
}
return ret;
@@ -1052,19 +1185,23 @@ int32_t lsm303agr_mag_power_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
+ (uint8_t *)&cfg_reg_a_m, 1);
- switch (cfg_reg_a_m.lp){
+ switch (cfg_reg_a_m.lp)
+ {
case LSM303AGR_HIGH_RESOLUTION:
*val = LSM303AGR_HIGH_RESOLUTION;
break;
+
case LSM303AGR_LOW_POWER:
*val = LSM303AGR_LOW_POWER;
break;
+
default:
*val = LSM303AGR_HIGH_RESOLUTION;
break;
}
+
return ret;
}
@@ -1076,17 +1213,20 @@ int32_t lsm303agr_mag_power_mode_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303agr_mag_offset_temp_comp_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm303agr_mag_offset_temp_comp_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm303agr_cfg_reg_a_m_t cfg_reg_a_m;
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_a_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_a_m.comp_temp_en = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
+ (uint8_t *)&cfg_reg_a_m, 1);
}
return ret;
@@ -1100,13 +1240,14 @@ int32_t lsm303agr_mag_offset_temp_comp_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303agr_mag_offset_temp_comp_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm303agr_mag_offset_temp_comp_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm303agr_cfg_reg_a_m_t cfg_reg_a_m;
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
+ (uint8_t *)&cfg_reg_a_m, 1);
*val = cfg_reg_a_m.comp_temp_en;
return ret;
@@ -1127,11 +1268,13 @@ int32_t lsm303agr_mag_low_pass_bandwidth_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_B_M,
- (uint8_t*)&cfg_reg_b_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_b_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_b_m.lpf = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_B_M,
- (uint8_t*)&cfg_reg_b_m, 1);
+ (uint8_t *)&cfg_reg_b_m, 1);
}
return ret;
@@ -1152,19 +1295,23 @@ int32_t lsm303agr_mag_low_pass_bandwidth_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_B_M,
- (uint8_t*)&cfg_reg_b_m, 1);
+ (uint8_t *)&cfg_reg_b_m, 1);
- switch (cfg_reg_b_m.lpf){
+ switch (cfg_reg_b_m.lpf)
+ {
case LSM303AGR_ODR_DIV_2:
*val = LSM303AGR_ODR_DIV_2;
break;
+
case LSM303AGR_ODR_DIV_4:
*val = LSM303AGR_ODR_DIV_4;
break;
+
default:
*val = LSM303AGR_ODR_DIV_2;
break;
}
+
return ret;
}
@@ -1183,11 +1330,13 @@ int32_t lsm303agr_mag_set_rst_mode_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_B_M,
- (uint8_t*)&cfg_reg_b_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_b_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_b_m.set_rst = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_B_M,
- (uint8_t*)&cfg_reg_b_m, 1);
+ (uint8_t *)&cfg_reg_b_m, 1);
}
return ret;
@@ -1208,22 +1357,27 @@ int32_t lsm303agr_mag_set_rst_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_B_M,
- (uint8_t*)&cfg_reg_b_m, 1);
+ (uint8_t *)&cfg_reg_b_m, 1);
- switch (cfg_reg_b_m.set_rst){
+ switch (cfg_reg_b_m.set_rst)
+ {
case LSM303AGR_SET_SENS_ODR_DIV_63:
*val = LSM303AGR_SET_SENS_ODR_DIV_63;
break;
+
case LSM303AGR_SENS_OFF_CANC_EVERY_ODR:
*val = LSM303AGR_SENS_OFF_CANC_EVERY_ODR;
break;
+
case LSM303AGR_SET_SENS_ONLY_AT_POWER_ON:
*val = LSM303AGR_SET_SENS_ONLY_AT_POWER_ON;
break;
+
default:
*val = LSM303AGR_SET_SENS_ODR_DIV_63;
break;
}
+
return ret;
}
@@ -1248,11 +1402,13 @@ int32_t lsm303agr_mag_set_rst_sensor_single_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_B_M,
- (uint8_t*)&cfg_reg_b_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_b_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_b_m.off_canc_one_shot = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_B_M,
- (uint8_t*)&cfg_reg_b_m, 1);
+ (uint8_t *)&cfg_reg_b_m, 1);
}
return ret;
@@ -1280,7 +1436,7 @@ int32_t lsm303agr_mag_set_rst_sensor_single_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_B_M,
- (uint8_t*)&cfg_reg_b_m, 1);
+ (uint8_t *)&cfg_reg_b_m, 1);
*val = cfg_reg_b_m.off_canc_one_shot;
return ret;
@@ -1301,11 +1457,13 @@ int32_t lsm303agr_mag_block_data_update_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_c_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_c_m.bdu = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
+ (uint8_t *)&cfg_reg_c_m, 1);
}
return ret;
@@ -1326,7 +1484,7 @@ int32_t lsm303agr_mag_block_data_update_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
+ (uint8_t *)&cfg_reg_c_m, 1);
*val = cfg_reg_c_m.bdu;
return ret;
@@ -1346,7 +1504,7 @@ int32_t lsm303agr_mag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_STATUS_REG_M,
- (uint8_t*)&status_reg_m, 1);
+ (uint8_t *)&status_reg_m, 1);
*val = status_reg_m.zyxda;
return ret;
@@ -1366,7 +1524,7 @@ int32_t lsm303agr_mag_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_STATUS_REG_M,
- (uint8_t*)&status_reg_m, 1);
+ (uint8_t *)&status_reg_m, 1);
*val = status_reg_m.zyxor;
return ret;
@@ -1380,10 +1538,19 @@ int32_t lsm303agr_mag_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303agr_magnetic_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm303agr_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lsm303agr_read_reg(ctx, LSM303AGR_OUTX_L_REG_M, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -1394,7 +1561,7 @@ int32_t lsm303agr_magnetic_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
/**
* @addtogroup common
- * @brief This section group common usefull functions
+ * @brief This section group common useful functions
* @{
*
*/
@@ -1410,7 +1577,9 @@ int32_t lsm303agr_magnetic_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lsm303agr_xl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm303agr_read_reg(ctx, LSM303AGR_WHO_AM_I_A, buff, 1);
+
return ret;
}
@@ -1429,11 +1598,13 @@ int32_t lsm303agr_xl_self_test_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG4_A,
- (uint8_t*)&ctrl_reg4_a, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg4_a, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4_a.st = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG4_A,
- (uint8_t*)&ctrl_reg4_a, 1);
+ (uint8_t *)&ctrl_reg4_a, 1);
}
return ret;
@@ -1454,22 +1625,27 @@ int32_t lsm303agr_xl_self_test_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG4_A,
- (uint8_t*)&ctrl_reg4_a, 1);
+ (uint8_t *)&ctrl_reg4_a, 1);
- switch (ctrl_reg4_a.st){
+ switch (ctrl_reg4_a.st)
+ {
case LSM303AGR_ST_DISABLE:
*val = LSM303AGR_ST_DISABLE;
break;
+
case LSM303AGR_ST_POSITIVE:
*val = LSM303AGR_ST_POSITIVE;
break;
+
case LSM303AGR_ST_NEGATIVE:
*val = LSM303AGR_ST_NEGATIVE;
break;
+
default:
*val = LSM303AGR_ST_DISABLE;
break;
}
+
return ret;
}
@@ -1488,11 +1664,13 @@ int32_t lsm303agr_xl_data_format_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG4_A,
- (uint8_t*)&ctrl_reg4_a, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg4_a, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4_a.ble = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG4_A,
- (uint8_t*)&ctrl_reg4_a, 1);
+ (uint8_t *)&ctrl_reg4_a, 1);
}
return ret;
@@ -1513,19 +1691,23 @@ int32_t lsm303agr_xl_data_format_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG4_A,
- (uint8_t*)&ctrl_reg4_a, 1);
+ (uint8_t *)&ctrl_reg4_a, 1);
- switch (ctrl_reg4_a.ble){
+ switch (ctrl_reg4_a.ble)
+ {
case LSM303AGR_XL_LSB_AT_LOW_ADD:
*val = LSM303AGR_XL_LSB_AT_LOW_ADD;
break;
+
case LSM303AGR_XL_MSB_AT_LOW_ADD:
*val = LSM303AGR_XL_MSB_AT_LOW_ADD;
break;
+
default:
*val = LSM303AGR_XL_LSB_AT_LOW_ADD;
break;
}
+
return ret;
}
@@ -1543,11 +1725,13 @@ int32_t lsm303agr_xl_boot_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG5_A,
- (uint8_t*)&ctrl_reg5_a, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg5_a, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5_a.boot = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG5_A,
- (uint8_t*)&ctrl_reg5_a, 1);
+ (uint8_t *)&ctrl_reg5_a, 1);
}
return ret;
@@ -1567,7 +1751,7 @@ int32_t lsm303agr_xl_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG5_A,
- (uint8_t*)&ctrl_reg5_a, 1);
+ (uint8_t *)&ctrl_reg5_a, 1);
*val = ctrl_reg5_a.boot;
return ret;
@@ -1585,7 +1769,9 @@ int32_t lsm303agr_xl_status_get(stmdev_ctx_t *ctx,
lsm303agr_status_reg_a_t *val)
{
int32_t ret;
- ret = lsm303agr_read_reg(ctx, LSM303AGR_STATUS_REG_A, (uint8_t*) val, 1);
+
+ ret = lsm303agr_read_reg(ctx, LSM303AGR_STATUS_REG_A, (uint8_t *) val, 1);
+
return ret;
}
@@ -1600,7 +1786,9 @@ int32_t lsm303agr_xl_status_get(stmdev_ctx_t *ctx,
int32_t lsm303agr_mag_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm303agr_read_reg(ctx, LSM303AGR_WHO_AM_I_M, buff, 1);
+
return ret;
}
@@ -1618,11 +1806,13 @@ int32_t lsm303agr_mag_reset_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_a_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_a_m.soft_rst = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
+ (uint8_t *)&cfg_reg_a_m, 1);
}
return ret;
@@ -1642,7 +1832,7 @@ int32_t lsm303agr_mag_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
+ (uint8_t *)&cfg_reg_a_m, 1);
*val = cfg_reg_a_m.soft_rst;
return ret;
@@ -1662,11 +1852,13 @@ int32_t lsm303agr_mag_boot_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_a_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_a_m.reboot = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
+ (uint8_t *)&cfg_reg_a_m, 1);
}
return ret;
@@ -1686,7 +1878,7 @@ int32_t lsm303agr_mag_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_A_M,
- (uint8_t*)&cfg_reg_a_m, 1);
+ (uint8_t *)&cfg_reg_a_m, 1);
*val = cfg_reg_a_m.reboot;
return ret;
@@ -1706,11 +1898,13 @@ int32_t lsm303agr_mag_self_test_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_c_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_c_m.self_test = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
+ (uint8_t *)&cfg_reg_c_m, 1);
}
return ret;
@@ -1730,7 +1924,7 @@ int32_t lsm303agr_mag_self_test_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
+ (uint8_t *)&cfg_reg_c_m, 1);
*val = cfg_reg_c_m.self_test;
return ret;
@@ -1751,11 +1945,13 @@ int32_t lsm303agr_mag_data_format_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_c_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_c_m.ble = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
+ (uint8_t *)&cfg_reg_c_m, 1);
}
return ret;
@@ -1776,19 +1972,23 @@ int32_t lsm303agr_mag_data_format_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
+ (uint8_t *)&cfg_reg_c_m, 1);
- switch (cfg_reg_c_m.ble){
+ switch (cfg_reg_c_m.ble)
+ {
case LSM303AGR_MG_LSB_AT_LOW_ADD:
*val = LSM303AGR_MG_LSB_AT_LOW_ADD;
break;
+
case LSM303AGR_MG_MSB_AT_LOW_ADD:
*val = LSM303AGR_MG_MSB_AT_LOW_ADD;
break;
+
default:
*val = LSM303AGR_MG_LSB_AT_LOW_ADD;
break;
}
+
return ret;
}
@@ -1804,7 +2004,9 @@ int32_t lsm303agr_mag_status_get(stmdev_ctx_t *ctx,
lsm303agr_status_reg_m_t *val)
{
int32_t ret;
- ret = lsm303agr_read_reg(ctx, LSM303AGR_STATUS_REG_M, (uint8_t*) val, 1);
+
+ ret = lsm303agr_read_reg(ctx, LSM303AGR_STATUS_REG_M, (uint8_t *) val, 1);
+
return ret;
}
@@ -1833,7 +2035,9 @@ int32_t lsm303agr_xl_int1_gen_conf_set(stmdev_ctx_t *ctx,
lsm303agr_int1_cfg_a_t *val)
{
int32_t ret;
- ret = lsm303agr_write_reg(ctx, LSM303AGR_INT1_CFG_A, (uint8_t*) val, 1);
+
+ ret = lsm303agr_write_reg(ctx, LSM303AGR_INT1_CFG_A, (uint8_t *) val, 1);
+
return ret;
}
@@ -1849,7 +2053,9 @@ int32_t lsm303agr_xl_int1_gen_conf_get(stmdev_ctx_t *ctx,
lsm303agr_int1_cfg_a_t *val)
{
int32_t ret;
- ret = lsm303agr_read_reg(ctx, LSM303AGR_INT1_CFG_A, (uint8_t*) val, 1);
+
+ ret = lsm303agr_read_reg(ctx, LSM303AGR_INT1_CFG_A, (uint8_t *) val, 1);
+
return ret;
}
@@ -1865,7 +2071,9 @@ int32_t lsm303agr_xl_int1_gen_source_get(stmdev_ctx_t *ctx,
lsm303agr_int1_src_a_t *val)
{
int32_t ret;
- ret = lsm303agr_read_reg(ctx, LSM303AGR_INT1_SRC_A, (uint8_t*) val, 1);
+
+ ret = lsm303agr_read_reg(ctx, LSM303AGR_INT1_SRC_A, (uint8_t *) val, 1);
+
return ret;
}
@@ -1886,11 +2094,13 @@ int32_t lsm303agr_xl_int1_gen_threshold_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_INT1_THS_A,
- (uint8_t*)&int1_ths_a, 1);
- if(ret == 0){
+ (uint8_t *)&int1_ths_a, 1);
+
+ if (ret == 0)
+ {
int1_ths_a.ths = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_INT1_THS_A,
- (uint8_t*)&int1_ths_a, 1);
+ (uint8_t *)&int1_ths_a, 1);
}
return ret;
@@ -1913,7 +2123,7 @@ int32_t lsm303agr_xl_int1_gen_threshold_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_INT1_THS_A,
- (uint8_t*)&int1_ths_a, 1);
+ (uint8_t *)&int1_ths_a, 1);
*val = int1_ths_a.ths;
return ret;
@@ -1928,17 +2138,20 @@ int32_t lsm303agr_xl_int1_gen_threshold_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303agr_xl_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm303agr_xl_int1_gen_duration_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm303agr_int1_duration_a_t int1_duration_a;
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_INT1_DURATION_A,
- (uint8_t*)&int1_duration_a, 1);
- if(ret == 0){
+ (uint8_t *)&int1_duration_a, 1);
+
+ if (ret == 0)
+ {
int1_duration_a.d = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_INT1_DURATION_A,
- (uint8_t*)&int1_duration_a, 1);
+ (uint8_t *)&int1_duration_a, 1);
}
return ret;
@@ -1953,13 +2166,14 @@ int32_t lsm303agr_xl_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303agr_xl_int1_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm303agr_xl_int1_gen_duration_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm303agr_int1_duration_a_t int1_duration_a;
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_INT1_DURATION_A,
- (uint8_t*)&int1_duration_a, 1);
+ (uint8_t *)&int1_duration_a, 1);
*val = int1_duration_a.d;
return ret;
@@ -1990,7 +2204,9 @@ int32_t lsm303agr_xl_int2_gen_conf_set(stmdev_ctx_t *ctx,
lsm303agr_int2_cfg_a_t *val)
{
int32_t ret;
- ret = lsm303agr_write_reg(ctx, LSM303AGR_INT2_CFG_A, (uint8_t*) val, 1);
+
+ ret = lsm303agr_write_reg(ctx, LSM303AGR_INT2_CFG_A, (uint8_t *) val, 1);
+
return ret;
}
@@ -2006,7 +2222,9 @@ int32_t lsm303agr_xl_int2_gen_conf_get(stmdev_ctx_t *ctx,
lsm303agr_int2_cfg_a_t *val)
{
int32_t ret;
- ret = lsm303agr_read_reg(ctx, LSM303AGR_INT2_CFG_A, (uint8_t*) val, 1);
+
+ ret = lsm303agr_read_reg(ctx, LSM303AGR_INT2_CFG_A, (uint8_t *) val, 1);
+
return ret;
}
@@ -2022,7 +2240,9 @@ int32_t lsm303agr_xl_int2_gen_source_get(stmdev_ctx_t *ctx,
lsm303agr_int2_src_a_t *val)
{
int32_t ret;
- ret = lsm303agr_read_reg(ctx, LSM303AGR_INT2_SRC_A, (uint8_t*) val, 1);
+
+ ret = lsm303agr_read_reg(ctx, LSM303AGR_INT2_SRC_A, (uint8_t *) val, 1);
+
return ret;
}
@@ -2043,11 +2263,13 @@ int32_t lsm303agr_xl_int2_gen_threshold_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_INT2_THS_A,
- (uint8_t*)&int2_ths_a, 1);
- if(ret == 0){
+ (uint8_t *)&int2_ths_a, 1);
+
+ if (ret == 0)
+ {
int2_ths_a.ths = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_INT2_THS_A,
- (uint8_t*)&int2_ths_a, 1);
+ (uint8_t *)&int2_ths_a, 1);
}
return ret;
@@ -2070,7 +2292,7 @@ int32_t lsm303agr_xl_int2_gen_threshold_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_INT2_THS_A,
- (uint8_t*)&int2_ths_a, 1);
+ (uint8_t *)&int2_ths_a, 1);
*val = int2_ths_a.ths;
return ret;
@@ -2085,17 +2307,20 @@ int32_t lsm303agr_xl_int2_gen_threshold_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303agr_xl_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm303agr_xl_int2_gen_duration_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm303agr_int2_duration_a_t int2_duration_a;
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_INT2_DURATION_A,
- (uint8_t*)&int2_duration_a, 1);
- if(ret == 0){
+ (uint8_t *)&int2_duration_a, 1);
+
+ if (ret == 0)
+ {
int2_duration_a.d = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_INT2_DURATION_A,
- (uint8_t*)&int2_duration_a, 1);
+ (uint8_t *)&int2_duration_a, 1);
}
return ret;
@@ -2117,7 +2342,7 @@ int32_t lsm303agr_xl_int2_gen_duration_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_INT2_DURATION_A,
- (uint8_t*)&int2_duration_a, 1);
+ (uint8_t *)&int2_duration_a, 1);
*val = int2_duration_a.d;
return ret;
@@ -2151,11 +2376,13 @@ int32_t lsm303agr_xl_high_pass_int_conf_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG2_A,
- (uint8_t*)&ctrl_reg2_a, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg2_a, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2_a.hp = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG2_A,
- (uint8_t*)&ctrl_reg2_a, 1);
+ (uint8_t *)&ctrl_reg2_a, 1);
}
return ret;
@@ -2176,37 +2403,47 @@ int32_t lsm303agr_xl_high_pass_int_conf_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG2_A,
- (uint8_t*)&ctrl_reg2_a, 1);
+ (uint8_t *)&ctrl_reg2_a, 1);
- switch (ctrl_reg2_a.hp){
+ switch (ctrl_reg2_a.hp)
+ {
case LSM303AGR_DISC_FROM_INT_GENERATOR:
*val = LSM303AGR_DISC_FROM_INT_GENERATOR;
break;
+
case LSM303AGR_ON_INT1_GEN:
*val = LSM303AGR_ON_INT1_GEN;
break;
+
case LSM303AGR_ON_INT2_GEN:
*val = LSM303AGR_ON_INT2_GEN;
break;
+
case LSM303AGR_ON_TAP_GEN:
*val = LSM303AGR_ON_TAP_GEN;
break;
+
case LSM303AGR_ON_INT1_INT2_GEN:
*val = LSM303AGR_ON_INT1_INT2_GEN;
break;
+
case LSM303AGR_ON_INT1_TAP_GEN:
*val = LSM303AGR_ON_INT1_TAP_GEN;
break;
+
case LSM303AGR_ON_INT2_TAP_GEN:
*val = LSM303AGR_ON_INT2_TAP_GEN;
break;
+
case LSM303AGR_ON_INT1_INT2_TAP_GEN:
*val = LSM303AGR_ON_INT1_INT2_TAP_GEN;
break;
+
default:
*val = LSM303AGR_DISC_FROM_INT_GENERATOR;
break;
}
+
return ret;
}
@@ -2222,7 +2459,9 @@ int32_t lsm303agr_xl_pin_int1_config_set(stmdev_ctx_t *ctx,
lsm303agr_ctrl_reg3_a_t *val)
{
int32_t ret;
- ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG3_A, (uint8_t*) val, 1);
+
+ ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG3_A, (uint8_t *) val, 1);
+
return ret;
}
@@ -2238,7 +2477,9 @@ int32_t lsm303agr_xl_pin_int1_config_get(stmdev_ctx_t *ctx,
lsm303agr_ctrl_reg3_a_t *val)
{
int32_t ret;
- ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG3_A, (uint8_t*) val, 1);
+
+ ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG3_A, (uint8_t *) val, 1);
+
return ret;
}
@@ -2258,11 +2499,13 @@ int32_t lsm303agr_xl_int2_pin_detect_4d_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG5_A,
- (uint8_t*)&ctrl_reg5_a, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg5_a, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5_a.d4d_int2 = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG5_A,
- (uint8_t*)&ctrl_reg5_a, 1);
+ (uint8_t *)&ctrl_reg5_a, 1);
}
return ret;
@@ -2284,7 +2527,7 @@ int32_t lsm303agr_xl_int2_pin_detect_4d_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG5_A,
- (uint8_t*)&ctrl_reg5_a, 1);
+ (uint8_t *)&ctrl_reg5_a, 1);
*val = ctrl_reg5_a.d4d_int2;
return ret;
@@ -2307,11 +2550,13 @@ int32_t lsm303agr_xl_int2pin_notification_mode_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG5_A,
- (uint8_t*)&ctrl_reg5_a, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg5_a, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5_a.lir_int2 = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG5_A,
- (uint8_t*)&ctrl_reg5_a, 1);
+ (uint8_t *)&ctrl_reg5_a, 1);
}
return ret;
@@ -2328,25 +2573,29 @@ int32_t lsm303agr_xl_int2pin_notification_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm303agr_xl_int2pin_notification_mode_get(stmdev_ctx_t *ctx,
- lsm303agr_lir_int2_a_t *val)
+ lsm303agr_lir_int2_a_t *val)
{
lsm303agr_ctrl_reg5_a_t ctrl_reg5_a;
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG5_A,
- (uint8_t*)&ctrl_reg5_a, 1);
+ (uint8_t *)&ctrl_reg5_a, 1);
- switch (ctrl_reg5_a.lir_int2){
+ switch (ctrl_reg5_a.lir_int2)
+ {
case LSM303AGR_INT2_PULSED:
*val = LSM303AGR_INT2_PULSED;
break;
+
case LSM303AGR_INT2_LATCHED:
*val = LSM303AGR_INT2_LATCHED;
break;
+
default:
*val = LSM303AGR_INT2_PULSED;
break;
}
+
return ret;
}
@@ -2359,17 +2608,20 @@ int32_t lsm303agr_xl_int2pin_notification_mode_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303agr_xl_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm303agr_xl_int1_pin_detect_4d_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm303agr_ctrl_reg5_a_t ctrl_reg5_a;
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG5_A,
- (uint8_t*)&ctrl_reg5_a, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg5_a, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5_a.d4d_int1 = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG5_A,
- (uint8_t*)&ctrl_reg5_a, 1);
+ (uint8_t *)&ctrl_reg5_a, 1);
}
return ret;
@@ -2384,13 +2636,14 @@ int32_t lsm303agr_xl_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303agr_xl_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm303agr_xl_int1_pin_detect_4d_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm303agr_ctrl_reg5_a_t ctrl_reg5_a;
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG5_A,
- (uint8_t*)&ctrl_reg5_a, 1);
+ (uint8_t *)&ctrl_reg5_a, 1);
*val = ctrl_reg5_a.d4d_int1;
return ret;
@@ -2413,11 +2666,13 @@ int32_t lsm303agr_xl_int1pin_notification_mode_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG5_A,
- (uint8_t*)&ctrl_reg5_a, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg5_a, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5_a.lir_int1 = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG5_A,
- (uint8_t*)&ctrl_reg5_a, 1);
+ (uint8_t *)&ctrl_reg5_a, 1);
}
return ret;
@@ -2440,19 +2695,23 @@ int32_t lsm303agr_xl_int1pin_notification_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG5_A,
- (uint8_t*)&ctrl_reg5_a, 1);
+ (uint8_t *)&ctrl_reg5_a, 1);
- switch (ctrl_reg5_a.lir_int1){
+ switch (ctrl_reg5_a.lir_int1)
+ {
case LSM303AGR_INT1_PULSED:
*val = LSM303AGR_INT1_PULSED;
break;
+
case LSM303AGR_INT1_LATCHED:
*val = LSM303AGR_INT1_LATCHED;
break;
+
default:
*val = LSM303AGR_INT1_PULSED;
break;
}
+
return ret;
}
@@ -2468,7 +2727,9 @@ int32_t lsm303agr_xl_pin_int2_config_set(stmdev_ctx_t *ctx,
lsm303agr_ctrl_reg6_a_t *val)
{
int32_t ret;
- ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG6_A, (uint8_t*) val, 1);
+
+ ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG6_A, (uint8_t *) val, 1);
+
return ret;
}
@@ -2484,7 +2745,9 @@ int32_t lsm303agr_xl_pin_int2_config_get(stmdev_ctx_t *ctx,
lsm303agr_ctrl_reg6_a_t *val)
{
int32_t ret;
- ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG6_A, (uint8_t*) val, 1);
+
+ ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG6_A, (uint8_t *) val, 1);
+
return ret;
}
@@ -2493,7 +2756,7 @@ int32_t lsm303agr_xl_pin_int2_config_get(stmdev_ctx_t *ctx,
*
*/
- /**
+/**
* @addtogroup magnetometer interrupts
* @brief This section group all the functions that manage the
* magnetometer interrupts
@@ -2518,11 +2781,13 @@ int32_t lsm303agr_mag_offset_int_conf_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_B_M,
- (uint8_t*)&cfg_reg_b_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_b_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_b_m.int_on_dataoff = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_B_M,
- (uint8_t*)&cfg_reg_b_m, 1);
+ (uint8_t *)&cfg_reg_b_m, 1);
}
return ret;
@@ -2545,19 +2810,23 @@ int32_t lsm303agr_mag_offset_int_conf_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_B_M,
- (uint8_t*)&cfg_reg_b_m, 1);
+ (uint8_t *)&cfg_reg_b_m, 1);
- switch (cfg_reg_b_m.int_on_dataoff){
+ switch (cfg_reg_b_m.int_on_dataoff)
+ {
case LSM303AGR_CHECK_BEFORE:
*val = LSM303AGR_CHECK_BEFORE;
break;
+
case LSM303AGR_CHECK_AFTER:
*val = LSM303AGR_CHECK_AFTER;
break;
+
default:
*val = LSM303AGR_CHECK_BEFORE;
break;
}
+
return ret;
}
@@ -2575,11 +2844,13 @@ int32_t lsm303agr_mag_drdy_on_pin_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_c_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_c_m.int_mag = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
+ (uint8_t *)&cfg_reg_c_m, 1);
}
return ret;
@@ -2599,7 +2870,7 @@ int32_t lsm303agr_mag_drdy_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
+ (uint8_t *)&cfg_reg_c_m, 1);
*val = cfg_reg_c_m.int_mag;
return ret;
@@ -2619,11 +2890,13 @@ int32_t lsm303agr_mag_int_on_pin_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_c_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_c_m.int_mag_pin = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
+ (uint8_t *)&cfg_reg_c_m, 1);
}
return ret;
@@ -2643,7 +2916,7 @@ int32_t lsm303agr_mag_int_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
+ (uint8_t *)&cfg_reg_c_m, 1);
*val = cfg_reg_c_m.int_mag_pin;
return ret;
@@ -2661,7 +2934,10 @@ int32_t lsm303agr_mag_int_gen_conf_set(stmdev_ctx_t *ctx,
lsm303agr_int_crtl_reg_m_t *val)
{
int32_t ret;
- ret = lsm303agr_write_reg(ctx, LSM303AGR_INT_CRTL_REG_M, (uint8_t*) val, 1);
+
+ ret = lsm303agr_write_reg(ctx, LSM303AGR_INT_CRTL_REG_M,
+ (uint8_t *) val, 1);
+
return ret;
}
@@ -2677,8 +2953,10 @@ int32_t lsm303agr_mag_int_gen_conf_get(stmdev_ctx_t *ctx,
lsm303agr_int_crtl_reg_m_t *val)
{
int32_t ret;
+
ret = lsm303agr_read_reg(ctx, LSM303AGR_INT_CRTL_REG_M,
- (uint8_t*) val, 1);
+ (uint8_t *) val, 1);
+
return ret;
}
@@ -2694,8 +2972,10 @@ int32_t lsm303agr_mag_int_gen_source_get(stmdev_ctx_t *ctx,
lsm303agr_int_source_reg_m_t *val)
{
int32_t ret;
+
ret = lsm303agr_read_reg(ctx, LSM303AGR_INT_SOURCE_REG_M,
- (uint8_t*) val, 1);
+ (uint8_t *) val, 1);
+
return ret;
}
@@ -2711,10 +2991,15 @@ int32_t lsm303agr_mag_int_gen_source_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm303agr_mag_int_gen_treshold_set(stmdev_ctx_t *ctx,
- uint8_t *buff)
+ int16_t val)
{
+ uint8_t buff[6];
int32_t ret;
+
+ buff[1] = (uint8_t)((uint16_t)val / 256U);
+ buff[0] = (uint8_t)((uint16_t)val - (buff[1] * 256U));
ret = lsm303agr_write_reg(ctx, LSM303AGR_INT_THS_L_REG_M, buff, 2);
+
return ret;
}
@@ -2730,10 +3015,15 @@ int32_t lsm303agr_mag_int_gen_treshold_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm303agr_mag_int_gen_treshold_get(stmdev_ctx_t *ctx,
- uint8_t *buff)
+ int16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
+
ret = lsm303agr_read_reg(ctx, LSM303AGR_INT_THS_L_REG_M, buff, 2);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+
return ret;
}
@@ -2764,11 +3054,13 @@ int32_t lsm303agr_xl_fifo_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG5_A,
- (uint8_t*)&ctrl_reg5_a, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg5_a, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5_a.fifo_en = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG5_A,
- (uint8_t*)&ctrl_reg5_a, 1);
+ (uint8_t *)&ctrl_reg5_a, 1);
}
return ret;
@@ -2788,7 +3080,7 @@ int32_t lsm303agr_xl_fifo_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG5_A,
- (uint8_t*)&ctrl_reg5_a, 1);
+ (uint8_t *)&ctrl_reg5_a, 1);
*val = ctrl_reg5_a.fifo_en;
return ret;
@@ -2802,17 +3094,20 @@ int32_t lsm303agr_xl_fifo_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303agr_xl_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm303agr_xl_fifo_watermark_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm303agr_fifo_ctrl_reg_a_t fifo_ctrl_reg_a;
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_FIFO_CTRL_REG_A,
- (uint8_t*)&fifo_ctrl_reg_a, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl_reg_a, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl_reg_a.fth = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_FIFO_CTRL_REG_A,
- (uint8_t*)&fifo_ctrl_reg_a, 1);
+ (uint8_t *)&fifo_ctrl_reg_a, 1);
}
return ret;
@@ -2826,13 +3121,14 @@ int32_t lsm303agr_xl_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303agr_xl_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm303agr_xl_fifo_watermark_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm303agr_fifo_ctrl_reg_a_t fifo_ctrl_reg_a;
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_FIFO_CTRL_REG_A,
- (uint8_t*)&fifo_ctrl_reg_a, 1);
+ (uint8_t *)&fifo_ctrl_reg_a, 1);
*val = fifo_ctrl_reg_a.fth;
return ret;
@@ -2847,17 +3143,19 @@ int32_t lsm303agr_xl_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm303agr_xl_fifo_trigger_event_set(stmdev_ctx_t *ctx,
- lsm303agr_tr_a_t val)
+ lsm303agr_tr_a_t val)
{
lsm303agr_fifo_ctrl_reg_a_t fifo_ctrl_reg_a;
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_FIFO_CTRL_REG_A,
- (uint8_t*)&fifo_ctrl_reg_a, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl_reg_a, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl_reg_a.tr = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_FIFO_CTRL_REG_A,
- (uint8_t*)&fifo_ctrl_reg_a, 1);
+ (uint8_t *)&fifo_ctrl_reg_a, 1);
}
return ret;
@@ -2878,19 +3176,23 @@ int32_t lsm303agr_xl_fifo_trigger_event_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_FIFO_CTRL_REG_A,
- (uint8_t*)&fifo_ctrl_reg_a, 1);
+ (uint8_t *)&fifo_ctrl_reg_a, 1);
- switch (fifo_ctrl_reg_a.tr){
+ switch (fifo_ctrl_reg_a.tr)
+ {
case LSM303AGR_INT1_GEN:
*val = LSM303AGR_INT1_GEN;
break;
+
case LSM303AGR_INT2_GEN:
*val = LSM303AGR_INT2_GEN;
break;
+
default:
*val = LSM303AGR_INT1_GEN;
break;
}
+
return ret;
}
@@ -2909,11 +3211,13 @@ int32_t lsm303agr_xl_fifo_mode_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_FIFO_CTRL_REG_A,
- (uint8_t*)&fifo_ctrl_reg_a, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl_reg_a, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl_reg_a.fm = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_FIFO_CTRL_REG_A,
- (uint8_t*)&fifo_ctrl_reg_a, 1);
+ (uint8_t *)&fifo_ctrl_reg_a, 1);
}
return ret;
@@ -2934,25 +3238,31 @@ int32_t lsm303agr_xl_fifo_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_FIFO_CTRL_REG_A,
- (uint8_t*)&fifo_ctrl_reg_a, 1);
+ (uint8_t *)&fifo_ctrl_reg_a, 1);
- switch (fifo_ctrl_reg_a.fm){
+ switch (fifo_ctrl_reg_a.fm)
+ {
case LSM303AGR_BYPASS_MODE:
*val = LSM303AGR_BYPASS_MODE;
break;
+
case LSM303AGR_FIFO_MODE:
*val = LSM303AGR_FIFO_MODE;
break;
+
case LSM303AGR_DYNAMIC_STREAM_MODE:
*val = LSM303AGR_DYNAMIC_STREAM_MODE;
break;
+
case LSM303AGR_STREAM_TO_FIFO_MODE:
*val = LSM303AGR_STREAM_TO_FIFO_MODE;
break;
+
default:
*val = LSM303AGR_BYPASS_MODE;
break;
}
+
return ret;
}
@@ -2968,7 +3278,10 @@ int32_t lsm303agr_xl_fifo_status_get(stmdev_ctx_t *ctx,
lsm303agr_fifo_src_reg_a_t *val)
{
int32_t ret;
- ret = lsm303agr_read_reg(ctx, LSM303AGR_FIFO_SRC_REG_A, (uint8_t*) val, 1);
+
+ ret = lsm303agr_read_reg(ctx, LSM303AGR_FIFO_SRC_REG_A,
+ (uint8_t *) val, 1);
+
return ret;
}
@@ -2980,13 +3293,14 @@ int32_t lsm303agr_xl_fifo_status_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303agr_xl_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm303agr_xl_fifo_data_level_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm303agr_fifo_src_reg_a_t fifo_src_reg_a;
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_FIFO_SRC_REG_A,
- (uint8_t*)&fifo_src_reg_a, 1);
+ (uint8_t *)&fifo_src_reg_a, 1);
*val = fifo_src_reg_a.fss;
return ret;
@@ -3000,13 +3314,14 @@ int32_t lsm303agr_xl_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303agr_xl_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm303agr_xl_fifo_empty_flag_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm303agr_fifo_src_reg_a_t fifo_src_reg_a;
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_FIFO_SRC_REG_A,
- (uint8_t*)&fifo_src_reg_a, 1);
+ (uint8_t *)&fifo_src_reg_a, 1);
*val = fifo_src_reg_a.empty;
return ret;
@@ -3020,13 +3335,14 @@ int32_t lsm303agr_xl_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303agr_xl_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm303agr_xl_fifo_ovr_flag_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm303agr_fifo_src_reg_a_t fifo_src_reg_a;
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_FIFO_SRC_REG_A,
- (uint8_t*)&fifo_src_reg_a, 1);
+ (uint8_t *)&fifo_src_reg_a, 1);
*val = fifo_src_reg_a.ovrn_fifo;
return ret;
@@ -3040,13 +3356,14 @@ int32_t lsm303agr_xl_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303agr_xl_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm303agr_xl_fifo_fth_flag_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm303agr_fifo_src_reg_a_t fifo_src_reg_a;
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_FIFO_SRC_REG_A,
- (uint8_t*)&fifo_src_reg_a, 1);
+ (uint8_t *)&fifo_src_reg_a, 1);
*val = fifo_src_reg_a.wtm;
return ret;
@@ -3077,7 +3394,9 @@ int32_t lsm303agr_tap_conf_set(stmdev_ctx_t *ctx,
lsm303agr_click_cfg_a_t *val)
{
int32_t ret;
- ret = lsm303agr_write_reg(ctx, LSM303AGR_CLICK_CFG_A, (uint8_t*) val, 1);
+
+ ret = lsm303agr_write_reg(ctx, LSM303AGR_CLICK_CFG_A, (uint8_t *) val, 1);
+
return ret;
}
@@ -3093,7 +3412,9 @@ int32_t lsm303agr_tap_conf_get(stmdev_ctx_t *ctx,
lsm303agr_click_cfg_a_t *val)
{
int32_t ret;
- ret = lsm303agr_read_reg(ctx, LSM303AGR_CLICK_CFG_A, (uint8_t*) val, 1);
+
+ ret = lsm303agr_read_reg(ctx, LSM303AGR_CLICK_CFG_A, (uint8_t *) val, 1);
+
return ret;
}
@@ -3109,7 +3430,9 @@ int32_t lsm303agr_tap_source_get(stmdev_ctx_t *ctx,
lsm303agr_click_src_a_t *val)
{
int32_t ret;
- ret = lsm303agr_read_reg(ctx, LSM303AGR_CLICK_SRC_A, (uint8_t*) val, 1);
+
+ ret = lsm303agr_read_reg(ctx, LSM303AGR_CLICK_SRC_A, (uint8_t *) val, 1);
+
return ret;
}
@@ -3128,11 +3451,13 @@ int32_t lsm303agr_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CLICK_THS_A,
- (uint8_t*)&click_ths_a, 1);
- if(ret == 0){
+ (uint8_t *)&click_ths_a, 1);
+
+ if (ret == 0)
+ {
click_ths_a.ths = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CLICK_THS_A,
- (uint8_t*)&click_ths_a, 1);
+ (uint8_t *)&click_ths_a, 1);
}
return ret;
@@ -3153,7 +3478,7 @@ int32_t lsm303agr_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CLICK_THS_A,
- (uint8_t*)&click_ths_a, 1);
+ (uint8_t *)&click_ths_a, 1);
*val = click_ths_a.ths;
return ret;
@@ -3175,11 +3500,13 @@ int32_t lsm303agr_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_TIME_LIMIT_A,
- (uint8_t*)&time_limit_a, 1);
- if(ret == 0){
+ (uint8_t *)&time_limit_a, 1);
+
+ if (ret == 0)
+ {
time_limit_a.tli = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_TIME_LIMIT_A,
- (uint8_t*)&time_limit_a, 1);
+ (uint8_t *)&time_limit_a, 1);
}
return ret;
@@ -3201,7 +3528,7 @@ int32_t lsm303agr_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_TIME_LIMIT_A,
- (uint8_t*)&time_limit_a, 1);
+ (uint8_t *)&time_limit_a, 1);
*val = time_limit_a.tli;
return ret;
@@ -3224,11 +3551,13 @@ int32_t lsm303agr_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_TIME_LATENCY_A,
- (uint8_t*)&time_latency_a, 1);
- if(ret == 0){
+ (uint8_t *)&time_latency_a, 1);
+
+ if (ret == 0)
+ {
time_latency_a.tla = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_TIME_LATENCY_A,
- (uint8_t*)&time_latency_a, 1);
+ (uint8_t *)&time_latency_a, 1);
}
return ret;
@@ -3250,7 +3579,7 @@ int32_t lsm303agr_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_TIME_LATENCY_A,
- (uint8_t*)&time_latency_a, 1);
+ (uint8_t *)&time_latency_a, 1);
*val = time_latency_a.tla;
return ret;
@@ -3267,17 +3596,20 @@ int32_t lsm303agr_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303agr_double_tap_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm303agr_double_tap_timeout_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm303agr_time_window_a_t time_window_a;
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_TIME_WINDOW_A,
- (uint8_t*)&time_window_a, 1);
- if(ret == 0){
+ (uint8_t *)&time_window_a, 1);
+
+ if (ret == 0)
+ {
time_window_a.tw = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_TIME_WINDOW_A,
- (uint8_t*)&time_window_a, 1);
+ (uint8_t *)&time_window_a, 1);
}
return ret;
@@ -3294,13 +3626,14 @@ int32_t lsm303agr_double_tap_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303agr_double_tap_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm303agr_double_tap_timeout_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm303agr_time_window_a_t time_window_a;
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_TIME_WINDOW_A,
- (uint8_t*)&time_window_a, 1);
+ (uint8_t *)&time_window_a, 1);
*val = time_window_a.tw;
return ret;
@@ -3335,11 +3668,13 @@ int32_t lsm303agr_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_ACT_THS_A,
- (uint8_t*)&act_ths_a, 1);
- if(ret == 0){
+ (uint8_t *)&act_ths_a, 1);
+
+ if (ret == 0)
+ {
act_ths_a.acth = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_ACT_THS_A,
- (uint8_t*)&act_ths_a, 1);
+ (uint8_t *)&act_ths_a, 1);
}
return ret;
@@ -3361,7 +3696,7 @@ int32_t lsm303agr_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_ACT_THS_A,
- (uint8_t*)&act_ths_a, 1);
+ (uint8_t *)&act_ths_a, 1);
*val = act_ths_a.acth;
return ret;
@@ -3381,11 +3716,13 @@ int32_t lsm303agr_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_ACT_DUR_A,
- (uint8_t*)&act_dur_a, 1);
- if(ret == 0){
+ (uint8_t *)&act_dur_a, 1);
+
+ if (ret == 0)
+ {
act_dur_a.actd = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_ACT_DUR_A,
- (uint8_t*)&act_dur_a, 1);
+ (uint8_t *)&act_dur_a, 1);
}
return ret;
@@ -3405,7 +3742,7 @@ int32_t lsm303agr_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_ACT_DUR_A,
- (uint8_t*)&act_dur_a, 1);
+ (uint8_t *)&act_dur_a, 1);
*val = act_dur_a.actd;
return ret;
@@ -3439,11 +3776,13 @@ int32_t lsm303agr_xl_spi_mode_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG4_A,
- (uint8_t*)&ctrl_reg4_a, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg4_a, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4_a.spi_enable = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG4_A,
- (uint8_t*)&ctrl_reg4_a, 1);
+ (uint8_t *)&ctrl_reg4_a, 1);
}
return ret;
@@ -3464,19 +3803,23 @@ int32_t lsm303agr_xl_spi_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG4_A,
- (uint8_t*)&ctrl_reg4_a, 1);
+ (uint8_t *)&ctrl_reg4_a, 1);
- switch (ctrl_reg4_a.spi_enable){
+ switch (ctrl_reg4_a.spi_enable)
+ {
case LSM303AGR_SPI_4_WIRE:
*val = LSM303AGR_SPI_4_WIRE;
break;
+
case LSM303AGR_SPI_3_WIRE:
*val = LSM303AGR_SPI_3_WIRE;
break;
+
default:
*val = LSM303AGR_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -3495,11 +3838,13 @@ int32_t lsm303agr_mag_i2c_interface_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
- if(ret == 0){
+ (uint8_t *)&cfg_reg_c_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_c_m.i2c_dis = (uint8_t)val;
ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
+ (uint8_t *)&cfg_reg_c_m, 1);
}
return ret;
@@ -3520,19 +3865,23 @@ int32_t lsm303agr_mag_i2c_interface_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_C_M,
- (uint8_t*)&cfg_reg_c_m, 1);
+ (uint8_t *)&cfg_reg_c_m, 1);
- switch (cfg_reg_c_m.i2c_dis){
+ switch (cfg_reg_c_m.i2c_dis)
+ {
case LSM303AGR_I2C_ENABLE:
*val = LSM303AGR_I2C_ENABLE;
break;
+
case LSM303AGR_I2C_DISABLE:
*val = LSM303AGR_I2C_DISABLE;
break;
+
default:
*val = LSM303AGR_I2C_ENABLE;
break;
}
+
return ret;
}
diff --git a/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.h b/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.h
index e345301521dd2d8848ead94628792dbf8b7b5125..d4669b47c1e8205bf2b60b2351631b66ed1392c1 100644
--- a/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.h
+++ b/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file lsm303agr_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lsm303agr_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lsm303agr_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lsm303agr_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LSM303AGR_REGS_H
#define LSM303AGR_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup LSM303AGR
@@ -35,6 +36,37 @@
*
*/
+/** @defgroup Endianness definitions
+ * @{
+ *
+ */
+
+#ifndef DRV_BYTE_ORDER
+#ifndef __BYTE_ORDER__
+
+#define DRV_LITTLE_ENDIAN 1234
+#define DRV_BIG_ENDIAN 4321
+
+/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
+ * by uncommenting the define which fits your platform endianness
+ */
+//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
+#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
+
+#else /* defined __BYTE_ORDER__ */
+
+#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
+#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
+#define DRV_BYTE_ORDER __BYTE_ORDER__
+
+#endif /* __BYTE_ORDER__*/
+#endif /* DRV_BYTE_ORDER */
+
+/**
+ * @}
+ *
+ */
+
/** @defgroup STMicroelectronics sensors common types
* @{
*
@@ -43,7 +75,9 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -52,6 +86,16 @@ typedef struct{
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} bitwise_t;
#define PROPERTY_DISABLE (0U)
@@ -65,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -89,15 +134,16 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
- * Unico / Unicleo tools available on STMicroelectronics
- * web site.
+ * You can create a sensor configuration by your own or using
+ * Unico / Unicleo tools available on STMicroelectronics
+ * web site.
*
* @{
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -119,7 +165,7 @@ typedef struct {
*
*/
- /** I2C Device Address 8 bit format**/
+/** I2C Device Address 8 bit format**/
#define LSM303AGR_I2C_ADD_XL 0x33U
#define LSM303AGR_I2C_ADD_MG 0x3DU
@@ -133,12 +179,21 @@ typedef struct {
*/
#define LSM303AGR_STATUS_REG_AUX_A 0x07U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t tda : 1;
uint8_t not_used_02 : 3;
uint8_t tor : 1;
uint8_t not_used_03 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_03 : 1;
+ uint8_t tor : 1;
+ uint8_t not_used_02 : 3;
+ uint8_t tda : 1;
+ uint8_t not_used_01 : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm303agr_status_reg_aux_a_t;
#define LSM303AGR_OUT_TEMP_L_A 0x0CU
@@ -147,30 +202,57 @@ typedef struct {
#define LSM303AGR_WHO_AM_I_A 0x0FU
#define LSM303AGR_TEMP_CFG_REG_A 0x1FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 6;
uint8_t temp_en : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t temp_en : 2;
+ uint8_t not_used_01 : 6;
+#endif /* DRV_BYTE_ORDER */
} lsm303agr_temp_cfg_reg_a_t;
#define LSM303AGR_CTRL_REG1_A 0x20U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xen : 1;
uint8_t yen : 1;
uint8_t zen : 1;
uint8_t lpen : 1;
uint8_t odr : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr : 4;
+ uint8_t lpen : 1;
+ uint8_t zen : 1;
+ uint8_t yen : 1;
+ uint8_t xen : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303agr_ctrl_reg1_a_t;
#define LSM303AGR_CTRL_REG2_A 0x21U
-typedef struct {
- uint8_t hp : 3; /* HPCLICK + HPIS2 + HPIS1 -> HP */
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+uint8_t hp :
+ 3; /* HPCLICK + HPIS2 + HPIS1 -> HP */
uint8_t fds : 1;
uint8_t hpcf : 2;
uint8_t hpm : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t hpm : 2;
+ uint8_t hpcf : 2;
+ uint8_t fds : 1;
+uint8_t hp :
+ 3; /* HPCLICK + HPIS2 + HPIS1 -> HP */
+#endif /* DRV_BYTE_ORDER */
} lsm303agr_ctrl_reg2_a_t;
#define LSM303AGR_CTRL_REG3_A 0x22U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t i1_overrun : 1;
uint8_t i1_wtm : 1;
@@ -179,20 +261,42 @@ typedef struct {
uint8_t i1_aoi2 : 1;
uint8_t i1_aoi1 : 1;
uint8_t i1_click : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t i1_click : 1;
+ uint8_t i1_aoi1 : 1;
+ uint8_t i1_aoi2 : 1;
+ uint8_t i1_drdy1 : 1;
+ uint8_t i1_drdy2 : 1;
+ uint8_t i1_wtm : 1;
+ uint8_t i1_overrun : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303agr_ctrl_reg3_a_t;
#define LSM303AGR_CTRL_REG4_A 0x23U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t spi_enable : 1;
uint8_t st : 2;
uint8_t hr : 1;
uint8_t fs : 2;
uint8_t ble : 1;
uint8_t bdu : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bdu : 1;
+ uint8_t ble : 1;
+ uint8_t fs : 2;
+ uint8_t hr : 1;
+ uint8_t st : 2;
+ uint8_t spi_enable : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303agr_ctrl_reg4_a_t;
#define LSM303AGR_CTRL_REG5_A 0x24U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d4d_int2 : 1;
uint8_t lir_int2 : 1;
uint8_t d4d_int1 : 1;
@@ -200,10 +304,21 @@ typedef struct {
uint8_t not_used_01 : 2;
uint8_t fifo_en : 1;
uint8_t boot : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t boot : 1;
+ uint8_t fifo_en : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t lir_int1 : 1;
+ uint8_t d4d_int1 : 1;
+ uint8_t lir_int2 : 1;
+ uint8_t d4d_int2 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303agr_ctrl_reg5_a_t;
#define LSM303AGR_CTRL_REG6_A 0x25U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t h_lactive : 1;
uint8_t not_used_02 : 1;
@@ -212,11 +327,23 @@ typedef struct {
uint8_t i2_int2 : 1;
uint8_t i2_int1 : 1;
uint8_t i2_clicken : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t i2_clicken : 1;
+ uint8_t i2_int1 : 1;
+ uint8_t i2_int2 : 1;
+ uint8_t boot_i2 : 1;
+ uint8_t p2_act : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t h_lactive : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303agr_ctrl_reg6_a_t;
#define LSM303AGR_REFERENCE_A 0x26U
#define LSM303AGR_STATUS_REG_A 0x27U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xda : 1;
uint8_t yda : 1;
uint8_t zda : 1;
@@ -225,6 +352,16 @@ typedef struct {
uint8_t yor : 1;
uint8_t zor : 1;
uint8_t zyxor : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t zyxor : 1;
+ uint8_t zor : 1;
+ uint8_t yor : 1;
+ uint8_t _xor : 1;
+ uint8_t zyxda : 1;
+ uint8_t zda : 1;
+ uint8_t yda : 1;
+ uint8_t xda : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303agr_status_reg_a_t;
#define LSM303AGR_OUT_X_L_A 0x28U
@@ -234,22 +371,39 @@ typedef struct {
#define LSM303AGR_OUT_Z_L_A 0x2CU
#define LSM303AGR_OUT_Z_H_A 0x2DU
#define LSM303AGR_FIFO_CTRL_REG_A 0x2EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fth : 5;
uint8_t tr : 1;
uint8_t fm : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fm : 2;
+ uint8_t tr : 1;
+ uint8_t fth : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm303agr_fifo_ctrl_reg_a_t;
#define LSM303AGR_FIFO_SRC_REG_A 0x2FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fss : 5;
uint8_t empty : 1;
uint8_t ovrn_fifo : 1;
uint8_t wtm : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t wtm : 1;
+ uint8_t ovrn_fifo : 1;
+ uint8_t empty : 1;
+ uint8_t fss : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm303agr_fifo_src_reg_a_t;
#define LSM303AGR_INT1_CFG_A 0x30U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlie : 1; /* or XDOWNE */
uint8_t xhie : 1; /* or XUPE */
uint8_t ylie : 1; /* or YDOWNE */
@@ -258,10 +412,22 @@ typedef struct {
uint8_t zhie : 1; /* or ZUPE */
uint8_t _6d : 1;
uint8_t aoi : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t aoi : 1;
+ uint8_t _6d : 1;
+ uint8_t zhie : 1; /* or ZUPE */
+ uint8_t zlie : 1; /* or ZDOWNE */
+ uint8_t yhie : 1; /* or YUPE */
+ uint8_t ylie : 1; /* or YDOWNE */
+ uint8_t xhie : 1; /* or XUPE */
+ uint8_t xlie : 1; /* or XDOWNE */
+#endif /* DRV_BYTE_ORDER */
} lsm303agr_int1_cfg_a_t;
#define LSM303AGR_INT1_SRC_A 0x31U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
uint8_t yl : 1;
@@ -270,22 +436,46 @@ typedef struct {
uint8_t zh : 1;
uint8_t ia : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t ia : 1;
+ uint8_t zh : 1;
+ uint8_t zl : 1;
+ uint8_t yh : 1;
+ uint8_t yl : 1;
+ uint8_t xh : 1;
+ uint8_t xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303agr_int1_src_a_t;
#define LSM303AGR_INT1_THS_A 0x32U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t ths : 7;
+#endif /* DRV_BYTE_ORDER */
} lsm303agr_int1_ths_a_t;
#define LSM303AGR_INT1_DURATION_A 0x33U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d : 7;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t d : 7;
+#endif /* DRV_BYTE_ORDER */
} lsm303agr_int1_duration_a_t;
#define LSM303AGR_INT2_CFG_A 0x34U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlie : 1;
uint8_t xhie : 1;
uint8_t ylie : 1;
@@ -294,10 +484,22 @@ typedef struct {
uint8_t zhie : 1;
uint8_t _6d : 1;
uint8_t aoi : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t aoi : 1;
+ uint8_t _6d : 1;
+ uint8_t zhie : 1;
+ uint8_t zlie : 1;
+ uint8_t yhie : 1;
+ uint8_t ylie : 1;
+ uint8_t xhie : 1;
+ uint8_t xlie : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303agr_int2_cfg_a_t;
#define LSM303AGR_INT2_SRC_A 0x35U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
uint8_t yl : 1;
@@ -306,22 +508,46 @@ typedef struct {
uint8_t zh : 1;
uint8_t ia : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t ia : 1;
+ uint8_t zh : 1;
+ uint8_t zl : 1;
+ uint8_t yh : 1;
+ uint8_t yl : 1;
+ uint8_t xh : 1;
+ uint8_t xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303agr_int2_src_a_t;
#define LSM303AGR_INT2_THS_A 0x36U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t ths : 7;
+#endif /* DRV_BYTE_ORDER */
} lsm303agr_int2_ths_a_t;
#define LSM303AGR_INT2_DURATION_A 0x37U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t d : 7;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t d : 7;
+#endif /* DRV_BYTE_ORDER */
} lsm303agr_int2_duration_a_t;
#define LSM303AGR_CLICK_CFG_A 0x38U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xs : 1;
uint8_t xd : 1;
uint8_t ys : 1;
@@ -329,10 +555,21 @@ typedef struct {
uint8_t zs : 1;
uint8_t zd : 1;
uint8_t not_used_01 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 2;
+ uint8_t zd : 1;
+ uint8_t zs : 1;
+ uint8_t yd : 1;
+ uint8_t ys : 1;
+ uint8_t xd : 1;
+ uint8_t xs : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303agr_click_cfg_a_t;
#define LSM303AGR_CLICK_SRC_A 0x39U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t x : 1;
uint8_t y : 1;
uint8_t z : 1;
@@ -341,38 +578,69 @@ typedef struct {
uint8_t dclick : 1;
uint8_t ia : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t ia : 1;
+ uint8_t dclick : 1;
+ uint8_t sclick : 1;
+ uint8_t sign : 1;
+ uint8_t z : 1;
+ uint8_t y : 1;
+ uint8_t x : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303agr_click_src_a_t;
#define LSM303AGR_CLICK_THS_A 0x3AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t ths : 7;
+#endif /* DRV_BYTE_ORDER */
} lsm303agr_click_ths_a_t;
#define LSM303AGR_TIME_LIMIT_A 0x3BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tli : 7;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t tli : 7;
+#endif /* DRV_BYTE_ORDER */
} lsm303agr_time_limit_a_t;
#define LSM303AGR_TIME_LATENCY_A 0x3CU
-typedef struct {
+typedef struct
+{
uint8_t tla : 8;
} lsm303agr_time_latency_a_t;
#define LSM303AGR_TIME_WINDOW_A 0x3DU
-typedef struct {
+typedef struct
+{
uint8_t tw : 8;
} lsm303agr_time_window_a_t;
#define LSM303AGR_ACT_THS_A 0x3EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t acth : 7;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t acth : 7;
+#endif /* DRV_BYTE_ORDER */
} lsm303agr_act_ths_a_t;
#define LSM303AGR_ACT_DUR_A 0x3FU
-typedef struct {
+typedef struct
+{
uint8_t actd : 8;
} lsm303agr_act_dur_a_t;
@@ -384,26 +652,47 @@ typedef struct {
#define LSM303AGR_OFFSET_Z_REG_H_M 0x4AU
#define LSM303AGR_WHO_AM_I_M 0x4FU
#define LSM303AGR_CFG_REG_A_M 0x60U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t md : 2;
uint8_t odr : 2;
uint8_t lp : 1;
uint8_t soft_rst : 1;
uint8_t reboot : 1;
uint8_t comp_temp_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t comp_temp_en : 1;
+ uint8_t reboot : 1;
+ uint8_t soft_rst : 1;
+ uint8_t lp : 1;
+ uint8_t odr : 2;
+ uint8_t md : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm303agr_cfg_reg_a_m_t;
#define LSM303AGR_CFG_REG_B_M 0x61U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lpf : 1;
uint8_t set_rst : 2; /* OFF_CANC + Set_FREQ */
uint8_t int_on_dataoff : 1;
uint8_t off_canc_one_shot : 1;
uint8_t not_used_01 : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 3;
+ uint8_t off_canc_one_shot : 1;
+ uint8_t int_on_dataoff : 1;
+ uint8_t set_rst : 2; /* OFF_CANC + Set_FREQ */
+ uint8_t lpf : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303agr_cfg_reg_b_m_t;
#define LSM303AGR_CFG_REG_C_M 0x62U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int_mag : 1;
uint8_t self_test : 1;
uint8_t not_used_01 : 1;
@@ -412,10 +701,22 @@ typedef struct {
uint8_t i2c_dis : 1;
uint8_t int_mag_pin : 1;
uint8_t not_used_02 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 1;
+ uint8_t int_mag_pin : 1;
+ uint8_t i2c_dis : 1;
+ uint8_t bdu : 1;
+ uint8_t ble : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t self_test : 1;
+ uint8_t int_mag : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303agr_cfg_reg_c_m_t;
#define LSM303AGR_INT_CRTL_REG_M 0x63U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ien : 1;
uint8_t iel : 1;
uint8_t iea : 1;
@@ -423,11 +724,22 @@ typedef struct {
uint8_t zien : 1;
uint8_t yien : 1;
uint8_t xien : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t xien : 1;
+ uint8_t yien : 1;
+ uint8_t zien : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t iea : 1;
+ uint8_t iel : 1;
+ uint8_t ien : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303agr_int_crtl_reg_m_t;
#define LSM303AGR_INT_SOURCE_REG_M 0x64U
-typedef struct {
- uint8_t _int : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t _int : 1;
uint8_t mroi : 1;
uint8_t n_th_s_z : 1;
uint8_t n_th_s_y : 1;
@@ -435,12 +747,24 @@ typedef struct {
uint8_t p_th_s_z : 1;
uint8_t p_th_s_y : 1;
uint8_t p_th_s_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_th_s_x : 1;
+ uint8_t p_th_s_y : 1;
+ uint8_t p_th_s_z : 1;
+ uint8_t n_th_s_x : 1;
+ uint8_t n_th_s_y : 1;
+ uint8_t n_th_s_z : 1;
+ uint8_t mroi : 1;
+ uint8_t _int : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303agr_int_source_reg_m_t;
#define LSM303AGR_INT_THS_L_REG_M 0x65U
#define LSM303AGR_INT_THS_H_REG_M 0x66U
#define LSM303AGR_STATUS_REG_M 0x67U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xda : 1;
uint8_t yda : 1;
uint8_t zda : 1;
@@ -449,6 +773,16 @@ typedef struct {
uint8_t yor : 1;
uint8_t zor : 1;
uint8_t zyxor : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t zyxor : 1;
+ uint8_t zor : 1;
+ uint8_t yor : 1;
+ uint8_t _xor : 1;
+ uint8_t zyxda : 1;
+ uint8_t zda : 1;
+ uint8_t yda : 1;
+ uint8_t xda : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303agr_status_reg_m_t;
#define LSM303AGR_OUTX_L_REG_M 0x68U
@@ -460,9 +794,9 @@ typedef struct {
/**
* @defgroup LSM303AGR_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -470,7 +804,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
lsm303agr_status_reg_aux_a_t status_reg_aux_a;
lsm303agr_temp_cfg_reg_a_t temp_cfg_reg_a;
lsm303agr_ctrl_reg1_a_t ctrl_reg1_a;
@@ -513,40 +848,46 @@ typedef union{
*
*/
-int32_t lsm303agr_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lsm303agr_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t lsm303agr_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
- uint16_t len);
-
-extern float_t lsm303agr_from_fs_2g_hr_to_mg(int16_t lsb);
-extern float_t lsm303agr_from_fs_4g_hr_to_mg(int16_t lsb);
-extern float_t lsm303agr_from_fs_8g_hr_to_mg(int16_t lsb);
-extern float_t lsm303agr_from_fs_16g_hr_to_mg(int16_t lsb);
-extern float_t lsm303agr_from_lsb_hr_to_celsius(int16_t lsb);
-
-extern float_t lsm303agr_from_fs_2g_nm_to_mg(int16_t lsb);
-extern float_t lsm303agr_from_fs_4g_nm_to_mg(int16_t lsb);
-extern float_t lsm303agr_from_fs_8g_nm_to_mg(int16_t lsb);
-extern float_t lsm303agr_from_fs_16g_nm_to_mg(int16_t lsb);
-extern float_t lsm303agr_from_lsb_nm_to_celsius(int16_t lsb);
-
-extern float_t lsm303agr_from_fs_2g_lp_to_mg(int16_t lsb);
-extern float_t lsm303agr_from_fs_4g_lp_to_mg(int16_t lsb);
-extern float_t lsm303agr_from_fs_8g_lp_to_mg(int16_t lsb);
-extern float_t lsm303agr_from_fs_16g_lp_to_mg(int16_t lsb);
-extern float_t lsm303agr_from_lsb_lp_to_celsius(int16_t lsb);
-
-extern float_t lsm303agr_from_lsb_to_mgauss(int16_t lsb);
-
-int32_t lsm303agr_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm303agr_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len);
+
+float_t lsm303agr_from_fs_2g_hr_to_mg(int16_t lsb);
+float_t lsm303agr_from_fs_4g_hr_to_mg(int16_t lsb);
+float_t lsm303agr_from_fs_8g_hr_to_mg(int16_t lsb);
+float_t lsm303agr_from_fs_16g_hr_to_mg(int16_t lsb);
+float_t lsm303agr_from_lsb_hr_to_celsius(int16_t lsb);
+
+float_t lsm303agr_from_fs_2g_nm_to_mg(int16_t lsb);
+float_t lsm303agr_from_fs_4g_nm_to_mg(int16_t lsb);
+float_t lsm303agr_from_fs_8g_nm_to_mg(int16_t lsb);
+float_t lsm303agr_from_fs_16g_nm_to_mg(int16_t lsb);
+float_t lsm303agr_from_lsb_nm_to_celsius(int16_t lsb);
+
+float_t lsm303agr_from_fs_2g_lp_to_mg(int16_t lsb);
+float_t lsm303agr_from_fs_4g_lp_to_mg(int16_t lsb);
+float_t lsm303agr_from_fs_8g_lp_to_mg(int16_t lsb);
+float_t lsm303agr_from_fs_16g_lp_to_mg(int16_t lsb);
+float_t lsm303agr_from_lsb_lp_to_celsius(int16_t lsb);
+
+float_t lsm303agr_from_lsb_to_mgauss(int16_t lsb);
+
+int32_t lsm303agr_temp_status_reg_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
-int32_t lsm303agr_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm303agr_temp_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm303agr_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm303agr_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm303agr_temperature_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
-typedef enum {
+typedef enum
+{
LSM303AGR_TEMP_DISABLE = 0,
LSM303AGR_TEMP_ENABLE = 3,
} lsm303agr_temp_en_a_t;
@@ -555,7 +896,8 @@ int32_t lsm303agr_temperature_meas_set(stmdev_ctx_t *ctx,
int32_t lsm303agr_temperature_meas_get(stmdev_ctx_t *ctx,
lsm303agr_temp_en_a_t *val);
-typedef enum {
+typedef enum
+{
LSM303AGR_HR_12bit = 0,
LSM303AGR_NM_10bit = 1,
LSM303AGR_LP_8bit = 2,
@@ -565,7 +907,8 @@ int32_t lsm303agr_xl_operating_mode_set(stmdev_ctx_t *ctx,
int32_t lsm303agr_xl_operating_mode_get(stmdev_ctx_t *ctx,
lsm303agr_op_md_a_t *val);
-typedef enum {
+typedef enum
+{
LSM303AGR_XL_POWER_DOWN = 0,
LSM303AGR_XL_ODR_1Hz = 1,
LSM303AGR_XL_ODR_10Hz = 2,
@@ -587,7 +930,8 @@ int32_t lsm303agr_xl_high_pass_on_outputs_set(stmdev_ctx_t *ctx,
int32_t lsm303agr_xl_high_pass_on_outputs_get(stmdev_ctx_t *ctx,
uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM303AGR_AGGRESSIVE = 0,
LSM303AGR_STRONG = 1,
LSM303AGR_MEDIUM = 2,
@@ -598,7 +942,8 @@ int32_t lsm303agr_xl_high_pass_bandwidth_set(stmdev_ctx_t *ctx,
int32_t lsm303agr_xl_high_pass_bandwidth_get(stmdev_ctx_t *ctx,
lsm303agr_hpcf_a_t *val);
-typedef enum {
+typedef enum
+{
LSM303AGR_NORMAL_WITH_RST = 0,
LSM303AGR_REFERENCE_MODE = 1,
LSM303AGR_NORMAL = 2,
@@ -609,7 +954,8 @@ int32_t lsm303agr_xl_high_pass_mode_set(stmdev_ctx_t *ctx,
int32_t lsm303agr_xl_high_pass_mode_get(stmdev_ctx_t *ctx,
lsm303agr_hpm_a_t *val);
-typedef enum {
+typedef enum
+{
LSM303AGR_2g = 0,
LSM303AGR_4g = 1,
LSM303AGR_8g = 2,
@@ -634,11 +980,13 @@ int32_t lsm303agr_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm303agr_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm303agr_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm303agr_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
int32_t lsm303agr_xl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
-typedef enum {
+typedef enum
+{
LSM303AGR_ST_DISABLE = 0,
LSM303AGR_ST_POSITIVE = 1,
LSM303AGR_ST_NEGATIVE = 2,
@@ -648,7 +996,8 @@ int32_t lsm303agr_xl_self_test_set(stmdev_ctx_t *ctx,
int32_t lsm303agr_xl_self_test_get(stmdev_ctx_t *ctx,
lsm303agr_st_a_t *val);
-typedef enum {
+typedef enum
+{
LSM303AGR_XL_LSB_AT_LOW_ADD = 0,
LSM303AGR_XL_MSB_AT_LOW_ADD = 1,
} lsm303agr_ble_a_t;
@@ -699,7 +1048,8 @@ int32_t lsm303agr_xl_int2_gen_duration_set(stmdev_ctx_t *ctx,
int32_t lsm303agr_xl_int2_gen_duration_get(stmdev_ctx_t *ctx,
uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM303AGR_DISC_FROM_INT_GENERATOR = 0,
LSM303AGR_ON_INT1_GEN = 1,
LSM303AGR_ON_INT2_GEN = 2,
@@ -724,7 +1074,8 @@ int32_t lsm303agr_xl_int2_pin_detect_4d_set(stmdev_ctx_t *ctx,
int32_t lsm303agr_xl_int2_pin_detect_4d_get(stmdev_ctx_t *ctx,
uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM303AGR_INT2_PULSED = 0,
LSM303AGR_INT2_LATCHED = 1,
} lsm303agr_lir_int2_a_t;
@@ -738,7 +1089,8 @@ int32_t lsm303agr_xl_int1_pin_detect_4d_set(stmdev_ctx_t *ctx,
int32_t lsm303agr_xl_int1_pin_detect_4d_get(stmdev_ctx_t *ctx,
uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM303AGR_INT1_PULSED = 0,
LSM303AGR_INT1_LATCHED = 1,
} lsm303agr_lir_int1_a_t;
@@ -755,10 +1107,13 @@ int32_t lsm303agr_xl_pin_int2_config_get(stmdev_ctx_t *ctx,
int32_t lsm303agr_xl_fifo_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm303agr_xl_fifo_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm303agr_xl_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm303agr_xl_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm303agr_xl_fifo_watermark_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm303agr_xl_fifo_watermark_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM303AGR_INT1_GEN = 0,
LSM303AGR_INT2_GEN = 1,
} lsm303agr_tr_a_t;
@@ -767,7 +1122,8 @@ int32_t lsm303agr_xl_fifo_trigger_event_set(stmdev_ctx_t *ctx,
int32_t lsm303agr_xl_fifo_trigger_event_get(stmdev_ctx_t *ctx,
lsm303agr_tr_a_t *val);
-typedef enum {
+typedef enum
+{
LSM303AGR_BYPASS_MODE = 0,
LSM303AGR_FIFO_MODE = 1,
LSM303AGR_DYNAMIC_STREAM_MODE = 2,
@@ -781,13 +1137,17 @@ int32_t lsm303agr_xl_fifo_mode_get(stmdev_ctx_t *ctx,
int32_t lsm303agr_xl_fifo_status_get(stmdev_ctx_t *ctx,
lsm303agr_fifo_src_reg_a_t *val);
-int32_t lsm303agr_xl_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm303agr_xl_fifo_data_level_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm303agr_xl_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm303agr_xl_fifo_empty_flag_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm303agr_xl_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm303agr_xl_fifo_ovr_flag_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm303agr_xl_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm303agr_xl_fifo_fth_flag_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm303agr_tap_conf_set(stmdev_ctx_t *ctx,
lsm303agr_click_cfg_a_t *val);
@@ -795,7 +1155,7 @@ int32_t lsm303agr_tap_conf_get(stmdev_ctx_t *ctx,
lsm303agr_click_cfg_a_t *val);
int32_t lsm303agr_tap_source_get(stmdev_ctx_t *ctx,
- lsm303agr_click_src_a_t *val);
+ lsm303agr_click_src_a_t *val);
int32_t lsm303agr_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm303agr_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -817,7 +1177,8 @@ int32_t lsm303agr_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm303agr_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm303agr_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM303AGR_SPI_4_WIRE = 0,
LSM303AGR_SPI_3_WIRE = 1,
} lsm303agr_sim_a_t;
@@ -827,11 +1188,12 @@ int32_t lsm303agr_xl_spi_mode_get(stmdev_ctx_t *ctx,
lsm303agr_sim_a_t *val);
int32_t lsm303agr_mag_user_offset_set(stmdev_ctx_t *ctx,
- uint8_t *buff);
+ int16_t *val);
int32_t lsm303agr_mag_user_offset_get(stmdev_ctx_t *ctx,
- uint8_t *buff);
+ int16_t *val);
-typedef enum {
+typedef enum
+{
LSM303AGR_CONTINUOUS_MODE = 0,
LSM303AGR_SINGLE_TRIGGER = 1,
LSM303AGR_POWER_DOWN = 2,
@@ -841,7 +1203,8 @@ int32_t lsm303agr_mag_operating_mode_set(stmdev_ctx_t *ctx,
int32_t lsm303agr_mag_operating_mode_get(stmdev_ctx_t *ctx,
lsm303agr_md_m_t *val);
-typedef enum {
+typedef enum
+{
LSM303AGR_MG_ODR_10Hz = 0,
LSM303AGR_MG_ODR_20Hz = 1,
LSM303AGR_MG_ODR_50Hz = 2,
@@ -852,7 +1215,8 @@ int32_t lsm303agr_mag_data_rate_set(stmdev_ctx_t *ctx,
int32_t lsm303agr_mag_data_rate_get(stmdev_ctx_t *ctx,
lsm303agr_mg_odr_m_t *val);
-typedef enum {
+typedef enum
+{
LSM303AGR_HIGH_RESOLUTION = 0,
LSM303AGR_LOW_POWER = 1,
} lsm303agr_lp_m_t;
@@ -866,7 +1230,8 @@ int32_t lsm303agr_mag_offset_temp_comp_set(stmdev_ctx_t *ctx,
int32_t lsm303agr_mag_offset_temp_comp_get(stmdev_ctx_t *ctx,
uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM303AGR_ODR_DIV_2 = 0,
LSM303AGR_ODR_DIV_4 = 1,
} lsm303agr_lpf_m_t;
@@ -875,7 +1240,8 @@ int32_t lsm303agr_mag_low_pass_bandwidth_set(stmdev_ctx_t *ctx,
int32_t lsm303agr_mag_low_pass_bandwidth_get(stmdev_ctx_t *ctx,
lsm303agr_lpf_m_t *val);
-typedef enum {
+typedef enum
+{
LSM303AGR_SET_SENS_ODR_DIV_63 = 0,
LSM303AGR_SENS_OFF_CANC_EVERY_ODR = 1,
LSM303AGR_SET_SENS_ONLY_AT_POWER_ON = 2,
@@ -899,7 +1265,7 @@ int32_t lsm303agr_mag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm303agr_mag_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm303agr_magnetic_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm303agr_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val);
int32_t lsm303agr_mag_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
@@ -914,7 +1280,8 @@ int32_t lsm303agr_mag_self_test_set(stmdev_ctx_t *ctx,
int32_t lsm303agr_mag_self_test_get(stmdev_ctx_t *ctx,
uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM303AGR_MG_LSB_AT_LOW_ADD = 0,
LSM303AGR_MG_MSB_AT_LOW_ADD = 1,
} lsm303agr_ble_m_t;
@@ -926,7 +1293,8 @@ int32_t lsm303agr_mag_data_format_get(stmdev_ctx_t *ctx,
int32_t lsm303agr_mag_status_get(stmdev_ctx_t *ctx,
lsm303agr_status_reg_m_t *val);
-typedef enum {
+typedef enum
+{
LSM303AGR_CHECK_BEFORE = 0,
LSM303AGR_CHECK_AFTER = 1,
} lsm303agr_int_on_dataoff_m_t;
@@ -936,7 +1304,8 @@ int32_t lsm303agr_mag_offset_int_conf_get(stmdev_ctx_t *ctx,
lsm303agr_int_on_dataoff_m_t *val);
int32_t lsm303agr_mag_drdy_on_pin_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm303agr_mag_drdy_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm303agr_mag_drdy_on_pin_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm303agr_mag_int_on_pin_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm303agr_mag_int_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -950,10 +1319,12 @@ int32_t lsm303agr_mag_int_gen_source_get(stmdev_ctx_t *ctx,
lsm303agr_int_source_reg_m_t *val);
int32_t lsm303agr_mag_int_gen_treshold_set(stmdev_ctx_t *ctx,
- uint8_t *buff);
+ int16_t val);
int32_t lsm303agr_mag_int_gen_treshold_get(stmdev_ctx_t *ctx,
- uint8_t *buff);
-typedef enum {
+ int16_t *val);
+
+typedef enum
+{
LSM303AGR_I2C_ENABLE = 0,
LSM303AGR_I2C_DISABLE = 1,
} lsm303agr_i2c_dis_m_t;
diff --git a/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.c b/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.c
index e0a1168d6429122751ee18704f750aa881a559b8..c572d22afe2bd8e6358a1b4957e6725547ff2cdd 100644
--- a/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.c
+++ b/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file lsm303ah_reg.c
- * @author Sensors Software Solution Team
- * @brief LSM303AH driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lsm303ah_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LSM303AH driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lsm303ah_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm303ah_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lsm303ah_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t lsm303ah_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm303ah_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t lsm303ah_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -136,35 +142,47 @@ float_t lsm303ah_from_lsb_to_celsius(int16_t lsb)
*
*/
int32_t lsm303ah_xl_all_sources_get(stmdev_ctx_t *ctx,
- lsm303ah_xl_all_sources_t *val)
+ lsm303ah_xl_all_sources_t *val)
{
int32_t ret;
ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_SRC_A,
- (uint8_t*)&(val->fifo_src_a), 1);
- if(ret == 0){
+ (uint8_t *) & (val->fifo_src_a), 1);
+
+ if (ret == 0)
+ {
ret = lsm303ah_read_reg(ctx, LSM303AH_STATUS_DUP_A,
- (uint8_t*)&(val->status_dup_a), 1);
+ (uint8_t *) & (val->status_dup_a), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_SRC_A,
- (uint8_t*)&(val->wake_up_src_a), 1);
+ (uint8_t *) & (val->wake_up_src_a), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm303ah_read_reg(ctx, LSM303AH_TAP_SRC_A,
- (uint8_t*)&(val->tap_src_a), 1);
+ (uint8_t *) & (val->tap_src_a), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm303ah_read_reg(ctx, LSM303AH_6D_SRC_A,
- (uint8_t*)&(val->_6d_src_a), 1);
+ (uint8_t *) & (val->_6d_src_a), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm303ah_read_reg(ctx, LSM303AH_FUNC_CK_GATE_A,
- (uint8_t*)&(val->func_ck_gate_a), 1);
+ (uint8_t *) & (val->func_ck_gate_a), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm303ah_read_reg(ctx, LSM303AH_FUNC_SRC_A,
- (uint8_t*)&(val->func_src_a), 1);
+ (uint8_t *) & (val->func_src_a), 1);
}
return ret;
@@ -178,15 +196,18 @@ int32_t lsm303ah_xl_all_sources_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm303ah_xl_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm303ah_ctrl1_a_t ctrl1_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL1_A, (uint8_t*)&ctrl1_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL1_A, (uint8_t *)&ctrl1_a, 1);
+
+ if (ret == 0)
+ {
ctrl1_a.bdu = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL1_A, (uint8_t*)&ctrl1_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL1_A, (uint8_t *)&ctrl1_a, 1);
}
return ret;
@@ -200,12 +221,13 @@ int32_t lsm303ah_xl_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm303ah_xl_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm303ah_ctrl1_a_t ctrl1_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL1_A, (uint8_t*)&ctrl1_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL1_A, (uint8_t *)&ctrl1_a, 1);
*val = ctrl1_a.bdu;
return ret;
@@ -219,15 +241,20 @@ int32_t lsm303ah_xl_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_mg_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm303ah_mg_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm303ah_cfg_reg_c_m_t cfg_reg_c_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_C_M, (uint8_t*)&cfg_reg_c_m, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_C_M,
+ (uint8_t *)&cfg_reg_c_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_c_m.bdu = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_C_M, (uint8_t*)&cfg_reg_c_m, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_C_M,
+ (uint8_t *)&cfg_reg_c_m, 1);
}
return ret;
@@ -241,12 +268,14 @@ int32_t lsm303ah_mg_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_mg_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm303ah_mg_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm303ah_cfg_reg_c_m_t cfg_reg_c_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_C_M, (uint8_t*)&cfg_reg_c_m, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_C_M,
+ (uint8_t *)&cfg_reg_c_m, 1);
*val = cfg_reg_c_m.bdu;
return ret;
@@ -260,15 +289,20 @@ int32_t lsm303ah_mg_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_mg_data_format_set(stmdev_ctx_t *ctx, lsm303ah_mg_ble_t val)
+int32_t lsm303ah_mg_data_format_set(stmdev_ctx_t *ctx,
+ lsm303ah_mg_ble_t val)
{
lsm303ah_cfg_reg_c_m_t cfg_reg_c_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_C_M, (uint8_t*)&cfg_reg_c_m, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_C_M,
+ (uint8_t *)&cfg_reg_c_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_c_m.ble = (uint8_t)val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_C_M, (uint8_t*)&cfg_reg_c_m, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_C_M,
+ (uint8_t *)&cfg_reg_c_m, 1);
}
return ret;
@@ -288,18 +322,24 @@ int32_t lsm303ah_mg_data_format_get(stmdev_ctx_t *ctx,
lsm303ah_cfg_reg_c_m_t cfg_reg_c_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_C_M, (uint8_t*)&cfg_reg_c_m, 1);
- switch (cfg_reg_c_m.ble){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_C_M,
+ (uint8_t *)&cfg_reg_c_m, 1);
+
+ switch (cfg_reg_c_m.ble)
+ {
case LSM303AH_MG_LSB_AT_LOW_ADD:
*val = LSM303AH_MG_LSB_AT_LOW_ADD;
break;
+
case LSM303AH_MG_MSB_AT_LOW_ADD:
*val = LSM303AH_MG_MSB_AT_LOW_ADD;
break;
+
default:
*val = LSM303AH_MG_LSB_AT_LOW_ADD;
break;
}
+
return ret;
}
@@ -311,15 +351,18 @@ int32_t lsm303ah_mg_data_format_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_full_scale_set(stmdev_ctx_t *ctx, lsm303ah_xl_fs_t val)
+int32_t lsm303ah_xl_full_scale_set(stmdev_ctx_t *ctx,
+ lsm303ah_xl_fs_t val)
{
lsm303ah_ctrl1_a_t ctrl1_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL1_A, (uint8_t*)&ctrl1_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL1_A, (uint8_t *)&ctrl1_a, 1);
+
+ if (ret == 0)
+ {
ctrl1_a.fs = (uint8_t)val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL1_A, (uint8_t*)&ctrl1_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL1_A, (uint8_t *)&ctrl1_a, 1);
}
return ret;
@@ -333,29 +376,37 @@ int32_t lsm303ah_xl_full_scale_set(stmdev_ctx_t *ctx, lsm303ah_xl_fs_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_full_scale_get(stmdev_ctx_t *ctx, lsm303ah_xl_fs_t *val)
+int32_t lsm303ah_xl_full_scale_get(stmdev_ctx_t *ctx,
+ lsm303ah_xl_fs_t *val)
{
lsm303ah_ctrl1_a_t ctrl1_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL1_A, (uint8_t*)&ctrl1_a, 1);
- switch (ctrl1_a.fs){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL1_A, (uint8_t *)&ctrl1_a, 1);
+
+ switch (ctrl1_a.fs)
+ {
case LSM303AH_XL_2g:
*val = LSM303AH_XL_2g;
break;
+
case LSM303AH_XL_16g:
*val = LSM303AH_XL_16g;
break;
+
case LSM303AH_XL_4g:
*val = LSM303AH_XL_4g;
break;
+
case LSM303AH_XL_8g:
*val = LSM303AH_XL_8g;
break;
+
default:
*val = LSM303AH_XL_2g;
break;
}
+
return ret;
}
@@ -367,16 +418,19 @@ int32_t lsm303ah_xl_full_scale_get(stmdev_ctx_t *ctx, lsm303ah_xl_fs_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_data_rate_set(stmdev_ctx_t *ctx, lsm303ah_xl_odr_t val)
+int32_t lsm303ah_xl_data_rate_set(stmdev_ctx_t *ctx,
+ lsm303ah_xl_odr_t val)
{
lsm303ah_ctrl1_a_t ctrl1_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL1_A, (uint8_t*)&ctrl1_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL1_A, (uint8_t *)&ctrl1_a, 1);
+
+ if (ret == 0)
+ {
ctrl1_a.odr = (uint8_t)val & 0x0FU;
ctrl1_a.hf_odr = ((uint8_t)val & 0x10U) >> 4;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL1_A, (uint8_t*)&ctrl1_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL1_A, (uint8_t *)&ctrl1_a, 1);
}
return ret;
@@ -390,74 +444,97 @@ int32_t lsm303ah_xl_data_rate_set(stmdev_ctx_t *ctx, lsm303ah_xl_odr_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_data_rate_get(stmdev_ctx_t *ctx, lsm303ah_xl_odr_t *val)
+int32_t lsm303ah_xl_data_rate_get(stmdev_ctx_t *ctx,
+ lsm303ah_xl_odr_t *val)
{
lsm303ah_ctrl1_a_t ctrl1_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL1_A, (uint8_t*)&ctrl1_a, 1);
- switch ((ctrl1_a.hf_odr << 4) + ctrl1_a.odr){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL1_A, (uint8_t *)&ctrl1_a, 1);
+
+ switch ((ctrl1_a.hf_odr << 4) + ctrl1_a.odr)
+ {
case LSM303AH_XL_ODR_OFF:
*val = LSM303AH_XL_ODR_OFF;
break;
+
case LSM303AH_XL_ODR_1Hz_LP:
*val = LSM303AH_XL_ODR_1Hz_LP;
break;
+
case LSM303AH_XL_ODR_12Hz5_LP:
*val = LSM303AH_XL_ODR_12Hz5_LP;
break;
+
case LSM303AH_XL_ODR_25Hz_LP:
*val = LSM303AH_XL_ODR_25Hz_LP;
break;
+
case LSM303AH_XL_ODR_50Hz_LP:
*val = LSM303AH_XL_ODR_50Hz_LP;
break;
+
case LSM303AH_XL_ODR_100Hz_LP:
*val = LSM303AH_XL_ODR_100Hz_LP;
break;
+
case LSM303AH_XL_ODR_200Hz_LP:
*val = LSM303AH_XL_ODR_200Hz_LP;
break;
+
case LSM303AH_XL_ODR_400Hz_LP:
*val = LSM303AH_XL_ODR_400Hz_LP;
break;
+
case LSM303AH_XL_ODR_800Hz_LP:
*val = LSM303AH_XL_ODR_800Hz_LP;
break;
+
case LSM303AH_XL_ODR_12Hz5_HR:
*val = LSM303AH_XL_ODR_12Hz5_HR;
break;
+
case LSM303AH_XL_ODR_25Hz_HR:
*val = LSM303AH_XL_ODR_25Hz_HR;
break;
+
case LSM303AH_XL_ODR_50Hz_HR:
*val = LSM303AH_XL_ODR_50Hz_HR;
break;
+
case LSM303AH_XL_ODR_100Hz_HR:
*val = LSM303AH_XL_ODR_100Hz_HR;
break;
+
case LSM303AH_XL_ODR_200Hz_HR:
*val = LSM303AH_XL_ODR_200Hz_HR;
break;
+
case LSM303AH_XL_ODR_400Hz_HR:
*val = LSM303AH_XL_ODR_400Hz_HR;
break;
+
case LSM303AH_XL_ODR_800Hz_HR:
*val = LSM303AH_XL_ODR_800Hz_HR;
break;
+
case LSM303AH_XL_ODR_1k6Hz_HF:
*val = LSM303AH_XL_ODR_1k6Hz_HF;
break;
+
case LSM303AH_XL_ODR_3k2Hz_HF:
*val = LSM303AH_XL_ODR_3k2Hz_HF;
break;
+
case LSM303AH_XL_ODR_6k4Hz_HF:
*val = LSM303AH_XL_ODR_6k4Hz_HF;
break;
+
default:
*val = LSM303AH_XL_ODR_OFF;
break;
}
+
return ret;
}
@@ -473,7 +550,9 @@ int32_t lsm303ah_xl_status_reg_get(stmdev_ctx_t *ctx,
lsm303ah_status_a_t *val)
{
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_STATUS_A, (uint8_t*) val, 1);
+
+ ret = lsm303ah_read_reg(ctx, LSM303AH_STATUS_A, (uint8_t *) val, 1);
+
return ret;
}
@@ -489,7 +568,9 @@ int32_t lsm303ah_mg_status_get(stmdev_ctx_t *ctx,
lsm303ah_status_reg_m_t *val)
{
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_STATUS_REG_M, (uint8_t*) val, 1);
+
+ ret = lsm303ah_read_reg(ctx, LSM303AH_STATUS_REG_M, (uint8_t *) val, 1);
+
return ret;
}
@@ -501,12 +582,13 @@ int32_t lsm303ah_mg_status_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm303ah_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm303ah_status_a_t status_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_STATUS_A, (uint8_t*)&status_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_STATUS_A, (uint8_t *)&status_a, 1);
*val = status_a.drdy;
return ret;
@@ -525,7 +607,8 @@ int32_t lsm303ah_mg_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm303ah_status_reg_m_t status_reg_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_STATUS_REG_M, (uint8_t*)&status_reg_m, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_STATUS_REG_M,
+ (uint8_t *)&status_reg_m, 1);
*val = status_reg_m.zyxda;
return ret;
@@ -544,7 +627,8 @@ int32_t lsm303ah_mg_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm303ah_status_reg_m_t status_reg_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_STATUS_REG_M, (uint8_t*)&status_reg_m, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_STATUS_REG_M,
+ (uint8_t *)&status_reg_m, 1);
*val = status_reg_m.zyxor;
return ret;
@@ -562,10 +646,19 @@ int32_t lsm303ah_mg_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_mg_user_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm303ah_mg_user_offset_set(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
+ buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
+ buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
+ buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
+ buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
+ buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
+ buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
ret = lsm303ah_write_reg(ctx, LSM303AH_OFFSET_X_REG_L_M, buff, 6);
+
return ret;
}
@@ -581,10 +674,19 @@ int32_t lsm303ah_mg_user_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_mg_user_offset_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm303ah_mg_user_offset_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lsm303ah_read_reg(ctx, LSM303AH_OFFSET_X_REG_L_M, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -602,10 +704,14 @@ int32_t lsm303ah_mg_operating_mode_set(stmdev_ctx_t *ctx,
lsm303ah_cfg_reg_a_m_t cfg_reg_a_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_A_M, (uint8_t*)&cfg_reg_a_m, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_A_M,
+ (uint8_t *)&cfg_reg_a_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_a_m.md = (uint8_t)val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_A_M, (uint8_t*)&cfg_reg_a_m, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_A_M,
+ (uint8_t *)&cfg_reg_a_m, 1);
}
return ret;
@@ -625,21 +731,28 @@ int32_t lsm303ah_mg_operating_mode_get(stmdev_ctx_t *ctx,
lsm303ah_cfg_reg_a_m_t cfg_reg_a_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_A_M, (uint8_t*)&cfg_reg_a_m, 1);
- switch (cfg_reg_a_m.md){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_A_M,
+ (uint8_t *)&cfg_reg_a_m, 1);
+
+ switch (cfg_reg_a_m.md)
+ {
case LSM303AH_MG_CONTINUOUS_MODE:
*val = LSM303AH_MG_CONTINUOUS_MODE;
break;
+
case LSM303AH_MG_SINGLE_TRIGGER:
*val = LSM303AH_MG_SINGLE_TRIGGER;
break;
+
case LSM303AH_MG_POWER_DOWN:
*val = LSM303AH_MG_POWER_DOWN;
break;
+
default:
*val = LSM303AH_MG_CONTINUOUS_MODE;
break;
}
+
return ret;
}
@@ -651,15 +764,20 @@ int32_t lsm303ah_mg_operating_mode_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_mg_data_rate_set(stmdev_ctx_t *ctx, lsm303ah_mg_odr_t val)
+int32_t lsm303ah_mg_data_rate_set(stmdev_ctx_t *ctx,
+ lsm303ah_mg_odr_t val)
{
lsm303ah_cfg_reg_a_m_t cfg_reg_a_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_A_M, (uint8_t*)&cfg_reg_a_m, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_A_M,
+ (uint8_t *)&cfg_reg_a_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_a_m.odr = (uint8_t)val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_A_M, (uint8_t*)&cfg_reg_a_m, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_A_M,
+ (uint8_t *)&cfg_reg_a_m, 1);
}
return ret;
@@ -673,29 +791,38 @@ int32_t lsm303ah_mg_data_rate_set(stmdev_ctx_t *ctx, lsm303ah_mg_odr_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_mg_data_rate_get(stmdev_ctx_t *ctx, lsm303ah_mg_odr_t *val)
+int32_t lsm303ah_mg_data_rate_get(stmdev_ctx_t *ctx,
+ lsm303ah_mg_odr_t *val)
{
lsm303ah_cfg_reg_a_m_t cfg_reg_a_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_A_M, (uint8_t*)&cfg_reg_a_m, 1);
- switch (cfg_reg_a_m.odr){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_A_M,
+ (uint8_t *)&cfg_reg_a_m, 1);
+
+ switch (cfg_reg_a_m.odr)
+ {
case LSM303AH_MG_ODR_10Hz:
*val = LSM303AH_MG_ODR_10Hz;
break;
+
case LSM303AH_MG_ODR_20Hz:
*val = LSM303AH_MG_ODR_20Hz;
break;
+
case LSM303AH_MG_ODR_50Hz:
*val = LSM303AH_MG_ODR_50Hz;
break;
+
case LSM303AH_MG_ODR_100Hz:
*val = LSM303AH_MG_ODR_100Hz;
break;
+
default:
*val = LSM303AH_MG_ODR_10Hz;
break;
}
+
return ret;
}
@@ -707,15 +834,20 @@ int32_t lsm303ah_mg_data_rate_get(stmdev_ctx_t *ctx, lsm303ah_mg_odr_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_mg_power_mode_set(stmdev_ctx_t *ctx, lsm303ah_mg_lp_t val)
+int32_t lsm303ah_mg_power_mode_set(stmdev_ctx_t *ctx,
+ lsm303ah_mg_lp_t val)
{
lsm303ah_cfg_reg_a_m_t cfg_reg_a_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_A_M, (uint8_t*)&cfg_reg_a_m, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_A_M,
+ (uint8_t *)&cfg_reg_a_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_a_m.lp = (uint8_t)val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_A_M, (uint8_t*)&cfg_reg_a_m, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_A_M,
+ (uint8_t *)&cfg_reg_a_m, 1);
}
return ret;
@@ -729,19 +861,25 @@ int32_t lsm303ah_mg_power_mode_set(stmdev_ctx_t *ctx, lsm303ah_mg_lp_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_mg_power_mode_get(stmdev_ctx_t *ctx, lsm303ah_mg_lp_t *val)
+int32_t lsm303ah_mg_power_mode_get(stmdev_ctx_t *ctx,
+ lsm303ah_mg_lp_t *val)
{
lsm303ah_cfg_reg_a_m_t cfg_reg_a_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_A_M, (uint8_t*)&cfg_reg_a_m, 1);
- switch (cfg_reg_a_m.lp){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_A_M,
+ (uint8_t *)&cfg_reg_a_m, 1);
+
+ switch (cfg_reg_a_m.lp)
+ {
case LSM303AH_MG_HIGH_RESOLUTION:
*val = LSM303AH_MG_HIGH_RESOLUTION;
break;
+
case LSM303AH_MG_LOW_POWER:
*val = LSM303AH_MG_LOW_POWER;
break;
+
default:
*val = LSM303AH_MG_HIGH_RESOLUTION;
break;
@@ -758,15 +896,20 @@ int32_t lsm303ah_mg_power_mode_get(stmdev_ctx_t *ctx, lsm303ah_mg_lp_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_mg_offset_temp_comp_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm303ah_mg_offset_temp_comp_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm303ah_cfg_reg_a_m_t cfg_reg_a_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_A_M, (uint8_t*)&cfg_reg_a_m, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_A_M,
+ (uint8_t *)&cfg_reg_a_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_a_m.comp_temp_en = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_A_M, (uint8_t*)&cfg_reg_a_m, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_A_M,
+ (uint8_t *)&cfg_reg_a_m, 1);
}
return ret;
@@ -780,12 +923,14 @@ int32_t lsm303ah_mg_offset_temp_comp_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_mg_offset_temp_comp_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm303ah_mg_offset_temp_comp_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm303ah_cfg_reg_a_m_t cfg_reg_a_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_A_M, (uint8_t*)&cfg_reg_a_m, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_A_M,
+ (uint8_t *)&cfg_reg_a_m, 1);
*val = cfg_reg_a_m.comp_temp_en;
return ret;
@@ -805,10 +950,14 @@ int32_t lsm303ah_mg_set_rst_mode_set(stmdev_ctx_t *ctx,
lsm303ah_cfg_reg_b_m_t cfg_reg_b_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_B_M, (uint8_t*)&cfg_reg_b_m, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_B_M,
+ (uint8_t *)&cfg_reg_b_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_b_m.set_rst = (uint8_t)val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_B_M, (uint8_t*)&cfg_reg_b_m, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_B_M,
+ (uint8_t *)&cfg_reg_b_m, 1);
}
return ret;
@@ -828,21 +977,28 @@ int32_t lsm303ah_mg_set_rst_mode_get(stmdev_ctx_t *ctx,
lsm303ah_cfg_reg_b_m_t cfg_reg_b_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_B_M, (uint8_t*)&cfg_reg_b_m, 1);
- switch (cfg_reg_b_m.set_rst){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_B_M,
+ (uint8_t *)&cfg_reg_b_m, 1);
+
+ switch (cfg_reg_b_m.set_rst)
+ {
case LSM303AH_MG_SET_SENS_ODR_DIV_63:
*val = LSM303AH_MG_SET_SENS_ODR_DIV_63;
break;
+
case LSM303AH_MG_SENS_OFF_CANC_EVERY_ODR:
*val = LSM303AH_MG_SENS_OFF_CANC_EVERY_ODR;
break;
+
case LSM303AH_MG_SET_SENS_ONLY_AT_POWER_ON:
*val = LSM303AH_MG_SET_SENS_ONLY_AT_POWER_ON;
break;
+
default:
*val = LSM303AH_MG_SET_SENS_ODR_DIV_63;
break;
}
+
return ret;
}
@@ -863,10 +1019,14 @@ int32_t lsm303ah_mg_set_rst_sensor_single_set(stmdev_ctx_t *ctx,
lsm303ah_cfg_reg_b_m_t cfg_reg_b_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_B_M, (uint8_t*)&cfg_reg_b_m, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_B_M,
+ (uint8_t *)&cfg_reg_b_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_b_m.off_canc_one_shot = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_B_M, (uint8_t*)&cfg_reg_b_m, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_B_M,
+ (uint8_t *)&cfg_reg_b_m, 1);
}
return ret;
@@ -889,7 +1049,8 @@ int32_t lsm303ah_mg_set_rst_sensor_single_get(stmdev_ctx_t *ctx,
lsm303ah_cfg_reg_b_m_t cfg_reg_b_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_B_M, (uint8_t*)&cfg_reg_b_m, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_B_M,
+ (uint8_t *)&cfg_reg_b_m, 1);
*val = cfg_reg_b_m.off_canc_one_shot;
return ret;
@@ -919,7 +1080,9 @@ int32_t lsm303ah_acceleration_module_raw_get(stmdev_ctx_t *ctx,
uint8_t *buff)
{
int32_t ret;
+
ret = lsm303ah_read_reg(ctx, LSM303AH_MODULE_8BIT_A, buff, 1);
+
return ret;
}
@@ -932,10 +1095,13 @@ int32_t lsm303ah_acceleration_module_raw_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm303ah_xl_temperature_raw_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
+
ret = lsm303ah_read_reg(ctx, LSM303AH_OUT_T_A, buff, 1);
+
return ret;
}
@@ -948,10 +1114,19 @@ int32_t lsm303ah_xl_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm303ah_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lsm303ah_read_reg(ctx, LSM303AH_OUT_X_L_A, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -963,10 +1138,19 @@ int32_t lsm303ah_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_magnetic_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm303ah_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lsm303ah_read_reg(ctx, LSM303AH_OUTX_L_REG_M, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -978,10 +1162,15 @@ int32_t lsm303ah_magnetic_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_number_of_steps_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm303ah_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
+
ret = lsm303ah_read_reg(ctx, LSM303AH_STEP_COUNTER_L_A, buff, 2);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
+
return ret;
}
@@ -992,7 +1181,7 @@ int32_t lsm303ah_number_of_steps_get(stmdev_ctx_t *ctx, uint8_t *buff)
/**
* @defgroup common
- * @brief This section groups common usefull functions.
+ * @brief This section groups common useful functions.
* @{
*
*/
@@ -1008,7 +1197,9 @@ int32_t lsm303ah_number_of_steps_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lsm303ah_xl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm303ah_read_reg(ctx, LSM303AH_WHO_AM_I_A, buff, 1);
+
return ret;
}
@@ -1023,7 +1214,9 @@ int32_t lsm303ah_xl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lsm303ah_mg_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm303ah_read_reg(ctx, LSM303AH_WHO_AM_I_M, buff, 1);
+
return ret;
}
@@ -1041,10 +1234,12 @@ int32_t lsm303ah_xl_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
lsm303ah_ctrl2_a_t ctrl2_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
+
+ if (ret == 0)
+ {
ctrl2_a.if_add_inc = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
}
return ret;
@@ -1059,12 +1254,13 @@ int32_t lsm303ah_xl_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm303ah_xl_auto_increment_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm303ah_ctrl2_a_t ctrl2_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
*val = ctrl2_a.if_add_inc;
return ret;
@@ -1086,20 +1282,31 @@ int32_t lsm303ah_xl_mem_bank_set(stmdev_ctx_t *ctx,
lsm303ah_ctrl2_adv_a_t ctrl2_adv_a;
int32_t ret;
- if (val == LSM303AH_XL_ADV_BANK){
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
- if(ret == 0){
+
+ if (val == LSM303AH_XL_ADV_BANK)
+ {
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
+
+ if (ret == 0)
+ {
ctrl2_a.func_cfg_en = (uint8_t)val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
}
}
- else {
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_ADV_A, (uint8_t*)&ctrl2_adv_a, 1);
- if(ret == 0){
+
+ else
+ {
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_ADV_A,
+ (uint8_t *)&ctrl2_adv_a, 1);
+
+ if (ret == 0)
+ {
ctrl2_adv_a.func_cfg_en = (uint8_t)val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL2_ADV_A, (uint8_t*)&ctrl2_adv_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL2_ADV_A,
+ (uint8_t *)&ctrl2_adv_a, 1);
}
}
+
return ret;
}
@@ -1116,10 +1323,12 @@ int32_t lsm303ah_xl_reset_set(stmdev_ctx_t *ctx, uint8_t val)
lsm303ah_ctrl2_a_t ctrl2_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
+
+ if (ret == 0)
+ {
ctrl2_a.soft_reset = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
}
return ret;
@@ -1138,7 +1347,7 @@ int32_t lsm303ah_xl_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm303ah_ctrl2_a_t ctrl2_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
*val = ctrl2_a.soft_reset;
return ret;
@@ -1157,10 +1366,14 @@ int32_t lsm303ah_mg_reset_set(stmdev_ctx_t *ctx, uint8_t val)
lsm303ah_cfg_reg_a_m_t cfg_reg_a_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_A_M, (uint8_t*)&cfg_reg_a_m, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_A_M,
+ (uint8_t *)&cfg_reg_a_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_a_m.soft_rst = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_A_M, (uint8_t*)&cfg_reg_a_m, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_A_M,
+ (uint8_t *)&cfg_reg_a_m, 1);
}
return ret;
@@ -1179,7 +1392,8 @@ int32_t lsm303ah_mg_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm303ah_cfg_reg_a_m_t cfg_reg_a_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_A_M, (uint8_t*)&cfg_reg_a_m, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_A_M,
+ (uint8_t *)&cfg_reg_a_m, 1);
*val = cfg_reg_a_m.soft_rst;
return ret;
@@ -1198,10 +1412,12 @@ int32_t lsm303ah_xl_boot_set(stmdev_ctx_t *ctx, uint8_t val)
lsm303ah_ctrl2_a_t ctrl2_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
+
+ if (ret == 0)
+ {
ctrl2_a.boot = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
}
return ret;
@@ -1220,7 +1436,7 @@ int32_t lsm303ah_xl_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm303ah_ctrl2_a_t ctrl2_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
*val = ctrl2_a.boot;
return ret;
@@ -1239,10 +1455,14 @@ int32_t lsm303ah_mg_boot_set(stmdev_ctx_t *ctx, uint8_t val)
lsm303ah_cfg_reg_a_m_t cfg_reg_a_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_A_M, (uint8_t*)&cfg_reg_a_m, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_A_M,
+ (uint8_t *)&cfg_reg_a_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_a_m.reboot = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_A_M, (uint8_t*)&cfg_reg_a_m, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_A_M,
+ (uint8_t *)&cfg_reg_a_m, 1);
}
return ret;
@@ -1261,7 +1481,8 @@ int32_t lsm303ah_mg_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm303ah_cfg_reg_a_m_t cfg_reg_a_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_A_M, (uint8_t*)&cfg_reg_a_m, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_A_M,
+ (uint8_t *)&cfg_reg_a_m, 1);
*val = cfg_reg_a_m.reboot;
return ret;
@@ -1275,15 +1496,18 @@ int32_t lsm303ah_mg_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_self_test_set(stmdev_ctx_t *ctx, lsm303ah_xl_st_t val)
+int32_t lsm303ah_xl_self_test_set(stmdev_ctx_t *ctx,
+ lsm303ah_xl_st_t val)
{
lsm303ah_ctrl3_a_t ctrl3_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
+
+ if (ret == 0)
+ {
ctrl3_a.st = (uint8_t)val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
}
return ret;
@@ -1297,26 +1521,33 @@ int32_t lsm303ah_xl_self_test_set(stmdev_ctx_t *ctx, lsm303ah_xl_st_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_self_test_get(stmdev_ctx_t *ctx, lsm303ah_xl_st_t *val)
+int32_t lsm303ah_xl_self_test_get(stmdev_ctx_t *ctx,
+ lsm303ah_xl_st_t *val)
{
lsm303ah_ctrl3_a_t ctrl3_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
- switch (ctrl3_a.st){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
+
+ switch (ctrl3_a.st)
+ {
case LSM303AH_XL_ST_DISABLE:
*val = LSM303AH_XL_ST_DISABLE;
break;
+
case LSM303AH_XL_ST_POSITIVE:
*val = LSM303AH_XL_ST_POSITIVE;
break;
+
case LSM303AH_XL_ST_NEGATIVE:
*val = LSM303AH_XL_ST_NEGATIVE;
break;
+
default:
*val = LSM303AH_XL_ST_DISABLE;
break;
}
+
return ret;
}
@@ -1333,10 +1564,14 @@ int32_t lsm303ah_mg_self_test_set(stmdev_ctx_t *ctx, uint8_t val)
lsm303ah_cfg_reg_c_m_t cfg_reg_c_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_C_M, (uint8_t*)&cfg_reg_c_m, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_C_M,
+ (uint8_t *)&cfg_reg_c_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_c_m.self_test = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_C_M, (uint8_t*)&cfg_reg_c_m, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_C_M,
+ (uint8_t *)&cfg_reg_c_m, 1);
}
return ret;
@@ -1355,7 +1590,8 @@ int32_t lsm303ah_mg_self_test_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm303ah_cfg_reg_c_m_t cfg_reg_c_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_C_M, (uint8_t*)&cfg_reg_c_m, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_C_M,
+ (uint8_t *)&cfg_reg_c_m, 1);
*val = cfg_reg_c_m.self_test;
return ret;
@@ -1370,15 +1606,17 @@ int32_t lsm303ah_mg_self_test_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm303ah_xl_data_ready_mode_set(stmdev_ctx_t *ctx,
- lsm303ah_xl_drdy_pulsed_t val)
+ lsm303ah_xl_drdy_pulsed_t val)
{
lsm303ah_ctrl5_a_t ctrl5_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL5_A, (uint8_t*)&ctrl5_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL5_A, (uint8_t *)&ctrl5_a, 1);
+
+ if (ret == 0)
+ {
ctrl5_a.drdy_pulsed = (uint8_t)val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL5_A, (uint8_t*)&ctrl5_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL5_A, (uint8_t *)&ctrl5_a, 1);
}
return ret;
@@ -1393,19 +1631,23 @@ int32_t lsm303ah_xl_data_ready_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm303ah_xl_data_ready_mode_get(stmdev_ctx_t *ctx,
- lsm303ah_xl_drdy_pulsed_t *val)
+ lsm303ah_xl_drdy_pulsed_t *val)
{
lsm303ah_ctrl5_a_t ctrl5_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL5_A, (uint8_t*)&ctrl5_a, 1);
- switch (ctrl5_a.drdy_pulsed){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL5_A, (uint8_t *)&ctrl5_a, 1);
+
+ switch (ctrl5_a.drdy_pulsed)
+ {
case LSM303AH_XL_DRDY_LATCHED:
*val = LSM303AH_XL_DRDY_LATCHED;
break;
+
case LSM303AH_XL_DRDY_PULSED:
*val = LSM303AH_XL_DRDY_PULSED;
break;
+
default:
*val = LSM303AH_XL_DRDY_LATCHED;
break;
@@ -1441,10 +1683,12 @@ int32_t lsm303ah_xl_hp_path_set(stmdev_ctx_t *ctx,
lsm303ah_ctrl2_a_t ctrl2_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
+
+ if (ret == 0)
+ {
ctrl2_a.fds_slope = (uint8_t)val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
}
return ret;
@@ -1464,18 +1708,23 @@ int32_t lsm303ah_xl_hp_path_get(stmdev_ctx_t *ctx,
lsm303ah_ctrl2_a_t ctrl2_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
- switch (ctrl2_a.fds_slope){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
+
+ switch (ctrl2_a.fds_slope)
+ {
case LSM303AH_XL_HP_INTERNAL_ONLY:
*val = LSM303AH_XL_HP_INTERNAL_ONLY;
break;
+
case LSM303AH_XL_HP_ON_OUTPUTS:
*val = LSM303AH_XL_HP_ON_OUTPUTS;
break;
+
default:
*val = LSM303AH_XL_HP_INTERNAL_ONLY;
break;
}
+
return ret;
}
@@ -1488,15 +1737,19 @@ int32_t lsm303ah_xl_hp_path_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm303ah_mg_low_pass_bandwidth_set(stmdev_ctx_t *ctx,
- lsm303ah_mg_lpf_t val)
+ lsm303ah_mg_lpf_t val)
{
lsm303ah_cfg_reg_b_m_t cfg_reg_b_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_B_M, (uint8_t*)&cfg_reg_b_m, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_B_M,
+ (uint8_t *)&cfg_reg_b_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_b_m.lpf = (uint8_t)val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_B_M, (uint8_t*)&cfg_reg_b_m, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_B_M,
+ (uint8_t *)&cfg_reg_b_m, 1);
}
return ret;
@@ -1511,23 +1764,29 @@ int32_t lsm303ah_mg_low_pass_bandwidth_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm303ah_mg_low_pass_bandwidth_get(stmdev_ctx_t *ctx,
- lsm303ah_mg_lpf_t *val)
+ lsm303ah_mg_lpf_t *val)
{
lsm303ah_cfg_reg_b_m_t cfg_reg_b_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_B_M, (uint8_t*)&cfg_reg_b_m, 1);
- switch (cfg_reg_b_m.lpf){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_B_M,
+ (uint8_t *)&cfg_reg_b_m, 1);
+
+ switch (cfg_reg_b_m.lpf)
+ {
case LSM303AH_MG_ODR_DIV_2:
*val = LSM303AH_MG_ODR_DIV_2;
break;
+
case LSM303AH_MG_ODR_DIV_4:
*val = LSM303AH_MG_ODR_DIV_4;
break;
+
default:
*val = LSM303AH_MG_ODR_DIV_2;
break;
}
+
return ret;
}
@@ -1552,15 +1811,18 @@ int32_t lsm303ah_mg_low_pass_bandwidth_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_spi_mode_set(stmdev_ctx_t *ctx, lsm303ah_xl_sim_t val)
+int32_t lsm303ah_xl_spi_mode_set(stmdev_ctx_t *ctx,
+ lsm303ah_xl_sim_t val)
{
lsm303ah_ctrl2_a_t ctrl2_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
+
+ if (ret == 0)
+ {
ctrl2_a.sim = (uint8_t)val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
}
return ret;
@@ -1574,23 +1836,29 @@ int32_t lsm303ah_xl_spi_mode_set(stmdev_ctx_t *ctx, lsm303ah_xl_sim_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_spi_mode_get(stmdev_ctx_t *ctx, lsm303ah_xl_sim_t *val)
+int32_t lsm303ah_xl_spi_mode_get(stmdev_ctx_t *ctx,
+ lsm303ah_xl_sim_t *val)
{
lsm303ah_ctrl2_a_t ctrl2_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
- switch (ctrl2_a.sim){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
+
+ switch (ctrl2_a.sim)
+ {
case LSM303AH_XL_SPI_4_WIRE:
*val = LSM303AH_XL_SPI_4_WIRE;
break;
+
case LSM303AH_XL_SPI_3_WIRE:
*val = LSM303AH_XL_SPI_3_WIRE;
break;
+
default:
*val = LSM303AH_XL_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -1603,15 +1871,17 @@ int32_t lsm303ah_xl_spi_mode_get(stmdev_ctx_t *ctx, lsm303ah_xl_sim_t *val)
*
*/
int32_t lsm303ah_xl_i2c_interface_set(stmdev_ctx_t *ctx,
- lsm303ah_xl_i2c_disable_t val)
+ lsm303ah_xl_i2c_disable_t val)
{
lsm303ah_ctrl2_a_t ctrl2_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
+
+ if (ret == 0)
+ {
ctrl2_a.i2c_disable = (uint8_t)val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
}
return ret;
@@ -1626,23 +1896,28 @@ int32_t lsm303ah_xl_i2c_interface_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm303ah_xl_i2c_interface_get(stmdev_ctx_t *ctx,
- lsm303ah_xl_i2c_disable_t *val)
+ lsm303ah_xl_i2c_disable_t *val)
{
lsm303ah_ctrl2_a_t ctrl2_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t*)&ctrl2_a, 1);
- switch (ctrl2_a.i2c_disable){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
+
+ switch (ctrl2_a.i2c_disable)
+ {
case LSM303AH_XL_I2C_ENABLE:
*val = LSM303AH_XL_I2C_ENABLE;
break;
+
case LSM303AH_XL_I2C_DISABLE:
*val = LSM303AH_XL_I2C_DISABLE;
break;
+
default:
*val = LSM303AH_XL_I2C_ENABLE;
break;
}
+
return ret;
}
@@ -1660,10 +1935,14 @@ int32_t lsm303ah_mg_i2c_interface_set(stmdev_ctx_t *ctx,
lsm303ah_cfg_reg_c_m_t cfg_reg_c_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_C_M, (uint8_t*)&cfg_reg_c_m, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_C_M,
+ (uint8_t *)&cfg_reg_c_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_c_m.i2c_dis = (uint8_t)val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_C_M, (uint8_t*)&cfg_reg_c_m, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_C_M,
+ (uint8_t *)&cfg_reg_c_m, 1);
}
return ret;
@@ -1683,18 +1962,24 @@ int32_t lsm303ah_mg_i2c_interface_get(stmdev_ctx_t *ctx,
lsm303ah_cfg_reg_c_m_t cfg_reg_c_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_C_M, (uint8_t*)&cfg_reg_c_m, 1);
- switch (cfg_reg_c_m.i2c_dis){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_C_M,
+ (uint8_t *)&cfg_reg_c_m, 1);
+
+ switch (cfg_reg_c_m.i2c_dis)
+ {
case LSM303AH_MG_I2C_ENABLE:
*val = LSM303AH_MG_I2C_ENABLE;
break;
+
case LSM303AH_MG_I2C_DISABLE:
*val = LSM303AH_MG_I2C_DISABLE;
break;
+
default:
*val = LSM303AH_MG_I2C_ENABLE;
break;
}
+
return ret;
}
@@ -1707,15 +1992,19 @@ int32_t lsm303ah_mg_i2c_interface_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm303ah_xl_cs_mode_set(stmdev_ctx_t *ctx,
- lsm303ah_xl_if_cs_pu_dis_t val)
+ lsm303ah_xl_if_cs_pu_dis_t val)
{
lsm303ah_fifo_ctrl_a_t fifo_ctrl_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_CTRL_A, (uint8_t*)&fifo_ctrl_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_CTRL_A,
+ (uint8_t *)&fifo_ctrl_a, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl_a.if_cs_pu_dis = (uint8_t)val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_FIFO_CTRL_A, (uint8_t*)&fifo_ctrl_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_FIFO_CTRL_A,
+ (uint8_t *)&fifo_ctrl_a, 1);
}
return ret;
@@ -1730,23 +2019,29 @@ int32_t lsm303ah_xl_cs_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm303ah_xl_cs_mode_get(stmdev_ctx_t *ctx,
- lsm303ah_xl_if_cs_pu_dis_t *val)
+ lsm303ah_xl_if_cs_pu_dis_t *val)
{
lsm303ah_fifo_ctrl_a_t fifo_ctrl_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_CTRL_A, (uint8_t*)&fifo_ctrl_a, 1);
- switch (fifo_ctrl_a.if_cs_pu_dis){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_CTRL_A,
+ (uint8_t *)&fifo_ctrl_a, 1);
+
+ switch (fifo_ctrl_a.if_cs_pu_dis)
+ {
case LSM303AH_XL_PULL_UP_CONNECTED:
*val = LSM303AH_XL_PULL_UP_CONNECTED;
break;
+
case LSM303AH_XL_PULL_UP_DISCONNECTED:
*val = LSM303AH_XL_PULL_UP_DISCONNECTED;
break;
+
default:
*val = LSM303AH_XL_PULL_UP_CONNECTED;
break;
}
+
return ret;
}
@@ -1771,15 +2066,18 @@ int32_t lsm303ah_xl_cs_mode_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_pin_mode_set(stmdev_ctx_t *ctx, lsm303ah_xl_pp_od_t val)
+int32_t lsm303ah_xl_pin_mode_set(stmdev_ctx_t *ctx,
+ lsm303ah_xl_pp_od_t val)
{
lsm303ah_ctrl3_a_t ctrl3_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
+
+ if (ret == 0)
+ {
ctrl3_a.pp_od = (uint8_t)val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
}
return ret;
@@ -1799,18 +2097,23 @@ int32_t lsm303ah_xl_pin_mode_get(stmdev_ctx_t *ctx,
lsm303ah_ctrl3_a_t ctrl3_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
- switch (ctrl3_a.pp_od){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
+
+ switch (ctrl3_a.pp_od)
+ {
case LSM303AH_XL_PUSH_PULL:
*val = LSM303AH_XL_PUSH_PULL;
break;
+
case LSM303AH_XL_OPEN_DRAIN:
*val = LSM303AH_XL_OPEN_DRAIN;
break;
+
default:
*val = LSM303AH_XL_PUSH_PULL;
break;
}
+
return ret;
}
@@ -1823,15 +2126,17 @@ int32_t lsm303ah_xl_pin_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm303ah_xl_pin_polarity_set(stmdev_ctx_t *ctx,
- lsm303ah_xl_h_lactive_t val)
+ lsm303ah_xl_h_lactive_t val)
{
lsm303ah_ctrl3_a_t ctrl3_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
+
+ if (ret == 0)
+ {
ctrl3_a.h_lactive = (uint8_t)val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
}
return ret;
@@ -1846,23 +2151,28 @@ int32_t lsm303ah_xl_pin_polarity_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm303ah_xl_pin_polarity_get(stmdev_ctx_t *ctx,
- lsm303ah_xl_h_lactive_t *val)
+ lsm303ah_xl_h_lactive_t *val)
{
lsm303ah_ctrl3_a_t ctrl3_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
- switch (ctrl3_a.h_lactive){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
+
+ switch (ctrl3_a.h_lactive)
+ {
case LSM303AH_XL_ACTIVE_HIGH:
*val = LSM303AH_XL_ACTIVE_HIGH;
break;
+
case LSM303AH_XL_ACTIVE_LOW:
*val = LSM303AH_XL_ACTIVE_LOW;
break;
+
default:
*val = LSM303AH_XL_ACTIVE_HIGH;
break;
}
+
return ret;
}
@@ -1875,15 +2185,17 @@ int32_t lsm303ah_xl_pin_polarity_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm303ah_xl_int_notification_set(stmdev_ctx_t *ctx,
- lsm303ah_xl_lir_t val)
+ lsm303ah_xl_lir_t val)
{
lsm303ah_ctrl3_a_t ctrl3_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
+
+ if (ret == 0)
+ {
ctrl3_a.lir = (uint8_t)val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
}
return ret;
@@ -1898,23 +2210,28 @@ int32_t lsm303ah_xl_int_notification_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm303ah_xl_int_notification_get(stmdev_ctx_t *ctx,
- lsm303ah_xl_lir_t *val)
+ lsm303ah_xl_lir_t *val)
{
lsm303ah_ctrl3_a_t ctrl3_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
- switch (ctrl3_a.lir){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
+
+ switch (ctrl3_a.lir)
+ {
case LSM303AH_XL_INT_PULSED:
*val = LSM303AH_XL_INT_PULSED;
break;
+
case LSM303AH_XL_INT_LATCHED:
*val = LSM303AH_XL_INT_LATCHED;
break;
+
default:
*val = LSM303AH_XL_INT_PULSED;
break;
}
+
return ret;
}
@@ -1927,14 +2244,16 @@ int32_t lsm303ah_xl_int_notification_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm303ah_xl_pin_int1_route_set(stmdev_ctx_t *ctx,
- lsm303ah_xl_pin_int1_route_t val)
+ lsm303ah_xl_pin_int1_route_t val)
{
lsm303ah_ctrl4_a_t ctrl4_a;
lsm303ah_wake_up_dur_a_t wake_up_dur_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL4_A, (uint8_t*)&ctrl4_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL4_A, (uint8_t *)&ctrl4_a, 1);
+
+ if (ret == 0)
+ {
ctrl4_a.int1_drdy = val.int1_drdy;
ctrl4_a.int1_fth = val.int1_fth;
ctrl4_a.int1_6d = val.int1_6d;
@@ -1942,14 +2261,20 @@ int32_t lsm303ah_xl_pin_int1_route_set(stmdev_ctx_t *ctx,
ctrl4_a.int1_ff = val.int1_ff;
ctrl4_a.int1_wu = val.int1_wu;
ctrl4_a.int1_s_tap = val.int1_s_tap;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL4_A, (uint8_t*)&ctrl4_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL4_A, (uint8_t *)&ctrl4_a, 1);
}
- if(ret == 0){
- ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_DUR_A, (uint8_t*)&wake_up_dur_a, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_DUR_A,
+ (uint8_t *)&wake_up_dur_a, 1);
}
- if(ret == 0){
- wake_up_dur_a.int1_fss7 = val.int1_fss7;
- ret = lsm303ah_write_reg(ctx, LSM303AH_WAKE_UP_DUR_A, (uint8_t*)&wake_up_dur_a, 1);
+
+ if (ret == 0)
+ {
+ wake_up_dur_a.int1_fss7 = val.int1_fss7;
+ ret = lsm303ah_write_reg(ctx, LSM303AH_WAKE_UP_DUR_A,
+ (uint8_t *)&wake_up_dur_a, 1);
}
return ret;
@@ -1964,14 +2289,16 @@ int32_t lsm303ah_xl_pin_int1_route_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm303ah_xl_pin_int1_route_get(stmdev_ctx_t *ctx,
- lsm303ah_xl_pin_int1_route_t *val)
+ lsm303ah_xl_pin_int1_route_t *val)
{
lsm303ah_ctrl4_a_t ctrl4_a;
lsm303ah_wake_up_dur_a_t wake_up_dur_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL4_A, (uint8_t*)&ctrl4_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL4_A, (uint8_t *)&ctrl4_a, 1);
+
+ if (ret == 0)
+ {
val->int1_drdy = ctrl4_a.int1_drdy;
val->int1_fth = ctrl4_a.int1_fth;
val->int1_6d = ctrl4_a.int1_6d;
@@ -1980,9 +2307,13 @@ int32_t lsm303ah_xl_pin_int1_route_get(stmdev_ctx_t *ctx,
val->int1_wu = ctrl4_a.int1_wu;
val->int1_s_tap = ctrl4_a.int1_s_tap;
}
- if(ret == 0){
- ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_DUR_A, (uint8_t*)&wake_up_dur_a, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_DUR_A,
+ (uint8_t *)&wake_up_dur_a, 1);
}
+
val->int1_fss7 = wake_up_dur_a.int1_fss7;
return ret;
@@ -1997,20 +2328,22 @@ int32_t lsm303ah_xl_pin_int1_route_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm303ah_xl_pin_int2_route_set(stmdev_ctx_t *ctx,
- lsm303ah_xl_pin_int2_route_t val)
+ lsm303ah_xl_pin_int2_route_t val)
{
lsm303ah_ctrl5_a_t ctrl5_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL5_A, (uint8_t*)&ctrl5_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL5_A, (uint8_t *)&ctrl5_a, 1);
+
+ if (ret == 0)
+ {
ctrl5_a.int2_boot = val.int2_boot;
ctrl5_a.int2_tilt = val.int2_tilt;
ctrl5_a.int2_sig_mot = val.int2_sig_mot;
ctrl5_a.int2_step = val.int2_step;
ctrl5_a.int2_fth = val.int2_fth;
ctrl5_a.int2_drdy = val.int2_drdy;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL5_A, (uint8_t*)&ctrl5_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL5_A, (uint8_t *)&ctrl5_a, 1);
}
return ret;
@@ -2025,12 +2358,12 @@ int32_t lsm303ah_xl_pin_int2_route_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm303ah_xl_pin_int2_route_get(stmdev_ctx_t *ctx,
- lsm303ah_xl_pin_int2_route_t *val)
+ lsm303ah_xl_pin_int2_route_t *val)
{
lsm303ah_ctrl5_a_t ctrl5_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL5_A, (uint8_t*)&ctrl5_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL5_A, (uint8_t *)&ctrl5_a, 1);
val->int2_boot = ctrl5_a.int2_boot;
val->int2_tilt = ctrl5_a.int2_tilt;
val->int2_sig_mot = ctrl5_a.int2_sig_mot;
@@ -2054,10 +2387,12 @@ int32_t lsm303ah_xl_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
lsm303ah_ctrl5_a_t ctrl5_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL5_A, (uint8_t*)&ctrl5_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL5_A, (uint8_t *)&ctrl5_a, 1);
+
+ if (ret == 0)
+ {
ctrl5_a.int2_on_int1 = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL5_A, (uint8_t*)&ctrl5_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL5_A, (uint8_t *)&ctrl5_a, 1);
}
return ret;
@@ -2076,7 +2411,7 @@ int32_t lsm303ah_xl_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm303ah_ctrl5_a_t ctrl5_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL5_A, (uint8_t*)&ctrl5_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL5_A, (uint8_t *)&ctrl5_a, 1);
*val = ctrl5_a.int2_on_int1;
return ret;
@@ -2095,10 +2430,14 @@ int32_t lsm303ah_mg_drdy_on_pin_set(stmdev_ctx_t *ctx, uint8_t val)
lsm303ah_cfg_reg_c_m_t cfg_reg_c_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_C_M, (uint8_t*)&cfg_reg_c_m, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_C_M,
+ (uint8_t *)&cfg_reg_c_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_c_m.int_mag = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_C_M, (uint8_t*)&cfg_reg_c_m, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_C_M,
+ (uint8_t *)&cfg_reg_c_m, 1);
}
return ret;
@@ -2117,7 +2456,8 @@ int32_t lsm303ah_mg_drdy_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm303ah_cfg_reg_c_m_t cfg_reg_c_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_C_M, (uint8_t*)&cfg_reg_c_m, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_C_M,
+ (uint8_t *)&cfg_reg_c_m, 1);
*val = cfg_reg_c_m.int_mag;
return ret;
@@ -2136,10 +2476,14 @@ int32_t lsm303ah_mg_int_on_pin_set(stmdev_ctx_t *ctx, uint8_t val)
lsm303ah_cfg_reg_c_m_t cfg_reg_c_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_C_M, (uint8_t*)&cfg_reg_c_m, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_C_M,
+ (uint8_t *)&cfg_reg_c_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_c_m.int_mag_pin = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_C_M, (uint8_t*)&cfg_reg_c_m, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_C_M,
+ (uint8_t *)&cfg_reg_c_m, 1);
}
return ret;
@@ -2158,7 +2502,8 @@ int32_t lsm303ah_mg_int_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm303ah_cfg_reg_c_m_t cfg_reg_c_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_C_M, (uint8_t*)&cfg_reg_c_m, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_C_M,
+ (uint8_t *)&cfg_reg_c_m, 1);
*val = cfg_reg_c_m.int_mag_pin;
return ret;
@@ -2173,10 +2518,13 @@ int32_t lsm303ah_mg_int_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm303ah_mg_int_gen_conf_set(stmdev_ctx_t *ctx,
- lsm303ah_int_crtl_reg_m_t *val)
+ lsm303ah_int_crtl_reg_m_t *val)
{
int32_t ret;
- ret = lsm303ah_write_reg(ctx, LSM303AH_INT_CRTL_REG_M, (uint8_t*) val, 1);
+
+ ret = lsm303ah_write_reg(ctx, LSM303AH_INT_CRTL_REG_M,
+ (uint8_t *) val, 1);
+
return ret;
}
@@ -2189,10 +2537,12 @@ int32_t lsm303ah_mg_int_gen_conf_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm303ah_mg_int_gen_conf_get(stmdev_ctx_t *ctx,
- lsm303ah_int_crtl_reg_m_t *val)
+ lsm303ah_int_crtl_reg_m_t *val)
{
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_INT_CRTL_REG_M, (uint8_t*) val, 1);
+
+ ret = lsm303ah_read_reg(ctx, LSM303AH_INT_CRTL_REG_M, (uint8_t *) val, 1);
+
return ret;
}
@@ -2205,10 +2555,13 @@ int32_t lsm303ah_mg_int_gen_conf_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm303ah_mg_int_gen_source_get(stmdev_ctx_t *ctx,
- lsm303ah_int_source_reg_m_t *val)
+ lsm303ah_int_source_reg_m_t *val)
{
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_INT_SOURCE_REG_M, (uint8_t*) val, 1);
+
+ ret = lsm303ah_read_reg(ctx, LSM303AH_INT_SOURCE_REG_M,
+ (uint8_t *) val, 1);
+
return ret;
}
@@ -2222,10 +2575,16 @@ int32_t lsm303ah_mg_int_gen_source_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_mg_int_gen_treshold_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm303ah_mg_int_gen_treshold_set(stmdev_ctx_t *ctx,
+ uint16_t val)
{
+ uint8_t buff[2];
int32_t ret;
+
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
ret = lsm303ah_write_reg(ctx, LSM303AH_INT_THS_L_REG_M, buff, 2);
+
return ret;
}
@@ -2239,10 +2598,16 @@ int32_t lsm303ah_mg_int_gen_treshold_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_mg_int_gen_treshold_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm303ah_mg_int_gen_treshold_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
+
ret = lsm303ah_read_reg(ctx, LSM303AH_INT_THS_L_REG_M, buff, 2);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
+
return ret;
}
@@ -2253,7 +2618,7 @@ int32_t lsm303ah_mg_int_gen_treshold_get(stmdev_ctx_t *ctx, uint8_t *buff)
/**
* @defgroup interrupt_pins
- * @brief This section groups all the functions that manage interrup pins
+ * @brief This section groups all the functions that manage interrupt pins
* @{
*
*/
@@ -2283,15 +2648,19 @@ int32_t lsm303ah_mg_int_gen_treshold_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
*/
int32_t lsm303ah_mg_offset_int_conf_set(stmdev_ctx_t *ctx,
- lsm303ah_mg_int_on_dataoff_t val)
+ lsm303ah_mg_int_on_dataoff_t val)
{
lsm303ah_cfg_reg_b_m_t cfg_reg_b_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_B_M, (uint8_t*)&cfg_reg_b_m, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_B_M,
+ (uint8_t *)&cfg_reg_b_m, 1);
+
+ if (ret == 0)
+ {
cfg_reg_b_m.int_on_dataoff = (uint8_t)val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_B_M, (uint8_t*)&cfg_reg_b_m, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CFG_REG_B_M,
+ (uint8_t *)&cfg_reg_b_m, 1);
}
return ret;
@@ -2307,27 +2676,33 @@ int32_t lsm303ah_mg_offset_int_conf_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm303ah_mg_offset_int_conf_get(stmdev_ctx_t *ctx,
- lsm303ah_mg_int_on_dataoff_t *val)
+ lsm303ah_mg_int_on_dataoff_t *val)
{
lsm303ah_cfg_reg_b_m_t cfg_reg_b_m;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_B_M, (uint8_t*)&cfg_reg_b_m, 1);
- switch (cfg_reg_b_m.int_on_dataoff){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_B_M,
+ (uint8_t *)&cfg_reg_b_m, 1);
+
+ switch (cfg_reg_b_m.int_on_dataoff)
+ {
case LSM303AH_MG_CHECK_BEFORE:
*val = LSM303AH_MG_CHECK_BEFORE;
break;
+
case LSM303AH_MG_CHECK_AFTER:
*val = LSM303AH_MG_CHECK_AFTER;
break;
+
default:
*val = LSM303AH_MG_CHECK_BEFORE;
break;
}
+
return ret;
}
- /**
+/**
* @brief Threshold for wakeup [1 LSb = FS_XL / 64].[set]
*
* @param ctx read / write interface definitions.(ptr)
@@ -2340,10 +2715,14 @@ int32_t lsm303ah_xl_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
lsm303ah_wake_up_ths_a_t wake_up_ths_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_THS_A, (uint8_t*)&wake_up_ths_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_THS_A,
+ (uint8_t *)&wake_up_ths_a, 1);
+
+ if (ret == 0)
+ {
wake_up_ths_a.wu_ths = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_WAKE_UP_THS_A, (uint8_t*)&wake_up_ths_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_WAKE_UP_THS_A,
+ (uint8_t *)&wake_up_ths_a, 1);
}
return ret;
@@ -2357,12 +2736,14 @@ int32_t lsm303ah_xl_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm303ah_xl_wkup_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm303ah_wake_up_ths_a_t wake_up_ths_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_THS_A, (uint8_t*)&wake_up_ths_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_THS_A,
+ (uint8_t *)&wake_up_ths_a, 1);
*val = wake_up_ths_a.wu_ths;
return ret;
@@ -2381,10 +2762,14 @@ int32_t lsm303ah_xl_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm303ah_wake_up_dur_a_t wake_up_dur_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_DUR_A, (uint8_t*)&wake_up_dur_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_DUR_A,
+ (uint8_t *)&wake_up_dur_a, 1);
+
+ if (ret == 0)
+ {
wake_up_dur_a.wu_dur = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_WAKE_UP_DUR_A, (uint8_t*)&wake_up_dur_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_WAKE_UP_DUR_A,
+ (uint8_t *)&wake_up_dur_a, 1);
}
return ret;
@@ -2403,7 +2788,8 @@ int32_t lsm303ah_xl_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm303ah_wake_up_dur_a_t wake_up_dur_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_DUR_A, (uint8_t*)&wake_up_dur_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_DUR_A,
+ (uint8_t *)&wake_up_dur_a, 1);
*val = wake_up_dur_a.wu_dur;
return ret;
@@ -2434,10 +2820,14 @@ int32_t lsm303ah_xl_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
lsm303ah_wake_up_ths_a_t wake_up_ths_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_THS_A, (uint8_t*)&wake_up_ths_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_THS_A,
+ (uint8_t *)&wake_up_ths_a, 1);
+
+ if (ret == 0)
+ {
wake_up_ths_a.sleep_on = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_WAKE_UP_THS_A, (uint8_t*)&wake_up_ths_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_WAKE_UP_THS_A,
+ (uint8_t *)&wake_up_ths_a, 1);
}
return ret;
@@ -2456,7 +2846,8 @@ int32_t lsm303ah_xl_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm303ah_wake_up_ths_a_t wake_up_ths_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_THS_A, (uint8_t*)&wake_up_ths_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_THS_A,
+ (uint8_t *)&wake_up_ths_a, 1);
*val = wake_up_ths_a.sleep_on;
return ret;
@@ -2475,10 +2866,14 @@ int32_t lsm303ah_xl_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm303ah_wake_up_dur_a_t wake_up_dur_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_DUR_A, (uint8_t*)&wake_up_dur_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_DUR_A,
+ (uint8_t *)&wake_up_dur_a, 1);
+
+ if (ret == 0)
+ {
wake_up_dur_a.sleep_dur = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_WAKE_UP_DUR_A, (uint8_t*)&wake_up_dur_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_WAKE_UP_DUR_A,
+ (uint8_t *)&wake_up_dur_a, 1);
}
return ret;
@@ -2497,7 +2892,8 @@ int32_t lsm303ah_xl_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm303ah_wake_up_dur_a_t wake_up_dur_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_DUR_A, (uint8_t*)&wake_up_dur_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_DUR_A,
+ (uint8_t *)&wake_up_dur_a, 1);
*val = wake_up_dur_a.sleep_dur;
return ret;
@@ -2524,15 +2920,18 @@ int32_t lsm303ah_xl_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm303ah_xl_tap_detection_on_z_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm303ah_ctrl3_a_t ctrl3_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
+
+ if (ret == 0)
+ {
ctrl3_a.tap_z_en = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
}
return ret;
@@ -2546,12 +2945,13 @@ int32_t lsm303ah_xl_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm303ah_xl_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm303ah_ctrl3_a_t ctrl3_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
*val = ctrl3_a.tap_z_en;
return ret;
@@ -2565,15 +2965,18 @@ int32_t lsm303ah_xl_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm303ah_xl_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm303ah_ctrl3_a_t ctrl3_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
+
+ if (ret == 0)
+ {
ctrl3_a.tap_y_en = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
}
return ret;
@@ -2587,12 +2990,13 @@ int32_t lsm303ah_xl_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm303ah_xl_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm303ah_ctrl3_a_t ctrl3_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
*val = ctrl3_a.tap_y_en;
return ret;
@@ -2606,15 +3010,18 @@ int32_t lsm303ah_xl_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm303ah_xl_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm303ah_ctrl3_a_t ctrl3_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
+
+ if (ret == 0)
+ {
ctrl3_a.tap_x_en = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
}
return ret;
@@ -2628,12 +3035,13 @@ int32_t lsm303ah_xl_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm303ah_xl_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm303ah_ctrl3_a_t ctrl3_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t*)&ctrl3_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
*val = ctrl3_a.tap_x_en;
return ret;
@@ -2652,10 +3060,14 @@ int32_t lsm303ah_xl_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
lsm303ah_tap_6d_ths_a_t tap_6d_ths_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_TAP_6D_THS_A, (uint8_t*)&tap_6d_ths_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_TAP_6D_THS_A,
+ (uint8_t *)&tap_6d_ths_a, 1);
+
+ if (ret == 0)
+ {
tap_6d_ths_a.tap_ths = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_TAP_6D_THS_A, (uint8_t*)&tap_6d_ths_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_TAP_6D_THS_A,
+ (uint8_t *)&tap_6d_ths_a, 1);
}
return ret;
@@ -2674,7 +3086,8 @@ int32_t lsm303ah_xl_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm303ah_tap_6d_ths_a_t tap_6d_ths_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_TAP_6D_THS_A, (uint8_t*)&tap_6d_ths_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_TAP_6D_THS_A,
+ (uint8_t *)&tap_6d_ths_a, 1);
*val = tap_6d_ths_a.tap_ths;
return ret;
@@ -2697,10 +3110,14 @@ int32_t lsm303ah_xl_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
lsm303ah_int_dur_a_t int_dur_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_INT_DUR_A, (uint8_t*)&int_dur_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_INT_DUR_A,
+ (uint8_t *)&int_dur_a, 1);
+
+ if (ret == 0)
+ {
int_dur_a.shock = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_INT_DUR_A, (uint8_t*)&int_dur_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_INT_DUR_A,
+ (uint8_t *)&int_dur_a, 1);
}
return ret;
@@ -2723,7 +3140,8 @@ int32_t lsm303ah_xl_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm303ah_int_dur_a_t int_dur_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_INT_DUR_A, (uint8_t*)&int_dur_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_INT_DUR_A,
+ (uint8_t *)&int_dur_a, 1);
*val = int_dur_a.shock;
return ret;
@@ -2746,10 +3164,14 @@ int32_t lsm303ah_xl_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
lsm303ah_int_dur_a_t int_dur_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_INT_DUR_A, (uint8_t*)&int_dur_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_INT_DUR_A,
+ (uint8_t *)&int_dur_a, 1);
+
+ if (ret == 0)
+ {
int_dur_a.quiet = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_INT_DUR_A, (uint8_t*)&int_dur_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_INT_DUR_A,
+ (uint8_t *)&int_dur_a, 1);
}
return ret;
@@ -2772,7 +3194,8 @@ int32_t lsm303ah_xl_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm303ah_int_dur_a_t int_dur_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_INT_DUR_A, (uint8_t*)&int_dur_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_INT_DUR_A,
+ (uint8_t *)&int_dur_a, 1);
*val = int_dur_a.quiet;
return ret;
@@ -2795,10 +3218,14 @@ int32_t lsm303ah_xl_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm303ah_int_dur_a_t int_dur_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_INT_DUR_A, (uint8_t*)&int_dur_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_INT_DUR_A,
+ (uint8_t *)&int_dur_a, 1);
+
+ if (ret == 0)
+ {
int_dur_a.lat = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_INT_DUR_A, (uint8_t*)&int_dur_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_INT_DUR_A,
+ (uint8_t *)&int_dur_a, 1);
}
return ret;
@@ -2821,7 +3248,8 @@ int32_t lsm303ah_xl_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm303ah_int_dur_a_t int_dur_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_INT_DUR_A, (uint8_t*)&int_dur_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_INT_DUR_A,
+ (uint8_t *)&int_dur_a, 1);
*val = int_dur_a.lat;
return ret;
@@ -2836,15 +3264,19 @@ int32_t lsm303ah_xl_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm303ah_xl_tap_mode_set(stmdev_ctx_t *ctx,
- lsm303ah_xl_single_double_tap_t val)
+ lsm303ah_xl_single_double_tap_t val)
{
lsm303ah_wake_up_ths_a_t wake_up_ths_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_THS_A, (uint8_t*)&wake_up_ths_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_THS_A,
+ (uint8_t *)&wake_up_ths_a, 1);
+
+ if (ret == 0)
+ {
wake_up_ths_a.single_double_tap = (uint8_t)val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_WAKE_UP_THS_A, (uint8_t*)&wake_up_ths_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_WAKE_UP_THS_A,
+ (uint8_t *)&wake_up_ths_a, 1);
}
return ret;
@@ -2859,23 +3291,29 @@ int32_t lsm303ah_xl_tap_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm303ah_xl_tap_mode_get(stmdev_ctx_t *ctx,
- lsm303ah_xl_single_double_tap_t *val)
+ lsm303ah_xl_single_double_tap_t *val)
{
lsm303ah_wake_up_ths_a_t wake_up_ths_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_THS_A, (uint8_t*)&wake_up_ths_a, 1);
- switch (wake_up_ths_a.single_double_tap){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_THS_A,
+ (uint8_t *)&wake_up_ths_a, 1);
+
+ switch (wake_up_ths_a.single_double_tap)
+ {
case LSM303AH_XL_ONLY_SINGLE:
*val = LSM303AH_XL_ONLY_SINGLE;
break;
+
case LSM303AH_XL_ONLY_DOUBLE:
*val = LSM303AH_XL_ONLY_DOUBLE;
break;
+
default:
*val = LSM303AH_XL_ONLY_SINGLE;
break;
}
+
return ret;
}
@@ -2891,7 +3329,9 @@ int32_t lsm303ah_xl_tap_src_get(stmdev_ctx_t *ctx,
lsm303ah_tap_src_a_t *val)
{
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_TAP_SRC_A, (uint8_t*) val, 1);
+
+ ret = lsm303ah_read_reg(ctx, LSM303AH_TAP_SRC_A, (uint8_t *) val, 1);
+
return ret;
}
@@ -2922,10 +3362,14 @@ int32_t lsm303ah_xl_6d_threshold_set(stmdev_ctx_t *ctx,
lsm303ah_tap_6d_ths_a_t tap_6d_ths_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_TAP_6D_THS_A, (uint8_t*)&tap_6d_ths_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_TAP_6D_THS_A,
+ (uint8_t *)&tap_6d_ths_a, 1);
+
+ if (ret == 0)
+ {
tap_6d_ths_a._6d_ths = (uint8_t)val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_TAP_6D_THS_A, (uint8_t*)&tap_6d_ths_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_TAP_6D_THS_A,
+ (uint8_t *)&tap_6d_ths_a, 1);
}
return ret;
@@ -2945,24 +3389,32 @@ int32_t lsm303ah_xl_6d_threshold_get(stmdev_ctx_t *ctx,
lsm303ah_tap_6d_ths_a_t tap_6d_ths_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_TAP_6D_THS_A, (uint8_t*)&tap_6d_ths_a, 1);
- switch (tap_6d_ths_a._6d_ths){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_TAP_6D_THS_A,
+ (uint8_t *)&tap_6d_ths_a, 1);
+
+ switch (tap_6d_ths_a._6d_ths)
+ {
case LSM303AH_XL_DEG_80:
*val = LSM303AH_XL_DEG_80;
break;
+
case LSM303AH_XL_DEG_70:
*val = LSM303AH_XL_DEG_70;
break;
+
case LSM303AH_XL_DEG_60:
*val = LSM303AH_XL_DEG_60;
break;
+
case LSM303AH_XL_DEG_50:
*val = LSM303AH_XL_DEG_50;
break;
+
default:
*val = LSM303AH_XL_DEG_80;
break;
}
+
return ret;
}
@@ -2979,10 +3431,14 @@ int32_t lsm303ah_xl_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
lsm303ah_tap_6d_ths_a_t tap_6d_ths_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_TAP_6D_THS_A, (uint8_t*)&tap_6d_ths_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_TAP_6D_THS_A,
+ (uint8_t *)&tap_6d_ths_a, 1);
+
+ if (ret == 0)
+ {
tap_6d_ths_a._4d_en = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_TAP_6D_THS_A, (uint8_t*)&tap_6d_ths_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_TAP_6D_THS_A,
+ (uint8_t *)&tap_6d_ths_a, 1);
}
return ret;
@@ -3001,7 +3457,8 @@ int32_t lsm303ah_xl_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm303ah_tap_6d_ths_a_t tap_6d_ths_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_TAP_6D_THS_A, (uint8_t*)&tap_6d_ths_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_TAP_6D_THS_A,
+ (uint8_t *)&tap_6d_ths_a, 1);
*val = tap_6d_ths_a._4d_en;
return ret;
@@ -3015,10 +3472,13 @@ int32_t lsm303ah_xl_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_6d_src_get(stmdev_ctx_t *ctx, lsm303ah_6d_src_a_t *val)
+int32_t lsm303ah_xl_6d_src_get(stmdev_ctx_t *ctx,
+ lsm303ah_6d_src_a_t *val)
{
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_6D_SRC_A, (uint8_t*) val, 1);
+
+ ret = lsm303ah_read_reg(ctx, LSM303AH_6D_SRC_A, (uint8_t *) val, 1);
+
return ret;
}
@@ -3049,17 +3509,27 @@ int32_t lsm303ah_xl_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm303ah_free_fall_a_t free_fall_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_DUR_A, (uint8_t*)&wake_up_dur_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_DUR_A,
+ (uint8_t *)&wake_up_dur_a, 1);
+
+ if (ret == 0)
+ {
wake_up_dur_a.ff_dur = (val & 0x20U) >> 5;
- ret = lsm303ah_write_reg(ctx, LSM303AH_WAKE_UP_DUR_A, (uint8_t*)&wake_up_dur_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_WAKE_UP_DUR_A,
+ (uint8_t *)&wake_up_dur_a, 1);
}
- if(ret == 0){
- ret = lsm303ah_read_reg(ctx, LSM303AH_FREE_FALL_A, (uint8_t*)&free_fall_a, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm303ah_read_reg(ctx, LSM303AH_FREE_FALL_A,
+ (uint8_t *)&free_fall_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
free_fall_a.ff_dur = 0x1FU & val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_FREE_FALL_A, (uint8_t*)&free_fall_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_FREE_FALL_A,
+ (uint8_t *)&free_fall_a, 1);
}
return ret;
@@ -3079,10 +3549,15 @@ int32_t lsm303ah_xl_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm303ah_free_fall_a_t free_fall_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_DUR_A, (uint8_t*)&wake_up_dur_a, 1);
- if(ret == 0){
- ret = lsm303ah_read_reg(ctx, LSM303AH_FREE_FALL_A, (uint8_t*)&free_fall_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_DUR_A,
+ (uint8_t *)&wake_up_dur_a, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm303ah_read_reg(ctx, LSM303AH_FREE_FALL_A,
+ (uint8_t *)&free_fall_a, 1);
}
+
*val = (wake_up_dur_a.ff_dur << 5) + free_fall_a.ff_dur;
return ret;
@@ -3101,10 +3576,14 @@ int32_t lsm303ah_xl_ff_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
lsm303ah_free_fall_a_t free_fall_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_FREE_FALL_A, (uint8_t*)&free_fall_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_FREE_FALL_A,
+ (uint8_t *)&free_fall_a, 1);
+
+ if (ret == 0)
+ {
free_fall_a.ff_ths = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_FREE_FALL_A, (uint8_t*)&free_fall_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_FREE_FALL_A,
+ (uint8_t *)&free_fall_a, 1);
}
return ret;
@@ -3123,7 +3602,8 @@ int32_t lsm303ah_xl_ff_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm303ah_free_fall_a_t free_fall_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_FREE_FALL_A, (uint8_t*)&free_fall_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_FREE_FALL_A,
+ (uint8_t *)&free_fall_a, 1);
*val = free_fall_a.ff_ths;
return ret;
@@ -3150,15 +3630,20 @@ int32_t lsm303ah_xl_ff_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_fifo_xl_module_batch_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm303ah_xl_fifo_xl_module_batch_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm303ah_fifo_ctrl_a_t fifo_ctrl_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_CTRL_A, (uint8_t*)&fifo_ctrl_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_CTRL_A,
+ (uint8_t *)&fifo_ctrl_a, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl_a.module_to_fifo = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_FIFO_CTRL_A, (uint8_t*)&fifo_ctrl_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_FIFO_CTRL_A,
+ (uint8_t *)&fifo_ctrl_a, 1);
}
return ret;
@@ -3179,7 +3664,8 @@ int32_t lsm303ah_xl_fifo_xl_module_batch_get(stmdev_ctx_t *ctx,
lsm303ah_fifo_ctrl_a_t fifo_ctrl_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_CTRL_A, (uint8_t*)&fifo_ctrl_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_CTRL_A,
+ (uint8_t *)&fifo_ctrl_a, 1);
*val = fifo_ctrl_a.module_to_fifo;
return ret;
@@ -3199,10 +3685,14 @@ int32_t lsm303ah_xl_fifo_mode_set(stmdev_ctx_t *ctx,
lsm303ah_fifo_ctrl_a_t fifo_ctrl_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_CTRL_A, (uint8_t*)&fifo_ctrl_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_CTRL_A,
+ (uint8_t *)&fifo_ctrl_a, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl_a.fmode = (uint8_t)val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_FIFO_CTRL_A, (uint8_t*)&fifo_ctrl_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_FIFO_CTRL_A,
+ (uint8_t *)&fifo_ctrl_a, 1);
}
return ret;
@@ -3222,27 +3712,36 @@ int32_t lsm303ah_xl_fifo_mode_get(stmdev_ctx_t *ctx,
lsm303ah_fifo_ctrl_a_t fifo_ctrl_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_CTRL_A, (uint8_t*)&fifo_ctrl_a, 1);
- switch (fifo_ctrl_a.fmode){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_CTRL_A,
+ (uint8_t *)&fifo_ctrl_a, 1);
+
+ switch (fifo_ctrl_a.fmode)
+ {
case LSM303AH_XL_BYPASS_MODE:
*val = LSM303AH_XL_BYPASS_MODE;
break;
+
case LSM303AH_XL_FIFO_MODE:
*val = LSM303AH_XL_FIFO_MODE;
break;
+
case LSM303AH_XL_STREAM_TO_FIFO_MODE:
*val = LSM303AH_XL_STREAM_TO_FIFO_MODE;
break;
+
case LSM303AH_XL_BYPASS_TO_STREAM_MODE:
*val = LSM303AH_XL_BYPASS_TO_STREAM_MODE;
break;
+
case LSM303AH_XL_STREAM_MODE:
*val = LSM303AH_XL_STREAM_MODE;
break;
+
default:
*val = LSM303AH_XL_BYPASS_MODE;
break;
}
+
return ret;
}
@@ -3257,7 +3756,9 @@ int32_t lsm303ah_xl_fifo_mode_get(stmdev_ctx_t *ctx,
int32_t lsm303ah_xl_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
{
int32_t ret;
- ret = lsm303ah_write_reg(ctx, LSM303AH_FIFO_THS_A, (uint8_t*)&val, 1);
+
+ ret = lsm303ah_write_reg(ctx, LSM303AH_FIFO_THS_A, (uint8_t *)&val, 1);
+
return ret;
}
@@ -3269,10 +3770,13 @@ int32_t lsm303ah_xl_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm303ah_xl_fifo_watermark_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
int32_t ret;
+
ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_THS_A, val, 1);
+
return ret;
}
@@ -3284,12 +3788,14 @@ int32_t lsm303ah_xl_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm303ah_xl_fifo_full_flag_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm303ah_fifo_src_a_t fifo_src_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_SRC_A, (uint8_t*)&fifo_src_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_SRC_A,
+ (uint8_t *)&fifo_src_a, 1);
*val = fifo_src_a.diff;
return ret;
@@ -3308,7 +3814,8 @@ int32_t lsm303ah_xl_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm303ah_fifo_src_a_t fifo_src_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_SRC_A, (uint8_t*)&fifo_src_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_SRC_A,
+ (uint8_t *)&fifo_src_a, 1);
*val = fifo_src_a.fifo_ovr;
return ret;
@@ -3327,7 +3834,8 @@ int32_t lsm303ah_xl_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm303ah_fifo_src_a_t fifo_src_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_SRC_A, (uint8_t*)&fifo_src_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_SRC_A,
+ (uint8_t *)&fifo_src_a, 1);
*val = fifo_src_a.fth;
return ret;
@@ -3341,19 +3849,24 @@ int32_t lsm303ah_xl_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
+int32_t lsm303ah_xl_fifo_data_level_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
lsm303ah_fifo_src_a_t fifo_src_a;
uint8_t fifo_sample_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_SRC_A, (uint8_t*)&fifo_src_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_SRC_A,
+ (uint8_t *)&fifo_src_a, 1);
+
+ if (ret == 0)
+ {
ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_SRC_A, &fifo_sample_a, 1);
*val = fifo_src_a.diff;
*val = *val << 7;
*val += fifo_sample_a;
}
+
return ret;
}
@@ -3369,7 +3882,9 @@ int32_t lsm303ah_xl_fifo_src_get(stmdev_ctx_t *ctx,
lsm303ah_fifo_src_a_t *val)
{
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_SRC_A, (uint8_t*) val, 1);
+
+ ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_SRC_A, (uint8_t *) val, 1);
+
return ret;
}
@@ -3399,11 +3914,13 @@ int32_t lsm303ah_xl_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm303ah_read_reg(ctx, LSM303AH_STEP_COUNTER_MINTHS_A,
- (uint8_t*)&step_counter_minths_a, 1);
- if(ret == 0){
+ (uint8_t *)&step_counter_minths_a, 1);
+
+ if (ret == 0)
+ {
step_counter_minths_a.sc_mths = val;
ret = lsm303ah_write_reg(ctx, LSM303AH_STEP_COUNTER_MINTHS_A,
- (uint8_t*)&step_counter_minths_a, 1);
+ (uint8_t *)&step_counter_minths_a, 1);
}
return ret;
@@ -3417,13 +3934,14 @@ int32_t lsm303ah_xl_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm303ah_xl_pedo_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm303ah_step_counter_minths_a_t step_counter_minths_a;
int32_t ret;
ret = lsm303ah_read_reg(ctx, LSM303AH_STEP_COUNTER_MINTHS_A,
- (uint8_t*)&step_counter_minths_a, 1);
+ (uint8_t *)&step_counter_minths_a, 1);
*val = step_counter_minths_a.sc_mths;
return ret;
@@ -3438,17 +3956,19 @@ int32_t lsm303ah_xl_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm303ah_xl_pedo_full_scale_set(stmdev_ctx_t *ctx,
- lsm303ah_xl_pedo4g_t val)
+ lsm303ah_xl_pedo4g_t val)
{
lsm303ah_step_counter_minths_a_t step_counter_minths_a;
int32_t ret;
ret = lsm303ah_read_reg(ctx, LSM303AH_STEP_COUNTER_MINTHS_A,
- (uint8_t*)&step_counter_minths_a, 1);
- if(ret == 0){
+ (uint8_t *)&step_counter_minths_a, 1);
+
+ if (ret == 0)
+ {
step_counter_minths_a.pedo4g = (uint8_t)val;
ret = lsm303ah_write_reg(ctx, LSM303AH_STEP_COUNTER_MINTHS_A,
- (uint8_t*)&step_counter_minths_a, 1);
+ (uint8_t *)&step_counter_minths_a, 1);
}
return ret;
@@ -3463,23 +3983,29 @@ int32_t lsm303ah_xl_pedo_full_scale_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm303ah_xl_pedo_full_scale_get(stmdev_ctx_t *ctx,
- lsm303ah_xl_pedo4g_t *val)
+ lsm303ah_xl_pedo4g_t *val)
{
lsm303ah_step_counter_minths_a_t step_counter_minths_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_STEP_COUNTER_MINTHS_A, (uint8_t*)&step_counter_minths_a, 1);
- switch (step_counter_minths_a.pedo4g){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_STEP_COUNTER_MINTHS_A,
+ (uint8_t *)&step_counter_minths_a, 1);
+
+ switch (step_counter_minths_a.pedo4g)
+ {
case LSM303AH_XL_PEDO_AT_2g:
*val = LSM303AH_XL_PEDO_AT_2g;
break;
+
case LSM303AH_XL_PEDO_AT_4g:
*val = LSM303AH_XL_PEDO_AT_4g;
break;
+
default:
*val = LSM303AH_XL_PEDO_AT_2g;
break;
}
+
return ret;
}
@@ -3491,17 +4017,20 @@ int32_t lsm303ah_xl_pedo_full_scale_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm303ah_xl_pedo_step_reset_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm303ah_step_counter_minths_a_t step_counter_minths_a;
int32_t ret;
ret = lsm303ah_read_reg(ctx, LSM303AH_STEP_COUNTER_MINTHS_A,
- (uint8_t*)&step_counter_minths_a, 1);
- if(ret == 0){
+ (uint8_t *)&step_counter_minths_a, 1);
+
+ if (ret == 0)
+ {
step_counter_minths_a.rst_nstep = val;
ret = lsm303ah_write_reg(ctx, LSM303AH_STEP_COUNTER_MINTHS_A,
- (uint8_t*)&step_counter_minths_a, 1);
+ (uint8_t *)&step_counter_minths_a, 1);
}
return ret;
@@ -3515,13 +4044,14 @@ int32_t lsm303ah_xl_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm303ah_xl_pedo_step_reset_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm303ah_step_counter_minths_a_t step_counter_minths_a;
int32_t ret;
ret = lsm303ah_read_reg(ctx, LSM303AH_STEP_COUNTER_MINTHS_A,
- (uint8_t*)&step_counter_minths_a, 1);
+ (uint8_t *)&step_counter_minths_a, 1);
*val = step_counter_minths_a.rst_nstep;
return ret;
@@ -3541,7 +4071,8 @@ int32_t lsm303ah_xl_pedo_step_detect_flag_get(stmdev_ctx_t *ctx,
lsm303ah_func_ck_gate_a_t func_ck_gate_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_FUNC_CK_GATE_A, (uint8_t*)&func_ck_gate_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_FUNC_CK_GATE_A,
+ (uint8_t *)&func_ck_gate_a, 1);
*val = func_ck_gate_a.step_detect;
return ret;
@@ -3560,10 +4091,14 @@ int32_t lsm303ah_xl_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val)
lsm303ah_func_ctrl_a_t func_ctrl_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_FUNC_CTRL_A, (uint8_t*)&func_ctrl_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_FUNC_CTRL_A,
+ (uint8_t *)&func_ctrl_a, 1);
+
+ if (ret == 0)
+ {
func_ctrl_a.step_cnt_on = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_FUNC_CTRL_A, (uint8_t*)&func_ctrl_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_FUNC_CTRL_A,
+ (uint8_t *)&func_ctrl_a, 1);
}
return ret;
@@ -3582,7 +4117,8 @@ int32_t lsm303ah_xl_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm303ah_func_ctrl_a_t func_ctrl_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_FUNC_CTRL_A, (uint8_t*)&func_ctrl_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_FUNC_CTRL_A,
+ (uint8_t *)&func_ctrl_a, 1);
*val = func_ctrl_a.step_cnt_on;
return ret;
@@ -3596,20 +4132,29 @@ int32_t lsm303ah_xl_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm303ah_xl_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm303ah_pedo_deb_reg_a_t pedo_deb_reg_a;
int32_t ret;
ret = lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_ADV_BANK);
- if(ret == 0){
- ret = lsm303ah_read_reg(ctx, LSM303AH_PEDO_DEB_REG_A, (uint8_t*)&pedo_deb_reg_a, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm303ah_read_reg(ctx, LSM303AH_PEDO_DEB_REG_A,
+ (uint8_t *)&pedo_deb_reg_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
pedo_deb_reg_a.deb_step = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_PEDO_DEB_REG_A, (uint8_t*)&pedo_deb_reg_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_PEDO_DEB_REG_A,
+ (uint8_t *)&pedo_deb_reg_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_USER_BANK);
}
@@ -3624,16 +4169,22 @@ int32_t lsm303ah_xl_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm303ah_xl_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm303ah_pedo_deb_reg_a_t pedo_deb_reg_a;
int32_t ret;
ret = lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_ADV_BANK);
- if(ret == 0){
- ret = lsm303ah_read_reg(ctx, LSM303AH_PEDO_DEB_REG_A, (uint8_t*)&pedo_deb_reg_a, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm303ah_read_reg(ctx, LSM303AH_PEDO_DEB_REG_A,
+ (uint8_t *)&pedo_deb_reg_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = pedo_deb_reg_a.deb_step;
ret = lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_USER_BANK);
}
@@ -3657,14 +4208,22 @@ int32_t lsm303ah_xl_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_ADV_BANK);
- if(ret == 0){
- ret = lsm303ah_read_reg(ctx, LSM303AH_PEDO_DEB_REG_A, (uint8_t*)&pedo_deb_reg_a, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm303ah_read_reg(ctx, LSM303AH_PEDO_DEB_REG_A,
+ (uint8_t *)&pedo_deb_reg_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
pedo_deb_reg_a.deb_time = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_PEDO_DEB_REG_A, (uint8_t*)&pedo_deb_reg_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_PEDO_DEB_REG_A,
+ (uint8_t *)&pedo_deb_reg_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_USER_BANK);
}
@@ -3687,10 +4246,15 @@ int32_t lsm303ah_xl_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_ADV_BANK);
- if(ret == 0){
- ret = lsm303ah_read_reg(ctx, LSM303AH_PEDO_DEB_REG_A, (uint8_t*)&pedo_deb_reg_a, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm303ah_read_reg(ctx, LSM303AH_PEDO_DEB_REG_A,
+ (uint8_t *)&pedo_deb_reg_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = pedo_deb_reg_a.deb_time;
ret = lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_USER_BANK);
}
@@ -3707,15 +4271,20 @@ int32_t lsm303ah_xl_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_pedo_steps_period_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm303ah_xl_pedo_steps_period_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
ret = lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_ADV_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm303ah_write_reg(ctx, LSM303AH_STEP_COUNT_DELTA_A, buff, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_USER_BANK);
}
@@ -3731,15 +4300,20 @@ int32_t lsm303ah_xl_pedo_steps_period_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_pedo_steps_period_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm303ah_xl_pedo_steps_period_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
ret = lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_ADV_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm303ah_read_reg(ctx, LSM303AH_STEP_COUNT_DELTA_A, buff, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_USER_BANK);
}
@@ -3773,7 +4347,8 @@ int32_t lsm303ah_xl_motion_data_ready_flag_get(stmdev_ctx_t *ctx,
lsm303ah_func_ck_gate_a_t func_ck_gate_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_FUNC_CK_GATE_A, (uint8_t*)&func_ck_gate_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_FUNC_CK_GATE_A,
+ (uint8_t *)&func_ck_gate_a, 1);
*val = func_ck_gate_a.sig_mot_detect;
return ret;
@@ -3792,10 +4367,14 @@ int32_t lsm303ah_xl_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val)
lsm303ah_func_ctrl_a_t func_ctrl_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_FUNC_CTRL_A, (uint8_t*)&func_ctrl_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_FUNC_CTRL_A,
+ (uint8_t *)&func_ctrl_a, 1);
+
+ if (ret == 0)
+ {
func_ctrl_a.sign_mot_on = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_FUNC_CTRL_A, (uint8_t*)&func_ctrl_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_FUNC_CTRL_A,
+ (uint8_t *)&func_ctrl_a, 1);
}
return ret;
@@ -3814,7 +4393,8 @@ int32_t lsm303ah_xl_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm303ah_func_ctrl_a_t func_ctrl_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_FUNC_CTRL_A, (uint8_t*)&func_ctrl_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_FUNC_CTRL_A,
+ (uint8_t *)&func_ctrl_a, 1);
*val = func_ctrl_a.sign_mot_on;
return ret;
@@ -3832,20 +4412,27 @@ int32_t lsm303ah_xl_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_motion_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm303ah_xl_motion_threshold_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm303ah_sm_ths_a_t sm_ths_a;
int32_t ret;
ret = lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_ADV_BANK);
- if(ret == 0){
- ret = lsm303ah_read_reg(ctx, LSM303AH_SM_THS_A, (uint8_t*)&sm_ths_a, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm303ah_read_reg(ctx, LSM303AH_SM_THS_A, (uint8_t *)&sm_ths_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
sm_ths_a.sm_ths = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_SM_THS_A, (uint8_t*)&sm_ths_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_SM_THS_A, (uint8_t *)&sm_ths_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_USER_BANK);
}
@@ -3864,16 +4451,21 @@ int32_t lsm303ah_xl_motion_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm303ah_xl_motion_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm303ah_xl_motion_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm303ah_sm_ths_a_t sm_ths_a;
int32_t ret;
ret = lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_ADV_BANK);
- if(ret == 0){
- ret = lsm303ah_read_reg(ctx, LSM303AH_SM_THS_A, (uint8_t*)&sm_ths_a, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm303ah_read_reg(ctx, LSM303AH_SM_THS_A, (uint8_t *)&sm_ths_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = sm_ths_a.sm_ths;
ret = lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_USER_BANK);
}
@@ -3908,7 +4500,8 @@ int32_t lsm303ah_xl_tilt_data_ready_flag_get(stmdev_ctx_t *ctx,
lsm303ah_func_ck_gate_a_t func_ck_gate_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_FUNC_CK_GATE_A, (uint8_t*)&func_ck_gate_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_FUNC_CK_GATE_A,
+ (uint8_t *)&func_ck_gate_a, 1);
*val = func_ck_gate_a.tilt_int;
return ret;
@@ -3927,10 +4520,14 @@ int32_t lsm303ah_xl_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val)
lsm303ah_func_ctrl_a_t func_ctrl_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_FUNC_CTRL_A, (uint8_t*)&func_ctrl_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_FUNC_CTRL_A,
+ (uint8_t *)&func_ctrl_a, 1);
+
+ if (ret == 0)
+ {
func_ctrl_a.tilt_on = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_FUNC_CTRL_A, (uint8_t*)&func_ctrl_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_FUNC_CTRL_A,
+ (uint8_t *)&func_ctrl_a, 1);
}
return ret;
@@ -3949,7 +4546,8 @@ int32_t lsm303ah_xl_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm303ah_func_ctrl_a_t func_ctrl_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_FUNC_CTRL_A, (uint8_t*)&func_ctrl_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_FUNC_CTRL_A,
+ (uint8_t *)&func_ctrl_a, 1);
*val = func_ctrl_a.tilt_on;
return ret;
@@ -3981,10 +4579,14 @@ int32_t lsm303ah_xl_module_sens_set(stmdev_ctx_t *ctx, uint8_t val)
lsm303ah_func_ctrl_a_t func_ctrl_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_FUNC_CTRL_A, (uint8_t*)&func_ctrl_a, 1);
- if(ret == 0){
+ ret = lsm303ah_read_reg(ctx, LSM303AH_FUNC_CTRL_A,
+ (uint8_t *)&func_ctrl_a, 1);
+
+ if (ret == 0)
+ {
func_ctrl_a.module_on = val;
- ret = lsm303ah_write_reg(ctx, LSM303AH_FUNC_CTRL_A, (uint8_t*)&func_ctrl_a, 1);
+ ret = lsm303ah_write_reg(ctx, LSM303AH_FUNC_CTRL_A,
+ (uint8_t *)&func_ctrl_a, 1);
}
return ret;
@@ -4003,7 +4605,8 @@ int32_t lsm303ah_xl_module_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm303ah_func_ctrl_a_t func_ctrl_a;
int32_t ret;
- ret = lsm303ah_read_reg(ctx, LSM303AH_FUNC_CTRL_A, (uint8_t*)&func_ctrl_a, 1);
+ ret = lsm303ah_read_reg(ctx, LSM303AH_FUNC_CTRL_A,
+ (uint8_t *)&func_ctrl_a, 1);
*val = func_ctrl_a.module_on;
return ret;
diff --git a/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.h b/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.h
index 264edbb3ef192c11c3b89245cdeb2c91eec2c3f5..9f48086dd0dca5b8029f5e8eff76ac94ad4905e0 100644
--- a/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.h
+++ b/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file lsm303ah_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lsm303ah_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lsm303ah_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lsm303ah_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LSM303AH_REGS_H
#define LSM303AH_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup LSM303AH
@@ -35,6 +36,37 @@
*
*/
+/** @defgroup Endianness definitions
+ * @{
+ *
+ */
+
+#ifndef DRV_BYTE_ORDER
+#ifndef __BYTE_ORDER__
+
+#define DRV_LITTLE_ENDIAN 1234
+#define DRV_BIG_ENDIAN 4321
+
+/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
+ * by uncommenting the define which fits your platform endianness
+ */
+//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
+#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
+
+#else /* defined __BYTE_ORDER__ */
+
+#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
+#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
+#define DRV_BYTE_ORDER __BYTE_ORDER__
+
+#endif /* __BYTE_ORDER__*/
+#endif /* DRV_BYTE_ORDER */
+
+/**
+ * @}
+ *
+ */
+
/** @defgroup STMicroelectronics sensors common types
* @{
*
@@ -43,7 +75,9 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -52,6 +86,16 @@ typedef struct{
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} bitwise_t;
#define PROPERTY_DISABLE (0U)
@@ -65,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -89,15 +134,16 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
- * Unico / Unicleo tools available on STMicroelectronics
- * web site.
+ * You can create a sensor configuration by your own or using
+ * Unico / Unicleo tools available on STMicroelectronics
+ * web site.
*
* @{
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -119,7 +165,7 @@ typedef struct {
*
*/
- /** I2C Device Address 8 bit format **/
+/** I2C Device Address 8 bit format **/
#define LSM303AH_I2C_ADD_XL 0x3BU
#define LSM303AH_I2C_ADD_MG 0x3DU
@@ -135,15 +181,25 @@ typedef struct {
#define LSM303AH_MODULE_8BIT_A 0x0CU
#define LSM303AH_WHO_AM_I_A 0x0FU
#define LSM303AH_CTRL1_A 0x20U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bdu : 1;
uint8_t hf_odr : 1;
uint8_t fs : 2;
uint8_t odr : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr : 4;
+ uint8_t fs : 2;
+ uint8_t hf_odr : 1;
+ uint8_t bdu : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303ah_ctrl1_a_t;
#define LSM303AH_CTRL2_A 0x21U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t i2c_disable : 1;
uint8_t if_add_inc : 1;
@@ -152,10 +208,22 @@ typedef struct {
uint8_t not_used_01 : 1;
uint8_t soft_reset : 1;
uint8_t boot : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t boot : 1;
+ uint8_t soft_reset : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t func_cfg_en : 1;
+ uint8_t fds_slope : 1;
+ uint8_t if_add_inc : 1;
+ uint8_t i2c_disable : 1;
+ uint8_t sim : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303ah_ctrl2_a_t;
#define LSM303AH_CTRL3_A 0x22U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t pp_od : 1;
uint8_t h_lactive : 1;
uint8_t lir : 1;
@@ -163,10 +231,21 @@ typedef struct {
uint8_t tap_y_en : 1;
uint8_t tap_x_en : 1;
uint8_t st : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t st : 2;
+ uint8_t tap_x_en : 1;
+ uint8_t tap_y_en : 1;
+ uint8_t tap_z_en : 1;
+ uint8_t lir : 1;
+ uint8_t h_lactive : 1;
+ uint8_t pp_od : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303ah_ctrl3_a_t;
#define LSM303AH_CTRL4_A 0x23U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_drdy : 1;
uint8_t int1_fth : 1;
uint8_t int1_6d : 1;
@@ -174,11 +253,23 @@ typedef struct {
uint8_t int1_ff : 1;
uint8_t int1_wu : 1;
uint8_t int1_s_tap : 1;
- uint8_t not_used_01 : 1;
+ uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t int1_s_tap : 1;
+ uint8_t int1_wu : 1;
+ uint8_t int1_ff : 1;
+ uint8_t int1_tap : 1;
+ uint8_t int1_6d : 1;
+ uint8_t int1_fth : 1;
+ uint8_t int1_drdy : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303ah_ctrl4_a_t;
#define LSM303AH_CTRL5_A 0x24U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_drdy : 1;
uint8_t int2_fth : 1;
uint8_t int2_step : 1;
@@ -187,20 +278,41 @@ typedef struct {
uint8_t int2_on_int1 : 1;
uint8_t int2_boot : 1;
uint8_t drdy_pulsed : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t drdy_pulsed : 1;
+ uint8_t int2_boot : 1;
+ uint8_t int2_on_int1 : 1;
+ uint8_t int2_tilt : 1;
+ uint8_t int2_sig_mot : 1;
+ uint8_t int2_step : 1;
+ uint8_t int2_fth : 1;
+ uint8_t int2_drdy : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303ah_ctrl5_a_t;
#define LSM303AH_FIFO_CTRL_A 0x25U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t if_cs_pu_dis : 1;
uint8_t not_used_01 : 2;
uint8_t module_to_fifo : 1;
uint8_t int2_step_count_ov : 1;
uint8_t fmode : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fmode : 3;
+ uint8_t int2_step_count_ov : 1;
+ uint8_t module_to_fifo : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t if_cs_pu_dis : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303ah_fifo_ctrl_a_t;
#define LSM303AH_OUT_T_A 0x26U
#define LSM303AH_STATUS_A 0x27U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t drdy : 1;
uint8_t ff_ia : 1;
uint8_t _6d_ia : 1;
@@ -209,6 +321,16 @@ typedef struct {
uint8_t sleep_state : 1;
uint8_t wu_ia : 1;
uint8_t fifo_ths : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fifo_ths : 1;
+ uint8_t wu_ia : 1;
+ uint8_t sleep_state : 1;
+ uint8_t double_tap : 1;
+ uint8_t single_tap : 1;
+ uint8_t _6d_ia : 1;
+ uint8_t ff_ia : 1;
+ uint8_t drdy : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303ah_status_a_t;
#define LSM303AH_OUT_X_L_A 0x28U
@@ -219,51 +341,96 @@ typedef struct {
#define LSM303AH_OUT_Z_H_A 0x2DU
#define LSM303AH_FIFO_THS_A 0x2EU
#define LSM303AH_FIFO_SRC_A 0x2FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 5;
uint8_t diff : 1;
uint8_t fifo_ovr : 1;
uint8_t fth : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fth : 1;
+ uint8_t fifo_ovr : 1;
+ uint8_t diff : 1;
+ uint8_t not_used_01 : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm303ah_fifo_src_a_t;
#define LSM303AH_FIFO_SAMPLES_A 0x30U
#define LSM303AH_TAP_6D_THS_A 0x31U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_ths : 5;
uint8_t _6d_ths : 2;
uint8_t _4d_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t _4d_en : 1;
+ uint8_t _6d_ths : 2;
+ uint8_t tap_ths : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm303ah_tap_6d_ths_a_t;
#define LSM303AH_INT_DUR_A 0x32U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shock : 2;
uint8_t quiet : 2;
uint8_t lat : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t lat : 4;
+ uint8_t quiet : 2;
+ uint8_t shock : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm303ah_int_dur_a_t;
#define LSM303AH_WAKE_UP_THS_A 0x33U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wu_ths : 6;
uint8_t sleep_on : 1;
uint8_t single_double_tap : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t single_double_tap : 1;
+ uint8_t sleep_on : 1;
+ uint8_t wu_ths : 6;
+#endif /* DRV_BYTE_ORDER */
} lsm303ah_wake_up_ths_a_t;
#define LSM303AH_WAKE_UP_DUR_A 0x34U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sleep_dur : 4;
uint8_t int1_fss7 : 1;
uint8_t wu_dur : 2;
uint8_t ff_dur : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t ff_dur : 1;
+ uint8_t wu_dur : 2;
+ uint8_t int1_fss7 : 1;
+ uint8_t sleep_dur : 4;
+#endif /* DRV_BYTE_ORDER */
} lsm303ah_wake_up_dur_a_t;
#define LSM303AH_FREE_FALL_A 0x35U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ths : 3;
uint8_t ff_dur : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t ff_dur : 5;
+ uint8_t ff_ths : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm303ah_free_fall_a_t;
#define LSM303AH_STATUS_DUP_A 0x36U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t drdy : 1;
uint8_t ff_ia : 1;
uint8_t _6d_ia : 1;
@@ -272,10 +439,22 @@ typedef struct {
uint8_t sleep_state : 1;
uint8_t wu_ia : 1;
uint8_t ovr : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t ovr : 1;
+ uint8_t wu_ia : 1;
+ uint8_t sleep_state : 1;
+ uint8_t double_tap : 1;
+ uint8_t single_tap : 1;
+ uint8_t _6d_ia : 1;
+ uint8_t ff_ia : 1;
+ uint8_t drdy : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303ah_status_dup_a_t;
#define LSM303AH_WAKE_UP_SRC_A 0x37U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_wu : 1;
uint8_t y_wu : 1;
uint8_t x_wu : 1;
@@ -283,10 +462,21 @@ typedef struct {
uint8_t sleep_state_ia : 1;
uint8_t ff_ia : 1;
uint8_t not_used_01 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 2;
+ uint8_t ff_ia : 1;
+ uint8_t sleep_state_ia : 1;
+ uint8_t wu_ia : 1;
+ uint8_t x_wu : 1;
+ uint8_t y_wu : 1;
+ uint8_t z_wu : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303ah_wake_up_src_a_t;
#define LSM303AH_TAP_SRC_A 0x38U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_tap : 1;
uint8_t y_tap : 1;
uint8_t x_tap : 1;
@@ -295,10 +485,22 @@ typedef struct {
uint8_t single_tap : 1;
uint8_t tap_ia : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t tap_ia : 1;
+ uint8_t single_tap : 1;
+ uint8_t double_tap : 1;
+ uint8_t tap_sign : 1;
+ uint8_t x_tap : 1;
+ uint8_t y_tap : 1;
+ uint8_t z_tap : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303ah_tap_src_a_t;
#define LSM303AH_6D_SRC_A 0x39U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
uint8_t yl : 1;
@@ -307,19 +509,38 @@ typedef struct {
uint8_t zh : 1;
uint8_t _6d_ia : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t _6d_ia : 1;
+ uint8_t zh : 1;
+ uint8_t zl : 1;
+ uint8_t yh : 1;
+ uint8_t yl : 1;
+ uint8_t xh : 1;
+ uint8_t xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303ah_6d_src_a_t;
#define LSM303AH_STEP_COUNTER_MINTHS_A 0x3AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sc_mths : 6;
uint8_t pedo4g : 1;
uint8_t rst_nstep : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t rst_nstep : 1;
+ uint8_t pedo4g : 1;
+ uint8_t sc_mths : 6;
+#endif /* DRV_BYTE_ORDER */
} lsm303ah_step_counter_minths_a_t;
#define LSM303AH_STEP_COUNTER_L_A 0x3BU
#define LSM303AH_STEP_COUNTER_H_A 0x3CU
#define LSM303AH_FUNC_CK_GATE_A 0x3DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ck_gate_func : 1;
uint8_t step_detect : 1;
uint8_t rst_pedo : 1;
@@ -327,44 +548,81 @@ typedef struct {
uint8_t sig_mot_detect : 1;
uint8_t fs_src : 2;
uint8_t tilt_int : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t tilt_int : 1;
+ uint8_t fs_src : 2;
+ uint8_t sig_mot_detect : 1;
+ uint8_t rst_sign_mot : 1;
+ uint8_t rst_pedo : 1;
+ uint8_t step_detect : 1;
+ uint8_t ck_gate_func : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303ah_func_ck_gate_a_t;
#define LSM303AH_FUNC_SRC_A 0x3EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t module_ready : 1;
uint8_t rst_tilt : 1;
uint8_t not_used_02 : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 5;
+ uint8_t rst_tilt : 1;
+ uint8_t module_ready : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303ah_func_src_a_t;
#define LSM303AH_FUNC_CTRL_A 0x3FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t step_cnt_on : 1;
uint8_t sign_mot_on : 1;
uint8_t not_used_01 : 2;
uint8_t tilt_on : 1;
uint8_t module_on : 1;
uint8_t not_used_02 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 2;
+ uint8_t module_on : 1;
+ uint8_t tilt_on : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t sign_mot_on : 1;
+ uint8_t step_cnt_on : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303ah_func_ctrl_a_t;
#define LSM303AH_PEDO_DEB_REG_A 0x2BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t deb_step : 3;
uint8_t deb_time : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t deb_time : 5;
+ uint8_t deb_step : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm303ah_pedo_deb_reg_a_t;
#define LSM303AH_SM_THS_A 0x34U
-typedef struct {
+typedef struct
+{
uint8_t sm_ths : 8;
} lsm303ah_sm_ths_a_t;
#define LSM303AH_STEP_COUNT_DELTA_A 0x3AU
-typedef struct {
+typedef struct
+{
uint8_t step_count_d : 8;
} lsm303ah_step_count_delta_a_t;
#define LSM303AH_CTRL2_ADV_A 0x3FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t i2c_disable : 1;
uint8_t if_add_inc : 1;
@@ -373,6 +631,16 @@ typedef struct {
uint8_t not_used_01 : 1;
uint8_t soft_reset : 1;
uint8_t boot : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t boot : 1;
+ uint8_t soft_reset : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t func_cfg_en : 1;
+ uint8_t fds_slope : 1;
+ uint8_t if_add_inc : 1;
+ uint8_t i2c_disable : 1;
+ uint8_t sim : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303ah_ctrl2_adv_a_t;
#define LSM303AH_OFFSET_X_REG_L_M 0x45U
@@ -383,26 +651,47 @@ typedef struct {
#define LSM303AH_OFFSET_Z_REG_H_M 0x4AU
#define LSM303AH_WHO_AM_I_M 0x4FU
#define LSM303AH_CFG_REG_A_M 0x60U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t md : 2;
uint8_t odr : 2;
uint8_t lp : 1;
uint8_t soft_rst : 1;
uint8_t reboot : 1;
uint8_t comp_temp_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t comp_temp_en : 1;
+ uint8_t reboot : 1;
+ uint8_t soft_rst : 1;
+ uint8_t lp : 1;
+ uint8_t odr : 2;
+ uint8_t md : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm303ah_cfg_reg_a_m_t;
#define LSM303AH_CFG_REG_B_M 0x61U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lpf : 1;
uint8_t set_rst : 2; /* off_canc + set_freq */
uint8_t int_on_dataoff : 1;
uint8_t off_canc_one_shot : 1;
uint8_t not_used_01 : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 3;
+ uint8_t off_canc_one_shot : 1;
+ uint8_t int_on_dataoff : 1;
+ uint8_t set_rst : 2; /* off_canc + set_freq */
+ uint8_t lpf : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303ah_cfg_reg_b_m_t;
#define LSM303AH_CFG_REG_C_M 0x62U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int_mag : 1;
uint8_t self_test : 1;
uint8_t not_used_01 : 1;
@@ -411,10 +700,22 @@ typedef struct {
uint8_t i2c_dis : 1;
uint8_t int_mag_pin : 1;
uint8_t not_used_02 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 1;
+ uint8_t int_mag_pin : 1;
+ uint8_t i2c_dis : 1;
+ uint8_t bdu : 1;
+ uint8_t ble : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t self_test : 1;
+ uint8_t int_mag : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303ah_cfg_reg_c_m_t;
#define LSM303AH_INT_CRTL_REG_M 0x63U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ien : 1;
uint8_t iel : 1;
uint8_t iea : 1;
@@ -422,11 +723,22 @@ typedef struct {
uint8_t zien : 1;
uint8_t yien : 1;
uint8_t xien : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t xien : 1;
+ uint8_t yien : 1;
+ uint8_t zien : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t iea : 1;
+ uint8_t iel : 1;
+ uint8_t ien : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303ah_int_crtl_reg_m_t;
#define LSM303AH_INT_SOURCE_REG_M 0x64U
-typedef struct {
- uint8_t _int : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t _int : 1;
uint8_t mroi : 1;
uint8_t n_th_s_z : 1;
uint8_t n_th_s_y : 1;
@@ -434,12 +746,24 @@ typedef struct {
uint8_t p_th_s_z : 1;
uint8_t p_th_s_y : 1;
uint8_t p_th_s_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_th_s_x : 1;
+ uint8_t p_th_s_y : 1;
+ uint8_t p_th_s_z : 1;
+ uint8_t n_th_s_x : 1;
+ uint8_t n_th_s_y : 1;
+ uint8_t n_th_s_z : 1;
+ uint8_t mroi : 1;
+ uint8_t _int : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303ah_int_source_reg_m_t;
#define LSM303AH_INT_THS_L_REG_M 0x65U
#define LSM303AH_INT_THS_H_REG_M 0x66U
#define LSM303AH_STATUS_REG_M 0x67U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xda : 1;
uint8_t yda : 1;
uint8_t zda : 1;
@@ -448,6 +772,16 @@ typedef struct {
uint8_t yor : 1;
uint8_t zor : 1;
uint8_t zyxor : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t zyxor : 1;
+ uint8_t zor : 1;
+ uint8_t yor : 1;
+ uint8_t _xor : 1;
+ uint8_t zyxda : 1;
+ uint8_t zda : 1;
+ uint8_t yda : 1;
+ uint8_t xda : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm303ah_status_reg_m_t;
#define LSM303AH_OUTX_L_REG_M 0x68U
@@ -459,9 +793,9 @@ typedef struct {
/**
* @defgroup LSM303AH_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -469,7 +803,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
lsm303ah_ctrl1_a_t ctrl1_a;
lsm303ah_ctrl2_a_t ctrl2_a;
lsm303ah_ctrl3_a_t ctrl3_a;
@@ -510,21 +845,24 @@ typedef union{
*
*/
-int32_t lsm303ah_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lsm303ah_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t lsm303ah_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lsm303ah_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-extern float_t lsm303ah_from_fs2g_to_mg(int16_t lsb);
-extern float_t lsm303ah_from_fs4g_to_mg(int16_t lsb);
-extern float_t lsm303ah_from_fs8g_to_mg(int16_t lsb);
-extern float_t lsm303ah_from_fs16g_to_mg(int16_t lsb);
+float_t lsm303ah_from_fs2g_to_mg(int16_t lsb);
+float_t lsm303ah_from_fs4g_to_mg(int16_t lsb);
+float_t lsm303ah_from_fs8g_to_mg(int16_t lsb);
+float_t lsm303ah_from_fs16g_to_mg(int16_t lsb);
-extern float_t lsm303ah_from_lsb_to_mgauss(int16_t lsb);
+float_t lsm303ah_from_lsb_to_mgauss(int16_t lsb);
-extern float_t lsm303ah_from_lsb_to_celsius(int16_t lsb);
+float_t lsm303ah_from_lsb_to_celsius(int16_t lsb);
-typedef struct {
+typedef struct
+{
lsm303ah_fifo_src_a_t fifo_src_a;
lsm303ah_status_dup_a_t status_dup_a;
lsm303ah_wake_up_src_a_t wake_up_src_a;
@@ -537,13 +875,18 @@ int32_t lsm303ah_xl_all_sources_get(stmdev_ctx_t *ctx,
lsm303ah_xl_all_sources_t *val);
-int32_t lsm303ah_xl_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm303ah_xl_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm303ah_xl_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm303ah_xl_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm303ah_mg_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm303ah_mg_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm303ah_mg_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm303ah_mg_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM303AH_MG_LSB_AT_LOW_ADD = 0,
LSM303AH_MG_MSB_AT_LOW_ADD = 1,
} lsm303ah_mg_ble_t;
@@ -552,7 +895,8 @@ int32_t lsm303ah_mg_data_format_set(stmdev_ctx_t *ctx,
int32_t lsm303ah_mg_data_format_get(stmdev_ctx_t *ctx,
lsm303ah_mg_ble_t *val);
-typedef enum {
+typedef enum
+{
LSM303AH_XL_2g = 0,
LSM303AH_XL_16g = 1,
LSM303AH_XL_4g = 2,
@@ -563,7 +907,8 @@ int32_t lsm303ah_xl_full_scale_set(stmdev_ctx_t *ctx,
int32_t lsm303ah_xl_full_scale_get(stmdev_ctx_t *ctx,
lsm303ah_xl_fs_t *val);
-typedef enum {
+typedef enum
+{
LSM303AH_XL_ODR_OFF = 0x00,
LSM303AH_XL_ODR_1Hz_LP = 0x08,
LSM303AH_XL_ODR_12Hz5_LP = 0x09,
@@ -584,8 +929,10 @@ typedef enum {
LSM303AH_XL_ODR_3k2Hz_HF = 0x16,
LSM303AH_XL_ODR_6k4Hz_HF = 0x17,
} lsm303ah_xl_odr_t;
-int32_t lsm303ah_xl_data_rate_set(stmdev_ctx_t *ctx, lsm303ah_xl_odr_t val);
-int32_t lsm303ah_xl_data_rate_get(stmdev_ctx_t *ctx, lsm303ah_xl_odr_t *val);
+int32_t lsm303ah_xl_data_rate_set(stmdev_ctx_t *ctx,
+ lsm303ah_xl_odr_t val);
+int32_t lsm303ah_xl_data_rate_get(stmdev_ctx_t *ctx,
+ lsm303ah_xl_odr_t *val);
int32_t lsm303ah_xl_status_reg_get(stmdev_ctx_t *ctx,
lsm303ah_status_a_t *val);
@@ -593,15 +940,17 @@ int32_t lsm303ah_xl_status_reg_get(stmdev_ctx_t *ctx,
int32_t lsm303ah_mg_status_get(stmdev_ctx_t *ctx,
lsm303ah_status_reg_m_t *val);
-int32_t lsm303ah_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm303ah_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm303ah_mg_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm303ah_mg_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm303ah_mg_user_offset_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm303ah_mg_user_offset_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm303ah_mg_user_offset_set(stmdev_ctx_t *ctx, int16_t *val);
+int32_t lsm303ah_mg_user_offset_get(stmdev_ctx_t *ctx, int16_t *val);
-typedef enum {
+typedef enum
+{
LSM303AH_MG_CONTINUOUS_MODE = 0,
LSM303AH_MG_SINGLE_TRIGGER = 1,
LSM303AH_MG_POWER_DOWN = 2,
@@ -611,7 +960,8 @@ int32_t lsm303ah_mg_operating_mode_set(stmdev_ctx_t *ctx,
int32_t lsm303ah_mg_operating_mode_get(stmdev_ctx_t *ctx,
lsm303ah_mg_md_t *val);
-typedef enum {
+typedef enum
+{
LSM303AH_MG_ODR_10Hz = 0,
LSM303AH_MG_ODR_20Hz = 1,
LSM303AH_MG_ODR_50Hz = 2,
@@ -622,7 +972,8 @@ int32_t lsm303ah_mg_data_rate_set(stmdev_ctx_t *ctx,
int32_t lsm303ah_mg_data_rate_get(stmdev_ctx_t *ctx,
lsm303ah_mg_odr_t *val);
-typedef enum {
+typedef enum
+{
LSM303AH_MG_HIGH_RESOLUTION = 0,
LSM303AH_MG_LOW_POWER = 1,
} lsm303ah_mg_lp_t;
@@ -631,10 +982,13 @@ int32_t lsm303ah_mg_power_mode_set(stmdev_ctx_t *ctx,
int32_t lsm303ah_mg_power_mode_get(stmdev_ctx_t *ctx,
lsm303ah_mg_lp_t *val);
-int32_t lsm303ah_mg_offset_temp_comp_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm303ah_mg_offset_temp_comp_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm303ah_mg_offset_temp_comp_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm303ah_mg_offset_temp_comp_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM303AH_MG_SET_SENS_ODR_DIV_63 = 0,
LSM303AH_MG_SENS_OFF_CANC_EVERY_ODR = 1,
LSM303AH_MG_SET_SENS_ONLY_AT_POWER_ON = 2,
@@ -652,22 +1006,28 @@ int32_t lsm303ah_mg_set_rst_sensor_single_get(stmdev_ctx_t *ctx,
int32_t lsm303ah_acceleration_module_raw_get(stmdev_ctx_t *ctx,
uint8_t *buff);
-int32_t lsm303ah_magnetic_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm303ah_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val);
-int32_t lsm303ah_xl_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm303ah_xl_temperature_raw_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
-int32_t lsm303ah_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm303ah_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
-int32_t lsm303ah_number_of_steps_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm303ah_number_of_steps_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
int32_t lsm303ah_xl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t lsm303ah_mg_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm303ah_xl_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm303ah_xl_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm303ah_xl_auto_increment_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm303ah_xl_auto_increment_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM303AH_XL_USER_BANK = 0,
LSM303AH_XL_ADV_BANK = 1,
} lsm303ah_xl_func_cfg_en_t;
@@ -686,18 +1046,22 @@ int32_t lsm303ah_xl_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm303ah_mg_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm303ah_mg_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM303AH_XL_ST_DISABLE = 0,
LSM303AH_XL_ST_POSITIVE = 1,
LSM303AH_XL_ST_NEGATIVE = 2,
} lsm303ah_xl_st_t;
-int32_t lsm303ah_xl_self_test_set(stmdev_ctx_t *ctx, lsm303ah_xl_st_t val);
-int32_t lsm303ah_xl_self_test_get(stmdev_ctx_t *ctx, lsm303ah_xl_st_t *val);
+int32_t lsm303ah_xl_self_test_set(stmdev_ctx_t *ctx,
+ lsm303ah_xl_st_t val);
+int32_t lsm303ah_xl_self_test_get(stmdev_ctx_t *ctx,
+ lsm303ah_xl_st_t *val);
int32_t lsm303ah_mg_self_test_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm303ah_mg_self_test_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM303AH_XL_DRDY_LATCHED = 0,
LSM303AH_XL_DRDY_PULSED = 1,
} lsm303ah_xl_drdy_pulsed_t;
@@ -706,7 +1070,8 @@ int32_t lsm303ah_xl_data_ready_mode_set(stmdev_ctx_t *ctx,
int32_t lsm303ah_xl_data_ready_mode_get(stmdev_ctx_t *ctx,
lsm303ah_xl_drdy_pulsed_t *val);
-typedef enum {
+typedef enum
+{
LSM303AH_XL_HP_INTERNAL_ONLY = 0,
LSM303AH_XL_HP_ON_OUTPUTS = 1,
} lsm303ah_xl_fds_slope_t;
@@ -715,7 +1080,8 @@ int32_t lsm303ah_xl_hp_path_set(stmdev_ctx_t *ctx,
int32_t lsm303ah_xl_hp_path_get(stmdev_ctx_t *ctx,
lsm303ah_xl_fds_slope_t *val);
-typedef enum {
+typedef enum
+{
LSM303AH_MG_ODR_DIV_2 = 0,
LSM303AH_MG_ODR_DIV_4 = 1,
} lsm303ah_mg_lpf_t;
@@ -724,14 +1090,18 @@ int32_t lsm303ah_mg_low_pass_bandwidth_set(stmdev_ctx_t *ctx,
int32_t lsm303ah_mg_low_pass_bandwidth_get(stmdev_ctx_t *ctx,
lsm303ah_mg_lpf_t *val);
-typedef enum {
+typedef enum
+{
LSM303AH_XL_SPI_4_WIRE = 0,
LSM303AH_XL_SPI_3_WIRE = 1,
} lsm303ah_xl_sim_t;
-int32_t lsm303ah_xl_spi_mode_set(stmdev_ctx_t *ctx, lsm303ah_xl_sim_t val);
-int32_t lsm303ah_xl_spi_mode_get(stmdev_ctx_t *ctx, lsm303ah_xl_sim_t *val);
+int32_t lsm303ah_xl_spi_mode_set(stmdev_ctx_t *ctx,
+ lsm303ah_xl_sim_t val);
+int32_t lsm303ah_xl_spi_mode_get(stmdev_ctx_t *ctx,
+ lsm303ah_xl_sim_t *val);
-typedef enum {
+typedef enum
+{
LSM303AH_XL_I2C_ENABLE = 0,
LSM303AH_XL_I2C_DISABLE = 1,
} lsm303ah_xl_i2c_disable_t;
@@ -740,7 +1110,8 @@ int32_t lsm303ah_xl_i2c_interface_set(stmdev_ctx_t *ctx,
int32_t lsm303ah_xl_i2c_interface_get(stmdev_ctx_t *ctx,
lsm303ah_xl_i2c_disable_t *val);
-typedef enum {
+typedef enum
+{
LSM303AH_MG_I2C_ENABLE = 0,
LSM303AH_MG_I2C_DISABLE = 1,
} lsm303ah_mg_i2c_dis_t;
@@ -749,7 +1120,8 @@ int32_t lsm303ah_mg_i2c_interface_set(stmdev_ctx_t *ctx,
int32_t lsm303ah_mg_i2c_interface_get(stmdev_ctx_t *ctx,
lsm303ah_mg_i2c_dis_t *val);
-typedef enum {
+typedef enum
+{
LSM303AH_XL_PULL_UP_CONNECTED = 0,
LSM303AH_XL_PULL_UP_DISCONNECTED = 1,
} lsm303ah_xl_if_cs_pu_dis_t;
@@ -758,7 +1130,8 @@ int32_t lsm303ah_xl_cs_mode_set(stmdev_ctx_t *ctx,
int32_t lsm303ah_xl_cs_mode_get(stmdev_ctx_t *ctx,
lsm303ah_xl_if_cs_pu_dis_t *val);
-typedef enum {
+typedef enum
+{
LSM303AH_XL_PUSH_PULL = 0,
LSM303AH_XL_OPEN_DRAIN = 1,
} lsm303ah_xl_pp_od_t;
@@ -767,7 +1140,8 @@ int32_t lsm303ah_xl_pin_mode_set(stmdev_ctx_t *ctx,
int32_t lsm303ah_xl_pin_mode_get(stmdev_ctx_t *ctx,
lsm303ah_xl_pp_od_t *val);
-typedef enum {
+typedef enum
+{
LSM303AH_XL_ACTIVE_HIGH = 0,
LSM303AH_XL_ACTIVE_LOW = 1,
} lsm303ah_xl_h_lactive_t;
@@ -776,7 +1150,8 @@ int32_t lsm303ah_xl_pin_polarity_set(stmdev_ctx_t *ctx,
int32_t lsm303ah_xl_pin_polarity_get(stmdev_ctx_t *ctx,
lsm303ah_xl_h_lactive_t *val);
-typedef enum {
+typedef enum
+{
LSM303AH_XL_INT_PULSED = 0,
LSM303AH_XL_INT_LATCHED = 1,
} lsm303ah_xl_lir_t;
@@ -785,7 +1160,8 @@ int32_t lsm303ah_xl_int_notification_set(stmdev_ctx_t *ctx,
int32_t lsm303ah_xl_int_notification_get(stmdev_ctx_t *ctx,
lsm303ah_xl_lir_t *val);
-typedef struct{
+typedef struct
+{
uint8_t int1_drdy : 1;
uint8_t int1_fth : 1;
uint8_t int1_6d : 1;
@@ -800,7 +1176,8 @@ int32_t lsm303ah_xl_pin_int1_route_set(stmdev_ctx_t *ctx,
int32_t lsm303ah_xl_pin_int1_route_get(stmdev_ctx_t *ctx,
lsm303ah_xl_pin_int1_route_t *val);
-typedef struct{
+typedef struct
+{
uint8_t int2_boot : 1;
uint8_t int2_tilt : 1;
uint8_t int2_sig_mot : 1;
@@ -830,10 +1207,13 @@ int32_t lsm303ah_mg_int_gen_conf_get(stmdev_ctx_t *ctx,
int32_t lsm303ah_mg_int_gen_source_get(stmdev_ctx_t *ctx,
lsm303ah_int_source_reg_m_t *val);
-int32_t lsm303ah_mg_int_gen_treshold_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm303ah_mg_int_gen_treshold_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm303ah_mg_int_gen_treshold_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t lsm303ah_mg_int_gen_treshold_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
-typedef enum {
+typedef enum
+{
LSM303AH_MG_CHECK_BEFORE = 0,
LSM303AH_MG_CHECK_AFTER = 1,
} lsm303ah_mg_int_on_dataoff_t;
@@ -842,8 +1222,10 @@ int32_t lsm303ah_mg_offset_int_conf_set(stmdev_ctx_t *ctx,
int32_t lsm303ah_mg_offset_int_conf_get(stmdev_ctx_t *ctx,
lsm303ah_mg_int_on_dataoff_t *val);
-int32_t lsm303ah_xl_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm303ah_xl_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm303ah_xl_wkup_threshold_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm303ah_xl_wkup_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm303ah_xl_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm303ah_xl_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -852,19 +1234,27 @@ int32_t lsm303ah_xl_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm303ah_xl_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm303ah_xl_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm303ah_xl_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm303ah_xl_act_sleep_dur_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm303ah_xl_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm303ah_xl_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm303ah_xl_tap_detection_on_z_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm303ah_xl_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm303ah_xl_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm303ah_xl_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm303ah_xl_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm303ah_xl_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm303ah_xl_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm303ah_xl_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm303ah_xl_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm303ah_xl_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm303ah_xl_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm303ah_xl_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm303ah_xl_tap_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm303ah_xl_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm303ah_xl_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -875,7 +1265,8 @@ int32_t lsm303ah_xl_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm303ah_xl_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm303ah_xl_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM303AH_XL_ONLY_SINGLE = 0,
LSM303AH_XL_ONLY_DOUBLE = 1,
} lsm303ah_xl_single_double_tap_t;
@@ -887,7 +1278,8 @@ int32_t lsm303ah_xl_tap_mode_get(stmdev_ctx_t *ctx,
int32_t lsm303ah_xl_tap_src_get(stmdev_ctx_t *ctx,
lsm303ah_tap_src_a_t *val);
-typedef enum {
+typedef enum
+{
LSM303AH_XL_DEG_80 = 0,
LSM303AH_XL_DEG_70 = 1,
LSM303AH_XL_DEG_60 = 2,
@@ -901,7 +1293,8 @@ int32_t lsm303ah_xl_6d_threshold_get(stmdev_ctx_t *ctx,
int32_t lsm303ah_xl_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm303ah_xl_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm303ah_xl_6d_src_get(stmdev_ctx_t *ctx, lsm303ah_6d_src_a_t *val);
+int32_t lsm303ah_xl_6d_src_get(stmdev_ctx_t *ctx,
+ lsm303ah_6d_src_a_t *val);
int32_t lsm303ah_xl_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm303ah_xl_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -914,7 +1307,8 @@ int32_t lsm303ah_xl_fifo_xl_module_batch_set(stmdev_ctx_t *ctx,
int32_t lsm303ah_xl_fifo_xl_module_batch_get(stmdev_ctx_t *ctx,
uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM303AH_XL_BYPASS_MODE = 0,
LSM303AH_XL_FIFO_MODE = 1,
LSM303AH_XL_STREAM_TO_FIFO_MODE = 3,
@@ -926,24 +1320,33 @@ int32_t lsm303ah_xl_fifo_mode_set(stmdev_ctx_t *ctx,
int32_t lsm303ah_xl_fifo_mode_get(stmdev_ctx_t *ctx,
lsm303ah_xl_fmode_t *val);
-int32_t lsm303ah_xl_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm303ah_xl_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm303ah_xl_fifo_watermark_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm303ah_xl_fifo_watermark_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm303ah_xl_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm303ah_xl_fifo_full_flag_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm303ah_xl_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm303ah_xl_fifo_ovr_flag_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm303ah_xl_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm303ah_xl_fifo_wtm_flag_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm303ah_xl_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t lsm303ah_xl_fifo_data_level_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
int32_t lsm303ah_xl_fifo_src_get(stmdev_ctx_t *ctx,
lsm303ah_fifo_src_a_t *val);
-int32_t lsm303ah_xl_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm303ah_xl_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm303ah_xl_pedo_threshold_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm303ah_xl_pedo_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM303AH_XL_PEDO_AT_2g = 0,
LSM303AH_XL_PEDO_AT_4g = 1,
} lsm303ah_xl_pedo4g_t;
@@ -952,8 +1355,10 @@ int32_t lsm303ah_xl_pedo_full_scale_set(stmdev_ctx_t *ctx,
int32_t lsm303ah_xl_pedo_full_scale_get(stmdev_ctx_t *ctx,
lsm303ah_xl_pedo4g_t *val);
-int32_t lsm303ah_xl_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm303ah_xl_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm303ah_xl_pedo_step_reset_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm303ah_xl_pedo_step_reset_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm303ah_xl_pedo_step_detect_flag_get(stmdev_ctx_t *ctx,
uint8_t *val);
@@ -961,22 +1366,28 @@ int32_t lsm303ah_xl_pedo_step_detect_flag_get(stmdev_ctx_t *ctx,
int32_t lsm303ah_xl_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm303ah_xl_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm303ah_xl_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm303ah_xl_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm303ah_xl_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm303ah_xl_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm303ah_xl_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm303ah_xl_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm303ah_xl_pedo_steps_period_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm303ah_xl_pedo_steps_period_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm303ah_xl_pedo_steps_period_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lsm303ah_xl_pedo_steps_period_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
int32_t lsm303ah_xl_motion_data_ready_flag_get(stmdev_ctx_t *ctx,
uint8_t *val);
int32_t lsm303ah_xl_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm303ah_xl_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm303ah_xl_motion_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm303ah_xl_motion_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm303ah_xl_motion_threshold_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm303ah_xl_motion_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm303ah_xl_tilt_data_ready_flag_get(stmdev_ctx_t *ctx,
uint8_t *val);
diff --git a/sensor/stmemsc/lsm6ds3_STdC/driver/lsm6ds3_reg.c b/sensor/stmemsc/lsm6ds3_STdC/driver/lsm6ds3_reg.c
index a86c03bc8a52381c3b45e56b3b9560bd46463842..e5c5923c0ebae3402794e4aed5b025e12d83e7a1 100644
--- a/sensor/stmemsc/lsm6ds3_STdC/driver/lsm6ds3_reg.c
+++ b/sensor/stmemsc/lsm6ds3_STdC/driver/lsm6ds3_reg.c
@@ -1,22 +1,23 @@
-/*
- ******************************************************************************
- * @file lsm6ds3_reg.c
- * @author Sensors Software Solution Team
- * @brief LSM6DS3 driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-#include "lsm6ds3_reg.h"
+/**
+ ******************************************************************************
+ * @file lsm6ds3_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LSM6DS3 driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+# include "lsm6ds3_reg.h"
/**
* @defgroup LSM6DS3
@@ -45,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lsm6ds3_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -63,11 +67,14 @@ int32_t lsm6ds3_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lsm6ds3_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -130,7 +137,7 @@ float_t lsm6ds3_from_fs2000dps_to_mdps(int16_t lsb)
float_t lsm6ds3_from_lsb_to_celsius(int16_t lsb)
{
- return ((float_t)lsb / 16.0f + 25.0f );
+ return ((float_t)lsb / 16.0f + 25.0f);
}
/**
@@ -154,18 +161,22 @@ float_t lsm6ds3_from_lsb_to_celsius(int16_t lsb)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_gy_data_orient_set(stmdev_ctx_t *ctx, lsm6ds3_gy_orient_t val)
+int32_t lsm6ds3_gy_data_orient_set(stmdev_ctx_t *ctx,
+ lsm6ds3_gy_orient_t val)
{
lsm6ds3_orient_cfg_g_t orient_cfg_g;
int32_t ret;
ret = lsm6ds3_read_reg(ctx, LSM6DS3_ORIENT_CFG_G,
- (uint8_t*)&orient_cfg_g, 1);
- if(ret == 0){
+ (uint8_t *)&orient_cfg_g, 1);
+
+ if (ret == 0)
+ {
orient_cfg_g.orient = (uint8_t)val;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_ORIENT_CFG_G,
- (uint8_t*)&orient_cfg_g, 1);
+ (uint8_t *)&orient_cfg_g, 1);
}
+
return ret;
}
@@ -174,6 +185,7 @@ int32_t lsm6ds3_gy_data_orient_set(stmdev_ctx_t *ctx, lsm6ds3_gy_orient_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of orient in reg ORIENT_CFG_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_gy_data_orient_get(stmdev_ctx_t *ctx,
@@ -183,32 +195,39 @@ int32_t lsm6ds3_gy_data_orient_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6ds3_read_reg(ctx, LSM6DS3_ORIENT_CFG_G,
- (uint8_t*)&orient_cfg_g, 1);
+ (uint8_t *)&orient_cfg_g, 1);
switch (orient_cfg_g.orient)
{
case LSM6DS3_GY_ORIENT_XYZ:
*val = LSM6DS3_GY_ORIENT_XYZ;
break;
+
case LSM6DS3_GY_ORIENT_XZY:
*val = LSM6DS3_GY_ORIENT_XZY;
break;
+
case LSM6DS3_GY_ORIENT_YXZ:
*val = LSM6DS3_GY_ORIENT_YXZ;
break;
+
case LSM6DS3_GY_ORIENT_YZX:
*val = LSM6DS3_GY_ORIENT_YZX;
break;
+
case LSM6DS3_GY_ORIENT_ZXY:
*val = LSM6DS3_GY_ORIENT_ZXY;
break;
+
case LSM6DS3_GY_ORIENT_ZYX:
*val = LSM6DS3_GY_ORIENT_ZYX;
break;
+
default:
*val = LSM6DS3_GY_ORIENT_XYZ;
break;
}
+
return ret;
}
@@ -220,18 +239,22 @@ int32_t lsm6ds3_gy_data_orient_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_gy_data_sign_set(stmdev_ctx_t *ctx, lsm6ds3_gy_sgn_t val)
+int32_t lsm6ds3_gy_data_sign_set(stmdev_ctx_t *ctx,
+ lsm6ds3_gy_sgn_t val)
{
lsm6ds3_orient_cfg_g_t orient_cfg_g;
int32_t ret;
ret = lsm6ds3_read_reg(ctx, LSM6DS3_ORIENT_CFG_G,
- (uint8_t*)&orient_cfg_g, 1);
- if(ret == 0){
+ (uint8_t *)&orient_cfg_g, 1);
+
+ if (ret == 0)
+ {
orient_cfg_g.sign_g = (uint8_t)val;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_ORIENT_CFG_G,
- (uint8_t*)&orient_cfg_g, 1);
+ (uint8_t *)&orient_cfg_g, 1);
}
+
return ret;
}
@@ -240,46 +263,57 @@ int32_t lsm6ds3_gy_data_sign_set(stmdev_ctx_t *ctx, lsm6ds3_gy_sgn_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of sign_g in reg ORIENT_CFG_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_gy_data_sign_get(stmdev_ctx_t *ctx, lsm6ds3_gy_sgn_t *val)
+int32_t lsm6ds3_gy_data_sign_get(stmdev_ctx_t *ctx,
+ lsm6ds3_gy_sgn_t *val)
{
lsm6ds3_orient_cfg_g_t orient_cfg_g;
int32_t ret;
ret = lsm6ds3_read_reg(ctx, LSM6DS3_ORIENT_CFG_G,
- (uint8_t*)&orient_cfg_g, 1);
+ (uint8_t *)&orient_cfg_g, 1);
switch (orient_cfg_g.sign_g)
{
case LSM6DS3_GY_SIGN_PPP:
- *val =LSM6DS3_GY_SIGN_PPP;
+ *val = LSM6DS3_GY_SIGN_PPP;
break;
+
case LSM6DS3_GY_SIGN_PPN:
*val = LSM6DS3_GY_SIGN_PPN;
break;
+
case LSM6DS3_GY_SIGN_PNP:
*val = LSM6DS3_GY_SIGN_PNP;
break;
+
case LSM6DS3_GY_SIGN_NPP:
*val = LSM6DS3_GY_SIGN_NPP;
break;
+
case LSM6DS3_GY_SIGN_NNP:
*val = LSM6DS3_GY_SIGN_NNP;
break;
+
case LSM6DS3_GY_SIGN_NPN:
*val = LSM6DS3_GY_SIGN_NPN;
break;
+
case LSM6DS3_GY_SIGN_PNN:
*val = LSM6DS3_GY_SIGN_PNN;
break;
+
case LSM6DS3_GY_SIGN_NNN:
*val = LSM6DS3_GY_SIGN_NNN;
break;
+
default:
*val = LSM6DS3_GY_SIGN_PPP;
break;
}
+
return ret;
}
@@ -291,16 +325,20 @@ int32_t lsm6ds3_gy_data_sign_get(stmdev_ctx_t *ctx, lsm6ds3_gy_sgn_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_xl_full_scale_set(stmdev_ctx_t *ctx, lsm6ds3_xl_fs_t val)
+int32_t lsm6ds3_xl_full_scale_set(stmdev_ctx_t *ctx,
+ lsm6ds3_xl_fs_t val)
{
lsm6ds3_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
ctrl1_xl.fs_xl = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -309,33 +347,40 @@ int32_t lsm6ds3_xl_full_scale_set(stmdev_ctx_t *ctx, lsm6ds3_xl_fs_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of fs_xl in reg CTRL1_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_xl_full_scale_get(stmdev_ctx_t *ctx, lsm6ds3_xl_fs_t *val)
+int32_t lsm6ds3_xl_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6ds3_xl_fs_t *val)
{
lsm6ds3_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
switch (ctrl1_xl.fs_xl)
{
case LSM6DS3_2g:
*val = LSM6DS3_2g;
break;
+
case LSM6DS3_16g:
*val = LSM6DS3_16g;
break;
+
case LSM6DS3_4g:
*val = LSM6DS3_4g;
break;
+
case LSM6DS3_8g:
*val = LSM6DS3_8g;
break;
+
default:
*val = LSM6DS3_2g;
break;
}
+
return ret;
}
@@ -347,16 +392,20 @@ int32_t lsm6ds3_xl_full_scale_get(stmdev_ctx_t *ctx, lsm6ds3_xl_fs_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6ds3_odr_xl_t val)
+int32_t lsm6ds3_xl_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6ds3_odr_xl_t val)
{
lsm6ds3_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
ctrl1_xl.odr_xl = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -365,54 +414,68 @@ int32_t lsm6ds3_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6ds3_odr_xl_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of odr_xl in reg CTRL1_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_xl_data_rate_get(stmdev_ctx_t *ctx, lsm6ds3_odr_xl_t *val)
+int32_t lsm6ds3_xl_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6ds3_odr_xl_t *val)
{
lsm6ds3_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
switch (ctrl1_xl.odr_xl)
{
case LSM6DS3_XL_ODR_OFF:
*val = LSM6DS3_XL_ODR_OFF;
break;
+
case LSM6DS3_XL_ODR_12Hz5:
*val = LSM6DS3_XL_ODR_12Hz5;
break;
+
case LSM6DS3_XL_ODR_26Hz:
*val = LSM6DS3_XL_ODR_26Hz;
break;
+
case LSM6DS3_XL_ODR_52Hz:
*val = LSM6DS3_XL_ODR_52Hz;
break;
+
case LSM6DS3_XL_ODR_104Hz:
*val = LSM6DS3_XL_ODR_104Hz;
break;
+
case LSM6DS3_XL_ODR_208Hz:
*val = LSM6DS3_XL_ODR_208Hz;
break;
+
case LSM6DS3_XL_ODR_416Hz:
*val = LSM6DS3_XL_ODR_416Hz;
break;
+
case LSM6DS3_XL_ODR_833Hz:
*val = LSM6DS3_XL_ODR_833Hz;
break;
+
case LSM6DS3_XL_ODR_1k66Hz:
*val = LSM6DS3_XL_ODR_1k66Hz;
break;
+
case LSM6DS3_XL_ODR_3k33Hz:
*val = LSM6DS3_XL_ODR_3k33Hz;
break;
+
case LSM6DS3_XL_ODR_6k66Hz:
*val = LSM6DS3_XL_ODR_6k66Hz;
break;
+
default:
*val = LSM6DS3_XL_ODR_OFF;
break;
}
+
return ret;
}
@@ -424,16 +487,20 @@ int32_t lsm6ds3_xl_data_rate_get(stmdev_ctx_t *ctx, lsm6ds3_odr_xl_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_gy_full_scale_set(stmdev_ctx_t *ctx, lsm6ds3_fs_g_t val)
+int32_t lsm6ds3_gy_full_scale_set(stmdev_ctx_t *ctx,
+ lsm6ds3_fs_g_t val)
{
lsm6ds3_ctrl2_g_t ctrl2_g;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
+
+ if (ret == 0)
+ {
ctrl2_g.fs_g = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
}
+
return ret;
}
@@ -442,36 +509,44 @@ int32_t lsm6ds3_gy_full_scale_set(stmdev_ctx_t *ctx, lsm6ds3_fs_g_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of fs_g in reg CTRL2_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_gy_full_scale_get(stmdev_ctx_t *ctx, lsm6ds3_fs_g_t *val)
+int32_t lsm6ds3_gy_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6ds3_fs_g_t *val)
{
lsm6ds3_ctrl2_g_t ctrl2_g;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
switch (ctrl2_g.fs_g)
{
case LSM6DS3_250dps:
*val = LSM6DS3_250dps;
break;
+
case LSM6DS3_125dps:
*val = LSM6DS3_125dps;
break;
+
case LSM6DS3_500dps:
*val = LSM6DS3_500dps;
break;
+
case LSM6DS3_1000dps:
*val = LSM6DS3_1000dps;
break;
+
case LSM6DS3_2000dps:
*val = LSM6DS3_2000dps;
break;
+
default:
*val = LSM6DS3_250dps;
break;
}
+
return ret;
}
@@ -483,16 +558,20 @@ int32_t lsm6ds3_gy_full_scale_get(stmdev_ctx_t *ctx, lsm6ds3_fs_g_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_gy_data_rate_set(stmdev_ctx_t *ctx, lsm6ds3_odr_g_t val)
+int32_t lsm6ds3_gy_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6ds3_odr_g_t val)
{
lsm6ds3_ctrl2_g_t ctrl2_g;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
+
+ if (ret == 0)
+ {
ctrl2_g.odr_g = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
}
+
return ret;
}
@@ -501,48 +580,60 @@ int32_t lsm6ds3_gy_data_rate_set(stmdev_ctx_t *ctx, lsm6ds3_odr_g_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of odr_g in reg CTRL2_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_gy_data_rate_get(stmdev_ctx_t *ctx, lsm6ds3_odr_g_t *val)
+int32_t lsm6ds3_gy_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6ds3_odr_g_t *val)
{
lsm6ds3_ctrl2_g_t ctrl2_g;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
switch (ctrl2_g.odr_g)
{
case LSM6DS3_GY_ODR_OFF:
*val = LSM6DS3_GY_ODR_OFF;
break;
+
case LSM6DS3_GY_ODR_12Hz5:
*val = LSM6DS3_GY_ODR_12Hz5;
break;
+
case LSM6DS3_GY_ODR_26Hz:
*val = LSM6DS3_GY_ODR_26Hz;
break;
+
case LSM6DS3_GY_ODR_52Hz:
*val = LSM6DS3_GY_ODR_52Hz;
break;
+
case LSM6DS3_GY_ODR_104Hz:
*val = LSM6DS3_GY_ODR_104Hz;
break;
+
case LSM6DS3_GY_ODR_208Hz:
*val = LSM6DS3_GY_ODR_208Hz;
break;
+
case LSM6DS3_GY_ODR_416Hz:
*val = LSM6DS3_GY_ODR_416Hz;
break;
+
case LSM6DS3_GY_ODR_833Hz:
*val = LSM6DS3_GY_ODR_833Hz;
break;
+
case LSM6DS3_GY_ODR_1k66Hz:
*val = LSM6DS3_GY_ODR_1k66Hz;
break;
+
default:
*val = LSM6DS3_GY_ODR_OFF;
break;
}
+
return ret;
}
@@ -559,11 +650,14 @@ int32_t lsm6ds3_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.bdu = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -580,7 +674,7 @@ int32_t lsm6ds3_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = (uint8_t)ctrl3_c.bdu;
return ret;
@@ -594,16 +688,20 @@ int32_t lsm6ds3_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_xl_power_mode_set(stmdev_ctx_t *ctx, lsm6ds3_xl_hm_mode_t val)
+int32_t lsm6ds3_xl_power_mode_set(stmdev_ctx_t *ctx,
+ lsm6ds3_xl_hm_mode_t val)
{
lsm6ds3_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
ctrl6_c.xl_hm_mode = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -612,6 +710,7 @@ int32_t lsm6ds3_xl_power_mode_set(stmdev_ctx_t *ctx, lsm6ds3_xl_hm_mode_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of xl_hm_mode in reg CTRL6_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_xl_power_mode_get(stmdev_ctx_t *ctx,
@@ -620,20 +719,23 @@ int32_t lsm6ds3_xl_power_mode_get(stmdev_ctx_t *ctx,
lsm6ds3_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
switch (ctrl6_c.xl_hm_mode)
{
case LSM6DS3_XL_HIGH_PERFORMANCE:
*val = LSM6DS3_XL_HIGH_PERFORMANCE;
break;
+
case LSM6DS3_XL_NORMAL:
*val = LSM6DS3_XL_NORMAL;
break;
+
default:
*val = LSM6DS3_XL_HIGH_PERFORMANCE;
break;
}
+
return ret;
}
@@ -645,16 +747,20 @@ int32_t lsm6ds3_xl_power_mode_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_rounding_on_status_set(stmdev_ctx_t *ctx, lsm6ds3_rnd_stat_t val)
+int32_t lsm6ds3_rounding_on_status_set(stmdev_ctx_t *ctx,
+ lsm6ds3_rnd_stat_t val)
{
lsm6ds3_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
ctrl7_g.rounding_status = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
}
+
return ret;
}
@@ -663,6 +769,7 @@ int32_t lsm6ds3_rounding_on_status_set(stmdev_ctx_t *ctx, lsm6ds3_rnd_stat_t val
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of rounding_status in reg CTRL7_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_rounding_on_status_get(stmdev_ctx_t *ctx,
@@ -671,20 +778,23 @@ int32_t lsm6ds3_rounding_on_status_get(stmdev_ctx_t *ctx,
lsm6ds3_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
switch (ctrl7_g.rounding_status)
{
case LSM6DS3_STAT_RND_DISABLE:
*val = LSM6DS3_STAT_RND_DISABLE;
break;
+
case LSM6DS3_STAT_RND_ENABLE:
*val = LSM6DS3_STAT_RND_ENABLE;
break;
+
default:
*val = LSM6DS3_STAT_RND_DISABLE;
break;
}
+
return ret;
}
@@ -696,16 +806,20 @@ int32_t lsm6ds3_rounding_on_status_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_gy_power_mode_set(stmdev_ctx_t *ctx, lsm6ds3_g_hm_mode_t val)
+int32_t lsm6ds3_gy_power_mode_set(stmdev_ctx_t *ctx,
+ lsm6ds3_g_hm_mode_t val)
{
lsm6ds3_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
ctrl7_g.g_hm_mode = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
}
+
return ret;
}
@@ -714,27 +828,32 @@ int32_t lsm6ds3_gy_power_mode_set(stmdev_ctx_t *ctx, lsm6ds3_g_hm_mode_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of g_hm_mode in reg CTRL7_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_gy_power_mode_get(stmdev_ctx_t *ctx, lsm6ds3_g_hm_mode_t *val)
+int32_t lsm6ds3_gy_power_mode_get(stmdev_ctx_t *ctx,
+ lsm6ds3_g_hm_mode_t *val)
{
lsm6ds3_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
switch (ctrl7_g.g_hm_mode)
{
case LSM6DS3_GY_HIGH_PERFORMANCE:
*val = LSM6DS3_GY_HIGH_PERFORMANCE;
break;
+
case LSM6DS3_GY_NORMAL:
*val = LSM6DS3_GY_NORMAL;
break;
+
default:
*val = LSM6DS3_GY_HIGH_PERFORMANCE;
break;
}
+
return ret;
}
@@ -751,11 +870,14 @@ int32_t lsm6ds3_xl_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
ctrl9_xl.xen_xl = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -772,7 +894,7 @@ int32_t lsm6ds3_xl_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
*val = (uint8_t)ctrl9_xl.xen_xl;
return ret;
@@ -791,11 +913,14 @@ int32_t lsm6ds3_xl_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
ctrl9_xl.yen_xl = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -812,7 +937,7 @@ int32_t lsm6ds3_xl_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
*val = (uint8_t)ctrl9_xl.yen_xl;
return ret;
@@ -831,11 +956,14 @@ int32_t lsm6ds3_xl_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
ctrl9_xl.zen_xl = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -852,7 +980,7 @@ int32_t lsm6ds3_xl_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
*val = (uint8_t)ctrl9_xl.zen_xl;
return ret;
@@ -871,11 +999,14 @@ int32_t lsm6ds3_gy_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
ctrl10_c.xen_g = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
}
+
return ret;
}
@@ -892,7 +1023,7 @@ int32_t lsm6ds3_gy_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
*val = (uint8_t)ctrl10_c.xen_g;
return ret;
@@ -911,11 +1042,14 @@ int32_t lsm6ds3_gy_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
ctrl10_c.yen_g = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
}
+
return ret;
}
@@ -932,7 +1066,7 @@ int32_t lsm6ds3_gy_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
*val = (uint8_t)ctrl10_c.yen_g;
return ret;
@@ -951,11 +1085,14 @@ int32_t lsm6ds3_gy_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
ctrl10_c.zen_g = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
}
+
return ret;
}
@@ -972,7 +1109,7 @@ int32_t lsm6ds3_gy_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
*val = (uint8_t)ctrl10_c.zen_g;
return ret;
@@ -984,26 +1121,35 @@ int32_t lsm6ds3_gy_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val)
* @param ctx read / write interface definitions(ptr)
* @param val Read all the interrupt flag of the device:
* WAKE_UP_SRC, TAP_SRC, D6D_SRC, FUNC_SRC.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_all_sources_get(stmdev_ctx_t *ctx, lsm6ds3_all_src_t *val)
+int32_t lsm6ds3_all_sources_get(stmdev_ctx_t *ctx,
+ lsm6ds3_all_src_t *val)
{
int32_t ret;
ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_SRC,
- (uint8_t*)&(val->wake_up_src), 1);
- if(ret == 0) {
+ (uint8_t *) & (val->wake_up_src), 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_SRC,
- (uint8_t*)&(val->tap_src), 1);
+ (uint8_t *) & (val->tap_src), 1);
}
- if(ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6ds3_read_reg(ctx, LSM6DS3_D6D_SRC,
- (uint8_t*)&(val->d6d_src), 1);
+ (uint8_t *) & (val->d6d_src), 1);
}
- if(ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6ds3_read_reg(ctx, LSM6DS3_FUNC_SRC,
- (uint8_t*)&(val->func_src), 1);
+ (uint8_t *) & (val->func_src), 1);
}
+
return ret;
}
@@ -1012,13 +1158,15 @@ int32_t lsm6ds3_all_sources_get(stmdev_ctx_t *ctx, lsm6ds3_all_src_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val The STATUS_REG register of the device.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_status_reg_get(stmdev_ctx_t *ctx, lsm6ds3_status_reg_t *val)
+int32_t lsm6ds3_status_reg_get(stmdev_ctx_t *ctx,
+ lsm6ds3_status_reg_t *val)
{
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_STATUS_REG, (uint8_t*)&val, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_STATUS_REG, (uint8_t *)&val, 1);
return ret;
}
@@ -1031,12 +1179,14 @@ int32_t lsm6ds3_status_reg_get(stmdev_ctx_t *ctx, lsm6ds3_status_reg_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3_status_reg_t status_reg;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_STATUS_REG, (uint8_t*)&status_reg, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_STATUS_REG,
+ (uint8_t *)&status_reg, 1);
*val = (uint8_t)status_reg.xlda;
return ret;
@@ -1050,12 +1200,14 @@ int32_t lsm6ds3_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3_status_reg_t status_reg;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_STATUS_REG, (uint8_t*)&status_reg, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_STATUS_REG,
+ (uint8_t *)&status_reg, 1);
*val = (uint8_t)status_reg.gda;
return ret;
@@ -1069,12 +1221,14 @@ int32_t lsm6ds3_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3_status_reg_t status_reg;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_STATUS_REG, (uint8_t*)&status_reg, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_STATUS_REG,
+ (uint8_t *)&status_reg, 1);
*val = (uint8_t)status_reg.tda;
return ret;
@@ -1100,13 +1254,19 @@ int32_t lsm6ds3_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_timestamp_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6ds3_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val)
{
+ uint8_t buff[3];
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_TIMESTAMP0_REG, buff,
- 3);
+
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_TIMESTAMP0_REG, buff, 3);
+ *val = buff[2];
+ *val = (*val * 256U) + buff[1];
+ *val = (*val * 256U) + buff[0];
+
return ret;
}
@@ -1115,14 +1275,16 @@ int32_t lsm6ds3_timestamp_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions(ptr)
* @param buff buffer that stores data to be write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_timestamp_rst_set(stmdev_ctx_t *ctx)
{
int32_t ret;
- uint8_t rst_val = 0xAA;
+ uint8_t rst_val = 0xAA;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_TIMESTAMP2_REG, &rst_val, 1);
+
return ret;
}
@@ -1141,11 +1303,14 @@ int32_t lsm6ds3_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
tap_cfg.timer_en = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -1164,7 +1329,7 @@ int32_t lsm6ds3_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1);
*val = (uint8_t)tap_cfg.timer_en;
return ret;
@@ -1178,17 +1343,22 @@ int32_t lsm6ds3_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_timestamp_res_set(stmdev_ctx_t *ctx, lsm6ds3_ts_res_t val)
+int32_t lsm6ds3_timestamp_res_set(stmdev_ctx_t *ctx,
+ lsm6ds3_ts_res_t val)
{
lsm6ds3_wake_up_dur_t wake_up_dur;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
wake_up_dur.timer_hr = (uint8_t)val;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -1197,27 +1367,33 @@ int32_t lsm6ds3_timestamp_res_set(stmdev_ctx_t *ctx, lsm6ds3_ts_res_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of timer_hr in reg WAKE_UP_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_timestamp_res_get(stmdev_ctx_t *ctx, lsm6ds3_ts_res_t *val)
+int32_t lsm6ds3_timestamp_res_get(stmdev_ctx_t *ctx,
+ lsm6ds3_ts_res_t *val)
{
lsm6ds3_wake_up_dur_t wake_up_dur;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
switch (wake_up_dur.timer_hr)
{
case LSM6DS3_LSB_6ms4:
*val = LSM6DS3_LSB_6ms4;
break;
+
case LSM6DS3_LSB_25us:
*val = LSM6DS3_LSB_25us;
break;
+
default:
*val = LSM6DS3_LSB_6ms4;
break;
}
+
return ret;
}
@@ -1242,16 +1418,20 @@ int32_t lsm6ds3_timestamp_res_get(stmdev_ctx_t *ctx, lsm6ds3_ts_res_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_rounding_mode_set(stmdev_ctx_t *ctx, lsm6ds3_rounding_t val)
+int32_t lsm6ds3_rounding_mode_set(stmdev_ctx_t *ctx,
+ lsm6ds3_rounding_t val)
{
lsm6ds3_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ if (ret == 0)
+ {
ctrl5_c.rounding = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -1261,45 +1441,56 @@ int32_t lsm6ds3_rounding_mode_set(stmdev_ctx_t *ctx, lsm6ds3_rounding_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of rounding in reg CTRL5_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_rounding_mode_get(stmdev_ctx_t *ctx, lsm6ds3_rounding_t *val)
+int32_t lsm6ds3_rounding_mode_get(stmdev_ctx_t *ctx,
+ lsm6ds3_rounding_t *val)
{
lsm6ds3_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
switch (ctrl5_c.rounding)
{
case LSM6DS3_ROUND_DISABLE:
*val = LSM6DS3_ROUND_DISABLE;
break;
+
case LSM6DS3_ROUND_XL:
*val = LSM6DS3_ROUND_XL;
break;
+
case LSM6DS3_ROUND_GY:
*val = LSM6DS3_ROUND_GY;
break;
+
case LSM6DS3_ROUND_GY_XL:
*val = LSM6DS3_ROUND_GY_XL;
break;
+
case LSM6DS3_ROUND_SH1_TO_SH6:
*val = LSM6DS3_ROUND_SH1_TO_SH6;
break;
+
case LSM6DS3_ROUND_XL_SH1_TO_SH6:
*val = LSM6DS3_ROUND_XL_SH1_TO_SH6;
break;
+
case LSM6DS3_ROUND_GY_XL_SH1_TO_SH12:
*val = LSM6DS3_ROUND_GY_XL_SH1_TO_SH12;
break;
+
case LSM6DS3_ROUND_GY_XL_SH1_TO_SH6:
*val = LSM6DS3_ROUND_GY_XL_SH1_TO_SH6;
break;
+
default:
*val = LSM6DS3_ROUND_DISABLE;
break;
}
+
return ret;
}
@@ -1309,12 +1500,18 @@ int32_t lsm6ds3_rounding_mode_get(stmdev_ctx_t *ctx, lsm6ds3_rounding_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6ds3_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
+
ret = lsm6ds3_read_reg(ctx, LSM6DS3_OUT_TEMP_L, buff, 2);
+ *val = (int16_t)buff[1];
+ *val = (*val * 256) + (int16_t)buff[0];
+
return ret;
}
@@ -1324,12 +1521,22 @@ int32_t lsm6ds3_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions(ptr)
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6ds3_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lsm6ds3_read_reg(ctx, LSM6DS3_OUTX_L_G, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -1339,12 +1546,22 @@ int32_t lsm6ds3_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions(ptr)
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6ds3_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lsm6ds3_read_reg(ctx, LSM6DS3_OUTX_L_XL, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -1354,12 +1571,16 @@ int32_t lsm6ds3_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @param stmdev_ctx_t *ctx: read / write interface definitions
* @param uint8_t *: data buffer to store FIFO data.
* @param uint8_t : number of data to read from FIFO.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer, uint8_t len)
+int32_t lsm6ds3_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer,
+ uint8_t len)
{
int32_t ret;
+
ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_DATA_OUT_L, buffer, len);
+
return ret;
}
@@ -1368,12 +1589,18 @@ int32_t lsm6ds3_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer, uint8_t le
*
* @param ctx read / write interface definitions(ptr)
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_number_of_steps_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6ds3_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
+
ret = lsm6ds3_read_reg(ctx, LSM6DS3_STEP_COUNTER_L, buff, 2);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
+
return ret;
}
@@ -1382,12 +1609,23 @@ int32_t lsm6ds3_number_of_steps_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions(ptr)
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_mag_calibrated_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6ds3_mag_calibrated_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lsm6ds3_read_reg(ctx, LSM6DS3_OUT_MAG_RAW_X_L, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -1398,7 +1636,7 @@ int32_t lsm6ds3_mag_calibrated_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
/**
* @defgroup LSM6DS3_Common
- * @brief This section groups common usefull functions.
+ * @brief This section groups common useful functions.
* @{
*
*/
@@ -1411,18 +1649,22 @@ int32_t lsm6ds3_mag_calibrated_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_mem_bank_set(stmdev_ctx_t *ctx, lsm6ds3_func_cfg_en_t val)
+int32_t lsm6ds3_mem_bank_set(stmdev_ctx_t *ctx,
+ lsm6ds3_func_cfg_en_t val)
{
lsm6ds3_func_cfg_access_t func_cfg_access;
int32_t ret;
ret = lsm6ds3_read_reg(ctx, LSM6DS3_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
- if(ret == 0){
+ (uint8_t *)&func_cfg_access, 1);
+
+ if (ret == 0)
+ {
func_cfg_access.func_cfg_en = (uint8_t)val;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
+ (uint8_t *)&func_cfg_access, 1);
}
+
return ret;
}
@@ -1431,28 +1673,33 @@ int32_t lsm6ds3_mem_bank_set(stmdev_ctx_t *ctx, lsm6ds3_func_cfg_en_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of func_cfg_en in reg FUNC_CFG_ACCESS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_mem_bank_get(stmdev_ctx_t *ctx, lsm6ds3_func_cfg_en_t *val)
+int32_t lsm6ds3_mem_bank_get(stmdev_ctx_t *ctx,
+ lsm6ds3_func_cfg_en_t *val)
{
lsm6ds3_func_cfg_access_t func_cfg_access;
int32_t ret;
ret = lsm6ds3_read_reg(ctx, LSM6DS3_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
+ (uint8_t *)&func_cfg_access, 1);
switch (func_cfg_access.func_cfg_en)
{
case LSM6DS3_USER_BANK:
*val = LSM6DS3_USER_BANK;
break;
+
case LSM6DS3_EMBEDDED_FUNC_BANK:
*val = LSM6DS3_EMBEDDED_FUNC_BANK;
break;
+
default:
*val = LSM6DS3_USER_BANK;
break;
}
+
return ret;
}
@@ -1461,12 +1708,15 @@ int32_t lsm6ds3_mem_bank_get(stmdev_ctx_t *ctx, lsm6ds3_func_cfg_en_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6ds3_read_reg(ctx, LSM6DS3_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -1483,11 +1733,14 @@ int32_t lsm6ds3_reset_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.sw_reset = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1504,7 +1757,7 @@ int32_t lsm6ds3_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = (uint8_t)ctrl3_c.sw_reset;
return ret;
@@ -1523,11 +1776,14 @@ int32_t lsm6ds3_data_format_set(stmdev_ctx_t *ctx, lsm6ds3_ble_t val)
lsm6ds3_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.ble = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1536,6 +1792,7 @@ int32_t lsm6ds3_data_format_set(stmdev_ctx_t *ctx, lsm6ds3_ble_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of ble in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_data_format_get(stmdev_ctx_t *ctx, lsm6ds3_ble_t *val)
@@ -1543,20 +1800,23 @@ int32_t lsm6ds3_data_format_get(stmdev_ctx_t *ctx, lsm6ds3_ble_t *val)
lsm6ds3_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
switch (ctrl3_c.ble)
{
case LSM6DS3_LSB_AT_LOW_ADD:
*val = LSM6DS3_LSB_AT_LOW_ADD;
break;
+
case LSM6DS3_MSB_AT_LOW_ADD:
*val = LSM6DS3_MSB_AT_LOW_ADD;
break;
+
default:
*val = LSM6DS3_LSB_AT_LOW_ADD;
break;
}
+
return ret;
}
@@ -1574,11 +1834,14 @@ int32_t lsm6ds3_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.if_inc = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1596,7 +1859,7 @@ int32_t lsm6ds3_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = (uint8_t)ctrl3_c.if_inc;
return ret;
@@ -1615,11 +1878,14 @@ int32_t lsm6ds3_boot_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.boot = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1636,7 +1902,7 @@ int32_t lsm6ds3_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = (uint8_t)ctrl3_c.boot;
return ret;
@@ -1650,16 +1916,20 @@ int32_t lsm6ds3_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_xl_self_test_set(stmdev_ctx_t *ctx, lsm6ds3_st_xl_t val)
+int32_t lsm6ds3_xl_self_test_set(stmdev_ctx_t *ctx,
+ lsm6ds3_st_xl_t val)
{
lsm6ds3_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ if (ret == 0)
+ {
ctrl5_c.st_xl = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -1668,30 +1938,36 @@ int32_t lsm6ds3_xl_self_test_set(stmdev_ctx_t *ctx, lsm6ds3_st_xl_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of st_xl in reg CTRL5_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_xl_self_test_get(stmdev_ctx_t *ctx, lsm6ds3_st_xl_t *val)
+int32_t lsm6ds3_xl_self_test_get(stmdev_ctx_t *ctx,
+ lsm6ds3_st_xl_t *val)
{
lsm6ds3_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
switch (ctrl5_c.st_xl)
{
case LSM6DS3_XL_ST_DISABLE:
*val = LSM6DS3_XL_ST_DISABLE;
break;
+
case LSM6DS3_XL_ST_POSITIVE:
*val = LSM6DS3_XL_ST_POSITIVE;
break;
+
case LSM6DS3_XL_ST_NEGATIVE:
*val = LSM6DS3_XL_ST_NEGATIVE;
break;
+
default:
*val = LSM6DS3_XL_ST_DISABLE;
break;
}
+
return ret;
}
@@ -1703,16 +1979,20 @@ int32_t lsm6ds3_xl_self_test_get(stmdev_ctx_t *ctx, lsm6ds3_st_xl_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_gy_self_test_set(stmdev_ctx_t *ctx, lsm6ds3_st_g_t val)
+int32_t lsm6ds3_gy_self_test_set(stmdev_ctx_t *ctx,
+ lsm6ds3_st_g_t val)
{
lsm6ds3_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ if (ret == 0)
+ {
ctrl5_c.st_g = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -1721,30 +2001,36 @@ int32_t lsm6ds3_gy_self_test_set(stmdev_ctx_t *ctx, lsm6ds3_st_g_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of st_g in reg CTRL5_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_gy_self_test_get(stmdev_ctx_t *ctx, lsm6ds3_st_g_t *val)
+int32_t lsm6ds3_gy_self_test_get(stmdev_ctx_t *ctx,
+ lsm6ds3_st_g_t *val)
{
lsm6ds3_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
switch (ctrl5_c.st_g)
{
case LSM6DS3_GY_ST_DISABLE:
*val = LSM6DS3_GY_ST_DISABLE;
break;
+
case LSM6DS3_GY_ST_POSITIVE:
*val = LSM6DS3_GY_ST_POSITIVE;
break;
+
case LSM6DS3_GY_ST_NEGATIVE:
*val = LSM6DS3_GY_ST_NEGATIVE;
break;
+
default:
*val = LSM6DS3_GY_ST_DISABLE;
break;
}
+
return ret;
}
@@ -1776,11 +2062,14 @@ int32_t lsm6ds3_filter_settling_mask_set(stmdev_ctx_t *ctx,
lsm6ds3_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
ctrl4_c.drdy_mask = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -1793,12 +2082,13 @@ int32_t lsm6ds3_filter_settling_mask_set(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3_filter_settling_mask_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
*val = (uint8_t)ctrl4_c.drdy_mask;
return ret;
@@ -1812,16 +2102,20 @@ int32_t lsm6ds3_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_gy_hp_bandwidth_set(stmdev_ctx_t *ctx, lsm6ds3_hpcf_g_t val)
+int32_t lsm6ds3_gy_hp_bandwidth_set(stmdev_ctx_t *ctx,
+ lsm6ds3_hpcf_g_t val)
{
lsm6ds3_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
ctrl7_g.hpcf_g = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
}
+
return ret;
}
@@ -1830,33 +2124,40 @@ int32_t lsm6ds3_gy_hp_bandwidth_set(stmdev_ctx_t *ctx, lsm6ds3_hpcf_g_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of hpcf_g in reg CTRL7_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_gy_hp_bandwidth_get(stmdev_ctx_t *ctx, lsm6ds3_hpcf_g_t *val)
+int32_t lsm6ds3_gy_hp_bandwidth_get(stmdev_ctx_t *ctx,
+ lsm6ds3_hpcf_g_t *val)
{
lsm6ds3_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
switch (ctrl7_g.hpcf_g)
{
case LSM6DS3_HP_CUT_OFF_8mHz1:
*val = LSM6DS3_HP_CUT_OFF_8mHz1;
break;
+
case LSM6DS3_HP_CUT_OFF_32mHz4:
*val = LSM6DS3_HP_CUT_OFF_32mHz4;
break;
+
case LSM6DS3_HP_CUT_OFF_2Hz07:
*val = LSM6DS3_HP_CUT_OFF_2Hz07;
break;
+
case LSM6DS3_HP_CUT_OFF_16Hz32:
*val = LSM6DS3_HP_CUT_OFF_16Hz32;
break;
+
default:
*val = LSM6DS3_HP_CUT_OFF_8mHz1;
break;
}
+
return ret;
}
@@ -1873,11 +2174,14 @@ int32_t lsm6ds3_gy_hp_reset_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
ctrl7_g.hp_g_rst = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
}
+
return ret;
}
@@ -1894,7 +2198,7 @@ int32_t lsm6ds3_gy_hp_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
*val = (uint8_t)ctrl7_g.hp_g_rst;
return ret;
@@ -1909,17 +2213,21 @@ int32_t lsm6ds3_gy_hp_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_xl_hp_bandwidth_set(stmdev_ctx_t *ctx, lsm6ds3_hp_bw_t val)
+int32_t lsm6ds3_xl_hp_bandwidth_set(stmdev_ctx_t *ctx,
+ lsm6ds3_hp_bw_t val)
{
lsm6ds3_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
- ctrl8_xl.hp_slope_xl_en = PROPERTY_ENABLE;
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl8_xl.hp_slope_xl_en = PROPERTY_ENABLE;
ctrl8_xl.hpcf_xl = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -1929,33 +2237,40 @@ int32_t lsm6ds3_xl_hp_bandwidth_set(stmdev_ctx_t *ctx, lsm6ds3_hp_bw_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of hp_slope_xl_en in reg CTRL8_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_xl_hp_bandwidth_get(stmdev_ctx_t *ctx, lsm6ds3_hp_bw_t *val)
+int32_t lsm6ds3_xl_hp_bandwidth_get(stmdev_ctx_t *ctx,
+ lsm6ds3_hp_bw_t *val)
{
lsm6ds3_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
switch (ctrl8_xl.hpcf_xl)
{
case LSM6DS3_XL_HP_ODR_DIV_4:
*val = LSM6DS3_XL_HP_ODR_DIV_4;
break;
+
case LSM6DS3_XL_HP_ODR_DIV_100:
*val = LSM6DS3_XL_HP_ODR_DIV_100;
break;
+
case LSM6DS3_XL_HP_ODR_DIV_9:
*val = LSM6DS3_XL_HP_ODR_DIV_9;
break;
+
case LSM6DS3_XL_HP_ODR_DIV_400:
*val = LSM6DS3_XL_HP_ODR_DIV_400;
break;
+
default:
*val = LSM6DS3_XL_HP_ODR_DIV_4;
break;
}
+
return ret;
}
@@ -1968,17 +2283,21 @@ int32_t lsm6ds3_xl_hp_bandwidth_get(stmdev_ctx_t *ctx, lsm6ds3_hp_bw_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, lsm6ds3_lp_bw_t val)
+int32_t lsm6ds3_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx,
+ lsm6ds3_lp_bw_t val)
{
lsm6ds3_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
ctrl8_xl.lpf2_xl_en = PROPERTY_ENABLE;
- ctrl8_xl.hpcf_xl= (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ctrl8_xl.hpcf_xl = (uint8_t)val;
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -1988,33 +2307,40 @@ int32_t lsm6ds3_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, lsm6ds3_lp_bw_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of lpf2_xl_en in reg CTRL8_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, lsm6ds3_lp_bw_t *val)
+int32_t lsm6ds3_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx,
+ lsm6ds3_lp_bw_t *val)
{
lsm6ds3_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
switch (ctrl8_xl.hpcf_xl)
{
case LSM6DS3_XL_LP_ODR_DIV_50:
*val = LSM6DS3_XL_LP_ODR_DIV_50;
break;
+
case LSM6DS3_XL_LP_ODR_DIV_100:
*val = LSM6DS3_XL_LP_ODR_DIV_100;
break;
+
case LSM6DS3_XL_LP_ODR_DIV_9:
*val = LSM6DS3_XL_LP_ODR_DIV_9;
break;
+
case LSM6DS3_XL_LP_ODR_DIV_400:
*val = LSM6DS3_XL_LP_ODR_DIV_400;
break;
+
default:
*val = LSM6DS3_XL_LP_ODR_DIV_50;
break;
}
+
return ret;
}
@@ -2026,16 +2352,20 @@ int32_t lsm6ds3_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, lsm6ds3_lp_bw_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_xl_filter_analog_set(stmdev_ctx_t *ctx, lsm6ds3_bw_xl_t val)
+int32_t lsm6ds3_xl_filter_analog_set(stmdev_ctx_t *ctx,
+ lsm6ds3_bw_xl_t val)
{
lsm6ds3_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
ctrl1_xl.bw_xl = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -2044,33 +2374,40 @@ int32_t lsm6ds3_xl_filter_analog_set(stmdev_ctx_t *ctx, lsm6ds3_bw_xl_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of bw_xl in reg CTRL1_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_xl_filter_analog_get(stmdev_ctx_t *ctx, lsm6ds3_bw_xl_t *val)
+int32_t lsm6ds3_xl_filter_analog_get(stmdev_ctx_t *ctx,
+ lsm6ds3_bw_xl_t *val)
{
lsm6ds3_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
switch (ctrl1_xl.bw_xl)
{
case LSM6DS3_ANTI_ALIASING_400Hz:
*val = LSM6DS3_ANTI_ALIASING_400Hz;
break;
+
case LSM6DS3_ANTI_ALIASING_200Hz:
*val = LSM6DS3_ANTI_ALIASING_200Hz;
break;
+
case LSM6DS3_ANTI_ALIASING_100Hz:
*val = LSM6DS3_ANTI_ALIASING_100Hz;
break;
+
case LSM6DS3_ANTI_ALIASING_50Hz:
*val = LSM6DS3_ANTI_ALIASING_50Hz;
break;
+
default:
*val = LSM6DS3_ANTI_ALIASING_400Hz;
break;
}
+
return ret;
}
@@ -2100,11 +2437,14 @@ int32_t lsm6ds3_spi_mode_set(stmdev_ctx_t *ctx, lsm6ds3_sim_t val)
lsm6ds3_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.sim = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -2113,6 +2453,7 @@ int32_t lsm6ds3_spi_mode_set(stmdev_ctx_t *ctx, lsm6ds3_sim_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of sim in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_spi_mode_get(stmdev_ctx_t *ctx, lsm6ds3_sim_t *val)
@@ -2120,20 +2461,23 @@ int32_t lsm6ds3_spi_mode_get(stmdev_ctx_t *ctx, lsm6ds3_sim_t *val)
lsm6ds3_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
switch (ctrl3_c.sim)
{
case LSM6DS3_SPI_4_WIRE:
*val = LSM6DS3_SPI_4_WIRE;
break;
+
case LSM6DS3_SPI_3_WIRE:
*val = LSM6DS3_SPI_3_WIRE;
break;
+
default:
*val = LSM6DS3_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -2145,16 +2489,20 @@ int32_t lsm6ds3_spi_mode_get(stmdev_ctx_t *ctx, lsm6ds3_sim_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_i2c_interface_set(stmdev_ctx_t *ctx, lsm6ds3_i2c_dis_t val)
+int32_t lsm6ds3_i2c_interface_set(stmdev_ctx_t *ctx,
+ lsm6ds3_i2c_dis_t val)
{
lsm6ds3_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
ctrl4_c.i2c_disable = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -2163,27 +2511,32 @@ int32_t lsm6ds3_i2c_interface_set(stmdev_ctx_t *ctx, lsm6ds3_i2c_dis_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of i2c_disable in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_i2c_interface_get(stmdev_ctx_t *ctx, lsm6ds3_i2c_dis_t *val)
+int32_t lsm6ds3_i2c_interface_get(stmdev_ctx_t *ctx,
+ lsm6ds3_i2c_dis_t *val)
{
lsm6ds3_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
switch (ctrl4_c.i2c_disable)
{
case LSM6DS3_I2C_ENABLE:
*val = LSM6DS3_I2C_ENABLE;
break;
+
case LSM6DS3_I2C_DISABLE:
*val = LSM6DS3_I2C_DISABLE;
break;
+
default:
*val = LSM6DS3_I2C_ENABLE;
break;
}
+
return ret;
}
@@ -2205,6 +2558,7 @@ int32_t lsm6ds3_i2c_interface_get(stmdev_ctx_t *ctx, lsm6ds3_i2c_dis_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Select the signal that need to route on int1 pad.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_pin_int1_route_set(stmdev_ctx_t *ctx,
@@ -2216,9 +2570,10 @@ int32_t lsm6ds3_pin_int1_route_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
- if(ret == 0) {
+ if (ret == 0)
+ {
int1_ctrl.int1_drdy_xl = val->int1_drdy_xl;
int1_ctrl.int1_drdy_g = val->int1_drdy_g;
int1_ctrl.int1_boot = val->int1_boot;
@@ -2236,16 +2591,20 @@ int32_t lsm6ds3_pin_int1_route_set(stmdev_ctx_t *ctx,
md1_cfg.int1_single_tap = val->int1_single_tap;
md1_cfg.int1_inact_state = val->int1_inact_state;
master_config.drdy_on_int1 = val->drdy_on_int1;
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
- if(ret == 0) {
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_MD1_CFG, (uint8_t*)&md1_cfg, 1);
+ if (ret == 0)
+ {
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_MD1_CFG, (uint8_t *)&md1_cfg, 1);
}
- if(ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6ds3_write_reg(ctx, LSM6DS3_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
}
+
return ret;
}
@@ -2253,7 +2612,8 @@ int32_t lsm6ds3_pin_int1_route_set(stmdev_ctx_t *ctx,
* @brief Select the signal that need to route on int1 pad.[get]
*
* @param ctx read / write interface definitions(ptr)
- * @param val Select the signal that need to route on int1 pad.
+ * @param val Select the signal that need to route on int1 pad.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_pin_int1_route_get(stmdev_ctx_t *ctx,
@@ -2264,15 +2624,21 @@ int32_t lsm6ds3_pin_int1_route_get(stmdev_ctx_t *ctx,
lsm6ds3_master_config_t master_config;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
- if(ret == 0) {
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_MD1_CFG, (uint8_t*)&md1_cfg, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_MD1_CFG, (uint8_t *)&md1_cfg, 1);
}
- if(ret == 0) {
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG,
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0) {
+
+ if (ret == 0)
+ {
val->int1_drdy_xl = int1_ctrl.int1_drdy_xl;
val->int1_drdy_g = int1_ctrl.int1_drdy_g;
val->int1_boot = int1_ctrl.int1_boot;
@@ -2291,6 +2657,7 @@ int32_t lsm6ds3_pin_int1_route_get(stmdev_ctx_t *ctx,
val->int1_inact_state = md1_cfg.int1_inact_state;
val->drdy_on_int1 = master_config.drdy_on_int1;
}
+
return ret;
}
@@ -2299,6 +2666,7 @@ int32_t lsm6ds3_pin_int1_route_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Select the signal that need to route on int1 pad.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_pin_int2_route_set(stmdev_ctx_t *ctx,
@@ -2310,9 +2678,10 @@ int32_t lsm6ds3_pin_int2_route_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
- if(ret == 0) {
+ if (ret == 0)
+ {
int2_ctrl.int2_drdy_xl = val->int2_drdy_xl;
int2_ctrl.int2_drdy_g = val->int2_drdy_g;
int2_ctrl.int2_drdy_temp = val->int2_drdy_temp;
@@ -2330,16 +2699,20 @@ int32_t lsm6ds3_pin_int2_route_set(stmdev_ctx_t *ctx,
md2_cfg.int2_single_tap = val->int2_single_tap;
md2_cfg.int2_inact_state = val->int2_inact_state;
master_config.start_config = val->start_config;
-
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
}
- if(ret == 0) {
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_MD2_CFG, (uint8_t*)&md2_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_MD2_CFG, (uint8_t *)&md2_cfg, 1);
}
- if(ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6ds3_write_reg(ctx, LSM6DS3_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
+
return ret;
}
@@ -2348,6 +2721,7 @@ int32_t lsm6ds3_pin_int2_route_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Select the signal that need to route on int1 pad.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_pin_int2_route_get(stmdev_ctx_t *ctx,
@@ -2358,14 +2732,17 @@ int32_t lsm6ds3_pin_int2_route_get(stmdev_ctx_t *ctx,
lsm6ds3_master_config_t master_config;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
- if(ret == 0) {
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_MD2_CFG, (uint8_t*)&md2_cfg, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_MD2_CFG, (uint8_t *)&md2_cfg, 1);
}
- if(ret == 0) {
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ if (ret == 0)
+ {
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG,
+ (uint8_t *)&master_config, 1);
val->int2_drdy_xl = int2_ctrl.int2_drdy_xl;
val->int2_drdy_g = int2_ctrl.int2_drdy_g;
val->int2_drdy_temp = int2_ctrl.int2_drdy_temp;
@@ -2401,11 +2778,14 @@ int32_t lsm6ds3_pin_mode_set(stmdev_ctx_t *ctx, lsm6ds3_pp_od_t val)
lsm6ds3_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.pp_od = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -2414,6 +2794,7 @@ int32_t lsm6ds3_pin_mode_set(stmdev_ctx_t *ctx, lsm6ds3_pp_od_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of pp_od in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_pin_mode_get(stmdev_ctx_t *ctx, lsm6ds3_pp_od_t *val)
@@ -2421,20 +2802,23 @@ int32_t lsm6ds3_pin_mode_get(stmdev_ctx_t *ctx, lsm6ds3_pp_od_t *val)
lsm6ds3_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
switch (ctrl3_c.pp_od)
{
case LSM6DS3_PUSH_PULL:
*val = LSM6DS3_PUSH_PULL;
break;
+
case LSM6DS3_OPEN_DRAIN:
*val = LSM6DS3_OPEN_DRAIN;
break;
+
default:
*val = LSM6DS3_PUSH_PULL;
break;
}
+
return ret;
}
@@ -2446,16 +2830,20 @@ int32_t lsm6ds3_pin_mode_get(stmdev_ctx_t *ctx, lsm6ds3_pp_od_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_pin_polarity_set(stmdev_ctx_t *ctx, lsm6ds3_pin_pol_t val)
+int32_t lsm6ds3_pin_polarity_set(stmdev_ctx_t *ctx,
+ lsm6ds3_pin_pol_t val)
{
lsm6ds3_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.h_lactive = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -2464,27 +2852,32 @@ int32_t lsm6ds3_pin_polarity_set(stmdev_ctx_t *ctx, lsm6ds3_pin_pol_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of h_lactive in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_pin_polarity_get(stmdev_ctx_t *ctx, lsm6ds3_pin_pol_t *val)
+int32_t lsm6ds3_pin_polarity_get(stmdev_ctx_t *ctx,
+ lsm6ds3_pin_pol_t *val)
{
lsm6ds3_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
switch (ctrl3_c.h_lactive)
{
case LSM6DS3_ACTIVE_HIGH:
*val = LSM6DS3_ACTIVE_HIGH;
break;
+
case LSM6DS3_ACTIVE_LOW:
*val = LSM6DS3_ACTIVE_LOW;
break;
+
default:
*val = LSM6DS3_ACTIVE_HIGH;
break;
}
+
return ret;
}
@@ -2501,11 +2894,14 @@ int32_t lsm6ds3_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
ctrl4_c.int2_on_int1 = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -2522,7 +2918,7 @@ int32_t lsm6ds3_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
*val = (uint8_t)ctrl4_c.int2_on_int1;
return ret;
@@ -2536,16 +2932,20 @@ int32_t lsm6ds3_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_int_notification_set(stmdev_ctx_t *ctx, lsm6ds3_lir_t val)
+int32_t lsm6ds3_int_notification_set(stmdev_ctx_t *ctx,
+ lsm6ds3_lir_t val)
{
lsm6ds3_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
tap_cfg.lir = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -2554,27 +2954,32 @@ int32_t lsm6ds3_int_notification_set(stmdev_ctx_t *ctx, lsm6ds3_lir_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of lir in reg TAP_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_int_notification_get(stmdev_ctx_t *ctx, lsm6ds3_lir_t *val)
+int32_t lsm6ds3_int_notification_get(stmdev_ctx_t *ctx,
+ lsm6ds3_lir_t *val)
{
lsm6ds3_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1);
switch (tap_cfg.lir)
{
case LSM6DS3_INT_PULSED:
*val = LSM6DS3_INT_PULSED;
break;
+
case LSM6DS3_INT_LATCHED:
*val = LSM6DS3_INT_LATCHED;
break;
+
default:
*val = LSM6DS3_INT_PULSED;
break;
}
+
return ret;
}
@@ -2596,13 +3001,15 @@ int32_t lsm6ds3_int_notification_get(stmdev_ctx_t *ctx, lsm6ds3_lir_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Read the wake_up_src status flag of the device.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_wkup_src_get(stmdev_ctx_t *ctx, lsm6ds3_wake_up_src_t *val)
+int32_t lsm6ds3_wkup_src_get(stmdev_ctx_t *ctx,
+ lsm6ds3_wake_up_src_t *val)
{
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_SRC, (uint8_t*)val, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_SRC, (uint8_t *)val, 1);
return ret;
}
@@ -2620,12 +3027,16 @@ int32_t lsm6ds3_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_wake_up_ths_t wake_up_ths;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_THS, (uint8_t*)&wake_up_ths, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_THS,
+ (uint8_t *)&wake_up_ths, 1);
+
+ if (ret == 0)
+ {
wake_up_ths.wk_ths = (uint8_t)val;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
}
+
return ret;
}
@@ -2642,7 +3053,8 @@ int32_t lsm6ds3_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_wake_up_ths_t wake_up_ths;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_THS, (uint8_t*)&wake_up_ths, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_THS,
+ (uint8_t *)&wake_up_ths, 1);
*val = (uint8_t)wake_up_ths.wk_ths;
return ret;
@@ -2661,12 +3073,16 @@ int32_t lsm6ds3_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_wake_up_dur_t wake_up_dur;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
wake_up_dur.wake_dur = (uint8_t)val;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -2683,7 +3099,8 @@ int32_t lsm6ds3_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_wake_up_dur_t wake_up_dur;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
*val = (uint8_t)wake_up_dur.wake_dur;
return ret;
@@ -2715,11 +3132,14 @@ int32_t lsm6ds3_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
ctrl4_c.sleep_g = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -2736,7 +3156,7 @@ int32_t lsm6ds3_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
*val = (uint8_t)ctrl4_c.sleep_g;
return ret;
@@ -2755,12 +3175,16 @@ int32_t lsm6ds3_act_mode_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_wake_up_ths_t wake_up_ths;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_THS, (uint8_t*)&wake_up_ths, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_THS,
+ (uint8_t *)&wake_up_ths, 1);
+
+ if (ret == 0)
+ {
wake_up_ths.inactivity = (uint8_t)val;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
}
+
return ret;
}
@@ -2769,6 +3193,7 @@ int32_t lsm6ds3_act_mode_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of inactivity in reg WAKE_UP_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_act_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -2776,7 +3201,8 @@ int32_t lsm6ds3_act_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_wake_up_ths_t wake_up_ths;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_THS, (uint8_t*)&wake_up_ths, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_THS,
+ (uint8_t *)&wake_up_ths, 1);
*val = wake_up_ths.inactivity;
return ret;
@@ -2795,12 +3221,16 @@ int32_t lsm6ds3_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_wake_up_dur_t wake_up_dur;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
wake_up_dur.sleep_dur = (uint8_t)val;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -2817,7 +3247,8 @@ int32_t lsm6ds3_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_wake_up_dur_t wake_up_dur;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
*val = (uint8_t)wake_up_dur.sleep_dur;
return ret;
@@ -2841,13 +3272,14 @@ int32_t lsm6ds3_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions(ptr)
* @param val Read the tap_src status flag of the device.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_tap_src_get(stmdev_ctx_t *ctx, lsm6ds3_tap_src_t *val)
{
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_SRC, (uint8_t*)val, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_SRC, (uint8_t *)val, 1);
return ret;
}
@@ -2865,11 +3297,14 @@ int32_t lsm6ds3_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
tap_cfg.tap_z_en = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -2881,12 +3316,13 @@ int32_t lsm6ds3_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1);
*val = (uint8_t)tap_cfg.tap_z_en;
return ret;
@@ -2905,11 +3341,14 @@ int32_t lsm6ds3_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
tap_cfg.tap_y_en = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -2921,12 +3360,13 @@ int32_t lsm6ds3_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1);
*val = (uint8_t)tap_cfg.tap_y_en;
return ret;
@@ -2945,11 +3385,14 @@ int32_t lsm6ds3_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
tap_cfg.tap_x_en = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -2961,12 +3404,13 @@ int32_t lsm6ds3_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1);
*val = (uint8_t)tap_cfg.tap_x_en;
return ret;
@@ -2985,11 +3429,16 @@ int32_t lsm6ds3_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_tap_ths_6d_t tap_ths_6d;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_THS_6D,
+ (uint8_t *)&tap_ths_6d, 1);
+
+ if (ret == 0)
+ {
tap_ths_6d.tap_ths = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_THS_6D,
+ (uint8_t *)&tap_ths_6d, 1);
}
+
return ret;
}
@@ -3006,7 +3455,8 @@ int32_t lsm6ds3_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_tap_ths_6d_t tap_ths_6d;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_THS_6D,
+ (uint8_t *)&tap_ths_6d, 1);
*val = (uint8_t)tap_ths_6d.tap_ths;
return ret;
@@ -3029,11 +3479,14 @@ int32_t lsm6ds3_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t*)&int_dur2, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t *)&int_dur2, 1);
+
+ if (ret == 0)
+ {
int_dur2.shock = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t *)&int_dur2, 1);
}
+
return ret;
}
@@ -3054,7 +3507,7 @@ int32_t lsm6ds3_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t *)&int_dur2, 1);
*val = (uint8_t)int_dur2.shock;
return ret;
@@ -3077,11 +3530,14 @@ int32_t lsm6ds3_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t*)&int_dur2, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t *)&int_dur2, 1);
+
+ if (ret == 0)
+ {
int_dur2.quiet = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t *)&int_dur2, 1);
}
+
return ret;
}
@@ -3102,7 +3558,7 @@ int32_t lsm6ds3_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t *)&int_dur2, 1);
*val = (uint8_t)int_dur2.quiet;
return ret;
@@ -3126,11 +3582,14 @@ int32_t lsm6ds3_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t*)&int_dur2, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t *)&int_dur2, 1);
+
+ if (ret == 0)
+ {
int_dur2.dur = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t *)&int_dur2, 1);
}
+
return ret;
}
@@ -3152,7 +3611,7 @@ int32_t lsm6ds3_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t *)&int_dur2, 1);
*val = (uint8_t)int_dur2.dur;
return ret;
@@ -3171,12 +3630,16 @@ int32_t lsm6ds3_tap_mode_set(stmdev_ctx_t *ctx, lsm6ds3_tap_md_t val)
lsm6ds3_wake_up_ths_t wake_up_ths;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_THS, (uint8_t*)&wake_up_ths, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_THS,
+ (uint8_t *)&wake_up_ths, 1);
+
+ if (ret == 0)
+ {
wake_up_ths.single_double_tap = (uint8_t)val;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
}
+
return ret;
}
@@ -3185,6 +3648,7 @@ int32_t lsm6ds3_tap_mode_set(stmdev_ctx_t *ctx, lsm6ds3_tap_md_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of single_double_tap in reg WAKE_UP_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_tap_mode_get(stmdev_ctx_t *ctx, lsm6ds3_tap_md_t *val)
@@ -3192,20 +3656,24 @@ int32_t lsm6ds3_tap_mode_get(stmdev_ctx_t *ctx, lsm6ds3_tap_md_t *val)
lsm6ds3_wake_up_ths_t wake_up_ths;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_THS, (uint8_t*)&wake_up_ths, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_THS,
+ (uint8_t *)&wake_up_ths, 1);
switch (wake_up_ths.single_double_tap)
{
case LSM6DS3_ONLY_DOUBLE:
*val = LSM6DS3_ONLY_DOUBLE;
break;
+
case LSM6DS3_SINGLE_DOUBLE:
*val = LSM6DS3_SINGLE_DOUBLE;
break;
+
default:
*val = LSM6DS3_ONLY_DOUBLE;
break;
}
+
return ret;
}
@@ -3236,11 +3704,14 @@ int32_t lsm6ds3_6d_feed_data_set(stmdev_ctx_t *ctx,
lsm6ds3_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
ctrl8_xl.low_pass_on_6d = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -3249,6 +3720,7 @@ int32_t lsm6ds3_6d_feed_data_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of low_pass_on_6d in reg CTRL8_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_6d_feed_data_get(stmdev_ctx_t *ctx,
@@ -3257,20 +3729,23 @@ int32_t lsm6ds3_6d_feed_data_get(stmdev_ctx_t *ctx,
lsm6ds3_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
switch (ctrl8_xl.low_pass_on_6d)
{
case LSM6DS3_ODR_DIV_2_FEED:
*val = LSM6DS3_ODR_DIV_2_FEED;
break;
+
case LSM6DS3_LPF2_FEED:
*val = LSM6DS3_LPF2_FEED;
break;
+
default:
*val = LSM6DS3_ODR_DIV_2_FEED;
break;
}
+
return ret;
}
@@ -3279,13 +3754,14 @@ int32_t lsm6ds3_6d_feed_data_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val Read the d6d_src status flag of the device.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_6d_src_get(stmdev_ctx_t *ctx, lsm6ds3_d6d_src_t *val)
{
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_D6D_SRC, (uint8_t*)val, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_D6D_SRC, (uint8_t *)val, 1);
return ret;
}
@@ -3298,17 +3774,22 @@ int32_t lsm6ds3_6d_src_get(stmdev_ctx_t *ctx, lsm6ds3_d6d_src_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_6d_threshold_set(stmdev_ctx_t *ctx, lsm6ds3_sixd_ths_t val)
+int32_t lsm6ds3_6d_threshold_set(stmdev_ctx_t *ctx,
+ lsm6ds3_sixd_ths_t val)
{
lsm6ds3_tap_ths_6d_t tap_ths_6d;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_THS_6D,
+ (uint8_t *)&tap_ths_6d, 1);
+
+ if (ret == 0)
+ {
tap_ths_6d.sixd_ths = (uint8_t)val;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
+ (uint8_t *)&tap_ths_6d, 1);
}
+
return ret;
}
@@ -3317,33 +3798,41 @@ int32_t lsm6ds3_6d_threshold_set(stmdev_ctx_t *ctx, lsm6ds3_sixd_ths_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of sixd_ths in reg TAP_THS_6D
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_6d_threshold_get(stmdev_ctx_t *ctx, lsm6ds3_sixd_ths_t *val)
+int32_t lsm6ds3_6d_threshold_get(stmdev_ctx_t *ctx,
+ lsm6ds3_sixd_ths_t *val)
{
lsm6ds3_tap_ths_6d_t tap_ths_6d;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_THS_6D,
+ (uint8_t *)&tap_ths_6d, 1);
switch (tap_ths_6d.sixd_ths)
{
case LSM6DS3_DEG_80:
*val = LSM6DS3_DEG_80;
break;
+
case LSM6DS3_DEG_70:
*val = LSM6DS3_DEG_70;
break;
+
case LSM6DS3_DEG_60:
*val = LSM6DS3_DEG_60;
break;
+
case LSM6DS3_DEG_50:
*val = LSM6DS3_DEG_50;
break;
+
default:
*val = LSM6DS3_DEG_80;
break;
}
+
return ret;
}
@@ -3360,12 +3849,16 @@ int32_t lsm6ds3_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_tap_ths_6d_t tap_ths_6d;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_THS_6D,
+ (uint8_t *)&tap_ths_6d, 1);
+
+ if (ret == 0)
+ {
tap_ths_6d.d4d_en = (uint8_t)val;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
+ (uint8_t *)&tap_ths_6d, 1);
}
+
return ret;
}
@@ -3382,7 +3875,8 @@ int32_t lsm6ds3_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_tap_ths_6d_t tap_ths_6d;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_THS_6D,
+ (uint8_t *)&tap_ths_6d, 1);
*val = (uint8_t)tap_ths_6d.d4d_en;
return ret;
@@ -3409,16 +3903,20 @@ int32_t lsm6ds3_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_ff_threshold_set(stmdev_ctx_t *ctx, lsm6ds3_ff_ths_t val)
+int32_t lsm6ds3_ff_threshold_set(stmdev_ctx_t *ctx,
+ lsm6ds3_ff_ths_t val)
{
lsm6ds3_free_fall_t free_fall;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FREE_FALL, (uint8_t*)&free_fall, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FREE_FALL, (uint8_t *)&free_fall, 1);
+
+ if (ret == 0)
+ {
free_fall.ff_ths = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_FREE_FALL, (uint8_t*)&free_fall, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_FREE_FALL, (uint8_t *)&free_fall, 1);
}
+
return ret;
}
@@ -3427,45 +3925,56 @@ int32_t lsm6ds3_ff_threshold_set(stmdev_ctx_t *ctx, lsm6ds3_ff_ths_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of ff_ths in reg FREE_FALL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_ff_threshold_get(stmdev_ctx_t *ctx, lsm6ds3_ff_ths_t *val)
+int32_t lsm6ds3_ff_threshold_get(stmdev_ctx_t *ctx,
+ lsm6ds3_ff_ths_t *val)
{
lsm6ds3_free_fall_t free_fall;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FREE_FALL, (uint8_t*)&free_fall, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FREE_FALL, (uint8_t *)&free_fall, 1);
switch (free_fall.ff_ths)
{
case LSM6DS3_156_mg:
*val = LSM6DS3_156_mg;
break;
+
case LSM6DS3_219_mg:
*val = LSM6DS3_219_mg;
break;
+
case LSM6DS3_250_mg:
*val = LSM6DS3_250_mg;
break;
+
case LSM6DS3_312_mg:
*val = LSM6DS3_312_mg;
break;
+
case LSM6DS3_344_mg:
*val = LSM6DS3_344_mg;
break;
+
case LSM6DS3_406_mg:
*val = LSM6DS3_406_mg;
break;
+
case LSM6DS3_469_mg:
*val = LSM6DS3_469_mg;
break;
+
case LSM6DS3_500_mg:
*val = LSM6DS3_500_mg;
break;
+
default:
*val = LSM6DS3_156_mg;
break;
}
+
return ret;
}
@@ -3482,11 +3991,14 @@ int32_t lsm6ds3_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_free_fall_t free_fall;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FREE_FALL, (uint8_t*)&free_fall, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FREE_FALL, (uint8_t *)&free_fall, 1);
+
+ if (ret == 0)
+ {
free_fall.ff_dur = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_FREE_FALL, (uint8_t*)&free_fall, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_FREE_FALL, (uint8_t *)&free_fall, 1);
}
+
return ret;
}
@@ -3503,7 +4015,7 @@ int32_t lsm6ds3_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_free_fall_t free_fall;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FREE_FALL, (uint8_t*)&free_fall, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FREE_FALL, (uint8_t *)&free_fall, 1);
*val = (uint8_t)free_fall.ff_dur;
return ret;
@@ -3536,18 +4048,29 @@ int32_t lsm6ds3_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
lsm6ds3_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1);
- if(ret == 0){
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL1,
+ (uint8_t *)&fifo_ctrl1, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
fifo_ctrl2.fth = (uint8_t)((val & 0x0F00U) >> 8);
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
fifo_ctrl1.fth = (uint8_t)(val & 0x00FF0U);
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL1,
+ (uint8_t *)&fifo_ctrl1, 1);
}
+
return ret;
}
@@ -3565,12 +4088,17 @@ int32_t lsm6ds3_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
lsm6ds3_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1);
- if(ret == 0){
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL1,
+ (uint8_t *)&fifo_ctrl1, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
*val = (uint16_t)fifo_ctrl2.fth << 8;
*val |= fifo_ctrl1.fth;
}
+
return ret;
}
@@ -3583,16 +4111,21 @@ int32_t lsm6ds3_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
*
*/
int32_t lsm6ds3_fifo_write_trigger_set(stmdev_ctx_t *ctx,
- lsm6ds3_tmr_ped_fifo_drdy_t val)
+ lsm6ds3_tmr_ped_fifo_drdy_t val)
{
lsm6ds3_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl2. timer_pedo_fifo_drdy = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
}
+
return ret;
}
@@ -3602,6 +4135,7 @@ int32_t lsm6ds3_fifo_write_trigger_set(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions(ptr)
* @param val get the values of timer_pedo_fifo_drdy in
* reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_fifo_write_trigger_get(stmdev_ctx_t *ctx,
@@ -3610,20 +4144,24 @@ int32_t lsm6ds3_fifo_write_trigger_get(stmdev_ctx_t *ctx,
lsm6ds3_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
switch (fifo_ctrl2. timer_pedo_fifo_drdy)
{
case LSM6DS3_TRG_XL_GY_DRDY:
*val = LSM6DS3_TRG_XL_GY_DRDY;
break;
+
case LSM6DS3_TRG_STEP_DETECT:
*val = LSM6DS3_TRG_STEP_DETECT;
break;
+
default:
*val = LSM6DS3_TRG_XL_GY_DRDY;
break;
}
+
return ret;
}
@@ -3640,12 +4178,16 @@ int32_t lsm6ds3_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl2.timer_pedo_fifo_en = (uint8_t)val;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
+
return ret;
}
@@ -3662,7 +4204,8 @@ int32_t lsm6ds3_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
*val = (uint8_t)fifo_ctrl2.timer_pedo_fifo_en;
return ret;
@@ -3677,17 +4220,22 @@ int32_t lsm6ds3_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_fifo_xl_batch_set(stmdev_ctx_t *ctx, lsm6ds3_dec_fifo_xl_t val)
+int32_t lsm6ds3_fifo_xl_batch_set(stmdev_ctx_t *ctx,
+ lsm6ds3_dec_fifo_xl_t val)
{
lsm6ds3_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL3, (uint8_t*)&fifo_ctrl3, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL3,
+ (uint8_t *)&fifo_ctrl3, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl3.dec_fifo_xl = (uint8_t)val;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
+ (uint8_t *)&fifo_ctrl3, 1);
}
+
return ret;
}
@@ -3697,6 +4245,7 @@ int32_t lsm6ds3_fifo_xl_batch_set(stmdev_ctx_t *ctx, lsm6ds3_dec_fifo_xl_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of dec_fifo_xl in reg FIFO_CTRL3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_fifo_xl_batch_get(stmdev_ctx_t *ctx,
@@ -3705,38 +4254,48 @@ int32_t lsm6ds3_fifo_xl_batch_get(stmdev_ctx_t *ctx,
lsm6ds3_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL3, (uint8_t*)&fifo_ctrl3, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL3,
+ (uint8_t *)&fifo_ctrl3, 1);
switch (fifo_ctrl3.dec_fifo_xl)
{
case LSM6DS3_FIFO_XL_DISABLE:
*val = LSM6DS3_FIFO_XL_DISABLE;
break;
+
case LSM6DS3_FIFO_XL_NO_DEC:
*val = LSM6DS3_FIFO_XL_NO_DEC;
break;
+
case LSM6DS3_FIFO_XL_DEC_2:
*val = LSM6DS3_FIFO_XL_DEC_2;
break;
+
case LSM6DS3_FIFO_XL_DEC_3:
*val = LSM6DS3_FIFO_XL_DEC_3;
break;
+
case LSM6DS3_FIFO_XL_DEC_4:
*val = LSM6DS3_FIFO_XL_DEC_4;
break;
+
case LSM6DS3_FIFO_XL_DEC_8:
*val = LSM6DS3_FIFO_XL_DEC_8;
break;
+
case LSM6DS3_FIFO_XL_DEC_16:
*val = LSM6DS3_FIFO_XL_DEC_16;
break;
+
case LSM6DS3_FIFO_XL_DEC_32:
*val = LSM6DS3_FIFO_XL_DEC_32;
break;
+
default:
*val = LSM6DS3_FIFO_XL_DISABLE;
break;
}
+
return ret;
}
@@ -3749,17 +4308,22 @@ int32_t lsm6ds3_fifo_xl_batch_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_fifo_gy_batch_set(stmdev_ctx_t *ctx, lsm6ds3_dec_fifo_gyro_t val)
+int32_t lsm6ds3_fifo_gy_batch_set(stmdev_ctx_t *ctx,
+ lsm6ds3_dec_fifo_gyro_t val)
{
lsm6ds3_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL3, (uint8_t*)&fifo_ctrl3, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL3,
+ (uint8_t *)&fifo_ctrl3, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl3.dec_fifo_gyro = (uint8_t)val;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
+ (uint8_t *)&fifo_ctrl3, 1);
}
+
return ret;
}
@@ -3769,6 +4333,7 @@ int32_t lsm6ds3_fifo_gy_batch_set(stmdev_ctx_t *ctx, lsm6ds3_dec_fifo_gyro_t val
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of dec_fifo_gyro in reg FIFO_CTRL3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_fifo_gy_batch_get(stmdev_ctx_t *ctx,
@@ -3777,38 +4342,48 @@ int32_t lsm6ds3_fifo_gy_batch_get(stmdev_ctx_t *ctx,
lsm6ds3_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL3, (uint8_t*)&fifo_ctrl3, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL3,
+ (uint8_t *)&fifo_ctrl3, 1);
switch (fifo_ctrl3.dec_fifo_gyro)
{
case LSM6DS3_FIFO_GY_DISABLE:
*val = LSM6DS3_FIFO_GY_DISABLE;
break;
+
case LSM6DS3_FIFO_GY_NO_DEC:
*val = LSM6DS3_FIFO_GY_NO_DEC;
break;
+
case LSM6DS3_FIFO_GY_DEC_2:
*val = LSM6DS3_FIFO_GY_DEC_2;
break;
+
case LSM6DS3_FIFO_GY_DEC_3:
*val = LSM6DS3_FIFO_GY_DEC_3;
break;
+
case LSM6DS3_FIFO_GY_DEC_4:
*val = LSM6DS3_FIFO_GY_DEC_4;
break;
+
case LSM6DS3_FIFO_GY_DEC_8:
*val = LSM6DS3_FIFO_GY_DEC_8;
break;
+
case LSM6DS3_FIFO_GY_DEC_16:
*val = LSM6DS3_FIFO_GY_DEC_16;
break;
+
case LSM6DS3_FIFO_GY_DEC_32:
*val = LSM6DS3_FIFO_GY_DEC_32;
break;
+
default:
*val = LSM6DS3_FIFO_GY_DISABLE;
break;
}
+
return ret;
}
@@ -3827,12 +4402,16 @@ int32_t lsm6ds3_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx,
lsm6ds3_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl4.dec_ds3_fifo = (uint8_t)val;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -3842,46 +4421,57 @@ int32_t lsm6ds3_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of dec_ds3_fifo in reg FIFO_CTRL4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx,
- lsm6ds3_dec_ds3_fifo_t *val)
+ lsm6ds3_dec_ds3_fifo_t *val)
{
lsm6ds3_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
switch (fifo_ctrl4.dec_ds3_fifo)
{
case LSM6DS3_FIFO_DS3_DISABLE:
*val = LSM6DS3_FIFO_DS3_DISABLE;
break;
+
case LSM6DS3_FIFO_DS3_NO_DEC:
*val = LSM6DS3_FIFO_DS3_NO_DEC;
break;
+
case LSM6DS3_FIFO_DS3_DEC_2:
*val = LSM6DS3_FIFO_DS3_DEC_2;
break;
+
case LSM6DS3_FIFO_DS3_DEC_3:
*val = LSM6DS3_FIFO_DS3_DEC_3;
break;
+
case LSM6DS3_FIFO_DS3_DEC_4:
*val = LSM6DS3_FIFO_DS3_DEC_4;
break;
+
case LSM6DS3_FIFO_DS3_DEC_8:
*val = LSM6DS3_FIFO_DS3_DEC_8;
break;
+
case LSM6DS3_FIFO_DS3_DEC_16:
*val = LSM6DS3_FIFO_DS3_DEC_16;
break;
+
case LSM6DS3_FIFO_DS3_DEC_32:
*val = LSM6DS3_FIFO_DS3_DEC_32;
break;
+
default:
*val = LSM6DS3_FIFO_DS3_DISABLE;
break;
}
+
return ret;
}
@@ -3900,12 +4490,16 @@ int32_t lsm6ds3_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx,
lsm6ds3_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl4.dec_ds4_fifo = (uint8_t)val;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -3915,6 +4509,7 @@ int32_t lsm6ds3_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of dec_ds4_fifo in reg FIFO_CTRL4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx,
@@ -3923,38 +4518,48 @@ int32_t lsm6ds3_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx,
lsm6ds3_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
switch (fifo_ctrl4.dec_ds4_fifo)
{
case LSM6DS3_FIFO_DS4_DISABLE:
*val = LSM6DS3_FIFO_DS4_DISABLE;
break;
+
case LSM6DS3_FIFO_DS4_NO_DEC:
*val = LSM6DS3_FIFO_DS4_NO_DEC;
break;
+
case LSM6DS3_FIFO_DS4_DEC_2:
*val = LSM6DS3_FIFO_DS4_DEC_2;
break;
+
case LSM6DS3_FIFO_DS4_DEC_3:
*val = LSM6DS3_FIFO_DS4_DEC_3;
break;
+
case LSM6DS3_FIFO_DS4_DEC_4:
*val = LSM6DS3_FIFO_DS4_DEC_4;
break;
+
case LSM6DS3_FIFO_DS4_DEC_8:
*val = LSM6DS3_FIFO_DS4_DEC_8;
break;
+
case LSM6DS3_FIFO_DS4_DEC_16:
*val = LSM6DS3_FIFO_DS4_DEC_16;
break;
+
case LSM6DS3_FIFO_DS4_DEC_32:
*val = LSM6DS3_FIFO_DS4_DEC_32;
break;
+
default:
*val = LSM6DS3_FIFO_DS4_DISABLE;
break;
}
+
return ret;
}
@@ -3966,17 +4571,22 @@ int32_t lsm6ds3_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6ds3_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6ds3_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl4.only_high_data = (uint8_t)val;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -3988,12 +4598,14 @@ int32_t lsm6ds3_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
*val = (uint8_t)fifo_ctrl4.only_high_data;
return ret;
@@ -4007,17 +4619,22 @@ int32_t lsm6ds3_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_fifo_mode_set(stmdev_ctx_t *ctx, lsm6ds3_fifo_md_t val)
+int32_t lsm6ds3_fifo_mode_set(stmdev_ctx_t *ctx,
+ lsm6ds3_fifo_md_t val)
{
lsm6ds3_fifo_ctrl5_t fifo_ctrl5;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL5,
+ (uint8_t *)&fifo_ctrl5, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl5.fifo_mode = (uint8_t)val;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL5,
- (uint8_t*)&fifo_ctrl5, 1);
+ (uint8_t *)&fifo_ctrl5, 1);
}
+
return ret;
}
@@ -4026,33 +4643,41 @@ int32_t lsm6ds3_fifo_mode_set(stmdev_ctx_t *ctx, lsm6ds3_fifo_md_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of fifo_mode in reg FIFO_CTRL5
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_fifo_mode_get(stmdev_ctx_t *ctx, lsm6ds3_fifo_md_t *val)
+int32_t lsm6ds3_fifo_mode_get(stmdev_ctx_t *ctx,
+ lsm6ds3_fifo_md_t *val)
{
lsm6ds3_fifo_ctrl5_t fifo_ctrl5;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL5,
+ (uint8_t *)&fifo_ctrl5, 1);
switch (fifo_ctrl5.fifo_mode)
{
case LSM6DS3_BYPASS_MODE:
*val = LSM6DS3_BYPASS_MODE;
break;
+
case LSM6DS3_FIFO_MODE:
*val = LSM6DS3_FIFO_MODE;
break;
+
case LSM6DS3_STREAM_TO_FIFO_MODE:
*val = LSM6DS3_STREAM_TO_FIFO_MODE;
break;
+
case LSM6DS3_BYPASS_TO_STREAM_MODE:
*val = LSM6DS3_BYPASS_TO_STREAM_MODE;
break;
+
default:
*val = LSM6DS3_BYPASS_MODE;
break;
}
+
return ret;
}
@@ -4064,17 +4689,22 @@ int32_t lsm6ds3_fifo_mode_get(stmdev_ctx_t *ctx, lsm6ds3_fifo_md_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_fifo_data_rate_set(stmdev_ctx_t *ctx, lsm6ds3_odr_fifo_t val)
+int32_t lsm6ds3_fifo_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6ds3_odr_fifo_t val)
{
lsm6ds3_fifo_ctrl5_t fifo_ctrl5;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL5,
+ (uint8_t *)&fifo_ctrl5, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl5.odr_fifo = (uint8_t)val;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL5,
- (uint8_t*)&fifo_ctrl5, 1);
+ (uint8_t *)&fifo_ctrl5, 1);
}
+
return ret;
}
@@ -4083,6 +4713,7 @@ int32_t lsm6ds3_fifo_data_rate_set(stmdev_ctx_t *ctx, lsm6ds3_odr_fifo_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of odr_fifo in reg FIFO_CTRL5
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_fifo_data_rate_get(stmdev_ctx_t *ctx,
@@ -4091,47 +4722,60 @@ int32_t lsm6ds3_fifo_data_rate_get(stmdev_ctx_t *ctx,
lsm6ds3_fifo_ctrl5_t fifo_ctrl5;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL5,
+ (uint8_t *)&fifo_ctrl5, 1);
switch (fifo_ctrl5.odr_fifo)
{
case LSM6DS3_FIFO_DISABLE:
*val = LSM6DS3_FIFO_DISABLE;
break;
+
case LSM6DS3_FIFO_12Hz5:
*val = LSM6DS3_FIFO_12Hz5;
break;
+
case LSM6DS3_FIFO_26Hz:
*val = LSM6DS3_FIFO_26Hz;
break;
+
case LSM6DS3_FIFO_52Hz:
*val = LSM6DS3_FIFO_52Hz;
break;
+
case LSM6DS3_FIFO_104Hz:
*val = LSM6DS3_FIFO_104Hz;
break;
+
case LSM6DS3_FIFO_208Hz:
*val = LSM6DS3_FIFO_208Hz;
break;
+
case LSM6DS3_FIFO_416Hz:
*val = LSM6DS3_FIFO_416Hz;
break;
+
case LSM6DS3_FIFO_833Hz:
*val = LSM6DS3_FIFO_833Hz;
break;
+
case LSM6DS3_FIFO_1k66Hz:
*val = LSM6DS3_FIFO_1k66Hz;
break;
+
case LSM6DS3_FIFO_3k33Hz:
*val = LSM6DS3_FIFO_3k33Hz;
break;
+
case LSM6DS3_FIFO_6k66Hz:
*val = LSM6DS3_FIFO_6k66Hz;
break;
+
default:
*val = LSM6DS3_FIFO_DISABLE;
break;
}
+
return ret;
}
@@ -4149,11 +4793,14 @@ int32_t lsm6ds3_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
ctrl4_c.stop_on_fth = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -4171,7 +4818,7 @@ int32_t lsm6ds3_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
*val = (uint8_t)ctrl4_c.stop_on_fth;
return ret;
@@ -4190,11 +4837,14 @@ int32_t lsm6ds3_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
ctrl4_c.fifo_temp_en = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -4211,7 +4861,7 @@ int32_t lsm6ds3_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
*val = (uint8_t)ctrl4_c.fifo_temp_en;
return ret;
@@ -4232,15 +4882,16 @@ int32_t lsm6ds3_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
int32_t ret;
ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_STATUS1,
- (uint8_t*)&fifo_status1, 1);
+ (uint8_t *)&fifo_status1, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
-
+ (uint8_t *)&fifo_status2, 1);
*val = (uint16_t)fifo_status2.diff_fifo << 8;
*val |= fifo_status1.diff_fifo;
}
+
return ret;
}
@@ -4258,7 +4909,7 @@ int32_t lsm6ds3_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
+ (uint8_t *)&fifo_status2, 1);
*val = (uint8_t)fifo_status2.fifo_empty;
return ret;
@@ -4278,7 +4929,7 @@ int32_t lsm6ds3_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
+ (uint8_t *)&fifo_status2, 1);
*val = (uint8_t)fifo_status2.fifo_full;
return ret;
@@ -4298,7 +4949,7 @@ int32_t lsm6ds3_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
+ (uint8_t *)&fifo_status2, 1);
*val = (uint8_t)fifo_status2.fth;
return ret;
@@ -4316,18 +4967,19 @@ int32_t lsm6ds3_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val)
{
lsm6ds3_fifo_status3_t fifo_status3;
lsm6ds3_fifo_status4_t fifo_status4;
-
int32_t ret;
ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_STATUS3,
- (uint8_t*)&fifo_status3, 1);
- if(ret == 0){
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_STATUS4,
- (uint8_t*)&fifo_status4, 1);
+ (uint8_t *)&fifo_status3, 1);
+ if (ret == 0)
+ {
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_STATUS4,
+ (uint8_t *)&fifo_status4, 1);
*val = (uint16_t)fifo_status4.fifo_pattern << 8;
*val |= fifo_status3.fifo_pattern;
}
+
return ret;
}
@@ -4352,17 +5004,20 @@ int32_t lsm6ds3_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_den_mode_set(stmdev_ctx_t *ctx, lsm6ds3_den_mode_t val)
+int32_t lsm6ds3_den_mode_set(stmdev_ctx_t *ctx,
+ lsm6ds3_den_mode_t val)
{
lsm6ds3_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ctrl6_c.den_mode = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -4374,34 +5029,41 @@ int32_t lsm6ds3_den_mode_set(stmdev_ctx_t *ctx, lsm6ds3_den_mode_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_den_mode_get(stmdev_ctx_t *ctx, lsm6ds3_den_mode_t *val)
+int32_t lsm6ds3_den_mode_get(stmdev_ctx_t *ctx,
+ lsm6ds3_den_mode_t *val)
{
lsm6ds3_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
switch (ctrl6_c.den_mode)
{
case LSM6DS3_DEN_DISABLE:
*val = LSM6DS3_DEN_DISABLE;
break;
+
case LSM6DS3_LEVEL_FIFO:
*val = LSM6DS3_LEVEL_FIFO;
break;
+
case LSM6DS3_LEVEL_LETCHED:
*val = LSM6DS3_LEVEL_LETCHED;
break;
+
case LSM6DS3_LEVEL_TRIGGER:
*val = LSM6DS3_LEVEL_TRIGGER;
break;
+
case LSM6DS3_EDGE_TRIGGER:
*val = LSM6DS3_EDGE_TRIGGER;
break;
+
default:
*val = LSM6DS3_DEN_DISABLE;
break;
}
+
return ret;
}
@@ -4430,11 +5092,14 @@ int32_t lsm6ds3_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
ctrl10_c.pedo_rst_step = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
}
+
return ret;
}
@@ -4451,7 +5116,7 @@ int32_t lsm6ds3_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
*val = (uint8_t)ctrl10_c.pedo_rst_step;
return ret;
@@ -4460,16 +5125,23 @@ int32_t lsm6ds3_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @brief Step counter timestamp information register (r). When a step is
* detected, the value of TIMESTAMP_REG register is copied in
- * STEP_TIMESTAMP_L..[get]
+ * STEP_TIMESTAMP_L.[get]
*
* @param ctx read / write interface definitions(ptr)
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_pedo_timestamp_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6ds3_pedo_timestamp_raw_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
+
ret = lsm6ds3_read_reg(ctx, LSM6DS3_STEP_TIMESTAMP_L, buff, 2);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
+
return ret;
}
@@ -4482,12 +5154,13 @@ int32_t lsm6ds3_pedo_timestamp_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_pedo_step_detect_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3_pedo_step_detect_flag_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3_func_src_t func_src;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FUNC_SRC, (uint8_t*)&func_src, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FUNC_SRC, (uint8_t *)&func_src, 1);
*val = (uint8_t)func_src.step_detected;
return ret;
@@ -4508,23 +5181,34 @@ int32_t lsm6ds3_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = 0;
- if (val == PROPERTY_ENABLE){
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
+
+ if (val == PROPERTY_ENABLE)
+ {
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
ctrl10_c.func_en = PROPERTY_ENABLE;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
}
}
- if(ret == 0){
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
- if(ret == 0){
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
tap_cfg.pedo_en = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -4541,7 +5225,7 @@ int32_t lsm6ds3_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1);
*val = (uint8_t)tap_cfg.pedo_en;
return ret;
@@ -4562,18 +5246,25 @@ int32_t lsm6ds3_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_read_reg(ctx, LSM6DS3_PEDO_THS_REG,
- (uint8_t*)&pedo_ths_reg, 1);
+ (uint8_t *)&pedo_ths_reg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
pedo_ths_reg.ths_min = (uint8_t)val;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_PEDO_THS_REG,
- (uint8_t*)&pedo_ths_reg, 1);
+ (uint8_t *)&pedo_ths_reg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK);
}
+
return ret;
}
@@ -4592,14 +5283,19 @@ int32_t lsm6ds3_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_read_reg(ctx, LSM6DS3_PEDO_THS_REG,
- (uint8_t*)&pedo_ths_reg, 1);
+ (uint8_t *)&pedo_ths_reg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK);
*val = (uint8_t)pedo_ths_reg.ths_min;
}
+
return ret;
}
@@ -4612,24 +5308,32 @@ int32_t lsm6ds3_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_pedo_full_scale_set(stmdev_ctx_t *ctx, lsm6ds3_pedo_fs_t val)
+int32_t lsm6ds3_pedo_full_scale_set(stmdev_ctx_t *ctx,
+ lsm6ds3_pedo_fs_t val)
{
lsm6ds3_pedo_ths_reg_t pedo_ths_reg;
int32_t ret;
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_read_reg(ctx, LSM6DS3_PEDO_THS_REG,
- (uint8_t*)&pedo_ths_reg, 1);
+ (uint8_t *)&pedo_ths_reg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
pedo_ths_reg.pedo_4g = (uint8_t)val;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_PEDO_THS_REG,
- (uint8_t*)&pedo_ths_reg, 1);
+ (uint8_t *)&pedo_ths_reg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK);
}
+
return ret;
}
@@ -4639,33 +5343,43 @@ int32_t lsm6ds3_pedo_full_scale_set(stmdev_ctx_t *ctx, lsm6ds3_pedo_fs_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of pedo_4g in reg PEDO_THS_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_pedo_full_scale_get(stmdev_ctx_t *ctx, lsm6ds3_pedo_fs_t *val)
+int32_t lsm6ds3_pedo_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6ds3_pedo_fs_t *val)
{
lsm6ds3_pedo_ths_reg_t pedo_ths_reg;
int32_t ret;
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_read_reg(ctx, LSM6DS3_PEDO_THS_REG,
- (uint8_t*)&pedo_ths_reg, 1);
+ (uint8_t *)&pedo_ths_reg, 1);
+
switch (pedo_ths_reg.pedo_4g)
{
case LSM6DS3_PEDO_AT_2g:
*val = LSM6DS3_PEDO_AT_2g;
break;
+
case LSM6DS3_PEDO_AT_4g:
*val = LSM6DS3_PEDO_AT_4g;
break;
+
default:
*val = LSM6DS3_PEDO_AT_2g;
break;
}
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK);
}
+
return ret;
}
@@ -4677,24 +5391,32 @@ int32_t lsm6ds3_pedo_full_scale_get(stmdev_ctx_t *ctx, lsm6ds3_pedo_fs_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6ds3_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6ds3_pedo_deb_reg_t pedo_deb_reg;
int32_t ret;
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_read_reg(ctx, LSM6DS3_PEDO_DEB_REG,
- (uint8_t*)&pedo_deb_reg, 1);
+ (uint8_t *)&pedo_deb_reg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
pedo_deb_reg.deb_step = (uint8_t)val;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_PEDO_DEB_REG,
- (uint8_t*)&pedo_deb_reg, 1);
+ (uint8_t *)&pedo_deb_reg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK);
}
+
return ret;
}
@@ -4706,20 +5428,26 @@ int32_t lsm6ds3_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3_pedo_deb_reg_t pedo_deb_reg;
int32_t ret;
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_read_reg(ctx, LSM6DS3_PEDO_DEB_REG,
- (uint8_t*)&pedo_deb_reg, 1);
+ (uint8_t *)&pedo_deb_reg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK);
*val = (uint8_t)pedo_deb_reg.deb_step;
}
+
return ret;
}
@@ -4738,18 +5466,25 @@ int32_t lsm6ds3_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_read_reg(ctx, LSM6DS3_PEDO_DEB_REG,
- (uint8_t*)&pedo_deb_reg, 1);
+ (uint8_t *)&pedo_deb_reg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
pedo_deb_reg.deb_time = (uint8_t)val;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_PEDO_DEB_REG,
- (uint8_t*)&pedo_deb_reg, 1);
+ (uint8_t *)&pedo_deb_reg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK);
}
+
return ret;
}
@@ -4768,14 +5503,19 @@ int32_t lsm6ds3_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_read_reg(ctx, LSM6DS3_PEDO_DEB_REG,
- (uint8_t*)&pedo_deb_reg, 1);
+ (uint8_t *)&pedo_deb_reg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = (uint8_t)pedo_deb_reg.deb_time;
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK);
}
+
return ret;
}
@@ -4805,14 +5545,20 @@ int32_t lsm6ds3_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
ctrl10_c.sign_motion_en = (uint8_t)val;
- if (val == PROPERTY_ENABLE){
+
+ if (val == PROPERTY_ENABLE)
+ {
ctrl10_c.func_en = PROPERTY_ENABLE;
}
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
}
+
return ret;
}
@@ -4829,7 +5575,7 @@ int32_t lsm6ds3_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
*val = (uint8_t)ctrl10_c.sign_motion_en;
return ret;
@@ -4849,7 +5595,7 @@ int32_t lsm6ds3_motion_event_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_func_src_t func_src;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FUNC_SRC, (uint8_t*)&func_src, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FUNC_SRC, (uint8_t *)&func_src, 1);
*val = (uint8_t)func_src.sign_motion_ia;
return ret;
@@ -4869,16 +5615,23 @@ int32_t lsm6ds3_motion_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK);
- if(ret == 0){
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_SM_THS, (uint8_t*)&sm_ths, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_SM_THS, (uint8_t *)&sm_ths, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
sm_ths.sm_ths = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_SM_THS, (uint8_t*)&sm_ths, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_SM_THS, (uint8_t *)&sm_ths, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK);
}
+
return ret;
}
@@ -4896,13 +5649,18 @@ int32_t lsm6ds3_motion_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK);
- if(ret == 0){
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_SM_THS, (uint8_t*)&sm_ths, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_SM_THS, (uint8_t *)&sm_ths, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK);
*val = (uint8_t)sm_ths.sm_ths;
}
+
return ret;
}
@@ -4921,18 +5679,25 @@ int32_t lsm6ds3_sc_delta_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_read_reg(ctx, LSM6DS3_STEP_COUNT_DELTA,
- (uint8_t*)& step_count_delta, 1);
+ (uint8_t *)& step_count_delta, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
step_count_delta.sc_delta = (uint8_t)val;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_STEP_COUNT_DELTA,
- (uint8_t*)& step_count_delta, 1);
+ (uint8_t *)& step_count_delta, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK);
}
+
return ret;
}
@@ -4951,14 +5716,19 @@ int32_t lsm6ds3_sc_delta_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_read_reg(ctx, LSM6DS3_STEP_COUNT_DELTA,
- (uint8_t*)& step_count_delta, 1);
+ (uint8_t *)& step_count_delta, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK);
*val = (uint8_t) step_count_delta.sc_delta;
}
+
return ret;
}
@@ -4988,7 +5758,7 @@ int32_t lsm6ds3_tilt_event_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_func_src_t func_src;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FUNC_SRC, (uint8_t*)&func_src, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FUNC_SRC, (uint8_t *)&func_src, 1);
*val = (uint8_t)func_src.tilt_ia;
return ret;
@@ -5009,20 +5779,29 @@ int32_t lsm6ds3_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = 0;
- if (val == PROPERTY_ENABLE){
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
+
+ if (val == PROPERTY_ENABLE)
+ {
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
ctrl10_c.func_en = PROPERTY_ENABLE;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
}
}
- if(ret == 0){
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
tap_cfg.tilt_en = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -5039,7 +5818,7 @@ int32_t lsm6ds3_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1);
*val = (uint8_t)tap_cfg.tilt_en;
return ret;
@@ -5073,20 +5852,29 @@ int32_t lsm6ds3_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = 0;
- if (val == PROPERTY_ENABLE){
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
+
+ if (val == PROPERTY_ENABLE)
+ {
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
ctrl10_c.func_en = PROPERTY_ENABLE;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
}
}
- if(ret == 0){
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ctrl9_xl.soft_en = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -5103,7 +5891,7 @@ int32_t lsm6ds3_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
*val = (uint8_t)ctrl9_xl.soft_en;
return ret;
@@ -5124,22 +5912,31 @@ int32_t lsm6ds3_mag_hard_iron_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = 0;
- if (val == PROPERTY_ENABLE){
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+
+ if (val == PROPERTY_ENABLE)
+ {
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
ctrl10_c.func_en = PROPERTY_ENABLE;
- if(ret == 0){
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
}
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
master_config.iron_en = (uint8_t)val;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
+
return ret;
}
@@ -5157,7 +5954,7 @@ int32_t lsm6ds3_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
*val = (uint8_t)master_config.iron_en;
return ret;
@@ -5172,12 +5969,12 @@ int32_t lsm6ds3_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6ds3_mag_soft_iron_end_op_flag_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
lsm6ds3_func_src_t func_src;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FUNC_SRC, (uint8_t*)&func_src, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FUNC_SRC, (uint8_t *)&func_src, 1);
*val = (uint8_t)func_src.si_end_op;
return ret;
@@ -5188,18 +5985,26 @@ int32_t lsm6ds3_mag_soft_iron_end_op_flag_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param buff buffer that stores data to be write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_mag_soft_iron_coeff_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6ds3_mag_soft_iron_coeff_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
+
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_write_reg(ctx, LSM6DS3_MAG_SI_XX, buff, 9);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK);
}
+
return ret;
}
@@ -5208,19 +6013,26 @@ int32_t lsm6ds3_mag_soft_iron_coeff_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions(ptr)
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_mag_soft_iron_coeff_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6ds3_mag_soft_iron_coeff_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_read_reg(ctx, LSM6DS3_MAG_SI_XX, buff, 9);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK);
}
+
return ret;
}
@@ -5230,19 +6042,32 @@ int32_t lsm6ds3_mag_soft_iron_coeff_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions(ptr)
* @param buff buffer that stores data to be write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_mag_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6ds3_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK);
- if(ret == 0){
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_MAG_OFFX_L, buff, 6);
+
+ if (ret == 0)
+ {
+ buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
+ buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
+ buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
+ buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
+ buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
+ buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_MAG_OFFX_L, buff, 6);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK);
}
+
return ret;
}
@@ -5252,19 +6077,32 @@ int32_t lsm6ds3_mag_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions(ptr)
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_mag_offset_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6ds3_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_read_reg(ctx, LSM6DS3_MAG_OFFX_L, buff, 6);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK);
}
+
return ret;
}
@@ -5296,12 +6134,15 @@ int32_t lsm6ds3_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6ds3_read_reg(ctx, LSM6DS3_SENSOR_SYNC_TIME_FRAME,
- (uint8_t*)& sensor_sync_time_frame, 1);
- if(ret == 0){
- sensor_sync_time_frame.tph = (uint8_t)val;
+ (uint8_t *)& sensor_sync_time_frame, 1);
+
+ if (ret == 0)
+ {
+ sensor_sync_time_frame.tph = (uint8_t)val;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_SENSOR_SYNC_TIME_FRAME,
- (uint8_t*)& sensor_sync_time_frame, 1);
+ (uint8_t *)& sensor_sync_time_frame, 1);
}
+
return ret;
}
@@ -5314,13 +6155,14 @@ int32_t lsm6ds3_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3_sh_sync_sens_frame_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3_sensor_sync_time_frame_t sensor_sync_time_frame;
int32_t ret;
ret = lsm6ds3_read_reg(ctx, LSM6DS3_SENSOR_SYNC_TIME_FRAME,
- (uint8_t*)& sensor_sync_time_frame, 1);
+ (uint8_t *)& sensor_sync_time_frame, 1);
*val = (uint8_t) sensor_sync_time_frame.tph;
return ret;
@@ -5340,22 +6182,31 @@ int32_t lsm6ds3_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = 0;
- if (val == PROPERTY_ENABLE){
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
+
+ if (val == PROPERTY_ENABLE)
+ {
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
ctrl10_c.func_en = PROPERTY_ENABLE;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
}
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
master_config.master_on = (uint8_t)val;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
+
return ret;
}
@@ -5373,7 +6224,7 @@ int32_t lsm6ds3_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
*val = (uint8_t)master_config.master_on;
return ret;
@@ -5393,12 +6244,15 @@ int32_t lsm6ds3_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
master_config.pass_through_mode = (uint8_t)val;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
+
return ret;
}
@@ -5416,7 +6270,7 @@ int32_t lsm6ds3_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
*val = (uint8_t)master_config.pass_through_mode;
return ret;
@@ -5429,18 +6283,22 @@ int32_t lsm6ds3_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_sh_pin_mode_set(stmdev_ctx_t *ctx, lsm6ds3_sh_pin_md_t val)
+int32_t lsm6ds3_sh_pin_mode_set(stmdev_ctx_t *ctx,
+ lsm6ds3_sh_pin_md_t val)
{
lsm6ds3_master_config_t master_config;
int32_t ret;
ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
master_config.pull_up_en = (uint8_t)val;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
+
return ret;
}
@@ -5449,28 +6307,33 @@ int32_t lsm6ds3_sh_pin_mode_set(stmdev_ctx_t *ctx, lsm6ds3_sh_pin_md_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of pull_up_en in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_sh_pin_mode_get(stmdev_ctx_t *ctx, lsm6ds3_sh_pin_md_t *val)
+int32_t lsm6ds3_sh_pin_mode_get(stmdev_ctx_t *ctx,
+ lsm6ds3_sh_pin_md_t *val)
{
lsm6ds3_master_config_t master_config;
int32_t ret;
ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
switch (master_config.pull_up_en)
{
case LSM6DS3_EXT_PULL_UP:
*val = LSM6DS3_EXT_PULL_UP;
break;
+
case LSM6DS3_INTERNAL_PULL_UP:
*val = LSM6DS3_INTERNAL_PULL_UP;
break;
+
default:
*val = LSM6DS3_EXT_PULL_UP;
break;
}
+
return ret;
}
@@ -5482,18 +6345,22 @@ int32_t lsm6ds3_sh_pin_mode_get(stmdev_ctx_t *ctx, lsm6ds3_sh_pin_md_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_sh_syncro_mode_set(stmdev_ctx_t *ctx, lsm6ds3_start_cfg_t val)
+int32_t lsm6ds3_sh_syncro_mode_set(stmdev_ctx_t *ctx,
+ lsm6ds3_start_cfg_t val)
{
lsm6ds3_master_config_t master_config;
int32_t ret;
ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
master_config.start_config = (uint8_t)val;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
+
return ret;
}
@@ -5502,6 +6369,7 @@ int32_t lsm6ds3_sh_syncro_mode_set(stmdev_ctx_t *ctx, lsm6ds3_start_cfg_t val)
*
* @param ctx read / write interface definitions(ptr)
* @param val get the values of start_config in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_sh_syncro_mode_get(stmdev_ctx_t *ctx,
@@ -5511,20 +6379,23 @@ int32_t lsm6ds3_sh_syncro_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
switch (master_config.start_config)
{
case LSM6DS3_XL_GY_DRDY:
*val = LSM6DS3_XL_GY_DRDY;
break;
+
case LSM6DS3_EXT_ON_INT2_PIN:
*val = LSM6DS3_EXT_ON_INT2_PIN;
break;
+
default:
*val = LSM6DS3_XL_GY_DRDY;
break;
}
+
return ret;
}
@@ -5533,19 +6404,23 @@ int32_t lsm6ds3_sh_syncro_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions(ptr)
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_sh_read_data_raw_get(stmdev_ctx_t *ctx,
lsm6ds3_sh_read_t *buff)
{
int32_t ret;
+
ret = lsm6ds3_read_reg(ctx, LSM6DS3_SENSORHUB1_REG,
- (uint8_t*)&(buff->sh_byte_1), 12);
+ (uint8_t *) & (buff->sh_byte_1), 12);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6ds3_read_reg(ctx, LSM6DS3_SENSORHUB13_REG,
- (uint8_t*)&(buff->sh_byte_13), 6);
+ (uint8_t *) & (buff->sh_byte_13), 6);
}
+
return ret;
}
@@ -5557,28 +6432,38 @@ int32_t lsm6ds3_sh_read_data_raw_get(stmdev_ctx_t *ctx,
* - uint8_t slv1_add; 8 bit i2c device address
* - uint8_t slv1_subadd; 8 bit register device address
* - uint8_t slv1_data; 8 bit data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3_sh_cfg_write(stmdev_ctx_t *ctx, lsm6ds3_sh_cfg_write_t *val)
+int32_t lsm6ds3_sh_cfg_write(stmdev_ctx_t *ctx,
+ lsm6ds3_sh_cfg_write_t *val)
{
lsm6ds3_slv0_add_t slv0_add;
int32_t ret;
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv0_add.slave0_add = val->slv0_add >> 1;
slv0_add.rw_0 = 0;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV0_ADD, (uint8_t*)&slv0_add, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV0_ADD, (uint8_t *)&slv0_add, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV0_SUBADD,
&(val->slv0_subadd), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_write_reg(ctx, LSM6DS3_DATAWRITE_SRC_MODE_SUB_SLV0,
&(val->slv0_data), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK);
}
@@ -5593,6 +6478,7 @@ int32_t lsm6ds3_sh_cfg_write(stmdev_ctx_t *ctx, lsm6ds3_sh_cfg_write_t *val)
* - uint8_t slv1_add; 8 bit i2c device address
* - uint8_t slv1_subadd; 8 bit register device address
* - uint8_t slv1_len; num of bit to read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
@@ -5603,27 +6489,38 @@ int32_t lsm6ds3_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv0_add.slave0_add = val->slv_add >> 1;
slv0_add.rw_0 = 1;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV0_ADD, (uint8_t*)&slv0_add, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV0_ADD, (uint8_t *)&slv0_add, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV0_SUBADD,
&(val->slv_subadd), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_read_reg(ctx, LSM6DS3_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
+ (uint8_t *)&slave0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
slave0_config.slave0_numop = val->slv_len;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
+ (uint8_t *)&slave0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK);
}
+
return ret;
}
@@ -5635,6 +6532,7 @@ int32_t lsm6ds3_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
* - uint8_t slv1_add; 8 bit i2c device address
* - uint8_t slv1_subadd; 8 bit register device address
* - uint8_t slv1_len; num of bit to read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
@@ -5645,25 +6543,38 @@ int32_t lsm6ds3_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv1_add.slave1_add = val->slv_add >> 1;;
slv1_add.r_1 = 1;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV1_ADD, (uint8_t*)&slv1_add, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV1_ADD, (uint8_t *)&slv1_add, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV1_SUBADD,
&(val->slv_subadd), 1);
}
- if(ret == 0){
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_SLAVE1_CONFIG, (uint8_t*)&slave1_config, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_SLAVE1_CONFIG,
+ (uint8_t *)&slave1_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
slave1_config.slave1_numop = val->slv_len;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLAVE1_CONFIG, (uint8_t*)&slave1_config, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLAVE1_CONFIG,
+ (uint8_t *)&slave1_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK);
}
+
return ret;
}
@@ -5675,6 +6586,7 @@ int32_t lsm6ds3_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
* - uint8_t slv2_add; 8 bit i2c device address
* - uint8_t slv2_subadd; 8 bit register device address
* - uint8_t slv2_len; num of bit to read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
@@ -5685,28 +6597,39 @@ int32_t lsm6ds3_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv2_add.slave2_add = val->slv_add >> 1;
slv2_add.r_2 = 1;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV2_ADD,
- (uint8_t*)&slv2_add, 1);
+ (uint8_t *)&slv2_add, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV2_SUBADD,
&(val->slv_subadd), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_read_reg(ctx, LSM6DS3_SLAVE2_CONFIG,
- (uint8_t*)&slave2_config, 1);
+ (uint8_t *)&slave2_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
slave2_config.slave2_numop = val->slv_len;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLAVE2_CONFIG,
- (uint8_t*)&slave2_config, 1);
+ (uint8_t *)&slave2_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK);
}
+
return ret;
}
@@ -5718,6 +6641,7 @@ int32_t lsm6ds3_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
* - uint8_t slv3_add; 8 bit i2c device address
* - uint8_t slv3_subadd; 8 bit register device address
* - uint8_t slv3_len; num of bit to read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
@@ -5728,27 +6652,38 @@ int32_t lsm6ds3_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv3_add.slave3_add = val->slv_add >> 1;
slv3_add.r_3 = 1;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV3_ADD, (uint8_t*)&slv3_add, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV3_ADD, (uint8_t *)&slv3_add, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV3_SUBADD,
&(val->slv_subadd), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_read_reg(ctx, LSM6DS3_SLAVE3_CONFIG,
- (uint8_t*)&slave3_config, 1);
+ (uint8_t *)&slave3_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
slave3_config.slave3_numop = val->slv_len;
ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLAVE3_CONFIG,
- (uint8_t*)&slave3_config, 1);
+ (uint8_t *)&slave3_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK);
}
+
return ret;
}
@@ -5765,7 +6700,7 @@ int32_t lsm6ds3_sh_end_op_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3_func_src_t func_src;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_FUNC_SRC, (uint8_t*)&func_src, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_FUNC_SRC, (uint8_t *)&func_src, 1);
*val = (uint8_t)func_src.sensor_hub_end_op;
return ret;
@@ -5778,6 +6713,7 @@ int32_t lsm6ds3_sh_end_op_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param stmdev_ctx_t *ctx: read / write interface definitions
* @param lsm6ds3_slope_fds_t: change the values of slope_fds in reg TAP_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
@@ -5786,11 +6722,14 @@ int32_t lsm6ds3_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
lsm6ds3_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- if(ret == 0){
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
tap_cfg.slope_fds = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -5801,6 +6740,7 @@ int32_t lsm6ds3_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
*
* @param stmdev_ctx_t *ctx: read / write interface definitions
* @param lsm6ds3_slope_fds_t: Get the values of slope_fds in reg TAP_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
@@ -5809,19 +6749,23 @@ int32_t lsm6ds3_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
lsm6ds3_tap_cfg_t reg;
int32_t ret;
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)®, 1);
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)®, 1);
+
switch (reg.slope_fds)
{
case LSM6DS3_USE_SLOPE:
*val = LSM6DS3_USE_SLOPE;
break;
+
case LSM6DS3_USE_HPF:
*val = LSM6DS3_USE_HPF;
break;
+
default:
*val = LSM6DS3_USE_SLOPE;
break;
}
+
return ret;
}
@@ -5832,6 +6776,7 @@ int32_t lsm6ds3_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
* @param stmdev_ctx_t *ctx: read / write interface definitions
* @param lsm6ds3_aux_sens_on_t: change the values of aux_sens_on in
* reg SLAVE0_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx,
@@ -5841,16 +6786,23 @@ int32_t lsm6ds3_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK);
- if(ret == 0){
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_SLAVE0_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_SLAVE0_CONFIG, (uint8_t *)®, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
reg.aux_sens_on = (uint8_t)val;
- ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLAVE0_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLAVE0_CONFIG, (uint8_t *)®, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK);
}
+
return ret;
}
@@ -5861,6 +6813,7 @@ int32_t lsm6ds3_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx,
* @param stmdev_ctx_t *ctx: read / write interface definitions
* @param lsm6ds3_aux_sens_on_t: Get the values of aux_sens_on in
* reg SLAVE0_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6ds3_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx,
@@ -5870,30 +6823,40 @@ int32_t lsm6ds3_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK);
- if(ret == 0){
- ret = lsm6ds3_read_reg(ctx, LSM6DS3_SLAVE0_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3_read_reg(ctx, LSM6DS3_SLAVE0_CONFIG, (uint8_t *)®, 1);
+
switch (reg.aux_sens_on)
{
case LSM6DS3_SLV_0:
*val = LSM6DS3_SLV_0;
break;
+
case LSM6DS3_SLV_0_1:
*val = LSM6DS3_SLV_0_1;
break;
+
case LSM6DS3_SLV_0_1_2:
*val = LSM6DS3_SLV_0_1_2;
break;
- case LSM6DS3_SLV_0_1_2_3:
+
+ case LSM6DS3_SLV_0_1_2_3:
*val = LSM6DS3_SLV_0_1_2_3;
break;
+
default:
*val = LSM6DS3_SLV_0;
break;
}
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK);
}
+
return ret;
}
diff --git a/sensor/stmemsc/lsm6ds3_STdC/driver/lsm6ds3_reg.h b/sensor/stmemsc/lsm6ds3_STdC/driver/lsm6ds3_reg.h
index 17e926a511df6368e167f7c515ada6861facce03..62538de38b71bfe84b99478b5a137bda33dd89c1 100644
--- a/sensor/stmemsc/lsm6ds3_STdC/driver/lsm6ds3_reg.h
+++ b/sensor/stmemsc/lsm6ds3_STdC/driver/lsm6ds3_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file lsm6ds3_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lsm6ds3_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lsm6ds3_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lsm6ds3_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LSM6DS3_REGS_H
#define LSM6DS3_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup LSM6DS3
@@ -35,6 +36,37 @@
*
*/
+/** @defgroup Endianness definitions
+ * @{
+ *
+ */
+
+#ifndef DRV_BYTE_ORDER
+#ifndef __BYTE_ORDER__
+
+#define DRV_LITTLE_ENDIAN 1234
+#define DRV_BIG_ENDIAN 4321
+
+/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
+ * by uncommenting the define which fits your platform endianness
+ */
+//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
+#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
+
+#else /* defined __BYTE_ORDER__ */
+
+#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
+#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
+#define DRV_BYTE_ORDER __BYTE_ORDER__
+
+#endif /* __BYTE_ORDER__*/
+#endif /* DRV_BYTE_ORDER */
+
+/**
+ * @}
+ *
+ */
+
/** @defgroup STMicroelectronics sensors common types
* @{
*
@@ -43,7 +75,9 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -52,6 +86,16 @@ typedef struct{
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} bitwise_t;
#define PROPERTY_DISABLE (0U)
@@ -65,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -89,15 +134,16 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
- * Unico / Unicleo tools available on STMicroelectronics
- * web site.
+ * You can create a sensor configuration by your own or using
+ * Unico / Unicleo tools available on STMicroelectronics
+ * web site.
*
* @{
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -131,60 +177,109 @@ typedef struct {
*/
#define LSM6DS3_FUNC_CFG_ACCESS 0x01U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 7;
uint8_t func_cfg_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t func_cfg_en : 1;
+ uint8_t not_used_01 : 7;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_func_cfg_access_t;
#define LSM6DS3_SENSOR_SYNC_TIME_FRAME 0x04U
-typedef struct {
+typedef struct
+{
uint8_t tph : 8;
} lsm6ds3_sensor_sync_time_frame_t;
#define LSM6DS3_FIFO_CTRL1 0x06U
-typedef struct {
+typedef struct
+{
uint8_t fth : 8;
} lsm6ds3_fifo_ctrl1_t;
#define LSM6DS3_FIFO_CTRL2 0x07U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fth : 4;
uint8_t not_used_01 : 2;
uint8_t timer_pedo_fifo_drdy : 1;
uint8_t timer_pedo_fifo_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t timer_pedo_fifo_en : 1;
+ uint8_t timer_pedo_fifo_drdy : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t fth : 4;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_fifo_ctrl2_t;
#define LSM6DS3_FIFO_CTRL3 0x08U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t dec_fifo_xl : 3;
uint8_t dec_fifo_gyro : 3;
uint8_t not_used_01 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 2;
+ uint8_t dec_fifo_gyro : 3;
+ uint8_t dec_fifo_xl : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_fifo_ctrl3_t;
#define LSM6DS3_FIFO_CTRL4 0x09U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t dec_ds3_fifo : 3;
uint8_t dec_ds4_fifo : 3;
uint8_t only_high_data : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t only_high_data : 1;
+ uint8_t dec_ds4_fifo : 3;
+ uint8_t dec_ds3_fifo : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_fifo_ctrl4_t;
#define LSM6DS3_FIFO_CTRL5 0x0AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fifo_mode : 3;
uint8_t odr_fifo : 4;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t odr_fifo : 4;
+ uint8_t fifo_mode : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_fifo_ctrl5_t;
#define LSM6DS3_ORIENT_CFG_G 0x0BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t orient : 3;
- uint8_t sign_g : 3; /* SignX_G) + SignY_G + SignZ_G */
+uint8_t sign_g :
+ 3; /* SignX_G) + SignY_G + SignZ_G */
uint8_t not_used_01 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 2;
+uint8_t sign_g :
+ 3; /* SignX_G) + SignY_G + SignZ_G */
+ uint8_t orient : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_orient_cfg_g_t;
#define LSM6DS3_INT1_CTRL 0x0DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_drdy_xl : 1;
uint8_t int1_drdy_g : 1;
uint8_t int1_boot : 1;
@@ -193,10 +288,22 @@ typedef struct {
uint8_t int1_full_flag : 1;
uint8_t int1_sign_mot : 1;
uint8_t int1_step_detector : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_step_detector : 1;
+ uint8_t int1_sign_mot : 1;
+ uint8_t int1_full_flag : 1;
+ uint8_t int1_fifo_ovr : 1;
+ uint8_t int1_fth : 1;
+ uint8_t int1_boot : 1;
+ uint8_t int1_drdy_g : 1;
+ uint8_t int1_drdy_xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_int1_ctrl_t;
#define LSM6DS3_INT2_CTRL 0x0EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_drdy_xl : 1;
uint8_t int2_drdy_g : 1;
uint8_t int2_drdy_temp : 1;
@@ -205,25 +312,51 @@ typedef struct {
uint8_t int2_full_flag : 1;
uint8_t int2_step_count_ov : 1;
uint8_t int2_step_delta : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_step_delta : 1;
+ uint8_t int2_step_count_ov : 1;
+ uint8_t int2_full_flag : 1;
+ uint8_t int2_fifo_ovr : 1;
+ uint8_t int2_fth : 1;
+ uint8_t int2_drdy_temp : 1;
+ uint8_t int2_drdy_g : 1;
+ uint8_t int2_drdy_xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_int2_ctrl_t;
#define LSM6DS3_WHO_AM_I 0x0FU
#define LSM6DS3_CTRL1_XL 0x10U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bw_xl : 2;
uint8_t fs_xl : 2;
uint8_t odr_xl : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr_xl : 4;
+ uint8_t fs_xl : 2;
+ uint8_t bw_xl : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_ctrl1_xl_t;
#define LSM6DS3_CTRL2_G 0x11U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t fs_g : 3; /* FS_G + FS_125 */
uint8_t odr_g : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr_g : 4;
+ uint8_t fs_g : 3; /* FS_G + FS_125 */
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_ctrl2_g_t;
#define LSM6DS3_CTRL3_C 0x12U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sw_reset : 1;
uint8_t ble : 1;
uint8_t if_inc : 1;
@@ -232,10 +365,22 @@ typedef struct {
uint8_t h_lactive : 1;
uint8_t bdu : 1;
uint8_t boot : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t boot : 1;
+ uint8_t bdu : 1;
+ uint8_t h_lactive : 1;
+ uint8_t pp_od : 1;
+ uint8_t sim : 1;
+ uint8_t if_inc : 1;
+ uint8_t ble : 1;
+ uint8_t sw_reset : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_ctrl3_c_t;
#define LSM6DS3_CTRL4_C 0x13U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t stop_on_fth : 1;
uint8_t not_used_01 : 1;
uint8_t i2c_disable : 1;
@@ -244,55 +389,114 @@ typedef struct {
uint8_t int2_on_int1 : 1;
uint8_t sleep_g : 1;
uint8_t xl_bw_scal_odr : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t xl_bw_scal_odr : 1;
+ uint8_t sleep_g : 1;
+ uint8_t int2_on_int1 : 1;
+ uint8_t fifo_temp_en : 1;
+ uint8_t drdy_mask : 1;
+ uint8_t i2c_disable : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t stop_on_fth : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_ctrl4_c_t;
#define LSM6DS3_CTRL5_C 0x14U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_xl : 2;
uint8_t st_g : 2;
uint8_t not_used_01 : 1;
uint8_t rounding : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t rounding : 3;
+ uint8_t not_used_01 : 1;
+ uint8_t st_g : 2;
+ uint8_t st_xl : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_ctrl5_c_t;
#define LSM6DS3_CTRL6_C 0x15U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 4;
uint8_t xl_hm_mode : 1;
- uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */
+uint8_t den_mode :
+ 3; /* trig_en + lvl1_en + lvl2_en */
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+uint8_t den_mode :
+ 3; /* trig_en + lvl1_en + lvl2_en */
+ uint8_t xl_hm_mode : 1;
+ uint8_t not_used_01 : 4;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_ctrl6_c_t;
#define LSM6DS3_CTRL7_G 0x16U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t rounding_status : 1;
uint8_t hpcf_g : 2;
uint8_t hp_g_rst : 1;
uint8_t hp_g_en : 1;
uint8_t g_hm_mode : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t g_hm_mode : 1;
+ uint8_t hp_g_en : 1;
+ uint8_t hp_g_rst : 1;
+ uint8_t hpcf_g : 2;
+ uint8_t rounding_status : 1;
+ uint8_t not_used_01 : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_ctrl7_g_t;
#define LSM6DS3_CTRL8_XL 0x17U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t low_pass_on_6d : 1;
uint8_t not_used_01 : 1;
uint8_t hp_slope_xl_en : 1;
uint8_t not_used_02 : 2;
uint8_t hpcf_xl : 2;
uint8_t lpf2_xl_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t lpf2_xl_en : 1;
+ uint8_t hpcf_xl : 2;
+ uint8_t not_used_02 : 2;
+ uint8_t hp_slope_xl_en : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t low_pass_on_6d : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_ctrl8_xl_t;
#define LSM6DS3_CTRL9_XL 0x18U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t soft_en : 1;
uint8_t xen_xl : 1;
uint8_t yen_xl : 1;
uint8_t zen_xl : 1;
uint8_t not_used_02 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 2;
+ uint8_t zen_xl : 1;
+ uint8_t yen_xl : 1;
+ uint8_t xen_xl : 1;
+ uint8_t soft_en : 1;
+ uint8_t not_used_01 : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_ctrl9_xl_t;
#define LSM6DS3_CTRL10_C 0x19U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sign_motion_en : 1;
uint8_t pedo_rst_step : 1;
uint8_t func_en : 1;
@@ -300,10 +504,21 @@ typedef struct {
uint8_t yen_g : 1;
uint8_t zen_g : 1;
uint8_t not_used_01 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 2;
+ uint8_t zen_g : 1;
+ uint8_t yen_g : 1;
+ uint8_t xen_g : 1;
+ uint8_t func_en : 1;
+ uint8_t pedo_rst_step : 1;
+ uint8_t sign_motion_en : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_ctrl10_c_t;
#define LSM6DS3_MASTER_CONFIG 0x1AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t master_on : 1;
uint8_t iron_en : 1;
uint8_t pass_through_mode : 1;
@@ -312,10 +527,22 @@ typedef struct {
uint8_t not_used_01 : 1;
uint8_t data_valid_sel_fifo : 1;
uint8_t drdy_on_int1 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t drdy_on_int1 : 1;
+ uint8_t data_valid_sel_fifo : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t start_config : 1;
+ uint8_t pull_up_en : 1;
+ uint8_t pass_through_mode : 1;
+ uint8_t iron_en : 1;
+ uint8_t master_on : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_master_config_t;
#define LSM6DS3_WAKE_UP_SRC 0x1BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_wu : 1;
uint8_t y_wu : 1;
uint8_t x_wu : 1;
@@ -323,10 +550,21 @@ typedef struct {
uint8_t sleep_state_ia : 1;
uint8_t ff_ia : 1;
uint8_t not_used_01 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 2;
+ uint8_t ff_ia : 1;
+ uint8_t sleep_state_ia : 1;
+ uint8_t wu_ia : 1;
+ uint8_t x_wu : 1;
+ uint8_t y_wu : 1;
+ uint8_t z_wu : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_wake_up_src_t;
#define LSM6DS3_TAP_SRC 0x1CU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_tap : 1;
uint8_t y_tap : 1;
uint8_t x_tap : 1;
@@ -335,10 +573,22 @@ typedef struct {
uint8_t single_tap : 1;
uint8_t tap_ia : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t tap_ia : 1;
+ uint8_t single_tap : 1;
+ uint8_t double_tap : 1;
+ uint8_t tap_sign : 1;
+ uint8_t x_tap : 1;
+ uint8_t y_tap : 1;
+ uint8_t z_tap : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_tap_src_t;
#define LSM6DS3_D6D_SRC 0x1DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
uint8_t yl : 1;
@@ -347,14 +597,32 @@ typedef struct {
uint8_t zh : 1;
uint8_t d6d_ia : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t d6d_ia : 1;
+ uint8_t zh : 1;
+ uint8_t zl : 1;
+ uint8_t yh : 1;
+ uint8_t yl : 1;
+ uint8_t xh : 1;
+ uint8_t xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_d6d_src_t;
#define LSM6DS3_STATUS_REG 0x1EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlda : 1;
uint8_t gda : 1;
uint8_t tda : 1;
uint8_t not_used_01 : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 5;
+ uint8_t tda : 1;
+ uint8_t gda : 1;
+ uint8_t xlda : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_status_reg_t;
#define LSM6DS3_OUT_TEMP_L 0x20U
@@ -372,7 +640,9 @@ typedef struct {
#define LSM6DS3_OUTZ_L_XL 0x2CU
#define LSM6DS3_OUTZ_H_XL 0x2DU
#define LSM6DS3_SENSORHUB1_REG 0x2EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shub1_0 : 1;
uint8_t shub1_1 : 1;
uint8_t shub1_2 : 1;
@@ -381,10 +651,22 @@ typedef struct {
uint8_t shub1_5 : 1;
uint8_t shub1_6 : 1;
uint8_t shub1_7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t shub1_7 : 1;
+ uint8_t shub1_6 : 1;
+ uint8_t shub1_5 : 1;
+ uint8_t shub1_4 : 1;
+ uint8_t shub1_3 : 1;
+ uint8_t shub1_2 : 1;
+ uint8_t shub1_1 : 1;
+ uint8_t shub1_0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_sensorhub1_reg_t;
#define LSM6DS3_SENSORHUB2_REG 0x2FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shub2_0 : 1;
uint8_t shub2_1 : 1;
uint8_t shub2_2 : 1;
@@ -393,10 +675,23 @@ typedef struct {
uint8_t shub2_5 : 1;
uint8_t shub2_6 : 1;
uint8_t shub2_7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t shub2_7 : 1;
+ uint8_t shub2_6 : 1;
+ uint8_t shub2_5 : 1;
+ uint8_t shub2_4 : 1;
+ uint8_t shub2_3 : 1;
+ uint8_t shub2_2 : 1;
+ uint8_t shub2_1 : 1;
+ uint8_t shub2_0 : 1;
+#endif /* DRV_BYTE_ORDER */
+
} lsm6ds3_sensorhub2_reg_t;
#define LSM6DS3_SENSORHUB3_REG 0x30U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shub3_0 : 1;
uint8_t shub3_1 : 1;
uint8_t shub3_2 : 1;
@@ -405,10 +700,23 @@ typedef struct {
uint8_t shub3_5 : 1;
uint8_t shub3_6 : 1;
uint8_t shub3_7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t shub3_7 : 1;
+ uint8_t shub3_6 : 1;
+ uint8_t shub3_5 : 1;
+ uint8_t shub3_4 : 1;
+ uint8_t shub3_3 : 1;
+ uint8_t shub3_2 : 1;
+ uint8_t shub3_1 : 1;
+ uint8_t shub3_0 : 1;
+#endif /* DRV_BYTE_ORDER */
+
} lsm6ds3_sensorhub3_reg_t;
#define LSM6DS3_SENSORHUB4_REG 0x31U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shub4_0 : 1;
uint8_t shub4_1 : 1;
uint8_t shub4_2 : 1;
@@ -417,10 +725,23 @@ typedef struct {
uint8_t shub4_5 : 1;
uint8_t shub4_6 : 1;
uint8_t shub4_7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t shub4_7 : 1;
+ uint8_t shub4_6 : 1;
+ uint8_t shub4_5 : 1;
+ uint8_t shub4_4 : 1;
+ uint8_t shub4_3 : 1;
+ uint8_t shub4_2 : 1;
+ uint8_t shub4_1 : 1;
+ uint8_t shub4_0 : 1;
+#endif /* DRV_BYTE_ORDER */
+
} lsm6ds3_sensorhub4_reg_t;
#define LSM6DS3_SENSORHUB5_REG 0x32U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shub5_0 : 1;
uint8_t shub5_1 : 1;
uint8_t shub5_2 : 1;
@@ -429,10 +750,22 @@ typedef struct {
uint8_t shub5_5 : 1;
uint8_t shub5_6 : 1;
uint8_t shub5_7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t shub5_7 : 1;
+ uint8_t shub5_6 : 1;
+ uint8_t shub5_5 : 1;
+ uint8_t shub5_4 : 1;
+ uint8_t shub5_3 : 1;
+ uint8_t shub5_2 : 1;
+ uint8_t shub5_1 : 1;
+ uint8_t shub5_0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_sensorhub5_reg_t;
#define LSM6DS3_SENSORHUB6_REG 0x33U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shub6_0 : 1;
uint8_t shub6_1 : 1;
uint8_t shub6_2 : 1;
@@ -441,10 +774,22 @@ typedef struct {
uint8_t shub6_5 : 1;
uint8_t shub6_6 : 1;
uint8_t shub6_7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t shub6_7 : 1;
+ uint8_t shub6_6 : 1;
+ uint8_t shub6_5 : 1;
+ uint8_t shub6_4 : 1;
+ uint8_t shub6_3 : 1;
+ uint8_t shub6_2 : 1;
+ uint8_t shub6_1 : 1;
+ uint8_t shub6_0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_sensorhub6_reg_t;
#define LSM6DS3_SENSORHUB7_REG 0x34U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shub7_0 : 1;
uint8_t shub7_1 : 1;
uint8_t shub7_2 : 1;
@@ -453,10 +798,22 @@ typedef struct {
uint8_t shub7_5 : 1;
uint8_t shub7_6 : 1;
uint8_t shub7_7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t shub7_7 : 1;
+ uint8_t shub7_6 : 1;
+ uint8_t shub7_5 : 1;
+ uint8_t shub7_4 : 1;
+ uint8_t shub7_3 : 1;
+ uint8_t shub7_2 : 1;
+ uint8_t shub7_1 : 1;
+ uint8_t shub7_0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_sensorhub7_reg_t;
#define LSM6DS3_SENSORHUB8_REG 0x35U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shub8_0 : 1;
uint8_t shub8_1 : 1;
uint8_t shub8_2 : 1;
@@ -465,10 +822,22 @@ typedef struct {
uint8_t shub8_5 : 1;
uint8_t shub8_6 : 1;
uint8_t shub8_7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t shub8_7 : 1;
+ uint8_t shub8_6 : 1;
+ uint8_t shub8_5 : 1;
+ uint8_t shub8_4 : 1;
+ uint8_t shub8_3 : 1;
+ uint8_t shub8_2 : 1;
+ uint8_t shub8_1 : 1;
+ uint8_t shub8_0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_sensorhub8_reg_t;
#define LSM6DS3_SENSORHUB9_REG 0x36U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shub9_0 : 1;
uint8_t shub9_1 : 1;
uint8_t shub9_2 : 1;
@@ -477,10 +846,22 @@ typedef struct {
uint8_t shub9_5 : 1;
uint8_t shub9_6 : 1;
uint8_t shub9_7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t shub9_7 : 1;
+ uint8_t shub9_6 : 1;
+ uint8_t shub9_5 : 1;
+ uint8_t shub9_4 : 1;
+ uint8_t shub9_3 : 1;
+ uint8_t shub9_2 : 1;
+ uint8_t shub9_1 : 1;
+ uint8_t shub9_0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_sensorhub9_reg_t;
#define LSM6DS3_SENSORHUB10_REG 0x37U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shub10_0 : 1;
uint8_t shub10_1 : 1;
uint8_t shub10_2 : 1;
@@ -489,10 +870,22 @@ typedef struct {
uint8_t shub10_5 : 1;
uint8_t shub10_6 : 1;
uint8_t shub10_7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t shub10_7 : 1;
+ uint8_t shub10_6 : 1;
+ uint8_t shub10_5 : 1;
+ uint8_t shub10_4 : 1;
+ uint8_t shub10_3 : 1;
+ uint8_t shub10_2 : 1;
+ uint8_t shub10_1 : 1;
+ uint8_t shub10_0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_sensorhub10_reg_t;
#define LSM6DS3_SENSORHUB11_REG 0x38U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shub11_0 : 1;
uint8_t shub11_1 : 1;
uint8_t shub11_2 : 1;
@@ -501,10 +894,22 @@ typedef struct {
uint8_t shub11_5 : 1;
uint8_t shub11_6 : 1;
uint8_t shub11_7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t shub11_7 : 1;
+ uint8_t shub11_6 : 1;
+ uint8_t shub11_5 : 1;
+ uint8_t shub11_4 : 1;
+ uint8_t shub11_3 : 1;
+ uint8_t shub11_2 : 1;
+ uint8_t shub11_1 : 1;
+ uint8_t shub11_0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_sensorhub11_reg_t;
#define LSM6DS3_SENSORHUB12_REG 0x39U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shub12_0 : 1;
uint8_t shub12_1 : 1;
uint8_t shub12_2 : 1;
@@ -513,31 +918,58 @@ typedef struct {
uint8_t shub12_5 : 1;
uint8_t shub12_6 : 1;
uint8_t shub12_7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t shub12_7 : 1;
+ uint8_t shub12_6 : 1;
+ uint8_t shub12_5 : 1;
+ uint8_t shub12_4 : 1;
+ uint8_t shub12_3 : 1;
+ uint8_t shub12_2 : 1;
+ uint8_t shub12_1 : 1;
+ uint8_t shub12_0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_sensorhub12_reg_t;
#define LSM6DS3_FIFO_STATUS1 0x3AU
-typedef struct {
+typedef struct
+{
uint8_t diff_fifo : 8;
} lsm6ds3_fifo_status1_t;
#define LSM6DS3_FIFO_STATUS2 0x3BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t diff_fifo : 4;
uint8_t fifo_empty : 1;
uint8_t fifo_full : 1;
uint8_t fifo_over_run : 1;
uint8_t fth : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fth : 1;
+ uint8_t fifo_over_run : 1;
+ uint8_t fifo_full : 1;
+ uint8_t fifo_empty : 1;
+ uint8_t diff_fifo : 4;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_fifo_status2_t;
#define LSM6DS3_FIFO_STATUS3 0x3CU
-typedef struct {
+typedef struct
+{
uint8_t fifo_pattern : 8;
} lsm6ds3_fifo_status3_t;
#define LSM6DS3_FIFO_STATUS4 0x3DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fifo_pattern : 2;
uint8_t not_used_01 : 6;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 6;
+ uint8_t fifo_pattern : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_fifo_status4_t;
#define LSM6DS3_FIFO_DATA_OUT_L 0x3EU
@@ -550,7 +982,9 @@ typedef struct {
#define LSM6DS3_STEP_COUNTER_L 0x4BU
#define LSM6DS3_STEP_COUNTER_H 0x4CU
#define LSM6DS3_SENSORHUB13_REG 0x4DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shub13_0 : 1;
uint8_t shub13_1 : 1;
uint8_t shub13_2 : 1;
@@ -559,10 +993,22 @@ typedef struct {
uint8_t shub13_5 : 1;
uint8_t shub13_6 : 1;
uint8_t shub13_7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t shub13_7 : 1;
+ uint8_t shub13_6 : 1;
+ uint8_t shub13_5 : 1;
+ uint8_t shub13_4 : 1;
+ uint8_t shub13_3 : 1;
+ uint8_t shub13_2 : 1;
+ uint8_t shub13_1 : 1;
+ uint8_t shub13_0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_sensorhub13_reg_t;
#define LSM6DS3_SENSORHUB14_REG 0x4EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shub14_0 : 1;
uint8_t shub14_1 : 1;
uint8_t shub14_2 : 1;
@@ -571,10 +1017,22 @@ typedef struct {
uint8_t shub14_5 : 1;
uint8_t shub14_6 : 1;
uint8_t shub14_7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t shub14_7 : 1;
+ uint8_t shub14_6 : 1;
+ uint8_t shub14_5 : 1;
+ uint8_t shub14_4 : 1;
+ uint8_t shub14_3 : 1;
+ uint8_t shub14_2 : 1;
+ uint8_t shub14_1 : 1;
+ uint8_t shub14_0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_sensorhub14_reg_t;
#define LSM6DS3_SENSORHUB15_REG 0x4FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shub15_0 : 1;
uint8_t shub15_1 : 1;
uint8_t shub15_2 : 1;
@@ -583,10 +1041,22 @@ typedef struct {
uint8_t shub15_5 : 1;
uint8_t shub15_6 : 1;
uint8_t shub15_7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t shub15_7 : 1;
+ uint8_t shub15_6 : 1;
+ uint8_t shub15_5 : 1;
+ uint8_t shub15_4 : 1;
+ uint8_t shub15_3 : 1;
+ uint8_t shub15_2 : 1;
+ uint8_t shub15_1 : 1;
+ uint8_t shub15_0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_sensorhub15_reg_t;
#define LSM6DS3_SENSORHUB16_REG 0x50U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shub16_0 : 1;
uint8_t shub16_1 : 1;
uint8_t shub16_2 : 1;
@@ -595,10 +1065,22 @@ typedef struct {
uint8_t shub16_5 : 1;
uint8_t shub16_6 : 1;
uint8_t shub16_7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t shub16_7 : 1;
+ uint8_t shub16_6 : 1;
+ uint8_t shub16_5 : 1;
+ uint8_t shub16_4 : 1;
+ uint8_t shub16_3 : 1;
+ uint8_t shub16_2 : 1;
+ uint8_t shub16_1 : 1;
+ uint8_t shub16_0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_sensorhub16_reg_t;
#define LSM6DS3_SENSORHUB17_REG 0x51U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shub17_0 : 1;
uint8_t shub17_1 : 1;
uint8_t shub17_2 : 1;
@@ -607,10 +1089,22 @@ typedef struct {
uint8_t shub17_5 : 1;
uint8_t shub17_6 : 1;
uint8_t shub17_7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t shub17_7 : 1;
+ uint8_t shub17_6 : 1;
+ uint8_t shub17_5 : 1;
+ uint8_t shub17_4 : 1;
+ uint8_t shub17_3 : 1;
+ uint8_t shub17_2 : 1;
+ uint8_t shub17_1 : 1;
+ uint8_t shub17_0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_sensorhub17_reg_t;
#define LSM6DS3_SENSORHUB18_REG 0x52U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shub18_0 : 1;
uint8_t shub18_1 : 1;
uint8_t shub18_2 : 1;
@@ -619,10 +1113,22 @@ typedef struct {
uint8_t shub18_5 : 1;
uint8_t shub18_6 : 1;
uint8_t shub18_7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t shub18_7 : 1;
+ uint8_t shub18_6 : 1;
+ uint8_t shub18_5 : 1;
+ uint8_t shub18_4 : 1;
+ uint8_t shub18_3 : 1;
+ uint8_t shub18_2 : 1;
+ uint8_t shub18_1 : 1;
+ uint8_t shub18_0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_sensorhub18_reg_t;
#define LSM6DS3_FUNC_SRC 0x53U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sensor_hub_end_op : 1;
uint8_t si_end_op : 1;
uint8_t not_used_01 : 1;
@@ -631,10 +1137,22 @@ typedef struct {
uint8_t tilt_ia : 1;
uint8_t sign_motion_ia : 1;
uint8_t step_count_delta_ia : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t step_count_delta_ia : 1;
+ uint8_t sign_motion_ia : 1;
+ uint8_t tilt_ia : 1;
+ uint8_t step_detected : 1;
+ uint8_t step_overflow : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t si_end_op : 1;
+ uint8_t sensor_hub_end_op : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_func_src_t;
#define LSM6DS3_TAP_CFG 0x58U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lir : 1;
uint8_t tap_z_en : 1;
uint8_t tap_y_en : 1;
@@ -643,45 +1161,92 @@ typedef struct {
uint8_t tilt_en : 1;
uint8_t pedo_en : 1;
uint8_t timer_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t timer_en : 1;
+ uint8_t pedo_en : 1;
+ uint8_t tilt_en : 1;
+ uint8_t slope_fds : 1;
+ uint8_t tap_x_en : 1;
+ uint8_t tap_y_en : 1;
+ uint8_t tap_z_en : 1;
+ uint8_t lir : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_tap_cfg_t;
#define LSM6DS3_TAP_THS_6D 0x59U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_ths : 5;
uint8_t sixd_ths : 2;
uint8_t d4d_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t d4d_en : 1;
+ uint8_t sixd_ths : 2;
+ uint8_t tap_ths : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_tap_ths_6d_t;
#define LSM6DS3_INT_DUR2 0x5AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shock : 2;
uint8_t quiet : 2;
uint8_t dur : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t dur : 4;
+ uint8_t quiet : 2;
+ uint8_t shock : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_int_dur2_t;
#define LSM6DS3_WAKE_UP_THS 0x5BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wk_ths : 6;
uint8_t inactivity : 1;
uint8_t single_double_tap : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t single_double_tap : 1;
+ uint8_t inactivity : 1;
+ uint8_t wk_ths : 6;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_wake_up_ths_t;
#define LSM6DS3_WAKE_UP_DUR 0x5CU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sleep_dur : 4;
uint8_t timer_hr : 1;
uint8_t wake_dur : 2;
uint8_t ff_dur : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t ff_dur : 1;
+ uint8_t wake_dur : 2;
+ uint8_t timer_hr : 1;
+ uint8_t sleep_dur : 4;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_wake_up_dur_t;
#define LSM6DS3_FREE_FALL 0x5DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ths : 3;
uint8_t ff_dur : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t ff_dur : 5;
+ uint8_t ff_ths : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_free_fall_t;
#define LSM6DS3_MD1_CFG 0x5EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_timer : 1;
uint8_t int1_tilt : 1;
uint8_t int1_6d : 1;
@@ -690,10 +1255,22 @@ typedef struct {
uint8_t int1_wu : 1;
uint8_t int1_single_tap : 1;
uint8_t int1_inact_state : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_inact_state : 1;
+ uint8_t int1_single_tap : 1;
+ uint8_t int1_wu : 1;
+ uint8_t int1_ff : 1;
+ uint8_t int1_double_tap : 1;
+ uint8_t int1_6d : 1;
+ uint8_t int1_tilt : 1;
+ uint8_t int1_timer : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_md1_cfg_t;
#define LSM6DS3_MD2_CFG 0x5FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_iron : 1;
uint8_t int2_tilt : 1;
uint8_t int2_6d : 1;
@@ -702,6 +1279,16 @@ typedef struct {
uint8_t int2_wu : 1;
uint8_t int2_single_tap : 1;
uint8_t int2_inact_state : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_inact_state : 1;
+ uint8_t int2_single_tap : 1;
+ uint8_t int2_wu : 1;
+ uint8_t int2_ff : 1;
+ uint8_t int2_double_tap : 1;
+ uint8_t int2_6d : 1;
+ uint8_t int2_tilt : 1;
+ uint8_t int2_iron : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_md2_cfg_t;
#define LSM6DS3_OUT_MAG_RAW_X_L 0x66U
@@ -711,103 +1298,176 @@ typedef struct {
#define LSM6DS3_OUT_MAG_RAW_Z_L 0x6AU
#define LSM6DS3_OUT_MAG_RAW_Z_H 0x6BU
#define LSM6DS3_SLV0_ADD 0x02U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t rw_0 : 1;
uint8_t slave0_add : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave0_add : 7;
+ uint8_t rw_0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_slv0_add_t;
#define LSM6DS3_SLV0_SUBADD 0x03U
-typedef struct {
+typedef struct
+{
uint8_t slave0_reg : 8;
} lsm6ds3_slv0_subadd_t;
#define LSM6DS3_SLAVE0_CONFIG 0x04U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave0_numop : 3;
uint8_t src_mode : 1;
uint8_t aux_sens_on : 2;
uint8_t slave0_rate : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave0_rate : 2;
+ uint8_t aux_sens_on : 2;
+ uint8_t src_mode : 1;
+ uint8_t slave0_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_slave0_config_t;
#define LSM6DS3_SLV1_ADD 0x05U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_1 : 1;
uint8_t slave1_add : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave1_add : 7;
+ uint8_t r_1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_slv1_add_t;
#define LSM6DS3_SLV1_SUBADD 0x06U
-typedef struct {
+typedef struct
+{
uint8_t slave1_reg : 8;
} lsm6ds3_slv1_subadd_t;
#define LSM6DS3_SLAVE1_CONFIG 0x07U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave1_numop : 3;
uint8_t not_used_01 : 3;
uint8_t slave1_rate : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave1_rate : 2;
+ uint8_t not_used_01 : 3;
+ uint8_t slave1_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_slave1_config_t;
#define LSM6DS3_SLV2_ADD 0x08U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_2 : 1;
uint8_t slave2_add : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave2_add : 7;
+ uint8_t r_2 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_slv2_add_t;
#define LSM6DS3_SLV2_SUBADD 0x09U
-typedef struct {
+typedef struct
+{
uint8_t slave2_reg : 8;
} lsm6ds3_slv2_subadd_t;
#define LSM6DS3_SLAVE2_CONFIG 0x0AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave2_numop : 3;
uint8_t not_used_01 : 3;
uint8_t slave2_rate : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave2_rate : 2;
+ uint8_t not_used_01 : 3;
+ uint8_t slave2_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_slave2_config_t;
#define LSM6DS3_SLV3_ADD 0x0BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_3 : 1;
uint8_t slave3_add : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave3_add : 7;
+ uint8_t r_3 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_slv3_add_t;
#define LSM6DS3_SLV3_SUBADD 0x0CU
-typedef struct {
+typedef struct
+{
uint8_t slave3_reg : 8;
} lsm6ds3_slv3_subadd_t;
#define LSM6DS3_SLAVE3_CONFIG 0x0DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave3_numop : 3;
uint8_t not_used_01 : 3;
uint8_t slave3_rate : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave3_rate : 2;
+ uint8_t not_used_01 : 3;
+ uint8_t slave3_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_slave3_config_t;
#define LSM6DS3_DATAWRITE_SRC_MODE_SUB_SLV0 0x0EU
-typedef struct {
+typedef struct
+{
uint8_t slave_dataw : 8;
} lsm6ds3_datawrite_src_mode_sub_slv0_t;
#define LSM6DS3_PEDO_THS_REG 0x0FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths_min : 5;
uint8_t not_used_01 : 2;
uint8_t pedo_4g : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t pedo_4g : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t ths_min : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_pedo_ths_reg_t;
#define LSM6DS3_SM_THS 0x13U
-typedef struct {
+typedef struct
+{
uint8_t sm_ths : 8;
} lsm6ds3_sm_ths_t;
#define LSM6DS3_PEDO_DEB_REG 0x14U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t deb_step : 3;
uint8_t deb_time : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t deb_time : 5;
+ uint8_t deb_step : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3_pedo_deb_reg_t;
#define LSM6DS3_STEP_COUNT_DELTA 0x15U
-typedef struct {
+typedef struct
+{
uint8_t sc_delta : 8;
} lsm6ds3_step_count_delta_t;
@@ -829,9 +1489,9 @@ typedef struct {
/**
* @defgroup LSM6DS3_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -840,7 +1500,8 @@ typedef struct {
*
*/
-typedef union{
+typedef union
+{
lsm6ds3_func_cfg_access_t func_cfg_access;
lsm6ds3_sensor_sync_time_frame_t sensor_sync_time_frame;
lsm6ds3_fifo_ctrl1_t fifo_ctrl1;
@@ -909,7 +1570,8 @@ typedef union{
lsm6ds3_slv3_add_t slv3_add;
lsm6ds3_slv3_subadd_t slv3_subadd;
lsm6ds3_slave3_config_t slave3_config;
- lsm6ds3_datawrite_src_mode_sub_slv0_t datawrite_src_mode_sub_slv0;
+ lsm6ds3_datawrite_src_mode_sub_slv0_t
+ datawrite_src_mode_sub_slv0;
lsm6ds3_pedo_ths_reg_t pedo_ths_reg;
lsm6ds3_sm_ths_t sm_ths;
lsm6ds3_pedo_deb_reg_t pedo_deb_reg;
@@ -923,25 +1585,28 @@ typedef union{
*
*/
-int32_t lsm6ds3_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lsm6ds3_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t lsm6ds3_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lsm6ds3_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-extern float_t lsm6ds3_from_fs2g_to_mg(int16_t lsb);
-extern float_t lsm6ds3_from_fs4g_to_mg(int16_t lsb);
-extern float_t lsm6ds3_from_fs8g_to_mg(int16_t lsb);
-extern float_t lsm6ds3_from_fs16g_to_mg(int16_t lsb);
+float_t lsm6ds3_from_fs2g_to_mg(int16_t lsb);
+float_t lsm6ds3_from_fs4g_to_mg(int16_t lsb);
+float_t lsm6ds3_from_fs8g_to_mg(int16_t lsb);
+float_t lsm6ds3_from_fs16g_to_mg(int16_t lsb);
-extern float_t lsm6ds3_from_fs125dps_to_mdps(int16_t lsb);
-extern float_t lsm6ds3_from_fs250dps_to_mdps(int16_t lsb);
-extern float_t lsm6ds3_from_fs500dps_to_mdps(int16_t lsb);
-extern float_t lsm6ds3_from_fs1000dps_to_mdps(int16_t lsb);
-extern float_t lsm6ds3_from_fs2000dps_to_mdps(int16_t lsb);
+float_t lsm6ds3_from_fs125dps_to_mdps(int16_t lsb);
+float_t lsm6ds3_from_fs250dps_to_mdps(int16_t lsb);
+float_t lsm6ds3_from_fs500dps_to_mdps(int16_t lsb);
+float_t lsm6ds3_from_fs1000dps_to_mdps(int16_t lsb);
+float_t lsm6ds3_from_fs2000dps_to_mdps(int16_t lsb);
-extern float_t lsm6ds3_from_lsb_to_celsius(int16_t lsb);
+float_t lsm6ds3_from_lsb_to_celsius(int16_t lsb);
-typedef enum {
+typedef enum
+{
LSM6DS3_GY_ORIENT_XYZ = 0,
LSM6DS3_GY_ORIENT_XZY = 1,
LSM6DS3_GY_ORIENT_YXZ = 2,
@@ -954,7 +1619,8 @@ int32_t lsm6ds3_gy_data_orient_set(stmdev_ctx_t *ctx,
int32_t lsm6ds3_gy_data_orient_get(stmdev_ctx_t *ctx,
lsm6ds3_gy_orient_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_GY_SIGN_PPP = 0,
LSM6DS3_GY_SIGN_PPN = 1,
LSM6DS3_GY_SIGN_PNP = 2,
@@ -964,19 +1630,25 @@ typedef enum {
LSM6DS3_GY_SIGN_PNN = 3,
LSM6DS3_GY_SIGN_NNN = 7,
} lsm6ds3_gy_sgn_t;
-int32_t lsm6ds3_gy_data_sign_set(stmdev_ctx_t *ctx, lsm6ds3_gy_sgn_t val);
-int32_t lsm6ds3_gy_data_sign_get(stmdev_ctx_t *ctx, lsm6ds3_gy_sgn_t *val);
+int32_t lsm6ds3_gy_data_sign_set(stmdev_ctx_t *ctx,
+ lsm6ds3_gy_sgn_t val);
+int32_t lsm6ds3_gy_data_sign_get(stmdev_ctx_t *ctx,
+ lsm6ds3_gy_sgn_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_2g = 0,
LSM6DS3_16g = 1,
LSM6DS3_4g = 2,
LSM6DS3_8g = 3,
} lsm6ds3_xl_fs_t;
-int32_t lsm6ds3_xl_full_scale_set(stmdev_ctx_t *ctx, lsm6ds3_xl_fs_t val);
-int32_t lsm6ds3_xl_full_scale_get(stmdev_ctx_t *ctx, lsm6ds3_xl_fs_t *val);
+int32_t lsm6ds3_xl_full_scale_set(stmdev_ctx_t *ctx,
+ lsm6ds3_xl_fs_t val);
+int32_t lsm6ds3_xl_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6ds3_xl_fs_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_XL_ODR_OFF = 0,
LSM6DS3_XL_ODR_12Hz5 = 1,
LSM6DS3_XL_ODR_26Hz = 2,
@@ -989,20 +1661,26 @@ typedef enum {
LSM6DS3_XL_ODR_3k33Hz = 9,
LSM6DS3_XL_ODR_6k66Hz = 10,
} lsm6ds3_odr_xl_t;
-int32_t lsm6ds3_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6ds3_odr_xl_t val);
-int32_t lsm6ds3_xl_data_rate_get(stmdev_ctx_t *ctx, lsm6ds3_odr_xl_t *val);
+int32_t lsm6ds3_xl_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6ds3_odr_xl_t val);
+int32_t lsm6ds3_xl_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6ds3_odr_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_250dps = 0,
LSM6DS3_125dps = 1,
LSM6DS3_500dps = 2,
LSM6DS3_1000dps = 4,
LSM6DS3_2000dps = 6,
} lsm6ds3_fs_g_t;
-int32_t lsm6ds3_gy_full_scale_set(stmdev_ctx_t *ctx, lsm6ds3_fs_g_t val);
-int32_t lsm6ds3_gy_full_scale_get(stmdev_ctx_t *ctx, lsm6ds3_fs_g_t *val);
+int32_t lsm6ds3_gy_full_scale_set(stmdev_ctx_t *ctx,
+ lsm6ds3_fs_g_t val);
+int32_t lsm6ds3_gy_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6ds3_fs_g_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_GY_ODR_OFF = 0,
LSM6DS3_GY_ODR_12Hz5 = 1,
LSM6DS3_GY_ODR_26Hz = 2,
@@ -1013,13 +1691,17 @@ typedef enum {
LSM6DS3_GY_ODR_833Hz = 7,
LSM6DS3_GY_ODR_1k66Hz = 8,
} lsm6ds3_odr_g_t;
-int32_t lsm6ds3_gy_data_rate_set(stmdev_ctx_t *ctx, lsm6ds3_odr_g_t val);
-int32_t lsm6ds3_gy_data_rate_get(stmdev_ctx_t *ctx, lsm6ds3_odr_g_t *val);
+int32_t lsm6ds3_gy_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6ds3_odr_g_t val);
+int32_t lsm6ds3_gy_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6ds3_odr_g_t *val);
int32_t lsm6ds3_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_XL_HIGH_PERFORMANCE = 0,
LSM6DS3_XL_NORMAL = 1,
} lsm6ds3_xl_hm_mode_t;
@@ -1028,7 +1710,8 @@ int32_t lsm6ds3_xl_power_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6ds3_xl_power_mode_get(stmdev_ctx_t *ctx,
lsm6ds3_xl_hm_mode_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_STAT_RND_DISABLE = 0,
LSM6DS3_STAT_RND_ENABLE = 1,
} lsm6ds3_rnd_stat_t;
@@ -1037,7 +1720,8 @@ int32_t lsm6ds3_rounding_on_status_set(stmdev_ctx_t *ctx,
int32_t lsm6ds3_rounding_on_status_get(stmdev_ctx_t *ctx,
lsm6ds3_rnd_stat_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_GY_HIGH_PERFORMANCE = 0,
LSM6DS3_GY_NORMAL = 1,
} lsm6ds3_g_hm_mode_t;
@@ -1064,36 +1748,46 @@ int32_t lsm6ds3_gy_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6ds3_gy_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3_gy_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef struct {
+typedef struct
+{
lsm6ds3_wake_up_src_t wake_up_src;
lsm6ds3_tap_src_t tap_src;
lsm6ds3_d6d_src_t d6d_src;
lsm6ds3_func_src_t func_src;
} lsm6ds3_all_src_t;
-int32_t lsm6ds3_all_sources_get(stmdev_ctx_t *ctx, lsm6ds3_all_src_t *val);
+int32_t lsm6ds3_all_sources_get(stmdev_ctx_t *ctx,
+ lsm6ds3_all_src_t *val);
-int32_t lsm6ds3_status_reg_get(stmdev_ctx_t *ctx, lsm6ds3_status_reg_t *val);
+int32_t lsm6ds3_status_reg_get(stmdev_ctx_t *ctx,
+ lsm6ds3_status_reg_t *val);
-int32_t lsm6ds3_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6ds3_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6ds3_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6ds3_timestamp_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6ds3_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val);
int32_t lsm6ds3_timestamp_rst_set(stmdev_ctx_t *ctx);
int32_t lsm6ds3_timestamp_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_LSB_6ms4 = 0,
LSM6DS3_LSB_25us = 1,
} lsm6ds3_ts_res_t;
-int32_t lsm6ds3_timestamp_res_set(stmdev_ctx_t *ctx, lsm6ds3_ts_res_t val);
-int32_t lsm6ds3_timestamp_res_get(stmdev_ctx_t *ctx, lsm6ds3_ts_res_t *val);
+int32_t lsm6ds3_timestamp_res_set(stmdev_ctx_t *ctx,
+ lsm6ds3_ts_res_t val);
+int32_t lsm6ds3_timestamp_res_get(stmdev_ctx_t *ctx,
+ lsm6ds3_ts_res_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_ROUND_DISABLE = 0,
LSM6DS3_ROUND_XL = 1,
LSM6DS3_ROUND_GY = 2,
@@ -1108,36 +1802,45 @@ int32_t lsm6ds3_rounding_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6ds3_rounding_mode_get(stmdev_ctx_t *ctx,
lsm6ds3_rounding_t *val);
-int32_t lsm6ds3_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6ds3_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val);
-int32_t lsm6ds3_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6ds3_angular_rate_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
-int32_t lsm6ds3_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6ds3_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
-int32_t lsm6ds3_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer, uint8_t len);
+int32_t lsm6ds3_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer,
+ uint8_t len);
-int32_t lsm6ds3_number_of_steps_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6ds3_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val);
-int32_t lsm6ds3_mag_calibrated_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6ds3_mag_calibrated_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_USER_BANK = 0,
LSM6DS3_EMBEDDED_FUNC_BANK = 1,
} lsm6ds3_func_cfg_en_t;
-int32_t lsm6ds3_mem_bank_set(stmdev_ctx_t *ctx, lsm6ds3_func_cfg_en_t val);
-int32_t lsm6ds3_mem_bank_get(stmdev_ctx_t *ctx, lsm6ds3_func_cfg_en_t *val);
+int32_t lsm6ds3_mem_bank_set(stmdev_ctx_t *ctx,
+ lsm6ds3_func_cfg_en_t val);
+int32_t lsm6ds3_mem_bank_get(stmdev_ctx_t *ctx,
+ lsm6ds3_func_cfg_en_t *val);
int32_t lsm6ds3_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t lsm6ds3_reset_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_LSB_AT_LOW_ADD = 0,
LSM6DS3_MSB_AT_LOW_ADD = 1,
} lsm6ds3_ble_t;
int32_t lsm6ds3_data_format_set(stmdev_ctx_t *ctx, lsm6ds3_ble_t val);
-int32_t lsm6ds3_data_format_get(stmdev_ctx_t *ctx, lsm6ds3_ble_t *val);
+int32_t lsm6ds3_data_format_get(stmdev_ctx_t *ctx,
+ lsm6ds3_ble_t *val);
int32_t lsm6ds3_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1145,79 +1848,104 @@ int32_t lsm6ds3_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6ds3_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_XL_ST_DISABLE = 0,
LSM6DS3_XL_ST_POSITIVE = 1,
LSM6DS3_XL_ST_NEGATIVE = 2,
} lsm6ds3_st_xl_t;
-int32_t lsm6ds3_xl_self_test_set(stmdev_ctx_t *ctx, lsm6ds3_st_xl_t val);
-int32_t lsm6ds3_xl_self_test_get(stmdev_ctx_t *ctx, lsm6ds3_st_xl_t *val);
+int32_t lsm6ds3_xl_self_test_set(stmdev_ctx_t *ctx,
+ lsm6ds3_st_xl_t val);
+int32_t lsm6ds3_xl_self_test_get(stmdev_ctx_t *ctx,
+ lsm6ds3_st_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_GY_ST_DISABLE = 0,
LSM6DS3_GY_ST_POSITIVE = 1,
LSM6DS3_GY_ST_NEGATIVE = 3,
} lsm6ds3_st_g_t;
-int32_t lsm6ds3_gy_self_test_set(stmdev_ctx_t *ctx, lsm6ds3_st_g_t val);
-int32_t lsm6ds3_gy_self_test_get(stmdev_ctx_t *ctx, lsm6ds3_st_g_t *val);
-
-int32_t lsm6ds3_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val);
-
-typedef enum {
+int32_t lsm6ds3_gy_self_test_set(stmdev_ctx_t *ctx,
+ lsm6ds3_st_g_t val);
+int32_t lsm6ds3_gy_self_test_get(stmdev_ctx_t *ctx,
+ lsm6ds3_st_g_t *val);
+
+int32_t lsm6ds3_filter_settling_mask_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3_filter_settling_mask_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+typedef enum
+{
LSM6DS3_HP_CUT_OFF_8mHz1 = 0,
LSM6DS3_HP_CUT_OFF_32mHz4 = 1,
LSM6DS3_HP_CUT_OFF_2Hz07 = 2,
LSM6DS3_HP_CUT_OFF_16Hz32 = 3,
} lsm6ds3_hpcf_g_t;
-int32_t lsm6ds3_gy_hp_bandwidth_set(stmdev_ctx_t *ctx, lsm6ds3_hpcf_g_t val);
-int32_t lsm6ds3_gy_hp_bandwidth_get(stmdev_ctx_t *ctx, lsm6ds3_hpcf_g_t *val);
+int32_t lsm6ds3_gy_hp_bandwidth_set(stmdev_ctx_t *ctx,
+ lsm6ds3_hpcf_g_t val);
+int32_t lsm6ds3_gy_hp_bandwidth_get(stmdev_ctx_t *ctx,
+ lsm6ds3_hpcf_g_t *val);
int32_t lsm6ds3_gy_hp_reset_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3_gy_hp_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_XL_HP_ODR_DIV_4 = 0,
LSM6DS3_XL_HP_ODR_DIV_100 = 1,
LSM6DS3_XL_HP_ODR_DIV_9 = 2,
LSM6DS3_XL_HP_ODR_DIV_400 = 3,
} lsm6ds3_hp_bw_t;
-int32_t lsm6ds3_xl_hp_bandwidth_set(stmdev_ctx_t *ctx, lsm6ds3_hp_bw_t val);
-int32_t lsm6ds3_xl_hp_bandwidth_get(stmdev_ctx_t *ctx, lsm6ds3_hp_bw_t *val);
+int32_t lsm6ds3_xl_hp_bandwidth_set(stmdev_ctx_t *ctx,
+ lsm6ds3_hp_bw_t val);
+int32_t lsm6ds3_xl_hp_bandwidth_get(stmdev_ctx_t *ctx,
+ lsm6ds3_hp_bw_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_XL_LP_ODR_DIV_50 = 0,
LSM6DS3_XL_LP_ODR_DIV_100 = 1,
LSM6DS3_XL_LP_ODR_DIV_9 = 2,
LSM6DS3_XL_LP_ODR_DIV_400 = 3,
} lsm6ds3_lp_bw_t;
-int32_t lsm6ds3_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, lsm6ds3_lp_bw_t val);
-int32_t lsm6ds3_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, lsm6ds3_lp_bw_t *val);
+int32_t lsm6ds3_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx,
+ lsm6ds3_lp_bw_t val);
+int32_t lsm6ds3_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx,
+ lsm6ds3_lp_bw_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_ANTI_ALIASING_400Hz = 0,
LSM6DS3_ANTI_ALIASING_200Hz = 1,
LSM6DS3_ANTI_ALIASING_100Hz = 2,
LSM6DS3_ANTI_ALIASING_50Hz = 3,
} lsm6ds3_bw_xl_t;
-int32_t lsm6ds3_xl_filter_analog_set(stmdev_ctx_t *ctx, lsm6ds3_bw_xl_t val);
-int32_t lsm6ds3_xl_filter_analog_get(stmdev_ctx_t *ctx, lsm6ds3_bw_xl_t *val);
+int32_t lsm6ds3_xl_filter_analog_set(stmdev_ctx_t *ctx,
+ lsm6ds3_bw_xl_t val);
+int32_t lsm6ds3_xl_filter_analog_get(stmdev_ctx_t *ctx,
+ lsm6ds3_bw_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_SPI_4_WIRE = 0,
LSM6DS3_SPI_3_WIRE = 1,
} lsm6ds3_sim_t;
int32_t lsm6ds3_spi_mode_set(stmdev_ctx_t *ctx, lsm6ds3_sim_t val);
int32_t lsm6ds3_spi_mode_get(stmdev_ctx_t *ctx, lsm6ds3_sim_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_I2C_ENABLE = 0,
LSM6DS3_I2C_DISABLE = 1,
} lsm6ds3_i2c_dis_t;
-int32_t lsm6ds3_i2c_interface_set(stmdev_ctx_t *ctx, lsm6ds3_i2c_dis_t val);
-int32_t lsm6ds3_i2c_interface_get(stmdev_ctx_t *ctx, lsm6ds3_i2c_dis_t *val);
+int32_t lsm6ds3_i2c_interface_set(stmdev_ctx_t *ctx,
+ lsm6ds3_i2c_dis_t val);
+int32_t lsm6ds3_i2c_interface_get(stmdev_ctx_t *ctx,
+ lsm6ds3_i2c_dis_t *val);
-typedef struct {
+typedef struct
+{
uint8_t int1_drdy_xl : 1;
uint8_t int1_drdy_g : 1;
uint8_t int1_boot : 1;
@@ -1241,7 +1969,8 @@ int32_t lsm6ds3_pin_int1_route_set(stmdev_ctx_t *ctx,
int32_t lsm6ds3_pin_int1_route_get(stmdev_ctx_t *ctx,
lsm6ds3_int1_route_t *val);
-typedef struct {
+typedef struct
+{
uint8_t int2_drdy_xl : 1;
uint8_t int2_drdy_g : 1;
uint8_t int2_drdy_temp : 1;
@@ -1260,34 +1989,44 @@ typedef struct {
uint8_t int2_inact_state : 1;
uint8_t start_config : 1;
} lsm6ds3_int2_route_t;
-int32_t lsm6ds3_pin_int2_route_set(stmdev_ctx_t *ctx, lsm6ds3_int2_route_t *val);
-int32_t lsm6ds3_pin_int2_route_get(stmdev_ctx_t *ctx, lsm6ds3_int2_route_t *val);
+int32_t lsm6ds3_pin_int2_route_set(stmdev_ctx_t *ctx,
+ lsm6ds3_int2_route_t *val);
+int32_t lsm6ds3_pin_int2_route_get(stmdev_ctx_t *ctx,
+ lsm6ds3_int2_route_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_PUSH_PULL = 0,
LSM6DS3_OPEN_DRAIN = 1,
} lsm6ds3_pp_od_t;
int32_t lsm6ds3_pin_mode_set(stmdev_ctx_t *ctx, lsm6ds3_pp_od_t val);
int32_t lsm6ds3_pin_mode_get(stmdev_ctx_t *ctx, lsm6ds3_pp_od_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_ACTIVE_HIGH = 0,
LSM6DS3_ACTIVE_LOW = 1,
} lsm6ds3_pin_pol_t;
-int32_t lsm6ds3_pin_polarity_set(stmdev_ctx_t *ctx, lsm6ds3_pin_pol_t val);
-int32_t lsm6ds3_pin_polarity_get(stmdev_ctx_t *ctx, lsm6ds3_pin_pol_t *val);
+int32_t lsm6ds3_pin_polarity_set(stmdev_ctx_t *ctx,
+ lsm6ds3_pin_pol_t val);
+int32_t lsm6ds3_pin_polarity_get(stmdev_ctx_t *ctx,
+ lsm6ds3_pin_pol_t *val);
int32_t lsm6ds3_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_INT_PULSED = 0,
LSM6DS3_INT_LATCHED = 1,
} lsm6ds3_lir_t;
-int32_t lsm6ds3_int_notification_set(stmdev_ctx_t *ctx, lsm6ds3_lir_t val);
-int32_t lsm6ds3_int_notification_get(stmdev_ctx_t *ctx, lsm6ds3_lir_t *val);
+int32_t lsm6ds3_int_notification_set(stmdev_ctx_t *ctx,
+ lsm6ds3_lir_t val);
+int32_t lsm6ds3_int_notification_get(stmdev_ctx_t *ctx,
+ lsm6ds3_lir_t *val);
-int32_t lsm6ds3_wkup_src_get(stmdev_ctx_t *ctx, lsm6ds3_wake_up_src_t *val);
+int32_t lsm6ds3_wkup_src_get(stmdev_ctx_t *ctx,
+ lsm6ds3_wake_up_src_t *val);
int32_t lsm6ds3_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1304,16 +2043,23 @@ int32_t lsm6ds3_act_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6ds3_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6ds3_tap_src_get(stmdev_ctx_t *ctx, lsm6ds3_tap_src_t *val);
+int32_t lsm6ds3_tap_src_get(stmdev_ctx_t *ctx,
+ lsm6ds3_tap_src_t *val);
-int32_t lsm6ds3_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3_tap_detection_on_z_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6ds3_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6ds3_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6ds3_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1327,14 +2073,17 @@ int32_t lsm6ds3_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6ds3_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_ONLY_DOUBLE = 1,
LSM6DS3_SINGLE_DOUBLE = 0,
} lsm6ds3_tap_md_t;
int32_t lsm6ds3_tap_mode_set(stmdev_ctx_t *ctx, lsm6ds3_tap_md_t val);
-int32_t lsm6ds3_tap_mode_get(stmdev_ctx_t *ctx, lsm6ds3_tap_md_t *val);
+int32_t lsm6ds3_tap_mode_get(stmdev_ctx_t *ctx,
+ lsm6ds3_tap_md_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_ODR_DIV_2_FEED = 0,
LSM6DS3_LPF2_FEED = 1,
} lsm6ds3_low_pass_on_6d_t;
@@ -1345,19 +2094,23 @@ int32_t lsm6ds3_6d_feed_data_get(stmdev_ctx_t *ctx,
int32_t lsm6ds3_6d_src_get(stmdev_ctx_t *ctx, lsm6ds3_d6d_src_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_DEG_80 = 0,
LSM6DS3_DEG_70 = 1,
LSM6DS3_DEG_60 = 2,
LSM6DS3_DEG_50 = 3,
} lsm6ds3_sixd_ths_t;
-int32_t lsm6ds3_6d_threshold_set(stmdev_ctx_t *ctx, lsm6ds3_sixd_ths_t val);
-int32_t lsm6ds3_6d_threshold_get(stmdev_ctx_t *ctx, lsm6ds3_sixd_ths_t *val);
+int32_t lsm6ds3_6d_threshold_set(stmdev_ctx_t *ctx,
+ lsm6ds3_sixd_ths_t val);
+int32_t lsm6ds3_6d_threshold_get(stmdev_ctx_t *ctx,
+ lsm6ds3_sixd_ths_t *val);
int32_t lsm6ds3_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_156_mg = 0,
LSM6DS3_219_mg = 1,
LSM6DS3_250_mg = 2,
@@ -1367,8 +2120,10 @@ typedef enum {
LSM6DS3_469_mg = 6,
LSM6DS3_500_mg = 7,
} lsm6ds3_ff_ths_t;
-int32_t lsm6ds3_ff_threshold_set(stmdev_ctx_t *ctx, lsm6ds3_ff_ths_t val);
-int32_t lsm6ds3_ff_threshold_get(stmdev_ctx_t *ctx, lsm6ds3_ff_ths_t *val);
+int32_t lsm6ds3_ff_threshold_set(stmdev_ctx_t *ctx,
+ lsm6ds3_ff_ths_t val);
+int32_t lsm6ds3_ff_threshold_get(stmdev_ctx_t *ctx,
+ lsm6ds3_ff_ths_t *val);
int32_t lsm6ds3_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1376,7 +2131,8 @@ int32_t lsm6ds3_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6ds3_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val);
int32_t lsm6ds3_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_TRG_XL_GY_DRDY = 0,
LSM6DS3_TRG_STEP_DETECT = 1,
} lsm6ds3_tmr_ped_fifo_drdy_t;
@@ -1388,7 +2144,8 @@ int32_t lsm6ds3_fifo_write_trigger_get(stmdev_ctx_t *ctx,
int32_t lsm6ds3_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_FIFO_XL_DISABLE = 0,
LSM6DS3_FIFO_XL_NO_DEC = 1,
LSM6DS3_FIFO_XL_DEC_2 = 2,
@@ -1403,7 +2160,8 @@ int32_t lsm6ds3_fifo_xl_batch_set(stmdev_ctx_t *ctx,
int32_t lsm6ds3_fifo_xl_batch_get(stmdev_ctx_t *ctx,
lsm6ds3_dec_fifo_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_FIFO_GY_DISABLE = 0,
LSM6DS3_FIFO_GY_NO_DEC = 1,
LSM6DS3_FIFO_GY_DEC_2 = 2,
@@ -1418,7 +2176,8 @@ int32_t lsm6ds3_fifo_gy_batch_set(stmdev_ctx_t *ctx,
int32_t lsm6ds3_fifo_gy_batch_get(stmdev_ctx_t *ctx,
lsm6ds3_dec_fifo_gyro_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_FIFO_DS3_DISABLE = 0,
LSM6DS3_FIFO_DS3_NO_DEC = 1,
LSM6DS3_FIFO_DS3_DEC_2 = 2,
@@ -1433,7 +2192,8 @@ int32_t lsm6ds3_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx,
int32_t lsm6ds3_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx,
lsm6ds3_dec_ds3_fifo_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_FIFO_DS4_DISABLE = 0,
LSM6DS3_FIFO_DS4_NO_DEC = 1,
LSM6DS3_FIFO_DS4_DEC_2 = 2,
@@ -1448,20 +2208,26 @@ int32_t lsm6ds3_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx,
int32_t lsm6ds3_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx,
lsm6ds3_dec_ds4_fifo_t *val);
-int32_t lsm6ds3_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_BYPASS_MODE = 0,
LSM6DS3_FIFO_MODE = 1,
LSM6DS3_STREAM_TO_FIFO_MODE = 3,
LSM6DS3_BYPASS_TO_STREAM_MODE = 4,
LSM6DS3_STREAM_MODE = 6,
} lsm6ds3_fifo_md_t;
-int32_t lsm6ds3_fifo_mode_set(stmdev_ctx_t *ctx, lsm6ds3_fifo_md_t val);
-int32_t lsm6ds3_fifo_mode_get(stmdev_ctx_t *ctx, lsm6ds3_fifo_md_t *val);
+int32_t lsm6ds3_fifo_mode_set(stmdev_ctx_t *ctx,
+ lsm6ds3_fifo_md_t val);
+int32_t lsm6ds3_fifo_mode_get(stmdev_ctx_t *ctx,
+ lsm6ds3_fifo_md_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_FIFO_DISABLE = 0,
LSM6DS3_FIFO_12Hz5 = 1,
LSM6DS3_FIFO_26Hz = 2,
@@ -1495,22 +2261,27 @@ int32_t lsm6ds3_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6ds3_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_DEN_DISABLE = 0,
LSM6DS3_LEVEL_FIFO = 6,
LSM6DS3_LEVEL_LETCHED = 3,
LSM6DS3_LEVEL_TRIGGER = 2,
LSM6DS3_EDGE_TRIGGER = 4,
} lsm6ds3_den_mode_t;
-int32_t lsm6ds3_den_mode_set(stmdev_ctx_t *ctx, lsm6ds3_den_mode_t val);
-int32_t lsm6ds3_den_mode_get(stmdev_ctx_t *ctx, lsm6ds3_den_mode_t *val);
+int32_t lsm6ds3_den_mode_set(stmdev_ctx_t *ctx,
+ lsm6ds3_den_mode_t val);
+int32_t lsm6ds3_den_mode_get(stmdev_ctx_t *ctx,
+ lsm6ds3_den_mode_t *val);
int32_t lsm6ds3_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6ds3_pedo_timestamp_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6ds3_pedo_timestamp_raw_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
-int32_t lsm6ds3_pedo_step_detect_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3_pedo_step_detect_flag_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6ds3_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1518,7 +2289,8 @@ int32_t lsm6ds3_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6ds3_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_PEDO_AT_2g = 0,
LSM6DS3_PEDO_AT_4g = 1,
} lsm6ds3_pedo_fs_t;
@@ -1527,8 +2299,10 @@ int32_t lsm6ds3_pedo_full_scale_set(stmdev_ctx_t *ctx,
int32_t lsm6ds3_pedo_full_scale_get(stmdev_ctx_t *ctx,
lsm6ds3_pedo_fs_t *val);
-int32_t lsm6ds3_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6ds3_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1536,7 +2310,8 @@ int32_t lsm6ds3_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6ds3_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6ds3_motion_event_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3_motion_event_flag_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6ds3_motion_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3_motion_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1558,14 +2333,18 @@ int32_t lsm6ds3_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6ds3_mag_soft_iron_end_op_flag_get(stmdev_ctx_t *ctx,
uint8_t *val);
-int32_t lsm6ds3_mag_soft_iron_coeff_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6ds3_mag_soft_iron_coeff_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6ds3_mag_soft_iron_coeff_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lsm6ds3_mag_soft_iron_coeff_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
-int32_t lsm6ds3_mag_offset_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6ds3_mag_offset_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6ds3_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val);
+int32_t lsm6ds3_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val);
-int32_t lsm6ds3_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3_sh_sync_sens_frame_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3_sh_sync_sens_frame_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6ds3_sh_master_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1573,14 +2352,18 @@ int32_t lsm6ds3_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6ds3_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_EXT_PULL_UP = 0,
LSM6DS3_INTERNAL_PULL_UP = 1,
} lsm6ds3_sh_pin_md_t;
-int32_t lsm6ds3_sh_pin_mode_set(stmdev_ctx_t *ctx, lsm6ds3_sh_pin_md_t val);
-int32_t lsm6ds3_sh_pin_mode_get(stmdev_ctx_t *ctx, lsm6ds3_sh_pin_md_t *val);
+int32_t lsm6ds3_sh_pin_mode_set(stmdev_ctx_t *ctx,
+ lsm6ds3_sh_pin_md_t val);
+int32_t lsm6ds3_sh_pin_mode_get(stmdev_ctx_t *ctx,
+ lsm6ds3_sh_pin_md_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_XL_GY_DRDY = 0,
LSM6DS3_EXT_ON_INT2_PIN = 1,
} lsm6ds3_start_cfg_t;
@@ -1589,30 +2372,32 @@ int32_t lsm6ds3_sh_syncro_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6ds3_sh_syncro_mode_get(stmdev_ctx_t *ctx,
lsm6ds3_start_cfg_t *val);
-typedef struct {
- lsm6ds3_sensorhub1_reg_t sh_byte_1;
- lsm6ds3_sensorhub2_reg_t sh_byte_2;
- lsm6ds3_sensorhub3_reg_t sh_byte_3;
- lsm6ds3_sensorhub4_reg_t sh_byte_4;
- lsm6ds3_sensorhub5_reg_t sh_byte_5;
- lsm6ds3_sensorhub6_reg_t sh_byte_6;
- lsm6ds3_sensorhub7_reg_t sh_byte_7;
- lsm6ds3_sensorhub8_reg_t sh_byte_8;
- lsm6ds3_sensorhub9_reg_t sh_byte_9;
- lsm6ds3_sensorhub10_reg_t sh_byte_10;
- lsm6ds3_sensorhub11_reg_t sh_byte_11;
- lsm6ds3_sensorhub12_reg_t sh_byte_12;
- lsm6ds3_sensorhub13_reg_t sh_byte_13;
- lsm6ds3_sensorhub14_reg_t sh_byte_14;
- lsm6ds3_sensorhub15_reg_t sh_byte_15;
- lsm6ds3_sensorhub16_reg_t sh_byte_16;
- lsm6ds3_sensorhub17_reg_t sh_byte_17;
- lsm6ds3_sensorhub18_reg_t sh_byte_18;
+typedef struct
+{
+ lsm6ds3_sensorhub1_reg_t sh_byte_1;
+ lsm6ds3_sensorhub2_reg_t sh_byte_2;
+ lsm6ds3_sensorhub3_reg_t sh_byte_3;
+ lsm6ds3_sensorhub4_reg_t sh_byte_4;
+ lsm6ds3_sensorhub5_reg_t sh_byte_5;
+ lsm6ds3_sensorhub6_reg_t sh_byte_6;
+ lsm6ds3_sensorhub7_reg_t sh_byte_7;
+ lsm6ds3_sensorhub8_reg_t sh_byte_8;
+ lsm6ds3_sensorhub9_reg_t sh_byte_9;
+ lsm6ds3_sensorhub10_reg_t sh_byte_10;
+ lsm6ds3_sensorhub11_reg_t sh_byte_11;
+ lsm6ds3_sensorhub12_reg_t sh_byte_12;
+ lsm6ds3_sensorhub13_reg_t sh_byte_13;
+ lsm6ds3_sensorhub14_reg_t sh_byte_14;
+ lsm6ds3_sensorhub15_reg_t sh_byte_15;
+ lsm6ds3_sensorhub16_reg_t sh_byte_16;
+ lsm6ds3_sensorhub17_reg_t sh_byte_17;
+ lsm6ds3_sensorhub18_reg_t sh_byte_18;
} lsm6ds3_sh_read_t;
int32_t lsm6ds3_sh_read_data_raw_get(stmdev_ctx_t *ctx,
lsm6ds3_sh_read_t *buff);
-typedef enum {
+typedef enum
+{
LSM6DS3_SLV_0 = 0,
LSM6DS3_SLV_0_1 = 1,
LSM6DS3_SLV_0_1_2 = 2,
@@ -1623,14 +2408,17 @@ int32_t lsm6ds3_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx,
int32_t lsm6ds3_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx,
lsm6ds3_aux_sens_on_t *val);
-typedef struct{
+typedef struct
+{
uint8_t slv0_add;
uint8_t slv0_subadd;
uint8_t slv0_data;
} lsm6ds3_sh_cfg_write_t;
-int32_t lsm6ds3_sh_cfg_write(stmdev_ctx_t *ctx, lsm6ds3_sh_cfg_write_t *val);
+int32_t lsm6ds3_sh_cfg_write(stmdev_ctx_t *ctx,
+ lsm6ds3_sh_cfg_write_t *val);
-typedef struct{
+typedef struct
+{
uint8_t slv_add;
uint8_t slv_subadd;
uint8_t slv_len;
@@ -1646,7 +2434,8 @@ int32_t lsm6ds3_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
int32_t lsm6ds3_sh_end_op_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3_USE_SLOPE = 0,
LSM6DS3_USE_HPF = 1,
} lsm6ds3_slope_fds_t;
diff --git a/sensor/stmemsc/lsm6ds3tr_c_STdC/driver/lsm6ds3tr_c_reg.c b/sensor/stmemsc/lsm6ds3tr-c_STdC/driver/lsm6ds3tr_c_reg.c
similarity index 68%
rename from sensor/stmemsc/lsm6ds3tr_c_STdC/driver/lsm6ds3tr_c_reg.c
rename to sensor/stmemsc/lsm6ds3tr-c_STdC/driver/lsm6ds3tr_c_reg.c
index 65e7cd9976ef7d23212c0b88bd9590448c9eb86c..ec99dc1f361701c5177965965892ce6fc7e980af 100644
--- a/sensor/stmemsc/lsm6ds3tr_c_STdC/driver/lsm6ds3tr_c_reg.c
+++ b/sensor/stmemsc/lsm6ds3tr-c_STdC/driver/lsm6ds3tr_c_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file lsm6ds3tr_c_reg.c
- * @author Sensors Software Solution Team
- * @brief LSM6DS3TR_C driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lsm6ds3tr_c_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LSM6DS3TR_C driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lsm6ds3tr_c_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3tr_c_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t lsm6ds3tr_c_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t lsm6ds3tr_c_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6ds3tr_c_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t lsm6ds3tr_c_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -146,7 +152,7 @@ float_t lsm6ds3tr_c_from_lsb_to_celsius(int16_t lsb)
* generation
* @{
*
-*/
+ */
/**
* @brief Accelerometer full-scale selection.[set]
@@ -156,16 +162,22 @@ float_t lsm6ds3tr_c_from_lsb_to_celsius(int16_t lsb)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_xl_full_scale_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_fs_xl_t val)
+int32_t lsm6ds3tr_c_xl_full_scale_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_fs_xl_t val)
{
lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
ctrl1_xl.fs_xl = (uint8_t) val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -177,25 +189,33 @@ int32_t lsm6ds3tr_c_xl_full_scale_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_fs_xl_t val
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_xl_full_scale_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_fs_xl_t *val)
+int32_t lsm6ds3tr_c_xl_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_fs_xl_t *val)
{
lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- switch (ctrl1_xl.fs_xl) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
+
+ switch (ctrl1_xl.fs_xl)
+ {
case LSM6DS3TR_C_2g:
*val = LSM6DS3TR_C_2g;
break;
+
case LSM6DS3TR_C_16g:
*val = LSM6DS3TR_C_16g;
break;
+
case LSM6DS3TR_C_4g:
*val = LSM6DS3TR_C_4g;
break;
+
case LSM6DS3TR_C_8g:
*val = LSM6DS3TR_C_8g;
break;
+
default:
*val = LSM6DS3TR_C_XL_FS_ND;
break;
@@ -212,16 +232,22 @@ int32_t lsm6ds3tr_c_xl_full_scale_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_fs_xl_t *va
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_xl_t val)
+int32_t lsm6ds3tr_c_xl_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_odr_xl_t val)
{
lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
ctrl1_xl.odr_xl = (uint8_t) val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -233,49 +259,65 @@ int32_t lsm6ds3tr_c_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_xl_t val
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_xl_data_rate_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_xl_t *val)
+int32_t lsm6ds3tr_c_xl_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_odr_xl_t *val)
{
lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- switch (ctrl1_xl.odr_xl) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
+
+ switch (ctrl1_xl.odr_xl)
+ {
case LSM6DS3TR_C_XL_ODR_OFF:
*val = LSM6DS3TR_C_XL_ODR_OFF;
break;
+
case LSM6DS3TR_C_XL_ODR_12Hz5:
*val = LSM6DS3TR_C_XL_ODR_12Hz5;
break;
+
case LSM6DS3TR_C_XL_ODR_26Hz:
*val = LSM6DS3TR_C_XL_ODR_26Hz;
break;
+
case LSM6DS3TR_C_XL_ODR_52Hz:
*val = LSM6DS3TR_C_XL_ODR_52Hz;
break;
+
case LSM6DS3TR_C_XL_ODR_104Hz:
*val = LSM6DS3TR_C_XL_ODR_104Hz;
break;
+
case LSM6DS3TR_C_XL_ODR_208Hz:
*val = LSM6DS3TR_C_XL_ODR_208Hz;
break;
+
case LSM6DS3TR_C_XL_ODR_416Hz:
*val = LSM6DS3TR_C_XL_ODR_416Hz;
break;
+
case LSM6DS3TR_C_XL_ODR_833Hz:
*val = LSM6DS3TR_C_XL_ODR_833Hz;
break;
+
case LSM6DS3TR_C_XL_ODR_1k66Hz:
*val = LSM6DS3TR_C_XL_ODR_1k66Hz;
break;
+
case LSM6DS3TR_C_XL_ODR_3k33Hz:
*val = LSM6DS3TR_C_XL_ODR_3k33Hz;
break;
+
case LSM6DS3TR_C_XL_ODR_6k66Hz:
*val = LSM6DS3TR_C_XL_ODR_6k66Hz;
break;
+
case LSM6DS3TR_C_XL_ODR_1Hz6:
*val = LSM6DS3TR_C_XL_ODR_1Hz6;
break;
+
default:
*val = LSM6DS3TR_C_XL_ODR_ND;
break;
@@ -292,16 +334,22 @@ int32_t lsm6ds3tr_c_xl_data_rate_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_xl_t *va
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_gy_full_scale_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_fs_g_t val)
+int32_t lsm6ds3tr_c_gy_full_scale_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_fs_g_t val)
{
lsm6ds3tr_c_ctrl2_g_t ctrl2_g;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL2_G,
+ (uint8_t *)&ctrl2_g, 1);
+
+ if (ret == 0)
+ {
ctrl2_g.fs_g = (uint8_t) val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL2_G,
+ (uint8_t *)&ctrl2_g, 1);
}
+
return ret;
}
@@ -313,28 +361,37 @@ int32_t lsm6ds3tr_c_gy_full_scale_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_fs_g_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_gy_full_scale_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_fs_g_t *val)
+int32_t lsm6ds3tr_c_gy_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_fs_g_t *val)
{
lsm6ds3tr_c_ctrl2_g_t ctrl2_g;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- switch (ctrl2_g.fs_g) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL2_G,
+ (uint8_t *)&ctrl2_g, 1);
+
+ switch (ctrl2_g.fs_g)
+ {
case LSM6DS3TR_C_250dps:
*val = LSM6DS3TR_C_250dps;
break;
+
case LSM6DS3TR_C_125dps:
*val = LSM6DS3TR_C_125dps;
break;
+
case LSM6DS3TR_C_500dps:
*val = LSM6DS3TR_C_500dps;
break;
+
case LSM6DS3TR_C_1000dps:
*val = LSM6DS3TR_C_1000dps;
break;
+
case LSM6DS3TR_C_2000dps:
*val = LSM6DS3TR_C_2000dps;
break;
+
default:
*val = LSM6DS3TR_C_GY_FS_ND;
break;
@@ -351,16 +408,22 @@ int32_t lsm6ds3tr_c_gy_full_scale_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_fs_g_t *val
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_gy_data_rate_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_g_t val)
+int32_t lsm6ds3tr_c_gy_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_odr_g_t val)
{
lsm6ds3tr_c_ctrl2_g_t ctrl2_g;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL2_G,
+ (uint8_t *)&ctrl2_g, 1);
+
+ if (ret == 0)
+ {
ctrl2_g.odr_g = (uint8_t) val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL2_G,
+ (uint8_t *)&ctrl2_g, 1);
}
+
return ret;
}
@@ -372,46 +435,61 @@ int32_t lsm6ds3tr_c_gy_data_rate_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_g_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_gy_data_rate_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_g_t *val)
+int32_t lsm6ds3tr_c_gy_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_odr_g_t *val)
{
lsm6ds3tr_c_ctrl2_g_t ctrl2_g;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- switch (ctrl2_g.odr_g) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL2_G,
+ (uint8_t *)&ctrl2_g, 1);
+
+ switch (ctrl2_g.odr_g)
+ {
case LSM6DS3TR_C_GY_ODR_OFF:
*val = LSM6DS3TR_C_GY_ODR_OFF;
break;
+
case LSM6DS3TR_C_GY_ODR_12Hz5:
*val = LSM6DS3TR_C_GY_ODR_12Hz5;
break;
+
case LSM6DS3TR_C_GY_ODR_26Hz:
*val = LSM6DS3TR_C_GY_ODR_26Hz;
break;
+
case LSM6DS3TR_C_GY_ODR_52Hz:
*val = LSM6DS3TR_C_GY_ODR_52Hz;
break;
+
case LSM6DS3TR_C_GY_ODR_104Hz:
*val = LSM6DS3TR_C_GY_ODR_104Hz;
break;
+
case LSM6DS3TR_C_GY_ODR_208Hz:
*val = LSM6DS3TR_C_GY_ODR_208Hz;
break;
+
case LSM6DS3TR_C_GY_ODR_416Hz:
*val = LSM6DS3TR_C_GY_ODR_416Hz;
break;
+
case LSM6DS3TR_C_GY_ODR_833Hz:
*val = LSM6DS3TR_C_GY_ODR_833Hz;
break;
+
case LSM6DS3TR_C_GY_ODR_1k66Hz:
*val = LSM6DS3TR_C_GY_ODR_1k66Hz;
break;
+
case LSM6DS3TR_C_GY_ODR_3k33Hz:
*val = LSM6DS3TR_C_GY_ODR_3k33Hz;
break;
+
case LSM6DS3TR_C_GY_ODR_6k66Hz:
*val = LSM6DS3TR_C_GY_ODR_6k66Hz;
break;
+
default:
*val = LSM6DS3TR_C_GY_ODR_ND;
break;
@@ -428,16 +506,22 @@ int32_t lsm6ds3tr_c_gy_data_rate_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_g_t *val
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6ds3tr_c_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.bdu = val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -449,12 +533,14 @@ int32_t lsm6ds3tr_c_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3tr_c_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.bdu;
return ret;
@@ -470,16 +556,21 @@ int32_t lsm6ds3tr_c_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6ds3tr_c_xl_offset_weight_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_usr_off_w_t val)
+ lsm6ds3tr_c_usr_off_w_t val)
{
lsm6ds3tr_c_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C,
+ (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
ctrl6_c.usr_off_w = (uint8_t) val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL6_C,
+ (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -493,19 +584,24 @@ int32_t lsm6ds3tr_c_xl_offset_weight_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_xl_offset_weight_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_usr_off_w_t *val)
+ lsm6ds3tr_c_usr_off_w_t *val)
{
lsm6ds3tr_c_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- switch (ctrl6_c.usr_off_w) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C,
+ (uint8_t *)&ctrl6_c, 1);
+
+ switch (ctrl6_c.usr_off_w)
+ {
case LSM6DS3TR_C_LSb_1mg:
*val = LSM6DS3TR_C_LSb_1mg;
break;
+
case LSM6DS3TR_C_LSb_16mg:
*val = LSM6DS3TR_C_LSb_16mg;
break;
+
default:
*val = LSM6DS3TR_C_WEIGHT_ND;
break;
@@ -523,16 +619,21 @@ int32_t lsm6ds3tr_c_xl_offset_weight_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_xl_power_mode_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_xl_hm_mode_t val)
+ lsm6ds3tr_c_xl_hm_mode_t val)
{
lsm6ds3tr_c_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C,
+ (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
ctrl6_c.xl_hm_mode = (uint8_t) val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL6_C,
+ (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -545,19 +646,24 @@ int32_t lsm6ds3tr_c_xl_power_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_xl_power_mode_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_xl_hm_mode_t *val)
+ lsm6ds3tr_c_xl_hm_mode_t *val)
{
lsm6ds3tr_c_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- switch (ctrl6_c.xl_hm_mode) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C,
+ (uint8_t *)&ctrl6_c, 1);
+
+ switch (ctrl6_c.xl_hm_mode)
+ {
case LSM6DS3TR_C_XL_HIGH_PERFORMANCE:
*val = LSM6DS3TR_C_XL_HIGH_PERFORMANCE;
break;
+
case LSM6DS3TR_C_XL_NORMAL:
*val = LSM6DS3TR_C_XL_NORMAL;
break;
+
default:
*val = LSM6DS3TR_C_XL_PW_MODE_ND;
break;
@@ -577,16 +683,21 @@ int32_t lsm6ds3tr_c_xl_power_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_rounding_on_status_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_rounding_status_t val)
+ lsm6ds3tr_c_rounding_status_t val)
{
lsm6ds3tr_c_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL7_G,
+ (uint8_t *)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
ctrl7_g.rounding_status = (uint8_t) val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL7_G,
+ (uint8_t *)&ctrl7_g, 1);
}
+
return ret;
}
@@ -601,19 +712,24 @@ int32_t lsm6ds3tr_c_rounding_on_status_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_rounding_on_status_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_rounding_status_t *val)
+ lsm6ds3tr_c_rounding_status_t *val)
{
lsm6ds3tr_c_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- switch (ctrl7_g.rounding_status) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL7_G,
+ (uint8_t *)&ctrl7_g, 1);
+
+ switch (ctrl7_g.rounding_status)
+ {
case LSM6DS3TR_C_STAT_RND_DISABLE:
*val = LSM6DS3TR_C_STAT_RND_DISABLE;
break;
+
case LSM6DS3TR_C_STAT_RND_ENABLE:
*val = LSM6DS3TR_C_STAT_RND_ENABLE;
break;
+
default:
*val = LSM6DS3TR_C_STAT_RND_ND;
break;
@@ -630,16 +746,22 @@ int32_t lsm6ds3tr_c_rounding_on_status_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_gy_power_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_g_hm_mode_t val)
+int32_t lsm6ds3tr_c_gy_power_mode_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_g_hm_mode_t val)
{
lsm6ds3tr_c_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL7_G,
+ (uint8_t *)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
ctrl7_g.g_hm_mode = (uint8_t) val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL7_G,
+ (uint8_t *)&ctrl7_g, 1);
}
+
return ret;
}
@@ -651,19 +773,25 @@ int32_t lsm6ds3tr_c_gy_power_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_g_hm_mode_t
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_gy_power_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_g_hm_mode_t *val)
+int32_t lsm6ds3tr_c_gy_power_mode_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_g_hm_mode_t *val)
{
lsm6ds3tr_c_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- switch (ctrl7_g.g_hm_mode) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL7_G,
+ (uint8_t *)&ctrl7_g, 1);
+
+ switch (ctrl7_g.g_hm_mode)
+ {
case LSM6DS3TR_C_GY_HIGH_PERFORMANCE:
*val = LSM6DS3TR_C_GY_HIGH_PERFORMANCE;
break;
+
case LSM6DS3TR_C_GY_NORMAL:
*val = LSM6DS3TR_C_GY_NORMAL;
break;
+
default:
*val = LSM6DS3TR_C_GY_PW_MODE_ND;
break;
@@ -682,44 +810,62 @@ int32_t lsm6ds3tr_c_gy_power_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_g_hm_mode_t
*
*/
int32_t lsm6ds3tr_c_all_sources_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_all_sources_t *val)
+ lsm6ds3tr_c_all_sources_t *val)
{
int32_t ret;
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_SRC,
- (uint8_t*)&(val->wake_up_src), 1);
- if(ret == 0){
+ (uint8_t *) & (val->wake_up_src), 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_SRC,
- (uint8_t*)&(val->tap_src), 1);
+ (uint8_t *) & (val->tap_src), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_D6D_SRC,
- (uint8_t*)&(val->d6d_src), 1);
+ (uint8_t *) & (val->d6d_src), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_STATUS_REG,
- (uint8_t*)&(val->status_reg), 1);
+ (uint8_t *) & (val->status_reg), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FUNC_SRC1,
- (uint8_t*)&(val->func_src1), 1);
+ (uint8_t *) & (val->func_src1), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FUNC_SRC2,
- (uint8_t*)&(val->func_src2), 1);
+ (uint8_t *) & (val->func_src2), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WRIST_TILT_IA,
- (uint8_t*)&(val->wrist_tilt_ia), 1);
+ (uint8_t *) & (val->wrist_tilt_ia), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_B);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_A_WRIST_TILT_MASK,
- (uint8_t*)&(val->a_wrist_tilt_mask), 1);
+ (uint8_t *) & (val->a_wrist_tilt_mask), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
@@ -733,10 +879,14 @@ int32_t lsm6ds3tr_c_all_sources_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_status_reg_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_status_reg_t *val)
+int32_t lsm6ds3tr_c_status_reg_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_status_reg_t *val)
{
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_STATUS_REG, (uint8_t*) val, 1);
+
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_STATUS_REG,
+ (uint8_t *) val, 1);
+
return ret;
}
@@ -748,12 +898,14 @@ int32_t lsm6ds3tr_c_status_reg_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_status_reg_t *
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3tr_c_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3tr_c_status_reg_t status_reg;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_STATUS_REG, (uint8_t*)&status_reg, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_STATUS_REG,
+ (uint8_t *)&status_reg, 1);
*val = status_reg.xlda;
return ret;
@@ -767,12 +919,14 @@ int32_t lsm6ds3tr_c_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3tr_c_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3tr_c_status_reg_t status_reg;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_STATUS_REG, (uint8_t*)&status_reg, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_STATUS_REG,
+ (uint8_t *)&status_reg, 1);
*val = status_reg.gda;
return ret;
@@ -786,12 +940,14 @@ int32_t lsm6ds3tr_c_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3tr_c_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3tr_c_status_reg_t status_reg;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_STATUS_REG, (uint8_t*)&status_reg, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_STATUS_REG,
+ (uint8_t *)&status_reg, 1);
*val = status_reg.tda;
return ret;
@@ -807,10 +963,13 @@ int32_t lsm6ds3tr_c_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6ds3tr_c_xl_usr_offset_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
+
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_X_OFS_USR, buff, 3);
+
return ret;
}
@@ -824,10 +983,13 @@ int32_t lsm6ds3tr_c_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6ds3tr_c_xl_usr_offset_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
+
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_X_OFS_USR, buff, 3);
+
return ret;
}
@@ -858,14 +1020,21 @@ int32_t lsm6ds3tr_c_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3tr_c_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C,
+ (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
ctrl10_c.timer_en = val;
- if ( val != 0x00U) {
+
+ if (val != 0x00U)
+ {
ctrl10_c.func_en = val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL10_C,
+ (uint8_t *)&ctrl10_c, 1);
}
}
+
return ret;
}
@@ -883,7 +1052,8 @@ int32_t lsm6ds3tr_c_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3tr_c_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C,
+ (uint8_t *)&ctrl10_c, 1);
*val = ctrl10_c.timer_en;
return ret;
@@ -902,17 +1072,22 @@ int32_t lsm6ds3tr_c_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_timestamp_res_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_timer_hr_t val)
+int32_t lsm6ds3tr_c_timestamp_res_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_timer_hr_t val)
{
lsm6ds3tr_c_wake_up_dur_t wake_up_dur;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
wake_up_dur.timer_hr = (uint8_t) val;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -929,19 +1104,25 @@ int32_t lsm6ds3tr_c_timestamp_res_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_timer_hr_t
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_timestamp_res_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_timer_hr_t *val)
+int32_t lsm6ds3tr_c_timestamp_res_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_timer_hr_t *val)
{
lsm6ds3tr_c_wake_up_dur_t wake_up_dur;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
- switch (wake_up_dur.timer_hr) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
+
+ switch (wake_up_dur.timer_hr)
+ {
case LSM6DS3TR_C_LSB_6ms4:
*val = LSM6DS3TR_C_LSB_6ms4;
break;
+
case LSM6DS3TR_C_LSB_25us:
*val = LSM6DS3TR_C_LSB_25us;
break;
+
default:
*val = LSM6DS3TR_C_TS_RES_ND;
break;
@@ -971,16 +1152,22 @@ int32_t lsm6ds3tr_c_timestamp_res_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_timer_hr_t
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_rounding_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_rounding_t val)
+int32_t lsm6ds3tr_c_rounding_mode_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_rounding_t val)
{
lsm6ds3tr_c_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C,
+ (uint8_t *)&ctrl5_c, 1);
+
+ if (ret == 0)
+ {
ctrl5_c.rounding = (uint8_t) val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL5_C,
+ (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -993,37 +1180,49 @@ int32_t lsm6ds3tr_c_rounding_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_rounding_t
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_rounding_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_rounding_t *val)
+int32_t lsm6ds3tr_c_rounding_mode_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_rounding_t *val)
{
lsm6ds3tr_c_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- switch (ctrl5_c.rounding) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C,
+ (uint8_t *)&ctrl5_c, 1);
+
+ switch (ctrl5_c.rounding)
+ {
case LSM6DS3TR_C_ROUND_DISABLE:
*val = LSM6DS3TR_C_ROUND_DISABLE;
break;
+
case LSM6DS3TR_C_ROUND_XL:
*val = LSM6DS3TR_C_ROUND_XL;
break;
+
case LSM6DS3TR_C_ROUND_GY:
*val = LSM6DS3TR_C_ROUND_GY;
break;
+
case LSM6DS3TR_C_ROUND_GY_XL:
*val = LSM6DS3TR_C_ROUND_GY_XL;
break;
+
case LSM6DS3TR_C_ROUND_SH1_TO_SH6:
*val = LSM6DS3TR_C_ROUND_SH1_TO_SH6;
break;
+
case LSM6DS3TR_C_ROUND_XL_SH1_TO_SH6:
*val = LSM6DS3TR_C_ROUND_XL_SH1_TO_SH6;
break;
+
case LSM6DS3TR_C_ROUND_GY_XL_SH1_TO_SH12:
*val = LSM6DS3TR_C_ROUND_GY_XL_SH1_TO_SH12;
break;
+
case LSM6DS3TR_C_ROUND_GY_XL_SH1_TO_SH6:
*val = LSM6DS3TR_C_ROUND_GY_XL_SH1_TO_SH6;
break;
+
default:
*val = LSM6DS3TR_C_ROUND_OUT_ND;
break;
@@ -1041,10 +1240,16 @@ int32_t lsm6ds3tr_c_rounding_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_rounding_t
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6ds3tr_c_temperature_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
+
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_OUT_TEMP_L, buff, 2);
+ *val = (int16_t)buff[1];
+ *val = (*val * 256) + (int16_t)buff[0];
+
return ret;
}
@@ -1057,10 +1262,20 @@ int32_t lsm6ds3tr_c_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6ds3tr_c_angular_rate_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_OUTX_L_G, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -1073,10 +1288,20 @@ int32_t lsm6ds3tr_c_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6ds3tr_c_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_OUTX_L_XL, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -1088,10 +1313,20 @@ int32_t lsm6ds3tr_c_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_mag_calibrated_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6ds3tr_c_mag_calibrated_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_OUT_MAG_RAW_X_L, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -1104,11 +1339,15 @@ int32_t lsm6ds3tr_c_mag_calibrated_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer,
- uint8_t len)
+int32_t lsm6ds3tr_c_fifo_raw_data_get(stmdev_ctx_t *ctx,
+ uint8_t *buffer,
+ uint8_t len)
{
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_DATA_OUT_L, buffer, len);
+
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_DATA_OUT_L, buffer,
+ len);
+
return ret;
}
@@ -1119,7 +1358,7 @@ int32_t lsm6ds3tr_c_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer,
/**
* @defgroup LSM6DS3TR_C_common
- * @brief This section groups common usefull functions.
+ * @brief This section groups common useful functions.
* @{
*
*/
@@ -1133,17 +1372,20 @@ int32_t lsm6ds3tr_c_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_mem_bank_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_func_cfg_en_t val)
+int32_t lsm6ds3tr_c_mem_bank_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_func_cfg_en_t val)
{
lsm6ds3tr_c_func_cfg_access_t func_cfg_access;
int32_t ret;
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
- if(ret == 0){
+ (uint8_t *)&func_cfg_access, 1);
+
+ if (ret == 0)
+ {
func_cfg_access.func_cfg_en = (uint8_t) val;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
+ (uint8_t *)&func_cfg_access, 1);
}
return ret;
@@ -1158,20 +1400,25 @@ int32_t lsm6ds3tr_c_mem_bank_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_func_cfg_en_t va
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_mem_bank_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_func_cfg_en_t *val)
+int32_t lsm6ds3tr_c_mem_bank_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_func_cfg_en_t *val)
{
lsm6ds3tr_c_func_cfg_access_t func_cfg_access;
int32_t ret;
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
- switch (func_cfg_access.func_cfg_en) {
+ (uint8_t *)&func_cfg_access, 1);
+
+ switch (func_cfg_access.func_cfg_en)
+ {
case LSM6DS3TR_C_USER_BANK:
*val = LSM6DS3TR_C_USER_BANK;
break;
+
case LSM6DS3TR_C_BANK_B:
*val = LSM6DS3TR_C_BANK_B;
break;
+
default:
*val = LSM6DS3TR_C_BANK_ND;
break;
@@ -1189,18 +1436,21 @@ int32_t lsm6ds3tr_c_mem_bank_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_func_cfg_en_t *v
*
*/
int32_t lsm6ds3tr_c_data_ready_mode_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_drdy_pulsed_g_t val)
+ lsm6ds3tr_c_drdy_pulsed_g_t val)
{
lsm6ds3tr_c_drdy_pulse_cfg_g_t drdy_pulse_cfg_g;
int32_t ret;
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_DRDY_PULSE_CFG_G,
- (uint8_t*)&drdy_pulse_cfg_g, 1);
- if(ret == 0){
+ (uint8_t *)&drdy_pulse_cfg_g, 1);
+
+ if (ret == 0)
+ {
drdy_pulse_cfg_g.drdy_pulsed = (uint8_t) val;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_DRDY_PULSE_CFG_G,
- (uint8_t*)&drdy_pulse_cfg_g, 1);
+ (uint8_t *)&drdy_pulse_cfg_g, 1);
}
+
return ret;
}
@@ -1213,20 +1463,24 @@ int32_t lsm6ds3tr_c_data_ready_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_data_ready_mode_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_drdy_pulsed_g_t *val)
+ lsm6ds3tr_c_drdy_pulsed_g_t *val)
{
lsm6ds3tr_c_drdy_pulse_cfg_g_t drdy_pulse_cfg_g;
int32_t ret;
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_DRDY_PULSE_CFG_G,
- (uint8_t*)&drdy_pulse_cfg_g, 1);
- switch (drdy_pulse_cfg_g.drdy_pulsed) {
+ (uint8_t *)&drdy_pulse_cfg_g, 1);
+
+ switch (drdy_pulse_cfg_g.drdy_pulsed)
+ {
case LSM6DS3TR_C_DRDY_LATCHED:
*val = LSM6DS3TR_C_DRDY_LATCHED;
break;
+
case LSM6DS3TR_C_DRDY_PULSED:
*val = LSM6DS3TR_C_DRDY_PULSED;
break;
+
default:
*val = LSM6DS3TR_C_DRDY_ND;
break;
@@ -1246,7 +1500,9 @@ int32_t lsm6ds3tr_c_data_ready_mode_get(stmdev_ctx_t *ctx,
int32_t lsm6ds3tr_c_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -1263,11 +1519,16 @@ int32_t lsm6ds3tr_c_reset_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.sw_reset = val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1284,7 +1545,8 @@ int32_t lsm6ds3tr_c_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.sw_reset;
return ret;
@@ -1298,16 +1560,22 @@ int32_t lsm6ds3tr_c_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_data_format_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_ble_t val)
+int32_t lsm6ds3tr_c_data_format_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_ble_t val)
{
lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.ble = (uint8_t) val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1319,19 +1587,25 @@ int32_t lsm6ds3tr_c_data_format_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_ble_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_data_format_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_ble_t *val)
+int32_t lsm6ds3tr_c_data_format_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_ble_t *val)
{
lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- switch (ctrl3_c.ble) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
+
+ switch (ctrl3_c.ble)
+ {
case LSM6DS3TR_C_LSB_AT_LOW_ADD:
*val = LSM6DS3TR_C_LSB_AT_LOW_ADD;
break;
+
case LSM6DS3TR_C_MSB_AT_LOW_ADD:
*val = LSM6DS3TR_C_MSB_AT_LOW_ADD;
break;
+
default:
*val = LSM6DS3TR_C_DATA_FMT_ND;
break;
@@ -1354,11 +1628,16 @@ int32_t lsm6ds3tr_c_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.if_inc = val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1371,12 +1650,14 @@ int32_t lsm6ds3tr_c_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3tr_c_auto_increment_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.if_inc;
return ret;
@@ -1395,11 +1676,16 @@ int32_t lsm6ds3tr_c_boot_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.boot = val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1416,7 +1702,8 @@ int32_t lsm6ds3tr_c_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.boot;
return ret;
@@ -1430,16 +1717,22 @@ int32_t lsm6ds3tr_c_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_xl_self_test_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_st_xl_t val)
+int32_t lsm6ds3tr_c_xl_self_test_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_st_xl_t val)
{
lsm6ds3tr_c_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C,
+ (uint8_t *)&ctrl5_c, 1);
+
+ if (ret == 0)
+ {
ctrl5_c.st_xl = (uint8_t) val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL5_C,
+ (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -1451,26 +1744,34 @@ int32_t lsm6ds3tr_c_xl_self_test_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_st_xl_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_xl_self_test_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_st_xl_t *val)
+int32_t lsm6ds3tr_c_xl_self_test_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_st_xl_t *val)
{
lsm6ds3tr_c_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- switch (ctrl5_c.st_xl) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C,
+ (uint8_t *)&ctrl5_c, 1);
+
+ switch (ctrl5_c.st_xl)
+ {
case LSM6DS3TR_C_XL_ST_DISABLE:
*val = LSM6DS3TR_C_XL_ST_DISABLE;
break;
+
case LSM6DS3TR_C_XL_ST_POSITIVE:
*val = LSM6DS3TR_C_XL_ST_POSITIVE;
break;
+
case LSM6DS3TR_C_XL_ST_NEGATIVE:
*val = LSM6DS3TR_C_XL_ST_NEGATIVE;
break;
+
default:
*val = LSM6DS3TR_C_XL_ST_ND;
break;
}
+
return ret;
}
@@ -1482,16 +1783,22 @@ int32_t lsm6ds3tr_c_xl_self_test_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_st_xl_t *val
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_gy_self_test_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_st_g_t val)
+int32_t lsm6ds3tr_c_gy_self_test_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_st_g_t val)
{
lsm6ds3tr_c_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C,
+ (uint8_t *)&ctrl5_c, 1);
+
+ if (ret == 0)
+ {
ctrl5_c.st_g = (uint8_t) val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL5_C,
+ (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -1503,22 +1810,29 @@ int32_t lsm6ds3tr_c_gy_self_test_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_st_g_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_gy_self_test_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_st_g_t *val)
+int32_t lsm6ds3tr_c_gy_self_test_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_st_g_t *val)
{
lsm6ds3tr_c_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- switch (ctrl5_c.st_g) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C,
+ (uint8_t *)&ctrl5_c, 1);
+
+ switch (ctrl5_c.st_g)
+ {
case LSM6DS3TR_C_GY_ST_DISABLE:
*val = LSM6DS3TR_C_GY_ST_DISABLE;
break;
+
case LSM6DS3TR_C_GY_ST_POSITIVE:
*val = LSM6DS3TR_C_GY_ST_POSITIVE;
break;
+
case LSM6DS3TR_C_GY_ST_NEGATIVE:
*val = LSM6DS3TR_C_GY_ST_NEGATIVE;
break;
+
default:
*val = LSM6DS3TR_C_GY_ST_ND;
break;
@@ -1549,16 +1863,22 @@ int32_t lsm6ds3tr_c_gy_self_test_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_st_g_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6ds3tr_c_filter_settling_mask_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6ds3tr_c_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
ctrl4_c.drdy_mask = val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -1571,12 +1891,14 @@ int32_t lsm6ds3tr_c_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3tr_c_filter_settling_mask_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3tr_c_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.drdy_mask;
return ret;
@@ -1592,16 +1914,21 @@ int32_t lsm6ds3tr_c_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6ds3tr_c_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_slope_fds_t val)
+ lsm6ds3tr_c_slope_fds_t val)
{
lsm6ds3tr_c_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG,
+ (uint8_t *)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
tap_cfg.slope_fds = (uint8_t) val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG,
+ (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -1615,19 +1942,24 @@ int32_t lsm6ds3tr_c_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_slope_fds_t *val)
+ lsm6ds3tr_c_slope_fds_t *val)
{
lsm6ds3tr_c_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- switch (tap_cfg.slope_fds) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG,
+ (uint8_t *)&tap_cfg, 1);
+
+ switch (tap_cfg.slope_fds)
+ {
case LSM6DS3TR_C_USE_SLOPE:
*val = LSM6DS3TR_C_USE_SLOPE;
break;
+
case LSM6DS3TR_C_USE_HPF:
*val = LSM6DS3TR_C_USE_HPF;
break;
+
default:
*val = LSM6DS3TR_C_HP_PATH_ND;
break;
@@ -1658,16 +1990,22 @@ int32_t lsm6ds3tr_c_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_xl_filter_analog_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_bw0_xl_t val)
+int32_t lsm6ds3tr_c_xl_filter_analog_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_bw0_xl_t val)
{
lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
ctrl1_xl.bw0_xl = (uint8_t) val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -1681,19 +2019,24 @@ int32_t lsm6ds3tr_c_xl_filter_analog_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_bw0_xl_t
*
*/
int32_t lsm6ds3tr_c_xl_filter_analog_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_bw0_xl_t *val)
+ lsm6ds3tr_c_bw0_xl_t *val)
{
lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- switch (ctrl1_xl.bw0_xl) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
+
+ switch (ctrl1_xl.bw0_xl)
+ {
case LSM6DS3TR_C_XL_ANA_BW_1k5Hz:
*val = LSM6DS3TR_C_XL_ANA_BW_1k5Hz;
break;
+
case LSM6DS3TR_C_XL_ANA_BW_400Hz:
*val = LSM6DS3TR_C_XL_ANA_BW_400Hz;
break;
+
default:
*val = LSM6DS3TR_C_XL_ANA_BW_ND;
break;
@@ -1725,25 +2068,36 @@ int32_t lsm6ds3tr_c_xl_filter_analog_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_xl_lp1_bandwidth_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_lpf1_bw_sel_t val)
+ lsm6ds3tr_c_lpf1_bw_sel_t val)
{
lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl;
lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
ctrl1_xl.lpf1_bw_sel = (uint8_t) val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
ctrl8_xl.lpf2_xl_en = 0;
ctrl8_xl.hp_slope_xl_en = 0;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
}
}
}
+
return ret;
}
@@ -1757,33 +2111,45 @@ int32_t lsm6ds3tr_c_xl_lp1_bandwidth_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_xl_lp1_bandwidth_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_lpf1_bw_sel_t *val)
+ lsm6ds3tr_c_lpf1_bw_sel_t *val)
{
lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl;
lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
if ((ctrl8_xl.lpf2_xl_en != 0x00U) ||
- (ctrl8_xl.hp_slope_xl_en != 0x00U)){
+ (ctrl8_xl.hp_slope_xl_en != 0x00U))
+ {
*val = LSM6DS3TR_C_XL_LP1_NA;
}
- else{
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- switch ( ctrl1_xl.lpf1_bw_sel) {
+
+ else
+ {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
+
+ switch (ctrl1_xl.lpf1_bw_sel)
+ {
case LSM6DS3TR_C_XL_LP1_ODR_DIV_2:
*val = LSM6DS3TR_C_XL_LP1_ODR_DIV_2;
break;
+
case LSM6DS3TR_C_XL_LP1_ODR_DIV_4:
*val = LSM6DS3TR_C_XL_LP1_ODR_DIV_4;
break;
+
default:
*val = LSM6DS3TR_C_XL_LP1_NA;
break;
}
}
}
+
return ret;
}
@@ -1796,19 +2162,24 @@ int32_t lsm6ds3tr_c_xl_lp1_bandwidth_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_input_composite_t val)
+ lsm6ds3tr_c_input_composite_t val)
{
lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
- ctrl8_xl.input_composite = ( (uint8_t) val & 0x10U ) >> 4;
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl8_xl.input_composite = ((uint8_t) val & 0x10U) >> 4;
ctrl8_xl.hpcf_xl = (uint8_t) val & 0x03U;
ctrl8_xl.lpf2_xl_en = 1;
ctrl8_xl.hp_slope_xl_en = 0;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -1821,43 +2192,58 @@ int32_t lsm6ds3tr_c_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_input_composite_t *val)
+ lsm6ds3tr_c_input_composite_t *val)
{
lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
if ((ctrl8_xl.lpf2_xl_en == 0x00U) ||
- (ctrl8_xl.hp_slope_xl_en != 0x00U)){
+ (ctrl8_xl.hp_slope_xl_en != 0x00U))
+ {
*val = LSM6DS3TR_C_XL_LP_NA;
}
- else{
- switch ((ctrl8_xl.input_composite << 4) + ctrl8_xl.hpcf_xl) {
+
+ else
+ {
+ switch ((ctrl8_xl.input_composite << 4) + ctrl8_xl.hpcf_xl)
+ {
case LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_50:
*val = LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_50;
break;
+
case LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_100:
*val = LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_100;
break;
+
case LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_9:
*val = LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_9;
break;
+
case LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_400:
*val = LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_400;
break;
+
case LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_50:
*val = LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_50;
break;
+
case LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_100:
*val = LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_100;
break;
+
case LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_9:
*val = LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_9;
break;
+
case LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_400:
*val = LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_400;
break;
+
default:
*val = LSM6DS3TR_C_XL_LP_NA;
break;
@@ -1876,16 +2262,22 @@ int32_t lsm6ds3tr_c_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_xl_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6ds3tr_c_xl_reference_mode_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
ctrl8_xl.hp_ref_mode = val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -1897,12 +2289,14 @@ int32_t lsm6ds3tr_c_xl_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_xl_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3tr_c_xl_reference_mode_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
*val = ctrl8_xl.hp_ref_mode;
return ret;
@@ -1916,18 +2310,24 @@ int32_t lsm6ds3tr_c_xl_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_xl_hp_bandwidth_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_hpcf_xl_t val)
+int32_t lsm6ds3tr_c_xl_hp_bandwidth_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_hpcf_xl_t val)
{
lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
ctrl8_xl.input_composite = 0;
ctrl8_xl.hpcf_xl = (uint8_t)val & 0x03U;
ctrl8_xl.hp_slope_xl_en = 1;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -1939,28 +2339,38 @@ int32_t lsm6ds3tr_c_xl_hp_bandwidth_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_hpcf_xl_t
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_xl_hp_bandwidth_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_hpcf_xl_t *val)
+int32_t lsm6ds3tr_c_xl_hp_bandwidth_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_hpcf_xl_t *val)
{
lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if (ctrl8_xl.hp_slope_xl_en == 0x00U){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
+
+ if (ctrl8_xl.hp_slope_xl_en == 0x00U)
+ {
*val = LSM6DS3TR_C_XL_HP_NA;
}
- switch (ctrl8_xl.hpcf_xl) {
+
+ switch (ctrl8_xl.hpcf_xl)
+ {
case LSM6DS3TR_C_XL_HP_ODR_DIV_4:
*val = LSM6DS3TR_C_XL_HP_ODR_DIV_4;
break;
+
case LSM6DS3TR_C_XL_HP_ODR_DIV_100:
*val = LSM6DS3TR_C_XL_HP_ODR_DIV_100;
break;
+
case LSM6DS3TR_C_XL_HP_ODR_DIV_9:
*val = LSM6DS3TR_C_XL_HP_ODR_DIV_9;
break;
+
case LSM6DS3TR_C_XL_HP_ODR_DIV_400:
*val = LSM6DS3TR_C_XL_HP_ODR_DIV_400;
break;
+
default:
*val = LSM6DS3TR_C_XL_HP_NA;
break;
@@ -1990,35 +2400,51 @@ int32_t lsm6ds3tr_c_xl_hp_bandwidth_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_hpcf_xl_t
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_gy_band_pass_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_lpf1_sel_g_t val)
+int32_t lsm6ds3tr_c_gy_band_pass_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_lpf1_sel_g_t val)
{
lsm6ds3tr_c_ctrl4_c_t ctrl4_c;
lsm6ds3tr_c_ctrl6_c_t ctrl6_c;
lsm6ds3tr_c_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
- ctrl7_g.hpm_g = ( (uint8_t)val & 0x30U ) >> 4;
- ctrl7_g.hp_en_g = ( (uint8_t)val & 0x80U ) >> 7;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL7_G,
+ (uint8_t *)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
+ ctrl7_g.hpm_g = ((uint8_t)val & 0x30U) >> 4;
+ ctrl7_g.hp_en_g = ((uint8_t)val & 0x80U) >> 7;
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL7_G,
+ (uint8_t *)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C,
+ (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
ctrl6_c.ftype = (uint8_t)val & 0x03U;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL6_C,
+ (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C,
- (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ctrl4_c.lpf1_sel_g = ( (uint8_t)val & 0x08U ) >> 3;
+ (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl4_c.lpf1_sel_g = ((uint8_t)val & 0x08U) >> 3;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL4_C,
- (uint8_t*)&ctrl4_c, 1);
+ (uint8_t *)&ctrl4_c, 1);
}
}
}
}
}
+
return ret;
}
@@ -2030,57 +2456,78 @@ int32_t lsm6ds3tr_c_gy_band_pass_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_lpf1_sel_g_t
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_gy_band_pass_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_lpf1_sel_g_t *val)
+int32_t lsm6ds3tr_c_gy_band_pass_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_lpf1_sel_g_t *val)
{
lsm6ds3tr_c_ctrl4_c_t ctrl4_c;
lsm6ds3tr_c_ctrl6_c_t ctrl6_c;
lsm6ds3tr_c_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C,
+ (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
- switch ( ( ctrl7_g.hp_en_g << 7 ) + ( ctrl7_g.hpm_g << 4 ) +
- ( ctrl4_c.lpf1_sel_g << 3) + ctrl6_c.ftype ) {
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL7_G,
+ (uint8_t *)&ctrl7_g, 1);
+
+ switch ((ctrl7_g.hp_en_g << 7) + (ctrl7_g.hpm_g << 4) +
+ (ctrl4_c.lpf1_sel_g << 3) + ctrl6_c.ftype)
+ {
case LSM6DS3TR_C_HP_16mHz_LP2:
*val = LSM6DS3TR_C_HP_16mHz_LP2;
break;
+
case LSM6DS3TR_C_HP_65mHz_LP2:
*val = LSM6DS3TR_C_HP_65mHz_LP2;
break;
+
case LSM6DS3TR_C_HP_260mHz_LP2:
*val = LSM6DS3TR_C_HP_260mHz_LP2;
break;
+
case LSM6DS3TR_C_HP_1Hz04_LP2:
*val = LSM6DS3TR_C_HP_1Hz04_LP2;
break;
+
case LSM6DS3TR_C_HP_DISABLE_LP1_LIGHT:
*val = LSM6DS3TR_C_HP_DISABLE_LP1_LIGHT;
break;
+
case LSM6DS3TR_C_HP_DISABLE_LP1_NORMAL:
*val = LSM6DS3TR_C_HP_DISABLE_LP1_NORMAL;
break;
+
case LSM6DS3TR_C_HP_DISABLE_LP_STRONG:
*val = LSM6DS3TR_C_HP_DISABLE_LP_STRONG;
break;
+
case LSM6DS3TR_C_HP_DISABLE_LP1_AGGRESSIVE:
*val = LSM6DS3TR_C_HP_DISABLE_LP1_AGGRESSIVE;
break;
+
case LSM6DS3TR_C_HP_16mHz_LP1_LIGHT:
*val = LSM6DS3TR_C_HP_16mHz_LP1_LIGHT;
break;
+
case LSM6DS3TR_C_HP_65mHz_LP1_NORMAL:
*val = LSM6DS3TR_C_HP_65mHz_LP1_NORMAL;
break;
+
case LSM6DS3TR_C_HP_260mHz_LP1_STRONG:
*val = LSM6DS3TR_C_HP_260mHz_LP1_STRONG;
break;
+
case LSM6DS3TR_C_HP_1Hz04_LP1_AGGRESSIVE:
*val = LSM6DS3TR_C_HP_1Hz04_LP1_AGGRESSIVE;
break;
+
default:
*val = LSM6DS3TR_C_HP_GY_BAND_NA;
break;
@@ -2112,16 +2559,22 @@ int32_t lsm6ds3tr_c_gy_band_pass_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_lpf1_sel_g_t
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_spi_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_sim_t val)
+int32_t lsm6ds3tr_c_spi_mode_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_sim_t val)
{
lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.sim = (uint8_t) val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -2133,23 +2586,30 @@ int32_t lsm6ds3tr_c_spi_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_sim_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_spi_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_sim_t *val)
+int32_t lsm6ds3tr_c_spi_mode_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_sim_t *val)
{
lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- switch (ctrl3_c.sim) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
+
+ switch (ctrl3_c.sim)
+ {
case LSM6DS3TR_C_SPI_4_WIRE:
*val = LSM6DS3TR_C_SPI_4_WIRE;
break;
+
case LSM6DS3TR_C_SPI_3_WIRE:
*val = LSM6DS3TR_C_SPI_3_WIRE;
break;
+
default:
*val = LSM6DS3TR_C_SPI_MODE_ND;
break;
}
+
return ret;
}
@@ -2162,16 +2622,21 @@ int32_t lsm6ds3tr_c_spi_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_sim_t *val)
*
*/
int32_t lsm6ds3tr_c_i2c_interface_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_i2c_disable_t val)
+ lsm6ds3tr_c_i2c_disable_t val)
{
lsm6ds3tr_c_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
ctrl4_c.i2c_disable = (uint8_t)val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -2184,19 +2649,24 @@ int32_t lsm6ds3tr_c_i2c_interface_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_i2c_interface_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_i2c_disable_t *val)
+ lsm6ds3tr_c_i2c_disable_t *val)
{
lsm6ds3tr_c_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- switch (ctrl4_c.i2c_disable) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
+
+ switch (ctrl4_c.i2c_disable)
+ {
case LSM6DS3TR_C_I2C_ENABLE:
*val = LSM6DS3TR_C_I2C_ENABLE;
break;
+
case LSM6DS3TR_C_I2C_DISABLE:
*val = LSM6DS3TR_C_I2C_DISABLE;
break;
+
default:
*val = LSM6DS3TR_C_I2C_MODE_ND;
break;
@@ -2213,7 +2683,7 @@ int32_t lsm6ds3tr_c_i2c_interface_get(stmdev_ctx_t *ctx,
/**
* @defgroup LSM6DS3TR_C_interrupt_pins
* @brief This section groups all the functions that manage
- * interrup pins
+ * interrupt pins
* @{
*
*/
@@ -2228,7 +2698,7 @@ int32_t lsm6ds3tr_c_i2c_interface_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_pin_int1_route_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_int1_route_t val)
+ lsm6ds3tr_c_int1_route_t val)
{
lsm6ds3tr_c_master_config_t master_config;
lsm6ds3tr_c_int1_ctrl_t int1_ctrl;
@@ -2238,8 +2708,11 @@ int32_t lsm6ds3tr_c_pin_int1_route_set(stmdev_ctx_t *ctx,
lsm6ds3tr_c_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT1_CTRL,
+ (uint8_t *)&int1_ctrl, 1);
+
+ if (ret == 0)
+ {
int1_ctrl.int1_drdy_xl = val.int1_drdy_xl;
int1_ctrl.int1_drdy_g = val.int1_drdy_g;
int1_ctrl.int1_boot = val.int1_boot;
@@ -2248,64 +2721,95 @@ int32_t lsm6ds3tr_c_pin_int1_route_set(stmdev_ctx_t *ctx,
int1_ctrl.int1_full_flag = val.int1_full_flag;
int1_ctrl.int1_sign_mot = val.int1_sign_mot;
int1_ctrl.int1_step_detector = val.int1_step_detector;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_INT1_CTRL,
+ (uint8_t *)&int1_ctrl, 1);
}
- if(ret == 0){
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MD1_CFG, (uint8_t*)&md1_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MD1_CFG,
+ (uint8_t *)&md1_cfg, 1);
}
- if(ret == 0){
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MD2_CFG, (uint8_t*)&md2_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MD2_CFG,
+ (uint8_t *)&md2_cfg, 1);
}
- if(ret == 0){
- md1_cfg.int1_timer = val.int1_timer;
- md1_cfg.int1_tilt = val.int1_tilt;
- md1_cfg.int1_6d = val.int1_6d;
- md1_cfg.int1_double_tap = val.int1_double_tap;
- md1_cfg.int1_ff = val.int1_ff;
- md1_cfg.int1_wu = val.int1_wu;
- md1_cfg.int1_single_tap = val.int1_single_tap;
- md1_cfg.int1_inact_state = val.int1_inact_state;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MD1_CFG, (uint8_t*)&md1_cfg, 1);
+
+ if (ret == 0)
+ {
+ md1_cfg.int1_timer = val.int1_timer;
+ md1_cfg.int1_tilt = val.int1_tilt;
+ md1_cfg.int1_6d = val.int1_6d;
+ md1_cfg.int1_double_tap = val.int1_double_tap;
+ md1_cfg.int1_ff = val.int1_ff;
+ md1_cfg.int1_wu = val.int1_wu;
+ md1_cfg.int1_single_tap = val.int1_single_tap;
+ md1_cfg.int1_inact_state = val.int1_inact_state;
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MD1_CFG,
+ (uint8_t *)&md1_cfg, 1);
}
- if(ret == 0){
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ctrl4_c.den_drdy_int1 = val.den_drdy_int1;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- master_config.drdy_on_int1 = val.den_drdy_int1;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+
+ if (ret == 0)
+ {
+ master_config.drdy_on_int1 = val.den_drdy_int1;
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG,
+ (uint8_t *)&tap_cfg, 1);
+
if ((val.int1_6d != 0x00U) ||
(val.int1_ff != 0x00U) ||
(val.int1_wu != 0x00U) ||
(val.int1_single_tap != 0x00U) ||
(val.int1_double_tap != 0x00U) ||
- (val.int1_inact_state != 0x00U)||
+ (val.int1_inact_state != 0x00U) ||
(md2_cfg.int2_6d != 0x00U) ||
(md2_cfg.int2_ff != 0x00U) ||
(md2_cfg.int2_wu != 0x00U) ||
(md2_cfg.int2_single_tap != 0x00U) ||
(md2_cfg.int2_double_tap != 0x00U) ||
- (md2_cfg.int2_inact_state!= 0x00U) ){
+ (md2_cfg.int2_inact_state != 0x00U))
+ {
tap_cfg.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
tap_cfg.interrupts_enable = PROPERTY_DISABLE;
}
}
- if(ret == 0){
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG,
+ (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -2319,17 +2823,19 @@ int32_t lsm6ds3tr_c_pin_int1_route_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_pin_int1_route_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_int1_route_t *val)
+ lsm6ds3tr_c_int1_route_t *val)
{
lsm6ds3tr_c_master_config_t master_config;
lsm6ds3tr_c_int1_ctrl_t int1_ctrl;
lsm6ds3tr_c_md1_cfg_t md1_cfg;
lsm6ds3tr_c_ctrl4_c_t ctrl4_c;
-
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT1_CTRL,
+ (uint8_t *)&int1_ctrl, 1);
+
+ if (ret == 0)
+ {
val->int1_drdy_xl = int1_ctrl.int1_drdy_xl;
val->int1_drdy_g = int1_ctrl.int1_drdy_g;
val->int1_boot = int1_ctrl.int1_boot;
@@ -2338,27 +2844,32 @@ int32_t lsm6ds3tr_c_pin_int1_route_get(stmdev_ctx_t *ctx,
val->int1_full_flag = int1_ctrl.int1_full_flag;
val->int1_sign_mot = int1_ctrl.int1_sign_mot;
val->int1_step_detector = int1_ctrl.int1_step_detector ;
-
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MD1_CFG, (uint8_t*)&md1_cfg, 1);
- if(ret == 0){
- val->int1_timer = md1_cfg.int1_timer;
- val->int1_tilt = md1_cfg.int1_tilt;
- val->int1_6d = md1_cfg.int1_6d;
- val->int1_double_tap = md1_cfg.int1_double_tap;
- val->int1_ff = md1_cfg.int1_ff;
- val->int1_wu = md1_cfg.int1_wu;
- val->int1_single_tap = md1_cfg.int1_single_tap;
- val->int1_inact_state = md1_cfg.int1_inact_state;
-
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MD1_CFG,
+ (uint8_t *)&md1_cfg, 1);
+
+ if (ret == 0)
+ {
+ val->int1_timer = md1_cfg.int1_timer;
+ val->int1_tilt = md1_cfg.int1_tilt;
+ val->int1_6d = md1_cfg.int1_6d;
+ val->int1_double_tap = md1_cfg.int1_double_tap;
+ val->int1_ff = md1_cfg.int1_ff;
+ val->int1_wu = md1_cfg.int1_wu;
+ val->int1_single_tap = md1_cfg.int1_single_tap;
+ val->int1_inact_state = md1_cfg.int1_inact_state;
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
val->den_drdy_int1 = ctrl4_c.den_drdy_int1;
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
val->den_drdy_int1 = master_config.drdy_on_int1;
}
}
}
+
return ret;
}
@@ -2371,7 +2882,7 @@ int32_t lsm6ds3tr_c_pin_int1_route_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_pin_int2_route_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_int2_route_t val)
+ lsm6ds3tr_c_int2_route_t val)
{
lsm6ds3tr_c_int2_ctrl_t int2_ctrl;
lsm6ds3tr_c_md1_cfg_t md1_cfg;
@@ -2380,9 +2891,11 @@ int32_t lsm6ds3tr_c_pin_int2_route_set(stmdev_ctx_t *ctx,
lsm6ds3tr_c_tap_cfg_t tap_cfg;
int32_t ret;
-
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT2_CTRL,
+ (uint8_t *)&int2_ctrl, 1);
+
+ if (ret == 0)
+ {
int2_ctrl.int2_drdy_xl = val.int2_drdy_xl;
int2_ctrl.int2_drdy_g = val.int2_drdy_g;
int2_ctrl.int2_drdy_temp = val.int2_drdy_temp;
@@ -2391,15 +2904,24 @@ int32_t lsm6ds3tr_c_pin_int2_route_set(stmdev_ctx_t *ctx,
int2_ctrl.int2_full_flag = val.int2_full_flag;
int2_ctrl.int2_step_count_ov = val.int2_step_count_ov;
int2_ctrl.int2_step_delta = val.int2_step_delta;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_INT2_CTRL,
+ (uint8_t *)&int2_ctrl, 1);
}
- if(ret == 0){
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MD1_CFG, (uint8_t*)&md1_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MD1_CFG,
+ (uint8_t *)&md1_cfg, 1);
}
- if(ret == 0){
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MD2_CFG, (uint8_t*)&md2_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MD2_CFG,
+ (uint8_t *)&md2_cfg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
md2_cfg.int2_iron = val.int2_iron;
md2_cfg.int2_tilt = val.int2_tilt;
md2_cfg.int2_6d = val.int2_6d;
@@ -2408,19 +2930,28 @@ int32_t lsm6ds3tr_c_pin_int2_route_set(stmdev_ctx_t *ctx,
md2_cfg.int2_wu = val.int2_wu;
md2_cfg.int2_single_tap = val.int2_single_tap;
md2_cfg.int2_inact_state = val.int2_inact_state;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MD2_CFG, (uint8_t*)&md2_cfg, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MD2_CFG,
+ (uint8_t *)&md2_cfg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_DRDY_PULSE_CFG_G,
- (uint8_t*)&drdy_pulse_cfg_g, 1);
+ (uint8_t *)&drdy_pulse_cfg_g, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
drdy_pulse_cfg_g.int2_wrist_tilt = val.int2_wrist_tilt;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_DRDY_PULSE_CFG_G,
- (uint8_t*)&drdy_pulse_cfg_g, 1);
+ (uint8_t *)&drdy_pulse_cfg_g, 1);
}
- if(ret == 0){
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG,
+ (uint8_t *)&tap_cfg, 1);
+
if ((md1_cfg.int1_6d != 0x00U) ||
(md1_cfg.int1_ff != 0x00U) ||
(md1_cfg.int1_wu != 0x00U) ||
@@ -2432,16 +2963,23 @@ int32_t lsm6ds3tr_c_pin_int2_route_set(stmdev_ctx_t *ctx,
(val.int2_wu != 0x00U) ||
(val.int2_single_tap != 0x00U) ||
(val.int2_double_tap != 0x00U) ||
- (val.int2_inact_state!= 0x00U) ){
+ (val.int2_inact_state != 0x00U))
+ {
tap_cfg.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
tap_cfg.interrupts_enable = PROPERTY_DISABLE;
}
}
- if(ret == 0){
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG,
+ (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -2454,16 +2992,18 @@ int32_t lsm6ds3tr_c_pin_int2_route_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_pin_int2_route_get(stmdev_ctx_t *ctx,
-lsm6ds3tr_c_int2_route_t *val)
+ lsm6ds3tr_c_int2_route_t *val)
{
lsm6ds3tr_c_int2_ctrl_t int2_ctrl;
lsm6ds3tr_c_md2_cfg_t md2_cfg;
lsm6ds3tr_c_drdy_pulse_cfg_g_t drdy_pulse_cfg_g;
-
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT2_CTRL,
+ (uint8_t *)&int2_ctrl, 1);
+
+ if (ret == 0)
+ {
val->int2_drdy_xl = int2_ctrl.int2_drdy_xl;
val->int2_drdy_g = int2_ctrl.int2_drdy_g;
val->int2_drdy_temp = int2_ctrl.int2_drdy_temp;
@@ -2472,9 +3012,11 @@ lsm6ds3tr_c_int2_route_t *val)
val->int2_full_flag = int2_ctrl.int2_full_flag;
val->int2_step_count_ov = int2_ctrl.int2_step_count_ov;
val->int2_step_delta = int2_ctrl.int2_step_delta;
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MD2_CFG,
+ (uint8_t *)&md2_cfg, 1);
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MD2_CFG, (uint8_t*)&md2_cfg, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
val->int2_iron = md2_cfg.int2_iron;
val->int2_tilt = md2_cfg.int2_tilt;
val->int2_6d = md2_cfg.int2_6d;
@@ -2483,12 +3025,12 @@ lsm6ds3tr_c_int2_route_t *val)
val->int2_wu = md2_cfg.int2_wu;
val->int2_single_tap = md2_cfg.int2_single_tap;
val->int2_inact_state = md2_cfg.int2_inact_state;
-
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_DRDY_PULSE_CFG_G,
- (uint8_t*)&drdy_pulse_cfg_g, 1);
+ (uint8_t *)&drdy_pulse_cfg_g, 1);
val->int2_wrist_tilt = drdy_pulse_cfg_g.int2_wrist_tilt;
}
}
+
return ret;
}
@@ -2500,16 +3042,22 @@ lsm6ds3tr_c_int2_route_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_pin_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_pp_od_t val)
+int32_t lsm6ds3tr_c_pin_mode_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_pp_od_t val)
{
lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.pp_od = (uint8_t) val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -2521,19 +3069,25 @@ int32_t lsm6ds3tr_c_pin_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_pp_od_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_pin_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_pp_od_t *val)
+int32_t lsm6ds3tr_c_pin_mode_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_pp_od_t *val)
{
lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- switch (ctrl3_c.pp_od) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
+
+ switch (ctrl3_c.pp_od)
+ {
case LSM6DS3TR_C_PUSH_PULL:
*val = LSM6DS3TR_C_PUSH_PULL;
break;
+
case LSM6DS3TR_C_OPEN_DRAIN:
*val = LSM6DS3TR_C_OPEN_DRAIN;
break;
+
default:
*val = LSM6DS3TR_C_PIN_MODE_ND;
break;
@@ -2550,16 +3104,22 @@ int32_t lsm6ds3tr_c_pin_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_pp_od_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_pin_polarity_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_h_lactive_t val)
+int32_t lsm6ds3tr_c_pin_polarity_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_h_lactive_t val)
{
lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.h_lactive = (uint8_t) val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -2571,19 +3131,25 @@ int32_t lsm6ds3tr_c_pin_polarity_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_h_lactive_t
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_pin_polarity_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_h_lactive_t *val)
+int32_t lsm6ds3tr_c_pin_polarity_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_h_lactive_t *val)
{
lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- switch (ctrl3_c.h_lactive) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
+
+ switch (ctrl3_c.h_lactive)
+ {
case LSM6DS3TR_C_ACTIVE_HIGH:
*val = LSM6DS3TR_C_ACTIVE_HIGH;
break;
+
case LSM6DS3TR_C_ACTIVE_LOW:
*val = LSM6DS3TR_C_ACTIVE_LOW;
break;
+
default:
*val = LSM6DS3TR_C_POLARITY_ND;
break;
@@ -2605,11 +3171,16 @@ int32_t lsm6ds3tr_c_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3tr_c_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
ctrl4_c.int2_on_int1 = val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -2626,7 +3197,8 @@ int32_t lsm6ds3tr_c_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3tr_c_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.int2_on_int1;
return ret;
@@ -2640,16 +3212,22 @@ int32_t lsm6ds3tr_c_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_int_notification_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_lir_t val)
+int32_t lsm6ds3tr_c_int_notification_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_lir_t val)
{
lsm6ds3tr_c_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG,
+ (uint8_t *)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
tap_cfg.lir = (uint8_t) val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG,
+ (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -2661,19 +3239,25 @@ int32_t lsm6ds3tr_c_int_notification_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_lir_t va
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_int_notification_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_lir_t *val)
+int32_t lsm6ds3tr_c_int_notification_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_lir_t *val)
{
lsm6ds3tr_c_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- switch (tap_cfg.lir) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG,
+ (uint8_t *)&tap_cfg, 1);
+
+ switch (tap_cfg.lir)
+ {
case LSM6DS3TR_C_INT_PULSED:
*val = LSM6DS3TR_C_INT_PULSED;
break;
+
case LSM6DS3TR_C_INT_LATCHED:
*val = LSM6DS3TR_C_INT_LATCHED;
break;
+
default:
*val = LSM6DS3TR_C_INT_MODE;
break;
@@ -2708,12 +3292,16 @@ int32_t lsm6ds3tr_c_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3tr_c_wake_up_ths_t wake_up_ths;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_THS, (uint8_t*)&wake_up_ths, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_THS,
+ (uint8_t *)&wake_up_ths, 1);
+
+ if (ret == 0)
+ {
wake_up_ths.wk_ths = val;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
}
+
return ret;
}
@@ -2725,12 +3313,14 @@ int32_t lsm6ds3tr_c_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3tr_c_wkup_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3tr_c_wake_up_ths_t wake_up_ths;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_THS, (uint8_t*)&wake_up_ths, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_THS,
+ (uint8_t *)&wake_up_ths, 1);
*val = wake_up_ths.wk_ths;
return ret;
@@ -2749,12 +3339,16 @@ int32_t lsm6ds3tr_c_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3tr_c_wake_up_dur_t wake_up_dur;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
wake_up_dur.wake_dur = val;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -2771,7 +3365,8 @@ int32_t lsm6ds3tr_c_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3tr_c_wake_up_dur_t wake_up_dur;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
*val = wake_up_dur.wake_dur;
return ret;
@@ -2803,11 +3398,16 @@ int32_t lsm6ds3tr_c_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3tr_c_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
ctrl4_c.sleep = val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -2824,7 +3424,8 @@ int32_t lsm6ds3tr_c_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3tr_c_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.sleep;
return ret;
@@ -2838,16 +3439,22 @@ int32_t lsm6ds3tr_c_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_act_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_inact_en_t val)
+int32_t lsm6ds3tr_c_act_mode_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_inact_en_t val)
{
lsm6ds3tr_c_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG,
+ (uint8_t *)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
tap_cfg.inact_en = (uint8_t) val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG,
+ (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -2859,25 +3466,33 @@ int32_t lsm6ds3tr_c_act_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_inact_en_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_act_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_inact_en_t *val)
+int32_t lsm6ds3tr_c_act_mode_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_inact_en_t *val)
{
lsm6ds3tr_c_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- switch (tap_cfg.inact_en) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG,
+ (uint8_t *)&tap_cfg, 1);
+
+ switch (tap_cfg.inact_en)
+ {
case LSM6DS3TR_C_PROPERTY_DISABLE:
*val = LSM6DS3TR_C_PROPERTY_DISABLE;
break;
+
case LSM6DS3TR_C_XL_12Hz5_GY_NOT_AFFECTED:
*val = LSM6DS3TR_C_XL_12Hz5_GY_NOT_AFFECTED;
break;
+
case LSM6DS3TR_C_XL_12Hz5_GY_SLEEP:
*val = LSM6DS3TR_C_XL_12Hz5_GY_SLEEP;
break;
+
case LSM6DS3TR_C_XL_12Hz5_GY_PD:
*val = LSM6DS3TR_C_XL_12Hz5_GY_PD;
break;
+
default:
*val = LSM6DS3TR_C_ACT_MODE_ND;
break;
@@ -2899,12 +3514,16 @@ int32_t lsm6ds3tr_c_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3tr_c_wake_up_dur_t wake_up_dur;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
wake_up_dur.sleep_dur = val;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -2921,7 +3540,8 @@ int32_t lsm6ds3tr_c_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3tr_c_wake_up_dur_t wake_up_dur;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
*val = wake_up_dur.sleep_dur;
return ret;
@@ -2948,10 +3568,13 @@ int32_t lsm6ds3tr_c_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_tap_src_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_tap_src_t *val)
+int32_t lsm6ds3tr_c_tap_src_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_tap_src_t *val)
{
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_SRC, (uint8_t*) val, 1);
+
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_SRC, (uint8_t *) val, 1);
+
return ret;
}
@@ -2962,16 +3585,22 @@ int32_t lsm6ds3tr_c_tap_src_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_tap_src_t *val)
* @param val Change the values of tap_z_en in reg TAP_CFG
*
*/
-int32_t lsm6ds3tr_c_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6ds3tr_c_tap_detection_on_z_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6ds3tr_c_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG,
+ (uint8_t *)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
tap_cfg.tap_z_en = val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG,
+ (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -2983,12 +3612,14 @@ int32_t lsm6ds3tr_c_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3tr_c_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3tr_c_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG,
+ (uint8_t *)&tap_cfg, 1);
*val = tap_cfg.tap_z_en;
return ret;
@@ -3002,16 +3633,22 @@ int32_t lsm6ds3tr_c_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6ds3tr_c_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6ds3tr_c_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG,
+ (uint8_t *)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
tap_cfg.tap_y_en = val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG,
+ (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -3023,12 +3660,14 @@ int32_t lsm6ds3tr_c_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3tr_c_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3tr_c_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG,
+ (uint8_t *)&tap_cfg, 1);
*val = tap_cfg.tap_y_en;
return ret;
@@ -3042,16 +3681,22 @@ int32_t lsm6ds3tr_c_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6ds3tr_c_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6ds3tr_c_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG,
+ (uint8_t *)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
tap_cfg.tap_x_en = val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG,
+ (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -3063,12 +3708,14 @@ int32_t lsm6ds3tr_c_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3tr_c_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3tr_c_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG,
+ (uint8_t *)&tap_cfg, 1);
*val = tap_cfg.tap_x_en;
return ret;
@@ -3082,17 +3729,22 @@ int32_t lsm6ds3tr_c_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6ds3tr_c_tap_threshold_x_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6ds3tr_c_tap_ths_6d_t tap_ths_6d;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_THS_6D,
+ (uint8_t *)&tap_ths_6d, 1);
+
+ if (ret == 0)
+ {
tap_ths_6d.tap_ths = val;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
+ (uint8_t *)&tap_ths_6d, 1);
}
+
return ret;
}
@@ -3104,12 +3756,14 @@ int32_t lsm6ds3tr_c_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3tr_c_tap_threshold_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3tr_c_tap_ths_6d_t tap_ths_6d;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_THS_6D,
+ (uint8_t *)&tap_ths_6d, 1);
*val = tap_ths_6d.tap_ths;
return ret;
@@ -3133,11 +3787,16 @@ int32_t lsm6ds3tr_c_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3tr_c_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT_DUR2, (uint8_t*)&int_dur2, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT_DUR2,
+ (uint8_t *)&int_dur2, 1);
+
+ if (ret == 0)
+ {
int_dur2.shock = val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_INT_DUR2,
+ (uint8_t *)&int_dur2, 1);
}
+
return ret;
}
@@ -3159,7 +3818,8 @@ int32_t lsm6ds3tr_c_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3tr_c_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT_DUR2,
+ (uint8_t *)&int_dur2, 1);
*val = int_dur2.shock;
return ret;
@@ -3183,11 +3843,16 @@ int32_t lsm6ds3tr_c_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3tr_c_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT_DUR2, (uint8_t*)&int_dur2, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT_DUR2,
+ (uint8_t *)&int_dur2, 1);
+
+ if (ret == 0)
+ {
int_dur2.quiet = val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_INT_DUR2,
+ (uint8_t *)&int_dur2, 1);
}
+
return ret;
}
@@ -3209,7 +3874,8 @@ int32_t lsm6ds3tr_c_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3tr_c_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT_DUR2,
+ (uint8_t *)&int_dur2, 1);
*val = int_dur2.quiet;
return ret;
@@ -3234,11 +3900,16 @@ int32_t lsm6ds3tr_c_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3tr_c_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT_DUR2, (uint8_t*)&int_dur2, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT_DUR2,
+ (uint8_t *)&int_dur2, 1);
+
+ if (ret == 0)
+ {
int_dur2.dur = val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_INT_DUR2,
+ (uint8_t *)&int_dur2, 1);
}
+
return ret;
}
@@ -3261,7 +3932,8 @@ int32_t lsm6ds3tr_c_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3tr_c_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT_DUR2,
+ (uint8_t *)&int_dur2, 1);
*val = int_dur2.dur;
return ret;
@@ -3277,17 +3949,21 @@ int32_t lsm6ds3tr_c_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6ds3tr_c_tap_mode_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_single_double_tap_t val)
+ lsm6ds3tr_c_single_double_tap_t val)
{
lsm6ds3tr_c_wake_up_ths_t wake_up_ths;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_THS, (uint8_t*)&wake_up_ths, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_THS,
+ (uint8_t *)&wake_up_ths, 1);
+
+ if (ret == 0)
+ {
wake_up_ths.single_double_tap = (uint8_t) val;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
}
+
return ret;
}
@@ -3301,19 +3977,24 @@ int32_t lsm6ds3tr_c_tap_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_tap_mode_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_single_double_tap_t *val)
+ lsm6ds3tr_c_single_double_tap_t *val)
{
lsm6ds3tr_c_wake_up_ths_t wake_up_ths;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_THS, (uint8_t*)&wake_up_ths, 1);
- switch (wake_up_ths.single_double_tap) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_THS,
+ (uint8_t *)&wake_up_ths, 1);
+
+ switch (wake_up_ths.single_double_tap)
+ {
case LSM6DS3TR_C_ONLY_SINGLE:
*val = LSM6DS3TR_C_ONLY_SINGLE;
break;
+
case LSM6DS3TR_C_BOTH_SINGLE_DOUBLE:
*val = LSM6DS3TR_C_BOTH_SINGLE_DOUBLE;
break;
+
default:
*val = LSM6DS3TR_C_TAP_MODE_ND;
break;
@@ -3345,16 +4026,21 @@ int32_t lsm6ds3tr_c_tap_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_6d_feed_data_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_low_pass_on_6d_t val)
+ lsm6ds3tr_c_low_pass_on_6d_t val)
{
lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
ctrl8_xl.low_pass_on_6d = (uint8_t) val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -3367,19 +4053,24 @@ int32_t lsm6ds3tr_c_6d_feed_data_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_6d_feed_data_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_low_pass_on_6d_t *val)
+ lsm6ds3tr_c_low_pass_on_6d_t *val)
{
lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- switch (ctrl8_xl.low_pass_on_6d) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL,
+ (uint8_t *)&ctrl8_xl, 1);
+
+ switch (ctrl8_xl.low_pass_on_6d)
+ {
case LSM6DS3TR_C_ODR_DIV_2_FEED:
*val = LSM6DS3TR_C_ODR_DIV_2_FEED;
break;
+
case LSM6DS3TR_C_LPF2_FEED:
*val = LSM6DS3TR_C_LPF2_FEED;
break;
+
default:
*val = LSM6DS3TR_C_6D_FEED_ND;
break;
@@ -3396,16 +4087,22 @@ int32_t lsm6ds3tr_c_6d_feed_data_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_6d_threshold_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_sixd_ths_t val)
+int32_t lsm6ds3tr_c_6d_threshold_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_sixd_ths_t val)
{
lsm6ds3tr_c_tap_ths_6d_t tap_ths_6d;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_THS_6D,
+ (uint8_t *)&tap_ths_6d, 1);
+
+ if (ret == 0)
+ {
tap_ths_6d.sixd_ths = (uint8_t) val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_THS_6D,
+ (uint8_t *)&tap_ths_6d, 1);
}
+
return ret;
}
@@ -3417,25 +4114,33 @@ int32_t lsm6ds3tr_c_6d_threshold_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_sixd_ths_t v
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_6d_threshold_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_sixd_ths_t *val)
+int32_t lsm6ds3tr_c_6d_threshold_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_sixd_ths_t *val)
{
lsm6ds3tr_c_tap_ths_6d_t tap_ths_6d;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1);
- switch (tap_ths_6d.sixd_ths) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_THS_6D,
+ (uint8_t *)&tap_ths_6d, 1);
+
+ switch (tap_ths_6d.sixd_ths)
+ {
case LSM6DS3TR_C_DEG_80:
*val = LSM6DS3TR_C_DEG_80;
break;
+
case LSM6DS3TR_C_DEG_70:
*val = LSM6DS3TR_C_DEG_70;
break;
+
case LSM6DS3TR_C_DEG_60:
*val = LSM6DS3TR_C_DEG_60;
break;
+
case LSM6DS3TR_C_DEG_50:
*val = LSM6DS3TR_C_DEG_50;
break;
+
default:
*val = LSM6DS3TR_C_6D_TH_ND;
break;
@@ -3457,12 +4162,16 @@ int32_t lsm6ds3tr_c_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3tr_c_tap_ths_6d_t tap_ths_6d;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_THS_6D,
+ (uint8_t *)&tap_ths_6d, 1);
+
+ if (ret == 0)
+ {
tap_ths_6d.d4d_en = val;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
+ (uint8_t *)&tap_ths_6d, 1);
}
+
return ret;
}
@@ -3479,7 +4188,8 @@ int32_t lsm6ds3tr_c_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3tr_c_tap_ths_6d_t tap_ths_6d;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_THS_6D,
+ (uint8_t *)&tap_ths_6d, 1);
*val = tap_ths_6d.d4d_en;
return ret;
@@ -3512,20 +4222,29 @@ int32_t lsm6ds3tr_c_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3tr_c_free_fall_t free_fall;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FREE_FALL, (uint8_t*)&free_fall, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FREE_FALL,
+ (uint8_t *)&free_fall, 1);
+
+ if (ret == 0)
+ {
free_fall.ff_dur = (val & 0x1FU);
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FREE_FALL, (uint8_t*)&free_fall, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FREE_FALL,
+ (uint8_t *)&free_fall, 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
wake_up_dur.ff_dur = (val & 0x20U) >> 5;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
}
}
+
return ret;
}
@@ -3543,10 +4262,15 @@ int32_t lsm6ds3tr_c_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3tr_c_free_fall_t free_fall;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FREE_FALL, (uint8_t*)&free_fall, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FREE_FALL,
+ (uint8_t *)&free_fall, 1);
}
+
*val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
return ret;
@@ -3560,16 +4284,22 @@ int32_t lsm6ds3tr_c_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_ff_threshold_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_ff_ths_t val)
+int32_t lsm6ds3tr_c_ff_threshold_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_ff_ths_t val)
{
lsm6ds3tr_c_free_fall_t free_fall;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FREE_FALL, (uint8_t*)&free_fall, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FREE_FALL,
+ (uint8_t *)&free_fall, 1);
+
+ if (ret == 0)
+ {
free_fall.ff_ths = (uint8_t) val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FREE_FALL, (uint8_t*)&free_fall, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FREE_FALL,
+ (uint8_t *)&free_fall, 1);
}
+
return ret;
}
@@ -3581,37 +4311,49 @@ int32_t lsm6ds3tr_c_ff_threshold_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_ff_ths_t val
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_ff_threshold_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_ff_ths_t *val)
+int32_t lsm6ds3tr_c_ff_threshold_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_ff_ths_t *val)
{
lsm6ds3tr_c_free_fall_t free_fall;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FREE_FALL, (uint8_t*)&free_fall, 1);
- switch (free_fall.ff_ths) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FREE_FALL,
+ (uint8_t *)&free_fall, 1);
+
+ switch (free_fall.ff_ths)
+ {
case LSM6DS3TR_C_FF_TSH_156mg:
*val = LSM6DS3TR_C_FF_TSH_156mg;
break;
+
case LSM6DS3TR_C_FF_TSH_219mg:
*val = LSM6DS3TR_C_FF_TSH_219mg;
break;
+
case LSM6DS3TR_C_FF_TSH_250mg:
*val = LSM6DS3TR_C_FF_TSH_250mg;
break;
+
case LSM6DS3TR_C_FF_TSH_312mg:
*val = LSM6DS3TR_C_FF_TSH_312mg;
break;
+
case LSM6DS3TR_C_FF_TSH_344mg:
*val = LSM6DS3TR_C_FF_TSH_344mg;
break;
+
case LSM6DS3TR_C_FF_TSH_406mg:
*val = LSM6DS3TR_C_FF_TSH_406mg;
break;
+
case LSM6DS3TR_C_FF_TSH_469mg:
*val = LSM6DS3TR_C_FF_TSH_469mg;
break;
+
case LSM6DS3TR_C_FF_TSH_500mg:
*val = LSM6DS3TR_C_FF_TSH_500mg;
break;
+
default:
*val = LSM6DS3TR_C_FF_TSH_ND;
break;
@@ -3641,22 +4383,30 @@ int32_t lsm6ds3tr_c_ff_threshold_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_ff_ths_t *va
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
+int32_t lsm6ds3tr_c_fifo_watermark_set(stmdev_ctx_t *ctx,
+ uint16_t val)
{
lsm6ds3tr_c_fifo_ctrl1_t fifo_ctrl1;
lsm6ds3tr_c_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
- fifo_ctrl1.fth = (uint8_t) (0x00FFU & val);
- fifo_ctrl2.fth = (uint8_t) (( 0x0700U & val ) >> 8);
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl1.fth = (uint8_t)(0x00FFU & val);
+ fifo_ctrl2.fth = (uint8_t)((0x0700U & val) >> 8);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL1,
+ (uint8_t *)&fifo_ctrl1, 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
}
+
return ret;
}
@@ -3668,16 +4418,22 @@ int32_t lsm6ds3tr_c_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
+int32_t lsm6ds3tr_c_fifo_watermark_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
lsm6ds3tr_c_fifo_ctrl1_t fifo_ctrl1;
lsm6ds3tr_c_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1);
- if(ret == 0){
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL1,
+ (uint8_t *)&fifo_ctrl1, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
}
+
*val = ((uint16_t)fifo_ctrl2.fth << 8) + (uint16_t)fifo_ctrl1.fth;
return ret;
@@ -3693,19 +4449,22 @@ int32_t lsm6ds3tr_c_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
+int32_t lsm6ds3tr_c_fifo_data_level_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
lsm6ds3tr_c_fifo_status1_t fifo_status1;
lsm6ds3tr_c_fifo_status2_t fifo_status2;
int32_t ret;
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_STATUS1,
- (uint8_t*)&fifo_status1, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_status1, 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
- *val = ( (uint16_t) fifo_status2.diff_fifo << 8) +
- (uint16_t) fifo_status1.diff_fifo;
+ (uint8_t *)&fifo_status2, 1);
+ *val = ((uint16_t) fifo_status2.diff_fifo << 8) +
+ (uint16_t) fifo_status1.diff_fifo;
}
return ret;
@@ -3724,7 +4483,8 @@ int32_t lsm6ds3tr_c_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3tr_c_fifo_status2_t fifo_status2;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_STATUS2, (uint8_t*)&fifo_status2, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_STATUS2,
+ (uint8_t *)&fifo_status2, 1);
*val = fifo_status2.waterm;
return ret;
@@ -3746,13 +4506,16 @@ int32_t lsm6ds3tr_c_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val)
int32_t ret;
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_STATUS3,
- (uint8_t*)&fifo_status3, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_status3, 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_STATUS4,
- (uint8_t*)&fifo_status4, 1);
- *val = ( (uint16_t)fifo_status4.fifo_pattern << 8) +
- fifo_status3.fifo_pattern;
+ (uint8_t *)&fifo_status4, 1);
+ *val = ((uint16_t)fifo_status4.fifo_pattern << 8) +
+ fifo_status3.fifo_pattern;
}
+
return ret;
}
@@ -3764,16 +4527,20 @@ int32_t lsm6ds3tr_c_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6ds3tr_c_fifo_temp_batch_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6ds3tr_c_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl2.fifo_temp_en = val;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
return ret;
@@ -3787,12 +4554,14 @@ int32_t lsm6ds3tr_c_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3tr_c_fifo_temp_batch_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3tr_c_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
*val = fifo_ctrl2.fifo_temp_en;
return ret;
@@ -3808,24 +4577,31 @@ int32_t lsm6ds3tr_c_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6ds3tr_c_fifo_write_trigger_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_trigger_fifo_t val)
+ lsm6ds3tr_c_trigger_fifo_t val)
{
lsm6ds3tr_c_fifo_ctrl2_t fifo_ctrl2;
lsm6ds3tr_c_master_config_t master_config;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl2.timer_pedo_fifo_drdy = (uint8_t)val & 0x01U;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
master_config.data_valid_sel_fifo = (((uint8_t)val & 0x02U) >> 1);
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
}
}
@@ -3843,28 +4619,35 @@ int32_t lsm6ds3tr_c_fifo_write_trigger_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_fifo_write_trigger_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_trigger_fifo_t *val)
+ lsm6ds3tr_c_trigger_fifo_t *val)
{
lsm6ds3tr_c_fifo_ctrl2_t fifo_ctrl2;
lsm6ds3tr_c_master_config_t master_config;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
- switch ( ( fifo_ctrl2.timer_pedo_fifo_drdy << 1 ) +
- fifo_ctrl2. timer_pedo_fifo_drdy ) {
+ switch ((fifo_ctrl2.timer_pedo_fifo_drdy << 1) +
+ fifo_ctrl2. timer_pedo_fifo_drdy)
+ {
case LSM6DS3TR_C_TRG_XL_GY_DRDY:
*val = LSM6DS3TR_C_TRG_XL_GY_DRDY;
break;
+
case LSM6DS3TR_C_TRG_STEP_DETECT:
*val = LSM6DS3TR_C_TRG_STEP_DETECT;
break;
+
case LSM6DS3TR_C_TRG_SH_DRDY:
*val = LSM6DS3TR_C_TRG_SH_DRDY;
break;
+
default:
*val = LSM6DS3TR_C_TRG_SH_ND;
break;
@@ -3883,18 +4666,23 @@ int32_t lsm6ds3tr_c_fifo_write_trigger_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_fifo_pedo_and_timestamp_batch_set(stmdev_ctx_t *ctx,
- uint8_t val)
+int32_t lsm6ds3tr_c_fifo_pedo_and_timestamp_batch_set(
+ stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6ds3tr_c_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl2.timer_pedo_fifo_en = val;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
+
return ret;
}
@@ -3907,13 +4695,15 @@ int32_t lsm6ds3tr_c_fifo_pedo_and_timestamp_batch_set(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_fifo_pedo_and_timestamp_batch_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+int32_t lsm6ds3tr_c_fifo_pedo_and_timestamp_batch_get(
+ stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3tr_c_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
*val = fifo_ctrl2.timer_pedo_fifo_en;
return ret;
@@ -3929,17 +4719,21 @@ int32_t lsm6ds3tr_c_fifo_pedo_and_timestamp_batch_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_fifo_xl_batch_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_dec_fifo_xl_t val)
+ lsm6ds3tr_c_dec_fifo_xl_t val)
{
lsm6ds3tr_c_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL3, (uint8_t*)&fifo_ctrl3, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL3,
+ (uint8_t *)&fifo_ctrl3, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl3.dec_fifo_xl = (uint8_t)val;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
+ (uint8_t *)&fifo_ctrl3, 1);
}
+
return ret;
}
@@ -3953,37 +4747,48 @@ int32_t lsm6ds3tr_c_fifo_xl_batch_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_fifo_xl_batch_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_dec_fifo_xl_t *val)
+ lsm6ds3tr_c_dec_fifo_xl_t *val)
{
lsm6ds3tr_c_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL3, (uint8_t*)&fifo_ctrl3, 1);
- switch (fifo_ctrl3.dec_fifo_xl) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL3,
+ (uint8_t *)&fifo_ctrl3, 1);
+
+ switch (fifo_ctrl3.dec_fifo_xl)
+ {
case LSM6DS3TR_C_FIFO_XL_DISABLE:
*val = LSM6DS3TR_C_FIFO_XL_DISABLE;
break;
+
case LSM6DS3TR_C_FIFO_XL_NO_DEC:
*val = LSM6DS3TR_C_FIFO_XL_NO_DEC;
break;
+
case LSM6DS3TR_C_FIFO_XL_DEC_2:
*val = LSM6DS3TR_C_FIFO_XL_DEC_2;
break;
+
case LSM6DS3TR_C_FIFO_XL_DEC_3:
*val = LSM6DS3TR_C_FIFO_XL_DEC_3;
break;
+
case LSM6DS3TR_C_FIFO_XL_DEC_4:
*val = LSM6DS3TR_C_FIFO_XL_DEC_4;
break;
+
case LSM6DS3TR_C_FIFO_XL_DEC_8:
*val = LSM6DS3TR_C_FIFO_XL_DEC_8;
break;
+
case LSM6DS3TR_C_FIFO_XL_DEC_16:
*val = LSM6DS3TR_C_FIFO_XL_DEC_16;
break;
+
case LSM6DS3TR_C_FIFO_XL_DEC_32:
*val = LSM6DS3TR_C_FIFO_XL_DEC_32;
break;
+
default:
*val = LSM6DS3TR_C_FIFO_XL_DEC_ND;
break;
@@ -4002,16 +4807,21 @@ int32_t lsm6ds3tr_c_fifo_xl_batch_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_fifo_gy_batch_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_dec_fifo_gyro_t val)
+ lsm6ds3tr_c_dec_fifo_gyro_t val)
{
lsm6ds3tr_c_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL3, (uint8_t*)&fifo_ctrl3, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL3,
+ (uint8_t *)&fifo_ctrl3, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl3.dec_fifo_gyro = (uint8_t)val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL3, (uint8_t*)&fifo_ctrl3, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL3,
+ (uint8_t *)&fifo_ctrl3, 1);
}
+
return ret;
}
@@ -4025,37 +4835,48 @@ int32_t lsm6ds3tr_c_fifo_gy_batch_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_fifo_gy_batch_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_dec_fifo_gyro_t *val)
+ lsm6ds3tr_c_dec_fifo_gyro_t *val)
{
lsm6ds3tr_c_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL3, (uint8_t*)&fifo_ctrl3, 1);
- switch (fifo_ctrl3.dec_fifo_gyro) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL3,
+ (uint8_t *)&fifo_ctrl3, 1);
+
+ switch (fifo_ctrl3.dec_fifo_gyro)
+ {
case LSM6DS3TR_C_FIFO_GY_DISABLE:
*val = LSM6DS3TR_C_FIFO_GY_DISABLE;
break;
+
case LSM6DS3TR_C_FIFO_GY_NO_DEC:
*val = LSM6DS3TR_C_FIFO_GY_NO_DEC;
break;
+
case LSM6DS3TR_C_FIFO_GY_DEC_2:
*val = LSM6DS3TR_C_FIFO_GY_DEC_2;
break;
+
case LSM6DS3TR_C_FIFO_GY_DEC_3:
*val = LSM6DS3TR_C_FIFO_GY_DEC_3;
break;
+
case LSM6DS3TR_C_FIFO_GY_DEC_4:
*val = LSM6DS3TR_C_FIFO_GY_DEC_4;
break;
+
case LSM6DS3TR_C_FIFO_GY_DEC_8:
*val = LSM6DS3TR_C_FIFO_GY_DEC_8;
break;
+
case LSM6DS3TR_C_FIFO_GY_DEC_16:
*val = LSM6DS3TR_C_FIFO_GY_DEC_16;
break;
+
case LSM6DS3TR_C_FIFO_GY_DEC_32:
*val = LSM6DS3TR_C_FIFO_GY_DEC_32;
break;
+
default:
*val = LSM6DS3TR_C_FIFO_GY_DEC_ND;
break;
@@ -4074,17 +4895,21 @@ int32_t lsm6ds3tr_c_fifo_gy_batch_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_dec_ds3_fifo_t val)
+ lsm6ds3tr_c_dec_ds3_fifo_t val)
{
lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl4.dec_ds3_fifo = (uint8_t)val;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -4098,37 +4923,48 @@ int32_t lsm6ds3tr_c_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_dec_ds3_fifo_t *val)
+ lsm6ds3tr_c_dec_ds3_fifo_t *val)
{
lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
- switch (fifo_ctrl4.dec_ds3_fifo) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ switch (fifo_ctrl4.dec_ds3_fifo)
+ {
case LSM6DS3TR_C_FIFO_DS3_DISABLE:
*val = LSM6DS3TR_C_FIFO_DS3_DISABLE;
break;
+
case LSM6DS3TR_C_FIFO_DS3_NO_DEC:
*val = LSM6DS3TR_C_FIFO_DS3_NO_DEC;
break;
+
case LSM6DS3TR_C_FIFO_DS3_DEC_2:
*val = LSM6DS3TR_C_FIFO_DS3_DEC_2;
break;
+
case LSM6DS3TR_C_FIFO_DS3_DEC_3:
*val = LSM6DS3TR_C_FIFO_DS3_DEC_3;
break;
+
case LSM6DS3TR_C_FIFO_DS3_DEC_4:
*val = LSM6DS3TR_C_FIFO_DS3_DEC_4;
break;
+
case LSM6DS3TR_C_FIFO_DS3_DEC_8:
*val = LSM6DS3TR_C_FIFO_DS3_DEC_8;
break;
+
case LSM6DS3TR_C_FIFO_DS3_DEC_16:
*val = LSM6DS3TR_C_FIFO_DS3_DEC_16;
break;
+
case LSM6DS3TR_C_FIFO_DS3_DEC_32:
*val = LSM6DS3TR_C_FIFO_DS3_DEC_32;
break;
+
default:
*val = LSM6DS3TR_C_FIFO_DS3_DEC_ND;
break;
@@ -4147,17 +4983,21 @@ int32_t lsm6ds3tr_c_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_dec_ds4_fifo_t val)
+ lsm6ds3tr_c_dec_ds4_fifo_t val)
{
lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl4.dec_ds4_fifo = (uint8_t)val;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -4171,37 +5011,48 @@ int32_t lsm6ds3tr_c_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_dec_ds4_fifo_t *val)
+ lsm6ds3tr_c_dec_ds4_fifo_t *val)
{
lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
- switch (fifo_ctrl4.dec_ds4_fifo) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ switch (fifo_ctrl4.dec_ds4_fifo)
+ {
case LSM6DS3TR_C_FIFO_DS4_DISABLE:
*val = LSM6DS3TR_C_FIFO_DS4_DISABLE;
break;
+
case LSM6DS3TR_C_FIFO_DS4_NO_DEC:
*val = LSM6DS3TR_C_FIFO_DS4_NO_DEC;
break;
+
case LSM6DS3TR_C_FIFO_DS4_DEC_2:
*val = LSM6DS3TR_C_FIFO_DS4_DEC_2;
break;
+
case LSM6DS3TR_C_FIFO_DS4_DEC_3:
*val = LSM6DS3TR_C_FIFO_DS4_DEC_3;
break;
+
case LSM6DS3TR_C_FIFO_DS4_DEC_4:
*val = LSM6DS3TR_C_FIFO_DS4_DEC_4;
break;
+
case LSM6DS3TR_C_FIFO_DS4_DEC_8:
*val = LSM6DS3TR_C_FIFO_DS4_DEC_8;
break;
+
case LSM6DS3TR_C_FIFO_DS4_DEC_16:
*val = LSM6DS3TR_C_FIFO_DS4_DEC_16;
break;
+
case LSM6DS3TR_C_FIFO_DS4_DEC_32:
*val = LSM6DS3TR_C_FIFO_DS4_DEC_32;
break;
+
default:
*val = LSM6DS3TR_C_FIFO_DS4_DEC_ND;
break;
@@ -4218,16 +5069,22 @@ int32_t lsm6ds3tr_c_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6ds3tr_c_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl4.only_high_data = val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -4239,12 +5096,14 @@ int32_t lsm6ds3tr_c_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3tr_c_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
*val = fifo_ctrl4.only_high_data;
return ret;
@@ -4259,16 +5118,22 @@ int32_t lsm6ds3tr_c_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6ds3tr_c_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl4.stop_on_fth = val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -4281,12 +5146,14 @@ int32_t lsm6ds3tr_c_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3tr_c_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
*val = fifo_ctrl4.stop_on_fth;
return ret;
@@ -4300,16 +5167,22 @@ int32_t lsm6ds3tr_c_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_fifo_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_fifo_mode_t val)
+int32_t lsm6ds3tr_c_fifo_mode_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_fifo_mode_t val)
{
lsm6ds3tr_c_fifo_ctrl5_t fifo_ctrl5;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL5,
+ (uint8_t *)&fifo_ctrl5, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl5.fifo_mode = (uint8_t)val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL5,
+ (uint8_t *)&fifo_ctrl5, 1);
}
+
return ret;
}
@@ -4321,28 +5194,37 @@ int32_t lsm6ds3tr_c_fifo_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_fifo_mode_t val
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_fifo_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_fifo_mode_t *val)
+int32_t lsm6ds3tr_c_fifo_mode_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_fifo_mode_t *val)
{
lsm6ds3tr_c_fifo_ctrl5_t fifo_ctrl5;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1);
- switch (fifo_ctrl5.fifo_mode) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL5,
+ (uint8_t *)&fifo_ctrl5, 1);
+
+ switch (fifo_ctrl5.fifo_mode)
+ {
case LSM6DS3TR_C_BYPASS_MODE:
*val = LSM6DS3TR_C_BYPASS_MODE;
break;
+
case LSM6DS3TR_C_FIFO_MODE:
*val = LSM6DS3TR_C_FIFO_MODE;
break;
+
case LSM6DS3TR_C_STREAM_TO_FIFO_MODE:
*val = LSM6DS3TR_C_STREAM_TO_FIFO_MODE;
break;
+
case LSM6DS3TR_C_BYPASS_TO_STREAM_MODE:
*val = LSM6DS3TR_C_BYPASS_TO_STREAM_MODE;
break;
+
case LSM6DS3TR_C_STREAM_MODE:
*val = LSM6DS3TR_C_STREAM_MODE;
break;
+
default:
*val = LSM6DS3TR_C_FIFO_MODE_ND;
break;
@@ -4359,16 +5241,22 @@ int32_t lsm6ds3tr_c_fifo_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_fifo_mode_t *va
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_fifo_data_rate_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_fifo_t val)
+int32_t lsm6ds3tr_c_fifo_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_odr_fifo_t val)
{
lsm6ds3tr_c_fifo_ctrl5_t fifo_ctrl5;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL5,
+ (uint8_t *)&fifo_ctrl5, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl5.odr_fifo = (uint8_t)val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL5,
+ (uint8_t *)&fifo_ctrl5, 1);
}
+
return ret;
}
@@ -4380,46 +5268,61 @@ int32_t lsm6ds3tr_c_fifo_data_rate_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_fifo_t
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_fifo_data_rate_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_fifo_t *val)
+int32_t lsm6ds3tr_c_fifo_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_odr_fifo_t *val)
{
lsm6ds3tr_c_fifo_ctrl5_t fifo_ctrl5;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1);
- switch (fifo_ctrl5.odr_fifo) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL5,
+ (uint8_t *)&fifo_ctrl5, 1);
+
+ switch (fifo_ctrl5.odr_fifo)
+ {
case LSM6DS3TR_C_FIFO_DISABLE:
*val = LSM6DS3TR_C_FIFO_DISABLE;
break;
+
case LSM6DS3TR_C_FIFO_12Hz5:
*val = LSM6DS3TR_C_FIFO_12Hz5;
break;
+
case LSM6DS3TR_C_FIFO_26Hz:
*val = LSM6DS3TR_C_FIFO_26Hz;
break;
+
case LSM6DS3TR_C_FIFO_52Hz:
*val = LSM6DS3TR_C_FIFO_52Hz;
break;
+
case LSM6DS3TR_C_FIFO_104Hz:
*val = LSM6DS3TR_C_FIFO_104Hz;
break;
+
case LSM6DS3TR_C_FIFO_208Hz:
*val = LSM6DS3TR_C_FIFO_208Hz;
break;
+
case LSM6DS3TR_C_FIFO_416Hz:
*val = LSM6DS3TR_C_FIFO_416Hz;
break;
+
case LSM6DS3TR_C_FIFO_833Hz:
*val = LSM6DS3TR_C_FIFO_833Hz;
break;
+
case LSM6DS3TR_C_FIFO_1k66Hz:
*val = LSM6DS3TR_C_FIFO_1k66Hz;
break;
+
case LSM6DS3TR_C_FIFO_3k33Hz:
*val = LSM6DS3TR_C_FIFO_3k33Hz;
break;
+
case LSM6DS3TR_C_FIFO_6k66Hz:
*val = LSM6DS3TR_C_FIFO_6k66Hz;
break;
+
default:
*val = LSM6DS3TR_C_FIFO_RATE_ND;
break;
@@ -4449,16 +5352,22 @@ int32_t lsm6ds3tr_c_fifo_data_rate_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_fifo_t
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
- int32_t lsm6ds3tr_c_den_polarity_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_den_lh_t val)
+int32_t lsm6ds3tr_c_den_polarity_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_den_lh_t val)
{
lsm6ds3tr_c_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C,
+ (uint8_t *)&ctrl5_c, 1);
+
+ if (ret == 0)
+ {
ctrl5_c.den_lh = (uint8_t)val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL5_C,
+ (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -4470,19 +5379,25 @@ int32_t lsm6ds3tr_c_fifo_data_rate_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_fifo_t
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_den_polarity_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_den_lh_t *val)
+int32_t lsm6ds3tr_c_den_polarity_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_den_lh_t *val)
{
lsm6ds3tr_c_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- switch (ctrl5_c.den_lh) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C,
+ (uint8_t *)&ctrl5_c, 1);
+
+ switch (ctrl5_c.den_lh)
+ {
case LSM6DS3TR_C_DEN_ACT_LOW:
*val = LSM6DS3TR_C_DEN_ACT_LOW;
break;
+
case LSM6DS3TR_C_DEN_ACT_HIGH:
*val = LSM6DS3TR_C_DEN_ACT_HIGH;
break;
+
default:
*val = LSM6DS3TR_C_DEN_POL_ND;
break;
@@ -4499,16 +5414,22 @@ int32_t lsm6ds3tr_c_den_polarity_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_den_lh_t *va
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_den_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_den_mode_t val)
+int32_t lsm6ds3tr_c_den_mode_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_den_mode_t val)
{
lsm6ds3tr_c_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C,
+ (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
ctrl6_c.den_mode = (uint8_t)val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL6_C,
+ (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -4520,25 +5441,33 @@ int32_t lsm6ds3tr_c_den_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_den_mode_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_den_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_den_mode_t *val)
+int32_t lsm6ds3tr_c_den_mode_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_den_mode_t *val)
{
lsm6ds3tr_c_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- switch (ctrl6_c.den_mode) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C,
+ (uint8_t *)&ctrl6_c, 1);
+
+ switch (ctrl6_c.den_mode)
+ {
case LSM6DS3TR_C_DEN_DISABLE:
*val = LSM6DS3TR_C_DEN_DISABLE;
break;
+
case LSM6DS3TR_C_LEVEL_LETCHED:
*val = LSM6DS3TR_C_LEVEL_LETCHED;
break;
+
case LSM6DS3TR_C_LEVEL_TRIGGER:
*val = LSM6DS3TR_C_LEVEL_TRIGGER;
break;
+
case LSM6DS3TR_C_EDGE_TRIGGER:
*val = LSM6DS3TR_C_EDGE_TRIGGER;
break;
+
default:
*val = LSM6DS3TR_C_DEN_MODE_ND;
break;
@@ -4556,24 +5485,36 @@ int32_t lsm6ds3tr_c_den_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_den_mode_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_den_enable_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_den_xl_en_t val)
+int32_t lsm6ds3tr_c_den_enable_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_den_xl_en_t val)
{
lsm6ds3tr_c_ctrl4_c_t ctrl4_c;
lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
ctrl9_xl.den_xl_g = (uint8_t)val & 0x01U;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
ctrl4_c.den_xl_en = (uint8_t)val & 0x02U;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
}
}
}
+
return ret;
}
@@ -4586,25 +5527,35 @@ int32_t lsm6ds3tr_c_den_enable_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_den_xl_en_t va
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_den_enable_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_den_xl_en_t *val)
+int32_t lsm6ds3tr_c_den_enable_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_den_xl_en_t *val)
{
lsm6ds3tr_c_ctrl4_c_t ctrl4_c;
lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- switch ( ( ctrl4_c.den_xl_en << 1) + ctrl9_xl.den_xl_g ) {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
+
+ switch ((ctrl4_c.den_xl_en << 1) + ctrl9_xl.den_xl_g)
+ {
case LSM6DS3TR_C_STAMP_IN_GY_DATA:
*val = LSM6DS3TR_C_STAMP_IN_GY_DATA;
break;
+
case LSM6DS3TR_C_STAMP_IN_XL_DATA:
*val = LSM6DS3TR_C_STAMP_IN_XL_DATA;
break;
+
case LSM6DS3TR_C_STAMP_IN_GY_XL_DATA:
*val = LSM6DS3TR_C_STAMP_IN_GY_XL_DATA;
break;
+
default:
*val = LSM6DS3TR_C_DEN_STAMP_ND;
break;
@@ -4622,16 +5573,22 @@ int32_t lsm6ds3tr_c_den_enable_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_den_xl_en_t *v
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6ds3tr_c_den_mark_axis_z_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
ctrl9_xl.den_z = val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -4643,12 +5600,14 @@ int32_t lsm6ds3tr_c_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3tr_c_den_mark_axis_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
*val = ctrl9_xl.den_z;
return ret;
@@ -4662,16 +5621,22 @@ int32_t lsm6ds3tr_c_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6ds3tr_c_den_mark_axis_y_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
ctrl9_xl.den_y = val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -4683,12 +5648,14 @@ int32_t lsm6ds3tr_c_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3tr_c_den_mark_axis_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
*val = ctrl9_xl.den_y;
return ret;
@@ -4702,16 +5669,22 @@ int32_t lsm6ds3tr_c_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6ds3tr_c_den_mark_axis_x_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
ctrl9_xl.den_x = val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -4723,12 +5696,14 @@ int32_t lsm6ds3tr_c_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3tr_c_den_mark_axis_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
*val = ctrl9_xl.den_x;
return ret;
@@ -4754,16 +5729,22 @@ int32_t lsm6ds3tr_c_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6ds3tr_c_pedo_step_reset_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6ds3tr_c_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C,
+ (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
ctrl10_c.pedo_rst_step = val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL10_C,
+ (uint8_t *)&ctrl10_c, 1);
}
+
return ret;
}
@@ -4775,12 +5756,14 @@ int32_t lsm6ds3tr_c_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3tr_c_pedo_step_reset_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3tr_c_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C,
+ (uint8_t *)&ctrl10_c, 1);
*val = ctrl10_c.pedo_rst_step;
return ret;
@@ -4799,13 +5782,20 @@ int32_t lsm6ds3tr_c_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3tr_c_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C,
+ (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
ctrl10_c.pedo_en = val;
- if (val != 0x00U) {
+
+ if (val != 0x00U)
+ {
ctrl10_c.func_en = val;
}
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL10_C,
+ (uint8_t *)&ctrl10_c, 1);
}
return ret;
@@ -4824,7 +5814,8 @@ int32_t lsm6ds3tr_c_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3tr_c_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C,
+ (uint8_t *)&ctrl10_c, 1);
*val = ctrl10_c.pedo_en;
return ret;
@@ -4845,18 +5836,25 @@ int32_t lsm6ds3tr_c_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CONFIG_PEDO_THS_MIN,
- (uint8_t*)&config_pedo_ths_min, 1);
- if(ret == 0){
- config_pedo_ths_min.ths_min = val;
+ (uint8_t *)&config_pedo_ths_min, 1);
+
+ if (ret == 0)
+ {
+ config_pedo_ths_min.ths_min = val;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CONFIG_PEDO_THS_MIN,
- (uint8_t*)&config_pedo_ths_min, 1);
- if(ret == 0){
- ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
- }
+ (uint8_t *)&config_pedo_ths_min, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
+ }
+
return ret;
}
@@ -4868,20 +5866,26 @@ int32_t lsm6ds3tr_c_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3tr_c_pedo_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3tr_c_config_pedo_ths_min_t config_pedo_ths_min;
int32_t ret;
- ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CONFIG_PEDO_THS_MIN,
- (uint8_t*)&config_pedo_ths_min, 1);
- if(ret == 0){
- *val = config_pedo_ths_min.ths_min;
- ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
- }
+ ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CONFIG_PEDO_THS_MIN,
+ (uint8_t *)&config_pedo_ths_min, 1);
+
+ if (ret == 0)
+ {
+ *val = config_pedo_ths_min.ths_min;
+ ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
+ }
+
return ret;
}
@@ -4894,24 +5898,32 @@ int32_t lsm6ds3tr_c_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_pedo_full_scale_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_pedo_fs_t val)
+int32_t lsm6ds3tr_c_pedo_full_scale_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_pedo_fs_t val)
{
lsm6ds3tr_c_config_pedo_ths_min_t config_pedo_ths_min;
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CONFIG_PEDO_THS_MIN,
- (uint8_t*)&config_pedo_ths_min, 1);
- if(ret == 0){
- config_pedo_ths_min.pedo_fs = (uint8_t) val;
+ (uint8_t *)&config_pedo_ths_min, 1);
+
+ if (ret == 0)
+ {
+ config_pedo_ths_min.pedo_fs = (uint8_t) val;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CONFIG_PEDO_THS_MIN,
- (uint8_t*)&config_pedo_ths_min, 1);
- if(ret == 0){
+ (uint8_t *)&config_pedo_ths_min, 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
}
+
return ret;
}
@@ -4924,30 +5936,40 @@ int32_t lsm6ds3tr_c_pedo_full_scale_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_pedo_fs_t
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_pedo_full_scale_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_pedo_fs_t *val)
+int32_t lsm6ds3tr_c_pedo_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_pedo_fs_t *val)
{
lsm6ds3tr_c_config_pedo_ths_min_t config_pedo_ths_min;
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CONFIG_PEDO_THS_MIN,
- (uint8_t*)&config_pedo_ths_min, 1);
- if(ret == 0){
- switch (config_pedo_ths_min.pedo_fs) {
- case LSM6DS3TR_C_PEDO_AT_2g:
+ (uint8_t *)&config_pedo_ths_min, 1);
+
+ if (ret == 0)
+ {
+ switch (config_pedo_ths_min.pedo_fs)
+ {
+ case LSM6DS3TR_C_PEDO_AT_2g:
*val = LSM6DS3TR_C_PEDO_AT_2g;
break;
+
case LSM6DS3TR_C_PEDO_AT_4g:
*val = LSM6DS3TR_C_PEDO_AT_4g;
break;
+
default:
*val = LSM6DS3TR_C_PEDO_FS_ND;
break;
}
+
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
+
return ret;
}
@@ -4959,24 +5981,32 @@ int32_t lsm6ds3tr_c_pedo_full_scale_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_pedo_fs_t
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6ds3tr_c_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6ds3tr_c_pedo_deb_reg_t pedo_deb_reg;
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_PEDO_DEB_REG,
- (uint8_t*)&pedo_deb_reg, 1);
- if(ret == 0){
+ (uint8_t *)&pedo_deb_reg, 1);
+
+ if (ret == 0)
+ {
pedo_deb_reg.deb_step = val;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_PEDO_DEB_REG,
- (uint8_t*)&pedo_deb_reg, 1);
- if(ret == 0){
- ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
- }
+ (uint8_t *)&pedo_deb_reg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
+ }
+
return ret;
}
@@ -4988,20 +6018,25 @@ int32_t lsm6ds3tr_c_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3tr_c_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3tr_c_pedo_deb_reg_t pedo_deb_reg;
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_PEDO_DEB_REG,
- (uint8_t*)&pedo_deb_reg, 1);
- if(ret == 0){
- *val = pedo_deb_reg.deb_step;
- ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
- }
+ (uint8_t *)&pedo_deb_reg, 1);
+
+ if (ret == 0)
+ {
+ *val = pedo_deb_reg.deb_step;
+ ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
+ }
return ret;
}
@@ -5022,18 +6057,25 @@ int32_t lsm6ds3tr_c_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_PEDO_DEB_REG,
- (uint8_t*)&pedo_deb_reg, 1);
- if(ret == 0){
+ (uint8_t *)&pedo_deb_reg, 1);
+
+ if (ret == 0)
+ {
pedo_deb_reg.deb_time = val;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_PEDO_DEB_REG,
- (uint8_t*)&pedo_deb_reg, 1);
- if(ret == 0){
+ (uint8_t *)&pedo_deb_reg, 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
}
+
return ret;
}
@@ -5053,14 +6095,19 @@ int32_t lsm6ds3tr_c_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_PEDO_DEB_REG,
- (uint8_t*)&pedo_deb_reg, 1);
- if(ret == 0){
+ (uint8_t *)&pedo_deb_reg, 1);
+
+ if (ret == 0)
+ {
*val = pedo_deb_reg.deb_time;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
+
return ret;
}
@@ -5072,17 +6119,23 @@ int32_t lsm6ds3tr_c_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_pedo_steps_period_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6ds3tr_c_pedo_steps_period_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_STEP_COUNT_DELTA, buff, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
+
return ret;
}
@@ -5094,17 +6147,23 @@ int32_t lsm6ds3tr_c_pedo_steps_period_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_pedo_steps_period_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6ds3tr_c_pedo_steps_period_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_STEP_COUNT_DELTA, buff, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
+
return ret;
}
@@ -5134,14 +6193,21 @@ int32_t lsm6ds3tr_c_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3tr_c_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C,
+ (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
ctrl10_c.sign_motion_en = val;
- if (val != 0x00U) {
+
+ if (val != 0x00U)
+ {
ctrl10_c.func_en = val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL10_C,
+ (uint8_t *)&ctrl10_c, 1);
}
}
+
return ret;
}
@@ -5158,7 +6224,8 @@ int32_t lsm6ds3tr_c_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3tr_c_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C,
+ (uint8_t *)&ctrl10_c, 1);
*val = ctrl10_c.sign_motion_en;
return ret;
@@ -5172,17 +6239,23 @@ int32_t lsm6ds3tr_c_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_motion_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6ds3tr_c_motion_threshold_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SM_THS, buff, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
+
return ret;
}
@@ -5194,17 +6267,23 @@ int32_t lsm6ds3tr_c_motion_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_motion_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6ds3tr_c_motion_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SM_THS, buff, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
+
return ret;
}
@@ -5234,14 +6313,22 @@ int32_t lsm6ds3tr_c_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3tr_c_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C,
+ (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
ctrl10_c.tilt_en = val;
- if (val != 0x00U) {
+
+ if (val != 0x00U)
+ {
ctrl10_c.func_en = val;
}
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL10_C,
+ (uint8_t *)&ctrl10_c, 1);
}
+
return ret;
}
@@ -5258,7 +6345,8 @@ int32_t lsm6ds3tr_c_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3tr_c_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C,
+ (uint8_t *)&ctrl10_c, 1);
*val = ctrl10_c.tilt_en;
return ret;
@@ -5272,19 +6360,28 @@ int32_t lsm6ds3tr_c_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_wrist_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6ds3tr_c_wrist_tilt_sens_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6ds3tr_c_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C,
+ (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
ctrl10_c.wrist_tilt_en = val;
- if (val != 0x00U) {
+
+ if (val != 0x00U)
+ {
ctrl10_c.func_en = val;
}
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL10_C,
+ (uint8_t *)&ctrl10_c, 1);
}
+
return ret;
}
@@ -5296,12 +6393,14 @@ int32_t lsm6ds3tr_c_wrist_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_wrist_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3tr_c_wrist_tilt_sens_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3tr_c_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C,
+ (uint8_t *)&ctrl10_c, 1);
*val = ctrl10_c.wrist_tilt_en;
return ret;
@@ -5322,12 +6421,17 @@ int32_t lsm6ds3tr_c_tilt_latency_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_B);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_A_WRIST_TILT_LAT, buff, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
+
return ret;
}
@@ -5346,12 +6450,17 @@ int32_t lsm6ds3tr_c_tilt_latency_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_B);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_A_WRIST_TILT_LAT, buff, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
+
return ret;
}
@@ -5365,17 +6474,23 @@ int32_t lsm6ds3tr_c_tilt_latency_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_tilt_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6ds3tr_c_tilt_threshold_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_B);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_A_WRIST_TILT_THS, buff, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
+
return ret;
}
@@ -5389,17 +6504,23 @@ int32_t lsm6ds3tr_c_tilt_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_tilt_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6ds3tr_c_tilt_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_B);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_A_WRIST_TILT_THS, buff, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
+
return ret;
}
@@ -5412,18 +6533,23 @@ int32_t lsm6ds3tr_c_tilt_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
*/
int32_t lsm6ds3tr_c_tilt_src_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_a_wrist_tilt_mask_t *val)
+ lsm6ds3tr_c_a_wrist_tilt_mask_t *val)
{
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_B);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_A_WRIST_TILT_MASK,
- (uint8_t*) val, 1);
- if(ret == 0){
+ (uint8_t *) val, 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
+
return ret;
}
@@ -5436,20 +6562,24 @@ int32_t lsm6ds3tr_c_tilt_src_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_tilt_src_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_a_wrist_tilt_mask_t *val)
+ lsm6ds3tr_c_a_wrist_tilt_mask_t *val)
{
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_B);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_A_WRIST_TILT_MASK,
- (uint8_t*) val, 1);
- if(ret == 0){
+ (uint8_t *) val, 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
- return ret;
+ return ret;
}
/**
@@ -5478,11 +6608,16 @@ int32_t lsm6ds3tr_c_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
ctrl9_xl.soft_en = val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -5499,7 +6634,8 @@ int32_t lsm6ds3tr_c_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
*val = ctrl9_xl.soft_en;
return ret;
@@ -5520,22 +6656,32 @@ int32_t lsm6ds3tr_c_mag_hard_iron_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
master_config.iron_en = val;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
- if (val != 0x00U) {
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C,
+ (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
+ if (val != 0x00U)
+ {
ctrl10_c.func_en = val;
}
+
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL10_C,
- (uint8_t*)&ctrl10_c, 1);
+ (uint8_t *)&ctrl10_c, 1);
}
}
}
+
return ret;
}
@@ -5553,7 +6699,7 @@ int32_t lsm6ds3tr_c_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
*val = master_config.iron_en;
return ret;
@@ -5568,17 +6714,23 @@ int32_t lsm6ds3tr_c_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_mag_soft_iron_mat_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6ds3tr_c_mag_soft_iron_mat_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MAG_SI_XX, buff, 9);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
+
return ret;
}
@@ -5591,17 +6743,23 @@ int32_t lsm6ds3tr_c_mag_soft_iron_mat_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_mag_soft_iron_mat_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6ds3tr_c_mag_soft_iron_mat_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MAG_SI_XX, buff, 9);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
+
return ret;
}
@@ -5614,17 +6772,29 @@ int32_t lsm6ds3tr_c_mag_soft_iron_mat_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_mag_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6ds3tr_c_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
+ buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
+ buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
+ buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
+ buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
+ buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
+ buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MAG_OFFX_L, buff, 6);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
+
return ret;
}
@@ -5637,17 +6807,29 @@ int32_t lsm6ds3tr_c_mag_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_mag_offset_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6ds3tr_c_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MAG_OFFX_L, buff, 6);
- if(ret == 0){
+
+ if (ret == 0)
+ {
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
+
return ret;
}
@@ -5664,7 +6846,7 @@ int32_t lsm6ds3tr_c_mag_offset_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
*/
- /**
+/**
* @brief Enable function.[set]
*
* @param ctx Read / write interface definitions
@@ -5677,10 +6859,14 @@ int32_t lsm6ds3tr_c_func_en_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6ds3tr_c_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C,
+ (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
ctrl10_c.func_en = val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL10_C,
+ (uint8_t *)&ctrl10_c, 1);
}
return ret;
@@ -5695,18 +6881,22 @@ int32_t lsm6ds3tr_c_func_en_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6ds3tr_c_sh_sync_sens_frame_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6ds3tr_c_sensor_sync_time_frame_t sensor_sync_time_frame;
int32_t ret;
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SENSOR_SYNC_TIME_FRAME,
- (uint8_t*)&sensor_sync_time_frame, 1);
- if(ret == 0){
- sensor_sync_time_frame.tph = val;
+ (uint8_t *)&sensor_sync_time_frame, 1);
+
+ if (ret == 0)
+ {
+ sensor_sync_time_frame.tph = val;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SENSOR_SYNC_TIME_FRAME,
- (uint8_t*)&sensor_sync_time_frame, 1);
+ (uint8_t *)&sensor_sync_time_frame, 1);
}
+
return ret;
}
@@ -5719,13 +6909,14 @@ int32_t lsm6ds3tr_c_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3tr_c_sh_sync_sens_frame_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3tr_c_sensor_sync_time_frame_t sensor_sync_time_frame;
int32_t ret;
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SENSOR_SYNC_TIME_FRAME,
- (uint8_t*)&sensor_sync_time_frame, 1);
+ (uint8_t *)&sensor_sync_time_frame, 1);
*val = sensor_sync_time_frame.tph;
return ret;
@@ -5739,18 +6930,22 @@ int32_t lsm6ds3tr_c_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_rr_t val)
+int32_t lsm6ds3tr_c_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_rr_t val)
{
lsm6ds3tr_c_sensor_sync_res_ratio_t sensor_sync_res_ratio;
int32_t ret;
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SENSOR_SYNC_RES_RATIO,
- (uint8_t*)&sensor_sync_res_ratio, 1);
- if(ret == 0){
+ (uint8_t *)&sensor_sync_res_ratio, 1);
+
+ if (ret == 0)
+ {
sensor_sync_res_ratio.rr = (uint8_t) val;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SENSOR_SYNC_RES_RATIO,
- (uint8_t*)&sensor_sync_res_ratio, 1);
+ (uint8_t *)&sensor_sync_res_ratio, 1);
}
+
return ret;
}
@@ -5762,27 +6957,33 @@ int32_t lsm6ds3tr_c_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_rr_t v
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_rr_t *val)
+int32_t lsm6ds3tr_c_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_rr_t *val)
{
lsm6ds3tr_c_sensor_sync_res_ratio_t sensor_sync_res_ratio;
int32_t ret;
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SENSOR_SYNC_RES_RATIO,
- (uint8_t*)&sensor_sync_res_ratio, 1);
+ (uint8_t *)&sensor_sync_res_ratio, 1);
- switch ( sensor_sync_res_ratio.rr) {
+ switch (sensor_sync_res_ratio.rr)
+ {
case LSM6DS3TR_C_RES_RATIO_2_11:
*val = LSM6DS3TR_C_RES_RATIO_2_11;
break;
+
case LSM6DS3TR_C_RES_RATIO_2_12:
*val = LSM6DS3TR_C_RES_RATIO_2_12;
break;
+
case LSM6DS3TR_C_RES_RATIO_2_13:
*val = LSM6DS3TR_C_RES_RATIO_2_13;
break;
+
case LSM6DS3TR_C_RES_RATIO_2_14:
*val = LSM6DS3TR_C_RES_RATIO_2_14;
break;
+
default:
*val = LSM6DS3TR_C_RES_RATIO_ND;
break;
@@ -5805,12 +7006,15 @@ int32_t lsm6ds3tr_c_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
master_config.master_on = val;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
+
return ret;
}
@@ -5828,7 +7032,7 @@ int32_t lsm6ds3tr_c_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
*val = master_config.master_on;
return ret;
@@ -5842,18 +7046,22 @@ int32_t lsm6ds3tr_c_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6ds3tr_c_sh_pass_through_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6ds3tr_c_master_config_t master_config;
int32_t ret;
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
master_config.pass_through_mode = val;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
+
return ret;
}
@@ -5865,13 +7073,14 @@ int32_t lsm6ds3tr_c_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3tr_c_sh_pass_through_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3tr_c_master_config_t master_config;
int32_t ret;
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
*val = master_config.pass_through_mode;
return ret;
@@ -5885,17 +7094,20 @@ int32_t lsm6ds3tr_c_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_sh_pin_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_pull_up_en_t val)
+int32_t lsm6ds3tr_c_sh_pin_mode_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_pull_up_en_t val)
{
lsm6ds3tr_c_master_config_t master_config;
int32_t ret;
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
master_config.pull_up_en = (uint8_t) val;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
return ret;
@@ -5909,24 +7121,30 @@ int32_t lsm6ds3tr_c_sh_pin_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_pull_up_en_t
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_sh_pin_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_pull_up_en_t *val)
+int32_t lsm6ds3tr_c_sh_pin_mode_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_pull_up_en_t *val)
{
lsm6ds3tr_c_master_config_t master_config;
int32_t ret;
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- switch (master_config.pull_up_en) {
+ (uint8_t *)&master_config, 1);
+
+ switch (master_config.pull_up_en)
+ {
case LSM6DS3TR_C_EXT_PULL_UP:
*val = LSM6DS3TR_C_EXT_PULL_UP;
break;
+
case LSM6DS3TR_C_INTERNAL_PULL_UP:
*val = LSM6DS3TR_C_INTERNAL_PULL_UP;
break;
+
default:
*val = LSM6DS3TR_C_SH_PIN_MODE;
break;
}
+
return ret;
}
@@ -5939,18 +7157,21 @@ int32_t lsm6ds3tr_c_sh_pin_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_pull_up_en_t
*
*/
int32_t lsm6ds3tr_c_sh_syncro_mode_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_start_config_t val)
+ lsm6ds3tr_c_start_config_t val)
{
lsm6ds3tr_c_master_config_t master_config;
int32_t ret;
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
master_config.start_config = (uint8_t)val;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
+
return ret;
}
@@ -5963,20 +7184,24 @@ int32_t lsm6ds3tr_c_sh_syncro_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_sh_syncro_mode_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_start_config_t *val)
+ lsm6ds3tr_c_start_config_t *val)
{
lsm6ds3tr_c_master_config_t master_config;
int32_t ret;
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- switch (master_config.start_config) {
+ (uint8_t *)&master_config, 1);
+
+ switch (master_config.start_config)
+ {
case LSM6DS3TR_C_XL_GY_DRDY:
*val = LSM6DS3TR_C_XL_GY_DRDY;
break;
+
case LSM6DS3TR_C_EXT_ON_INT2_PIN:
*val = LSM6DS3TR_C_EXT_ON_INT2_PIN;
break;
+
default:
*val = LSM6DS3TR_C_SH_SYNCRO_ND;
break;
@@ -5993,18 +7218,22 @@ int32_t lsm6ds3tr_c_sh_syncro_mode_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_sh_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6ds3tr_c_sh_drdy_on_int1_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6ds3tr_c_master_config_t master_config;
int32_t ret;
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
master_config.drdy_on_int1 = val;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
+
return ret;
}
@@ -6016,13 +7245,14 @@ int32_t lsm6ds3tr_c_sh_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_sh_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3tr_c_sh_drdy_on_int1_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3tr_c_master_config_t master_config;
int32_t ret;
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
*val = master_config.drdy_on_int1;
return ret;
@@ -6037,15 +7267,19 @@ int32_t lsm6ds3tr_c_sh_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6ds3tr_c_sh_read_data_raw_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_emb_sh_read_t *val)
+ lsm6ds3tr_c_emb_sh_read_t *val)
{
int32_t ret;
+
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SENSORHUB1_REG,
- (uint8_t*)&(val->sh_byte_1), 12);
- if(ret == 0){
+ (uint8_t *) & (val->sh_byte_1), 12);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SENSORHUB13_REG,
- (uint8_t*)&(val->sh_byte_13), 6);
+ (uint8_t *) & (val->sh_byte_13), 6);
}
+
return ret;
}
@@ -6058,18 +7292,22 @@ int32_t lsm6ds3tr_c_sh_read_data_raw_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_sh_cmd_sens_sync_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6ds3tr_c_sh_cmd_sens_sync_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6ds3tr_c_master_cmd_code_t master_cmd_code;
int32_t ret;
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CMD_CODE,
- (uint8_t*)&master_cmd_code, 1);
- if(ret == 0){
+ (uint8_t *)&master_cmd_code, 1);
+
+ if (ret == 0)
+ {
master_cmd_code.master_cmd_code = val;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MASTER_CMD_CODE,
- (uint8_t*)&master_cmd_code, 1);
+ (uint8_t *)&master_cmd_code, 1);
}
+
return ret;
}
@@ -6082,13 +7320,14 @@ int32_t lsm6ds3tr_c_sh_cmd_sens_sync_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3tr_c_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3tr_c_master_cmd_code_t master_cmd_code;
int32_t ret;
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CMD_CODE,
- (uint8_t*)&master_cmd_code, 1);
+ (uint8_t *)&master_cmd_code, 1);
*val = master_cmd_code.master_cmd_code;
return ret;
@@ -6103,18 +7342,22 @@ int32_t lsm6ds3tr_c_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_sh_spi_sync_error_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6ds3tr_c_sh_spi_sync_error_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6ds3tr_c_sens_sync_spi_error_code_t sens_sync_spi_error_code;
int32_t ret;
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SENS_SYNC_SPI_ERROR_CODE,
- (uint8_t*)&sens_sync_spi_error_code, 1);
- if(ret == 0){
- sens_sync_spi_error_code.error_code = val;
+ (uint8_t *)&sens_sync_spi_error_code, 1);
+
+ if (ret == 0)
+ {
+ sens_sync_spi_error_code.error_code = val;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SENS_SYNC_SPI_ERROR_CODE,
- (uint8_t*)&sens_sync_spi_error_code, 1);
+ (uint8_t *)&sens_sync_spi_error_code, 1);
}
+
return ret;
}
@@ -6127,13 +7370,14 @@ int32_t lsm6ds3tr_c_sh_spi_sync_error_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_sh_spi_sync_error_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6ds3tr_c_sh_spi_sync_error_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6ds3tr_c_sens_sync_spi_error_code_t sens_sync_spi_error_code;
int32_t ret;
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SENS_SYNC_SPI_ERROR_CODE,
- (uint8_t*)&sens_sync_spi_error_code, 1);
+ (uint8_t *)&sens_sync_spi_error_code, 1);
*val = sens_sync_spi_error_code.error_code;
return ret;
@@ -6148,24 +7392,31 @@ int32_t lsm6ds3tr_c_sh_spi_sync_error_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6ds3tr_c_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_aux_sens_on_t val)
+ lsm6ds3tr_c_aux_sens_on_t val)
{
lsm6ds3tr_c_slave0_config_t slave0_config;
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave0_config, 1);
+
+ if (ret == 0)
+ {
slave0_config.aux_sens_on = (uint8_t) val;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave0_config, 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
}
+
return ret;
}
@@ -6178,33 +7429,43 @@ int32_t lsm6ds3tr_c_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_aux_sens_on_t *val)
+ lsm6ds3tr_c_aux_sens_on_t *val)
{
lsm6ds3tr_c_slave0_config_t slave0_config;
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
- if(ret == 0){
- switch (slave0_config.aux_sens_on) {
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE0_CONFIG,
+ (uint8_t *)&slave0_config, 1);
+
+ if (ret == 0)
+ {
+ switch (slave0_config.aux_sens_on)
+ {
case LSM6DS3TR_C_SLV_0:
*val = LSM6DS3TR_C_SLV_0;
break;
+
case LSM6DS3TR_C_SLV_0_1:
*val = LSM6DS3TR_C_SLV_0_1;
break;
+
case LSM6DS3TR_C_SLV_0_1_2:
*val = LSM6DS3TR_C_SLV_0_1_2;
break;
+
case LSM6DS3TR_C_SLV_0_1_2_3:
*val = LSM6DS3TR_C_SLV_0_1_2_3;
break;
+
default:
*val = LSM6DS3TR_C_SLV_EN_ND;
break;
}
+
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
@@ -6223,28 +7484,40 @@ int32_t lsm6ds3tr_c_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_sh_cfg_write(stmdev_ctx_t *ctx, lsm6ds3tr_c_sh_cfg_write_t *val)
+int32_t lsm6ds3tr_c_sh_cfg_write(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_sh_cfg_write_t *val)
{
lsm6ds3tr_c_slv0_add_t slv0_add;
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv0_add.slave0_add = val->slv0_add;
slv0_add.rw_0 = 0;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV0_ADD, (uint8_t*)&slv0_add, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV0_ADD,
+ (uint8_t *)&slv0_add, 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV0_SUBADD,
- &(val->slv0_subadd), 1);
- if(ret == 0){
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_DATAWRITE_SRC_MODE_SUB_SLV0,
- &(val->slv0_data), 1);
- if(ret == 0){
+ &(val->slv0_subadd), 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_write_reg(ctx,
+ LSM6DS3TR_C_DATAWRITE_SRC_MODE_SUB_SLV0,
+ &(val->slv0_data), 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
}
}
+
return ret;
}
@@ -6260,34 +7533,46 @@ int32_t lsm6ds3tr_c_sh_cfg_write(stmdev_ctx_t *ctx, lsm6ds3tr_c_sh_cfg_write_t *
*
*/
int32_t lsm6ds3tr_c_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_sh_cfg_read_t *val)
+ lsm6ds3tr_c_sh_cfg_read_t *val)
{
lsm6ds3tr_c_slave0_config_t slave0_config;
lsm6ds3tr_c_slv0_add_t slv0_add;
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv0_add.slave0_add = val->slv_add;
slv0_add.rw_0 = 1;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV0_ADD, (uint8_t*)&slv0_add, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV0_ADD,
+ (uint8_t *)&slv0_add, 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV0_SUBADD,
- &(val->slv_subadd), 1);
- if(ret == 0){
+ &(val->slv_subadd), 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
+ (uint8_t *)&slave0_config, 1);
slave0_config.slave0_numop = val->slv_len;
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave0_config, 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
}
}
}
+
return ret;
}
@@ -6303,34 +7588,46 @@ int32_t lsm6ds3tr_c_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_sh_cfg_read_t *val)
+ lsm6ds3tr_c_sh_cfg_read_t *val)
{
lsm6ds3tr_c_slave1_config_t slave1_config;
lsm6ds3tr_c_slv1_add_t slv1_add;
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv1_add.slave1_add = val->slv_add;
slv1_add.r_1 = 1;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV1_ADD, (uint8_t*)&slv1_add, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV1_ADD,
+ (uint8_t *)&slv1_add, 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV1_SUBADD,
- &(val->slv_subadd), 1);
- if(ret == 0){
+ &(val->slv_subadd), 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
+ (uint8_t *)&slave1_config, 1);
slave1_config.slave1_numop = val->slv_len;
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave1_config, 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
}
}
}
+
return ret;
}
@@ -6346,28 +7643,39 @@ int32_t lsm6ds3tr_c_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_sh_cfg_read_t *val)
+ lsm6ds3tr_c_sh_cfg_read_t *val)
{
lsm6ds3tr_c_slv2_add_t slv2_add;
lsm6ds3tr_c_slave2_config_t slave2_config;
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv2_add.slave2_add = val->slv_add;
slv2_add.r_2 = 1;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV2_ADD, (uint8_t*)&slv2_add, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV2_ADD,
+ (uint8_t *)&slv2_add, 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV2_SUBADD,
- &(val->slv_subadd), 1);
- if(ret == 0){
+ &(val->slv_subadd), 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE2_CONFIG,
- (uint8_t*)&slave2_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave2_config, 1);
+
+ if (ret == 0)
+ {
slave2_config.slave2_numop = val->slv_len;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE2_CONFIG,
- (uint8_t*)&slave2_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave2_config, 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
@@ -6390,34 +7698,46 @@ int32_t lsm6ds3tr_c_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_sh_cfg_read_t *val)
+ lsm6ds3tr_c_sh_cfg_read_t *val)
{
lsm6ds3tr_c_slave3_config_t slave3_config;
lsm6ds3tr_c_slv3_add_t slv3_add;
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv3_add.slave3_add = val->slv_add;
slv3_add.r_3 = 1;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV3_ADD, (uint8_t*)&slv3_add, 1);
- if(ret == 0){
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV3_ADD,
+ (uint8_t *)&slv3_add, 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV3_SUBADD,
- (uint8_t*)&(val->slv_subadd), 1);
- if(ret == 0){
+ (uint8_t *) & (val->slv_subadd), 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE3_CONFIG,
- (uint8_t*)&slave3_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave3_config, 1);
+
+ if (ret == 0)
+ {
slave3_config.slave3_numop = val->slv_len;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE3_CONFIG,
- (uint8_t*)&slave3_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave3_config, 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
}
}
}
+
return ret;
}
@@ -6431,24 +7751,31 @@ int32_t lsm6ds3tr_c_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_sh_slave_0_dec_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_slave0_rate_t val)
+ lsm6ds3tr_c_slave0_rate_t val)
{
lsm6ds3tr_c_slave0_config_t slave0_config;
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave0_config, 1);
+
+ if (ret == 0)
+ {
slave0_config.slave0_rate = (uint8_t) val;
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave0_config, 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
}
+
return ret;
}
@@ -6462,33 +7789,43 @@ int32_t lsm6ds3tr_c_sh_slave_0_dec_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_sh_slave_0_dec_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_slave0_rate_t *val)
+ lsm6ds3tr_c_slave0_rate_t *val)
{
lsm6ds3tr_c_slave0_config_t slave0_config;
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
- if(ret == 0){
- switch (slave0_config.slave0_rate) {
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE0_CONFIG,
+ (uint8_t *)&slave0_config, 1);
+
+ if (ret == 0)
+ {
+ switch (slave0_config.slave0_rate)
+ {
case LSM6DS3TR_C_SL0_NO_DEC:
*val = LSM6DS3TR_C_SL0_NO_DEC;
break;
+
case LSM6DS3TR_C_SL0_DEC_2:
*val = LSM6DS3TR_C_SL0_DEC_2;
break;
+
case LSM6DS3TR_C_SL0_DEC_4:
*val = LSM6DS3TR_C_SL0_DEC_4;
break;
+
case LSM6DS3TR_C_SL0_DEC_8:
*val = LSM6DS3TR_C_SL0_DEC_8;
break;
+
default:
*val = LSM6DS3TR_C_SL0_DEC_ND;
break;
}
+
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
@@ -6507,24 +7844,32 @@ int32_t lsm6ds3tr_c_sh_slave_0_dec_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6ds3tr_c_sh_write_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_write_once_t val)
+int32_t lsm6ds3tr_c_sh_write_mode_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_write_once_t val)
{
lsm6ds3tr_c_slave1_config_t slave1_config;
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
+ (uint8_t *)&slave1_config, 1);
slave1_config.write_once = (uint8_t) val;
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave1_config, 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
}
+
return ret;
}
@@ -6540,27 +7885,35 @@ int32_t lsm6ds3tr_c_sh_write_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_write_once_
*
*/
int32_t lsm6ds3tr_c_sh_write_mode_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_write_once_t *val)
+ lsm6ds3tr_c_write_once_t *val)
{
lsm6ds3tr_c_slave1_config_t slave1_config;
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
- if(ret == 0){
- switch (slave1_config.write_once) {
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG,
+ (uint8_t *)&slave1_config, 1);
+
+ if (ret == 0)
+ {
+ switch (slave1_config.write_once)
+ {
case LSM6DS3TR_C_EACH_SH_CYCLE:
*val = LSM6DS3TR_C_EACH_SH_CYCLE;
break;
+
case LSM6DS3TR_C_ONLY_FIRST_CYCLE:
*val = LSM6DS3TR_C_ONLY_FIRST_CYCLE;
break;
+
default:
*val = LSM6DS3TR_C_SH_WR_MODE_ND;
break;
}
+
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
@@ -6578,24 +7931,31 @@ int32_t lsm6ds3tr_c_sh_write_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_sh_slave_1_dec_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_slave1_rate_t val)
+ lsm6ds3tr_c_slave1_rate_t val)
{
lsm6ds3tr_c_slave1_config_t slave1_config;
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG,
+ (uint8_t *)&slave1_config, 1);
+
+ if (ret == 0)
+ {
slave1_config.slave1_rate = (uint8_t) val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
- if(ret == 0){
- ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG,
+ (uint8_t *)&slave1_config, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
}
+
return ret;
}
@@ -6608,33 +7968,43 @@ int32_t lsm6ds3tr_c_sh_slave_1_dec_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_sh_slave_1_dec_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_slave1_rate_t *val)
+ lsm6ds3tr_c_slave1_rate_t *val)
{
lsm6ds3tr_c_slave1_config_t slave1_config;
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
- if(ret == 0){
- switch (slave1_config.slave1_rate) {
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG,
+ (uint8_t *)&slave1_config, 1);
+
+ if (ret == 0)
+ {
+ switch (slave1_config.slave1_rate)
+ {
case LSM6DS3TR_C_SL1_NO_DEC:
*val = LSM6DS3TR_C_SL1_NO_DEC;
break;
+
case LSM6DS3TR_C_SL1_DEC_2:
*val = LSM6DS3TR_C_SL1_DEC_2;
break;
+
case LSM6DS3TR_C_SL1_DEC_4:
*val = LSM6DS3TR_C_SL1_DEC_4;
break;
+
case LSM6DS3TR_C_SL1_DEC_8:
*val = LSM6DS3TR_C_SL1_DEC_8;
break;
+
default:
*val = LSM6DS3TR_C_SL1_DEC_ND;
break;
}
+
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
@@ -6652,24 +8022,31 @@ int32_t lsm6ds3tr_c_sh_slave_1_dec_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_sh_slave_2_dec_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_slave2_rate_t val)
+ lsm6ds3tr_c_slave2_rate_t val)
{
lsm6ds3tr_c_slave2_config_t slave2_config;
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE2_CONFIG,
- (uint8_t*)&slave2_config, 1);
- if(ret == 0){
- slave2_config.slave2_rate =(uint8_t) val;
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE2_CONFIG,
- (uint8_t*)&slave2_config, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE2_CONFIG,
+ (uint8_t *)&slave2_config, 1);
+
+ if (ret == 0)
+ {
+ slave2_config.slave2_rate = (uint8_t) val;
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE2_CONFIG,
+ (uint8_t *)&slave2_config, 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
}
+
return ret;
}
@@ -6683,33 +8060,43 @@ int32_t lsm6ds3tr_c_sh_slave_2_dec_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_sh_slave_2_dec_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_slave2_rate_t *val)
+ lsm6ds3tr_c_slave2_rate_t *val)
{
lsm6ds3tr_c_slave2_config_t slave2_config;
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE2_CONFIG,
- (uint8_t*)&slave2_config, 1);
- if(ret == 0){
- switch (slave2_config.slave2_rate) {
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE2_CONFIG,
+ (uint8_t *)&slave2_config, 1);
+
+ if (ret == 0)
+ {
+ switch (slave2_config.slave2_rate)
+ {
case LSM6DS3TR_C_SL2_NO_DEC:
*val = LSM6DS3TR_C_SL2_NO_DEC;
break;
+
case LSM6DS3TR_C_SL2_DEC_2:
*val = LSM6DS3TR_C_SL2_DEC_2;
break;
+
case LSM6DS3TR_C_SL2_DEC_4:
*val = LSM6DS3TR_C_SL2_DEC_4;
break;
+
case LSM6DS3TR_C_SL2_DEC_8:
*val = LSM6DS3TR_C_SL2_DEC_8;
break;
+
default:
*val = LSM6DS3TR_C_SL2_DEC_ND;
break;
}
+
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
@@ -6727,24 +8114,31 @@ int32_t lsm6ds3tr_c_sh_slave_2_dec_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_sh_slave_3_dec_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_slave3_rate_t val)
+ lsm6ds3tr_c_slave3_rate_t val)
{
lsm6ds3tr_c_slave3_config_t slave3_config;
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE3_CONFIG,
- (uint8_t*)&slave3_config, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE3_CONFIG,
+ (uint8_t *)&slave3_config, 1);
slave3_config.slave3_rate = (uint8_t)val;
- if(ret == 0){
- ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE3_CONFIG,
- (uint8_t*)&slave3_config, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE3_CONFIG,
+ (uint8_t *)&slave3_config, 1);
+
+ if (ret == 0)
+ {
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
}
+
return ret;
}
@@ -6758,33 +8152,43 @@ int32_t lsm6ds3tr_c_sh_slave_3_dec_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6ds3tr_c_sh_slave_3_dec_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_slave3_rate_t *val)
+ lsm6ds3tr_c_slave3_rate_t *val)
{
lsm6ds3tr_c_slave3_config_t slave3_config;
int32_t ret;
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
- if(ret == 0){
- ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE3_CONFIG,
- (uint8_t*)&slave3_config, 1);
- if(ret == 0){
- switch (slave3_config.slave3_rate) {
+
+ if (ret == 0)
+ {
+ ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE3_CONFIG,
+ (uint8_t *)&slave3_config, 1);
+
+ if (ret == 0)
+ {
+ switch (slave3_config.slave3_rate)
+ {
case LSM6DS3TR_C_SL3_NO_DEC:
*val = LSM6DS3TR_C_SL3_NO_DEC;
break;
+
case LSM6DS3TR_C_SL3_DEC_2:
*val = LSM6DS3TR_C_SL3_DEC_2;
break;
+
case LSM6DS3TR_C_SL3_DEC_4:
*val = LSM6DS3TR_C_SL3_DEC_4;
break;
+
case LSM6DS3TR_C_SL3_DEC_8:
*val = LSM6DS3TR_C_SL3_DEC_8;
break;
+
default:
*val = LSM6DS3TR_C_SL3_DEC_ND;
break;
}
+
ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
}
}
@@ -6796,7 +8200,7 @@ int32_t lsm6ds3tr_c_sh_slave_3_dec_get(stmdev_ctx_t *ctx,
* @}
*
*/
-
+
/**
* @}
*
diff --git a/sensor/stmemsc/lsm6ds3tr_c_STdC/driver/lsm6ds3tr_c_reg.h b/sensor/stmemsc/lsm6ds3tr-c_STdC/driver/lsm6ds3tr_c_reg.h
similarity index 52%
rename from sensor/stmemsc/lsm6ds3tr_c_STdC/driver/lsm6ds3tr_c_reg.h
rename to sensor/stmemsc/lsm6ds3tr-c_STdC/driver/lsm6ds3tr_c_reg.h
index 9ea4569cd1758126fcb66bc00dda4d88f7ab3ed4..d483dca1af015e3b69f247231d558a6f446975fb 100644
--- a/sensor/stmemsc/lsm6ds3tr_c_STdC/driver/lsm6ds3tr_c_reg.h
+++ b/sensor/stmemsc/lsm6ds3tr-c_STdC/driver/lsm6ds3tr_c_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file lsm6ds3tr_c_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lsm6ds3tr_c_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lsm6ds3tr_c_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lsm6ds3tr_c_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LSM6DS3TR_C_DRIVER_H
#define LSM6DS3TR_C_DRIVER_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup LSM6DS3TR_C
@@ -35,6 +36,37 @@
*
*/
+/** @defgroup Endianness definitions
+ * @{
+ *
+ */
+
+#ifndef DRV_BYTE_ORDER
+#ifndef __BYTE_ORDER__
+
+#define DRV_LITTLE_ENDIAN 1234
+#define DRV_BIG_ENDIAN 4321
+
+/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
+ * by uncommenting the define which fits your platform endianness
+ */
+//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
+#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
+
+#else /* defined __BYTE_ORDER__ */
+
+#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
+#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
+#define DRV_BYTE_ORDER __BYTE_ORDER__
+
+#endif /* __BYTE_ORDER__*/
+#endif /* DRV_BYTE_ORDER */
+
+/**
+ * @}
+ *
+ */
+
/** @defgroup STMicroelectronics sensors common types
* @{
*
@@ -43,7 +75,9 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -52,6 +86,16 @@ typedef struct{
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} bitwise_t;
#define PROPERTY_DISABLE (0U)
@@ -65,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -89,7 +134,7 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
+ * You can create a sensor configuration by your own or using
* Unico / Unicleo tools available on STMicroelectronics
* web site.
*
@@ -97,7 +142,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -132,68 +178,129 @@ typedef struct {
*/
#define LSM6DS3TR_C_FUNC_CFG_ACCESS 0x01U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 5;
- uint8_t func_cfg_en : 3; /* func_cfg_en + func_cfg_en_b */
+uint8_t func_cfg_en :
+ 3; /* func_cfg_en + func_cfg_en_b */
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+uint8_t func_cfg_en :
+ 3; /* func_cfg_en + func_cfg_en_b */
+ uint8_t not_used_01 : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_func_cfg_access_t;
#define LSM6DS3TR_C_SENSOR_SYNC_TIME_FRAME 0x04U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tph : 4;
uint8_t not_used_01 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 4;
+ uint8_t tph : 4;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_sensor_sync_time_frame_t;
#define LSM6DS3TR_C_SENSOR_SYNC_RES_RATIO 0x05U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t rr : 2;
uint8_t not_used_01 : 6;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 6;
+ uint8_t rr : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_sensor_sync_res_ratio_t;
#define LSM6DS3TR_C_FIFO_CTRL1 0x06U
-typedef struct {
+typedef struct
+{
uint8_t fth : 8; /* + FIFO_CTRL2(fth) */
} lsm6ds3tr_c_fifo_ctrl1_t;
#define LSM6DS3TR_C_FIFO_CTRL2 0x07U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fth : 3; /* + FIFO_CTRL1(fth) */
uint8_t fifo_temp_en : 1;
uint8_t not_used_01 : 2;
uint8_t timer_pedo_fifo_drdy : 1;
uint8_t timer_pedo_fifo_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t timer_pedo_fifo_en : 1;
+ uint8_t timer_pedo_fifo_drdy : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t fifo_temp_en : 1;
+ uint8_t fth : 3; /* + FIFO_CTRL1(fth) */
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_fifo_ctrl2_t;
#define LSM6DS3TR_C_FIFO_CTRL3 0x08U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t dec_fifo_xl : 3;
uint8_t dec_fifo_gyro : 3;
uint8_t not_used_01 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 2;
+ uint8_t dec_fifo_gyro : 3;
+ uint8_t dec_fifo_xl : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_fifo_ctrl3_t;
#define LSM6DS3TR_C_FIFO_CTRL4 0x09U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t dec_ds3_fifo : 3;
uint8_t dec_ds4_fifo : 3;
uint8_t only_high_data : 1;
uint8_t stop_on_fth : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t stop_on_fth : 1;
+ uint8_t only_high_data : 1;
+ uint8_t dec_ds4_fifo : 3;
+ uint8_t dec_ds3_fifo : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_fifo_ctrl4_t;
#define LSM6DS3TR_C_FIFO_CTRL5 0x0AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fifo_mode : 3;
uint8_t odr_fifo : 4;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t odr_fifo : 4;
+ uint8_t fifo_mode : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_fifo_ctrl5_t;
#define LSM6DS3TR_C_DRDY_PULSE_CFG_G 0x0BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_wrist_tilt : 1;
uint8_t not_used_01 : 6;
uint8_t drdy_pulsed : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t drdy_pulsed : 1;
+ uint8_t not_used_01 : 6;
+ uint8_t int2_wrist_tilt : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_drdy_pulse_cfg_g_t;
#define LSM6DS3TR_C_INT1_CTRL 0x0DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_drdy_xl : 1;
uint8_t int1_drdy_g : 1;
uint8_t int1_boot : 1;
@@ -202,10 +309,22 @@ typedef struct {
uint8_t int1_full_flag : 1;
uint8_t int1_sign_mot : 1;
uint8_t int1_step_detector : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_step_detector : 1;
+ uint8_t int1_sign_mot : 1;
+ uint8_t int1_full_flag : 1;
+ uint8_t int1_fifo_ovr : 1;
+ uint8_t int1_fth : 1;
+ uint8_t int1_boot : 1;
+ uint8_t int1_drdy_g : 1;
+ uint8_t int1_drdy_xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_int1_ctrl_t;
#define LSM6DS3TR_C_INT2_CTRL 0x0EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_drdy_xl : 1;
uint8_t int2_drdy_g : 1;
uint8_t int2_drdy_temp : 1;
@@ -214,26 +333,53 @@ typedef struct {
uint8_t int2_full_flag : 1;
uint8_t int2_step_count_ov : 1;
uint8_t int2_step_delta : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_step_delta : 1;
+ uint8_t int2_step_count_ov : 1;
+ uint8_t int2_full_flag : 1;
+ uint8_t int2_fifo_ovr : 1;
+ uint8_t int2_fth : 1;
+ uint8_t int2_drdy_temp : 1;
+ uint8_t int2_drdy_g : 1;
+ uint8_t int2_drdy_xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_int2_ctrl_t;
#define LSM6DS3TR_C_WHO_AM_I 0x0FU
#define LSM6DS3TR_C_CTRL1_XL 0x10U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bw0_xl : 1;
uint8_t lpf1_bw_sel : 1;
uint8_t fs_xl : 2;
uint8_t odr_xl : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr_xl : 4;
+ uint8_t fs_xl : 2;
+ uint8_t lpf1_bw_sel : 1;
+ uint8_t bw0_xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_ctrl1_xl_t;
#define LSM6DS3TR_C_CTRL2_G 0x11U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t fs_g : 3; /* fs_g + fs_125 */
uint8_t odr_g : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr_g : 4;
+ uint8_t fs_g : 3; /* fs_g + fs_125 */
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_ctrl2_g_t;
#define LSM6DS3TR_C_CTRL3_C 0x12U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sw_reset : 1;
uint8_t ble : 1;
uint8_t if_inc : 1;
@@ -242,10 +388,22 @@ typedef struct {
uint8_t h_lactive : 1;
uint8_t bdu : 1;
uint8_t boot : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t boot : 1;
+ uint8_t bdu : 1;
+ uint8_t h_lactive : 1;
+ uint8_t pp_od : 1;
+ uint8_t sim : 1;
+ uint8_t if_inc : 1;
+ uint8_t ble : 1;
+ uint8_t sw_reset : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_ctrl3_c_t;
#define LSM6DS3TR_C_CTRL4_C 0x13U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t lpf1_sel_g : 1;
uint8_t i2c_disable : 1;
@@ -254,37 +412,78 @@ typedef struct {
uint8_t int2_on_int1 : 1;
uint8_t sleep : 1;
uint8_t den_xl_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t den_xl_en : 1;
+ uint8_t sleep : 1;
+ uint8_t int2_on_int1 : 1;
+ uint8_t den_drdy_int1 : 1;
+ uint8_t drdy_mask : 1;
+ uint8_t i2c_disable : 1;
+ uint8_t lpf1_sel_g : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_ctrl4_c_t;
#define LSM6DS3TR_C_CTRL5_C 0x14U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_xl : 2;
uint8_t st_g : 2;
uint8_t den_lh : 1;
uint8_t rounding : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t rounding : 3;
+ uint8_t den_lh : 1;
+ uint8_t st_g : 2;
+ uint8_t st_xl : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_ctrl5_c_t;
#define LSM6DS3TR_C_CTRL6_C 0x15U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ftype : 2;
uint8_t not_used_01 : 1;
uint8_t usr_off_w : 1;
uint8_t xl_hm_mode : 1;
- uint8_t den_mode : 3; /* trig_en + lvl_en + lvl2_en */
+uint8_t den_mode :
+ 3; /* trig_en + lvl_en + lvl2_en */
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+uint8_t den_mode :
+ 3; /* trig_en + lvl_en + lvl2_en */
+ uint8_t xl_hm_mode : 1;
+ uint8_t usr_off_w : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t ftype : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_ctrl6_c_t;
#define LSM6DS3TR_C_CTRL7_G 0x16U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t rounding_status : 1;
uint8_t not_used_02 : 1;
uint8_t hpm_g : 2;
uint8_t hp_en_g : 1;
uint8_t g_hm_mode : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t g_hm_mode : 1;
+ uint8_t hp_en_g : 1;
+ uint8_t hpm_g : 2;
+ uint8_t not_used_02 : 1;
+ uint8_t rounding_status : 1;
+ uint8_t not_used_01 : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_ctrl7_g_t;
#define LSM6DS3TR_C_CTRL8_XL 0x17U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t low_pass_on_6d : 1;
uint8_t not_used_01 : 1;
uint8_t hp_slope_xl_en : 1;
@@ -292,10 +491,21 @@ typedef struct {
uint8_t hp_ref_mode : 1;
uint8_t hpcf_xl : 2;
uint8_t lpf2_xl_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t lpf2_xl_en : 1;
+ uint8_t hpcf_xl : 2;
+ uint8_t hp_ref_mode : 1;
+ uint8_t input_composite : 1;
+ uint8_t hp_slope_xl_en : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t low_pass_on_6d : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_ctrl8_xl_t;
#define LSM6DS3TR_C_CTRL9_XL 0x18U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t soft_en : 1;
uint8_t not_used_02 : 1;
@@ -303,10 +513,21 @@ typedef struct {
uint8_t den_z : 1;
uint8_t den_y : 1;
uint8_t den_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t den_x : 1;
+ uint8_t den_y : 1;
+ uint8_t den_z : 1;
+ uint8_t den_xl_g : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t soft_en : 1;
+ uint8_t not_used_01 : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_ctrl9_xl_t;
#define LSM6DS3TR_C_CTRL10_C 0x19U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sign_motion_en : 1;
uint8_t pedo_rst_step : 1;
uint8_t func_en : 1;
@@ -315,10 +536,22 @@ typedef struct {
uint8_t timer_en : 1;
uint8_t not_used_01 : 1;
uint8_t wrist_tilt_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t wrist_tilt_en : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t timer_en : 1;
+ uint8_t pedo_en : 1;
+ uint8_t tilt_en : 1;
+ uint8_t func_en : 1;
+ uint8_t pedo_rst_step : 1;
+ uint8_t sign_motion_en : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_ctrl10_c_t;
#define LSM6DS3TR_C_MASTER_CONFIG 0x1AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t master_on : 1;
uint8_t iron_en : 1;
uint8_t pass_through_mode : 1;
@@ -327,10 +560,22 @@ typedef struct {
uint8_t not_used_01 : 1;
uint8_t data_valid_sel_fifo : 1;
uint8_t drdy_on_int1 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t drdy_on_int1 : 1;
+ uint8_t data_valid_sel_fifo : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t start_config : 1;
+ uint8_t pull_up_en : 1;
+ uint8_t pass_through_mode : 1;
+ uint8_t iron_en : 1;
+ uint8_t master_on : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_master_config_t;
#define LSM6DS3TR_C_WAKE_UP_SRC 0x1BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_wu : 1;
uint8_t y_wu : 1;
uint8_t x_wu : 1;
@@ -338,10 +583,21 @@ typedef struct {
uint8_t sleep_state_ia : 1;
uint8_t ff_ia : 1;
uint8_t not_used_01 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 2;
+ uint8_t ff_ia : 1;
+ uint8_t sleep_state_ia : 1;
+ uint8_t wu_ia : 1;
+ uint8_t x_wu : 1;
+ uint8_t y_wu : 1;
+ uint8_t z_wu : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_wake_up_src_t;
#define LSM6DS3TR_C_TAP_SRC 0x1CU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_tap : 1;
uint8_t y_tap : 1;
uint8_t x_tap : 1;
@@ -350,10 +606,22 @@ typedef struct {
uint8_t single_tap : 1;
uint8_t tap_ia : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t tap_ia : 1;
+ uint8_t single_tap : 1;
+ uint8_t double_tap : 1;
+ uint8_t tap_sign : 1;
+ uint8_t x_tap : 1;
+ uint8_t y_tap : 1;
+ uint8_t z_tap : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_tap_src_t;
#define LSM6DS3TR_C_D6D_SRC 0x1DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
uint8_t yl : 1;
@@ -362,14 +630,32 @@ typedef struct {
uint8_t zh : 1;
uint8_t d6d_ia : 1;
uint8_t den_drdy : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t den_drdy : 1;
+ uint8_t d6d_ia : 1;
+ uint8_t zh : 1;
+ uint8_t zl : 1;
+ uint8_t yh : 1;
+ uint8_t yl : 1;
+ uint8_t xh : 1;
+ uint8_t xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_d6d_src_t;
#define LSM6DS3TR_C_STATUS_REG 0x1EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlda : 1;
uint8_t gda : 1;
uint8_t tda : 1;
uint8_t not_used_01 : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 5;
+ uint8_t tda : 1;
+ uint8_t gda : 1;
+ uint8_t xlda : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_status_reg_t;
#define LSM6DS3TR_C_OUT_TEMP_L 0x20U
@@ -387,7 +673,9 @@ typedef struct {
#define LSM6DS3TR_C_OUTZ_L_XL 0x2CU
#define LSM6DS3TR_C_OUTZ_H_XL 0x2DU
#define LSM6DS3TR_C_SENSORHUB1_REG 0x2EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -396,10 +684,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_sensorhub1_reg_t;
#define LSM6DS3TR_C_SENSORHUB2_REG 0x2FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -408,10 +708,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_sensorhub2_reg_t;
#define LSM6DS3TR_C_SENSORHUB3_REG 0x30U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -420,10 +732,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_sensorhub3_reg_t;
#define LSM6DS3TR_C_SENSORHUB4_REG 0x31U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -432,10 +756,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_sensorhub4_reg_t;
#define LSM6DS3TR_C_SENSORHUB5_REG 0x32U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -444,10 +780,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_sensorhub5_reg_t;
#define LSM6DS3TR_C_SENSORHUB6_REG 0x33U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -456,10 +804,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_sensorhub6_reg_t;
#define LSM6DS3TR_C_SENSORHUB7_REG 0x34U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -468,10 +828,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_sensorhub7_reg_t;
#define LSM6DS3TR_C_SENSORHUB8_REG 0x35U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -480,10 +852,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_sensorhub8_reg_t;
#define LSM6DS3TR_C_SENSORHUB9_REG 0x36U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -492,10 +876,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_sensorhub9_reg_t;
#define LSM6DS3TR_C_SENSORHUB10_REG 0x37U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -504,10 +900,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_sensorhub10_reg_t;
#define LSM6DS3TR_C_SENSORHUB11_REG 0x38U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -516,10 +924,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_sensorhub11_reg_t;
#define LSM6DS3TR_C_SENSORHUB12_REG 0x39U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -528,32 +948,63 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_sensorhub12_reg_t;
#define LSM6DS3TR_C_FIFO_STATUS1 0x3AU
-typedef struct {
+typedef struct
+{
uint8_t diff_fifo : 8; /* + FIFO_STATUS2(diff_fifo) */
} lsm6ds3tr_c_fifo_status1_t;
#define LSM6DS3TR_C_FIFO_STATUS2 0x3BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t diff_fifo : 3; /* + FIFO_STATUS1(diff_fifo) */
uint8_t not_used_01 : 1;
uint8_t fifo_empty : 1;
uint8_t fifo_full_smart : 1;
uint8_t over_run : 1;
uint8_t waterm : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t waterm : 1;
+ uint8_t over_run : 1;
+ uint8_t fifo_full_smart : 1;
+ uint8_t fifo_empty : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t diff_fifo : 3; /* + FIFO_STATUS1(diff_fifo) */
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_fifo_status2_t;
#define LSM6DS3TR_C_FIFO_STATUS3 0x3CU
-typedef struct {
- uint8_t fifo_pattern : 8; /* + FIFO_STATUS4(fifo_pattern) */
+typedef struct
+{
+uint8_t fifo_pattern :
+ 8; /* + FIFO_STATUS4(fifo_pattern) */
} lsm6ds3tr_c_fifo_status3_t;
#define LSM6DS3TR_C_FIFO_STATUS4 0x3DU
-typedef struct {
- uint8_t fifo_pattern : 2; /* + FIFO_STATUS3(fifo_pattern) */
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+uint8_t fifo_pattern :
+ 2; /* + FIFO_STATUS3(fifo_pattern) */
+ uint8_t not_used_01 : 6;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used_01 : 6;
+uint8_t fifo_pattern :
+ 2; /* + FIFO_STATUS3(fifo_pattern) */
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_fifo_status4_t;
#define LSM6DS3TR_C_FIFO_DATA_OUT_L 0x3EU
@@ -567,7 +1018,9 @@ typedef struct {
#define LSM6DS3TR_C_STEP_COUNTER_H 0x4CU
#define LSM6DS3TR_C_SENSORHUB13_REG 0x4DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -576,10 +1029,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_sensorhub13_reg_t;
#define LSM6DS3TR_C_SENSORHUB14_REG 0x4EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -588,10 +1053,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_sensorhub14_reg_t;
#define LSM6DS3TR_C_SENSORHUB15_REG 0x4FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -600,10 +1077,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_sensorhub15_reg_t;
#define LSM6DS3TR_C_SENSORHUB16_REG 0x50U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -612,10 +1101,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_sensorhub16_reg_t;
#define LSM6DS3TR_C_SENSORHUB17_REG 0x51U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -624,10 +1125,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_sensorhub17_reg_t;
#define LSM6DS3TR_C_SENSORHUB18_REG 0x52U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -636,10 +1149,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_sensorhub18_reg_t;
#define LSM6DS3TR_C_FUNC_SRC1 0x53U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sensorhub_end_op : 1;
uint8_t si_end_op : 1;
uint8_t hi_fail : 1;
@@ -648,10 +1173,22 @@ typedef struct {
uint8_t tilt_ia : 1;
uint8_t sign_motion_ia : 1;
uint8_t step_count_delta_ia : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t step_count_delta_ia : 1;
+ uint8_t sign_motion_ia : 1;
+ uint8_t tilt_ia : 1;
+ uint8_t step_detected : 1;
+ uint8_t step_overflow : 1;
+ uint8_t hi_fail : 1;
+ uint8_t si_end_op : 1;
+ uint8_t sensorhub_end_op : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_func_src1_t;
#define LSM6DS3TR_C_FUNC_SRC2 0x54U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wrist_tilt_ia : 1;
uint8_t not_used_01 : 2;
uint8_t slave0_nack : 1;
@@ -659,10 +1196,21 @@ typedef struct {
uint8_t slave2_nack : 1;
uint8_t slave3_nack : 1;
uint8_t not_used_02 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 1;
+ uint8_t slave3_nack : 1;
+ uint8_t slave2_nack : 1;
+ uint8_t slave1_nack : 1;
+ uint8_t slave0_nack : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t wrist_tilt_ia : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_func_src2_t;
#define LSM6DS3TR_C_WRIST_TILT_IA 0x55U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t wrist_tilt_ia_zneg : 1;
uint8_t wrist_tilt_ia_zpos : 1;
@@ -670,10 +1218,21 @@ typedef struct {
uint8_t wrist_tilt_ia_ypos : 1;
uint8_t wrist_tilt_ia_xneg : 1;
uint8_t wrist_tilt_ia_xpos : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t wrist_tilt_ia_xpos : 1;
+ uint8_t wrist_tilt_ia_xneg : 1;
+ uint8_t wrist_tilt_ia_ypos : 1;
+ uint8_t wrist_tilt_ia_yneg : 1;
+ uint8_t wrist_tilt_ia_zpos : 1;
+ uint8_t wrist_tilt_ia_zneg : 1;
+ uint8_t not_used_01 : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_wrist_tilt_ia_t;
#define LSM6DS3TR_C_TAP_CFG 0x58U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lir : 1;
uint8_t tap_z_en : 1;
uint8_t tap_y_en : 1;
@@ -681,45 +1240,91 @@ typedef struct {
uint8_t slope_fds : 1;
uint8_t inact_en : 2;
uint8_t interrupts_enable : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t interrupts_enable : 1;
+ uint8_t inact_en : 2;
+ uint8_t slope_fds : 1;
+ uint8_t tap_x_en : 1;
+ uint8_t tap_y_en : 1;
+ uint8_t tap_z_en : 1;
+ uint8_t lir : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_tap_cfg_t;
#define LSM6DS3TR_C_TAP_THS_6D 0x59U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_ths : 5;
uint8_t sixd_ths : 2;
uint8_t d4d_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t d4d_en : 1;
+ uint8_t sixd_ths : 2;
+ uint8_t tap_ths : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_tap_ths_6d_t;
#define LSM6DS3TR_C_INT_DUR2 0x5AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shock : 2;
uint8_t quiet : 2;
uint8_t dur : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t dur : 4;
+ uint8_t quiet : 2;
+ uint8_t shock : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_int_dur2_t;
#define LSM6DS3TR_C_WAKE_UP_THS 0x5BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wk_ths : 6;
uint8_t not_used_01 : 1;
uint8_t single_double_tap : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t single_double_tap : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t wk_ths : 6;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_wake_up_ths_t;
#define LSM6DS3TR_C_WAKE_UP_DUR 0x5CU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sleep_dur : 4;
uint8_t timer_hr : 1;
uint8_t wake_dur : 2;
uint8_t ff_dur : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t ff_dur : 1;
+ uint8_t wake_dur : 2;
+ uint8_t timer_hr : 1;
+ uint8_t sleep_dur : 4;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_wake_up_dur_t;
#define LSM6DS3TR_C_FREE_FALL 0x5DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ths : 3;
uint8_t ff_dur : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t ff_dur : 5;
+ uint8_t ff_ths : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_free_fall_t;
#define LSM6DS3TR_C_MD1_CFG 0x5EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_timer : 1;
uint8_t int1_tilt : 1;
uint8_t int1_6d : 1;
@@ -728,10 +1333,22 @@ typedef struct {
uint8_t int1_wu : 1;
uint8_t int1_single_tap : 1;
uint8_t int1_inact_state : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_inact_state : 1;
+ uint8_t int1_single_tap : 1;
+ uint8_t int1_wu : 1;
+ uint8_t int1_ff : 1;
+ uint8_t int1_double_tap : 1;
+ uint8_t int1_6d : 1;
+ uint8_t int1_tilt : 1;
+ uint8_t int1_timer : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_md1_cfg_t;
#define LSM6DS3TR_C_MD2_CFG 0x5FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_iron : 1;
uint8_t int2_tilt : 1;
uint8_t int2_6d : 1;
@@ -740,15 +1357,27 @@ typedef struct {
uint8_t int2_wu : 1;
uint8_t int2_single_tap : 1;
uint8_t int2_inact_state : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_inact_state : 1;
+ uint8_t int2_single_tap : 1;
+ uint8_t int2_wu : 1;
+ uint8_t int2_ff : 1;
+ uint8_t int2_double_tap : 1;
+ uint8_t int2_6d : 1;
+ uint8_t int2_tilt : 1;
+ uint8_t int2_iron : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_md2_cfg_t;
#define LSM6DS3TR_C_MASTER_CMD_CODE 0x60U
-typedef struct {
+typedef struct
+{
uint8_t master_cmd_code : 8;
} lsm6ds3tr_c_master_cmd_code_t;
#define LSM6DS3TR_C_SENS_SYNC_SPI_ERROR_CODE 0x61U
-typedef struct {
+typedef struct
+{
uint8_t error_code : 8;
} lsm6ds3tr_c_sens_sync_spi_error_code_t;
@@ -762,96 +1391,168 @@ typedef struct {
#define LSM6DS3TR_C_Y_OFS_USR 0x74U
#define LSM6DS3TR_C_Z_OFS_USR 0x75U
#define LSM6DS3TR_C_SLV0_ADD 0x02U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t rw_0 : 1;
uint8_t slave0_add : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave0_add : 7;
+ uint8_t rw_0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_slv0_add_t;
#define LSM6DS3TR_C_SLV0_SUBADD 0x03U
-typedef struct {
+typedef struct
+{
uint8_t slave0_reg : 8;
} lsm6ds3tr_c_slv0_subadd_t;
#define LSM6DS3TR_C_SLAVE0_CONFIG 0x04U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave0_numop : 3;
uint8_t src_mode : 1;
uint8_t aux_sens_on : 2;
uint8_t slave0_rate : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave0_rate : 2;
+ uint8_t aux_sens_on : 2;
+ uint8_t src_mode : 1;
+ uint8_t slave0_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_slave0_config_t;
#define LSM6DS3TR_C_SLV1_ADD 0x05U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_1 : 1;
uint8_t slave1_add : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave1_add : 7;
+ uint8_t r_1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_slv1_add_t;
#define LSM6DS3TR_C_SLV1_SUBADD 0x06U
-typedef struct {
+typedef struct
+{
uint8_t slave1_reg : 8;
} lsm6ds3tr_c_slv1_subadd_t;
#define LSM6DS3TR_C_SLAVE1_CONFIG 0x07U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave1_numop : 3;
uint8_t not_used_01 : 2;
uint8_t write_once : 1;
uint8_t slave1_rate : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave1_rate : 2;
+ uint8_t write_once : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t slave1_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_slave1_config_t;
#define LSM6DS3TR_C_SLV2_ADD 0x08U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_2 : 1;
uint8_t slave2_add : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave2_add : 7;
+ uint8_t r_2 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_slv2_add_t;
#define LSM6DS3TR_C_SLV2_SUBADD 0x09U
-typedef struct {
+typedef struct
+{
uint8_t slave2_reg : 8;
} lsm6ds3tr_c_slv2_subadd_t;
#define LSM6DS3TR_C_SLAVE2_CONFIG 0x0AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave2_numop : 3;
uint8_t not_used_01 : 3;
uint8_t slave2_rate : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave2_rate : 2;
+ uint8_t not_used_01 : 3;
+ uint8_t slave2_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_slave2_config_t;
#define LSM6DS3TR_C_SLV3_ADD 0x0BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_3 : 1;
uint8_t slave3_add : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave3_add : 7;
+ uint8_t r_3 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_slv3_add_t;
#define LSM6DS3TR_C_SLV3_SUBADD 0x0CU
-typedef struct {
+typedef struct
+{
uint8_t slave3_reg : 8;
} lsm6ds3tr_c_slv3_subadd_t;
#define LSM6DS3TR_C_SLAVE3_CONFIG 0x0DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave3_numop : 3;
uint8_t not_used_01 : 3;
uint8_t slave3_rate : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave3_rate : 2;
+ uint8_t not_used_01 : 3;
+ uint8_t slave3_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_slave3_config_t;
#define LSM6DS3TR_C_DATAWRITE_SRC_MODE_SUB_SLV0 0x0EU
-typedef struct {
+typedef struct
+{
uint8_t slave_dataw : 8;
} lsm6ds3tr_c_datawrite_src_mode_sub_slv0_t;
#define LSM6DS3TR_C_CONFIG_PEDO_THS_MIN 0x0FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths_min : 5;
uint8_t not_used_01 : 2;
uint8_t pedo_fs : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t pedo_fs : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t ths_min : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_config_pedo_ths_min_t;
#define LSM6DS3TR_C_SM_THS 0x13U
#define LSM6DS3TR_C_PEDO_DEB_REG 0x14U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t deb_step : 3;
uint8_t deb_time : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t deb_time : 5;
+ uint8_t deb_step : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_pedo_deb_reg_t;
#define LSM6DS3TR_C_STEP_COUNT_DELTA 0x15U
@@ -873,7 +1574,9 @@ typedef struct {
#define LSM6DS3TR_C_A_WRIST_TILT_LAT 0x50U
#define LSM6DS3TR_C_A_WRIST_TILT_THS 0x54U
#define LSM6DS3TR_C_A_WRIST_TILT_MASK 0x59U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t wrist_tilt_mask_zneg : 1;
uint8_t wrist_tilt_mask_zpos : 1;
@@ -881,13 +1584,22 @@ typedef struct {
uint8_t wrist_tilt_mask_ypos : 1;
uint8_t wrist_tilt_mask_xneg : 1;
uint8_t wrist_tilt_mask_xpos : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t wrist_tilt_mask_xpos : 1;
+ uint8_t wrist_tilt_mask_xneg : 1;
+ uint8_t wrist_tilt_mask_ypos : 1;
+ uint8_t wrist_tilt_mask_yneg : 1;
+ uint8_t wrist_tilt_mask_zpos : 1;
+ uint8_t wrist_tilt_mask_zneg : 1;
+ uint8_t not_used_01 : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6ds3tr_c_a_wrist_tilt_mask_t;
/**
* @defgroup LSM6DS3TR_C_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -895,7 +1607,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
lsm6ds3tr_c_func_cfg_access_t func_cfg_access;
lsm6ds3tr_c_sensor_sync_time_frame_t sensor_sync_time_frame;
lsm6ds3tr_c_sensor_sync_res_ratio_t sensor_sync_res_ratio;
@@ -956,7 +1669,8 @@ typedef union{
lsm6ds3tr_c_md1_cfg_t md1_cfg;
lsm6ds3tr_c_md2_cfg_t md2_cfg;
lsm6ds3tr_c_master_cmd_code_t master_cmd_code;
- lsm6ds3tr_c_sens_sync_spi_error_code_t sens_sync_spi_error_code;
+ lsm6ds3tr_c_sens_sync_spi_error_code_t
+ sens_sync_spi_error_code;
lsm6ds3tr_c_slv0_add_t slv0_add;
lsm6ds3tr_c_slv0_subadd_t slv0_subadd;
lsm6ds3tr_c_slave0_config_t slave0_config;
@@ -969,7 +1683,8 @@ typedef union{
lsm6ds3tr_c_slv3_add_t slv3_add;
lsm6ds3tr_c_slv3_subadd_t slv3_subadd;
lsm6ds3tr_c_slave3_config_t slave3_config;
- lsm6ds3tr_c_datawrite_src_mode_sub_slv0_t datawrite_src_mode_sub_slv0;
+ lsm6ds3tr_c_datawrite_src_mode_sub_slv0_t
+ datawrite_src_mode_sub_slv0;
lsm6ds3tr_c_config_pedo_ths_min_t config_pedo_ths_min;
lsm6ds3tr_c_pedo_deb_reg_t pedo_deb_reg;
lsm6ds3tr_c_a_wrist_tilt_mask_t a_wrist_tilt_mask;
@@ -982,35 +1697,41 @@ typedef union{
*
*/
-int32_t lsm6ds3tr_c_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
- uint16_t len);
-int32_t lsm6ds3tr_c_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
- uint16_t len);
+int32_t lsm6ds3tr_c_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len);
+int32_t lsm6ds3tr_c_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len);
-extern float_t lsm6ds3tr_c_from_fs2g_to_mg(int16_t lsb);
-extern float_t lsm6ds3tr_c_from_fs4g_to_mg(int16_t lsb);
-extern float_t lsm6ds3tr_c_from_fs8g_to_mg(int16_t lsb);
-extern float_t lsm6ds3tr_c_from_fs16g_to_mg(int16_t lsb);
+float_t lsm6ds3tr_c_from_fs2g_to_mg(int16_t lsb);
+float_t lsm6ds3tr_c_from_fs4g_to_mg(int16_t lsb);
+float_t lsm6ds3tr_c_from_fs8g_to_mg(int16_t lsb);
+float_t lsm6ds3tr_c_from_fs16g_to_mg(int16_t lsb);
-extern float_t lsm6ds3tr_c_from_fs125dps_to_mdps(int16_t lsb);
-extern float_t lsm6ds3tr_c_from_fs250dps_to_mdps(int16_t lsb);
-extern float_t lsm6ds3tr_c_from_fs500dps_to_mdps(int16_t lsb);
-extern float_t lsm6ds3tr_c_from_fs1000dps_to_mdps(int16_t lsb);
-extern float_t lsm6ds3tr_c_from_fs2000dps_to_mdps(int16_t lsb);
+float_t lsm6ds3tr_c_from_fs125dps_to_mdps(int16_t lsb);
+float_t lsm6ds3tr_c_from_fs250dps_to_mdps(int16_t lsb);
+float_t lsm6ds3tr_c_from_fs500dps_to_mdps(int16_t lsb);
+float_t lsm6ds3tr_c_from_fs1000dps_to_mdps(int16_t lsb);
+float_t lsm6ds3tr_c_from_fs2000dps_to_mdps(int16_t lsb);
-extern float_t lsm6ds3tr_c_from_lsb_to_celsius(int16_t lsb);
+float_t lsm6ds3tr_c_from_lsb_to_celsius(int16_t lsb);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_2g = 0,
LSM6DS3TR_C_16g = 1,
LSM6DS3TR_C_4g = 2,
LSM6DS3TR_C_8g = 3,
LSM6DS3TR_C_XL_FS_ND = 4, /* ERROR CODE */
} lsm6ds3tr_c_fs_xl_t;
-int32_t lsm6ds3tr_c_xl_full_scale_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_fs_xl_t val);
-int32_t lsm6ds3tr_c_xl_full_scale_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_fs_xl_t *val);
+int32_t lsm6ds3tr_c_xl_full_scale_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_fs_xl_t val);
+int32_t lsm6ds3tr_c_xl_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_fs_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_XL_ODR_OFF = 0,
LSM6DS3TR_C_XL_ODR_12Hz5 = 1,
LSM6DS3TR_C_XL_ODR_26Hz = 2,
@@ -1025,10 +1746,13 @@ typedef enum {
LSM6DS3TR_C_XL_ODR_1Hz6 = 11,
LSM6DS3TR_C_XL_ODR_ND = 12, /* ERROR CODE */
} lsm6ds3tr_c_odr_xl_t;
-int32_t lsm6ds3tr_c_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_xl_t val);
-int32_t lsm6ds3tr_c_xl_data_rate_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_xl_t *val);
+int32_t lsm6ds3tr_c_xl_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_odr_xl_t val);
+int32_t lsm6ds3tr_c_xl_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_odr_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_250dps = 0,
LSM6DS3TR_C_125dps = 1,
LSM6DS3TR_C_500dps = 2,
@@ -1036,10 +1760,13 @@ typedef enum {
LSM6DS3TR_C_2000dps = 6,
LSM6DS3TR_C_GY_FS_ND = 7, /* ERROR CODE */
} lsm6ds3tr_c_fs_g_t;
-int32_t lsm6ds3tr_c_gy_full_scale_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_fs_g_t val);
-int32_t lsm6ds3tr_c_gy_full_scale_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_fs_g_t *val);
+int32_t lsm6ds3tr_c_gy_full_scale_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_fs_g_t val);
+int32_t lsm6ds3tr_c_gy_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_fs_g_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_GY_ODR_OFF = 0,
LSM6DS3TR_C_GY_ODR_12Hz5 = 1,
LSM6DS3TR_C_GY_ODR_26Hz = 2,
@@ -1053,53 +1780,62 @@ typedef enum {
LSM6DS3TR_C_GY_ODR_6k66Hz = 10,
LSM6DS3TR_C_GY_ODR_ND = 11, /* ERROR CODE */
} lsm6ds3tr_c_odr_g_t;
-int32_t lsm6ds3tr_c_gy_data_rate_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_g_t val);
-int32_t lsm6ds3tr_c_gy_data_rate_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_g_t *val);
-
-int32_t lsm6ds3tr_c_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3tr_c_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
-
-typedef enum {
+int32_t lsm6ds3tr_c_gy_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_odr_g_t val);
+int32_t lsm6ds3tr_c_gy_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_odr_g_t *val);
+
+int32_t lsm6ds3tr_c_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3tr_c_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+typedef enum
+{
LSM6DS3TR_C_LSb_1mg = 0,
LSM6DS3TR_C_LSb_16mg = 1,
LSM6DS3TR_C_WEIGHT_ND = 2,
} lsm6ds3tr_c_usr_off_w_t;
int32_t lsm6ds3tr_c_xl_offset_weight_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_usr_off_w_t val);
+ lsm6ds3tr_c_usr_off_w_t val);
int32_t lsm6ds3tr_c_xl_offset_weight_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_usr_off_w_t *val);
+ lsm6ds3tr_c_usr_off_w_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_XL_HIGH_PERFORMANCE = 0,
LSM6DS3TR_C_XL_NORMAL = 1,
LSM6DS3TR_C_XL_PW_MODE_ND = 2, /* ERROR CODE */
} lsm6ds3tr_c_xl_hm_mode_t;
int32_t lsm6ds3tr_c_xl_power_mode_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_xl_hm_mode_t val);
+ lsm6ds3tr_c_xl_hm_mode_t val);
int32_t lsm6ds3tr_c_xl_power_mode_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_xl_hm_mode_t *val);
+ lsm6ds3tr_c_xl_hm_mode_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_STAT_RND_DISABLE = 0,
LSM6DS3TR_C_STAT_RND_ENABLE = 1,
LSM6DS3TR_C_STAT_RND_ND = 2, /* ERROR CODE */
} lsm6ds3tr_c_rounding_status_t;
int32_t lsm6ds3tr_c_rounding_on_status_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_rounding_status_t val);
+ lsm6ds3tr_c_rounding_status_t val);
int32_t lsm6ds3tr_c_rounding_on_status_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_rounding_status_t *val);
+ lsm6ds3tr_c_rounding_status_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_GY_HIGH_PERFORMANCE = 0,
LSM6DS3TR_C_GY_NORMAL = 1,
LSM6DS3TR_C_GY_PW_MODE_ND = 2, /* ERROR CODE */
} lsm6ds3tr_c_g_hm_mode_t;
int32_t lsm6ds3tr_c_gy_power_mode_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_g_hm_mode_t val);
+ lsm6ds3tr_c_g_hm_mode_t val);
int32_t lsm6ds3tr_c_gy_power_mode_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_g_hm_mode_t *val);
+ lsm6ds3tr_c_g_hm_mode_t *val);
-typedef struct {
+typedef struct
+{
lsm6ds3tr_c_wake_up_src_t wake_up_src;
lsm6ds3tr_c_tap_src_t tap_src;
lsm6ds3tr_c_d6d_src_t d6d_src;
@@ -1110,30 +1846,40 @@ typedef struct {
lsm6ds3tr_c_a_wrist_tilt_mask_t a_wrist_tilt_mask;
} lsm6ds3tr_c_all_sources_t;
int32_t lsm6ds3tr_c_all_sources_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_all_sources_t *val);
+ lsm6ds3tr_c_all_sources_t *val);
-int32_t lsm6ds3tr_c_status_reg_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_status_reg_t *val);
+int32_t lsm6ds3tr_c_status_reg_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_status_reg_t *val);
-int32_t lsm6ds3tr_c_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3tr_c_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6ds3tr_c_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3tr_c_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6ds3tr_c_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3tr_c_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6ds3tr_c_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6ds3tr_c_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6ds3tr_c_xl_usr_offset_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lsm6ds3tr_c_xl_usr_offset_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
int32_t lsm6ds3tr_c_timestamp_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3tr_c_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_LSB_6ms4 = 0,
LSM6DS3TR_C_LSB_25us = 1,
LSM6DS3TR_C_TS_RES_ND = 2, /* ERROR CODE */
} lsm6ds3tr_c_timer_hr_t;
-int32_t lsm6ds3tr_c_timestamp_res_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_timer_hr_t val);
-int32_t lsm6ds3tr_c_timestamp_res_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_timer_hr_t *val);
+int32_t lsm6ds3tr_c_timestamp_res_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_timer_hr_t val);
+int32_t lsm6ds3tr_c_timestamp_res_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_timer_hr_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_ROUND_DISABLE = 0,
LSM6DS3TR_C_ROUND_XL = 1,
LSM6DS3TR_C_ROUND_GY = 2,
@@ -1144,107 +1890,135 @@ typedef enum {
LSM6DS3TR_C_ROUND_GY_XL_SH1_TO_SH6 = 7,
LSM6DS3TR_C_ROUND_OUT_ND = 8, /* ERROR CODE */
} lsm6ds3tr_c_rounding_t;
-int32_t lsm6ds3tr_c_rounding_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_rounding_t val);
-int32_t lsm6ds3tr_c_rounding_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_rounding_t *val);
-
-int32_t lsm6ds3tr_c_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6ds3tr_c_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6ds3tr_c_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
-
-int32_t lsm6ds3tr_c_mag_calibrated_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
-
-int32_t lsm6ds3tr_c_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer,
- uint8_t len);
-
-typedef enum {
+int32_t lsm6ds3tr_c_rounding_mode_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_rounding_t val);
+int32_t lsm6ds3tr_c_rounding_mode_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_rounding_t *val);
+
+int32_t lsm6ds3tr_c_temperature_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
+int32_t lsm6ds3tr_c_angular_rate_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
+int32_t lsm6ds3tr_c_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
+
+int32_t lsm6ds3tr_c_mag_calibrated_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
+
+int32_t lsm6ds3tr_c_fifo_raw_data_get(stmdev_ctx_t *ctx,
+ uint8_t *buffer,
+ uint8_t len);
+
+typedef enum
+{
LSM6DS3TR_C_USER_BANK = 0,
LSM6DS3TR_C_BANK_A = 4,
LSM6DS3TR_C_BANK_B = 5,
LSM6DS3TR_C_BANK_ND = 6, /* ERROR CODE */
} lsm6ds3tr_c_func_cfg_en_t;
-int32_t lsm6ds3tr_c_mem_bank_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_func_cfg_en_t val);
-int32_t lsm6ds3tr_c_mem_bank_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_func_cfg_en_t *val);
+int32_t lsm6ds3tr_c_mem_bank_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_func_cfg_en_t val);
+int32_t lsm6ds3tr_c_mem_bank_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_func_cfg_en_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_DRDY_LATCHED = 0,
LSM6DS3TR_C_DRDY_PULSED = 1,
LSM6DS3TR_C_DRDY_ND = 2, /* ERROR CODE */
} lsm6ds3tr_c_drdy_pulsed_g_t;
int32_t lsm6ds3tr_c_data_ready_mode_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_drdy_pulsed_g_t val);
+ lsm6ds3tr_c_drdy_pulsed_g_t val);
int32_t lsm6ds3tr_c_data_ready_mode_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_drdy_pulsed_g_t *val);
+ lsm6ds3tr_c_drdy_pulsed_g_t *val);
int32_t lsm6ds3tr_c_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t lsm6ds3tr_c_reset_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3tr_c_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_LSB_AT_LOW_ADD = 0,
LSM6DS3TR_C_MSB_AT_LOW_ADD = 1,
LSM6DS3TR_C_DATA_FMT_ND = 2, /* ERROR CODE */
} lsm6ds3tr_c_ble_t;
-int32_t lsm6ds3tr_c_data_format_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_ble_t val);
-int32_t lsm6ds3tr_c_data_format_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_ble_t *val);
+int32_t lsm6ds3tr_c_data_format_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_ble_t val);
+int32_t lsm6ds3tr_c_data_format_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_ble_t *val);
-int32_t lsm6ds3tr_c_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3tr_c_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3tr_c_auto_increment_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3tr_c_auto_increment_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6ds3tr_c_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3tr_c_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_XL_ST_DISABLE = 0,
LSM6DS3TR_C_XL_ST_POSITIVE = 1,
LSM6DS3TR_C_XL_ST_NEGATIVE = 2,
LSM6DS3TR_C_XL_ST_ND = 3, /* ERROR CODE */
} lsm6ds3tr_c_st_xl_t;
-int32_t lsm6ds3tr_c_xl_self_test_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_st_xl_t val);
-int32_t lsm6ds3tr_c_xl_self_test_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_st_xl_t *val);
+int32_t lsm6ds3tr_c_xl_self_test_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_st_xl_t val);
+int32_t lsm6ds3tr_c_xl_self_test_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_st_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_GY_ST_DISABLE = 0,
LSM6DS3TR_C_GY_ST_POSITIVE = 1,
LSM6DS3TR_C_GY_ST_NEGATIVE = 3,
LSM6DS3TR_C_GY_ST_ND = 4, /* ERROR CODE */
} lsm6ds3tr_c_st_g_t;
-int32_t lsm6ds3tr_c_gy_self_test_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_st_g_t val);
-int32_t lsm6ds3tr_c_gy_self_test_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_st_g_t *val);
-
-int32_t lsm6ds3tr_c_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3tr_c_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val);
-
-typedef enum {
+int32_t lsm6ds3tr_c_gy_self_test_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_st_g_t val);
+int32_t lsm6ds3tr_c_gy_self_test_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_st_g_t *val);
+
+int32_t lsm6ds3tr_c_filter_settling_mask_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3tr_c_filter_settling_mask_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+typedef enum
+{
LSM6DS3TR_C_USE_SLOPE = 0,
LSM6DS3TR_C_USE_HPF = 1,
LSM6DS3TR_C_HP_PATH_ND = 2, /* ERROR CODE */
} lsm6ds3tr_c_slope_fds_t;
int32_t lsm6ds3tr_c_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_slope_fds_t val);
+ lsm6ds3tr_c_slope_fds_t val);
int32_t lsm6ds3tr_c_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_slope_fds_t *val);
+ lsm6ds3tr_c_slope_fds_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_XL_ANA_BW_1k5Hz = 0,
LSM6DS3TR_C_XL_ANA_BW_400Hz = 1,
LSM6DS3TR_C_XL_ANA_BW_ND = 2, /* ERROR CODE */
} lsm6ds3tr_c_bw0_xl_t;
int32_t lsm6ds3tr_c_xl_filter_analog_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_bw0_xl_t val);
+ lsm6ds3tr_c_bw0_xl_t val);
int32_t lsm6ds3tr_c_xl_filter_analog_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_bw0_xl_t *val);
+ lsm6ds3tr_c_bw0_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_XL_LP1_ODR_DIV_2 = 0,
LSM6DS3TR_C_XL_LP1_ODR_DIV_4 = 1,
LSM6DS3TR_C_XL_LP1_NA = 2, /* ERROR CODE */
} lsm6ds3tr_c_lpf1_bw_sel_t;
int32_t lsm6ds3tr_c_xl_lp1_bandwidth_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_lpf1_bw_sel_t val);
+ lsm6ds3tr_c_lpf1_bw_sel_t val);
int32_t lsm6ds3tr_c_xl_lp1_bandwidth_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_lpf1_bw_sel_t *val);
+ lsm6ds3tr_c_lpf1_bw_sel_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_50 = 0x00,
LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_100 = 0x01,
LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_9 = 0x02,
@@ -1256,14 +2030,17 @@ typedef enum {
LSM6DS3TR_C_XL_LP_NA = 0x20, /* ERROR CODE */
} lsm6ds3tr_c_input_composite_t;
int32_t lsm6ds3tr_c_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_input_composite_t val);
+ lsm6ds3tr_c_input_composite_t val);
int32_t lsm6ds3tr_c_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_input_composite_t *val);
+ lsm6ds3tr_c_input_composite_t *val);
-int32_t lsm6ds3tr_c_xl_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3tr_c_xl_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3tr_c_xl_reference_mode_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3tr_c_xl_reference_mode_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_XL_HP_ODR_DIV_4 = 0x00, /* Slope filter */
LSM6DS3TR_C_XL_HP_ODR_DIV_100 = 0x01,
LSM6DS3TR_C_XL_HP_ODR_DIV_9 = 0x02,
@@ -1271,11 +2048,12 @@ typedef enum {
LSM6DS3TR_C_XL_HP_NA = 0x10, /* ERROR CODE */
} lsm6ds3tr_c_hpcf_xl_t;
int32_t lsm6ds3tr_c_xl_hp_bandwidth_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_hpcf_xl_t val);
+ lsm6ds3tr_c_hpcf_xl_t val);
int32_t lsm6ds3tr_c_xl_hp_bandwidth_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_hpcf_xl_t *val);
+ lsm6ds3tr_c_hpcf_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_LP2_ONLY = 0x00,
LSM6DS3TR_C_HP_16mHz_LP2 = 0x80,
@@ -1296,29 +2074,34 @@ typedef enum {
LSM6DS3TR_C_HP_GY_BAND_NA = 0xFF, /* ERROR CODE */
} lsm6ds3tr_c_lpf1_sel_g_t;
int32_t lsm6ds3tr_c_gy_band_pass_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_lpf1_sel_g_t val);
+ lsm6ds3tr_c_lpf1_sel_g_t val);
int32_t lsm6ds3tr_c_gy_band_pass_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_lpf1_sel_g_t *val);
+ lsm6ds3tr_c_lpf1_sel_g_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_SPI_4_WIRE = 0,
LSM6DS3TR_C_SPI_3_WIRE = 1,
LSM6DS3TR_C_SPI_MODE_ND = 2, /* ERROR CODE */
} lsm6ds3tr_c_sim_t;
-int32_t lsm6ds3tr_c_spi_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_sim_t val);
-int32_t lsm6ds3tr_c_spi_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_sim_t *val);
+int32_t lsm6ds3tr_c_spi_mode_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_sim_t val);
+int32_t lsm6ds3tr_c_spi_mode_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_sim_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_I2C_ENABLE = 0,
LSM6DS3TR_C_I2C_DISABLE = 1,
LSM6DS3TR_C_I2C_MODE_ND = 2, /* ERROR CODE */
} lsm6ds3tr_c_i2c_disable_t;
int32_t lsm6ds3tr_c_i2c_interface_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_i2c_disable_t val);
+ lsm6ds3tr_c_i2c_disable_t val);
int32_t lsm6ds3tr_c_i2c_interface_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_i2c_disable_t *val);
+ lsm6ds3tr_c_i2c_disable_t *val);
-typedef struct {
+typedef struct
+{
uint8_t int1_drdy_xl : 1;
uint8_t int1_drdy_g : 1;
uint8_t int1_boot : 1;
@@ -1339,11 +2122,12 @@ typedef struct {
uint8_t drdy_on_int1 : 1;
} lsm6ds3tr_c_int1_route_t;
int32_t lsm6ds3tr_c_pin_int1_route_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_int1_route_t val);
+ lsm6ds3tr_c_int1_route_t val);
int32_t lsm6ds3tr_c_pin_int1_route_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_int1_route_t *val);
+ lsm6ds3tr_c_int1_route_t *val);
-typedef struct{
+typedef struct
+{
uint8_t int2_drdy_xl : 1;
uint8_t int2_drdy_g : 1;
uint8_t int2_drdy_temp : 1;
@@ -1363,72 +2147,97 @@ typedef struct{
uint8_t int2_wrist_tilt : 1;
} lsm6ds3tr_c_int2_route_t;
int32_t lsm6ds3tr_c_pin_int2_route_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_int2_route_t val);
+ lsm6ds3tr_c_int2_route_t val);
int32_t lsm6ds3tr_c_pin_int2_route_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_int2_route_t *val);
+ lsm6ds3tr_c_int2_route_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_PUSH_PULL = 0,
LSM6DS3TR_C_OPEN_DRAIN = 1,
LSM6DS3TR_C_PIN_MODE_ND = 2, /* ERROR CODE */
} lsm6ds3tr_c_pp_od_t;
-int32_t lsm6ds3tr_c_pin_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_pp_od_t val);
-int32_t lsm6ds3tr_c_pin_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_pp_od_t *val);
+int32_t lsm6ds3tr_c_pin_mode_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_pp_od_t val);
+int32_t lsm6ds3tr_c_pin_mode_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_pp_od_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_ACTIVE_HIGH = 0,
LSM6DS3TR_C_ACTIVE_LOW = 1,
LSM6DS3TR_C_POLARITY_ND = 2, /* ERROR CODE */
} lsm6ds3tr_c_h_lactive_t;
-int32_t lsm6ds3tr_c_pin_polarity_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_h_lactive_t val);
-int32_t lsm6ds3tr_c_pin_polarity_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_h_lactive_t *val);
+int32_t lsm6ds3tr_c_pin_polarity_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_h_lactive_t val);
+int32_t lsm6ds3tr_c_pin_polarity_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_h_lactive_t *val);
int32_t lsm6ds3tr_c_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3tr_c_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_INT_PULSED = 0,
LSM6DS3TR_C_INT_LATCHED = 1,
LSM6DS3TR_C_INT_MODE = 2, /* ERROR CODE */
} lsm6ds3tr_c_lir_t;
-int32_t lsm6ds3tr_c_int_notification_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_lir_t val);
-int32_t lsm6ds3tr_c_int_notification_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_lir_t *val);
+int32_t lsm6ds3tr_c_int_notification_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_lir_t val);
+int32_t lsm6ds3tr_c_int_notification_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_lir_t *val);
-int32_t lsm6ds3tr_c_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3tr_c_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3tr_c_wkup_threshold_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3tr_c_wkup_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6ds3tr_c_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3tr_c_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6ds3tr_c_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3tr_c_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3tr_c_gy_sleep_mode_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_PROPERTY_DISABLE = 0,
LSM6DS3TR_C_XL_12Hz5_GY_NOT_AFFECTED = 1,
LSM6DS3TR_C_XL_12Hz5_GY_SLEEP = 2,
LSM6DS3TR_C_XL_12Hz5_GY_PD = 3,
LSM6DS3TR_C_ACT_MODE_ND = 4, /* ERROR CODE */
} lsm6ds3tr_c_inact_en_t;
-int32_t lsm6ds3tr_c_act_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_inact_en_t val);
-int32_t lsm6ds3tr_c_act_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_inact_en_t *val);
+int32_t lsm6ds3tr_c_act_mode_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_inact_en_t val);
+int32_t lsm6ds3tr_c_act_mode_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_inact_en_t *val);
int32_t lsm6ds3tr_c_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3tr_c_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3tr_c_act_sleep_dur_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6ds3tr_c_tap_src_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_tap_src_t *val);
+int32_t lsm6ds3tr_c_tap_src_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_tap_src_t *val);
-int32_t lsm6ds3tr_c_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3tr_c_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3tr_c_tap_detection_on_z_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3tr_c_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6ds3tr_c_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3tr_c_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3tr_c_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3tr_c_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6ds3tr_c_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3tr_c_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3tr_c_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3tr_c_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6ds3tr_c_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3tr_c_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3tr_c_tap_threshold_x_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3tr_c_tap_threshold_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6ds3tr_c_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3tr_c_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1439,35 +2248,40 @@ int32_t lsm6ds3tr_c_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6ds3tr_c_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3tr_c_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_ONLY_SINGLE = 0,
LSM6DS3TR_C_BOTH_SINGLE_DOUBLE = 1,
LSM6DS3TR_C_TAP_MODE_ND = 2, /* ERROR CODE */
} lsm6ds3tr_c_single_double_tap_t;
int32_t lsm6ds3tr_c_tap_mode_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_single_double_tap_t val);
+ lsm6ds3tr_c_single_double_tap_t val);
int32_t lsm6ds3tr_c_tap_mode_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_single_double_tap_t *val);
+ lsm6ds3tr_c_single_double_tap_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_ODR_DIV_2_FEED = 0,
LSM6DS3TR_C_LPF2_FEED = 1,
LSM6DS3TR_C_6D_FEED_ND = 2, /* ERROR CODE */
} lsm6ds3tr_c_low_pass_on_6d_t;
int32_t lsm6ds3tr_c_6d_feed_data_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_low_pass_on_6d_t val);
+ lsm6ds3tr_c_low_pass_on_6d_t val);
int32_t lsm6ds3tr_c_6d_feed_data_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_low_pass_on_6d_t *val);
+ lsm6ds3tr_c_low_pass_on_6d_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_DEG_80 = 0,
LSM6DS3TR_C_DEG_70 = 1,
LSM6DS3TR_C_DEG_60 = 2,
LSM6DS3TR_C_DEG_50 = 3,
LSM6DS3TR_C_6D_TH_ND = 4, /* ERROR CODE */
} lsm6ds3tr_c_sixd_ths_t;
-int32_t lsm6ds3tr_c_6d_threshold_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_sixd_ths_t val);
-int32_t lsm6ds3tr_c_6d_threshold_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_sixd_ths_t *val);
+int32_t lsm6ds3tr_c_6d_threshold_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_sixd_ths_t val);
+int32_t lsm6ds3tr_c_6d_threshold_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_sixd_ths_t *val);
int32_t lsm6ds3tr_c_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3tr_c_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1475,7 +2289,8 @@ int32_t lsm6ds3tr_c_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6ds3tr_c_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3tr_c_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_FF_TSH_156mg = 0,
LSM6DS3TR_C_FF_TSH_219mg = 1,
LSM6DS3TR_C_FF_TSH_250mg = 2,
@@ -1486,38 +2301,51 @@ typedef enum {
LSM6DS3TR_C_FF_TSH_500mg = 7,
LSM6DS3TR_C_FF_TSH_ND = 8, /* ERROR CODE */
} lsm6ds3tr_c_ff_ths_t;
-int32_t lsm6ds3tr_c_ff_threshold_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_ff_ths_t val);
-int32_t lsm6ds3tr_c_ff_threshold_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_ff_ths_t *val);
+int32_t lsm6ds3tr_c_ff_threshold_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_ff_ths_t val);
+int32_t lsm6ds3tr_c_ff_threshold_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_ff_ths_t *val);
-int32_t lsm6ds3tr_c_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val);
-int32_t lsm6ds3tr_c_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t lsm6ds3tr_c_fifo_watermark_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t lsm6ds3tr_c_fifo_watermark_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
-int32_t lsm6ds3tr_c_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t lsm6ds3tr_c_fifo_data_level_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
-int32_t lsm6ds3tr_c_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3tr_c_fifo_wtm_flag_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6ds3tr_c_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t lsm6ds3tr_c_fifo_pattern_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
-int32_t lsm6ds3tr_c_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3tr_c_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3tr_c_fifo_temp_batch_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3tr_c_fifo_temp_batch_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_TRG_XL_GY_DRDY = 0,
LSM6DS3TR_C_TRG_STEP_DETECT = 1,
LSM6DS3TR_C_TRG_SH_DRDY = 2,
LSM6DS3TR_C_TRG_SH_ND = 3, /* ERROR CODE */
} lsm6ds3tr_c_trigger_fifo_t;
int32_t lsm6ds3tr_c_fifo_write_trigger_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_trigger_fifo_t val);
+ lsm6ds3tr_c_trigger_fifo_t val);
int32_t lsm6ds3tr_c_fifo_write_trigger_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_trigger_fifo_t *val);
+ lsm6ds3tr_c_trigger_fifo_t *val);
-int32_t lsm6ds3tr_c_fifo_pedo_and_timestamp_batch_set(stmdev_ctx_t *ctx,
- uint8_t val);
-int32_t lsm6ds3tr_c_fifo_pedo_and_timestamp_batch_get(stmdev_ctx_t *ctx,
- uint8_t *val);
+int32_t lsm6ds3tr_c_fifo_pedo_and_timestamp_batch_set(
+ stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3tr_c_fifo_pedo_and_timestamp_batch_get(
+ stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_FIFO_XL_DISABLE = 0,
LSM6DS3TR_C_FIFO_XL_NO_DEC = 1,
LSM6DS3TR_C_FIFO_XL_DEC_2 = 2,
@@ -1529,11 +2357,12 @@ typedef enum {
LSM6DS3TR_C_FIFO_XL_DEC_ND = 8, /* ERROR CODE */
} lsm6ds3tr_c_dec_fifo_xl_t;
int32_t lsm6ds3tr_c_fifo_xl_batch_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_dec_fifo_xl_t val);
+ lsm6ds3tr_c_dec_fifo_xl_t val);
int32_t lsm6ds3tr_c_fifo_xl_batch_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_dec_fifo_xl_t *val);
+ lsm6ds3tr_c_dec_fifo_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_FIFO_GY_DISABLE = 0,
LSM6DS3TR_C_FIFO_GY_NO_DEC = 1,
LSM6DS3TR_C_FIFO_GY_DEC_2 = 2,
@@ -1545,11 +2374,12 @@ typedef enum {
LSM6DS3TR_C_FIFO_GY_DEC_ND = 8, /* ERROR CODE */
} lsm6ds3tr_c_dec_fifo_gyro_t;
int32_t lsm6ds3tr_c_fifo_gy_batch_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_dec_fifo_gyro_t val);
+ lsm6ds3tr_c_dec_fifo_gyro_t val);
int32_t lsm6ds3tr_c_fifo_gy_batch_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_dec_fifo_gyro_t *val);
+ lsm6ds3tr_c_dec_fifo_gyro_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_FIFO_DS3_DISABLE = 0,
LSM6DS3TR_C_FIFO_DS3_NO_DEC = 1,
LSM6DS3TR_C_FIFO_DS3_DEC_2 = 2,
@@ -1561,11 +2391,12 @@ typedef enum {
LSM6DS3TR_C_FIFO_DS3_DEC_ND = 8, /* ERROR CODE */
} lsm6ds3tr_c_dec_ds3_fifo_t;
int32_t lsm6ds3tr_c_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_dec_ds3_fifo_t val);
+ lsm6ds3tr_c_dec_ds3_fifo_t val);
int32_t lsm6ds3tr_c_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_dec_ds3_fifo_t *val);
+ lsm6ds3tr_c_dec_ds3_fifo_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_FIFO_DS4_DISABLE = 0,
LSM6DS3TR_C_FIFO_DS4_NO_DEC = 1,
LSM6DS3TR_C_FIFO_DS4_DEC_2 = 2,
@@ -1577,17 +2408,22 @@ typedef enum {
LSM6DS3TR_C_FIFO_DS4_DEC_ND = 8, /* ERROR CODE */
} lsm6ds3tr_c_dec_ds4_fifo_t;
int32_t lsm6ds3tr_c_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_dec_ds4_fifo_t val);
+ lsm6ds3tr_c_dec_ds4_fifo_t val);
int32_t lsm6ds3tr_c_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_dec_ds4_fifo_t *val);
+ lsm6ds3tr_c_dec_ds4_fifo_t *val);
-int32_t lsm6ds3tr_c_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3tr_c_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3tr_c_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3tr_c_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6ds3tr_c_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3tr_c_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3tr_c_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3tr_c_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_BYPASS_MODE = 0,
LSM6DS3TR_C_FIFO_MODE = 1,
LSM6DS3TR_C_STREAM_TO_FIFO_MODE = 3,
@@ -1595,10 +2431,13 @@ typedef enum {
LSM6DS3TR_C_STREAM_MODE = 6,
LSM6DS3TR_C_FIFO_MODE_ND = 8, /* ERROR CODE */
} lsm6ds3tr_c_fifo_mode_t;
-int32_t lsm6ds3tr_c_fifo_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_fifo_mode_t val);
-int32_t lsm6ds3tr_c_fifo_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_fifo_mode_t *val);
+int32_t lsm6ds3tr_c_fifo_mode_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_fifo_mode_t val);
+int32_t lsm6ds3tr_c_fifo_mode_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_fifo_mode_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_FIFO_DISABLE = 0,
LSM6DS3TR_C_FIFO_12Hz5 = 1,
LSM6DS3TR_C_FIFO_26Hz = 2,
@@ -1613,19 +2452,23 @@ typedef enum {
LSM6DS3TR_C_FIFO_RATE_ND = 11, /* ERROR CODE */
} lsm6ds3tr_c_odr_fifo_t;
int32_t lsm6ds3tr_c_fifo_data_rate_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_odr_fifo_t val);
+ lsm6ds3tr_c_odr_fifo_t val);
int32_t lsm6ds3tr_c_fifo_data_rate_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_odr_fifo_t *val);
+ lsm6ds3tr_c_odr_fifo_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_DEN_ACT_LOW = 0,
LSM6DS3TR_C_DEN_ACT_HIGH = 1,
LSM6DS3TR_C_DEN_POL_ND = 2, /* ERROR CODE */
} lsm6ds3tr_c_den_lh_t;
-int32_t lsm6ds3tr_c_den_polarity_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_den_lh_t val);
-int32_t lsm6ds3tr_c_den_polarity_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_den_lh_t *val);
+int32_t lsm6ds3tr_c_den_polarity_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_den_lh_t val);
+int32_t lsm6ds3tr_c_den_polarity_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_den_lh_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_DEN_DISABLE = 0,
LSM6DS3TR_C_LEVEL_FIFO = 6,
LSM6DS3TR_C_LEVEL_LETCHED = 3,
@@ -1633,162 +2476,213 @@ typedef enum {
LSM6DS3TR_C_EDGE_TRIGGER = 4,
LSM6DS3TR_C_DEN_MODE_ND = 5, /* ERROR CODE */
} lsm6ds3tr_c_den_mode_t;
-int32_t lsm6ds3tr_c_den_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_den_mode_t val);
-int32_t lsm6ds3tr_c_den_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_den_mode_t *val);
+int32_t lsm6ds3tr_c_den_mode_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_den_mode_t val);
+int32_t lsm6ds3tr_c_den_mode_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_den_mode_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_STAMP_IN_GY_DATA = 0,
LSM6DS3TR_C_STAMP_IN_XL_DATA = 1,
LSM6DS3TR_C_STAMP_IN_GY_XL_DATA = 2,
LSM6DS3TR_C_DEN_STAMP_ND = 3, /* ERROR CODE */
} lsm6ds3tr_c_den_xl_en_t;
-int32_t lsm6ds3tr_c_den_enable_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_den_xl_en_t val);
-int32_t lsm6ds3tr_c_den_enable_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_den_xl_en_t *val);
-
-int32_t lsm6ds3tr_c_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3tr_c_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val);
-
-int32_t lsm6ds3tr_c_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3tr_c_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val);
-
-int32_t lsm6ds3tr_c_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3tr_c_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val);
-
-int32_t lsm6ds3tr_c_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3tr_c_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3tr_c_den_enable_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_den_xl_en_t val);
+int32_t lsm6ds3tr_c_den_enable_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_den_xl_en_t *val);
+
+int32_t lsm6ds3tr_c_den_mark_axis_z_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3tr_c_den_mark_axis_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6ds3tr_c_den_mark_axis_y_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3tr_c_den_mark_axis_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6ds3tr_c_den_mark_axis_x_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3tr_c_den_mark_axis_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6ds3tr_c_pedo_step_reset_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3tr_c_pedo_step_reset_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6ds3tr_c_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3tr_c_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6ds3tr_c_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3tr_c_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3tr_c_pedo_threshold_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3tr_c_pedo_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_PEDO_AT_2g = 0,
LSM6DS3TR_C_PEDO_AT_4g = 1,
LSM6DS3TR_C_PEDO_FS_ND = 2, /* ERROR CODE */
} lsm6ds3tr_c_pedo_fs_t;
int32_t lsm6ds3tr_c_pedo_full_scale_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_pedo_fs_t val);
+ lsm6ds3tr_c_pedo_fs_t val);
int32_t lsm6ds3tr_c_pedo_full_scale_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_pedo_fs_t *val);
+ lsm6ds3tr_c_pedo_fs_t *val);
-int32_t lsm6ds3tr_c_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3tr_c_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3tr_c_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3tr_c_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6ds3tr_c_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3tr_c_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6ds3tr_c_pedo_steps_period_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6ds3tr_c_pedo_steps_period_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6ds3tr_c_pedo_steps_period_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lsm6ds3tr_c_pedo_steps_period_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
int32_t lsm6ds3tr_c_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3tr_c_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6ds3tr_c_motion_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6ds3tr_c_motion_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6ds3tr_c_motion_threshold_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lsm6ds3tr_c_motion_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
int32_t lsm6ds3tr_c_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3tr_c_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6ds3tr_c_wrist_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3tr_c_wrist_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3tr_c_wrist_tilt_sens_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3tr_c_wrist_tilt_sens_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6ds3tr_c_tilt_latency_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6ds3tr_c_tilt_latency_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6ds3tr_c_tilt_latency_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lsm6ds3tr_c_tilt_latency_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
-int32_t lsm6ds3tr_c_tilt_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6ds3tr_c_tilt_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6ds3tr_c_tilt_threshold_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lsm6ds3tr_c_tilt_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
int32_t lsm6ds3tr_c_tilt_src_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_a_wrist_tilt_mask_t *val);
+ lsm6ds3tr_c_a_wrist_tilt_mask_t *val);
int32_t lsm6ds3tr_c_tilt_src_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_a_wrist_tilt_mask_t *val);
+ lsm6ds3tr_c_a_wrist_tilt_mask_t *val);
int32_t lsm6ds3tr_c_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3tr_c_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3tr_c_mag_soft_iron_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6ds3tr_c_mag_hard_iron_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3tr_c_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3tr_c_mag_hard_iron_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6ds3tr_c_mag_soft_iron_mat_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6ds3tr_c_mag_soft_iron_mat_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6ds3tr_c_mag_soft_iron_mat_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lsm6ds3tr_c_mag_soft_iron_mat_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
-int32_t lsm6ds3tr_c_mag_offset_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6ds3tr_c_mag_offset_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6ds3tr_c_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val);
+int32_t lsm6ds3tr_c_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val);
int32_t lsm6ds3tr_c_func_en_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3tr_c_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3tr_c_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3tr_c_sh_sync_sens_frame_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3tr_c_sh_sync_sens_frame_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_RES_RATIO_2_11 = 0,
LSM6DS3TR_C_RES_RATIO_2_12 = 1,
LSM6DS3TR_C_RES_RATIO_2_13 = 2,
LSM6DS3TR_C_RES_RATIO_2_14 = 3,
LSM6DS3TR_C_RES_RATIO_ND = 4, /* ERROR CODE */
} lsm6ds3tr_c_rr_t;
-int32_t lsm6ds3tr_c_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_rr_t val);
-int32_t lsm6ds3tr_c_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_rr_t *val);
+int32_t lsm6ds3tr_c_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_rr_t val);
+int32_t lsm6ds3tr_c_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_rr_t *val);
int32_t lsm6ds3tr_c_sh_master_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6ds3tr_c_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6ds3tr_c_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3tr_c_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3tr_c_sh_pass_through_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3tr_c_sh_pass_through_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_EXT_PULL_UP = 0,
LSM6DS3TR_C_INTERNAL_PULL_UP = 1,
LSM6DS3TR_C_SH_PIN_MODE = 2, /* ERROR CODE */
} lsm6ds3tr_c_pull_up_en_t;
-int32_t lsm6ds3tr_c_sh_pin_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_pull_up_en_t val);
-int32_t lsm6ds3tr_c_sh_pin_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_pull_up_en_t *val);
+int32_t lsm6ds3tr_c_sh_pin_mode_set(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_pull_up_en_t val);
+int32_t lsm6ds3tr_c_sh_pin_mode_get(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_pull_up_en_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_XL_GY_DRDY = 0,
LSM6DS3TR_C_EXT_ON_INT2_PIN = 1,
LSM6DS3TR_C_SH_SYNCRO_ND = 2, /* ERROR CODE */
} lsm6ds3tr_c_start_config_t;
int32_t lsm6ds3tr_c_sh_syncro_mode_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_start_config_t val);
+ lsm6ds3tr_c_start_config_t val);
int32_t lsm6ds3tr_c_sh_syncro_mode_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_start_config_t *val);
-
-int32_t lsm6ds3tr_c_sh_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3tr_c_sh_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
-
-typedef struct {
- lsm6ds3tr_c_sensorhub1_reg_t sh_byte_1;
- lsm6ds3tr_c_sensorhub2_reg_t sh_byte_2;
- lsm6ds3tr_c_sensorhub3_reg_t sh_byte_3;
- lsm6ds3tr_c_sensorhub4_reg_t sh_byte_4;
- lsm6ds3tr_c_sensorhub5_reg_t sh_byte_5;
- lsm6ds3tr_c_sensorhub6_reg_t sh_byte_6;
- lsm6ds3tr_c_sensorhub7_reg_t sh_byte_7;
- lsm6ds3tr_c_sensorhub8_reg_t sh_byte_8;
- lsm6ds3tr_c_sensorhub9_reg_t sh_byte_9;
- lsm6ds3tr_c_sensorhub10_reg_t sh_byte_10;
- lsm6ds3tr_c_sensorhub11_reg_t sh_byte_11;
- lsm6ds3tr_c_sensorhub12_reg_t sh_byte_12;
- lsm6ds3tr_c_sensorhub13_reg_t sh_byte_13;
- lsm6ds3tr_c_sensorhub14_reg_t sh_byte_14;
- lsm6ds3tr_c_sensorhub15_reg_t sh_byte_15;
- lsm6ds3tr_c_sensorhub16_reg_t sh_byte_16;
- lsm6ds3tr_c_sensorhub17_reg_t sh_byte_17;
- lsm6ds3tr_c_sensorhub18_reg_t sh_byte_18;
+ lsm6ds3tr_c_start_config_t *val);
+
+int32_t lsm6ds3tr_c_sh_drdy_on_int1_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3tr_c_sh_drdy_on_int1_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+typedef struct
+{
+ lsm6ds3tr_c_sensorhub1_reg_t sh_byte_1;
+ lsm6ds3tr_c_sensorhub2_reg_t sh_byte_2;
+ lsm6ds3tr_c_sensorhub3_reg_t sh_byte_3;
+ lsm6ds3tr_c_sensorhub4_reg_t sh_byte_4;
+ lsm6ds3tr_c_sensorhub5_reg_t sh_byte_5;
+ lsm6ds3tr_c_sensorhub6_reg_t sh_byte_6;
+ lsm6ds3tr_c_sensorhub7_reg_t sh_byte_7;
+ lsm6ds3tr_c_sensorhub8_reg_t sh_byte_8;
+ lsm6ds3tr_c_sensorhub9_reg_t sh_byte_9;
+ lsm6ds3tr_c_sensorhub10_reg_t sh_byte_10;
+ lsm6ds3tr_c_sensorhub11_reg_t sh_byte_11;
+ lsm6ds3tr_c_sensorhub12_reg_t sh_byte_12;
+ lsm6ds3tr_c_sensorhub13_reg_t sh_byte_13;
+ lsm6ds3tr_c_sensorhub14_reg_t sh_byte_14;
+ lsm6ds3tr_c_sensorhub15_reg_t sh_byte_15;
+ lsm6ds3tr_c_sensorhub16_reg_t sh_byte_16;
+ lsm6ds3tr_c_sensorhub17_reg_t sh_byte_17;
+ lsm6ds3tr_c_sensorhub18_reg_t sh_byte_18;
} lsm6ds3tr_c_emb_sh_read_t;
int32_t lsm6ds3tr_c_sh_read_data_raw_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_emb_sh_read_t *val);
+ lsm6ds3tr_c_emb_sh_read_t *val);
-int32_t lsm6ds3tr_c_sh_cmd_sens_sync_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3tr_c_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3tr_c_sh_cmd_sens_sync_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3tr_c_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6ds3tr_c_sh_spi_sync_error_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6ds3tr_c_sh_spi_sync_error_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6ds3tr_c_sh_spi_sync_error_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6ds3tr_c_sh_spi_sync_error_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_SLV_0 = 0,
LSM6DS3TR_C_SLV_0_1 = 1,
LSM6DS3TR_C_SLV_0_1_2 = 2,
@@ -1796,32 +2690,36 @@ typedef enum {
LSM6DS3TR_C_SLV_EN_ND = 4, /* ERROR CODE */
} lsm6ds3tr_c_aux_sens_on_t;
int32_t lsm6ds3tr_c_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_aux_sens_on_t val);
+ lsm6ds3tr_c_aux_sens_on_t val);
int32_t lsm6ds3tr_c_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_aux_sens_on_t *val);
+ lsm6ds3tr_c_aux_sens_on_t *val);
-typedef struct{
+typedef struct
+{
uint8_t slv0_add;
uint8_t slv0_subadd;
uint8_t slv0_data;
} lsm6ds3tr_c_sh_cfg_write_t;
-int32_t lsm6ds3tr_c_sh_cfg_write(stmdev_ctx_t *ctx, lsm6ds3tr_c_sh_cfg_write_t *val);
+int32_t lsm6ds3tr_c_sh_cfg_write(stmdev_ctx_t *ctx,
+ lsm6ds3tr_c_sh_cfg_write_t *val);
-typedef struct{
+typedef struct
+{
uint8_t slv_add;
uint8_t slv_subadd;
uint8_t slv_len;
} lsm6ds3tr_c_sh_cfg_read_t;
int32_t lsm6ds3tr_c_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_sh_cfg_read_t *val);
+ lsm6ds3tr_c_sh_cfg_read_t *val);
int32_t lsm6ds3tr_c_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_sh_cfg_read_t *val);
+ lsm6ds3tr_c_sh_cfg_read_t *val);
int32_t lsm6ds3tr_c_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_sh_cfg_read_t *val);
+ lsm6ds3tr_c_sh_cfg_read_t *val);
int32_t lsm6ds3tr_c_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_sh_cfg_read_t *val);
+ lsm6ds3tr_c_sh_cfg_read_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_SL0_NO_DEC = 0,
LSM6DS3TR_C_SL0_DEC_2 = 1,
LSM6DS3TR_C_SL0_DEC_4 = 2,
@@ -1829,21 +2727,23 @@ typedef enum {
LSM6DS3TR_C_SL0_DEC_ND = 4, /* ERROR CODE */
} lsm6ds3tr_c_slave0_rate_t;
int32_t lsm6ds3tr_c_sh_slave_0_dec_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_slave0_rate_t val);
+ lsm6ds3tr_c_slave0_rate_t val);
int32_t lsm6ds3tr_c_sh_slave_0_dec_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_slave0_rate_t *val);
+ lsm6ds3tr_c_slave0_rate_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_EACH_SH_CYCLE = 0,
LSM6DS3TR_C_ONLY_FIRST_CYCLE = 1,
LSM6DS3TR_C_SH_WR_MODE_ND = 2, /* ERROR CODE */
} lsm6ds3tr_c_write_once_t;
int32_t lsm6ds3tr_c_sh_write_mode_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_write_once_t val);
+ lsm6ds3tr_c_write_once_t val);
int32_t lsm6ds3tr_c_sh_write_mode_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_write_once_t *val);
+ lsm6ds3tr_c_write_once_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_SL1_NO_DEC = 0,
LSM6DS3TR_C_SL1_DEC_2 = 1,
LSM6DS3TR_C_SL1_DEC_4 = 2,
@@ -1851,11 +2751,12 @@ typedef enum {
LSM6DS3TR_C_SL1_DEC_ND = 4, /* ERROR CODE */
} lsm6ds3tr_c_slave1_rate_t;
int32_t lsm6ds3tr_c_sh_slave_1_dec_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_slave1_rate_t val);
+ lsm6ds3tr_c_slave1_rate_t val);
int32_t lsm6ds3tr_c_sh_slave_1_dec_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_slave1_rate_t *val);
+ lsm6ds3tr_c_slave1_rate_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_SL2_NO_DEC = 0,
LSM6DS3TR_C_SL2_DEC_2 = 1,
LSM6DS3TR_C_SL2_DEC_4 = 2,
@@ -1863,11 +2764,12 @@ typedef enum {
LSM6DS3TR_C_SL2_DEC_ND = 4, /* ERROR CODE */
} lsm6ds3tr_c_slave2_rate_t;
int32_t lsm6ds3tr_c_sh_slave_2_dec_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_slave2_rate_t val);
+ lsm6ds3tr_c_slave2_rate_t val);
int32_t lsm6ds3tr_c_sh_slave_2_dec_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_slave2_rate_t *val);
+ lsm6ds3tr_c_slave2_rate_t *val);
-typedef enum {
+typedef enum
+{
LSM6DS3TR_C_SL3_NO_DEC = 0,
LSM6DS3TR_C_SL3_DEC_2 = 1,
LSM6DS3TR_C_SL3_DEC_4 = 2,
@@ -1875,9 +2777,9 @@ typedef enum {
LSM6DS3TR_C_SL3_DEC_ND = 4, /* ERROR CODE */
} lsm6ds3tr_c_slave3_rate_t;
int32_t lsm6ds3tr_c_sh_slave_3_dec_set(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_slave3_rate_t val);
+ lsm6ds3tr_c_slave3_rate_t val);
int32_t lsm6ds3tr_c_sh_slave_3_dec_get(stmdev_ctx_t *ctx,
- lsm6ds3tr_c_slave3_rate_t *val);
+ lsm6ds3tr_c_slave3_rate_t *val);
/**
* @}
diff --git a/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.c b/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.c
index ce01640346e38b35d3bbd9b9dd2ea2c5418c6d6a..92a588b679bf911463a566c5d6d8eb978e1177b4 100644
--- a/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.c
+++ b/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file lsm6dsl_reg.c
- * @author Sensors Software Solution Team
- * @brief LSM6DSL driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lsm6dsl_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LSM6DSL driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lsm6dsl_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsl_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lsm6dsl_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t lsm6dsl_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsl_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lsm6dsl_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -146,7 +152,7 @@ float_t lsm6dsl_from_lsb_to_celsius(int16_t lsb)
* generation
* @{
*
-*/
+ */
/**
* @brief Accelerometer full-scale selection.[set]
@@ -156,16 +162,20 @@ float_t lsm6dsl_from_lsb_to_celsius(int16_t lsb)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_xl_full_scale_set(stmdev_ctx_t *ctx, lsm6dsl_fs_xl_t val)
+int32_t lsm6dsl_xl_full_scale_set(stmdev_ctx_t *ctx,
+ lsm6dsl_fs_xl_t val)
{
lsm6dsl_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
ctrl1_xl.fs_xl = (uint8_t) val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -177,25 +187,32 @@ int32_t lsm6dsl_xl_full_scale_set(stmdev_ctx_t *ctx, lsm6dsl_fs_xl_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_xl_full_scale_get(stmdev_ctx_t *ctx, lsm6dsl_fs_xl_t *val)
+int32_t lsm6dsl_xl_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6dsl_fs_xl_t *val)
{
lsm6dsl_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- switch (ctrl1_xl.fs_xl) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ switch (ctrl1_xl.fs_xl)
+ {
case LSM6DSL_2g:
*val = LSM6DSL_2g;
break;
+
case LSM6DSL_16g:
*val = LSM6DSL_16g;
break;
+
case LSM6DSL_4g:
*val = LSM6DSL_4g;
break;
+
case LSM6DSL_8g:
*val = LSM6DSL_8g;
break;
+
default:
*val = LSM6DSL_XL_FS_ND;
break;
@@ -212,16 +229,20 @@ int32_t lsm6dsl_xl_full_scale_get(stmdev_ctx_t *ctx, lsm6dsl_fs_xl_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6dsl_odr_xl_t val)
+int32_t lsm6dsl_xl_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dsl_odr_xl_t val)
{
lsm6dsl_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
ctrl1_xl.odr_xl = (uint8_t) val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -233,49 +254,64 @@ int32_t lsm6dsl_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6dsl_odr_xl_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_xl_data_rate_get(stmdev_ctx_t *ctx, lsm6dsl_odr_xl_t *val)
+int32_t lsm6dsl_xl_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dsl_odr_xl_t *val)
{
lsm6dsl_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- switch (ctrl1_xl.odr_xl) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ switch (ctrl1_xl.odr_xl)
+ {
case LSM6DSL_XL_ODR_OFF:
*val = LSM6DSL_XL_ODR_OFF;
break;
+
case LSM6DSL_XL_ODR_12Hz5:
*val = LSM6DSL_XL_ODR_12Hz5;
break;
+
case LSM6DSL_XL_ODR_26Hz:
*val = LSM6DSL_XL_ODR_26Hz;
break;
+
case LSM6DSL_XL_ODR_52Hz:
*val = LSM6DSL_XL_ODR_52Hz;
break;
+
case LSM6DSL_XL_ODR_104Hz:
*val = LSM6DSL_XL_ODR_104Hz;
break;
+
case LSM6DSL_XL_ODR_208Hz:
*val = LSM6DSL_XL_ODR_208Hz;
break;
+
case LSM6DSL_XL_ODR_416Hz:
*val = LSM6DSL_XL_ODR_416Hz;
break;
+
case LSM6DSL_XL_ODR_833Hz:
*val = LSM6DSL_XL_ODR_833Hz;
break;
+
case LSM6DSL_XL_ODR_1k66Hz:
*val = LSM6DSL_XL_ODR_1k66Hz;
break;
+
case LSM6DSL_XL_ODR_3k33Hz:
*val = LSM6DSL_XL_ODR_3k33Hz;
break;
+
case LSM6DSL_XL_ODR_6k66Hz:
*val = LSM6DSL_XL_ODR_6k66Hz;
break;
+
case LSM6DSL_XL_ODR_1Hz6:
*val = LSM6DSL_XL_ODR_1Hz6;
break;
+
default:
*val = LSM6DSL_XL_ODR_ND;
break;
@@ -292,16 +328,20 @@ int32_t lsm6dsl_xl_data_rate_get(stmdev_ctx_t *ctx, lsm6dsl_odr_xl_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_gy_full_scale_set(stmdev_ctx_t *ctx, lsm6dsl_fs_g_t val)
+int32_t lsm6dsl_gy_full_scale_set(stmdev_ctx_t *ctx,
+ lsm6dsl_fs_g_t val)
{
lsm6dsl_ctrl2_g_t ctrl2_g;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
+
+ if (ret == 0)
+ {
ctrl2_g.fs_g = (uint8_t) val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
}
+
return ret;
}
@@ -313,28 +353,36 @@ int32_t lsm6dsl_gy_full_scale_set(stmdev_ctx_t *ctx, lsm6dsl_fs_g_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_gy_full_scale_get(stmdev_ctx_t *ctx, lsm6dsl_fs_g_t *val)
+int32_t lsm6dsl_gy_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6dsl_fs_g_t *val)
{
lsm6dsl_ctrl2_g_t ctrl2_g;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- switch (ctrl2_g.fs_g) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
+
+ switch (ctrl2_g.fs_g)
+ {
case LSM6DSL_250dps:
*val = LSM6DSL_250dps;
break;
+
case LSM6DSL_125dps:
*val = LSM6DSL_125dps;
break;
+
case LSM6DSL_500dps:
*val = LSM6DSL_500dps;
break;
+
case LSM6DSL_1000dps:
*val = LSM6DSL_1000dps;
break;
+
case LSM6DSL_2000dps:
*val = LSM6DSL_2000dps;
break;
+
default:
*val = LSM6DSL_GY_FS_ND;
break;
@@ -351,16 +399,20 @@ int32_t lsm6dsl_gy_full_scale_get(stmdev_ctx_t *ctx, lsm6dsl_fs_g_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_gy_data_rate_set(stmdev_ctx_t *ctx, lsm6dsl_odr_g_t val)
+int32_t lsm6dsl_gy_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dsl_odr_g_t val)
{
lsm6dsl_ctrl2_g_t ctrl2_g;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
+
+ if (ret == 0)
+ {
ctrl2_g.odr_g = (uint8_t) val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
}
+
return ret;
}
@@ -372,46 +424,60 @@ int32_t lsm6dsl_gy_data_rate_set(stmdev_ctx_t *ctx, lsm6dsl_odr_g_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_gy_data_rate_get(stmdev_ctx_t *ctx, lsm6dsl_odr_g_t *val)
+int32_t lsm6dsl_gy_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dsl_odr_g_t *val)
{
lsm6dsl_ctrl2_g_t ctrl2_g;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- switch (ctrl2_g.odr_g) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
+
+ switch (ctrl2_g.odr_g)
+ {
case LSM6DSL_GY_ODR_OFF:
*val = LSM6DSL_GY_ODR_OFF;
break;
+
case LSM6DSL_GY_ODR_12Hz5:
*val = LSM6DSL_GY_ODR_12Hz5;
break;
+
case LSM6DSL_GY_ODR_26Hz:
*val = LSM6DSL_GY_ODR_26Hz;
break;
+
case LSM6DSL_GY_ODR_52Hz:
*val = LSM6DSL_GY_ODR_52Hz;
break;
+
case LSM6DSL_GY_ODR_104Hz:
*val = LSM6DSL_GY_ODR_104Hz;
break;
+
case LSM6DSL_GY_ODR_208Hz:
*val = LSM6DSL_GY_ODR_208Hz;
break;
+
case LSM6DSL_GY_ODR_416Hz:
*val = LSM6DSL_GY_ODR_416Hz;
break;
+
case LSM6DSL_GY_ODR_833Hz:
*val = LSM6DSL_GY_ODR_833Hz;
break;
+
case LSM6DSL_GY_ODR_1k66Hz:
*val = LSM6DSL_GY_ODR_1k66Hz;
break;
+
case LSM6DSL_GY_ODR_3k33Hz:
*val = LSM6DSL_GY_ODR_3k33Hz;
break;
+
case LSM6DSL_GY_ODR_6k66Hz:
*val = LSM6DSL_GY_ODR_6k66Hz;
break;
+
default:
*val = LSM6DSL_GY_ODR_ND;
break;
@@ -433,11 +499,14 @@ int32_t lsm6dsl_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.bdu = val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -454,7 +523,7 @@ int32_t lsm6dsl_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsl_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.bdu;
return ret;
@@ -475,11 +544,14 @@ int32_t lsm6dsl_xl_offset_weight_set(stmdev_ctx_t *ctx,
lsm6dsl_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
ctrl6_c.usr_off_w = (uint8_t) val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -498,14 +570,18 @@ int32_t lsm6dsl_xl_offset_weight_get(stmdev_ctx_t *ctx,
lsm6dsl_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- switch (ctrl6_c.usr_off_w) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ switch (ctrl6_c.usr_off_w)
+ {
case LSM6DSL_LSb_1mg:
*val = LSM6DSL_LSb_1mg;
break;
+
case LSM6DSL_LSb_16mg:
*val = LSM6DSL_LSb_16mg;
break;
+
default:
*val = LSM6DSL_WEIGHT_ND;
break;
@@ -528,11 +604,14 @@ int32_t lsm6dsl_xl_power_mode_set(stmdev_ctx_t *ctx,
lsm6dsl_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
ctrl6_c.xl_hm_mode = (uint8_t) val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -550,14 +629,18 @@ int32_t lsm6dsl_xl_power_mode_get(stmdev_ctx_t *ctx,
lsm6dsl_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- switch (ctrl6_c.xl_hm_mode) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ switch (ctrl6_c.xl_hm_mode)
+ {
case LSM6DSL_XL_HIGH_PERFORMANCE:
*val = LSM6DSL_XL_HIGH_PERFORMANCE;
break;
+
case LSM6DSL_XL_NORMAL:
*val = LSM6DSL_XL_NORMAL;
break;
+
default:
*val = LSM6DSL_XL_PW_MODE_ND;
break;
@@ -582,11 +665,14 @@ int32_t lsm6dsl_rounding_on_status_set(stmdev_ctx_t *ctx,
lsm6dsl_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
ctrl7_g.rounding_status = (uint8_t) val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
}
+
return ret;
}
@@ -606,14 +692,18 @@ int32_t lsm6dsl_rounding_on_status_get(stmdev_ctx_t *ctx,
lsm6dsl_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- switch (ctrl7_g.rounding_status) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ switch (ctrl7_g.rounding_status)
+ {
case LSM6DSL_STAT_RND_DISABLE:
*val = LSM6DSL_STAT_RND_DISABLE;
break;
+
case LSM6DSL_STAT_RND_ENABLE:
*val = LSM6DSL_STAT_RND_ENABLE;
break;
+
default:
*val = LSM6DSL_STAT_RND_ND;
break;
@@ -630,16 +720,20 @@ int32_t lsm6dsl_rounding_on_status_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_gy_power_mode_set(stmdev_ctx_t *ctx, lsm6dsl_g_hm_mode_t val)
+int32_t lsm6dsl_gy_power_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsl_g_hm_mode_t val)
{
lsm6dsl_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
ctrl7_g.g_hm_mode = (uint8_t) val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
}
+
return ret;
}
@@ -651,19 +745,24 @@ int32_t lsm6dsl_gy_power_mode_set(stmdev_ctx_t *ctx, lsm6dsl_g_hm_mode_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_gy_power_mode_get(stmdev_ctx_t *ctx, lsm6dsl_g_hm_mode_t *val)
+int32_t lsm6dsl_gy_power_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsl_g_hm_mode_t *val)
{
lsm6dsl_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- switch (ctrl7_g.g_hm_mode) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ switch (ctrl7_g.g_hm_mode)
+ {
case LSM6DSL_GY_HIGH_PERFORMANCE:
*val = LSM6DSL_GY_HIGH_PERFORMANCE;
break;
+
case LSM6DSL_GY_NORMAL:
*val = LSM6DSL_GY_NORMAL;
break;
+
default:
*val = LSM6DSL_GY_PW_MODE_ND;
break;
@@ -687,39 +786,57 @@ int32_t lsm6dsl_all_sources_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_SRC,
- (uint8_t*)&(val->wake_up_src), 1);
- if(ret == 0){
+ (uint8_t *) & (val->wake_up_src), 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_SRC,
- (uint8_t*)&(val->tap_src), 1);
+ (uint8_t *) & (val->tap_src), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_D6D_SRC,
- (uint8_t*)&(val->d6d_src), 1);
+ (uint8_t *) & (val->d6d_src), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_STATUS_REG,
- (uint8_t*)&(val->status_reg), 1);
+ (uint8_t *) & (val->status_reg), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_FUNC_SRC1,
- (uint8_t*)&(val->func_src1), 1);
+ (uint8_t *) & (val->func_src1), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_FUNC_SRC2,
- (uint8_t*)&(val->func_src2), 1);
+ (uint8_t *) & (val->func_src2), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_WRIST_TILT_IA,
- (uint8_t*)&(val->wrist_tilt_ia), 1);
+ (uint8_t *) & (val->wrist_tilt_ia), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_B);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_A_WRIST_TILT_MASK,
- (uint8_t*)&(val->a_wrist_tilt_mask), 1);
+ (uint8_t *) & (val->a_wrist_tilt_mask), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
@@ -733,10 +850,13 @@ int32_t lsm6dsl_all_sources_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_status_reg_get(stmdev_ctx_t *ctx, lsm6dsl_status_reg_t *val)
+int32_t lsm6dsl_status_reg_get(stmdev_ctx_t *ctx,
+ lsm6dsl_status_reg_t *val)
{
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_STATUS_REG, (uint8_t*) val, 1);
+
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_STATUS_REG, (uint8_t *) val, 1);
+
return ret;
}
@@ -748,12 +868,14 @@ int32_t lsm6dsl_status_reg_get(stmdev_ctx_t *ctx, lsm6dsl_status_reg_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsl_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsl_status_reg_t status_reg;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_STATUS_REG, (uint8_t*)&status_reg, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_STATUS_REG,
+ (uint8_t *)&status_reg, 1);
*val = status_reg.xlda;
return ret;
@@ -767,12 +889,14 @@ int32_t lsm6dsl_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsl_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsl_status_reg_t status_reg;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_STATUS_REG, (uint8_t*)&status_reg, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_STATUS_REG,
+ (uint8_t *)&status_reg, 1);
*val = status_reg.gda;
return ret;
@@ -786,12 +910,14 @@ int32_t lsm6dsl_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsl_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsl_status_reg_t status_reg;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_STATUS_REG, (uint8_t*)&status_reg, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_STATUS_REG,
+ (uint8_t *)&status_reg, 1);
*val = status_reg.tda;
return ret;
@@ -810,7 +936,9 @@ int32_t lsm6dsl_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t lsm6dsl_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsl_write_reg(ctx, LSM6DSL_X_OFS_USR, buff, 3);
+
return ret;
}
@@ -827,7 +955,9 @@ int32_t lsm6dsl_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lsm6dsl_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsl_read_reg(ctx, LSM6DSL_X_OFS_USR, buff, 3);
+
return ret;
}
@@ -858,14 +988,19 @@ int32_t lsm6dsl_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
ctrl10_c.timer_en = val;
- if ( val != 0x00U) {
+
+ if (val != 0x00U)
+ {
ctrl10_c.func_en = val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
}
}
+
return ret;
}
@@ -883,7 +1018,7 @@ int32_t lsm6dsl_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsl_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
*val = ctrl10_c.timer_en;
return ret;
@@ -902,17 +1037,22 @@ int32_t lsm6dsl_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_timestamp_res_set(stmdev_ctx_t *ctx, lsm6dsl_timer_hr_t val)
+int32_t lsm6dsl_timestamp_res_set(stmdev_ctx_t *ctx,
+ lsm6dsl_timer_hr_t val)
{
lsm6dsl_wake_up_dur_t wake_up_dur;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
wake_up_dur.timer_hr = (uint8_t) val;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -929,19 +1069,25 @@ int32_t lsm6dsl_timestamp_res_set(stmdev_ctx_t *ctx, lsm6dsl_timer_hr_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_timestamp_res_get(stmdev_ctx_t *ctx, lsm6dsl_timer_hr_t *val)
+int32_t lsm6dsl_timestamp_res_get(stmdev_ctx_t *ctx,
+ lsm6dsl_timer_hr_t *val)
{
lsm6dsl_wake_up_dur_t wake_up_dur;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
- switch (wake_up_dur.timer_hr) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
+
+ switch (wake_up_dur.timer_hr)
+ {
case LSM6DSL_LSB_6ms4:
*val = LSM6DSL_LSB_6ms4;
break;
+
case LSM6DSL_LSB_25us:
*val = LSM6DSL_LSB_25us;
break;
+
default:
*val = LSM6DSL_TS_RES_ND;
break;
@@ -971,16 +1117,20 @@ int32_t lsm6dsl_timestamp_res_get(stmdev_ctx_t *ctx, lsm6dsl_timer_hr_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_rounding_mode_set(stmdev_ctx_t *ctx, lsm6dsl_rounding_t val)
+int32_t lsm6dsl_rounding_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsl_rounding_t val)
{
lsm6dsl_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ if (ret == 0)
+ {
ctrl5_c.rounding = (uint8_t) val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -993,37 +1143,48 @@ int32_t lsm6dsl_rounding_mode_set(stmdev_ctx_t *ctx, lsm6dsl_rounding_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_rounding_mode_get(stmdev_ctx_t *ctx, lsm6dsl_rounding_t *val)
+int32_t lsm6dsl_rounding_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsl_rounding_t *val)
{
lsm6dsl_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- switch (ctrl5_c.rounding) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ switch (ctrl5_c.rounding)
+ {
case LSM6DSL_ROUND_DISABLE:
*val = LSM6DSL_ROUND_DISABLE;
break;
+
case LSM6DSL_ROUND_XL:
*val = LSM6DSL_ROUND_XL;
break;
+
case LSM6DSL_ROUND_GY:
*val = LSM6DSL_ROUND_GY;
break;
+
case LSM6DSL_ROUND_GY_XL:
*val = LSM6DSL_ROUND_GY_XL;
break;
+
case LSM6DSL_ROUND_SH1_TO_SH6:
*val = LSM6DSL_ROUND_SH1_TO_SH6;
break;
+
case LSM6DSL_ROUND_XL_SH1_TO_SH6:
*val = LSM6DSL_ROUND_XL_SH1_TO_SH6;
break;
+
case LSM6DSL_ROUND_GY_XL_SH1_TO_SH12:
*val = LSM6DSL_ROUND_GY_XL_SH1_TO_SH12;
break;
+
case LSM6DSL_ROUND_GY_XL_SH1_TO_SH6:
*val = LSM6DSL_ROUND_GY_XL_SH1_TO_SH6;
break;
+
default:
*val = LSM6DSL_ROUND_OUT_ND;
break;
@@ -1041,10 +1202,15 @@ int32_t lsm6dsl_rounding_mode_get(stmdev_ctx_t *ctx, lsm6dsl_rounding_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsl_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
+
ret = lsm6dsl_read_reg(ctx, LSM6DSL_OUT_TEMP_L, buff, 2);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+
return ret;
}
@@ -1057,10 +1223,19 @@ int32_t lsm6dsl_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsl_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lsm6dsl_read_reg(ctx, LSM6DSL_OUTX_L_G, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -1073,10 +1248,19 @@ int32_t lsm6dsl_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsl_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lsm6dsl_read_reg(ctx, LSM6DSL_OUTX_L_XL, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -1088,10 +1272,20 @@ int32_t lsm6dsl_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_mag_calibrated_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsl_mag_calibrated_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lsm6dsl_read_reg(ctx, LSM6DSL_OUT_MAG_RAW_X_L, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -1108,7 +1302,9 @@ int32_t lsm6dsl_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer,
uint8_t len)
{
int32_t ret;
+
ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_DATA_OUT_L, buffer, len);
+
return ret;
}
@@ -1119,7 +1315,7 @@ int32_t lsm6dsl_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer,
/**
* @defgroup LSM6DSL_common
- * @brief This section groups common usefull functions.
+ * @brief This section groups common useful functions.
* @{
*
*/
@@ -1133,17 +1329,20 @@ int32_t lsm6dsl_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_mem_bank_set(stmdev_ctx_t *ctx, lsm6dsl_func_cfg_en_t val)
+int32_t lsm6dsl_mem_bank_set(stmdev_ctx_t *ctx,
+ lsm6dsl_func_cfg_en_t val)
{
lsm6dsl_func_cfg_access_t func_cfg_access;
int32_t ret;
ret = lsm6dsl_read_reg(ctx, LSM6DSL_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
- if(ret == 0){
+ (uint8_t *)&func_cfg_access, 1);
+
+ if (ret == 0)
+ {
func_cfg_access.func_cfg_en = (uint8_t) val;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
+ (uint8_t *)&func_cfg_access, 1);
}
return ret;
@@ -1158,20 +1357,25 @@ int32_t lsm6dsl_mem_bank_set(stmdev_ctx_t *ctx, lsm6dsl_func_cfg_en_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_mem_bank_get(stmdev_ctx_t *ctx, lsm6dsl_func_cfg_en_t *val)
+int32_t lsm6dsl_mem_bank_get(stmdev_ctx_t *ctx,
+ lsm6dsl_func_cfg_en_t *val)
{
lsm6dsl_func_cfg_access_t func_cfg_access;
int32_t ret;
ret = lsm6dsl_read_reg(ctx, LSM6DSL_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
- switch (func_cfg_access.func_cfg_en) {
+ (uint8_t *)&func_cfg_access, 1);
+
+ switch (func_cfg_access.func_cfg_en)
+ {
case LSM6DSL_USER_BANK:
*val = LSM6DSL_USER_BANK;
break;
+
case LSM6DSL_BANK_B:
*val = LSM6DSL_BANK_B;
break;
+
default:
*val = LSM6DSL_BANK_ND;
break;
@@ -1195,12 +1399,15 @@ int32_t lsm6dsl_data_ready_mode_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsl_read_reg(ctx, LSM6DSL_DRDY_PULSE_CFG_G,
- (uint8_t*)&drdy_pulse_cfg_g, 1);
- if(ret == 0){
+ (uint8_t *)&drdy_pulse_cfg_g, 1);
+
+ if (ret == 0)
+ {
drdy_pulse_cfg_g.drdy_pulsed = (uint8_t) val;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_DRDY_PULSE_CFG_G,
- (uint8_t*)&drdy_pulse_cfg_g, 1);
+ (uint8_t *)&drdy_pulse_cfg_g, 1);
}
+
return ret;
}
@@ -1219,14 +1426,18 @@ int32_t lsm6dsl_data_ready_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsl_read_reg(ctx, LSM6DSL_DRDY_PULSE_CFG_G,
- (uint8_t*)&drdy_pulse_cfg_g, 1);
- switch (drdy_pulse_cfg_g.drdy_pulsed) {
+ (uint8_t *)&drdy_pulse_cfg_g, 1);
+
+ switch (drdy_pulse_cfg_g.drdy_pulsed)
+ {
case LSM6DSL_DRDY_LATCHED:
*val = LSM6DSL_DRDY_LATCHED;
break;
+
case LSM6DSL_DRDY_PULSED:
*val = LSM6DSL_DRDY_PULSED;
break;
+
default:
*val = LSM6DSL_DRDY_ND;
break;
@@ -1246,7 +1457,9 @@ int32_t lsm6dsl_data_ready_mode_get(stmdev_ctx_t *ctx,
int32_t lsm6dsl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsl_read_reg(ctx, LSM6DSL_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -1263,11 +1476,14 @@ int32_t lsm6dsl_reset_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.sw_reset = val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1284,7 +1500,7 @@ int32_t lsm6dsl_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsl_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.sw_reset;
return ret;
@@ -1303,11 +1519,14 @@ int32_t lsm6dsl_data_format_set(stmdev_ctx_t *ctx, lsm6dsl_ble_t val)
lsm6dsl_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.ble = (uint8_t) val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1324,14 +1543,18 @@ int32_t lsm6dsl_data_format_get(stmdev_ctx_t *ctx, lsm6dsl_ble_t *val)
lsm6dsl_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- switch (ctrl3_c.ble) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ switch (ctrl3_c.ble)
+ {
case LSM6DSL_LSB_AT_LOW_ADD:
*val = LSM6DSL_LSB_AT_LOW_ADD;
break;
+
case LSM6DSL_MSB_AT_LOW_ADD:
*val = LSM6DSL_MSB_AT_LOW_ADD;
break;
+
default:
*val = LSM6DSL_DATA_FMT_ND;
break;
@@ -1354,11 +1577,14 @@ int32_t lsm6dsl_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.if_inc = val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1376,7 +1602,7 @@ int32_t lsm6dsl_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsl_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.if_inc;
return ret;
@@ -1395,11 +1621,14 @@ int32_t lsm6dsl_boot_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.boot = val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1416,7 +1645,7 @@ int32_t lsm6dsl_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsl_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.boot;
return ret;
@@ -1430,16 +1659,20 @@ int32_t lsm6dsl_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_xl_self_test_set(stmdev_ctx_t *ctx, lsm6dsl_st_xl_t val)
+int32_t lsm6dsl_xl_self_test_set(stmdev_ctx_t *ctx,
+ lsm6dsl_st_xl_t val)
{
lsm6dsl_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ if (ret == 0)
+ {
ctrl5_c.st_xl = (uint8_t) val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -1451,26 +1684,33 @@ int32_t lsm6dsl_xl_self_test_set(stmdev_ctx_t *ctx, lsm6dsl_st_xl_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_xl_self_test_get(stmdev_ctx_t *ctx, lsm6dsl_st_xl_t *val)
+int32_t lsm6dsl_xl_self_test_get(stmdev_ctx_t *ctx,
+ lsm6dsl_st_xl_t *val)
{
lsm6dsl_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- switch (ctrl5_c.st_xl) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ switch (ctrl5_c.st_xl)
+ {
case LSM6DSL_XL_ST_DISABLE:
*val = LSM6DSL_XL_ST_DISABLE;
break;
+
case LSM6DSL_XL_ST_POSITIVE:
*val = LSM6DSL_XL_ST_POSITIVE;
break;
+
case LSM6DSL_XL_ST_NEGATIVE:
*val = LSM6DSL_XL_ST_NEGATIVE;
break;
+
default:
*val = LSM6DSL_XL_ST_ND;
break;
}
+
return ret;
}
@@ -1482,16 +1722,20 @@ int32_t lsm6dsl_xl_self_test_get(stmdev_ctx_t *ctx, lsm6dsl_st_xl_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_gy_self_test_set(stmdev_ctx_t *ctx, lsm6dsl_st_g_t val)
+int32_t lsm6dsl_gy_self_test_set(stmdev_ctx_t *ctx,
+ lsm6dsl_st_g_t val)
{
lsm6dsl_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ if (ret == 0)
+ {
ctrl5_c.st_g = (uint8_t) val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -1503,22 +1747,28 @@ int32_t lsm6dsl_gy_self_test_set(stmdev_ctx_t *ctx, lsm6dsl_st_g_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_gy_self_test_get(stmdev_ctx_t *ctx, lsm6dsl_st_g_t *val)
+int32_t lsm6dsl_gy_self_test_get(stmdev_ctx_t *ctx,
+ lsm6dsl_st_g_t *val)
{
lsm6dsl_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- switch (ctrl5_c.st_g) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ switch (ctrl5_c.st_g)
+ {
case LSM6DSL_GY_ST_DISABLE:
*val = LSM6DSL_GY_ST_DISABLE;
break;
+
case LSM6DSL_GY_ST_POSITIVE:
*val = LSM6DSL_GY_ST_POSITIVE;
break;
+
case LSM6DSL_GY_ST_NEGATIVE:
*val = LSM6DSL_GY_ST_NEGATIVE;
break;
+
default:
*val = LSM6DSL_GY_ST_ND;
break;
@@ -1549,16 +1799,20 @@ int32_t lsm6dsl_gy_self_test_get(stmdev_ctx_t *ctx, lsm6dsl_st_g_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dsl_filter_settling_mask_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dsl_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
ctrl4_c.drdy_mask = val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -1571,12 +1825,13 @@ int32_t lsm6dsl_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsl_filter_settling_mask_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsl_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.drdy_mask;
return ret;
@@ -1597,11 +1852,14 @@ int32_t lsm6dsl_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
lsm6dsl_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
tap_cfg.slope_fds = (uint8_t) val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -1620,14 +1878,18 @@ int32_t lsm6dsl_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
lsm6dsl_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- switch (tap_cfg.slope_fds) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
+
+ switch (tap_cfg.slope_fds)
+ {
case LSM6DSL_USE_SLOPE:
*val = LSM6DSL_USE_SLOPE;
break;
+
case LSM6DSL_USE_HPF:
*val = LSM6DSL_USE_HPF;
break;
+
default:
*val = LSM6DSL_HP_PATH_ND;
break;
@@ -1658,16 +1920,20 @@ int32_t lsm6dsl_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_xl_filter_analog_set(stmdev_ctx_t *ctx, lsm6dsl_bw0_xl_t val)
+int32_t lsm6dsl_xl_filter_analog_set(stmdev_ctx_t *ctx,
+ lsm6dsl_bw0_xl_t val)
{
lsm6dsl_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
ctrl1_xl.bw0_xl = (uint8_t) val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -1686,14 +1952,18 @@ int32_t lsm6dsl_xl_filter_analog_get(stmdev_ctx_t *ctx,
lsm6dsl_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- switch (ctrl1_xl.bw0_xl) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ switch (ctrl1_xl.bw0_xl)
+ {
case LSM6DSL_XL_ANA_BW_1k5Hz:
*val = LSM6DSL_XL_ANA_BW_1k5Hz;
break;
+
case LSM6DSL_XL_ANA_BW_400Hz:
*val = LSM6DSL_XL_ANA_BW_400Hz;
break;
+
default:
*val = LSM6DSL_XL_ANA_BW_ND;
break;
@@ -1731,19 +2001,26 @@ int32_t lsm6dsl_xl_lp1_bandwidth_set(stmdev_ctx_t *ctx,
lsm6dsl_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
ctrl1_xl.lpf1_bw_sel = (uint8_t) val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
ctrl8_xl.lpf2_xl_en = 0;
ctrl8_xl.hp_slope_xl_en = 0;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
}
}
}
+
return ret;
}
@@ -1763,27 +2040,37 @@ int32_t lsm6dsl_xl_lp1_bandwidth_get(stmdev_ctx_t *ctx,
lsm6dsl_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
if ((ctrl8_xl.lpf2_xl_en != 0x00U) ||
- (ctrl8_xl.hp_slope_xl_en != 0x00U)){
+ (ctrl8_xl.hp_slope_xl_en != 0x00U))
+ {
*val = LSM6DSL_XL_LP1_NA;
}
- else{
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- switch ( ctrl1_xl.lpf1_bw_sel) {
+
+ else
+ {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ switch (ctrl1_xl.lpf1_bw_sel)
+ {
case LSM6DSL_XL_LP1_ODR_DIV_2:
*val = LSM6DSL_XL_LP1_ODR_DIV_2;
break;
+
case LSM6DSL_XL_LP1_ODR_DIV_4:
*val = LSM6DSL_XL_LP1_ODR_DIV_4;
break;
+
default:
*val = LSM6DSL_XL_LP1_NA;
break;
}
}
}
+
return ret;
}
@@ -1801,14 +2088,17 @@ int32_t lsm6dsl_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx,
lsm6dsl_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
- ctrl8_xl.input_composite = ( (uint8_t) val & 0x10U ) >> 4;
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl8_xl.input_composite = ((uint8_t) val & 0x10U) >> 4;
ctrl8_xl.hpcf_xl = (uint8_t) val & 0x03U;
ctrl8_xl.lpf2_xl_en = 1;
ctrl8_xl.hp_slope_xl_en = 0;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -1826,38 +2116,52 @@ int32_t lsm6dsl_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx,
lsm6dsl_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
if ((ctrl8_xl.lpf2_xl_en == 0x00U) ||
- (ctrl8_xl.hp_slope_xl_en != 0x00U)){
+ (ctrl8_xl.hp_slope_xl_en != 0x00U))
+ {
*val = LSM6DSL_XL_LP_NA;
}
- else{
- switch ((ctrl8_xl.input_composite << 4) + ctrl8_xl.hpcf_xl) {
+
+ else
+ {
+ switch ((ctrl8_xl.input_composite << 4) + ctrl8_xl.hpcf_xl)
+ {
case LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_50:
*val = LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_50;
break;
+
case LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_100:
*val = LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_100;
break;
+
case LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_9:
*val = LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_9;
break;
+
case LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_400:
*val = LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_400;
break;
+
case LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_50:
*val = LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_50;
break;
+
case LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_100:
*val = LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_100;
break;
+
case LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_9:
*val = LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_9;
break;
+
case LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_400:
*val = LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_400;
break;
+
default:
*val = LSM6DSL_XL_LP_NA;
break;
@@ -1881,11 +2185,14 @@ int32_t lsm6dsl_xl_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
ctrl8_xl.hp_ref_mode = val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -1902,7 +2209,7 @@ int32_t lsm6dsl_xl_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsl_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
*val = ctrl8_xl.hp_ref_mode;
return ret;
@@ -1916,18 +2223,22 @@ int32_t lsm6dsl_xl_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_xl_hp_bandwidth_set(stmdev_ctx_t *ctx, lsm6dsl_hpcf_xl_t val)
+int32_t lsm6dsl_xl_hp_bandwidth_set(stmdev_ctx_t *ctx,
+ lsm6dsl_hpcf_xl_t val)
{
lsm6dsl_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
ctrl8_xl.input_composite = 0;
ctrl8_xl.hpcf_xl = (uint8_t)val & 0x03U;
ctrl8_xl.hp_slope_xl_en = 1;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -1939,28 +2250,37 @@ int32_t lsm6dsl_xl_hp_bandwidth_set(stmdev_ctx_t *ctx, lsm6dsl_hpcf_xl_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_xl_hp_bandwidth_get(stmdev_ctx_t *ctx, lsm6dsl_hpcf_xl_t *val)
+int32_t lsm6dsl_xl_hp_bandwidth_get(stmdev_ctx_t *ctx,
+ lsm6dsl_hpcf_xl_t *val)
{
lsm6dsl_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if (ctrl8_xl.hp_slope_xl_en == 0x00U){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ if (ctrl8_xl.hp_slope_xl_en == 0x00U)
+ {
*val = LSM6DSL_XL_HP_NA;
}
- switch (ctrl8_xl.hpcf_xl) {
+
+ switch (ctrl8_xl.hpcf_xl)
+ {
case LSM6DSL_XL_HP_ODR_DIV_4:
*val = LSM6DSL_XL_HP_ODR_DIV_4;
break;
+
case LSM6DSL_XL_HP_ODR_DIV_100:
*val = LSM6DSL_XL_HP_ODR_DIV_100;
break;
+
case LSM6DSL_XL_HP_ODR_DIV_9:
*val = LSM6DSL_XL_HP_ODR_DIV_9;
break;
+
case LSM6DSL_XL_HP_ODR_DIV_400:
*val = LSM6DSL_XL_HP_ODR_DIV_400;
break;
+
default:
*val = LSM6DSL_XL_HP_NA;
break;
@@ -1990,35 +2310,47 @@ int32_t lsm6dsl_xl_hp_bandwidth_get(stmdev_ctx_t *ctx, lsm6dsl_hpcf_xl_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_gy_band_pass_set(stmdev_ctx_t *ctx, lsm6dsl_lpf1_sel_g_t val)
+int32_t lsm6dsl_gy_band_pass_set(stmdev_ctx_t *ctx,
+ lsm6dsl_lpf1_sel_g_t val)
{
lsm6dsl_ctrl4_c_t ctrl4_c;
lsm6dsl_ctrl6_c_t ctrl6_c;
lsm6dsl_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
- ctrl7_g.hpm_g = ( (uint8_t)val & 0x30U ) >> 4;
- ctrl7_g.hp_en_g = ( (uint8_t)val & 0x80U ) >> 7;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
+ ctrl7_g.hpm_g = ((uint8_t)val & 0x30U) >> 4;
+ ctrl7_g.hp_en_g = ((uint8_t)val & 0x80U) >> 7;
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
ctrl6_c.ftype = (uint8_t)val & 0x03U;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C,
- (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ctrl4_c.lpf1_sel_g = ( (uint8_t)val & 0x08U ) >> 3;
+ (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl4_c.lpf1_sel_g = ((uint8_t)val & 0x08U) >> 3;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL4_C,
- (uint8_t*)&ctrl4_c, 1);
+ (uint8_t *)&ctrl4_c, 1);
}
}
}
}
}
+
return ret;
}
@@ -2030,57 +2362,75 @@ int32_t lsm6dsl_gy_band_pass_set(stmdev_ctx_t *ctx, lsm6dsl_lpf1_sel_g_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_gy_band_pass_get(stmdev_ctx_t *ctx, lsm6dsl_lpf1_sel_g_t *val)
+int32_t lsm6dsl_gy_band_pass_get(stmdev_ctx_t *ctx,
+ lsm6dsl_lpf1_sel_g_t *val)
{
lsm6dsl_ctrl4_c_t ctrl4_c;
lsm6dsl_ctrl6_c_t ctrl6_c;
lsm6dsl_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
- switch ( ( ctrl7_g.hp_en_g << 7 ) + ( ctrl7_g.hpm_g << 4 ) +
- ( ctrl4_c.lpf1_sel_g << 3) + ctrl6_c.ftype ) {
+ if (ret == 0)
+ {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ switch ((ctrl7_g.hp_en_g << 7) + (ctrl7_g.hpm_g << 4) +
+ (ctrl4_c.lpf1_sel_g << 3) + ctrl6_c.ftype)
+ {
case LSM6DSL_HP_16mHz_LP2:
*val = LSM6DSL_HP_16mHz_LP2;
break;
+
case LSM6DSL_HP_65mHz_LP2:
*val = LSM6DSL_HP_65mHz_LP2;
break;
+
case LSM6DSL_HP_260mHz_LP2:
*val = LSM6DSL_HP_260mHz_LP2;
break;
+
case LSM6DSL_HP_1Hz04_LP2:
*val = LSM6DSL_HP_1Hz04_LP2;
break;
+
case LSM6DSL_HP_DISABLE_LP1_LIGHT:
*val = LSM6DSL_HP_DISABLE_LP1_LIGHT;
break;
+
case LSM6DSL_HP_DISABLE_LP1_NORMAL:
*val = LSM6DSL_HP_DISABLE_LP1_NORMAL;
break;
+
case LSM6DSL_HP_DISABLE_LP_STRONG:
*val = LSM6DSL_HP_DISABLE_LP_STRONG;
break;
+
case LSM6DSL_HP_DISABLE_LP1_AGGRESSIVE:
*val = LSM6DSL_HP_DISABLE_LP1_AGGRESSIVE;
break;
+
case LSM6DSL_HP_16mHz_LP1_LIGHT:
*val = LSM6DSL_HP_16mHz_LP1_LIGHT;
break;
+
case LSM6DSL_HP_65mHz_LP1_NORMAL:
*val = LSM6DSL_HP_65mHz_LP1_NORMAL;
break;
+
case LSM6DSL_HP_260mHz_LP1_STRONG:
*val = LSM6DSL_HP_260mHz_LP1_STRONG;
break;
+
case LSM6DSL_HP_1Hz04_LP1_AGGRESSIVE:
*val = LSM6DSL_HP_1Hz04_LP1_AGGRESSIVE;
break;
+
default:
*val = LSM6DSL_HP_GY_BAND_NA;
break;
@@ -2117,11 +2467,14 @@ int32_t lsm6dsl_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsl_sim_t val)
lsm6dsl_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.sim = (uint8_t) val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -2138,18 +2491,23 @@ int32_t lsm6dsl_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsl_sim_t *val)
lsm6dsl_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- switch (ctrl3_c.sim) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ switch (ctrl3_c.sim)
+ {
case LSM6DSL_SPI_4_WIRE:
*val = LSM6DSL_SPI_4_WIRE;
break;
+
case LSM6DSL_SPI_3_WIRE:
*val = LSM6DSL_SPI_3_WIRE;
break;
+
default:
*val = LSM6DSL_SPI_MODE_ND;
break;
}
+
return ret;
}
@@ -2167,11 +2525,14 @@ int32_t lsm6dsl_i2c_interface_set(stmdev_ctx_t *ctx,
lsm6dsl_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
ctrl4_c.i2c_disable = (uint8_t)val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -2189,14 +2550,18 @@ int32_t lsm6dsl_i2c_interface_get(stmdev_ctx_t *ctx,
lsm6dsl_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- switch (ctrl4_c.i2c_disable) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ switch (ctrl4_c.i2c_disable)
+ {
case LSM6DSL_I2C_ENABLE:
*val = LSM6DSL_I2C_ENABLE;
break;
+
case LSM6DSL_I2C_DISABLE:
*val = LSM6DSL_I2C_DISABLE;
break;
+
default:
*val = LSM6DSL_I2C_MODE_ND;
break;
@@ -2213,7 +2578,7 @@ int32_t lsm6dsl_i2c_interface_get(stmdev_ctx_t *ctx,
/**
* @defgroup LSM6DSL_interrupt_pins
* @brief This section groups all the functions that manage
- * interrup pins
+ * interrupt pins
* @{
*
*/
@@ -2238,8 +2603,10 @@ int32_t lsm6dsl_pin_int1_route_set(stmdev_ctx_t *ctx,
lsm6dsl_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
+
+ if (ret == 0)
+ {
int1_ctrl.int1_drdy_xl = val.int1_drdy_xl;
int1_ctrl.int1_drdy_g = val.int1_drdy_g;
int1_ctrl.int1_boot = val.int1_boot;
@@ -2248,64 +2615,87 @@ int32_t lsm6dsl_pin_int1_route_set(stmdev_ctx_t *ctx,
int1_ctrl.int1_full_flag = val.int1_full_flag;
int1_ctrl.int1_sign_mot = val.int1_sign_mot;
int1_ctrl.int1_step_detector = val.int1_step_detector;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
}
- if(ret == 0){
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_MD1_CFG, (uint8_t*)&md1_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_MD1_CFG, (uint8_t *)&md1_cfg, 1);
}
- if(ret == 0){
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_MD2_CFG, (uint8_t*)&md2_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_MD2_CFG, (uint8_t *)&md2_cfg, 1);
}
- if(ret == 0){
- md1_cfg.int1_timer = val.int1_timer;
- md1_cfg.int1_tilt = val.int1_tilt;
- md1_cfg.int1_6d = val.int1_6d;
- md1_cfg.int1_double_tap = val.int1_double_tap;
- md1_cfg.int1_ff = val.int1_ff;
- md1_cfg.int1_wu = val.int1_wu;
- md1_cfg.int1_single_tap = val.int1_single_tap;
- md1_cfg.int1_inact_state = val.int1_inact_state;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_MD1_CFG, (uint8_t*)&md1_cfg, 1);
+
+ if (ret == 0)
+ {
+ md1_cfg.int1_timer = val.int1_timer;
+ md1_cfg.int1_tilt = val.int1_tilt;
+ md1_cfg.int1_6d = val.int1_6d;
+ md1_cfg.int1_double_tap = val.int1_double_tap;
+ md1_cfg.int1_ff = val.int1_ff;
+ md1_cfg.int1_wu = val.int1_wu;
+ md1_cfg.int1_single_tap = val.int1_single_tap;
+ md1_cfg.int1_inact_state = val.int1_inact_state;
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_MD1_CFG, (uint8_t *)&md1_cfg, 1);
}
- if(ret == 0){
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ctrl4_c.den_drdy_int1 = val.den_drdy_int1;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- master_config.drdy_on_int1 = val.den_drdy_int1;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+
+ if (ret == 0)
+ {
+ master_config.drdy_on_int1 = val.den_drdy_int1;
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_MASTER_CONFIG,
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
+
if ((val.int1_6d != 0x00U) ||
(val.int1_ff != 0x00U) ||
(val.int1_wu != 0x00U) ||
(val.int1_single_tap != 0x00U) ||
(val.int1_double_tap != 0x00U) ||
- (val.int1_inact_state != 0x00U)||
+ (val.int1_inact_state != 0x00U) ||
(md2_cfg.int2_6d != 0x00U) ||
(md2_cfg.int2_ff != 0x00U) ||
(md2_cfg.int2_wu != 0x00U) ||
(md2_cfg.int2_single_tap != 0x00U) ||
(md2_cfg.int2_double_tap != 0x00U) ||
- (md2_cfg.int2_inact_state!= 0x00U) ){
+ (md2_cfg.int2_inact_state != 0x00U))
+ {
tap_cfg.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
tap_cfg.interrupts_enable = PROPERTY_DISABLE;
}
}
- if(ret == 0){
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -2325,11 +2715,12 @@ int32_t lsm6dsl_pin_int1_route_get(stmdev_ctx_t *ctx,
lsm6dsl_int1_ctrl_t int1_ctrl;
lsm6dsl_md1_cfg_t md1_cfg;
lsm6dsl_ctrl4_c_t ctrl4_c;
-
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
+
+ if (ret == 0)
+ {
val->int1_drdy_xl = int1_ctrl.int1_drdy_xl;
val->int1_drdy_g = int1_ctrl.int1_drdy_g;
val->int1_boot = int1_ctrl.int1_boot;
@@ -2338,27 +2729,30 @@ int32_t lsm6dsl_pin_int1_route_get(stmdev_ctx_t *ctx,
val->int1_full_flag = int1_ctrl.int1_full_flag;
val->int1_sign_mot = int1_ctrl.int1_sign_mot;
val->int1_step_detector = int1_ctrl.int1_step_detector ;
-
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_MD1_CFG, (uint8_t*)&md1_cfg, 1);
- if(ret == 0){
- val->int1_timer = md1_cfg.int1_timer;
- val->int1_tilt = md1_cfg.int1_tilt;
- val->int1_6d = md1_cfg.int1_6d;
- val->int1_double_tap = md1_cfg.int1_double_tap;
- val->int1_ff = md1_cfg.int1_ff;
- val->int1_wu = md1_cfg.int1_wu;
- val->int1_single_tap = md1_cfg.int1_single_tap;
- val->int1_inact_state = md1_cfg.int1_inact_state;
-
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_MD1_CFG, (uint8_t *)&md1_cfg, 1);
+
+ if (ret == 0)
+ {
+ val->int1_timer = md1_cfg.int1_timer;
+ val->int1_tilt = md1_cfg.int1_tilt;
+ val->int1_6d = md1_cfg.int1_6d;
+ val->int1_double_tap = md1_cfg.int1_double_tap;
+ val->int1_ff = md1_cfg.int1_ff;
+ val->int1_wu = md1_cfg.int1_wu;
+ val->int1_single_tap = md1_cfg.int1_single_tap;
+ val->int1_inact_state = md1_cfg.int1_inact_state;
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
val->den_drdy_int1 = ctrl4_c.den_drdy_int1;
ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
val->den_drdy_int1 = master_config.drdy_on_int1;
}
}
}
+
return ret;
}
@@ -2380,9 +2774,10 @@ int32_t lsm6dsl_pin_int2_route_set(stmdev_ctx_t *ctx,
lsm6dsl_tap_cfg_t tap_cfg;
int32_t ret;
-
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
+
+ if (ret == 0)
+ {
int2_ctrl.int2_drdy_xl = val.int2_drdy_xl;
int2_ctrl.int2_drdy_g = val.int2_drdy_g;
int2_ctrl.int2_drdy_temp = val.int2_drdy_temp;
@@ -2391,15 +2786,21 @@ int32_t lsm6dsl_pin_int2_route_set(stmdev_ctx_t *ctx,
int2_ctrl.int2_full_flag = val.int2_full_flag;
int2_ctrl.int2_step_count_ov = val.int2_step_count_ov;
int2_ctrl.int2_step_delta = val.int2_step_delta;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
}
- if(ret == 0){
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_MD1_CFG, (uint8_t*)&md1_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_MD1_CFG, (uint8_t *)&md1_cfg, 1);
}
- if(ret == 0){
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_MD2_CFG, (uint8_t*)&md2_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_MD2_CFG, (uint8_t *)&md2_cfg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
md2_cfg.int2_iron = val.int2_iron;
md2_cfg.int2_tilt = val.int2_tilt;
md2_cfg.int2_6d = val.int2_6d;
@@ -2408,19 +2809,26 @@ int32_t lsm6dsl_pin_int2_route_set(stmdev_ctx_t *ctx,
md2_cfg.int2_wu = val.int2_wu;
md2_cfg.int2_single_tap = val.int2_single_tap;
md2_cfg.int2_inact_state = val.int2_inact_state;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_MD2_CFG, (uint8_t*)&md2_cfg, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_MD2_CFG, (uint8_t *)&md2_cfg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_DRDY_PULSE_CFG_G,
- (uint8_t*)&drdy_pulse_cfg_g, 1);
+ (uint8_t *)&drdy_pulse_cfg_g, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
drdy_pulse_cfg_g.int2_wrist_tilt = val.int2_wrist_tilt;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_DRDY_PULSE_CFG_G,
- (uint8_t*)&drdy_pulse_cfg_g, 1);
+ (uint8_t *)&drdy_pulse_cfg_g, 1);
}
- if(ret == 0){
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
+
if ((md1_cfg.int1_6d != 0x00U) ||
(md1_cfg.int1_ff != 0x00U) ||
(md1_cfg.int1_wu != 0x00U) ||
@@ -2432,16 +2840,22 @@ int32_t lsm6dsl_pin_int2_route_set(stmdev_ctx_t *ctx,
(val.int2_wu != 0x00U) ||
(val.int2_single_tap != 0x00U) ||
(val.int2_double_tap != 0x00U) ||
- (val.int2_inact_state!= 0x00U) ){
+ (val.int2_inact_state != 0x00U))
+ {
tap_cfg.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
tap_cfg.interrupts_enable = PROPERTY_DISABLE;
}
}
- if(ret == 0){
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -2454,16 +2868,17 @@ int32_t lsm6dsl_pin_int2_route_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsl_pin_int2_route_get(stmdev_ctx_t *ctx,
-lsm6dsl_int2_route_t *val)
+ lsm6dsl_int2_route_t *val)
{
lsm6dsl_int2_ctrl_t int2_ctrl;
lsm6dsl_md2_cfg_t md2_cfg;
lsm6dsl_drdy_pulse_cfg_g_t drdy_pulse_cfg_g;
-
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
+
+ if (ret == 0)
+ {
val->int2_drdy_xl = int2_ctrl.int2_drdy_xl;
val->int2_drdy_g = int2_ctrl.int2_drdy_g;
val->int2_drdy_temp = int2_ctrl.int2_drdy_temp;
@@ -2472,9 +2887,10 @@ lsm6dsl_int2_route_t *val)
val->int2_full_flag = int2_ctrl.int2_full_flag;
val->int2_step_count_ov = int2_ctrl.int2_step_count_ov;
val->int2_step_delta = int2_ctrl.int2_step_delta;
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_MD2_CFG, (uint8_t *)&md2_cfg, 1);
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_MD2_CFG, (uint8_t*)&md2_cfg, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
val->int2_iron = md2_cfg.int2_iron;
val->int2_tilt = md2_cfg.int2_tilt;
val->int2_6d = md2_cfg.int2_6d;
@@ -2483,12 +2899,12 @@ lsm6dsl_int2_route_t *val)
val->int2_wu = md2_cfg.int2_wu;
val->int2_single_tap = md2_cfg.int2_single_tap;
val->int2_inact_state = md2_cfg.int2_inact_state;
-
ret = lsm6dsl_read_reg(ctx, LSM6DSL_DRDY_PULSE_CFG_G,
- (uint8_t*)&drdy_pulse_cfg_g, 1);
+ (uint8_t *)&drdy_pulse_cfg_g, 1);
val->int2_wrist_tilt = drdy_pulse_cfg_g.int2_wrist_tilt;
}
}
+
return ret;
}
@@ -2505,11 +2921,14 @@ int32_t lsm6dsl_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsl_pp_od_t val)
lsm6dsl_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.pp_od = (uint8_t) val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -2526,14 +2945,18 @@ int32_t lsm6dsl_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsl_pp_od_t *val)
lsm6dsl_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- switch (ctrl3_c.pp_od) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ switch (ctrl3_c.pp_od)
+ {
case LSM6DSL_PUSH_PULL:
*val = LSM6DSL_PUSH_PULL;
break;
+
case LSM6DSL_OPEN_DRAIN:
*val = LSM6DSL_OPEN_DRAIN;
break;
+
default:
*val = LSM6DSL_PIN_MODE_ND;
break;
@@ -2550,16 +2973,20 @@ int32_t lsm6dsl_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsl_pp_od_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_pin_polarity_set(stmdev_ctx_t *ctx, lsm6dsl_h_lactive_t val)
+int32_t lsm6dsl_pin_polarity_set(stmdev_ctx_t *ctx,
+ lsm6dsl_h_lactive_t val)
{
lsm6dsl_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.h_lactive = (uint8_t) val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -2571,19 +2998,24 @@ int32_t lsm6dsl_pin_polarity_set(stmdev_ctx_t *ctx, lsm6dsl_h_lactive_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_pin_polarity_get(stmdev_ctx_t *ctx, lsm6dsl_h_lactive_t *val)
+int32_t lsm6dsl_pin_polarity_get(stmdev_ctx_t *ctx,
+ lsm6dsl_h_lactive_t *val)
{
lsm6dsl_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- switch (ctrl3_c.h_lactive) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ switch (ctrl3_c.h_lactive)
+ {
case LSM6DSL_ACTIVE_HIGH:
*val = LSM6DSL_ACTIVE_HIGH;
break;
+
case LSM6DSL_ACTIVE_LOW:
*val = LSM6DSL_ACTIVE_LOW;
break;
+
default:
*val = LSM6DSL_POLARITY_ND;
break;
@@ -2605,11 +3037,14 @@ int32_t lsm6dsl_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
ctrl4_c.int2_on_int1 = val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -2626,7 +3061,7 @@ int32_t lsm6dsl_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsl_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.int2_on_int1;
return ret;
@@ -2640,16 +3075,20 @@ int32_t lsm6dsl_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_int_notification_set(stmdev_ctx_t *ctx, lsm6dsl_lir_t val)
+int32_t lsm6dsl_int_notification_set(stmdev_ctx_t *ctx,
+ lsm6dsl_lir_t val)
{
lsm6dsl_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
tap_cfg.lir = (uint8_t) val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -2661,19 +3100,24 @@ int32_t lsm6dsl_int_notification_set(stmdev_ctx_t *ctx, lsm6dsl_lir_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_int_notification_get(stmdev_ctx_t *ctx, lsm6dsl_lir_t *val)
+int32_t lsm6dsl_int_notification_get(stmdev_ctx_t *ctx,
+ lsm6dsl_lir_t *val)
{
lsm6dsl_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- switch (tap_cfg.lir) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
+
+ switch (tap_cfg.lir)
+ {
case LSM6DSL_INT_PULSED:
*val = LSM6DSL_INT_PULSED;
break;
+
case LSM6DSL_INT_LATCHED:
*val = LSM6DSL_INT_LATCHED;
break;
+
default:
*val = LSM6DSL_INT_MODE;
break;
@@ -2708,12 +3152,16 @@ int32_t lsm6dsl_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_wake_up_ths_t wake_up_ths;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_THS, (uint8_t*)&wake_up_ths, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_THS,
+ (uint8_t *)&wake_up_ths, 1);
+
+ if (ret == 0)
+ {
wake_up_ths.wk_ths = val;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
}
+
return ret;
}
@@ -2730,7 +3178,8 @@ int32_t lsm6dsl_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsl_wake_up_ths_t wake_up_ths;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_THS, (uint8_t*)&wake_up_ths, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_THS,
+ (uint8_t *)&wake_up_ths, 1);
*val = wake_up_ths.wk_ths;
return ret;
@@ -2749,12 +3198,16 @@ int32_t lsm6dsl_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_wake_up_dur_t wake_up_dur;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
wake_up_dur.wake_dur = val;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -2771,7 +3224,8 @@ int32_t lsm6dsl_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsl_wake_up_dur_t wake_up_dur;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
*val = wake_up_dur.wake_dur;
return ret;
@@ -2803,11 +3257,14 @@ int32_t lsm6dsl_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
ctrl4_c.sleep = val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -2824,7 +3281,7 @@ int32_t lsm6dsl_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsl_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.sleep;
return ret;
@@ -2838,16 +3295,20 @@ int32_t lsm6dsl_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_act_mode_set(stmdev_ctx_t *ctx, lsm6dsl_inact_en_t val)
+int32_t lsm6dsl_act_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsl_inact_en_t val)
{
lsm6dsl_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
tap_cfg.inact_en = (uint8_t) val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -2859,25 +3320,32 @@ int32_t lsm6dsl_act_mode_set(stmdev_ctx_t *ctx, lsm6dsl_inact_en_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_act_mode_get(stmdev_ctx_t *ctx, lsm6dsl_inact_en_t *val)
+int32_t lsm6dsl_act_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsl_inact_en_t *val)
{
lsm6dsl_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- switch (tap_cfg.inact_en) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
+
+ switch (tap_cfg.inact_en)
+ {
case LSM6DSL_PROPERTY_DISABLE:
*val = LSM6DSL_PROPERTY_DISABLE;
break;
+
case LSM6DSL_XL_12Hz5_GY_NOT_AFFECTED:
*val = LSM6DSL_XL_12Hz5_GY_NOT_AFFECTED;
break;
+
case LSM6DSL_XL_12Hz5_GY_SLEEP:
*val = LSM6DSL_XL_12Hz5_GY_SLEEP;
break;
+
case LSM6DSL_XL_12Hz5_GY_PD:
*val = LSM6DSL_XL_12Hz5_GY_PD;
break;
+
default:
*val = LSM6DSL_ACT_MODE_ND;
break;
@@ -2899,12 +3367,16 @@ int32_t lsm6dsl_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_wake_up_dur_t wake_up_dur;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
wake_up_dur.sleep_dur = val;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -2921,7 +3393,8 @@ int32_t lsm6dsl_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsl_wake_up_dur_t wake_up_dur;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
*val = wake_up_dur.sleep_dur;
return ret;
@@ -2951,7 +3424,9 @@ int32_t lsm6dsl_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t lsm6dsl_tap_src_get(stmdev_ctx_t *ctx, lsm6dsl_tap_src_t *val)
{
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_SRC, (uint8_t*) val, 1);
+
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_SRC, (uint8_t *) val, 1);
+
return ret;
}
@@ -2967,11 +3442,14 @@ int32_t lsm6dsl_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
tap_cfg.tap_z_en = val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -2983,12 +3461,13 @@ int32_t lsm6dsl_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsl_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsl_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
*val = tap_cfg.tap_z_en;
return ret;
@@ -3007,11 +3486,14 @@ int32_t lsm6dsl_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
tap_cfg.tap_y_en = val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -3023,12 +3505,13 @@ int32_t lsm6dsl_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsl_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsl_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
*val = tap_cfg.tap_y_en;
return ret;
@@ -3047,11 +3530,14 @@ int32_t lsm6dsl_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
tap_cfg.tap_x_en = val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -3063,12 +3549,13 @@ int32_t lsm6dsl_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsl_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsl_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
*val = tap_cfg.tap_x_en;
return ret;
@@ -3087,12 +3574,16 @@ int32_t lsm6dsl_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_tap_ths_6d_t tap_ths_6d;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_THS_6D,
+ (uint8_t *)&tap_ths_6d, 1);
+
+ if (ret == 0)
+ {
tap_ths_6d.tap_ths = val;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
+ (uint8_t *)&tap_ths_6d, 1);
}
+
return ret;
}
@@ -3109,7 +3600,8 @@ int32_t lsm6dsl_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsl_tap_ths_6d_t tap_ths_6d;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_THS_6D,
+ (uint8_t *)&tap_ths_6d, 1);
*val = tap_ths_6d.tap_ths;
return ret;
@@ -3133,11 +3625,14 @@ int32_t lsm6dsl_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t*)&int_dur2, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t *)&int_dur2, 1);
+
+ if (ret == 0)
+ {
int_dur2.shock = val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t *)&int_dur2, 1);
}
+
return ret;
}
@@ -3159,7 +3654,7 @@ int32_t lsm6dsl_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsl_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t *)&int_dur2, 1);
*val = int_dur2.shock;
return ret;
@@ -3183,11 +3678,14 @@ int32_t lsm6dsl_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t*)&int_dur2, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t *)&int_dur2, 1);
+
+ if (ret == 0)
+ {
int_dur2.quiet = val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t *)&int_dur2, 1);
}
+
return ret;
}
@@ -3209,7 +3707,7 @@ int32_t lsm6dsl_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsl_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t *)&int_dur2, 1);
*val = int_dur2.quiet;
return ret;
@@ -3234,11 +3732,14 @@ int32_t lsm6dsl_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t*)&int_dur2, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t *)&int_dur2, 1);
+
+ if (ret == 0)
+ {
int_dur2.dur = val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t *)&int_dur2, 1);
}
+
return ret;
}
@@ -3261,7 +3762,7 @@ int32_t lsm6dsl_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsl_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t *)&int_dur2, 1);
*val = int_dur2.dur;
return ret;
@@ -3282,12 +3783,16 @@ int32_t lsm6dsl_tap_mode_set(stmdev_ctx_t *ctx,
lsm6dsl_wake_up_ths_t wake_up_ths;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_THS, (uint8_t*)&wake_up_ths, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_THS,
+ (uint8_t *)&wake_up_ths, 1);
+
+ if (ret == 0)
+ {
wake_up_ths.single_double_tap = (uint8_t) val;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
}
+
return ret;
}
@@ -3306,14 +3811,19 @@ int32_t lsm6dsl_tap_mode_get(stmdev_ctx_t *ctx,
lsm6dsl_wake_up_ths_t wake_up_ths;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_THS, (uint8_t*)&wake_up_ths, 1);
- switch (wake_up_ths.single_double_tap) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_THS,
+ (uint8_t *)&wake_up_ths, 1);
+
+ switch (wake_up_ths.single_double_tap)
+ {
case LSM6DSL_ONLY_SINGLE:
*val = LSM6DSL_ONLY_SINGLE;
break;
+
case LSM6DSL_BOTH_SINGLE_DOUBLE:
*val = LSM6DSL_BOTH_SINGLE_DOUBLE;
break;
+
default:
*val = LSM6DSL_TAP_MODE_ND;
break;
@@ -3350,11 +3860,14 @@ int32_t lsm6dsl_6d_feed_data_set(stmdev_ctx_t *ctx,
lsm6dsl_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
ctrl8_xl.low_pass_on_6d = (uint8_t) val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -3372,14 +3885,18 @@ int32_t lsm6dsl_6d_feed_data_get(stmdev_ctx_t *ctx,
lsm6dsl_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- switch (ctrl8_xl.low_pass_on_6d) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ switch (ctrl8_xl.low_pass_on_6d)
+ {
case LSM6DSL_ODR_DIV_2_FEED:
*val = LSM6DSL_ODR_DIV_2_FEED;
break;
+
case LSM6DSL_LPF2_FEED:
*val = LSM6DSL_LPF2_FEED;
break;
+
default:
*val = LSM6DSL_6D_FEED_ND;
break;
@@ -3396,16 +3913,22 @@ int32_t lsm6dsl_6d_feed_data_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_6d_threshold_set(stmdev_ctx_t *ctx, lsm6dsl_sixd_ths_t val)
+int32_t lsm6dsl_6d_threshold_set(stmdev_ctx_t *ctx,
+ lsm6dsl_sixd_ths_t val)
{
lsm6dsl_tap_ths_6d_t tap_ths_6d;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_THS_6D,
+ (uint8_t *)&tap_ths_6d, 1);
+
+ if (ret == 0)
+ {
tap_ths_6d.sixd_ths = (uint8_t) val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_THS_6D,
+ (uint8_t *)&tap_ths_6d, 1);
}
+
return ret;
}
@@ -3417,25 +3940,33 @@ int32_t lsm6dsl_6d_threshold_set(stmdev_ctx_t *ctx, lsm6dsl_sixd_ths_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_6d_threshold_get(stmdev_ctx_t *ctx, lsm6dsl_sixd_ths_t *val)
+int32_t lsm6dsl_6d_threshold_get(stmdev_ctx_t *ctx,
+ lsm6dsl_sixd_ths_t *val)
{
lsm6dsl_tap_ths_6d_t tap_ths_6d;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1);
- switch (tap_ths_6d.sixd_ths) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_THS_6D,
+ (uint8_t *)&tap_ths_6d, 1);
+
+ switch (tap_ths_6d.sixd_ths)
+ {
case LSM6DSL_DEG_80:
*val = LSM6DSL_DEG_80;
break;
+
case LSM6DSL_DEG_70:
*val = LSM6DSL_DEG_70;
break;
+
case LSM6DSL_DEG_60:
*val = LSM6DSL_DEG_60;
break;
+
case LSM6DSL_DEG_50:
*val = LSM6DSL_DEG_50;
break;
+
default:
*val = LSM6DSL_6D_TH_ND;
break;
@@ -3457,12 +3988,16 @@ int32_t lsm6dsl_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_tap_ths_6d_t tap_ths_6d;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_THS_6D,
+ (uint8_t *)&tap_ths_6d, 1);
+
+ if (ret == 0)
+ {
tap_ths_6d.d4d_en = val;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
+ (uint8_t *)&tap_ths_6d, 1);
}
+
return ret;
}
@@ -3479,7 +4014,8 @@ int32_t lsm6dsl_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsl_tap_ths_6d_t tap_ths_6d;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_THS_6D,
+ (uint8_t *)&tap_ths_6d, 1);
*val = tap_ths_6d.d4d_en;
return ret;
@@ -3512,20 +4048,27 @@ int32_t lsm6dsl_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_free_fall_t free_fall;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_FREE_FALL, (uint8_t*)&free_fall, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_FREE_FALL, (uint8_t *)&free_fall, 1);
+
+ if (ret == 0)
+ {
free_fall.ff_dur = (val & 0x1FU);
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_FREE_FALL, (uint8_t*)&free_fall, 1);
- if(ret == 0){
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_FREE_FALL, (uint8_t *)&free_fall, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
wake_up_dur.ff_dur = (val & 0x20U) >> 5;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
}
}
+
return ret;
}
@@ -3543,10 +4086,14 @@ int32_t lsm6dsl_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsl_free_fall_t free_fall;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_FREE_FALL, (uint8_t*)&free_fall, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_FREE_FALL, (uint8_t *)&free_fall, 1);
}
+
*val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
return ret;
@@ -3560,16 +4107,20 @@ int32_t lsm6dsl_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_ff_threshold_set(stmdev_ctx_t *ctx, lsm6dsl_ff_ths_t val)
+int32_t lsm6dsl_ff_threshold_set(stmdev_ctx_t *ctx,
+ lsm6dsl_ff_ths_t val)
{
lsm6dsl_free_fall_t free_fall;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_FREE_FALL, (uint8_t*)&free_fall, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_FREE_FALL, (uint8_t *)&free_fall, 1);
+
+ if (ret == 0)
+ {
free_fall.ff_ths = (uint8_t) val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_FREE_FALL, (uint8_t*)&free_fall, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_FREE_FALL, (uint8_t *)&free_fall, 1);
}
+
return ret;
}
@@ -3581,37 +4132,48 @@ int32_t lsm6dsl_ff_threshold_set(stmdev_ctx_t *ctx, lsm6dsl_ff_ths_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_ff_threshold_get(stmdev_ctx_t *ctx, lsm6dsl_ff_ths_t *val)
+int32_t lsm6dsl_ff_threshold_get(stmdev_ctx_t *ctx,
+ lsm6dsl_ff_ths_t *val)
{
lsm6dsl_free_fall_t free_fall;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_FREE_FALL, (uint8_t*)&free_fall, 1);
- switch (free_fall.ff_ths) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_FREE_FALL, (uint8_t *)&free_fall, 1);
+
+ switch (free_fall.ff_ths)
+ {
case LSM6DSL_FF_TSH_156mg:
*val = LSM6DSL_FF_TSH_156mg;
break;
+
case LSM6DSL_FF_TSH_219mg:
*val = LSM6DSL_FF_TSH_219mg;
break;
+
case LSM6DSL_FF_TSH_250mg:
*val = LSM6DSL_FF_TSH_250mg;
break;
+
case LSM6DSL_FF_TSH_312mg:
*val = LSM6DSL_FF_TSH_312mg;
break;
+
case LSM6DSL_FF_TSH_344mg:
*val = LSM6DSL_FF_TSH_344mg;
break;
+
case LSM6DSL_FF_TSH_406mg:
*val = LSM6DSL_FF_TSH_406mg;
break;
+
case LSM6DSL_FF_TSH_469mg:
*val = LSM6DSL_FF_TSH_469mg;
break;
+
case LSM6DSL_FF_TSH_500mg:
*val = LSM6DSL_FF_TSH_500mg;
break;
+
default:
*val = LSM6DSL_FF_TSH_ND;
break;
@@ -3647,16 +4209,23 @@ int32_t lsm6dsl_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
lsm6dsl_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
- fifo_ctrl1.fth = (uint8_t) (0x00FFU & val);
- fifo_ctrl2.fth = (uint8_t) (( 0x0700U & val ) >> 8);
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl1.fth = (uint8_t)(0x00FFU & val);
+ fifo_ctrl2.fth = (uint8_t)((0x0700U & val) >> 8);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL1,
+ (uint8_t *)&fifo_ctrl1, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
}
+
return ret;
}
@@ -3674,10 +4243,15 @@ int32_t lsm6dsl_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
lsm6dsl_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1);
- if(ret == 0){
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL1,
+ (uint8_t *)&fifo_ctrl1, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
}
+
*val = ((uint16_t)fifo_ctrl2.fth << 8) + (uint16_t)fifo_ctrl1.fth;
return ret;
@@ -3700,12 +4274,14 @@ int32_t lsm6dsl_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
int32_t ret;
ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_STATUS1,
- (uint8_t*)&fifo_status1, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_status1, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
- *val = ( (uint16_t) fifo_status2.diff_fifo << 8) +
- (uint16_t) fifo_status1.diff_fifo;
+ (uint8_t *)&fifo_status2, 1);
+ *val = ((uint16_t) fifo_status2.diff_fifo << 8) +
+ (uint16_t) fifo_status1.diff_fifo;
}
return ret;
@@ -3724,7 +4300,8 @@ int32_t lsm6dsl_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsl_fifo_status2_t fifo_status2;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_STATUS2, (uint8_t*)&fifo_status2, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_STATUS2,
+ (uint8_t *)&fifo_status2, 1);
*val = fifo_status2.waterm;
return ret;
@@ -3746,13 +4323,16 @@ int32_t lsm6dsl_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val)
int32_t ret;
ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_STATUS3,
- (uint8_t*)&fifo_status3, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_status3, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_STATUS4,
- (uint8_t*)&fifo_status4, 1);
- *val = ( (uint16_t)fifo_status4.fifo_pattern << 8) +
- fifo_status3.fifo_pattern;
+ (uint8_t *)&fifo_status4, 1);
+ *val = ((uint16_t)fifo_status4.fifo_pattern << 8) +
+ fifo_status3.fifo_pattern;
}
+
return ret;
}
@@ -3769,11 +4349,14 @@ int32_t lsm6dsl_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl2.fifo_temp_en = val;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
return ret;
@@ -3792,7 +4375,8 @@ int32_t lsm6dsl_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsl_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
*val = fifo_ctrl2.fifo_temp_en;
return ret;
@@ -3814,18 +4398,25 @@ int32_t lsm6dsl_fifo_write_trigger_set(stmdev_ctx_t *ctx,
lsm6dsl_master_config_t master_config;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl2.timer_pedo_fifo_drdy = (uint8_t)val & 0x01U;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
master_config.data_valid_sel_fifo = (((uint8_t)val & 0x02U) >> 1);
ret = lsm6dsl_write_reg(ctx, LSM6DSL_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
}
}
@@ -3849,22 +4440,29 @@ int32_t lsm6dsl_fifo_write_trigger_get(stmdev_ctx_t *ctx,
lsm6dsl_master_config_t master_config;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
- switch ( ( fifo_ctrl2.timer_pedo_fifo_drdy << 1 ) +
- fifo_ctrl2. timer_pedo_fifo_drdy ) {
+ switch ((fifo_ctrl2.timer_pedo_fifo_drdy << 1) +
+ fifo_ctrl2. timer_pedo_fifo_drdy)
+ {
case LSM6DSL_TRG_XL_GY_DRDY:
*val = LSM6DSL_TRG_XL_GY_DRDY;
break;
+
case LSM6DSL_TRG_STEP_DETECT:
*val = LSM6DSL_TRG_STEP_DETECT;
break;
+
case LSM6DSL_TRG_SH_DRDY:
*val = LSM6DSL_TRG_SH_DRDY;
break;
+
default:
*val = LSM6DSL_TRG_SH_ND;
break;
@@ -3889,12 +4487,16 @@ int32_t lsm6dsl_fifo_pedo_and_timestamp_batch_set(stmdev_ctx_t *ctx,
lsm6dsl_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl2.timer_pedo_fifo_en = val;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
+
return ret;
}
@@ -3913,7 +4515,8 @@ int32_t lsm6dsl_fifo_pedo_and_timestamp_batch_get(stmdev_ctx_t *ctx,
lsm6dsl_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
*val = fifo_ctrl2.timer_pedo_fifo_en;
return ret;
@@ -3934,12 +4537,16 @@ int32_t lsm6dsl_fifo_xl_batch_set(stmdev_ctx_t *ctx,
lsm6dsl_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL3, (uint8_t*)&fifo_ctrl3, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL3,
+ (uint8_t *)&fifo_ctrl3, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl3.dec_fifo_xl = (uint8_t)val;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
+ (uint8_t *)&fifo_ctrl3, 1);
}
+
return ret;
}
@@ -3958,32 +4565,43 @@ int32_t lsm6dsl_fifo_xl_batch_get(stmdev_ctx_t *ctx,
lsm6dsl_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL3, (uint8_t*)&fifo_ctrl3, 1);
- switch (fifo_ctrl3.dec_fifo_xl) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL3,
+ (uint8_t *)&fifo_ctrl3, 1);
+
+ switch (fifo_ctrl3.dec_fifo_xl)
+ {
case LSM6DSL_FIFO_XL_DISABLE:
*val = LSM6DSL_FIFO_XL_DISABLE;
break;
+
case LSM6DSL_FIFO_XL_NO_DEC:
*val = LSM6DSL_FIFO_XL_NO_DEC;
break;
+
case LSM6DSL_FIFO_XL_DEC_2:
*val = LSM6DSL_FIFO_XL_DEC_2;
break;
+
case LSM6DSL_FIFO_XL_DEC_3:
*val = LSM6DSL_FIFO_XL_DEC_3;
break;
+
case LSM6DSL_FIFO_XL_DEC_4:
*val = LSM6DSL_FIFO_XL_DEC_4;
break;
+
case LSM6DSL_FIFO_XL_DEC_8:
*val = LSM6DSL_FIFO_XL_DEC_8;
break;
+
case LSM6DSL_FIFO_XL_DEC_16:
*val = LSM6DSL_FIFO_XL_DEC_16;
break;
+
case LSM6DSL_FIFO_XL_DEC_32:
*val = LSM6DSL_FIFO_XL_DEC_32;
break;
+
default:
*val = LSM6DSL_FIFO_XL_DEC_ND;
break;
@@ -4007,11 +4625,16 @@ int32_t lsm6dsl_fifo_gy_batch_set(stmdev_ctx_t *ctx,
lsm6dsl_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL3, (uint8_t*)&fifo_ctrl3, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL3,
+ (uint8_t *)&fifo_ctrl3, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl3.dec_fifo_gyro = (uint8_t)val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL3, (uint8_t*)&fifo_ctrl3, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL3,
+ (uint8_t *)&fifo_ctrl3, 1);
}
+
return ret;
}
@@ -4030,32 +4653,43 @@ int32_t lsm6dsl_fifo_gy_batch_get(stmdev_ctx_t *ctx,
lsm6dsl_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL3, (uint8_t*)&fifo_ctrl3, 1);
- switch (fifo_ctrl3.dec_fifo_gyro) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL3,
+ (uint8_t *)&fifo_ctrl3, 1);
+
+ switch (fifo_ctrl3.dec_fifo_gyro)
+ {
case LSM6DSL_FIFO_GY_DISABLE:
*val = LSM6DSL_FIFO_GY_DISABLE;
break;
+
case LSM6DSL_FIFO_GY_NO_DEC:
*val = LSM6DSL_FIFO_GY_NO_DEC;
break;
+
case LSM6DSL_FIFO_GY_DEC_2:
*val = LSM6DSL_FIFO_GY_DEC_2;
break;
+
case LSM6DSL_FIFO_GY_DEC_3:
*val = LSM6DSL_FIFO_GY_DEC_3;
break;
+
case LSM6DSL_FIFO_GY_DEC_4:
*val = LSM6DSL_FIFO_GY_DEC_4;
break;
+
case LSM6DSL_FIFO_GY_DEC_8:
*val = LSM6DSL_FIFO_GY_DEC_8;
break;
+
case LSM6DSL_FIFO_GY_DEC_16:
*val = LSM6DSL_FIFO_GY_DEC_16;
break;
+
case LSM6DSL_FIFO_GY_DEC_32:
*val = LSM6DSL_FIFO_GY_DEC_32;
break;
+
default:
*val = LSM6DSL_FIFO_GY_DEC_ND;
break;
@@ -4079,12 +4713,16 @@ int32_t lsm6dsl_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx,
lsm6dsl_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl4.dec_ds3_fifo = (uint8_t)val;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -4103,32 +4741,43 @@ int32_t lsm6dsl_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx,
lsm6dsl_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
- switch (fifo_ctrl4.dec_ds3_fifo) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ switch (fifo_ctrl4.dec_ds3_fifo)
+ {
case LSM6DSL_FIFO_DS3_DISABLE:
*val = LSM6DSL_FIFO_DS3_DISABLE;
break;
+
case LSM6DSL_FIFO_DS3_NO_DEC:
*val = LSM6DSL_FIFO_DS3_NO_DEC;
break;
+
case LSM6DSL_FIFO_DS3_DEC_2:
*val = LSM6DSL_FIFO_DS3_DEC_2;
break;
+
case LSM6DSL_FIFO_DS3_DEC_3:
*val = LSM6DSL_FIFO_DS3_DEC_3;
break;
+
case LSM6DSL_FIFO_DS3_DEC_4:
*val = LSM6DSL_FIFO_DS3_DEC_4;
break;
+
case LSM6DSL_FIFO_DS3_DEC_8:
*val = LSM6DSL_FIFO_DS3_DEC_8;
break;
+
case LSM6DSL_FIFO_DS3_DEC_16:
*val = LSM6DSL_FIFO_DS3_DEC_16;
break;
+
case LSM6DSL_FIFO_DS3_DEC_32:
*val = LSM6DSL_FIFO_DS3_DEC_32;
break;
+
default:
*val = LSM6DSL_FIFO_DS3_DEC_ND;
break;
@@ -4152,12 +4801,16 @@ int32_t lsm6dsl_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx,
lsm6dsl_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl4.dec_ds4_fifo = (uint8_t)val;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -4176,32 +4829,43 @@ int32_t lsm6dsl_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx,
lsm6dsl_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
- switch (fifo_ctrl4.dec_ds4_fifo) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ switch (fifo_ctrl4.dec_ds4_fifo)
+ {
case LSM6DSL_FIFO_DS4_DISABLE:
*val = LSM6DSL_FIFO_DS4_DISABLE;
break;
+
case LSM6DSL_FIFO_DS4_NO_DEC:
*val = LSM6DSL_FIFO_DS4_NO_DEC;
break;
+
case LSM6DSL_FIFO_DS4_DEC_2:
*val = LSM6DSL_FIFO_DS4_DEC_2;
break;
+
case LSM6DSL_FIFO_DS4_DEC_3:
*val = LSM6DSL_FIFO_DS4_DEC_3;
break;
+
case LSM6DSL_FIFO_DS4_DEC_4:
*val = LSM6DSL_FIFO_DS4_DEC_4;
break;
+
case LSM6DSL_FIFO_DS4_DEC_8:
*val = LSM6DSL_FIFO_DS4_DEC_8;
break;
+
case LSM6DSL_FIFO_DS4_DEC_16:
*val = LSM6DSL_FIFO_DS4_DEC_16;
break;
+
case LSM6DSL_FIFO_DS4_DEC_32:
*val = LSM6DSL_FIFO_DS4_DEC_32;
break;
+
default:
*val = LSM6DSL_FIFO_DS4_DEC_ND;
break;
@@ -4218,16 +4882,22 @@ int32_t lsm6dsl_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dsl_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dsl_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl4.only_high_data = val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -4239,12 +4909,14 @@ int32_t lsm6dsl_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsl_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsl_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
*val = fifo_ctrl4.only_high_data;
return ret;
@@ -4264,11 +4936,16 @@ int32_t lsm6dsl_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl4.stop_on_fth = val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -4286,7 +4963,8 @@ int32_t lsm6dsl_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsl_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
*val = fifo_ctrl4.stop_on_fth;
return ret;
@@ -4300,16 +4978,22 @@ int32_t lsm6dsl_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_fifo_mode_set(stmdev_ctx_t *ctx, lsm6dsl_fifo_mode_t val)
+int32_t lsm6dsl_fifo_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsl_fifo_mode_t val)
{
lsm6dsl_fifo_ctrl5_t fifo_ctrl5;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL5,
+ (uint8_t *)&fifo_ctrl5, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl5.fifo_mode = (uint8_t)val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL5,
+ (uint8_t *)&fifo_ctrl5, 1);
}
+
return ret;
}
@@ -4321,28 +5005,37 @@ int32_t lsm6dsl_fifo_mode_set(stmdev_ctx_t *ctx, lsm6dsl_fifo_mode_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_fifo_mode_get(stmdev_ctx_t *ctx, lsm6dsl_fifo_mode_t *val)
+int32_t lsm6dsl_fifo_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsl_fifo_mode_t *val)
{
lsm6dsl_fifo_ctrl5_t fifo_ctrl5;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1);
- switch (fifo_ctrl5.fifo_mode) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL5,
+ (uint8_t *)&fifo_ctrl5, 1);
+
+ switch (fifo_ctrl5.fifo_mode)
+ {
case LSM6DSL_BYPASS_MODE:
*val = LSM6DSL_BYPASS_MODE;
break;
+
case LSM6DSL_FIFO_MODE:
*val = LSM6DSL_FIFO_MODE;
break;
+
case LSM6DSL_STREAM_TO_FIFO_MODE:
*val = LSM6DSL_STREAM_TO_FIFO_MODE;
break;
+
case LSM6DSL_BYPASS_TO_STREAM_MODE:
*val = LSM6DSL_BYPASS_TO_STREAM_MODE;
break;
+
case LSM6DSL_STREAM_MODE:
*val = LSM6DSL_STREAM_MODE;
break;
+
default:
*val = LSM6DSL_FIFO_MODE_ND;
break;
@@ -4359,16 +5052,22 @@ int32_t lsm6dsl_fifo_mode_get(stmdev_ctx_t *ctx, lsm6dsl_fifo_mode_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_fifo_data_rate_set(stmdev_ctx_t *ctx, lsm6dsl_odr_fifo_t val)
+int32_t lsm6dsl_fifo_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dsl_odr_fifo_t val)
{
lsm6dsl_fifo_ctrl5_t fifo_ctrl5;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL5,
+ (uint8_t *)&fifo_ctrl5, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl5.odr_fifo = (uint8_t)val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL5,
+ (uint8_t *)&fifo_ctrl5, 1);
}
+
return ret;
}
@@ -4380,46 +5079,61 @@ int32_t lsm6dsl_fifo_data_rate_set(stmdev_ctx_t *ctx, lsm6dsl_odr_fifo_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_fifo_data_rate_get(stmdev_ctx_t *ctx, lsm6dsl_odr_fifo_t *val)
+int32_t lsm6dsl_fifo_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dsl_odr_fifo_t *val)
{
lsm6dsl_fifo_ctrl5_t fifo_ctrl5;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1);
- switch (fifo_ctrl5.odr_fifo) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL5,
+ (uint8_t *)&fifo_ctrl5, 1);
+
+ switch (fifo_ctrl5.odr_fifo)
+ {
case LSM6DSL_FIFO_DISABLE:
*val = LSM6DSL_FIFO_DISABLE;
break;
+
case LSM6DSL_FIFO_12Hz5:
*val = LSM6DSL_FIFO_12Hz5;
break;
+
case LSM6DSL_FIFO_26Hz:
*val = LSM6DSL_FIFO_26Hz;
break;
+
case LSM6DSL_FIFO_52Hz:
*val = LSM6DSL_FIFO_52Hz;
break;
+
case LSM6DSL_FIFO_104Hz:
*val = LSM6DSL_FIFO_104Hz;
break;
+
case LSM6DSL_FIFO_208Hz:
*val = LSM6DSL_FIFO_208Hz;
break;
+
case LSM6DSL_FIFO_416Hz:
*val = LSM6DSL_FIFO_416Hz;
break;
+
case LSM6DSL_FIFO_833Hz:
*val = LSM6DSL_FIFO_833Hz;
break;
+
case LSM6DSL_FIFO_1k66Hz:
*val = LSM6DSL_FIFO_1k66Hz;
break;
+
case LSM6DSL_FIFO_3k33Hz:
*val = LSM6DSL_FIFO_3k33Hz;
break;
+
case LSM6DSL_FIFO_6k66Hz:
*val = LSM6DSL_FIFO_6k66Hz;
break;
+
default:
*val = LSM6DSL_FIFO_RATE_ND;
break;
@@ -4449,16 +5163,20 @@ int32_t lsm6dsl_fifo_data_rate_get(stmdev_ctx_t *ctx, lsm6dsl_odr_fifo_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
- int32_t lsm6dsl_den_polarity_set(stmdev_ctx_t *ctx, lsm6dsl_den_lh_t val)
+int32_t lsm6dsl_den_polarity_set(stmdev_ctx_t *ctx,
+ lsm6dsl_den_lh_t val)
{
lsm6dsl_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ if (ret == 0)
+ {
ctrl5_c.den_lh = (uint8_t)val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -4470,19 +5188,24 @@ int32_t lsm6dsl_fifo_data_rate_get(stmdev_ctx_t *ctx, lsm6dsl_odr_fifo_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_den_polarity_get(stmdev_ctx_t *ctx, lsm6dsl_den_lh_t *val)
+int32_t lsm6dsl_den_polarity_get(stmdev_ctx_t *ctx,
+ lsm6dsl_den_lh_t *val)
{
lsm6dsl_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- switch (ctrl5_c.den_lh) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ switch (ctrl5_c.den_lh)
+ {
case LSM6DSL_DEN_ACT_LOW:
*val = LSM6DSL_DEN_ACT_LOW;
break;
+
case LSM6DSL_DEN_ACT_HIGH:
*val = LSM6DSL_DEN_ACT_HIGH;
break;
+
default:
*val = LSM6DSL_DEN_POL_ND;
break;
@@ -4499,16 +5222,20 @@ int32_t lsm6dsl_den_polarity_get(stmdev_ctx_t *ctx, lsm6dsl_den_lh_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_den_mode_set(stmdev_ctx_t *ctx, lsm6dsl_den_mode_t val)
+int32_t lsm6dsl_den_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsl_den_mode_t val)
{
lsm6dsl_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
ctrl6_c.den_mode = (uint8_t)val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -4520,25 +5247,32 @@ int32_t lsm6dsl_den_mode_set(stmdev_ctx_t *ctx, lsm6dsl_den_mode_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_den_mode_get(stmdev_ctx_t *ctx, lsm6dsl_den_mode_t *val)
+int32_t lsm6dsl_den_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsl_den_mode_t *val)
{
lsm6dsl_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- switch (ctrl6_c.den_mode) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ switch (ctrl6_c.den_mode)
+ {
case LSM6DSL_DEN_DISABLE:
*val = LSM6DSL_DEN_DISABLE;
break;
+
case LSM6DSL_LEVEL_LETCHED:
*val = LSM6DSL_LEVEL_LETCHED;
break;
+
case LSM6DSL_LEVEL_TRIGGER:
*val = LSM6DSL_LEVEL_TRIGGER;
break;
+
case LSM6DSL_EDGE_TRIGGER:
*val = LSM6DSL_EDGE_TRIGGER;
break;
+
default:
*val = LSM6DSL_DEN_MODE_ND;
break;
@@ -4556,24 +5290,32 @@ int32_t lsm6dsl_den_mode_get(stmdev_ctx_t *ctx, lsm6dsl_den_mode_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_den_enable_set(stmdev_ctx_t *ctx, lsm6dsl_den_xl_en_t val)
+int32_t lsm6dsl_den_enable_set(stmdev_ctx_t *ctx,
+ lsm6dsl_den_xl_en_t val)
{
lsm6dsl_ctrl4_c_t ctrl4_c;
lsm6dsl_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
ctrl9_xl.den_xl_g = (uint8_t)val & 0x01U;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
ctrl4_c.den_xl_en = (uint8_t)val & 0x02U;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
}
}
+
return ret;
}
@@ -4586,25 +5328,33 @@ int32_t lsm6dsl_den_enable_set(stmdev_ctx_t *ctx, lsm6dsl_den_xl_en_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_den_enable_get(stmdev_ctx_t *ctx, lsm6dsl_den_xl_en_t *val)
+int32_t lsm6dsl_den_enable_get(stmdev_ctx_t *ctx,
+ lsm6dsl_den_xl_en_t *val)
{
lsm6dsl_ctrl4_c_t ctrl4_c;
lsm6dsl_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- switch ( ( ctrl4_c.den_xl_en << 1) + ctrl9_xl.den_xl_g ) {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ switch ((ctrl4_c.den_xl_en << 1) + ctrl9_xl.den_xl_g)
+ {
case LSM6DSL_STAMP_IN_GY_DATA:
*val = LSM6DSL_STAMP_IN_GY_DATA;
break;
+
case LSM6DSL_STAMP_IN_XL_DATA:
*val = LSM6DSL_STAMP_IN_XL_DATA;
break;
+
case LSM6DSL_STAMP_IN_GY_XL_DATA:
*val = LSM6DSL_STAMP_IN_GY_XL_DATA;
break;
+
default:
*val = LSM6DSL_DEN_STAMP_ND;
break;
@@ -4627,11 +5377,14 @@ int32_t lsm6dsl_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
ctrl9_xl.den_z = val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -4648,7 +5401,7 @@ int32_t lsm6dsl_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsl_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
*val = ctrl9_xl.den_z;
return ret;
@@ -4667,11 +5420,14 @@ int32_t lsm6dsl_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
ctrl9_xl.den_y = val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -4688,7 +5444,7 @@ int32_t lsm6dsl_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsl_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
*val = ctrl9_xl.den_y;
return ret;
@@ -4707,11 +5463,14 @@ int32_t lsm6dsl_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
ctrl9_xl.den_x = val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -4728,7 +5487,7 @@ int32_t lsm6dsl_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsl_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
*val = ctrl9_xl.den_x;
return ret;
@@ -4759,11 +5518,14 @@ int32_t lsm6dsl_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
ctrl10_c.pedo_rst_step = val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
}
+
return ret;
}
@@ -4780,7 +5542,7 @@ int32_t lsm6dsl_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsl_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
*val = ctrl10_c.pedo_rst_step;
return ret;
@@ -4799,13 +5561,18 @@ int32_t lsm6dsl_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
ctrl10_c.pedo_en = val;
- if (val != 0x00U) {
+
+ if (val != 0x00U)
+ {
ctrl10_c.func_en = val;
}
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
}
return ret;
@@ -4824,7 +5591,7 @@ int32_t lsm6dsl_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsl_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
*val = ctrl10_c.pedo_en;
return ret;
@@ -4845,18 +5612,25 @@ int32_t lsm6dsl_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_CONFIG_PEDO_THS_MIN,
- (uint8_t*)&config_pedo_ths_min, 1);
- if(ret == 0){
- config_pedo_ths_min.ths_min = val;
+ (uint8_t *)&config_pedo_ths_min, 1);
+
+ if (ret == 0)
+ {
+ config_pedo_ths_min.ths_min = val;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_CONFIG_PEDO_THS_MIN,
- (uint8_t*)&config_pedo_ths_min, 1);
- if(ret == 0){
- ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
- }
+ (uint8_t *)&config_pedo_ths_min, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
+ }
+
return ret;
}
@@ -4873,15 +5647,20 @@ int32_t lsm6dsl_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsl_config_pedo_ths_min_t config_pedo_ths_min;
int32_t ret;
- ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CONFIG_PEDO_THS_MIN,
- (uint8_t*)&config_pedo_ths_min, 1);
- if(ret == 0){
- *val = config_pedo_ths_min.ths_min;
- ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
- }
+ ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CONFIG_PEDO_THS_MIN,
+ (uint8_t *)&config_pedo_ths_min, 1);
+
+ if (ret == 0)
+ {
+ *val = config_pedo_ths_min.ths_min;
+ ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
+ }
+
return ret;
}
@@ -4894,24 +5673,32 @@ int32_t lsm6dsl_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_pedo_full_scale_set(stmdev_ctx_t *ctx, lsm6dsl_pedo_fs_t val)
+int32_t lsm6dsl_pedo_full_scale_set(stmdev_ctx_t *ctx,
+ lsm6dsl_pedo_fs_t val)
{
lsm6dsl_config_pedo_ths_min_t config_pedo_ths_min;
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_CONFIG_PEDO_THS_MIN,
- (uint8_t*)&config_pedo_ths_min, 1);
- if(ret == 0){
- config_pedo_ths_min.pedo_fs = (uint8_t) val;
+ (uint8_t *)&config_pedo_ths_min, 1);
+
+ if (ret == 0)
+ {
+ config_pedo_ths_min.pedo_fs = (uint8_t) val;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_CONFIG_PEDO_THS_MIN,
- (uint8_t*)&config_pedo_ths_min, 1);
- if(ret == 0){
+ (uint8_t *)&config_pedo_ths_min, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
}
+
return ret;
}
@@ -4924,30 +5711,40 @@ int32_t lsm6dsl_pedo_full_scale_set(stmdev_ctx_t *ctx, lsm6dsl_pedo_fs_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_pedo_full_scale_get(stmdev_ctx_t *ctx, lsm6dsl_pedo_fs_t *val)
+int32_t lsm6dsl_pedo_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6dsl_pedo_fs_t *val)
{
lsm6dsl_config_pedo_ths_min_t config_pedo_ths_min;
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_CONFIG_PEDO_THS_MIN,
- (uint8_t*)&config_pedo_ths_min, 1);
- if(ret == 0){
- switch (config_pedo_ths_min.pedo_fs) {
- case LSM6DSL_PEDO_AT_2g:
+ (uint8_t *)&config_pedo_ths_min, 1);
+
+ if (ret == 0)
+ {
+ switch (config_pedo_ths_min.pedo_fs)
+ {
+ case LSM6DSL_PEDO_AT_2g:
*val = LSM6DSL_PEDO_AT_2g;
break;
+
case LSM6DSL_PEDO_AT_4g:
*val = LSM6DSL_PEDO_AT_4g;
break;
+
default:
*val = LSM6DSL_PEDO_FS_ND;
break;
}
+
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
+
return ret;
}
@@ -4959,24 +5756,32 @@ int32_t lsm6dsl_pedo_full_scale_get(stmdev_ctx_t *ctx, lsm6dsl_pedo_fs_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dsl_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dsl_pedo_deb_reg_t pedo_deb_reg;
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_PEDO_DEB_REG,
- (uint8_t*)&pedo_deb_reg, 1);
- if(ret == 0){
+ (uint8_t *)&pedo_deb_reg, 1);
+
+ if (ret == 0)
+ {
pedo_deb_reg.deb_step = val;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_PEDO_DEB_REG,
- (uint8_t*)&pedo_deb_reg, 1);
- if(ret == 0){
- ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
- }
+ (uint8_t *)&pedo_deb_reg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
+ }
+
return ret;
}
@@ -4988,20 +5793,25 @@ int32_t lsm6dsl_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsl_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsl_pedo_deb_reg_t pedo_deb_reg;
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_PEDO_DEB_REG,
- (uint8_t*)&pedo_deb_reg, 1);
- if(ret == 0){
- *val = pedo_deb_reg.deb_step;
- ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
- }
+ (uint8_t *)&pedo_deb_reg, 1);
+
+ if (ret == 0)
+ {
+ *val = pedo_deb_reg.deb_step;
+ ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
+ }
return ret;
}
@@ -5022,18 +5832,25 @@ int32_t lsm6dsl_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_PEDO_DEB_REG,
- (uint8_t*)&pedo_deb_reg, 1);
- if(ret == 0){
+ (uint8_t *)&pedo_deb_reg, 1);
+
+ if (ret == 0)
+ {
pedo_deb_reg.deb_time = val;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_PEDO_DEB_REG,
- (uint8_t*)&pedo_deb_reg, 1);
- if(ret == 0){
+ (uint8_t *)&pedo_deb_reg, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
}
+
return ret;
}
@@ -5053,14 +5870,19 @@ int32_t lsm6dsl_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_PEDO_DEB_REG,
- (uint8_t*)&pedo_deb_reg, 1);
- if(ret == 0){
+ (uint8_t *)&pedo_deb_reg, 1);
+
+ if (ret == 0)
+ {
*val = pedo_deb_reg.deb_time;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
+
return ret;
}
@@ -5072,17 +5894,23 @@ int32_t lsm6dsl_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_pedo_steps_period_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsl_pedo_steps_period_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_write_reg(ctx, LSM6DSL_STEP_COUNT_DELTA, buff, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
+
return ret;
}
@@ -5094,17 +5922,23 @@ int32_t lsm6dsl_pedo_steps_period_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_pedo_steps_period_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsl_pedo_steps_period_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_STEP_COUNT_DELTA, buff, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
+
return ret;
}
@@ -5134,14 +5968,19 @@ int32_t lsm6dsl_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
ctrl10_c.sign_motion_en = val;
- if (val != 0x00U) {
+
+ if (val != 0x00U)
+ {
ctrl10_c.func_en = val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
}
}
+
return ret;
}
@@ -5158,7 +5997,7 @@ int32_t lsm6dsl_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsl_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
*val = ctrl10_c.sign_motion_en;
return ret;
@@ -5177,12 +6016,17 @@ int32_t lsm6dsl_motion_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_write_reg(ctx, LSM6DSL_SM_THS, buff, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
+
return ret;
}
@@ -5199,12 +6043,17 @@ int32_t lsm6dsl_motion_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_SM_THS, buff, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
+
return ret;
}
@@ -5234,14 +6083,20 @@ int32_t lsm6dsl_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
ctrl10_c.tilt_en = val;
- if (val != 0x00U) {
+
+ if (val != 0x00U)
+ {
ctrl10_c.func_en = val;
}
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
}
+
return ret;
}
@@ -5258,7 +6113,7 @@ int32_t lsm6dsl_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsl_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
*val = ctrl10_c.tilt_en;
return ret;
@@ -5277,14 +6132,20 @@ int32_t lsm6dsl_wrist_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
ctrl10_c.wrist_tilt_en = val;
- if (val != 0x00U) {
+
+ if (val != 0x00U)
+ {
ctrl10_c.func_en = val;
}
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
}
+
return ret;
}
@@ -5301,7 +6162,7 @@ int32_t lsm6dsl_wrist_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsl_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
*val = ctrl10_c.wrist_tilt_en;
return ret;
@@ -5322,12 +6183,17 @@ int32_t lsm6dsl_tilt_latency_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_B);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_write_reg(ctx, LSM6DSL_A_WRIST_TILT_LAT, buff, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
+
return ret;
}
@@ -5346,12 +6212,17 @@ int32_t lsm6dsl_tilt_latency_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_B);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_A_WRIST_TILT_LAT, buff, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
+
return ret;
}
@@ -5370,12 +6241,17 @@ int32_t lsm6dsl_tilt_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_B);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_write_reg(ctx, LSM6DSL_A_WRIST_TILT_THS, buff, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
+
return ret;
}
@@ -5394,12 +6270,17 @@ int32_t lsm6dsl_tilt_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_B);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_A_WRIST_TILT_THS, buff, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
+
return ret;
}
@@ -5417,13 +6298,18 @@ int32_t lsm6dsl_tilt_src_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_B);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_A_WRIST_TILT_MASK,
- (uint8_t*) val, 1);
- if(ret == 0){
+ (uint8_t *) val, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
+
return ret;
}
@@ -5441,15 +6327,19 @@ int32_t lsm6dsl_tilt_src_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_B);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_A_WRIST_TILT_MASK,
- (uint8_t*) val, 1);
- if(ret == 0){
+ (uint8_t *) val, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
- return ret;
+ return ret;
}
/**
@@ -5478,11 +6368,14 @@ int32_t lsm6dsl_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
ctrl9_xl.soft_en = val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -5499,7 +6392,7 @@ int32_t lsm6dsl_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsl_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
*val = ctrl9_xl.soft_en;
return ret;
@@ -5520,22 +6413,31 @@ int32_t lsm6dsl_mag_hard_iron_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
master_config.iron_en = val;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
- if (val != 0x00U) {
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
+ if (val != 0x00U)
+ {
ctrl10_c.func_en = val;
}
+
ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL10_C,
- (uint8_t*)&ctrl10_c, 1);
+ (uint8_t *)&ctrl10_c, 1);
}
}
}
+
return ret;
}
@@ -5553,7 +6455,7 @@ int32_t lsm6dsl_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
*val = master_config.iron_en;
return ret;
@@ -5568,17 +6470,23 @@ int32_t lsm6dsl_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_mag_soft_iron_mat_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsl_mag_soft_iron_mat_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_write_reg(ctx, LSM6DSL_MAG_SI_XX, buff, 9);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
+
return ret;
}
@@ -5591,17 +6499,23 @@ int32_t lsm6dsl_mag_soft_iron_mat_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_mag_soft_iron_mat_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsl_mag_soft_iron_mat_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_MAG_SI_XX, buff, 9);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
+
return ret;
}
@@ -5614,17 +6528,29 @@ int32_t lsm6dsl_mag_soft_iron_mat_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_mag_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsl_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
+ buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
+ buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
+ buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
+ buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
+ buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
+ buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
ret = lsm6dsl_write_reg(ctx, LSM6DSL_MAG_OFFX_L, buff, 6);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
+
return ret;
}
@@ -5637,17 +6563,29 @@ int32_t lsm6dsl_mag_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_mag_offset_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsl_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_MAG_OFFX_L, buff, 6);
- if(ret == 0){
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
+ if (ret == 0)
+ {
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
+
return ret;
}
@@ -5664,7 +6602,7 @@ int32_t lsm6dsl_mag_offset_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
*/
- /**
+/**
* @brief Enable function.[set]
*
* @param ctx Read / write interface definitions
@@ -5677,10 +6615,12 @@ int32_t lsm6dsl_func_en_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsl_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
ctrl10_c.func_en = val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
}
return ret;
@@ -5701,12 +6641,15 @@ int32_t lsm6dsl_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsl_read_reg(ctx, LSM6DSL_SENSOR_SYNC_TIME_FRAME,
- (uint8_t*)&sensor_sync_time_frame, 1);
- if(ret == 0){
- sensor_sync_time_frame.tph = val;
+ (uint8_t *)&sensor_sync_time_frame, 1);
+
+ if (ret == 0)
+ {
+ sensor_sync_time_frame.tph = val;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_SENSOR_SYNC_TIME_FRAME,
- (uint8_t*)&sensor_sync_time_frame, 1);
+ (uint8_t *)&sensor_sync_time_frame, 1);
}
+
return ret;
}
@@ -5719,13 +6662,14 @@ int32_t lsm6dsl_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsl_sh_sync_sens_frame_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsl_sensor_sync_time_frame_t sensor_sync_time_frame;
int32_t ret;
ret = lsm6dsl_read_reg(ctx, LSM6DSL_SENSOR_SYNC_TIME_FRAME,
- (uint8_t*)&sensor_sync_time_frame, 1);
+ (uint8_t *)&sensor_sync_time_frame, 1);
*val = sensor_sync_time_frame.tph;
return ret;
@@ -5739,18 +6683,22 @@ int32_t lsm6dsl_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx, lsm6dsl_rr_t val)
+int32_t lsm6dsl_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx,
+ lsm6dsl_rr_t val)
{
lsm6dsl_sensor_sync_res_ratio_t sensor_sync_res_ratio;
int32_t ret;
ret = lsm6dsl_read_reg(ctx, LSM6DSL_SENSOR_SYNC_RES_RATIO,
- (uint8_t*)&sensor_sync_res_ratio, 1);
- if(ret == 0){
+ (uint8_t *)&sensor_sync_res_ratio, 1);
+
+ if (ret == 0)
+ {
sensor_sync_res_ratio.rr = (uint8_t) val;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_SENSOR_SYNC_RES_RATIO,
- (uint8_t*)&sensor_sync_res_ratio, 1);
+ (uint8_t *)&sensor_sync_res_ratio, 1);
}
+
return ret;
}
@@ -5762,27 +6710,33 @@ int32_t lsm6dsl_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx, lsm6dsl_rr_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx, lsm6dsl_rr_t *val)
+int32_t lsm6dsl_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx,
+ lsm6dsl_rr_t *val)
{
lsm6dsl_sensor_sync_res_ratio_t sensor_sync_res_ratio;
int32_t ret;
ret = lsm6dsl_read_reg(ctx, LSM6DSL_SENSOR_SYNC_RES_RATIO,
- (uint8_t*)&sensor_sync_res_ratio, 1);
+ (uint8_t *)&sensor_sync_res_ratio, 1);
- switch ( sensor_sync_res_ratio.rr) {
+ switch (sensor_sync_res_ratio.rr)
+ {
case LSM6DSL_RES_RATIO_2_11:
*val = LSM6DSL_RES_RATIO_2_11;
break;
+
case LSM6DSL_RES_RATIO_2_12:
*val = LSM6DSL_RES_RATIO_2_12;
break;
+
case LSM6DSL_RES_RATIO_2_13:
*val = LSM6DSL_RES_RATIO_2_13;
break;
+
case LSM6DSL_RES_RATIO_2_14:
*val = LSM6DSL_RES_RATIO_2_14;
break;
+
default:
*val = LSM6DSL_RES_RATIO_ND;
break;
@@ -5805,12 +6759,15 @@ int32_t lsm6dsl_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
master_config.master_on = val;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
+
return ret;
}
@@ -5828,7 +6785,7 @@ int32_t lsm6dsl_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
*val = master_config.master_on;
return ret;
@@ -5848,12 +6805,15 @@ int32_t lsm6dsl_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
master_config.pass_through_mode = val;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
+
return ret;
}
@@ -5871,7 +6831,7 @@ int32_t lsm6dsl_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
*val = master_config.pass_through_mode;
return ret;
@@ -5885,17 +6845,20 @@ int32_t lsm6dsl_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_sh_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsl_pull_up_en_t val)
+int32_t lsm6dsl_sh_pin_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsl_pull_up_en_t val)
{
lsm6dsl_master_config_t master_config;
int32_t ret;
ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
master_config.pull_up_en = (uint8_t) val;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
return ret;
@@ -5909,24 +6872,30 @@ int32_t lsm6dsl_sh_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsl_pull_up_en_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_sh_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsl_pull_up_en_t *val)
+int32_t lsm6dsl_sh_pin_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsl_pull_up_en_t *val)
{
lsm6dsl_master_config_t master_config;
int32_t ret;
ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- switch (master_config.pull_up_en) {
+ (uint8_t *)&master_config, 1);
+
+ switch (master_config.pull_up_en)
+ {
case LSM6DSL_EXT_PULL_UP:
*val = LSM6DSL_EXT_PULL_UP;
break;
+
case LSM6DSL_INTERNAL_PULL_UP:
*val = LSM6DSL_INTERNAL_PULL_UP;
break;
+
default:
*val = LSM6DSL_SH_PIN_MODE;
break;
}
+
return ret;
}
@@ -5945,12 +6914,15 @@ int32_t lsm6dsl_sh_syncro_mode_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
master_config.start_config = (uint8_t)val;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
+
return ret;
}
@@ -5969,14 +6941,18 @@ int32_t lsm6dsl_sh_syncro_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- switch (master_config.start_config) {
+ (uint8_t *)&master_config, 1);
+
+ switch (master_config.start_config)
+ {
case LSM6DSL_XL_GY_DRDY:
*val = LSM6DSL_XL_GY_DRDY;
break;
+
case LSM6DSL_EXT_ON_INT2_PIN:
*val = LSM6DSL_EXT_ON_INT2_PIN;
break;
+
default:
*val = LSM6DSL_SH_SYNCRO_ND;
break;
@@ -5999,12 +6975,15 @@ int32_t lsm6dsl_sh_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
master_config.drdy_on_int1 = val;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
+
return ret;
}
@@ -6022,7 +7001,7 @@ int32_t lsm6dsl_sh_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
*val = master_config.drdy_on_int1;
return ret;
@@ -6040,12 +7019,16 @@ int32_t lsm6dsl_sh_read_data_raw_get(stmdev_ctx_t *ctx,
lsm6dsl_emb_sh_read_t *val)
{
int32_t ret;
+
ret = lsm6dsl_read_reg(ctx, LSM6DSL_SENSORHUB1_REG,
- (uint8_t*)&(val->sh_byte_1), 12);
- if(ret == 0){
+ (uint8_t *) & (val->sh_byte_1), 12);
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_SENSORHUB13_REG,
- (uint8_t*)&(val->sh_byte_13), 6);
+ (uint8_t *) & (val->sh_byte_13), 6);
}
+
return ret;
}
@@ -6064,12 +7047,15 @@ int32_t lsm6dsl_sh_cmd_sens_sync_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CMD_CODE,
- (uint8_t*)&master_cmd_code, 1);
- if(ret == 0){
+ (uint8_t *)&master_cmd_code, 1);
+
+ if (ret == 0)
+ {
master_cmd_code.master_cmd_code = val;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_MASTER_CMD_CODE,
- (uint8_t*)&master_cmd_code, 1);
+ (uint8_t *)&master_cmd_code, 1);
}
+
return ret;
}
@@ -6088,7 +7074,7 @@ int32_t lsm6dsl_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CMD_CODE,
- (uint8_t*)&master_cmd_code, 1);
+ (uint8_t *)&master_cmd_code, 1);
*val = master_cmd_code.master_cmd_code;
return ret;
@@ -6109,12 +7095,15 @@ int32_t lsm6dsl_sh_spi_sync_error_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsl_read_reg(ctx, LSM6DSL_SENS_SYNC_SPI_ERROR_CODE,
- (uint8_t*)&sens_sync_spi_error_code, 1);
- if(ret == 0){
- sens_sync_spi_error_code.error_code = val;
+ (uint8_t *)&sens_sync_spi_error_code, 1);
+
+ if (ret == 0)
+ {
+ sens_sync_spi_error_code.error_code = val;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_SENS_SYNC_SPI_ERROR_CODE,
- (uint8_t*)&sens_sync_spi_error_code, 1);
+ (uint8_t *)&sens_sync_spi_error_code, 1);
}
+
return ret;
}
@@ -6133,7 +7122,7 @@ int32_t lsm6dsl_sh_spi_sync_error_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsl_read_reg(ctx, LSM6DSL_SENS_SYNC_SPI_ERROR_CODE,
- (uint8_t*)&sens_sync_spi_error_code, 1);
+ (uint8_t *)&sens_sync_spi_error_code, 1);
*val = sens_sync_spi_error_code.error_code;
return ret;
@@ -6154,18 +7143,25 @@ int32_t lsm6dsl_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave0_config, 1);
+
+ if (ret == 0)
+ {
slave0_config.aux_sens_on = (uint8_t) val;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave0_config, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
}
+
return ret;
}
@@ -6184,27 +7180,37 @@ int32_t lsm6dsl_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
- if(ret == 0){
- switch (slave0_config.aux_sens_on) {
+
+ if (ret == 0)
+ {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE0_CONFIG,
+ (uint8_t *)&slave0_config, 1);
+
+ if (ret == 0)
+ {
+ switch (slave0_config.aux_sens_on)
+ {
case LSM6DSL_SLV_0:
*val = LSM6DSL_SLV_0;
break;
+
case LSM6DSL_SLV_0_1:
*val = LSM6DSL_SLV_0_1;
break;
+
case LSM6DSL_SLV_0_1_2:
*val = LSM6DSL_SLV_0_1_2;
break;
+
case LSM6DSL_SLV_0_1_2_3:
*val = LSM6DSL_SLV_0_1_2_3;
break;
+
default:
*val = LSM6DSL_SLV_EN_ND;
break;
}
+
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
@@ -6223,28 +7229,38 @@ int32_t lsm6dsl_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_sh_cfg_write(stmdev_ctx_t *ctx, lsm6dsl_sh_cfg_write_t *val)
+int32_t lsm6dsl_sh_cfg_write(stmdev_ctx_t *ctx,
+ lsm6dsl_sh_cfg_write_t *val)
{
lsm6dsl_slv0_add_t slv0_add;
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv0_add.slave0_add = val->slv0_add;
slv0_add.rw_0 = 0;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV0_ADD, (uint8_t*)&slv0_add, 1);
- if(ret == 0){
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV0_ADD, (uint8_t *)&slv0_add, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV0_SUBADD,
&(val->slv0_subadd), 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_write_reg(ctx, LSM6DSL_DATAWRITE_SRC_MODE_SUB_SLV0,
&(val->slv0_data), 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
}
}
+
return ret;
}
@@ -6267,27 +7283,38 @@ int32_t lsm6dsl_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv0_add.slave0_add = val->slv_add;
slv0_add.rw_0 = 1;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV0_ADD, (uint8_t*)&slv0_add, 1);
- if(ret == 0){
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV0_ADD, (uint8_t *)&slv0_add, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV0_SUBADD,
&(val->slv_subadd), 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
+ (uint8_t *)&slave0_config, 1);
slave0_config.slave0_numop = val->slv_len;
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave0_config, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
}
}
}
+
return ret;
}
@@ -6310,27 +7337,38 @@ int32_t lsm6dsl_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv1_add.slave1_add = val->slv_add;
slv1_add.r_1 = 1;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV1_ADD, (uint8_t*)&slv1_add, 1);
- if(ret == 0){
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV1_ADD, (uint8_t *)&slv1_add, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV1_SUBADD,
- &(val->slv_subadd), 1);
- if(ret == 0){
+ &(val->slv_subadd), 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
+ (uint8_t *)&slave1_config, 1);
slave1_config.slave1_numop = val->slv_len;
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave1_config, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
}
}
}
+
return ret;
}
@@ -6353,21 +7391,31 @@ int32_t lsm6dsl_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv2_add.slave2_add = val->slv_add;
slv2_add.r_2 = 1;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV2_ADD, (uint8_t*)&slv2_add, 1);
- if(ret == 0){
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV2_ADD, (uint8_t *)&slv2_add, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV2_SUBADD,
&(val->slv_subadd), 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE2_CONFIG,
- (uint8_t*)&slave2_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave2_config, 1);
+
+ if (ret == 0)
+ {
slave2_config.slave2_numop = val->slv_len;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE2_CONFIG,
- (uint8_t*)&slave2_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave2_config, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
@@ -6397,27 +7445,38 @@ int32_t lsm6dsl_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv3_add.slave3_add = val->slv_add;
slv3_add.r_3 = 1;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV3_ADD, (uint8_t*)&slv3_add, 1);
- if(ret == 0){
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV3_ADD, (uint8_t *)&slv3_add, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV3_SUBADD,
- (uint8_t*)&(val->slv_subadd), 1);
- if(ret == 0){
+ (uint8_t *) & (val->slv_subadd), 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE3_CONFIG,
- (uint8_t*)&slave3_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave3_config, 1);
+
+ if (ret == 0)
+ {
slave3_config.slave3_numop = val->slv_len;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE3_CONFIG,
- (uint8_t*)&slave3_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave3_config, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
}
}
}
+
return ret;
}
@@ -6437,18 +7496,25 @@ int32_t lsm6dsl_sh_slave_0_dec_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave0_config, 1);
+
+ if (ret == 0)
+ {
slave0_config.slave0_rate = (uint8_t) val;
ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave0_config, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
}
+
return ret;
}
@@ -6468,27 +7534,37 @@ int32_t lsm6dsl_sh_slave_0_dec_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
- if(ret == 0){
- switch (slave0_config.slave0_rate) {
+
+ if (ret == 0)
+ {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE0_CONFIG,
+ (uint8_t *)&slave0_config, 1);
+
+ if (ret == 0)
+ {
+ switch (slave0_config.slave0_rate)
+ {
case LSM6DSL_SL0_NO_DEC:
*val = LSM6DSL_SL0_NO_DEC;
break;
+
case LSM6DSL_SL0_DEC_2:
*val = LSM6DSL_SL0_DEC_2;
break;
+
case LSM6DSL_SL0_DEC_4:
*val = LSM6DSL_SL0_DEC_4;
break;
+
case LSM6DSL_SL0_DEC_8:
*val = LSM6DSL_SL0_DEC_8;
break;
+
default:
*val = LSM6DSL_SL0_DEC_ND;
break;
}
+
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
@@ -6507,24 +7583,32 @@ int32_t lsm6dsl_sh_slave_0_dec_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsl_sh_write_mode_set(stmdev_ctx_t *ctx, lsm6dsl_write_once_t val)
+int32_t lsm6dsl_sh_write_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsl_write_once_t val)
{
lsm6dsl_slave1_config_t slave1_config;
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
+ (uint8_t *)&slave1_config, 1);
slave1_config.write_once = (uint8_t) val;
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave1_config, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
}
+
return ret;
}
@@ -6546,21 +7630,29 @@ int32_t lsm6dsl_sh_write_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
- if(ret == 0){
- switch (slave1_config.write_once) {
+
+ if (ret == 0)
+ {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE1_CONFIG,
+ (uint8_t *)&slave1_config, 1);
+
+ if (ret == 0)
+ {
+ switch (slave1_config.write_once)
+ {
case LSM6DSL_EACH_SH_CYCLE:
*val = LSM6DSL_EACH_SH_CYCLE;
break;
+
case LSM6DSL_ONLY_FIRST_CYCLE:
*val = LSM6DSL_ONLY_FIRST_CYCLE;
break;
+
default:
*val = LSM6DSL_SH_WR_MODE_ND;
break;
}
+
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
@@ -6584,18 +7676,25 @@ int32_t lsm6dsl_sh_slave_1_dec_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE1_CONFIG,
+ (uint8_t *)&slave1_config, 1);
+
+ if (ret == 0)
+ {
slave1_config.slave1_rate = (uint8_t) val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
- if(ret == 0){
- ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE1_CONFIG,
+ (uint8_t *)&slave1_config, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
}
+
return ret;
}
@@ -6614,27 +7713,37 @@ int32_t lsm6dsl_sh_slave_1_dec_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
- if(ret == 0){
- switch (slave1_config.slave1_rate) {
+
+ if (ret == 0)
+ {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE1_CONFIG,
+ (uint8_t *)&slave1_config, 1);
+
+ if (ret == 0)
+ {
+ switch (slave1_config.slave1_rate)
+ {
case LSM6DSL_SL1_NO_DEC:
*val = LSM6DSL_SL1_NO_DEC;
break;
+
case LSM6DSL_SL1_DEC_2:
*val = LSM6DSL_SL1_DEC_2;
break;
+
case LSM6DSL_SL1_DEC_4:
*val = LSM6DSL_SL1_DEC_4;
break;
+
case LSM6DSL_SL1_DEC_8:
*val = LSM6DSL_SL1_DEC_8;
break;
+
default:
*val = LSM6DSL_SL1_DEC_ND;
break;
}
+
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
@@ -6658,18 +7767,25 @@ int32_t lsm6dsl_sh_slave_2_dec_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE2_CONFIG,
- (uint8_t*)&slave2_config, 1);
- if(ret == 0){
- slave2_config.slave2_rate =(uint8_t) val;
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE2_CONFIG,
- (uint8_t*)&slave2_config, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE2_CONFIG,
+ (uint8_t *)&slave2_config, 1);
+
+ if (ret == 0)
+ {
+ slave2_config.slave2_rate = (uint8_t) val;
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE2_CONFIG,
+ (uint8_t *)&slave2_config, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
}
+
return ret;
}
@@ -6689,27 +7805,37 @@ int32_t lsm6dsl_sh_slave_2_dec_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE2_CONFIG,
- (uint8_t*)&slave2_config, 1);
- if(ret == 0){
- switch (slave2_config.slave2_rate) {
+
+ if (ret == 0)
+ {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE2_CONFIG,
+ (uint8_t *)&slave2_config, 1);
+
+ if (ret == 0)
+ {
+ switch (slave2_config.slave2_rate)
+ {
case LSM6DSL_SL2_NO_DEC:
*val = LSM6DSL_SL2_NO_DEC;
break;
+
case LSM6DSL_SL2_DEC_2:
*val = LSM6DSL_SL2_DEC_2;
break;
+
case LSM6DSL_SL2_DEC_4:
*val = LSM6DSL_SL2_DEC_4;
break;
+
case LSM6DSL_SL2_DEC_8:
*val = LSM6DSL_SL2_DEC_8;
break;
+
default:
*val = LSM6DSL_SL2_DEC_ND;
break;
}
+
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
@@ -6733,18 +7859,25 @@ int32_t lsm6dsl_sh_slave_3_dec_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE3_CONFIG,
- (uint8_t*)&slave3_config, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE3_CONFIG,
+ (uint8_t *)&slave3_config, 1);
slave3_config.slave3_rate = (uint8_t)val;
- if(ret == 0){
- ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE3_CONFIG,
- (uint8_t*)&slave3_config, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
+ ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE3_CONFIG,
+ (uint8_t *)&slave3_config, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
}
+
return ret;
}
@@ -6764,27 +7897,37 @@ int32_t lsm6dsl_sh_slave_3_dec_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
- if(ret == 0){
- ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE3_CONFIG,
- (uint8_t*)&slave3_config, 1);
- if(ret == 0){
- switch (slave3_config.slave3_rate) {
+
+ if (ret == 0)
+ {
+ ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE3_CONFIG,
+ (uint8_t *)&slave3_config, 1);
+
+ if (ret == 0)
+ {
+ switch (slave3_config.slave3_rate)
+ {
case LSM6DSL_SL3_NO_DEC:
*val = LSM6DSL_SL3_NO_DEC;
break;
+
case LSM6DSL_SL3_DEC_2:
*val = LSM6DSL_SL3_DEC_2;
break;
+
case LSM6DSL_SL3_DEC_4:
*val = LSM6DSL_SL3_DEC_4;
break;
+
case LSM6DSL_SL3_DEC_8:
*val = LSM6DSL_SL3_DEC_8;
break;
+
default:
*val = LSM6DSL_SL3_DEC_ND;
break;
}
+
ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
}
}
diff --git a/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.h b/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.h
index 1503a8d01512ca2c90c0475cdf84368d7455f246..69c241db162575660aa568f549c755296e334752 100644
--- a/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.h
+++ b/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file lsm6dsl_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lsm6dsl_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lsm6dsl_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lsm6dsl_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LSM6DSL_REGS_H
#define LSM6DSL_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup LSM6DSL
@@ -35,6 +36,37 @@
*
*/
+/** @defgroup Endianness definitions
+ * @{
+ *
+ */
+
+#ifndef DRV_BYTE_ORDER
+#ifndef __BYTE_ORDER__
+
+#define DRV_LITTLE_ENDIAN 1234
+#define DRV_BIG_ENDIAN 4321
+
+/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
+ * by uncommenting the define which fits your platform endianness
+ */
+//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
+#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
+
+#else /* defined __BYTE_ORDER__ */
+
+#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
+#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
+#define DRV_BYTE_ORDER __BYTE_ORDER__
+
+#endif /* __BYTE_ORDER__*/
+#endif /* DRV_BYTE_ORDER */
+
+/**
+ * @}
+ *
+ */
+
/** @defgroup STMicroelectronics sensors common types
* @{
*
@@ -43,7 +75,9 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -52,6 +86,16 @@ typedef struct{
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} bitwise_t;
#define PROPERTY_DISABLE (0U)
@@ -65,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -89,15 +134,16 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
- * Unico / Unicleo tools available on STMicroelectronics
- * web site.
+ * You can create a sensor configuration by your own or using
+ * Unico / Unicleo tools available on STMicroelectronics
+ * web site.
*
* @{
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -132,68 +178,129 @@ typedef struct {
*/
#define LSM6DSL_FUNC_CFG_ACCESS 0x01U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t not_used_01 : 5;
+uint8_t func_cfg_en :
+ 3; /* func_cfg_en + func_cfg_en_b */
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+uint8_t func_cfg_en :
+ 3; /* func_cfg_en + func_cfg_en_b */
uint8_t not_used_01 : 5;
- uint8_t func_cfg_en : 3; /* func_cfg_en + func_cfg_en_b */
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_func_cfg_access_t;
#define LSM6DSL_SENSOR_SYNC_TIME_FRAME 0x04U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tph : 4;
uint8_t not_used_01 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 4;
+ uint8_t tph : 4;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_sensor_sync_time_frame_t;
#define LSM6DSL_SENSOR_SYNC_RES_RATIO 0x05U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t rr : 2;
uint8_t not_used_01 : 6;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 6;
+ uint8_t rr : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_sensor_sync_res_ratio_t;
#define LSM6DSL_FIFO_CTRL1 0x06U
-typedef struct {
+typedef struct
+{
uint8_t fth : 8; /* + FIFO_CTRL2(fth) */
} lsm6dsl_fifo_ctrl1_t;
#define LSM6DSL_FIFO_CTRL2 0x07U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fth : 3; /* + FIFO_CTRL1(fth) */
uint8_t fifo_temp_en : 1;
uint8_t not_used_01 : 2;
uint8_t timer_pedo_fifo_drdy : 1;
uint8_t timer_pedo_fifo_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t timer_pedo_fifo_en : 1;
+ uint8_t timer_pedo_fifo_drdy : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t fifo_temp_en : 1;
+ uint8_t fth : 3; /* + FIFO_CTRL1(fth) */
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_fifo_ctrl2_t;
#define LSM6DSL_FIFO_CTRL3 0x08U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t dec_fifo_xl : 3;
uint8_t dec_fifo_gyro : 3;
uint8_t not_used_01 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 2;
+ uint8_t dec_fifo_gyro : 3;
+ uint8_t dec_fifo_xl : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_fifo_ctrl3_t;
#define LSM6DSL_FIFO_CTRL4 0x09U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t dec_ds3_fifo : 3;
uint8_t dec_ds4_fifo : 3;
uint8_t only_high_data : 1;
uint8_t stop_on_fth : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t stop_on_fth : 1;
+ uint8_t only_high_data : 1;
+ uint8_t dec_ds4_fifo : 3;
+ uint8_t dec_ds3_fifo : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_fifo_ctrl4_t;
#define LSM6DSL_FIFO_CTRL5 0x0AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fifo_mode : 3;
uint8_t odr_fifo : 4;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t odr_fifo : 4;
+ uint8_t fifo_mode : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_fifo_ctrl5_t;
#define LSM6DSL_DRDY_PULSE_CFG_G 0x0BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_wrist_tilt : 1;
uint8_t not_used_01 : 6;
uint8_t drdy_pulsed : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t drdy_pulsed : 1;
+ uint8_t not_used_01 : 6;
+ uint8_t int2_wrist_tilt : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_drdy_pulse_cfg_g_t;
#define LSM6DSL_INT1_CTRL 0x0DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_drdy_xl : 1;
uint8_t int1_drdy_g : 1;
uint8_t int1_boot : 1;
@@ -202,10 +309,22 @@ typedef struct {
uint8_t int1_full_flag : 1;
uint8_t int1_sign_mot : 1;
uint8_t int1_step_detector : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_step_detector : 1;
+ uint8_t int1_sign_mot : 1;
+ uint8_t int1_full_flag : 1;
+ uint8_t int1_fifo_ovr : 1;
+ uint8_t int1_fth : 1;
+ uint8_t int1_boot : 1;
+ uint8_t int1_drdy_g : 1;
+ uint8_t int1_drdy_xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_int1_ctrl_t;
#define LSM6DSL_INT2_CTRL 0x0EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_drdy_xl : 1;
uint8_t int2_drdy_g : 1;
uint8_t int2_drdy_temp : 1;
@@ -214,26 +333,53 @@ typedef struct {
uint8_t int2_full_flag : 1;
uint8_t int2_step_count_ov : 1;
uint8_t int2_step_delta : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_step_delta : 1;
+ uint8_t int2_step_count_ov : 1;
+ uint8_t int2_full_flag : 1;
+ uint8_t int2_fifo_ovr : 1;
+ uint8_t int2_fth : 1;
+ uint8_t int2_drdy_temp : 1;
+ uint8_t int2_drdy_g : 1;
+ uint8_t int2_drdy_xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_int2_ctrl_t;
#define LSM6DSL_WHO_AM_I 0x0FU
#define LSM6DSL_CTRL1_XL 0x10U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bw0_xl : 1;
uint8_t lpf1_bw_sel : 1;
uint8_t fs_xl : 2;
uint8_t odr_xl : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr_xl : 4;
+ uint8_t fs_xl : 2;
+ uint8_t lpf1_bw_sel : 1;
+ uint8_t bw0_xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_ctrl1_xl_t;
#define LSM6DSL_CTRL2_G 0x11U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t fs_g : 3; /* fs_g + fs_125 */
uint8_t odr_g : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr_g : 4;
+ uint8_t fs_g : 3; /* fs_g + fs_125 */
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_ctrl2_g_t;
#define LSM6DSL_CTRL3_C 0x12U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sw_reset : 1;
uint8_t ble : 1;
uint8_t if_inc : 1;
@@ -242,10 +388,22 @@ typedef struct {
uint8_t h_lactive : 1;
uint8_t bdu : 1;
uint8_t boot : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t boot : 1;
+ uint8_t bdu : 1;
+ uint8_t h_lactive : 1;
+ uint8_t pp_od : 1;
+ uint8_t sim : 1;
+ uint8_t if_inc : 1;
+ uint8_t ble : 1;
+ uint8_t sw_reset : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_ctrl3_c_t;
#define LSM6DSL_CTRL4_C 0x13U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t lpf1_sel_g : 1;
uint8_t i2c_disable : 1;
@@ -254,37 +412,78 @@ typedef struct {
uint8_t int2_on_int1 : 1;
uint8_t sleep : 1;
uint8_t den_xl_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t den_xl_en : 1;
+ uint8_t sleep : 1;
+ uint8_t int2_on_int1 : 1;
+ uint8_t den_drdy_int1 : 1;
+ uint8_t drdy_mask : 1;
+ uint8_t i2c_disable : 1;
+ uint8_t lpf1_sel_g : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_ctrl4_c_t;
#define LSM6DSL_CTRL5_C 0x14U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_xl : 2;
uint8_t st_g : 2;
uint8_t den_lh : 1;
uint8_t rounding : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t rounding : 3;
+ uint8_t den_lh : 1;
+ uint8_t st_g : 2;
+ uint8_t st_xl : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_ctrl5_c_t;
#define LSM6DSL_CTRL6_C 0x15U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ftype : 2;
uint8_t not_used_01 : 1;
uint8_t usr_off_w : 1;
uint8_t xl_hm_mode : 1;
- uint8_t den_mode : 3; /* trig_en + lvl_en + lvl2_en */
+uint8_t den_mode :
+ 3; /* trig_en + lvl_en + lvl2_en */
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+uint8_t den_mode :
+ 3; /* trig_en + lvl_en + lvl2_en */
+ uint8_t xl_hm_mode : 1;
+ uint8_t usr_off_w : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t ftype : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_ctrl6_c_t;
#define LSM6DSL_CTRL7_G 0x16U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t rounding_status : 1;
uint8_t not_used_02 : 1;
uint8_t hpm_g : 2;
uint8_t hp_en_g : 1;
uint8_t g_hm_mode : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t g_hm_mode : 1;
+ uint8_t hp_en_g : 1;
+ uint8_t hpm_g : 2;
+ uint8_t not_used_02 : 1;
+ uint8_t rounding_status : 1;
+ uint8_t not_used_01 : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_ctrl7_g_t;
#define LSM6DSL_CTRL8_XL 0x17U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t low_pass_on_6d : 1;
uint8_t not_used_01 : 1;
uint8_t hp_slope_xl_en : 1;
@@ -292,10 +491,21 @@ typedef struct {
uint8_t hp_ref_mode : 1;
uint8_t hpcf_xl : 2;
uint8_t lpf2_xl_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t lpf2_xl_en : 1;
+ uint8_t hpcf_xl : 2;
+ uint8_t hp_ref_mode : 1;
+ uint8_t input_composite : 1;
+ uint8_t hp_slope_xl_en : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t low_pass_on_6d : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_ctrl8_xl_t;
#define LSM6DSL_CTRL9_XL 0x18U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t soft_en : 1;
uint8_t not_used_02 : 1;
@@ -303,10 +513,21 @@ typedef struct {
uint8_t den_z : 1;
uint8_t den_y : 1;
uint8_t den_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t den_x : 1;
+ uint8_t den_y : 1;
+ uint8_t den_z : 1;
+ uint8_t den_xl_g : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t soft_en : 1;
+ uint8_t not_used_01 : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_ctrl9_xl_t;
#define LSM6DSL_CTRL10_C 0x19U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sign_motion_en : 1;
uint8_t pedo_rst_step : 1;
uint8_t func_en : 1;
@@ -315,10 +536,22 @@ typedef struct {
uint8_t timer_en : 1;
uint8_t not_used_01 : 1;
uint8_t wrist_tilt_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t wrist_tilt_en : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t timer_en : 1;
+ uint8_t pedo_en : 1;
+ uint8_t tilt_en : 1;
+ uint8_t func_en : 1;
+ uint8_t pedo_rst_step : 1;
+ uint8_t sign_motion_en : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_ctrl10_c_t;
#define LSM6DSL_MASTER_CONFIG 0x1AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t master_on : 1;
uint8_t iron_en : 1;
uint8_t pass_through_mode : 1;
@@ -327,10 +560,22 @@ typedef struct {
uint8_t not_used_01 : 1;
uint8_t data_valid_sel_fifo : 1;
uint8_t drdy_on_int1 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t drdy_on_int1 : 1;
+ uint8_t data_valid_sel_fifo : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t start_config : 1;
+ uint8_t pull_up_en : 1;
+ uint8_t pass_through_mode : 1;
+ uint8_t iron_en : 1;
+ uint8_t master_on : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_master_config_t;
#define LSM6DSL_WAKE_UP_SRC 0x1BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_wu : 1;
uint8_t y_wu : 1;
uint8_t x_wu : 1;
@@ -338,10 +583,21 @@ typedef struct {
uint8_t sleep_state_ia : 1;
uint8_t ff_ia : 1;
uint8_t not_used_01 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 2;
+ uint8_t ff_ia : 1;
+ uint8_t sleep_state_ia : 1;
+ uint8_t wu_ia : 1;
+ uint8_t x_wu : 1;
+ uint8_t y_wu : 1;
+ uint8_t z_wu : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_wake_up_src_t;
#define LSM6DSL_TAP_SRC 0x1CU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_tap : 1;
uint8_t y_tap : 1;
uint8_t x_tap : 1;
@@ -350,10 +606,22 @@ typedef struct {
uint8_t single_tap : 1;
uint8_t tap_ia : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t tap_ia : 1;
+ uint8_t single_tap : 1;
+ uint8_t double_tap : 1;
+ uint8_t tap_sign : 1;
+ uint8_t x_tap : 1;
+ uint8_t y_tap : 1;
+ uint8_t z_tap : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_tap_src_t;
#define LSM6DSL_D6D_SRC 0x1DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
uint8_t yl : 1;
@@ -362,14 +630,32 @@ typedef struct {
uint8_t zh : 1;
uint8_t d6d_ia : 1;
uint8_t den_drdy : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t den_drdy : 1;
+ uint8_t d6d_ia : 1;
+ uint8_t zh : 1;
+ uint8_t zl : 1;
+ uint8_t yh : 1;
+ uint8_t yl : 1;
+ uint8_t xh : 1;
+ uint8_t xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_d6d_src_t;
#define LSM6DSL_STATUS_REG 0x1EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlda : 1;
uint8_t gda : 1;
uint8_t tda : 1;
uint8_t not_used_01 : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 5;
+ uint8_t tda : 1;
+ uint8_t gda : 1;
+ uint8_t xlda : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_status_reg_t;
#define LSM6DSL_OUT_TEMP_L 0x20U
@@ -387,7 +673,9 @@ typedef struct {
#define LSM6DSL_OUTZ_L_XL 0x2CU
#define LSM6DSL_OUTZ_H_XL 0x2DU
#define LSM6DSL_SENSORHUB1_REG 0x2EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -396,10 +684,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_sensorhub1_reg_t;
#define LSM6DSL_SENSORHUB2_REG 0x2FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -408,10 +708,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_sensorhub2_reg_t;
#define LSM6DSL_SENSORHUB3_REG 0x30U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -420,10 +732,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_sensorhub3_reg_t;
#define LSM6DSL_SENSORHUB4_REG 0x31U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -432,10 +756,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_sensorhub4_reg_t;
#define LSM6DSL_SENSORHUB5_REG 0x32U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -444,10 +780,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_sensorhub5_reg_t;
#define LSM6DSL_SENSORHUB6_REG 0x33U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -456,10 +804,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_sensorhub6_reg_t;
#define LSM6DSL_SENSORHUB7_REG 0x34U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -468,10 +828,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_sensorhub7_reg_t;
#define LSM6DSL_SENSORHUB8_REG 0x35U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -480,10 +852,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_sensorhub8_reg_t;
#define LSM6DSL_SENSORHUB9_REG 0x36U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -492,10 +876,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_sensorhub9_reg_t;
#define LSM6DSL_SENSORHUB10_REG 0x37U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -504,10 +900,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_sensorhub10_reg_t;
#define LSM6DSL_SENSORHUB11_REG 0x38U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -516,10 +924,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_sensorhub11_reg_t;
#define LSM6DSL_SENSORHUB12_REG 0x39U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -528,32 +948,63 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_sensorhub12_reg_t;
#define LSM6DSL_FIFO_STATUS1 0x3AU
-typedef struct {
+typedef struct
+{
uint8_t diff_fifo : 8; /* + FIFO_STATUS2(diff_fifo) */
} lsm6dsl_fifo_status1_t;
#define LSM6DSL_FIFO_STATUS2 0x3BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t diff_fifo : 3; /* + FIFO_STATUS1(diff_fifo) */
uint8_t not_used_01 : 1;
uint8_t fifo_empty : 1;
uint8_t fifo_full_smart : 1;
uint8_t over_run : 1;
uint8_t waterm : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t waterm : 1;
+ uint8_t over_run : 1;
+ uint8_t fifo_full_smart : 1;
+ uint8_t fifo_empty : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t diff_fifo : 3; /* + FIFO_STATUS1(diff_fifo) */
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_fifo_status2_t;
#define LSM6DSL_FIFO_STATUS3 0x3CU
-typedef struct {
- uint8_t fifo_pattern : 8; /* + FIFO_STATUS4(fifo_pattern) */
+typedef struct
+{
+uint8_t fifo_pattern :
+ 8; /* + FIFO_STATUS4(fifo_pattern) */
} lsm6dsl_fifo_status3_t;
#define LSM6DSL_FIFO_STATUS4 0x3DU
-typedef struct {
- uint8_t fifo_pattern : 2; /* + FIFO_STATUS3(fifo_pattern) */
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+uint8_t fifo_pattern :
+ 2; /* + FIFO_STATUS3(fifo_pattern) */
+ uint8_t not_used_01 : 6;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used_01 : 6;
+uint8_t fifo_pattern :
+ 2; /* + FIFO_STATUS3(fifo_pattern) */
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_fifo_status4_t;
#define LSM6DSL_FIFO_DATA_OUT_L 0x3EU
@@ -567,7 +1018,9 @@ typedef struct {
#define LSM6DSL_STEP_COUNTER_H 0x4CU
#define LSM6DSL_SENSORHUB13_REG 0x4DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -576,10 +1029,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_sensorhub13_reg_t;
#define LSM6DSL_SENSORHUB14_REG 0x4EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -588,10 +1053,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_sensorhub14_reg_t;
#define LSM6DSL_SENSORHUB15_REG 0x4FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -600,10 +1077,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_sensorhub15_reg_t;
#define LSM6DSL_SENSORHUB16_REG 0x50U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -612,10 +1101,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_sensorhub16_reg_t;
#define LSM6DSL_SENSORHUB17_REG 0x51U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -624,10 +1125,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_sensorhub17_reg_t;
#define LSM6DSL_SENSORHUB18_REG 0x52U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -636,10 +1149,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_sensorhub18_reg_t;
#define LSM6DSL_FUNC_SRC1 0x53U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sensorhub_end_op : 1;
uint8_t si_end_op : 1;
uint8_t hi_fail : 1;
@@ -648,10 +1173,22 @@ typedef struct {
uint8_t tilt_ia : 1;
uint8_t sign_motion_ia : 1;
uint8_t step_count_delta_ia : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t step_count_delta_ia : 1;
+ uint8_t sign_motion_ia : 1;
+ uint8_t tilt_ia : 1;
+ uint8_t step_detected : 1;
+ uint8_t step_overflow : 1;
+ uint8_t hi_fail : 1;
+ uint8_t si_end_op : 1;
+ uint8_t sensorhub_end_op : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_func_src1_t;
#define LSM6DSL_FUNC_SRC2 0x54U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wrist_tilt_ia : 1;
uint8_t not_used_01 : 2;
uint8_t slave0_nack : 1;
@@ -659,10 +1196,21 @@ typedef struct {
uint8_t slave2_nack : 1;
uint8_t slave3_nack : 1;
uint8_t not_used_02 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 1;
+ uint8_t slave3_nack : 1;
+ uint8_t slave2_nack : 1;
+ uint8_t slave1_nack : 1;
+ uint8_t slave0_nack : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t wrist_tilt_ia : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_func_src2_t;
#define LSM6DSL_WRIST_TILT_IA 0x55U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t wrist_tilt_ia_zneg : 1;
uint8_t wrist_tilt_ia_zpos : 1;
@@ -670,10 +1218,21 @@ typedef struct {
uint8_t wrist_tilt_ia_ypos : 1;
uint8_t wrist_tilt_ia_xneg : 1;
uint8_t wrist_tilt_ia_xpos : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t wrist_tilt_ia_xpos : 1;
+ uint8_t wrist_tilt_ia_xneg : 1;
+ uint8_t wrist_tilt_ia_ypos : 1;
+ uint8_t wrist_tilt_ia_yneg : 1;
+ uint8_t wrist_tilt_ia_zpos : 1;
+ uint8_t wrist_tilt_ia_zneg : 1;
+ uint8_t not_used_01 : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_wrist_tilt_ia_t;
#define LSM6DSL_TAP_CFG 0x58U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lir : 1;
uint8_t tap_z_en : 1;
uint8_t tap_y_en : 1;
@@ -681,45 +1240,91 @@ typedef struct {
uint8_t slope_fds : 1;
uint8_t inact_en : 2;
uint8_t interrupts_enable : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t interrupts_enable : 1;
+ uint8_t inact_en : 2;
+ uint8_t slope_fds : 1;
+ uint8_t tap_x_en : 1;
+ uint8_t tap_y_en : 1;
+ uint8_t tap_z_en : 1;
+ uint8_t lir : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_tap_cfg_t;
#define LSM6DSL_TAP_THS_6D 0x59U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_ths : 5;
uint8_t sixd_ths : 2;
uint8_t d4d_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t d4d_en : 1;
+ uint8_t sixd_ths : 2;
+ uint8_t tap_ths : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_tap_ths_6d_t;
#define LSM6DSL_INT_DUR2 0x5AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shock : 2;
uint8_t quiet : 2;
uint8_t dur : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t dur : 4;
+ uint8_t quiet : 2;
+ uint8_t shock : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_int_dur2_t;
#define LSM6DSL_WAKE_UP_THS 0x5BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wk_ths : 6;
uint8_t not_used_01 : 1;
uint8_t single_double_tap : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t single_double_tap : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t wk_ths : 6;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_wake_up_ths_t;
#define LSM6DSL_WAKE_UP_DUR 0x5CU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sleep_dur : 4;
uint8_t timer_hr : 1;
uint8_t wake_dur : 2;
uint8_t ff_dur : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t ff_dur : 1;
+ uint8_t wake_dur : 2;
+ uint8_t timer_hr : 1;
+ uint8_t sleep_dur : 4;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_wake_up_dur_t;
#define LSM6DSL_FREE_FALL 0x5DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ths : 3;
uint8_t ff_dur : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t ff_dur : 5;
+ uint8_t ff_ths : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_free_fall_t;
#define LSM6DSL_MD1_CFG 0x5EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_timer : 1;
uint8_t int1_tilt : 1;
uint8_t int1_6d : 1;
@@ -728,10 +1333,22 @@ typedef struct {
uint8_t int1_wu : 1;
uint8_t int1_single_tap : 1;
uint8_t int1_inact_state : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_inact_state : 1;
+ uint8_t int1_single_tap : 1;
+ uint8_t int1_wu : 1;
+ uint8_t int1_ff : 1;
+ uint8_t int1_double_tap : 1;
+ uint8_t int1_6d : 1;
+ uint8_t int1_tilt : 1;
+ uint8_t int1_timer : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_md1_cfg_t;
#define LSM6DSL_MD2_CFG 0x5FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_iron : 1;
uint8_t int2_tilt : 1;
uint8_t int2_6d : 1;
@@ -740,15 +1357,27 @@ typedef struct {
uint8_t int2_wu : 1;
uint8_t int2_single_tap : 1;
uint8_t int2_inact_state : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_inact_state : 1;
+ uint8_t int2_single_tap : 1;
+ uint8_t int2_wu : 1;
+ uint8_t int2_ff : 1;
+ uint8_t int2_double_tap : 1;
+ uint8_t int2_6d : 1;
+ uint8_t int2_tilt : 1;
+ uint8_t int2_iron : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_md2_cfg_t;
#define LSM6DSL_MASTER_CMD_CODE 0x60U
-typedef struct {
+typedef struct
+{
uint8_t master_cmd_code : 8;
} lsm6dsl_master_cmd_code_t;
#define LSM6DSL_SENS_SYNC_SPI_ERROR_CODE 0x61U
-typedef struct {
+typedef struct
+{
uint8_t error_code : 8;
} lsm6dsl_sens_sync_spi_error_code_t;
@@ -762,96 +1391,168 @@ typedef struct {
#define LSM6DSL_Y_OFS_USR 0x74U
#define LSM6DSL_Z_OFS_USR 0x75U
#define LSM6DSL_SLV0_ADD 0x02U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t rw_0 : 1;
uint8_t slave0_add : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave0_add : 7;
+ uint8_t rw_0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_slv0_add_t;
#define LSM6DSL_SLV0_SUBADD 0x03U
-typedef struct {
+typedef struct
+{
uint8_t slave0_reg : 8;
} lsm6dsl_slv0_subadd_t;
#define LSM6DSL_SLAVE0_CONFIG 0x04U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave0_numop : 3;
uint8_t src_mode : 1;
uint8_t aux_sens_on : 2;
uint8_t slave0_rate : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave0_rate : 2;
+ uint8_t aux_sens_on : 2;
+ uint8_t src_mode : 1;
+ uint8_t slave0_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_slave0_config_t;
#define LSM6DSL_SLV1_ADD 0x05U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_1 : 1;
uint8_t slave1_add : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave1_add : 7;
+ uint8_t r_1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_slv1_add_t;
#define LSM6DSL_SLV1_SUBADD 0x06U
-typedef struct {
+typedef struct
+{
uint8_t slave1_reg : 8;
} lsm6dsl_slv1_subadd_t;
#define LSM6DSL_SLAVE1_CONFIG 0x07U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave1_numop : 3;
uint8_t not_used_01 : 2;
uint8_t write_once : 1;
uint8_t slave1_rate : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave1_rate : 2;
+ uint8_t write_once : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t slave1_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_slave1_config_t;
#define LSM6DSL_SLV2_ADD 0x08U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_2 : 1;
uint8_t slave2_add : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave2_add : 7;
+ uint8_t r_2 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_slv2_add_t;
#define LSM6DSL_SLV2_SUBADD 0x09U
-typedef struct {
+typedef struct
+{
uint8_t slave2_reg : 8;
} lsm6dsl_slv2_subadd_t;
#define LSM6DSL_SLAVE2_CONFIG 0x0AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave2_numop : 3;
uint8_t not_used_01 : 3;
uint8_t slave2_rate : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave2_rate : 2;
+ uint8_t not_used_01 : 3;
+ uint8_t slave2_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_slave2_config_t;
#define LSM6DSL_SLV3_ADD 0x0BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_3 : 1;
uint8_t slave3_add : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave3_add : 7;
+ uint8_t r_3 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_slv3_add_t;
#define LSM6DSL_SLV3_SUBADD 0x0CU
-typedef struct {
+typedef struct
+{
uint8_t slave3_reg : 8;
} lsm6dsl_slv3_subadd_t;
#define LSM6DSL_SLAVE3_CONFIG 0x0DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave3_numop : 3;
uint8_t not_used_01 : 3;
uint8_t slave3_rate : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave3_rate : 2;
+ uint8_t not_used_01 : 3;
+ uint8_t slave3_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_slave3_config_t;
#define LSM6DSL_DATAWRITE_SRC_MODE_SUB_SLV0 0x0EU
-typedef struct {
+typedef struct
+{
uint8_t slave_dataw : 8;
} lsm6dsl_datawrite_src_mode_sub_slv0_t;
#define LSM6DSL_CONFIG_PEDO_THS_MIN 0x0FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths_min : 5;
uint8_t not_used_01 : 2;
uint8_t pedo_fs : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t pedo_fs : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t ths_min : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_config_pedo_ths_min_t;
#define LSM6DSL_SM_THS 0x13U
#define LSM6DSL_PEDO_DEB_REG 0x14U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t deb_step : 3;
uint8_t deb_time : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t deb_time : 5;
+ uint8_t deb_step : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_pedo_deb_reg_t;
#define LSM6DSL_STEP_COUNT_DELTA 0x15U
@@ -873,7 +1574,9 @@ typedef struct {
#define LSM6DSL_A_WRIST_TILT_LAT 0x50U
#define LSM6DSL_A_WRIST_TILT_THS 0x54U
#define LSM6DSL_A_WRIST_TILT_MASK 0x59U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t wrist_tilt_mask_zneg : 1;
uint8_t wrist_tilt_mask_zpos : 1;
@@ -881,13 +1584,22 @@ typedef struct {
uint8_t wrist_tilt_mask_ypos : 1;
uint8_t wrist_tilt_mask_xneg : 1;
uint8_t wrist_tilt_mask_xpos : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t wrist_tilt_mask_xpos : 1;
+ uint8_t wrist_tilt_mask_xneg : 1;
+ uint8_t wrist_tilt_mask_ypos : 1;
+ uint8_t wrist_tilt_mask_yneg : 1;
+ uint8_t wrist_tilt_mask_zpos : 1;
+ uint8_t wrist_tilt_mask_zneg : 1;
+ uint8_t not_used_01 : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsl_a_wrist_tilt_mask_t;
/**
* @defgroup LSM6DSL_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -895,7 +1607,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
lsm6dsl_func_cfg_access_t func_cfg_access;
lsm6dsl_sensor_sync_time_frame_t sensor_sync_time_frame;
lsm6dsl_sensor_sync_res_ratio_t sensor_sync_res_ratio;
@@ -969,7 +1682,8 @@ typedef union{
lsm6dsl_slv3_add_t slv3_add;
lsm6dsl_slv3_subadd_t slv3_subadd;
lsm6dsl_slave3_config_t slave3_config;
- lsm6dsl_datawrite_src_mode_sub_slv0_t datawrite_src_mode_sub_slv0;
+ lsm6dsl_datawrite_src_mode_sub_slv0_t
+ datawrite_src_mode_sub_slv0;
lsm6dsl_config_pedo_ths_min_t config_pedo_ths_min;
lsm6dsl_pedo_deb_reg_t pedo_deb_reg;
lsm6dsl_a_wrist_tilt_mask_t a_wrist_tilt_mask;
@@ -982,35 +1696,41 @@ typedef union{
*
*/
-int32_t lsm6dsl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lsm6dsl_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t lsm6dsl_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lsm6dsl_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-extern float_t lsm6dsl_from_fs2g_to_mg(int16_t lsb);
-extern float_t lsm6dsl_from_fs4g_to_mg(int16_t lsb);
-extern float_t lsm6dsl_from_fs8g_to_mg(int16_t lsb);
-extern float_t lsm6dsl_from_fs16g_to_mg(int16_t lsb);
+float_t lsm6dsl_from_fs2g_to_mg(int16_t lsb);
+float_t lsm6dsl_from_fs4g_to_mg(int16_t lsb);
+float_t lsm6dsl_from_fs8g_to_mg(int16_t lsb);
+float_t lsm6dsl_from_fs16g_to_mg(int16_t lsb);
-extern float_t lsm6dsl_from_fs125dps_to_mdps(int16_t lsb);
-extern float_t lsm6dsl_from_fs250dps_to_mdps(int16_t lsb);
-extern float_t lsm6dsl_from_fs500dps_to_mdps(int16_t lsb);
-extern float_t lsm6dsl_from_fs1000dps_to_mdps(int16_t lsb);
-extern float_t lsm6dsl_from_fs2000dps_to_mdps(int16_t lsb);
+float_t lsm6dsl_from_fs125dps_to_mdps(int16_t lsb);
+float_t lsm6dsl_from_fs250dps_to_mdps(int16_t lsb);
+float_t lsm6dsl_from_fs500dps_to_mdps(int16_t lsb);
+float_t lsm6dsl_from_fs1000dps_to_mdps(int16_t lsb);
+float_t lsm6dsl_from_fs2000dps_to_mdps(int16_t lsb);
-extern float_t lsm6dsl_from_lsb_to_celsius(int16_t lsb);
+float_t lsm6dsl_from_lsb_to_celsius(int16_t lsb);
-typedef enum {
+typedef enum
+{
LSM6DSL_2g = 0,
LSM6DSL_16g = 1,
LSM6DSL_4g = 2,
LSM6DSL_8g = 3,
LSM6DSL_XL_FS_ND = 4, /* ERROR CODE */
} lsm6dsl_fs_xl_t;
-int32_t lsm6dsl_xl_full_scale_set(stmdev_ctx_t *ctx, lsm6dsl_fs_xl_t val);
-int32_t lsm6dsl_xl_full_scale_get(stmdev_ctx_t *ctx, lsm6dsl_fs_xl_t *val);
+int32_t lsm6dsl_xl_full_scale_set(stmdev_ctx_t *ctx,
+ lsm6dsl_fs_xl_t val);
+int32_t lsm6dsl_xl_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6dsl_fs_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_XL_ODR_OFF = 0,
LSM6DSL_XL_ODR_12Hz5 = 1,
LSM6DSL_XL_ODR_26Hz = 2,
@@ -1025,10 +1745,13 @@ typedef enum {
LSM6DSL_XL_ODR_1Hz6 = 11,
LSM6DSL_XL_ODR_ND = 12, /* ERROR CODE */
} lsm6dsl_odr_xl_t;
-int32_t lsm6dsl_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6dsl_odr_xl_t val);
-int32_t lsm6dsl_xl_data_rate_get(stmdev_ctx_t *ctx, lsm6dsl_odr_xl_t *val);
+int32_t lsm6dsl_xl_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dsl_odr_xl_t val);
+int32_t lsm6dsl_xl_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dsl_odr_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_250dps = 0,
LSM6DSL_125dps = 1,
LSM6DSL_500dps = 2,
@@ -1036,10 +1759,13 @@ typedef enum {
LSM6DSL_2000dps = 6,
LSM6DSL_GY_FS_ND = 7, /* ERROR CODE */
} lsm6dsl_fs_g_t;
-int32_t lsm6dsl_gy_full_scale_set(stmdev_ctx_t *ctx, lsm6dsl_fs_g_t val);
-int32_t lsm6dsl_gy_full_scale_get(stmdev_ctx_t *ctx, lsm6dsl_fs_g_t *val);
+int32_t lsm6dsl_gy_full_scale_set(stmdev_ctx_t *ctx,
+ lsm6dsl_fs_g_t val);
+int32_t lsm6dsl_gy_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6dsl_fs_g_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_GY_ODR_OFF = 0,
LSM6DSL_GY_ODR_12Hz5 = 1,
LSM6DSL_GY_ODR_26Hz = 2,
@@ -1053,13 +1779,17 @@ typedef enum {
LSM6DSL_GY_ODR_6k66Hz = 10,
LSM6DSL_GY_ODR_ND = 11, /* ERROR CODE */
} lsm6dsl_odr_g_t;
-int32_t lsm6dsl_gy_data_rate_set(stmdev_ctx_t *ctx, lsm6dsl_odr_g_t val);
-int32_t lsm6dsl_gy_data_rate_get(stmdev_ctx_t *ctx, lsm6dsl_odr_g_t *val);
+int32_t lsm6dsl_gy_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dsl_odr_g_t val);
+int32_t lsm6dsl_gy_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dsl_odr_g_t *val);
int32_t lsm6dsl_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsl_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsl_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_LSb_1mg = 0,
LSM6DSL_LSb_16mg = 1,
LSM6DSL_WEIGHT_ND = 2,
@@ -1069,7 +1799,8 @@ int32_t lsm6dsl_xl_offset_weight_set(stmdev_ctx_t *ctx,
int32_t lsm6dsl_xl_offset_weight_get(stmdev_ctx_t *ctx,
lsm6dsl_usr_off_w_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_XL_HIGH_PERFORMANCE = 0,
LSM6DSL_XL_NORMAL = 1,
LSM6DSL_XL_PW_MODE_ND = 2, /* ERROR CODE */
@@ -1079,7 +1810,8 @@ int32_t lsm6dsl_xl_power_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dsl_xl_power_mode_get(stmdev_ctx_t *ctx,
lsm6dsl_xl_hm_mode_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_STAT_RND_DISABLE = 0,
LSM6DSL_STAT_RND_ENABLE = 1,
LSM6DSL_STAT_RND_ND = 2, /* ERROR CODE */
@@ -1089,7 +1821,8 @@ int32_t lsm6dsl_rounding_on_status_set(stmdev_ctx_t *ctx,
int32_t lsm6dsl_rounding_on_status_get(stmdev_ctx_t *ctx,
lsm6dsl_rounding_status_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_GY_HIGH_PERFORMANCE = 0,
LSM6DSL_GY_NORMAL = 1,
LSM6DSL_GY_PW_MODE_ND = 2, /* ERROR CODE */
@@ -1099,7 +1832,8 @@ int32_t lsm6dsl_gy_power_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dsl_gy_power_mode_get(stmdev_ctx_t *ctx,
lsm6dsl_g_hm_mode_t *val);
-typedef struct {
+typedef struct
+{
lsm6dsl_wake_up_src_t wake_up_src;
lsm6dsl_tap_src_t tap_src;
lsm6dsl_d6d_src_t d6d_src;
@@ -1112,28 +1846,36 @@ typedef struct {
int32_t lsm6dsl_all_sources_get(stmdev_ctx_t *ctx,
lsm6dsl_all_sources_t *val);
-int32_t lsm6dsl_status_reg_get(stmdev_ctx_t *ctx, lsm6dsl_status_reg_t *val);
+int32_t lsm6dsl_status_reg_get(stmdev_ctx_t *ctx,
+ lsm6dsl_status_reg_t *val);
-int32_t lsm6dsl_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsl_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsl_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsl_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsl_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsl_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dsl_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t lsm6dsl_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t lsm6dsl_timestamp_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsl_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_LSB_6ms4 = 0,
LSM6DSL_LSB_25us = 1,
LSM6DSL_TS_RES_ND = 2, /* ERROR CODE */
} lsm6dsl_timer_hr_t;
-int32_t lsm6dsl_timestamp_res_set(stmdev_ctx_t *ctx, lsm6dsl_timer_hr_t val);
-int32_t lsm6dsl_timestamp_res_get(stmdev_ctx_t *ctx, lsm6dsl_timer_hr_t *val);
+int32_t lsm6dsl_timestamp_res_set(stmdev_ctx_t *ctx,
+ lsm6dsl_timer_hr_t val);
+int32_t lsm6dsl_timestamp_res_get(stmdev_ctx_t *ctx,
+ lsm6dsl_timer_hr_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_ROUND_DISABLE = 0,
LSM6DSL_ROUND_XL = 1,
LSM6DSL_ROUND_GY = 2,
@@ -1144,28 +1886,35 @@ typedef enum {
LSM6DSL_ROUND_GY_XL_SH1_TO_SH6 = 7,
LSM6DSL_ROUND_OUT_ND = 8, /* ERROR CODE */
} lsm6dsl_rounding_t;
-int32_t lsm6dsl_rounding_mode_set(stmdev_ctx_t *ctx, lsm6dsl_rounding_t val);
-int32_t lsm6dsl_rounding_mode_get(stmdev_ctx_t *ctx, lsm6dsl_rounding_t *val);
+int32_t lsm6dsl_rounding_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsl_rounding_t val);
+int32_t lsm6dsl_rounding_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsl_rounding_t *val);
-int32_t lsm6dsl_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsl_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsl_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsl_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t lsm6dsl_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t lsm6dsl_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val);
-int32_t lsm6dsl_mag_calibrated_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsl_mag_calibrated_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
int32_t lsm6dsl_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer,
uint8_t len);
-typedef enum {
+typedef enum
+{
LSM6DSL_USER_BANK = 0,
LSM6DSL_BANK_A = 4,
LSM6DSL_BANK_B = 5,
LSM6DSL_BANK_ND = 6, /* ERROR CODE */
} lsm6dsl_func_cfg_en_t;
-int32_t lsm6dsl_mem_bank_set(stmdev_ctx_t *ctx, lsm6dsl_func_cfg_en_t val);
-int32_t lsm6dsl_mem_bank_get(stmdev_ctx_t *ctx, lsm6dsl_func_cfg_en_t *val);
+int32_t lsm6dsl_mem_bank_set(stmdev_ctx_t *ctx,
+ lsm6dsl_func_cfg_en_t val);
+int32_t lsm6dsl_mem_bank_get(stmdev_ctx_t *ctx,
+ lsm6dsl_func_cfg_en_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_DRDY_LATCHED = 0,
LSM6DSL_DRDY_PULSED = 1,
LSM6DSL_DRDY_ND = 2, /* ERROR CODE */
@@ -1179,13 +1928,15 @@ int32_t lsm6dsl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t lsm6dsl_reset_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsl_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_LSB_AT_LOW_ADD = 0,
LSM6DSL_MSB_AT_LOW_ADD = 1,
LSM6DSL_DATA_FMT_ND = 2, /* ERROR CODE */
} lsm6dsl_ble_t;
int32_t lsm6dsl_data_format_set(stmdev_ctx_t *ctx, lsm6dsl_ble_t val);
-int32_t lsm6dsl_data_format_get(stmdev_ctx_t *ctx, lsm6dsl_ble_t *val);
+int32_t lsm6dsl_data_format_get(stmdev_ctx_t *ctx,
+ lsm6dsl_ble_t *val);
int32_t lsm6dsl_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsl_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1193,28 +1944,37 @@ int32_t lsm6dsl_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsl_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsl_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_XL_ST_DISABLE = 0,
LSM6DSL_XL_ST_POSITIVE = 1,
LSM6DSL_XL_ST_NEGATIVE = 2,
LSM6DSL_XL_ST_ND = 3, /* ERROR CODE */
} lsm6dsl_st_xl_t;
-int32_t lsm6dsl_xl_self_test_set(stmdev_ctx_t *ctx, lsm6dsl_st_xl_t val);
-int32_t lsm6dsl_xl_self_test_get(stmdev_ctx_t *ctx, lsm6dsl_st_xl_t *val);
+int32_t lsm6dsl_xl_self_test_set(stmdev_ctx_t *ctx,
+ lsm6dsl_st_xl_t val);
+int32_t lsm6dsl_xl_self_test_get(stmdev_ctx_t *ctx,
+ lsm6dsl_st_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_GY_ST_DISABLE = 0,
LSM6DSL_GY_ST_POSITIVE = 1,
LSM6DSL_GY_ST_NEGATIVE = 3,
LSM6DSL_GY_ST_ND = 4, /* ERROR CODE */
} lsm6dsl_st_g_t;
-int32_t lsm6dsl_gy_self_test_set(stmdev_ctx_t *ctx, lsm6dsl_st_g_t val);
-int32_t lsm6dsl_gy_self_test_get(stmdev_ctx_t *ctx, lsm6dsl_st_g_t *val);
-
-int32_t lsm6dsl_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsl_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val);
-
-typedef enum {
+int32_t lsm6dsl_gy_self_test_set(stmdev_ctx_t *ctx,
+ lsm6dsl_st_g_t val);
+int32_t lsm6dsl_gy_self_test_get(stmdev_ctx_t *ctx,
+ lsm6dsl_st_g_t *val);
+
+int32_t lsm6dsl_filter_settling_mask_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsl_filter_settling_mask_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+typedef enum
+{
LSM6DSL_USE_SLOPE = 0,
LSM6DSL_USE_HPF = 1,
LSM6DSL_HP_PATH_ND = 2, /* ERROR CODE */
@@ -1224,7 +1984,8 @@ int32_t lsm6dsl_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
int32_t lsm6dsl_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
lsm6dsl_slope_fds_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_XL_ANA_BW_1k5Hz = 0,
LSM6DSL_XL_ANA_BW_400Hz = 1,
LSM6DSL_XL_ANA_BW_ND = 2, /* ERROR CODE */
@@ -1234,7 +1995,8 @@ int32_t lsm6dsl_xl_filter_analog_set(stmdev_ctx_t *ctx,
int32_t lsm6dsl_xl_filter_analog_get(stmdev_ctx_t *ctx,
lsm6dsl_bw0_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_XL_LP1_ODR_DIV_2 = 0,
LSM6DSL_XL_LP1_ODR_DIV_4 = 1,
LSM6DSL_XL_LP1_NA = 2, /* ERROR CODE */
@@ -1244,7 +2006,8 @@ int32_t lsm6dsl_xl_lp1_bandwidth_set(stmdev_ctx_t *ctx,
int32_t lsm6dsl_xl_lp1_bandwidth_get(stmdev_ctx_t *ctx,
lsm6dsl_lpf1_bw_sel_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_50 = 0x00,
LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_100 = 0x01,
LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_9 = 0x02,
@@ -1261,9 +2024,11 @@ int32_t lsm6dsl_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx,
lsm6dsl_input_composite_t *val);
int32_t lsm6dsl_xl_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsl_xl_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsl_xl_reference_mode_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_XL_HP_ODR_DIV_4 = 0x00, /* Slope filter */
LSM6DSL_XL_HP_ODR_DIV_100 = 0x01,
LSM6DSL_XL_HP_ODR_DIV_9 = 0x02,
@@ -1275,7 +2040,8 @@ int32_t lsm6dsl_xl_hp_bandwidth_set(stmdev_ctx_t *ctx,
int32_t lsm6dsl_xl_hp_bandwidth_get(stmdev_ctx_t *ctx,
lsm6dsl_hpcf_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_LP2_ONLY = 0x00,
LSM6DSL_HP_16mHz_LP2 = 0x80,
@@ -1296,11 +2062,12 @@ typedef enum {
LSM6DSL_HP_GY_BAND_NA = 0xFF, /* ERROR CODE */
} lsm6dsl_lpf1_sel_g_t;
int32_t lsm6dsl_gy_band_pass_set(stmdev_ctx_t *ctx,
- lsm6dsl_lpf1_sel_g_t val);
+ lsm6dsl_lpf1_sel_g_t val);
int32_t lsm6dsl_gy_band_pass_get(stmdev_ctx_t *ctx,
- lsm6dsl_lpf1_sel_g_t *val);
+ lsm6dsl_lpf1_sel_g_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_SPI_4_WIRE = 0,
LSM6DSL_SPI_3_WIRE = 1,
LSM6DSL_SPI_MODE_ND = 2, /* ERROR CODE */
@@ -1308,7 +2075,8 @@ typedef enum {
int32_t lsm6dsl_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsl_sim_t val);
int32_t lsm6dsl_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsl_sim_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_I2C_ENABLE = 0,
LSM6DSL_I2C_DISABLE = 1,
LSM6DSL_I2C_MODE_ND = 2, /* ERROR CODE */
@@ -1318,7 +2086,8 @@ int32_t lsm6dsl_i2c_interface_set(stmdev_ctx_t *ctx,
int32_t lsm6dsl_i2c_interface_get(stmdev_ctx_t *ctx,
lsm6dsl_i2c_disable_t *val);
-typedef struct {
+typedef struct
+{
uint8_t int1_drdy_xl : 1;
uint8_t int1_drdy_g : 1;
uint8_t int1_boot : 1;
@@ -1343,7 +2112,8 @@ int32_t lsm6dsl_pin_int1_route_set(stmdev_ctx_t *ctx,
int32_t lsm6dsl_pin_int1_route_get(stmdev_ctx_t *ctx,
lsm6dsl_int1_route_t *val);
-typedef struct{
+typedef struct
+{
uint8_t int2_drdy_xl : 1;
uint8_t int2_drdy_g : 1;
uint8_t int2_drdy_temp : 1;
@@ -1367,7 +2137,8 @@ int32_t lsm6dsl_pin_int2_route_set(stmdev_ctx_t *ctx,
int32_t lsm6dsl_pin_int2_route_get(stmdev_ctx_t *ctx,
lsm6dsl_int2_route_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_PUSH_PULL = 0,
LSM6DSL_OPEN_DRAIN = 1,
LSM6DSL_PIN_MODE_ND = 2, /* ERROR CODE */
@@ -1375,24 +2146,30 @@ typedef enum {
int32_t lsm6dsl_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsl_pp_od_t val);
int32_t lsm6dsl_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsl_pp_od_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_ACTIVE_HIGH = 0,
LSM6DSL_ACTIVE_LOW = 1,
LSM6DSL_POLARITY_ND = 2, /* ERROR CODE */
} lsm6dsl_h_lactive_t;
-int32_t lsm6dsl_pin_polarity_set(stmdev_ctx_t *ctx, lsm6dsl_h_lactive_t val);
-int32_t lsm6dsl_pin_polarity_get(stmdev_ctx_t *ctx, lsm6dsl_h_lactive_t *val);
+int32_t lsm6dsl_pin_polarity_set(stmdev_ctx_t *ctx,
+ lsm6dsl_h_lactive_t val);
+int32_t lsm6dsl_pin_polarity_get(stmdev_ctx_t *ctx,
+ lsm6dsl_h_lactive_t *val);
int32_t lsm6dsl_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsl_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_INT_PULSED = 0,
LSM6DSL_INT_LATCHED = 1,
LSM6DSL_INT_MODE = 2, /* ERROR CODE */
} lsm6dsl_lir_t;
-int32_t lsm6dsl_int_notification_set(stmdev_ctx_t *ctx, lsm6dsl_lir_t val);
-int32_t lsm6dsl_int_notification_get(stmdev_ctx_t *ctx, lsm6dsl_lir_t *val);
+int32_t lsm6dsl_int_notification_set(stmdev_ctx_t *ctx,
+ lsm6dsl_lir_t val);
+int32_t lsm6dsl_int_notification_get(stmdev_ctx_t *ctx,
+ lsm6dsl_lir_t *val);
int32_t lsm6dsl_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsl_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1403,29 +2180,39 @@ int32_t lsm6dsl_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsl_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsl_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_PROPERTY_DISABLE = 0,
LSM6DSL_XL_12Hz5_GY_NOT_AFFECTED = 1,
LSM6DSL_XL_12Hz5_GY_SLEEP = 2,
LSM6DSL_XL_12Hz5_GY_PD = 3,
LSM6DSL_ACT_MODE_ND = 4, /* ERROR CODE */
} lsm6dsl_inact_en_t;
-int32_t lsm6dsl_act_mode_set(stmdev_ctx_t *ctx, lsm6dsl_inact_en_t val);
-int32_t lsm6dsl_act_mode_get(stmdev_ctx_t *ctx, lsm6dsl_inact_en_t *val);
+int32_t lsm6dsl_act_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsl_inact_en_t val);
+int32_t lsm6dsl_act_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsl_inact_en_t *val);
int32_t lsm6dsl_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsl_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dsl_tap_src_get(stmdev_ctx_t *ctx, lsm6dsl_tap_src_t *val);
+int32_t lsm6dsl_tap_src_get(stmdev_ctx_t *ctx,
+ lsm6dsl_tap_src_t *val);
-int32_t lsm6dsl_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsl_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsl_tap_detection_on_z_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsl_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsl_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsl_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsl_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsl_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsl_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsl_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsl_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsl_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dsl_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsl_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1439,7 +2226,8 @@ int32_t lsm6dsl_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsl_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsl_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_ONLY_SINGLE = 0,
LSM6DSL_BOTH_SINGLE_DOUBLE = 1,
LSM6DSL_TAP_MODE_ND = 2, /* ERROR CODE */
@@ -1449,7 +2237,8 @@ int32_t lsm6dsl_tap_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dsl_tap_mode_get(stmdev_ctx_t *ctx,
lsm6dsl_single_double_tap_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_ODR_DIV_2_FEED = 0,
LSM6DSL_LPF2_FEED = 1,
LSM6DSL_6D_FEED_ND = 2, /* ERROR CODE */
@@ -1459,15 +2248,18 @@ int32_t lsm6dsl_6d_feed_data_set(stmdev_ctx_t *ctx,
int32_t lsm6dsl_6d_feed_data_get(stmdev_ctx_t *ctx,
lsm6dsl_low_pass_on_6d_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_DEG_80 = 0,
LSM6DSL_DEG_70 = 1,
LSM6DSL_DEG_60 = 2,
LSM6DSL_DEG_50 = 3,
LSM6DSL_6D_TH_ND = 4, /* ERROR CODE */
} lsm6dsl_sixd_ths_t;
-int32_t lsm6dsl_6d_threshold_set(stmdev_ctx_t *ctx, lsm6dsl_sixd_ths_t val);
-int32_t lsm6dsl_6d_threshold_get(stmdev_ctx_t *ctx, lsm6dsl_sixd_ths_t *val);
+int32_t lsm6dsl_6d_threshold_set(stmdev_ctx_t *ctx,
+ lsm6dsl_sixd_ths_t val);
+int32_t lsm6dsl_6d_threshold_get(stmdev_ctx_t *ctx,
+ lsm6dsl_sixd_ths_t *val);
int32_t lsm6dsl_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsl_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1475,7 +2267,8 @@ int32_t lsm6dsl_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsl_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsl_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_FF_TSH_156mg = 0,
LSM6DSL_FF_TSH_219mg = 1,
LSM6DSL_FF_TSH_250mg = 2,
@@ -1486,8 +2279,10 @@ typedef enum {
LSM6DSL_FF_TSH_500mg = 7,
LSM6DSL_FF_TSH_ND = 8, /* ERROR CODE */
} lsm6dsl_ff_ths_t;
-int32_t lsm6dsl_ff_threshold_set(stmdev_ctx_t *ctx, lsm6dsl_ff_ths_t val);
-int32_t lsm6dsl_ff_threshold_get(stmdev_ctx_t *ctx, lsm6dsl_ff_ths_t *val);
+int32_t lsm6dsl_ff_threshold_set(stmdev_ctx_t *ctx,
+ lsm6dsl_ff_ths_t val);
+int32_t lsm6dsl_ff_threshold_get(stmdev_ctx_t *ctx,
+ lsm6dsl_ff_ths_t *val);
int32_t lsm6dsl_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val);
int32_t lsm6dsl_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val);
@@ -1501,7 +2296,8 @@ int32_t lsm6dsl_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val);
int32_t lsm6dsl_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsl_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_TRG_XL_GY_DRDY = 0,
LSM6DSL_TRG_STEP_DETECT = 1,
LSM6DSL_TRG_SH_DRDY = 2,
@@ -1517,7 +2313,8 @@ int32_t lsm6dsl_fifo_pedo_and_timestamp_batch_set(stmdev_ctx_t *ctx,
int32_t lsm6dsl_fifo_pedo_and_timestamp_batch_get(stmdev_ctx_t *ctx,
uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_FIFO_XL_DISABLE = 0,
LSM6DSL_FIFO_XL_NO_DEC = 1,
LSM6DSL_FIFO_XL_DEC_2 = 2,
@@ -1533,7 +2330,8 @@ int32_t lsm6dsl_fifo_xl_batch_set(stmdev_ctx_t *ctx,
int32_t lsm6dsl_fifo_xl_batch_get(stmdev_ctx_t *ctx,
lsm6dsl_dec_fifo_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_FIFO_GY_DISABLE = 0,
LSM6DSL_FIFO_GY_NO_DEC = 1,
LSM6DSL_FIFO_GY_DEC_2 = 2,
@@ -1549,7 +2347,8 @@ int32_t lsm6dsl_fifo_gy_batch_set(stmdev_ctx_t *ctx,
int32_t lsm6dsl_fifo_gy_batch_get(stmdev_ctx_t *ctx,
lsm6dsl_dec_fifo_gyro_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_FIFO_DS3_DISABLE = 0,
LSM6DSL_FIFO_DS3_NO_DEC = 1,
LSM6DSL_FIFO_DS3_DEC_2 = 2,
@@ -1565,7 +2364,8 @@ int32_t lsm6dsl_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx,
int32_t lsm6dsl_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx,
lsm6dsl_dec_ds3_fifo_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_FIFO_DS4_DISABLE = 0,
LSM6DSL_FIFO_DS4_NO_DEC = 1,
LSM6DSL_FIFO_DS4_DEC_2 = 2,
@@ -1581,13 +2381,16 @@ int32_t lsm6dsl_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx,
int32_t lsm6dsl_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx,
lsm6dsl_dec_ds4_fifo_t *val);
-int32_t lsm6dsl_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsl_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsl_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsl_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dsl_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsl_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_BYPASS_MODE = 0,
LSM6DSL_FIFO_MODE = 1,
LSM6DSL_STREAM_TO_FIFO_MODE = 3,
@@ -1595,10 +2398,13 @@ typedef enum {
LSM6DSL_STREAM_MODE = 6,
LSM6DSL_FIFO_MODE_ND = 8, /* ERROR CODE */
} lsm6dsl_fifo_mode_t;
-int32_t lsm6dsl_fifo_mode_set(stmdev_ctx_t *ctx, lsm6dsl_fifo_mode_t val);
-int32_t lsm6dsl_fifo_mode_get(stmdev_ctx_t *ctx, lsm6dsl_fifo_mode_t *val);
+int32_t lsm6dsl_fifo_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsl_fifo_mode_t val);
+int32_t lsm6dsl_fifo_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsl_fifo_mode_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_FIFO_DISABLE = 0,
LSM6DSL_FIFO_12Hz5 = 1,
LSM6DSL_FIFO_26Hz = 2,
@@ -1617,15 +2423,19 @@ int32_t lsm6dsl_fifo_data_rate_set(stmdev_ctx_t *ctx,
int32_t lsm6dsl_fifo_data_rate_get(stmdev_ctx_t *ctx,
lsm6dsl_odr_fifo_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_DEN_ACT_LOW = 0,
LSM6DSL_DEN_ACT_HIGH = 1,
LSM6DSL_DEN_POL_ND = 2, /* ERROR CODE */
} lsm6dsl_den_lh_t;
-int32_t lsm6dsl_den_polarity_set(stmdev_ctx_t *ctx, lsm6dsl_den_lh_t val);
-int32_t lsm6dsl_den_polarity_get(stmdev_ctx_t *ctx, lsm6dsl_den_lh_t *val);
+int32_t lsm6dsl_den_polarity_set(stmdev_ctx_t *ctx,
+ lsm6dsl_den_lh_t val);
+int32_t lsm6dsl_den_polarity_get(stmdev_ctx_t *ctx,
+ lsm6dsl_den_lh_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_DEN_DISABLE = 0,
LSM6DSL_LEVEL_FIFO = 6,
LSM6DSL_LEVEL_LETCHED = 3,
@@ -1633,17 +2443,22 @@ typedef enum {
LSM6DSL_EDGE_TRIGGER = 4,
LSM6DSL_DEN_MODE_ND = 5, /* ERROR CODE */
} lsm6dsl_den_mode_t;
-int32_t lsm6dsl_den_mode_set(stmdev_ctx_t *ctx, lsm6dsl_den_mode_t val);
-int32_t lsm6dsl_den_mode_get(stmdev_ctx_t *ctx, lsm6dsl_den_mode_t *val);
+int32_t lsm6dsl_den_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsl_den_mode_t val);
+int32_t lsm6dsl_den_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsl_den_mode_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_STAMP_IN_GY_DATA = 0,
LSM6DSL_STAMP_IN_XL_DATA = 1,
LSM6DSL_STAMP_IN_GY_XL_DATA = 2,
LSM6DSL_DEN_STAMP_ND = 3, /* ERROR CODE */
} lsm6dsl_den_xl_en_t;
-int32_t lsm6dsl_den_enable_set(stmdev_ctx_t *ctx, lsm6dsl_den_xl_en_t val);
-int32_t lsm6dsl_den_enable_get(stmdev_ctx_t *ctx, lsm6dsl_den_xl_en_t *val);
+int32_t lsm6dsl_den_enable_set(stmdev_ctx_t *ctx,
+ lsm6dsl_den_xl_en_t val);
+int32_t lsm6dsl_den_enable_get(stmdev_ctx_t *ctx,
+ lsm6dsl_den_xl_en_t *val);
int32_t lsm6dsl_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsl_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1663,7 +2478,8 @@ int32_t lsm6dsl_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsl_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsl_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_PEDO_AT_2g = 0,
LSM6DSL_PEDO_AT_4g = 1,
LSM6DSL_PEDO_FS_ND = 2, /* ERROR CODE */
@@ -1673,20 +2489,26 @@ int32_t lsm6dsl_pedo_full_scale_set(stmdev_ctx_t *ctx,
int32_t lsm6dsl_pedo_full_scale_get(stmdev_ctx_t *ctx,
lsm6dsl_pedo_fs_t *val);
-int32_t lsm6dsl_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsl_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsl_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsl_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dsl_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsl_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dsl_pedo_steps_period_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsl_pedo_steps_period_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsl_pedo_steps_period_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lsm6dsl_pedo_steps_period_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
int32_t lsm6dsl_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsl_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dsl_motion_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsl_motion_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsl_motion_threshold_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lsm6dsl_motion_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
int32_t lsm6dsl_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsl_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1711,26 +2533,33 @@ int32_t lsm6dsl_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsl_mag_hard_iron_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsl_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dsl_mag_soft_iron_mat_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsl_mag_soft_iron_mat_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsl_mag_soft_iron_mat_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lsm6dsl_mag_soft_iron_mat_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
-int32_t lsm6dsl_mag_offset_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsl_mag_offset_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsl_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val);
+int32_t lsm6dsl_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val);
int32_t lsm6dsl_func_en_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsl_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsl_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsl_sh_sync_sens_frame_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsl_sh_sync_sens_frame_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_RES_RATIO_2_11 = 0,
LSM6DSL_RES_RATIO_2_12 = 1,
LSM6DSL_RES_RATIO_2_13 = 2,
LSM6DSL_RES_RATIO_2_14 = 3,
LSM6DSL_RES_RATIO_ND = 4, /* ERROR CODE */
} lsm6dsl_rr_t;
-int32_t lsm6dsl_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx, lsm6dsl_rr_t val);
-int32_t lsm6dsl_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx, lsm6dsl_rr_t *val);
+int32_t lsm6dsl_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx,
+ lsm6dsl_rr_t val);
+int32_t lsm6dsl_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx,
+ lsm6dsl_rr_t *val);
int32_t lsm6dsl_sh_master_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsl_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1738,15 +2567,19 @@ int32_t lsm6dsl_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsl_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsl_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_EXT_PULL_UP = 0,
LSM6DSL_INTERNAL_PULL_UP = 1,
LSM6DSL_SH_PIN_MODE = 2, /* ERROR CODE */
} lsm6dsl_pull_up_en_t;
-int32_t lsm6dsl_sh_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsl_pull_up_en_t val);
-int32_t lsm6dsl_sh_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsl_pull_up_en_t *val);
+int32_t lsm6dsl_sh_pin_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsl_pull_up_en_t val);
+int32_t lsm6dsl_sh_pin_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsl_pull_up_en_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_XL_GY_DRDY = 0,
LSM6DSL_EXT_ON_INT2_PIN = 1,
LSM6DSL_SH_SYNCRO_ND = 2, /* ERROR CODE */
@@ -1759,25 +2592,26 @@ int32_t lsm6dsl_sh_syncro_mode_get(stmdev_ctx_t *ctx,
int32_t lsm6dsl_sh_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsl_sh_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef struct {
- lsm6dsl_sensorhub1_reg_t sh_byte_1;
- lsm6dsl_sensorhub2_reg_t sh_byte_2;
- lsm6dsl_sensorhub3_reg_t sh_byte_3;
- lsm6dsl_sensorhub4_reg_t sh_byte_4;
- lsm6dsl_sensorhub5_reg_t sh_byte_5;
- lsm6dsl_sensorhub6_reg_t sh_byte_6;
- lsm6dsl_sensorhub7_reg_t sh_byte_7;
- lsm6dsl_sensorhub8_reg_t sh_byte_8;
- lsm6dsl_sensorhub9_reg_t sh_byte_9;
- lsm6dsl_sensorhub10_reg_t sh_byte_10;
- lsm6dsl_sensorhub11_reg_t sh_byte_11;
- lsm6dsl_sensorhub12_reg_t sh_byte_12;
- lsm6dsl_sensorhub13_reg_t sh_byte_13;
- lsm6dsl_sensorhub14_reg_t sh_byte_14;
- lsm6dsl_sensorhub15_reg_t sh_byte_15;
- lsm6dsl_sensorhub16_reg_t sh_byte_16;
- lsm6dsl_sensorhub17_reg_t sh_byte_17;
- lsm6dsl_sensorhub18_reg_t sh_byte_18;
+typedef struct
+{
+ lsm6dsl_sensorhub1_reg_t sh_byte_1;
+ lsm6dsl_sensorhub2_reg_t sh_byte_2;
+ lsm6dsl_sensorhub3_reg_t sh_byte_3;
+ lsm6dsl_sensorhub4_reg_t sh_byte_4;
+ lsm6dsl_sensorhub5_reg_t sh_byte_5;
+ lsm6dsl_sensorhub6_reg_t sh_byte_6;
+ lsm6dsl_sensorhub7_reg_t sh_byte_7;
+ lsm6dsl_sensorhub8_reg_t sh_byte_8;
+ lsm6dsl_sensorhub9_reg_t sh_byte_9;
+ lsm6dsl_sensorhub10_reg_t sh_byte_10;
+ lsm6dsl_sensorhub11_reg_t sh_byte_11;
+ lsm6dsl_sensorhub12_reg_t sh_byte_12;
+ lsm6dsl_sensorhub13_reg_t sh_byte_13;
+ lsm6dsl_sensorhub14_reg_t sh_byte_14;
+ lsm6dsl_sensorhub15_reg_t sh_byte_15;
+ lsm6dsl_sensorhub16_reg_t sh_byte_16;
+ lsm6dsl_sensorhub17_reg_t sh_byte_17;
+ lsm6dsl_sensorhub18_reg_t sh_byte_18;
} lsm6dsl_emb_sh_read_t;
int32_t lsm6dsl_sh_read_data_raw_get(stmdev_ctx_t *ctx,
lsm6dsl_emb_sh_read_t *val);
@@ -1786,9 +2620,11 @@ int32_t lsm6dsl_sh_cmd_sens_sync_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsl_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsl_sh_spi_sync_error_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsl_sh_spi_sync_error_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsl_sh_spi_sync_error_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_SLV_0 = 0,
LSM6DSL_SLV_0_1 = 1,
LSM6DSL_SLV_0_1_2 = 2,
@@ -1800,14 +2636,17 @@ int32_t lsm6dsl_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx,
int32_t lsm6dsl_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx,
lsm6dsl_aux_sens_on_t *val);
-typedef struct{
+typedef struct
+{
uint8_t slv0_add;
uint8_t slv0_subadd;
uint8_t slv0_data;
} lsm6dsl_sh_cfg_write_t;
-int32_t lsm6dsl_sh_cfg_write(stmdev_ctx_t *ctx, lsm6dsl_sh_cfg_write_t *val);
+int32_t lsm6dsl_sh_cfg_write(stmdev_ctx_t *ctx,
+ lsm6dsl_sh_cfg_write_t *val);
-typedef struct{
+typedef struct
+{
uint8_t slv_add;
uint8_t slv_subadd;
uint8_t slv_len;
@@ -1821,7 +2660,8 @@ int32_t lsm6dsl_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
int32_t lsm6dsl_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
lsm6dsl_sh_cfg_read_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_SL0_NO_DEC = 0,
LSM6DSL_SL0_DEC_2 = 1,
LSM6DSL_SL0_DEC_4 = 2,
@@ -1833,7 +2673,8 @@ int32_t lsm6dsl_sh_slave_0_dec_set(stmdev_ctx_t *ctx,
int32_t lsm6dsl_sh_slave_0_dec_get(stmdev_ctx_t *ctx,
lsm6dsl_slave0_rate_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_EACH_SH_CYCLE = 0,
LSM6DSL_ONLY_FIRST_CYCLE = 1,
LSM6DSL_SH_WR_MODE_ND = 2, /* ERROR CODE */
@@ -1843,7 +2684,8 @@ int32_t lsm6dsl_sh_write_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dsl_sh_write_mode_get(stmdev_ctx_t *ctx,
lsm6dsl_write_once_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_SL1_NO_DEC = 0,
LSM6DSL_SL1_DEC_2 = 1,
LSM6DSL_SL1_DEC_4 = 2,
@@ -1855,7 +2697,8 @@ int32_t lsm6dsl_sh_slave_1_dec_set(stmdev_ctx_t *ctx,
int32_t lsm6dsl_sh_slave_1_dec_get(stmdev_ctx_t *ctx,
lsm6dsl_slave1_rate_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_SL2_NO_DEC = 0,
LSM6DSL_SL2_DEC_2 = 1,
LSM6DSL_SL2_DEC_4 = 2,
@@ -1867,7 +2710,8 @@ int32_t lsm6dsl_sh_slave_2_dec_set(stmdev_ctx_t *ctx,
int32_t lsm6dsl_sh_slave_2_dec_get(stmdev_ctx_t *ctx,
lsm6dsl_slave2_rate_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSL_SL3_NO_DEC = 0,
LSM6DSL_SL3_DEC_2 = 1,
LSM6DSL_SL3_DEC_4 = 2,
diff --git a/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.c b/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.c
index 6d190a75675c93433a40957834866971ab9accbc..3645b0f6cfe8673c71002d80b682e0d72e1996cf 100644
--- a/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.c
+++ b/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file lsm6dsm_reg.c
- * @author Sensors Software Solution Team
- * @brief LSM6DSM driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lsm6dsm_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LSM6DSM driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lsm6dsm_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsm_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lsm6dsm_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t lsm6dsm_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsm_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lsm6dsm_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -156,16 +162,20 @@ float_t lsm6dsm_from_lsb_to_celsius(int16_t lsb)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_xl_full_scale_set(stmdev_ctx_t *ctx, lsm6dsm_fs_xl_t val)
+int32_t lsm6dsm_xl_full_scale_set(stmdev_ctx_t *ctx,
+ lsm6dsm_fs_xl_t val)
{
lsm6dsm_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
ctrl1_xl.fs_xl = (uint8_t) val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -177,25 +187,32 @@ int32_t lsm6dsm_xl_full_scale_set(stmdev_ctx_t *ctx, lsm6dsm_fs_xl_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_xl_full_scale_get(stmdev_ctx_t *ctx, lsm6dsm_fs_xl_t *val)
+int32_t lsm6dsm_xl_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6dsm_fs_xl_t *val)
{
lsm6dsm_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- switch (ctrl1_xl.fs_xl) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ switch (ctrl1_xl.fs_xl)
+ {
case LSM6DSM_2g:
*val = LSM6DSM_2g;
break;
+
case LSM6DSM_16g:
*val = LSM6DSM_16g;
break;
+
case LSM6DSM_4g:
*val = LSM6DSM_4g;
break;
+
case LSM6DSM_8g:
*val = LSM6DSM_8g;
break;
+
default:
*val = LSM6DSM_2g;
break;
@@ -212,16 +229,20 @@ int32_t lsm6dsm_xl_full_scale_get(stmdev_ctx_t *ctx, lsm6dsm_fs_xl_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6dsm_odr_xl_t val)
+int32_t lsm6dsm_xl_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dsm_odr_xl_t val)
{
lsm6dsm_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
ctrl1_xl.odr_xl = (uint8_t) val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -233,49 +254,64 @@ int32_t lsm6dsm_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6dsm_odr_xl_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_xl_data_rate_get(stmdev_ctx_t *ctx, lsm6dsm_odr_xl_t *val)
+int32_t lsm6dsm_xl_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dsm_odr_xl_t *val)
{
lsm6dsm_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- switch (ctrl1_xl.odr_xl) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ switch (ctrl1_xl.odr_xl)
+ {
case LSM6DSM_XL_ODR_OFF:
*val = LSM6DSM_XL_ODR_OFF;
break;
+
case LSM6DSM_XL_ODR_12Hz5:
*val = LSM6DSM_XL_ODR_12Hz5;
break;
+
case LSM6DSM_XL_ODR_26Hz:
*val = LSM6DSM_XL_ODR_26Hz;
break;
+
case LSM6DSM_XL_ODR_52Hz:
*val = LSM6DSM_XL_ODR_52Hz;
break;
+
case LSM6DSM_XL_ODR_104Hz:
*val = LSM6DSM_XL_ODR_104Hz;
break;
+
case LSM6DSM_XL_ODR_208Hz:
*val = LSM6DSM_XL_ODR_208Hz;
break;
+
case LSM6DSM_XL_ODR_416Hz:
*val = LSM6DSM_XL_ODR_416Hz;
break;
+
case LSM6DSM_XL_ODR_833Hz:
*val = LSM6DSM_XL_ODR_833Hz;
break;
+
case LSM6DSM_XL_ODR_1k66Hz:
*val = LSM6DSM_XL_ODR_1k66Hz;
break;
+
case LSM6DSM_XL_ODR_3k33Hz:
*val = LSM6DSM_XL_ODR_3k33Hz;
break;
+
case LSM6DSM_XL_ODR_6k66Hz:
*val = LSM6DSM_XL_ODR_6k66Hz;
break;
+
case LSM6DSM_XL_ODR_1Hz6:
*val = LSM6DSM_XL_ODR_1Hz6;
break;
+
default:
*val = LSM6DSM_XL_ODR_OFF;
break;
@@ -292,16 +328,20 @@ int32_t lsm6dsm_xl_data_rate_get(stmdev_ctx_t *ctx, lsm6dsm_odr_xl_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_gy_full_scale_set(stmdev_ctx_t *ctx, lsm6dsm_fs_g_t val)
+int32_t lsm6dsm_gy_full_scale_set(stmdev_ctx_t *ctx,
+ lsm6dsm_fs_g_t val)
{
lsm6dsm_ctrl2_g_t ctrl2_g;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
+
+ if (ret == 0)
+ {
ctrl2_g.fs_g = (uint8_t) val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
}
+
return ret;
}
@@ -313,28 +353,36 @@ int32_t lsm6dsm_gy_full_scale_set(stmdev_ctx_t *ctx, lsm6dsm_fs_g_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_gy_full_scale_get(stmdev_ctx_t *ctx, lsm6dsm_fs_g_t *val)
+int32_t lsm6dsm_gy_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6dsm_fs_g_t *val)
{
lsm6dsm_ctrl2_g_t ctrl2_g;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- switch (ctrl2_g.fs_g) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
+
+ switch (ctrl2_g.fs_g)
+ {
case LSM6DSM_250dps:
*val = LSM6DSM_250dps;
break;
+
case LSM6DSM_125dps:
*val = LSM6DSM_125dps;
break;
+
case LSM6DSM_500dps:
*val = LSM6DSM_500dps;
break;
+
case LSM6DSM_1000dps:
*val = LSM6DSM_1000dps;
break;
+
case LSM6DSM_2000dps:
*val = LSM6DSM_2000dps;
break;
+
default:
*val = LSM6DSM_250dps;
break;
@@ -351,16 +399,20 @@ int32_t lsm6dsm_gy_full_scale_get(stmdev_ctx_t *ctx, lsm6dsm_fs_g_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_gy_data_rate_set(stmdev_ctx_t *ctx, lsm6dsm_odr_g_t val)
+int32_t lsm6dsm_gy_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dsm_odr_g_t val)
{
lsm6dsm_ctrl2_g_t ctrl2_g;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
+
+ if (ret == 0)
+ {
ctrl2_g.odr_g = (uint8_t) val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
}
+
return ret;
}
@@ -372,46 +424,60 @@ int32_t lsm6dsm_gy_data_rate_set(stmdev_ctx_t *ctx, lsm6dsm_odr_g_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_gy_data_rate_get(stmdev_ctx_t *ctx, lsm6dsm_odr_g_t *val)
+int32_t lsm6dsm_gy_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dsm_odr_g_t *val)
{
lsm6dsm_ctrl2_g_t ctrl2_g;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- switch (ctrl2_g.odr_g) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
+
+ switch (ctrl2_g.odr_g)
+ {
case LSM6DSM_GY_ODR_OFF:
*val = LSM6DSM_GY_ODR_OFF;
break;
+
case LSM6DSM_GY_ODR_12Hz5:
*val = LSM6DSM_GY_ODR_12Hz5;
break;
+
case LSM6DSM_GY_ODR_26Hz:
*val = LSM6DSM_GY_ODR_26Hz;
break;
+
case LSM6DSM_GY_ODR_52Hz:
*val = LSM6DSM_GY_ODR_52Hz;
break;
+
case LSM6DSM_GY_ODR_104Hz:
*val = LSM6DSM_GY_ODR_104Hz;
break;
+
case LSM6DSM_GY_ODR_208Hz:
*val = LSM6DSM_GY_ODR_208Hz;
break;
+
case LSM6DSM_GY_ODR_416Hz:
*val = LSM6DSM_GY_ODR_416Hz;
break;
+
case LSM6DSM_GY_ODR_833Hz:
*val = LSM6DSM_GY_ODR_833Hz;
break;
+
case LSM6DSM_GY_ODR_1k66Hz:
*val = LSM6DSM_GY_ODR_1k66Hz;
break;
+
case LSM6DSM_GY_ODR_3k33Hz:
*val = LSM6DSM_GY_ODR_3k33Hz;
break;
+
case LSM6DSM_GY_ODR_6k66Hz:
*val = LSM6DSM_GY_ODR_6k66Hz;
break;
+
default:
*val = LSM6DSM_GY_ODR_OFF;
break;
@@ -433,11 +499,14 @@ int32_t lsm6dsm_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.bdu = val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -454,7 +523,7 @@ int32_t lsm6dsm_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.bdu;
return ret;
@@ -475,11 +544,14 @@ int32_t lsm6dsm_xl_offset_weight_set(stmdev_ctx_t *ctx,
lsm6dsm_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
ctrl6_c.usr_off_w = (uint8_t) val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -498,14 +570,18 @@ int32_t lsm6dsm_xl_offset_weight_get(stmdev_ctx_t *ctx,
lsm6dsm_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- switch (ctrl6_c.usr_off_w) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ switch (ctrl6_c.usr_off_w)
+ {
case LSM6DSM_LSb_1mg:
*val = LSM6DSM_LSb_1mg;
break;
+
case LSM6DSM_LSb_16mg:
*val = LSM6DSM_LSb_16mg;
break;
+
default:
*val = LSM6DSM_LSb_1mg;
break;
@@ -528,11 +604,14 @@ int32_t lsm6dsm_xl_power_mode_set(stmdev_ctx_t *ctx,
lsm6dsm_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
ctrl6_c.xl_hm_mode = (uint8_t) val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -550,14 +629,18 @@ int32_t lsm6dsm_xl_power_mode_get(stmdev_ctx_t *ctx,
lsm6dsm_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- switch (ctrl6_c.xl_hm_mode) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ switch (ctrl6_c.xl_hm_mode)
+ {
case LSM6DSM_XL_HIGH_PERFORMANCE:
*val = LSM6DSM_XL_HIGH_PERFORMANCE;
break;
+
case LSM6DSM_XL_NORMAL:
*val = LSM6DSM_XL_NORMAL;
break;
+
default:
*val = LSM6DSM_XL_HIGH_PERFORMANCE;
break;
@@ -582,11 +665,14 @@ int32_t lsm6dsm_rounding_on_status_set(stmdev_ctx_t *ctx,
lsm6dsm_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
ctrl7_g.rounding_status = (uint8_t) val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
}
+
return ret;
}
@@ -606,14 +692,18 @@ int32_t lsm6dsm_rounding_on_status_get(stmdev_ctx_t *ctx,
lsm6dsm_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- switch (ctrl7_g.rounding_status) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ switch (ctrl7_g.rounding_status)
+ {
case LSM6DSM_STAT_RND_DISABLE:
*val = LSM6DSM_STAT_RND_DISABLE;
break;
+
case LSM6DSM_STAT_RND_ENABLE:
*val = LSM6DSM_STAT_RND_ENABLE;
break;
+
default:
*val = LSM6DSM_STAT_RND_DISABLE;
break;
@@ -630,16 +720,20 @@ int32_t lsm6dsm_rounding_on_status_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_gy_power_mode_set(stmdev_ctx_t *ctx, lsm6dsm_g_hm_mode_t val)
+int32_t lsm6dsm_gy_power_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsm_g_hm_mode_t val)
{
lsm6dsm_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
ctrl7_g.g_hm_mode = (uint8_t) val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
}
+
return ret;
}
@@ -651,19 +745,24 @@ int32_t lsm6dsm_gy_power_mode_set(stmdev_ctx_t *ctx, lsm6dsm_g_hm_mode_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_gy_power_mode_get(stmdev_ctx_t *ctx, lsm6dsm_g_hm_mode_t *val)
+int32_t lsm6dsm_gy_power_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsm_g_hm_mode_t *val)
{
lsm6dsm_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- switch (ctrl7_g.g_hm_mode) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ switch (ctrl7_g.g_hm_mode)
+ {
case LSM6DSM_GY_HIGH_PERFORMANCE:
*val = LSM6DSM_GY_HIGH_PERFORMANCE;
break;
+
case LSM6DSM_GY_NORMAL:
*val = LSM6DSM_GY_NORMAL;
break;
+
default:
*val = LSM6DSM_GY_HIGH_PERFORMANCE;
break;
@@ -687,39 +786,57 @@ int32_t lsm6dsm_all_sources_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_SRC,
- (uint8_t*)&(val->wake_up_src), 1);
- if(ret == 0){
+ (uint8_t *) & (val->wake_up_src), 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_SRC,
- (uint8_t*)&(val->tap_src), 1);
+ (uint8_t *) & (val->tap_src), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_D6D_SRC,
- (uint8_t*)&(val->d6d_src), 1);
+ (uint8_t *) & (val->d6d_src), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_REG,
- (uint8_t*)&(val->status_reg), 1);
+ (uint8_t *) & (val->status_reg), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_FUNC_SRC1,
- (uint8_t*)&(val->func_src1), 1);
+ (uint8_t *) & (val->func_src1), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_FUNC_SRC2,
- (uint8_t*)&(val->func_src2), 1);
+ (uint8_t *) & (val->func_src2), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_WRIST_TILT_IA,
- (uint8_t*)&(val->wrist_tilt_ia), 1);
+ (uint8_t *) & (val->wrist_tilt_ia), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_B);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_A_WRIST_TILT_MASK,
- (uint8_t*)&(val->a_wrist_tilt_mask), 1);
+ (uint8_t *) & (val->a_wrist_tilt_mask), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
@@ -733,10 +850,13 @@ int32_t lsm6dsm_all_sources_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_status_reg_get(stmdev_ctx_t *ctx, lsm6dsm_status_reg_t *val)
+int32_t lsm6dsm_status_reg_get(stmdev_ctx_t *ctx,
+ lsm6dsm_status_reg_t *val)
{
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_REG, (uint8_t*) val, 1);
+
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_REG, (uint8_t *) val, 1);
+
return ret;
}
@@ -748,12 +868,14 @@ int32_t lsm6dsm_status_reg_get(stmdev_ctx_t *ctx, lsm6dsm_status_reg_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsm_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsm_status_reg_t status_reg;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_REG, (uint8_t*)&status_reg, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_REG,
+ (uint8_t *)&status_reg, 1);
*val = status_reg.xlda;
return ret;
@@ -767,12 +889,14 @@ int32_t lsm6dsm_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsm_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsm_status_reg_t status_reg;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_REG, (uint8_t*)&status_reg, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_REG,
+ (uint8_t *)&status_reg, 1);
*val = status_reg.gda;
return ret;
@@ -786,12 +910,14 @@ int32_t lsm6dsm_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsm_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsm_status_reg_t status_reg;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_REG, (uint8_t*)&status_reg, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_REG,
+ (uint8_t *)&status_reg, 1);
*val = status_reg.tda;
return ret;
@@ -810,7 +936,9 @@ int32_t lsm6dsm_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t lsm6dsm_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsm_write_reg(ctx, LSM6DSM_X_OFS_USR, buff, 3);
+
return ret;
}
@@ -827,7 +955,9 @@ int32_t lsm6dsm_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lsm6dsm_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsm_read_reg(ctx, LSM6DSM_X_OFS_USR, buff, 3);
+
return ret;
}
@@ -858,14 +988,19 @@ int32_t lsm6dsm_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
ctrl10_c.timer_en = val;
- if ( val != 0x00U) {
+
+ if (val != 0x00U)
+ {
ctrl10_c.func_en = val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
}
}
+
return ret;
}
@@ -883,7 +1018,7 @@ int32_t lsm6dsm_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
*val = ctrl10_c.timer_en;
return ret;
@@ -902,17 +1037,22 @@ int32_t lsm6dsm_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_timestamp_res_set(stmdev_ctx_t *ctx, lsm6dsm_timer_hr_t val)
+int32_t lsm6dsm_timestamp_res_set(stmdev_ctx_t *ctx,
+ lsm6dsm_timer_hr_t val)
{
lsm6dsm_wake_up_dur_t wake_up_dur;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
wake_up_dur.timer_hr = (uint8_t) val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -929,19 +1069,25 @@ int32_t lsm6dsm_timestamp_res_set(stmdev_ctx_t *ctx, lsm6dsm_timer_hr_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_timestamp_res_get(stmdev_ctx_t *ctx, lsm6dsm_timer_hr_t *val)
+int32_t lsm6dsm_timestamp_res_get(stmdev_ctx_t *ctx,
+ lsm6dsm_timer_hr_t *val)
{
lsm6dsm_wake_up_dur_t wake_up_dur;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
- switch (wake_up_dur.timer_hr) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
+
+ switch (wake_up_dur.timer_hr)
+ {
case LSM6DSM_LSB_6ms4:
*val = LSM6DSM_LSB_6ms4;
break;
+
case LSM6DSM_LSB_25us:
*val = LSM6DSM_LSB_25us;
break;
+
default:
*val = LSM6DSM_LSB_6ms4;
break;
@@ -971,16 +1117,20 @@ int32_t lsm6dsm_timestamp_res_get(stmdev_ctx_t *ctx, lsm6dsm_timer_hr_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_rounding_mode_set(stmdev_ctx_t *ctx, lsm6dsm_rounding_t val)
+int32_t lsm6dsm_rounding_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsm_rounding_t val)
{
lsm6dsm_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ if (ret == 0)
+ {
ctrl5_c.rounding = (uint8_t) val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -993,37 +1143,48 @@ int32_t lsm6dsm_rounding_mode_set(stmdev_ctx_t *ctx, lsm6dsm_rounding_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_rounding_mode_get(stmdev_ctx_t *ctx, lsm6dsm_rounding_t *val)
+int32_t lsm6dsm_rounding_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsm_rounding_t *val)
{
lsm6dsm_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- switch (ctrl5_c.rounding) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ switch (ctrl5_c.rounding)
+ {
case LSM6DSM_ROUND_DISABLE:
*val = LSM6DSM_ROUND_DISABLE;
break;
+
case LSM6DSM_ROUND_XL:
*val = LSM6DSM_ROUND_XL;
break;
+
case LSM6DSM_ROUND_GY:
*val = LSM6DSM_ROUND_GY;
break;
+
case LSM6DSM_ROUND_GY_XL:
*val = LSM6DSM_ROUND_GY_XL;
break;
+
case LSM6DSM_ROUND_SH1_TO_SH6:
*val = LSM6DSM_ROUND_SH1_TO_SH6;
break;
+
case LSM6DSM_ROUND_XL_SH1_TO_SH6:
*val = LSM6DSM_ROUND_XL_SH1_TO_SH6;
break;
+
case LSM6DSM_ROUND_GY_XL_SH1_TO_SH12:
*val = LSM6DSM_ROUND_GY_XL_SH1_TO_SH12;
break;
+
case LSM6DSM_ROUND_GY_XL_SH1_TO_SH6:
*val = LSM6DSM_ROUND_GY_XL_SH1_TO_SH6;
break;
+
default:
*val = LSM6DSM_ROUND_DISABLE;
break;
@@ -1041,10 +1202,15 @@ int32_t lsm6dsm_rounding_mode_get(stmdev_ctx_t *ctx, lsm6dsm_rounding_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsm_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
+
ret = lsm6dsm_read_reg(ctx, LSM6DSM_OUT_TEMP_L, buff, 2);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+
return ret;
}
@@ -1057,10 +1223,19 @@ int32_t lsm6dsm_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsm_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lsm6dsm_read_reg(ctx, LSM6DSM_OUTX_L_G, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -1073,10 +1248,19 @@ int32_t lsm6dsm_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsm_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lsm6dsm_read_reg(ctx, LSM6DSM_OUTX_L_XL, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -1088,10 +1272,20 @@ int32_t lsm6dsm_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_mag_calibrated_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsm_mag_calibrated_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lsm6dsm_read_reg(ctx, LSM6DSM_OUT_MAG_RAW_X_L, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -1108,7 +1302,9 @@ int32_t lsm6dsm_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer,
uint8_t len)
{
int32_t ret;
+
ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_DATA_OUT_L, buffer, len);
+
return ret;
}
@@ -1119,7 +1315,7 @@ int32_t lsm6dsm_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer,
/**
* @defgroup LSM6DSM_common
- * @brief This section groups common usefull functions.
+ * @brief This section groups common useful functions.
* @{
*
*/
@@ -1133,17 +1329,20 @@ int32_t lsm6dsm_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_mem_bank_set(stmdev_ctx_t *ctx, lsm6dsm_func_cfg_en_t val)
+int32_t lsm6dsm_mem_bank_set(stmdev_ctx_t *ctx,
+ lsm6dsm_func_cfg_en_t val)
{
lsm6dsm_func_cfg_access_t func_cfg_access;
int32_t ret;
ret = lsm6dsm_read_reg(ctx, LSM6DSM_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
- if(ret == 0){
+ (uint8_t *)&func_cfg_access, 1);
+
+ if (ret == 0)
+ {
func_cfg_access.func_cfg_en = (uint8_t) val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
+ (uint8_t *)&func_cfg_access, 1);
}
return ret;
@@ -1158,20 +1357,25 @@ int32_t lsm6dsm_mem_bank_set(stmdev_ctx_t *ctx, lsm6dsm_func_cfg_en_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_mem_bank_get(stmdev_ctx_t *ctx, lsm6dsm_func_cfg_en_t *val)
+int32_t lsm6dsm_mem_bank_get(stmdev_ctx_t *ctx,
+ lsm6dsm_func_cfg_en_t *val)
{
lsm6dsm_func_cfg_access_t func_cfg_access;
int32_t ret;
ret = lsm6dsm_read_reg(ctx, LSM6DSM_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
- switch (func_cfg_access.func_cfg_en) {
+ (uint8_t *)&func_cfg_access, 1);
+
+ switch (func_cfg_access.func_cfg_en)
+ {
case LSM6DSM_USER_BANK:
*val = LSM6DSM_USER_BANK;
break;
+
case LSM6DSM_BANK_B:
*val = LSM6DSM_BANK_B;
break;
+
default:
*val = LSM6DSM_USER_BANK;
break;
@@ -1195,12 +1399,15 @@ int32_t lsm6dsm_data_ready_mode_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsm_read_reg(ctx, LSM6DSM_DRDY_PULSE_CFG,
- (uint8_t*)&drdy_pulse_cfg, 1);
- if(ret == 0){
+ (uint8_t *)&drdy_pulse_cfg, 1);
+
+ if (ret == 0)
+ {
drdy_pulse_cfg.drdy_pulsed = (uint8_t) val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_DRDY_PULSE_CFG,
- (uint8_t*)&drdy_pulse_cfg, 1);
+ (uint8_t *)&drdy_pulse_cfg, 1);
}
+
return ret;
}
@@ -1219,14 +1426,18 @@ int32_t lsm6dsm_data_ready_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsm_read_reg(ctx, LSM6DSM_DRDY_PULSE_CFG,
- (uint8_t*)&drdy_pulse_cfg, 1);
- switch (drdy_pulse_cfg.drdy_pulsed) {
+ (uint8_t *)&drdy_pulse_cfg, 1);
+
+ switch (drdy_pulse_cfg.drdy_pulsed)
+ {
case LSM6DSM_DRDY_LATCHED:
*val = LSM6DSM_DRDY_LATCHED;
break;
+
case LSM6DSM_DRDY_PULSED:
*val = LSM6DSM_DRDY_PULSED;
break;
+
default:
*val = LSM6DSM_DRDY_LATCHED;
break;
@@ -1246,7 +1457,9 @@ int32_t lsm6dsm_data_ready_mode_get(stmdev_ctx_t *ctx,
int32_t lsm6dsm_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsm_read_reg(ctx, LSM6DSM_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -1263,11 +1476,14 @@ int32_t lsm6dsm_reset_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.sw_reset = val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1284,7 +1500,7 @@ int32_t lsm6dsm_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.sw_reset;
return ret;
@@ -1303,11 +1519,14 @@ int32_t lsm6dsm_data_format_set(stmdev_ctx_t *ctx, lsm6dsm_ble_t val)
lsm6dsm_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.ble = (uint8_t) val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1324,14 +1543,18 @@ int32_t lsm6dsm_data_format_get(stmdev_ctx_t *ctx, lsm6dsm_ble_t *val)
lsm6dsm_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- switch (ctrl3_c.ble) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ switch (ctrl3_c.ble)
+ {
case LSM6DSM_LSB_AT_LOW_ADD:
*val = LSM6DSM_LSB_AT_LOW_ADD;
break;
+
case LSM6DSM_MSB_AT_LOW_ADD:
*val = LSM6DSM_MSB_AT_LOW_ADD;
break;
+
default:
*val = LSM6DSM_LSB_AT_LOW_ADD;
break;
@@ -1354,11 +1577,14 @@ int32_t lsm6dsm_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.if_inc = val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1376,7 +1602,7 @@ int32_t lsm6dsm_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.if_inc;
return ret;
@@ -1395,11 +1621,14 @@ int32_t lsm6dsm_boot_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.boot = val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1416,7 +1645,7 @@ int32_t lsm6dsm_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.boot;
return ret;
@@ -1430,16 +1659,20 @@ int32_t lsm6dsm_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_xl_self_test_set(stmdev_ctx_t *ctx, lsm6dsm_st_xl_t val)
+int32_t lsm6dsm_xl_self_test_set(stmdev_ctx_t *ctx,
+ lsm6dsm_st_xl_t val)
{
lsm6dsm_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ if (ret == 0)
+ {
ctrl5_c.st_xl = (uint8_t) val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -1451,26 +1684,33 @@ int32_t lsm6dsm_xl_self_test_set(stmdev_ctx_t *ctx, lsm6dsm_st_xl_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_xl_self_test_get(stmdev_ctx_t *ctx, lsm6dsm_st_xl_t *val)
+int32_t lsm6dsm_xl_self_test_get(stmdev_ctx_t *ctx,
+ lsm6dsm_st_xl_t *val)
{
lsm6dsm_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- switch (ctrl5_c.st_xl) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ switch (ctrl5_c.st_xl)
+ {
case LSM6DSM_XL_ST_DISABLE:
*val = LSM6DSM_XL_ST_DISABLE;
break;
+
case LSM6DSM_XL_ST_POSITIVE:
*val = LSM6DSM_XL_ST_POSITIVE;
break;
+
case LSM6DSM_XL_ST_NEGATIVE:
*val = LSM6DSM_XL_ST_NEGATIVE;
break;
+
default:
*val = LSM6DSM_XL_ST_DISABLE;
break;
}
+
return ret;
}
@@ -1482,16 +1722,20 @@ int32_t lsm6dsm_xl_self_test_get(stmdev_ctx_t *ctx, lsm6dsm_st_xl_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_gy_self_test_set(stmdev_ctx_t *ctx, lsm6dsm_st_g_t val)
+int32_t lsm6dsm_gy_self_test_set(stmdev_ctx_t *ctx,
+ lsm6dsm_st_g_t val)
{
lsm6dsm_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ if (ret == 0)
+ {
ctrl5_c.st_g = (uint8_t) val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -1503,22 +1747,28 @@ int32_t lsm6dsm_gy_self_test_set(stmdev_ctx_t *ctx, lsm6dsm_st_g_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_gy_self_test_get(stmdev_ctx_t *ctx, lsm6dsm_st_g_t *val)
+int32_t lsm6dsm_gy_self_test_get(stmdev_ctx_t *ctx,
+ lsm6dsm_st_g_t *val)
{
lsm6dsm_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- switch (ctrl5_c.st_g) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ switch (ctrl5_c.st_g)
+ {
case LSM6DSM_GY_ST_DISABLE:
*val = LSM6DSM_GY_ST_DISABLE;
break;
+
case LSM6DSM_GY_ST_POSITIVE:
*val = LSM6DSM_GY_ST_POSITIVE;
break;
+
case LSM6DSM_GY_ST_NEGATIVE:
*val = LSM6DSM_GY_ST_NEGATIVE;
break;
+
default:
*val = LSM6DSM_GY_ST_DISABLE;
break;
@@ -1549,16 +1799,20 @@ int32_t lsm6dsm_gy_self_test_get(stmdev_ctx_t *ctx, lsm6dsm_st_g_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dsm_filter_settling_mask_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dsm_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
ctrl4_c.drdy_mask = val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -1571,12 +1825,13 @@ int32_t lsm6dsm_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsm_filter_settling_mask_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsm_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.drdy_mask;
return ret;
@@ -1597,11 +1852,14 @@ int32_t lsm6dsm_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
lsm6dsm_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
tap_cfg.slope_fds = (uint8_t) val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -1620,14 +1878,18 @@ int32_t lsm6dsm_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
lsm6dsm_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- switch (tap_cfg.slope_fds) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
+
+ switch (tap_cfg.slope_fds)
+ {
case LSM6DSM_USE_SLOPE:
*val = LSM6DSM_USE_SLOPE;
break;
+
case LSM6DSM_USE_HPF:
*val = LSM6DSM_USE_HPF;
break;
+
default:
*val = LSM6DSM_USE_SLOPE;
break;
@@ -1658,16 +1920,20 @@ int32_t lsm6dsm_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_xl_filter_analog_set(stmdev_ctx_t *ctx, lsm6dsm_bw0_xl_t val)
+int32_t lsm6dsm_xl_filter_analog_set(stmdev_ctx_t *ctx,
+ lsm6dsm_bw0_xl_t val)
{
lsm6dsm_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
ctrl1_xl.bw0_xl = (uint8_t) val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -1686,14 +1952,18 @@ int32_t lsm6dsm_xl_filter_analog_get(stmdev_ctx_t *ctx,
lsm6dsm_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- switch (ctrl1_xl.bw0_xl) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ switch (ctrl1_xl.bw0_xl)
+ {
case LSM6DSM_XL_ANA_BW_1k5Hz:
*val = LSM6DSM_XL_ANA_BW_1k5Hz;
break;
+
case LSM6DSM_XL_ANA_BW_400Hz:
*val = LSM6DSM_XL_ANA_BW_400Hz;
break;
+
default:
*val = LSM6DSM_XL_ANA_BW_1k5Hz;
break;
@@ -1732,19 +2002,26 @@ int32_t lsm6dsm_xl_lp1_bandwidth_set(stmdev_ctx_t *ctx,
lsm6dsm_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
ctrl1_xl.lpf1_bw_sel = (uint8_t) val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
ctrl8_xl.lpf2_xl_en = 0;
ctrl8_xl.hp_slope_xl_en = 0;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
}
}
}
+
return ret;
}
@@ -1764,27 +2041,37 @@ int32_t lsm6dsm_xl_lp1_bandwidth_get(stmdev_ctx_t *ctx,
lsm6dsm_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
if ((ctrl8_xl.lpf2_xl_en != 0x00U) ||
- (ctrl8_xl.hp_slope_xl_en != 0x00U)){
+ (ctrl8_xl.hp_slope_xl_en != 0x00U))
+ {
*val = LSM6DSM_XL_LP1_NA;
}
- else{
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- switch ( ctrl1_xl.lpf1_bw_sel) {
+
+ else
+ {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ switch (ctrl1_xl.lpf1_bw_sel)
+ {
case LSM6DSM_XL_LP1_ODR_DIV_2:
*val = LSM6DSM_XL_LP1_ODR_DIV_2;
break;
+
case LSM6DSM_XL_LP1_ODR_DIV_4:
*val = LSM6DSM_XL_LP1_ODR_DIV_4;
break;
+
default:
*val = LSM6DSM_XL_LP1_ODR_DIV_2;
break;
}
}
}
+
return ret;
}
@@ -1802,14 +2089,17 @@ int32_t lsm6dsm_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx,
lsm6dsm_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
- ctrl8_xl.input_composite = ( (uint8_t) val & 0x10U ) >> 4;
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl8_xl.input_composite = ((uint8_t) val & 0x10U) >> 4;
ctrl8_xl.hpcf_xl = (uint8_t) val & 0x03U;
ctrl8_xl.lpf2_xl_en = 1;
ctrl8_xl.hp_slope_xl_en = 0;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -1827,38 +2117,52 @@ int32_t lsm6dsm_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx,
lsm6dsm_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
if ((ctrl8_xl.lpf2_xl_en == 0x00U) ||
- (ctrl8_xl.hp_slope_xl_en != 0x00U)){
+ (ctrl8_xl.hp_slope_xl_en != 0x00U))
+ {
*val = LSM6DSM_XL_LP_NA;
}
- else{
- switch ((ctrl8_xl.input_composite << 4) + ctrl8_xl.hpcf_xl) {
+
+ else
+ {
+ switch ((ctrl8_xl.input_composite << 4) + ctrl8_xl.hpcf_xl)
+ {
case LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_50:
*val = LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_50;
break;
+
case LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_100:
*val = LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_100;
break;
+
case LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_9:
*val = LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_9;
break;
+
case LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_400:
*val = LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_400;
break;
+
case LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_50:
*val = LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_50;
break;
+
case LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_100:
*val = LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_100;
break;
+
case LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_9:
*val = LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_9;
break;
+
case LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_400:
*val = LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_400;
break;
+
default:
*val = LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_50;
break;
@@ -1882,11 +2186,14 @@ int32_t lsm6dsm_xl_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
ctrl8_xl.hp_ref_mode = val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -1903,7 +2210,7 @@ int32_t lsm6dsm_xl_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
*val = ctrl8_xl.hp_ref_mode;
return ret;
@@ -1917,18 +2224,22 @@ int32_t lsm6dsm_xl_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_xl_hp_bandwidth_set(stmdev_ctx_t *ctx, lsm6dsm_hpcf_xl_t val)
+int32_t lsm6dsm_xl_hp_bandwidth_set(stmdev_ctx_t *ctx,
+ lsm6dsm_hpcf_xl_t val)
{
lsm6dsm_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
ctrl8_xl.input_composite = 0;
ctrl8_xl.hpcf_xl = (uint8_t)val & 0x03U;
ctrl8_xl.hp_slope_xl_en = 1;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -1940,28 +2251,37 @@ int32_t lsm6dsm_xl_hp_bandwidth_set(stmdev_ctx_t *ctx, lsm6dsm_hpcf_xl_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_xl_hp_bandwidth_get(stmdev_ctx_t *ctx, lsm6dsm_hpcf_xl_t *val)
+int32_t lsm6dsm_xl_hp_bandwidth_get(stmdev_ctx_t *ctx,
+ lsm6dsm_hpcf_xl_t *val)
{
lsm6dsm_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if (ctrl8_xl.hp_slope_xl_en == 0x00U){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ if (ctrl8_xl.hp_slope_xl_en == 0x00U)
+ {
*val = LSM6DSM_XL_HP_NA;
}
- switch (ctrl8_xl.hpcf_xl) {
+
+ switch (ctrl8_xl.hpcf_xl)
+ {
case LSM6DSM_XL_HP_ODR_DIV_4:
*val = LSM6DSM_XL_HP_ODR_DIV_4;
break;
+
case LSM6DSM_XL_HP_ODR_DIV_100:
*val = LSM6DSM_XL_HP_ODR_DIV_100;
break;
+
case LSM6DSM_XL_HP_ODR_DIV_9:
*val = LSM6DSM_XL_HP_ODR_DIV_9;
break;
+
case LSM6DSM_XL_HP_ODR_DIV_400:
*val = LSM6DSM_XL_HP_ODR_DIV_400;
break;
+
default:
*val = LSM6DSM_XL_HP_ODR_DIV_4;
break;
@@ -2000,18 +2320,25 @@ int32_t lsm6dsm_xl_ui_lp1_bandwidth_set(stmdev_ctx_t *ctx,
lsm6dsm_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
ctrl1_xl.lpf1_bw_sel = (uint8_t)val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
}
- if(ret == 0){
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ctrl8_xl.hp_slope_xl_en = 0x00U;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -2023,7 +2350,7 @@ int32_t lsm6dsm_xl_ui_lp1_bandwidth_set(stmdev_ctx_t *ctx,
* @param val Get the values of lpf1_bw_sel in reg CTRL1_XL
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
-*/
+ */
int32_t lsm6dsm_xl_ui_lp1_bandwidth_get(stmdev_ctx_t *ctx,
lsm6dsm_ui_lpf1_bw_sel_t *val)
{
@@ -2031,20 +2358,29 @@ int32_t lsm6dsm_xl_ui_lp1_bandwidth_get(stmdev_ctx_t *ctx,
lsm6dsm_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
- if (ctrl8_xl.hp_slope_xl_en != PROPERTY_DISABLE){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
+ if (ctrl8_xl.hp_slope_xl_en != PROPERTY_DISABLE)
+ {
*val = LSM6DSM_XL_UI_LP1_NA;
}
- else{
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- switch (ctrl1_xl.lpf1_bw_sel) {
+
+ else
+ {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ switch (ctrl1_xl.lpf1_bw_sel)
+ {
case LSM6DSM_XL_UI_LP1_ODR_DIV_2:
*val = LSM6DSM_XL_UI_LP1_ODR_DIV_2;
break;
+
case LSM6DSM_XL_UI_LP1_ODR_DIV_4:
*val = LSM6DSM_XL_UI_LP1_ODR_DIV_4;
break;
+
default:
*val = LSM6DSM_XL_UI_LP1_ODR_DIV_2;
break;
@@ -2062,17 +2398,20 @@ int32_t lsm6dsm_xl_ui_lp1_bandwidth_get(stmdev_ctx_t *ctx,
* @param val change the values of hp_slope_xl_en in reg CTRL8_XL
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
-*/
+ */
int32_t lsm6dsm_xl_ui_slope_set(stmdev_ctx_t *ctx, uint8_t val)
{
lsm6dsm_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
ctrl8_xl.hp_slope_xl_en = (uint8_t) val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -2083,13 +2422,13 @@ int32_t lsm6dsm_xl_ui_slope_set(stmdev_ctx_t *ctx, uint8_t val)
* @param val Get the values of hp_slope_xl_en in reg CTRL8_XL
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
-*/
+ */
int32_t lsm6dsm_xl_ui_slope_get(stmdev_ctx_t *ctx, uint8_t *val)
{
lsm6dsm_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
*val = ctrl8_xl.hp_slope_xl_en;
return ret;
@@ -2122,11 +2461,14 @@ int32_t lsm6dsm_xl_aux_lp_bandwidth_set(stmdev_ctx_t *ctx,
lsm6dsm_ctrl3_ois_t ctrl3_ois;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
+
+ if (ret == 0)
+ {
ctrl3_ois.filter_xl_conf_ois = (uint8_t) val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
}
+
return ret;
}
@@ -2157,24 +2499,31 @@ int32_t lsm6dsm_xl_aux_lp_bandwidth_get(stmdev_ctx_t *ctx,
lsm6dsm_ctrl3_ois_t ctrl3_ois;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
- switch (ctrl3_ois.filter_xl_conf_ois) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
+
+ switch (ctrl3_ois.filter_xl_conf_ois)
+ {
case LSM6DSM_AUX_LP_LIGHT:
*val = LSM6DSM_AUX_LP_LIGHT;
break;
+
case LSM6DSM_AUX_LP_NORMAL:
*val = LSM6DSM_AUX_LP_NORMAL;
break;
+
case LSM6DSM_AUX_LP_STRONG:
*val = LSM6DSM_AUX_LP_STRONG;
break;
+
case LSM6DSM_AUX_LP_AGGRESSIVE:
*val = LSM6DSM_AUX_LP_AGGRESSIVE;
break;
+
default:
*val = LSM6DSM_AUX_LP_LIGHT;
break;
}
+
return ret;
}
@@ -2200,35 +2549,47 @@ int32_t lsm6dsm_xl_aux_lp_bandwidth_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_gy_band_pass_set(stmdev_ctx_t *ctx, lsm6dsm_lpf1_sel_g_t val)
+int32_t lsm6dsm_gy_band_pass_set(stmdev_ctx_t *ctx,
+ lsm6dsm_lpf1_sel_g_t val)
{
lsm6dsm_ctrl4_c_t ctrl4_c;
lsm6dsm_ctrl6_c_t ctrl6_c;
lsm6dsm_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
- ctrl7_g.hpm_g = ( (uint8_t)val & 0x30U ) >> 4;
- ctrl7_g.hp_en_g = ( (uint8_t)val & 0x80U ) >> 7;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
+ ctrl7_g.hpm_g = ((uint8_t)val & 0x30U) >> 4;
+ ctrl7_g.hp_en_g = ((uint8_t)val & 0x80U) >> 7;
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
ctrl6_c.ftype = (uint8_t)val & 0x03U;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C,
- (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ctrl4_c.lpf1_sel_g = ( (uint8_t)val & 0x08U ) >> 3;
+ (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl4_c.lpf1_sel_g = ((uint8_t)val & 0x08U) >> 3;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL4_C,
- (uint8_t*)&ctrl4_c, 1);
+ (uint8_t *)&ctrl4_c, 1);
}
}
}
}
}
+
return ret;
}
@@ -2248,50 +2609,67 @@ int32_t lsm6dsm_gy_band_pass_get(stmdev_ctx_t *ctx,
lsm6dsm_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
- switch ( ( ctrl7_g.hp_en_g << 7 ) + ( ctrl7_g.hpm_g << 4 ) +
- ( ctrl4_c.lpf1_sel_g << 3) + ctrl6_c.ftype ) {
+ switch ((ctrl7_g.hp_en_g << 7) + (ctrl7_g.hpm_g << 4) +
+ (ctrl4_c.lpf1_sel_g << 3) + ctrl6_c.ftype)
+ {
case LSM6DSM_HP_16mHz_LP2:
*val = LSM6DSM_HP_16mHz_LP2;
break;
+
case LSM6DSM_HP_65mHz_LP2:
*val = LSM6DSM_HP_65mHz_LP2;
break;
+
case LSM6DSM_HP_260mHz_LP2:
*val = LSM6DSM_HP_260mHz_LP2;
break;
+
case LSM6DSM_HP_1Hz04_LP2:
*val = LSM6DSM_HP_1Hz04_LP2;
break;
+
case LSM6DSM_HP_DISABLE_LP1_LIGHT:
*val = LSM6DSM_HP_DISABLE_LP1_LIGHT;
break;
+
case LSM6DSM_HP_DISABLE_LP1_NORMAL:
*val = LSM6DSM_HP_DISABLE_LP1_NORMAL;
break;
+
case LSM6DSM_HP_DISABLE_LP_STRONG:
*val = LSM6DSM_HP_DISABLE_LP_STRONG;
break;
+
case LSM6DSM_HP_DISABLE_LP1_AGGRESSIVE:
*val = LSM6DSM_HP_DISABLE_LP1_AGGRESSIVE;
break;
+
case LSM6DSM_HP_16mHz_LP1_LIGHT:
*val = LSM6DSM_HP_16mHz_LP1_LIGHT;
break;
+
case LSM6DSM_HP_65mHz_LP1_NORMAL:
*val = LSM6DSM_HP_65mHz_LP1_NORMAL;
break;
+
case LSM6DSM_HP_260mHz_LP1_STRONG:
*val = LSM6DSM_HP_260mHz_LP1_STRONG;
break;
+
case LSM6DSM_HP_1Hz04_LP1_AGGRESSIVE:
*val = LSM6DSM_HP_1Hz04_LP1_AGGRESSIVE;
break;
+
default:
*val = LSM6DSM_HP_65mHz_LP2;
break;
@@ -2330,11 +2708,14 @@ int32_t lsm6dsm_gy_ui_high_pass_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
ctrl7_g.hp_en_g = val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
}
+
return ret;
}
@@ -2352,8 +2733,7 @@ int32_t lsm6dsm_gy_ui_high_pass_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
-
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
*val = ctrl7_g.hp_en_g;
return ret;
@@ -2377,20 +2757,27 @@ int32_t lsm6dsm_gy_aux_bandwidth_set(stmdev_ctx_t *ctx,
lsm6dsm_ctrl2_ois_t ctrl2_ois;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
ctrl7_g.hp_en_g = 0x00U;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
}
- if(ret == 0){
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL2_OIS, (uint8_t*)&ctrl2_ois, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL2_OIS, (uint8_t *)&ctrl2_ois, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ctrl2_ois.ftype_ois = (uint8_t)val & 0x03U;
- ctrl2_ois.hp_en_ois = ( (uint8_t)val & 0x80U ) >> 7;
- ctrl2_ois.hpm_ois = ( (uint8_t)val & 0x30U ) >> 4;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL2_OIS, (uint8_t*)&ctrl2_ois, 1);
+ ctrl2_ois.hp_en_ois = ((uint8_t)val & 0x80U) >> 7;
+ ctrl2_ois.hpm_ois = ((uint8_t)val & 0x30U) >> 4;
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL2_OIS, (uint8_t *)&ctrl2_ois, 1);
}
+
return ret;
}
@@ -2410,35 +2797,43 @@ int32_t lsm6dsm_gy_aux_bandwidth_get(stmdev_ctx_t *ctx,
lsm6dsm_ctrl2_ois_t ctrl2_ois;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL2_OIS, (uint8_t*)&ctrl2_ois, 1);
-
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL2_OIS, (uint8_t *)&ctrl2_ois, 1);
- switch ( ( ( ctrl2_ois.hp_en_ois << 7 ) + ( ctrl2_ois.hpm_ois << 4 )
- + ctrl2_ois.ftype_ois) ) {
+ switch (((ctrl2_ois.hp_en_ois << 7) + (ctrl2_ois.hpm_ois << 4)
+ + ctrl2_ois.ftype_ois))
+ {
case LSM6DSM_HP_DISABLE_LP_173Hz:
*val = LSM6DSM_HP_DISABLE_LP_173Hz;
break;
+
case LSM6DSM_HP_DISABLE_LP_237Hz:
*val = LSM6DSM_HP_DISABLE_LP_237Hz;
break;
+
case LSM6DSM_HP_DISABLE_LP_351Hz:
*val = LSM6DSM_HP_DISABLE_LP_351Hz;
break;
+
case LSM6DSM_HP_DISABLE_LP_937Hz:
*val = LSM6DSM_HP_DISABLE_LP_937Hz;
break;
+
case LSM6DSM_HP_16mHz_LP_173Hz:
*val = LSM6DSM_HP_16mHz_LP_173Hz;
break;
+
case LSM6DSM_HP_65mHz_LP_237Hz:
*val = LSM6DSM_HP_65mHz_LP_237Hz;
break;
+
case LSM6DSM_HP_260mHz_LP_351Hz:
*val = LSM6DSM_HP_260mHz_LP_351Hz;
break;
+
case LSM6DSM_HP_1Hz04_LP_937Hz:
*val = LSM6DSM_HP_1Hz04_LP_937Hz;
break;
+
default:
*val = LSM6DSM_HP_DISABLE_LP_173Hz;
break;
@@ -2472,7 +2867,9 @@ int32_t lsm6dsm_aux_status_reg_get(stmdev_ctx_t *ctx,
lsm6dsm_status_spiaux_t *val)
{
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_SPIAUX, (uint8_t*) val, 1);
+
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_SPIAUX, (uint8_t *) val, 1);
+
return ret;
}
@@ -2484,12 +2881,14 @@ int32_t lsm6dsm_aux_status_reg_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsm_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsm_status_spiaux_t status_spiaux;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_SPIAUX, (uint8_t*)&status_spiaux, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_SPIAUX,
+ (uint8_t *)&status_spiaux, 1);
*val = status_spiaux.xlda;
return ret;
@@ -2503,12 +2902,14 @@ int32_t lsm6dsm_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsm_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsm_status_spiaux_t status_spiaux;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_SPIAUX, (uint8_t*)&status_spiaux, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_SPIAUX,
+ (uint8_t *)&status_spiaux, 1);
*val = status_spiaux.gda;
return ret;
@@ -2522,12 +2923,14 @@ int32_t lsm6dsm_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsm_aux_gy_flag_settling_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsm_status_spiaux_t status_spiaux;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_SPIAUX, (uint8_t*)&status_spiaux, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_SPIAUX,
+ (uint8_t *)&status_spiaux, 1);
*val = status_spiaux.gyro_settling;
return ret;
@@ -2541,23 +2944,30 @@ int32_t lsm6dsm_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_aux_den_mode_set(stmdev_ctx_t *ctx, lsm6dsm_lvl_ois_t val)
+int32_t lsm6dsm_aux_den_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsm_lvl_ois_t val)
{
lsm6dsm_int_ois_t int_ois;
lsm6dsm_ctrl1_ois_t ctrl1_ois;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_OIS, (uint8_t*)&int_ois, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_OIS, (uint8_t *)&int_ois, 1);
+
+ if (ret == 0)
+ {
int_ois.lvl2_ois = (uint8_t)val & 0x01U;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_INT_OIS, (uint8_t*)&int_ois, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_INT_OIS, (uint8_t *)&int_ois, 1);
}
- if(ret == 0){
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
ctrl1_ois.lvl1_ois = ((uint8_t)val & 0x02U) >> 1;
}
- if(ret == 0){
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
}
return ret;
@@ -2571,30 +2981,39 @@ int32_t lsm6dsm_aux_den_mode_set(stmdev_ctx_t *ctx, lsm6dsm_lvl_ois_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_aux_den_mode_get(stmdev_ctx_t *ctx, lsm6dsm_lvl_ois_t *val)
+int32_t lsm6dsm_aux_den_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsm_lvl_ois_t *val)
{
lsm6dsm_int_ois_t int_ois;
lsm6dsm_ctrl1_ois_t ctrl1_ois;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_OIS, (uint8_t*)&int_ois, 1);
- if(ret == 0){
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
- switch ( ( ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois ) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_OIS, (uint8_t *)&int_ois, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
+
+ switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois)
+ {
case LSM6DSM_AUX_DEN_DISABLE:
*val = LSM6DSM_AUX_DEN_DISABLE;
break;
+
case LSM6DSM_AUX_DEN_LEVEL_LATCH:
*val = LSM6DSM_AUX_DEN_LEVEL_LATCH;
break;
+
case LSM6DSM_AUX_DEN_LEVEL_TRIG:
*val = LSM6DSM_AUX_DEN_LEVEL_TRIG;
break;
+
default:
*val = LSM6DSM_AUX_DEN_DISABLE;
break;
}
}
+
return ret;
}
@@ -2612,11 +3031,14 @@ int32_t lsm6dsm_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_int_ois_t int_ois;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_OIS, (uint8_t*)&int_ois, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_OIS, (uint8_t *)&int_ois, 1);
+
+ if (ret == 0)
+ {
int_ois.int2_drdy_ois = val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_INT_OIS, (uint8_t*)&int_ois, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_INT_OIS, (uint8_t *)&int_ois, 1);
}
+
return ret;
}
@@ -2634,7 +3056,7 @@ int32_t lsm6dsm_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_int_ois_t int_ois;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_OIS, (uint8_t*)&int_ois, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_OIS, (uint8_t *)&int_ois, 1);
*val = int_ois.int2_drdy_ois;
return ret;
@@ -2655,17 +3077,21 @@ int32_t lsm6dsm_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_aux_mode_set(stmdev_ctx_t *ctx, lsm6dsm_ois_en_spi2_t val)
+int32_t lsm6dsm_aux_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsm_ois_en_spi2_t val)
{
lsm6dsm_ctrl1_ois_t ctrl1_ois;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
+
+ if (ret == 0)
+ {
ctrl1_ois.ois_en_spi2 = (uint8_t)val & 0x01U;
ctrl1_ois.mode4_en = ((uint8_t)val & 0x02U) >> 1;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
}
+
return ret;
}
@@ -2684,26 +3110,33 @@ int32_t lsm6dsm_aux_mode_set(stmdev_ctx_t *ctx, lsm6dsm_ois_en_spi2_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_aux_mode_get(stmdev_ctx_t *ctx, lsm6dsm_ois_en_spi2_t *val)
+int32_t lsm6dsm_aux_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsm_ois_en_spi2_t *val)
{
lsm6dsm_ctrl1_ois_t ctrl1_ois;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
- switch ( (ctrl1_ois.mode4_en << 1) + ctrl1_ois.ois_en_spi2 ) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
+
+ switch ((ctrl1_ois.mode4_en << 1) + ctrl1_ois.ois_en_spi2)
+ {
case LSM6DSM_AUX_DISABLE:
*val = LSM6DSM_AUX_DISABLE;
break;
+
case LSM6DSM_MODE_3_GY:
*val = LSM6DSM_MODE_3_GY;
break;
+
case LSM6DSM_MODE_4_GY_XL:
*val = LSM6DSM_MODE_4_GY_XL;
break;
+
default:
*val = LSM6DSM_AUX_DISABLE;
break;
}
+
return ret;
}
@@ -2721,11 +3154,14 @@ int32_t lsm6dsm_aux_gy_full_scale_set(stmdev_ctx_t *ctx,
lsm6dsm_ctrl1_ois_t ctrl1_ois;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
+
+ if (ret == 0)
+ {
ctrl1_ois.fs_g_ois = (uint8_t)val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
}
+
return ret;
}
@@ -2743,27 +3179,35 @@ int32_t lsm6dsm_aux_gy_full_scale_get(stmdev_ctx_t *ctx,
lsm6dsm_ctrl1_ois_t ctrl1_ois;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
- switch ( ctrl1_ois.fs_g_ois ) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
+
+ switch (ctrl1_ois.fs_g_ois)
+ {
case LSM6DSM_250dps_AUX:
*val = LSM6DSM_250dps_AUX;
break;
+
case LSM6DSM_125dps_AUX:
*val = LSM6DSM_125dps_AUX;
break;
+
case LSM6DSM_500dps_AUX:
*val = LSM6DSM_500dps_AUX;
break;
+
case LSM6DSM_1000dps_AUX:
*val = LSM6DSM_1000dps_AUX;
break;
+
case LSM6DSM_2000dps_AUX:
*val = LSM6DSM_2000dps_AUX;
break;
+
default:
*val = LSM6DSM_250dps_AUX;
break;
}
+
return ret;
}
@@ -2775,16 +3219,20 @@ int32_t lsm6dsm_aux_gy_full_scale_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_aux_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsm_sim_ois_t val)
+int32_t lsm6dsm_aux_spi_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsm_sim_ois_t val)
{
lsm6dsm_ctrl1_ois_t ctrl1_ois;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
+
+ if (ret == 0)
+ {
ctrl1_ois.sim_ois = (uint8_t)val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
}
+
return ret;
}
@@ -2796,23 +3244,29 @@ int32_t lsm6dsm_aux_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsm_sim_ois_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_aux_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsm_sim_ois_t *val)
+int32_t lsm6dsm_aux_spi_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsm_sim_ois_t *val)
{
lsm6dsm_ctrl1_ois_t ctrl1_ois;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
- switch ( ctrl1_ois.sim_ois ) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
+
+ switch (ctrl1_ois.sim_ois)
+ {
case LSM6DSM_AUX_SPI_4_WIRE:
*val = LSM6DSM_AUX_SPI_4_WIRE;
break;
+
case LSM6DSM_AUX_SPI_3_WIRE:
*val = LSM6DSM_AUX_SPI_3_WIRE;
break;
+
default:
*val = LSM6DSM_AUX_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -2824,16 +3278,20 @@ int32_t lsm6dsm_aux_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsm_sim_ois_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_aux_data_format_set(stmdev_ctx_t *ctx, lsm6dsm_ble_ois_t val)
+int32_t lsm6dsm_aux_data_format_set(stmdev_ctx_t *ctx,
+ lsm6dsm_ble_ois_t val)
{
lsm6dsm_ctrl1_ois_t ctrl1_ois;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
+
+ if (ret == 0)
+ {
ctrl1_ois.ble_ois = (uint8_t)val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
}
+
return ret;
}
@@ -2845,23 +3303,29 @@ int32_t lsm6dsm_aux_data_format_set(stmdev_ctx_t *ctx, lsm6dsm_ble_ois_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_aux_data_format_get(stmdev_ctx_t *ctx, lsm6dsm_ble_ois_t *val)
+int32_t lsm6dsm_aux_data_format_get(stmdev_ctx_t *ctx,
+ lsm6dsm_ble_ois_t *val)
{
lsm6dsm_ctrl1_ois_t ctrl1_ois;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
- switch ( ctrl1_ois.ble_ois ) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
+
+ switch (ctrl1_ois.ble_ois)
+ {
case LSM6DSM_AUX_LSB_AT_LOW_ADD:
*val = LSM6DSM_AUX_LSB_AT_LOW_ADD;
break;
+
case LSM6DSM_AUX_MSB_AT_LOW_ADD:
*val = LSM6DSM_AUX_MSB_AT_LOW_ADD;
break;
+
default:
*val = LSM6DSM_AUX_LSB_AT_LOW_ADD;
break;
}
+
return ret;
}
@@ -2883,11 +3347,14 @@ int32_t lsm6dsm_aux_gy_clamp_set(stmdev_ctx_t *ctx,
lsm6dsm_ctrl3_ois_t ctrl3_ois;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
+
+ if (ret == 0)
+ {
ctrl3_ois.st_ois_clampdis = (uint8_t)val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
}
+
return ret;
}
@@ -2909,18 +3376,23 @@ int32_t lsm6dsm_aux_gy_clamp_get(stmdev_ctx_t *ctx,
lsm6dsm_ctrl3_ois_t ctrl3_ois;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
- switch ( ctrl3_ois.st_ois_clampdis ) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
+
+ switch (ctrl3_ois.st_ois_clampdis)
+ {
case LSM6DSM_ENABLE_CLAMP:
*val = LSM6DSM_ENABLE_CLAMP;
break;
+
case LSM6DSM_DISABLE_CLAMP:
*val = LSM6DSM_DISABLE_CLAMP;
break;
+
default:
*val = LSM6DSM_ENABLE_CLAMP;
break;
}
+
return ret;
}
@@ -2932,16 +3404,20 @@ int32_t lsm6dsm_aux_gy_clamp_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_aux_gy_self_test_set(stmdev_ctx_t *ctx, lsm6dsm_st_ois_t val)
+int32_t lsm6dsm_aux_gy_self_test_set(stmdev_ctx_t *ctx,
+ lsm6dsm_st_ois_t val)
{
lsm6dsm_ctrl3_ois_t ctrl3_ois;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
+
+ if (ret == 0)
+ {
ctrl3_ois.st_ois = (uint8_t)val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
}
+
return ret;
}
@@ -2959,21 +3435,27 @@ int32_t lsm6dsm_aux_gy_self_test_get(stmdev_ctx_t *ctx,
lsm6dsm_ctrl3_ois_t ctrl3_ois;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
- switch ( ctrl3_ois.st_ois ) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
+
+ switch (ctrl3_ois.st_ois)
+ {
case LSM6DSM_AUX_GY_DISABLE:
*val = LSM6DSM_AUX_GY_DISABLE;
break;
+
case LSM6DSM_AUX_GY_POS:
*val = LSM6DSM_AUX_GY_POS;
break;
+
case LSM6DSM_AUX_GY_NEG:
*val = LSM6DSM_AUX_GY_NEG;
break;
+
default:
*val = LSM6DSM_AUX_GY_DISABLE;
break;
}
+
return ret;
}
@@ -2991,11 +3473,14 @@ int32_t lsm6dsm_aux_xl_full_scale_set(stmdev_ctx_t *ctx,
lsm6dsm_ctrl3_ois_t ctrl3_ois;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
+
+ if (ret == 0)
+ {
ctrl3_ois.fs_xl_ois = (uint8_t)val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
}
+
return ret;
}
@@ -3013,24 +3498,31 @@ int32_t lsm6dsm_aux_xl_full_scale_get(stmdev_ctx_t *ctx,
lsm6dsm_ctrl3_ois_t ctrl3_ois;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
- switch ( ctrl3_ois.fs_xl_ois ) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
+
+ switch (ctrl3_ois.fs_xl_ois)
+ {
case LSM6DSM_AUX_2g:
*val = LSM6DSM_AUX_2g;
break;
+
case LSM6DSM_AUX_16g:
*val = LSM6DSM_AUX_16g;
break;
+
case LSM6DSM_AUX_4g:
*val = LSM6DSM_AUX_4g;
break;
+
case LSM6DSM_AUX_8g:
*val = LSM6DSM_AUX_8g;
break;
+
default:
*val = LSM6DSM_AUX_2g;
break;
}
+
return ret;
}
@@ -3048,11 +3540,14 @@ int32_t lsm6dsm_aux_den_polarity_set(stmdev_ctx_t *ctx,
lsm6dsm_ctrl3_ois_t ctrl3_ois;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
+
+ if (ret == 0)
+ {
ctrl3_ois.den_lh_ois = (uint8_t)val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
}
+
return ret;
}
@@ -3070,18 +3565,23 @@ int32_t lsm6dsm_aux_den_polarity_get(stmdev_ctx_t *ctx,
lsm6dsm_ctrl3_ois_t ctrl3_ois;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
- switch ( ctrl3_ois.den_lh_ois ) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
+
+ switch (ctrl3_ois.den_lh_ois)
+ {
case LSM6DSM_AUX_DEN_ACTIVE_LOW:
*val = LSM6DSM_AUX_DEN_ACTIVE_LOW;
break;
+
case LSM6DSM_AUX_DEN_ACTIVE_HIGH:
*val = LSM6DSM_AUX_DEN_ACTIVE_HIGH;
break;
+
default:
*val = LSM6DSM_AUX_DEN_ACTIVE_LOW;
break;
}
+
return ret;
}
@@ -3111,11 +3611,14 @@ int32_t lsm6dsm_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsm_sim_t val)
lsm6dsm_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.sim = (uint8_t)val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -3132,18 +3635,23 @@ int32_t lsm6dsm_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsm_sim_t *val)
lsm6dsm_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- switch (ctrl3_c.sim) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ switch (ctrl3_c.sim)
+ {
case LSM6DSM_SPI_4_WIRE:
*val = LSM6DSM_SPI_4_WIRE;
break;
+
case LSM6DSM_SPI_3_WIRE:
*val = LSM6DSM_SPI_3_WIRE;
break;
+
default:
*val = LSM6DSM_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -3161,11 +3669,14 @@ int32_t lsm6dsm_i2c_interface_set(stmdev_ctx_t *ctx,
lsm6dsm_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
ctrl4_c.i2c_disable = (uint8_t)val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -3183,14 +3694,18 @@ int32_t lsm6dsm_i2c_interface_get(stmdev_ctx_t *ctx,
lsm6dsm_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- switch (ctrl4_c.i2c_disable) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ switch (ctrl4_c.i2c_disable)
+ {
case LSM6DSM_I2C_ENABLE:
*val = LSM6DSM_I2C_ENABLE;
break;
+
case LSM6DSM_I2C_DISABLE:
*val = LSM6DSM_I2C_DISABLE;
break;
+
default:
*val = LSM6DSM_I2C_ENABLE;
break;
@@ -3207,7 +3722,7 @@ int32_t lsm6dsm_i2c_interface_get(stmdev_ctx_t *ctx,
/**
* @defgroup LSM6DSM_interrupt_pins
* @brief This section groups all the functions that manage
- * interrup pins
+ * interrupt pins
* @{
*
*/
@@ -3232,8 +3747,10 @@ int32_t lsm6dsm_pin_int1_route_set(stmdev_ctx_t *ctx,
lsm6dsm_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
+
+ if (ret == 0)
+ {
int1_ctrl.int1_drdy_xl = val.int1_drdy_xl;
int1_ctrl.int1_drdy_g = val.int1_drdy_g;
int1_ctrl.int1_boot = val.int1_boot;
@@ -3242,64 +3759,87 @@ int32_t lsm6dsm_pin_int1_route_set(stmdev_ctx_t *ctx,
int1_ctrl.int1_full_flag = val.int1_full_flag;
int1_ctrl.int1_sign_mot = val.int1_sign_mot;
int1_ctrl.int1_step_detector = val.int1_step_detector;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
}
- if(ret == 0){
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_MD1_CFG, (uint8_t*)&md1_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_MD1_CFG, (uint8_t *)&md1_cfg, 1);
}
- if(ret == 0){
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_MD2_CFG, (uint8_t*)&md2_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_MD2_CFG, (uint8_t *)&md2_cfg, 1);
}
- if(ret == 0){
- md1_cfg.int1_timer = val.int1_timer;
- md1_cfg.int1_tilt = val.int1_tilt;
- md1_cfg.int1_6d = val.int1_6d;
- md1_cfg.int1_double_tap = val.int1_double_tap;
- md1_cfg.int1_ff = val.int1_ff;
- md1_cfg.int1_wu = val.int1_wu;
- md1_cfg.int1_single_tap = val.int1_single_tap;
- md1_cfg.int1_inact_state = val.int1_inact_state;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_MD1_CFG, (uint8_t*)&md1_cfg, 1);
+
+ if (ret == 0)
+ {
+ md1_cfg.int1_timer = val.int1_timer;
+ md1_cfg.int1_tilt = val.int1_tilt;
+ md1_cfg.int1_6d = val.int1_6d;
+ md1_cfg.int1_double_tap = val.int1_double_tap;
+ md1_cfg.int1_ff = val.int1_ff;
+ md1_cfg.int1_wu = val.int1_wu;
+ md1_cfg.int1_single_tap = val.int1_single_tap;
+ md1_cfg.int1_inact_state = val.int1_inact_state;
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_MD1_CFG, (uint8_t *)&md1_cfg, 1);
}
- if(ret == 0){
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ctrl4_c.den_drdy_int1 = val.den_drdy_int1;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- master_config.drdy_on_int1 = val.den_drdy_int1;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+
+ if (ret == 0)
+ {
+ master_config.drdy_on_int1 = val.den_drdy_int1;
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_MASTER_CONFIG,
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
+
if ((val.int1_6d != 0x00U) ||
(val.int1_ff != 0x00U) ||
(val.int1_wu != 0x00U) ||
(val.int1_single_tap != 0x00U) ||
(val.int1_double_tap != 0x00U) ||
- (val.int1_inact_state != 0x00U)||
+ (val.int1_inact_state != 0x00U) ||
(md2_cfg.int2_6d != 0x00U) ||
(md2_cfg.int2_ff != 0x00U) ||
(md2_cfg.int2_wu != 0x00U) ||
(md2_cfg.int2_single_tap != 0x00U) ||
(md2_cfg.int2_double_tap != 0x00U) ||
- (md2_cfg.int2_inact_state!= 0x00U) ){
+ (md2_cfg.int2_inact_state != 0x00U))
+ {
tap_cfg.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
tap_cfg.interrupts_enable = PROPERTY_DISABLE;
}
}
- if(ret == 0){
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -3319,11 +3859,12 @@ int32_t lsm6dsm_pin_int1_route_get(stmdev_ctx_t *ctx,
lsm6dsm_int1_ctrl_t int1_ctrl;
lsm6dsm_md1_cfg_t md1_cfg;
lsm6dsm_ctrl4_c_t ctrl4_c;
-
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
+
+ if (ret == 0)
+ {
val->int1_drdy_xl = int1_ctrl.int1_drdy_xl;
val->int1_drdy_g = int1_ctrl.int1_drdy_g;
val->int1_boot = int1_ctrl.int1_boot;
@@ -3332,27 +3873,30 @@ int32_t lsm6dsm_pin_int1_route_get(stmdev_ctx_t *ctx,
val->int1_full_flag = int1_ctrl.int1_full_flag;
val->int1_sign_mot = int1_ctrl.int1_sign_mot;
val->int1_step_detector = int1_ctrl.int1_step_detector ;
-
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_MD1_CFG, (uint8_t*)&md1_cfg, 1);
- if(ret == 0){
- val->int1_timer = md1_cfg.int1_timer;
- val->int1_tilt = md1_cfg.int1_tilt;
- val->int1_6d = md1_cfg.int1_6d;
- val->int1_double_tap = md1_cfg.int1_double_tap;
- val->int1_ff = md1_cfg.int1_ff;
- val->int1_wu = md1_cfg.int1_wu;
- val->int1_single_tap = md1_cfg.int1_single_tap;
- val->int1_inact_state = md1_cfg.int1_inact_state;
-
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_MD1_CFG, (uint8_t *)&md1_cfg, 1);
+
+ if (ret == 0)
+ {
+ val->int1_timer = md1_cfg.int1_timer;
+ val->int1_tilt = md1_cfg.int1_tilt;
+ val->int1_6d = md1_cfg.int1_6d;
+ val->int1_double_tap = md1_cfg.int1_double_tap;
+ val->int1_ff = md1_cfg.int1_ff;
+ val->int1_wu = md1_cfg.int1_wu;
+ val->int1_single_tap = md1_cfg.int1_single_tap;
+ val->int1_inact_state = md1_cfg.int1_inact_state;
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
val->den_drdy_int1 = ctrl4_c.den_drdy_int1;
ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
val->den_drdy_int1 = master_config.drdy_on_int1;
}
}
}
+
return ret;
}
@@ -3374,9 +3918,10 @@ int32_t lsm6dsm_pin_int2_route_set(stmdev_ctx_t *ctx,
lsm6dsm_tap_cfg_t tap_cfg;
int32_t ret;
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
int2_ctrl.int2_drdy_xl = val.int2_drdy_xl;
int2_ctrl.int2_drdy_g = val.int2_drdy_g;
int2_ctrl.int2_drdy_temp = val.int2_drdy_temp;
@@ -3385,15 +3930,21 @@ int32_t lsm6dsm_pin_int2_route_set(stmdev_ctx_t *ctx,
int2_ctrl.int2_full_flag = val.int2_full_flag;
int2_ctrl.int2_step_count_ov = val.int2_step_count_ov;
int2_ctrl.int2_step_delta = val.int2_step_delta;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
}
- if(ret == 0){
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_MD1_CFG, (uint8_t*)&md1_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_MD1_CFG, (uint8_t *)&md1_cfg, 1);
}
- if(ret == 0){
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_MD2_CFG, (uint8_t*)&md2_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_MD2_CFG, (uint8_t *)&md2_cfg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
md2_cfg.int2_iron = val.int2_iron;
md2_cfg.int2_tilt = val.int2_tilt;
md2_cfg.int2_6d = val.int2_6d;
@@ -3402,19 +3953,26 @@ int32_t lsm6dsm_pin_int2_route_set(stmdev_ctx_t *ctx,
md2_cfg.int2_wu = val.int2_wu;
md2_cfg.int2_single_tap = val.int2_single_tap;
md2_cfg.int2_inact_state = val.int2_inact_state;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_MD2_CFG, (uint8_t*)&md2_cfg, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_MD2_CFG, (uint8_t *)&md2_cfg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_DRDY_PULSE_CFG,
- (uint8_t*)&drdy_pulse_cfg, 1);
+ (uint8_t *)&drdy_pulse_cfg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
drdy_pulse_cfg.int2_wrist_tilt = val.int2_wrist_tilt;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_DRDY_PULSE_CFG,
- (uint8_t*)&drdy_pulse_cfg, 1);
+ (uint8_t *)&drdy_pulse_cfg, 1);
}
- if(ret == 0){
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
+
if ((md1_cfg.int1_6d != 0x00U) ||
(md1_cfg.int1_ff != 0x00U) ||
(md1_cfg.int1_wu != 0x00U) ||
@@ -3426,16 +3984,22 @@ int32_t lsm6dsm_pin_int2_route_set(stmdev_ctx_t *ctx,
(val.int2_wu != 0x00U) ||
(val.int2_single_tap != 0x00U) ||
(val.int2_double_tap != 0x00U) ||
- (val.int2_inact_state!= 0x00U) ){
+ (val.int2_inact_state != 0x00U))
+ {
tap_cfg.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
tap_cfg.interrupts_enable = PROPERTY_DISABLE;
}
}
- if(ret == 0){
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -3448,16 +4012,17 @@ int32_t lsm6dsm_pin_int2_route_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsm_pin_int2_route_get(stmdev_ctx_t *ctx,
-lsm6dsm_int2_route_t *val)
+ lsm6dsm_int2_route_t *val)
{
lsm6dsm_int2_ctrl_t int2_ctrl;
lsm6dsm_md2_cfg_t md2_cfg;
lsm6dsm_drdy_pulse_cfg_t drdy_pulse_cfg;
-
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
+
+ if (ret == 0)
+ {
val->int2_drdy_xl = int2_ctrl.int2_drdy_xl;
val->int2_drdy_g = int2_ctrl.int2_drdy_g;
val->int2_drdy_temp = int2_ctrl.int2_drdy_temp;
@@ -3466,9 +4031,10 @@ lsm6dsm_int2_route_t *val)
val->int2_full_flag = int2_ctrl.int2_full_flag;
val->int2_step_count_ov = int2_ctrl.int2_step_count_ov;
val->int2_step_delta = int2_ctrl.int2_step_delta;
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_MD2_CFG, (uint8_t *)&md2_cfg, 1);
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_MD2_CFG, (uint8_t*)&md2_cfg, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
val->int2_iron = md2_cfg.int2_iron;
val->int2_tilt = md2_cfg.int2_tilt;
val->int2_6d = md2_cfg.int2_6d;
@@ -3477,12 +4043,12 @@ lsm6dsm_int2_route_t *val)
val->int2_wu = md2_cfg.int2_wu;
val->int2_single_tap = md2_cfg.int2_single_tap;
val->int2_inact_state = md2_cfg.int2_inact_state;
-
ret = lsm6dsm_read_reg(ctx, LSM6DSM_DRDY_PULSE_CFG,
- (uint8_t*)&drdy_pulse_cfg, 1);
+ (uint8_t *)&drdy_pulse_cfg, 1);
val->int2_wrist_tilt = drdy_pulse_cfg.int2_wrist_tilt;
}
}
+
return ret;
}
@@ -3499,11 +4065,14 @@ int32_t lsm6dsm_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsm_pp_od_t val)
lsm6dsm_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.pp_od = (uint8_t) val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -3520,14 +4089,18 @@ int32_t lsm6dsm_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsm_pp_od_t *val)
lsm6dsm_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- switch (ctrl3_c.pp_od) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ switch (ctrl3_c.pp_od)
+ {
case LSM6DSM_PUSH_PULL:
*val = LSM6DSM_PUSH_PULL;
break;
+
case LSM6DSM_OPEN_DRAIN:
*val = LSM6DSM_OPEN_DRAIN;
break;
+
default:
*val = LSM6DSM_PUSH_PULL;
break;
@@ -3544,16 +4117,20 @@ int32_t lsm6dsm_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsm_pp_od_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_pin_polarity_set(stmdev_ctx_t *ctx, lsm6dsm_h_lactive_t val)
+int32_t lsm6dsm_pin_polarity_set(stmdev_ctx_t *ctx,
+ lsm6dsm_h_lactive_t val)
{
lsm6dsm_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.h_lactive = (uint8_t) val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -3565,19 +4142,24 @@ int32_t lsm6dsm_pin_polarity_set(stmdev_ctx_t *ctx, lsm6dsm_h_lactive_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_pin_polarity_get(stmdev_ctx_t *ctx, lsm6dsm_h_lactive_t *val)
+int32_t lsm6dsm_pin_polarity_get(stmdev_ctx_t *ctx,
+ lsm6dsm_h_lactive_t *val)
{
lsm6dsm_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- switch (ctrl3_c.h_lactive) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ switch (ctrl3_c.h_lactive)
+ {
case LSM6DSM_ACTIVE_HIGH:
*val = LSM6DSM_ACTIVE_HIGH;
break;
+
case LSM6DSM_ACTIVE_LOW:
*val = LSM6DSM_ACTIVE_LOW;
break;
+
default:
*val = LSM6DSM_ACTIVE_HIGH;
break;
@@ -3599,11 +4181,14 @@ int32_t lsm6dsm_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
ctrl4_c.int2_on_int1 = val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -3620,7 +4205,7 @@ int32_t lsm6dsm_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.int2_on_int1;
return ret;
@@ -3634,16 +4219,20 @@ int32_t lsm6dsm_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_int_notification_set(stmdev_ctx_t *ctx, lsm6dsm_lir_t val)
+int32_t lsm6dsm_int_notification_set(stmdev_ctx_t *ctx,
+ lsm6dsm_lir_t val)
{
lsm6dsm_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
tap_cfg.lir = (uint8_t) val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -3655,19 +4244,24 @@ int32_t lsm6dsm_int_notification_set(stmdev_ctx_t *ctx, lsm6dsm_lir_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_int_notification_get(stmdev_ctx_t *ctx, lsm6dsm_lir_t *val)
+int32_t lsm6dsm_int_notification_get(stmdev_ctx_t *ctx,
+ lsm6dsm_lir_t *val)
{
lsm6dsm_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- switch (tap_cfg.lir) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
+
+ switch (tap_cfg.lir)
+ {
case LSM6DSM_INT_PULSED:
*val = LSM6DSM_INT_PULSED;
break;
+
case LSM6DSM_INT_LATCHED:
*val = LSM6DSM_INT_LATCHED;
break;
+
default:
*val = LSM6DSM_INT_PULSED;
break;
@@ -3702,12 +4296,16 @@ int32_t lsm6dsm_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_wake_up_ths_t wake_up_ths;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_THS, (uint8_t*)&wake_up_ths, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_THS,
+ (uint8_t *)&wake_up_ths, 1);
+
+ if (ret == 0)
+ {
wake_up_ths.wk_ths = val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
}
+
return ret;
}
@@ -3724,7 +4322,8 @@ int32_t lsm6dsm_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_wake_up_ths_t wake_up_ths;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_THS, (uint8_t*)&wake_up_ths, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_THS,
+ (uint8_t *)&wake_up_ths, 1);
*val = wake_up_ths.wk_ths;
return ret;
@@ -3743,12 +4342,16 @@ int32_t lsm6dsm_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_wake_up_dur_t wake_up_dur;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
wake_up_dur.wake_dur = val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -3765,7 +4368,8 @@ int32_t lsm6dsm_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_wake_up_dur_t wake_up_dur;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
*val = wake_up_dur.wake_dur;
return ret;
@@ -3797,11 +4401,14 @@ int32_t lsm6dsm_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
ctrl4_c.sleep = val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -3818,7 +4425,7 @@ int32_t lsm6dsm_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.sleep;
return ret;
@@ -3832,16 +4439,20 @@ int32_t lsm6dsm_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_act_mode_set(stmdev_ctx_t *ctx, lsm6dsm_inact_en_t val)
+int32_t lsm6dsm_act_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsm_inact_en_t val)
{
lsm6dsm_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
tap_cfg.inact_en = (uint8_t) val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -3853,25 +4464,32 @@ int32_t lsm6dsm_act_mode_set(stmdev_ctx_t *ctx, lsm6dsm_inact_en_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_act_mode_get(stmdev_ctx_t *ctx, lsm6dsm_inact_en_t *val)
+int32_t lsm6dsm_act_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsm_inact_en_t *val)
{
lsm6dsm_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- switch (tap_cfg.inact_en) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
+
+ switch (tap_cfg.inact_en)
+ {
case LSM6DSM_PROPERTY_DISABLE:
*val = LSM6DSM_PROPERTY_DISABLE;
break;
+
case LSM6DSM_XL_12Hz5_GY_NOT_AFFECTED:
*val = LSM6DSM_XL_12Hz5_GY_NOT_AFFECTED;
break;
+
case LSM6DSM_XL_12Hz5_GY_SLEEP:
*val = LSM6DSM_XL_12Hz5_GY_SLEEP;
break;
+
case LSM6DSM_XL_12Hz5_GY_PD:
*val = LSM6DSM_XL_12Hz5_GY_PD;
break;
+
default:
*val = LSM6DSM_PROPERTY_DISABLE;
break;
@@ -3893,12 +4511,16 @@ int32_t lsm6dsm_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_wake_up_dur_t wake_up_dur;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
wake_up_dur.sleep_dur = val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -3915,7 +4537,8 @@ int32_t lsm6dsm_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_wake_up_dur_t wake_up_dur;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
*val = wake_up_dur.sleep_dur;
return ret;
@@ -3945,7 +4568,9 @@ int32_t lsm6dsm_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t lsm6dsm_tap_src_get(stmdev_ctx_t *ctx, lsm6dsm_tap_src_t *val)
{
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_SRC, (uint8_t*) val, 1);
+
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_SRC, (uint8_t *) val, 1);
+
return ret;
}
@@ -3961,11 +4586,14 @@ int32_t lsm6dsm_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
tap_cfg.tap_z_en = val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -3977,12 +4605,13 @@ int32_t lsm6dsm_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsm_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsm_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
*val = tap_cfg.tap_z_en;
return ret;
@@ -4001,11 +4630,14 @@ int32_t lsm6dsm_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
tap_cfg.tap_y_en = val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -4017,12 +4649,13 @@ int32_t lsm6dsm_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsm_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsm_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
*val = tap_cfg.tap_y_en;
return ret;
@@ -4041,11 +4674,14 @@ int32_t lsm6dsm_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t*)&tap_cfg, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
+
+ if (ret == 0)
+ {
tap_cfg.tap_x_en = val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
}
+
return ret;
}
@@ -4057,12 +4693,13 @@ int32_t lsm6dsm_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsm_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsm_tap_cfg_t tap_cfg;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t*)&tap_cfg, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
*val = tap_cfg.tap_x_en;
return ret;
@@ -4081,12 +4718,16 @@ int32_t lsm6dsm_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_tap_ths_6d_t tap_ths_6d;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_THS_6D,
+ (uint8_t *)&tap_ths_6d, 1);
+
+ if (ret == 0)
+ {
tap_ths_6d.tap_ths = val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
+ (uint8_t *)&tap_ths_6d, 1);
}
+
return ret;
}
@@ -4103,7 +4744,8 @@ int32_t lsm6dsm_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_tap_ths_6d_t tap_ths_6d;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_THS_6D,
+ (uint8_t *)&tap_ths_6d, 1);
*val = tap_ths_6d.tap_ths;
return ret;
@@ -4127,11 +4769,14 @@ int32_t lsm6dsm_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t*)&int_dur2, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t *)&int_dur2, 1);
+
+ if (ret == 0)
+ {
int_dur2.shock = val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t *)&int_dur2, 1);
}
+
return ret;
}
@@ -4153,7 +4798,7 @@ int32_t lsm6dsm_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t *)&int_dur2, 1);
*val = int_dur2.shock;
return ret;
@@ -4177,11 +4822,14 @@ int32_t lsm6dsm_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t*)&int_dur2, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t *)&int_dur2, 1);
+
+ if (ret == 0)
+ {
int_dur2.quiet = val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t *)&int_dur2, 1);
}
+
return ret;
}
@@ -4203,7 +4851,7 @@ int32_t lsm6dsm_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t *)&int_dur2, 1);
*val = int_dur2.quiet;
return ret;
@@ -4228,11 +4876,14 @@ int32_t lsm6dsm_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t*)&int_dur2, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t *)&int_dur2, 1);
+
+ if (ret == 0)
+ {
int_dur2.dur = val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t *)&int_dur2, 1);
}
+
return ret;
}
@@ -4255,7 +4906,7 @@ int32_t lsm6dsm_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t *)&int_dur2, 1);
*val = int_dur2.dur;
return ret;
@@ -4276,12 +4927,16 @@ int32_t lsm6dsm_tap_mode_set(stmdev_ctx_t *ctx,
lsm6dsm_wake_up_ths_t wake_up_ths;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_THS, (uint8_t*)&wake_up_ths, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_THS,
+ (uint8_t *)&wake_up_ths, 1);
+
+ if (ret == 0)
+ {
wake_up_ths.single_double_tap = (uint8_t) val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
}
+
return ret;
}
@@ -4300,14 +4955,19 @@ int32_t lsm6dsm_tap_mode_get(stmdev_ctx_t *ctx,
lsm6dsm_wake_up_ths_t wake_up_ths;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_THS, (uint8_t*)&wake_up_ths, 1);
- switch (wake_up_ths.single_double_tap) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_THS,
+ (uint8_t *)&wake_up_ths, 1);
+
+ switch (wake_up_ths.single_double_tap)
+ {
case LSM6DSM_ONLY_SINGLE:
*val = LSM6DSM_ONLY_SINGLE;
break;
+
case LSM6DSM_BOTH_SINGLE_DOUBLE:
*val = LSM6DSM_BOTH_SINGLE_DOUBLE;
break;
+
default:
*val = LSM6DSM_ONLY_SINGLE;
break;
@@ -4344,11 +5004,14 @@ int32_t lsm6dsm_6d_feed_data_set(stmdev_ctx_t *ctx,
lsm6dsm_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
ctrl8_xl.low_pass_on_6d = (uint8_t) val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -4366,14 +5029,18 @@ int32_t lsm6dsm_6d_feed_data_get(stmdev_ctx_t *ctx,
lsm6dsm_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- switch (ctrl8_xl.low_pass_on_6d) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ switch (ctrl8_xl.low_pass_on_6d)
+ {
case LSM6DSM_ODR_DIV_2_FEED:
*val = LSM6DSM_ODR_DIV_2_FEED;
break;
+
case LSM6DSM_LPF2_FEED:
*val = LSM6DSM_LPF2_FEED;
break;
+
default:
*val = LSM6DSM_ODR_DIV_2_FEED;
break;
@@ -4390,16 +5057,22 @@ int32_t lsm6dsm_6d_feed_data_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_6d_threshold_set(stmdev_ctx_t *ctx, lsm6dsm_sixd_ths_t val)
+int32_t lsm6dsm_6d_threshold_set(stmdev_ctx_t *ctx,
+ lsm6dsm_sixd_ths_t val)
{
lsm6dsm_tap_ths_6d_t tap_ths_6d;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_THS_6D,
+ (uint8_t *)&tap_ths_6d, 1);
+
+ if (ret == 0)
+ {
tap_ths_6d.sixd_ths = (uint8_t) val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_THS_6D,
+ (uint8_t *)&tap_ths_6d, 1);
}
+
return ret;
}
@@ -4411,25 +5084,33 @@ int32_t lsm6dsm_6d_threshold_set(stmdev_ctx_t *ctx, lsm6dsm_sixd_ths_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_6d_threshold_get(stmdev_ctx_t *ctx, lsm6dsm_sixd_ths_t *val)
+int32_t lsm6dsm_6d_threshold_get(stmdev_ctx_t *ctx,
+ lsm6dsm_sixd_ths_t *val)
{
lsm6dsm_tap_ths_6d_t tap_ths_6d;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1);
- switch (tap_ths_6d.sixd_ths) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_THS_6D,
+ (uint8_t *)&tap_ths_6d, 1);
+
+ switch (tap_ths_6d.sixd_ths)
+ {
case LSM6DSM_DEG_80:
*val = LSM6DSM_DEG_80;
break;
+
case LSM6DSM_DEG_70:
*val = LSM6DSM_DEG_70;
break;
+
case LSM6DSM_DEG_60:
*val = LSM6DSM_DEG_60;
break;
+
case LSM6DSM_DEG_50:
*val = LSM6DSM_DEG_50;
break;
+
default:
*val = LSM6DSM_DEG_80;
break;
@@ -4451,12 +5132,16 @@ int32_t lsm6dsm_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_tap_ths_6d_t tap_ths_6d;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_THS_6D,
+ (uint8_t *)&tap_ths_6d, 1);
+
+ if (ret == 0)
+ {
tap_ths_6d.d4d_en = val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
+ (uint8_t *)&tap_ths_6d, 1);
}
+
return ret;
}
@@ -4473,7 +5158,8 @@ int32_t lsm6dsm_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_tap_ths_6d_t tap_ths_6d;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_THS_6D,
+ (uint8_t *)&tap_ths_6d, 1);
*val = tap_ths_6d.d4d_en;
return ret;
@@ -4506,20 +5192,27 @@ int32_t lsm6dsm_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_free_fall_t free_fall;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_FREE_FALL, (uint8_t*)&free_fall, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_FREE_FALL, (uint8_t *)&free_fall, 1);
+
+ if (ret == 0)
+ {
free_fall.ff_dur = (val & 0x1FU);
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_FREE_FALL, (uint8_t*)&free_fall, 1);
- if(ret == 0){
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_FREE_FALL, (uint8_t *)&free_fall, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
wake_up_dur.ff_dur = (val & 0x20U) >> 5;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
}
}
+
return ret;
}
@@ -4537,10 +5230,14 @@ int32_t lsm6dsm_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_free_fall_t free_fall;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_FREE_FALL, (uint8_t*)&free_fall, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_FREE_FALL, (uint8_t *)&free_fall, 1);
}
+
*val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
return ret;
@@ -4554,16 +5251,20 @@ int32_t lsm6dsm_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_ff_threshold_set(stmdev_ctx_t *ctx, lsm6dsm_ff_ths_t val)
+int32_t lsm6dsm_ff_threshold_set(stmdev_ctx_t *ctx,
+ lsm6dsm_ff_ths_t val)
{
lsm6dsm_free_fall_t free_fall;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_FREE_FALL, (uint8_t*)&free_fall, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_FREE_FALL, (uint8_t *)&free_fall, 1);
+
+ if (ret == 0)
+ {
free_fall.ff_ths = (uint8_t) val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_FREE_FALL, (uint8_t*)&free_fall, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_FREE_FALL, (uint8_t *)&free_fall, 1);
}
+
return ret;
}
@@ -4575,37 +5276,48 @@ int32_t lsm6dsm_ff_threshold_set(stmdev_ctx_t *ctx, lsm6dsm_ff_ths_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_ff_threshold_get(stmdev_ctx_t *ctx, lsm6dsm_ff_ths_t *val)
+int32_t lsm6dsm_ff_threshold_get(stmdev_ctx_t *ctx,
+ lsm6dsm_ff_ths_t *val)
{
lsm6dsm_free_fall_t free_fall;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_FREE_FALL, (uint8_t*)&free_fall, 1);
- switch (free_fall.ff_ths) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_FREE_FALL, (uint8_t *)&free_fall, 1);
+
+ switch (free_fall.ff_ths)
+ {
case LSM6DSM_FF_TSH_156mg:
*val = LSM6DSM_FF_TSH_156mg;
break;
+
case LSM6DSM_FF_TSH_219mg:
*val = LSM6DSM_FF_TSH_219mg;
break;
+
case LSM6DSM_FF_TSH_250mg:
*val = LSM6DSM_FF_TSH_250mg;
break;
+
case LSM6DSM_FF_TSH_312mg:
*val = LSM6DSM_FF_TSH_312mg;
break;
+
case LSM6DSM_FF_TSH_344mg:
*val = LSM6DSM_FF_TSH_344mg;
break;
+
case LSM6DSM_FF_TSH_406mg:
*val = LSM6DSM_FF_TSH_406mg;
break;
+
case LSM6DSM_FF_TSH_469mg:
*val = LSM6DSM_FF_TSH_469mg;
break;
+
case LSM6DSM_FF_TSH_500mg:
*val = LSM6DSM_FF_TSH_500mg;
break;
+
default:
*val = LSM6DSM_FF_TSH_156mg;
break;
@@ -4641,16 +5353,23 @@ int32_t lsm6dsm_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
lsm6dsm_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
- fifo_ctrl1.fth = (uint8_t) (0x00FFU & val);
- fifo_ctrl2.fth = (uint8_t) (( 0x0700U & val ) >> 8);
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl1.fth = (uint8_t)(0x00FFU & val);
+ fifo_ctrl2.fth = (uint8_t)((0x0700U & val) >> 8);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL1,
+ (uint8_t *)&fifo_ctrl1, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
}
+
return ret;
}
@@ -4668,10 +5387,15 @@ int32_t lsm6dsm_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
lsm6dsm_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1);
- if(ret == 0){
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL1,
+ (uint8_t *)&fifo_ctrl1, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
}
+
*val = ((uint16_t)fifo_ctrl2.fth << 8) + (uint16_t)fifo_ctrl1.fth;
return ret;
@@ -4694,12 +5418,14 @@ int32_t lsm6dsm_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
int32_t ret;
ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_STATUS1,
- (uint8_t*)&fifo_status1, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_status1, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
- *val = ( (uint16_t) fifo_status2.diff_fifo << 8) +
- (uint16_t) fifo_status1.diff_fifo;
+ (uint8_t *)&fifo_status2, 1);
+ *val = ((uint16_t) fifo_status2.diff_fifo << 8) +
+ (uint16_t) fifo_status1.diff_fifo;
}
return ret;
@@ -4718,7 +5444,8 @@ int32_t lsm6dsm_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_fifo_status2_t fifo_status2;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_STATUS2, (uint8_t*)&fifo_status2, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_STATUS2,
+ (uint8_t *)&fifo_status2, 1);
*val = fifo_status2.waterm;
return ret;
@@ -4737,7 +5464,8 @@ int32_t lsm6dsm_fifo_over_run_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_fifo_status2_t fifo_status2;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_STATUS2, (uint8_t*)&fifo_status2, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_STATUS2,
+ (uint8_t *)&fifo_status2, 1);
*val = fifo_status2.over_run;
return ret;
@@ -4759,13 +5487,16 @@ int32_t lsm6dsm_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val)
int32_t ret;
ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_STATUS3,
- (uint8_t*)&fifo_status3, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_status3, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_STATUS4,
- (uint8_t*)&fifo_status4, 1);
- *val = ( (uint16_t)fifo_status4.fifo_pattern << 8) +
- fifo_status3.fifo_pattern;
+ (uint8_t *)&fifo_status4, 1);
+ *val = ((uint16_t)fifo_status4.fifo_pattern << 8) +
+ fifo_status3.fifo_pattern;
}
+
return ret;
}
@@ -4782,11 +5513,14 @@ int32_t lsm6dsm_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl2.fifo_temp_en = val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
return ret;
@@ -4805,7 +5539,8 @@ int32_t lsm6dsm_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
*val = fifo_ctrl2.fifo_temp_en;
return ret;
@@ -4827,18 +5562,25 @@ int32_t lsm6dsm_fifo_write_trigger_set(stmdev_ctx_t *ctx,
lsm6dsm_master_config_t master_config;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl2.timer_pedo_fifo_drdy = (uint8_t)val & 0x01U;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
master_config.data_valid_sel_fifo = (((uint8_t)val & 0x02U) >> 1);
ret = lsm6dsm_write_reg(ctx, LSM6DSM_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
}
}
@@ -4862,22 +5604,29 @@ int32_t lsm6dsm_fifo_write_trigger_get(stmdev_ctx_t *ctx,
lsm6dsm_master_config_t master_config;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
- switch ( ( fifo_ctrl2.timer_pedo_fifo_drdy << 1 ) +
- fifo_ctrl2. timer_pedo_fifo_drdy ) {
+ switch ((fifo_ctrl2.timer_pedo_fifo_drdy << 1) +
+ fifo_ctrl2. timer_pedo_fifo_drdy)
+ {
case LSM6DSM_TRG_XL_GY_DRDY:
*val = LSM6DSM_TRG_XL_GY_DRDY;
break;
+
case LSM6DSM_TRG_STEP_DETECT:
*val = LSM6DSM_TRG_STEP_DETECT;
break;
+
case LSM6DSM_TRG_SH_DRDY:
*val = LSM6DSM_TRG_SH_DRDY;
break;
+
default:
*val = LSM6DSM_TRG_XL_GY_DRDY;
break;
@@ -4902,12 +5651,16 @@ int32_t lsm6dsm_fifo_pedo_and_timestamp_batch_set(stmdev_ctx_t *ctx,
lsm6dsm_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl2.timer_pedo_fifo_en = val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
+
return ret;
}
@@ -4926,7 +5679,8 @@ int32_t lsm6dsm_fifo_pedo_and_timestamp_batch_get(stmdev_ctx_t *ctx,
lsm6dsm_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
*val = fifo_ctrl2.timer_pedo_fifo_en;
return ret;
@@ -4947,12 +5701,16 @@ int32_t lsm6dsm_fifo_xl_batch_set(stmdev_ctx_t *ctx,
lsm6dsm_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL3, (uint8_t*)&fifo_ctrl3, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL3,
+ (uint8_t *)&fifo_ctrl3, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl3.dec_fifo_xl = (uint8_t)val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
+ (uint8_t *)&fifo_ctrl3, 1);
}
+
return ret;
}
@@ -4971,32 +5729,43 @@ int32_t lsm6dsm_fifo_xl_batch_get(stmdev_ctx_t *ctx,
lsm6dsm_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL3, (uint8_t*)&fifo_ctrl3, 1);
- switch (fifo_ctrl3.dec_fifo_xl) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL3,
+ (uint8_t *)&fifo_ctrl3, 1);
+
+ switch (fifo_ctrl3.dec_fifo_xl)
+ {
case LSM6DSM_FIFO_XL_DISABLE:
*val = LSM6DSM_FIFO_XL_DISABLE;
break;
+
case LSM6DSM_FIFO_XL_NO_DEC:
*val = LSM6DSM_FIFO_XL_NO_DEC;
break;
+
case LSM6DSM_FIFO_XL_DEC_2:
*val = LSM6DSM_FIFO_XL_DEC_2;
break;
+
case LSM6DSM_FIFO_XL_DEC_3:
*val = LSM6DSM_FIFO_XL_DEC_3;
break;
+
case LSM6DSM_FIFO_XL_DEC_4:
*val = LSM6DSM_FIFO_XL_DEC_4;
break;
+
case LSM6DSM_FIFO_XL_DEC_8:
*val = LSM6DSM_FIFO_XL_DEC_8;
break;
+
case LSM6DSM_FIFO_XL_DEC_16:
*val = LSM6DSM_FIFO_XL_DEC_16;
break;
+
case LSM6DSM_FIFO_XL_DEC_32:
*val = LSM6DSM_FIFO_XL_DEC_32;
break;
+
default:
*val = LSM6DSM_FIFO_XL_DISABLE;
break;
@@ -5020,11 +5789,16 @@ int32_t lsm6dsm_fifo_gy_batch_set(stmdev_ctx_t *ctx,
lsm6dsm_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL3, (uint8_t*)&fifo_ctrl3, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL3,
+ (uint8_t *)&fifo_ctrl3, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl3.dec_fifo_gyro = (uint8_t)val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL3, (uint8_t*)&fifo_ctrl3, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL3,
+ (uint8_t *)&fifo_ctrl3, 1);
}
+
return ret;
}
@@ -5043,32 +5817,43 @@ int32_t lsm6dsm_fifo_gy_batch_get(stmdev_ctx_t *ctx,
lsm6dsm_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL3, (uint8_t*)&fifo_ctrl3, 1);
- switch (fifo_ctrl3.dec_fifo_gyro) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL3,
+ (uint8_t *)&fifo_ctrl3, 1);
+
+ switch (fifo_ctrl3.dec_fifo_gyro)
+ {
case LSM6DSM_FIFO_GY_DISABLE:
*val = LSM6DSM_FIFO_GY_DISABLE;
break;
+
case LSM6DSM_FIFO_GY_NO_DEC:
*val = LSM6DSM_FIFO_GY_NO_DEC;
break;
+
case LSM6DSM_FIFO_GY_DEC_2:
*val = LSM6DSM_FIFO_GY_DEC_2;
break;
+
case LSM6DSM_FIFO_GY_DEC_3:
*val = LSM6DSM_FIFO_GY_DEC_3;
break;
+
case LSM6DSM_FIFO_GY_DEC_4:
*val = LSM6DSM_FIFO_GY_DEC_4;
break;
+
case LSM6DSM_FIFO_GY_DEC_8:
*val = LSM6DSM_FIFO_GY_DEC_8;
break;
+
case LSM6DSM_FIFO_GY_DEC_16:
*val = LSM6DSM_FIFO_GY_DEC_16;
break;
+
case LSM6DSM_FIFO_GY_DEC_32:
*val = LSM6DSM_FIFO_GY_DEC_32;
break;
+
default:
*val = LSM6DSM_FIFO_GY_DISABLE;
break;
@@ -5092,12 +5877,16 @@ int32_t lsm6dsm_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx,
lsm6dsm_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl4.dec_ds3_fifo = (uint8_t)val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -5116,32 +5905,43 @@ int32_t lsm6dsm_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx,
lsm6dsm_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
- switch (fifo_ctrl4.dec_ds3_fifo) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ switch (fifo_ctrl4.dec_ds3_fifo)
+ {
case LSM6DSM_FIFO_DS3_DISABLE:
*val = LSM6DSM_FIFO_DS3_DISABLE;
break;
+
case LSM6DSM_FIFO_DS3_NO_DEC:
*val = LSM6DSM_FIFO_DS3_NO_DEC;
break;
+
case LSM6DSM_FIFO_DS3_DEC_2:
*val = LSM6DSM_FIFO_DS3_DEC_2;
break;
+
case LSM6DSM_FIFO_DS3_DEC_3:
*val = LSM6DSM_FIFO_DS3_DEC_3;
break;
+
case LSM6DSM_FIFO_DS3_DEC_4:
*val = LSM6DSM_FIFO_DS3_DEC_4;
break;
+
case LSM6DSM_FIFO_DS3_DEC_8:
*val = LSM6DSM_FIFO_DS3_DEC_8;
break;
+
case LSM6DSM_FIFO_DS3_DEC_16:
*val = LSM6DSM_FIFO_DS3_DEC_16;
break;
+
case LSM6DSM_FIFO_DS3_DEC_32:
*val = LSM6DSM_FIFO_DS3_DEC_32;
break;
+
default:
*val = LSM6DSM_FIFO_DS3_DISABLE;
break;
@@ -5165,12 +5965,16 @@ int32_t lsm6dsm_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx,
lsm6dsm_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl4.dec_ds4_fifo = (uint8_t)val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -5189,32 +5993,43 @@ int32_t lsm6dsm_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx,
lsm6dsm_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
- switch (fifo_ctrl4.dec_ds4_fifo) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ switch (fifo_ctrl4.dec_ds4_fifo)
+ {
case LSM6DSM_FIFO_DS4_DISABLE:
*val = LSM6DSM_FIFO_DS4_DISABLE;
break;
+
case LSM6DSM_FIFO_DS4_NO_DEC:
*val = LSM6DSM_FIFO_DS4_NO_DEC;
break;
+
case LSM6DSM_FIFO_DS4_DEC_2:
*val = LSM6DSM_FIFO_DS4_DEC_2;
break;
+
case LSM6DSM_FIFO_DS4_DEC_3:
*val = LSM6DSM_FIFO_DS4_DEC_3;
break;
+
case LSM6DSM_FIFO_DS4_DEC_4:
*val = LSM6DSM_FIFO_DS4_DEC_4;
break;
+
case LSM6DSM_FIFO_DS4_DEC_8:
*val = LSM6DSM_FIFO_DS4_DEC_8;
break;
+
case LSM6DSM_FIFO_DS4_DEC_16:
*val = LSM6DSM_FIFO_DS4_DEC_16;
break;
+
case LSM6DSM_FIFO_DS4_DEC_32:
*val = LSM6DSM_FIFO_DS4_DEC_32;
break;
+
default:
*val = LSM6DSM_FIFO_DS4_DISABLE;
break;
@@ -5231,16 +6046,22 @@ int32_t lsm6dsm_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dsm_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dsm_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl4.only_high_data = val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -5252,12 +6073,14 @@ int32_t lsm6dsm_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsm_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsm_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
*val = fifo_ctrl4.only_high_data;
return ret;
@@ -5277,11 +6100,16 @@ int32_t lsm6dsm_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl4.stop_on_fth = val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -5299,7 +6127,8 @@ int32_t lsm6dsm_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4,
+ (uint8_t *)&fifo_ctrl4, 1);
*val = fifo_ctrl4.stop_on_fth;
return ret;
@@ -5313,16 +6142,22 @@ int32_t lsm6dsm_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_fifo_mode_set(stmdev_ctx_t *ctx, lsm6dsm_fifo_mode_t val)
+int32_t lsm6dsm_fifo_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsm_fifo_mode_t val)
{
lsm6dsm_fifo_ctrl5_t fifo_ctrl5;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL5,
+ (uint8_t *)&fifo_ctrl5, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl5.fifo_mode = (uint8_t)val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL5,
+ (uint8_t *)&fifo_ctrl5, 1);
}
+
return ret;
}
@@ -5334,28 +6169,37 @@ int32_t lsm6dsm_fifo_mode_set(stmdev_ctx_t *ctx, lsm6dsm_fifo_mode_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_fifo_mode_get(stmdev_ctx_t *ctx, lsm6dsm_fifo_mode_t *val)
+int32_t lsm6dsm_fifo_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsm_fifo_mode_t *val)
{
lsm6dsm_fifo_ctrl5_t fifo_ctrl5;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1);
- switch (fifo_ctrl5.fifo_mode) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL5,
+ (uint8_t *)&fifo_ctrl5, 1);
+
+ switch (fifo_ctrl5.fifo_mode)
+ {
case LSM6DSM_BYPASS_MODE:
*val = LSM6DSM_BYPASS_MODE;
break;
+
case LSM6DSM_FIFO_MODE:
*val = LSM6DSM_FIFO_MODE;
break;
+
case LSM6DSM_STREAM_TO_FIFO_MODE:
*val = LSM6DSM_STREAM_TO_FIFO_MODE;
break;
+
case LSM6DSM_BYPASS_TO_STREAM_MODE:
*val = LSM6DSM_BYPASS_TO_STREAM_MODE;
break;
+
case LSM6DSM_STREAM_MODE:
*val = LSM6DSM_STREAM_MODE;
break;
+
default:
*val = LSM6DSM_BYPASS_MODE;
break;
@@ -5372,16 +6216,22 @@ int32_t lsm6dsm_fifo_mode_get(stmdev_ctx_t *ctx, lsm6dsm_fifo_mode_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_fifo_data_rate_set(stmdev_ctx_t *ctx, lsm6dsm_odr_fifo_t val)
+int32_t lsm6dsm_fifo_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dsm_odr_fifo_t val)
{
lsm6dsm_fifo_ctrl5_t fifo_ctrl5;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL5,
+ (uint8_t *)&fifo_ctrl5, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl5.odr_fifo = (uint8_t)val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL5,
+ (uint8_t *)&fifo_ctrl5, 1);
}
+
return ret;
}
@@ -5393,46 +6243,61 @@ int32_t lsm6dsm_fifo_data_rate_set(stmdev_ctx_t *ctx, lsm6dsm_odr_fifo_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_fifo_data_rate_get(stmdev_ctx_t *ctx, lsm6dsm_odr_fifo_t *val)
+int32_t lsm6dsm_fifo_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dsm_odr_fifo_t *val)
{
lsm6dsm_fifo_ctrl5_t fifo_ctrl5;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1);
- switch (fifo_ctrl5.odr_fifo) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL5,
+ (uint8_t *)&fifo_ctrl5, 1);
+
+ switch (fifo_ctrl5.odr_fifo)
+ {
case LSM6DSM_FIFO_DISABLE:
*val = LSM6DSM_FIFO_DISABLE;
break;
+
case LSM6DSM_FIFO_12Hz5:
*val = LSM6DSM_FIFO_12Hz5;
break;
+
case LSM6DSM_FIFO_26Hz:
*val = LSM6DSM_FIFO_26Hz;
break;
+
case LSM6DSM_FIFO_52Hz:
*val = LSM6DSM_FIFO_52Hz;
break;
+
case LSM6DSM_FIFO_104Hz:
*val = LSM6DSM_FIFO_104Hz;
break;
+
case LSM6DSM_FIFO_208Hz:
*val = LSM6DSM_FIFO_208Hz;
break;
+
case LSM6DSM_FIFO_416Hz:
*val = LSM6DSM_FIFO_416Hz;
break;
+
case LSM6DSM_FIFO_833Hz:
*val = LSM6DSM_FIFO_833Hz;
break;
+
case LSM6DSM_FIFO_1k66Hz:
*val = LSM6DSM_FIFO_1k66Hz;
break;
+
case LSM6DSM_FIFO_3k33Hz:
*val = LSM6DSM_FIFO_3k33Hz;
break;
+
case LSM6DSM_FIFO_6k66Hz:
*val = LSM6DSM_FIFO_6k66Hz;
break;
+
default:
*val = LSM6DSM_FIFO_DISABLE;
break;
@@ -5462,16 +6327,20 @@ int32_t lsm6dsm_fifo_data_rate_get(stmdev_ctx_t *ctx, lsm6dsm_odr_fifo_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
- int32_t lsm6dsm_den_polarity_set(stmdev_ctx_t *ctx, lsm6dsm_den_lh_t val)
+int32_t lsm6dsm_den_polarity_set(stmdev_ctx_t *ctx,
+ lsm6dsm_den_lh_t val)
{
lsm6dsm_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ if (ret == 0)
+ {
ctrl5_c.den_lh = (uint8_t)val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -5483,19 +6352,24 @@ int32_t lsm6dsm_fifo_data_rate_get(stmdev_ctx_t *ctx, lsm6dsm_odr_fifo_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_den_polarity_get(stmdev_ctx_t *ctx, lsm6dsm_den_lh_t *val)
+int32_t lsm6dsm_den_polarity_get(stmdev_ctx_t *ctx,
+ lsm6dsm_den_lh_t *val)
{
lsm6dsm_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- switch (ctrl5_c.den_lh) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ switch (ctrl5_c.den_lh)
+ {
case LSM6DSM_DEN_ACT_LOW:
*val = LSM6DSM_DEN_ACT_LOW;
break;
+
case LSM6DSM_DEN_ACT_HIGH:
*val = LSM6DSM_DEN_ACT_HIGH;
break;
+
default:
*val = LSM6DSM_DEN_ACT_LOW;
break;
@@ -5512,16 +6386,20 @@ int32_t lsm6dsm_den_polarity_get(stmdev_ctx_t *ctx, lsm6dsm_den_lh_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_den_mode_set(stmdev_ctx_t *ctx, lsm6dsm_den_mode_t val)
+int32_t lsm6dsm_den_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsm_den_mode_t val)
{
lsm6dsm_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
ctrl6_c.den_mode = (uint8_t)val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -5533,25 +6411,32 @@ int32_t lsm6dsm_den_mode_set(stmdev_ctx_t *ctx, lsm6dsm_den_mode_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_den_mode_get(stmdev_ctx_t *ctx, lsm6dsm_den_mode_t *val)
+int32_t lsm6dsm_den_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsm_den_mode_t *val)
{
lsm6dsm_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- switch (ctrl6_c.den_mode) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ switch (ctrl6_c.den_mode)
+ {
case LSM6DSM_DEN_DISABLE:
*val = LSM6DSM_DEN_DISABLE;
break;
+
case LSM6DSM_LEVEL_LETCHED:
*val = LSM6DSM_LEVEL_LETCHED;
break;
+
case LSM6DSM_LEVEL_TRIGGER:
*val = LSM6DSM_LEVEL_TRIGGER;
break;
+
case LSM6DSM_EDGE_TRIGGER:
*val = LSM6DSM_EDGE_TRIGGER;
break;
+
default:
*val = LSM6DSM_DEN_DISABLE;
break;
@@ -5569,24 +6454,32 @@ int32_t lsm6dsm_den_mode_get(stmdev_ctx_t *ctx, lsm6dsm_den_mode_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_den_enable_set(stmdev_ctx_t *ctx, lsm6dsm_den_xl_en_t val)
+int32_t lsm6dsm_den_enable_set(stmdev_ctx_t *ctx,
+ lsm6dsm_den_xl_en_t val)
{
lsm6dsm_ctrl4_c_t ctrl4_c;
lsm6dsm_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
ctrl9_xl.den_xl_g = (uint8_t)val & 0x01U;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
ctrl4_c.den_xl_en = (uint8_t)val & 0x02U;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
}
}
+
return ret;
}
@@ -5599,25 +6492,33 @@ int32_t lsm6dsm_den_enable_set(stmdev_ctx_t *ctx, lsm6dsm_den_xl_en_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_den_enable_get(stmdev_ctx_t *ctx, lsm6dsm_den_xl_en_t *val)
+int32_t lsm6dsm_den_enable_get(stmdev_ctx_t *ctx,
+ lsm6dsm_den_xl_en_t *val)
{
lsm6dsm_ctrl4_c_t ctrl4_c;
lsm6dsm_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- switch ( ( ctrl4_c.den_xl_en << 1) + ctrl9_xl.den_xl_g ) {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ switch ((ctrl4_c.den_xl_en << 1) + ctrl9_xl.den_xl_g)
+ {
case LSM6DSM_STAMP_IN_GY_DATA:
*val = LSM6DSM_STAMP_IN_GY_DATA;
break;
+
case LSM6DSM_STAMP_IN_XL_DATA:
*val = LSM6DSM_STAMP_IN_XL_DATA;
break;
+
case LSM6DSM_STAMP_IN_GY_XL_DATA:
*val = LSM6DSM_STAMP_IN_GY_XL_DATA;
break;
+
default:
*val = LSM6DSM_STAMP_IN_GY_DATA;
break;
@@ -5640,11 +6541,14 @@ int32_t lsm6dsm_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
ctrl9_xl.den_z = val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -5661,7 +6565,7 @@ int32_t lsm6dsm_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
*val = ctrl9_xl.den_z;
return ret;
@@ -5680,11 +6584,14 @@ int32_t lsm6dsm_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
ctrl9_xl.den_y = val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -5701,7 +6608,7 @@ int32_t lsm6dsm_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
*val = ctrl9_xl.den_y;
return ret;
@@ -5720,11 +6627,14 @@ int32_t lsm6dsm_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
ctrl9_xl.den_x = val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -5741,7 +6651,7 @@ int32_t lsm6dsm_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
*val = ctrl9_xl.den_x;
return ret;
@@ -5772,11 +6682,14 @@ int32_t lsm6dsm_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
ctrl10_c.pedo_rst_step = val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
}
+
return ret;
}
@@ -5793,7 +6706,7 @@ int32_t lsm6dsm_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
*val = ctrl10_c.pedo_rst_step;
return ret;
@@ -5812,13 +6725,18 @@ int32_t lsm6dsm_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
ctrl10_c.pedo_en = val;
- if (val != 0x00U) {
+
+ if (val != 0x00U)
+ {
ctrl10_c.func_en = val;
}
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
}
return ret;
@@ -5837,7 +6755,7 @@ int32_t lsm6dsm_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
*val = ctrl10_c.pedo_en;
return ret;
@@ -5858,18 +6776,25 @@ int32_t lsm6dsm_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_CONFIG_PEDO_THS_MIN,
- (uint8_t*)&config_pedo_ths_min, 1);
- if(ret == 0){
- config_pedo_ths_min.ths_min = val;
+ (uint8_t *)&config_pedo_ths_min, 1);
+
+ if (ret == 0)
+ {
+ config_pedo_ths_min.ths_min = val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_CONFIG_PEDO_THS_MIN,
- (uint8_t*)&config_pedo_ths_min, 1);
- if(ret == 0){
- ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
- }
+ (uint8_t *)&config_pedo_ths_min, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
+ }
+
return ret;
}
@@ -5886,15 +6811,20 @@ int32_t lsm6dsm_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_config_pedo_ths_min_t config_pedo_ths_min;
int32_t ret;
- ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CONFIG_PEDO_THS_MIN,
- (uint8_t*)&config_pedo_ths_min, 1);
- if(ret == 0){
- *val = config_pedo_ths_min.ths_min;
- ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
- }
+ ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CONFIG_PEDO_THS_MIN,
+ (uint8_t *)&config_pedo_ths_min, 1);
+
+ if (ret == 0)
+ {
+ *val = config_pedo_ths_min.ths_min;
+ ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
+ }
+
return ret;
}
@@ -5907,24 +6837,32 @@ int32_t lsm6dsm_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_pedo_full_scale_set(stmdev_ctx_t *ctx, lsm6dsm_pedo_fs_t val)
+int32_t lsm6dsm_pedo_full_scale_set(stmdev_ctx_t *ctx,
+ lsm6dsm_pedo_fs_t val)
{
lsm6dsm_config_pedo_ths_min_t config_pedo_ths_min;
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_CONFIG_PEDO_THS_MIN,
- (uint8_t*)&config_pedo_ths_min, 1);
- if(ret == 0){
- config_pedo_ths_min.pedo_fs = (uint8_t) val;
+ (uint8_t *)&config_pedo_ths_min, 1);
+
+ if (ret == 0)
+ {
+ config_pedo_ths_min.pedo_fs = (uint8_t) val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_CONFIG_PEDO_THS_MIN,
- (uint8_t*)&config_pedo_ths_min, 1);
- if(ret == 0){
+ (uint8_t *)&config_pedo_ths_min, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
}
+
return ret;
}
@@ -5937,30 +6875,40 @@ int32_t lsm6dsm_pedo_full_scale_set(stmdev_ctx_t *ctx, lsm6dsm_pedo_fs_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_pedo_full_scale_get(stmdev_ctx_t *ctx, lsm6dsm_pedo_fs_t *val)
+int32_t lsm6dsm_pedo_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6dsm_pedo_fs_t *val)
{
lsm6dsm_config_pedo_ths_min_t config_pedo_ths_min;
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_CONFIG_PEDO_THS_MIN,
- (uint8_t*)&config_pedo_ths_min, 1);
- if(ret == 0){
- switch (config_pedo_ths_min.pedo_fs) {
- case LSM6DSM_PEDO_AT_2g:
+ (uint8_t *)&config_pedo_ths_min, 1);
+
+ if (ret == 0)
+ {
+ switch (config_pedo_ths_min.pedo_fs)
+ {
+ case LSM6DSM_PEDO_AT_2g:
*val = LSM6DSM_PEDO_AT_2g;
break;
+
case LSM6DSM_PEDO_AT_4g:
*val = LSM6DSM_PEDO_AT_4g;
break;
+
default:
*val = LSM6DSM_PEDO_AT_2g;
break;
}
+
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
+
return ret;
}
@@ -5972,24 +6920,32 @@ int32_t lsm6dsm_pedo_full_scale_get(stmdev_ctx_t *ctx, lsm6dsm_pedo_fs_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dsm_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dsm_pedo_deb_reg_t pedo_deb_reg;
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_PEDO_DEB_REG,
- (uint8_t*)&pedo_deb_reg, 1);
- if(ret == 0){
+ (uint8_t *)&pedo_deb_reg, 1);
+
+ if (ret == 0)
+ {
pedo_deb_reg.deb_step = val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_PEDO_DEB_REG,
- (uint8_t*)&pedo_deb_reg, 1);
- if(ret == 0){
- ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
- }
+ (uint8_t *)&pedo_deb_reg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
+ }
+
return ret;
}
@@ -6001,20 +6957,25 @@ int32_t lsm6dsm_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsm_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsm_pedo_deb_reg_t pedo_deb_reg;
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_PEDO_DEB_REG,
- (uint8_t*)&pedo_deb_reg, 1);
- if(ret == 0){
- *val = pedo_deb_reg.deb_step;
- ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
- }
+ (uint8_t *)&pedo_deb_reg, 1);
+
+ if (ret == 0)
+ {
+ *val = pedo_deb_reg.deb_step;
+ ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
+ }
return ret;
}
@@ -6035,18 +6996,25 @@ int32_t lsm6dsm_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_PEDO_DEB_REG,
- (uint8_t*)&pedo_deb_reg, 1);
- if(ret == 0){
+ (uint8_t *)&pedo_deb_reg, 1);
+
+ if (ret == 0)
+ {
pedo_deb_reg.deb_time = val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_PEDO_DEB_REG,
- (uint8_t*)&pedo_deb_reg, 1);
- if(ret == 0){
+ (uint8_t *)&pedo_deb_reg, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
}
+
return ret;
}
@@ -6066,14 +7034,19 @@ int32_t lsm6dsm_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_PEDO_DEB_REG,
- (uint8_t*)&pedo_deb_reg, 1);
- if(ret == 0){
+ (uint8_t *)&pedo_deb_reg, 1);
+
+ if (ret == 0)
+ {
*val = pedo_deb_reg.deb_time;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
+
return ret;
}
@@ -6085,17 +7058,23 @@ int32_t lsm6dsm_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_pedo_steps_period_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsm_pedo_steps_period_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_write_reg(ctx, LSM6DSM_STEP_COUNT_DELTA, buff, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
+
return ret;
}
@@ -6107,17 +7086,23 @@ int32_t lsm6dsm_pedo_steps_period_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_pedo_steps_period_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsm_pedo_steps_period_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_STEP_COUNT_DELTA, buff, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
+
return ret;
}
@@ -6147,14 +7132,19 @@ int32_t lsm6dsm_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
ctrl10_c.sign_motion_en = val;
- if (val != 0x00U) {
+
+ if (val != 0x00U)
+ {
ctrl10_c.func_en = val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
}
}
+
return ret;
}
@@ -6171,7 +7161,7 @@ int32_t lsm6dsm_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
*val = ctrl10_c.sign_motion_en;
return ret;
@@ -6190,12 +7180,17 @@ int32_t lsm6dsm_motion_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_write_reg(ctx, LSM6DSM_SM_THS, buff, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
+
return ret;
}
@@ -6212,12 +7207,17 @@ int32_t lsm6dsm_motion_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_SM_THS, buff, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
+
return ret;
}
@@ -6247,14 +7247,20 @@ int32_t lsm6dsm_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
ctrl10_c.tilt_en = val;
- if (val != 0x00U) {
+
+ if (val != 0x00U)
+ {
ctrl10_c.func_en = val;
}
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
}
+
return ret;
}
@@ -6271,7 +7277,7 @@ int32_t lsm6dsm_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
*val = ctrl10_c.tilt_en;
return ret;
@@ -6290,14 +7296,20 @@ int32_t lsm6dsm_wrist_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
ctrl10_c.wrist_tilt_en = val;
- if (val != 0x00U) {
+
+ if (val != 0x00U)
+ {
ctrl10_c.func_en = val;
}
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
}
+
return ret;
}
@@ -6314,7 +7326,7 @@ int32_t lsm6dsm_wrist_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
*val = ctrl10_c.wrist_tilt_en;
return ret;
@@ -6335,12 +7347,17 @@ int32_t lsm6dsm_tilt_latency_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_B);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_write_reg(ctx, LSM6DSM_A_WRIST_TILT_LAT, buff, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
+
return ret;
}
@@ -6359,12 +7376,17 @@ int32_t lsm6dsm_tilt_latency_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_B);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_A_WRIST_TILT_LAT, buff, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
+
return ret;
}
@@ -6383,12 +7405,17 @@ int32_t lsm6dsm_tilt_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_B);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_write_reg(ctx, LSM6DSM_A_WRIST_TILT_THS, buff, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
+
return ret;
}
@@ -6407,12 +7434,17 @@ int32_t lsm6dsm_tilt_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_B);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_A_WRIST_TILT_THS, buff, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
+
return ret;
}
@@ -6430,13 +7462,18 @@ int32_t lsm6dsm_tilt_src_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_B);
- if(ret == 0){
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_A_WRIST_TILT_MASK,
- (uint8_t*) val, 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_A_WRIST_TILT_MASK,
+ (uint8_t *) val, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
+
return ret;
}
@@ -6454,15 +7491,19 @@ int32_t lsm6dsm_tilt_src_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_B);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_A_WRIST_TILT_MASK,
- (uint8_t*) val, 1);
- if(ret == 0){
+ (uint8_t *) val, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
- return ret;
+ return ret;
}
/**
@@ -6491,11 +7532,14 @@ int32_t lsm6dsm_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
ctrl9_xl.soft_en = val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -6512,7 +7556,7 @@ int32_t lsm6dsm_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsm_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
*val = ctrl9_xl.soft_en;
return ret;
@@ -6533,22 +7577,31 @@ int32_t lsm6dsm_mag_hard_iron_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
master_config.iron_en = val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
- if (val != 0x00U) {
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
+ if (val != 0x00U)
+ {
ctrl10_c.func_en = val;
}
+
ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL10_C,
- (uint8_t*)&ctrl10_c, 1);
+ (uint8_t *)&ctrl10_c, 1);
}
}
}
+
return ret;
}
@@ -6566,7 +7619,7 @@ int32_t lsm6dsm_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
*val = master_config.iron_en;
return ret;
@@ -6581,17 +7634,23 @@ int32_t lsm6dsm_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_mag_soft_iron_mat_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsm_mag_soft_iron_mat_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_write_reg(ctx, LSM6DSM_MAG_SI_XX, buff, 9);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
+
return ret;
}
@@ -6604,17 +7663,23 @@ int32_t lsm6dsm_mag_soft_iron_mat_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_mag_soft_iron_mat_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsm_mag_soft_iron_mat_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_MAG_SI_XX, buff, 9);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
+
return ret;
}
@@ -6627,17 +7692,29 @@ int32_t lsm6dsm_mag_soft_iron_mat_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_mag_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsm_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
+ buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
+ buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
+ buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
+ buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
+ buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
+ buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
ret = lsm6dsm_write_reg(ctx, LSM6DSM_MAG_OFFX_L, buff, 6);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
+
return ret;
}
@@ -6650,17 +7727,29 @@ int32_t lsm6dsm_mag_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_mag_offset_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsm_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_MAG_OFFX_L, buff, 6);
- if(ret == 0){
+
+ if (ret == 0)
+ {
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
+
return ret;
}
@@ -6677,7 +7766,7 @@ int32_t lsm6dsm_mag_offset_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
*/
- /**
+/**
* @brief Enable function.[set]
*
* @param ctx Read / write interface definitions
@@ -6690,10 +7779,12 @@ int32_t lsm6dsm_func_en_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsm_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
+ ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
ctrl10_c.func_en = val;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
}
return ret;
@@ -6714,12 +7805,15 @@ int32_t lsm6dsm_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsm_read_reg(ctx, LSM6DSM_SENSOR_SYNC_TIME_FRAME,
- (uint8_t*)&sensor_sync_time_frame, 1);
- if(ret == 0){
- sensor_sync_time_frame.tph = val;
+ (uint8_t *)&sensor_sync_time_frame, 1);
+
+ if (ret == 0)
+ {
+ sensor_sync_time_frame.tph = val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_SENSOR_SYNC_TIME_FRAME,
- (uint8_t*)&sensor_sync_time_frame, 1);
+ (uint8_t *)&sensor_sync_time_frame, 1);
}
+
return ret;
}
@@ -6732,13 +7826,14 @@ int32_t lsm6dsm_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsm_sh_sync_sens_frame_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsm_sensor_sync_time_frame_t sensor_sync_time_frame;
int32_t ret;
ret = lsm6dsm_read_reg(ctx, LSM6DSM_SENSOR_SYNC_TIME_FRAME,
- (uint8_t*)&sensor_sync_time_frame, 1);
+ (uint8_t *)&sensor_sync_time_frame, 1);
*val = sensor_sync_time_frame.tph;
return ret;
@@ -6752,18 +7847,22 @@ int32_t lsm6dsm_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx, lsm6dsm_rr_t val)
+int32_t lsm6dsm_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx,
+ lsm6dsm_rr_t val)
{
lsm6dsm_sensor_sync_res_ratio_t sensor_sync_res_ratio;
int32_t ret;
ret = lsm6dsm_read_reg(ctx, LSM6DSM_SENSOR_SYNC_RES_RATIO,
- (uint8_t*)&sensor_sync_res_ratio, 1);
- if(ret == 0){
+ (uint8_t *)&sensor_sync_res_ratio, 1);
+
+ if (ret == 0)
+ {
sensor_sync_res_ratio.rr = (uint8_t) val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_SENSOR_SYNC_RES_RATIO,
- (uint8_t*)&sensor_sync_res_ratio, 1);
+ (uint8_t *)&sensor_sync_res_ratio, 1);
}
+
return ret;
}
@@ -6775,27 +7874,33 @@ int32_t lsm6dsm_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx, lsm6dsm_rr_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx, lsm6dsm_rr_t *val)
+int32_t lsm6dsm_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx,
+ lsm6dsm_rr_t *val)
{
lsm6dsm_sensor_sync_res_ratio_t sensor_sync_res_ratio;
int32_t ret;
ret = lsm6dsm_read_reg(ctx, LSM6DSM_SENSOR_SYNC_RES_RATIO,
- (uint8_t*)&sensor_sync_res_ratio, 1);
+ (uint8_t *)&sensor_sync_res_ratio, 1);
- switch ( sensor_sync_res_ratio.rr) {
+ switch (sensor_sync_res_ratio.rr)
+ {
case LSM6DSM_RES_RATIO_2_11:
*val = LSM6DSM_RES_RATIO_2_11;
break;
+
case LSM6DSM_RES_RATIO_2_12:
*val = LSM6DSM_RES_RATIO_2_12;
break;
+
case LSM6DSM_RES_RATIO_2_13:
*val = LSM6DSM_RES_RATIO_2_13;
break;
+
case LSM6DSM_RES_RATIO_2_14:
*val = LSM6DSM_RES_RATIO_2_14;
break;
+
default:
*val = LSM6DSM_RES_RATIO_2_11;
break;
@@ -6818,12 +7923,15 @@ int32_t lsm6dsm_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
master_config.master_on = val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
+
return ret;
}
@@ -6841,7 +7949,7 @@ int32_t lsm6dsm_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
*val = master_config.master_on;
return ret;
@@ -6861,12 +7969,15 @@ int32_t lsm6dsm_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
master_config.pass_through_mode = val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
+
return ret;
}
@@ -6884,7 +7995,7 @@ int32_t lsm6dsm_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
*val = master_config.pass_through_mode;
return ret;
@@ -6898,17 +8009,20 @@ int32_t lsm6dsm_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_sh_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsm_pull_up_en_t val)
+int32_t lsm6dsm_sh_pin_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsm_pull_up_en_t val)
{
lsm6dsm_master_config_t master_config;
int32_t ret;
ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
master_config.pull_up_en = (uint8_t) val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
return ret;
@@ -6922,24 +8036,30 @@ int32_t lsm6dsm_sh_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsm_pull_up_en_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_sh_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsm_pull_up_en_t *val)
+int32_t lsm6dsm_sh_pin_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsm_pull_up_en_t *val)
{
lsm6dsm_master_config_t master_config;
int32_t ret;
ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- switch (master_config.pull_up_en) {
+ (uint8_t *)&master_config, 1);
+
+ switch (master_config.pull_up_en)
+ {
case LSM6DSM_EXT_PULL_UP:
*val = LSM6DSM_EXT_PULL_UP;
break;
+
case LSM6DSM_INTERNAL_PULL_UP:
*val = LSM6DSM_INTERNAL_PULL_UP;
break;
+
default:
*val = LSM6DSM_SH_PIN_MODE;
break;
}
+
return ret;
}
@@ -6958,12 +8078,15 @@ int32_t lsm6dsm_sh_syncro_mode_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
master_config.start_config = (uint8_t)val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
+
return ret;
}
@@ -6982,14 +8105,18 @@ int32_t lsm6dsm_sh_syncro_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- switch (master_config.start_config) {
+ (uint8_t *)&master_config, 1);
+
+ switch (master_config.start_config)
+ {
case LSM6DSM_XL_GY_DRDY:
*val = LSM6DSM_XL_GY_DRDY;
break;
+
case LSM6DSM_EXT_ON_INT2_PIN:
*val = LSM6DSM_EXT_ON_INT2_PIN;
break;
+
default:
*val = LSM6DSM_XL_GY_DRDY;
break;
@@ -7012,12 +8139,15 @@ int32_t lsm6dsm_sh_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
- if(ret == 0){
+ (uint8_t *)&master_config, 1);
+
+ if (ret == 0)
+ {
master_config.drdy_on_int1 = val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
+
return ret;
}
@@ -7035,7 +8165,7 @@ int32_t lsm6dsm_sh_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
*val = master_config.drdy_on_int1;
return ret;
@@ -7053,12 +8183,16 @@ int32_t lsm6dsm_sh_read_data_raw_get(stmdev_ctx_t *ctx,
lsm6dsm_emb_sh_read_t *val)
{
int32_t ret;
+
ret = lsm6dsm_read_reg(ctx, LSM6DSM_SENSORHUB1_REG,
- (uint8_t*)&(val->sh_byte_1), 12);
- if(ret == 0){
+ (uint8_t *) & (val->sh_byte_1), 12);
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_SENSORHUB13_REG,
- (uint8_t*)&(val->sh_byte_13), 6);
+ (uint8_t *) & (val->sh_byte_13), 6);
}
+
return ret;
}
@@ -7077,12 +8211,15 @@ int32_t lsm6dsm_sh_cmd_sens_sync_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CMD_CODE,
- (uint8_t*)&master_cmd_code, 1);
- if(ret == 0){
+ (uint8_t *)&master_cmd_code, 1);
+
+ if (ret == 0)
+ {
master_cmd_code.master_cmd_code = val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_MASTER_CMD_CODE,
- (uint8_t*)&master_cmd_code, 1);
+ (uint8_t *)&master_cmd_code, 1);
}
+
return ret;
}
@@ -7101,7 +8238,7 @@ int32_t lsm6dsm_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CMD_CODE,
- (uint8_t*)&master_cmd_code, 1);
+ (uint8_t *)&master_cmd_code, 1);
*val = master_cmd_code.master_cmd_code;
return ret;
@@ -7122,12 +8259,15 @@ int32_t lsm6dsm_sh_spi_sync_error_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsm_read_reg(ctx, LSM6DSM_SENS_SYNC_SPI_ERROR_CODE,
- (uint8_t*)&sens_sync_spi_error_code, 1);
- if(ret == 0){
- sens_sync_spi_error_code.error_code = val;
+ (uint8_t *)&sens_sync_spi_error_code, 1);
+
+ if (ret == 0)
+ {
+ sens_sync_spi_error_code.error_code = val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_SENS_SYNC_SPI_ERROR_CODE,
- (uint8_t*)&sens_sync_spi_error_code, 1);
+ (uint8_t *)&sens_sync_spi_error_code, 1);
}
+
return ret;
}
@@ -7146,7 +8286,7 @@ int32_t lsm6dsm_sh_spi_sync_error_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsm_read_reg(ctx, LSM6DSM_SENS_SYNC_SPI_ERROR_CODE,
- (uint8_t*)&sens_sync_spi_error_code, 1);
+ (uint8_t *)&sens_sync_spi_error_code, 1);
*val = sens_sync_spi_error_code.error_code;
return ret;
@@ -7167,18 +8307,25 @@ int32_t lsm6dsm_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave0_config, 1);
+
+ if (ret == 0)
+ {
slave0_config.aux_sens_on = (uint8_t) val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave0_config, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
}
+
return ret;
}
@@ -7197,27 +8344,37 @@ int32_t lsm6dsm_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
- if(ret == 0){
- switch (slave0_config.aux_sens_on) {
+ (uint8_t *)&slave0_config, 1);
+
+ if (ret == 0)
+ {
+ switch (slave0_config.aux_sens_on)
+ {
case LSM6DSM_SLV_0:
*val = LSM6DSM_SLV_0;
break;
+
case LSM6DSM_SLV_0_1:
*val = LSM6DSM_SLV_0_1;
break;
+
case LSM6DSM_SLV_0_1_2:
*val = LSM6DSM_SLV_0_1_2;
break;
+
case LSM6DSM_SLV_0_1_2_3:
*val = LSM6DSM_SLV_0_1_2_3;
break;
+
default:
*val = LSM6DSM_SLV_0;
break;
}
+
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
@@ -7236,28 +8393,38 @@ int32_t lsm6dsm_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_sh_cfg_write(stmdev_ctx_t *ctx, lsm6dsm_sh_cfg_write_t *val)
+int32_t lsm6dsm_sh_cfg_write(stmdev_ctx_t *ctx,
+ lsm6dsm_sh_cfg_write_t *val)
{
lsm6dsm_slv0_add_t slv0_add;
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv0_add.slave0_add = val->slv0_add;
slv0_add.rw_0 = 0;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV0_ADD, (uint8_t*)&slv0_add, 1);
- if(ret == 0){
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV0_ADD, (uint8_t *)&slv0_add, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV0_SUBADD,
&(val->slv0_subadd), 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_write_reg(ctx, LSM6DSM_DATAWRITE_SRC_MODE_SUB_SLV0,
&(val->slv0_data), 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
}
}
+
return ret;
}
@@ -7280,27 +8447,38 @@ int32_t lsm6dsm_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv0_add.slave0_add = val->slv_add;
slv0_add.rw_0 = 1;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV0_ADD, (uint8_t*)&slv0_add, 1);
- if(ret == 0){
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV0_ADD, (uint8_t *)&slv0_add, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV0_SUBADD,
&(val->slv_subadd), 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
+ (uint8_t *)&slave0_config, 1);
slave0_config.slave0_numop = val->slv_len;
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave0_config, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
}
}
}
+
return ret;
}
@@ -7323,27 +8501,38 @@ int32_t lsm6dsm_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv1_add.slave1_add = val->slv_add;
slv1_add.r_1 = 1;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV1_ADD, (uint8_t*)&slv1_add, 1);
- if(ret == 0){
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV1_ADD, (uint8_t *)&slv1_add, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV1_SUBADD,
- &(val->slv_subadd), 1);
- if(ret == 0){
+ &(val->slv_subadd), 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
+ (uint8_t *)&slave1_config, 1);
slave1_config.slave1_numop = val->slv_len;
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave1_config, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
}
}
}
+
return ret;
}
@@ -7366,21 +8555,31 @@ int32_t lsm6dsm_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv2_add.slave2_add = val->slv_add;
slv2_add.r_2 = 1;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV2_ADD, (uint8_t*)&slv2_add, 1);
- if(ret == 0){
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV2_ADD, (uint8_t *)&slv2_add, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV2_SUBADD,
&(val->slv_subadd), 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE2_CONFIG,
- (uint8_t*)&slave2_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave2_config, 1);
+
+ if (ret == 0)
+ {
slave2_config.slave2_numop = val->slv_len;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE2_CONFIG,
- (uint8_t*)&slave2_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave2_config, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
@@ -7410,27 +8609,38 @@ int32_t lsm6dsm_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv3_add.slave3_add = val->slv_add;
slv3_add.r_3 = 1;
- ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV3_ADD, (uint8_t*)&slv3_add, 1);
- if(ret == 0){
+ ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV3_ADD, (uint8_t *)&slv3_add, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV3_SUBADD,
- (uint8_t*)&(val->slv_subadd), 1);
- if(ret == 0){
+ (uint8_t *) & (val->slv_subadd), 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE3_CONFIG,
- (uint8_t*)&slave3_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave3_config, 1);
+
+ if (ret == 0)
+ {
slave3_config.slave3_numop = val->slv_len;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE3_CONFIG,
- (uint8_t*)&slave3_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave3_config, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
}
}
}
+
return ret;
}
@@ -7450,18 +8660,25 @@ int32_t lsm6dsm_sh_slave_0_dec_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave0_config, 1);
+
+ if (ret == 0)
+ {
slave0_config.slave0_rate = (uint8_t) val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave0_config, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
}
+
return ret;
}
@@ -7481,27 +8698,37 @@ int32_t lsm6dsm_sh_slave_0_dec_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE0_CONFIG,
- (uint8_t*)&slave0_config, 1);
- if(ret == 0){
- switch (slave0_config.slave0_rate) {
+ (uint8_t *)&slave0_config, 1);
+
+ if (ret == 0)
+ {
+ switch (slave0_config.slave0_rate)
+ {
case LSM6DSM_SL0_NO_DEC:
*val = LSM6DSM_SL0_NO_DEC;
break;
+
case LSM6DSM_SL0_DEC_2:
*val = LSM6DSM_SL0_DEC_2;
break;
+
case LSM6DSM_SL0_DEC_4:
*val = LSM6DSM_SL0_DEC_4;
break;
+
case LSM6DSM_SL0_DEC_8:
*val = LSM6DSM_SL0_DEC_8;
break;
+
default:
*val = LSM6DSM_SL0_NO_DEC;
break;
}
+
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
@@ -7520,24 +8747,32 @@ int32_t lsm6dsm_sh_slave_0_dec_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsm_sh_write_mode_set(stmdev_ctx_t *ctx, lsm6dsm_write_once_t val)
+int32_t lsm6dsm_sh_write_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsm_write_once_t val)
{
lsm6dsm_slave1_config_t slave1_config;
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
+ (uint8_t *)&slave1_config, 1);
slave1_config.write_once = (uint8_t) val;
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave1_config, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
}
+
return ret;
}
@@ -7559,21 +8794,29 @@ int32_t lsm6dsm_sh_write_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
- if(ret == 0){
- switch (slave1_config.write_once) {
+ (uint8_t *)&slave1_config, 1);
+
+ if (ret == 0)
+ {
+ switch (slave1_config.write_once)
+ {
case LSM6DSM_EACH_SH_CYCLE:
*val = LSM6DSM_EACH_SH_CYCLE;
break;
+
case LSM6DSM_ONLY_FIRST_CYCLE:
*val = LSM6DSM_ONLY_FIRST_CYCLE;
break;
+
default:
*val = LSM6DSM_EACH_SH_CYCLE;
break;
}
+
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
@@ -7597,18 +8840,25 @@ int32_t lsm6dsm_sh_slave_1_dec_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave1_config, 1);
+
+ if (ret == 0)
+ {
slave1_config.slave1_rate = (uint8_t) val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
- if(ret == 0){
- ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
+ (uint8_t *)&slave1_config, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
}
+
return ret;
}
@@ -7627,27 +8877,37 @@ int32_t lsm6dsm_sh_slave_1_dec_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE1_CONFIG,
- (uint8_t*)&slave1_config, 1);
- if(ret == 0){
- switch (slave1_config.slave1_rate) {
+ (uint8_t *)&slave1_config, 1);
+
+ if (ret == 0)
+ {
+ switch (slave1_config.slave1_rate)
+ {
case LSM6DSM_SL1_NO_DEC:
*val = LSM6DSM_SL1_NO_DEC;
break;
+
case LSM6DSM_SL1_DEC_2:
*val = LSM6DSM_SL1_DEC_2;
break;
+
case LSM6DSM_SL1_DEC_4:
*val = LSM6DSM_SL1_DEC_4;
break;
+
case LSM6DSM_SL1_DEC_8:
*val = LSM6DSM_SL1_DEC_8;
break;
+
default:
*val = LSM6DSM_SL1_NO_DEC;
break;
}
+
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
@@ -7671,18 +8931,25 @@ int32_t lsm6dsm_sh_slave_2_dec_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE2_CONFIG,
- (uint8_t*)&slave2_config, 1);
- if(ret == 0){
- slave2_config.slave2_rate =(uint8_t) val;
+ (uint8_t *)&slave2_config, 1);
+
+ if (ret == 0)
+ {
+ slave2_config.slave2_rate = (uint8_t) val;
ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE2_CONFIG,
- (uint8_t*)&slave2_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave2_config, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
}
+
return ret;
}
@@ -7702,27 +8969,37 @@ int32_t lsm6dsm_sh_slave_2_dec_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE2_CONFIG,
- (uint8_t*)&slave2_config, 1);
- if(ret == 0){
- switch (slave2_config.slave2_rate) {
+ (uint8_t *)&slave2_config, 1);
+
+ if (ret == 0)
+ {
+ switch (slave2_config.slave2_rate)
+ {
case LSM6DSM_SL2_NO_DEC:
*val = LSM6DSM_SL2_NO_DEC;
break;
+
case LSM6DSM_SL2_DEC_2:
*val = LSM6DSM_SL2_DEC_2;
break;
+
case LSM6DSM_SL2_DEC_4:
*val = LSM6DSM_SL2_DEC_4;
break;
+
case LSM6DSM_SL2_DEC_8:
*val = LSM6DSM_SL2_DEC_8;
break;
+
default:
*val = LSM6DSM_SL2_NO_DEC;
break;
}
+
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
@@ -7746,18 +9023,25 @@ int32_t lsm6dsm_sh_slave_3_dec_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE3_CONFIG,
- (uint8_t*)&slave3_config, 1);
+ (uint8_t *)&slave3_config, 1);
slave3_config.slave3_rate = (uint8_t)val;
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE3_CONFIG,
- (uint8_t*)&slave3_config, 1);
- if(ret == 0){
+ (uint8_t *)&slave3_config, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
}
+
return ret;
}
@@ -7777,27 +9061,37 @@ int32_t lsm6dsm_sh_slave_3_dec_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE3_CONFIG,
- (uint8_t*)&slave3_config, 1);
- if(ret == 0){
- switch (slave3_config.slave3_rate) {
+ (uint8_t *)&slave3_config, 1);
+
+ if (ret == 0)
+ {
+ switch (slave3_config.slave3_rate)
+ {
case LSM6DSM_SL3_NO_DEC:
*val = LSM6DSM_SL3_NO_DEC;
break;
+
case LSM6DSM_SL3_DEC_2:
*val = LSM6DSM_SL3_DEC_2;
break;
+
case LSM6DSM_SL3_DEC_4:
*val = LSM6DSM_SL3_DEC_4;
break;
+
case LSM6DSM_SL3_DEC_8:
*val = LSM6DSM_SL3_DEC_8;
break;
+
default:
*val = LSM6DSM_SL3_NO_DEC;
break;
}
+
ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
}
}
diff --git a/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.h b/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.h
index 10bb3162053e080858a87369acde2545662c5f55..0834624c3150ba9a3b6ffbdf83d8a67342283c55 100644
--- a/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.h
+++ b/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file lsm6dsm_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lsm6dsm_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lsm6dsm_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lsm6dsm_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LSM6DSM_REGS_H
#define LSM6DSM_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup LSM6DSM
@@ -35,6 +36,38 @@
*
*/
+/** @defgroup Endianness definitions
+ * @{
+ *
+ */
+
+#ifndef DRV_BYTE_ORDER
+#ifndef __BYTE_ORDER__
+
+#define DRV_LITTLE_ENDIAN 1234
+#define DRV_BIG_ENDIAN 4321
+
+/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
+ * by uncommenting the define which fits your platform endianness
+ */
+//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
+#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
+
+#else /* defined __BYTE_ORDER__ */
+
+#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
+#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
+#define DRV_BYTE_ORDER __BYTE_ORDER__
+
+#endif /* __BYTE_ORDER__*/
+#endif /* DRV_BYTE_ORDER */
+
+/**
+ * @}
+ *
+ */
+
+
/** @defgroup STMicroelectronics sensors common types
* @{
*
@@ -43,7 +76,9 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -52,6 +87,16 @@ typedef struct{
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} bitwise_t;
#define PROPERTY_DISABLE (0U)
@@ -65,10 +110,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -89,15 +135,16 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
- * Unico / Unicleo tools available on STMicroelectronics
- * web site.
+ * You can create a sensor configuration by your own or using
+ * Unico / Unicleo tools available on STMicroelectronics
+ * web site.
*
* @{
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -132,68 +179,129 @@ typedef struct {
*/
#define LSM6DSM_FUNC_CFG_ACCESS 0x01U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 5;
- uint8_t func_cfg_en : 3; /* func_cfg_en + func_cfg_en_b */
+uint8_t func_cfg_en :
+ 3; /* func_cfg_en + func_cfg_en_b */
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+uint8_t func_cfg_en :
+ 3; /* func_cfg_en + func_cfg_en_b */
+ uint8_t not_used_01 : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_func_cfg_access_t;
#define LSM6DSM_SENSOR_SYNC_TIME_FRAME 0x04U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tph : 4;
uint8_t not_used_01 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 4;
+ uint8_t tph : 4;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_sensor_sync_time_frame_t;
#define LSM6DSM_SENSOR_SYNC_RES_RATIO 0x05U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t rr : 2;
uint8_t not_used_01 : 6;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 6;
+ uint8_t rr : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_sensor_sync_res_ratio_t;
#define LSM6DSM_FIFO_CTRL1 0x06U
-typedef struct {
+typedef struct
+{
uint8_t fth : 8; /* + FIFO_CTRL2(fth) */
} lsm6dsm_fifo_ctrl1_t;
#define LSM6DSM_FIFO_CTRL2 0x07U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fth : 3; /* + FIFO_CTRL1(fth) */
uint8_t fifo_temp_en : 1;
uint8_t not_used_01 : 2;
uint8_t timer_pedo_fifo_drdy : 1;
uint8_t timer_pedo_fifo_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t timer_pedo_fifo_en : 1;
+ uint8_t timer_pedo_fifo_drdy : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t fifo_temp_en : 1;
+ uint8_t fth : 3; /* + FIFO_CTRL1(fth) */
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_fifo_ctrl2_t;
#define LSM6DSM_FIFO_CTRL3 0x08U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t dec_fifo_xl : 3;
uint8_t dec_fifo_gyro : 3;
uint8_t not_used_01 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 2;
+ uint8_t dec_fifo_gyro : 3;
+ uint8_t dec_fifo_xl : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_fifo_ctrl3_t;
#define LSM6DSM_FIFO_CTRL4 0x09U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t dec_ds3_fifo : 3;
uint8_t dec_ds4_fifo : 3;
uint8_t only_high_data : 1;
uint8_t stop_on_fth : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t stop_on_fth : 1;
+ uint8_t only_high_data : 1;
+ uint8_t dec_ds4_fifo : 3;
+ uint8_t dec_ds3_fifo : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_fifo_ctrl4_t;
#define LSM6DSM_FIFO_CTRL5 0x0AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fifo_mode : 3;
uint8_t odr_fifo : 4;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t odr_fifo : 4;
+ uint8_t fifo_mode : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_fifo_ctrl5_t;
#define LSM6DSM_DRDY_PULSE_CFG 0x0BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_wrist_tilt : 1;
uint8_t not_used_01 : 6;
uint8_t drdy_pulsed : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t drdy_pulsed : 1;
+ uint8_t not_used_01 : 6;
+ uint8_t int2_wrist_tilt : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_drdy_pulse_cfg_t;
#define LSM6DSM_INT1_CTRL 0x0DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_drdy_xl : 1;
uint8_t int1_drdy_g : 1;
uint8_t int1_boot : 1;
@@ -202,10 +310,22 @@ typedef struct {
uint8_t int1_full_flag : 1;
uint8_t int1_sign_mot : 1;
uint8_t int1_step_detector : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_step_detector : 1;
+ uint8_t int1_sign_mot : 1;
+ uint8_t int1_full_flag : 1;
+ uint8_t int1_fifo_ovr : 1;
+ uint8_t int1_fth : 1;
+ uint8_t int1_boot : 1;
+ uint8_t int1_drdy_g : 1;
+ uint8_t int1_drdy_xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_int1_ctrl_t;
#define LSM6DSM_INT2_CTRL 0x0EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_drdy_xl : 1;
uint8_t int2_drdy_g : 1;
uint8_t int2_drdy_temp : 1;
@@ -214,26 +334,53 @@ typedef struct {
uint8_t int2_full_flag : 1;
uint8_t int2_step_count_ov : 1;
uint8_t int2_step_delta : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_step_delta : 1;
+ uint8_t int2_step_count_ov : 1;
+ uint8_t int2_full_flag : 1;
+ uint8_t int2_fifo_ovr : 1;
+ uint8_t int2_fth : 1;
+ uint8_t int2_drdy_temp : 1;
+ uint8_t int2_drdy_g : 1;
+ uint8_t int2_drdy_xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_int2_ctrl_t;
#define LSM6DSM_WHO_AM_I 0x0FU
#define LSM6DSM_CTRL1_XL 0x10U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bw0_xl : 1;
uint8_t lpf1_bw_sel : 1;
uint8_t fs_xl : 2;
uint8_t odr_xl : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr_xl : 4;
+ uint8_t fs_xl : 2;
+ uint8_t lpf1_bw_sel : 1;
+ uint8_t bw0_xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_ctrl1_xl_t;
#define LSM6DSM_CTRL2_G 0x11U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t fs_g : 3; /* fs_g + fs_125 */
uint8_t odr_g : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr_g : 4;
+ uint8_t fs_g : 3; /* fs_g + fs_125 */
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_ctrl2_g_t;
#define LSM6DSM_CTRL3_C 0x12U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sw_reset : 1;
uint8_t ble : 1;
uint8_t if_inc : 1;
@@ -242,10 +389,22 @@ typedef struct {
uint8_t h_lactive : 1;
uint8_t bdu : 1;
uint8_t boot : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t boot : 1;
+ uint8_t bdu : 1;
+ uint8_t h_lactive : 1;
+ uint8_t pp_od : 1;
+ uint8_t sim : 1;
+ uint8_t if_inc : 1;
+ uint8_t ble : 1;
+ uint8_t sw_reset : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_ctrl3_c_t;
#define LSM6DSM_CTRL4_C 0x13U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t lpf1_sel_g : 1;
uint8_t i2c_disable : 1;
@@ -254,37 +413,78 @@ typedef struct {
uint8_t int2_on_int1 : 1;
uint8_t sleep : 1;
uint8_t den_xl_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t den_xl_en : 1;
+ uint8_t sleep : 1;
+ uint8_t int2_on_int1 : 1;
+ uint8_t den_drdy_int1 : 1;
+ uint8_t drdy_mask : 1;
+ uint8_t i2c_disable : 1;
+ uint8_t lpf1_sel_g : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_ctrl4_c_t;
#define LSM6DSM_CTRL5_C 0x14U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_xl : 2;
uint8_t st_g : 2;
uint8_t den_lh : 1;
uint8_t rounding : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t rounding : 3;
+ uint8_t den_lh : 1;
+ uint8_t st_g : 2;
+ uint8_t st_xl : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_ctrl5_c_t;
#define LSM6DSM_CTRL6_C 0x15U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ftype : 2;
uint8_t not_used_01 : 1;
uint8_t usr_off_w : 1;
uint8_t xl_hm_mode : 1;
- uint8_t den_mode : 3; /* trig_en + lvl_en + lvl2_en */
+uint8_t den_mode :
+ 3; /* trig_en + lvl_en + lvl2_en */
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+uint8_t den_mode :
+ 3; /* trig_en + lvl_en + lvl2_en */
+ uint8_t xl_hm_mode : 1;
+ uint8_t usr_off_w : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t ftype : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_ctrl6_c_t;
#define LSM6DSM_CTRL7_G 0x16U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t rounding_status : 1;
uint8_t not_used_02 : 1;
uint8_t hpm_g : 2;
uint8_t hp_en_g : 1;
uint8_t g_hm_mode : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t g_hm_mode : 1;
+ uint8_t hp_en_g : 1;
+ uint8_t hpm_g : 2;
+ uint8_t not_used_02 : 1;
+ uint8_t rounding_status : 1;
+ uint8_t not_used_01 : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_ctrl7_g_t;
#define LSM6DSM_CTRL8_XL 0x17U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t low_pass_on_6d : 1;
uint8_t not_used_01 : 1;
uint8_t hp_slope_xl_en : 1;
@@ -292,10 +492,21 @@ typedef struct {
uint8_t hp_ref_mode : 1;
uint8_t hpcf_xl : 2;
uint8_t lpf2_xl_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t lpf2_xl_en : 1;
+ uint8_t hpcf_xl : 2;
+ uint8_t hp_ref_mode : 1;
+ uint8_t input_composite : 1;
+ uint8_t hp_slope_xl_en : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t low_pass_on_6d : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_ctrl8_xl_t;
#define LSM6DSM_CTRL9_XL 0x18U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t soft_en : 1;
uint8_t not_used_02 : 1;
@@ -303,10 +514,21 @@ typedef struct {
uint8_t den_z : 1;
uint8_t den_y : 1;
uint8_t den_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t den_x : 1;
+ uint8_t den_y : 1;
+ uint8_t den_z : 1;
+ uint8_t den_xl_g : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t soft_en : 1;
+ uint8_t not_used_01 : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_ctrl9_xl_t;
#define LSM6DSM_CTRL10_C 0x19U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sign_motion_en : 1;
uint8_t pedo_rst_step : 1;
uint8_t func_en : 1;
@@ -315,10 +537,22 @@ typedef struct {
uint8_t timer_en : 1;
uint8_t not_used_01 : 1;
uint8_t wrist_tilt_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t wrist_tilt_en : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t timer_en : 1;
+ uint8_t pedo_en : 1;
+ uint8_t tilt_en : 1;
+ uint8_t func_en : 1;
+ uint8_t pedo_rst_step : 1;
+ uint8_t sign_motion_en : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_ctrl10_c_t;
#define LSM6DSM_MASTER_CONFIG 0x1AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t master_on : 1;
uint8_t iron_en : 1;
uint8_t pass_through_mode : 1;
@@ -327,10 +561,22 @@ typedef struct {
uint8_t not_used_01 : 1;
uint8_t data_valid_sel_fifo : 1;
uint8_t drdy_on_int1 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t drdy_on_int1 : 1;
+ uint8_t data_valid_sel_fifo : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t start_config : 1;
+ uint8_t pull_up_en : 1;
+ uint8_t pass_through_mode : 1;
+ uint8_t iron_en : 1;
+ uint8_t master_on : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_master_config_t;
#define LSM6DSM_WAKE_UP_SRC 0x1BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_wu : 1;
uint8_t y_wu : 1;
uint8_t x_wu : 1;
@@ -338,10 +584,21 @@ typedef struct {
uint8_t sleep_state_ia : 1;
uint8_t ff_ia : 1;
uint8_t not_used_01 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 2;
+ uint8_t ff_ia : 1;
+ uint8_t sleep_state_ia : 1;
+ uint8_t wu_ia : 1;
+ uint8_t x_wu : 1;
+ uint8_t y_wu : 1;
+ uint8_t z_wu : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_wake_up_src_t;
#define LSM6DSM_TAP_SRC 0x1CU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_tap : 1;
uint8_t y_tap : 1;
uint8_t x_tap : 1;
@@ -350,10 +607,22 @@ typedef struct {
uint8_t single_tap : 1;
uint8_t tap_ia : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t tap_ia : 1;
+ uint8_t single_tap : 1;
+ uint8_t double_tap : 1;
+ uint8_t tap_sign : 1;
+ uint8_t x_tap : 1;
+ uint8_t y_tap : 1;
+ uint8_t z_tap : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_tap_src_t;
#define LSM6DSM_D6D_SRC 0x1DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
uint8_t yl : 1;
@@ -362,22 +631,48 @@ typedef struct {
uint8_t zh : 1;
uint8_t d6d_ia : 1;
uint8_t den_drdy : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t den_drdy : 1;
+ uint8_t d6d_ia : 1;
+ uint8_t zh : 1;
+ uint8_t zl : 1;
+ uint8_t yh : 1;
+ uint8_t yl : 1;
+ uint8_t xh : 1;
+ uint8_t xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_d6d_src_t;
#define LSM6DSM_STATUS_REG 0x1EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlda : 1;
uint8_t gda : 1;
uint8_t tda : 1;
uint8_t not_used_01 : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 5;
+ uint8_t tda : 1;
+ uint8_t gda : 1;
+ uint8_t xlda : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_status_reg_t;
#define LSM6DSM_STATUS_SPIAUX 0x1EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlda : 1;
uint8_t gda : 1;
uint8_t gyro_settling : 1;
uint8_t not_used_01 : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 5;
+ uint8_t gyro_settling : 1;
+ uint8_t gda : 1;
+ uint8_t xlda : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_status_spiaux_t;
#define LSM6DSM_OUT_TEMP_L 0x20U
@@ -395,7 +690,9 @@ typedef struct {
#define LSM6DSM_OUTZ_L_XL 0x2CU
#define LSM6DSM_OUTZ_H_XL 0x2DU
#define LSM6DSM_SENSORHUB1_REG 0x2EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -404,10 +701,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_sensorhub1_reg_t;
#define LSM6DSM_SENSORHUB2_REG 0x2FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -416,10 +725,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_sensorhub2_reg_t;
#define LSM6DSM_SENSORHUB3_REG 0x30U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -428,10 +749,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_sensorhub3_reg_t;
#define LSM6DSM_SENSORHUB4_REG 0x31U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -440,10 +773,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_sensorhub4_reg_t;
#define LSM6DSM_SENSORHUB5_REG 0x32U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -452,10 +797,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_sensorhub5_reg_t;
#define LSM6DSM_SENSORHUB6_REG 0x33U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -464,10 +821,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_sensorhub6_reg_t;
#define LSM6DSM_SENSORHUB7_REG 0x34U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -476,10 +845,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_sensorhub7_reg_t;
#define LSM6DSM_SENSORHUB8_REG 0x35U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -488,10 +869,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_sensorhub8_reg_t;
#define LSM6DSM_SENSORHUB9_REG 0x36U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -500,10 +893,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_sensorhub9_reg_t;
#define LSM6DSM_SENSORHUB10_REG 0x37U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -512,10 +917,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_sensorhub10_reg_t;
#define LSM6DSM_SENSORHUB11_REG 0x38U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -524,10 +941,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_sensorhub11_reg_t;
#define LSM6DSM_SENSORHUB12_REG 0x39U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -536,32 +965,63 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_sensorhub12_reg_t;
#define LSM6DSM_FIFO_STATUS1 0x3AU
-typedef struct {
+typedef struct
+{
uint8_t diff_fifo : 8; /* + FIFO_STATUS2(diff_fifo) */
} lsm6dsm_fifo_status1_t;
#define LSM6DSM_FIFO_STATUS2 0x3BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t diff_fifo : 3; /* + FIFO_STATUS1(diff_fifo) */
uint8_t not_used_01 : 1;
uint8_t fifo_empty : 1;
uint8_t fifo_full_smart : 1;
uint8_t over_run : 1;
uint8_t waterm : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t waterm : 1;
+ uint8_t over_run : 1;
+ uint8_t fifo_full_smart : 1;
+ uint8_t fifo_empty : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t diff_fifo : 3; /* + FIFO_STATUS1(diff_fifo) */
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_fifo_status2_t;
#define LSM6DSM_FIFO_STATUS3 0x3CU
-typedef struct {
- uint8_t fifo_pattern : 8; /* + FIFO_STATUS4(fifo_pattern) */
+typedef struct
+{
+uint8_t fifo_pattern :
+ 8; /* + FIFO_STATUS4(fifo_pattern) */
} lsm6dsm_fifo_status3_t;
#define LSM6DSM_FIFO_STATUS4 0x3DU
-typedef struct {
- uint8_t fifo_pattern : 2; /* + FIFO_STATUS3(fifo_pattern) */
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+uint8_t fifo_pattern :
+ 2; /* + FIFO_STATUS3(fifo_pattern) */
+ uint8_t not_used_01 : 6;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used_01 : 6;
+uint8_t fifo_pattern :
+ 2; /* + FIFO_STATUS3(fifo_pattern) */
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_fifo_status4_t;
#define LSM6DSM_FIFO_DATA_OUT_L 0x3EU
@@ -575,7 +1035,9 @@ typedef struct {
#define LSM6DSM_STEP_COUNTER_H 0x4CU
#define LSM6DSM_SENSORHUB13_REG 0x4DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -584,10 +1046,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_sensorhub13_reg_t;
#define LSM6DSM_SENSORHUB14_REG 0x4EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -596,10 +1070,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_sensorhub14_reg_t;
#define LSM6DSM_SENSORHUB15_REG 0x4FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -608,10 +1094,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_sensorhub15_reg_t;
#define LSM6DSM_SENSORHUB16_REG 0x50U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -620,10 +1118,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_sensorhub16_reg_t;
#define LSM6DSM_SENSORHUB17_REG 0x51U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -632,10 +1142,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_sensorhub17_reg_t;
#define LSM6DSM_SENSORHUB18_REG 0x52U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -644,10 +1166,22 @@ typedef struct {
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_sensorhub18_reg_t;
#define LSM6DSM_FUNC_SRC1 0x53U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sensorhub_end_op : 1;
uint8_t si_end_op : 1;
uint8_t hi_fail : 1;
@@ -656,10 +1190,22 @@ typedef struct {
uint8_t tilt_ia : 1;
uint8_t sign_motion_ia : 1;
uint8_t step_count_delta_ia : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t step_count_delta_ia : 1;
+ uint8_t sign_motion_ia : 1;
+ uint8_t tilt_ia : 1;
+ uint8_t step_detected : 1;
+ uint8_t step_overflow : 1;
+ uint8_t hi_fail : 1;
+ uint8_t si_end_op : 1;
+ uint8_t sensorhub_end_op : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_func_src1_t;
#define LSM6DSM_FUNC_SRC2 0x54U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wrist_tilt_ia : 1;
uint8_t not_used_01 : 2;
uint8_t slave0_nack : 1;
@@ -667,10 +1213,21 @@ typedef struct {
uint8_t slave2_nack : 1;
uint8_t slave3_nack : 1;
uint8_t not_used_02 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 1;
+ uint8_t slave3_nack : 1;
+ uint8_t slave2_nack : 1;
+ uint8_t slave1_nack : 1;
+ uint8_t slave0_nack : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t wrist_tilt_ia : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_func_src2_t;
#define LSM6DSM_WRIST_TILT_IA 0x55U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t wrist_tilt_ia_zneg : 1;
uint8_t wrist_tilt_ia_zpos : 1;
@@ -678,10 +1235,21 @@ typedef struct {
uint8_t wrist_tilt_ia_ypos : 1;
uint8_t wrist_tilt_ia_xneg : 1;
uint8_t wrist_tilt_ia_xpos : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t wrist_tilt_ia_xpos : 1;
+ uint8_t wrist_tilt_ia_xneg : 1;
+ uint8_t wrist_tilt_ia_ypos : 1;
+ uint8_t wrist_tilt_ia_yneg : 1;
+ uint8_t wrist_tilt_ia_zpos : 1;
+ uint8_t wrist_tilt_ia_zneg : 1;
+ uint8_t not_used_01 : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_wrist_tilt_ia_t;
#define LSM6DSM_TAP_CFG 0x58U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lir : 1;
uint8_t tap_z_en : 1;
uint8_t tap_y_en : 1;
@@ -689,45 +1257,91 @@ typedef struct {
uint8_t slope_fds : 1;
uint8_t inact_en : 2;
uint8_t interrupts_enable : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t interrupts_enable : 1;
+ uint8_t inact_en : 2;
+ uint8_t slope_fds : 1;
+ uint8_t tap_x_en : 1;
+ uint8_t tap_y_en : 1;
+ uint8_t tap_z_en : 1;
+ uint8_t lir : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_tap_cfg_t;
#define LSM6DSM_TAP_THS_6D 0x59U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_ths : 5;
uint8_t sixd_ths : 2;
uint8_t d4d_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t d4d_en : 1;
+ uint8_t sixd_ths : 2;
+ uint8_t tap_ths : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_tap_ths_6d_t;
#define LSM6DSM_INT_DUR2 0x5AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shock : 2;
uint8_t quiet : 2;
uint8_t dur : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t dur : 4;
+ uint8_t quiet : 2;
+ uint8_t shock : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_int_dur2_t;
#define LSM6DSM_WAKE_UP_THS 0x5BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wk_ths : 6;
uint8_t not_used_01 : 1;
uint8_t single_double_tap : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t single_double_tap : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t wk_ths : 6;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_wake_up_ths_t;
#define LSM6DSM_WAKE_UP_DUR 0x5CU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sleep_dur : 4;
uint8_t timer_hr : 1;
uint8_t wake_dur : 2;
uint8_t ff_dur : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t ff_dur : 1;
+ uint8_t wake_dur : 2;
+ uint8_t timer_hr : 1;
+ uint8_t sleep_dur : 4;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_wake_up_dur_t;
#define LSM6DSM_FREE_FALL 0x5DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ths : 3;
uint8_t ff_dur : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t ff_dur : 5;
+ uint8_t ff_ths : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_free_fall_t;
#define LSM6DSM_MD1_CFG 0x5EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_timer : 1;
uint8_t int1_tilt : 1;
uint8_t int1_6d : 1;
@@ -736,10 +1350,22 @@ typedef struct {
uint8_t int1_wu : 1;
uint8_t int1_single_tap : 1;
uint8_t int1_inact_state : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_inact_state : 1;
+ uint8_t int1_single_tap : 1;
+ uint8_t int1_wu : 1;
+ uint8_t int1_ff : 1;
+ uint8_t int1_double_tap : 1;
+ uint8_t int1_6d : 1;
+ uint8_t int1_tilt : 1;
+ uint8_t int1_timer : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_md1_cfg_t;
#define LSM6DSM_MD2_CFG 0x5FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_iron : 1;
uint8_t int2_tilt : 1;
uint8_t int2_6d : 1;
@@ -748,15 +1374,27 @@ typedef struct {
uint8_t int2_wu : 1;
uint8_t int2_single_tap : 1;
uint8_t int2_inact_state : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_inact_state : 1;
+ uint8_t int2_single_tap : 1;
+ uint8_t int2_wu : 1;
+ uint8_t int2_ff : 1;
+ uint8_t int2_double_tap : 1;
+ uint8_t int2_6d : 1;
+ uint8_t int2_tilt : 1;
+ uint8_t int2_iron : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_md2_cfg_t;
#define LSM6DSM_MASTER_CMD_CODE 0x60U
-typedef struct {
+typedef struct
+{
uint8_t master_cmd_code : 8;
} lsm6dsm_master_cmd_code_t;
#define LSM6DSM_SENS_SYNC_SPI_ERROR_CODE 0x61U
-typedef struct {
+typedef struct
+{
uint8_t error_code : 8;
} lsm6dsm_sens_sync_spi_error_code_t;
@@ -767,134 +1405,241 @@ typedef struct {
#define LSM6DSM_OUT_MAG_RAW_Z_L 0x6AU
#define LSM6DSM_OUT_MAG_RAW_Z_H 0x6BU
#define LSM6DSM_INT_OIS 0x6FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 6;
uint8_t lvl2_ois : 1;
uint8_t int2_drdy_ois : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_drdy_ois : 1;
+ uint8_t lvl2_ois : 1;
+ uint8_t not_used_01 : 6;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_int_ois_t;
#define LSM6DSM_CTRL1_OIS 0x70U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ois_en_spi2 : 1;
uint8_t fs_g_ois : 3; /* fs_g_ois + fs_125_ois */
uint8_t mode4_en : 1;
uint8_t sim_ois : 1;
uint8_t lvl1_ois : 1;
uint8_t ble_ois : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t ble_ois : 1;
+ uint8_t lvl1_ois : 1;
+ uint8_t sim_ois : 1;
+ uint8_t mode4_en : 1;
+ uint8_t fs_g_ois : 3; /* fs_g_ois + fs_125_ois */
+ uint8_t ois_en_spi2 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_ctrl1_ois_t;
#define LSM6DSM_CTRL2_OIS 0x71U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t hp_en_ois : 1;
uint8_t ftype_ois : 2;
uint8_t not_used_01 : 1;
uint8_t hpm_ois : 2;
uint8_t not_used_02 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 2;
+ uint8_t hpm_ois : 2;
+ uint8_t not_used_01 : 1;
+ uint8_t ftype_ois : 2;
+ uint8_t hp_en_ois : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_ctrl2_ois_t;
#define LSM6DSM_CTRL3_OIS 0x72U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_ois_clampdis : 1;
uint8_t st_ois : 2;
uint8_t filter_xl_conf_ois : 2;
uint8_t fs_xl_ois : 2;
uint8_t den_lh_ois : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t den_lh_ois : 1;
+ uint8_t fs_xl_ois : 2;
+ uint8_t filter_xl_conf_ois : 2;
+ uint8_t st_ois : 2;
+ uint8_t st_ois_clampdis : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_ctrl3_ois_t;
#define LSM6DSM_X_OFS_USR 0x73U
#define LSM6DSM_Y_OFS_USR 0x74U
#define LSM6DSM_Z_OFS_USR 0x75U
#define LSM6DSM_SLV0_ADD 0x02U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t rw_0 : 1;
uint8_t slave0_add : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave0_add : 7;
+ uint8_t rw_0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_slv0_add_t;
#define LSM6DSM_SLV0_SUBADD 0x03U
-typedef struct {
+typedef struct
+{
uint8_t slave0_reg : 8;
} lsm6dsm_slv0_subadd_t;
#define LSM6DSM_SLAVE0_CONFIG 0x04U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave0_numop : 3;
uint8_t src_mode : 1;
uint8_t aux_sens_on : 2;
uint8_t slave0_rate : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave0_rate : 2;
+ uint8_t aux_sens_on : 2;
+ uint8_t src_mode : 1;
+ uint8_t slave0_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_slave0_config_t;
#define LSM6DSM_SLV1_ADD 0x05U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_1 : 1;
uint8_t slave1_add : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave1_add : 7;
+ uint8_t r_1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_slv1_add_t;
#define LSM6DSM_SLV1_SUBADD 0x06U
-typedef struct {
+typedef struct
+{
uint8_t slave1_reg : 8;
} lsm6dsm_slv1_subadd_t;
#define LSM6DSM_SLAVE1_CONFIG 0x07U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave1_numop : 3;
uint8_t not_used_01 : 2;
uint8_t write_once : 1;
uint8_t slave1_rate : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave1_rate : 2;
+ uint8_t write_once : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t slave1_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_slave1_config_t;
#define LSM6DSM_SLV2_ADD 0x08U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_2 : 1;
uint8_t slave2_add : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave2_add : 7;
+ uint8_t r_2 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_slv2_add_t;
#define LSM6DSM_SLV2_SUBADD 0x09U
-typedef struct {
+typedef struct
+{
uint8_t slave2_reg : 8;
} lsm6dsm_slv2_subadd_t;
#define LSM6DSM_SLAVE2_CONFIG 0x0AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave2_numop : 3;
uint8_t not_used_01 : 3;
uint8_t slave2_rate : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave2_rate : 2;
+ uint8_t not_used_01 : 3;
+ uint8_t slave2_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_slave2_config_t;
#define LSM6DSM_SLV3_ADD 0x0BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_3 : 1;
uint8_t slave3_add : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave3_add : 7;
+ uint8_t r_3 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_slv3_add_t;
#define LSM6DSM_SLV3_SUBADD 0x0CU
-typedef struct {
+typedef struct
+{
uint8_t slave3_reg : 8;
} lsm6dsm_slv3_subadd_t;
#define LSM6DSM_SLAVE3_CONFIG 0x0DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave3_numop : 3;
uint8_t not_used_01 : 3;
uint8_t slave3_rate : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave3_rate : 2;
+ uint8_t not_used_01 : 3;
+ uint8_t slave3_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_slave3_config_t;
#define LSM6DSM_DATAWRITE_SRC_MODE_SUB_SLV0 0x0EU
-typedef struct {
+typedef struct
+{
uint8_t slave_dataw : 8;
} lsm6dsm_datawrite_src_mode_sub_slv0_t;
#define LSM6DSM_CONFIG_PEDO_THS_MIN 0x0FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths_min : 5;
uint8_t not_used_01 : 2;
uint8_t pedo_fs : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t pedo_fs : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t ths_min : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_config_pedo_ths_min_t;
#define LSM6DSM_SM_THS 0x13U
#define LSM6DSM_PEDO_DEB_REG 0x14U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t deb_step : 3;
uint8_t deb_time : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t deb_time : 5;
+ uint8_t deb_step : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_pedo_deb_reg_t;
#define LSM6DSM_STEP_COUNT_DELTA 0x15U
@@ -916,7 +1661,9 @@ typedef struct {
#define LSM6DSM_A_WRIST_TILT_LAT 0x50U
#define LSM6DSM_A_WRIST_TILT_THS 0x54U
#define LSM6DSM_A_WRIST_TILT_MASK 0x59U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t wrist_tilt_mask_zneg : 1;
uint8_t wrist_tilt_mask_zpos : 1;
@@ -924,13 +1671,22 @@ typedef struct {
uint8_t wrist_tilt_mask_ypos : 1;
uint8_t wrist_tilt_mask_xneg : 1;
uint8_t wrist_tilt_mask_xpos : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t wrist_tilt_mask_xpos : 1;
+ uint8_t wrist_tilt_mask_xneg : 1;
+ uint8_t wrist_tilt_mask_ypos : 1;
+ uint8_t wrist_tilt_mask_yneg : 1;
+ uint8_t wrist_tilt_mask_zpos : 1;
+ uint8_t wrist_tilt_mask_zneg : 1;
+ uint8_t not_used_01 : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsm_a_wrist_tilt_mask_t;
/**
* @defgroup LSM6DSM_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -938,7 +1694,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
lsm6dsm_func_cfg_access_t func_cfg_access;
lsm6dsm_sensor_sync_time_frame_t sensor_sync_time_frame;
lsm6dsm_sensor_sync_res_ratio_t sensor_sync_res_ratio;
@@ -1017,7 +1774,8 @@ typedef union{
lsm6dsm_slv3_add_t slv3_add;
lsm6dsm_slv3_subadd_t slv3_subadd;
lsm6dsm_slave3_config_t slave3_config;
- lsm6dsm_datawrite_src_mode_sub_slv0_t datawrite_src_mode_sub_slv0;
+ lsm6dsm_datawrite_src_mode_sub_slv0_t
+ datawrite_src_mode_sub_slv0;
lsm6dsm_config_pedo_ths_min_t config_pedo_ths_min;
lsm6dsm_pedo_deb_reg_t pedo_deb_reg;
lsm6dsm_a_wrist_tilt_mask_t a_wrist_tilt_mask;
@@ -1030,34 +1788,40 @@ typedef union{
*
*/
-int32_t lsm6dsm_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lsm6dsm_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t lsm6dsm_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lsm6dsm_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-extern float_t lsm6dsm_from_fs2g_to_mg(int16_t lsb);
-extern float_t lsm6dsm_from_fs4g_to_mg(int16_t lsb);
-extern float_t lsm6dsm_from_fs8g_to_mg(int16_t lsb);
-extern float_t lsm6dsm_from_fs16g_to_mg(int16_t lsb);
+float_t lsm6dsm_from_fs2g_to_mg(int16_t lsb);
+float_t lsm6dsm_from_fs4g_to_mg(int16_t lsb);
+float_t lsm6dsm_from_fs8g_to_mg(int16_t lsb);
+float_t lsm6dsm_from_fs16g_to_mg(int16_t lsb);
-extern float_t lsm6dsm_from_fs125dps_to_mdps(int16_t lsb);
-extern float_t lsm6dsm_from_fs250dps_to_mdps(int16_t lsb);
-extern float_t lsm6dsm_from_fs500dps_to_mdps(int16_t lsb);
-extern float_t lsm6dsm_from_fs1000dps_to_mdps(int16_t lsb);
-extern float_t lsm6dsm_from_fs2000dps_to_mdps(int16_t lsb);
+float_t lsm6dsm_from_fs125dps_to_mdps(int16_t lsb);
+float_t lsm6dsm_from_fs250dps_to_mdps(int16_t lsb);
+float_t lsm6dsm_from_fs500dps_to_mdps(int16_t lsb);
+float_t lsm6dsm_from_fs1000dps_to_mdps(int16_t lsb);
+float_t lsm6dsm_from_fs2000dps_to_mdps(int16_t lsb);
-extern float_t lsm6dsm_from_lsb_to_celsius(int16_t lsb);
+float_t lsm6dsm_from_lsb_to_celsius(int16_t lsb);
-typedef enum {
+typedef enum
+{
LSM6DSM_2g = 0,
LSM6DSM_16g = 1,
LSM6DSM_4g = 2,
LSM6DSM_8g = 3,
} lsm6dsm_fs_xl_t;
-int32_t lsm6dsm_xl_full_scale_set(stmdev_ctx_t *ctx, lsm6dsm_fs_xl_t val);
-int32_t lsm6dsm_xl_full_scale_get(stmdev_ctx_t *ctx, lsm6dsm_fs_xl_t *val);
+int32_t lsm6dsm_xl_full_scale_set(stmdev_ctx_t *ctx,
+ lsm6dsm_fs_xl_t val);
+int32_t lsm6dsm_xl_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6dsm_fs_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_XL_ODR_OFF = 0,
LSM6DSM_XL_ODR_12Hz5 = 1,
LSM6DSM_XL_ODR_26Hz = 2,
@@ -1071,20 +1835,26 @@ typedef enum {
LSM6DSM_XL_ODR_6k66Hz = 10,
LSM6DSM_XL_ODR_1Hz6 = 11,
} lsm6dsm_odr_xl_t;
-int32_t lsm6dsm_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6dsm_odr_xl_t val);
-int32_t lsm6dsm_xl_data_rate_get(stmdev_ctx_t *ctx, lsm6dsm_odr_xl_t *val);
+int32_t lsm6dsm_xl_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dsm_odr_xl_t val);
+int32_t lsm6dsm_xl_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dsm_odr_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_250dps = 0,
LSM6DSM_125dps = 1,
LSM6DSM_500dps = 2,
LSM6DSM_1000dps = 4,
LSM6DSM_2000dps = 6,
} lsm6dsm_fs_g_t;
-int32_t lsm6dsm_gy_full_scale_set(stmdev_ctx_t *ctx, lsm6dsm_fs_g_t val);
-int32_t lsm6dsm_gy_full_scale_get(stmdev_ctx_t *ctx, lsm6dsm_fs_g_t *val);
+int32_t lsm6dsm_gy_full_scale_set(stmdev_ctx_t *ctx,
+ lsm6dsm_fs_g_t val);
+int32_t lsm6dsm_gy_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6dsm_fs_g_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_GY_ODR_OFF = 0,
LSM6DSM_GY_ODR_12Hz5 = 1,
LSM6DSM_GY_ODR_26Hz = 2,
@@ -1097,13 +1867,17 @@ typedef enum {
LSM6DSM_GY_ODR_3k33Hz = 9,
LSM6DSM_GY_ODR_6k66Hz = 10,
} lsm6dsm_odr_g_t;
-int32_t lsm6dsm_gy_data_rate_set(stmdev_ctx_t *ctx, lsm6dsm_odr_g_t val);
-int32_t lsm6dsm_gy_data_rate_get(stmdev_ctx_t *ctx, lsm6dsm_odr_g_t *val);
+int32_t lsm6dsm_gy_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dsm_odr_g_t val);
+int32_t lsm6dsm_gy_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dsm_odr_g_t *val);
int32_t lsm6dsm_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsm_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsm_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_LSb_1mg = 0,
LSM6DSM_LSb_16mg = 1,
} lsm6dsm_usr_off_w_t;
@@ -1112,7 +1886,8 @@ int32_t lsm6dsm_xl_offset_weight_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_xl_offset_weight_get(stmdev_ctx_t *ctx,
lsm6dsm_usr_off_w_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_XL_HIGH_PERFORMANCE = 0,
LSM6DSM_XL_NORMAL = 1,
} lsm6dsm_xl_hm_mode_t;
@@ -1121,7 +1896,8 @@ int32_t lsm6dsm_xl_power_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_xl_power_mode_get(stmdev_ctx_t *ctx,
lsm6dsm_xl_hm_mode_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_STAT_RND_DISABLE = 0,
LSM6DSM_STAT_RND_ENABLE = 1,
} lsm6dsm_rounding_status_t;
@@ -1130,7 +1906,8 @@ int32_t lsm6dsm_rounding_on_status_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_rounding_on_status_get(stmdev_ctx_t *ctx,
lsm6dsm_rounding_status_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_GY_HIGH_PERFORMANCE = 0,
LSM6DSM_GY_NORMAL = 1,
} lsm6dsm_g_hm_mode_t;
@@ -1139,7 +1916,8 @@ int32_t lsm6dsm_gy_power_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_gy_power_mode_get(stmdev_ctx_t *ctx,
lsm6dsm_g_hm_mode_t *val);
-typedef struct {
+typedef struct
+{
lsm6dsm_wake_up_src_t wake_up_src;
lsm6dsm_tap_src_t tap_src;
lsm6dsm_d6d_src_t d6d_src;
@@ -1152,27 +1930,35 @@ typedef struct {
int32_t lsm6dsm_all_sources_get(stmdev_ctx_t *ctx,
lsm6dsm_all_sources_t *val);
-int32_t lsm6dsm_status_reg_get(stmdev_ctx_t *ctx, lsm6dsm_status_reg_t *val);
+int32_t lsm6dsm_status_reg_get(stmdev_ctx_t *ctx,
+ lsm6dsm_status_reg_t *val);
-int32_t lsm6dsm_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsm_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsm_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsm_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsm_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsm_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dsm_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t lsm6dsm_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t lsm6dsm_timestamp_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsm_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_LSB_6ms4 = 0,
LSM6DSM_LSB_25us = 1,
} lsm6dsm_timer_hr_t;
-int32_t lsm6dsm_timestamp_res_set(stmdev_ctx_t *ctx, lsm6dsm_timer_hr_t val);
-int32_t lsm6dsm_timestamp_res_get(stmdev_ctx_t *ctx, lsm6dsm_timer_hr_t *val);
+int32_t lsm6dsm_timestamp_res_set(stmdev_ctx_t *ctx,
+ lsm6dsm_timer_hr_t val);
+int32_t lsm6dsm_timestamp_res_get(stmdev_ctx_t *ctx,
+ lsm6dsm_timer_hr_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_ROUND_DISABLE = 0,
LSM6DSM_ROUND_XL = 1,
LSM6DSM_ROUND_GY = 2,
@@ -1182,27 +1968,34 @@ typedef enum {
LSM6DSM_ROUND_GY_XL_SH1_TO_SH12 = 6,
LSM6DSM_ROUND_GY_XL_SH1_TO_SH6 = 7,
} lsm6dsm_rounding_t;
-int32_t lsm6dsm_rounding_mode_set(stmdev_ctx_t *ctx, lsm6dsm_rounding_t val);
-int32_t lsm6dsm_rounding_mode_get(stmdev_ctx_t *ctx, lsm6dsm_rounding_t *val);
+int32_t lsm6dsm_rounding_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsm_rounding_t val);
+int32_t lsm6dsm_rounding_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsm_rounding_t *val);
-int32_t lsm6dsm_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsm_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsm_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsm_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t lsm6dsm_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t lsm6dsm_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val);
-int32_t lsm6dsm_mag_calibrated_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsm_mag_calibrated_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
int32_t lsm6dsm_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer,
uint8_t len);
-typedef enum {
+typedef enum
+{
LSM6DSM_USER_BANK = 0,
LSM6DSM_BANK_A = 4,
LSM6DSM_BANK_B = 5,
} lsm6dsm_func_cfg_en_t;
-int32_t lsm6dsm_mem_bank_set(stmdev_ctx_t *ctx, lsm6dsm_func_cfg_en_t val);
-int32_t lsm6dsm_mem_bank_get(stmdev_ctx_t *ctx, lsm6dsm_func_cfg_en_t *val);
+int32_t lsm6dsm_mem_bank_set(stmdev_ctx_t *ctx,
+ lsm6dsm_func_cfg_en_t val);
+int32_t lsm6dsm_mem_bank_get(stmdev_ctx_t *ctx,
+ lsm6dsm_func_cfg_en_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_DRDY_LATCHED = 0,
LSM6DSM_DRDY_PULSED = 1,
} lsm6dsm_drdy_pulsed_g_t;
@@ -1215,12 +2008,14 @@ int32_t lsm6dsm_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t lsm6dsm_reset_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsm_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_LSB_AT_LOW_ADD = 0,
LSM6DSM_MSB_AT_LOW_ADD = 1,
} lsm6dsm_ble_t;
int32_t lsm6dsm_data_format_set(stmdev_ctx_t *ctx, lsm6dsm_ble_t val);
-int32_t lsm6dsm_data_format_get(stmdev_ctx_t *ctx, lsm6dsm_ble_t *val);
+int32_t lsm6dsm_data_format_get(stmdev_ctx_t *ctx,
+ lsm6dsm_ble_t *val);
int32_t lsm6dsm_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsm_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1228,26 +2023,35 @@ int32_t lsm6dsm_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsm_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsm_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_XL_ST_DISABLE = 0,
LSM6DSM_XL_ST_POSITIVE = 1,
LSM6DSM_XL_ST_NEGATIVE = 2,
} lsm6dsm_st_xl_t;
-int32_t lsm6dsm_xl_self_test_set(stmdev_ctx_t *ctx, lsm6dsm_st_xl_t val);
-int32_t lsm6dsm_xl_self_test_get(stmdev_ctx_t *ctx, lsm6dsm_st_xl_t *val);
+int32_t lsm6dsm_xl_self_test_set(stmdev_ctx_t *ctx,
+ lsm6dsm_st_xl_t val);
+int32_t lsm6dsm_xl_self_test_get(stmdev_ctx_t *ctx,
+ lsm6dsm_st_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_GY_ST_DISABLE = 0,
LSM6DSM_GY_ST_POSITIVE = 1,
LSM6DSM_GY_ST_NEGATIVE = 3,
} lsm6dsm_st_g_t;
-int32_t lsm6dsm_gy_self_test_set(stmdev_ctx_t *ctx, lsm6dsm_st_g_t val);
-int32_t lsm6dsm_gy_self_test_get(stmdev_ctx_t *ctx, lsm6dsm_st_g_t *val);
-
-int32_t lsm6dsm_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsm_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val);
-
-typedef enum {
+int32_t lsm6dsm_gy_self_test_set(stmdev_ctx_t *ctx,
+ lsm6dsm_st_g_t val);
+int32_t lsm6dsm_gy_self_test_get(stmdev_ctx_t *ctx,
+ lsm6dsm_st_g_t *val);
+
+int32_t lsm6dsm_filter_settling_mask_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsm_filter_settling_mask_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+typedef enum
+{
LSM6DSM_USE_SLOPE = 0,
LSM6DSM_USE_HPF = 1,
} lsm6dsm_slope_fds_t;
@@ -1256,7 +2060,8 @@ int32_t lsm6dsm_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
lsm6dsm_slope_fds_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_XL_ANA_BW_1k5Hz = 0,
LSM6DSM_XL_ANA_BW_400Hz = 1,
} lsm6dsm_bw0_xl_t;
@@ -1265,7 +2070,8 @@ int32_t lsm6dsm_xl_filter_analog_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_xl_filter_analog_get(stmdev_ctx_t *ctx,
lsm6dsm_bw0_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_XL_LP1_ODR_DIV_2 = 0,
LSM6DSM_XL_LP1_ODR_DIV_4 = 1,
LSM6DSM_XL_LP1_NA = 2, /* ERROR CODE */
@@ -1275,7 +2081,8 @@ int32_t lsm6dsm_xl_lp1_bandwidth_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_xl_lp1_bandwidth_get(stmdev_ctx_t *ctx,
lsm6dsm_lpf1_bw_sel_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_50 = 0x00,
LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_100 = 0x01,
LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_9 = 0x02,
@@ -1292,9 +2099,11 @@ int32_t lsm6dsm_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx,
lsm6dsm_input_composite_t *val);
int32_t lsm6dsm_xl_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsm_xl_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsm_xl_reference_mode_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_XL_HP_ODR_DIV_4 = 0x00, /* Slope filter */
LSM6DSM_XL_HP_ODR_DIV_100 = 0x01,
LSM6DSM_XL_HP_ODR_DIV_9 = 0x02,
@@ -1306,7 +2115,8 @@ int32_t lsm6dsm_xl_hp_bandwidth_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_xl_hp_bandwidth_get(stmdev_ctx_t *ctx,
lsm6dsm_hpcf_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_XL_UI_LP1_ODR_DIV_2 = 0,
LSM6DSM_XL_UI_LP1_ODR_DIV_4 = 1,
LSM6DSM_XL_UI_LP1_NA = 2,
@@ -1319,7 +2129,8 @@ int32_t lsm6dsm_xl_ui_lp1_bandwidth_get(stmdev_ctx_t *ctx,
int32_t lsm6dsm_xl_ui_slope_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsm_xl_ui_slope_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_AUX_LP_LIGHT = 2,
LSM6DSM_AUX_LP_NORMAL = 3,
LSM6DSM_AUX_LP_STRONG = 0,
@@ -1330,7 +2141,8 @@ int32_t lsm6dsm_xl_aux_lp_bandwidth_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_xl_aux_lp_bandwidth_get(stmdev_ctx_t *ctx,
lsm6dsm_filter_xl_conf_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_LP2_ONLY = 0x00,
LSM6DSM_HP_16mHz_LP2 = 0x80,
@@ -1349,14 +2161,15 @@ typedef enum {
LSM6DSM_HP_1Hz04_LP1_AGGRESSIVE = 0xBB,
} lsm6dsm_lpf1_sel_g_t;
int32_t lsm6dsm_gy_band_pass_set(stmdev_ctx_t *ctx,
- lsm6dsm_lpf1_sel_g_t val);
+ lsm6dsm_lpf1_sel_g_t val);
int32_t lsm6dsm_gy_band_pass_get(stmdev_ctx_t *ctx,
- lsm6dsm_lpf1_sel_g_t *val);
+ lsm6dsm_lpf1_sel_g_t *val);
int32_t lsm6dsm_gy_ui_high_pass_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsm_gy_ui_high_pass_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_HP_DISABLE_LP_173Hz = 0x02,
LSM6DSM_HP_DISABLE_LP_237Hz = 0x01,
LSM6DSM_HP_DISABLE_LP_351Hz = 0x00,
@@ -1375,13 +2188,17 @@ int32_t lsm6dsm_gy_aux_bandwidth_get(stmdev_ctx_t *ctx,
int32_t lsm6dsm_aux_status_reg_get(stmdev_ctx_t *ctx,
lsm6dsm_status_spiaux_t *val);
-int32_t lsm6dsm_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsm_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsm_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsm_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsm_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsm_aux_gy_flag_settling_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_AUX_DEN_DISABLE = 0,
LSM6DSM_AUX_DEN_LEVEL_LATCH = 3,
LSM6DSM_AUX_DEN_LEVEL_TRIG = 2,
@@ -1394,15 +2211,19 @@ int32_t lsm6dsm_aux_den_mode_get(stmdev_ctx_t *ctx,
int32_t lsm6dsm_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsm_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_AUX_DISABLE = 0,
LSM6DSM_MODE_3_GY = 1,
LSM6DSM_MODE_4_GY_XL = 3,
} lsm6dsm_ois_en_spi2_t;
-int32_t lsm6dsm_aux_mode_set(stmdev_ctx_t *ctx, lsm6dsm_ois_en_spi2_t val);
-int32_t lsm6dsm_aux_mode_get(stmdev_ctx_t *ctx, lsm6dsm_ois_en_spi2_t *val);
+int32_t lsm6dsm_aux_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsm_ois_en_spi2_t val);
+int32_t lsm6dsm_aux_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsm_ois_en_spi2_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_250dps_AUX = 0,
LSM6DSM_125dps_AUX = 1,
LSM6DSM_500dps_AUX = 2,
@@ -1414,14 +2235,18 @@ int32_t lsm6dsm_aux_gy_full_scale_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_aux_gy_full_scale_get(stmdev_ctx_t *ctx,
lsm6dsm_fs_g_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_AUX_SPI_4_WIRE = 0,
LSM6DSM_AUX_SPI_3_WIRE = 1,
} lsm6dsm_sim_ois_t;
-int32_t lsm6dsm_aux_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsm_sim_ois_t val);
-int32_t lsm6dsm_aux_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsm_sim_ois_t *val);
+int32_t lsm6dsm_aux_spi_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsm_sim_ois_t val);
+int32_t lsm6dsm_aux_spi_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsm_sim_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_AUX_LSB_AT_LOW_ADD = 0,
LSM6DSM_AUX_MSB_AT_LOW_ADD = 1,
} lsm6dsm_ble_ois_t;
@@ -1430,7 +2255,8 @@ int32_t lsm6dsm_aux_data_format_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_aux_data_format_get(stmdev_ctx_t *ctx,
lsm6dsm_ble_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_ENABLE_CLAMP = 0,
LSM6DSM_DISABLE_CLAMP = 1,
} lsm6dsm_st_ois_clampdis_t;
@@ -1439,7 +2265,8 @@ int32_t lsm6dsm_aux_gy_clamp_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_aux_gy_clamp_get(stmdev_ctx_t *ctx,
lsm6dsm_st_ois_clampdis_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_AUX_GY_DISABLE = 0,
LSM6DSM_AUX_GY_POS = 1,
LSM6DSM_AUX_GY_NEG = 3,
@@ -1449,7 +2276,8 @@ int32_t lsm6dsm_aux_gy_self_test_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_aux_gy_self_test_get(stmdev_ctx_t *ctx,
lsm6dsm_st_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_AUX_2g = 0,
LSM6DSM_AUX_16g = 1,
LSM6DSM_AUX_4g = 2,
@@ -1460,7 +2288,8 @@ int32_t lsm6dsm_aux_xl_full_scale_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_aux_xl_full_scale_get(stmdev_ctx_t *ctx,
lsm6dsm_fs_xl_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_AUX_DEN_ACTIVE_LOW = 0,
LSM6DSM_AUX_DEN_ACTIVE_HIGH = 1,
} lsm6dsm_den_lh_ois_t;
@@ -1469,14 +2298,16 @@ int32_t lsm6dsm_aux_den_polarity_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_aux_den_polarity_get(stmdev_ctx_t *ctx,
lsm6dsm_den_lh_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_SPI_4_WIRE = 0,
LSM6DSM_SPI_3_WIRE = 1,
} lsm6dsm_sim_t;
int32_t lsm6dsm_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsm_sim_t val);
int32_t lsm6dsm_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsm_sim_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_I2C_ENABLE = 0,
LSM6DSM_I2C_DISABLE = 1,
} lsm6dsm_i2c_disable_t;
@@ -1485,7 +2316,8 @@ int32_t lsm6dsm_i2c_interface_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_i2c_interface_get(stmdev_ctx_t *ctx,
lsm6dsm_i2c_disable_t *val);
-typedef struct {
+typedef struct
+{
uint8_t int1_drdy_xl : 1;
uint8_t int1_drdy_g : 1;
uint8_t int1_boot : 1;
@@ -1510,7 +2342,8 @@ int32_t lsm6dsm_pin_int1_route_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_pin_int1_route_get(stmdev_ctx_t *ctx,
lsm6dsm_int1_route_t *val);
-typedef struct{
+typedef struct
+{
uint8_t int2_drdy_xl : 1;
uint8_t int2_drdy_g : 1;
uint8_t int2_drdy_temp : 1;
@@ -1534,29 +2367,36 @@ int32_t lsm6dsm_pin_int2_route_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_pin_int2_route_get(stmdev_ctx_t *ctx,
lsm6dsm_int2_route_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_PUSH_PULL = 0,
LSM6DSM_OPEN_DRAIN = 1,
} lsm6dsm_pp_od_t;
int32_t lsm6dsm_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsm_pp_od_t val);
int32_t lsm6dsm_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsm_pp_od_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_ACTIVE_HIGH = 0,
LSM6DSM_ACTIVE_LOW = 1,
} lsm6dsm_h_lactive_t;
-int32_t lsm6dsm_pin_polarity_set(stmdev_ctx_t *ctx, lsm6dsm_h_lactive_t val);
-int32_t lsm6dsm_pin_polarity_get(stmdev_ctx_t *ctx, lsm6dsm_h_lactive_t *val);
+int32_t lsm6dsm_pin_polarity_set(stmdev_ctx_t *ctx,
+ lsm6dsm_h_lactive_t val);
+int32_t lsm6dsm_pin_polarity_get(stmdev_ctx_t *ctx,
+ lsm6dsm_h_lactive_t *val);
int32_t lsm6dsm_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsm_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_INT_PULSED = 0,
LSM6DSM_INT_LATCHED = 1,
} lsm6dsm_lir_t;
-int32_t lsm6dsm_int_notification_set(stmdev_ctx_t *ctx, lsm6dsm_lir_t val);
-int32_t lsm6dsm_int_notification_get(stmdev_ctx_t *ctx, lsm6dsm_lir_t *val);
+int32_t lsm6dsm_int_notification_set(stmdev_ctx_t *ctx,
+ lsm6dsm_lir_t val);
+int32_t lsm6dsm_int_notification_get(stmdev_ctx_t *ctx,
+ lsm6dsm_lir_t *val);
int32_t lsm6dsm_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsm_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1567,28 +2407,38 @@ int32_t lsm6dsm_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsm_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsm_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_PROPERTY_DISABLE = 0,
LSM6DSM_XL_12Hz5_GY_NOT_AFFECTED = 1,
LSM6DSM_XL_12Hz5_GY_SLEEP = 2,
LSM6DSM_XL_12Hz5_GY_PD = 3,
} lsm6dsm_inact_en_t;
-int32_t lsm6dsm_act_mode_set(stmdev_ctx_t *ctx, lsm6dsm_inact_en_t val);
-int32_t lsm6dsm_act_mode_get(stmdev_ctx_t *ctx, lsm6dsm_inact_en_t *val);
+int32_t lsm6dsm_act_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsm_inact_en_t val);
+int32_t lsm6dsm_act_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsm_inact_en_t *val);
int32_t lsm6dsm_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsm_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dsm_tap_src_get(stmdev_ctx_t *ctx, lsm6dsm_tap_src_t *val);
+int32_t lsm6dsm_tap_src_get(stmdev_ctx_t *ctx,
+ lsm6dsm_tap_src_t *val);
-int32_t lsm6dsm_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsm_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsm_tap_detection_on_z_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsm_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsm_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsm_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsm_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsm_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsm_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsm_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsm_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsm_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dsm_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsm_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1602,7 +2452,8 @@ int32_t lsm6dsm_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsm_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsm_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_ONLY_SINGLE = 0,
LSM6DSM_BOTH_SINGLE_DOUBLE = 1,
} lsm6dsm_single_double_tap_t;
@@ -1611,7 +2462,8 @@ int32_t lsm6dsm_tap_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_tap_mode_get(stmdev_ctx_t *ctx,
lsm6dsm_single_double_tap_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_ODR_DIV_2_FEED = 0,
LSM6DSM_LPF2_FEED = 1,
} lsm6dsm_low_pass_on_6d_t;
@@ -1620,14 +2472,17 @@ int32_t lsm6dsm_6d_feed_data_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_6d_feed_data_get(stmdev_ctx_t *ctx,
lsm6dsm_low_pass_on_6d_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_DEG_80 = 0,
LSM6DSM_DEG_70 = 1,
LSM6DSM_DEG_60 = 2,
LSM6DSM_DEG_50 = 3,
} lsm6dsm_sixd_ths_t;
-int32_t lsm6dsm_6d_threshold_set(stmdev_ctx_t *ctx, lsm6dsm_sixd_ths_t val);
-int32_t lsm6dsm_6d_threshold_get(stmdev_ctx_t *ctx, lsm6dsm_sixd_ths_t *val);
+int32_t lsm6dsm_6d_threshold_set(stmdev_ctx_t *ctx,
+ lsm6dsm_sixd_ths_t val);
+int32_t lsm6dsm_6d_threshold_get(stmdev_ctx_t *ctx,
+ lsm6dsm_sixd_ths_t *val);
int32_t lsm6dsm_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsm_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1635,7 +2490,8 @@ int32_t lsm6dsm_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsm_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsm_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_FF_TSH_156mg = 0,
LSM6DSM_FF_TSH_219mg = 1,
LSM6DSM_FF_TSH_250mg = 2,
@@ -1645,8 +2501,10 @@ typedef enum {
LSM6DSM_FF_TSH_469mg = 6,
LSM6DSM_FF_TSH_500mg = 7,
} lsm6dsm_ff_ths_t;
-int32_t lsm6dsm_ff_threshold_set(stmdev_ctx_t *ctx, lsm6dsm_ff_ths_t val);
-int32_t lsm6dsm_ff_threshold_get(stmdev_ctx_t *ctx, lsm6dsm_ff_ths_t *val);
+int32_t lsm6dsm_ff_threshold_set(stmdev_ctx_t *ctx,
+ lsm6dsm_ff_ths_t val);
+int32_t lsm6dsm_ff_threshold_get(stmdev_ctx_t *ctx,
+ lsm6dsm_ff_ths_t *val);
int32_t lsm6dsm_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val);
int32_t lsm6dsm_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val);
@@ -1661,7 +2519,8 @@ int32_t lsm6dsm_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val);
int32_t lsm6dsm_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsm_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_TRG_XL_GY_DRDY = 0,
LSM6DSM_TRG_STEP_DETECT = 1,
LSM6DSM_TRG_SH_DRDY = 2,
@@ -1676,7 +2535,8 @@ int32_t lsm6dsm_fifo_pedo_and_timestamp_batch_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_fifo_pedo_and_timestamp_batch_get(stmdev_ctx_t *ctx,
uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_FIFO_XL_DISABLE = 0,
LSM6DSM_FIFO_XL_NO_DEC = 1,
LSM6DSM_FIFO_XL_DEC_2 = 2,
@@ -1691,7 +2551,8 @@ int32_t lsm6dsm_fifo_xl_batch_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_fifo_xl_batch_get(stmdev_ctx_t *ctx,
lsm6dsm_dec_fifo_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_FIFO_GY_DISABLE = 0,
LSM6DSM_FIFO_GY_NO_DEC = 1,
LSM6DSM_FIFO_GY_DEC_2 = 2,
@@ -1706,7 +2567,8 @@ int32_t lsm6dsm_fifo_gy_batch_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_fifo_gy_batch_get(stmdev_ctx_t *ctx,
lsm6dsm_dec_fifo_gyro_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_FIFO_DS3_DISABLE = 0,
LSM6DSM_FIFO_DS3_NO_DEC = 1,
LSM6DSM_FIFO_DS3_DEC_2 = 2,
@@ -1721,7 +2583,8 @@ int32_t lsm6dsm_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx,
lsm6dsm_dec_ds3_fifo_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_FIFO_DS4_DISABLE = 0,
LSM6DSM_FIFO_DS4_NO_DEC = 1,
LSM6DSM_FIFO_DS4_DEC_2 = 2,
@@ -1736,23 +2599,29 @@ int32_t lsm6dsm_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx,
lsm6dsm_dec_ds4_fifo_t *val);
-int32_t lsm6dsm_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsm_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsm_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsm_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dsm_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsm_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_BYPASS_MODE = 0,
LSM6DSM_FIFO_MODE = 1,
LSM6DSM_STREAM_TO_FIFO_MODE = 3,
LSM6DSM_BYPASS_TO_STREAM_MODE = 4,
LSM6DSM_STREAM_MODE = 6,
} lsm6dsm_fifo_mode_t;
-int32_t lsm6dsm_fifo_mode_set(stmdev_ctx_t *ctx, lsm6dsm_fifo_mode_t val);
-int32_t lsm6dsm_fifo_mode_get(stmdev_ctx_t *ctx, lsm6dsm_fifo_mode_t *val);
+int32_t lsm6dsm_fifo_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsm_fifo_mode_t val);
+int32_t lsm6dsm_fifo_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsm_fifo_mode_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_FIFO_DISABLE = 0,
LSM6DSM_FIFO_12Hz5 = 1,
LSM6DSM_FIFO_26Hz = 2,
@@ -1770,30 +2639,39 @@ int32_t lsm6dsm_fifo_data_rate_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_fifo_data_rate_get(stmdev_ctx_t *ctx,
lsm6dsm_odr_fifo_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_DEN_ACT_LOW = 0,
LSM6DSM_DEN_ACT_HIGH = 1,
} lsm6dsm_den_lh_t;
-int32_t lsm6dsm_den_polarity_set(stmdev_ctx_t *ctx, lsm6dsm_den_lh_t val);
-int32_t lsm6dsm_den_polarity_get(stmdev_ctx_t *ctx, lsm6dsm_den_lh_t *val);
+int32_t lsm6dsm_den_polarity_set(stmdev_ctx_t *ctx,
+ lsm6dsm_den_lh_t val);
+int32_t lsm6dsm_den_polarity_get(stmdev_ctx_t *ctx,
+ lsm6dsm_den_lh_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_DEN_DISABLE = 0,
LSM6DSM_LEVEL_FIFO = 6,
LSM6DSM_LEVEL_LETCHED = 3,
LSM6DSM_LEVEL_TRIGGER = 2,
LSM6DSM_EDGE_TRIGGER = 4,
} lsm6dsm_den_mode_t;
-int32_t lsm6dsm_den_mode_set(stmdev_ctx_t *ctx, lsm6dsm_den_mode_t val);
-int32_t lsm6dsm_den_mode_get(stmdev_ctx_t *ctx, lsm6dsm_den_mode_t *val);
+int32_t lsm6dsm_den_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsm_den_mode_t val);
+int32_t lsm6dsm_den_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsm_den_mode_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_STAMP_IN_GY_DATA = 0,
LSM6DSM_STAMP_IN_XL_DATA = 1,
LSM6DSM_STAMP_IN_GY_XL_DATA = 2,
} lsm6dsm_den_xl_en_t;
-int32_t lsm6dsm_den_enable_set(stmdev_ctx_t *ctx, lsm6dsm_den_xl_en_t val);
-int32_t lsm6dsm_den_enable_get(stmdev_ctx_t *ctx, lsm6dsm_den_xl_en_t *val);
+int32_t lsm6dsm_den_enable_set(stmdev_ctx_t *ctx,
+ lsm6dsm_den_xl_en_t val);
+int32_t lsm6dsm_den_enable_get(stmdev_ctx_t *ctx,
+ lsm6dsm_den_xl_en_t *val);
int32_t lsm6dsm_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsm_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1813,7 +2691,8 @@ int32_t lsm6dsm_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsm_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsm_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_PEDO_AT_2g = 0,
LSM6DSM_PEDO_AT_4g = 1,
} lsm6dsm_pedo_fs_t;
@@ -1822,20 +2701,26 @@ int32_t lsm6dsm_pedo_full_scale_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_pedo_full_scale_get(stmdev_ctx_t *ctx,
lsm6dsm_pedo_fs_t *val);
-int32_t lsm6dsm_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsm_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsm_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsm_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dsm_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsm_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dsm_pedo_steps_period_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsm_pedo_steps_period_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsm_pedo_steps_period_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lsm6dsm_pedo_steps_period_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
int32_t lsm6dsm_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsm_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dsm_motion_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsm_motion_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsm_motion_threshold_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lsm6dsm_motion_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
int32_t lsm6dsm_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsm_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1860,25 +2745,32 @@ int32_t lsm6dsm_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsm_mag_hard_iron_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsm_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dsm_mag_soft_iron_mat_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsm_mag_soft_iron_mat_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsm_mag_soft_iron_mat_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lsm6dsm_mag_soft_iron_mat_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
-int32_t lsm6dsm_mag_offset_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsm_mag_offset_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsm_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val);
+int32_t lsm6dsm_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val);
int32_t lsm6dsm_func_en_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsm_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsm_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsm_sh_sync_sens_frame_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsm_sh_sync_sens_frame_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_RES_RATIO_2_11 = 0,
LSM6DSM_RES_RATIO_2_12 = 1,
LSM6DSM_RES_RATIO_2_13 = 2,
LSM6DSM_RES_RATIO_2_14 = 3,
} lsm6dsm_rr_t;
-int32_t lsm6dsm_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx, lsm6dsm_rr_t val);
-int32_t lsm6dsm_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx, lsm6dsm_rr_t *val);
+int32_t lsm6dsm_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx,
+ lsm6dsm_rr_t val);
+int32_t lsm6dsm_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx,
+ lsm6dsm_rr_t *val);
int32_t lsm6dsm_sh_master_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsm_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1886,15 +2778,19 @@ int32_t lsm6dsm_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsm_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsm_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_EXT_PULL_UP = 0,
LSM6DSM_INTERNAL_PULL_UP = 1,
LSM6DSM_SH_PIN_MODE = 2,
} lsm6dsm_pull_up_en_t;
-int32_t lsm6dsm_sh_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsm_pull_up_en_t val);
-int32_t lsm6dsm_sh_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsm_pull_up_en_t *val);
+int32_t lsm6dsm_sh_pin_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsm_pull_up_en_t val);
+int32_t lsm6dsm_sh_pin_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsm_pull_up_en_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_XL_GY_DRDY = 0,
LSM6DSM_EXT_ON_INT2_PIN = 1,
} lsm6dsm_start_config_t;
@@ -1906,25 +2802,26 @@ int32_t lsm6dsm_sh_syncro_mode_get(stmdev_ctx_t *ctx,
int32_t lsm6dsm_sh_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsm_sh_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef struct {
- lsm6dsm_sensorhub1_reg_t sh_byte_1;
- lsm6dsm_sensorhub2_reg_t sh_byte_2;
- lsm6dsm_sensorhub3_reg_t sh_byte_3;
- lsm6dsm_sensorhub4_reg_t sh_byte_4;
- lsm6dsm_sensorhub5_reg_t sh_byte_5;
- lsm6dsm_sensorhub6_reg_t sh_byte_6;
- lsm6dsm_sensorhub7_reg_t sh_byte_7;
- lsm6dsm_sensorhub8_reg_t sh_byte_8;
- lsm6dsm_sensorhub9_reg_t sh_byte_9;
- lsm6dsm_sensorhub10_reg_t sh_byte_10;
- lsm6dsm_sensorhub11_reg_t sh_byte_11;
- lsm6dsm_sensorhub12_reg_t sh_byte_12;
- lsm6dsm_sensorhub13_reg_t sh_byte_13;
- lsm6dsm_sensorhub14_reg_t sh_byte_14;
- lsm6dsm_sensorhub15_reg_t sh_byte_15;
- lsm6dsm_sensorhub16_reg_t sh_byte_16;
- lsm6dsm_sensorhub17_reg_t sh_byte_17;
- lsm6dsm_sensorhub18_reg_t sh_byte_18;
+typedef struct
+{
+ lsm6dsm_sensorhub1_reg_t sh_byte_1;
+ lsm6dsm_sensorhub2_reg_t sh_byte_2;
+ lsm6dsm_sensorhub3_reg_t sh_byte_3;
+ lsm6dsm_sensorhub4_reg_t sh_byte_4;
+ lsm6dsm_sensorhub5_reg_t sh_byte_5;
+ lsm6dsm_sensorhub6_reg_t sh_byte_6;
+ lsm6dsm_sensorhub7_reg_t sh_byte_7;
+ lsm6dsm_sensorhub8_reg_t sh_byte_8;
+ lsm6dsm_sensorhub9_reg_t sh_byte_9;
+ lsm6dsm_sensorhub10_reg_t sh_byte_10;
+ lsm6dsm_sensorhub11_reg_t sh_byte_11;
+ lsm6dsm_sensorhub12_reg_t sh_byte_12;
+ lsm6dsm_sensorhub13_reg_t sh_byte_13;
+ lsm6dsm_sensorhub14_reg_t sh_byte_14;
+ lsm6dsm_sensorhub15_reg_t sh_byte_15;
+ lsm6dsm_sensorhub16_reg_t sh_byte_16;
+ lsm6dsm_sensorhub17_reg_t sh_byte_17;
+ lsm6dsm_sensorhub18_reg_t sh_byte_18;
} lsm6dsm_emb_sh_read_t;
int32_t lsm6dsm_sh_read_data_raw_get(stmdev_ctx_t *ctx,
lsm6dsm_emb_sh_read_t *val);
@@ -1933,9 +2830,11 @@ int32_t lsm6dsm_sh_cmd_sens_sync_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsm_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsm_sh_spi_sync_error_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsm_sh_spi_sync_error_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsm_sh_spi_sync_error_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_NORMAL_MODE_READ = 0,
LSM6DSM_SRC_MODE_READ = 1,
} lsm6dsm_src_mode_t;
@@ -1944,7 +2843,8 @@ int32_t lsm6dsm_sh_cfg_slave_0_rd_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_sh_cfg_slave_0_rd_mode_get(stmdev_ctx_t *ctx,
lsm6dsm_src_mode_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_SLV_0 = 0,
LSM6DSM_SLV_0_1 = 1,
LSM6DSM_SLV_0_1_2 = 2,
@@ -1955,14 +2855,17 @@ int32_t lsm6dsm_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx,
lsm6dsm_aux_sens_on_t *val);
-typedef struct{
+typedef struct
+{
uint8_t slv0_add;
uint8_t slv0_subadd;
uint8_t slv0_data;
} lsm6dsm_sh_cfg_write_t;
-int32_t lsm6dsm_sh_cfg_write(stmdev_ctx_t *ctx, lsm6dsm_sh_cfg_write_t *val);
+int32_t lsm6dsm_sh_cfg_write(stmdev_ctx_t *ctx,
+ lsm6dsm_sh_cfg_write_t *val);
-typedef struct{
+typedef struct
+{
uint8_t slv_add;
uint8_t slv_subadd;
uint8_t slv_len;
@@ -1976,7 +2879,8 @@ int32_t lsm6dsm_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
int32_t lsm6dsm_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
lsm6dsm_sh_cfg_read_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_SL0_NO_DEC = 0,
LSM6DSM_SL0_DEC_2 = 1,
LSM6DSM_SL0_DEC_4 = 2,
@@ -1987,7 +2891,8 @@ int32_t lsm6dsm_sh_slave_0_dec_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_sh_slave_0_dec_get(stmdev_ctx_t *ctx,
lsm6dsm_slave0_rate_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_EACH_SH_CYCLE = 0,
LSM6DSM_ONLY_FIRST_CYCLE = 1,
} lsm6dsm_write_once_t;
@@ -1996,7 +2901,8 @@ int32_t lsm6dsm_sh_write_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_sh_write_mode_get(stmdev_ctx_t *ctx,
lsm6dsm_write_once_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_SL1_NO_DEC = 0,
LSM6DSM_SL1_DEC_2 = 1,
LSM6DSM_SL1_DEC_4 = 2,
@@ -2007,7 +2913,8 @@ int32_t lsm6dsm_sh_slave_1_dec_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_sh_slave_1_dec_get(stmdev_ctx_t *ctx,
lsm6dsm_slave1_rate_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_SL2_NO_DEC = 0,
LSM6DSM_SL2_DEC_2 = 1,
LSM6DSM_SL2_DEC_4 = 2,
@@ -2018,7 +2925,8 @@ int32_t lsm6dsm_sh_slave_2_dec_set(stmdev_ctx_t *ctx,
int32_t lsm6dsm_sh_slave_2_dec_get(stmdev_ctx_t *ctx,
lsm6dsm_slave2_rate_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSM_SL3_NO_DEC = 0,
LSM6DSM_SL3_DEC_2 = 1,
LSM6DSM_SL3_DEC_4 = 2,
diff --git a/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.c b/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.c
index e5b171db835c0678b80447c1b98daffcbd8e2f2d..cb430306da13743ddf9a9c7719194d5759bffc4b 100644
--- a/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.c
+++ b/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file lsm6dso32_reg.c
- * @author Sensors Software Solution Team
- * @brief LSM6DSO32 driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lsm6dso32_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LSM6DSO32 driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lsm6dso32_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lsm6dso32_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t lsm6dso32_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lsm6dso32_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -95,7 +101,7 @@ float_t lsm6dso32_from_fs8_to_mg(int16_t lsb)
float_t lsm6dso32_from_fs16_to_mg(int16_t lsb)
{
- return ((float_t)lsb) *0.488f;
+ return ((float_t)lsb) * 0.488f;
}
float_t lsm6dso32_from_fs32_to_mg(int16_t lsb)
@@ -155,6 +161,7 @@ float_t lsm6dso32_from_lsb_to_nsec(int16_t lsb)
*
* @param ctx read / write interface definitions
* @param val change the values of fs_xl in reg CTRL1_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_xl_full_scale_set(stmdev_ctx_t *ctx,
@@ -163,12 +170,16 @@ int32_t lsm6dso32_xl_full_scale_set(stmdev_ctx_t *ctx,
lsm6dso32_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
ctrl1_xl.fs_xl = (uint8_t) val & 0x03U;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
+ (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -177,6 +188,7 @@ int32_t lsm6dso32_xl_full_scale_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of fs_xl in reg CTRL1_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_xl_full_scale_get(stmdev_ctx_t *ctx,
@@ -185,20 +197,26 @@ int32_t lsm6dso32_xl_full_scale_get(stmdev_ctx_t *ctx,
lsm6dso32_ctrl1_xl_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL, (uint8_t*)®, 1);
- switch (reg.fs_xl) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL, (uint8_t *)®, 1);
+
+ switch (reg.fs_xl)
+ {
case LSM6DSO32_4g:
*val = LSM6DSO32_4g;
break;
+
case LSM6DSO32_8g:
*val = LSM6DSO32_8g;
break;
+
case LSM6DSO32_16g:
*val = LSM6DSO32_16g;
break;
+
case LSM6DSO32_32g:
*val = LSM6DSO32_32g;
break;
+
default:
*val = LSM6DSO32_4g;
break;
@@ -213,6 +231,7 @@ int32_t lsm6dso32_xl_full_scale_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val Change the data rate and the power mode of
* the accelerometer
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_xl_data_rate_set(stmdev_ctx_t *ctx,
@@ -224,36 +243,57 @@ int32_t lsm6dso32_xl_data_rate_set(stmdev_ctx_t *ctx,
lsm6dso32_func_cfg_access_t func_cfg_access;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
ctrl1_xl.odr_xl = (uint8_t) LSM6DSO32_XL_ODR_OFF & 0x0FU;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
+ (uint8_t *)&ctrl1_xl, 1);
}
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FUNC_CFG_ACCESS,
+ (uint8_t *)&func_cfg_access, 1);
}
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t*) &ctrl5_c, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *) &ctrl5_c, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ctrl5_c.xl_ulp_en = ((uint8_t)val & 0x20U) >> 5;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t*) &ctrl5_c, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL5_C,
+ (uint8_t *) &ctrl5_c, 1);
}
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t*) &ctrl6_c, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *) &ctrl6_c, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ctrl6_c.xl_hm_mode = ((uint8_t)val & 0x10U) >> 4;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t*) &ctrl6_c, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL6_C,
+ (uint8_t *) &ctrl6_c, 1);
}
- if (ret == 0){
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ctrl1_xl.odr_xl = (uint8_t) val & 0x0FU;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
}
return ret;
@@ -265,6 +305,7 @@ int32_t lsm6dso32_xl_data_rate_set(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val Get the data rate and the power mode of
* the accelerometer
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_xl_data_rate_get(stmdev_ctx_t *ctx,
@@ -276,93 +317,125 @@ int32_t lsm6dso32_xl_data_rate_get(stmdev_ctx_t *ctx,
lsm6dso32_func_cfg_access_t func_cfg_access;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FUNC_CFG_ACCESS,
+ (uint8_t *)&func_cfg_access, 1);
}
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t*) &ctrl5_c, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *) &ctrl5_c, 1);
}
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t*) &ctrl6_c, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *) &ctrl6_c, 1);
}
switch ((ctrl5_c.xl_ulp_en << 5) + (ctrl6_c.xl_hm_mode << 4) +
- ctrl1_xl.odr_xl ) {
+ ctrl1_xl.odr_xl)
+ {
case LSM6DSO32_XL_ODR_OFF:
*val = LSM6DSO32_XL_ODR_OFF;
break;
+
case LSM6DSO32_XL_ODR_6Hz5_LOW_PW:
*val = LSM6DSO32_XL_ODR_6Hz5_LOW_PW;
break;
+
case LSM6DSO32_XL_ODR_12Hz5_LOW_PW:
*val = LSM6DSO32_XL_ODR_12Hz5_LOW_PW;
break;
+
case LSM6DSO32_XL_ODR_26Hz_LOW_PW:
*val = LSM6DSO32_XL_ODR_26Hz_LOW_PW;
break;
+
case LSM6DSO32_XL_ODR_52Hz_LOW_PW:
*val = LSM6DSO32_XL_ODR_52Hz_LOW_PW;
break;
+
case LSM6DSO32_XL_ODR_104Hz_NORMAL_MD:
*val = LSM6DSO32_XL_ODR_104Hz_NORMAL_MD;
break;
+
case LSM6DSO32_XL_ODR_208Hz_NORMAL_MD:
*val = LSM6DSO32_XL_ODR_208Hz_NORMAL_MD;
break;
+
case LSM6DSO32_XL_ODR_12Hz5_HIGH_PERF:
*val = LSM6DSO32_XL_ODR_12Hz5_HIGH_PERF;
break;
+
case LSM6DSO32_XL_ODR_26Hz_HIGH_PERF:
*val = LSM6DSO32_XL_ODR_26Hz_HIGH_PERF;
break;
+
case LSM6DSO32_XL_ODR_52Hz_HIGH_PERF:
*val = LSM6DSO32_XL_ODR_52Hz_HIGH_PERF;
break;
+
case LSM6DSO32_XL_ODR_104Hz_HIGH_PERF:
*val = LSM6DSO32_XL_ODR_104Hz_HIGH_PERF;
break;
+
case LSM6DSO32_XL_ODR_208Hz_HIGH_PERF:
*val = LSM6DSO32_XL_ODR_208Hz_HIGH_PERF;
break;
+
case LSM6DSO32_XL_ODR_417Hz_HIGH_PERF:
*val = LSM6DSO32_XL_ODR_417Hz_HIGH_PERF;
break;
+
case LSM6DSO32_XL_ODR_833Hz_HIGH_PERF:
*val = LSM6DSO32_XL_ODR_833Hz_HIGH_PERF;
break;
+
case LSM6DSO32_XL_ODR_1667Hz_HIGH_PERF:
*val = LSM6DSO32_XL_ODR_1667Hz_HIGH_PERF;
break;
+
case LSM6DSO32_XL_ODR_3333Hz_HIGH_PERF:
*val = LSM6DSO32_XL_ODR_3333Hz_HIGH_PERF;
break;
+
case LSM6DSO32_XL_ODR_6667Hz_HIGH_PERF:
*val = LSM6DSO32_XL_ODR_6667Hz_HIGH_PERF;
break;
+
case LSM6DSO32_XL_ODR_6Hz5_ULTRA_LOW_PW:
*val = LSM6DSO32_XL_ODR_6Hz5_ULTRA_LOW_PW;
break;
+
case LSM6DSO32_XL_ODR_12Hz5_ULTRA_LOW_PW:
*val = LSM6DSO32_XL_ODR_12Hz5_ULTRA_LOW_PW;
break;
+
case LSM6DSO32_XL_ODR_26Hz_ULTRA_LOW_PW:
*val = LSM6DSO32_XL_ODR_26Hz_ULTRA_LOW_PW;
break;
+
case LSM6DSO32_XL_ODR_52Hz_ULTRA_LOW_PW:
*val = LSM6DSO32_XL_ODR_52Hz_ULTRA_LOW_PW;
break;
+
case LSM6DSO32_XL_ODR_104Hz_ULTRA_LOW_PW:
*val = LSM6DSO32_XL_ODR_104Hz_ULTRA_LOW_PW;
break;
+
case LSM6DSO32_XL_ODR_208Hz_ULTRA_LOW_PW:
*val = LSM6DSO32_XL_ODR_208Hz_ULTRA_LOW_PW;
break;
+
default:
*val = LSM6DSO32_XL_ODR_OFF;
break;
}
+
return ret;
}
@@ -371,6 +444,7 @@ int32_t lsm6dso32_xl_data_rate_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of fs_g in reg CTRL2_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_gy_full_scale_set(stmdev_ctx_t *ctx,
@@ -379,10 +453,12 @@ int32_t lsm6dso32_gy_full_scale_set(stmdev_ctx_t *ctx,
lsm6dso32_ctrl2_g_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.fs_g = (uint8_t) val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t *)®, 1);
}
return ret;
@@ -393,6 +469,7 @@ int32_t lsm6dso32_gy_full_scale_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of fs_g in reg CTRL2_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_gy_full_scale_get(stmdev_ctx_t *ctx,
@@ -401,23 +478,30 @@ int32_t lsm6dso32_gy_full_scale_get(stmdev_ctx_t *ctx,
lsm6dso32_ctrl2_g_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t*)®, 1);
- switch (reg.fs_g) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t *)®, 1);
+
+ switch (reg.fs_g)
+ {
case LSM6DSO32_250dps:
*val = LSM6DSO32_250dps;
break;
+
case LSM6DSO32_125dps:
*val = LSM6DSO32_125dps;
break;
+
case LSM6DSO32_500dps:
*val = LSM6DSO32_500dps;
break;
+
case LSM6DSO32_1000dps:
*val = LSM6DSO32_1000dps;
break;
+
case LSM6DSO32_2000dps:
*val = LSM6DSO32_2000dps;
break;
+
default:
*val = LSM6DSO32_250dps;
break;
@@ -431,6 +515,7 @@ int32_t lsm6dso32_gy_full_scale_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of odr_g in reg CTRL2_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_gy_data_rate_set(stmdev_ctx_t *ctx,
@@ -440,25 +525,36 @@ int32_t lsm6dso32_gy_data_rate_set(stmdev_ctx_t *ctx,
lsm6dso32_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
+
+ if (ret == 0)
+ {
ctrl2_g.odr_g = (uint8_t) LSM6DSO32_GY_ODR_OFF & 0x0FU;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
}
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ctrl7_g.g_hm_mode = ((uint8_t)val & 0x10U) >> 4;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
}
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ctrl2_g.odr_g = (uint8_t)val & 0x0FU;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
}
+
return ret;
}
@@ -467,6 +563,7 @@ int32_t lsm6dso32_gy_data_rate_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of odr_g in reg CTRL2_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_gy_data_rate_get(stmdev_ctx_t *ctx,
@@ -476,64 +573,84 @@ int32_t lsm6dso32_gy_data_rate_get(stmdev_ctx_t *ctx,
lsm6dso32_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
}
- switch ( (ctrl7_g.g_hm_mode << 4) + ctrl2_g.odr_g) {
+ switch ((ctrl7_g.g_hm_mode << 4) + ctrl2_g.odr_g)
+ {
case LSM6DSO32_GY_ODR_OFF:
*val = LSM6DSO32_GY_ODR_OFF;
break;
+
case LSM6DSO32_GY_ODR_12Hz5_HIGH_PERF:
*val = LSM6DSO32_GY_ODR_12Hz5_HIGH_PERF;
break;
+
case LSM6DSO32_GY_ODR_26Hz_HIGH_PERF:
*val = LSM6DSO32_GY_ODR_26Hz_HIGH_PERF;
break;
+
case LSM6DSO32_GY_ODR_52Hz_HIGH_PERF:
*val = LSM6DSO32_GY_ODR_52Hz_HIGH_PERF;
break;
+
case LSM6DSO32_GY_ODR_104Hz_HIGH_PERF:
*val = LSM6DSO32_GY_ODR_104Hz_HIGH_PERF;
break;
+
case LSM6DSO32_GY_ODR_208Hz_HIGH_PERF:
*val = LSM6DSO32_GY_ODR_208Hz_HIGH_PERF;
break;
+
case LSM6DSO32_GY_ODR_417Hz_HIGH_PERF:
*val = LSM6DSO32_GY_ODR_417Hz_HIGH_PERF;
break;
+
case LSM6DSO32_GY_ODR_833Hz_HIGH_PERF:
*val = LSM6DSO32_GY_ODR_833Hz_HIGH_PERF;
break;
+
case LSM6DSO32_GY_ODR_1667Hz_HIGH_PERF:
*val = LSM6DSO32_GY_ODR_1667Hz_HIGH_PERF;
break;
+
case LSM6DSO32_GY_ODR_3333Hz_HIGH_PERF:
*val = LSM6DSO32_GY_ODR_3333Hz_HIGH_PERF;
break;
+
case LSM6DSO32_GY_ODR_6667Hz_HIGH_PERF:
*val = LSM6DSO32_GY_ODR_6667Hz_HIGH_PERF;
break;
+
case LSM6DSO32_GY_ODR_104Hz_NORMAL_MD:
*val = LSM6DSO32_GY_ODR_104Hz_NORMAL_MD;
break;
+
case LSM6DSO32_GY_ODR_208Hz_NORMAL_MD:
*val = LSM6DSO32_GY_ODR_208Hz_NORMAL_MD;
break;
+
case LSM6DSO32_GY_ODR_12Hz5_LOW_PW:
*val = LSM6DSO32_GY_ODR_12Hz5_LOW_PW;
break;
+
case LSM6DSO32_GY_ODR_26Hz_LOW_PW:
*val = LSM6DSO32_GY_ODR_26Hz_LOW_PW;
break;
+
case LSM6DSO32_GY_ODR_52Hz_LOW_PW:
*val = LSM6DSO32_GY_ODR_52Hz_LOW_PW;
break;
+
default:
*val = LSM6DSO32_GY_ODR_OFF;
break;
}
+
return ret;
}
@@ -542,18 +659,23 @@ int32_t lsm6dso32_gy_data_rate_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of bdu in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dso32_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dso32_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.bdu = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -562,14 +684,16 @@ int32_t lsm6dso32_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of bdu in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso32_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso32_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
*val = reg.bdu;
return ret;
@@ -581,6 +705,7 @@ int32_t lsm6dso32_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of usr_off_w in reg CTRL6_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_xl_offset_weight_set(stmdev_ctx_t *ctx,
@@ -589,11 +714,14 @@ int32_t lsm6dso32_xl_offset_weight_set(stmdev_ctx_t *ctx,
lsm6dso32_ctrl6_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.usr_off_w = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -603,6 +731,7 @@ int32_t lsm6dso32_xl_offset_weight_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of usr_off_w in reg CTRL6_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_xl_offset_weight_get(stmdev_ctx_t *ctx,
@@ -611,19 +740,23 @@ int32_t lsm6dso32_xl_offset_weight_get(stmdev_ctx_t *ctx,
lsm6dso32_ctrl6_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *)®, 1);
- switch (reg.usr_off_w) {
+ switch (reg.usr_off_w)
+ {
case LSM6DSO32_LSb_1mg:
*val = LSM6DSO32_LSb_1mg;
break;
+
case LSM6DSO32_LSb_16mg:
*val = LSM6DSO32_LSb_16mg;
break;
+
default:
*val = LSM6DSO32_LSb_1mg;
break;
}
+
return ret;
}
@@ -634,6 +767,7 @@ int32_t lsm6dso32_xl_offset_weight_get(stmdev_ctx_t *ctx,
* @param val registers ALL_INT_SRC; WAKE_UP_SRC;
* TAP_SRC; D6D_SRC; STATUS_REG;
* EMB_FUNC_STATUS; FSM_STATUS_A/B
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_all_sources_get(stmdev_ctx_t *ctx,
@@ -642,42 +776,60 @@ int32_t lsm6dso32_all_sources_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_ALL_INT_SRC,
- (uint8_t*)&val->all_int_src, 1);
- if (ret == 0) {
+ (uint8_t *)&val->all_int_src, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_SRC,
- (uint8_t*)&val->wake_up_src, 1);
+ (uint8_t *)&val->wake_up_src, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_SRC,
- (uint8_t*)&val->tap_src, 1);
+ (uint8_t *)&val->tap_src, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_D6D_SRC,
- (uint8_t*)&val->d6d_src, 1);
+ (uint8_t *)&val->d6d_src, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_STATUS_REG,
- (uint8_t*)&val->status_reg, 1);
+ (uint8_t *)&val->status_reg, 1);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_STATUS,
- (uint8_t*)&val->emb_func_status, 1);
+ (uint8_t *)&val->emb_func_status, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_STATUS_A,
- (uint8_t*)&val->fsm_status_a, 1);
+ (uint8_t *)&val->fsm_status_a, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_STATUS_B,
- (uint8_t*)&val->fsm_status_b, 1);
+ (uint8_t *)&val->fsm_status_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
+
return ret;
}
@@ -686,13 +838,16 @@ int32_t lsm6dso32_all_sources_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val register STATUS_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_status_reg_get(stmdev_ctx_t *ctx,
lsm6dso32_status_reg_t *val)
{
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_STATUS_REG, (uint8_t*) val, 1);
+
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_STATUS_REG, (uint8_t *) val, 1);
+
return ret;
}
@@ -701,14 +856,16 @@ int32_t lsm6dso32_status_reg_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of xlda in reg STATUS_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso32_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso32_status_reg_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_STATUS_REG, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_STATUS_REG, (uint8_t *)®, 1);
*val = reg.xlda;
return ret;
@@ -719,14 +876,16 @@ int32_t lsm6dso32_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of gda in reg STATUS_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso32_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso32_status_reg_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_STATUS_REG, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_STATUS_REG, (uint8_t *)®, 1);
*val = reg.gda;
return ret;
@@ -737,14 +896,16 @@ int32_t lsm6dso32_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of tda in reg STATUS_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso32_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso32_status_reg_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_STATUS_REG, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_STATUS_REG, (uint8_t *)®, 1);
*val = reg.tda;
return ret;
@@ -757,12 +918,16 @@ int32_t lsm6dso32_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso32_xl_usr_offset_x_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_X_OFS_USR, buff, 1);
+
return ret;
}
@@ -773,12 +938,16 @@ int32_t lsm6dso32_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso32_xl_usr_offset_x_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_X_OFS_USR, buff, 1);
+
return ret;
}
@@ -789,12 +958,16 @@ int32_t lsm6dso32_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso32_xl_usr_offset_y_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_Y_OFS_USR, buff, 1);
+
return ret;
}
@@ -805,12 +978,16 @@ int32_t lsm6dso32_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso32_xl_usr_offset_y_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_Y_OFS_USR, buff, 1);
+
return ret;
}
@@ -821,12 +998,16 @@ int32_t lsm6dso32_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso32_xl_usr_offset_z_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_Z_OFS_USR, buff, 1);
+
return ret;
}
@@ -837,12 +1018,16 @@ int32_t lsm6dso32_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso32_xl_usr_offset_z_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_Z_OFS_USR, buff, 1);
+
return ret;
}
@@ -851,6 +1036,7 @@ int32_t lsm6dso32_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param val change the values of usr_off_on_out in reg CTRL7_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -858,11 +1044,14 @@ int32_t lsm6dso32_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso32_ctrl7_g_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.usr_off_on_out = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -871,6 +1060,7 @@ int32_t lsm6dso32_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val values of usr_off_on_out in reg CTRL7_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -878,7 +1068,7 @@ int32_t lsm6dso32_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso32_ctrl7_g_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t *)®, 1);
*val = reg.usr_off_on_out;
return ret;
@@ -902,6 +1092,7 @@ int32_t lsm6dso32_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of timestamp_en in reg CTRL10_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -909,11 +1100,14 @@ int32_t lsm6dso32_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso32_ctrl10_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL10_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL10_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.timestamp_en = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL10_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL10_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -922,6 +1116,7 @@ int32_t lsm6dso32_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of timestamp_en in reg CTRL10_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -929,7 +1124,7 @@ int32_t lsm6dso32_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso32_ctrl10_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL10_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL10_C, (uint8_t *)®, 1);
*val = reg.timestamp_en;
return ret;
@@ -942,12 +1137,20 @@ int32_t lsm6dso32_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_timestamp_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso32_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val)
{
+ uint8_t buff[4];
int32_t ret;
+
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TIMESTAMP0, buff, 4);
+ *val = buff[3];
+ *val = (*val * 256U) + buff[2];
+ *val = (*val * 256U) + buff[1];
+ *val = (*val * 256U) + buff[0];
+
return ret;
}
@@ -969,6 +1172,7 @@ int32_t lsm6dso32_timestamp_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param val change the values of rounding in reg CTRL5_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_rounding_mode_set(stmdev_ctx_t *ctx,
@@ -977,11 +1181,14 @@ int32_t lsm6dso32_rounding_mode_set(stmdev_ctx_t *ctx,
lsm6dso32_ctrl5_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.rounding = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -990,6 +1197,7 @@ int32_t lsm6dso32_rounding_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of rounding in reg CTRL5_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_rounding_mode_get(stmdev_ctx_t *ctx,
@@ -998,24 +1206,31 @@ int32_t lsm6dso32_rounding_mode_get(stmdev_ctx_t *ctx,
lsm6dso32_ctrl5_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t*)®, 1);
- switch (reg.rounding) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *)®, 1);
+
+ switch (reg.rounding)
+ {
case LSM6DSO32_NO_ROUND:
*val = LSM6DSO32_NO_ROUND;
break;
+
case LSM6DSO32_ROUND_XL:
*val = LSM6DSO32_ROUND_XL;
break;
+
case LSM6DSO32_ROUND_GY:
*val = LSM6DSO32_ROUND_GY;
break;
+
case LSM6DSO32_ROUND_GY_XL:
*val = LSM6DSO32_ROUND_GY_XL;
break;
+
default:
*val = LSM6DSO32_NO_ROUND;
break;
}
+
return ret;
}
@@ -1026,12 +1241,18 @@ int32_t lsm6dso32_rounding_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso32_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
+
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_OUT_TEMP_L, buff, 2);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+
return ret;
}
@@ -1041,12 +1262,23 @@ int32_t lsm6dso32_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso32_angular_rate_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_OUTX_L_G, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -1056,12 +1288,23 @@ int32_t lsm6dso32_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso32_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_OUTX_L_A, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -1070,12 +1313,15 @@ int32_t lsm6dso32_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_DATA_OUT_X_L, buff, 6);
+
return ret;
}
@@ -1084,19 +1330,29 @@ int32_t lsm6dso32_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_number_of_steps_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso32_number_of_steps_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_STEP_COUNTER_L, buff, 2);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
+
return ret;
}
@@ -1104,6 +1360,7 @@ int32_t lsm6dso32_number_of_steps_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @brief Reset step counter register.[get]
*
* @param ctx read / write interface definitions
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_steps_reset(stmdev_ctx_t *ctx)
@@ -1112,16 +1369,24 @@ int32_t lsm6dso32_steps_reset(stmdev_ctx_t *ctx)
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_SRC, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_SRC, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.pedo_rst_step = PROPERTY_ENABLE;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_SRC, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_SRC,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
+
return ret;
}
@@ -1132,7 +1397,7 @@ int32_t lsm6dso32_steps_reset(stmdev_ctx_t *ctx)
/**
* @defgroup LSM6DSO32_common
- * @brief This section groups common usefull functions.
+ * @brief This section groups common useful functions.
* @{
*
*/
@@ -1145,6 +1410,7 @@ int32_t lsm6dso32_steps_reset(stmdev_ctx_t *ctx)
* @param ctx read / write interface definitions
* @param val change the values of freq_fine in reg
* INTERNAL_FREQ_FINE
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1153,12 +1419,15 @@ int32_t lsm6dso32_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INTERNAL_FREQ_FINE,
- (uint8_t*)®, 1);
- if (ret == 0) {
+ (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.freq_fine = val;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_INTERNAL_FREQ_FINE,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1169,6 +1438,7 @@ int32_t lsm6dso32_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of freq_fine in reg INTERNAL_FREQ_FINE
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1177,7 +1447,7 @@ int32_t lsm6dso32_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INTERNAL_FREQ_FINE,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
*val = reg.freq_fine;
return ret;
@@ -1190,6 +1460,7 @@ int32_t lsm6dso32_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of reg_access in reg FUNC_CFG_ACCESS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_mem_bank_set(stmdev_ctx_t *ctx,
@@ -1198,12 +1469,16 @@ int32_t lsm6dso32_mem_bank_set(stmdev_ctx_t *ctx,
lsm6dso32_func_cfg_access_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FUNC_CFG_ACCESS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FUNC_CFG_ACCESS,
+ (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.reg_access = (uint8_t)val;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FUNC_CFG_ACCESS,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1213,6 +1488,7 @@ int32_t lsm6dso32_mem_bank_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of reg_access in reg FUNC_CFG_ACCESS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_mem_bank_get(stmdev_ctx_t *ctx,
@@ -1221,21 +1497,28 @@ int32_t lsm6dso32_mem_bank_get(stmdev_ctx_t *ctx,
lsm6dso32_func_cfg_access_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FUNC_CFG_ACCESS, (uint8_t*)®, 1);
- switch (reg.reg_access) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FUNC_CFG_ACCESS,
+ (uint8_t *)®, 1);
+
+ switch (reg.reg_access)
+ {
case LSM6DSO32_USER_BANK:
*val = LSM6DSO32_USER_BANK;
break;
+
case LSM6DSO32_SENSOR_HUB_BANK:
*val = LSM6DSO32_SENSOR_HUB_BANK;
break;
+
case LSM6DSO32_EMBEDDED_FUNC_BANK:
*val = LSM6DSO32_EMBEDDED_FUNC_BANK;
break;
+
default:
*val = LSM6DSO32_USER_BANK;
break;
}
+
return ret;
}
@@ -1245,9 +1528,11 @@ int32_t lsm6dso32_mem_bank_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param uint8_t address: page line address
* @param val value to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address,
+int32_t lsm6dso32_ln_pg_write_byte(stmdev_ctx_t *ctx,
+ uint16_t address,
uint8_t *val)
{
lsm6dso32_page_rw_t page_rw;
@@ -1257,42 +1542,61 @@ int32_t lsm6dso32_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address,
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t*) &page_rw, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x02; /* page_write enable */
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t*) &page_rw, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW,
+ (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t*) &page_sel, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_SEL,
+ (uint8_t *) &page_sel, 1);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
page_sel.not_used_01 = 1;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL,
- (uint8_t*) &page_sel, 1);
+ (uint8_t *) &page_sel, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_address.page_addr = (uint8_t)address & 0xFFU;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_ADDRESS,
- (uint8_t*)&page_address, 1);
+ (uint8_t *)&page_address, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_VALUE, val, 1);
}
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t*) &page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x00; /* page_write disable */
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t*) &page_rw, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW,
+ (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
+
return ret;
}
@@ -1303,6 +1607,7 @@ int32_t lsm6dso32_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address,
* @param uint8_t address: page line address
* @param uint8_t *buf: buffer to write
* @param uint8_t len: buffer len
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address,
@@ -1312,72 +1617,93 @@ int32_t lsm6dso32_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address,
lsm6dso32_page_sel_t page_sel;
lsm6dso32_page_address_t page_address;
int32_t ret;
+
uint8_t msb, lsb;
uint8_t i ;
-
msb = ((uint8_t)(address >> 8) & 0x0FU);
lsb = (uint8_t)address & 0xFFU;
-
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t*) &page_rw, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x02; /* page_write enable*/
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t*) &page_rw, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW,
+ (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t*) &page_sel, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_SEL,
+ (uint8_t *) &page_sel, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_sel.page_sel = msb;
page_sel.not_used_01 = 1;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL,
- (uint8_t*) &page_sel, 1);
+ (uint8_t *) &page_sel, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_address.page_addr = lsb;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_ADDRESS,
- (uint8_t*)&page_address, 1);
+ (uint8_t *)&page_address, 1);
}
- if (ret == 0) {
-
- for (i = 0; ( (i < len) && (ret == 0) ); i++)
+ if (ret == 0)
+ {
+ for (i = 0; ((i < len) && (ret == 0)); i++)
{
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_VALUE, &buf[i], 1);
/* Check if page wrap */
- if ( (lsb == 0x00U) && (ret == 0) ) {
+ if ((lsb == 0x00U) && (ret == 0))
+ {
lsb++;
msb++;
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
- if (ret == 0) {
+ (uint8_t *)&page_sel, 1);
+
+ if (ret == 0)
+ {
page_sel.page_sel = msb;
page_sel.not_used_01 = 1;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
+ (uint8_t *)&page_sel, 1);
}
}
}
+
page_sel.page_sel = 0;
page_sel.not_used_01 = 1;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL,
- (uint8_t*) &page_sel, 1);
+ (uint8_t *) &page_sel, 1);
}
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t*) &page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x00; /* page_write disable */
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t*) &page_rw, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW,
+ (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
+
return ret;
}
@@ -1387,6 +1713,7 @@ int32_t lsm6dso32_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address,
* @param ctx read / write interface definitions
* @param uint8_t address: page line address
* @param val read value
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t address,
@@ -1398,42 +1725,59 @@ int32_t lsm6dso32_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t address,
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t*) &page_rw, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x01; /* page_read enable*/
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t*) &page_rw, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW,
+ (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_SEL,
- (uint8_t*) &page_sel, 1);
+ (uint8_t *) &page_sel, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
page_sel.not_used_01 = 1;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL,
- (uint8_t*) &page_sel, 1);
+ (uint8_t *) &page_sel, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_address.page_addr = (uint8_t)address & 0x00FFU;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_ADDRESS,
- (uint8_t*)&page_address, 1);
+ (uint8_t *)&page_address, 1);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_VALUE, val, 2);
}
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t*) &page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x00; /* page_read disable */
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t*) &page_rw, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW,
+ (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -1446,6 +1790,7 @@ int32_t lsm6dso32_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t address,
* @param ctx read / write interface definitions
* @param val change the values of dataready_pulsed in
* reg COUNTER_BDR_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_data_ready_mode_set(stmdev_ctx_t *ctx,
@@ -1455,12 +1800,15 @@ int32_t lsm6dso32_data_ready_mode_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
- (uint8_t*)®, 1);
- if (ret == 0) {
+ (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.dataready_pulsed = (uint8_t)val;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1471,6 +1819,7 @@ int32_t lsm6dso32_data_ready_mode_set(stmdev_ctx_t *ctx,
* @param val Get the values of
* dataready_pulsed in
* reg COUNTER_BDR_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_data_ready_mode_get(stmdev_ctx_t *ctx,
@@ -1480,18 +1829,23 @@ int32_t lsm6dso32_data_ready_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
- (uint8_t*)®, 1);
- switch (reg.dataready_pulsed) {
+ (uint8_t *)®, 1);
+
+ switch (reg.dataready_pulsed)
+ {
case LSM6DSO32_DRDY_LATCHED:
*val = LSM6DSO32_DRDY_LATCHED;
break;
+
case LSM6DSO32_DRDY_PULSED:
*val = LSM6DSO32_DRDY_PULSED;
break;
+
default:
*val = LSM6DSO32_DRDY_LATCHED;
break;
}
+
return ret;
}
@@ -1500,12 +1854,15 @@ int32_t lsm6dso32_data_ready_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -1515,6 +1872,7 @@ int32_t lsm6dso32_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param val change the values of sw_reset in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_reset_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1522,10 +1880,12 @@ int32_t lsm6dso32_reset_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso32_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.sw_reset = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
}
return ret;
@@ -1536,6 +1896,7 @@ int32_t lsm6dso32_reset_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of sw_reset in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1543,7 +1904,7 @@ int32_t lsm6dso32_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso32_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
*val = reg.sw_reset;
return ret;
@@ -1555,6 +1916,7 @@ int32_t lsm6dso32_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of if_inc in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1562,11 +1924,14 @@ int32_t lsm6dso32_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso32_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.if_inc = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1576,6 +1941,7 @@ int32_t lsm6dso32_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of if_inc in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1583,7 +1949,7 @@ int32_t lsm6dso32_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso32_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
*val = reg.if_inc;
return ret;
@@ -1594,6 +1960,7 @@ int32_t lsm6dso32_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of boot in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_boot_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1601,11 +1968,14 @@ int32_t lsm6dso32_boot_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso32_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.boot = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1614,6 +1984,7 @@ int32_t lsm6dso32_boot_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of boot in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1621,7 +1992,7 @@ int32_t lsm6dso32_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso32_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
*val = reg.boot;
return ret;
@@ -1632,6 +2003,7 @@ int32_t lsm6dso32_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of st_xl in reg CTRL5_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_xl_self_test_set(stmdev_ctx_t *ctx,
@@ -1640,11 +2012,14 @@ int32_t lsm6dso32_xl_self_test_set(stmdev_ctx_t *ctx,
lsm6dso32_ctrl5_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.st_xl = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1653,6 +2028,7 @@ int32_t lsm6dso32_xl_self_test_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of st_xl in reg CTRL5_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_xl_self_test_get(stmdev_ctx_t *ctx,
@@ -1661,21 +2037,27 @@ int32_t lsm6dso32_xl_self_test_get(stmdev_ctx_t *ctx,
lsm6dso32_ctrl5_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t*)®, 1);
- switch (reg.st_xl) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *)®, 1);
+
+ switch (reg.st_xl)
+ {
case LSM6DSO32_XL_ST_DISABLE:
*val = LSM6DSO32_XL_ST_DISABLE;
break;
+
case LSM6DSO32_XL_ST_POSITIVE:
*val = LSM6DSO32_XL_ST_POSITIVE;
break;
+
case LSM6DSO32_XL_ST_NEGATIVE:
*val = LSM6DSO32_XL_ST_NEGATIVE;
break;
+
default:
*val = LSM6DSO32_XL_ST_DISABLE;
break;
}
+
return ret;
}
@@ -1684,6 +2066,7 @@ int32_t lsm6dso32_xl_self_test_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of st_g in reg CTRL5_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_gy_self_test_set(stmdev_ctx_t *ctx,
@@ -1692,11 +2075,14 @@ int32_t lsm6dso32_gy_self_test_set(stmdev_ctx_t *ctx,
lsm6dso32_ctrl5_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.st_g = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1705,6 +2091,7 @@ int32_t lsm6dso32_gy_self_test_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of st_g in reg CTRL5_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_gy_self_test_get(stmdev_ctx_t *ctx,
@@ -1713,21 +2100,27 @@ int32_t lsm6dso32_gy_self_test_get(stmdev_ctx_t *ctx,
lsm6dso32_ctrl5_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t*)®, 1);
- switch (reg.st_g) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *)®, 1);
+
+ switch (reg.st_g)
+ {
case LSM6DSO32_GY_ST_DISABLE:
*val = LSM6DSO32_GY_ST_DISABLE;
break;
+
case LSM6DSO32_GY_ST_POSITIVE:
*val = LSM6DSO32_GY_ST_POSITIVE;
break;
+
case LSM6DSO32_GY_ST_NEGATIVE:
*val = LSM6DSO32_GY_ST_NEGATIVE;
break;
+
default:
*val = LSM6DSO32_GY_ST_DISABLE;
break;
}
+
return ret;
}
@@ -1749,6 +2142,7 @@ int32_t lsm6dso32_gy_self_test_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of lpf2_xl_en in reg CTRL1_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1756,11 +2150,14 @@ int32_t lsm6dso32_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso32_ctrl1_xl_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.lpf2_xl_en = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL1_XL, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL1_XL, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1769,6 +2166,7 @@ int32_t lsm6dso32_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of lpf2_xl_en in reg CTRL1_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1776,7 +2174,7 @@ int32_t lsm6dso32_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso32_ctrl1_xl_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL, (uint8_t *)®, 1);
*val = reg.lpf2_xl_en;
return ret;
@@ -1789,6 +2187,7 @@ int32_t lsm6dso32_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of lpf1_sel_g in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1796,11 +2195,14 @@ int32_t lsm6dso32_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso32_ctrl4_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.lpf1_sel_g = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1811,6 +2213,7 @@ int32_t lsm6dso32_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of lpf1_sel_g in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1818,7 +2221,7 @@ int32_t lsm6dso32_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso32_ctrl4_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
*val = reg.lpf1_sel_g;
return ret;
@@ -1830,18 +2233,23 @@ int32_t lsm6dso32_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of drdy_mask in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dso32_filter_settling_mask_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dso32_ctrl4_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.drdy_mask = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1851,14 +2259,16 @@ int32_t lsm6dso32_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of drdy_mask in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso32_filter_settling_mask_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso32_ctrl4_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
*val = reg.drdy_mask;
return ret;
@@ -1869,6 +2279,7 @@ int32_t lsm6dso32_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of ftype in reg CTRL6_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
@@ -1877,11 +2288,14 @@ int32_t lsm6dso32_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
lsm6dso32_ctrl6_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.ftype = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1890,6 +2304,7 @@ int32_t lsm6dso32_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of ftype in reg CTRL6_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
@@ -1898,36 +2313,47 @@ int32_t lsm6dso32_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
lsm6dso32_ctrl6_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t*)®, 1);
- switch (reg.ftype) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *)®, 1);
+
+ switch (reg.ftype)
+ {
case LSM6DSO32_ULTRA_LIGHT:
*val = LSM6DSO32_ULTRA_LIGHT;
break;
+
case LSM6DSO32_VERY_LIGHT:
*val = LSM6DSO32_VERY_LIGHT;
break;
+
case LSM6DSO32_LIGHT:
*val = LSM6DSO32_LIGHT;
break;
+
case LSM6DSO32_MEDIUM:
*val = LSM6DSO32_MEDIUM;
break;
+
case LSM6DSO32_STRONG:
*val = LSM6DSO32_STRONG;
break;
+
case LSM6DSO32_VERY_STRONG:
*val = LSM6DSO32_VERY_STRONG;
break;
+
case LSM6DSO32_AGGRESSIVE:
*val = LSM6DSO32_AGGRESSIVE;
break;
+
case LSM6DSO32_XTREME:
*val = LSM6DSO32_XTREME;
break;
+
default:
*val = LSM6DSO32_ULTRA_LIGHT;
break;
}
+
return ret;
}
@@ -1936,6 +2362,7 @@ int32_t lsm6dso32_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of low_pass_on_6d in reg CTRL8_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1943,11 +2370,14 @@ int32_t lsm6dso32_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso32_ctrl8_xl_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.low_pass_on_6d = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1956,6 +2386,7 @@ int32_t lsm6dso32_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of low_pass_on_6d in reg CTRL8_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1963,7 +2394,7 @@ int32_t lsm6dso32_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso32_ctrl8_xl_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t *)®, 1);
*val = reg.low_pass_on_6d;
return ret;
@@ -1976,6 +2407,7 @@ int32_t lsm6dso32_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val)
* @param ctx read / write interface definitions
* @param val change the values of hp_slope_xl_en
* in reg CTRL8_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
@@ -1984,13 +2416,16 @@ int32_t lsm6dso32_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
lsm6dso32_ctrl8_xl_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.hp_slope_xl_en = ((uint8_t)val & 0x10U) >> 4;
reg.hp_ref_mode_xl = ((uint8_t)val & 0x20U) >> 5;
reg.hpcf_xl = (uint8_t)val & 0x07U;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2000,6 +2435,7 @@ int32_t lsm6dso32_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of hp_slope_xl_en in reg CTRL8_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
@@ -2008,78 +2444,103 @@ int32_t lsm6dso32_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
lsm6dso32_ctrl8_xl_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t *)®, 1);
+
switch ((reg.hp_ref_mode_xl << 5) | (reg.hp_slope_xl_en << 4) |
- reg.hpcf_xl) {
+ reg.hpcf_xl)
+ {
case LSM6DSO32_HP_PATH_DISABLE_ON_OUT:
*val = LSM6DSO32_HP_PATH_DISABLE_ON_OUT;
break;
+
case LSM6DSO32_SLOPE_ODR_DIV_4:
*val = LSM6DSO32_SLOPE_ODR_DIV_4;
break;
+
case LSM6DSO32_HP_ODR_DIV_10:
*val = LSM6DSO32_HP_ODR_DIV_10;
break;
+
case LSM6DSO32_HP_ODR_DIV_20:
*val = LSM6DSO32_HP_ODR_DIV_20;
break;
+
case LSM6DSO32_HP_ODR_DIV_45:
*val = LSM6DSO32_HP_ODR_DIV_45;
break;
+
case LSM6DSO32_HP_ODR_DIV_100:
*val = LSM6DSO32_HP_ODR_DIV_100;
break;
+
case LSM6DSO32_HP_ODR_DIV_200:
*val = LSM6DSO32_HP_ODR_DIV_200;
break;
+
case LSM6DSO32_HP_ODR_DIV_400:
*val = LSM6DSO32_HP_ODR_DIV_400;
break;
+
case LSM6DSO32_HP_ODR_DIV_800:
*val = LSM6DSO32_HP_ODR_DIV_800;
break;
+
case LSM6DSO32_HP_REF_MD_ODR_DIV_10:
*val = LSM6DSO32_HP_REF_MD_ODR_DIV_10;
break;
+
case LSM6DSO32_HP_REF_MD_ODR_DIV_20:
*val = LSM6DSO32_HP_REF_MD_ODR_DIV_20;
break;
+
case LSM6DSO32_HP_REF_MD_ODR_DIV_45:
*val = LSM6DSO32_HP_REF_MD_ODR_DIV_45;
break;
+
case LSM6DSO32_HP_REF_MD_ODR_DIV_100:
*val = LSM6DSO32_HP_REF_MD_ODR_DIV_100;
break;
+
case LSM6DSO32_HP_REF_MD_ODR_DIV_200:
*val = LSM6DSO32_HP_REF_MD_ODR_DIV_200;
break;
+
case LSM6DSO32_HP_REF_MD_ODR_DIV_400:
*val = LSM6DSO32_HP_REF_MD_ODR_DIV_400;
break;
+
case LSM6DSO32_HP_REF_MD_ODR_DIV_800:
*val = LSM6DSO32_HP_REF_MD_ODR_DIV_800;
break;
+
case LSM6DSO32_LP_ODR_DIV_10:
*val = LSM6DSO32_LP_ODR_DIV_10;
break;
+
case LSM6DSO32_LP_ODR_DIV_20:
*val = LSM6DSO32_LP_ODR_DIV_20;
break;
+
case LSM6DSO32_LP_ODR_DIV_45:
*val = LSM6DSO32_LP_ODR_DIV_45;
break;
+
case LSM6DSO32_LP_ODR_DIV_100:
*val = LSM6DSO32_LP_ODR_DIV_100;
break;
+
case LSM6DSO32_LP_ODR_DIV_200:
*val = LSM6DSO32_LP_ODR_DIV_200;
break;
+
case LSM6DSO32_LP_ODR_DIV_400:
*val = LSM6DSO32_LP_ODR_DIV_400;
break;
+
case LSM6DSO32_LP_ODR_DIV_800:
*val = LSM6DSO32_LP_ODR_DIV_800;
break;
+
default:
*val = LSM6DSO32_HP_PATH_DISABLE_ON_OUT;
break;
@@ -2096,6 +2557,7 @@ int32_t lsm6dso32_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of fastsettl_mode_xl in
* reg CTRL8_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -2103,11 +2565,14 @@ int32_t lsm6dso32_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso32_ctrl8_xl_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.fastsettl_mode_xl = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2118,14 +2583,16 @@ int32_t lsm6dso32_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of fastsettl_mode_xl in reg CTRL8_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso32_xl_fast_settling_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso32_ctrl8_xl_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t *)®, 1);
*val = reg.fastsettl_mode_xl;
return ret;
@@ -2137,6 +2604,7 @@ int32_t lsm6dso32_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of slope_fds in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
@@ -2145,11 +2613,14 @@ int32_t lsm6dso32_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
lsm6dso32_tap_cfg0_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.slope_fds = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2159,6 +2630,7 @@ int32_t lsm6dso32_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of slope_fds in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
@@ -2167,18 +2639,23 @@ int32_t lsm6dso32_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
lsm6dso32_tap_cfg0_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t*)®, 1);
- switch (reg.slope_fds) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
+
+ switch (reg.slope_fds)
+ {
case LSM6DSO32_USE_SLOPE:
*val = LSM6DSO32_USE_SLOPE;
break;
+
case LSM6DSO32_USE_HPF:
*val = LSM6DSO32_USE_HPF;
break;
+
default:
*val = LSM6DSO32_USE_SLOPE;
break;
}
+
return ret;
}
@@ -2188,6 +2665,7 @@ int32_t lsm6dso32_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of hp_en_g and hp_en_g in reg CTRL7_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
@@ -2196,12 +2674,15 @@ int32_t lsm6dso32_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
lsm6dso32_ctrl7_g_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.hp_en_g = ((uint8_t)val & 0x80U) >> 7;
reg.hpm_g = (uint8_t)val & 0x03U;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2211,6 +2692,7 @@ int32_t lsm6dso32_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of hp_en_g and hp_en_g in reg CTRL7_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
@@ -2219,27 +2701,35 @@ int32_t lsm6dso32_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
lsm6dso32_ctrl7_g_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t*)®, 1);
- switch ((reg.hp_en_g << 7) + reg.hpm_g) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t *)®, 1);
+
+ switch ((reg.hp_en_g << 7) + reg.hpm_g)
+ {
case LSM6DSO32_HP_FILTER_NONE:
*val = LSM6DSO32_HP_FILTER_NONE;
break;
+
case LSM6DSO32_HP_FILTER_16mHz:
*val = LSM6DSO32_HP_FILTER_16mHz;
break;
+
case LSM6DSO32_HP_FILTER_65mHz:
*val = LSM6DSO32_HP_FILTER_65mHz;
break;
+
case LSM6DSO32_HP_FILTER_260mHz:
*val = LSM6DSO32_HP_FILTER_260mHz;
break;
+
case LSM6DSO32_HP_FILTER_1Hz04:
*val = LSM6DSO32_HP_FILTER_1Hz04;
break;
+
default:
*val = LSM6DSO32_HP_FILTER_NONE;
break;
}
+
return ret;
}
@@ -2262,6 +2752,7 @@ int32_t lsm6dso32_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of sdo_pu_en in
* reg PIN_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
@@ -2270,11 +2761,14 @@ int32_t lsm6dso32_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
lsm6dso32_pin_ctrl_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PIN_CTRL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PIN_CTRL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.sdo_pu_en = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PIN_CTRL, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PIN_CTRL, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2283,6 +2777,7 @@ int32_t lsm6dso32_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of sdo_pu_en in reg PIN_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
@@ -2291,18 +2786,23 @@ int32_t lsm6dso32_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
lsm6dso32_pin_ctrl_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PIN_CTRL, (uint8_t*)®, 1);
- switch (reg.sdo_pu_en) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PIN_CTRL, (uint8_t *)®, 1);
+
+ switch (reg.sdo_pu_en)
+ {
case LSM6DSO32_PULL_UP_DISC:
*val = LSM6DSO32_PULL_UP_DISC;
break;
+
case LSM6DSO32_PULL_UP_CONNECT:
*val = LSM6DSO32_PULL_UP_CONNECT;
break;
+
default:
*val = LSM6DSO32_PULL_UP_DISC;
break;
}
+
return ret;
}
@@ -2311,6 +2811,7 @@ int32_t lsm6dso32_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of sim in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_spi_mode_set(stmdev_ctx_t *ctx, lsm6dso32_sim_t val)
@@ -2318,11 +2819,14 @@ int32_t lsm6dso32_spi_mode_set(stmdev_ctx_t *ctx, lsm6dso32_sim_t val)
lsm6dso32_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.sim = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2331,25 +2835,32 @@ int32_t lsm6dso32_spi_mode_set(stmdev_ctx_t *ctx, lsm6dso32_sim_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of sim in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_spi_mode_get(stmdev_ctx_t *ctx, lsm6dso32_sim_t *val)
+int32_t lsm6dso32_spi_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32_sim_t *val)
{
lsm6dso32_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t*)®, 1);
- switch (reg.sim) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
+
+ switch (reg.sim)
+ {
case LSM6DSO32_SPI_4_WIRE:
*val = LSM6DSO32_SPI_4_WIRE;
break;
+
case LSM6DSO32_SPI_3_WIRE:
*val = LSM6DSO32_SPI_3_WIRE;
break;
+
default:
*val = LSM6DSO32_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -2359,6 +2870,7 @@ int32_t lsm6dso32_spi_mode_get(stmdev_ctx_t *ctx, lsm6dso32_sim_t *val)
* @param ctx read / write interface definitions
* @param val change the values of i2c_disable in
* reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_i2c_interface_set(stmdev_ctx_t *ctx,
@@ -2367,11 +2879,14 @@ int32_t lsm6dso32_i2c_interface_set(stmdev_ctx_t *ctx,
lsm6dso32_ctrl4_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.i2c_disable = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2381,6 +2896,7 @@ int32_t lsm6dso32_i2c_interface_set(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val Get the values of i2c_disable in
* reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_i2c_interface_get(stmdev_ctx_t *ctx,
@@ -2389,18 +2905,23 @@ int32_t lsm6dso32_i2c_interface_get(stmdev_ctx_t *ctx,
lsm6dso32_ctrl4_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t*)®, 1);
- switch (reg.i2c_disable) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
+
+ switch (reg.i2c_disable)
+ {
case LSM6DSO32_I2C_ENABLE:
*val = LSM6DSO32_I2C_ENABLE;
break;
+
case LSM6DSO32_I2C_DISABLE:
*val = LSM6DSO32_I2C_DISABLE;
break;
+
default:
*val = LSM6DSO32_I2C_ENABLE;
break;
}
+
return ret;
}
@@ -2409,6 +2930,7 @@ int32_t lsm6dso32_i2c_interface_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of i3c_disable in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_i3c_disable_set(stmdev_ctx_t *ctx,
@@ -2419,21 +2941,26 @@ int32_t lsm6dso32_i3c_disable_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
- if (ret == 0) {
+ (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
+ (uint8_t *)&ctrl9_xl, 1);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
}
return ret;
@@ -2444,6 +2971,7 @@ int32_t lsm6dso32_i3c_disable_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of i3c_disable in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_i3c_disable_get(stmdev_ctx_t *ctx,
@@ -2453,32 +2981,42 @@ int32_t lsm6dso32_i3c_disable_get(stmdev_ctx_t *ctx,
lsm6dso32_i3c_bus_avb_t i3c_bus_avb;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
- switch ((ctrl9_xl.i3c_disable << 7) | i3c_bus_avb.i3c_bus_avb_sel) {
+ switch ((ctrl9_xl.i3c_disable << 7) | i3c_bus_avb.i3c_bus_avb_sel)
+ {
case LSM6DSO32_I3C_DISABLE:
*val = LSM6DSO32_I3C_DISABLE;
break;
+
case LSM6DSO32_I3C_ENABLE_T_50us:
*val = LSM6DSO32_I3C_ENABLE_T_50us;
break;
+
case LSM6DSO32_I3C_ENABLE_T_2us:
*val = LSM6DSO32_I3C_ENABLE_T_2us;
break;
+
case LSM6DSO32_I3C_ENABLE_T_1ms:
*val = LSM6DSO32_I3C_ENABLE_T_1ms;
break;
+
case LSM6DSO32_I3C_ENABLE_T_25ms:
*val = LSM6DSO32_I3C_ENABLE_T_25ms;
break;
+
default:
*val = LSM6DSO32_I3C_DISABLE;
break;
}
}
+
return ret;
}
@@ -2489,7 +3027,7 @@ int32_t lsm6dso32_i3c_disable_get(stmdev_ctx_t *ctx,
/**
* @defgroup LSM6DSO32_interrupt_pins
- * @brief This section groups all the functions that manage interrup pins
+ * @brief This section groups all the functions that manage interrupt pins
* @{
*
*/
@@ -2499,6 +3037,7 @@ int32_t lsm6dso32_i3c_disable_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of pd_dis_int1 in reg I3C_BUS_AVB
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_int1_mode_set(stmdev_ctx_t *ctx,
@@ -2507,11 +3046,14 @@ int32_t lsm6dso32_int1_mode_set(stmdev_ctx_t *ctx,
lsm6dso32_i3c_bus_avb_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_I3C_BUS_AVB, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_I3C_BUS_AVB, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.pd_dis_int1 = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_I3C_BUS_AVB, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_I3C_BUS_AVB, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2520,6 +3062,7 @@ int32_t lsm6dso32_int1_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of pd_dis_int1 in reg I3C_BUS_AVB
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_int1_mode_get(stmdev_ctx_t *ctx,
@@ -2528,18 +3071,23 @@ int32_t lsm6dso32_int1_mode_get(stmdev_ctx_t *ctx,
lsm6dso32_i3c_bus_avb_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_I3C_BUS_AVB, (uint8_t*)®, 1);
- switch (reg.pd_dis_int1) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_I3C_BUS_AVB, (uint8_t *)®, 1);
+
+ switch (reg.pd_dis_int1)
+ {
case LSM6DSO32_PULL_DOWN_DISC:
*val = LSM6DSO32_PULL_DOWN_DISC;
break;
+
case LSM6DSO32_PULL_DOWN_CONNECT:
*val = LSM6DSO32_PULL_DOWN_CONNECT;
break;
+
default:
*val = LSM6DSO32_PULL_DOWN_DISC;
break;
}
+
return ret;
}
@@ -2550,6 +3098,7 @@ int32_t lsm6dso32_int1_mode_get(stmdev_ctx_t *ctx,
* @param val struct of registers: INT1_CTRL,
* MD1_CFG, EMB_FUNC_INT1, FSM_INT1_A,
* FSM_INT1_B
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_pin_int1_route_set(stmdev_ctx_t *ctx,
@@ -2560,24 +3109,33 @@ int32_t lsm6dso32_pin_int1_route_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_INT1,
- (uint8_t*)&val->emb_func_int1, 1);
+ (uint8_t *)&val->emb_func_int1, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FSM_INT1_A,
- (uint8_t*)&val->fsm_int1_a, 1);
+ (uint8_t *)&val->fsm_int1_a, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FSM_INT1_B,
- (uint8_t*)&val->fsm_int1_b, 1);
+ (uint8_t *)&val->fsm_int1_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
- if (ret == 0) {
- if ( ( val->emb_func_int1.int1_fsm_lc
+ if (ret == 0)
+ {
+ if ((val->emb_func_int1.int1_fsm_lc
| val->emb_func_int1.int1_sig_mot
| val->emb_func_int1.int1_step_detector
| val->emb_func_int1.int1_tilt
@@ -2596,29 +3154,40 @@ int32_t lsm6dso32_pin_int1_route_set(stmdev_ctx_t *ctx,
| val->fsm_int1_b.int1_fsm13
| val->fsm_int1_b.int1_fsm14
| val->fsm_int1_b.int1_fsm15
- | val->fsm_int1_b.int1_fsm16) != PROPERTY_DISABLE){
+ | val->fsm_int1_b.int1_fsm16) != PROPERTY_DISABLE)
+ {
val->md1_cfg.int1_emb_func = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
val->md1_cfg.int1_emb_func = PROPERTY_DISABLE;
}
+
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_INT1_CTRL,
- (uint8_t*)&val->int1_ctrl, 1);
+ (uint8_t *)&val->int1_ctrl, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MD1_CFG,
- (uint8_t*)&val->md1_cfg, 1);
+ (uint8_t *)&val->md1_cfg, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG2,
- (uint8_t*) &tap_cfg2, 1);
+ (uint8_t *) &tap_cfg2, 1);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dso32_pin_int2_route_get(ctx, &pin_int2_route);
}
- if (ret == 0) {
- if ( ( pin_int2_route.int2_ctrl.int2_cnt_bdr
+
+ if (ret == 0)
+ {
+ if ((pin_int2_route.int2_ctrl.int2_cnt_bdr
| pin_int2_route.int2_ctrl.int2_drdy_g
| pin_int2_route.int2_ctrl.int2_drdy_temp
| pin_int2_route.int2_ctrl.int2_drdy_xl
@@ -2644,15 +3213,20 @@ int32_t lsm6dso32_pin_int1_route_set(stmdev_ctx_t *ctx,
| val->md1_cfg.int1_ff
| val->md1_cfg.int1_wu
| val->md1_cfg.int1_single_tap
- | val->md1_cfg.int1_sleep_change) != PROPERTY_DISABLE) {
+ | val->md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
+ {
tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
}
+
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG2,
- (uint8_t*) &tap_cfg2, 1);
+ (uint8_t *) &tap_cfg2, 1);
}
+
return ret;
}
@@ -2662,6 +3236,7 @@ int32_t lsm6dso32_pin_int1_route_set(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val struct of registers: INT1_CTRL, MD1_CFG,
* EMB_FUNC_INT1, FSM_INT1_A, FSM_INT1_B
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_pin_int1_route_get(stmdev_ctx_t *ctx,
@@ -2670,29 +3245,40 @@ int32_t lsm6dso32_pin_int1_route_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_INT1,
- (uint8_t*)&val->emb_func_int1, 1);
+ (uint8_t *)&val->emb_func_int1, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_INT1_A,
- (uint8_t*)&val->fsm_int1_a, 1);
+ (uint8_t *)&val->fsm_int1_a, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_INT1_B,
- (uint8_t*)&val->fsm_int1_b, 1);
+ (uint8_t *)&val->fsm_int1_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT1_CTRL,
- (uint8_t*)&val->int1_ctrl, 1);
+ (uint8_t *)&val->int1_ctrl, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MD1_CFG,
- (uint8_t*)&val->md1_cfg, 1);
+ (uint8_t *)&val->md1_cfg, 1);
}
return ret;
@@ -2704,6 +3290,7 @@ int32_t lsm6dso32_pin_int1_route_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val union of registers INT2_CTRL, MD2_CFG,
* EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_pin_int2_route_set(stmdev_ctx_t *ctx,
@@ -2714,66 +3301,85 @@ int32_t lsm6dso32_pin_int2_route_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_INT2,
- (uint8_t*)&val->emb_func_int2, 1);
+ (uint8_t *)&val->emb_func_int2, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FSM_INT2_A,
- (uint8_t*)&val->fsm_int2_a, 1);
+ (uint8_t *)&val->fsm_int2_a, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FSM_INT2_B,
- (uint8_t*)&val->fsm_int2_b, 1);
+ (uint8_t *)&val->fsm_int2_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
- if (ret == 0) {
- if (( val->emb_func_int2.int2_fsm_lc
- | val->emb_func_int2.int2_sig_mot
- | val->emb_func_int2.int2_step_detector
- | val->emb_func_int2.int2_tilt
- | val->fsm_int2_a.int2_fsm1
- | val->fsm_int2_a.int2_fsm2
- | val->fsm_int2_a.int2_fsm3
- | val->fsm_int2_a.int2_fsm4
- | val->fsm_int2_a.int2_fsm5
- | val->fsm_int2_a.int2_fsm6
- | val->fsm_int2_a.int2_fsm7
- | val->fsm_int2_a.int2_fsm8
- | val->fsm_int2_b.int2_fsm9
- | val->fsm_int2_b.int2_fsm10
- | val->fsm_int2_b.int2_fsm11
- | val->fsm_int2_b.int2_fsm12
- | val->fsm_int2_b.int2_fsm13
- | val->fsm_int2_b.int2_fsm14
- | val->fsm_int2_b.int2_fsm15
- | val->fsm_int2_b.int2_fsm16 )!= PROPERTY_DISABLE ){
+ if (ret == 0)
+ {
+ if ((val->emb_func_int2.int2_fsm_lc
+ | val->emb_func_int2.int2_sig_mot
+ | val->emb_func_int2.int2_step_detector
+ | val->emb_func_int2.int2_tilt
+ | val->fsm_int2_a.int2_fsm1
+ | val->fsm_int2_a.int2_fsm2
+ | val->fsm_int2_a.int2_fsm3
+ | val->fsm_int2_a.int2_fsm4
+ | val->fsm_int2_a.int2_fsm5
+ | val->fsm_int2_a.int2_fsm6
+ | val->fsm_int2_a.int2_fsm7
+ | val->fsm_int2_a.int2_fsm8
+ | val->fsm_int2_b.int2_fsm9
+ | val->fsm_int2_b.int2_fsm10
+ | val->fsm_int2_b.int2_fsm11
+ | val->fsm_int2_b.int2_fsm12
+ | val->fsm_int2_b.int2_fsm13
+ | val->fsm_int2_b.int2_fsm14
+ | val->fsm_int2_b.int2_fsm15
+ | val->fsm_int2_b.int2_fsm16) != PROPERTY_DISABLE)
+ {
val->md2_cfg.int2_emb_func = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
val->md2_cfg.int2_emb_func = PROPERTY_DISABLE;
}
+
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_INT2_CTRL,
- (uint8_t*)&val->int2_ctrl, 1);
+ (uint8_t *)&val->int2_ctrl, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MD2_CFG,
- (uint8_t*)&val->md2_cfg, 1);
+ (uint8_t *)&val->md2_cfg, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG2,
- (uint8_t*) &tap_cfg2, 1);
+ (uint8_t *) &tap_cfg2, 1);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dso32_pin_int1_route_get(ctx, &pin_int1_route);
}
- if (ret == 0) {
- if ( ( val->int2_ctrl.int2_cnt_bdr
+ if (ret == 0)
+ {
+ if ((val->int2_ctrl.int2_cnt_bdr
| val->int2_ctrl.int2_drdy_g
| val->int2_ctrl.int2_drdy_temp
| val->int2_ctrl.int2_drdy_xl
@@ -2799,15 +3405,20 @@ int32_t lsm6dso32_pin_int2_route_set(stmdev_ctx_t *ctx,
| pin_int1_route.md1_cfg.int1_ff
| pin_int1_route.md1_cfg.int1_wu
| pin_int1_route.md1_cfg.int1_single_tap
- | pin_int1_route.md1_cfg.int1_sleep_change ) != PROPERTY_DISABLE) {
+ | pin_int1_route.md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
+ {
tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
}
+
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG2,
- (uint8_t*) &tap_cfg2, 1);
+ (uint8_t *) &tap_cfg2, 1);
}
+
return ret;
}
@@ -2817,6 +3428,7 @@ int32_t lsm6dso32_pin_int2_route_set(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val union of registers INT2_CTRL, MD2_CFG,
* EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_pin_int2_route_get(stmdev_ctx_t *ctx,
@@ -2825,30 +3437,42 @@ int32_t lsm6dso32_pin_int2_route_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_INT2,
- (uint8_t*)&val->emb_func_int2, 1);
+ (uint8_t *)&val->emb_func_int2, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_INT2_A,
- (uint8_t*)&val->fsm_int2_a, 1);
+ (uint8_t *)&val->fsm_int2_a, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_INT2_B,
- (uint8_t*)&val->fsm_int2_b, 1);
+ (uint8_t *)&val->fsm_int2_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT2_CTRL,
- (uint8_t*)&val->int2_ctrl, 1);
+ (uint8_t *)&val->int2_ctrl, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MD2_CFG,
- (uint8_t*)&val->md2_cfg, 1);
+ (uint8_t *)&val->md2_cfg, 1);
}
+
return ret;
}
@@ -2857,18 +3481,23 @@ int32_t lsm6dso32_pin_int2_route_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of pp_od in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_pin_mode_set(stmdev_ctx_t *ctx, lsm6dso32_pp_od_t val)
+int32_t lsm6dso32_pin_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32_pp_od_t val)
{
lsm6dso32_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.pp_od = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2877,26 +3506,32 @@ int32_t lsm6dso32_pin_mode_set(stmdev_ctx_t *ctx, lsm6dso32_pp_od_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of pp_od in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_pin_mode_get(stmdev_ctx_t *ctx, lsm6dso32_pp_od_t *val)
+int32_t lsm6dso32_pin_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32_pp_od_t *val)
{
lsm6dso32_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
- switch (reg.pp_od) {
+ switch (reg.pp_od)
+ {
case LSM6DSO32_PUSH_PULL:
*val = LSM6DSO32_PUSH_PULL;
break;
+
case LSM6DSO32_OPEN_DRAIN:
*val = LSM6DSO32_OPEN_DRAIN;
break;
+
default:
*val = LSM6DSO32_PUSH_PULL;
break;
}
+
return ret;
}
@@ -2905,6 +3540,7 @@ int32_t lsm6dso32_pin_mode_get(stmdev_ctx_t *ctx, lsm6dso32_pp_od_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of h_lactive in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_pin_polarity_set(stmdev_ctx_t *ctx,
@@ -2913,10 +3549,12 @@ int32_t lsm6dso32_pin_polarity_set(stmdev_ctx_t *ctx,
lsm6dso32_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.h_lactive = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
}
return ret;
@@ -2927,6 +3565,7 @@ int32_t lsm6dso32_pin_polarity_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of h_lactive in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_pin_polarity_get(stmdev_ctx_t *ctx,
@@ -2935,19 +3574,23 @@ int32_t lsm6dso32_pin_polarity_get(stmdev_ctx_t *ctx,
lsm6dso32_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
- switch (reg.h_lactive) {
+ switch (reg.h_lactive)
+ {
case LSM6DSO32_ACTIVE_HIGH:
*val = LSM6DSO32_ACTIVE_HIGH;
break;
+
case LSM6DSO32_ACTIVE_LOW:
*val = LSM6DSO32_ACTIVE_LOW;
break;
+
default:
*val = LSM6DSO32_ACTIVE_HIGH;
break;
}
+
return ret;
}
@@ -2956,6 +3599,7 @@ int32_t lsm6dso32_pin_polarity_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of int2_on_int1 in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -2963,10 +3607,12 @@ int32_t lsm6dso32_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso32_ctrl4_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.int2_on_int1 = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
}
return ret;
@@ -2977,6 +3623,7 @@ int32_t lsm6dso32_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of int2_on_int1 in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -2984,7 +3631,7 @@ int32_t lsm6dso32_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso32_ctrl4_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
*val = reg.int2_on_int1;
return ret;
@@ -2995,6 +3642,7 @@ int32_t lsm6dso32_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of lir in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_int_notification_set(stmdev_ctx_t *ctx,
@@ -3004,25 +3652,36 @@ int32_t lsm6dso32_int_notification_set(stmdev_ctx_t *ctx,
lsm6dso32_page_rw_t page_rw;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0,
+ (uint8_t *) &tap_cfg0, 1);
+
+ if (ret == 0)
+ {
tap_cfg0.lir = (uint8_t)val & 0x01U;
tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG0,
- (uint8_t*) &tap_cfg0, 1);
+ (uint8_t *) &tap_cfg0, 1);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
}
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t*) &page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t*) &page_rw, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW,
+ (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -3034,6 +3693,7 @@ int32_t lsm6dso32_int_notification_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of lir in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_int_notification_get(stmdev_ctx_t *ctx,
@@ -3043,42 +3703,59 @@ int32_t lsm6dso32_int_notification_get(stmdev_ctx_t *ctx,
lsm6dso32_page_rw_t page_rw;
int32_t ret;
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0,
+ (uint8_t *) &tap_cfg0, 1);
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
- if (ret == 0) {
-
- ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
+ if (ret == 0)
+ {
+ ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
}
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t*) &page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
- if (ret == 0) {
- switch ((page_rw.emb_func_lir << 1) | tap_cfg0.lir) {
+
+ if (ret == 0)
+ {
+ switch ((page_rw.emb_func_lir << 1) | tap_cfg0.lir)
+ {
case LSM6DSO32_ALL_INT_PULSED:
*val = LSM6DSO32_ALL_INT_PULSED;
break;
+
case LSM6DSO32_BASE_LATCHED_EMB_PULSED:
*val = LSM6DSO32_BASE_LATCHED_EMB_PULSED;
break;
+
case LSM6DSO32_BASE_PULSED_EMB_LATCHED:
*val = LSM6DSO32_BASE_PULSED_EMB_LATCHED;
break;
+
case LSM6DSO32_ALL_INT_LATCHED:
*val = LSM6DSO32_ALL_INT_LATCHED;
break;
+
default:
*val = LSM6DSO32_ALL_INT_PULSED;
break;
}
+
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
}
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t*) &page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -3106,6 +3783,7 @@ int32_t lsm6dso32_int_notification_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of wake_ths_w in
* reg WAKE_UP_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_wkup_ths_weight_set(stmdev_ctx_t *ctx,
@@ -3114,11 +3792,14 @@ int32_t lsm6dso32_wkup_ths_weight_set(stmdev_ctx_t *ctx,
lsm6dso32_wake_up_dur_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.wake_ths_w = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3130,6 +3811,7 @@ int32_t lsm6dso32_wkup_ths_weight_set(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val Get the values of wake_ths_w in
* reg WAKE_UP_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_wkup_ths_weight_get(stmdev_ctx_t *ctx,
@@ -3138,19 +3820,23 @@ int32_t lsm6dso32_wkup_ths_weight_get(stmdev_ctx_t *ctx,
lsm6dso32_wake_up_dur_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)®, 1);
- switch (reg.wake_ths_w) {
+ switch (reg.wake_ths_w)
+ {
case LSM6DSO32_LSb_FS_DIV_64:
*val = LSM6DSO32_LSb_FS_DIV_64;
break;
+
case LSM6DSO32_LSb_FS_DIV_256:
*val = LSM6DSO32_LSb_FS_DIV_256;
break;
+
default:
*val = LSM6DSO32_LSb_FS_DIV_64;
break;
}
+
return ret;
}
@@ -3160,6 +3846,7 @@ int32_t lsm6dso32_wkup_ths_weight_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of wk_ths in reg WAKE_UP_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -3167,11 +3854,14 @@ int32_t lsm6dso32_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso32_wake_up_ths_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.wk_ths = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3181,6 +3871,7 @@ int32_t lsm6dso32_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of wk_ths in reg WAKE_UP_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -3188,7 +3879,7 @@ int32_t lsm6dso32_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso32_wake_up_ths_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t *)®, 1);
*val = reg.wk_ths;
return ret;
@@ -3200,18 +3891,23 @@ int32_t lsm6dso32_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of usr_off_on_wu in reg WAKE_UP_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dso32_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dso32_wake_up_ths_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.usr_off_on_wu = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3221,14 +3917,16 @@ int32_t lsm6dso32_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of usr_off_on_wu in reg WAKE_UP_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso32_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso32_wake_up_ths_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t *)®, 1);
*val = reg.usr_off_on_wu;
return ret;
@@ -3240,6 +3938,7 @@ int32_t lsm6dso32_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of wake_dur in reg WAKE_UP_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -3247,11 +3946,14 @@ int32_t lsm6dso32_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso32_wake_up_dur_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.wake_dur = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3261,6 +3963,7 @@ int32_t lsm6dso32_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of wake_dur in reg WAKE_UP_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -3268,7 +3971,7 @@ int32_t lsm6dso32_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso32_wake_up_dur_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)®, 1);
*val = reg.wake_dur;
return ret;
@@ -3285,13 +3988,14 @@ int32_t lsm6dso32_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
* activity/inactivity detection.
* @{
*
-*/
+ */
/**
* @brief Enables gyroscope Sleep mode.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of sleep_g in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -3299,11 +4003,14 @@ int32_t lsm6dso32_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso32_ctrl4_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.sleep_g = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3312,6 +4019,7 @@ int32_t lsm6dso32_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of sleep_g in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -3319,7 +4027,7 @@ int32_t lsm6dso32_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso32_ctrl4_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
*val = reg.sleep_g;
return ret;
@@ -3333,6 +4041,7 @@ int32_t lsm6dso32_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of sleep_status_on_int in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_act_pin_notification_set(stmdev_ctx_t *ctx,
@@ -3341,11 +4050,14 @@ int32_t lsm6dso32_act_pin_notification_set(stmdev_ctx_t *ctx,
lsm6dso32_tap_cfg0_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.sleep_status_on_int = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3357,6 +4069,7 @@ int32_t lsm6dso32_act_pin_notification_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of sleep_status_on_int in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_act_pin_notification_get(stmdev_ctx_t *ctx,
@@ -3365,18 +4078,23 @@ int32_t lsm6dso32_act_pin_notification_get(stmdev_ctx_t *ctx,
lsm6dso32_tap_cfg0_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t*)®, 1);
- switch (reg.sleep_status_on_int) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
+
+ switch (reg.sleep_status_on_int)
+ {
case LSM6DSO32_DRIVE_SLEEP_CHG_EVENT:
*val = LSM6DSO32_DRIVE_SLEEP_CHG_EVENT;
break;
+
case LSM6DSO32_DRIVE_SLEEP_STATUS:
*val = LSM6DSO32_DRIVE_SLEEP_STATUS;
break;
+
default:
*val = LSM6DSO32_DRIVE_SLEEP_CHG_EVENT;
break;
}
+
return ret;
}
@@ -3385,18 +4103,23 @@ int32_t lsm6dso32_act_pin_notification_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of inact_en in reg TAP_CFG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_act_mode_set(stmdev_ctx_t *ctx, lsm6dso32_inact_en_t val)
+int32_t lsm6dso32_act_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32_inact_en_t val)
{
lsm6dso32_tap_cfg2_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG2, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.inact_en = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG2, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3405,31 +4128,40 @@ int32_t lsm6dso32_act_mode_set(stmdev_ctx_t *ctx, lsm6dso32_inact_en_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of inact_en in reg TAP_CFG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_act_mode_get(stmdev_ctx_t *ctx, lsm6dso32_inact_en_t *val)
+int32_t lsm6dso32_act_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32_inact_en_t *val)
{
lsm6dso32_tap_cfg2_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG2, (uint8_t*)®, 1);
- switch (reg.inact_en) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG2, (uint8_t *)®, 1);
+
+ switch (reg.inact_en)
+ {
case LSM6DSO32_XL_AND_GY_NOT_AFFECTED:
*val = LSM6DSO32_XL_AND_GY_NOT_AFFECTED;
break;
+
case LSM6DSO32_XL_12Hz5_GY_NOT_AFFECTED:
*val = LSM6DSO32_XL_12Hz5_GY_NOT_AFFECTED;
break;
+
case LSM6DSO32_XL_12Hz5_GY_SLEEP:
*val = LSM6DSO32_XL_12Hz5_GY_SLEEP;
break;
+
case LSM6DSO32_XL_12Hz5_GY_PD:
*val = LSM6DSO32_XL_12Hz5_GY_PD;
break;
+
default:
*val = LSM6DSO32_XL_AND_GY_NOT_AFFECTED;
break;
}
+
return ret;
}
@@ -3439,6 +4171,7 @@ int32_t lsm6dso32_act_mode_get(stmdev_ctx_t *ctx, lsm6dso32_inact_en_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of sleep_dur in reg WAKE_UP_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -3446,11 +4179,14 @@ int32_t lsm6dso32_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso32_wake_up_dur_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.sleep_dur = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3460,6 +4196,7 @@ int32_t lsm6dso32_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of sleep_dur in reg WAKE_UP_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -3467,7 +4204,7 @@ int32_t lsm6dso32_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso32_wake_up_dur_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)®, 1);
*val = reg.sleep_dur;
return ret;
@@ -3491,18 +4228,23 @@ int32_t lsm6dso32_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_z_en in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dso32_tap_detection_on_z_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dso32_tap_cfg0_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.tap_z_en = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3511,14 +4253,16 @@ int32_t lsm6dso32_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_z_en in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso32_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso32_tap_cfg0_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
*val = reg.tap_z_en;
return ret;
@@ -3529,18 +4273,23 @@ int32_t lsm6dso32_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_y_en in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dso32_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dso32_tap_cfg0_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.tap_y_en = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3549,14 +4298,16 @@ int32_t lsm6dso32_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_y_en in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso32_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso32_tap_cfg0_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
*val = reg.tap_y_en;
return ret;
@@ -3567,18 +4318,23 @@ int32_t lsm6dso32_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_x_en in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dso32_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dso32_tap_cfg0_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.tap_x_en = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3587,14 +4343,16 @@ int32_t lsm6dso32_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_x_en in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso32_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso32_tap_cfg0_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
*val = reg.tap_x_en;
return ret;
@@ -3605,6 +4363,7 @@ int32_t lsm6dso32_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_ths_x in reg TAP_CFG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -3612,11 +4371,14 @@ int32_t lsm6dso32_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso32_tap_cfg1_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG1, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG1, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.tap_ths_x = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG1, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG1, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3625,6 +4387,7 @@ int32_t lsm6dso32_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_ths_x in reg TAP_CFG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -3632,7 +4395,7 @@ int32_t lsm6dso32_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso32_tap_cfg1_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG1, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG1, (uint8_t *)®, 1);
*val = reg.tap_ths_x;
return ret;
@@ -3643,19 +4406,23 @@ int32_t lsm6dso32_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_priority in reg TAP_CFG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_tap_axis_priority_set(stmdev_ctx_t *ctx,
- lsm6dso32_tap_priority_t val)
+ lsm6dso32_tap_priority_t val)
{
lsm6dso32_tap_cfg1_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG1, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG1, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.tap_priority = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG1, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG1, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3664,6 +4431,7 @@ int32_t lsm6dso32_tap_axis_priority_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of tap_priority in reg TAP_CFG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_tap_axis_priority_get(stmdev_ctx_t *ctx,
@@ -3672,30 +4440,39 @@ int32_t lsm6dso32_tap_axis_priority_get(stmdev_ctx_t *ctx,
lsm6dso32_tap_cfg1_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG1, (uint8_t*)®, 1);
- switch (reg.tap_priority) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG1, (uint8_t *)®, 1);
+
+ switch (reg.tap_priority)
+ {
case LSM6DSO32_XYZ:
*val = LSM6DSO32_XYZ;
break;
+
case LSM6DSO32_YXZ:
*val = LSM6DSO32_YXZ;
break;
+
case LSM6DSO32_XZY:
*val = LSM6DSO32_XZY;
break;
+
case LSM6DSO32_ZYX:
*val = LSM6DSO32_ZYX;
break;
+
case LSM6DSO32_YZX:
*val = LSM6DSO32_YZX;
break;
+
case LSM6DSO32_ZXY:
*val = LSM6DSO32_ZXY;
break;
+
default:
*val = LSM6DSO32_XYZ;
break;
}
+
return ret;
}
@@ -3704,6 +4481,7 @@ int32_t lsm6dso32_tap_axis_priority_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of tap_ths_y in reg TAP_CFG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -3711,11 +4489,14 @@ int32_t lsm6dso32_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso32_tap_cfg2_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG2, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.tap_ths_y = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG2, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3724,6 +4505,7 @@ int32_t lsm6dso32_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_ths_y in reg TAP_CFG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -3731,7 +4513,7 @@ int32_t lsm6dso32_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso32_tap_cfg2_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG2, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG2, (uint8_t *)®, 1);
*val = reg.tap_ths_y;
return ret;
@@ -3742,6 +4524,7 @@ int32_t lsm6dso32_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_ths_z in reg TAP_THS_6D
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -3749,11 +4532,14 @@ int32_t lsm6dso32_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso32_tap_ths_6d_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.tap_ths_z = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3762,6 +4548,7 @@ int32_t lsm6dso32_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_ths_z in reg TAP_THS_6D
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -3769,7 +4556,7 @@ int32_t lsm6dso32_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso32_tap_ths_6d_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t *)®, 1);
*val = reg.tap_ths_z;
return ret;
@@ -3785,6 +4572,7 @@ int32_t lsm6dso32_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of shock in reg INT_DUR2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -3792,11 +4580,14 @@ int32_t lsm6dso32_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso32_int_dur2_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.shock = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3810,6 +4601,7 @@ int32_t lsm6dso32_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of shock in reg INT_DUR2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -3817,7 +4609,7 @@ int32_t lsm6dso32_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso32_int_dur2_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t *)®, 1);
*val = reg.shock;
return ret;
@@ -3834,6 +4626,7 @@ int32_t lsm6dso32_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of quiet in reg INT_DUR2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -3841,11 +4634,14 @@ int32_t lsm6dso32_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso32_int_dur2_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.quiet = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3860,6 +4656,7 @@ int32_t lsm6dso32_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of quiet in reg INT_DUR2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -3867,7 +4664,7 @@ int32_t lsm6dso32_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso32_int_dur2_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t *)®, 1);
*val = reg.quiet;
return ret;
@@ -3885,6 +4682,7 @@ int32_t lsm6dso32_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of dur in reg INT_DUR2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -3892,11 +4690,14 @@ int32_t lsm6dso32_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso32_int_dur2_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.dur = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3912,6 +4713,7 @@ int32_t lsm6dso32_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of dur in reg INT_DUR2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -3919,7 +4721,7 @@ int32_t lsm6dso32_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso32_int_dur2_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t *)®, 1);
*val = reg.dur;
return ret;
@@ -3930,6 +4732,7 @@ int32_t lsm6dso32_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of single_double_tap in reg WAKE_UP_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_tap_mode_set(stmdev_ctx_t *ctx,
@@ -3938,11 +4741,14 @@ int32_t lsm6dso32_tap_mode_set(stmdev_ctx_t *ctx,
lsm6dso32_wake_up_ths_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.single_double_tap = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3951,6 +4757,7 @@ int32_t lsm6dso32_tap_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of single_double_tap in reg WAKE_UP_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_tap_mode_get(stmdev_ctx_t *ctx,
@@ -3959,15 +4766,18 @@ int32_t lsm6dso32_tap_mode_get(stmdev_ctx_t *ctx,
lsm6dso32_wake_up_ths_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t *)®, 1);
- switch (reg.single_double_tap) {
+ switch (reg.single_double_tap)
+ {
case LSM6DSO32_ONLY_SINGLE:
*val = LSM6DSO32_ONLY_SINGLE;
break;
+
case LSM6DSO32_BOTH_SINGLE_DOUBLE:
*val = LSM6DSO32_BOTH_SINGLE_DOUBLE;
break;
+
default:
*val = LSM6DSO32_ONLY_SINGLE;
break;
@@ -3994,6 +4804,7 @@ int32_t lsm6dso32_tap_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of sixd_ths in reg TAP_THS_6D
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_6d_threshold_set(stmdev_ctx_t *ctx,
@@ -4002,11 +4813,14 @@ int32_t lsm6dso32_6d_threshold_set(stmdev_ctx_t *ctx,
lsm6dso32_tap_ths_6d_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.sixd_ths = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4015,6 +4829,7 @@ int32_t lsm6dso32_6d_threshold_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of sixd_ths in reg TAP_THS_6D
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_6d_threshold_get(stmdev_ctx_t *ctx,
@@ -4023,18 +4838,23 @@ int32_t lsm6dso32_6d_threshold_get(stmdev_ctx_t *ctx,
lsm6dso32_tap_ths_6d_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t*)®, 1);
- switch (reg.sixd_ths) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t *)®, 1);
+
+ switch (reg.sixd_ths)
+ {
case LSM6DSO32_DEG_68:
*val = LSM6DSO32_DEG_68;
break;
+
case LSM6DSO32_DEG_47:
*val = LSM6DSO32_DEG_47;
break;
+
default:
*val = LSM6DSO32_DEG_68;
break;
}
+
return ret;
}
@@ -4043,6 +4863,7 @@ int32_t lsm6dso32_6d_threshold_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of d4d_en in reg TAP_THS_6D
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -4050,11 +4871,14 @@ int32_t lsm6dso32_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso32_tap_ths_6d_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.d4d_en = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4063,6 +4887,7 @@ int32_t lsm6dso32_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of d4d_en in reg TAP_THS_6D
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -4070,7 +4895,7 @@ int32_t lsm6dso32_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso32_tap_ths_6d_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t *)®, 1);
*val = reg.d4d_en;
return ret;
@@ -4094,6 +4919,7 @@ int32_t lsm6dso32_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of ff_ths in reg FREE_FALL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_ff_threshold_set(stmdev_ctx_t *ctx,
@@ -4102,11 +4928,14 @@ int32_t lsm6dso32_ff_threshold_set(stmdev_ctx_t *ctx,
lsm6dso32_free_fall_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FREE_FALL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FREE_FALL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.ff_ths = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FREE_FALL, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FREE_FALL, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4115,6 +4944,7 @@ int32_t lsm6dso32_ff_threshold_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of ff_ths in reg FREE_FALL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_ff_threshold_get(stmdev_ctx_t *ctx,
@@ -4123,21 +4953,27 @@ int32_t lsm6dso32_ff_threshold_get(stmdev_ctx_t *ctx,
lsm6dso32_free_fall_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FREE_FALL, (uint8_t*)®, 1);
- switch (reg.ff_ths) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FREE_FALL, (uint8_t *)®, 1);
+
+ switch (reg.ff_ths)
+ {
case LSM6DSO32_FF_TSH_312mg:
*val = LSM6DSO32_FF_TSH_312mg;
break;
+
case LSM6DSO32_FF_TSH_438mg:
*val = LSM6DSO32_FF_TSH_438mg;
break;
+
case LSM6DSO32_FF_TSH_500mg:
*val = LSM6DSO32_FF_TSH_500mg;
break;
+
default:
*val = LSM6DSO32_FF_TSH_312mg;
break;
}
+
return ret;
}
@@ -4147,6 +4983,7 @@ int32_t lsm6dso32_ff_threshold_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of ff_dur in reg FREE_FALL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -4156,21 +4993,28 @@ int32_t lsm6dso32_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if (ret == 0) {
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FREE_FALL,
- (uint8_t*)&free_fall, 1);
+ (uint8_t *)&free_fall, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5;
free_fall.ff_dur = (uint8_t)val & 0x1FU;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FREE_FALL,
- (uint8_t*)&free_fall, 1);
+ (uint8_t *)&free_fall, 1);
}
+
return ret;
}
@@ -4180,6 +5024,7 @@ int32_t lsm6dso32_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of ff_dur in reg FREE_FALL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -4189,12 +5034,15 @@ int32_t lsm6dso32_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if (ret == 0) {
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FREE_FALL,
- (uint8_t*)&free_fall, 1);
+ (uint8_t *)&free_fall, 1);
*val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
}
+
return ret;
}
@@ -4215,6 +5063,7 @@ int32_t lsm6dso32_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of wtm in reg FIFO_CTRL1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
@@ -4224,17 +5073,22 @@ int32_t lsm6dso32_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
int32_t ret;
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if (ret == 0) {
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl1.wtm = 0x00FFU & (uint8_t)val;
- fifo_ctrl2.wtm = (uint8_t)(( 0x0100U & val ) >> 8);
+ fifo_ctrl2.wtm = (uint8_t)((0x0100U & val) >> 8);
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL1,
- (uint8_t*)&fifo_ctrl1, 1);
+ (uint8_t *)&fifo_ctrl1, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
+
return ret;
}
@@ -4243,6 +5097,7 @@ int32_t lsm6dso32_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of wtm in reg FIFO_CTRL1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
@@ -4252,12 +5107,15 @@ int32_t lsm6dso32_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
int32_t ret;
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL1,
- (uint8_t*)&fifo_ctrl1, 1);
- if (ret == 0) {
+ (uint8_t *)&fifo_ctrl1, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
*val = ((uint16_t)fifo_ctrl2.wtm << 8) + (uint16_t)fifo_ctrl1.wtm;
}
+
return ret;
}
@@ -4267,24 +5125,32 @@ int32_t lsm6dso32_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
* @param ctx read / write interface definitions
* @param val change the values of FIFO_COMPR_INIT in
* reg EMB_FUNC_INIT_B
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_compression_algo_init_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dso32_compression_algo_init_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dso32_emb_func_init_b_t reg;
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_INIT_B,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.fifo_compr_init = val;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_INIT_B,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -4297,6 +5163,7 @@ int32_t lsm6dso32_compression_algo_init_set(stmdev_ctx_t *ctx, uint8_t val)
* @param ctx read / write interface definitions
* @param val change the values of FIFO_COMPR_INIT in
* reg EMB_FUNC_INIT_B
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_compression_algo_init_get(stmdev_ctx_t *ctx,
@@ -4306,11 +5173,15 @@ int32_t lsm6dso32_compression_algo_init_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_INIT_B,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.fifo_compr_init;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -4324,6 +5195,7 @@ int32_t lsm6dso32_compression_algo_init_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of uncoptr_rate in
* reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_compression_algo_set(stmdev_ctx_t *ctx,
@@ -4334,29 +5206,39 @@ int32_t lsm6dso32_compression_algo_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
emb_func_en_b.fifo_compr_en = ((uint8_t)val & 0x04U) >> 2;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
fifo_ctrl2.fifo_compr_rt_en = ((uint8_t)val & 0x04U) >> 2;
fifo_ctrl2.uncoptr_rate = (uint8_t)val & 0x03U;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
+
return ret;
}
@@ -4366,6 +5248,7 @@ int32_t lsm6dso32_compression_algo_set(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val Get the values of uncoptr_rate in
* reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_compression_algo_get(stmdev_ctx_t *ctx,
@@ -4374,28 +5257,35 @@ int32_t lsm6dso32_compression_algo_get(stmdev_ctx_t *ctx,
lsm6dso32_fifo_ctrl2_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1);
- switch ((reg.fifo_compr_rt_en<<2) | reg.uncoptr_rate) {
+ switch ((reg.fifo_compr_rt_en << 2) | reg.uncoptr_rate)
+ {
case LSM6DSO32_CMP_DISABLE:
*val = LSM6DSO32_CMP_DISABLE;
break;
+
case LSM6DSO32_CMP_ALWAYS:
*val = LSM6DSO32_CMP_ALWAYS;
break;
+
case LSM6DSO32_CMP_8_TO_1:
*val = LSM6DSO32_CMP_8_TO_1;
break;
+
case LSM6DSO32_CMP_16_TO_1:
*val = LSM6DSO32_CMP_16_TO_1;
break;
+
case LSM6DSO32_CMP_32_TO_1:
*val = LSM6DSO32_CMP_32_TO_1;
break;
+
default:
*val = LSM6DSO32_CMP_DISABLE;
break;
}
+
return ret;
}
@@ -4404,6 +5294,7 @@ int32_t lsm6dso32_compression_algo_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of odrchg_en in reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
@@ -4412,11 +5303,14 @@ int32_t lsm6dso32_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
lsm6dso32_fifo_ctrl2_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.odrchg_en = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4425,6 +5319,7 @@ int32_t lsm6dso32_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of odrchg_en in reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
@@ -4433,7 +5328,7 @@ int32_t lsm6dso32_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
lsm6dso32_fifo_ctrl2_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1);
*val = reg.odrchg_en;
return ret;
@@ -4445,6 +5340,7 @@ int32_t lsm6dso32_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of fifo_compr_rt_en in
* reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_compression_algo_real_time_set(stmdev_ctx_t *ctx,
@@ -4453,11 +5349,14 @@ int32_t lsm6dso32_compression_algo_real_time_set(stmdev_ctx_t *ctx,
lsm6dso32_fifo_ctrl2_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.fifo_compr_rt_en = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4466,6 +5365,7 @@ int32_t lsm6dso32_compression_algo_real_time_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of fifo_compr_rt_en in reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_compression_algo_real_time_get(stmdev_ctx_t *ctx,
@@ -4474,7 +5374,7 @@ int32_t lsm6dso32_compression_algo_real_time_get(stmdev_ctx_t *ctx,
lsm6dso32_fifo_ctrl2_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1);
*val = reg.fifo_compr_rt_en;
return ret;
@@ -4486,6 +5386,7 @@ int32_t lsm6dso32_compression_algo_real_time_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of stop_on_wtm in reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -4493,11 +5394,14 @@ int32_t lsm6dso32_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso32_fifo_ctrl2_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.stop_on_wtm = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4507,14 +5411,16 @@ int32_t lsm6dso32_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of stop_on_wtm in reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso32_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso32_fifo_ctrl2_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1);
*val = reg.stop_on_wtm;
return ret;
@@ -4526,6 +5432,7 @@ int32_t lsm6dso32_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of bdr_xl in reg FIFO_CTRL3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fifo_xl_batch_set(stmdev_ctx_t *ctx,
@@ -4534,11 +5441,14 @@ int32_t lsm6dso32_fifo_xl_batch_set(stmdev_ctx_t *ctx,
lsm6dso32_fifo_ctrl3_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL3, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL3, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.bdr_xl = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL3, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL3, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4548,6 +5458,7 @@ int32_t lsm6dso32_fifo_xl_batch_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of bdr_xl in reg FIFO_CTRL3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fifo_xl_batch_get(stmdev_ctx_t *ctx,
@@ -4556,44 +5467,58 @@ int32_t lsm6dso32_fifo_xl_batch_get(stmdev_ctx_t *ctx,
lsm6dso32_fifo_ctrl3_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL3, (uint8_t*)®, 1);
- switch (reg.bdr_xl) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL3, (uint8_t *)®, 1);
+
+ switch (reg.bdr_xl)
+ {
case LSM6DSO32_XL_NOT_BATCHED:
*val = LSM6DSO32_XL_NOT_BATCHED;
break;
+
case LSM6DSO32_XL_BATCHED_AT_12Hz5:
*val = LSM6DSO32_XL_BATCHED_AT_12Hz5;
break;
+
case LSM6DSO32_XL_BATCHED_AT_26Hz:
*val = LSM6DSO32_XL_BATCHED_AT_26Hz;
break;
+
case LSM6DSO32_XL_BATCHED_AT_52Hz:
*val = LSM6DSO32_XL_BATCHED_AT_52Hz;
break;
+
case LSM6DSO32_XL_BATCHED_AT_104Hz:
*val = LSM6DSO32_XL_BATCHED_AT_104Hz;
break;
+
case LSM6DSO32_XL_BATCHED_AT_208Hz:
*val = LSM6DSO32_XL_BATCHED_AT_208Hz;
break;
+
case LSM6DSO32_XL_BATCHED_AT_417Hz:
*val = LSM6DSO32_XL_BATCHED_AT_417Hz;
break;
+
case LSM6DSO32_XL_BATCHED_AT_833Hz:
*val = LSM6DSO32_XL_BATCHED_AT_833Hz;
break;
+
case LSM6DSO32_XL_BATCHED_AT_1667Hz:
*val = LSM6DSO32_XL_BATCHED_AT_1667Hz;
break;
+
case LSM6DSO32_XL_BATCHED_AT_3333Hz:
*val = LSM6DSO32_XL_BATCHED_AT_3333Hz;
break;
+
case LSM6DSO32_XL_BATCHED_AT_6667Hz:
*val = LSM6DSO32_XL_BATCHED_AT_6667Hz;
break;
+
case LSM6DSO32_XL_BATCHED_AT_6Hz5:
*val = LSM6DSO32_XL_BATCHED_AT_6Hz5;
break;
+
default:
*val = LSM6DSO32_XL_NOT_BATCHED;
break;
@@ -4608,6 +5533,7 @@ int32_t lsm6dso32_fifo_xl_batch_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of bdr_gy in reg FIFO_CTRL3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fifo_gy_batch_set(stmdev_ctx_t *ctx,
@@ -4616,11 +5542,14 @@ int32_t lsm6dso32_fifo_gy_batch_set(stmdev_ctx_t *ctx,
lsm6dso32_fifo_ctrl3_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL3, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL3, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.bdr_gy = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL3, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL3, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4630,6 +5559,7 @@ int32_t lsm6dso32_fifo_gy_batch_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of bdr_gy in reg FIFO_CTRL3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fifo_gy_batch_get(stmdev_ctx_t *ctx,
@@ -4638,48 +5568,63 @@ int32_t lsm6dso32_fifo_gy_batch_get(stmdev_ctx_t *ctx,
lsm6dso32_fifo_ctrl3_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL3, (uint8_t*)®, 1);
- switch (reg.bdr_gy) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL3, (uint8_t *)®, 1);
+
+ switch (reg.bdr_gy)
+ {
case LSM6DSO32_GY_NOT_BATCHED:
*val = LSM6DSO32_GY_NOT_BATCHED;
break;
+
case LSM6DSO32_GY_BATCHED_AT_12Hz5:
*val = LSM6DSO32_GY_BATCHED_AT_12Hz5;
break;
+
case LSM6DSO32_GY_BATCHED_AT_26Hz:
*val = LSM6DSO32_GY_BATCHED_AT_26Hz;
break;
+
case LSM6DSO32_GY_BATCHED_AT_52Hz:
*val = LSM6DSO32_GY_BATCHED_AT_52Hz;
break;
+
case LSM6DSO32_GY_BATCHED_AT_104Hz:
*val = LSM6DSO32_GY_BATCHED_AT_104Hz;
break;
+
case LSM6DSO32_GY_BATCHED_AT_208Hz:
*val = LSM6DSO32_GY_BATCHED_AT_208Hz;
break;
+
case LSM6DSO32_GY_BATCHED_AT_417Hz:
*val = LSM6DSO32_GY_BATCHED_AT_417Hz;
break;
+
case LSM6DSO32_GY_BATCHED_AT_833Hz:
*val = LSM6DSO32_GY_BATCHED_AT_833Hz;
break;
+
case LSM6DSO32_GY_BATCHED_AT_1667Hz:
*val = LSM6DSO32_GY_BATCHED_AT_1667Hz;
break;
+
case LSM6DSO32_GY_BATCHED_AT_3333Hz:
*val = LSM6DSO32_GY_BATCHED_AT_3333Hz;
break;
+
case LSM6DSO32_GY_BATCHED_AT_6667Hz:
*val = LSM6DSO32_GY_BATCHED_AT_6667Hz;
break;
+
case LSM6DSO32_GY_BATCHED_AT_6Hz5:
*val = LSM6DSO32_GY_BATCHED_AT_6Hz5;
break;
+
default:
*val = LSM6DSO32_GY_NOT_BATCHED;
break;
}
+
return ret;
}
@@ -4688,6 +5633,7 @@ int32_t lsm6dso32_fifo_gy_batch_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of fifo_mode in reg FIFO_CTRL4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fifo_mode_set(stmdev_ctx_t *ctx,
@@ -4696,11 +5642,14 @@ int32_t lsm6dso32_fifo_mode_set(stmdev_ctx_t *ctx,
lsm6dso32_fifo_ctrl4_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.fifo_mode = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4709,6 +5658,7 @@ int32_t lsm6dso32_fifo_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of fifo_mode in reg FIFO_CTRL4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fifo_mode_get(stmdev_ctx_t *ctx,
@@ -4717,31 +5667,39 @@ int32_t lsm6dso32_fifo_mode_get(stmdev_ctx_t *ctx,
lsm6dso32_fifo_ctrl4_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t *)®, 1);
- switch (reg.fifo_mode) {
+ switch (reg.fifo_mode)
+ {
case LSM6DSO32_BYPASS_MODE:
*val = LSM6DSO32_BYPASS_MODE;
break;
+
case LSM6DSO32_FIFO_MODE:
*val = LSM6DSO32_FIFO_MODE;
break;
+
case LSM6DSO32_STREAM_TO_FIFO_MODE:
*val = LSM6DSO32_STREAM_TO_FIFO_MODE;
break;
+
case LSM6DSO32_BYPASS_TO_STREAM_MODE:
*val = LSM6DSO32_BYPASS_TO_STREAM_MODE;
break;
+
case LSM6DSO32_STREAM_MODE:
*val = LSM6DSO32_STREAM_MODE;
break;
+
case LSM6DSO32_BYPASS_TO_FIFO_MODE:
*val = LSM6DSO32_BYPASS_TO_FIFO_MODE;
break;
+
default:
*val = LSM6DSO32_BYPASS_MODE;
break;
}
+
return ret;
}
@@ -4751,6 +5709,7 @@ int32_t lsm6dso32_fifo_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of odr_t_batch in reg FIFO_CTRL4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fifo_temp_batch_set(stmdev_ctx_t *ctx,
@@ -4759,11 +5718,14 @@ int32_t lsm6dso32_fifo_temp_batch_set(stmdev_ctx_t *ctx,
lsm6dso32_fifo_ctrl4_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.odr_t_batch = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4773,6 +5735,7 @@ int32_t lsm6dso32_fifo_temp_batch_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of odr_t_batch in reg FIFO_CTRL4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fifo_temp_batch_get(stmdev_ctx_t *ctx,
@@ -4781,25 +5744,31 @@ int32_t lsm6dso32_fifo_temp_batch_get(stmdev_ctx_t *ctx,
lsm6dso32_fifo_ctrl4_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t *)®, 1);
- switch (reg.odr_t_batch) {
+ switch (reg.odr_t_batch)
+ {
case LSM6DSO32_TEMP_NOT_BATCHED:
*val = LSM6DSO32_TEMP_NOT_BATCHED;
break;
+
case LSM6DSO32_TEMP_BATCHED_AT_1Hz6:
*val = LSM6DSO32_TEMP_BATCHED_AT_1Hz6;
break;
+
case LSM6DSO32_TEMP_BATCHED_AT_12Hz5:
*val = LSM6DSO32_TEMP_BATCHED_AT_12Hz5;
break;
+
case LSM6DSO32_TEMP_BATCHED_AT_52Hz:
*val = LSM6DSO32_TEMP_BATCHED_AT_52Hz;
break;
+
default:
*val = LSM6DSO32_TEMP_NOT_BATCHED;
break;
}
+
return ret;
}
@@ -4810,6 +5779,7 @@ int32_t lsm6dso32_fifo_temp_batch_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of odr_ts_batch in reg FIFO_CTRL4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
@@ -4818,11 +5788,14 @@ int32_t lsm6dso32_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
lsm6dso32_fifo_ctrl4_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.odr_ts_batch = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4833,6 +5806,7 @@ int32_t lsm6dso32_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of odr_ts_batch in reg FIFO_CTRL4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
@@ -4841,24 +5815,31 @@ int32_t lsm6dso32_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
lsm6dso32_fifo_ctrl4_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t*)®, 1);
- switch (reg.odr_ts_batch) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t *)®, 1);
+
+ switch (reg.odr_ts_batch)
+ {
case LSM6DSO32_NO_DECIMATION:
*val = LSM6DSO32_NO_DECIMATION;
break;
+
case LSM6DSO32_DEC_1:
*val = LSM6DSO32_DEC_1;
break;
+
case LSM6DSO32_DEC_8:
*val = LSM6DSO32_DEC_8;
break;
+
case LSM6DSO32_DEC_32:
*val = LSM6DSO32_DEC_32;
break;
+
default:
*val = LSM6DSO32_NO_DECIMATION;
break;
}
+
return ret;
}
@@ -4869,6 +5850,7 @@ int32_t lsm6dso32_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of trig_counter_bdr
* in reg COUNTER_BDR_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
@@ -4878,12 +5860,15 @@ int32_t lsm6dso32_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
- (uint8_t*)®, 1);
- if (ret == 0) {
+ (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.trig_counter_bdr = (uint8_t)val;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4894,6 +5879,7 @@ int32_t lsm6dso32_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val Get the values of trig_counter_bdr
* in reg COUNTER_BDR_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
@@ -4903,18 +5889,23 @@ int32_t lsm6dso32_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
- (uint8_t*)®, 1);
- switch (reg.trig_counter_bdr) {
+ (uint8_t *)®, 1);
+
+ switch (reg.trig_counter_bdr)
+ {
case LSM6DSO32_XL_BATCH_EVENT:
*val = LSM6DSO32_XL_BATCH_EVENT;
break;
+
case LSM6DSO32_GYRO_BATCH_EVENT:
*val = LSM6DSO32_GYRO_BATCH_EVENT;
break;
+
default:
*val = LSM6DSO32_XL_BATCH_EVENT;
break;
}
+
return ret;
}
@@ -4925,20 +5916,25 @@ int32_t lsm6dso32_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of rst_counter_bdr in
* reg COUNTER_BDR_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dso32_rst_batch_counter_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dso32_counter_bdr_reg1_t reg;
int32_t ret;
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
- (uint8_t*)®, 1);
- if (ret == 0) {
+ (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.rst_counter_bdr = val;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4949,15 +5945,17 @@ int32_t lsm6dso32_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val)
* @param ctx read / write interface definitions
* @param val change the values of rst_counter_bdr in
* reg COUNTER_BDR_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso32_rst_batch_counter_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso32_counter_bdr_reg1_t reg;
int32_t ret;
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
*val = reg.rst_counter_bdr;
return ret;
@@ -4969,6 +5967,7 @@ int32_t lsm6dso32_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val)
* @param ctx read / write interface definitions
* @param val change the values of cnt_bdr_th in
* reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_batch_counter_threshold_set(stmdev_ctx_t *ctx,
@@ -4979,17 +5978,22 @@ int32_t lsm6dso32_batch_counter_threshold_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if (ret == 0) {
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
counter_bdr_reg2.cnt_bdr_th = 0x00FFU & (uint8_t)val;
counter_bdr_reg1.cnt_bdr_th = (uint8_t)(0x0700U & val) >> 8;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_COUNTER_BDR_REG2,
- (uint8_t*)&counter_bdr_reg2, 1);
+ (uint8_t *)&counter_bdr_reg2, 1);
}
+
return ret;
}
@@ -4999,6 +6003,7 @@ int32_t lsm6dso32_batch_counter_threshold_set(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of cnt_bdr_th in
* reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_batch_counter_threshold_get(stmdev_ctx_t *ctx,
@@ -5009,13 +6014,14 @@ int32_t lsm6dso32_batch_counter_threshold_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG2,
- (uint8_t*)&counter_bdr_reg2, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG2,
+ (uint8_t *)&counter_bdr_reg2, 1);
*val = ((uint16_t)counter_bdr_reg1.cnt_bdr_th << 8)
- + (uint16_t)counter_bdr_reg2.cnt_bdr_th;
+ + (uint16_t)counter_bdr_reg2.cnt_bdr_th;
}
return ret;
@@ -5026,22 +6032,27 @@ int32_t lsm6dso32_batch_counter_threshold_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of diff_fifo in reg FIFO_STATUS1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
+int32_t lsm6dso32_fifo_data_level_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
lsm6dso32_fifo_status1_t fifo_status1;
lsm6dso32_fifo_status2_t fifo_status2;
int32_t ret;
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_STATUS1,
- (uint8_t*)&fifo_status1, 1);
- if (ret == 0) {
+ (uint8_t *)&fifo_status1, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
+ (uint8_t *)&fifo_status2, 1);
*val = ((uint16_t)fifo_status2.diff_fifo << 8) +
- (uint16_t)fifo_status1.diff_fifo;
+ (uint16_t)fifo_status1.diff_fifo;
}
+
return ret;
}
@@ -5050,13 +6061,16 @@ int32_t lsm6dso32_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
*
* @param ctx read / write interface definitions
* @param val registers FIFO_STATUS2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fifo_status_get(stmdev_ctx_t *ctx,
lsm6dso32_fifo_status2_t *val)
{
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_STATUS2, (uint8_t*) val, 1);
+
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_STATUS2, (uint8_t *) val, 1);
+
return ret;
}
@@ -5065,6 +6079,7 @@ int32_t lsm6dso32_fifo_status_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of fifo_full_ia in reg FIFO_STATUS2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -5072,7 +6087,7 @@ int32_t lsm6dso32_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso32_fifo_status2_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_STATUS2, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_STATUS2, (uint8_t *)®, 1);
*val = reg.fifo_full_ia;
return ret;
@@ -5084,6 +6099,7 @@ int32_t lsm6dso32_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
* @param ctx read / write interface definitions
* @param val change the values of fifo_over_run_latched in
* reg FIFO_STATUS2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -5091,7 +6107,7 @@ int32_t lsm6dso32_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso32_fifo_status2_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_STATUS2, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_STATUS2, (uint8_t *)®, 1);
*val = reg.fifo_ovr_ia;
return ret;
@@ -5102,6 +6118,7 @@ int32_t lsm6dso32_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of fifo_wtm_ia in reg FIFO_STATUS2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -5109,7 +6126,7 @@ int32_t lsm6dso32_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso32_fifo_status2_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_STATUS2, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_STATUS2, (uint8_t *)®, 1);
*val = reg.fifo_wtm_ia;
return ret;
@@ -5120,6 +6137,7 @@ int32_t lsm6dso32_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of tag_sensor in reg FIFO_DATA_OUT_TAG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
@@ -5129,66 +6147,87 @@ int32_t lsm6dso32_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_DATA_OUT_TAG,
- (uint8_t*)®, 1);
- switch (reg.tag_sensor) {
+ (uint8_t *)®, 1);
+
+ switch (reg.tag_sensor)
+ {
case LSM6DSO32_GYRO_NC_TAG:
*val = LSM6DSO32_GYRO_NC_TAG;
break;
+
case LSM6DSO32_XL_NC_TAG:
*val = LSM6DSO32_XL_NC_TAG;
break;
+
case LSM6DSO32_TEMPERATURE_TAG:
*val = LSM6DSO32_TEMPERATURE_TAG;
break;
+
case LSM6DSO32_CFG_CHANGE_TAG:
*val = LSM6DSO32_CFG_CHANGE_TAG;
break;
+
case LSM6DSO32_XL_NC_T_2_TAG:
*val = LSM6DSO32_XL_NC_T_2_TAG;
break;
+
case LSM6DSO32_XL_NC_T_1_TAG:
*val = LSM6DSO32_XL_NC_T_1_TAG;
break;
+
case LSM6DSO32_XL_2XC_TAG:
*val = LSM6DSO32_XL_2XC_TAG;
break;
+
case LSM6DSO32_XL_3XC_TAG:
*val = LSM6DSO32_XL_3XC_TAG;
break;
+
case LSM6DSO32_GYRO_NC_T_2_TAG:
*val = LSM6DSO32_GYRO_NC_T_2_TAG;
break;
+
case LSM6DSO32_GYRO_NC_T_1_TAG:
*val = LSM6DSO32_GYRO_NC_T_1_TAG;
break;
+
case LSM6DSO32_GYRO_2XC_TAG:
*val = LSM6DSO32_GYRO_2XC_TAG;
break;
+
case LSM6DSO32_GYRO_3XC_TAG:
*val = LSM6DSO32_GYRO_3XC_TAG;
break;
+
case LSM6DSO32_SENSORHUB_SLAVE0_TAG:
*val = LSM6DSO32_SENSORHUB_SLAVE0_TAG;
break;
+
case LSM6DSO32_SENSORHUB_SLAVE1_TAG:
*val = LSM6DSO32_SENSORHUB_SLAVE1_TAG;
break;
+
case LSM6DSO32_SENSORHUB_SLAVE2_TAG:
*val = LSM6DSO32_SENSORHUB_SLAVE2_TAG;
break;
+
case LSM6DSO32_SENSORHUB_SLAVE3_TAG:
*val = LSM6DSO32_SENSORHUB_SLAVE3_TAG;
break;
+
case LSM6DSO32_STEP_COUNTER_TAG:
*val = LSM6DSO32_STEP_COUNTER_TAG;
break;
+
case LSM6DSO32_SENSORHUB_NACK_TAG:
*val = LSM6DSO32_SENSORHUB_NACK_TAG;
break;
+
default:
*val = LSM6DSO32_GYRO_NC_TAG;
break;
}
+
return ret;
}
@@ -5199,6 +6238,7 @@ int32_t lsm6dso32_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of gbias_fifo_en in
* reg LSM6DSO32_EMB_FUNC_FIFO_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -5207,18 +6247,25 @@ int32_t lsm6dso32_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_FIFO_CFG,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.pedo_fifo_en = val;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_FIFO_CFG,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
+
return ret;
}
@@ -5228,6 +6275,7 @@ int32_t lsm6dso32_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val)
* @param ctx read / write interface definitions
* @param val change the values of pedo_fifo_en in
* reg LSM6DSO32_EMB_FUNC_FIFO_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -5236,14 +6284,19 @@ int32_t lsm6dso32_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_FIFO_CFG,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.pedo_fifo_en;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
+
return ret;
}
@@ -5253,6 +6306,7 @@ int32_t lsm6dso32_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
* @param ctx read / write interface definitions
* @param val change the values of batch_ext_sens_0_en in
* reg SLV0_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -5261,16 +6315,23 @@ int32_t lsm6dso32_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV0_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV0_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.batch_ext_sens_0_en = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV0_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV0_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
+
return ret;
}
@@ -5280,21 +6341,28 @@ int32_t lsm6dso32_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val)
* @param ctx read / write interface definitions
* @param val change the values of batch_ext_sens_0_en in
* reg SLV0_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso32_sh_batch_slave_0_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso32_slv0_config_t reg;
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV0_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV0_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.batch_ext_sens_0_en;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
+
return ret;
}
@@ -5304,6 +6372,7 @@ int32_t lsm6dso32_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val)
* @param ctx read / write interface definitions
* @param val change the values of batch_ext_sens_1_en in
* reg SLV1_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -5312,14 +6381,20 @@ int32_t lsm6dso32_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV1_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV1_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.batch_ext_sens_1_en = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV1_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV1_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -5332,21 +6407,28 @@ int32_t lsm6dso32_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val)
* @param ctx read / write interface definitions
* @param val change the values of batch_ext_sens_1_en in
* reg SLV1_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso32_sh_batch_slave_1_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso32_slv1_config_t reg;
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV1_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV1_CONFIG, (uint8_t *)®, 1);
*val = reg.batch_ext_sens_1_en;
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
+
return ret;
}
@@ -5356,6 +6438,7 @@ int32_t lsm6dso32_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val)
* @param ctx read / write interface definitions
* @param val change the values of batch_ext_sens_2_en in
* reg SLV2_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -5365,16 +6448,22 @@ int32_t lsm6dso32_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val)
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV2_CONFIG, (uint8_t*)®, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV2_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.batch_ext_sens_2_en = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV2_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV2_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
+
return ret;
}
@@ -5384,18 +6473,24 @@ int32_t lsm6dso32_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val)
* @param ctx read / write interface definitions
* @param val change the values of batch_ext_sens_2_en in
* reg SLV2_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso32_sh_batch_slave_2_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso32_slv2_config_t reg;
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV2_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV2_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.batch_ext_sens_2_en;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -5409,6 +6504,7 @@ int32_t lsm6dso32_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val)
* @param ctx read / write interface definitions
* @param val change the values of batch_ext_sens_3_en
* in reg SLV3_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -5417,14 +6513,20 @@ int32_t lsm6dso32_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV3_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV3_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.batch_ext_sens_3_en = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV3_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV3_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -5437,18 +6539,24 @@ int32_t lsm6dso32_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val)
* @param ctx read / write interface definitions
* @param val change the values of batch_ext_sens_3_en in
* reg SLV3_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso32_sh_batch_slave_3_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso32_slv3_config_t reg;
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV3_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV3_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.batch_ext_sens_3_en;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -5474,17 +6582,21 @@ int32_t lsm6dso32_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of den_mode in reg CTRL6_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_den_mode_set(stmdev_ctx_t *ctx, lsm6dso32_den_mode_t val)
+int32_t lsm6dso32_den_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32_den_mode_t val)
{
lsm6dso32_ctrl6_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.den_mode = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *)®, 1);
}
return ret;
@@ -5495,6 +6607,7 @@ int32_t lsm6dso32_den_mode_set(stmdev_ctx_t *ctx, lsm6dso32_den_mode_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of den_mode in reg CTRL6_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_den_mode_get(stmdev_ctx_t *ctx,
@@ -5503,28 +6616,35 @@ int32_t lsm6dso32_den_mode_get(stmdev_ctx_t *ctx,
lsm6dso32_ctrl6_c_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *)®, 1);
- switch (reg.den_mode) {
+ switch (reg.den_mode)
+ {
case LSM6DSO32_DEN_DISABLE:
*val = LSM6DSO32_DEN_DISABLE;
break;
+
case LSM6DSO32_LEVEL_FIFO:
*val = LSM6DSO32_LEVEL_FIFO;
break;
+
case LSM6DSO32_LEVEL_LETCHED:
*val = LSM6DSO32_LEVEL_LETCHED;
break;
+
case LSM6DSO32_LEVEL_TRIGGER:
*val = LSM6DSO32_LEVEL_TRIGGER;
break;
+
case LSM6DSO32_EDGE_TRIGGER:
*val = LSM6DSO32_EDGE_TRIGGER;
break;
+
default:
*val = LSM6DSO32_DEN_DISABLE;
break;
}
+
return ret;
}
@@ -5533,6 +6653,7 @@ int32_t lsm6dso32_den_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of den_lh in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_den_polarity_set(stmdev_ctx_t *ctx,
@@ -5541,10 +6662,12 @@ int32_t lsm6dso32_den_polarity_set(stmdev_ctx_t *ctx,
lsm6dso32_ctrl9_xl_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.den_lh = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
}
return ret;
@@ -5555,6 +6678,7 @@ int32_t lsm6dso32_den_polarity_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of den_lh in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_den_polarity_get(stmdev_ctx_t *ctx,
@@ -5563,19 +6687,23 @@ int32_t lsm6dso32_den_polarity_get(stmdev_ctx_t *ctx,
lsm6dso32_ctrl9_xl_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
- switch (reg.den_lh) {
+ switch (reg.den_lh)
+ {
case LSM6DSO32_DEN_ACT_LOW:
*val = LSM6DSO32_DEN_ACT_LOW;
break;
+
case LSM6DSO32_DEN_ACT_HIGH:
*val = LSM6DSO32_DEN_ACT_HIGH;
break;
+
default:
*val = LSM6DSO32_DEN_ACT_LOW;
break;
}
+
return ret;
}
@@ -5584,6 +6712,7 @@ int32_t lsm6dso32_den_polarity_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of den_xl_g in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_den_enable_set(stmdev_ctx_t *ctx,
@@ -5592,10 +6721,12 @@ int32_t lsm6dso32_den_enable_set(stmdev_ctx_t *ctx,
lsm6dso32_ctrl9_xl_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.den_xl_g = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
}
return ret;
@@ -5606,6 +6737,7 @@ int32_t lsm6dso32_den_enable_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of den_xl_g in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_den_enable_get(stmdev_ctx_t *ctx,
@@ -5614,22 +6746,27 @@ int32_t lsm6dso32_den_enable_get(stmdev_ctx_t *ctx,
lsm6dso32_ctrl9_xl_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
- switch (reg.den_xl_g) {
+ switch (reg.den_xl_g)
+ {
case LSM6DSO32_STAMP_IN_GY_DATA:
*val = LSM6DSO32_STAMP_IN_GY_DATA;
break;
+
case LSM6DSO32_STAMP_IN_XL_DATA:
*val = LSM6DSO32_STAMP_IN_XL_DATA;
break;
+
case LSM6DSO32_STAMP_IN_GY_XL_DATA:
*val = LSM6DSO32_STAMP_IN_GY_XL_DATA;
break;
+
default:
*val = LSM6DSO32_STAMP_IN_GY_DATA;
break;
}
+
return ret;
}
@@ -5638,6 +6775,7 @@ int32_t lsm6dso32_den_enable_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of den_z in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -5645,10 +6783,12 @@ int32_t lsm6dso32_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso32_ctrl9_xl_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.den_z = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
}
return ret;
@@ -5659,6 +6799,7 @@ int32_t lsm6dso32_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of den_z in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -5666,7 +6807,7 @@ int32_t lsm6dso32_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso32_ctrl9_xl_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
*val = reg.den_z;
return ret;
@@ -5677,6 +6818,7 @@ int32_t lsm6dso32_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of den_y in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -5684,10 +6826,12 @@ int32_t lsm6dso32_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso32_ctrl9_xl_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.den_y = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
}
return ret;
@@ -5698,6 +6842,7 @@ int32_t lsm6dso32_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of den_y in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -5705,7 +6850,7 @@ int32_t lsm6dso32_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso32_ctrl9_xl_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
*val = reg.den_y;
return ret;
@@ -5716,6 +6861,7 @@ int32_t lsm6dso32_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of den_x in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -5723,10 +6869,12 @@ int32_t lsm6dso32_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso32_ctrl9_xl_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.den_x = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
}
return ret;
@@ -5737,6 +6885,7 @@ int32_t lsm6dso32_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of den_x in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -5744,7 +6893,7 @@ int32_t lsm6dso32_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso32_ctrl9_xl_t reg;
int32_t ret;
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t*)®, 1);
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
*val = reg.den_x;
return ret;
@@ -5767,9 +6916,11 @@ int32_t lsm6dso32_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val turn on and configure pedometer
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_pedo_sens_set(stmdev_ctx_t *ctx, lsm6dso32_pedo_md_t val)
+int32_t lsm6dso32_pedo_sens_set(stmdev_ctx_t *ctx,
+ lsm6dso32_pedo_md_t val)
{
lsm6dso32_emb_func_en_a_t emb_func_en_a;
lsm6dso32_emb_func_en_b_t emb_func_en_b;
@@ -5777,38 +6928,52 @@ int32_t lsm6dso32_pedo_sens_set(stmdev_ctx_t *ctx, lsm6dso32_pedo_md_t val)
int32_t ret;
ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_PEDO_CMD_REG,
- (uint8_t*)&pedo_cmd_reg);
- if (ret == 0) {
+ (uint8_t *)&pedo_cmd_reg);
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
+ (uint8_t *)&emb_func_en_a, 1);
}
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
+ (uint8_t *)&emb_func_en_b, 1);
emb_func_en_a.pedo_en = (uint8_t)val & 0x01U;
- emb_func_en_b.pedo_adv_en = ((uint8_t)val & 0x02U)>>1;
- pedo_cmd_reg.fp_rejection_en = ((uint8_t)val & 0x10U)>>4;
- pedo_cmd_reg.ad_det_en = ((uint8_t)val & 0x20U)>>5;
+ emb_func_en_b.pedo_adv_en = ((uint8_t)val & 0x02U) >> 1;
+ pedo_cmd_reg.fp_rejection_en = ((uint8_t)val & 0x10U) >> 4;
+ pedo_cmd_reg.ad_det_en = ((uint8_t)val & 0x20U) >> 5;
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
+ (uint8_t *)&emb_func_en_a, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_PEDO_CMD_REG,
- (uint8_t*)&pedo_cmd_reg);
+ (uint8_t *)&pedo_cmd_reg);
}
+
return ret;
}
@@ -5817,9 +6982,11 @@ int32_t lsm6dso32_pedo_sens_set(stmdev_ctx_t *ctx, lsm6dso32_pedo_md_t val)
*
* @param ctx read / write interface definitions
* @param val turn on and configure pedometer
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_pedo_sens_get(stmdev_ctx_t *ctx, lsm6dso32_pedo_md_t *val)
+int32_t lsm6dso32_pedo_sens_get(stmdev_ctx_t *ctx,
+ lsm6dso32_pedo_md_t *val)
{
lsm6dso32_emb_func_en_a_t emb_func_en_a;
lsm6dso32_emb_func_en_b_t emb_func_en_b;
@@ -5827,42 +6994,59 @@ int32_t lsm6dso32_pedo_sens_get(stmdev_ctx_t *ctx, lsm6dso32_pedo_md_t *val)
int32_t ret;
ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_PEDO_CMD_REG,
- (uint8_t*)&pedo_cmd_reg);
- if (ret == 0) {
+ (uint8_t *)&pedo_cmd_reg);
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
+ (uint8_t *)&emb_func_en_a, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
- switch ( (pedo_cmd_reg.ad_det_en <<5) | (pedo_cmd_reg.fp_rejection_en << 4) |
- (emb_func_en_b.pedo_adv_en << 1) | emb_func_en_a.pedo_en) {
+
+ switch ((pedo_cmd_reg.ad_det_en << 5) | (pedo_cmd_reg.fp_rejection_en
+ << 4) |
+ (emb_func_en_b.pedo_adv_en << 1) | emb_func_en_a.pedo_en)
+ {
case LSM6DSO32_PEDO_DISABLE:
*val = LSM6DSO32_PEDO_DISABLE;
break;
+
case LSM6DSO32_PEDO_BASE_MODE:
*val = LSM6DSO32_PEDO_BASE_MODE;
break;
+
case LSM6DSO32_PEDO_ADV_MODE:
*val = LSM6DSO32_PEDO_ADV_MODE;
break;
+
case LSM6DSO32_FALSE_STEP_REJ:
*val = LSM6DSO32_FALSE_STEP_REJ;
break;
+
case LSM6DSO32_FALSE_STEP_REJ_ADV_MODE:
*val = LSM6DSO32_FALSE_STEP_REJ_ADV_MODE;
break;
+
default:
*val = LSM6DSO32_PEDO_DISABLE;
break;
}
+
return ret;
}
@@ -5871,19 +7055,25 @@ int32_t lsm6dso32_pedo_sens_get(stmdev_ctx_t *ctx, lsm6dso32_pedo_md_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of is_step_det in reg EMB_FUNC_STATUS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso32_pedo_step_detect_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso32_emb_func_status_t reg;
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_STATUS,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.is_step_det;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -5896,12 +7086,17 @@ int32_t lsm6dso32_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso32_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
- ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_PEDO_DEB_STEPS_CONF, buff);
+
+ ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_PEDO_DEB_STEPS_CONF,
+ buff);
+
return ret;
}
@@ -5910,12 +7105,17 @@ int32_t lsm6dso32_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso32_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
- ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_PEDO_DEB_STEPS_CONF, buff);
+
+ ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_PEDO_DEB_STEPS_CONF,
+ buff);
+
return ret;
}
@@ -5924,21 +7124,26 @@ int32_t lsm6dso32_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_pedo_steps_period_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso32_pedo_steps_period_set(stmdev_ctx_t *ctx,
+ uint16_t val)
{
+ uint8_t buff[2];
int32_t ret;
- uint8_t index;
- index = 0x00U;
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_PEDO_SC_DELTAT_L,
- &buff[index]);
- if (ret == 0) {
- index++;
+ &buff[0]);
+
+ if (ret == 0)
+ {
ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_PEDO_SC_DELTAT_H,
- &buff[index]);
+ &buff[1]);
}
+
return ret;
}
@@ -5947,21 +7152,26 @@ int32_t lsm6dso32_pedo_steps_period_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_pedo_steps_period_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso32_pedo_steps_period_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
- uint8_t index;
- index = 0x00U;
ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_PEDO_SC_DELTAT_L,
- &buff[index]);
- if (ret == 0) {
- index++;
+ &buff[0]);
+
+ if (ret == 0)
+ {
ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_PEDO_SC_DELTAT_H,
- &buff[index]);
+ &buff[1]);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
}
+
return ret;
}
@@ -5971,6 +7181,7 @@ int32_t lsm6dso32_pedo_steps_period_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param val change the values of carry_count_en in reg PEDO_CMD_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_pedo_int_mode_set(stmdev_ctx_t *ctx,
@@ -5980,12 +7191,15 @@ int32_t lsm6dso32_pedo_int_mode_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_PEDO_CMD_REG,
- (uint8_t*)®);
- if (ret == 0) {
+ (uint8_t *)®);
+
+ if (ret == 0)
+ {
reg.carry_count_en = (uint8_t)val;
ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_PEDO_CMD_REG,
- (uint8_t*)®);
+ (uint8_t *)®);
}
+
return ret;
}
@@ -5995,6 +7209,7 @@ int32_t lsm6dso32_pedo_int_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of carry_count_en in reg PEDO_CMD_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_pedo_int_mode_get(stmdev_ctx_t *ctx,
@@ -6003,18 +7218,24 @@ int32_t lsm6dso32_pedo_int_mode_get(stmdev_ctx_t *ctx,
lsm6dso32_pedo_cmd_reg_t reg;
int32_t ret;
- ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_PEDO_CMD_REG, (uint8_t*)®);
- switch (reg.carry_count_en) {
+ ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_PEDO_CMD_REG,
+ (uint8_t *)®);
+
+ switch (reg.carry_count_en)
+ {
case LSM6DSO32_EVERY_STEP:
*val = LSM6DSO32_EVERY_STEP;
break;
+
case LSM6DSO32_COUNT_OVERFLOW:
*val = LSM6DSO32_COUNT_OVERFLOW;
break;
+
default:
*val = LSM6DSO32_EVERY_STEP;
break;
}
+
return ret;
}
@@ -6036,6 +7257,7 @@ int32_t lsm6dso32_pedo_int_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of sign_motion_en in reg EMB_FUNC_EN_A
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -6044,16 +7266,25 @@ int32_t lsm6dso32_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.sign_motion_en = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
+
return ret;
}
@@ -6062,6 +7293,7 @@ int32_t lsm6dso32_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of sign_motion_en in reg EMB_FUNC_EN_A
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -6070,13 +7302,19 @@ int32_t lsm6dso32_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.sign_motion_en;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
+
return ret;
}
@@ -6085,6 +7323,7 @@ int32_t lsm6dso32_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of is_sigmot in reg EMB_FUNC_STATUS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_motion_flag_data_ready_get(stmdev_ctx_t *ctx,
@@ -6094,11 +7333,15 @@ int32_t lsm6dso32_motion_flag_data_ready_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_STATUS,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.is_sigmot;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -6124,6 +7367,7 @@ int32_t lsm6dso32_motion_flag_data_ready_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of tilt_en in reg EMB_FUNC_EN_A
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -6132,16 +7376,25 @@ int32_t lsm6dso32_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.tilt_en = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
+
return ret;
}
@@ -6150,6 +7403,7 @@ int32_t lsm6dso32_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of tilt_en in reg EMB_FUNC_EN_A
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -6158,10 +7412,15 @@ int32_t lsm6dso32_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.tilt_en;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -6174,19 +7433,25 @@ int32_t lsm6dso32_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of is_tilt in reg EMB_FUNC_STATUS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso32_tilt_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso32_emb_func_status_t reg;
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_STATUS,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.is_tilt;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -6212,20 +7477,23 @@ int32_t lsm6dso32_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_mag_sensitivity_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso32_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val)
{
+ uint8_t buff[2];
int32_t ret;
- uint8_t index;
- index = 0x00U;
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SENSITIVITY_L,
- &buff[index]);
- if (ret == 0) {
- index++;
+ &buff[0]);
+
+ if (ret == 0)
+ {
ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SENSITIVITY_H,
- &buff[index]);
+ &buff[1]);
}
return ret;
@@ -6236,20 +7504,24 @@ int32_t lsm6dso32_mag_sensitivity_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_mag_sensitivity_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso32_mag_sensitivity_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
- uint8_t index;
- index = 0x00U;
ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SENSITIVITY_L,
- &buff[index]);
- if (ret == 0) {
- index++;
+ &buff[0]);
+
+ if (ret == 0)
+ {
ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SENSITIVITY_H,
- &buff[index]);
+ &buff[1]);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
}
return ret;
@@ -6260,35 +7532,51 @@ int32_t lsm6dso32_mag_sensitivity_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_mag_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso32_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
- uint8_t index;
- index = 0x00U;
- ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_OFFX_L, &buff[index]);
- if (ret == 0) {
- index++;
- ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_OFFX_H, &buff[index]);
+ buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
+ buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
+ buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
+ buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
+ buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
+ buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
+ ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_OFFX_L,
+ &buff[0]);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_OFFX_H,
+ &buff[1]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_OFFY_L, &buff[index]);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_OFFY_L,
+ &buff[2]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_OFFY_H, &buff[index]);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_OFFY_H,
+ &buff[3]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_OFFZ_L, &buff[index]);
+ if (ret == 0)
+ {
+ ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_OFFZ_L,
+ &buff[4]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_OFFZ_H, &buff[index]);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_OFFZ_H,
+ &buff[5]);
}
return ret;
@@ -6299,37 +7587,53 @@ int32_t lsm6dso32_mag_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_mag_offset_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso32_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
- uint8_t index;
- index = 0x00U;
- ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_OFFX_L, &buff[index]);
- if (ret == 0) {
- index++;
- ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_OFFX_H, &buff[index]);
+ ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_OFFX_L,
+ &buff[0]);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_OFFX_H,
+ &buff[1]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_OFFY_L, &buff[index]);
+ if (ret == 0)
+ {
+ ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_OFFY_L,
+ &buff[2]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_OFFY_H, &buff[index]);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_OFFY_H,
+ &buff[3]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_OFFZ_L, &buff[index]);
+ if (ret == 0)
+ {
+ ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_OFFZ_L,
+ &buff[4]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_OFFZ_H, &buff[index]);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_OFFZ_H,
+ &buff[5]);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
}
+
return ret;
}
@@ -6344,63 +7648,106 @@ int32_t lsm6dso32_mag_offset_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso32_mag_soft_iron_set(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[12];
int32_t ret;
- uint8_t index;
+ uint8_t index;
+ buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
+ buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
+ buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
+ buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
+ buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
+ buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
+ buff[7] = (uint8_t)((uint16_t)val[3] / 256U);
+ buff[6] = (uint8_t)((uint16_t)val[3] - (buff[7] * 256U));
+ buff[9] = (uint8_t)((uint16_t)val[4] / 256U);
+ buff[8] = (uint8_t)((uint16_t)val[4] - (buff[9] * 256U));
+ buff[11] = (uint8_t)((uint16_t)val[5] / 256U);
+ buff[10] = (uint8_t)((uint16_t)val[5] - (buff[11] * 256U));
index = 0x00U;
- ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_XX_L, &buff[index]);
- if (ret == 0) {
+ ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_XX_L,
+ &buff[index]);
+
+ if (ret == 0)
+ {
index++;
- ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_XX_H, &buff[index]);
+ ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_XX_H,
+ &buff[index]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_XY_L, &buff[index]);
- }
- if (ret == 0) {
+ if (ret == 0)
+ {
index++;
- ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_XY_H, &buff[index]);
+ ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_XY_L,
+ &buff[index]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_XZ_L, &buff[index]);
- }
- if (ret == 0) {
+ if (ret == 0)
+ {
index++;
- ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_XZ_H, &buff[index]);
+ ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_XY_H,
+ &buff[index]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_YY_L, &buff[index]);
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_XZ_L,
+ &buff[index]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
index++;
- ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_YY_H, &buff[index]);
+ ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_XZ_H,
+ &buff[index]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
index++;
+ ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_YY_L,
+ &buff[index]);
+ }
- ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_YZ_L, &buff[index]);
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_YY_H,
+ &buff[index]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
index++;
- ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_YZ_H, &buff[index]);
+ ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_YZ_L,
+ &buff[index]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
index++;
+ ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_YZ_H,
+ &buff[index]);
+ }
- ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_ZZ_L, &buff[index]);
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_ZZ_L,
+ &buff[index]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
index++;
- ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_ZZ_H, &buff[index]);
+ ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_ZZ_H,
+ &buff[index]);
}
return ret;
@@ -6418,65 +7765,109 @@ int32_t lsm6dso32_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso32_mag_soft_iron_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[12];
int32_t ret;
- uint8_t index;
+ uint8_t index;
index = 0x00U;
- ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_XX_L, &buff[index]);
- if (ret == 0) {
+ ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_XX_L,
+ &buff[index]);
+
+ if (ret == 0)
+ {
index++;
- ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_XX_H, &buff[index]);
+ ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_XX_H,
+ &buff[index]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_XY_L, &buff[index]);
- }
- if (ret == 0) {
+ if (ret == 0)
+ {
index++;
- ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_XY_H, &buff[index]);
+ ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_XY_L,
+ &buff[index]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_XZ_L, &buff[index]);
- }
- if (ret == 0) {
+ if (ret == 0)
+ {
index++;
- ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_XZ_H, &buff[index]);
+ ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_XY_H,
+ &buff[index]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_YY_L, &buff[index]);
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_XZ_L,
+ &buff[index]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
index++;
- ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_YY_H, &buff[index]);
+ ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_XZ_H,
+ &buff[index]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
index++;
+ ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_YY_L,
+ &buff[index]);
+ }
- ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_YZ_L, &buff[index]);
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_YY_H,
+ &buff[index]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
index++;
- ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_YZ_H, &buff[index]);
+ ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_YZ_L,
+ &buff[index]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
index++;
+ ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_YZ_H,
+ &buff[index]);
+ }
- ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_ZZ_L, &buff[index]);
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_ZZ_L,
+ &buff[index]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
index++;
- ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_ZZ_H, &buff[index]);
+ ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_ZZ_H,
+ &buff[index]);
}
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+ val[3] = (int16_t)buff[7];
+ val[3] = (val[3] * 256) + (int16_t)buff[6];
+ val[4] = (int16_t)buff[9];
+ val[4] = (val[4] * 256) + (int16_t)buff[8];
+ val[5] = (int16_t)buff[11];
+ val[5] = (val[5] * 256) + (int16_t)buff[10];
+
return ret;
}
@@ -6488,6 +7879,7 @@ int32_t lsm6dso32_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param val change the values of mag_z_axis in reg MAG_CFG_A
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_mag_z_orient_set(stmdev_ctx_t *ctx,
@@ -6496,11 +7888,14 @@ int32_t lsm6dso32_mag_z_orient_set(stmdev_ctx_t *ctx,
lsm6dso32_mag_cfg_a_t reg;
int32_t ret;
- ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_CFG_A, (uint8_t*)®);
- if (ret == 0) {
+ ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_CFG_A,
+ (uint8_t *)®);
+
+ if (ret == 0)
+ {
reg.mag_z_axis = (uint8_t) val;
ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_CFG_A,
- (uint8_t*)®);
+ (uint8_t *)®);
}
return ret;
@@ -6514,6 +7909,7 @@ int32_t lsm6dso32_mag_z_orient_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of mag_z_axis in reg MAG_CFG_A
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_mag_z_orient_get(stmdev_ctx_t *ctx,
@@ -6521,30 +7917,41 @@ int32_t lsm6dso32_mag_z_orient_get(stmdev_ctx_t *ctx,
{
lsm6dso32_mag_cfg_a_t reg;
int32_t ret;
- ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_CFG_A, (uint8_t*)®);
- switch (reg.mag_z_axis) {
+
+ ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_CFG_A,
+ (uint8_t *)®);
+
+ switch (reg.mag_z_axis)
+ {
case LSM6DSO32_Z_EQ_Y:
*val = LSM6DSO32_Z_EQ_Y;
break;
+
case LSM6DSO32_Z_EQ_MIN_Y:
*val = LSM6DSO32_Z_EQ_MIN_Y;
break;
+
case LSM6DSO32_Z_EQ_X:
*val = LSM6DSO32_Z_EQ_X;
break;
+
case LSM6DSO32_Z_EQ_MIN_X:
*val = LSM6DSO32_Z_EQ_MIN_X;
break;
+
case LSM6DSO32_Z_EQ_MIN_Z:
*val = LSM6DSO32_Z_EQ_MIN_Z;
break;
+
case LSM6DSO32_Z_EQ_Z:
*val = LSM6DSO32_Z_EQ_Z;
break;
+
default:
*val = LSM6DSO32_Z_EQ_Y;
break;
}
+
return ret;
}
@@ -6556,6 +7963,7 @@ int32_t lsm6dso32_mag_z_orient_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of mag_y_axis in reg MAG_CFG_A
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_mag_y_orient_set(stmdev_ctx_t *ctx,
@@ -6564,11 +7972,16 @@ int32_t lsm6dso32_mag_y_orient_set(stmdev_ctx_t *ctx,
lsm6dso32_mag_cfg_a_t reg;
int32_t ret;
- ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_CFG_A, (uint8_t*)®);
- if (ret == 0) {
+ ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_CFG_A,
+ (uint8_t *)®);
+
+ if (ret == 0)
+ {
reg.mag_y_axis = (uint8_t)val;
- ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_CFG_A,(uint8_t*) ®);
+ ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_CFG_A,
+ (uint8_t *) ®);
}
+
return ret;
}
@@ -6580,6 +7993,7 @@ int32_t lsm6dso32_mag_y_orient_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of mag_y_axis in reg MAG_CFG_A
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_mag_y_orient_get(stmdev_ctx_t *ctx,
@@ -6588,30 +8002,40 @@ int32_t lsm6dso32_mag_y_orient_get(stmdev_ctx_t *ctx,
lsm6dso32_mag_cfg_a_t reg;
int32_t ret;
- ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_CFG_A, (uint8_t*)®);
- switch (reg.mag_y_axis) {
+ ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_CFG_A,
+ (uint8_t *)®);
+
+ switch (reg.mag_y_axis)
+ {
case LSM6DSO32_Y_EQ_Y:
*val = LSM6DSO32_Y_EQ_Y;
break;
+
case LSM6DSO32_Y_EQ_MIN_Y:
*val = LSM6DSO32_Y_EQ_MIN_Y;
break;
+
case LSM6DSO32_Y_EQ_X:
*val = LSM6DSO32_Y_EQ_X;
break;
+
case LSM6DSO32_Y_EQ_MIN_X:
*val = LSM6DSO32_Y_EQ_MIN_X;
break;
+
case LSM6DSO32_Y_EQ_MIN_Z:
*val = LSM6DSO32_Y_EQ_MIN_Z;
break;
+
case LSM6DSO32_Y_EQ_Z:
*val = LSM6DSO32_Y_EQ_Z;
break;
+
default:
*val = LSM6DSO32_Y_EQ_Y;
break;
}
+
return ret;
}
@@ -6623,6 +8047,7 @@ int32_t lsm6dso32_mag_y_orient_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of mag_x_axis in reg MAG_CFG_B
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_mag_x_orient_set(stmdev_ctx_t *ctx,
@@ -6631,11 +8056,16 @@ int32_t lsm6dso32_mag_x_orient_set(stmdev_ctx_t *ctx,
lsm6dso32_mag_cfg_b_t reg;
int32_t ret;
- ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_CFG_B, (uint8_t*)®);
- if (ret == 0) {
+ ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_CFG_B,
+ (uint8_t *)®);
+
+ if (ret == 0)
+ {
reg.mag_x_axis = (uint8_t)val;
- ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_CFG_B, (uint8_t*)®);
+ ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_CFG_B,
+ (uint8_t *)®);
}
+
return ret;
}
@@ -6647,6 +8077,7 @@ int32_t lsm6dso32_mag_x_orient_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of mag_x_axis in reg MAG_CFG_B
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_mag_x_orient_get(stmdev_ctx_t *ctx,
@@ -6655,30 +8086,40 @@ int32_t lsm6dso32_mag_x_orient_get(stmdev_ctx_t *ctx,
lsm6dso32_mag_cfg_b_t reg;
int32_t ret;
- ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_CFG_B, (uint8_t*)®);
- switch (reg.mag_x_axis) {
+ ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_CFG_B,
+ (uint8_t *)®);
+
+ switch (reg.mag_x_axis)
+ {
case LSM6DSO32_X_EQ_Y:
*val = LSM6DSO32_X_EQ_Y;
break;
+
case LSM6DSO32_X_EQ_MIN_Y:
*val = LSM6DSO32_X_EQ_MIN_Y;
break;
+
case LSM6DSO32_X_EQ_X:
*val = LSM6DSO32_X_EQ_X;
break;
+
case LSM6DSO32_X_EQ_MIN_X:
*val = LSM6DSO32_X_EQ_MIN_X;
break;
+
case LSM6DSO32_X_EQ_MIN_Z:
*val = LSM6DSO32_X_EQ_MIN_Z;
break;
+
case LSM6DSO32_X_EQ_Z:
*val = LSM6DSO32_X_EQ_Z;
break;
+
default:
*val = LSM6DSO32_X_EQ_Y;
break;
}
+
return ret;
}
@@ -6701,6 +8142,7 @@ int32_t lsm6dso32_mag_x_orient_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of is_fsm_lc in reg EMB_FUNC_STATUS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
@@ -6710,14 +8152,19 @@ int32_t lsm6dso32_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_STATUS,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.is_fsm_lc;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
+
return ret;
}
@@ -6726,24 +8173,34 @@ int32_t lsm6dso32_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of fsm_en in reg EMB_FUNC_EN_B
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val)
{
int32_t ret;
- lsm6dso32_emb_func_en_b_t reg;
+ lsm6dso32_emb_func_en_b_t reg;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.fsm_en = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
+
return ret;
}
@@ -6752,22 +8209,31 @@ int32_t lsm6dso32_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param uint8_t *: return the values of fsm_en in reg EMB_FUNC_EN_B
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val)
{
int32_t ret;
- lsm6dso32_emb_func_en_b_t reg;
+ lsm6dso32_emb_func_en_b_t reg;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.fsm_en;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -6779,28 +8245,38 @@ int32_t lsm6dso32_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fsm_enable_set(stmdev_ctx_t *ctx,
lsm6dso32_emb_fsm_enable_t *val)
{
int32_t ret;
- lsm6dso32_emb_func_en_b_t reg;
+ lsm6dso32_emb_func_en_b_t reg;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FSM_ENABLE_A,
- (uint8_t*)&val->fsm_enable_a, 1);
+ (uint8_t *)&val->fsm_enable_a, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FSM_ENABLE_B,
- (uint8_t*)&val->fsm_enable_b, 1);
+ (uint8_t *)&val->fsm_enable_b, 1);
}
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
- if ( (val->fsm_enable_a.fsm1_en |
+
+ if (ret == 0)
+ {
+ if ((val->fsm_enable_a.fsm1_en |
val->fsm_enable_a.fsm2_en |
val->fsm_enable_a.fsm3_en |
val->fsm_enable_a.fsm4_en |
@@ -6815,19 +8291,23 @@ int32_t lsm6dso32_fsm_enable_set(stmdev_ctx_t *ctx,
val->fsm_enable_b.fsm13_en |
val->fsm_enable_b.fsm14_en |
val->fsm_enable_b.fsm15_en |
- val->fsm_enable_b.fsm16_en )
+ val->fsm_enable_b.fsm16_en)
!= PROPERTY_DISABLE)
{
reg.fsm_en = PROPERTY_ENABLE;
}
+
else
{
reg.fsm_en = PROPERTY_DISABLE;
}
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -6839,6 +8319,7 @@ int32_t lsm6dso32_fsm_enable_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fsm_enable_get(stmdev_ctx_t *ctx,
@@ -6847,12 +8328,18 @@ int32_t lsm6dso32_fsm_enable_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_ENABLE_A, (uint8_t*) val, 2);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_ENABLE_A, (uint8_t *) val,
+ 2);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
+
return ret;
}
@@ -6862,17 +8349,25 @@ int32_t lsm6dso32_fsm_enable_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_long_cnt_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso32_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val)
{
+ uint8_t buff[2];
int32_t ret;
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FSM_LONG_COUNTER_L, buff, 2);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -6885,18 +8380,26 @@ int32_t lsm6dso32_long_cnt_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_long_cnt_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso32_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_LONG_COUNTER_L, buff, 2);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
}
return ret;
@@ -6908,6 +8411,7 @@ int32_t lsm6dso32_long_cnt_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @param ctx read / write interface definitions
* @param val change the values of fsm_lc_clr in
* reg FSM_LONG_COUNTER_CLEAR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_long_clr_set(stmdev_ctx_t *ctx,
@@ -6917,18 +8421,25 @@ int32_t lsm6dso32_long_clr_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_LONG_COUNTER_CLEAR,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg. fsm_lc_clr = (uint8_t)val;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FSM_LONG_COUNTER_CLEAR,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
+
return ret;
}
@@ -6938,6 +8449,7 @@ int32_t lsm6dso32_long_clr_set(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val Get the values of fsm_lc_clr in
* reg FSM_LONG_COUNTER_CLEAR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_long_clr_get(stmdev_ctx_t *ctx,
@@ -6947,28 +8459,37 @@ int32_t lsm6dso32_long_clr_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_LONG_COUNTER_CLEAR,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
- switch (reg.fsm_lc_clr) {
+
+ if (ret == 0)
+ {
+ switch (reg.fsm_lc_clr)
+ {
case LSM6DSO32_LC_NORMAL:
*val = LSM6DSO32_LC_NORMAL;
break;
+
case LSM6DSO32_LC_CLEAR:
*val = LSM6DSO32_LC_CLEAR;
break;
+
case LSM6DSO32_LC_CLEAR_DONE:
*val = LSM6DSO32_LC_CLEAR_DONE;
break;
+
default:
*val = LSM6DSO32_LC_NORMAL;
break;
}
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -6980,17 +8501,24 @@ int32_t lsm6dso32_long_clr_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val struct of registers from FSM_OUTS1 to FSM_OUTS16
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_fsm_out_get(stmdev_ctx_t *ctx, lsm6dso32_fsm_out_t *val)
+int32_t lsm6dso32_fsm_out_get(stmdev_ctx_t *ctx,
+ lsm6dso32_fsm_out_t *val)
{
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_OUTS1, (uint8_t*) &val, 16);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_OUTS1, (uint8_t *) &val,
+ 16);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -7002,6 +8530,7 @@ int32_t lsm6dso32_fsm_out_get(stmdev_ctx_t *ctx, lsm6dso32_fsm_out_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fsm_data_rate_set(stmdev_ctx_t *ctx,
@@ -7011,20 +8540,27 @@ int32_t lsm6dso32_fsm_data_rate_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_ODR_CFG_B,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.not_used_01 = 3; /* set default values */
reg.not_used_02 = 1; /* set default values */
reg.fsm_odr = (uint8_t)val;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_ODR_CFG_B,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
+
return ret;
}
@@ -7033,6 +8569,7 @@ int32_t lsm6dso32_fsm_data_rate_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fsm_data_rate_get(stmdev_ctx_t *ctx,
@@ -7042,28 +8579,38 @@ int32_t lsm6dso32_fsm_data_rate_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_ODR_CFG_B,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
- switch (reg.fsm_odr) {
+
+ if (ret == 0)
+ {
+ switch (reg.fsm_odr)
+ {
case LSM6DSO32_ODR_FSM_12Hz5:
*val = LSM6DSO32_ODR_FSM_12Hz5;
break;
+
case LSM6DSO32_ODR_FSM_26Hz:
*val = LSM6DSO32_ODR_FSM_26Hz;
break;
+
case LSM6DSO32_ODR_FSM_52Hz:
*val = LSM6DSO32_ODR_FSM_52Hz;
break;
+
case LSM6DSO32_ODR_FSM_104Hz:
*val = LSM6DSO32_ODR_FSM_104Hz;
break;
+
default:
*val = LSM6DSO32_ODR_FSM_12Hz5;
break;
}
+
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -7075,6 +8622,7 @@ int32_t lsm6dso32_fsm_data_rate_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of fsm_init in reg FSM_INIT
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -7083,16 +8631,22 @@ int32_t lsm6dso32_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_INIT_B,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.fsm_init = val;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_INIT_B,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -7104,6 +8658,7 @@ int32_t lsm6dso32_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of fsm_init in reg FSM_INIT
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -7112,14 +8667,19 @@ int32_t lsm6dso32_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_INIT_B,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.fsm_init;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
+
return ret;
}
@@ -7131,20 +8691,24 @@ int32_t lsm6dso32_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso32_long_cnt_int_value_set(stmdev_ctx_t *ctx,
+ uint16_t val)
{
+ uint8_t buff[2];
int32_t ret;
- uint8_t index;
- index = 0x00U;
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_FSM_LC_TIMEOUT_L,
- &buff[index]);
- if (ret == 0) {
- index++;
+ &buff[0]);
+
+ if (ret == 0)
+ {
ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_FSM_LC_TIMEOUT_H,
- &buff[index]);
+ &buff[1]);
}
return ret;
@@ -7158,20 +8722,24 @@ int32_t lsm6dso32_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso32_long_cnt_int_value_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
- uint8_t index;
- index = 0x00U;
ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_FSM_LC_TIMEOUT_L,
- &buff[index]);
- if (ret == 0) {
- index++;
+ &buff[0]);
+
+ if (ret == 0)
+ {
ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_FSM_LC_TIMEOUT_H,
- &buff[index]);
+ &buff[1]);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
}
return ret;
@@ -7182,6 +8750,7 @@ int32_t lsm6dso32_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fsm_number_of_programs_set(stmdev_ctx_t *ctx,
@@ -7199,6 +8768,7 @@ int32_t lsm6dso32_fsm_number_of_programs_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_fsm_number_of_programs_get(stmdev_ctx_t *ctx,
@@ -7217,21 +8787,27 @@ int32_t lsm6dso32_fsm_number_of_programs_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_fsm_start_address_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso32_fsm_start_address_set(stmdev_ctx_t *ctx,
+ uint16_t val)
{
+ uint8_t buff[2];
int32_t ret;
- uint8_t index;
- index = 0x00U;
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_FSM_START_ADD_L,
- &buff[index]);
- if (ret == 0) {
- index++;
+ &buff[0]);
+
+ if (ret == 0)
+ {
+ ;
ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_FSM_START_ADD_H,
- &buff[index]);
+ &buff[1]);
}
+
return ret;
}
@@ -7241,19 +8817,26 @@ int32_t lsm6dso32_fsm_start_address_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso32_fsm_start_address_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso32_fsm_start_address_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
- uint8_t index;
- index = 0x00U;
- ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_FSM_START_ADD_L, buff);
- if (ret == 0) {
- index++;
- ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_FSM_START_ADD_H, buff);
+ ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_FSM_START_ADD_L,
+ &buff[0]);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_FSM_START_ADD_H,
+ &buff[1]);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
}
+
return ret;
}
@@ -7275,19 +8858,24 @@ int32_t lsm6dso32_fsm_start_address_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param val union of registers from SENSOR_HUB_1 to SENSOR_HUB_18
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_sh_read_data_raw_get(stmdev_ctx_t *ctx,
- lsm6dso32_emb_sh_read_t *val)
+ lsm6dso32_emb_sh_read_t *val)
{
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SENSOR_HUB_1,
- (uint8_t*) val, 18U);
+ (uint8_t *) val, 18U);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -7299,6 +8887,7 @@ int32_t lsm6dso32_sh_read_data_raw_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of aux_sens_on in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_sh_slave_connected_set(stmdev_ctx_t *ctx,
@@ -7308,16 +8897,25 @@ int32_t lsm6dso32_sh_slave_connected_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.aux_sens_on = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
+
return ret;
}
@@ -7326,6 +8924,7 @@ int32_t lsm6dso32_sh_slave_connected_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of aux_sens_on in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_sh_slave_connected_get(stmdev_ctx_t *ctx,
@@ -7335,27 +8934,38 @@ int32_t lsm6dso32_sh_slave_connected_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
- switch (reg.aux_sens_on) {
+
+ if (ret == 0)
+ {
+ switch (reg.aux_sens_on)
+ {
case LSM6DSO32_SLV_0:
*val = LSM6DSO32_SLV_0;
break;
+
case LSM6DSO32_SLV_0_1:
*val = LSM6DSO32_SLV_0_1;
break;
+
case LSM6DSO32_SLV_0_1_2:
*val = LSM6DSO32_SLV_0_1_2;
break;
+
case LSM6DSO32_SLV_0_1_2_3:
*val = LSM6DSO32_SLV_0_1_2_3;
break;
+
default:
*val = LSM6DSO32_SLV_0;
break;
}
+
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -7367,6 +8977,7 @@ int32_t lsm6dso32_sh_slave_connected_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of master_on in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -7375,16 +8986,25 @@ int32_t lsm6dso32_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.master_on = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
+
return ret;
}
@@ -7393,6 +9013,7 @@ int32_t lsm6dso32_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of master_on in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -7401,10 +9022,15 @@ int32_t lsm6dso32_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.master_on;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -7417,6 +9043,7 @@ int32_t lsm6dso32_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of shub_pu_en in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_sh_pin_mode_set(stmdev_ctx_t *ctx,
@@ -7426,14 +9053,22 @@ int32_t lsm6dso32_sh_pin_mode_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.shub_pu_en = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -7445,6 +9080,7 @@ int32_t lsm6dso32_sh_pin_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of shub_pu_en in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_sh_pin_mode_get(stmdev_ctx_t *ctx,
@@ -7454,21 +9090,30 @@ int32_t lsm6dso32_sh_pin_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
- switch (reg.shub_pu_en) {
+
+ if (ret == 0)
+ {
+ switch (reg.shub_pu_en)
+ {
case LSM6DSO32_EXT_PULL_UP:
*val = LSM6DSO32_EXT_PULL_UP;
break;
+
case LSM6DSO32_INTERNAL_PULL_UP:
*val = LSM6DSO32_INTERNAL_PULL_UP;
break;
+
default:
*val = LSM6DSO32_EXT_PULL_UP;
break;
}
+
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -7481,6 +9126,7 @@ int32_t lsm6dso32_sh_pin_mode_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of pass_through_mode in
* reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -7489,14 +9135,22 @@ int32_t lsm6dso32_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.pass_through_mode = val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -7509,6 +9163,7 @@ int32_t lsm6dso32_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
* @param ctx read / write interface definitions
* @param val change the values of pass_through_mode in
* reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -7517,10 +9172,15 @@ int32_t lsm6dso32_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.pass_through_mode;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -7533,6 +9193,7 @@ int32_t lsm6dso32_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of start_config in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_sh_syncro_mode_set(stmdev_ctx_t *ctx,
@@ -7542,14 +9203,22 @@ int32_t lsm6dso32_sh_syncro_mode_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.start_config = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -7561,6 +9230,7 @@ int32_t lsm6dso32_sh_syncro_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of start_config in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_sh_syncro_mode_get(stmdev_ctx_t *ctx,
@@ -7570,23 +9240,33 @@ int32_t lsm6dso32_sh_syncro_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
- switch (reg.start_config) {
+
+ if (ret == 0)
+ {
+ switch (reg.start_config)
+ {
case LSM6DSO32_EXT_ON_INT2_PIN:
*val = LSM6DSO32_EXT_ON_INT2_PIN;
break;
+
case LSM6DSO32_XL_GY_DRDY:
*val = LSM6DSO32_XL_GY_DRDY;
break;
+
default:
*val = LSM6DSO32_EXT_ON_INT2_PIN;
break;
}
+
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
+
return ret;
}
@@ -7596,6 +9276,7 @@ int32_t lsm6dso32_sh_syncro_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of write_once in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_sh_write_mode_set(stmdev_ctx_t *ctx,
@@ -7605,14 +9286,22 @@ int32_t lsm6dso32_sh_write_mode_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.write_once = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -7625,6 +9314,7 @@ int32_t lsm6dso32_sh_write_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of write_once in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_sh_write_mode_get(stmdev_ctx_t *ctx,
@@ -7634,21 +9324,30 @@ int32_t lsm6dso32_sh_write_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
- switch (reg.write_once) {
+
+ if (ret == 0)
+ {
+ switch (reg.write_once)
+ {
case LSM6DSO32_EACH_SH_CYCLE:
*val = LSM6DSO32_EACH_SH_CYCLE;
break;
+
case LSM6DSO32_ONLY_FIRST_CYCLE:
*val = LSM6DSO32_ONLY_FIRST_CYCLE;
break;
+
default:
*val = LSM6DSO32_EACH_SH_CYCLE;
break;
}
+
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -7659,6 +9358,7 @@ int32_t lsm6dso32_sh_write_mode_get(stmdev_ctx_t *ctx,
* @brief Reset Master logic and output registers.[set]
*
* @param ctx read / write interface definitions
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_sh_reset_set(stmdev_ctx_t *ctx)
@@ -7667,18 +9367,29 @@ int32_t lsm6dso32_sh_reset_set(stmdev_ctx_t *ctx)
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.rst_master_regs = PROPERTY_ENABLE;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.rst_master_regs = PROPERTY_DISABLE;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -7690,6 +9401,7 @@ int32_t lsm6dso32_sh_reset_set(stmdev_ctx_t *ctx)
*
* @param ctx read / write interface definitions
* @param val change the values of rst_master_regs in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -7698,13 +9410,19 @@ int32_t lsm6dso32_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.rst_master_regs;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
+
return ret;
}
@@ -7713,6 +9431,7 @@ int32_t lsm6dso32_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of shub_odr in reg slv1_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_sh_data_rate_set(stmdev_ctx_t *ctx,
@@ -7722,14 +9441,20 @@ int32_t lsm6dso32_sh_data_rate_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV1_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV0_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.shub_odr = (uint8_t)val;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV1_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV0_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -7741,6 +9466,7 @@ int32_t lsm6dso32_sh_data_rate_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of shub_odr in reg slv1_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_sh_data_rate_get(stmdev_ctx_t *ctx,
@@ -7750,27 +9476,37 @@ int32_t lsm6dso32_sh_data_rate_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV1_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV0_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
- switch (reg.shub_odr) {
+
+ if (ret == 0)
+ {
+ switch (reg.shub_odr)
+ {
case LSM6DSO32_SH_ODR_104Hz:
*val = LSM6DSO32_SH_ODR_104Hz;
break;
+
case LSM6DSO32_SH_ODR_52Hz:
*val = LSM6DSO32_SH_ODR_52Hz;
break;
+
case LSM6DSO32_SH_ODR_26Hz:
*val = LSM6DSO32_SH_ODR_26Hz;
break;
+
case LSM6DSO32_SH_ODR_13Hz:
*val = LSM6DSO32_SH_ODR_13Hz;
break;
+
default:
*val = LSM6DSO32_SH_ODR_104Hz;
break;
}
+
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -7785,6 +9521,7 @@ int32_t lsm6dso32_sh_data_rate_get(stmdev_ctx_t *ctx,
* - uint8_t slv1_add; 8 bit i2c device address
* - uint8_t slv1_subadd; 8 bit register device address
* - uint8_t slv1_data; 8 bit data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_sh_cfg_write(stmdev_ctx_t *ctx,
@@ -7794,22 +9531,31 @@ int32_t lsm6dso32_sh_cfg_write(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.slave0 = val->slv0_add;
reg.rw_0 = 0;
- ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV0_ADD, (uint8_t*)®, 1);
+ ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV0_ADD, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV0_SUBADD,
- &(val->slv0_subadd), 1);
+ &(val->slv0_subadd), 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_DATAWRITE_SLV0,
- &(val->slv0_data), 1);
+ &(val->slv0_data), 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
+
return ret;
}
@@ -7821,6 +9567,7 @@ int32_t lsm6dso32_sh_cfg_write(stmdev_ctx_t *ctx,
* - uint8_t slv1_add; 8 bit i2c device address
* - uint8_t slv1_subadd; 8 bit register device address
* - uint8_t slv1_len; num of bit to read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
@@ -7831,26 +9578,36 @@ int32_t lsm6dso32_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
slv0_add.slave0 = val->slv_add;
slv0_add.rw_0 = 1;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV0_ADD,
- (uint8_t*)&slv0_add, 1);
+ (uint8_t *)&slv0_add, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV0_SUBADD,
- &(val->slv_subadd), 1);
+ &(val->slv_subadd), 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
slv0_config.slave0_numop = val->slv_len;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -7865,6 +9622,7 @@ int32_t lsm6dso32_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
* - uint8_t slv1_add; 8 bit i2c device address
* - uint8_t slv1_subadd; 8 bit register device address
* - uint8_t slv1_len; num of bit to read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
@@ -7875,26 +9633,36 @@ int32_t lsm6dso32_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
slv1_add.slave1_add = val->slv_add;
slv1_add.r_1 = 1;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV1_ADD,
- (uint8_t*)&slv1_add, 1);
+ (uint8_t *)&slv1_add, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV1_SUBADD,
- &(val->slv_subadd), 1);
+ &(val->slv_subadd), 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV1_CONFIG,
- (uint8_t*)&slv1_config, 1);
+ (uint8_t *)&slv1_config, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
slv1_config.slave1_numop = val->slv_len;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV1_CONFIG,
- (uint8_t*)&slv1_config, 1);
+ (uint8_t *)&slv1_config, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
@@ -7909,6 +9677,7 @@ int32_t lsm6dso32_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
* - uint8_t slv2_add; 8 bit i2c device address
* - uint8_t slv2_subadd; 8 bit register device address
* - uint8_t slv2_len; num of bit to read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
@@ -7919,28 +9688,39 @@ int32_t lsm6dso32_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
slv2_add.slave2_add = val->slv_add;
slv2_add.r_2 = 1;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV2_ADD,
- (uint8_t*)&slv2_add, 1);
+ (uint8_t *)&slv2_add, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV2_SUBADD,
- &(val->slv_subadd), 1);
+ &(val->slv_subadd), 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV2_CONFIG,
- (uint8_t*)&slv2_config, 1);
+ (uint8_t *)&slv2_config, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
slv2_config.slave2_numop = val->slv_len;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV2_CONFIG,
- (uint8_t*)&slv2_config, 1);
+ (uint8_t *)&slv2_config, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
+
return ret;
}
@@ -7952,6 +9732,7 @@ int32_t lsm6dso32_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
* - uint8_t slv3_add; 8 bit i2c device address
* - uint8_t slv3_subadd; 8 bit register device address
* - uint8_t slv3_len; num of bit to read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
@@ -7962,28 +9743,39 @@ int32_t lsm6dso32_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
slv3_add.slave3_add = val->slv_add;
slv3_add.r_3 = 1;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV3_ADD,
- (uint8_t*)&slv3_add, 1);
+ (uint8_t *)&slv3_add, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV3_SUBADD,
- &(val->slv_subadd), 1);
+ &(val->slv_subadd), 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV3_CONFIG,
- (uint8_t*)&slv3_config, 1);
+ (uint8_t *)&slv3_config, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
slv3_config.slave3_numop = val->slv_len;
ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV3_CONFIG,
- (uint8_t*)&slv3_config, 1);
+ (uint8_t *)&slv3_config, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
+
return ret;
}
@@ -7992,6 +9784,7 @@ int32_t lsm6dso32_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val union of registers from STATUS_MASTER to
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso32_sh_status_get(stmdev_ctx_t *ctx,
@@ -8000,10 +9793,15 @@ int32_t lsm6dso32_sh_status_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso32_read_reg(ctx, LSM6DSO32_STATUS_MASTER, (uint8_t*) val, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_STATUS_MASTER,
+ (uint8_t *) val, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
}
diff --git a/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.h b/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.h
index 921d667081d1de250f0e0c2049b0fbb8c9ba045c..58bd04595f9c250be20634bbef2ab00d70a940f3 100644
--- a/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.h
+++ b/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file lsm6dso32_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lsm6dso_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lsm6dso32_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lsm6dso32_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LSM6DSO32_REGS_H
#define LSM6DSO32_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup LSM6DSO32
@@ -35,6 +36,37 @@
*
*/
+/** @defgroup Endianness definitions
+ * @{
+ *
+ */
+
+#ifndef DRV_BYTE_ORDER
+#ifndef __BYTE_ORDER__
+
+#define DRV_LITTLE_ENDIAN 1234
+#define DRV_BIG_ENDIAN 4321
+
+/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
+ * by uncommenting the define which fits your platform endianness
+ */
+//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
+#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
+
+#else /* defined __BYTE_ORDER__ */
+
+#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
+#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
+#define DRV_BYTE_ORDER __BYTE_ORDER__
+
+#endif /* __BYTE_ORDER__*/
+#endif /* DRV_BYTE_ORDER */
+
+/**
+ * @}
+ *
+ */
+
/** @defgroup STMicroelectronics sensors common types
* @{
*
@@ -43,7 +75,9 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -52,6 +86,16 @@ typedef struct{
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} bitwise_t;
#define PROPERTY_DISABLE (0U)
@@ -65,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -97,7 +142,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -132,25 +178,43 @@ typedef struct {
*/
#define LSM6DSO32_FUNC_CFG_ACCESS 0x01U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t not_used_00 : 6;
+uint8_t reg_access :
+ 2; /* shub_reg_access + func_cfg_access */
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+uint8_t reg_access :
+ 2; /* shub_reg_access + func_cfg_access */
uint8_t not_used_00 : 6;
- uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_func_cfg_access_t;
#define LSM6DSO32_PIN_CTRL 0x02U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 6;
uint8_t sdo_pu_en : 1;
uint8_t not_used_02 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 1;
+ uint8_t sdo_pu_en : 1;
+ uint8_t not_used_01 : 6;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_pin_ctrl_t;
#define LSM6DSO32_FIFO_CTRL1 0x07U
-typedef struct {
+typedef struct
+{
uint8_t wtm : 8;
} lsm6dso32_fifo_ctrl1_t;
#define LSM6DSO32_FIFO_CTRL2 0x08U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wtm : 1;
uint8_t uncoptr_rate : 2;
uint8_t not_used_01 : 1;
@@ -158,38 +222,73 @@ typedef struct {
uint8_t not_used_02 : 1;
uint8_t fifo_compr_rt_en : 1;
uint8_t stop_on_wtm : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t stop_on_wtm : 1;
+ uint8_t fifo_compr_rt_en : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t odrchg_en : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t uncoptr_rate : 2;
+ uint8_t wtm : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_fifo_ctrl2_t;
#define LSM6DSO32_FIFO_CTRL3 0x09U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bdr_xl : 4;
uint8_t bdr_gy : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bdr_gy : 4;
+ uint8_t bdr_xl : 4;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_fifo_ctrl3_t;
#define LSM6DSO32_FIFO_CTRL4 0x0AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fifo_mode : 3;
uint8_t not_used_01 : 1;
uint8_t odr_t_batch : 2;
uint8_t odr_ts_batch : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr_ts_batch : 2;
+ uint8_t odr_t_batch : 2;
+ uint8_t not_used_01 : 1;
+ uint8_t fifo_mode : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_fifo_ctrl4_t;
#define LSM6DSO32_COUNTER_BDR_REG1 0x0BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t cnt_bdr_th : 3;
uint8_t not_used_01 : 2;
uint8_t trig_counter_bdr : 1;
uint8_t rst_counter_bdr : 1;
uint8_t dataready_pulsed : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t dataready_pulsed : 1;
+ uint8_t rst_counter_bdr : 1;
+ uint8_t trig_counter_bdr : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t cnt_bdr_th : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_counter_bdr_reg1_t;
#define LSM6DSO32_COUNTER_BDR_REG2 0x0CU
-typedef struct {
+typedef struct
+{
uint8_t cnt_bdr_th : 8;
} lsm6dso32_counter_bdr_reg2_t;
#define LSM6DSO32_INT1_CTRL 0x0DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_drdy_xl : 1;
uint8_t int1_drdy_g : 1;
uint8_t int1_boot : 1;
@@ -198,10 +297,22 @@ typedef struct {
uint8_t int1_fifo_full : 1;
uint8_t int1_cnt_bdr : 1;
uint8_t den_drdy_flag : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t den_drdy_flag : 1;
+ uint8_t int1_cnt_bdr : 1;
+ uint8_t int1_fifo_full : 1;
+ uint8_t int1_fifo_ovr : 1;
+ uint8_t int1_fifo_th : 1;
+ uint8_t int1_boot : 1;
+ uint8_t int1_drdy_g : 1;
+ uint8_t int1_drdy_xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_int1_ctrl_t;
#define LSM6DSO32_INT2_CTRL 0x0EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_drdy_xl : 1;
uint8_t int2_drdy_g : 1;
uint8_t int2_drdy_temp : 1;
@@ -210,26 +321,53 @@ typedef struct {
uint8_t int2_fifo_full : 1;
uint8_t int2_cnt_bdr : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t int2_cnt_bdr : 1;
+ uint8_t int2_fifo_full : 1;
+ uint8_t int2_fifo_ovr : 1;
+ uint8_t int2_fifo_th : 1;
+ uint8_t int2_drdy_temp : 1;
+ uint8_t int2_drdy_g : 1;
+ uint8_t int2_drdy_xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_int2_ctrl_t;
#define LSM6DSO32_WHO_AM_I 0x0FU
#define LSM6DSO32_CTRL1_XL 0x10U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t lpf2_xl_en : 1;
uint8_t fs_xl : 2;
uint8_t odr_xl : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr_xl : 4;
+ uint8_t fs_xl : 2;
+ uint8_t lpf2_xl_en : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_ctrl1_xl_t;
#define LSM6DSO32_CTRL2_G 0x11U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t fs_g : 3; /* fs_125 + fs_g */
uint8_t odr_g : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr_g : 4;
+ uint8_t fs_g : 3; /* fs_125 + fs_g */
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_ctrl2_g_t;
#define LSM6DSO32_CTRL3_C 0x12U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sw_reset : 1;
uint8_t not_used_01 : 1;
uint8_t if_inc : 1;
@@ -238,10 +376,22 @@ typedef struct {
uint8_t h_lactive : 1;
uint8_t bdu : 1;
uint8_t boot : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t boot : 1;
+ uint8_t bdu : 1;
+ uint8_t h_lactive : 1;
+ uint8_t pp_od : 1;
+ uint8_t sim : 1;
+ uint8_t if_inc : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t sw_reset : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_ctrl3_c_t;
#define LSM6DSO32_CTRL4_C 0x13U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t lpf1_sel_g : 1;
uint8_t i2c_disable : 1;
@@ -250,47 +400,98 @@ typedef struct {
uint8_t int2_on_int1 : 1;
uint8_t sleep_g : 1;
uint8_t not_used_03 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_03 : 1;
+ uint8_t sleep_g : 1;
+ uint8_t int2_on_int1 : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t drdy_mask : 1;
+ uint8_t i2c_disable : 1;
+ uint8_t lpf1_sel_g : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_ctrl4_c_t;
#define LSM6DSO32_CTRL5_C 0x14U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_xl : 2;
uint8_t st_g : 2;
uint8_t not_used_01 : 1;
uint8_t rounding : 2;
uint8_t xl_ulp_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t xl_ulp_en : 1;
+ uint8_t rounding : 2;
+ uint8_t not_used_01 : 1;
+ uint8_t st_g : 2;
+ uint8_t st_xl : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_ctrl5_c_t;
#define LSM6DSO32_CTRL6_C 0x15U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ftype : 3;
uint8_t usr_off_w : 1;
uint8_t xl_hm_mode : 1;
- uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */
+uint8_t den_mode :
+ 3; /* trig_en + lvl1_en + lvl2_en */
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+uint8_t den_mode :
+ 3; /* trig_en + lvl1_en + lvl2_en */
+ uint8_t xl_hm_mode : 1;
+ uint8_t usr_off_w : 1;
+ uint8_t ftype : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_ctrl6_c_t;
#define LSM6DSO32_CTRL7_G 0x16U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t usr_off_on_out : 1;
uint8_t not_used_02 : 2;
uint8_t hpm_g : 2;
uint8_t hp_en_g : 1;
uint8_t g_hm_mode : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t g_hm_mode : 1;
+ uint8_t hp_en_g : 1;
+ uint8_t hpm_g : 2;
+ uint8_t not_used_02 : 2;
+ uint8_t usr_off_on_out : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_ctrl7_g_t;
#define LSM6DSO32_CTRL8_XL 0x17U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t low_pass_on_6d : 1;
uint8_t not_used_01 : 1;
uint8_t hp_slope_xl_en : 1;
uint8_t fastsettl_mode_xl : 1;
uint8_t hp_ref_mode_xl : 1;
uint8_t hpcf_xl : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t hpcf_xl : 3;
+ uint8_t hp_ref_mode_xl : 1;
+ uint8_t fastsettl_mode_xl : 1;
+ uint8_t hp_slope_xl_en : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t low_pass_on_6d : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_ctrl8_xl_t;
#define LSM6DSO32_CTRL9_XL 0x18U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t i3c_disable : 1;
uint8_t den_lh : 1;
@@ -298,17 +499,35 @@ typedef struct {
uint8_t den_z : 1;
uint8_t den_y : 1;
uint8_t den_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t den_x : 1;
+ uint8_t den_y : 1;
+ uint8_t den_z : 1;
+ uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */
+ uint8_t den_lh : 1;
+ uint8_t i3c_disable : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_ctrl9_xl_t;
#define LSM6DSO32_CTRL10_C 0x19U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 5;
uint8_t timestamp_en : 1;
uint8_t not_used_02 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 2;
+ uint8_t timestamp_en : 1;
+ uint8_t not_used_01 : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_ctrl10_c_t;
#define LSM6DSO32_ALL_INT_SRC 0x1AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ia : 1;
uint8_t wu_ia : 1;
uint8_t single_tap : 1;
@@ -317,10 +536,22 @@ typedef struct {
uint8_t sleep_change_ia : 1;
uint8_t not_used_01 : 1;
uint8_t timestamp_endcount : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t timestamp_endcount : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t sleep_change_ia : 1;
+ uint8_t d6d_ia : 1;
+ uint8_t double_tap : 1;
+ uint8_t single_tap : 1;
+ uint8_t wu_ia : 1;
+ uint8_t ff_ia : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_all_int_src_t;
#define LSM6DSO32_WAKE_UP_SRC 0x1BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_wu : 1;
uint8_t y_wu : 1;
uint8_t x_wu : 1;
@@ -329,10 +560,22 @@ typedef struct {
uint8_t ff_ia : 1;
uint8_t sleep_change_ia : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t sleep_change_ia : 1;
+ uint8_t ff_ia : 1;
+ uint8_t sleep_state : 1;
+ uint8_t wu_ia : 1;
+ uint8_t x_wu : 1;
+ uint8_t y_wu : 1;
+ uint8_t z_wu : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_wake_up_src_t;
#define LSM6DSO32_TAP_SRC 0x1CU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_tap : 1;
uint8_t y_tap : 1;
uint8_t x_tap : 1;
@@ -341,10 +584,22 @@ typedef struct {
uint8_t single_tap : 1;
uint8_t tap_ia : 1;
uint8_t not_used_02 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 1;
+ uint8_t tap_ia : 1;
+ uint8_t single_tap : 1;
+ uint8_t double_tap : 1;
+ uint8_t tap_sign : 1;
+ uint8_t x_tap : 1;
+ uint8_t y_tap : 1;
+ uint8_t z_tap : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_tap_src_t;
#define LSM6DSO32_D6D_SRC 0x1DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
uint8_t yl : 1;
@@ -353,14 +608,32 @@ typedef struct {
uint8_t zh : 1;
uint8_t d6d_ia : 1;
uint8_t den_drdy : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t den_drdy : 1;
+ uint8_t d6d_ia : 1;
+ uint8_t zh : 1;
+ uint8_t zl : 1;
+ uint8_t yh : 1;
+ uint8_t yl : 1;
+ uint8_t xh : 1;
+ uint8_t xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_d6d_src_t;
#define LSM6DSO32_STATUS_REG 0x1EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlda : 1;
uint8_t gda : 1;
uint8_t tda : 1;
uint8_t not_used_01 : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 5;
+ uint8_t tda : 1;
+ uint8_t gda : 1;
+ uint8_t xlda : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_status_reg_t;
#define LSM6DSO32_OUT_TEMP_L 0x20U
@@ -378,17 +651,29 @@ typedef struct {
#define LSM6DSO32_OUTZ_L_A 0x2CU
#define LSM6DSO32_OUTZ_H_A 0x2DU
#define LSM6DSO32_EMB_FUNC_STATUS_MAINPAGE 0x35U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t is_step_det : 1;
uint8_t is_tilt : 1;
uint8_t is_sigmot : 1;
uint8_t not_used_02 : 1;
uint8_t is_fsm_lc : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_fsm_lc : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t is_sigmot : 1;
+ uint8_t is_tilt : 1;
+ uint8_t is_step_det : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_emb_func_status_mainpage_t;
#define LSM6DSO32_FSM_STATUS_A_MAINPAGE 0x36U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_fsm1 : 1;
uint8_t is_fsm2 : 1;
uint8_t is_fsm3 : 1;
@@ -397,10 +682,22 @@ typedef struct {
uint8_t is_fsm6 : 1;
uint8_t is_fsm7 : 1;
uint8_t is_fsm8 : 1;
- } lsm6dso32_fsm_status_a_mainpage_t;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_fsm8 : 1;
+ uint8_t is_fsm7 : 1;
+ uint8_t is_fsm6 : 1;
+ uint8_t is_fsm5 : 1;
+ uint8_t is_fsm4 : 1;
+ uint8_t is_fsm3 : 1;
+ uint8_t is_fsm2 : 1;
+ uint8_t is_fsm1 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32_fsm_status_a_mainpage_t;
#define LSM6DSO32_FSM_STATUS_B_MAINPAGE 0x37U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_fsm9 : 1;
uint8_t is_fsm10 : 1;
uint8_t is_fsm11 : 1;
@@ -409,10 +706,22 @@ typedef struct {
uint8_t is_fsm14 : 1;
uint8_t is_fsm15 : 1;
uint8_t is_fsm16 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_fsm16 : 1;
+ uint8_t is_fsm15 : 1;
+ uint8_t is_fsm14 : 1;
+ uint8_t is_fsm13 : 1;
+ uint8_t is_fsm12 : 1;
+ uint8_t is_fsm11 : 1;
+ uint8_t is_fsm10 : 1;
+ uint8_t is_fsm9 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_fsm_status_b_mainpage_t;
#define LSM6DSO32_STATUS_MASTER_MAINPAGE 0x39U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sens_hub_endop : 1;
uint8_t not_used_01 : 2;
uint8_t slave0_nack : 1;
@@ -420,15 +729,27 @@ typedef struct {
uint8_t slave2_nack : 1;
uint8_t slave3_nack : 1;
uint8_t wr_once_done : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t wr_once_done : 1;
+ uint8_t slave3_nack : 1;
+ uint8_t slave2_nack : 1;
+ uint8_t slave1_nack : 1;
+ uint8_t slave0_nack : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t sens_hub_endop : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_status_master_mainpage_t;
#define LSM6DSO32_FIFO_STATUS1 0x3AU
-typedef struct {
+typedef struct
+{
uint8_t diff_fifo : 8;
} lsm6dso32_fifo_status1_t;
#define LSM6DSO32_FIFO_STATUS2 0x3B
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t diff_fifo : 2;
uint8_t not_used_01 : 1;
uint8_t over_run_latched : 1;
@@ -436,6 +757,15 @@ typedef struct {
uint8_t fifo_full_ia : 1;
uint8_t fifo_ovr_ia : 1;
uint8_t fifo_wtm_ia : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fifo_wtm_ia : 1;
+ uint8_t fifo_ovr_ia : 1;
+ uint8_t fifo_full_ia : 1;
+ uint8_t counter_bdr_ia : 1;
+ uint8_t over_run_latched : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t diff_fifo : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_fifo_status2_t;
#define LSM6DSO32_TIMESTAMP0 0x40U
@@ -444,7 +774,9 @@ typedef struct {
#define LSM6DSO32_TIMESTAMP3 0x43U
#define LSM6DSO32_TAP_CFG0 0x56U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lir : 1;
uint8_t tap_z_en : 1;
uint8_t tap_y_en : 1;
@@ -453,58 +785,118 @@ typedef struct {
uint8_t sleep_status_on_int : 1;
uint8_t int_clr_on_read : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t int_clr_on_read : 1;
+ uint8_t sleep_status_on_int : 1;
+ uint8_t slope_fds : 1;
+ uint8_t tap_x_en : 1;
+ uint8_t tap_y_en : 1;
+ uint8_t tap_z_en : 1;
+ uint8_t lir : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_tap_cfg0_t;
#define LSM6DSO32_TAP_CFG1 0x57U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_ths_x : 5;
uint8_t tap_priority : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t tap_priority : 3;
+ uint8_t tap_ths_x : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_tap_cfg1_t;
#define LSM6DSO32_TAP_CFG2 0x58U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_ths_y : 5;
uint8_t inact_en : 2;
uint8_t interrupts_enable : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t interrupts_enable : 1;
+ uint8_t inact_en : 2;
+ uint8_t tap_ths_y : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_tap_cfg2_t;
#define LSM6DSO32_TAP_THS_6D 0x59U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_ths_z : 5;
uint8_t sixd_ths : 2;
uint8_t d4d_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t d4d_en : 1;
+ uint8_t sixd_ths : 2;
+ uint8_t tap_ths_z : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_tap_ths_6d_t;
#define LSM6DSO32_INT_DUR2 0x5AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shock : 2;
uint8_t quiet : 2;
uint8_t dur : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t dur : 4;
+ uint8_t quiet : 2;
+ uint8_t shock : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_int_dur2_t;
#define LSM6DSO32_WAKE_UP_THS 0x5BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wk_ths : 6;
uint8_t usr_off_on_wu : 1;
uint8_t single_double_tap : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t single_double_tap : 1;
+ uint8_t usr_off_on_wu : 1;
+ uint8_t wk_ths : 6;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_wake_up_ths_t;
#define LSM6DSO32_WAKE_UP_DUR 0x5CU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sleep_dur : 4;
uint8_t wake_ths_w : 1;
uint8_t wake_dur : 2;
uint8_t ff_dur : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t ff_dur : 1;
+ uint8_t wake_dur : 2;
+ uint8_t wake_ths_w : 1;
+ uint8_t sleep_dur : 4;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_wake_up_dur_t;
#define LSM6DSO32_FREE_FALL 0x5DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ths : 3;
uint8_t ff_dur : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t ff_dur : 5;
+ uint8_t ff_ths : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_free_fall_t;
#define LSM6DSO32_MD1_CFG 0x5EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_shub : 1;
uint8_t int1_emb_func : 1;
uint8_t int1_6d : 1;
@@ -513,10 +905,22 @@ typedef struct {
uint8_t int1_wu : 1;
uint8_t int1_single_tap : 1;
uint8_t int1_sleep_change : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_sleep_change : 1;
+ uint8_t int1_single_tap : 1;
+ uint8_t int1_wu : 1;
+ uint8_t int1_ff : 1;
+ uint8_t int1_double_tap : 1;
+ uint8_t int1_6d : 1;
+ uint8_t int1_emb_func : 1;
+ uint8_t int1_shub : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_md1_cfg_t;
#define LSM6DSO32_MD2_CFG 0x5FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_timestamp : 1;
uint8_t int2_emb_func : 1;
uint8_t int2_6d : 1;
@@ -525,18 +929,37 @@ typedef struct {
uint8_t int2_wu : 1;
uint8_t int2_single_tap : 1;
uint8_t int2_sleep_change : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_sleep_change : 1;
+ uint8_t int2_single_tap : 1;
+ uint8_t int2_wu : 1;
+ uint8_t int2_ff : 1;
+ uint8_t int2_double_tap : 1;
+ uint8_t int2_6d : 1;
+ uint8_t int2_emb_func : 1;
+ uint8_t int2_timestamp : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_md2_cfg_t;
#define LSM6DSO32_I3C_BUS_AVB 0x62U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t pd_dis_int1 : 1;
uint8_t not_used_01 : 2;
uint8_t i3c_bus_avb_sel : 2;
uint8_t not_used_02 : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 3;
+ uint8_t i3c_bus_avb_sel : 2;
+ uint8_t not_used_01 : 2;
+ uint8_t pd_dis_int1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_i3c_bus_avb_t;
#define LSM6DSO32_INTERNAL_FREQ_FINE 0x63U
-typedef struct {
+typedef struct
+{
uint8_t freq_fine : 8;
} lsm6dso32_internal_freq_fine_t;
@@ -544,10 +967,17 @@ typedef struct {
#define LSM6DSO32_Y_OFS_USR 0x74U
#define LSM6DSO32_Z_OFS_USR 0x75U
#define LSM6DSO32_FIFO_DATA_OUT_TAG 0x78U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tag_parity : 1;
uint8_t tag_cnt : 2;
uint8_t tag_sensor : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t tag_sensor : 5;
+ uint8_t tag_cnt : 2;
+ uint8_t tag_parity : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_fifo_data_out_tag_t;
#define LSM6DSO32_FIFO_DATA_OUT_X_L 0x79U
@@ -557,51 +987,89 @@ typedef struct {
#define LSM6DSO32_FIFO_DATA_OUT_Z_L 0x7DU
#define LSM6DSO32_FIFO_DATA_OUT_Z_H 0x7EU
#define LSM6DSO32_PAGE_SEL 0x02U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 4;
uint8_t page_sel : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t page_sel : 4;
+ uint8_t not_used_01 : 4;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_page_sel_t;
#define LSM6DSO32_EMB_FUNC_EN_A 0x04U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t pedo_en : 1;
uint8_t tilt_en : 1;
uint8_t sign_motion_en : 1;
uint8_t not_used_02 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 2;
+ uint8_t sign_motion_en : 1;
+ uint8_t tilt_en : 1;
+ uint8_t pedo_en : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_emb_func_en_a_t;
#define LSM6DSO32_EMB_FUNC_EN_B 0x05U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fsm_en : 1;
uint8_t not_used_01 : 2;
uint8_t fifo_compr_en : 1;
uint8_t pedo_adv_en : 1;
uint8_t not_used_02 : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 3;
+ uint8_t pedo_adv_en : 1;
+ uint8_t fifo_compr_en : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t fsm_en : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_emb_func_en_b_t;
#define LSM6DSO32_PAGE_ADDRESS 0x08U
-typedef struct {
+typedef struct
+{
uint8_t page_addr : 8;
} lsm6dso32_page_address_t;
#define LSM6DSO32_PAGE_VALUE 0x09U
-typedef struct {
+typedef struct
+{
uint8_t page_value : 8;
} lsm6dso32_page_value_t;
#define LSM6DSO32_EMB_FUNC_INT1 0x0AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t int1_step_detector : 1;
uint8_t int1_tilt : 1;
uint8_t int1_sig_mot : 1;
uint8_t not_used_02 : 1;
uint8_t int1_fsm_lc : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_fsm_lc : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t int1_sig_mot : 1;
+ uint8_t int1_tilt : 1;
+ uint8_t int1_step_detector : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_emb_func_int1_t;
#define LSM6DSO32_FSM_INT1_A 0x0BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_fsm1 : 1;
uint8_t int1_fsm2 : 1;
uint8_t int1_fsm3 : 1;
@@ -610,10 +1078,22 @@ typedef struct {
uint8_t int1_fsm6 : 1;
uint8_t int1_fsm7 : 1;
uint8_t int1_fsm8 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_fsm8 : 1;
+ uint8_t int1_fsm7 : 1;
+ uint8_t int1_fsm6 : 1;
+ uint8_t int1_fsm5 : 1;
+ uint8_t int1_fsm4 : 1;
+ uint8_t int1_fsm3 : 1;
+ uint8_t int1_fsm2 : 1;
+ uint8_t int1_fsm1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_fsm_int1_a_t;
#define LSM6DSO32_FSM_INT1_B 0x0CU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_fsm9 : 1;
uint8_t int1_fsm10 : 1;
uint8_t int1_fsm11 : 1;
@@ -622,20 +1102,42 @@ typedef struct {
uint8_t int1_fsm14 : 1;
uint8_t int1_fsm15 : 1;
uint8_t int1_fsm16 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_fsm16 : 1;
+ uint8_t int1_fsm15 : 1;
+ uint8_t int1_fsm14 : 1;
+ uint8_t int1_fsm13 : 1;
+ uint8_t int1_fsm12 : 1;
+ uint8_t int1_fsm11 : 1;
+ uint8_t int1_fsm10 : 1;
+ uint8_t int1_fsm9 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_fsm_int1_b_t;
#define LSM6DSO32_EMB_FUNC_INT2 0x0EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t int2_step_detector : 1;
uint8_t int2_tilt : 1;
uint8_t int2_sig_mot : 1;
uint8_t not_used_02 : 1;
uint8_t int2_fsm_lc : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_fsm_lc : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t int2_sig_mot : 1;
+ uint8_t int2_tilt : 1;
+ uint8_t int2_step_detector : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_emb_func_int2_t;
#define LSM6DSO32_FSM_INT2_A 0x0FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_fsm1 : 1;
uint8_t int2_fsm2 : 1;
uint8_t int2_fsm3 : 1;
@@ -644,10 +1146,22 @@ typedef struct {
uint8_t int2_fsm6 : 1;
uint8_t int2_fsm7 : 1;
uint8_t int2_fsm8 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_fsm8 : 1;
+ uint8_t int2_fsm7 : 1;
+ uint8_t int2_fsm6 : 1;
+ uint8_t int2_fsm5 : 1;
+ uint8_t int2_fsm4 : 1;
+ uint8_t int2_fsm3 : 1;
+ uint8_t int2_fsm2 : 1;
+ uint8_t int2_fsm1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_fsm_int2_a_t;
#define LSM6DSO32_FSM_INT2_B 0x10U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_fsm9 : 1;
uint8_t int2_fsm10 : 1;
uint8_t int2_fsm11 : 1;
@@ -656,20 +1170,42 @@ typedef struct {
uint8_t int2_fsm14 : 1;
uint8_t int2_fsm15 : 1;
uint8_t int2_fsm16 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_fsm16 : 1;
+ uint8_t int2_fsm15 : 1;
+ uint8_t int2_fsm14 : 1;
+ uint8_t int2_fsm13 : 1;
+ uint8_t int2_fsm12 : 1;
+ uint8_t int2_fsm11 : 1;
+ uint8_t int2_fsm10 : 1;
+ uint8_t int2_fsm9 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_fsm_int2_b_t;
#define LSM6DSO32_EMB_FUNC_STATUS 0x12U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t is_step_det : 1;
uint8_t is_tilt : 1;
uint8_t is_sigmot : 1;
uint8_t not_used_02 : 1;
uint8_t is_fsm_lc : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_fsm_lc : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t is_sigmot : 1;
+ uint8_t is_tilt : 1;
+ uint8_t is_step_det : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_emb_func_status_t;
#define LSM6DSO32_FSM_STATUS_A 0x13U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_fsm1 : 1;
uint8_t is_fsm2 : 1;
uint8_t is_fsm3 : 1;
@@ -678,10 +1214,22 @@ typedef struct {
uint8_t is_fsm6 : 1;
uint8_t is_fsm7 : 1;
uint8_t is_fsm8 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_fsm8 : 1;
+ uint8_t is_fsm7 : 1;
+ uint8_t is_fsm6 : 1;
+ uint8_t is_fsm5 : 1;
+ uint8_t is_fsm4 : 1;
+ uint8_t is_fsm3 : 1;
+ uint8_t is_fsm2 : 1;
+ uint8_t is_fsm1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_fsm_status_a_t;
#define LSM6DSO32_FSM_STATUS_B 0x14U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_fsm9 : 1;
uint8_t is_fsm10 : 1;
uint8_t is_fsm11 : 1;
@@ -690,24 +1238,50 @@ typedef struct {
uint8_t is_fsm14 : 1;
uint8_t is_fsm15 : 1;
uint8_t is_fsm16 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_fsm16 : 1;
+ uint8_t is_fsm15 : 1;
+ uint8_t is_fsm14 : 1;
+ uint8_t is_fsm13 : 1;
+ uint8_t is_fsm12 : 1;
+ uint8_t is_fsm11 : 1;
+ uint8_t is_fsm10 : 1;
+ uint8_t is_fsm9 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_fsm_status_b_t;
#define LSM6DSO32_PAGE_RW 0x17U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 5;
uint8_t page_rw : 2; /* page_write + page_read */
uint8_t emb_func_lir : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t emb_func_lir : 1;
+ uint8_t page_rw : 2; /* page_write + page_read */
+ uint8_t not_used_01 : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_page_rw_t;
#define LSM6DSO32_EMB_FUNC_FIFO_CFG 0x44U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_00 : 6;
uint8_t pedo_fifo_en : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t pedo_fifo_en : 1;
+ uint8_t not_used_00 : 6;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_emb_func_fifo_cfg_t;
#define LSM6DSO32_FSM_ENABLE_A 0x46U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fsm1_en : 1;
uint8_t fsm2_en : 1;
uint8_t fsm3_en : 1;
@@ -716,10 +1290,22 @@ typedef struct {
uint8_t fsm6_en : 1;
uint8_t fsm7_en : 1;
uint8_t fsm8_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fsm8_en : 1;
+ uint8_t fsm7_en : 1;
+ uint8_t fsm6_en : 1;
+ uint8_t fsm5_en : 1;
+ uint8_t fsm4_en : 1;
+ uint8_t fsm3_en : 1;
+ uint8_t fsm2_en : 1;
+ uint8_t fsm1_en : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_fsm_enable_a_t;
#define LSM6DSO32_FSM_ENABLE_B 0x47U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fsm9_en : 1;
uint8_t fsm10_en : 1;
uint8_t fsm11_en : 1;
@@ -728,18 +1314,38 @@ typedef struct {
uint8_t fsm14_en : 1;
uint8_t fsm15_en : 1;
uint8_t fsm16_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fsm16_en : 1;
+ uint8_t fsm15_en : 1;
+ uint8_t fsm14_en : 1;
+ uint8_t fsm13_en : 1;
+ uint8_t fsm12_en : 1;
+ uint8_t fsm11_en : 1;
+ uint8_t fsm10_en : 1;
+ uint8_t fsm9_en : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_fsm_enable_b_t;
#define LSM6DSO32_FSM_LONG_COUNTER_L 0x48U
#define LSM6DSO32_FSM_LONG_COUNTER_H 0x49U
#define LSM6DSO32_FSM_LONG_COUNTER_CLEAR 0x4AU
-typedef struct {
- uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+uint8_t fsm_lc_clr :
+ 2; /* fsm_lc_cleared + fsm_lc_clear */
uint8_t not_used_01 : 6;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 6;
+uint8_t fsm_lc_clr :
+ 2; /* fsm_lc_cleared + fsm_lc_clear */
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_fsm_long_counter_clear_t;
#define LSM6DSO32_FSM_OUTS1 0x4CU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -748,10 +1354,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_fsm_outs1_t;
#define LSM6DSO32_FSM_OUTS2 0x4DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -760,10 +1378,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_fsm_outs2_t;
#define LSM6DSO32_FSM_OUTS3 0x4EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -772,10 +1402,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_fsm_outs3_t;
#define LSM6DSO32_FSM_OUTS4 0x4FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -784,10 +1426,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_fsm_outs4_t;
#define LSM6DSO32_FSM_OUTS5 0x50U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -796,10 +1450,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_fsm_outs5_t;
#define LSM6DSO32_FSM_OUTS6 0x51U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -808,10 +1474,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_fsm_outs6_t;
#define LSM6DSO32_FSM_OUTS7 0x52U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -820,10 +1498,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_fsm_outs7_t;
#define LSM6DSO32_FSM_OUTS8 0x53U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -832,10 +1522,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_fsm_outs8_t;
#define LSM6DSO32_FSM_OUTS9 0x54U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -844,10 +1546,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_fsm_outs9_t;
#define LSM6DSO32_FSM_OUTS10 0x55U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -856,10 +1570,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_fsm_outs10_t;
#define LSM6DSO32_FSM_OUTS11 0x56U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -868,10 +1594,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_fsm_outs11_t;
#define LSM6DSO32_FSM_OUTS12 0x57U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -880,10 +1618,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_fsm_outs12_t;
#define LSM6DSO32_FSM_OUTS13 0x58U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -892,10 +1642,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_fsm_outs13_t;
#define LSM6DSO32_FSM_OUTS14 0x59U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -904,10 +1666,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_fsm_outs14_t;
#define LSM6DSO32_FSM_OUTS15 0x5AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -916,10 +1690,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_fsm_outs15_t;
#define LSM6DSO32_FSM_OUTS16 0x5BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -928,19 +1714,38 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_fsm_outs16_t;
#define LSM6DSO32_EMB_FUNC_ODR_CFG_B 0x5FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t fsm_odr : 2;
uint8_t not_used_02 : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 3;
+ uint8_t fsm_odr : 2;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_emb_func_odr_cfg_b_t;
#define LSM6DSO32_STEP_COUNTER_L 0x62U
#define LSM6DSO32_STEP_COUNTER_H 0x63U
#define LSM6DSO32_EMB_FUNC_SRC 0x64U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t stepcounter_bit_set : 1;
uint8_t step_overflow : 1;
@@ -948,23 +1753,49 @@ typedef struct {
uint8_t step_detected : 1;
uint8_t not_used_02 : 1;
uint8_t pedo_rst_step : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t pedo_rst_step : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t step_detected : 1;
+ uint8_t step_count_delta_ia : 1;
+ uint8_t step_overflow : 1;
+ uint8_t stepcounter_bit_set : 1;
+ uint8_t not_used_01 : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_emb_func_src_t;
#define LSM6DSO32_EMB_FUNC_INIT_A 0x66U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t step_det_init : 1;
uint8_t tilt_init : 1;
uint8_t sig_mot_init : 1;
uint8_t not_used_02 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 2;
+ uint8_t sig_mot_init : 1;
+ uint8_t tilt_init : 1;
+ uint8_t step_det_init : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_emb_func_init_a_t;
#define LSM6DSO32_EMB_FUNC_INIT_B 0x67U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fsm_init : 1;
uint8_t not_used_01 : 2;
uint8_t fifo_compr_init : 1;
uint8_t not_used_02 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 4;
+ uint8_t fifo_compr_init : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t fsm_init : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_emb_func_init_b_t;
#define LSM6DSO32_MAG_SENSITIVITY_L 0xBAU
@@ -988,17 +1819,31 @@ typedef struct {
#define LSM6DSO32_MAG_SI_ZZ_L 0xD0U
#define LSM6DSO32_MAG_SI_ZZ_H 0xD1U
#define LSM6DSO32_MAG_CFG_A 0xD4U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t mag_z_axis : 3;
uint8_t not_used_01 : 1;
uint8_t mag_y_axis : 3;
uint8_t not_used_02 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 1;
+ uint8_t mag_y_axis : 3;
+ uint8_t not_used_01 : 1;
+ uint8_t mag_z_axis : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_mag_cfg_a_t;
#define LSM6DSO32_MAG_CFG_B 0xD5U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t mag_x_axis : 3;
uint8_t not_used_01 : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 5;
+ uint8_t mag_x_axis : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_mag_cfg_b_t;
#define LSM6DSO32_FSM_LC_TIMEOUT_L 0x17AU
@@ -1007,235 +1852,462 @@ typedef struct {
#define LSM6DSO32_FSM_START_ADD_L 0x17EU
#define LSM6DSO32_FSM_START_ADD_H 0x17FU
#define LSM6DSO32_PEDO_CMD_REG 0x183U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ad_det_en : 1;
uint8_t not_used_01 : 1;
uint8_t fp_rejection_en : 1;
uint8_t carry_count_en : 1;
uint8_t not_used_02 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 4;
+ uint8_t carry_count_en : 1;
+ uint8_t fp_rejection_en : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t ad_det_en : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_pedo_cmd_reg_t;
#define LSM6DSO32_PEDO_DEB_STEPS_CONF 0x184U
#define LSM6DSO32_PEDO_SC_DELTAT_L 0x1D0U
#define LSM6DSO32_PEDO_SC_DELTAT_H 0x1D1U
#define LSM6DSO32_SENSOR_HUB_1 0x02U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_sensor_hub_1_t;
#define LSM6DSO32_SENSOR_HUB_2 0x03U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_sensor_hub_2_t;
#define LSM6DSO32_SENSOR_HUB_3 0x04U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_sensor_hub_3_t;
#define LSM6DSO32_SENSOR_HUB_4 0x05U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_sensor_hub_4_t;
#define LSM6DSO32_SENSOR_HUB_5 0x06U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_sensor_hub_5_t;
#define LSM6DSO32_SENSOR_HUB_6 0x07U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_sensor_hub_6_t;
#define LSM6DSO32_SENSOR_HUB_7 0x08U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_sensor_hub_7_t;
#define LSM6DSO32_SENSOR_HUB_8 0x09U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_sensor_hub_8_t;
#define LSM6DSO32_SENSOR_HUB_9 0x0AU
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_sensor_hub_9_t;
#define LSM6DSO32_SENSOR_HUB_10 0x0BU
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_sensor_hub_10_t;
#define LSM6DSO32_SENSOR_HUB_11 0x0CU
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_sensor_hub_11_t;
#define LSM6DSO32_SENSOR_HUB_12 0x0DU
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_sensor_hub_12_t;
#define LSM6DSO32_SENSOR_HUB_13 0x0EU
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_sensor_hub_13_t;
#define LSM6DSO32_SENSOR_HUB_14 0x0FU
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_sensor_hub_14_t;
#define LSM6DSO32_SENSOR_HUB_15 0x10U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_sensor_hub_15_t;
#define LSM6DSO32_SENSOR_HUB_16 0x11U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_sensor_hub_16_t;
#define LSM6DSO32_SENSOR_HUB_17 0x12U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_sensor_hub_17_t;
#define LSM6DSO32_SENSOR_HUB_18 0x13U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_sensor_hub_18_t;
#define LSM6DSO32_MASTER_CONFIG 0x14U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t aux_sens_on : 2;
uint8_t master_on : 1;
uint8_t shub_pu_en : 1;
@@ -1243,88 +2315,157 @@ typedef struct {
uint8_t start_config : 1;
uint8_t write_once : 1;
uint8_t rst_master_regs : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t rst_master_regs : 1;
+ uint8_t write_once : 1;
+ uint8_t start_config : 1;
+ uint8_t pass_through_mode : 1;
+ uint8_t shub_pu_en : 1;
+ uint8_t master_on : 1;
+ uint8_t aux_sens_on : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_master_config_t;
#define LSM6DSO32_SLV0_ADD 0x15U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t rw_0 : 1;
uint8_t slave0 : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave0 : 7;
+ uint8_t rw_0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_slv0_add_t;
#define LSM6DSO32_SLV0_SUBADD 0x16U
-typedef struct {
+typedef struct
+{
uint8_t slave0_reg : 8;
} lsm6dso32_slv0_subadd_t;
#define LSM6DSO32_SLV0_CONFIG 0x17U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave0_numop : 3;
uint8_t batch_ext_sens_0_en : 1;
uint8_t not_used_01 : 2;
uint8_t shub_odr : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t shub_odr : 2;
+ uint8_t not_used_01 : 2;
+ uint8_t batch_ext_sens_0_en : 1;
+ uint8_t slave0_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_slv0_config_t;
#define LSM6DSO32_SLV1_ADD 0x18U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_1 : 1;
uint8_t slave1_add : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave1_add : 7;
+ uint8_t r_1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_slv1_add_t;
#define LSM6DSO32_SLV1_SUBADD 0x19U
-typedef struct {
+typedef struct
+{
uint8_t slave1_reg : 8;
} lsm6dso32_slv1_subadd_t;
#define LSM6DSO32_SLV1_CONFIG 0x1AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave1_numop : 3;
uint8_t batch_ext_sens_1_en : 1;
uint8_t not_used_01 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 4;
+ uint8_t batch_ext_sens_1_en : 1;
+ uint8_t slave1_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_slv1_config_t;
#define LSM6DSO32_SLV2_ADD 0x1BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_2 : 1;
uint8_t slave2_add : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave2_add : 7;
+ uint8_t r_2 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_slv2_add_t;
#define LSM6DSO32_SLV2_SUBADD 0x1CU
-typedef struct {
+typedef struct
+{
uint8_t slave2_reg : 8;
} lsm6dso32_slv2_subadd_t;
#define LSM6DSO32_SLV2_CONFIG 0x1DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave2_numop : 3;
uint8_t batch_ext_sens_2_en : 1;
uint8_t not_used_01 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 4;
+ uint8_t batch_ext_sens_2_en : 1;
+ uint8_t slave2_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_slv2_config_t;
#define LSM6DSO32_SLV3_ADD 0x1EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_3 : 1;
uint8_t slave3_add : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave3_add : 7;
+ uint8_t r_3 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_slv3_add_t;
#define LSM6DSO32_SLV3_SUBADD 0x1FU
-typedef struct {
+typedef struct
+{
uint8_t slave3_reg : 8;
} lsm6dso32_slv3_subadd_t;
#define LSM6DSO32_SLV3_CONFIG 0x20U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave3_numop : 3;
uint8_t batch_ext_sens_3_en : 1;
uint8_t not_used_01 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 4;
+ uint8_t batch_ext_sens_3_en : 1;
+ uint8_t slave3_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_slv3_config_t;
#define LSM6DSO32_DATAWRITE_SLV0 0x21U
-typedef struct {
+typedef struct
+{
uint8_t slave0_dataw : 8;
} lsm6dso32_datawrite_src_mode_sub_slv0_t;
#define LSM6DSO32_STATUS_MASTER 0x22U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sens_hub_endop : 1;
uint8_t not_used_01 : 2;
uint8_t slave0_nack : 1;
@@ -1332,13 +2473,22 @@ typedef struct {
uint8_t slave2_nack : 1;
uint8_t slave3_nack : 1;
uint8_t wr_once_done : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t wr_once_done : 1;
+ uint8_t slave3_nack : 1;
+ uint8_t slave2_nack : 1;
+ uint8_t slave1_nack : 1;
+ uint8_t slave0_nack : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t sens_hub_endop : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso32_status_master_t;
/**
* @defgroup LSM6DSO32_Register_Union
- * @brief This union group all the registers that has a bitfield
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -1346,7 +2496,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
lsm6dso32_func_cfg_access_t func_cfg_access;
lsm6dso32_pin_ctrl_t pin_ctrl;
lsm6dso32_fifo_ctrl1_t fifo_ctrl1;
@@ -1471,27 +2622,30 @@ typedef union{
*
*/
-int32_t lsm6dso32_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lsm6dso32_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t lsm6dso32_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lsm6dso32_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-extern float_t lsm6dso32_from_fs4_to_mg(int16_t lsb);
-extern float_t lsm6dso32_from_fs8_to_mg(int16_t lsb);
-extern float_t lsm6dso32_from_fs16_to_mg(int16_t lsb);
-extern float_t lsm6dso32_from_fs32_to_mg(int16_t lsb);
+float_t lsm6dso32_from_fs4_to_mg(int16_t lsb);
+float_t lsm6dso32_from_fs8_to_mg(int16_t lsb);
+float_t lsm6dso32_from_fs16_to_mg(int16_t lsb);
+float_t lsm6dso32_from_fs32_to_mg(int16_t lsb);
-extern float_t lsm6dso32_from_fs125_to_mdps(int16_t lsb);
-extern float_t lsm6dso32_from_fs250_to_mdps(int16_t lsb);
-extern float_t lsm6dso32_from_fs500_to_mdps(int16_t lsb);
-extern float_t lsm6dso32_from_fs1000_to_mdps(int16_t lsb);
-extern float_t lsm6dso32_from_fs2000_to_mdps(int16_t lsb);
+float_t lsm6dso32_from_fs125_to_mdps(int16_t lsb);
+float_t lsm6dso32_from_fs250_to_mdps(int16_t lsb);
+float_t lsm6dso32_from_fs500_to_mdps(int16_t lsb);
+float_t lsm6dso32_from_fs1000_to_mdps(int16_t lsb);
+float_t lsm6dso32_from_fs2000_to_mdps(int16_t lsb);
-extern float_t lsm6dso32_from_lsb_to_celsius(int16_t lsb);
+float_t lsm6dso32_from_lsb_to_celsius(int16_t lsb);
-extern float_t lsm6dso32_from_lsb_to_nsec(int16_t lsb);
+float_t lsm6dso32_from_lsb_to_nsec(int16_t lsb);
-typedef enum {
+typedef enum
+{
LSM6DSO32_4g = 0x00,
LSM6DSO32_8g = 0x02,
LSM6DSO32_16g = 0x03,
@@ -1502,7 +2656,8 @@ int32_t lsm6dso32_xl_full_scale_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_xl_full_scale_get(stmdev_ctx_t *ctx,
lsm6dso32_fs_xl_t *val);
-typedef enum {
+typedef enum
+{
/* Accelerometer power off */
LSM6DSO32_XL_ODR_OFF = 0x00,
/* Accelerometer low power mode */
@@ -1540,7 +2695,8 @@ int32_t lsm6dso32_xl_data_rate_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_xl_data_rate_get(stmdev_ctx_t *ctx,
lsm6dso32_odr_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_250dps = 0,
LSM6DSO32_125dps = 1,
LSM6DSO32_500dps = 2,
@@ -1552,7 +2708,8 @@ int32_t lsm6dso32_gy_full_scale_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_gy_full_scale_get(stmdev_ctx_t *ctx,
lsm6dso32_fs_g_t *val);
-typedef enum {
+typedef enum
+{
/* Gyroscope power off */
LSM6DSO32_GY_ODR_OFF = 0x00,
/* Gyroscope high performance mode */
@@ -1579,10 +2736,13 @@ int32_t lsm6dso32_gy_data_rate_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_gy_data_rate_get(stmdev_ctx_t *ctx,
lsm6dso32_odr_g_t *val);
-int32_t lsm6dso32_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dso32_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso32_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_LSb_1mg = 0,
LSM6DSO32_LSb_16mg = 1,
} lsm6dso32_usr_off_w_t;
@@ -1591,7 +2751,8 @@ int32_t lsm6dso32_xl_offset_weight_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_xl_offset_weight_get(stmdev_ctx_t *ctx,
lsm6dso32_usr_off_w_t *val);
-typedef struct {
+typedef struct
+{
lsm6dso32_all_int_src_t all_int_src;
lsm6dso32_wake_up_src_t wake_up_src;
lsm6dso32_tap_src_t tap_src;
@@ -1605,22 +2766,31 @@ int32_t lsm6dso32_all_sources_get(stmdev_ctx_t *ctx,
lsm6dso32_all_sources_t *val);
int32_t lsm6dso32_status_reg_get(stmdev_ctx_t *ctx,
- lsm6dso32_status_reg_t *val);
+ lsm6dso32_status_reg_t *val);
-int32_t lsm6dso32_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso32_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dso32_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso32_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dso32_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso32_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dso32_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dso32_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dso32_xl_usr_offset_x_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lsm6dso32_xl_usr_offset_x_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
-int32_t lsm6dso32_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dso32_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dso32_xl_usr_offset_y_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lsm6dso32_xl_usr_offset_y_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
-int32_t lsm6dso32_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dso32_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dso32_xl_usr_offset_z_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lsm6dso32_xl_usr_offset_z_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
int32_t lsm6dso32_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso32_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1628,9 +2798,10 @@ int32_t lsm6dso32_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dso32_timestamp_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso32_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dso32_timestamp_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dso32_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_NO_ROUND = 0,
LSM6DSO32_ROUND_XL = 1,
LSM6DSO32_ROUND_GY = 2,
@@ -1641,23 +2812,27 @@ int32_t lsm6dso32_rounding_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_rounding_mode_get(stmdev_ctx_t *ctx,
lsm6dso32_rounding_t *val);
-int32_t lsm6dso32_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dso32_temperature_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
-int32_t lsm6dso32_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dso32_angular_rate_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
int32_t lsm6dso32_acceleration_raw_get(stmdev_ctx_t *ctx,
- uint8_t *buff);
+ int16_t *val);
int32_t lsm6dso32_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dso32_number_of_steps_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dso32_number_of_steps_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
int32_t lsm6dso32_steps_reset(stmdev_ctx_t *ctx);
int32_t lsm6dso32_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso32_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_USER_BANK = 0,
LSM6DSO32_SENSOR_HUB_BANK = 1,
LSM6DSO32_EMBEDDED_FUNC_BANK = 2,
@@ -1667,7 +2842,8 @@ int32_t lsm6dso32_mem_bank_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_mem_bank_get(stmdev_ctx_t *ctx,
lsm6dso32_reg_access_t *val);
-int32_t lsm6dso32_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address,
+int32_t lsm6dso32_ln_pg_write_byte(stmdev_ctx_t *ctx,
+ uint16_t address,
uint8_t *val);
int32_t lsm6dso32_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t address,
uint8_t *val);
@@ -1676,7 +2852,8 @@ int32_t lsm6dso32_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address,
int32_t lsm6dso32_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address,
uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_DRDY_LATCHED = 0,
LSM6DSO32_DRDY_PULSED = 1,
} lsm6dso32_dataready_pulsed_t;
@@ -1696,7 +2873,8 @@ int32_t lsm6dso32_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dso32_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso32_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_XL_ST_DISABLE = 0,
LSM6DSO32_XL_ST_POSITIVE = 1,
LSM6DSO32_XL_ST_NEGATIVE = 2,
@@ -1706,7 +2884,8 @@ int32_t lsm6dso32_xl_self_test_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_xl_self_test_get(stmdev_ctx_t *ctx,
lsm6dso32_st_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_GY_ST_DISABLE = 0,
LSM6DSO32_GY_ST_POSITIVE = 1,
LSM6DSO32_GY_ST_NEGATIVE = 3,
@@ -1727,7 +2906,8 @@ int32_t lsm6dso32_filter_settling_mask_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_filter_settling_mask_get(stmdev_ctx_t *ctx,
uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_ULTRA_LIGHT = 0,
LSM6DSO32_VERY_LIGHT = 1,
LSM6DSO32_LIGHT = 2,
@@ -1745,7 +2925,8 @@ int32_t lsm6dso32_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
int32_t lsm6dso32_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso32_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_HP_PATH_DISABLE_ON_OUT = 0x00,
LSM6DSO32_SLOPE_ODR_DIV_4 = 0x10,
LSM6DSO32_HP_ODR_DIV_10 = 0x11,
@@ -1775,10 +2956,13 @@ int32_t lsm6dso32_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
lsm6dso32_hp_slope_xl_en_t *val);
-int32_t lsm6dso32_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dso32_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso32_xl_fast_settling_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32_xl_fast_settling_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_USE_SLOPE = 0,
LSM6DSO32_USE_HPF = 1,
} lsm6dso32_slope_fds_t;
@@ -1787,7 +2971,8 @@ int32_t lsm6dso32_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
lsm6dso32_slope_fds_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_HP_FILTER_NONE = 0x00,
LSM6DSO32_HP_FILTER_16mHz = 0x80,
LSM6DSO32_HP_FILTER_65mHz = 0x81,
@@ -1799,7 +2984,8 @@ int32_t lsm6dso32_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
lsm6dso32_hpm_g_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_PULL_UP_DISC = 0,
LSM6DSO32_PULL_UP_CONNECT = 1,
} lsm6dso32_sdo_pu_en_t;
@@ -1808,14 +2994,18 @@ int32_t lsm6dso32_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
lsm6dso32_sdo_pu_en_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_SPI_4_WIRE = 0,
LSM6DSO32_SPI_3_WIRE = 1,
} lsm6dso32_sim_t;
-int32_t lsm6dso32_spi_mode_set(stmdev_ctx_t *ctx, lsm6dso32_sim_t val);
-int32_t lsm6dso32_spi_mode_get(stmdev_ctx_t *ctx, lsm6dso32_sim_t *val);
+int32_t lsm6dso32_spi_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32_sim_t val);
+int32_t lsm6dso32_spi_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32_sim_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_I2C_ENABLE = 0,
LSM6DSO32_I2C_DISABLE = 1,
} lsm6dso32_i2c_disable_t;
@@ -1824,7 +3014,8 @@ int32_t lsm6dso32_i2c_interface_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_i2c_interface_get(stmdev_ctx_t *ctx,
lsm6dso32_i2c_disable_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_I3C_DISABLE = 0x80,
LSM6DSO32_I3C_ENABLE_T_50us = 0x00,
LSM6DSO32_I3C_ENABLE_T_2us = 0x01,
@@ -1836,7 +3027,8 @@ int32_t lsm6dso32_i3c_disable_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_i3c_disable_get(stmdev_ctx_t *ctx,
lsm6dso32_i3c_disable_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_PULL_DOWN_DISC = 0,
LSM6DSO32_PULL_DOWN_CONNECT = 1,
} lsm6dso32_int1_pd_en_t;
@@ -1845,19 +3037,21 @@ int32_t lsm6dso32_int1_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_int1_mode_get(stmdev_ctx_t *ctx,
lsm6dso32_int1_pd_en_t *val);
-typedef struct {
- lsm6dso32_int1_ctrl_t int1_ctrl;
- lsm6dso32_md1_cfg_t md1_cfg;
- lsm6dso32_emb_func_int1_t emb_func_int1;
- lsm6dso32_fsm_int1_a_t fsm_int1_a;
- lsm6dso32_fsm_int1_b_t fsm_int1_b;
+typedef struct
+{
+ lsm6dso32_int1_ctrl_t int1_ctrl;
+ lsm6dso32_md1_cfg_t md1_cfg;
+ lsm6dso32_emb_func_int1_t emb_func_int1;
+ lsm6dso32_fsm_int1_a_t fsm_int1_a;
+ lsm6dso32_fsm_int1_b_t fsm_int1_b;
} lsm6dso32_pin_int1_route_t;
int32_t lsm6dso32_pin_int1_route_set(stmdev_ctx_t *ctx,
lsm6dso32_pin_int1_route_t *val);
int32_t lsm6dso32_pin_int1_route_get(stmdev_ctx_t *ctx,
lsm6dso32_pin_int1_route_t *val);
-typedef struct {
+typedef struct
+{
lsm6dso32_int2_ctrl_t int2_ctrl;
lsm6dso32_md2_cfg_t md2_cfg;
lsm6dso32_emb_func_int2_t emb_func_int2;
@@ -1869,14 +3063,18 @@ int32_t lsm6dso32_pin_int2_route_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_pin_int2_route_get(stmdev_ctx_t *ctx,
lsm6dso32_pin_int2_route_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_PUSH_PULL = 0,
LSM6DSO32_OPEN_DRAIN = 1,
} lsm6dso32_pp_od_t;
-int32_t lsm6dso32_pin_mode_set(stmdev_ctx_t *ctx, lsm6dso32_pp_od_t val);
-int32_t lsm6dso32_pin_mode_get(stmdev_ctx_t *ctx, lsm6dso32_pp_od_t *val);
+int32_t lsm6dso32_pin_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32_pp_od_t val);
+int32_t lsm6dso32_pin_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32_pp_od_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_ACTIVE_HIGH = 0,
LSM6DSO32_ACTIVE_LOW = 1,
} lsm6dso32_h_lactive_t;
@@ -1888,7 +3086,8 @@ int32_t lsm6dso32_pin_polarity_get(stmdev_ctx_t *ctx,
int32_t lsm6dso32_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso32_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_ALL_INT_PULSED = 0,
LSM6DSO32_BASE_LATCHED_EMB_PULSED = 1,
LSM6DSO32_BASE_PULSED_EMB_LATCHED = 2,
@@ -1899,7 +3098,8 @@ int32_t lsm6dso32_int_notification_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_int_notification_get(stmdev_ctx_t *ctx,
lsm6dso32_lir_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_LSb_FS_DIV_64 = 0,
LSM6DSO32_LSb_FS_DIV_256 = 1,
} lsm6dso32_wake_ths_w_t;
@@ -1922,16 +3122,18 @@ int32_t lsm6dso32_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dso32_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso32_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_DRIVE_SLEEP_CHG_EVENT = 0,
LSM6DSO32_DRIVE_SLEEP_STATUS = 1,
} lsm6dso32_sleep_status_on_int_t;
int32_t lsm6dso32_act_pin_notification_set(stmdev_ctx_t *ctx,
lsm6dso32_sleep_status_on_int_t val);
int32_t lsm6dso32_act_pin_notification_get(stmdev_ctx_t *ctx,
- lsm6dso32_sleep_status_on_int_t *val);
+ lsm6dso32_sleep_status_on_int_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_XL_AND_GY_NOT_AFFECTED = 0,
LSM6DSO32_XL_12Hz5_GY_NOT_AFFECTED = 1,
LSM6DSO32_XL_12Hz5_GY_SLEEP = 2,
@@ -1945,19 +3147,27 @@ int32_t lsm6dso32_act_mode_get(stmdev_ctx_t *ctx,
int32_t lsm6dso32_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso32_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dso32_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dso32_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso32_tap_detection_on_z_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dso32_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dso32_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso32_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dso32_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dso32_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso32_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dso32_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dso32_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso32_tap_threshold_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_XYZ = 0,
LSM6DSO32_YXZ = 1,
LSM6DSO32_XZY = 2,
@@ -1971,10 +3181,12 @@ int32_t lsm6dso32_tap_axis_priority_get(stmdev_ctx_t *ctx,
lsm6dso32_tap_priority_t *val);
int32_t lsm6dso32_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dso32_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso32_tap_threshold_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dso32_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dso32_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso32_tap_threshold_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dso32_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso32_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1985,7 +3197,8 @@ int32_t lsm6dso32_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dso32_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso32_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_ONLY_SINGLE = 0,
LSM6DSO32_BOTH_SINGLE_DOUBLE = 1,
} lsm6dso32_single_double_tap_t;
@@ -1994,7 +3207,8 @@ int32_t lsm6dso32_tap_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_tap_mode_get(stmdev_ctx_t *ctx,
lsm6dso32_single_double_tap_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_DEG_68 = 0,
LSM6DSO32_DEG_47 = 1,
} lsm6dso32_sixd_ths_t;
@@ -2006,7 +3220,8 @@ int32_t lsm6dso32_6d_threshold_get(stmdev_ctx_t *ctx,
int32_t lsm6dso32_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso32_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_FF_TSH_312mg = 0,
LSM6DSO32_FF_TSH_438mg = 1,
LSM6DSO32_FF_TSH_500mg = 2,
@@ -2020,14 +3235,16 @@ int32_t lsm6dso32_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso32_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dso32_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val);
-int32_t lsm6dso32_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t lsm6dso32_fifo_watermark_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
int32_t lsm6dso32_compression_algo_init_set(stmdev_ctx_t *ctx,
uint8_t val);
int32_t lsm6dso32_compression_algo_init_get(stmdev_ctx_t *ctx,
uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_CMP_DISABLE = 0x00,
LSM6DSO32_CMP_ALWAYS = 0x04,
LSM6DSO32_CMP_8_TO_1 = 0x05,
@@ -2049,10 +3266,13 @@ int32_t lsm6dso32_compression_algo_real_time_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_compression_algo_real_time_get(stmdev_ctx_t *ctx,
uint8_t *val);
-int32_t lsm6dso32_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dso32_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso32_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_XL_NOT_BATCHED = 0,
LSM6DSO32_XL_BATCHED_AT_12Hz5 = 1,
LSM6DSO32_XL_BATCHED_AT_26Hz = 2,
@@ -2071,7 +3291,8 @@ int32_t lsm6dso32_fifo_xl_batch_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_fifo_xl_batch_get(stmdev_ctx_t *ctx,
lsm6dso32_bdr_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_GY_NOT_BATCHED = 0,
LSM6DSO32_GY_BATCHED_AT_12Hz5 = 1,
LSM6DSO32_GY_BATCHED_AT_26Hz = 2,
@@ -2090,7 +3311,8 @@ int32_t lsm6dso32_fifo_gy_batch_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_fifo_gy_batch_get(stmdev_ctx_t *ctx,
lsm6dso32_bdr_gy_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_BYPASS_MODE = 0,
LSM6DSO32_FIFO_MODE = 1,
LSM6DSO32_STREAM_TO_FIFO_MODE = 3,
@@ -2103,7 +3325,8 @@ int32_t lsm6dso32_fifo_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_fifo_mode_get(stmdev_ctx_t *ctx,
lsm6dso32_fifo_mode_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_TEMP_NOT_BATCHED = 0,
LSM6DSO32_TEMP_BATCHED_AT_1Hz6 = 1,
LSM6DSO32_TEMP_BATCHED_AT_12Hz5 = 2,
@@ -2114,7 +3337,8 @@ int32_t lsm6dso32_fifo_temp_batch_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_fifo_temp_batch_get(stmdev_ctx_t *ctx,
lsm6dso32_odr_t_batch_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_NO_DECIMATION = 0,
LSM6DSO32_DEC_1 = 1,
LSM6DSO32_DEC_8 = 2,
@@ -2125,12 +3349,14 @@ int32_t lsm6dso32_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
lsm6dso32_odr_ts_batch_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_XL_BATCH_EVENT = 0,
LSM6DSO32_GYRO_BATCH_EVENT = 1,
} lsm6dso32_trig_counter_bdr_t;
-typedef enum {
+typedef enum
+{
LSM6DSO32_GYRO_NC_TAG = 1,
LSM6DSO32_XL_NC_TAG,
LSM6DSO32_TEMPERATURE_TAG,
@@ -2156,15 +3382,18 @@ int32_t lsm6dso32_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
lsm6dso32_trig_counter_bdr_t *val);
-int32_t lsm6dso32_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dso32_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso32_rst_batch_counter_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32_rst_batch_counter_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dso32_batch_counter_threshold_set(stmdev_ctx_t *ctx,
uint16_t val);
int32_t lsm6dso32_batch_counter_threshold_get(stmdev_ctx_t *ctx,
uint16_t *val);
-int32_t lsm6dso32_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t lsm6dso32_fifo_data_level_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
int32_t lsm6dso32_fifo_status_get(stmdev_ctx_t *ctx,
lsm6dso32_fifo_status2_t *val);
@@ -2179,21 +3408,31 @@ int32_t lsm6dso32_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
lsm6dso32_fifo_tag_t *val);
int32_t lsm6dso32_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dso32_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val);
-
-int32_t lsm6dso32_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dso32_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val);
-
-int32_t lsm6dso32_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dso32_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val);
-
-int32_t lsm6dso32_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dso32_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val);
-
-int32_t lsm6dso32_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dso32_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val);
-
-typedef enum {
+int32_t lsm6dso32_fifo_pedo_batch_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6dso32_sh_batch_slave_0_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32_sh_batch_slave_0_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6dso32_sh_batch_slave_1_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32_sh_batch_slave_1_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6dso32_sh_batch_slave_2_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32_sh_batch_slave_2_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6dso32_sh_batch_slave_3_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32_sh_batch_slave_3_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+typedef enum
+{
LSM6DSO32_DEN_DISABLE = 0,
LSM6DSO32_LEVEL_FIFO = 6,
LSM6DSO32_LEVEL_LETCHED = 3,
@@ -2205,7 +3444,8 @@ int32_t lsm6dso32_den_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_den_mode_get(stmdev_ctx_t *ctx,
lsm6dso32_den_mode_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_DEN_ACT_LOW = 0,
LSM6DSO32_DEN_ACT_HIGH = 1,
} lsm6dso32_den_lh_t;
@@ -2214,7 +3454,8 @@ int32_t lsm6dso32_den_polarity_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_den_polarity_get(stmdev_ctx_t *ctx,
lsm6dso32_den_lh_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_STAMP_IN_GY_DATA = 0,
LSM6DSO32_STAMP_IN_XL_DATA = 1,
LSM6DSO32_STAMP_IN_GY_XL_DATA = 2,
@@ -2225,15 +3466,19 @@ int32_t lsm6dso32_den_enable_get(stmdev_ctx_t *ctx,
lsm6dso32_den_xl_g_t *val);
int32_t lsm6dso32_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dso32_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso32_den_mark_axis_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dso32_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dso32_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso32_den_mark_axis_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dso32_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dso32_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso32_den_mark_axis_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_PEDO_DISABLE = 0x00,
LSM6DSO32_PEDO_BASE_MODE = 0x01,
LSM6DSO32_PEDO_ADV_MODE = 0x03,
@@ -2245,17 +3490,21 @@ int32_t lsm6dso32_pedo_sens_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_pedo_sens_get(stmdev_ctx_t *ctx,
lsm6dso32_pedo_md_t *val);
-int32_t lsm6dso32_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso32_pedo_step_detect_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dso32_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
uint8_t *buff);
int32_t lsm6dso32_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
uint8_t *buff);
-int32_t lsm6dso32_pedo_steps_period_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dso32_pedo_steps_period_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dso32_pedo_steps_period_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t lsm6dso32_pedo_steps_period_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_EVERY_STEP = 0,
LSM6DSO32_COUNT_OVERFLOW = 1,
} lsm6dso32_carry_count_en_t;
@@ -2276,16 +3525,19 @@ int32_t lsm6dso32_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dso32_tilt_flag_data_ready_get(stmdev_ctx_t *ctx,
uint8_t *val);
-int32_t lsm6dso32_mag_sensitivity_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dso32_mag_sensitivity_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dso32_mag_sensitivity_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t lsm6dso32_mag_sensitivity_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
-int32_t lsm6dso32_mag_offset_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dso32_mag_offset_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dso32_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val);
+int32_t lsm6dso32_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val);
-int32_t lsm6dso32_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dso32_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dso32_mag_soft_iron_set(stmdev_ctx_t *ctx, int16_t *val);
+int32_t lsm6dso32_mag_soft_iron_get(stmdev_ctx_t *ctx, int16_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_Z_EQ_Y = 0,
LSM6DSO32_Z_EQ_MIN_Y = 1,
LSM6DSO32_Z_EQ_X = 2,
@@ -2298,7 +3550,8 @@ int32_t lsm6dso32_mag_z_orient_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_mag_z_orient_get(stmdev_ctx_t *ctx,
lsm6dso32_mag_z_axis_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_Y_EQ_Y = 0,
LSM6DSO32_Y_EQ_MIN_Y = 1,
LSM6DSO32_Y_EQ_X = 2,
@@ -2311,7 +3564,8 @@ int32_t lsm6dso32_mag_y_orient_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_mag_y_orient_get(stmdev_ctx_t *ctx,
lsm6dso32_mag_y_axis_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_X_EQ_Y = 0,
LSM6DSO32_X_EQ_MIN_Y = 1,
LSM6DSO32_X_EQ_X = 2,
@@ -2330,19 +3584,21 @@ int32_t lsm6dso32_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
int32_t lsm6dso32_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso32_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef struct {
- lsm6dso32_fsm_enable_a_t fsm_enable_a;
- lsm6dso32_fsm_enable_b_t fsm_enable_b;
+typedef struct
+{
+ lsm6dso32_fsm_enable_a_t fsm_enable_a;
+ lsm6dso32_fsm_enable_b_t fsm_enable_b;
} lsm6dso32_emb_fsm_enable_t;
int32_t lsm6dso32_fsm_enable_set(stmdev_ctx_t *ctx,
lsm6dso32_emb_fsm_enable_t *val);
int32_t lsm6dso32_fsm_enable_get(stmdev_ctx_t *ctx,
lsm6dso32_emb_fsm_enable_t *val);
-int32_t lsm6dso32_long_cnt_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dso32_long_cnt_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dso32_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val);
+int32_t lsm6dso32_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_LC_NORMAL = 0,
LSM6DSO32_LC_CLEAR = 1,
LSM6DSO32_LC_CLEAR_DONE = 2,
@@ -2352,27 +3608,30 @@ int32_t lsm6dso32_long_clr_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_long_clr_get(stmdev_ctx_t *ctx,
lsm6dso32_fsm_lc_clr_t *val);
-typedef struct {
- lsm6dso32_fsm_outs1_t fsm_outs1;
- lsm6dso32_fsm_outs2_t fsm_outs2;
- lsm6dso32_fsm_outs3_t fsm_outs3;
- lsm6dso32_fsm_outs4_t fsm_outs4;
- lsm6dso32_fsm_outs5_t fsm_outs5;
- lsm6dso32_fsm_outs6_t fsm_outs6;
- lsm6dso32_fsm_outs7_t fsm_outs7;
- lsm6dso32_fsm_outs8_t fsm_outs8;
- lsm6dso32_fsm_outs1_t fsm_outs9;
- lsm6dso32_fsm_outs2_t fsm_outs10;
- lsm6dso32_fsm_outs3_t fsm_outs11;
- lsm6dso32_fsm_outs4_t fsm_outs12;
- lsm6dso32_fsm_outs5_t fsm_outs13;
- lsm6dso32_fsm_outs6_t fsm_outs14;
- lsm6dso32_fsm_outs7_t fsm_outs15;
- lsm6dso32_fsm_outs8_t fsm_outs16;
+typedef struct
+{
+ lsm6dso32_fsm_outs1_t fsm_outs1;
+ lsm6dso32_fsm_outs2_t fsm_outs2;
+ lsm6dso32_fsm_outs3_t fsm_outs3;
+ lsm6dso32_fsm_outs4_t fsm_outs4;
+ lsm6dso32_fsm_outs5_t fsm_outs5;
+ lsm6dso32_fsm_outs6_t fsm_outs6;
+ lsm6dso32_fsm_outs7_t fsm_outs7;
+ lsm6dso32_fsm_outs8_t fsm_outs8;
+ lsm6dso32_fsm_outs1_t fsm_outs9;
+ lsm6dso32_fsm_outs2_t fsm_outs10;
+ lsm6dso32_fsm_outs3_t fsm_outs11;
+ lsm6dso32_fsm_outs4_t fsm_outs12;
+ lsm6dso32_fsm_outs5_t fsm_outs13;
+ lsm6dso32_fsm_outs6_t fsm_outs14;
+ lsm6dso32_fsm_outs7_t fsm_outs15;
+ lsm6dso32_fsm_outs8_t fsm_outs16;
} lsm6dso32_fsm_out_t;
-int32_t lsm6dso32_fsm_out_get(stmdev_ctx_t *ctx, lsm6dso32_fsm_out_t *val);
+int32_t lsm6dso32_fsm_out_get(stmdev_ctx_t *ctx,
+ lsm6dso32_fsm_out_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_ODR_FSM_12Hz5 = 0,
LSM6DSO32_ODR_FSM_26Hz = 1,
LSM6DSO32_ODR_FSM_52Hz = 2,
@@ -2386,41 +3645,47 @@ int32_t lsm6dso32_fsm_data_rate_get(stmdev_ctx_t *ctx,
int32_t lsm6dso32_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso32_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dso32_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dso32_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dso32_long_cnt_int_value_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t lsm6dso32_long_cnt_int_value_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
int32_t lsm6dso32_fsm_number_of_programs_set(stmdev_ctx_t *ctx,
uint8_t *buff);
int32_t lsm6dso32_fsm_number_of_programs_get(stmdev_ctx_t *ctx,
uint8_t *buff);
-int32_t lsm6dso32_fsm_start_address_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dso32_fsm_start_address_get(stmdev_ctx_t *ctx, uint8_t *buff);
-
-typedef struct {
- lsm6dso32_sensor_hub_1_t sh_byte_1;
- lsm6dso32_sensor_hub_2_t sh_byte_2;
- lsm6dso32_sensor_hub_3_t sh_byte_3;
- lsm6dso32_sensor_hub_4_t sh_byte_4;
- lsm6dso32_sensor_hub_5_t sh_byte_5;
- lsm6dso32_sensor_hub_6_t sh_byte_6;
- lsm6dso32_sensor_hub_7_t sh_byte_7;
- lsm6dso32_sensor_hub_8_t sh_byte_8;
- lsm6dso32_sensor_hub_9_t sh_byte_9;
- lsm6dso32_sensor_hub_10_t sh_byte_10;
- lsm6dso32_sensor_hub_11_t sh_byte_11;
- lsm6dso32_sensor_hub_12_t sh_byte_12;
- lsm6dso32_sensor_hub_13_t sh_byte_13;
- lsm6dso32_sensor_hub_14_t sh_byte_14;
- lsm6dso32_sensor_hub_15_t sh_byte_15;
- lsm6dso32_sensor_hub_16_t sh_byte_16;
- lsm6dso32_sensor_hub_17_t sh_byte_17;
- lsm6dso32_sensor_hub_18_t sh_byte_18;
+int32_t lsm6dso32_fsm_start_address_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t lsm6dso32_fsm_start_address_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
+
+typedef struct
+{
+ lsm6dso32_sensor_hub_1_t sh_byte_1;
+ lsm6dso32_sensor_hub_2_t sh_byte_2;
+ lsm6dso32_sensor_hub_3_t sh_byte_3;
+ lsm6dso32_sensor_hub_4_t sh_byte_4;
+ lsm6dso32_sensor_hub_5_t sh_byte_5;
+ lsm6dso32_sensor_hub_6_t sh_byte_6;
+ lsm6dso32_sensor_hub_7_t sh_byte_7;
+ lsm6dso32_sensor_hub_8_t sh_byte_8;
+ lsm6dso32_sensor_hub_9_t sh_byte_9;
+ lsm6dso32_sensor_hub_10_t sh_byte_10;
+ lsm6dso32_sensor_hub_11_t sh_byte_11;
+ lsm6dso32_sensor_hub_12_t sh_byte_12;
+ lsm6dso32_sensor_hub_13_t sh_byte_13;
+ lsm6dso32_sensor_hub_14_t sh_byte_14;
+ lsm6dso32_sensor_hub_15_t sh_byte_15;
+ lsm6dso32_sensor_hub_16_t sh_byte_16;
+ lsm6dso32_sensor_hub_17_t sh_byte_17;
+ lsm6dso32_sensor_hub_18_t sh_byte_18;
} lsm6dso32_emb_sh_read_t;
int32_t lsm6dso32_sh_read_data_raw_get(stmdev_ctx_t *ctx,
lsm6dso32_emb_sh_read_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_SLV_0 = 0,
LSM6DSO32_SLV_0_1 = 1,
LSM6DSO32_SLV_0_1_2 = 2,
@@ -2434,7 +3699,8 @@ int32_t lsm6dso32_sh_slave_connected_get(stmdev_ctx_t *ctx,
int32_t lsm6dso32_sh_master_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso32_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_EXT_PULL_UP = 0,
LSM6DSO32_INTERNAL_PULL_UP = 1,
} lsm6dso32_shub_pu_en_t;
@@ -2444,18 +3710,21 @@ int32_t lsm6dso32_sh_pin_mode_get(stmdev_ctx_t *ctx,
lsm6dso32_shub_pu_en_t *val);
int32_t lsm6dso32_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dso32_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso32_sh_pass_through_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
- LSM6DSO32_EXT_ON_INT2_PIN = 0,
- LSM6DSO32_XL_GY_DRDY = 1,
+typedef enum
+{
+ LSM6DSO32_EXT_ON_INT2_PIN = 1,
+ LSM6DSO32_XL_GY_DRDY = 0,
} lsm6dso32_start_config_t;
int32_t lsm6dso32_sh_syncro_mode_set(stmdev_ctx_t *ctx,
lsm6dso32_start_config_t val);
int32_t lsm6dso32_sh_syncro_mode_get(stmdev_ctx_t *ctx,
lsm6dso32_start_config_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_EACH_SH_CYCLE = 0,
LSM6DSO32_ONLY_FIRST_CYCLE = 1,
} lsm6dso32_write_once_t;
@@ -2467,7 +3736,8 @@ int32_t lsm6dso32_sh_write_mode_get(stmdev_ctx_t *ctx,
int32_t lsm6dso32_sh_reset_set(stmdev_ctx_t *ctx);
int32_t lsm6dso32_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO32_SH_ODR_104Hz = 0,
LSM6DSO32_SH_ODR_52Hz = 1,
LSM6DSO32_SH_ODR_26Hz = 2,
@@ -2478,7 +3748,8 @@ int32_t lsm6dso32_sh_data_rate_set(stmdev_ctx_t *ctx,
int32_t lsm6dso32_sh_data_rate_get(stmdev_ctx_t *ctx,
lsm6dso32_shub_odr_t *val);
-typedef struct{
+typedef struct
+{
uint8_t slv0_add;
uint8_t slv0_subadd;
uint8_t slv0_data;
@@ -2486,7 +3757,8 @@ typedef struct{
int32_t lsm6dso32_sh_cfg_write(stmdev_ctx_t *ctx,
lsm6dso32_sh_cfg_write_t *val);
-typedef struct{
+typedef struct
+{
uint8_t slv_add;
uint8_t slv_subadd;
uint8_t slv_len;
diff --git a/sensor/stmemsc/lsm6dso32x_STdC/driver/lsm6dso32x_reg.c b/sensor/stmemsc/lsm6dso32x_STdC/driver/lsm6dso32x_reg.c
new file mode 100644
index 0000000000000000000000000000000000000000..e9cce78fc51da1c4a0d68988dd7b242161df3511
--- /dev/null
+++ b/sensor/stmemsc/lsm6dso32x_STdC/driver/lsm6dso32x_reg.c
@@ -0,0 +1,12338 @@
+/**
+ ******************************************************************************
+ * @file lsm6dso32x_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LSM6DSO32X driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+#include "lsm6dso32x_reg.h"
+
+/**
+ * @defgroup LSM6DSO32X
+ * @brief This file provides a set of functions needed to drive the
+ * lsm6dso32x enhanced inertial module.
+ * @{
+ *
+ */
+
+/**
+ * @defgroup LSM6DSO32X_Interfaces_Functions
+ * @brief This section provide a set of functions used to read and
+ * write a generic register of the device.
+ * MANDATORY: return 0 -> no Error.
+ * @{
+ *
+ */
+
+/**
+ * @brief Read generic device register
+ *
+ * @param ctx communication interface handler.(ptr)
+ * @param reg first register address to read.
+ * @param data buffer for data read.(ptr)
+ * @param len number of consecutive register to read.
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
+{
+ int32_t ret;
+
+ ret = ctx->read_reg(ctx->handle, reg, data, len);
+
+ return ret;
+}
+
+/**
+ * @brief Write generic device register
+ *
+ * @param ctx communication interface handler.(ptr)
+ * @param reg first register address to write.
+ * @param data the buffer contains data to be written.(ptr)
+ * @param len number of consecutive register to write.
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
+{
+ int32_t ret;
+
+ ret = ctx->write_reg(ctx->handle, reg, data, len);
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LSM6DSO32X_Private_functions
+ * @brief Section collect all the utility functions needed by APIs.
+ * @{
+ *
+ */
+
+static void bytecpy(uint8_t *target, uint8_t *source)
+{
+ if ((target != NULL) && (source != NULL))
+ {
+ *target = *source;
+ }
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LSM6DSO32X_Sensitivity
+ * @brief These functions convert raw-data into engineering units.
+ * @{
+ *
+ */
+float_t lsm6dso32x_from_fs4_to_mg(int16_t lsb)
+{
+ return ((float_t)lsb) * 0.122f;
+}
+
+float_t lsm6dso32x_from_fs8_to_mg(int16_t lsb)
+{
+ return ((float_t)lsb) * 0.244f;
+}
+
+float_t lsm6dso32x_from_fs16_to_mg(int16_t lsb)
+{
+ return ((float_t)lsb) * 0.488f;
+}
+
+float_t lsm6dso32x_from_fs32_to_mg(int16_t lsb)
+{
+ return ((float_t)lsb) * 0.976f;
+}
+
+float_t lsm6dso32x_from_fs125_to_mdps(int16_t lsb)
+{
+ return ((float_t)lsb) * 4.375f;
+}
+
+float_t lsm6dso32x_from_fs500_to_mdps(int16_t lsb)
+{
+ return ((float_t)lsb) * 17.50f;
+}
+
+float_t lsm6dso32x_from_fs250_to_mdps(int16_t lsb)
+{
+ return ((float_t)lsb) * 8.750f;
+}
+
+float_t lsm6dso32x_from_fs1000_to_mdps(int16_t lsb)
+{
+ return ((float_t)lsb) * 35.0f;
+}
+
+float_t lsm6dso32x_from_fs2000_to_mdps(int16_t lsb)
+{
+ return ((float_t)lsb) * 70.0f;
+}
+
+float_t lsm6dso32x_from_lsb_to_celsius(int16_t lsb)
+{
+ return (((float_t)lsb / 256.0f) + 25.0f);
+}
+
+float_t lsm6dso32x_from_lsb_to_nsec(int16_t lsb)
+{
+ return ((float_t)lsb * 25000.0f);
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LSM6DSO32X_Data_Generation
+ * @brief This section groups all the functions concerning
+ * data generation.
+ *
+ */
+
+/**
+ * @brief Accelerometer full-scale selection.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of fs_xl in reg CTRL1_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_xl_full_scale_set(stmdev_ctx_t *ctx, lsm6dso32x_fs_xl_t val)
+{
+ lsm6dso32x_ctrl1_xl_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.fs_xl = (uint8_t) val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Accelerometer full-scale selection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of fs_xl in reg CTRL1_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_xl_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_fs_xl_t *val)
+{
+ lsm6dso32x_ctrl1_xl_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®, 1);
+
+ switch (reg.fs_xl)
+ {
+ case LSM6DSO32X_16g:
+ *val = LSM6DSO32X_16g;
+ break;
+
+ case LSM6DSO32X_4g:
+ *val = LSM6DSO32X_4g;
+ break;
+
+ case LSM6DSO32X_8g:
+ *val = LSM6DSO32X_8g;
+ break;
+
+ case LSM6DSO32X_32g:
+ *val = LSM6DSO32X_32g;
+ break;
+
+ default:
+ *val = LSM6DSO32X_4g;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Accelerometer UI data rate selection.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of odr_xl in reg CTRL1_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6dso32x_odr_xl_t val)
+{
+ lsm6dso32x_odr_xl_t odr_xl = val;
+ lsm6dso32x_emb_fsm_enable_t fsm_enable;
+ lsm6dso32x_fsm_odr_t fsm_odr;
+ lsm6dso32x_emb_sens_t emb_sens;
+ lsm6dso32x_mlc_odr_t mlc_odr;
+ lsm6dso32x_ctrl1_xl_t reg;
+ int32_t ret;
+
+ /* Check the Finite State Machine data rate constraints */
+ ret = lsm6dso32x_fsm_enable_get(ctx, &fsm_enable);
+
+ if (ret == 0)
+ {
+ if ((fsm_enable.fsm_enable_a.fsm1_en |
+ fsm_enable.fsm_enable_a.fsm2_en |
+ fsm_enable.fsm_enable_a.fsm3_en |
+ fsm_enable.fsm_enable_a.fsm4_en |
+ fsm_enable.fsm_enable_a.fsm5_en |
+ fsm_enable.fsm_enable_a.fsm6_en |
+ fsm_enable.fsm_enable_a.fsm7_en |
+ fsm_enable.fsm_enable_a.fsm8_en |
+ fsm_enable.fsm_enable_b.fsm9_en |
+ fsm_enable.fsm_enable_b.fsm10_en |
+ fsm_enable.fsm_enable_b.fsm11_en |
+ fsm_enable.fsm_enable_b.fsm12_en |
+ fsm_enable.fsm_enable_b.fsm13_en |
+ fsm_enable.fsm_enable_b.fsm14_en |
+ fsm_enable.fsm_enable_b.fsm15_en |
+ fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
+ {
+ ret = lsm6dso32x_fsm_data_rate_get(ctx, &fsm_odr);
+
+ if (ret == 0)
+ {
+ switch (fsm_odr)
+ {
+ case LSM6DSO32X_ODR_FSM_12Hz5:
+ if (val == LSM6DSO32X_XL_ODR_OFF)
+ {
+ odr_xl = LSM6DSO32X_XL_ODR_12Hz5;
+ }
+
+ else
+ {
+ odr_xl = val;
+ }
+
+ break;
+
+ case LSM6DSO32X_ODR_FSM_26Hz:
+ if (val == LSM6DSO32X_XL_ODR_OFF)
+ {
+ odr_xl = LSM6DSO32X_XL_ODR_26Hz;
+ }
+
+ else if (val == LSM6DSO32X_XL_ODR_12Hz5)
+ {
+ odr_xl = LSM6DSO32X_XL_ODR_26Hz;
+ }
+
+ else
+ {
+ odr_xl = val;
+ }
+
+ break;
+
+ case LSM6DSO32X_ODR_FSM_52Hz:
+ if (val == LSM6DSO32X_XL_ODR_OFF)
+ {
+ odr_xl = LSM6DSO32X_XL_ODR_52Hz;
+ }
+
+ else if (val == LSM6DSO32X_XL_ODR_12Hz5)
+ {
+ odr_xl = LSM6DSO32X_XL_ODR_52Hz;
+ }
+
+ else if (val == LSM6DSO32X_XL_ODR_26Hz)
+ {
+ odr_xl = LSM6DSO32X_XL_ODR_52Hz;
+ }
+
+ else
+ {
+ odr_xl = val;
+ }
+
+ break;
+
+ case LSM6DSO32X_ODR_FSM_104Hz:
+ if (val == LSM6DSO32X_XL_ODR_OFF)
+ {
+ odr_xl = LSM6DSO32X_XL_ODR_104Hz;
+ }
+
+ else if (val == LSM6DSO32X_XL_ODR_12Hz5)
+ {
+ odr_xl = LSM6DSO32X_XL_ODR_104Hz;
+ }
+
+ else if (val == LSM6DSO32X_XL_ODR_26Hz)
+ {
+ odr_xl = LSM6DSO32X_XL_ODR_104Hz;
+ }
+
+ else if (val == LSM6DSO32X_XL_ODR_52Hz)
+ {
+ odr_xl = LSM6DSO32X_XL_ODR_104Hz;
+ }
+
+ else
+ {
+ odr_xl = val;
+ }
+
+ break;
+
+ default:
+ odr_xl = val;
+ break;
+ }
+ }
+ }
+ }
+
+ /* Check the Machine Learning Core data rate constraints */
+ emb_sens.mlc = PROPERTY_DISABLE;
+
+ if (ret == 0)
+ {
+ lsm6dso32x_embedded_sens_get(ctx, &emb_sens);
+
+ if (emb_sens.mlc == PROPERTY_ENABLE)
+ {
+ ret = lsm6dso32x_mlc_data_rate_get(ctx, &mlc_odr);
+
+ if (ret == 0)
+ {
+ switch (mlc_odr)
+ {
+ case LSM6DSO32X_ODR_PRGS_12Hz5:
+ if (val == LSM6DSO32X_XL_ODR_OFF)
+ {
+ odr_xl = LSM6DSO32X_XL_ODR_12Hz5;
+ }
+
+ else
+ {
+ odr_xl = val;
+ }
+
+ break;
+
+ case LSM6DSO32X_ODR_PRGS_26Hz:
+ if (val == LSM6DSO32X_XL_ODR_OFF)
+ {
+ odr_xl = LSM6DSO32X_XL_ODR_26Hz;
+ }
+
+ else if (val == LSM6DSO32X_XL_ODR_12Hz5)
+ {
+ odr_xl = LSM6DSO32X_XL_ODR_26Hz;
+ }
+
+ else
+ {
+ odr_xl = val;
+ }
+
+ break;
+
+ case LSM6DSO32X_ODR_PRGS_52Hz:
+ if (val == LSM6DSO32X_XL_ODR_OFF)
+ {
+ odr_xl = LSM6DSO32X_XL_ODR_52Hz;
+ }
+
+ else if (val == LSM6DSO32X_XL_ODR_12Hz5)
+ {
+ odr_xl = LSM6DSO32X_XL_ODR_52Hz;
+ }
+
+ else if (val == LSM6DSO32X_XL_ODR_26Hz)
+ {
+ odr_xl = LSM6DSO32X_XL_ODR_52Hz;
+ }
+
+ else
+ {
+ odr_xl = val;
+ }
+
+ break;
+
+ case LSM6DSO32X_ODR_PRGS_104Hz:
+ if (val == LSM6DSO32X_XL_ODR_OFF)
+ {
+ odr_xl = LSM6DSO32X_XL_ODR_104Hz;
+ }
+
+ else if (val == LSM6DSO32X_XL_ODR_12Hz5)
+ {
+ odr_xl = LSM6DSO32X_XL_ODR_104Hz;
+ }
+
+ else if (val == LSM6DSO32X_XL_ODR_26Hz)
+ {
+ odr_xl = LSM6DSO32X_XL_ODR_104Hz;
+ }
+
+ else if (val == LSM6DSO32X_XL_ODR_52Hz)
+ {
+ odr_xl = LSM6DSO32X_XL_ODR_104Hz;
+ }
+
+ else
+ {
+ odr_xl = val;
+ }
+
+ break;
+
+ default:
+ odr_xl = val;
+ break;
+ }
+ }
+ }
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ reg.odr_xl = (uint8_t) odr_xl;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Accelerometer UI data rate selection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of odr_xl in reg CTRL1_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_xl_data_rate_get(stmdev_ctx_t *ctx, lsm6dso32x_odr_xl_t *val)
+{
+ lsm6dso32x_ctrl1_xl_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®, 1);
+
+ switch (reg.odr_xl)
+ {
+ case LSM6DSO32X_XL_ODR_OFF:
+ *val = LSM6DSO32X_XL_ODR_OFF;
+ break;
+
+ case LSM6DSO32X_XL_ODR_12Hz5:
+ *val = LSM6DSO32X_XL_ODR_12Hz5;
+ break;
+
+ case LSM6DSO32X_XL_ODR_26Hz:
+ *val = LSM6DSO32X_XL_ODR_26Hz;
+ break;
+
+ case LSM6DSO32X_XL_ODR_52Hz:
+ *val = LSM6DSO32X_XL_ODR_52Hz;
+ break;
+
+ case LSM6DSO32X_XL_ODR_104Hz:
+ *val = LSM6DSO32X_XL_ODR_104Hz;
+ break;
+
+ case LSM6DSO32X_XL_ODR_208Hz:
+ *val = LSM6DSO32X_XL_ODR_208Hz;
+ break;
+
+ case LSM6DSO32X_XL_ODR_417Hz:
+ *val = LSM6DSO32X_XL_ODR_417Hz;
+ break;
+
+ case LSM6DSO32X_XL_ODR_833Hz:
+ *val = LSM6DSO32X_XL_ODR_833Hz;
+ break;
+
+ case LSM6DSO32X_XL_ODR_1667Hz:
+ *val = LSM6DSO32X_XL_ODR_1667Hz;
+ break;
+
+ case LSM6DSO32X_XL_ODR_3333Hz:
+ *val = LSM6DSO32X_XL_ODR_3333Hz;
+ break;
+
+ case LSM6DSO32X_XL_ODR_6667Hz:
+ *val = LSM6DSO32X_XL_ODR_6667Hz;
+ break;
+
+ case LSM6DSO32X_XL_ODR_1Hz6:
+ *val = LSM6DSO32X_XL_ODR_1Hz6;
+ break;
+
+ default:
+ *val = LSM6DSO32X_XL_ODR_OFF;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Gyroscope UI chain full-scale selection.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of fs_g in reg CTRL2_G
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_gy_full_scale_set(stmdev_ctx_t *ctx, lsm6dso32x_fs_g_t val)
+{
+ lsm6dso32x_ctrl2_g_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL2_G, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.fs_g = (uint8_t) val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL2_G, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Gyroscope UI chain full-scale selection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of fs_g in reg CTRL2_G
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_gy_full_scale_get(stmdev_ctx_t *ctx, lsm6dso32x_fs_g_t *val)
+{
+ lsm6dso32x_ctrl2_g_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL2_G, (uint8_t *)®, 1);
+
+ switch (reg.fs_g)
+ {
+ case LSM6DSO32X_250dps:
+ *val = LSM6DSO32X_250dps;
+ break;
+
+ case LSM6DSO32X_125dps:
+ *val = LSM6DSO32X_125dps;
+ break;
+
+ case LSM6DSO32X_500dps:
+ *val = LSM6DSO32X_500dps;
+ break;
+
+ case LSM6DSO32X_1000dps:
+ *val = LSM6DSO32X_1000dps;
+ break;
+
+ case LSM6DSO32X_2000dps:
+ *val = LSM6DSO32X_2000dps;
+ break;
+
+ default:
+ *val = LSM6DSO32X_250dps;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Gyroscope UI data rate selection.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of odr_g in reg CTRL2_G
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_gy_data_rate_set(stmdev_ctx_t *ctx, lsm6dso32x_odr_g_t val)
+{
+ lsm6dso32x_odr_g_t odr_gy = val;
+ lsm6dso32x_emb_fsm_enable_t fsm_enable;
+ lsm6dso32x_fsm_odr_t fsm_odr;
+ lsm6dso32x_emb_sens_t emb_sens;
+ lsm6dso32x_mlc_odr_t mlc_odr;
+ lsm6dso32x_ctrl2_g_t reg;
+ int32_t ret;
+
+ /* Check the Finite State Machine data rate constraints */
+ ret = lsm6dso32x_fsm_enable_get(ctx, &fsm_enable);
+
+ if (ret == 0)
+ {
+ if ((fsm_enable.fsm_enable_a.fsm1_en |
+ fsm_enable.fsm_enable_a.fsm2_en |
+ fsm_enable.fsm_enable_a.fsm3_en |
+ fsm_enable.fsm_enable_a.fsm4_en |
+ fsm_enable.fsm_enable_a.fsm5_en |
+ fsm_enable.fsm_enable_a.fsm6_en |
+ fsm_enable.fsm_enable_a.fsm7_en |
+ fsm_enable.fsm_enable_a.fsm8_en |
+ fsm_enable.fsm_enable_b.fsm9_en |
+ fsm_enable.fsm_enable_b.fsm10_en |
+ fsm_enable.fsm_enable_b.fsm11_en |
+ fsm_enable.fsm_enable_b.fsm12_en |
+ fsm_enable.fsm_enable_b.fsm13_en |
+ fsm_enable.fsm_enable_b.fsm14_en |
+ fsm_enable.fsm_enable_b.fsm15_en |
+ fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
+ {
+ ret = lsm6dso32x_fsm_data_rate_get(ctx, &fsm_odr);
+
+ if (ret == 0)
+ {
+ switch (fsm_odr)
+ {
+ case LSM6DSO32X_ODR_FSM_12Hz5:
+ if (val == LSM6DSO32X_GY_ODR_OFF)
+ {
+ odr_gy = LSM6DSO32X_GY_ODR_12Hz5;
+ }
+
+ else
+ {
+ odr_gy = val;
+ }
+
+ break;
+
+ case LSM6DSO32X_ODR_FSM_26Hz:
+ if (val == LSM6DSO32X_GY_ODR_OFF)
+ {
+ odr_gy = LSM6DSO32X_GY_ODR_26Hz;
+ }
+
+ else if (val == LSM6DSO32X_GY_ODR_12Hz5)
+ {
+ odr_gy = LSM6DSO32X_GY_ODR_26Hz;
+ }
+
+ else
+ {
+ odr_gy = val;
+ }
+
+ break;
+
+ case LSM6DSO32X_ODR_FSM_52Hz:
+ if (val == LSM6DSO32X_GY_ODR_OFF)
+ {
+ odr_gy = LSM6DSO32X_GY_ODR_52Hz;
+ }
+
+ else if (val == LSM6DSO32X_GY_ODR_12Hz5)
+ {
+ odr_gy = LSM6DSO32X_GY_ODR_52Hz;
+ }
+
+ else if (val == LSM6DSO32X_GY_ODR_26Hz)
+ {
+ odr_gy = LSM6DSO32X_GY_ODR_52Hz;
+ }
+
+ else
+ {
+ odr_gy = val;
+ }
+
+ break;
+
+ case LSM6DSO32X_ODR_FSM_104Hz:
+ if (val == LSM6DSO32X_GY_ODR_OFF)
+ {
+ odr_gy = LSM6DSO32X_GY_ODR_104Hz;
+ }
+
+ else if (val == LSM6DSO32X_GY_ODR_12Hz5)
+ {
+ odr_gy = LSM6DSO32X_GY_ODR_104Hz;
+ }
+
+ else if (val == LSM6DSO32X_GY_ODR_26Hz)
+ {
+ odr_gy = LSM6DSO32X_GY_ODR_104Hz;
+ }
+
+ else if (val == LSM6DSO32X_GY_ODR_52Hz)
+ {
+ odr_gy = LSM6DSO32X_GY_ODR_104Hz;
+ }
+
+ else
+ {
+ odr_gy = val;
+ }
+
+ break;
+
+ default:
+ odr_gy = val;
+ break;
+ }
+ }
+ }
+ }
+
+ /* Check the Machine Learning Core data rate constraints */
+ emb_sens.mlc = PROPERTY_DISABLE;
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_embedded_sens_get(ctx, &emb_sens);
+
+ if (emb_sens.mlc == PROPERTY_ENABLE)
+ {
+ ret = lsm6dso32x_mlc_data_rate_get(ctx, &mlc_odr);
+
+ if (ret == 0)
+ {
+ switch (mlc_odr)
+ {
+ case LSM6DSO32X_ODR_PRGS_12Hz5:
+ if (val == LSM6DSO32X_GY_ODR_OFF)
+ {
+ odr_gy = LSM6DSO32X_GY_ODR_12Hz5;
+ }
+
+ else
+ {
+ odr_gy = val;
+ }
+
+ break;
+
+ case LSM6DSO32X_ODR_PRGS_26Hz:
+ if (val == LSM6DSO32X_GY_ODR_OFF)
+ {
+ odr_gy = LSM6DSO32X_GY_ODR_26Hz;
+ }
+
+ else if (val == LSM6DSO32X_GY_ODR_12Hz5)
+ {
+ odr_gy = LSM6DSO32X_GY_ODR_26Hz;
+ }
+
+ else
+ {
+ odr_gy = val;
+ }
+
+ break;
+
+ case LSM6DSO32X_ODR_PRGS_52Hz:
+ if (val == LSM6DSO32X_GY_ODR_OFF)
+ {
+ odr_gy = LSM6DSO32X_GY_ODR_52Hz;
+ }
+
+ else if (val == LSM6DSO32X_GY_ODR_12Hz5)
+ {
+ odr_gy = LSM6DSO32X_GY_ODR_52Hz;
+ }
+
+ else if (val == LSM6DSO32X_GY_ODR_26Hz)
+ {
+ odr_gy = LSM6DSO32X_GY_ODR_52Hz;
+ }
+
+ else
+ {
+ odr_gy = val;
+ }
+
+ break;
+
+ case LSM6DSO32X_ODR_PRGS_104Hz:
+ if (val == LSM6DSO32X_GY_ODR_OFF)
+ {
+ odr_gy = LSM6DSO32X_GY_ODR_104Hz;
+ }
+
+ else if (val == LSM6DSO32X_GY_ODR_12Hz5)
+ {
+ odr_gy = LSM6DSO32X_GY_ODR_104Hz;
+ }
+
+ else if (val == LSM6DSO32X_GY_ODR_26Hz)
+ {
+ odr_gy = LSM6DSO32X_GY_ODR_104Hz;
+ }
+
+ else if (val == LSM6DSO32X_GY_ODR_52Hz)
+ {
+ odr_gy = LSM6DSO32X_GY_ODR_104Hz;
+ }
+
+ else
+ {
+ odr_gy = val;
+ }
+
+ break;
+
+ default:
+ odr_gy = val;
+ break;
+ }
+ }
+ }
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL2_G, (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ reg.odr_g = (uint8_t) odr_gy;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL2_G, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Gyroscope UI data rate selection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of odr_g in reg CTRL2_G
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_gy_data_rate_get(stmdev_ctx_t *ctx, lsm6dso32x_odr_g_t *val)
+{
+ lsm6dso32x_ctrl2_g_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL2_G, (uint8_t *)®, 1);
+
+ switch (reg.odr_g)
+ {
+ case LSM6DSO32X_GY_ODR_OFF:
+ *val = LSM6DSO32X_GY_ODR_OFF;
+ break;
+
+ case LSM6DSO32X_GY_ODR_12Hz5:
+ *val = LSM6DSO32X_GY_ODR_12Hz5;
+ break;
+
+ case LSM6DSO32X_GY_ODR_26Hz:
+ *val = LSM6DSO32X_GY_ODR_26Hz;
+ break;
+
+ case LSM6DSO32X_GY_ODR_52Hz:
+ *val = LSM6DSO32X_GY_ODR_52Hz;
+ break;
+
+ case LSM6DSO32X_GY_ODR_104Hz:
+ *val = LSM6DSO32X_GY_ODR_104Hz;
+ break;
+
+ case LSM6DSO32X_GY_ODR_208Hz:
+ *val = LSM6DSO32X_GY_ODR_208Hz;
+ break;
+
+ case LSM6DSO32X_GY_ODR_417Hz:
+ *val = LSM6DSO32X_GY_ODR_417Hz;
+ break;
+
+ case LSM6DSO32X_GY_ODR_833Hz:
+ *val = LSM6DSO32X_GY_ODR_833Hz;
+ break;
+
+ case LSM6DSO32X_GY_ODR_1667Hz:
+ *val = LSM6DSO32X_GY_ODR_1667Hz;
+ break;
+
+ case LSM6DSO32X_GY_ODR_3333Hz:
+ *val = LSM6DSO32X_GY_ODR_3333Hz;
+ break;
+
+ case LSM6DSO32X_GY_ODR_6667Hz:
+ *val = LSM6DSO32X_GY_ODR_6667Hz;
+ break;
+
+ default:
+ *val = LSM6DSO32X_GY_ODR_OFF;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Block data update.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of bdu in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lsm6dso32x_ctrl3_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.bdu = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Block data update.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of bdu in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lsm6dso32x_ctrl3_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
+ *val = reg.bdu;
+
+ return ret;
+}
+
+/**
+ * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
+ * Y_OFS_USR (74h), Z_OFS_USR (75h).[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of usr_off_w in reg CTRL6_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_xl_offset_weight_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_usr_off_w_t val)
+{
+ lsm6dso32x_ctrl6_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL6_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.usr_off_w = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL6_C, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
+ * Y_OFS_USR (74h), Z_OFS_USR (75h).[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of usr_off_w in reg CTRL6_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_xl_offset_weight_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_usr_off_w_t *val)
+{
+ lsm6dso32x_ctrl6_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL6_C, (uint8_t *)®, 1);
+
+ switch (reg.usr_off_w)
+ {
+ case LSM6DSO32X_LSb_1mg:
+ *val = LSM6DSO32X_LSb_1mg;
+ break;
+
+ case LSM6DSO32X_LSb_16mg:
+ *val = LSM6DSO32X_LSb_16mg;
+ break;
+
+ default:
+ *val = LSM6DSO32X_LSb_1mg;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Accelerometer power mode.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of xl_hm_mode in
+ * reg CTRL6_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_xl_power_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_xl_hm_mode_t val)
+{
+ lsm6dso32x_ctrl5_c_t ctrl5_c;
+ lsm6dso32x_ctrl6_c_t ctrl6_c;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL5_C,
+ (uint8_t *) &ctrl5_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl5_c.xl_ulp_en = ((uint8_t)val & 0x02U) >> 1;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL5_C,
+ (uint8_t *) &ctrl5_c, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL6_C,
+ (uint8_t *) &ctrl6_c, 1);
+ }
+
+ if (ret == 0)
+ {
+ ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL6_C,
+ (uint8_t *) &ctrl6_c, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Accelerometer power mode.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of xl_hm_mode in reg CTRL6_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_xl_power_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_xl_hm_mode_t *val)
+{
+ lsm6dso32x_ctrl5_c_t ctrl5_c;
+ lsm6dso32x_ctrl6_c_t ctrl6_c;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL5_C,
+ (uint8_t *) &ctrl5_c, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL6_C,
+ (uint8_t *) &ctrl6_c, 1);
+
+ switch ((ctrl5_c.xl_ulp_en << 1) | ctrl6_c.xl_hm_mode)
+ {
+ case LSM6DSO32X_HIGH_PERFORMANCE_MD:
+ *val = LSM6DSO32X_HIGH_PERFORMANCE_MD;
+ break;
+
+ case LSM6DSO32X_LOW_NORMAL_POWER_MD:
+ *val = LSM6DSO32X_LOW_NORMAL_POWER_MD;
+ break;
+
+ case LSM6DSO32X_ULTRA_LOW_POWER_MD:
+ *val = LSM6DSO32X_ULTRA_LOW_POWER_MD;
+ break;
+
+ default:
+ *val = LSM6DSO32X_HIGH_PERFORMANCE_MD;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Operating mode for gyroscope.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of g_hm_mode in reg CTRL7_G
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_gy_power_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_g_hm_mode_t val)
+{
+ lsm6dso32x_ctrl7_g_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL7_G, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.g_hm_mode = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL7_G, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Operating mode for gyroscope.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of g_hm_mode in reg CTRL7_G
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_gy_power_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_g_hm_mode_t *val)
+{
+ lsm6dso32x_ctrl7_g_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL7_G, (uint8_t *)®, 1);
+
+ switch (reg.g_hm_mode)
+ {
+ case LSM6DSO32X_GY_HIGH_PERFORMANCE:
+ *val = LSM6DSO32X_GY_HIGH_PERFORMANCE;
+ break;
+
+ case LSM6DSO32X_GY_NORMAL:
+ *val = LSM6DSO32X_GY_NORMAL;
+ break;
+
+ default:
+ *val = LSM6DSO32X_GY_HIGH_PERFORMANCE;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief The STATUS_REG register is read by the primary interface.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val register STATUS_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_status_reg_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_status_reg_t *val)
+{
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_STATUS_REG, (uint8_t *) val, 1);
+
+ return ret;
+}
+
+/**
+ * @brief Accelerometer new data available.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of xlda in reg STATUS_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lsm6dso32x_status_reg_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_STATUS_REG, (uint8_t *)®, 1);
+ *val = reg.xlda;
+
+ return ret;
+}
+
+/**
+ * @brief Gyroscope new data available.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of gda in reg STATUS_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lsm6dso32x_status_reg_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_STATUS_REG, (uint8_t *)®, 1);
+ *val = reg.gda;
+
+ return ret;
+}
+
+/**
+ * @brief Temperature new data available.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of tda in reg STATUS_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lsm6dso32x_status_reg_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_STATUS_REG, (uint8_t *)®, 1);
+ *val = reg.tda;
+
+ return ret;
+}
+
+/**
+ * @brief Accelerometer X-axis user offset correction expressed in
+ * two’s complement, weight depends on USR_OFF_W in CTRL6_C (15h).
+ * The value must be in the range [-127 127].[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
+{
+ int32_t ret;
+
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_X_OFS_USR, buff, 1);
+
+ return ret;
+}
+
+/**
+ * @brief Accelerometer X-axis user offset correction expressed in two’s
+ * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
+ * The value must be in the range [-127 127].[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
+{
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_X_OFS_USR, buff, 1);
+
+ return ret;
+}
+
+/**
+ * @brief Accelerometer Y-axis user offset correction expressed in two’s
+ * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
+ * The value must be in the range [-127 127].[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
+{
+ int32_t ret;
+
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_Y_OFS_USR, buff, 1);
+
+ return ret;
+}
+
+/**
+ * @brief Accelerometer Y-axis user offset correction expressed in two’s
+ * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
+ * The value must be in the range [-127 127].[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
+{
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_Y_OFS_USR, buff, 1);
+
+ return ret;
+}
+
+/**
+ * @brief Accelerometer Z-axis user offset correction expressed in two’s
+ * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
+ * The value must be in the range [-127 127].[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
+{
+ int32_t ret;
+
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_Z_OFS_USR, buff, 1);
+
+ return ret;
+}
+
+/**
+ * @brief Accelerometer Z-axis user offset correction expressed in two’s
+ * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
+ * The value must be in the range [-127 127].[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff)
+{
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_Z_OFS_USR, buff, 1);
+
+ return ret;
+}
+
+/**
+ * @brief Enables user offset on out.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of usr_off_on_out in reg CTRL7_G
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lsm6dso32x_ctrl7_g_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL7_G, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.usr_off_on_out = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL7_G, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief User offset on out flag.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val values of usr_off_on_out in reg CTRL7_G
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lsm6dso32x_ctrl7_g_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL7_G, (uint8_t *)®, 1);
+ *val = reg.usr_off_on_out;
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LSM6DSO32X_Timestamp
+ * @brief This section groups all the functions that manage the
+ * timestamp generation.
+ * @{
+ *
+ */
+
+/**
+ * @brief Reset timestamp counter.[set]
+ *
+ * @param ctx Read / write interface definitions.(ptr)
+ * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_timestamp_rst(stmdev_ctx_t *ctx)
+{
+ uint8_t rst_val = 0xAA;
+ return lsm6dso32x_write_reg(ctx, LSM6DSO32X_TIMESTAMP2, &rst_val, 1);
+}
+
+/**
+ * @brief Enables timestamp counter.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of timestamp_en in reg CTRL10_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lsm6dso32x_ctrl10_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL10_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.timestamp_en = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL10_C, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enables timestamp counter.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of timestamp_en in reg CTRL10_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lsm6dso32x_ctrl10_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL10_C, (uint8_t *)®, 1);
+ *val = reg.timestamp_en;
+
+ return ret;
+}
+
+/**
+ * @brief Timestamp first data output register (r).
+ * The value is expressed as a 32-bit word and the bit
+ * resolution is 25 μs.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val)
+{
+ uint8_t buff[4];
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TIMESTAMP0, buff, 4);
+ *val = buff[3];
+ *val = (*val * 256U) + buff[2];
+ *val = (*val * 256U) + buff[1];
+ *val = (*val * 256U) + buff[0];
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LSM6DSO32X_Data output
+ * @brief This section groups all the data output functions.
+ * @{
+ *
+ */
+
+/**
+ * @brief Circular burst-mode (rounding) read of the output
+ * registers.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of rounding in reg CTRL5_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_rounding_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_rounding_t val)
+{
+ lsm6dso32x_ctrl5_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL5_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.rounding = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL5_C, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Gyroscope UI chain full-scale selection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of rounding in reg CTRL5_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_rounding_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_rounding_t *val)
+{
+ lsm6dso32x_ctrl5_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL5_C, (uint8_t *)®, 1);
+
+ switch (reg.rounding)
+ {
+ case LSM6DSO32X_NO_ROUND:
+ *val = LSM6DSO32X_NO_ROUND;
+ break;
+
+ case LSM6DSO32X_ROUND_XL:
+ *val = LSM6DSO32X_ROUND_XL;
+ break;
+
+ case LSM6DSO32X_ROUND_GY:
+ *val = LSM6DSO32X_ROUND_GY;
+ break;
+
+ case LSM6DSO32X_ROUND_GY_XL:
+ *val = LSM6DSO32X_ROUND_GY_XL;
+ break;
+
+ default:
+ *val = LSM6DSO32X_NO_ROUND;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Temperature data output register (r).
+ * L and H registers together express a 16-bit word in two’s
+ * complement.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_temperature_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
+{
+ uint8_t buff[2];
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_OUT_TEMP_L, buff, 2);
+ *val = (int16_t)buff[1];
+ *val = (*val * 256) + (int16_t)buff[0];
+
+ return ret;
+}
+
+/**
+ * @brief Angular rate sensor. The value is expressed as a 16-bit
+ * word in two’s complement.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_angular_rate_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
+{
+ uint8_t buff[6];
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_OUTX_L_G, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
+ return ret;
+}
+
+/**
+ * @brief Linear acceleration output register.
+ * The value is expressed as a 16-bit word in two’s complement.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
+{
+ uint8_t buff[6];
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_OUTX_L_A, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
+ return ret;
+}
+
+/**
+ * @brief FIFO data output [get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+{
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_DATA_OUT_X_L, buff, 6);
+
+ return ret;
+}
+
+/**
+ * @brief Step counter output register.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_number_of_steps_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
+{
+ uint8_t buff[2];
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_STEP_COUNTER_L, buff, 2);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Reset step counter register.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_steps_reset(stmdev_ctx_t *ctx)
+{
+ lsm6dso32x_emb_func_src_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_SRC,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ reg.pedo_rst_step = PROPERTY_ENABLE;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_SRC,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief prgsens_out: [get] Output value of all MLCx decision trees.
+ *
+ * @param ctx_t *ctx: read / write interface definitions
+ * @param uint8_t * : buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff)
+{
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MLC0_SRC, buff, 8);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LSM6DSO32X_common
+ * @brief This section groups common useful functions.
+ * @{
+ *
+ */
+
+/**
+ * @brief Difference in percentage of the effective ODR(and timestamp rate)
+ * with respect to the typical.
+ * Step: 0.15%. 8-bit format, 2's complement.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of freq_fine in reg
+ * INTERNAL_FREQ_FINE
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lsm6dso32x_internal_freq_fine_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INTERNAL_FREQ_FINE,
+ (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.freq_fine = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_INTERNAL_FREQ_FINE,
+ (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Difference in percentage of the effective ODR(and timestamp rate)
+ * with respect to the typical.
+ * Step: 0.15%. 8-bit format, 2's complement.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of freq_fine in reg INTERNAL_FREQ_FINE
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lsm6dso32x_internal_freq_fine_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INTERNAL_FREQ_FINE,
+ (uint8_t *)®, 1);
+ *val = reg.freq_fine;
+
+ return ret;
+}
+
+
+/**
+ * @brief Enable access to the embedded functions/sensor
+ * hub configuration registers.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of reg_access in
+ * reg FUNC_CFG_ACCESS
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_mem_bank_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_reg_access_t val)
+{
+ lsm6dso32x_func_cfg_access_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FUNC_CFG_ACCESS,
+ (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.reg_access = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FUNC_CFG_ACCESS,
+ (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable access to the embedded functions/sensor
+ * hub configuration registers.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of reg_access in
+ * reg FUNC_CFG_ACCESS
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_mem_bank_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_reg_access_t *val)
+{
+ lsm6dso32x_func_cfg_access_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FUNC_CFG_ACCESS,
+ (uint8_t *)®, 1);
+
+ switch (reg.reg_access)
+ {
+ case LSM6DSO32X_USER_BANK:
+ *val = LSM6DSO32X_USER_BANK;
+ break;
+
+ case LSM6DSO32X_SENSOR_HUB_BANK:
+ *val = LSM6DSO32X_SENSOR_HUB_BANK;
+ break;
+
+ case LSM6DSO32X_EMBEDDED_FUNC_BANK:
+ *val = LSM6DSO32X_EMBEDDED_FUNC_BANK;
+ break;
+
+ default:
+ *val = LSM6DSO32X_USER_BANK;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Write a line(byte) in a page.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param uint8_t address: page line address
+ * @param val value to write
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_ln_pg_write_byte(stmdev_ctx_t *ctx,
+ uint16_t address,
+ uint8_t *val)
+{
+ lsm6dso32x_page_rw_t page_rw;
+ lsm6dso32x_page_sel_t page_sel;
+ lsm6dso32x_page_address_t page_address;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
+ (uint8_t *) &page_rw, 1);
+ }
+
+ if (ret == 0)
+ {
+ page_rw.page_rw = 0x02; /* page_write enable */
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW,
+ (uint8_t *) &page_rw, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_SEL,
+ (uint8_t *) &page_sel, 1);
+ }
+
+ if (ret == 0)
+ {
+ page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
+ page_sel.not_used_01 = 1;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_SEL,
+ (uint8_t *) &page_sel, 1);
+ }
+
+ if (ret == 0)
+ {
+ page_address.page_addr = (uint8_t)address & 0xFFU;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_ADDRESS,
+ (uint8_t *)&page_address, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_VALUE, val, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
+ (uint8_t *) &page_rw, 1);
+ }
+
+ if (ret == 0)
+ {
+ page_rw.page_rw = 0x00; /* page_write disable */
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW,
+ (uint8_t *) &page_rw, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Write buffer in a page.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param uint8_t address: page line address
+ * @param uint8_t *buf: buffer to write
+ * @param uint8_t len: buffer len
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address,
+ uint8_t *buf, uint8_t len)
+{
+ lsm6dso32x_page_rw_t page_rw;
+ lsm6dso32x_page_sel_t page_sel;
+ lsm6dso32x_page_address_t page_address;
+ int32_t ret;
+
+ uint8_t msb, lsb;
+ uint8_t i ;
+ msb = ((uint8_t)(address >> 8) & 0x0FU);
+ lsb = (uint8_t)address & 0xFFU;
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
+ (uint8_t *) &page_rw, 1);
+ }
+
+ if (ret == 0)
+ {
+ page_rw.page_rw = 0x02; /* page_write enable*/
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW,
+ (uint8_t *) &page_rw, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_SEL,
+ (uint8_t *) &page_sel, 1);
+ }
+
+ if (ret == 0)
+ {
+ page_sel.page_sel = msb;
+ page_sel.not_used_01 = 1;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_SEL,
+ (uint8_t *) &page_sel, 1);
+ }
+
+ if (ret == 0)
+ {
+ page_address.page_addr = lsb;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_ADDRESS,
+ (uint8_t *)&page_address, 1);
+ }
+
+ if (ret == 0)
+ {
+ for (i = 0; ((i < len) && (ret == 0)); i++)
+ {
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_VALUE, &buf[i], 1);
+ lsb++;
+
+ /* Check if page wrap */
+ if ((lsb == 0x00U) && (ret == 0))
+ {
+ msb++;
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_SEL,
+ (uint8_t *)&page_sel, 1);
+
+ if (ret == 0)
+ {
+ page_sel.page_sel = msb;
+ page_sel.not_used_01 = 1;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_SEL,
+ (uint8_t *)&page_sel, 1);
+ }
+ }
+ }
+ }
+
+ page_sel.page_sel = 0;
+ page_sel.not_used_01 = 1;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_SEL,
+ (uint8_t *) &page_sel, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
+ (uint8_t *) &page_rw, 1);
+ }
+
+ if (ret == 0)
+ {
+ page_rw.page_rw = 0x00; /* page_write disable */
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW,
+ (uint8_t *) &page_rw, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Read a line(byte) in a page.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param uint8_t address: page line address
+ * @param val read value
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_ln_pg_read_byte(stmdev_ctx_t *ctx,
+ uint16_t address,
+ uint8_t *val)
+{
+ lsm6dso32x_page_rw_t page_rw;
+ lsm6dso32x_page_sel_t page_sel;
+ lsm6dso32x_page_address_t page_address;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
+ (uint8_t *) &page_rw, 1);
+ }
+
+ if (ret == 0)
+ {
+ page_rw.page_rw = 0x01; /* page_read enable*/
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW,
+ (uint8_t *) &page_rw, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_SEL,
+ (uint8_t *) &page_sel, 1);
+ }
+
+ if (ret == 0)
+ {
+ page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
+ page_sel.not_used_01 = 1;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_SEL,
+ (uint8_t *) &page_sel, 1);
+ }
+
+ if (ret == 0)
+ {
+ page_address.page_addr = (uint8_t)address & 0x00FFU;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_ADDRESS,
+ (uint8_t *)&page_address, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_VALUE, val, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
+ (uint8_t *) &page_rw, 1);
+ }
+
+ if (ret == 0)
+ {
+ page_rw.page_rw = 0x00; /* page_read disable */
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW,
+ (uint8_t *) &page_rw, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Data-ready pulsed / letched mode.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of
+ * dataready_pulsed in
+ * reg COUNTER_BDR_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_data_ready_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_dataready_pulsed_t val)
+{
+ lsm6dso32x_counter_bdr_reg1_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
+ (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.dataready_pulsed = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
+ (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Data-ready pulsed / letched mode.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of
+ * dataready_pulsed in
+ * reg COUNTER_BDR_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_data_ready_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_dataready_pulsed_t *val)
+{
+ lsm6dso32x_counter_bdr_reg1_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
+ (uint8_t *)®, 1);
+
+ switch (reg.dataready_pulsed)
+ {
+ case LSM6DSO32X_DRDY_LATCHED:
+ *val = LSM6DSO32X_DRDY_LATCHED;
+ break;
+
+ case LSM6DSO32X_DRDY_PULSED:
+ *val = LSM6DSO32X_DRDY_PULSED;
+ break;
+
+ default:
+ *val = LSM6DSO32X_DRDY_LATCHED;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Device "Who am I".[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
+{
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WHO_AM_I, buff, 1);
+
+ return ret;
+}
+
+/**
+ * @brief Software reset. Restore the default values
+ * in user registers[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of sw_reset in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_reset_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lsm6dso32x_ctrl3_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.sw_reset = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Software reset. Restore the default values in user registers.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of sw_reset in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lsm6dso32x_ctrl3_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
+ *val = reg.sw_reset;
+
+ return ret;
+}
+
+/**
+ * @brief Register address automatically incremented during a multiple byte
+ * access with a serial interface.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of if_inc in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lsm6dso32x_ctrl3_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.if_inc = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Register address automatically incremented during a multiple byte
+ * access with a serial interface.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of if_inc in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lsm6dso32x_ctrl3_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
+ *val = reg.if_inc;
+
+ return ret;
+}
+
+/**
+ * @brief Reboot memory content. Reload the calibration parameters.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of boot in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_boot_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lsm6dso32x_ctrl3_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.boot = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Reboot memory content. Reload the calibration parameters.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of boot in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lsm6dso32x_ctrl3_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
+ *val = reg.boot;
+
+ return ret;
+}
+
+/**
+ * @brief Linear acceleration sensor self-test enable.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of st_xl in reg CTRL5_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_xl_self_test_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_st_xl_t val)
+{
+ lsm6dso32x_ctrl5_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL5_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.st_xl = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL5_C, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Linear acceleration sensor self-test enable.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of st_xl in reg CTRL5_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_xl_self_test_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_st_xl_t *val)
+{
+ lsm6dso32x_ctrl5_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL5_C, (uint8_t *)®, 1);
+
+ switch (reg.st_xl)
+ {
+ case LSM6DSO32X_XL_ST_DISABLE:
+ *val = LSM6DSO32X_XL_ST_DISABLE;
+ break;
+
+ case LSM6DSO32X_XL_ST_POSITIVE:
+ *val = LSM6DSO32X_XL_ST_POSITIVE;
+ break;
+
+ case LSM6DSO32X_XL_ST_NEGATIVE:
+ *val = LSM6DSO32X_XL_ST_NEGATIVE;
+ break;
+
+ default:
+ *val = LSM6DSO32X_XL_ST_DISABLE;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Angular rate sensor self-test enable.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of st_g in reg CTRL5_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_gy_self_test_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_st_g_t val)
+{
+ lsm6dso32x_ctrl5_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL5_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.st_g = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL5_C, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Angular rate sensor self-test enable.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of st_g in reg CTRL5_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_gy_self_test_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_st_g_t *val)
+{
+ lsm6dso32x_ctrl5_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL5_C, (uint8_t *)®, 1);
+
+ switch (reg.st_g)
+ {
+ case LSM6DSO32X_GY_ST_DISABLE:
+ *val = LSM6DSO32X_GY_ST_DISABLE;
+ break;
+
+ case LSM6DSO32X_GY_ST_POSITIVE:
+ *val = LSM6DSO32X_GY_ST_POSITIVE;
+ break;
+
+ case LSM6DSO32X_GY_ST_NEGATIVE:
+ *val = LSM6DSO32X_GY_ST_NEGATIVE;
+ break;
+
+ default:
+ *val = LSM6DSO32X_GY_ST_DISABLE;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LSM6DSO32X_filters
+ * @brief This section group all the functions concerning the
+ * filters configuration
+ * @{
+ *
+ */
+
+/**
+ * @brief Accelerometer output from LPF2 filtering stage selection.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of lpf2_xl_en in reg CTRL1_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lsm6dso32x_ctrl1_xl_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.lpf2_xl_en = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Accelerometer output from LPF2 filtering stage selection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of lpf2_xl_en in reg CTRL1_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lsm6dso32x_ctrl1_xl_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®, 1);
+ *val = reg.lpf2_xl_en;
+
+ return ret;
+}
+
+/**
+ * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
+ * the bandwidth can be selected through FTYPE [2:0]
+ * in CTRL6_C (15h).[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of lpf1_sel_g in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lsm6dso32x_ctrl4_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.lpf1_sel_g = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
+ * the bandwidth can be selected through FTYPE [2:0]
+ * in CTRL6_C (15h).[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of lpf1_sel_g in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lsm6dso32x_ctrl4_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
+ *val = reg.lpf1_sel_g;
+
+ return ret;
+}
+
+/**
+ * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
+ * (XL and Gyro independently masked).[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of drdy_mask in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_filter_settling_mask_set(stmdev_ctx_t *ctx,
+ uint8_t val)
+{
+ lsm6dso32x_ctrl4_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.drdy_mask = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
+ * (XL and Gyro independently masked).[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of drdy_mask in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_filter_settling_mask_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lsm6dso32x_ctrl4_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
+ *val = reg.drdy_mask;
+
+ return ret;
+}
+
+/**
+ * @brief Gyroscope lp1 bandwidth.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of ftype in reg CTRL6_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_ftype_t val)
+{
+ lsm6dso32x_ctrl6_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL6_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.ftype = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL6_C, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Gyroscope lp1 bandwidth.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of ftype in reg CTRL6_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_ftype_t *val)
+{
+ lsm6dso32x_ctrl6_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL6_C, (uint8_t *)®, 1);
+
+ switch (reg.ftype)
+ {
+ case LSM6DSO32X_ULTRA_LIGHT:
+ *val = LSM6DSO32X_ULTRA_LIGHT;
+ break;
+
+ case LSM6DSO32X_VERY_LIGHT:
+ *val = LSM6DSO32X_VERY_LIGHT;
+ break;
+
+ case LSM6DSO32X_LIGHT:
+ *val = LSM6DSO32X_LIGHT;
+ break;
+
+ case LSM6DSO32X_MEDIUM:
+ *val = LSM6DSO32X_MEDIUM;
+ break;
+
+ case LSM6DSO32X_STRONG:
+ *val = LSM6DSO32X_STRONG;
+ break;
+
+ case LSM6DSO32X_VERY_STRONG:
+ *val = LSM6DSO32X_VERY_STRONG;
+ break;
+
+ case LSM6DSO32X_AGGRESSIVE:
+ *val = LSM6DSO32X_AGGRESSIVE;
+ break;
+
+ case LSM6DSO32X_XTREME:
+ *val = LSM6DSO32X_XTREME;
+ break;
+
+ default:
+ *val = LSM6DSO32X_ULTRA_LIGHT;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Low pass filter 2 on 6D function selection.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of low_pass_on_6d in reg CTRL8_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lsm6dso32x_ctrl8_xl_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL8_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.low_pass_on_6d = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL8_XL, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Low pass filter 2 on 6D function selection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of low_pass_on_6d in reg CTRL8_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lsm6dso32x_ctrl8_xl_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL8_XL, (uint8_t *)®, 1);
+ *val = reg.low_pass_on_6d;
+
+ return ret;
+}
+
+/**
+ * @brief Accelerometer slope filter / high-pass filter selection
+ * on output.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of hp_slope_xl_en
+ * in reg CTRL8_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_hp_slope_xl_en_t val)
+{
+ lsm6dso32x_ctrl8_xl_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL8_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.hp_slope_xl_en = ((uint8_t)val & 0x10U) >> 4;
+ reg.hp_ref_mode_xl = ((uint8_t)val & 0x20U) >> 5;
+ reg.hpcf_xl = (uint8_t)val & 0x07U;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL8_XL, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Accelerometer slope filter / high-pass filter selection
+ * on output.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of hp_slope_xl_en
+ * in reg CTRL8_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_hp_slope_xl_en_t *val)
+{
+ lsm6dso32x_ctrl8_xl_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL8_XL, (uint8_t *)®, 1);
+
+ switch ((reg.hp_ref_mode_xl << 5) | (reg.hp_slope_xl_en << 4) |
+ reg.hpcf_xl)
+ {
+ case LSM6DSO32X_HP_PATH_DISABLE_ON_OUT:
+ *val = LSM6DSO32X_HP_PATH_DISABLE_ON_OUT;
+ break;
+
+ case LSM6DSO32X_SLOPE_ODR_DIV_4:
+ *val = LSM6DSO32X_SLOPE_ODR_DIV_4;
+ break;
+
+ case LSM6DSO32X_HP_ODR_DIV_10:
+ *val = LSM6DSO32X_HP_ODR_DIV_10;
+ break;
+
+ case LSM6DSO32X_HP_ODR_DIV_20:
+ *val = LSM6DSO32X_HP_ODR_DIV_20;
+ break;
+
+ case LSM6DSO32X_HP_ODR_DIV_45:
+ *val = LSM6DSO32X_HP_ODR_DIV_45;
+ break;
+
+ case LSM6DSO32X_HP_ODR_DIV_100:
+ *val = LSM6DSO32X_HP_ODR_DIV_100;
+ break;
+
+ case LSM6DSO32X_HP_ODR_DIV_200:
+ *val = LSM6DSO32X_HP_ODR_DIV_200;
+ break;
+
+ case LSM6DSO32X_HP_ODR_DIV_400:
+ *val = LSM6DSO32X_HP_ODR_DIV_400;
+ break;
+
+ case LSM6DSO32X_HP_ODR_DIV_800:
+ *val = LSM6DSO32X_HP_ODR_DIV_800;
+ break;
+
+ case LSM6DSO32X_HP_REF_MD_ODR_DIV_10:
+ *val = LSM6DSO32X_HP_REF_MD_ODR_DIV_10;
+ break;
+
+ case LSM6DSO32X_HP_REF_MD_ODR_DIV_20:
+ *val = LSM6DSO32X_HP_REF_MD_ODR_DIV_20;
+ break;
+
+ case LSM6DSO32X_HP_REF_MD_ODR_DIV_45:
+ *val = LSM6DSO32X_HP_REF_MD_ODR_DIV_45;
+ break;
+
+ case LSM6DSO32X_HP_REF_MD_ODR_DIV_100:
+ *val = LSM6DSO32X_HP_REF_MD_ODR_DIV_100;
+ break;
+
+ case LSM6DSO32X_HP_REF_MD_ODR_DIV_200:
+ *val = LSM6DSO32X_HP_REF_MD_ODR_DIV_200;
+ break;
+
+ case LSM6DSO32X_HP_REF_MD_ODR_DIV_400:
+ *val = LSM6DSO32X_HP_REF_MD_ODR_DIV_400;
+ break;
+
+ case LSM6DSO32X_HP_REF_MD_ODR_DIV_800:
+ *val = LSM6DSO32X_HP_REF_MD_ODR_DIV_800;
+ break;
+
+ case LSM6DSO32X_LP_ODR_DIV_10:
+ *val = LSM6DSO32X_LP_ODR_DIV_10;
+ break;
+
+ case LSM6DSO32X_LP_ODR_DIV_20:
+ *val = LSM6DSO32X_LP_ODR_DIV_20;
+ break;
+
+ case LSM6DSO32X_LP_ODR_DIV_45:
+ *val = LSM6DSO32X_LP_ODR_DIV_45;
+ break;
+
+ case LSM6DSO32X_LP_ODR_DIV_100:
+ *val = LSM6DSO32X_LP_ODR_DIV_100;
+ break;
+
+ case LSM6DSO32X_LP_ODR_DIV_200:
+ *val = LSM6DSO32X_LP_ODR_DIV_200;
+ break;
+
+ case LSM6DSO32X_LP_ODR_DIV_400:
+ *val = LSM6DSO32X_LP_ODR_DIV_400;
+ break;
+
+ case LSM6DSO32X_LP_ODR_DIV_800:
+ *val = LSM6DSO32X_LP_ODR_DIV_800;
+ break;
+
+ default:
+ *val = LSM6DSO32X_HP_PATH_DISABLE_ON_OUT;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
+ * The filter sets the second samples after writing this bit.
+ * Active only during device exit from power-down mode.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of fastsettl_mode_xl in
+ * reg CTRL8_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_xl_fast_settling_set(stmdev_ctx_t *ctx,
+ uint8_t val)
+{
+ lsm6dso32x_ctrl8_xl_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL8_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.fastsettl_mode_xl = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL8_XL, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
+ * The filter sets the second samples after writing this bit.
+ * Active only during device exit from power-down mode.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of fastsettl_mode_xl in reg CTRL8_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_xl_fast_settling_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lsm6dso32x_ctrl8_xl_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL8_XL, (uint8_t *)®, 1);
+ *val = reg.fastsettl_mode_xl;
+
+ return ret;
+}
+
+/**
+ * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
+ * functions.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of slope_fds in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_slope_fds_t val)
+{
+ lsm6dso32x_tap_cfg0_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.slope_fds = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
+ * functions.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Change the values of slope_fds in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_slope_fds_t *val)
+{
+ lsm6dso32x_tap_cfg0_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
+
+ switch (reg.slope_fds)
+ {
+ case LSM6DSO32X_USE_SLOPE:
+ *val = LSM6DSO32X_USE_SLOPE;
+ break;
+
+ case LSM6DSO32X_USE_HPF:
+ *val = LSM6DSO32X_USE_HPF;
+ break;
+
+ default:
+ *val = LSM6DSO32X_USE_SLOPE;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enables gyroscope digital high-pass filter. The filter is
+ * enabled only if the gyro is in HP mode.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of hp_en_g and hp_en_g
+ * in reg CTRL7_G
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_hpm_g_t val)
+{
+ lsm6dso32x_ctrl7_g_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL7_G, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.hp_en_g = ((uint8_t)val & 0x80U) >> 7;
+ reg.hpm_g = (uint8_t)val & 0x03U;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL7_G, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enables gyroscope digital high-pass filter. The filter is
+ * enabled only if the gyro is in HP mode.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of hp_en_g and hp_en_g
+ * in reg CTRL7_G
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_hpm_g_t *val)
+{
+ lsm6dso32x_ctrl7_g_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL7_G, (uint8_t *)®, 1);
+
+ switch ((reg.hp_en_g << 7) + reg.hpm_g)
+ {
+ case LSM6DSO32X_HP_FILTER_NONE:
+ *val = LSM6DSO32X_HP_FILTER_NONE;
+ break;
+
+ case LSM6DSO32X_HP_FILTER_16mHz:
+ *val = LSM6DSO32X_HP_FILTER_16mHz;
+ break;
+
+ case LSM6DSO32X_HP_FILTER_65mHz:
+ *val = LSM6DSO32X_HP_FILTER_65mHz;
+ break;
+
+ case LSM6DSO32X_HP_FILTER_260mHz:
+ *val = LSM6DSO32X_HP_FILTER_260mHz;
+ break;
+
+ case LSM6DSO32X_HP_FILTER_1Hz04:
+ *val = LSM6DSO32X_HP_FILTER_1Hz04;
+ break;
+
+ default:
+ *val = LSM6DSO32X_HP_FILTER_NONE;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LSM6DSO32X_ main_serial_interface
+ * @brief This section groups all the functions concerning main
+ * serial interface management (not auxiliary)
+ * @{
+ *
+ */
+
+/**
+ * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of sdo_pu_en in
+ * reg PIN_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_sdo_pu_en_t val)
+{
+ lsm6dso32x_pin_ctrl_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PIN_CTRL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.sdo_pu_en = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PIN_CTRL, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of sdo_pu_en in reg PIN_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_sdo_pu_en_t *val)
+{
+ lsm6dso32x_pin_ctrl_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PIN_CTRL, (uint8_t *)®, 1);
+
+ switch (reg.sdo_pu_en)
+ {
+ case LSM6DSO32X_PULL_UP_DISC:
+ *val = LSM6DSO32X_PULL_UP_DISC;
+ break;
+
+ case LSM6DSO32X_PULL_UP_CONNECT:
+ *val = LSM6DSO32X_PULL_UP_CONNECT;
+ break;
+
+ default:
+ *val = LSM6DSO32X_PULL_UP_DISC;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief SPI Serial Interface Mode selection.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of sim in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_spi_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_sim_t val)
+{
+ lsm6dso32x_ctrl3_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.sim = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief SPI Serial Interface Mode selection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of sim in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_spi_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_sim_t *val)
+{
+ lsm6dso32x_ctrl3_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
+
+ switch (reg.sim)
+ {
+ case LSM6DSO32X_SPI_4_WIRE:
+ *val = LSM6DSO32X_SPI_4_WIRE;
+ break;
+
+ case LSM6DSO32X_SPI_3_WIRE:
+ *val = LSM6DSO32X_SPI_3_WIRE;
+ break;
+
+ default:
+ *val = LSM6DSO32X_SPI_4_WIRE;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Disable / Enable I2C interface.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of i2c_disable in
+ * reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_i2c_interface_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_i2c_disable_t val)
+{
+ lsm6dso32x_ctrl4_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.i2c_disable = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Disable / Enable I2C interface.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of i2c_disable in
+ * reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_i2c_interface_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_i2c_disable_t *val)
+{
+ lsm6dso32x_ctrl4_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
+
+ switch (reg.i2c_disable)
+ {
+ case LSM6DSO32X_I2C_ENABLE:
+ *val = LSM6DSO32X_I2C_ENABLE;
+ break;
+
+ case LSM6DSO32X_I2C_DISABLE:
+ *val = LSM6DSO32X_I2C_DISABLE;
+ break;
+
+ default:
+ *val = LSM6DSO32X_I2C_ENABLE;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief I3C Enable/Disable communication protocol[.set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of i3c_disable
+ * in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_i3c_disable_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_i3c_disable_t val)
+{
+ lsm6dso32x_i3c_bus_avb_t i3c_bus_avb;
+ lsm6dso32x_ctrl9_xl_t ctrl9_xl;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
+ (uint8_t *)&i3c_bus_avb, 1);
+ }
+
+ if (ret == 0)
+ {
+ i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
+ (uint8_t *)&i3c_bus_avb, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief I3C Enable/Disable communication protocol.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of i3c_disable in
+ * reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_i3c_disable_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_i3c_disable_t *val)
+{
+ lsm6dso32x_ctrl9_xl_t ctrl9_xl;
+ lsm6dso32x_i3c_bus_avb_t i3c_bus_avb;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
+ (uint8_t *)&i3c_bus_avb, 1);
+
+ switch ((ctrl9_xl.i3c_disable << 7) | i3c_bus_avb.i3c_bus_avb_sel)
+ {
+ case LSM6DSO32X_I3C_DISABLE:
+ *val = LSM6DSO32X_I3C_DISABLE;
+ break;
+
+ case LSM6DSO32X_I3C_ENABLE_T_50us:
+ *val = LSM6DSO32X_I3C_ENABLE_T_50us;
+ break;
+
+ case LSM6DSO32X_I3C_ENABLE_T_2us:
+ *val = LSM6DSO32X_I3C_ENABLE_T_2us;
+ break;
+
+ case LSM6DSO32X_I3C_ENABLE_T_1ms:
+ *val = LSM6DSO32X_I3C_ENABLE_T_1ms;
+ break;
+
+ case LSM6DSO32X_I3C_ENABLE_T_25ms:
+ *val = LSM6DSO32X_I3C_ENABLE_T_25ms;
+ break;
+
+ default:
+ *val = LSM6DSO32X_I3C_DISABLE;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LSM6DSO32X_interrupt_pins
+ * @brief This section groups all the functions that manage interrupt pins
+ * @{
+ *
+ */
+
+/**
+ * @brief Push-pull/open drain selection on interrupt pads.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of pp_od in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_pin_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_pp_od_t val)
+{
+ lsm6dso32x_i3c_bus_avb_t i3c_bus_avb;
+ lsm6dso32x_ctrl3_c_t ctrl3_c;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.pp_od = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
+ (uint8_t *)&i3c_bus_avb, 1);
+ }
+
+ if (ret == 0)
+ {
+ i3c_bus_avb.pd_dis_int1 = ((uint8_t) val & 0x02U) >> 1;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
+ (uint8_t *)&i3c_bus_avb, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Push-pull/open drain selection on interrupt pads.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of pp_od in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_pin_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_pp_od_t *val)
+{
+ lsm6dso32x_i3c_bus_avb_t i3c_bus_avb;
+ lsm6dso32x_ctrl3_c_t ctrl3_c;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
+ (uint8_t *)&i3c_bus_avb, 1);
+ }
+
+ switch ((i3c_bus_avb.pd_dis_int1 << 1) + ctrl3_c.pp_od)
+ {
+ case LSM6DSO32X_PUSH_PULL:
+ *val = LSM6DSO32X_PUSH_PULL;
+ break;
+
+ case LSM6DSO32X_OPEN_DRAIN:
+ *val = LSM6DSO32X_OPEN_DRAIN;
+ break;
+
+ case LSM6DSO32X_INT1_NOPULL_DOWN_INT2_PUSH_PULL:
+ *val = LSM6DSO32X_INT1_NOPULL_DOWN_INT2_PUSH_PULL;
+ break;
+
+ case LSM6DSO32X_INT1_NOPULL_DOWN_INT2_OPEN_DRAIN:
+ *val = LSM6DSO32X_INT1_NOPULL_DOWN_INT2_OPEN_DRAIN;
+ break;
+
+ default:
+ *val = LSM6DSO32X_PUSH_PULL;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Interrupt active-high/low.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of h_lactive in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_pin_polarity_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_h_lactive_t val)
+{
+ lsm6dso32x_ctrl3_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.h_lactive = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Interrupt active-high/low.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of h_lactive in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_pin_polarity_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_h_lactive_t *val)
+{
+ lsm6dso32x_ctrl3_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
+
+ switch (reg.h_lactive)
+ {
+ case LSM6DSO32X_ACTIVE_HIGH:
+ *val = LSM6DSO32X_ACTIVE_HIGH;
+ break;
+
+ case LSM6DSO32X_ACTIVE_LOW:
+ *val = LSM6DSO32X_ACTIVE_LOW;
+ break;
+
+ default:
+ *val = LSM6DSO32X_ACTIVE_HIGH;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief All interrupt signals become available on INT1 pin.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of int2_on_int1 in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lsm6dso32x_ctrl4_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.int2_on_int1 = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief All interrupt signals become available on INT1 pin.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of int2_on_int1 in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lsm6dso32x_ctrl4_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
+ *val = reg.int2_on_int1;
+
+ return ret;
+}
+
+/**
+ * @brief Interrupt notification mode.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of lir in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_int_notification_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_lir_t val)
+{
+ lsm6dso32x_tap_cfg0_t tap_cfg0;
+ lsm6dso32x_page_rw_t page_rw;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0,
+ (uint8_t *) &tap_cfg0, 1);
+
+ if (ret == 0)
+ {
+ tap_cfg0.lir = (uint8_t)val & 0x01U;
+ tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG0,
+ (uint8_t *) &tap_cfg0, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
+ (uint8_t *) &page_rw, 1);
+ }
+
+ if (ret == 0)
+ {
+ page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW,
+ (uint8_t *) &page_rw, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Interrupt notification mode.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of lir in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_int_notification_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_lir_t *val)
+{
+ lsm6dso32x_tap_cfg0_t tap_cfg0;
+ lsm6dso32x_page_rw_t page_rw;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0,
+ (uint8_t *) &tap_cfg0, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
+ (uint8_t *) &page_rw, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ if (ret == 0)
+ {
+ switch ((page_rw.emb_func_lir << 1) | tap_cfg0.lir)
+ {
+ case LSM6DSO32X_ALL_INT_PULSED:
+ *val = LSM6DSO32X_ALL_INT_PULSED;
+ break;
+
+ case LSM6DSO32X_BASE_LATCHED_EMB_PULSED:
+ *val = LSM6DSO32X_BASE_LATCHED_EMB_PULSED;
+ break;
+
+ case LSM6DSO32X_BASE_PULSED_EMB_LATCHED:
+ *val = LSM6DSO32X_BASE_PULSED_EMB_LATCHED;
+ break;
+
+ case LSM6DSO32X_ALL_INT_LATCHED:
+ *val = LSM6DSO32X_ALL_INT_LATCHED;
+ break;
+
+ default:
+ *val = LSM6DSO32X_ALL_INT_PULSED;
+ break;
+ }
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
+ (uint8_t *) &page_rw, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LSM6DSO32X_Wake_Up_event
+ * @brief This section groups all the functions that manage the Wake Up
+ * event generation.
+ * @{
+ *
+ */
+
+/**
+ * @brief Weight of 1 LSB of wakeup threshold.[set]
+ * 0: 1 LSB =FS_XL / 64
+ * 1: 1 LSB = FS_XL / 256
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of wake_ths_w in
+ * reg WAKE_UP_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_wkup_ths_weight_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_wake_ths_w_t val)
+{
+ lsm6dso32x_wake_up_dur_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
+ (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.wake_ths_w = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
+ (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Weight of 1 LSB of wakeup threshold.[get]
+ * 0: 1 LSB =FS_XL / 64
+ * 1: 1 LSB = FS_XL / 256
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of wake_ths_w in
+ * reg WAKE_UP_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_wkup_ths_weight_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_wake_ths_w_t *val)
+{
+ lsm6dso32x_wake_up_dur_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
+ (uint8_t *)®, 1);
+
+ switch (reg.wake_ths_w)
+ {
+ case LSM6DSO32X_LSb_FS_DIV_64:
+ *val = LSM6DSO32X_LSb_FS_DIV_64;
+ break;
+
+ case LSM6DSO32X_LSb_FS_DIV_256:
+ *val = LSM6DSO32X_LSb_FS_DIV_256;
+ break;
+
+ default:
+ *val = LSM6DSO32X_LSb_FS_DIV_64;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
+ * WAKE_UP_DUR.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of wk_ths in reg WAKE_UP_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lsm6dso32x_wake_up_ths_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_THS,
+ (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.wk_ths = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_WAKE_UP_THS,
+ (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
+ * WAKE_UP_DUR.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of wk_ths in reg WAKE_UP_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lsm6dso32x_wake_up_ths_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_THS,
+ (uint8_t *)®, 1);
+ *val = reg.wk_ths;
+
+ return ret;
+}
+
+/**
+ * @brief Wake up duration event.[set]
+ * 1LSb = 1 / ODR
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of usr_off_on_wu in reg WAKE_UP_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx,
+ uint8_t val)
+{
+ lsm6dso32x_wake_up_ths_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_THS,
+ (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.usr_off_on_wu = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_WAKE_UP_THS,
+ (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Wake up duration event.[get]
+ * 1LSb = 1 / ODR
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of usr_off_on_wu in reg WAKE_UP_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lsm6dso32x_wake_up_ths_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_THS,
+ (uint8_t *)®, 1);
+ *val = reg.usr_off_on_wu;
+
+ return ret;
+}
+
+/**
+ * @brief Wake up duration event.[set]
+ * 1LSb = 1 / ODR
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of wake_dur in reg WAKE_UP_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lsm6dso32x_wake_up_dur_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
+ (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.wake_dur = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
+ (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Wake up duration event.[get]
+ * 1LSb = 1 / ODR
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of wake_dur in reg WAKE_UP_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lsm6dso32x_wake_up_dur_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
+ (uint8_t *)®, 1);
+ *val = reg.wake_dur;
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LSM6DSO32X_ Activity/Inactivity_detection
+ * @brief This section groups all the functions concerning
+ * activity/inactivity detection.
+ * @{
+ *
+ */
+
+/**
+ * @brief Enables gyroscope Sleep mode.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of sleep_g in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lsm6dso32x_ctrl4_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.sleep_g = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enables gyroscope Sleep mode.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of sleep_g in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lsm6dso32x_ctrl4_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
+ *val = reg.sleep_g;
+
+ return ret;
+}
+
+/**
+ * @brief Drives the sleep status instead of
+ * sleep change on INT pins
+ * (only if INT1_SLEEP_CHANGE or
+ * INT2_SLEEP_CHANGE bits are enabled).[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of sleep_status_on_int in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_act_pin_notification_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_sleep_status_on_int_t val)
+{
+ lsm6dso32x_tap_cfg0_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.sleep_status_on_int = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Drives the sleep status instead of
+ * sleep change on INT pins (only if
+ * INT1_SLEEP_CHANGE or
+ * INT2_SLEEP_CHANGE bits are enabled).[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of sleep_status_on_int in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_act_pin_notification_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_sleep_status_on_int_t *val)
+{
+ lsm6dso32x_tap_cfg0_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
+
+ switch (reg.sleep_status_on_int)
+ {
+ case LSM6DSO32X_DRIVE_SLEEP_CHG_EVENT:
+ *val = LSM6DSO32X_DRIVE_SLEEP_CHG_EVENT;
+ break;
+
+ case LSM6DSO32X_DRIVE_SLEEP_STATUS:
+ *val = LSM6DSO32X_DRIVE_SLEEP_STATUS;
+ break;
+
+ default:
+ *val = LSM6DSO32X_DRIVE_SLEEP_CHG_EVENT;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable inactivity function.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of inact_en in reg TAP_CFG2
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_act_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_inact_en_t val)
+{
+ lsm6dso32x_tap_cfg2_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.inact_en = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG2, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable inactivity function.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of inact_en in reg TAP_CFG2
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_act_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_inact_en_t *val)
+{
+ lsm6dso32x_tap_cfg2_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG2, (uint8_t *)®, 1);
+
+ switch (reg.inact_en)
+ {
+ case LSM6DSO32X_XL_AND_GY_NOT_AFFECTED:
+ *val = LSM6DSO32X_XL_AND_GY_NOT_AFFECTED;
+ break;
+
+ case LSM6DSO32X_XL_12Hz5_GY_NOT_AFFECTED:
+ *val = LSM6DSO32X_XL_12Hz5_GY_NOT_AFFECTED;
+ break;
+
+ case LSM6DSO32X_XL_12Hz5_GY_SLEEP:
+ *val = LSM6DSO32X_XL_12Hz5_GY_SLEEP;
+ break;
+
+ case LSM6DSO32X_XL_12Hz5_GY_PD:
+ *val = LSM6DSO32X_XL_12Hz5_GY_PD;
+ break;
+
+ default:
+ *val = LSM6DSO32X_XL_AND_GY_NOT_AFFECTED;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Duration to go in sleep mode.[set]
+ * 1 LSb = 512 / ODR
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of sleep_dur in reg WAKE_UP_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lsm6dso32x_wake_up_dur_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
+ (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.sleep_dur = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
+ (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Duration to go in sleep mode.[get]
+ * 1 LSb = 512 / ODR
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of sleep_dur in reg WAKE_UP_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lsm6dso32x_wake_up_dur_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
+ (uint8_t *)®, 1);
+ *val = reg.sleep_dur;
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LSM6DSO32X_tap_generator
+ * @brief This section groups all the functions that manage the
+ * tap and double tap event generation.
+ * @{
+ *
+ */
+
+/**
+ * @brief Enable Z direction in tap recognition.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of tap_z_en in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_tap_detection_on_z_set(stmdev_ctx_t *ctx,
+ uint8_t val)
+{
+ lsm6dso32x_tap_cfg0_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.tap_z_en = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable Z direction in tap recognition.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of tap_z_en in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lsm6dso32x_tap_cfg0_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
+ *val = reg.tap_z_en;
+
+ return ret;
+}
+
+/**
+ * @brief Enable Y direction in tap recognition.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of tap_y_en in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+ uint8_t val)
+{
+ lsm6dso32x_tap_cfg0_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.tap_y_en = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable Y direction in tap recognition.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of tap_y_en in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lsm6dso32x_tap_cfg0_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
+ *val = reg.tap_y_en;
+
+ return ret;
+}
+
+/**
+ * @brief Enable X direction in tap recognition.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of tap_x_en in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val)
+{
+ lsm6dso32x_tap_cfg0_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.tap_x_en = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable X direction in tap recognition.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of tap_x_en in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lsm6dso32x_tap_cfg0_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
+ *val = reg.tap_x_en;
+
+ return ret;
+}
+
+/**
+ * @brief X-axis tap recognition threshold.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of tap_ths_x in reg TAP_CFG1
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lsm6dso32x_tap_cfg1_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG1, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.tap_ths_x = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG1, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief X-axis tap recognition threshold.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of tap_ths_x in reg TAP_CFG1
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_tap_threshold_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lsm6dso32x_tap_cfg1_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG1, (uint8_t *)®, 1);
+ *val = reg.tap_ths_x;
+
+ return ret;
+}
+
+/**
+ * @brief Selection of axis priority for TAP detection.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of tap_priority in
+ * reg TAP_CFG1
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_tap_axis_priority_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_tap_priority_t val)
+{
+ lsm6dso32x_tap_cfg1_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG1, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.tap_priority = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG1, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Selection of axis priority for TAP detection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of tap_priority in
+ * reg TAP_CFG1
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_tap_axis_priority_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_tap_priority_t *val)
+{
+ lsm6dso32x_tap_cfg1_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG1, (uint8_t *)®, 1);
+
+ switch (reg.tap_priority)
+ {
+ case LSM6DSO32X_XYZ:
+ *val = LSM6DSO32X_XYZ;
+ break;
+
+ case LSM6DSO32X_YXZ:
+ *val = LSM6DSO32X_YXZ;
+ break;
+
+ case LSM6DSO32X_XZY:
+ *val = LSM6DSO32X_XZY;
+ break;
+
+ case LSM6DSO32X_ZYX:
+ *val = LSM6DSO32X_ZYX;
+ break;
+
+ case LSM6DSO32X_YZX:
+ *val = LSM6DSO32X_YZX;
+ break;
+
+ case LSM6DSO32X_ZXY:
+ *val = LSM6DSO32X_ZXY;
+ break;
+
+ default:
+ *val = LSM6DSO32X_XYZ;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Y-axis tap recognition threshold.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of tap_ths_y in reg TAP_CFG2
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lsm6dso32x_tap_cfg2_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.tap_ths_y = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG2, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Y-axis tap recognition threshold.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of tap_ths_y in reg TAP_CFG2
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_tap_threshold_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lsm6dso32x_tap_cfg2_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG2, (uint8_t *)®, 1);
+ *val = reg.tap_ths_y;
+
+ return ret;
+}
+
+/**
+ * @brief Z-axis recognition threshold.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of tap_ths_z in reg TAP_THS_6D
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lsm6dso32x_tap_ths_6d_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_THS_6D, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.tap_ths_z = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_THS_6D,
+ (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Z-axis recognition threshold.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of tap_ths_z in reg TAP_THS_6D
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_tap_threshold_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lsm6dso32x_tap_ths_6d_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_THS_6D, (uint8_t *)®, 1);
+ *val = reg.tap_ths_z;
+
+ return ret;
+}
+
+/**
+ * @brief Maximum duration is the maximum time of an
+ * over threshold signal detection to be recognized
+ * as a tap event. The default value of these bits
+ * is 00b which corresponds to 4*ODR_XL time.
+ * If the SHOCK[1:0] bits are set to a different
+ * value, 1LSB corresponds to 8*ODR_XL time.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of shock in reg INT_DUR2
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lsm6dso32x_int_dur2_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT_DUR2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.shock = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_INT_DUR2, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Maximum duration is the maximum time of an
+ * over threshold signal detection to be recognized
+ * as a tap event. The default value of these bits
+ * is 00b which corresponds to 4*ODR_XL time.
+ * If the SHOCK[1:0] bits are set to a different
+ * value, 1LSB corresponds to 8*ODR_XL time.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of shock in reg INT_DUR2
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lsm6dso32x_int_dur2_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT_DUR2, (uint8_t *)®, 1);
+ *val = reg.shock;
+
+ return ret;
+}
+
+/**
+ * @brief Quiet time is the time after the first detected
+ * tap in which there must not be any over threshold
+ * event.
+ * The default value of these bits is 00b which
+ * corresponds to 2*ODR_XL time. If the QUIET[1:0]
+ * bits are set to a different value,
+ * 1LSB corresponds to 4*ODR_XL time.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of quiet in reg INT_DUR2
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lsm6dso32x_int_dur2_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT_DUR2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.quiet = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_INT_DUR2, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Quiet time is the time after the first detected
+ * tap in which there must not be any over threshold
+ * event.
+ * The default value of these bits is 00b which
+ * corresponds to 2*ODR_XL time.
+ * If the QUIET[1:0] bits are set to a different
+ * value, 1LSB corresponds to 4*ODR_XL time.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of quiet in reg INT_DUR2
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lsm6dso32x_int_dur2_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT_DUR2, (uint8_t *)®, 1);
+ *val = reg.quiet;
+
+ return ret;
+}
+
+/**
+ * @brief When double tap recognition is enabled,
+ * this register expresses the maximum time
+ * between two consecutive detected taps to
+ * determine a double tap event.
+ * The default value of these bits is 0000b which
+ * corresponds to 16*ODR_XL time.
+ * If the DUR[3:0] bits are set to a different value,
+ * 1LSB corresponds to 32*ODR_XL time.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of dur in reg INT_DUR2
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lsm6dso32x_int_dur2_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT_DUR2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.dur = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_INT_DUR2, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief When double tap recognition is enabled,
+ * this register expresses the maximum time
+ * between two consecutive detected taps to
+ * determine a double tap event.
+ * The default value of these bits is 0000b which
+ * corresponds to 16*ODR_XL time. If the DUR[3:0]
+ * bits are set to a different value,
+ * 1LSB corresponds to 32*ODR_XL time.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of dur in reg INT_DUR2
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lsm6dso32x_int_dur2_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT_DUR2, (uint8_t *)®, 1);
+ *val = reg.dur;
+
+ return ret;
+}
+
+/**
+ * @brief Single/double-tap event enable.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of single_double_tap in reg WAKE_UP_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_tap_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_single_double_tap_t val)
+{
+ lsm6dso32x_wake_up_ths_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_THS,
+ (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.single_double_tap = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_WAKE_UP_THS,
+ (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Single/double-tap event enable.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of single_double_tap in reg WAKE_UP_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_tap_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_single_double_tap_t *val)
+{
+ lsm6dso32x_wake_up_ths_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_THS,
+ (uint8_t *)®, 1);
+
+ switch (reg.single_double_tap)
+ {
+ case LSM6DSO32X_ONLY_SINGLE:
+ *val = LSM6DSO32X_ONLY_SINGLE;
+ break;
+
+ case LSM6DSO32X_BOTH_SINGLE_DOUBLE:
+ *val = LSM6DSO32X_BOTH_SINGLE_DOUBLE;
+ break;
+
+ default:
+ *val = LSM6DSO32X_ONLY_SINGLE;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LSM6DSO32X_ Six_position_detection(6D/4D)
+ * @brief This section groups all the functions concerning six position
+ * detection (6D).
+ * @{
+ *
+ */
+
+/**
+ * @brief Threshold for 4D/6D function.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of sixd_ths in reg TAP_THS_6D
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_6d_threshold_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_sixd_ths_t val)
+{
+ lsm6dso32x_tap_ths_6d_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_THS_6D, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.sixd_ths = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_THS_6D,
+ (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Threshold for 4D/6D function.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of sixd_ths in reg TAP_THS_6D
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_6d_threshold_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_sixd_ths_t *val)
+{
+ lsm6dso32x_tap_ths_6d_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_THS_6D, (uint8_t *)®, 1);
+
+ switch (reg.sixd_ths)
+ {
+ case LSM6DSO32X_DEG_80:
+ *val = LSM6DSO32X_DEG_80;
+ break;
+
+ case LSM6DSO32X_DEG_70:
+ *val = LSM6DSO32X_DEG_70;
+ break;
+
+ case LSM6DSO32X_DEG_60:
+ *val = LSM6DSO32X_DEG_60;
+ break;
+
+ case LSM6DSO32X_DEG_50:
+ *val = LSM6DSO32X_DEG_50;
+ break;
+
+ default:
+ *val = LSM6DSO32X_DEG_80;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief 4D orientation detection enable.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of d4d_en in reg TAP_THS_6D
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lsm6dso32x_tap_ths_6d_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_THS_6D, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.d4d_en = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_THS_6D,
+ (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief 4D orientation detection enable.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of d4d_en in reg TAP_THS_6D
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lsm6dso32x_tap_ths_6d_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_THS_6D, (uint8_t *)®, 1);
+ *val = reg.d4d_en;
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LSM6DSO32X_free_fall
+ * @brief This section group all the functions concerning the free
+ * fall detection.
+ * @{
+ *
+ */
+/**
+ * @brief Free fall threshold setting.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of ff_ths in reg FREE_FALL
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_ff_threshold_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_ff_ths_t val)
+{
+ lsm6dso32x_free_fall_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FREE_FALL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.ff_ths = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FREE_FALL, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Free fall threshold setting.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of ff_ths in reg FREE_FALL
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_ff_threshold_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_ff_ths_t *val)
+{
+ lsm6dso32x_free_fall_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FREE_FALL, (uint8_t *)®, 1);
+
+ switch (reg.ff_ths)
+ {
+ case LSM6DSO32X_FF_TSH_312mg:
+ *val = LSM6DSO32X_FF_TSH_312mg;
+ break;
+
+ case LSM6DSO32X_FF_TSH_438mg:
+ *val = LSM6DSO32X_FF_TSH_438mg;
+ break;
+
+ case LSM6DSO32X_FF_TSH_500mg:
+ *val = LSM6DSO32X_FF_TSH_500mg;
+ break;
+
+ default:
+ *val = LSM6DSO32X_FF_TSH_312mg;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Free-fall duration event.[set]
+ * 1LSb = 1 / ODR
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of ff_dur in reg FREE_FALL
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lsm6dso32x_wake_up_dur_t wake_up_dur;
+ lsm6dso32x_free_fall_t free_fall;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FREE_FALL,
+ (uint8_t *)&free_fall, 1);
+ }
+
+ if (ret == 0)
+ {
+ wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5;
+ free_fall.ff_dur = (uint8_t)val & 0x1FU;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FREE_FALL,
+ (uint8_t *)&free_fall, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Free-fall duration event.[get]
+ * 1LSb = 1 / ODR
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of ff_dur in reg FREE_FALL
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lsm6dso32x_wake_up_dur_t wake_up_dur;
+ lsm6dso32x_free_fall_t free_fall;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FREE_FALL,
+ (uint8_t *)&free_fall, 1);
+ *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
+ }
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LSM6DSO32X_fifo
+ * @brief This section group all the functions concerning the fifo usage
+ * @{
+ *
+ */
+
+/**
+ * @brief FIFO watermark level selection.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of wtm in reg FIFO_CTRL1
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
+{
+ lsm6dso32x_fifo_ctrl1_t fifo_ctrl1;
+ lsm6dso32x_fifo_ctrl2_t fifo_ctrl2;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl1.wtm = 0x00FFU & (uint8_t)val;
+ fifo_ctrl2.wtm = (uint8_t)((0x0100U & val) >> 8);
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL1,
+ (uint8_t *)&fifo_ctrl1, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief FIFO watermark level selection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of wtm in reg FIFO_CTRL1
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fifo_watermark_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
+{
+ lsm6dso32x_fifo_ctrl1_t fifo_ctrl1;
+ lsm6dso32x_fifo_ctrl2_t fifo_ctrl2;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL1,
+ (uint8_t *)&fifo_ctrl1, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
+ *val = ((uint16_t)fifo_ctrl2.wtm << 8) + (uint16_t)fifo_ctrl1.wtm;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief FIFO compression feature initialization request [set].
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of FIFO_COMPR_INIT in
+ * reg EMB_FUNC_INIT_B
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_compression_algo_init_set(stmdev_ctx_t *ctx,
+ uint8_t val)
+{
+ lsm6dso32x_emb_func_init_b_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_INIT_B,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ reg.fifo_compr_init = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_INIT_B,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief FIFO compression feature initialization request [get].
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of FIFO_COMPR_INIT in
+ * reg EMB_FUNC_INIT_B
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_compression_algo_init_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lsm6dso32x_emb_func_init_b_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_INIT_B,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ *val = reg.fifo_compr_init;
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable and configure compression algo.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of uncoptr_rate in
+ * reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_compression_algo_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_uncoptr_rate_t val)
+{
+ lsm6dso32x_fifo_ctrl2_t fifo_ctrl2;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl2.fifo_compr_rt_en = ((uint8_t)val & 0x04U) >> 2;
+ fifo_ctrl2.uncoptr_rate = (uint8_t)val & 0x03U;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable and configure compression algo.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of uncoptr_rate in
+ * reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_compression_algo_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_uncoptr_rate_t *val)
+{
+ lsm6dso32x_fifo_ctrl2_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2, (uint8_t *)®, 1);
+
+ switch ((reg.fifo_compr_rt_en << 2) | reg.uncoptr_rate)
+ {
+ case LSM6DSO32X_CMP_DISABLE:
+ *val = LSM6DSO32X_CMP_DISABLE;
+ break;
+
+ case LSM6DSO32X_CMP_ALWAYS:
+ *val = LSM6DSO32X_CMP_ALWAYS;
+ break;
+
+ case LSM6DSO32X_CMP_8_TO_1:
+ *val = LSM6DSO32X_CMP_8_TO_1;
+ break;
+
+ case LSM6DSO32X_CMP_16_TO_1:
+ *val = LSM6DSO32X_CMP_16_TO_1;
+ break;
+
+ case LSM6DSO32X_CMP_32_TO_1:
+ *val = LSM6DSO32X_CMP_32_TO_1;
+ break;
+
+ default:
+ *val = LSM6DSO32X_CMP_DISABLE;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of odrchg_en in reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
+ uint8_t val)
+{
+ lsm6dso32x_fifo_ctrl2_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.odrchg_en = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL2,
+ (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of odrchg_en in reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lsm6dso32x_fifo_ctrl2_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2, (uint8_t *)®, 1);
+ *val = reg.odrchg_en;
+
+ return ret;
+}
+
+/**
+ * @brief Enables/Disables compression algorithm runtime.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of fifo_compr_rt_en in
+ * reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_compression_algo_real_time_set(stmdev_ctx_t *ctx,
+ uint8_t val)
+{
+ lsm6dso32x_fifo_ctrl2_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.fifo_compr_rt_en = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL2,
+ (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enables/Disables compression algorithm runtime. [get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of fifo_compr_rt_en in reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_compression_algo_real_time_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lsm6dso32x_fifo_ctrl2_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2, (uint8_t *)®, 1);
+ *val = reg.fifo_compr_rt_en;
+
+ return ret;
+}
+
+/**
+ * @brief Sensing chain FIFO stop values memorization at
+ * threshold level.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of stop_on_wtm in reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx,
+ uint8_t val)
+{
+ lsm6dso32x_fifo_ctrl2_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.stop_on_wtm = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL2,
+ (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Sensing chain FIFO stop values memorization at
+ * threshold level.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of stop_on_wtm in reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lsm6dso32x_fifo_ctrl2_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2, (uint8_t *)®, 1);
+ *val = reg.stop_on_wtm;
+
+ return ret;
+}
+
+/**
+ * @brief Selects Batching Data Rate (writing frequency in FIFO)
+ * for accelerometer data.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of bdr_xl in reg FIFO_CTRL3
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fifo_xl_batch_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_bdr_xl_t val)
+{
+ lsm6dso32x_fifo_ctrl3_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL3, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.bdr_xl = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL3,
+ (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Selects Batching Data Rate (writing frequency in FIFO)
+ * for accelerometer data.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of bdr_xl in reg FIFO_CTRL3
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fifo_xl_batch_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_bdr_xl_t *val)
+{
+ lsm6dso32x_fifo_ctrl3_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL3, (uint8_t *)®, 1);
+
+ switch (reg.bdr_xl)
+ {
+ case LSM6DSO32X_XL_NOT_BATCHED:
+ *val = LSM6DSO32X_XL_NOT_BATCHED;
+ break;
+
+ case LSM6DSO32X_XL_BATCHED_AT_12Hz5:
+ *val = LSM6DSO32X_XL_BATCHED_AT_12Hz5;
+ break;
+
+ case LSM6DSO32X_XL_BATCHED_AT_26Hz:
+ *val = LSM6DSO32X_XL_BATCHED_AT_26Hz;
+ break;
+
+ case LSM6DSO32X_XL_BATCHED_AT_52Hz:
+ *val = LSM6DSO32X_XL_BATCHED_AT_52Hz;
+ break;
+
+ case LSM6DSO32X_XL_BATCHED_AT_104Hz:
+ *val = LSM6DSO32X_XL_BATCHED_AT_104Hz;
+ break;
+
+ case LSM6DSO32X_XL_BATCHED_AT_208Hz:
+ *val = LSM6DSO32X_XL_BATCHED_AT_208Hz;
+ break;
+
+ case LSM6DSO32X_XL_BATCHED_AT_417Hz:
+ *val = LSM6DSO32X_XL_BATCHED_AT_417Hz;
+ break;
+
+ case LSM6DSO32X_XL_BATCHED_AT_833Hz:
+ *val = LSM6DSO32X_XL_BATCHED_AT_833Hz;
+ break;
+
+ case LSM6DSO32X_XL_BATCHED_AT_1667Hz:
+ *val = LSM6DSO32X_XL_BATCHED_AT_1667Hz;
+ break;
+
+ case LSM6DSO32X_XL_BATCHED_AT_3333Hz:
+ *val = LSM6DSO32X_XL_BATCHED_AT_3333Hz;
+ break;
+
+ case LSM6DSO32X_XL_BATCHED_AT_6667Hz:
+ *val = LSM6DSO32X_XL_BATCHED_AT_6667Hz;
+ break;
+
+ case LSM6DSO32X_XL_BATCHED_AT_6Hz5:
+ *val = LSM6DSO32X_XL_BATCHED_AT_6Hz5;
+ break;
+
+ default:
+ *val = LSM6DSO32X_XL_NOT_BATCHED;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Selects Batching Data Rate (writing frequency in FIFO)
+ * for gyroscope data.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of bdr_gy in reg FIFO_CTRL3
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fifo_gy_batch_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_bdr_gy_t val)
+{
+ lsm6dso32x_fifo_ctrl3_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL3, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.bdr_gy = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL3,
+ (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Selects Batching Data Rate (writing frequency in FIFO)
+ * for gyroscope data.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of bdr_gy in reg FIFO_CTRL3
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fifo_gy_batch_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_bdr_gy_t *val)
+{
+ lsm6dso32x_fifo_ctrl3_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL3, (uint8_t *)®, 1);
+
+ switch (reg.bdr_gy)
+ {
+ case LSM6DSO32X_GY_NOT_BATCHED:
+ *val = LSM6DSO32X_GY_NOT_BATCHED;
+ break;
+
+ case LSM6DSO32X_GY_BATCHED_AT_12Hz5:
+ *val = LSM6DSO32X_GY_BATCHED_AT_12Hz5;
+ break;
+
+ case LSM6DSO32X_GY_BATCHED_AT_26Hz:
+ *val = LSM6DSO32X_GY_BATCHED_AT_26Hz;
+ break;
+
+ case LSM6DSO32X_GY_BATCHED_AT_52Hz:
+ *val = LSM6DSO32X_GY_BATCHED_AT_52Hz;
+ break;
+
+ case LSM6DSO32X_GY_BATCHED_AT_104Hz:
+ *val = LSM6DSO32X_GY_BATCHED_AT_104Hz;
+ break;
+
+ case LSM6DSO32X_GY_BATCHED_AT_208Hz:
+ *val = LSM6DSO32X_GY_BATCHED_AT_208Hz;
+ break;
+
+ case LSM6DSO32X_GY_BATCHED_AT_417Hz:
+ *val = LSM6DSO32X_GY_BATCHED_AT_417Hz;
+ break;
+
+ case LSM6DSO32X_GY_BATCHED_AT_833Hz:
+ *val = LSM6DSO32X_GY_BATCHED_AT_833Hz;
+ break;
+
+ case LSM6DSO32X_GY_BATCHED_AT_1667Hz:
+ *val = LSM6DSO32X_GY_BATCHED_AT_1667Hz;
+ break;
+
+ case LSM6DSO32X_GY_BATCHED_AT_3333Hz:
+ *val = LSM6DSO32X_GY_BATCHED_AT_3333Hz;
+ break;
+
+ case LSM6DSO32X_GY_BATCHED_AT_6667Hz:
+ *val = LSM6DSO32X_GY_BATCHED_AT_6667Hz;
+ break;
+
+ case LSM6DSO32X_GY_BATCHED_AT_6Hz5:
+ *val = LSM6DSO32X_GY_BATCHED_AT_6Hz5;
+ break;
+
+ default:
+ *val = LSM6DSO32X_GY_NOT_BATCHED;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief FIFO mode selection.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of fifo_mode in reg FIFO_CTRL4
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fifo_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_fifo_mode_t val)
+{
+ lsm6dso32x_fifo_ctrl4_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL4, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.fifo_mode = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL4,
+ (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief FIFO mode selection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of fifo_mode in reg FIFO_CTRL4
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fifo_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_fifo_mode_t *val)
+{
+ lsm6dso32x_fifo_ctrl4_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL4, (uint8_t *)®, 1);
+
+ switch (reg.fifo_mode)
+ {
+ case LSM6DSO32X_BYPASS_MODE:
+ *val = LSM6DSO32X_BYPASS_MODE;
+ break;
+
+ case LSM6DSO32X_FIFO_MODE:
+ *val = LSM6DSO32X_FIFO_MODE;
+ break;
+
+ case LSM6DSO32X_STREAM_TO_FIFO_MODE:
+ *val = LSM6DSO32X_STREAM_TO_FIFO_MODE;
+ break;
+
+ case LSM6DSO32X_BYPASS_TO_STREAM_MODE:
+ *val = LSM6DSO32X_BYPASS_TO_STREAM_MODE;
+ break;
+
+ case LSM6DSO32X_STREAM_MODE:
+ *val = LSM6DSO32X_STREAM_MODE;
+ break;
+
+ case LSM6DSO32X_BYPASS_TO_FIFO_MODE:
+ *val = LSM6DSO32X_BYPASS_TO_FIFO_MODE;
+ break;
+
+ default:
+ *val = LSM6DSO32X_BYPASS_MODE;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Selects Batching Data Rate (writing frequency in FIFO)
+ * for temperature data.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of odr_t_batch in reg FIFO_CTRL4
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fifo_temp_batch_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_odr_t_batch_t val)
+{
+ lsm6dso32x_fifo_ctrl4_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL4, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.odr_t_batch = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL4,
+ (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Selects Batching Data Rate (writing frequency in FIFO)
+ * for temperature data.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of odr_t_batch in reg FIFO_CTRL4
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fifo_temp_batch_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_odr_t_batch_t *val)
+{
+ lsm6dso32x_fifo_ctrl4_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL4, (uint8_t *)®, 1);
+
+ switch (reg.odr_t_batch)
+ {
+ case LSM6DSO32X_TEMP_NOT_BATCHED:
+ *val = LSM6DSO32X_TEMP_NOT_BATCHED;
+ break;
+
+ case LSM6DSO32X_TEMP_BATCHED_AT_1Hz6:
+ *val = LSM6DSO32X_TEMP_BATCHED_AT_1Hz6;
+ break;
+
+ case LSM6DSO32X_TEMP_BATCHED_AT_12Hz5:
+ *val = LSM6DSO32X_TEMP_BATCHED_AT_12Hz5;
+ break;
+
+ case LSM6DSO32X_TEMP_BATCHED_AT_52Hz:
+ *val = LSM6DSO32X_TEMP_BATCHED_AT_52Hz;
+ break;
+
+ default:
+ *val = LSM6DSO32X_TEMP_NOT_BATCHED;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Selects decimation for timestamp batching in FIFO.
+ * Writing rate will be the maximum rate between XL and
+ * GYRO BDR divided by decimation decoder.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of odr_ts_batch in reg FIFO_CTRL4
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_odr_ts_batch_t val)
+{
+ lsm6dso32x_fifo_ctrl4_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL4, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.odr_ts_batch = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL4,
+ (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Selects decimation for timestamp batching in FIFO.
+ * Writing rate will be the maximum rate between XL and
+ * GYRO BDR divided by decimation decoder.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of odr_ts_batch in reg FIFO_CTRL4
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_odr_ts_batch_t *val)
+{
+ lsm6dso32x_fifo_ctrl4_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL4, (uint8_t *)®, 1);
+
+ switch (reg.odr_ts_batch)
+ {
+ case LSM6DSO32X_NO_DECIMATION:
+ *val = LSM6DSO32X_NO_DECIMATION;
+ break;
+
+ case LSM6DSO32X_DEC_1:
+ *val = LSM6DSO32X_DEC_1;
+ break;
+
+ case LSM6DSO32X_DEC_8:
+ *val = LSM6DSO32X_DEC_8;
+ break;
+
+ case LSM6DSO32X_DEC_32:
+ *val = LSM6DSO32X_DEC_32;
+ break;
+
+ default:
+ *val = LSM6DSO32X_NO_DECIMATION;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Selects the trigger for the internal counter of batching events
+ * between XL and gyro.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of trig_counter_bdr
+ * in reg COUNTER_BDR_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_trig_counter_bdr_t val)
+{
+ lsm6dso32x_counter_bdr_reg1_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
+ (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.trig_counter_bdr = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
+ (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Selects the trigger for the internal counter of batching events
+ * between XL and gyro.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of trig_counter_bdr
+ * in reg COUNTER_BDR_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_trig_counter_bdr_t *val)
+{
+ lsm6dso32x_counter_bdr_reg1_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
+ (uint8_t *)®, 1);
+
+ switch (reg.trig_counter_bdr)
+ {
+ case LSM6DSO32X_XL_BATCH_EVENT:
+ *val = LSM6DSO32X_XL_BATCH_EVENT;
+ break;
+
+ case LSM6DSO32X_GYRO_BATCH_EVENT:
+ *val = LSM6DSO32X_GYRO_BATCH_EVENT;
+ break;
+
+ default:
+ *val = LSM6DSO32X_XL_BATCH_EVENT;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Resets the internal counter of batching vents for a single sensor.
+ * This bit is automatically reset to zero if it was set to ‘1’.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of rst_counter_bdr in
+ * reg COUNTER_BDR_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_rst_batch_counter_set(stmdev_ctx_t *ctx,
+ uint8_t val)
+{
+ lsm6dso32x_counter_bdr_reg1_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
+ (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.rst_counter_bdr = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
+ (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Resets the internal counter of batching events for a single sensor.
+ * This bit is automatically reset to zero if it was set to ‘1’.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of rst_counter_bdr in
+ * reg COUNTER_BDR_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_rst_batch_counter_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lsm6dso32x_counter_bdr_reg1_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
+ (uint8_t *)®, 1);
+ *val = reg.rst_counter_bdr;
+
+ return ret;
+}
+
+/**
+ * @brief Batch data rate counter.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of cnt_bdr_th in
+ * reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_batch_counter_threshold_set(stmdev_ctx_t *ctx,
+ uint16_t val)
+{
+ lsm6dso32x_counter_bdr_reg1_t counter_bdr_reg1;
+ lsm6dso32x_counter_bdr_reg2_t counter_bdr_reg2;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
+ counter_bdr_reg2.cnt_bdr_th = 0x00FFU & (uint8_t)val;
+ counter_bdr_reg1.cnt_bdr_th = (uint8_t)(0x0700U & val) >> 8;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
+ (uint8_t *)&counter_bdr_reg1, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG2,
+ (uint8_t *)&counter_bdr_reg2, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Batch data rate counter.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of cnt_bdr_th in
+ * reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_batch_counter_threshold_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
+{
+ lsm6dso32x_counter_bdr_reg1_t counter_bdr_reg1;
+ lsm6dso32x_counter_bdr_reg2_t counter_bdr_reg2;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG2,
+ (uint8_t *)&counter_bdr_reg2, 1);
+ *val = ((uint16_t)counter_bdr_reg1.cnt_bdr_th << 8)
+ + (uint16_t)counter_bdr_reg2.cnt_bdr_th;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Number of unread sensor data(TAG + 6 bytes) stored in FIFO.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of diff_fifo in reg FIFO_STATUS1
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fifo_data_level_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
+{
+ lsm6dso32x_fifo_status1_t fifo_status1;
+ lsm6dso32x_fifo_status2_t fifo_status2;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_STATUS1,
+ (uint8_t *)&fifo_status1, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_STATUS2,
+ (uint8_t *)&fifo_status2, 1);
+ *val = ((uint16_t)fifo_status2.diff_fifo << 8) +
+ (uint16_t)fifo_status1.diff_fifo;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief FIFO status.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val registers FIFO_STATUS2
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fifo_status_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_fifo_status2_t *val)
+{
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_STATUS2,
+ (uint8_t *) val, 1);
+
+ return ret;
+}
+
+/**
+ * @brief Smart FIFO full status.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of fifo_full_ia in reg FIFO_STATUS2
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lsm6dso32x_fifo_status2_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_STATUS2,
+ (uint8_t *)®, 1);
+ *val = reg.fifo_full_ia;
+
+ return ret;
+}
+
+/**
+ * @brief FIFO overrun status.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of fifo_over_run_latched in
+ * reg FIFO_STATUS2
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lsm6dso32x_fifo_status2_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_STATUS2,
+ (uint8_t *)®, 1);
+ *val = reg.fifo_ovr_ia;
+
+ return ret;
+}
+
+/**
+ * @brief FIFO watermark status.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of fifo_wtm_ia in reg FIFO_STATUS2
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lsm6dso32x_fifo_status2_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_STATUS2,
+ (uint8_t *)®, 1);
+ *val = reg.fifo_wtm_ia;
+
+ return ret;
+}
+
+/**
+ * @brief Identifies the sensor in FIFO_DATA_OUT.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of tag_sensor in reg FIFO_DATA_OUT_TAG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_fifo_tag_t *val)
+{
+ lsm6dso32x_fifo_data_out_tag_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_DATA_OUT_TAG,
+ (uint8_t *)®, 1);
+
+ switch (reg.tag_sensor)
+ {
+ case LSM6DSO32X_GYRO_NC_TAG:
+ *val = LSM6DSO32X_GYRO_NC_TAG;
+ break;
+
+ case LSM6DSO32X_XL_NC_TAG:
+ *val = LSM6DSO32X_XL_NC_TAG;
+ break;
+
+ case LSM6DSO32X_TEMPERATURE_TAG:
+ *val = LSM6DSO32X_TEMPERATURE_TAG;
+ break;
+
+ case LSM6DSO32X_TIMESTAMP_TAG:
+ *val = LSM6DSO32X_TIMESTAMP_TAG;
+ break;
+
+ case LSM6DSO32X_CFG_CHANGE_TAG:
+ *val = LSM6DSO32X_CFG_CHANGE_TAG;
+ break;
+
+ case LSM6DSO32X_XL_NC_T_2_TAG:
+ *val = LSM6DSO32X_XL_NC_T_2_TAG;
+ break;
+
+ case LSM6DSO32X_XL_NC_T_1_TAG:
+ *val = LSM6DSO32X_XL_NC_T_1_TAG;
+ break;
+
+ case LSM6DSO32X_XL_2XC_TAG:
+ *val = LSM6DSO32X_XL_2XC_TAG;
+ break;
+
+ case LSM6DSO32X_XL_3XC_TAG:
+ *val = LSM6DSO32X_XL_3XC_TAG;
+ break;
+
+ case LSM6DSO32X_GYRO_NC_T_2_TAG:
+ *val = LSM6DSO32X_GYRO_NC_T_2_TAG;
+ break;
+
+ case LSM6DSO32X_GYRO_NC_T_1_TAG:
+ *val = LSM6DSO32X_GYRO_NC_T_1_TAG;
+ break;
+
+ case LSM6DSO32X_GYRO_2XC_TAG:
+ *val = LSM6DSO32X_GYRO_2XC_TAG;
+ break;
+
+ case LSM6DSO32X_GYRO_3XC_TAG:
+ *val = LSM6DSO32X_GYRO_3XC_TAG;
+ break;
+
+ case LSM6DSO32X_SENSORHUB_SLAVE0_TAG:
+ *val = LSM6DSO32X_SENSORHUB_SLAVE0_TAG;
+ break;
+
+ case LSM6DSO32X_SENSORHUB_SLAVE1_TAG:
+ *val = LSM6DSO32X_SENSORHUB_SLAVE1_TAG;
+ break;
+
+ case LSM6DSO32X_SENSORHUB_SLAVE2_TAG:
+ *val = LSM6DSO32X_SENSORHUB_SLAVE2_TAG;
+ break;
+
+ case LSM6DSO32X_SENSORHUB_SLAVE3_TAG:
+ *val = LSM6DSO32X_SENSORHUB_SLAVE3_TAG;
+ break;
+
+ case LSM6DSO32X_STEP_CPUNTER_TAG:
+ *val = LSM6DSO32X_STEP_CPUNTER_TAG;
+ break;
+
+ case LSM6DSO32X_GAME_ROTATION_TAG:
+ *val = LSM6DSO32X_GAME_ROTATION_TAG;
+ break;
+
+ case LSM6DSO32X_GEOMAG_ROTATION_TAG:
+ *val = LSM6DSO32X_GEOMAG_ROTATION_TAG;
+ break;
+
+ case LSM6DSO32X_ROTATION_TAG:
+ *val = LSM6DSO32X_ROTATION_TAG;
+ break;
+
+ case LSM6DSO32X_SENSORHUB_NACK_TAG:
+ *val = LSM6DSO32X_SENSORHUB_NACK_TAG;
+ break;
+
+ default:
+ *val = LSM6DSO32X_GYRO_NC_TAG;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief : Enable FIFO batching of pedometer embedded
+ * function values.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of gbias_fifo_en in
+ * reg LSM6DSO32X_EMB_FUNC_FIFO_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lsm6dso32x_emb_func_fifo_cfg_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_FIFO_CFG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ reg.pedo_fifo_en = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_FIFO_CFG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable FIFO batching of pedometer embedded function values.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of pedo_fifo_en in
+ * reg LSM6DSO32X_EMB_FUNC_FIFO_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fifo_pedo_batch_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lsm6dso32x_emb_func_fifo_cfg_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_FIFO_CFG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ *val = reg.pedo_fifo_en;
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable FIFO batching data of first slave.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of batch_ext_sens_0_en in
+ * reg SLV0_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_batch_slave_0_set(stmdev_ctx_t *ctx,
+ uint8_t val)
+{
+ lsm6dso32x_slv0_config_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV0_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ reg.batch_ext_sens_0_en = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV0_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable FIFO batching data of first slave.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of batch_ext_sens_0_en in
+ * reg SLV0_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_batch_slave_0_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lsm6dso32x_slv0_config_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV0_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ *val = reg.batch_ext_sens_0_en;
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable FIFO batching data of second slave.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of batch_ext_sens_1_en in
+ * reg SLV1_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_batch_slave_1_set(stmdev_ctx_t *ctx,
+ uint8_t val)
+{
+ lsm6dso32x_slv1_config_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV1_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ reg.batch_ext_sens_1_en = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV1_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable FIFO batching data of second slave.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of batch_ext_sens_1_en in
+ * reg SLV1_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_batch_slave_1_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lsm6dso32x_slv1_config_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV1_CONFIG,
+ (uint8_t *)®, 1);
+ *val = reg.batch_ext_sens_1_en;
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable FIFO batching data of third slave.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of batch_ext_sens_2_en in
+ * reg SLV2_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_batch_slave_2_set(stmdev_ctx_t *ctx,
+ uint8_t val)
+{
+ lsm6dso32x_slv2_config_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV2_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ reg.batch_ext_sens_2_en = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV2_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable FIFO batching data of third slave.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of batch_ext_sens_2_en in
+ * reg SLV2_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_batch_slave_2_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lsm6dso32x_slv2_config_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV2_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ *val = reg.batch_ext_sens_2_en;
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable FIFO batching data of fourth slave.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of batch_ext_sens_3_en
+ * in reg SLV3_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_batch_slave_3_set(stmdev_ctx_t *ctx,
+ uint8_t val)
+{
+ lsm6dso32x_slv3_config_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV3_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ reg.batch_ext_sens_3_en = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV3_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable FIFO batching data of fourth slave.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of batch_ext_sens_3_en in
+ * reg SLV3_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_batch_slave_3_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lsm6dso32x_slv3_config_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV3_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ *val = reg.batch_ext_sens_3_en;
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LSM6DSO32X_DEN_functionality
+ * @brief This section groups all the functions concerning
+ * DEN functionality.
+ * @{
+ *
+ */
+
+/**
+ * @brief DEN functionality marking mode.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of den_mode in reg CTRL6_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_den_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_den_mode_t val)
+{
+ lsm6dso32x_ctrl6_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL6_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.den_mode = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL6_C, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief DEN functionality marking mode.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of den_mode in reg CTRL6_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_den_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_den_mode_t *val)
+{
+ lsm6dso32x_ctrl6_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL6_C, (uint8_t *)®, 1);
+
+ switch (reg.den_mode)
+ {
+ case LSM6DSO32X_DEN_DISABLE:
+ *val = LSM6DSO32X_DEN_DISABLE;
+ break;
+
+ case LSM6DSO32X_LEVEL_FIFO:
+ *val = LSM6DSO32X_LEVEL_FIFO;
+ break;
+
+ case LSM6DSO32X_LEVEL_LETCHED:
+ *val = LSM6DSO32X_LEVEL_LETCHED;
+ break;
+
+ case LSM6DSO32X_LEVEL_TRIGGER:
+ *val = LSM6DSO32X_LEVEL_TRIGGER;
+ break;
+
+ case LSM6DSO32X_EDGE_TRIGGER:
+ *val = LSM6DSO32X_EDGE_TRIGGER;
+ break;
+
+ default:
+ *val = LSM6DSO32X_DEN_DISABLE;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief DEN active level configuration.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of den_lh in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_den_polarity_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_den_lh_t val)
+{
+ lsm6dso32x_ctrl9_xl_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.den_lh = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief DEN active level configuration.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of den_lh in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_den_polarity_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_den_lh_t *val)
+{
+ lsm6dso32x_ctrl9_xl_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
+
+ switch (reg.den_lh)
+ {
+ case LSM6DSO32X_DEN_ACT_LOW:
+ *val = LSM6DSO32X_DEN_ACT_LOW;
+ break;
+
+ case LSM6DSO32X_DEN_ACT_HIGH:
+ *val = LSM6DSO32X_DEN_ACT_HIGH;
+ break;
+
+ default:
+ *val = LSM6DSO32X_DEN_ACT_LOW;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief DEN enable.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of den_xl_g in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_den_enable_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_den_xl_g_t val)
+{
+ lsm6dso32x_ctrl9_xl_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.den_xl_g = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief DEN enable.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of den_xl_g in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_den_enable_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_den_xl_g_t *val)
+{
+ lsm6dso32x_ctrl9_xl_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
+
+ switch (reg.den_xl_g)
+ {
+ case LSM6DSO32X_STAMP_IN_GY_DATA:
+ *val = LSM6DSO32X_STAMP_IN_GY_DATA;
+ break;
+
+ case LSM6DSO32X_STAMP_IN_XL_DATA:
+ *val = LSM6DSO32X_STAMP_IN_XL_DATA;
+ break;
+
+ case LSM6DSO32X_STAMP_IN_GY_XL_DATA:
+ *val = LSM6DSO32X_STAMP_IN_GY_XL_DATA;
+ break;
+
+ default:
+ *val = LSM6DSO32X_STAMP_IN_GY_DATA;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief DEN value stored in LSB of X-axis.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of den_z in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lsm6dso32x_ctrl9_xl_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.den_z = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief DEN value stored in LSB of X-axis.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of den_z in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_den_mark_axis_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lsm6dso32x_ctrl9_xl_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
+ *val = reg.den_z;
+
+ return ret;
+}
+
+/**
+ * @brief DEN value stored in LSB of Y-axis.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of den_y in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lsm6dso32x_ctrl9_xl_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.den_y = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief DEN value stored in LSB of Y-axis.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of den_y in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_den_mark_axis_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lsm6dso32x_ctrl9_xl_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
+ *val = reg.den_y;
+
+ return ret;
+}
+
+/**
+ * @brief DEN value stored in LSB of Z-axis.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of den_x in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lsm6dso32x_ctrl9_xl_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
+ reg.den_x = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief DEN value stored in LSB of Z-axis.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of den_x in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_den_mark_axis_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lsm6dso32x_ctrl9_xl_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
+ *val = reg.den_x;
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LSM6DSO32X_Pedometer
+ * @brief This section groups all the functions that manage pedometer.
+ * @{
+ *
+ */
+
+/**
+ * @brief Enable pedometer algorithm.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val turn on and configure pedometer
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_pedo_sens_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_pedo_md_t val)
+{
+ lsm6dso32x_pedo_cmd_reg_t pedo_cmd_reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_PEDO_CMD_REG,
+ (uint8_t *)&pedo_cmd_reg);
+
+ if (ret == 0)
+ {
+ pedo_cmd_reg.fp_rejection_en = ((uint8_t)val & 0x10U) >> 4;
+ pedo_cmd_reg.ad_det_en = ((uint8_t)val & 0x20U) >> 5;
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_PEDO_CMD_REG,
+ (uint8_t *)&pedo_cmd_reg);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Enable pedometer algorithm.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val turn on and configure pedometer
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_pedo_sens_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_pedo_md_t *val)
+{
+ lsm6dso32x_pedo_cmd_reg_t pedo_cmd_reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_PEDO_CMD_REG,
+ (uint8_t *)&pedo_cmd_reg);
+
+ switch ((pedo_cmd_reg.ad_det_en << 5) | (pedo_cmd_reg.fp_rejection_en
+ << 4))
+ {
+ case LSM6DSO32X_PEDO_BASE_MODE:
+ *val = LSM6DSO32X_PEDO_BASE_MODE;
+ break;
+
+ case LSM6DSO32X_FALSE_STEP_REJ:
+ *val = LSM6DSO32X_FALSE_STEP_REJ;
+ break;
+
+ case LSM6DSO32X_FALSE_STEP_REJ_ADV_MODE:
+ *val = LSM6DSO32X_FALSE_STEP_REJ_ADV_MODE;
+ break;
+
+ default:
+ *val = LSM6DSO32X_PEDO_BASE_MODE;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Interrupt status bit for step detection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of is_step_det in reg EMB_FUNC_STATUS
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_pedo_step_detect_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lsm6dso32x_emb_func_status_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_STATUS,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ *val = reg.is_step_det;
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Pedometer debounce configuration register (r/w).[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
+{
+ int32_t ret;
+
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_PEDO_DEB_STEPS_CONF,
+ buff);
+
+ return ret;
+}
+
+/**
+ * @brief Pedometer debounce configuration register (r/w).[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
+{
+ int32_t ret;
+
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_PEDO_DEB_STEPS_CONF,
+ buff);
+
+ return ret;
+}
+
+/**
+ * @brief Time period register for step detection on delta time (r/w).[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_pedo_steps_period_set(stmdev_ctx_t *ctx,
+ uint16_t val)
+{
+ uint8_t buff[2];
+ int32_t ret;
+
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_PEDO_SC_DELTAT_L,
+ &buff[0]);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_PEDO_SC_DELTAT_H,
+ &buff[1]);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Time period register for step detection on delta time (r/w).[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_pedo_steps_period_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
+{
+ uint8_t buff[2];
+ int32_t ret;
+
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_PEDO_SC_DELTAT_L,
+ &buff[0]);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_PEDO_SC_DELTAT_H,
+ &buff[1]);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Set when user wants to generate interrupt on count overflow
+ * event/every step.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of carry_count_en in reg PEDO_CMD_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_pedo_int_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_carry_count_en_t val)
+{
+ lsm6dso32x_pedo_cmd_reg_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_PEDO_CMD_REG,
+ (uint8_t *)®);
+
+ if (ret == 0)
+ {
+ reg.carry_count_en = (uint8_t)val;
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_PEDO_CMD_REG,
+ (uint8_t *)®);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Set when user wants to generate interrupt on count overflow
+ * event/every step.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of carry_count_en in reg PEDO_CMD_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_pedo_int_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_carry_count_en_t *val)
+{
+ lsm6dso32x_pedo_cmd_reg_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_PEDO_CMD_REG,
+ (uint8_t *)®);
+
+ switch (reg.carry_count_en)
+ {
+ case LSM6DSO32X_EVERY_STEP:
+ *val = LSM6DSO32X_EVERY_STEP;
+ break;
+
+ case LSM6DSO32X_COUNT_OVERFLOW:
+ *val = LSM6DSO32X_COUNT_OVERFLOW;
+ break;
+
+ default:
+ *val = LSM6DSO32X_EVERY_STEP;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LSM6DSO32X_significant_motion
+ * @brief This section groups all the functions that manage the
+ * significant motion detection.
+ * @{
+ *
+ */
+
+/**
+ * @brief Interrupt status bit for significant motion detection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of is_sigmot in reg EMB_FUNC_STATUS
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_motion_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lsm6dso32x_emb_func_status_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_STATUS,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ *val = reg.is_sigmot;
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LSM6DSO32X_tilt_detection
+ * @brief This section groups all the functions that manage the tilt
+ * event detection.
+ * @{
+ *
+ */
+
+/**
+ * @brief Interrupt status bit for tilt detection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of is_tilt in reg EMB_FUNC_STATUS
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_tilt_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lsm6dso32x_emb_func_status_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_STATUS,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ *val = reg.is_tilt;
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LSM6DSO32X_ magnetometer_sensor
+ * @brief This section groups all the functions that manage additional
+ * magnetometer sensor.
+ * @{
+ *
+ */
+
+/**
+ * @brief External magnetometer sensitivity value register for
+ * Sensor hub.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_mag_sensitivity_set(stmdev_ctx_t *ctx,
+ uint16_t val)
+{
+ uint8_t buff[2];
+ int32_t ret;
+
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SENSITIVITY_L,
+ &buff[0]);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SENSITIVITY_H,
+ &buff[1]);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief External magnetometer sensitivity value register for
+ * Sensor hub.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_mag_sensitivity_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
+{
+ uint8_t buff[2];
+ int32_t ret;
+
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SENSITIVITY_L,
+ &buff[0]);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SENSITIVITY_H,
+ &buff[1]);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
+ }
+
+ return ret;
+}
+
+/**
+ * @brief External magnetometer sensitivity value register for
+ * Machine Learning Core.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_mlc_mag_sensitivity_set(stmdev_ctx_t *ctx,
+ uint16_t val)
+{
+ uint8_t buff[2];
+ int32_t ret;
+
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
+ ret = lsm6dso32x_ln_pg_write_byte(ctx,
+ LSM6DSO32X_MLC_MAG_SENSITIVITY_L,
+ &buff[0]);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_ln_pg_write_byte(ctx,
+ LSM6DSO32X_MLC_MAG_SENSITIVITY_H,
+ &buff[1]);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief External magnetometer sensitivity value register for
+ * Machine Learning Core.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_mlc_mag_sensitivity_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
+{
+ uint8_t buff[2];
+ int32_t ret;
+
+ ret = lsm6dso32x_ln_pg_read_byte(ctx,
+ LSM6DSO32X_MLC_MAG_SENSITIVITY_L,
+ &buff[0]);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_ln_pg_read_byte(ctx,
+ LSM6DSO32X_MLC_MAG_SENSITIVITY_H,
+ &buff[1]);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
+ }
+
+ return ret;
+}
+
+
+/**
+ * @brief Offset for hard-iron compensation register (r/w).[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val)
+{
+ uint8_t buff[6];
+ int32_t ret;
+
+ uint8_t i;
+ buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
+ buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
+ buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
+ buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
+ buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
+ buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
+ i = 0x00U;
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_OFFX_L,
+ &buff[i]);
+
+ if (ret == 0)
+ {
+ i++;
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_OFFX_H,
+ &buff[i]);
+ }
+
+ if (ret == 0)
+ {
+ i++;
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_OFFY_L,
+ &buff[i]);
+ }
+
+ if (ret == 0)
+ {
+ i++;
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_OFFY_H,
+ &buff[i]);
+ }
+
+ if (ret == 0)
+ {
+ i++;
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_OFFZ_L,
+ &buff[i]);
+ }
+
+ if (ret == 0)
+ {
+ i++;
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_OFFZ_H,
+ &buff[i]);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Offset for hard-iron compensation register (r/w).[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val)
+{
+ uint8_t buff[6];
+ int32_t ret;
+
+ uint8_t i;
+ i = 0x00U;
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_OFFX_L,
+ &buff[i]);
+
+ if (ret == 0)
+ {
+ i++;
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_OFFX_H,
+ &buff[i]);
+ }
+
+ if (ret == 0)
+ {
+ i++;
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_OFFY_L,
+ &buff[i]);
+ }
+
+ if (ret == 0)
+ {
+ i++;
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_OFFY_H,
+ &buff[i]);
+ }
+
+ if (ret == 0)
+ {
+ i++;
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_OFFZ_L,
+ &buff[i]);
+ }
+
+ if (ret == 0)
+ {
+ i++;
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_OFFZ_H,
+ &buff[i]);
+ }
+
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
+ return ret;
+}
+
+/**
+ * @brief Soft-iron (3x3 symmetric) matrix correction
+ * register (r/w). The value is expressed as
+ * half-precision floating-point format:
+ * SEEEEEFFFFFFFFFF
+ * S: 1 sign bit;
+ * E: 5 exponent bits;
+ * F: 10 fraction bits).[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_mag_soft_iron_set(stmdev_ctx_t *ctx, uint16_t *val)
+{
+ uint8_t buff[12];
+ uint8_t index;
+ int32_t ret;
+
+ buff[1] = (uint8_t)(val[0] / 256U);
+ buff[0] = (uint8_t)(val[0] - (buff[1] * 256U));
+ buff[3] = (uint8_t)(val[1] / 256U);
+ buff[2] = (uint8_t)(val[1] - (buff[3] * 256U));
+ buff[5] = (uint8_t)(val[2] / 256U);
+ buff[4] = (uint8_t)(val[2] - (buff[5] * 256U));
+ buff[7] = (uint8_t)(val[3] / 256U);
+ buff[6] = (uint8_t)(val[3] - (buff[1] * 256U));
+ buff[9] = (uint8_t)(val[4] / 256U);
+ buff[8] = (uint8_t)(val[4] - (buff[3] * 256U));
+ buff[11] = (uint8_t)(val[5] / 256U);
+ buff[10] = (uint8_t)(val[5] - (buff[5] * 256U));
+ index = 0x00U;
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_XX_L,
+ &buff[index]);
+
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_XX_H,
+ &buff[index]);
+ }
+
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_XY_L,
+ &buff[index]);
+ }
+
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_XY_H,
+ &buff[index]);
+ }
+
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_XZ_L,
+ &buff[index]);
+ }
+
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_XZ_H,
+ &buff[index]);
+ }
+
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_YY_L,
+ &buff[index]);
+ }
+
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_YY_H,
+ &buff[index]);
+ }
+
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_YZ_L,
+ &buff[index]);
+ }
+
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_YZ_H,
+ &buff[index]);
+ }
+
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_ZZ_L,
+ &buff[index]);
+ }
+
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_ZZ_H,
+ &buff[index]);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Soft-iron (3x3 symmetric) matrix
+ * correction register (r/w).
+ * The value is expressed as half-precision
+ * floating-point format:
+ * SEEEEEFFFFFFFFFF
+ * S: 1 sign bit;
+ * E: 5 exponent bits;
+ * F: 10 fraction bits.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_mag_soft_iron_get(stmdev_ctx_t *ctx, uint16_t *val)
+{
+ uint8_t buff[12];
+ uint8_t index;
+ int32_t ret;
+
+ index = 0x00U;
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_XX_L,
+ &buff[index]);
+
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_XX_H,
+ &buff[index]);
+ }
+
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_XY_L,
+ &buff[index]);
+ }
+
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_XY_H,
+ &buff[index]);
+ }
+
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_XZ_L,
+ &buff[index]);
+ }
+
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_XZ_H,
+ &buff[index]);
+ }
+
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_YY_L,
+ &buff[index]);
+ }
+
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_YY_H,
+ &buff[index]);
+ }
+
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_YZ_L,
+ &buff[index]);
+ }
+
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_YZ_H,
+ &buff[index]);
+ }
+
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_ZZ_L,
+ &buff[index]);
+ }
+
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_ZZ_H,
+ &buff[index]);
+ }
+
+ val[0] = buff[1];
+ val[0] = (val[0] * 256U) + buff[0];
+ val[1] = buff[3];
+ val[1] = (val[1] * 256U) + buff[2];
+ val[2] = buff[5];
+ val[2] = (val[2] * 256U) + buff[4];
+ val[3] = buff[7];
+ val[3] = (val[3] * 256U) + buff[6];
+ val[4] = buff[9];
+ val[4] = (val[4] * 256U) + buff[8];
+ val[5] = buff[11];
+ val[6] = (val[5] * 256U) + buff[10];
+
+ return ret;
+}
+
+/**
+ * @brief Magnetometer Z-axis coordinates
+ * rotation (to be aligned to
+ * accelerometer/gyroscope axes
+ * orientation).[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of mag_z_axis in reg MAG_CFG_A
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_mag_z_orient_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_mag_z_axis_t val)
+{
+ lsm6dso32x_mag_cfg_a_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_CFG_A,
+ (uint8_t *)®);
+
+ if (ret == 0)
+ {
+ reg.mag_z_axis = (uint8_t) val;
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_CFG_A,
+ (uint8_t *)®);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Magnetometer Z-axis coordinates
+ * rotation (to be aligned to
+ * accelerometer/gyroscope axes
+ * orientation).[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of mag_z_axis in reg MAG_CFG_A
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_mag_z_orient_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_mag_z_axis_t *val)
+{
+ lsm6dso32x_mag_cfg_a_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_CFG_A,
+ (uint8_t *)®);
+
+ switch (reg.mag_z_axis)
+ {
+ case LSM6DSO32X_Z_EQ_Y:
+ *val = LSM6DSO32X_Z_EQ_Y;
+ break;
+
+ case LSM6DSO32X_Z_EQ_MIN_Y:
+ *val = LSM6DSO32X_Z_EQ_MIN_Y;
+ break;
+
+ case LSM6DSO32X_Z_EQ_X:
+ *val = LSM6DSO32X_Z_EQ_X;
+ break;
+
+ case LSM6DSO32X_Z_EQ_MIN_X:
+ *val = LSM6DSO32X_Z_EQ_MIN_X;
+ break;
+
+ case LSM6DSO32X_Z_EQ_MIN_Z:
+ *val = LSM6DSO32X_Z_EQ_MIN_Z;
+ break;
+
+ case LSM6DSO32X_Z_EQ_Z:
+ *val = LSM6DSO32X_Z_EQ_Z;
+ break;
+
+ default:
+ *val = LSM6DSO32X_Z_EQ_Y;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Magnetometer Y-axis coordinates
+ * rotation (to be aligned to
+ * accelerometer/gyroscope axes
+ * orientation).[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of mag_y_axis in reg MAG_CFG_A
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_mag_y_orient_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_mag_y_axis_t val)
+{
+ lsm6dso32x_mag_cfg_a_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_CFG_A,
+ (uint8_t *)®);
+
+ if (ret == 0)
+ {
+ reg.mag_y_axis = (uint8_t)val;
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_CFG_A,
+ (uint8_t *) ®);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Magnetometer Y-axis coordinates
+ * rotation (to be aligned to
+ * accelerometer/gyroscope axes
+ * orientation).[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of mag_y_axis in reg MAG_CFG_A
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_mag_y_orient_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_mag_y_axis_t *val)
+{
+ lsm6dso32x_mag_cfg_a_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_CFG_A,
+ (uint8_t *)®);
+
+ switch (reg.mag_y_axis)
+ {
+ case LSM6DSO32X_Y_EQ_Y:
+ *val = LSM6DSO32X_Y_EQ_Y;
+ break;
+
+ case LSM6DSO32X_Y_EQ_MIN_Y:
+ *val = LSM6DSO32X_Y_EQ_MIN_Y;
+ break;
+
+ case LSM6DSO32X_Y_EQ_X:
+ *val = LSM6DSO32X_Y_EQ_X;
+ break;
+
+ case LSM6DSO32X_Y_EQ_MIN_X:
+ *val = LSM6DSO32X_Y_EQ_MIN_X;
+ break;
+
+ case LSM6DSO32X_Y_EQ_MIN_Z:
+ *val = LSM6DSO32X_Y_EQ_MIN_Z;
+ break;
+
+ case LSM6DSO32X_Y_EQ_Z:
+ *val = LSM6DSO32X_Y_EQ_Z;
+ break;
+
+ default:
+ *val = LSM6DSO32X_Y_EQ_Y;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Magnetometer X-axis coordinates
+ * rotation (to be aligned to
+ * accelerometer/gyroscope axes
+ * orientation).[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of mag_x_axis in reg MAG_CFG_B
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_mag_x_orient_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_mag_x_axis_t val)
+{
+ lsm6dso32x_mag_cfg_b_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_CFG_B,
+ (uint8_t *)®);
+
+ if (ret == 0)
+ {
+ reg.mag_x_axis = (uint8_t)val;
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_CFG_B,
+ (uint8_t *)®);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Magnetometer X-axis coordinates
+ * rotation (to be aligned to
+ * accelerometer/gyroscope axes
+ * orientation).[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of mag_x_axis in reg MAG_CFG_B
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_mag_x_orient_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_mag_x_axis_t *val)
+{
+ lsm6dso32x_mag_cfg_b_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_CFG_B,
+ (uint8_t *)®);
+
+ switch (reg.mag_x_axis)
+ {
+ case LSM6DSO32X_X_EQ_Y:
+ *val = LSM6DSO32X_X_EQ_Y;
+ break;
+
+ case LSM6DSO32X_X_EQ_MIN_Y:
+ *val = LSM6DSO32X_X_EQ_MIN_Y;
+ break;
+
+ case LSM6DSO32X_X_EQ_X:
+ *val = LSM6DSO32X_X_EQ_X;
+ break;
+
+ case LSM6DSO32X_X_EQ_MIN_X:
+ *val = LSM6DSO32X_X_EQ_MIN_X;
+ break;
+
+ case LSM6DSO32X_X_EQ_MIN_Z:
+ *val = LSM6DSO32X_X_EQ_MIN_Z;
+ break;
+
+ case LSM6DSO32X_X_EQ_Z:
+ *val = LSM6DSO32X_X_EQ_Z;
+ break;
+
+ default:
+ *val = LSM6DSO32X_X_EQ_Y;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LSM6DSO32X_finite_state_machine
+ * @brief This section groups all the functions that manage the
+ * state_machine.
+ * @{
+ *
+ */
+
+/**
+ * @brief Interrupt status bit for FSM long counter
+ * timeout interrupt event.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of is_fsm_lc in reg EMB_FUNC_STATUS
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lsm6dso32x_emb_func_status_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_STATUS,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ *val = reg.is_fsm_lc;
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Finite State Machine enable.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fsm_enable_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_emb_fsm_enable_t *val)
+{
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_ENABLE_A,
+ (uint8_t *)&val->fsm_enable_a, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_ENABLE_B,
+ (uint8_t *)&val->fsm_enable_b, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Finite State Machine enable.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fsm_enable_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_emb_fsm_enable_t *val)
+{
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_ENABLE_A,
+ (uint8_t *) val,
+ 2);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief FSM long counter status register. Long counter value is an
+ * unsigned integer value (16-bit format).[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val)
+{
+ uint8_t buff[2];
+ int32_t ret;
+
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_LONG_COUNTER_L, buff,
+ 2);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief FSM long counter status register. Long counter value is an
+ * unsigned integer value (16-bit format).[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val)
+{
+ uint8_t buff[2];
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_LONG_COUNTER_L, buff,
+ 2);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Clear FSM long counter value.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of fsm_lc_clr in
+ * reg FSM_LONG_COUNTER_CLEAR
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_long_clr_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_fsm_lc_clr_t val)
+{
+ lsm6dso32x_fsm_long_counter_clear_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_LONG_COUNTER_CLEAR,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ reg. fsm_lc_clr = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_LONG_COUNTER_CLEAR,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Clear FSM long counter value.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of fsm_lc_clr in
+ * reg FSM_LONG_COUNTER_CLEAR
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_long_clr_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_fsm_lc_clr_t *val)
+{
+ lsm6dso32x_fsm_long_counter_clear_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_LONG_COUNTER_CLEAR,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ switch (reg.fsm_lc_clr)
+ {
+ case LSM6DSO32X_LC_NORMAL:
+ *val = LSM6DSO32X_LC_NORMAL;
+ break;
+
+ case LSM6DSO32X_LC_CLEAR:
+ *val = LSM6DSO32X_LC_CLEAR;
+ break;
+
+ case LSM6DSO32X_LC_CLEAR_DONE:
+ *val = LSM6DSO32X_LC_CLEAR_DONE;
+ break;
+
+ default:
+ *val = LSM6DSO32X_LC_NORMAL;
+ break;
+ }
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief FSM output registers[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val struct of registers from FSM_OUTS1 to FSM_OUTS16
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fsm_out_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_fsm_out_t *val)
+{
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_OUTS1, (uint8_t *)val,
+ 16);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Finite State Machine ODR configuration.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fsm_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_fsm_odr_t val)
+{
+ lsm6dso32x_emb_func_odr_cfg_b_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_ODR_CFG_B,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ reg.not_used_01 = 3; /* set default values */
+ reg.not_used_02 = 2; /* set default values */
+ reg.fsm_odr = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_ODR_CFG_B,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Finite State Machine ODR configuration.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fsm_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_fsm_odr_t *val)
+{
+ lsm6dso32x_emb_func_odr_cfg_b_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_ODR_CFG_B,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ switch (reg.fsm_odr)
+ {
+ case LSM6DSO32X_ODR_FSM_12Hz5:
+ *val = LSM6DSO32X_ODR_FSM_12Hz5;
+ break;
+
+ case LSM6DSO32X_ODR_FSM_26Hz:
+ *val = LSM6DSO32X_ODR_FSM_26Hz;
+ break;
+
+ case LSM6DSO32X_ODR_FSM_52Hz:
+ *val = LSM6DSO32X_ODR_FSM_52Hz;
+ break;
+
+ case LSM6DSO32X_ODR_FSM_104Hz:
+ *val = LSM6DSO32X_ODR_FSM_104Hz;
+ break;
+
+ default:
+ *val = LSM6DSO32X_ODR_FSM_12Hz5;
+ break;
+ }
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief FSM initialization request.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of fsm_init in reg FSM_INIT
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lsm6dso32x_emb_func_init_b_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_INIT_B,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ reg.fsm_init = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_INIT_B,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief FSM initialization request.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of fsm_init in reg FSM_INIT
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lsm6dso32x_emb_func_init_b_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_INIT_B,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ *val = reg.fsm_init;
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief FSM long counter timeout register (r/w). The long counter
+ * timeout value is an unsigned integer value (16-bit format).
+ * When the long counter value reached this value,
+ * the FSM generates an interrupt.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val the value of long counter
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_long_cnt_int_value_set(stmdev_ctx_t *ctx,
+ uint16_t val)
+{
+ int32_t ret;
+
+ uint8_t add_l;
+ uint8_t add_h;
+ add_h = (uint8_t)((val & 0xFF00U) >> 8);
+ add_l = (uint8_t)(val & 0x00FFU);
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_FSM_LC_TIMEOUT_L,
+ &add_l);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_FSM_LC_TIMEOUT_H,
+ &add_h);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief FSM long counter timeout register (r/w). The long counter
+ * timeout value is an unsigned integer value (16-bit format).
+ * When the long counter value reached this value,
+ * the FSM generates an interrupt.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val buffer that stores the value of long counter
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_long_cnt_int_value_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
+{
+ int32_t ret;
+
+ uint8_t add_l;
+ uint8_t add_h;
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_FSM_LC_TIMEOUT_L,
+ &add_l);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_FSM_LC_TIMEOUT_H,
+ &add_h);
+ *val = add_h;
+ *val = *val << 8;
+ *val += add_l;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief FSM number of programs register.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val value to write
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fsm_number_of_programs_set(stmdev_ctx_t *ctx,
+ uint8_t val)
+{
+ int32_t ret;
+
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_FSM_PROGRAMS, &val);
+
+ return ret;
+}
+
+/**
+ * @brief FSM number of programs register.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val buffer that stores data read.
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fsm_number_of_programs_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ int32_t ret;
+
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_FSM_PROGRAMS, val);
+
+ return ret;
+}
+
+/**
+ * @brief FSM start address register (r/w).
+ * First available address is 0x033C.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val the value of start address
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fsm_start_address_set(stmdev_ctx_t *ctx,
+ uint16_t val)
+{
+ int32_t ret;
+
+ uint8_t add_l;
+ uint8_t add_h;
+ add_h = (uint8_t)((val & 0xFF00U) >> 8);
+ add_l = (uint8_t)(val & 0x00FFU);
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_FSM_START_ADD_L,
+ &add_l);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_FSM_START_ADD_H,
+ &add_h);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief FSM start address register (r/w).
+ * First available address is 0x033C.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val buffer the value of start address.
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_fsm_start_address_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
+{
+ int32_t ret;
+
+ uint8_t add_l;
+ uint8_t add_h;
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_FSM_START_ADD_L,
+ &add_l);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_FSM_START_ADD_H,
+ &add_h);
+ *val = add_h;
+ *val = *val << 8;
+ *val += add_l;
+ }
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @addtogroup Machine Learning Core
+ * @brief This section group all the functions concerning the
+ * usage of Machine Learning Core
+ * @{
+ *
+ */
+
+/**
+ * @brief Machine Learning Core status register[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val register MLC_STATUS_MAINPAGE
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_mlc_status_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_mlc_status_mainpage_t *val)
+{
+ return lsm6dso32x_read_reg(ctx, LSM6DSO32X_MLC_STATUS_MAINPAGE,
+ (uint8_t *) val, 1);
+}
+
+/**
+ * @brief Machine Learning Core data rate selection.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val get the values of mlc_odr in
+ * reg EMB_FUNC_ODR_CFG_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_mlc_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_mlc_odr_t val)
+{
+ lsm6dso32x_emb_func_odr_cfg_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_ODR_CFG_C,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ reg.mlc_odr = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_ODR_CFG_C,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Machine Learning Core data rate selection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of mlc_odr in
+ * reg EMB_FUNC_ODR_CFG_C
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_mlc_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_mlc_odr_t *val)
+{
+ lsm6dso32x_emb_func_odr_cfg_c_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_ODR_CFG_C,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ switch (reg.mlc_odr)
+ {
+ case LSM6DSO32X_ODR_PRGS_12Hz5:
+ *val = LSM6DSO32X_ODR_PRGS_12Hz5;
+ break;
+
+ case LSM6DSO32X_ODR_PRGS_26Hz:
+ *val = LSM6DSO32X_ODR_PRGS_26Hz;
+ break;
+
+ case LSM6DSO32X_ODR_PRGS_52Hz:
+ *val = LSM6DSO32X_ODR_PRGS_52Hz;
+ break;
+
+ case LSM6DSO32X_ODR_PRGS_104Hz:
+ *val = LSM6DSO32X_ODR_PRGS_104Hz;
+ break;
+
+ default:
+ *val = LSM6DSO32X_ODR_PRGS_12Hz5;
+ break;
+ }
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup LSM6DSO32X_Sensor_hub
+ * @brief This section groups all the functions that manage the
+ * sensor hub.
+ * @{
+ *
+ */
+
+/**
+ * @brief Sensor hub output registers.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val union of registers from SENSOR_HUB_1 to SENSOR_HUB_18
+ *
+ */
+int32_t lsm6dso32x_sh_read_data_raw_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_emb_sh_read_t *val,
+ uint8_t len)
+{
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SENSOR_HUB_1,
+ (uint8_t *) val,
+ len);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Number of external sensors to be read by the sensor hub.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of aux_sens_on in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_slave_connected_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_aux_sens_on_t val)
+{
+ lsm6dso32x_master_config_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ reg.aux_sens_on = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Number of external sensors to be read by the sensor hub.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of aux_sens_on in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_slave_connected_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_aux_sens_on_t *val)
+{
+ lsm6dso32x_master_config_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ switch (reg.aux_sens_on)
+ {
+ case LSM6DSO32X_SLV_0:
+ *val = LSM6DSO32X_SLV_0;
+ break;
+
+ case LSM6DSO32X_SLV_0_1:
+ *val = LSM6DSO32X_SLV_0_1;
+ break;
+
+ case LSM6DSO32X_SLV_0_1_2:
+ *val = LSM6DSO32X_SLV_0_1_2;
+ break;
+
+ case LSM6DSO32X_SLV_0_1_2_3:
+ *val = LSM6DSO32X_SLV_0_1_2_3;
+ break;
+
+ default:
+ *val = LSM6DSO32X_SLV_0;
+ break;
+ }
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Sensor hub I2C master enable.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of master_on in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lsm6dso32x_master_config_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ reg.master_on = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Sensor hub I2C master enable.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of master_on in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lsm6dso32x_master_config_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ *val = reg.master_on;
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Master I2C pull-up enable.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of shub_pu_en in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_pin_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_shub_pu_en_t val)
+{
+ lsm6dso32x_master_config_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ reg.shub_pu_en = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Master I2C pull-up enable.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of shub_pu_en in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_pin_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_shub_pu_en_t *val)
+{
+ lsm6dso32x_master_config_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ switch (reg.shub_pu_en)
+ {
+ case LSM6DSO32X_EXT_PULL_UP:
+ *val = LSM6DSO32X_EXT_PULL_UP;
+ break;
+
+ case LSM6DSO32X_INTERNAL_PULL_UP:
+ *val = LSM6DSO32X_INTERNAL_PULL_UP;
+ break;
+
+ default:
+ *val = LSM6DSO32X_EXT_PULL_UP;
+ break;
+ }
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief I2C interface pass-through.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of pass_through_mode in
+ * reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+ lsm6dso32x_master_config_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ reg.pass_through_mode = val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief I2C interface pass-through.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of pass_through_mode in
+ * reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_pass_through_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
+{
+ lsm6dso32x_master_config_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ *val = reg.pass_through_mode;
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Sensor hub trigger signal selection.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of start_config in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_syncro_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_start_config_t val)
+{
+ lsm6dso32x_master_config_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ reg.start_config = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Sensor hub trigger signal selection.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of start_config in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_syncro_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_start_config_t *val)
+{
+ lsm6dso32x_master_config_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ switch (reg.start_config)
+ {
+ case LSM6DSO32X_EXT_ON_INT2_PIN:
+ *val = LSM6DSO32X_EXT_ON_INT2_PIN;
+ break;
+
+ case LSM6DSO32X_XL_GY_DRDY:
+ *val = LSM6DSO32X_XL_GY_DRDY;
+ break;
+
+ default:
+ *val = LSM6DSO32X_EXT_ON_INT2_PIN;
+ break;
+ }
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Slave 0 write operation is performed only at the first
+ * sensor hub cycle.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of write_once in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_write_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_write_once_t val)
+{
+ lsm6dso32x_master_config_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ reg.write_once = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Slave 0 write operation is performed only at the first sensor
+ * hub cycle.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of write_once in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_write_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_write_once_t *val)
+{
+ lsm6dso32x_master_config_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ switch (reg.write_once)
+ {
+ case LSM6DSO32X_EACH_SH_CYCLE:
+ *val = LSM6DSO32X_EACH_SH_CYCLE;
+ break;
+
+ case LSM6DSO32X_ONLY_FIRST_CYCLE:
+ *val = LSM6DSO32X_ONLY_FIRST_CYCLE;
+ break;
+
+ default:
+ *val = LSM6DSO32X_EACH_SH_CYCLE;
+ break;
+ }
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Reset Master logic and output registers.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_reset_set(stmdev_ctx_t *ctx)
+{
+ lsm6dso32x_master_config_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ reg.rst_master_regs = PROPERTY_ENABLE;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ reg.rst_master_regs = PROPERTY_DISABLE;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Reset Master logic and output registers.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of rst_master_regs in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+ lsm6dso32x_master_config_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ *val = reg.rst_master_regs;
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Rate at which the master communicates.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of shub_odr in reg slv1_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_shub_odr_t val)
+{
+ lsm6dso32x_slv0_config_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV0_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ reg.shub_odr = (uint8_t)val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV0_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Rate at which the master communicates.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Get the values of shub_odr in reg slv1_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_shub_odr_t *val)
+{
+ lsm6dso32x_slv0_config_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV0_CONFIG,
+ (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ switch (reg.shub_odr)
+ {
+ case LSM6DSO32X_SH_ODR_104Hz:
+ *val = LSM6DSO32X_SH_ODR_104Hz;
+ break;
+
+ case LSM6DSO32X_SH_ODR_52Hz:
+ *val = LSM6DSO32X_SH_ODR_52Hz;
+ break;
+
+ case LSM6DSO32X_SH_ODR_26Hz:
+ *val = LSM6DSO32X_SH_ODR_26Hz;
+ break;
+
+ case LSM6DSO32X_SH_ODR_13Hz:
+ *val = LSM6DSO32X_SH_ODR_13Hz;
+ break;
+
+ default:
+ *val = LSM6DSO32X_SH_ODR_104Hz;
+ break;
+ }
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Configure slave 0 for perform a write.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val a structure that contain
+ * - uint8_t slv1_add; 8 bit i2c device address
+ * - uint8_t slv1_subadd; 8 bit register device address
+ * - uint8_t slv1_data; 8 bit data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_cfg_write(stmdev_ctx_t *ctx,
+ lsm6dso32x_sh_cfg_write_t *val)
+{
+ lsm6dso32x_slv0_add_t reg;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
+
+ if (ret == 0)
+ {
+ reg.slave0 = val->slv0_add;
+ reg.rw_0 = 0;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV0_ADD, (uint8_t *)®, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV0_SUBADD,
+ &(val->slv0_subadd), 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_DATAWRITE_SLV0,
+ &(val->slv0_data), 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Configure slave 0 for perform a read.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Structure that contain
+ * - uint8_t slv1_add; 8 bit i2c device address
+ * - uint8_t slv1_subadd; 8 bit register device address
+ * - uint8_t slv1_len; num of bit to read
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
+ lsm6dso32x_sh_cfg_read_t *val)
+{
+ lsm6dso32x_slv0_add_t slv0_add;
+ lsm6dso32x_slv0_config_t slv0_config;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
+
+ if (ret == 0)
+ {
+ slv0_add.slave0 = val->slv_add;
+ slv0_add.rw_0 = 1;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV0_ADD,
+ (uint8_t *)&slv0_add, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV0_SUBADD,
+ &(val->slv_subadd), 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV0_CONFIG,
+ (uint8_t *)&slv0_config, 1);
+ }
+
+ if (ret == 0)
+ {
+ slv0_config.slave0_numop = val->slv_len;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV0_CONFIG,
+ (uint8_t *)&slv0_config, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Configure slave 0 for perform a write/read.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Structure that contain
+ * - uint8_t slv1_add; 8 bit i2c device address
+ * - uint8_t slv1_subadd; 8 bit register device address
+ * - uint8_t slv1_len; num of bit to read
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
+ lsm6dso32x_sh_cfg_read_t *val)
+{
+ lsm6dso32x_slv1_add_t slv1_add;
+ lsm6dso32x_slv1_config_t slv1_config;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
+
+ if (ret == 0)
+ {
+ slv1_add.slave1_add = val->slv_add;
+ slv1_add.r_1 = 1;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV1_ADD,
+ (uint8_t *)&slv1_add, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV1_SUBADD,
+ &(val->slv_subadd), 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV1_CONFIG,
+ (uint8_t *)&slv1_config, 1);
+ }
+
+ if (ret == 0)
+ {
+ slv1_config.slave1_numop = val->slv_len;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV1_CONFIG,
+ (uint8_t *)&slv1_config, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Configure slave 0 for perform a write/read.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Structure that contain
+ * - uint8_t slv2_add; 8 bit i2c device address
+ * - uint8_t slv2_subadd; 8 bit register device address
+ * - uint8_t slv2_len; num of bit to read
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
+ lsm6dso32x_sh_cfg_read_t *val)
+{
+ lsm6dso32x_slv2_add_t slv2_add;
+ lsm6dso32x_slv2_config_t slv2_config;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
+
+ if (ret == 0)
+ {
+ slv2_add.slave2_add = val->slv_add;
+ slv2_add.r_2 = 1;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV2_ADD,
+ (uint8_t *)&slv2_add, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV2_SUBADD,
+ &(val->slv_subadd), 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV2_CONFIG,
+ (uint8_t *)&slv2_config, 1);
+ }
+
+ if (ret == 0)
+ {
+ slv2_config.slave2_numop = val->slv_len;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV2_CONFIG,
+ (uint8_t *)&slv2_config, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Configure slave 0 for perform a write/read.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val Structure that contain
+ * - uint8_t slv3_add; 8 bit i2c device address
+ * - uint8_t slv3_subadd; 8 bit register device address
+ * - uint8_t slv3_len; num of bit to read
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
+ lsm6dso32x_sh_cfg_read_t *val)
+{
+ lsm6dso32x_slv3_add_t slv3_add;
+ lsm6dso32x_slv3_config_t slv3_config;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
+
+ if (ret == 0)
+ {
+ slv3_add.slave3_add = val->slv_add;
+ slv3_add.r_3 = 1;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV3_ADD,
+ (uint8_t *)&slv3_add, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV3_SUBADD,
+ &(val->slv_subadd), 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV3_CONFIG,
+ (uint8_t *)&slv3_config, 1);
+ }
+
+ if (ret == 0)
+ {
+ slv3_config.slave3_numop = val->slv_len;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV3_CONFIG,
+ (uint8_t *)&slv3_config, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Sensor hub source register.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val union of registers from STATUS_MASTER to
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_sh_status_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_status_master_t *val)
+{
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_STATUS_MASTER,
+ (uint8_t *) val, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @defgroup Basic configuration
+ * @brief This section groups all the functions concerning
+ * device basic configuration.
+ * @{
+ *
+ */
+
+/**
+ * @brief Device "Who am I".[get]
+ *
+ * @param ctx communication interface handler. Use NULL to ignore
+ * this interface.(ptr)
+ * @param val ID values read from the two interfaces. ID values
+ * will be the same.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_id_get(stmdev_ctx_t *ctx, lsm6dso32x_id_t *val)
+{
+ int32_t ret = 0;
+
+ if (ctx != NULL)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WHO_AM_I,
+ (uint8_t *) & (val->ui), 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Re-initialize the device.[set]
+ *
+ * @param ctx communication interface handler.(ptr)
+ * @param val re-initialization mode. Refer to datasheet
+ * and application note for more information
+ * about differencies between boot and sw_reset
+ * procedure.
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_init_set(stmdev_ctx_t *ctx, lsm6dso32x_init_t val)
+{
+ lsm6dso32x_emb_func_init_a_t emb_func_init_a;
+ lsm6dso32x_emb_func_init_b_t emb_func_init_b;
+ lsm6dso32x_ctrl3_c_t ctrl3_c;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_INIT_B,
+ (uint8_t *)&emb_func_init_b, 1);
+ }
+
+ if (ret == 0)
+ {
+ emb_func_init_b.fifo_compr_init = (uint8_t)val
+ & ((uint8_t)LSM6DSO32X_FIFO_COMP >> 2);
+ emb_func_init_b.fsm_init = (uint8_t)val
+ & ((uint8_t)LSM6DSO32X_FSM >> 3);
+ emb_func_init_b.mlc_init = (uint8_t)val
+ & ((uint8_t)LSM6DSO32X_MLC >> 4);
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_INIT_B,
+ (uint8_t *)&emb_func_init_b, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_INIT_A,
+ (uint8_t *)&emb_func_init_a, 1);
+ }
+
+ if (ret == 0)
+ {
+ emb_func_init_a.step_det_init = ((uint8_t)val
+ & (uint8_t)LSM6DSO32X_PEDO) >> 5;
+ emb_func_init_a.tilt_init = ((uint8_t)val
+ & (uint8_t)LSM6DSO32X_TILT) >> 6;
+ emb_func_init_a.sig_mot_init = ((uint8_t)val
+ & (uint8_t)LSM6DSO32X_SMOTION) >> 7;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_INIT_A,
+ (uint8_t *)&emb_func_init_a, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
+ }
+
+ if (((val == LSM6DSO32X_BOOT) || (val == LSM6DSO32X_RESET)) &&
+ (ret == 0))
+ {
+ ctrl3_c.boot = (uint8_t)val & (uint8_t)LSM6DSO32X_BOOT;
+ ctrl3_c.sw_reset = ((uint8_t)val & (uint8_t)LSM6DSO32X_RESET) >> 1;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
+ }
+
+ if ((val == LSM6DSO32X_DRV_RDY)
+ && ((ctrl3_c.bdu == PROPERTY_DISABLE)
+ || (ctrl3_c.if_inc == PROPERTY_DISABLE)) && (ret == 0))
+ {
+ ctrl3_c.bdu = PROPERTY_ENABLE;
+ ctrl3_c.if_inc = PROPERTY_ENABLE;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Configures the bus operating mode.[set]
+ *
+ * @param ctx communication interface handler. Use NULL to ignore
+ * this interface.(ptr)
+ * @param val configures the bus operating mode for both the
+ * main and the auxiliary interface.
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_bus_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_bus_mode_t val)
+{
+ lsm6dso32x_i3c_bus_avb_t i3c_bus_avb;
+ lsm6dso32x_ctrl9_xl_t ctrl9_xl;
+ lsm6dso32x_ctrl3_c_t ctrl3_c;
+ lsm6dso32x_ctrl4_c_t ctrl4_c;
+ uint8_t bit_val;
+ int32_t ret;
+
+ ret = 0;
+
+ if (ctx != NULL)
+ {
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
+ }
+
+ bit_val = ((uint8_t)val.ui_bus_md & 0x04U) >> 2;
+
+ if ((ret == 0) && (ctrl9_xl.i3c_disable != bit_val))
+ {
+ ctrl9_xl.i3c_disable = bit_val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
+ (uint8_t *)&i3c_bus_avb, 1);
+ }
+
+ bit_val = ((uint8_t)val.ui_bus_md & 0x30U) >> 4;
+
+ if ((ret == 0) && (i3c_bus_avb.i3c_bus_avb_sel != bit_val))
+ {
+ i3c_bus_avb.i3c_bus_avb_sel = bit_val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
+ (uint8_t *)&i3c_bus_avb, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
+ }
+
+ bit_val = ((uint8_t)val.ui_bus_md & 0x02U) >> 1;
+
+ if ((ret == 0) && (ctrl4_c.i2c_disable != bit_val))
+ {
+ ctrl4_c.i2c_disable = bit_val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
+ }
+
+ bit_val = (uint8_t)val.ui_bus_md & 0x01U;
+
+ if ((ret == 0) && (ctrl3_c.sim != bit_val))
+ {
+ ctrl3_c.sim = bit_val;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Get the bus operating mode.[get]
+ *
+ * @param ctx communication interface handler. Use NULL to ignore
+ * this interface.(ptr)
+ * @param val retrieves the bus operating mode for both the main
+ * and the auxiliary interface.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_bus_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_bus_mode_t *val)
+{
+ lsm6dso32x_i3c_bus_avb_t i3c_bus_avb;
+ lsm6dso32x_ctrl9_xl_t ctrl9_xl;
+ lsm6dso32x_ctrl3_c_t ctrl3_c;
+ lsm6dso32x_ctrl4_c_t ctrl4_c;
+ int32_t ret = 0;
+
+ if (ctx != NULL)
+ {
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL,
+ (uint8_t *)&ctrl9_xl, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
+ (uint8_t *)&i3c_bus_avb, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
+
+ switch ((i3c_bus_avb.i3c_bus_avb_sel << 4) &
+ (ctrl9_xl.i3c_disable << 2) &
+ (ctrl4_c.i2c_disable << 1) & ctrl3_c.sim)
+ {
+ case LSM6DSO32X_SEL_BY_HW:
+ val->ui_bus_md = LSM6DSO32X_SEL_BY_HW;
+ break;
+
+ case LSM6DSO32X_SPI_4W:
+ val->ui_bus_md = LSM6DSO32X_SPI_4W;
+ break;
+
+ case LSM6DSO32X_SPI_3W:
+ val->ui_bus_md = LSM6DSO32X_SPI_3W;
+ break;
+
+ case LSM6DSO32X_I2C:
+ val->ui_bus_md = LSM6DSO32X_I2C;
+ break;
+
+ case LSM6DSO32X_I3C_T_50us:
+ val->ui_bus_md = LSM6DSO32X_I3C_T_50us;
+ break;
+
+ case LSM6DSO32X_I3C_T_2us:
+ val->ui_bus_md = LSM6DSO32X_I3C_T_2us;
+ break;
+
+ case LSM6DSO32X_I3C_T_1ms:
+ val->ui_bus_md = LSM6DSO32X_I3C_T_1ms;
+ break;
+
+ case LSM6DSO32X_I3C_T_25ms:
+ val->ui_bus_md = LSM6DSO32X_I3C_T_25ms;
+ break;
+
+ default:
+ val->ui_bus_md = LSM6DSO32X_SEL_BY_HW;
+ break;
+ }
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Get the status of the device.[get]
+ *
+ * @param ctx communication interface handler. Use NULL to ignore
+ * this interface.(ptr)
+ * @param val the status of the device.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_status_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_status_t *val)
+{
+ lsm6dso32x_status_reg_t status_reg;
+ lsm6dso32x_ctrl3_c_t ctrl3_c;
+ int32_t ret;
+ ret = 0;
+
+ if (ctx != NULL)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
+ val->sw_reset = ctrl3_c.sw_reset;
+ val->boot = ctrl3_c.boot;
+
+ if ((ret == 0) && (ctrl3_c.sw_reset == PROPERTY_DISABLE) &&
+ (ctrl3_c.boot == PROPERTY_DISABLE))
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_STATUS_REG,
+ (uint8_t *)&status_reg, 1);
+ val->drdy_xl = status_reg.xlda;
+ val->drdy_g = status_reg.gda;
+ val->drdy_temp = status_reg.tda;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Electrical pin configuration.[set]
+ *
+ * @param ctx communication interface handler.(ptr)
+ * @param val the electrical settings for the configurable
+ * pins.
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_pin_conf_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_pin_conf_t val)
+{
+ lsm6dso32x_i3c_bus_avb_t i3c_bus_avb;
+ lsm6dso32x_pin_ctrl_t pin_ctrl;
+ lsm6dso32x_ctrl3_c_t ctrl3_c;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PIN_CTRL,
+ (uint8_t *)&pin_ctrl, 1);
+
+ if (ret == 0)
+ {
+ pin_ctrl.sdo_pu_en = val.sdo_sa0_pull_up;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PIN_CTRL,
+ (uint8_t *)&pin_ctrl, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
+ }
+
+ if (ret == 0)
+ {
+ ctrl3_c.pp_od = ~val.int1_int2_push_pull;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
+ (uint8_t *)&i3c_bus_avb, 1);
+ }
+
+ if (ret == 0)
+ {
+ i3c_bus_avb.pd_dis_int1 = ~val.int1_pull_down;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
+ (uint8_t *)&i3c_bus_avb, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Electrical pin configuration.[get]
+ *
+ * @param ctx communication interface handler.(ptr)
+ * @param val the electrical settings for the configurable
+ * pins.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_pin_conf_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_pin_conf_t *val)
+{
+ lsm6dso32x_i3c_bus_avb_t i3c_bus_avb;
+ lsm6dso32x_pin_ctrl_t pin_ctrl;
+ lsm6dso32x_ctrl3_c_t ctrl3_c;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PIN_CTRL,
+ (uint8_t *)&pin_ctrl, 1);
+
+ if (ret == 0)
+ {
+ val->aux_sdo_ocs_pull_up = pin_ctrl.sdo_pu_en;
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
+ }
+
+ if (ret == 0)
+ {
+ val->int1_int2_push_pull = ~ctrl3_c.pp_od;
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
+ (uint8_t *)&i3c_bus_avb, 1);
+ }
+
+ if (ret == 0)
+ {
+ val->int1_pull_down = ~i3c_bus_avb.pd_dis_int1;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Interrupt pins hardware signal configuration.[set]
+ *
+ * @param ctx communication interface handler.(ptr)
+ * @param val the pins hardware signal settings.
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_interrupt_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_int_mode_t val)
+{
+ lsm6dso32x_tap_cfg0_t tap_cfg0;
+ lsm6dso32x_page_rw_t page_rw;
+ lsm6dso32x_ctrl3_c_t ctrl3_c;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.h_lactive = val.active_low;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0,
+ (uint8_t *) &tap_cfg0, 1);
+ }
+
+ if (ret == 0)
+ {
+ tap_cfg0.lir = val.base_latched;
+ tap_cfg0.int_clr_on_read = val.base_latched | val.emb_latched;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG0,
+ (uint8_t *) &tap_cfg0, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
+ (uint8_t *) &page_rw, 1);
+ }
+
+ if (ret == 0)
+ {
+ page_rw.emb_func_lir = val.emb_latched;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW,
+ (uint8_t *) &page_rw, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Interrupt pins hardware signal configuration.[get]
+ *
+ * @param ctx communication interface handler.(ptr)
+ * @param val the pins hardware signal settings.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_interrupt_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_int_mode_t *val)
+{
+ lsm6dso32x_tap_cfg0_t tap_cfg0;
+ lsm6dso32x_page_rw_t page_rw;
+ lsm6dso32x_ctrl3_c_t ctrl3_c;
+ int32_t ret;
+
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C,
+ (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.h_lactive = val->active_low;
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0,
+ (uint8_t *) &tap_cfg0, 1);
+ }
+
+ if (ret == 0)
+ {
+ tap_cfg0.lir = val->base_latched;
+ tap_cfg0.int_clr_on_read = val->base_latched | val->emb_latched;
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
+ (uint8_t *) &page_rw, 1);
+ }
+
+ if (ret == 0)
+ {
+ page_rw.emb_func_lir = val->emb_latched;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW,
+ (uint8_t *) &page_rw, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Route interrupt signals on int1 pin.[set]
+ *
+ * @param ctx communication interface handler.(ptr)
+ * @param val the signals to route on int1 pin.
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_pin_int1_route_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_pin_int1_route_t val)
+{
+ lsm6dso32x_pin_int2_route_t pin_int2_route;
+ lsm6dso32x_emb_func_int1_t emb_func_int1;
+ lsm6dso32x_fsm_int1_a_t fsm_int1_a;
+ lsm6dso32x_fsm_int1_b_t fsm_int1_b;
+ lsm6dso32x_int1_ctrl_t int1_ctrl;
+ lsm6dso32x_int2_ctrl_t int2_ctrl;
+ lsm6dso32x_mlc_int1_t mlc_int1;
+ lsm6dso32x_tap_cfg2_t tap_cfg2;
+ lsm6dso32x_md2_cfg_t md2_cfg;
+ lsm6dso32x_md1_cfg_t md1_cfg;
+ lsm6dso32x_ctrl4_c_t ctrl4_c;
+ int32_t ret;
+ int1_ctrl.int1_drdy_xl = val.drdy_xl;
+ int1_ctrl.int1_drdy_g = val.drdy_g;
+ int1_ctrl.int1_boot = val.boot;
+ int1_ctrl.int1_fifo_th = val.fifo_th;
+ int1_ctrl.int1_fifo_ovr = val.fifo_ovr;
+ int1_ctrl.int1_fifo_full = val.fifo_full;
+ int1_ctrl.int1_cnt_bdr = val.fifo_bdr;
+ int1_ctrl.den_drdy_flag = val.den_flag;
+ md1_cfg.int1_shub = val.sh_endop;
+ md1_cfg.int1_6d = val.six_d;
+ md1_cfg.int1_double_tap = val.double_tap;
+ md1_cfg.int1_ff = val.free_fall;
+ md1_cfg.int1_wu = val.wake_up;
+ md1_cfg.int1_single_tap = val.single_tap;
+ md1_cfg.int1_sleep_change = val.sleep_change;
+ emb_func_int1.int1_step_detector = val.step_detector;
+ emb_func_int1.int1_tilt = val.tilt;
+ emb_func_int1.int1_sig_mot = val.sig_mot;
+ emb_func_int1.int1_fsm_lc = val.fsm_lc;
+ fsm_int1_a.int1_fsm1 = val.fsm1;
+ fsm_int1_a.int1_fsm2 = val.fsm2;
+ fsm_int1_a.int1_fsm3 = val.fsm3;
+ fsm_int1_a.int1_fsm4 = val.fsm4;
+ fsm_int1_a.int1_fsm5 = val.fsm5;
+ fsm_int1_a.int1_fsm6 = val.fsm6;
+ fsm_int1_a.int1_fsm7 = val.fsm7;
+ fsm_int1_a.int1_fsm8 = val.fsm8;
+ fsm_int1_b.int1_fsm9 = val.fsm9 ;
+ fsm_int1_b.int1_fsm10 = val.fsm10;
+ fsm_int1_b.int1_fsm11 = val.fsm11;
+ fsm_int1_b.int1_fsm12 = val.fsm12;
+ fsm_int1_b.int1_fsm13 = val.fsm13;
+ fsm_int1_b.int1_fsm14 = val.fsm14;
+ fsm_int1_b.int1_fsm15 = val.fsm15;
+ fsm_int1_b.int1_fsm16 = val.fsm16;
+ mlc_int1.int1_mlc1 = val.mlc1;
+ mlc_int1.int1_mlc2 = val.mlc2;
+ mlc_int1.int1_mlc3 = val.mlc3;
+ mlc_int1.int1_mlc4 = val.mlc4;
+ mlc_int1.int1_mlc5 = val.mlc5;
+ mlc_int1.int1_mlc6 = val.mlc6;
+ mlc_int1.int1_mlc7 = val.mlc7;
+ mlc_int1.int1_mlc8 = val.mlc8;
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ if ((val.drdy_temp | val.timestamp) != PROPERTY_DISABLE)
+ {
+ ctrl4_c.int2_on_int1 = PROPERTY_ENABLE;
+ }
+
+ else
+ {
+ ctrl4_c.int2_on_int1 = PROPERTY_DISABLE;
+ }
+
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MLC_INT1,
+ (uint8_t *)&mlc_int1, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_INT1,
+ (uint8_t *)&emb_func_int1, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_INT1_A,
+ (uint8_t *)&fsm_int1_a, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_INT1_B,
+ (uint8_t *)&fsm_int1_b, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ if (ret == 0)
+ {
+ if ((emb_func_int1.int1_fsm_lc
+ | emb_func_int1.int1_sig_mot
+ | emb_func_int1.int1_step_detector
+ | emb_func_int1.int1_tilt
+ | fsm_int1_a.int1_fsm1
+ | fsm_int1_a.int1_fsm2
+ | fsm_int1_a.int1_fsm3
+ | fsm_int1_a.int1_fsm4
+ | fsm_int1_a.int1_fsm5
+ | fsm_int1_a.int1_fsm6
+ | fsm_int1_a.int1_fsm7
+ | fsm_int1_a.int1_fsm8
+ | fsm_int1_b.int1_fsm9
+ | fsm_int1_b.int1_fsm10
+ | fsm_int1_b.int1_fsm11
+ | fsm_int1_b.int1_fsm12
+ | fsm_int1_b.int1_fsm13
+ | fsm_int1_b.int1_fsm14
+ | fsm_int1_b.int1_fsm15
+ | fsm_int1_b.int1_fsm16
+ | mlc_int1.int1_mlc1
+ | mlc_int1.int1_mlc2
+ | mlc_int1.int1_mlc3
+ | mlc_int1.int1_mlc4
+ | mlc_int1.int1_mlc5
+ | mlc_int1.int1_mlc6
+ | mlc_int1.int1_mlc7
+ | mlc_int1.int1_mlc8) != PROPERTY_DISABLE)
+ {
+ md1_cfg.int1_emb_func = PROPERTY_ENABLE;
+ }
+
+ else
+ {
+ md1_cfg.int1_emb_func = PROPERTY_DISABLE;
+ }
+
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_INT1_CTRL,
+ (uint8_t *)&int1_ctrl, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MD1_CFG,
+ (uint8_t *)&md1_cfg, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT2_CTRL,
+ (uint8_t *)&int2_ctrl, 1);
+ }
+
+ if (ret == 0)
+ {
+ int2_ctrl.int2_drdy_temp = val.drdy_temp;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_INT2_CTRL,
+ (uint8_t *)&int2_ctrl, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MD2_CFG,
+ (uint8_t *)&md2_cfg, 1);
+ }
+
+ if (ret == 0)
+ {
+ md2_cfg.int2_timestamp = val.timestamp;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MD2_CFG,
+ (uint8_t *)&md2_cfg, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG2,
+ (uint8_t *) &tap_cfg2, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_pin_int2_route_get(ctx, &pin_int2_route);
+ }
+
+ if (ret == 0)
+ {
+ if ((pin_int2_route.fifo_bdr
+ | pin_int2_route.drdy_g
+ | pin_int2_route.drdy_temp
+ | pin_int2_route.drdy_xl
+ | pin_int2_route.fifo_full
+ | pin_int2_route.fifo_ovr
+ | pin_int2_route.fifo_th
+ | pin_int2_route.six_d
+ | pin_int2_route.double_tap
+ | pin_int2_route.free_fall
+ | pin_int2_route.wake_up
+ | pin_int2_route.single_tap
+ | pin_int2_route.sleep_change
+ | int1_ctrl.den_drdy_flag
+ | int1_ctrl.int1_boot
+ | int1_ctrl.int1_cnt_bdr
+ | int1_ctrl.int1_drdy_g
+ | int1_ctrl.int1_drdy_xl
+ | int1_ctrl.int1_fifo_full
+ | int1_ctrl.int1_fifo_ovr
+ | int1_ctrl.int1_fifo_th
+ | md1_cfg.int1_shub
+ | md1_cfg.int1_6d
+ | md1_cfg.int1_double_tap
+ | md1_cfg.int1_ff
+ | md1_cfg.int1_wu
+ | md1_cfg.int1_single_tap
+ | md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
+ {
+ tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
+ }
+
+ else
+ {
+ tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
+ }
+
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG2,
+ (uint8_t *) &tap_cfg2, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Route interrupt signals on int1 pin.[get]
+ *
+ * @param ctx communication interface handler.(ptr)
+ * @param val the signals that are routed on int1 pin.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_pin_int1_route_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_pin_int1_route_t *val)
+{
+ lsm6dso32x_emb_func_int1_t emb_func_int1;
+ lsm6dso32x_fsm_int1_a_t fsm_int1_a;
+ lsm6dso32x_fsm_int1_b_t fsm_int1_b;
+ lsm6dso32x_int1_ctrl_t int1_ctrl;
+ lsm6dso32x_int2_ctrl_t int2_ctrl;
+ lsm6dso32x_mlc_int1_t mlc_int1;
+ lsm6dso32x_md2_cfg_t md2_cfg;
+ lsm6dso32x_md1_cfg_t md1_cfg;
+ lsm6dso32x_ctrl4_c_t ctrl4_c;
+ int32_t ret;
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MLC_INT1,
+ (uint8_t *)&mlc_int1, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_INT1,
+ (uint8_t *)&emb_func_int1, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_INT1_A,
+ (uint8_t *)&fsm_int1_a, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_INT1_B,
+ (uint8_t *)&fsm_int1_b, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT1_CTRL,
+ (uint8_t *)&int1_ctrl, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MD1_CFG,
+ (uint8_t *)&md1_cfg, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
+ }
+
+ if (ctrl4_c.int2_on_int1 == PROPERTY_ENABLE)
+ {
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT2_CTRL,
+ (uint8_t *)&int2_ctrl, 1);
+ val->drdy_temp = int2_ctrl.int2_drdy_temp;
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MD2_CFG,
+ (uint8_t *)&md2_cfg, 1);
+ val->timestamp = md2_cfg.int2_timestamp;
+ }
+ }
+
+ else
+ {
+ val->drdy_temp = PROPERTY_DISABLE;
+ val->timestamp = PROPERTY_DISABLE;
+ }
+
+ val->drdy_xl = int1_ctrl.int1_drdy_xl;
+ val->drdy_g = int1_ctrl.int1_drdy_g;
+ val->boot = int1_ctrl.int1_boot;
+ val->fifo_th = int1_ctrl.int1_fifo_th;
+ val->fifo_ovr = int1_ctrl.int1_fifo_ovr;
+ val->fifo_full = int1_ctrl.int1_fifo_full;
+ val->fifo_bdr = int1_ctrl.int1_cnt_bdr;
+ val->den_flag = int1_ctrl.den_drdy_flag;
+ val->sh_endop = md1_cfg.int1_shub;
+ val->six_d = md1_cfg.int1_6d;
+ val->double_tap = md1_cfg.int1_double_tap;
+ val->free_fall = md1_cfg.int1_ff;
+ val->wake_up = md1_cfg.int1_wu;
+ val->single_tap = md1_cfg.int1_single_tap;
+ val->sleep_change = md1_cfg.int1_sleep_change;
+ val->step_detector = emb_func_int1.int1_step_detector;
+ val->tilt = emb_func_int1.int1_tilt;
+ val->sig_mot = emb_func_int1.int1_sig_mot;
+ val->fsm_lc = emb_func_int1.int1_fsm_lc;
+ val->fsm1 = fsm_int1_a.int1_fsm1;
+ val->fsm2 = fsm_int1_a.int1_fsm2;
+ val->fsm3 = fsm_int1_a.int1_fsm3;
+ val->fsm4 = fsm_int1_a.int1_fsm4;
+ val->fsm5 = fsm_int1_a.int1_fsm5;
+ val->fsm6 = fsm_int1_a.int1_fsm6;
+ val->fsm7 = fsm_int1_a.int1_fsm7;
+ val->fsm8 = fsm_int1_a.int1_fsm8;
+ val->fsm9 = fsm_int1_b.int1_fsm9;
+ val->fsm10 = fsm_int1_b.int1_fsm10;
+ val->fsm11 = fsm_int1_b.int1_fsm11;
+ val->fsm12 = fsm_int1_b.int1_fsm12;
+ val->fsm13 = fsm_int1_b.int1_fsm13;
+ val->fsm14 = fsm_int1_b.int1_fsm14;
+ val->fsm15 = fsm_int1_b.int1_fsm15;
+ val->fsm16 = fsm_int1_b.int1_fsm16;
+ val->mlc1 = mlc_int1.int1_mlc1;
+ val->mlc2 = mlc_int1.int1_mlc2;
+ val->mlc3 = mlc_int1.int1_mlc3;
+ val->mlc4 = mlc_int1.int1_mlc4;
+ val->mlc5 = mlc_int1.int1_mlc5;
+ val->mlc6 = mlc_int1.int1_mlc6;
+ val->mlc7 = mlc_int1.int1_mlc7;
+ val->mlc8 = mlc_int1.int1_mlc8;
+
+ return ret;
+}
+
+/**
+ * @brief Route interrupt signals on int2 pin.[set]
+ *
+ * @param ctx communication interface handler. Use NULL to ignore
+ * this interface.(ptr)
+ * @param val the signals to route on int2 pin.
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_pin_int2_route_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_pin_int2_route_t val)
+{
+ lsm6dso32x_pin_int1_route_t pin_int1_route;
+ lsm6dso32x_emb_func_int2_t emb_func_int2;
+ lsm6dso32x_fsm_int2_a_t fsm_int2_a;
+ lsm6dso32x_fsm_int2_b_t fsm_int2_b;
+ lsm6dso32x_int2_ctrl_t int2_ctrl;
+ lsm6dso32x_mlc_int2_t mlc_int2;
+ lsm6dso32x_tap_cfg2_t tap_cfg2;
+ lsm6dso32x_md2_cfg_t md2_cfg;
+ lsm6dso32x_ctrl4_c_t ctrl4_c;
+ int32_t ret;
+ ret = 0;
+
+ if (ctx != NULL)
+ {
+ int2_ctrl.int2_drdy_xl = val.drdy_xl;
+ int2_ctrl.int2_drdy_g = val.drdy_g;
+ int2_ctrl.int2_drdy_temp = val.drdy_temp;
+ int2_ctrl.int2_fifo_th = val.fifo_th;
+ int2_ctrl.int2_fifo_ovr = val.fifo_ovr;
+ int2_ctrl.int2_fifo_full = val.fifo_full;
+ int2_ctrl.int2_cnt_bdr = val.fifo_bdr;
+ md2_cfg.int2_timestamp = val.timestamp;
+ md2_cfg.int2_6d = val.six_d;
+ md2_cfg.int2_double_tap = val.double_tap;
+ md2_cfg.int2_ff = val.free_fall;
+ md2_cfg.int2_wu = val.wake_up;
+ md2_cfg.int2_single_tap = val.single_tap;
+ md2_cfg.int2_sleep_change = val.sleep_change;
+ emb_func_int2. int2_step_detector = val.step_detector;
+ emb_func_int2.int2_tilt = val.tilt;
+ emb_func_int2.int2_fsm_lc = val.fsm_lc;
+ fsm_int2_a.int2_fsm1 = val.fsm1;
+ fsm_int2_a.int2_fsm2 = val.fsm2;
+ fsm_int2_a.int2_fsm3 = val.fsm3;
+ fsm_int2_a.int2_fsm4 = val.fsm4;
+ fsm_int2_a.int2_fsm5 = val.fsm5;
+ fsm_int2_a.int2_fsm6 = val.fsm6;
+ fsm_int2_a.int2_fsm7 = val.fsm7;
+ fsm_int2_a.int2_fsm8 = val.fsm8;
+ fsm_int2_b.int2_fsm9 = val.fsm9 ;
+ fsm_int2_b.int2_fsm10 = val.fsm10;
+ fsm_int2_b.int2_fsm11 = val.fsm11;
+ fsm_int2_b.int2_fsm12 = val.fsm12;
+ fsm_int2_b.int2_fsm13 = val.fsm13;
+ fsm_int2_b.int2_fsm14 = val.fsm14;
+ fsm_int2_b.int2_fsm15 = val.fsm15;
+ fsm_int2_b.int2_fsm16 = val.fsm16;
+ mlc_int2.int2_mlc1 = val.mlc1;
+ mlc_int2.int2_mlc2 = val.mlc2;
+ mlc_int2.int2_mlc3 = val.mlc3;
+ mlc_int2.int2_mlc4 = val.mlc4;
+ mlc_int2.int2_mlc5 = val.mlc5;
+ mlc_int2.int2_mlc6 = val.mlc6;
+ mlc_int2.int2_mlc7 = val.mlc7;
+ mlc_int2.int2_mlc8 = val.mlc8;
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ if ((val.drdy_temp | val.timestamp) != PROPERTY_DISABLE)
+ {
+ ctrl4_c.int2_on_int1 = PROPERTY_DISABLE;
+ }
+
+ else
+ {
+ ctrl4_c.int2_on_int1 = PROPERTY_ENABLE;
+ }
+
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
+ }
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MLC_INT2,
+ (uint8_t *)&mlc_int2, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_INT2,
+ (uint8_t *)&emb_func_int2, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_INT2_A,
+ (uint8_t *)&fsm_int2_a, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_INT2_B,
+ (uint8_t *)&fsm_int2_b, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ if (ret == 0)
+ {
+ if ((emb_func_int2.int2_fsm_lc
+ | emb_func_int2.int2_sig_mot
+ | emb_func_int2.int2_step_detector
+ | emb_func_int2.int2_tilt
+ | fsm_int2_a.int2_fsm1
+ | fsm_int2_a.int2_fsm2
+ | fsm_int2_a.int2_fsm3
+ | fsm_int2_a.int2_fsm4
+ | fsm_int2_a.int2_fsm5
+ | fsm_int2_a.int2_fsm6
+ | fsm_int2_a.int2_fsm7
+ | fsm_int2_a.int2_fsm8
+ | fsm_int2_b.int2_fsm9
+ | fsm_int2_b.int2_fsm10
+ | fsm_int2_b.int2_fsm11
+ | fsm_int2_b.int2_fsm12
+ | fsm_int2_b.int2_fsm13
+ | fsm_int2_b.int2_fsm14
+ | fsm_int2_b.int2_fsm15
+ | fsm_int2_b.int2_fsm16
+ | mlc_int2.int2_mlc1
+ | mlc_int2.int2_mlc2
+ | mlc_int2.int2_mlc3
+ | mlc_int2.int2_mlc4
+ | mlc_int2.int2_mlc5
+ | mlc_int2.int2_mlc6
+ | mlc_int2.int2_mlc7
+ | mlc_int2.int2_mlc8) != PROPERTY_DISABLE)
+ {
+ md2_cfg.int2_emb_func = PROPERTY_ENABLE;
+ }
+
+ else
+ {
+ md2_cfg.int2_emb_func = PROPERTY_DISABLE;
+ }
+
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_INT2_CTRL,
+ (uint8_t *)&int2_ctrl, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MD2_CFG,
+ (uint8_t *)&md2_cfg, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG2,
+ (uint8_t *) &tap_cfg2, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_pin_int1_route_get(ctx, &pin_int1_route);
+ }
+
+ if (ret == 0)
+ {
+ if ((val.fifo_bdr
+ | val.drdy_g
+ | val.drdy_temp
+ | val.drdy_xl
+ | val.fifo_full
+ | val.fifo_ovr
+ | val.fifo_th
+ | val.six_d
+ | val.double_tap
+ | val.free_fall
+ | val.wake_up
+ | val.single_tap
+ | val.sleep_change
+ | pin_int1_route.den_flag
+ | pin_int1_route.boot
+ | pin_int1_route.fifo_bdr
+ | pin_int1_route.drdy_g
+ | pin_int1_route.drdy_xl
+ | pin_int1_route.fifo_full
+ | pin_int1_route.fifo_ovr
+ | pin_int1_route.fifo_th
+ | pin_int1_route.six_d
+ | pin_int1_route.double_tap
+ | pin_int1_route.free_fall
+ | pin_int1_route.wake_up
+ | pin_int1_route.single_tap
+ | pin_int1_route.sleep_change) != PROPERTY_DISABLE)
+ {
+ tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
+ }
+
+ else
+ {
+ tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
+ }
+
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG2,
+ (uint8_t *) &tap_cfg2, 1);
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Route interrupt signals on int2 pin.[get]
+ *
+ * @param ctx communication interface handler. Use NULL to ignore
+ * this interface.(ptr)
+ * @param val the signals that are routed on int2 pin.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_pin_int2_route_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_pin_int2_route_t *val)
+{
+ lsm6dso32x_emb_func_int2_t emb_func_int2;
+ lsm6dso32x_fsm_int2_a_t fsm_int2_a;
+ lsm6dso32x_fsm_int2_b_t fsm_int2_b;
+ lsm6dso32x_int2_ctrl_t int2_ctrl;
+ lsm6dso32x_mlc_int2_t mlc_int2;
+ lsm6dso32x_md2_cfg_t md2_cfg;
+ lsm6dso32x_ctrl4_c_t ctrl4_c;
+ int32_t ret;
+ ret = 0;
+
+ if (ctx != NULL)
+ {
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MLC_INT2,
+ (uint8_t *)&mlc_int2, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_INT2,
+ (uint8_t *)&emb_func_int2, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_INT2_A,
+ (uint8_t *)&fsm_int2_a, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_INT2_B,
+ (uint8_t *)&fsm_int2_b, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT2_CTRL,
+ (uint8_t *)&int2_ctrl, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MD2_CFG,
+ (uint8_t *)&md2_cfg, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C,
+ (uint8_t *)&ctrl4_c, 1);
+ }
+
+ if (ctrl4_c.int2_on_int1 == PROPERTY_DISABLE)
+ {
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT2_CTRL,
+ (uint8_t *)&int2_ctrl, 1);
+ val->drdy_temp = int2_ctrl.int2_drdy_temp;
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MD2_CFG,
+ (uint8_t *)&md2_cfg, 1);
+ val->timestamp = md2_cfg.int2_timestamp;
+ }
+ }
+
+ else
+ {
+ val->drdy_temp = PROPERTY_DISABLE;
+ val->timestamp = PROPERTY_DISABLE;
+ }
+
+ val->drdy_xl = int2_ctrl.int2_drdy_xl;
+ val->drdy_g = int2_ctrl.int2_drdy_g;
+ val->drdy_temp = int2_ctrl.int2_drdy_temp;
+ val->fifo_th = int2_ctrl.int2_fifo_th;
+ val->fifo_ovr = int2_ctrl.int2_fifo_ovr;
+ val->fifo_full = int2_ctrl.int2_fifo_full;
+ val->fifo_bdr = int2_ctrl.int2_cnt_bdr;
+ val->timestamp = md2_cfg.int2_timestamp;
+ val->six_d = md2_cfg.int2_6d;
+ val->double_tap = md2_cfg.int2_double_tap;
+ val->free_fall = md2_cfg.int2_ff;
+ val->wake_up = md2_cfg.int2_wu;
+ val->single_tap = md2_cfg.int2_single_tap;
+ val->sleep_change = md2_cfg.int2_sleep_change;
+ val->step_detector = emb_func_int2. int2_step_detector;
+ val->tilt = emb_func_int2.int2_tilt;
+ val->fsm_lc = emb_func_int2.int2_fsm_lc;
+ val->fsm1 = fsm_int2_a.int2_fsm1;
+ val->fsm2 = fsm_int2_a.int2_fsm2;
+ val->fsm3 = fsm_int2_a.int2_fsm3;
+ val->fsm4 = fsm_int2_a.int2_fsm4;
+ val->fsm5 = fsm_int2_a.int2_fsm5;
+ val->fsm6 = fsm_int2_a.int2_fsm6;
+ val->fsm7 = fsm_int2_a.int2_fsm7;
+ val->fsm8 = fsm_int2_a.int2_fsm8;
+ val->fsm9 = fsm_int2_b.int2_fsm9;
+ val->fsm10 = fsm_int2_b.int2_fsm10;
+ val->fsm11 = fsm_int2_b.int2_fsm11;
+ val->fsm12 = fsm_int2_b.int2_fsm12;
+ val->fsm13 = fsm_int2_b.int2_fsm13;
+ val->fsm14 = fsm_int2_b.int2_fsm14;
+ val->fsm15 = fsm_int2_b.int2_fsm15;
+ val->fsm16 = fsm_int2_b.int2_fsm16;
+ val->mlc1 = mlc_int2.int2_mlc1;
+ val->mlc2 = mlc_int2.int2_mlc2;
+ val->mlc3 = mlc_int2.int2_mlc3;
+ val->mlc4 = mlc_int2.int2_mlc4;
+ val->mlc5 = mlc_int2.int2_mlc5;
+ val->mlc6 = mlc_int2.int2_mlc6;
+ val->mlc7 = mlc_int2.int2_mlc7;
+ val->mlc8 = mlc_int2.int2_mlc8;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Get the status of all the interrupt sources.[get]
+ *
+ * @param ctx communication interface handler.(ptr)
+ * @param val the status of all the interrupt sources.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_all_sources_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_all_sources_t *val)
+{
+ lsm6dso32x_emb_func_status_mainpage_t emb_func_status_mainpage;
+ lsm6dso32x_status_master_mainpage_t status_master_mainpage;
+ lsm6dso32x_fsm_status_a_mainpage_t fsm_status_a_mainpage;
+ lsm6dso32x_fsm_status_b_mainpage_t fsm_status_b_mainpage;
+ lsm6dso32x_mlc_status_mainpage_t mlc_status_mainpage;
+ lsm6dso32x_fifo_status1_t fifo_status1;
+ lsm6dso32x_fifo_status2_t fifo_status2;
+ lsm6dso32x_all_int_src_t all_int_src;
+ lsm6dso32x_wake_up_src_t wake_up_src;
+ lsm6dso32x_status_reg_t status_reg;
+ lsm6dso32x_tap_src_t tap_src;
+ lsm6dso32x_d6d_src_t d6d_src;
+ lsm6dso32x_ctrl5_c_t ctrl5_c;
+ uint8_t reg[12];
+ int32_t ret;
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL5_C,
+ (uint8_t *)&ctrl5_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl5_c.not_used_01 = PROPERTY_ENABLE;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL5_C,
+ (uint8_t *)&ctrl5_c, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_ALL_INT_SRC, reg, 12);
+ }
+
+ if (ret == 0)
+ {
+ bytecpy((uint8_t *)&all_int_src, ®[0]);
+ bytecpy((uint8_t *)&wake_up_src, ®[1]);
+ bytecpy((uint8_t *)&tap_src, ®[2]);
+ bytecpy((uint8_t *)&d6d_src, ®[3]);
+ bytecpy((uint8_t *)&status_reg, ®[4]);
+ bytecpy((uint8_t *)&emb_func_status_mainpage, ®[5]);
+ bytecpy((uint8_t *)&fsm_status_a_mainpage, ®[6]);
+ bytecpy((uint8_t *)&fsm_status_b_mainpage, ®[7]);
+ bytecpy((uint8_t *)&mlc_status_mainpage, ®[8]);
+ bytecpy((uint8_t *)&status_master_mainpage, ®[9]);
+ bytecpy((uint8_t *)&fifo_status1, ®[10]);
+ bytecpy((uint8_t *)&fifo_status2, ®[11]);
+ val->timestamp = all_int_src.timestamp_endcount;
+ val->wake_up_z = wake_up_src.z_wu;
+ val->wake_up_y = wake_up_src.y_wu;
+ val->wake_up_x = wake_up_src.x_wu;
+ val->wake_up = wake_up_src.wu_ia;
+ val->sleep_state = wake_up_src.sleep_state;
+ val->free_fall = wake_up_src.ff_ia;
+ val->sleep_change = wake_up_src.sleep_change_ia;
+ val->tap_x = tap_src.x_tap;
+ val->tap_y = tap_src.y_tap;
+ val->tap_z = tap_src.z_tap;
+ val->tap_sign = tap_src.tap_sign;
+ val->double_tap = tap_src.double_tap;
+ val->single_tap = tap_src.single_tap;
+ val->six_d_xl = d6d_src.xl;
+ val->six_d_xh = d6d_src.xh;
+ val->six_d_yl = d6d_src.yl;
+ val->six_d_yh = d6d_src.yh;
+ val->six_d_zl = d6d_src.zl;
+ val->six_d_zh = d6d_src.zh;
+ val->six_d = d6d_src.d6d_ia;
+ val->den_flag = d6d_src.den_drdy;
+ val->drdy_xl = status_reg.xlda;
+ val->drdy_g = status_reg.gda;
+ val->drdy_temp = status_reg.tda;
+ val->step_detector = emb_func_status_mainpage.is_step_det;
+ val->tilt = emb_func_status_mainpage.is_tilt;
+ val->sig_mot = emb_func_status_mainpage.is_sigmot;
+ val->fsm_lc = emb_func_status_mainpage.is_fsm_lc;
+ val->fsm1 = fsm_status_a_mainpage.is_fsm1;
+ val->fsm2 = fsm_status_a_mainpage.is_fsm2;
+ val->fsm3 = fsm_status_a_mainpage.is_fsm3;
+ val->fsm4 = fsm_status_a_mainpage.is_fsm4;
+ val->fsm5 = fsm_status_a_mainpage.is_fsm5;
+ val->fsm6 = fsm_status_a_mainpage.is_fsm6;
+ val->fsm7 = fsm_status_a_mainpage.is_fsm7;
+ val->fsm8 = fsm_status_a_mainpage.is_fsm8;
+ val->fsm9 = fsm_status_b_mainpage.is_fsm9;
+ val->fsm10 = fsm_status_b_mainpage.is_fsm10;
+ val->fsm11 = fsm_status_b_mainpage.is_fsm11;
+ val->fsm12 = fsm_status_b_mainpage.is_fsm12;
+ val->fsm13 = fsm_status_b_mainpage.is_fsm13;
+ val->fsm14 = fsm_status_b_mainpage.is_fsm14;
+ val->fsm15 = fsm_status_b_mainpage.is_fsm15;
+ val->fsm16 = fsm_status_b_mainpage.is_fsm16;
+ val->mlc1 = mlc_status_mainpage.is_mlc1;
+ val->mlc2 = mlc_status_mainpage.is_mlc2;
+ val->mlc3 = mlc_status_mainpage.is_mlc3;
+ val->mlc4 = mlc_status_mainpage.is_mlc4;
+ val->mlc5 = mlc_status_mainpage.is_mlc5;
+ val->mlc6 = mlc_status_mainpage.is_mlc6;
+ val->mlc7 = mlc_status_mainpage.is_mlc7;
+ val->mlc8 = mlc_status_mainpage.is_mlc8;
+ val->sh_endop = status_master_mainpage.sens_hub_endop;
+ val->sh_slave0_nack = status_master_mainpage.slave0_nack;
+ val->sh_slave1_nack = status_master_mainpage.slave1_nack;
+ val->sh_slave2_nack = status_master_mainpage.slave2_nack;
+ val->sh_slave3_nack = status_master_mainpage.slave3_nack;
+ val->sh_wr_once = status_master_mainpage.wr_once_done;
+ val->fifo_diff = (256U * fifo_status2.diff_fifo) +
+ fifo_status1.diff_fifo;
+ val->fifo_ovr_latched = fifo_status2.over_run_latched;
+ val->fifo_bdr = fifo_status2.counter_bdr_ia;
+ val->fifo_full = fifo_status2.fifo_full_ia;
+ val->fifo_ovr = fifo_status2.fifo_ovr_ia;
+ val->fifo_th = fifo_status2.fifo_wtm_ia;
+ ctrl5_c.not_used_01 = PROPERTY_DISABLE;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL5_C,
+ (uint8_t *)&ctrl5_c, 1);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Sensor conversion parameters selection.[set]
+ *
+ * @param ctx communication interface handler. Use NULL to ignore
+ * this interface.(ptr)
+ * @param val set the sensor conversion parameters by checking
+ * the constraints of the device.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_md_t *val)
+{
+ lsm6dso32x_func_cfg_access_t func_cfg_access;
+ lsm6dso32x_ctrl1_xl_t ctrl1_xl;
+ lsm6dso32x_ctrl8_xl_t ctrl8_xl;
+ lsm6dso32x_ctrl2_g_t ctrl2_g;
+ lsm6dso32x_ctrl3_c_t ctrl3_c;
+ lsm6dso32x_ctrl4_c_t ctrl4_c;
+ lsm6dso32x_ctrl5_c_t ctrl5_c;
+ lsm6dso32x_ctrl6_c_t ctrl6_c;
+ lsm6dso32x_ctrl7_g_t ctrl7_g;
+ uint8_t xl_hm_mode;
+ uint8_t g_hm_mode;
+ uint8_t xl_ulp_en;
+ uint8_t odr_gy;
+ uint8_t odr_xl;
+ uint8_t reg[8];
+ int32_t ret;
+
+ ret = 0;
+ /* FIXME: Remove warnings with STM32CubeIDE */
+ ctrl3_c.not_used_01 = 0;
+ ctrl4_c.not_used_01 = 0;
+ /* reading input configuration */
+ xl_hm_mode = ((uint8_t)val->ui.xl.odr & 0x10U) >> 4;
+ xl_ulp_en = ((uint8_t)val->ui.xl.odr & 0x20U) >> 5;
+ odr_xl = (uint8_t)val->ui.xl.odr & 0x0FU;
+ g_hm_mode = ((uint8_t)val->ui.gy.odr & 0x10U) >> 4;
+ odr_gy = (uint8_t)val->ui.gy.odr & 0x0FU;
+
+ /* reading registers to be configured */
+ if (ctx != NULL)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL1_XL, reg, 8);
+ bytecpy((uint8_t *)&ctrl1_xl, ®[0]);
+ bytecpy((uint8_t *)&ctrl2_g, ®[1]);
+ bytecpy((uint8_t *)&ctrl3_c, ®[2]);
+ bytecpy((uint8_t *)&ctrl4_c, ®[3]);
+ bytecpy((uint8_t *)&ctrl5_c, ®[4]);
+ bytecpy((uint8_t *)&ctrl6_c, ®[5]);
+ bytecpy((uint8_t *)&ctrl7_g, ®[6]);
+ bytecpy((uint8_t *)&ctrl8_xl, ®[7]);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FUNC_CFG_ACCESS,
+ (uint8_t *)&func_cfg_access, 1);
+ }
+
+ /* if toggle xl ultra low power mode, turn off xl before reconfigure */
+ if (ctrl5_c.xl_ulp_en != xl_ulp_en)
+ {
+ ctrl1_xl.odr_xl = (uint8_t) 0x00U;
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
+ }
+ }
+
+ /* Check the Finite State Machine data rate constraints */
+ if (val->fsm.sens != LSM6DSO32X_FSM_DISABLE)
+ {
+ switch (val->fsm.odr)
+ {
+ case LSM6DSO32X_FSM_12Hz5:
+ if ((val->fsm.sens != LSM6DSO32X_FSM_GY) && (odr_xl == 0x00U))
+ {
+ odr_xl = 0x01U;
+ }
+
+ if ((val->fsm.sens != LSM6DSO32X_FSM_XL) && (odr_gy == 0x00U))
+ {
+ xl_ulp_en = PROPERTY_DISABLE;
+ odr_gy = 0x01U;
+ }
+
+ break;
+
+ case LSM6DSO32X_FSM_26Hz:
+ if ((val->fsm.sens != LSM6DSO32X_FSM_GY) && (odr_xl < 0x02U))
+ {
+ odr_xl = 0x02U;
+ }
+
+ if ((val->fsm.sens != LSM6DSO32X_FSM_XL) && (odr_gy < 0x02U))
+ {
+ xl_ulp_en = PROPERTY_DISABLE;
+ odr_gy = 0x02U;
+ }
+
+ break;
+
+ case LSM6DSO32X_FSM_52Hz:
+ if ((val->fsm.sens != LSM6DSO32X_FSM_GY) && (odr_xl < 0x03U))
+ {
+ odr_xl = 0x03U;
+ }
+
+ if ((val->fsm.sens != LSM6DSO32X_FSM_XL) && (odr_gy < 0x03U))
+ {
+ xl_ulp_en = PROPERTY_DISABLE;
+ odr_gy = 0x03U;
+ }
+
+ break;
+
+ case LSM6DSO32X_FSM_104Hz:
+ if ((val->fsm.sens != LSM6DSO32X_FSM_GY) && (odr_xl < 0x04U))
+ {
+ odr_xl = 0x04U;
+ }
+
+ if ((val->fsm.sens != LSM6DSO32X_FSM_XL) && (odr_gy < 0x04U))
+ {
+ xl_ulp_en = PROPERTY_DISABLE;
+ odr_gy = 0x04U;
+ }
+
+ break;
+
+ default:
+ odr_xl = 0x00U;
+ odr_gy = 0x00U;
+ break;
+ }
+ }
+
+ /* Check the Machine Learning Core data rate constraints */
+ if (val->mlc.sens != LSM6DSO32X_MLC_DISABLE)
+ {
+ switch (val->mlc.odr)
+ {
+ case LSM6DSO32X_MLC_12Hz5:
+ if (odr_xl == 0x00U)
+ {
+ odr_xl = 0x01U;
+ }
+
+ if ((val->mlc.sens != LSM6DSO32X_MLC_XL) && (odr_gy == 0x00U))
+ {
+ xl_ulp_en = PROPERTY_DISABLE;
+ odr_gy = 0x01U;
+ }
+
+ break;
+
+ case LSM6DSO32X_MLC_26Hz:
+ if (odr_xl < 0x02U)
+ {
+ odr_xl = 0x02U;
+ }
+
+ if ((val->mlc.sens != LSM6DSO32X_MLC_XL) && (odr_gy < 0x02U))
+ {
+ xl_ulp_en = PROPERTY_DISABLE;
+ odr_gy = 0x02U;
+ }
+
+ break;
+
+ case LSM6DSO32X_MLC_52Hz:
+ if (odr_xl < 0x03U)
+ {
+ odr_xl = 0x03U;
+ }
+
+ if ((val->mlc.sens != LSM6DSO32X_MLC_XL) && (odr_gy < 0x03U))
+ {
+ xl_ulp_en = PROPERTY_DISABLE;
+ odr_gy = 0x03U;
+ }
+
+ break;
+
+ case LSM6DSO32X_MLC_104Hz:
+ if (odr_xl < 0x04U)
+ {
+ odr_xl = 0x04U;
+ }
+
+ if ((val->mlc.sens != LSM6DSO32X_MLC_XL) && (odr_gy < 0x04U))
+ {
+ xl_ulp_en = PROPERTY_DISABLE;
+ odr_gy = 0x04U;
+ }
+
+ break;
+
+ default:
+ odr_xl = 0x00U;
+ odr_gy = 0x00U;
+ break;
+ }
+ }
+
+ /* Updating the accelerometer data rate configuration */
+ switch ((ctrl5_c.xl_ulp_en << 5) | (ctrl6_c.xl_hm_mode << 4) |
+ ctrl1_xl.odr_xl)
+ {
+ case LSM6DSO32X_XL_UI_OFF:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_OFF;
+ break;
+
+ case LSM6DSO32X_XL_UI_12Hz5_HP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_12Hz5_HP;
+ break;
+
+ case LSM6DSO32X_XL_UI_26Hz_HP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_26Hz_HP;
+ break;
+
+ case LSM6DSO32X_XL_UI_52Hz_HP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_52Hz_HP;
+ break;
+
+ case LSM6DSO32X_XL_UI_104Hz_HP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_104Hz_HP;
+ break;
+
+ case LSM6DSO32X_XL_UI_208Hz_HP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_208Hz_HP;
+ break;
+
+ case LSM6DSO32X_XL_UI_416Hz_HP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_416Hz_HP;
+ break;
+
+ case LSM6DSO32X_XL_UI_833Hz_HP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_833Hz_HP;
+ break;
+
+ case LSM6DSO32X_XL_UI_1667Hz_HP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_1667Hz_HP;
+ break;
+
+ case LSM6DSO32X_XL_UI_3333Hz_HP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_3333Hz_HP;
+ break;
+
+ case LSM6DSO32X_XL_UI_6667Hz_HP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_6667Hz_HP;
+ break;
+
+ case LSM6DSO32X_XL_UI_1Hz6_LP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_1Hz6_LP;
+ break;
+
+ case LSM6DSO32X_XL_UI_12Hz5_LP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_12Hz5_LP;
+ break;
+
+ case LSM6DSO32X_XL_UI_26Hz_LP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_26Hz_LP;
+ break;
+
+ case LSM6DSO32X_XL_UI_52Hz_LP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_52Hz_LP;
+ break;
+
+ case LSM6DSO32X_XL_UI_104Hz_NM:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_104Hz_NM;
+ break;
+
+ case LSM6DSO32X_XL_UI_208Hz_NM:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_208Hz_NM;
+ break;
+
+ case LSM6DSO32X_XL_UI_1Hz6_ULP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_1Hz6_ULP;
+ break;
+
+ case LSM6DSO32X_XL_UI_12Hz5_ULP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_12Hz5_ULP;
+ break;
+
+ case LSM6DSO32X_XL_UI_26Hz_ULP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_26Hz_ULP;
+ break;
+
+ case LSM6DSO32X_XL_UI_52Hz_ULP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_52Hz_ULP;
+ break;
+
+ case LSM6DSO32X_XL_UI_104Hz_ULP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_104Hz_ULP;
+ break;
+
+ case LSM6DSO32X_XL_UI_208Hz_ULP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_208Hz_ULP;
+ break;
+
+ default:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_OFF;
+ break;
+ }
+
+ /* Updating the accelerometer data rate configuration */
+ switch ((ctrl7_g.g_hm_mode << 4) | ctrl2_g.odr_g)
+ {
+ case LSM6DSO32X_GY_UI_OFF:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_OFF;
+ break;
+
+ case LSM6DSO32X_GY_UI_12Hz5_LP:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_12Hz5_LP;
+ break;
+
+ case LSM6DSO32X_GY_UI_12Hz5_HP:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_12Hz5_HP;
+ break;
+
+ case LSM6DSO32X_GY_UI_26Hz_LP:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_26Hz_LP;
+ break;
+
+ case LSM6DSO32X_GY_UI_26Hz_HP:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_26Hz_HP;
+ break;
+
+ case LSM6DSO32X_GY_UI_52Hz_LP:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_52Hz_LP;
+ break;
+
+ case LSM6DSO32X_GY_UI_52Hz_HP:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_52Hz_HP;
+ break;
+
+ case LSM6DSO32X_GY_UI_104Hz_NM:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_104Hz_NM;
+ break;
+
+ case LSM6DSO32X_GY_UI_104Hz_HP:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_104Hz_HP;
+ break;
+
+ case LSM6DSO32X_GY_UI_208Hz_NM:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_208Hz_NM;
+ break;
+
+ case LSM6DSO32X_GY_UI_208Hz_HP:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_208Hz_HP;
+ break;
+
+ case LSM6DSO32X_GY_UI_416Hz_HP:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_416Hz_HP;
+ break;
+
+ case LSM6DSO32X_GY_UI_833Hz_HP:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_833Hz_HP;
+ break;
+
+ case LSM6DSO32X_GY_UI_1667Hz_HP:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_1667Hz_HP;
+ break;
+
+ case LSM6DSO32X_GY_UI_3333Hz_HP:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_3333Hz_HP;
+ break;
+
+ case LSM6DSO32X_GY_UI_6667Hz_HP:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_6667Hz_HP;
+ break;
+
+ default:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_OFF;
+ break;
+ }
+
+ /* prapare new configuration */
+ /* UI new configuration */
+ ctrl1_xl.odr_xl = odr_xl;
+ ctrl1_xl.fs_xl = (uint8_t)val->ui.xl.fs;
+ ctrl5_c.xl_ulp_en = xl_ulp_en;
+ ctrl6_c.xl_hm_mode = xl_hm_mode;
+ ctrl7_g.g_hm_mode = g_hm_mode;
+ ctrl2_g.odr_g = odr_gy;
+ ctrl2_g.fs_g = (uint8_t) val->ui.gy.fs;
+
+ /* writing checked configuration */
+ if (ctx != NULL)
+ {
+ bytecpy(®[0], (uint8_t *)&ctrl1_xl);
+ bytecpy(®[1], (uint8_t *)&ctrl2_g);
+ bytecpy(®[2], (uint8_t *)&ctrl3_c);
+ bytecpy(®[3], (uint8_t *)&ctrl4_c);
+ bytecpy(®[4], (uint8_t *)&ctrl5_c);
+ bytecpy(®[5], (uint8_t *)&ctrl6_c);
+ bytecpy(®[6], (uint8_t *)&ctrl7_g);
+ bytecpy(®[7], (uint8_t *)&ctrl8_xl);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®,
+ 8);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FUNC_CFG_ACCESS,
+ (uint8_t *)&func_cfg_access, 1);
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Sensor conversion parameters selection.[get]
+ *
+ * @param ctx communication interface handler. Use NULL to ignore
+ * this interface.(ptr)
+ * @param val get the sensor conversion parameters.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_md_t *val)
+{
+ lsm6dso32x_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
+ lsm6dso32x_emb_func_odr_cfg_c_t emb_func_odr_cfg_c;
+ lsm6dso32x_func_cfg_access_t func_cfg_access;
+ lsm6dso32x_emb_func_en_b_t emb_func_en_b;
+ lsm6dso32x_fsm_enable_a_t fsm_enable_a;
+ lsm6dso32x_fsm_enable_b_t fsm_enable_b;
+ lsm6dso32x_ctrl1_xl_t ctrl1_xl;
+ lsm6dso32x_ctrl2_g_t ctrl2_g;
+ lsm6dso32x_ctrl3_c_t ctrl3_c;
+ lsm6dso32x_ctrl4_c_t ctrl4_c;
+ lsm6dso32x_ctrl5_c_t ctrl5_c;
+ lsm6dso32x_ctrl6_c_t ctrl6_c;
+ lsm6dso32x_ctrl7_g_t ctrl7_g;
+ uint8_t reg[8];
+ int32_t ret;
+
+ ret = 0;
+
+ /* reading the registers of the device */
+ if (ctx != NULL)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL1_XL, reg, 7);
+ bytecpy((uint8_t *)&ctrl1_xl, ®[0]);
+ bytecpy((uint8_t *)&ctrl2_g, ®[1]);
+ bytecpy((uint8_t *)&ctrl3_c, ®[2]);
+ bytecpy((uint8_t *)&ctrl4_c, ®[3]);
+ bytecpy((uint8_t *)&ctrl5_c, ®[4]);
+ bytecpy((uint8_t *)&ctrl6_c, ®[5]);
+ bytecpy((uint8_t *)&ctrl7_g, ®[6]);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FUNC_CFG_ACCESS,
+ (uint8_t *)&func_cfg_access, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_ODR_CFG_B, reg, 2);
+ bytecpy((uint8_t *)&emb_func_odr_cfg_b, ®[0]);
+ bytecpy((uint8_t *)&emb_func_odr_cfg_c, ®[1]);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_B,
+ (uint8_t *)&emb_func_en_b, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_ENABLE_A, reg, 2);
+ bytecpy((uint8_t *)&fsm_enable_a, ®[0]);
+ bytecpy((uint8_t *)&fsm_enable_b, ®[1]);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+ }
+
+ /* fill the input structure */
+
+ /* get accelerometer configuration */
+ switch ((ctrl5_c.xl_ulp_en << 5) | (ctrl6_c.xl_hm_mode << 4) |
+ ctrl1_xl.odr_xl)
+ {
+ case LSM6DSO32X_XL_UI_OFF:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_OFF;
+ break;
+
+ case LSM6DSO32X_XL_UI_12Hz5_HP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_12Hz5_HP;
+ break;
+
+ case LSM6DSO32X_XL_UI_26Hz_HP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_26Hz_HP;
+ break;
+
+ case LSM6DSO32X_XL_UI_52Hz_HP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_52Hz_HP;
+ break;
+
+ case LSM6DSO32X_XL_UI_104Hz_HP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_104Hz_HP;
+ break;
+
+ case LSM6DSO32X_XL_UI_208Hz_HP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_208Hz_HP;
+ break;
+
+ case LSM6DSO32X_XL_UI_416Hz_HP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_416Hz_HP;
+ break;
+
+ case LSM6DSO32X_XL_UI_833Hz_HP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_833Hz_HP;
+ break;
+
+ case LSM6DSO32X_XL_UI_1667Hz_HP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_1667Hz_HP;
+ break;
+
+ case LSM6DSO32X_XL_UI_3333Hz_HP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_3333Hz_HP;
+ break;
+
+ case LSM6DSO32X_XL_UI_6667Hz_HP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_6667Hz_HP;
+ break;
+
+ case LSM6DSO32X_XL_UI_1Hz6_LP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_1Hz6_LP;
+ break;
+
+ case LSM6DSO32X_XL_UI_12Hz5_LP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_12Hz5_LP;
+ break;
+
+ case LSM6DSO32X_XL_UI_26Hz_LP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_26Hz_LP;
+ break;
+
+ case LSM6DSO32X_XL_UI_52Hz_LP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_52Hz_LP;
+ break;
+
+ case LSM6DSO32X_XL_UI_104Hz_NM:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_104Hz_NM;
+ break;
+
+ case LSM6DSO32X_XL_UI_208Hz_NM:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_208Hz_NM;
+ break;
+
+ case LSM6DSO32X_XL_UI_1Hz6_ULP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_1Hz6_ULP;
+ break;
+
+ case LSM6DSO32X_XL_UI_12Hz5_ULP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_12Hz5_ULP;
+ break;
+
+ case LSM6DSO32X_XL_UI_26Hz_ULP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_26Hz_ULP;
+ break;
+
+ case LSM6DSO32X_XL_UI_52Hz_ULP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_52Hz_ULP;
+ break;
+
+ case LSM6DSO32X_XL_UI_104Hz_ULP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_104Hz_ULP;
+ break;
+
+ case LSM6DSO32X_XL_UI_208Hz_ULP:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_208Hz_ULP;
+ break;
+
+ default:
+ val->ui.xl.odr = LSM6DSO32X_XL_UI_OFF;
+ break;
+ }
+
+ switch (ctrl1_xl.fs_xl)
+ {
+ case LSM6DSO32X_XL_UI_32g:
+ val->ui.xl.fs = LSM6DSO32X_XL_UI_32g;
+ break;
+
+ case LSM6DSO32X_XL_UI_4g:
+ val->ui.xl.fs = LSM6DSO32X_XL_UI_4g;
+ break;
+
+ case LSM6DSO32X_XL_UI_8g:
+ val->ui.xl.fs = LSM6DSO32X_XL_UI_8g;
+ break;
+
+ case LSM6DSO32X_XL_UI_16g:
+ val->ui.xl.fs = LSM6DSO32X_XL_UI_16g;
+ break;
+
+ default:
+ val->ui.xl.fs = LSM6DSO32X_XL_UI_4g;
+ break;
+ }
+
+ /* get gyroscope configuration */
+ switch ((ctrl7_g.g_hm_mode << 4) | ctrl2_g.odr_g)
+ {
+ case LSM6DSO32X_GY_UI_OFF:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_OFF;
+ break;
+
+ case LSM6DSO32X_GY_UI_12Hz5_LP:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_12Hz5_LP;
+ break;
+
+ case LSM6DSO32X_GY_UI_12Hz5_HP:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_12Hz5_HP;
+ break;
+
+ case LSM6DSO32X_GY_UI_26Hz_LP:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_26Hz_LP;
+ break;
+
+ case LSM6DSO32X_GY_UI_26Hz_HP:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_26Hz_HP;
+ break;
+
+ case LSM6DSO32X_GY_UI_52Hz_LP:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_52Hz_LP;
+ break;
+
+ case LSM6DSO32X_GY_UI_52Hz_HP:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_52Hz_HP;
+ break;
+
+ case LSM6DSO32X_GY_UI_104Hz_NM:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_104Hz_NM;
+ break;
+
+ case LSM6DSO32X_GY_UI_104Hz_HP:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_104Hz_HP;
+ break;
+
+ case LSM6DSO32X_GY_UI_208Hz_NM:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_208Hz_NM;
+ break;
+
+ case LSM6DSO32X_GY_UI_208Hz_HP:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_208Hz_HP;
+ break;
+
+ case LSM6DSO32X_GY_UI_416Hz_HP:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_416Hz_HP;
+ break;
+
+ case LSM6DSO32X_GY_UI_833Hz_HP:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_833Hz_HP;
+ break;
+
+ case LSM6DSO32X_GY_UI_1667Hz_HP:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_1667Hz_HP;
+ break;
+
+ case LSM6DSO32X_GY_UI_3333Hz_HP:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_3333Hz_HP;
+ break;
+
+ case LSM6DSO32X_GY_UI_6667Hz_HP:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_6667Hz_HP;
+ break;
+
+ default:
+ val->ui.gy.odr = LSM6DSO32X_GY_UI_OFF;
+ break;
+ }
+
+ switch (ctrl2_g.fs_g)
+ {
+ case LSM6DSO32X_GY_UI_125dps:
+ val->ui.gy.fs = LSM6DSO32X_GY_UI_125dps;
+ break;
+
+ case LSM6DSO32X_GY_UI_250dps:
+ val->ui.gy.fs = LSM6DSO32X_GY_UI_250dps;
+ break;
+
+ case LSM6DSO32X_GY_UI_500dps:
+ val->ui.gy.fs = LSM6DSO32X_GY_UI_500dps;
+ break;
+
+ case LSM6DSO32X_GY_UI_1000dps:
+ val->ui.gy.fs = LSM6DSO32X_GY_UI_1000dps;
+ break;
+
+ case LSM6DSO32X_GY_UI_2000dps:
+ val->ui.gy.fs = LSM6DSO32X_GY_UI_2000dps;
+ break;
+
+ default:
+ val->ui.gy.fs = LSM6DSO32X_GY_UI_125dps;
+ break;
+ }
+
+ /* get finite state machine configuration */
+ if ((fsm_enable_a.fsm1_en | fsm_enable_a.fsm2_en |
+ fsm_enable_a.fsm3_en |
+ fsm_enable_a.fsm4_en | fsm_enable_a.fsm5_en | fsm_enable_a.fsm6_en |
+ fsm_enable_a.fsm7_en | fsm_enable_a.fsm8_en | fsm_enable_b.fsm9_en |
+ fsm_enable_b.fsm10_en | fsm_enable_b.fsm11_en |
+ fsm_enable_b.fsm12_en | fsm_enable_b.fsm13_en |
+ fsm_enable_b.fsm14_en | fsm_enable_b.fsm15_en |
+ fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
+ {
+ switch (emb_func_odr_cfg_b.fsm_odr)
+ {
+ case LSM6DSO32X_FSM_12Hz5:
+ val->fsm.odr = LSM6DSO32X_FSM_12Hz5;
+ break;
+
+ case LSM6DSO32X_FSM_26Hz:
+ val->fsm.odr = LSM6DSO32X_FSM_26Hz;
+ break;
+
+ case LSM6DSO32X_FSM_52Hz:
+ val->fsm.odr = LSM6DSO32X_FSM_52Hz;
+ break;
+
+ case LSM6DSO32X_FSM_104Hz:
+ val->fsm.odr = LSM6DSO32X_FSM_104Hz;
+ break;
+
+ default:
+ val->fsm.odr = LSM6DSO32X_FSM_12Hz5;
+ break;
+ }
+
+ val->fsm.sens = LSM6DSO32X_FSM_XL_GY;
+
+ if (val->ui.gy.odr == LSM6DSO32X_GY_UI_OFF)
+ {
+ val->fsm.sens = LSM6DSO32X_FSM_XL;
+ }
+
+ if (val->ui.xl.odr == LSM6DSO32X_XL_UI_OFF)
+ {
+ val->fsm.sens = LSM6DSO32X_FSM_GY;
+ }
+ }
+
+ else
+ {
+ val->fsm.sens = LSM6DSO32X_FSM_DISABLE;
+ }
+
+ /* get machine learning core configuration */
+ if (emb_func_en_b.mlc_en == PROPERTY_ENABLE)
+ {
+ switch (emb_func_odr_cfg_c.mlc_odr)
+ {
+ case LSM6DSO32X_MLC_12Hz5:
+ val->mlc.odr = LSM6DSO32X_MLC_12Hz5;
+ break;
+
+ case LSM6DSO32X_MLC_26Hz:
+ val->mlc.odr = LSM6DSO32X_MLC_26Hz;
+ break;
+
+ case LSM6DSO32X_MLC_52Hz:
+ val->mlc.odr = LSM6DSO32X_MLC_52Hz;
+ break;
+
+ case LSM6DSO32X_MLC_104Hz:
+ val->mlc.odr = LSM6DSO32X_MLC_104Hz;
+ break;
+
+ default:
+ val->mlc.odr = LSM6DSO32X_MLC_12Hz5;
+ break;
+ }
+
+ val->mlc.sens = LSM6DSO32X_MLC_XL_GY;
+
+ if (val->ui.gy.odr == LSM6DSO32X_GY_UI_OFF)
+ {
+ val->mlc.sens = LSM6DSO32X_MLC_XL;
+ }
+
+ if (val->ui.xl.odr == LSM6DSO32X_XL_UI_OFF)
+ {
+ val->mlc.sens = LSM6DSO32X_MLC_DISABLE;
+ }
+ }
+
+ else
+ {
+ val->mlc.sens = LSM6DSO32X_MLC_DISABLE;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Read data in engineering unit.[get]
+ *
+ * @param ctx communication interface handler.(ptr)
+ * @param md the sensor conversion parameters.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_data_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_md_t *md,
+ lsm6dso32x_data_t *data)
+{
+ uint8_t buff[14];
+ int32_t ret;
+
+ uint8_t i;
+ uint8_t j;
+ ret = 0;
+
+ /* read data */
+ if (ctx != NULL)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_OUT_TEMP_L, buff, 14);
+ }
+
+ j = 0;
+ /* temperature conversion */
+ data->ui.heat.raw = (int16_t)buff[j + 1U];
+ data->ui.heat.raw = (((int16_t)data->ui.heat.raw * (int16_t)256) +
+ (int16_t)buff[j]);
+ j += 2U;
+ data->ui.heat.deg_c = lsm6dso32x_from_lsb_to_celsius((
+ int16_t)data->ui.heat.raw);
+
+ /* angular rate conversion */
+ for (i = 0U; i < 3U; i++)
+ {
+ data->ui.gy.raw[i] = (int16_t)buff[j + 1U];
+ data->ui.gy.raw[i] = (data->ui.gy.raw[i] * 256) + (int16_t) buff[j];
+ j += 2U;
+
+ switch (md->ui.gy.fs)
+ {
+ case LSM6DSO32X_GY_UI_250dps:
+ data->ui.gy.mdps[i] = lsm6dso32x_from_fs250_to_mdps(
+ data->ui.gy.raw[i]);
+ break;
+
+ case LSM6DSO32X_GY_UI_125dps:
+ data->ui.gy.mdps[i] = lsm6dso32x_from_fs125_to_mdps(
+ data->ui.gy.raw[i]);
+ break;
+
+ case LSM6DSO32X_GY_UI_500dps:
+ data->ui.gy.mdps[i] = lsm6dso32x_from_fs500_to_mdps(
+ data->ui.gy.raw[i]);
+ break;
+
+ case LSM6DSO32X_GY_UI_1000dps:
+ data->ui.gy.mdps[i] = lsm6dso32x_from_fs1000_to_mdps(
+ data->ui.gy.raw[i]);
+ break;
+
+ case LSM6DSO32X_GY_UI_2000dps:
+ data->ui.gy.mdps[i] = lsm6dso32x_from_fs2000_to_mdps(
+ data->ui.gy.raw[i]);
+ break;
+
+ default:
+ data->ui.gy.mdps[i] = 0.0f;
+ break;
+ }
+ }
+
+ /* acceleration conversion */
+ for (i = 0U; i < 3U; i++)
+ {
+ data->ui.xl.raw[i] = (int16_t)buff[j + 1U];
+ data->ui.xl.raw[i] = (data->ui.xl.raw[i] * 256) + (int16_t) buff[j];
+ j += 2U;
+
+ switch (md->ui.xl.fs)
+ {
+ case LSM6DSO32X_XL_UI_4g:
+ data->ui.xl.mg[i] = lsm6dso32x_from_fs4_to_mg(data->ui.xl.raw[i]);
+ break;
+
+ case LSM6DSO32X_XL_UI_32g:
+ data->ui.xl.mg[i] = lsm6dso32x_from_fs32_to_mg(data->ui.xl.raw[i]);
+ break;
+
+ case LSM6DSO32X_XL_UI_8g:
+ data->ui.xl.mg[i] = lsm6dso32x_from_fs8_to_mg(data->ui.xl.raw[i]);
+ break;
+
+ case LSM6DSO32X_XL_UI_16g:
+ data->ui.xl.mg[i] = lsm6dso32x_from_fs16_to_mg(data->ui.xl.raw[i]);
+ break;
+
+ default:
+ data->ui.xl.mg[i] = 0.0f;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Embedded functions.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of registers
+ * EMB_FUNC_EN_A e EMB_FUNC_EN_B.
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_embedded_sens_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_emb_sens_t *val)
+{
+ lsm6dso32x_emb_func_en_a_t emb_func_en_a;
+ lsm6dso32x_emb_func_en_b_t emb_func_en_b;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_A,
+ (uint8_t *)&emb_func_en_a, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_B,
+ (uint8_t *)&emb_func_en_b, 1);
+ emb_func_en_b.mlc_en = val->mlc;
+ emb_func_en_b.fsm_en = val->fsm;
+ emb_func_en_a.tilt_en = val->tilt;
+ emb_func_en_a.pedo_en = val->step;
+ emb_func_en_a.sign_motion_en = val->sig_mot;
+ emb_func_en_b.fifo_compr_en = val->fifo_compr;
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_A,
+ (uint8_t *)&emb_func_en_a, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_B,
+ (uint8_t *)&emb_func_en_b, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Embedded functions.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val get the values of registers
+ * EMB_FUNC_EN_A e EMB_FUNC_EN_B.
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_embedded_sens_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_emb_sens_t *emb_sens)
+{
+ lsm6dso32x_emb_func_en_a_t emb_func_en_a;
+ lsm6dso32x_emb_func_en_b_t emb_func_en_b;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_A,
+ (uint8_t *)&emb_func_en_a, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_B,
+ (uint8_t *)&emb_func_en_b, 1);
+ emb_sens->mlc = emb_func_en_b.mlc_en;
+ emb_sens->fsm = emb_func_en_b.fsm_en;
+ emb_sens->tilt = emb_func_en_a.tilt_en;
+ emb_sens->step = emb_func_en_a.pedo_en;
+ emb_sens->sig_mot = emb_func_en_a.sign_motion_en;
+ emb_sens->fifo_compr = emb_func_en_b.fifo_compr_en;
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief turn off all embedded functions.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val get the values of registers
+ * EMB_FUNC_EN_A e EMB_FUNC_EN_B.
+ * @retval interface status (MANDATORY: return 0 -> no Error).
+ *
+ */
+int32_t lsm6dso32x_embedded_sens_off(stmdev_ctx_t *ctx)
+{
+ lsm6dso32x_emb_func_en_a_t emb_func_en_a;
+ lsm6dso32x_emb_func_en_b_t emb_func_en_b;
+ int32_t ret;
+
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_A,
+ (uint8_t *)&emb_func_en_a, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_B,
+ (uint8_t *)&emb_func_en_b, 1);
+ emb_func_en_b.mlc_en = PROPERTY_DISABLE;
+ emb_func_en_b.fsm_en = PROPERTY_DISABLE;
+ emb_func_en_a.tilt_en = PROPERTY_DISABLE;
+ emb_func_en_a.pedo_en = PROPERTY_DISABLE;
+ emb_func_en_a.sign_motion_en = PROPERTY_DISABLE;
+ emb_func_en_b.fifo_compr_en = PROPERTY_DISABLE;
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_A,
+ (uint8_t *)&emb_func_en_a, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_B,
+ (uint8_t *)&emb_func_en_b, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @}
+ *
+ */
+
+/**
+ * @}
+ *
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/sensor/stmemsc/lsm6dso32x_STdC/driver/lsm6dso32x_reg.h b/sensor/stmemsc/lsm6dso32x_STdC/driver/lsm6dso32x_reg.h
new file mode 100644
index 0000000000000000000000000000000000000000..dee58bd41a10d05c937e65911ff2621cf3afe976
--- /dev/null
+++ b/sensor/stmemsc/lsm6dso32x_STdC/driver/lsm6dso32x_reg.h
@@ -0,0 +1,4333 @@
+/**
+ ******************************************************************************
+ * @file lsm6dso32x_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lsm6dso32x_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef LSM6DSO32X_REGS_H
+#define LSM6DSO32X_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include
+#include
+#include
+
+/** @addtogroup LSM6DSO32X
+ * @{
+ *
+ */
+
+/** @defgroup Endianness definitions
+ * @{
+ *
+ */
+
+#ifndef DRV_BYTE_ORDER
+#ifndef __BYTE_ORDER__
+
+#define DRV_LITTLE_ENDIAN 1234
+#define DRV_BIG_ENDIAN 4321
+
+/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
+ * by uncommenting the define which fits your platform endianness
+ */
+//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
+#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
+
+#else /* defined __BYTE_ORDER__ */
+
+#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
+#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
+#define DRV_BYTE_ORDER __BYTE_ORDER__
+
+#endif /* __BYTE_ORDER__*/
+#endif /* DRV_BYTE_ORDER */
+
+/**
+ * @}
+ *
+ */
+
+/** @defgroup STMicroelectronics sensors common types
+ * @{
+ *
+ */
+
+#ifndef MEMS_SHARED_TYPES
+#define MEMS_SHARED_TYPES
+
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
+} bitwise_t;
+
+#define PROPERTY_DISABLE (0U)
+#define PROPERTY_ENABLE (1U)
+
+/** @addtogroup Interfaces_Functions
+ * @brief This section provide a set of functions used to read and
+ * write a generic register of the device.
+ * MANDATORY: return 0 -> no Error.
+ * @{
+ *
+ */
+
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
+
+typedef struct
+{
+ /** Component mandatory fields **/
+ stmdev_write_ptr write_reg;
+ stmdev_read_ptr read_reg;
+ /** Customizable optional pointer **/
+ void *handle;
+} stmdev_ctx_t;
+
+/**
+ * @}
+ *
+ */
+
+#endif /* MEMS_SHARED_TYPES */
+
+#ifndef MEMS_UCF_SHARED_TYPES
+#define MEMS_UCF_SHARED_TYPES
+
+/** @defgroup Generic address-data structure definition
+ * @brief This structure is useful to load a predefined configuration
+ * of a sensor.
+ * You can create a sensor configuration by your own or using
+ * Unico / Unicleo tools available on STMicroelectronics
+ * web site.
+ *
+ * @{
+ *
+ */
+
+typedef struct
+{
+ uint8_t address;
+ uint8_t data;
+} ucf_line_t;
+
+/**
+ * @}
+ *
+ */
+
+#endif /* MEMS_UCF_SHARED_TYPES */
+
+/**
+ * @}
+ *
+ */
+
+/** @defgroup LSM6DSO32X_Infos
+ * @{
+ *
+ */
+
+/** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/
+#define LSM6DSO32X_I2C_ADD_L 0xD5U
+#define LSM6DSO32X_I2C_ADD_H 0xD7U
+
+/** Device Identification (Who am I) **/
+#define LSM6DSO32X_ID 0x6CU
+
+/**
+ * @}
+ *
+ */
+
+#define LSM6DSO32X_FUNC_CFG_ACCESS 0x01U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t not_used_01 : 6;
+uint8_t reg_access :
+ 2; /* shub_reg_access + func_cfg_access */
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+uint8_t reg_access :
+ 2; /* shub_reg_access + func_cfg_access */
+ uint8_t not_used_01 : 6;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_func_cfg_access_t;
+
+#define LSM6DSO32X_PIN_CTRL 0x02U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t not_used_01 : 6;
+ uint8_t sdo_pu_en : 1;
+ uint8_t not_used_02 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 1;
+ uint8_t sdo_pu_en : 1;
+ uint8_t not_used_01 : 6;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_pin_ctrl_t;
+
+#define LSM6DSO32X_FIFO_CTRL1 0x07U
+typedef struct
+{
+ uint8_t wtm : 8;
+} lsm6dso32x_fifo_ctrl1_t;
+
+#define LSM6DSO32X_FIFO_CTRL2 0x08U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t wtm : 1;
+ uint8_t uncoptr_rate : 2;
+ uint8_t not_used_01 : 1;
+ uint8_t odrchg_en : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t fifo_compr_rt_en : 1;
+ uint8_t stop_on_wtm : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t stop_on_wtm : 1;
+ uint8_t fifo_compr_rt_en : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t odrchg_en : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t uncoptr_rate : 2;
+ uint8_t wtm : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fifo_ctrl2_t;
+
+#define LSM6DSO32X_FIFO_CTRL3 0x09U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bdr_xl : 4;
+ uint8_t bdr_gy : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bdr_gy : 4;
+ uint8_t bdr_xl : 4;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fifo_ctrl3_t;
+
+#define LSM6DSO32X_FIFO_CTRL4 0x0AU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t fifo_mode : 3;
+ uint8_t not_used_01 : 1;
+ uint8_t odr_t_batch : 2;
+ uint8_t odr_ts_batch : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr_ts_batch : 2;
+ uint8_t odr_t_batch : 2;
+ uint8_t not_used_01 : 1;
+ uint8_t fifo_mode : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fifo_ctrl4_t;
+
+#define LSM6DSO32X_COUNTER_BDR_REG1 0x0BU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t cnt_bdr_th : 3;
+ uint8_t not_used_01 : 2;
+ uint8_t trig_counter_bdr : 1;
+ uint8_t rst_counter_bdr : 1;
+ uint8_t dataready_pulsed : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t dataready_pulsed : 1;
+ uint8_t rst_counter_bdr : 1;
+ uint8_t trig_counter_bdr : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t cnt_bdr_th : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_counter_bdr_reg1_t;
+
+#define LSM6DSO32X_COUNTER_BDR_REG2 0x0CU
+typedef struct
+{
+ uint8_t cnt_bdr_th : 8;
+} lsm6dso32x_counter_bdr_reg2_t;
+
+#define LSM6DSO32X_INT1_CTRL 0x0D
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t int1_drdy_xl : 1;
+ uint8_t int1_drdy_g : 1;
+ uint8_t int1_boot : 1;
+ uint8_t int1_fifo_th : 1;
+ uint8_t int1_fifo_ovr : 1;
+ uint8_t int1_fifo_full : 1;
+ uint8_t int1_cnt_bdr : 1;
+ uint8_t den_drdy_flag : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t den_drdy_flag : 1;
+ uint8_t int1_cnt_bdr : 1;
+ uint8_t int1_fifo_full : 1;
+ uint8_t int1_fifo_ovr : 1;
+ uint8_t int1_fifo_th : 1;
+ uint8_t int1_boot : 1;
+ uint8_t int1_drdy_g : 1;
+ uint8_t int1_drdy_xl : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_int1_ctrl_t;
+
+#define LSM6DSO32X_INT2_CTRL 0x0EU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t int2_drdy_xl : 1;
+ uint8_t int2_drdy_g : 1;
+ uint8_t int2_drdy_temp : 1;
+ uint8_t int2_fifo_th : 1;
+ uint8_t int2_fifo_ovr : 1;
+ uint8_t int2_fifo_full : 1;
+ uint8_t int2_cnt_bdr : 1;
+ uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t int2_cnt_bdr : 1;
+ uint8_t int2_fifo_full : 1;
+ uint8_t int2_fifo_ovr : 1;
+ uint8_t int2_fifo_th : 1;
+ uint8_t int2_drdy_temp : 1;
+ uint8_t int2_drdy_g : 1;
+ uint8_t int2_drdy_xl : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_int2_ctrl_t;
+
+#define LSM6DSO32X_WHO_AM_I 0x0FU
+#define LSM6DSO32X_CTRL1_XL 0x10U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t lpf2_xl_en : 1;
+ uint8_t fs_xl : 2;
+ uint8_t odr_xl : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr_xl : 4;
+ uint8_t fs_xl : 2;
+ uint8_t lpf2_xl_en : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_ctrl1_xl_t;
+
+#define LSM6DSO32X_CTRL2_G 0x11U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t fs_g : 3; /* fs_125 + fs_g */
+ uint8_t odr_g : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr_g : 4;
+ uint8_t fs_g : 3; /* fs_125 + fs_g */
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_ctrl2_g_t;
+
+#define LSM6DSO32X_CTRL3_C 0x12U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t sw_reset : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t if_inc : 1;
+ uint8_t sim : 1;
+ uint8_t pp_od : 1;
+ uint8_t h_lactive : 1;
+ uint8_t bdu : 1;
+ uint8_t boot : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t boot : 1;
+ uint8_t bdu : 1;
+ uint8_t h_lactive : 1;
+ uint8_t pp_od : 1;
+ uint8_t sim : 1;
+ uint8_t if_inc : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t sw_reset : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_ctrl3_c_t;
+
+#define LSM6DSO32X_CTRL4_C 0x13U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t lpf1_sel_g : 1;
+ uint8_t i2c_disable : 1;
+ uint8_t drdy_mask : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t int2_on_int1 : 1;
+ uint8_t sleep_g : 1;
+ uint8_t not_used_03 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_03 : 1;
+ uint8_t sleep_g : 1;
+ uint8_t int2_on_int1 : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t drdy_mask : 1;
+ uint8_t i2c_disable : 1;
+ uint8_t lpf1_sel_g : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_ctrl4_c_t;
+
+#define LSM6DSO32X_CTRL5_C 0x14U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t st_xl : 2;
+ uint8_t st_g : 2;
+ uint8_t not_used_01 : 1;
+ uint8_t rounding : 2;
+ uint8_t xl_ulp_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t xl_ulp_en : 1;
+ uint8_t rounding : 2;
+ uint8_t not_used_01 : 1;
+ uint8_t st_g : 2;
+ uint8_t st_xl : 2;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_ctrl5_c_t;
+
+#define LSM6DSO32X_CTRL6_C 0x15U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t ftype : 3;
+ uint8_t usr_off_w : 1;
+ uint8_t xl_hm_mode : 1;
+uint8_t den_mode :
+ 3; /* trig_en + lvl1_en + lvl2_en */
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+uint8_t den_mode :
+ 3; /* trig_en + lvl1_en + lvl2_en */
+ uint8_t xl_hm_mode : 1;
+ uint8_t usr_off_w : 1;
+ uint8_t ftype : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_ctrl6_c_t;
+
+#define LSM6DSO32X_CTRL7_G 0x16U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t usr_off_on_out : 1;
+ uint8_t not_used_02 : 2;
+ uint8_t hpm_g : 2;
+ uint8_t hp_en_g : 1;
+ uint8_t g_hm_mode : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t g_hm_mode : 1;
+ uint8_t hp_en_g : 1;
+ uint8_t hpm_g : 2;
+ uint8_t not_used_02 : 2;
+ uint8_t usr_off_on_out : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_ctrl7_g_t;
+
+#define LSM6DSO32X_CTRL8_XL 0x17U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t low_pass_on_6d : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t hp_slope_xl_en : 1;
+ uint8_t fastsettl_mode_xl : 1;
+ uint8_t hp_ref_mode_xl : 1;
+ uint8_t hpcf_xl : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t hpcf_xl : 3;
+ uint8_t hp_ref_mode_xl : 1;
+ uint8_t fastsettl_mode_xl : 1;
+ uint8_t hp_slope_xl_en : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t low_pass_on_6d : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_ctrl8_xl_t;
+
+#define LSM6DSO32X_CTRL9_XL 0x18U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t i3c_disable : 1;
+ uint8_t den_lh : 1;
+ uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */
+ uint8_t den_z : 1;
+ uint8_t den_y : 1;
+ uint8_t den_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t den_x : 1;
+ uint8_t den_y : 1;
+ uint8_t den_z : 1;
+ uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */
+ uint8_t den_lh : 1;
+ uint8_t i3c_disable : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_ctrl9_xl_t;
+
+#define LSM6DSO32X_CTRL10_C 0x19U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t not_used_01 : 5;
+ uint8_t timestamp_en : 1;
+ uint8_t not_used_02 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 2;
+ uint8_t timestamp_en : 1;
+ uint8_t not_used_01 : 5;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_ctrl10_c_t;
+
+#define LSM6DSO32X_ALL_INT_SRC 0x1AU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t ff_ia : 1;
+ uint8_t wu_ia : 1;
+ uint8_t single_tap : 1;
+ uint8_t double_tap : 1;
+ uint8_t d6d_ia : 1;
+ uint8_t sleep_change_ia : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t timestamp_endcount : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t timestamp_endcount : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t sleep_change_ia : 1;
+ uint8_t d6d_ia : 1;
+ uint8_t double_tap : 1;
+ uint8_t single_tap : 1;
+ uint8_t wu_ia : 1;
+ uint8_t ff_ia : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_all_int_src_t;
+
+#define LSM6DSO32X_WAKE_UP_SRC 0x1BU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t z_wu : 1;
+ uint8_t y_wu : 1;
+ uint8_t x_wu : 1;
+ uint8_t wu_ia : 1;
+ uint8_t sleep_state : 1;
+ uint8_t ff_ia : 1;
+ uint8_t sleep_change_ia : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t sleep_change_ia : 2;
+ uint8_t ff_ia : 1;
+ uint8_t sleep_state : 1;
+ uint8_t wu_ia : 1;
+ uint8_t x_wu : 1;
+ uint8_t y_wu : 1;
+ uint8_t z_wu : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_wake_up_src_t;
+
+#define LSM6DSO32X_TAP_SRC 0x1CU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t z_tap : 1;
+ uint8_t y_tap : 1;
+ uint8_t x_tap : 1;
+ uint8_t tap_sign : 1;
+ uint8_t double_tap : 1;
+ uint8_t single_tap : 1;
+ uint8_t tap_ia : 1;
+ uint8_t not_used_02 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 1;
+ uint8_t tap_ia : 1;
+ uint8_t single_tap : 1;
+ uint8_t double_tap : 1;
+ uint8_t tap_sign : 1;
+ uint8_t x_tap : 1;
+ uint8_t y_tap : 1;
+ uint8_t z_tap : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_tap_src_t;
+
+#define LSM6DSO32X_D6D_SRC 0x1DU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t xl : 1;
+ uint8_t xh : 1;
+ uint8_t yl : 1;
+ uint8_t yh : 1;
+ uint8_t zl : 1;
+ uint8_t zh : 1;
+ uint8_t d6d_ia : 1;
+ uint8_t den_drdy : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t den_drdy : 1;
+ uint8_t d6d_ia : 1;
+ uint8_t zh : 1;
+ uint8_t zl : 1;
+ uint8_t yh : 1;
+ uint8_t yl : 1;
+ uint8_t xh : 1;
+ uint8_t xl : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_d6d_src_t;
+
+#define LSM6DSO32X_STATUS_REG 0x1EU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t xlda : 1;
+ uint8_t gda : 1;
+ uint8_t tda : 1;
+ uint8_t not_used_01 : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 5;
+ uint8_t tda : 1;
+ uint8_t gda : 1;
+ uint8_t xlda : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_status_reg_t;
+
+#define LSM6DSO32X_OUT_TEMP_L 0x20U
+#define LSM6DSO32X_OUT_TEMP_H 0x21U
+#define LSM6DSO32X_OUTX_L_G 0x22U
+#define LSM6DSO32X_OUTX_H_G 0x23U
+#define LSM6DSO32X_OUTY_L_G 0x24U
+#define LSM6DSO32X_OUTY_H_G 0x25U
+#define LSM6DSO32X_OUTZ_L_G 0x26U
+#define LSM6DSO32X_OUTZ_H_G 0x27U
+#define LSM6DSO32X_OUTX_L_A 0x28U
+#define LSM6DSO32X_OUTX_H_A 0x29U
+#define LSM6DSO32X_OUTY_L_A 0x2AU
+#define LSM6DSO32X_OUTY_H_A 0x2BU
+#define LSM6DSO32X_OUTZ_L_A 0x2CU
+#define LSM6DSO32X_OUTZ_H_A 0x2DU
+#define LSM6DSO32X_EMB_FUNC_STATUS_MAINPAGE 0x35U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t not_used_01 : 3;
+ uint8_t is_step_det : 1;
+ uint8_t is_tilt : 1;
+ uint8_t is_sigmot : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t is_fsm_lc : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_fsm_lc : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t is_sigmot : 1;
+ uint8_t is_tilt : 1;
+ uint8_t is_step_det : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_emb_func_status_mainpage_t;
+
+#define LSM6DSO32X_FSM_STATUS_A_MAINPAGE 0x36U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t is_fsm1 : 1;
+ uint8_t is_fsm2 : 1;
+ uint8_t is_fsm3 : 1;
+ uint8_t is_fsm4 : 1;
+ uint8_t is_fsm5 : 1;
+ uint8_t is_fsm6 : 1;
+ uint8_t is_fsm7 : 1;
+ uint8_t is_fsm8 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_fsm8 : 1;
+ uint8_t is_fsm7 : 1;
+ uint8_t is_fsm6 : 1;
+ uint8_t is_fsm5 : 1;
+ uint8_t is_fsm4 : 1;
+ uint8_t is_fsm3 : 1;
+ uint8_t is_fsm2 : 1;
+ uint8_t is_fsm1 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fsm_status_a_mainpage_t;
+
+#define LSM6DSO32X_FSM_STATUS_B_MAINPAGE 0x37U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t is_fsm9 : 1;
+ uint8_t is_fsm10 : 1;
+ uint8_t is_fsm11 : 1;
+ uint8_t is_fsm12 : 1;
+ uint8_t is_fsm13 : 1;
+ uint8_t is_fsm14 : 1;
+ uint8_t is_fsm15 : 1;
+ uint8_t is_fsm16 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_fsm16 : 1;
+ uint8_t is_fsm15 : 1;
+ uint8_t is_fsm14 : 1;
+ uint8_t is_fsm13 : 1;
+ uint8_t is_fsm12 : 1;
+ uint8_t is_fsm11 : 1;
+ uint8_t is_fsm10 : 1;
+ uint8_t is_fsm9 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fsm_status_b_mainpage_t;
+
+#define LSM6DSO32X_MLC_STATUS_MAINPAGE 0x38U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t is_mlc1 : 1;
+ uint8_t is_mlc2 : 1;
+ uint8_t is_mlc3 : 1;
+ uint8_t is_mlc4 : 1;
+ uint8_t is_mlc5 : 1;
+ uint8_t is_mlc6 : 1;
+ uint8_t is_mlc7 : 1;
+ uint8_t is_mlc8 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_mlc8 : 1;
+ uint8_t is_mlc7 : 1;
+ uint8_t is_mlc6 : 1;
+ uint8_t is_mlc5 : 1;
+ uint8_t is_mlc4 : 1;
+ uint8_t is_mlc3 : 1;
+ uint8_t is_mlc2 : 1;
+ uint8_t is_mlc1 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_mlc_status_mainpage_t;
+
+#define LSM6DSO32X_STATUS_MASTER_MAINPAGE 0x39U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t sens_hub_endop : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t slave0_nack : 1;
+ uint8_t slave1_nack : 1;
+ uint8_t slave2_nack : 1;
+ uint8_t slave3_nack : 1;
+ uint8_t wr_once_done : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t wr_once_done : 1;
+ uint8_t slave3_nack : 1;
+ uint8_t slave2_nack : 1;
+ uint8_t slave1_nack : 1;
+ uint8_t slave0_nack : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t sens_hub_endop : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_status_master_mainpage_t;
+
+#define LSM6DSO32X_FIFO_STATUS1 0x3AU
+typedef struct
+{
+ uint8_t diff_fifo : 8;
+} lsm6dso32x_fifo_status1_t;
+
+#define LSM6DSO32X_FIFO_STATUS2 0x3B
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t diff_fifo : 2;
+ uint8_t not_used_01 : 1;
+ uint8_t over_run_latched : 1;
+ uint8_t counter_bdr_ia : 1;
+ uint8_t fifo_full_ia : 1;
+ uint8_t fifo_ovr_ia : 1;
+ uint8_t fifo_wtm_ia : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fifo_wtm_ia : 1;
+ uint8_t fifo_ovr_ia : 1;
+ uint8_t fifo_full_ia : 1;
+ uint8_t counter_bdr_ia : 1;
+ uint8_t over_run_latched : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t diff_fifo : 2;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fifo_status2_t;
+
+#define LSM6DSO32X_TIMESTAMP0 0x40U
+#define LSM6DSO32X_TIMESTAMP1 0x41U
+#define LSM6DSO32X_TIMESTAMP2 0x42U
+#define LSM6DSO32X_TIMESTAMP3 0x43U
+
+#define LSM6DSO32X_TAP_CFG0 0x56U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t lir : 1;
+ uint8_t tap_z_en : 1;
+ uint8_t tap_y_en : 1;
+ uint8_t tap_x_en : 1;
+ uint8_t slope_fds : 1;
+ uint8_t sleep_status_on_int : 1;
+ uint8_t int_clr_on_read : 1;
+ uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t int_clr_on_read : 1;
+ uint8_t sleep_status_on_int : 1;
+ uint8_t slope_fds : 1;
+ uint8_t tap_x_en : 1;
+ uint8_t tap_y_en : 1;
+ uint8_t tap_z_en : 1;
+ uint8_t lir : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_tap_cfg0_t;
+
+#define LSM6DSO32X_TAP_CFG1 0x57U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t tap_ths_x : 5;
+ uint8_t tap_priority : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t tap_priority : 3;
+ uint8_t tap_ths_x : 5;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_tap_cfg1_t;
+
+#define LSM6DSO32X_TAP_CFG2 0x58U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t tap_ths_y : 5;
+ uint8_t inact_en : 2;
+ uint8_t interrupts_enable : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t interrupts_enable : 1;
+ uint8_t inact_en : 2;
+ uint8_t tap_ths_y : 5;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_tap_cfg2_t;
+
+#define LSM6DSO32X_TAP_THS_6D 0x59U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t tap_ths_z : 5;
+ uint8_t sixd_ths : 2;
+ uint8_t d4d_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t d4d_en : 1;
+ uint8_t sixd_ths : 2;
+ uint8_t tap_ths_z : 5;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_tap_ths_6d_t;
+
+#define LSM6DSO32X_INT_DUR2 0x5AU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t shock : 2;
+ uint8_t quiet : 2;
+ uint8_t dur : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t dur : 4;
+ uint8_t quiet : 2;
+ uint8_t shock : 2;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_int_dur2_t;
+
+#define LSM6DSO32X_WAKE_UP_THS 0x5BU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t wk_ths : 6;
+ uint8_t usr_off_on_wu : 1;
+ uint8_t single_double_tap : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t single_double_tap : 1;
+ uint8_t usr_off_on_wu : 1;
+ uint8_t wk_ths : 6;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_wake_up_ths_t;
+
+#define LSM6DSO32X_WAKE_UP_DUR 0x5CU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t sleep_dur : 4;
+ uint8_t wake_ths_w : 1;
+ uint8_t wake_dur : 2;
+ uint8_t ff_dur : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t ff_dur : 1;
+ uint8_t wake_dur : 2;
+ uint8_t wake_ths_w : 1;
+ uint8_t sleep_dur : 4;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_wake_up_dur_t;
+
+#define LSM6DSO32X_FREE_FALL 0x5DU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t ff_ths : 3;
+ uint8_t ff_dur : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t ff_dur : 5;
+ uint8_t ff_ths : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_free_fall_t;
+
+#define LSM6DSO32X_MD1_CFG 0x5EU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t int1_shub : 1;
+ uint8_t int1_emb_func : 1;
+ uint8_t int1_6d : 1;
+ uint8_t int1_double_tap : 1;
+ uint8_t int1_ff : 1;
+ uint8_t int1_wu : 1;
+ uint8_t int1_single_tap : 1;
+ uint8_t int1_sleep_change : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_sleep_change : 1;
+ uint8_t int1_single_tap : 1;
+ uint8_t int1_wu : 1;
+ uint8_t int1_ff : 1;
+ uint8_t int1_double_tap : 1;
+ uint8_t int1_6d : 1;
+ uint8_t int1_emb_func : 1;
+ uint8_t int1_shub : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_md1_cfg_t;
+
+#define LSM6DSO32X_MD2_CFG 0x5FU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t int2_timestamp : 1;
+ uint8_t int2_emb_func : 1;
+ uint8_t int2_6d : 1;
+ uint8_t int2_double_tap : 1;
+ uint8_t int2_ff : 1;
+ uint8_t int2_wu : 1;
+ uint8_t int2_single_tap : 1;
+ uint8_t int2_sleep_change : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_sleep_change : 1;
+ uint8_t int2_single_tap : 1;
+ uint8_t int2_wu : 1;
+ uint8_t int2_ff : 1;
+ uint8_t int2_double_tap : 1;
+ uint8_t int2_6d : 1;
+ uint8_t int2_emb_func : 1;
+ uint8_t int2_timestamp : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_md2_cfg_t;
+
+#define LSM6DSO32X_I3C_BUS_AVB 0x62U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t pd_dis_int1 : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t i3c_bus_avb_sel : 2;
+ uint8_t not_used_02 : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 3;
+ uint8_t i3c_bus_avb_sel : 2;
+ uint8_t not_used_01 : 2;
+ uint8_t pd_dis_int1 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_i3c_bus_avb_t;
+
+#define LSM6DSO32X_INTERNAL_FREQ_FINE 0x63U
+typedef struct
+{
+ uint8_t freq_fine : 8;
+} lsm6dso32x_internal_freq_fine_t;
+
+#define LSM6DSO32X_X_OFS_USR 0x73U
+#define LSM6DSO32X_Y_OFS_USR 0x74U
+#define LSM6DSO32X_Z_OFS_USR 0x75U
+#define LSM6DSO32X_FIFO_DATA_OUT_TAG 0x78U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t tag_parity : 1;
+ uint8_t tag_cnt : 2;
+ uint8_t tag_sensor : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t tag_sensor : 5;
+ uint8_t tag_cnt : 2;
+ uint8_t tag_parity : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fifo_data_out_tag_t;
+
+#define LSM6DSO32X_FIFO_DATA_OUT_X_L 0x79
+#define LSM6DSO32X_FIFO_DATA_OUT_X_H 0x7A
+#define LSM6DSO32X_FIFO_DATA_OUT_Y_L 0x7B
+#define LSM6DSO32X_FIFO_DATA_OUT_Y_H 0x7C
+#define LSM6DSO32X_FIFO_DATA_OUT_Z_L 0x7D
+#define LSM6DSO32X_FIFO_DATA_OUT_Z_H 0x7E
+
+#define LSM6DSO32X_PAGE_SEL 0x02U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t not_used_01 : 4;
+ uint8_t page_sel : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t page_sel : 4;
+ uint8_t not_used_01 : 4;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_page_sel_t;
+
+#define LSM6DSO32X_EMB_FUNC_EN_A 0x04U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t not_used_01 : 3;
+ uint8_t pedo_en : 1;
+ uint8_t tilt_en : 1;
+ uint8_t sign_motion_en : 1;
+ uint8_t not_used_02 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 2;
+ uint8_t sign_motion_en : 1;
+ uint8_t tilt_en : 1;
+ uint8_t pedo_en : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_emb_func_en_a_t;
+
+#define LSM6DSO32X_EMB_FUNC_EN_B 0x05U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t fsm_en : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t fifo_compr_en : 1;
+ uint8_t mlc_en : 1;
+ uint8_t not_used_02 : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 3;
+ uint8_t mlc_en : 1;
+ uint8_t fifo_compr_en : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t fsm_en : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_emb_func_en_b_t;
+
+#define LSM6DSO32X_PAGE_ADDRESS 0x08U
+typedef struct
+{
+ uint8_t page_addr : 8;
+} lsm6dso32x_page_address_t;
+
+#define LSM6DSO32X_PAGE_VALUE 0x09U
+typedef struct
+{
+ uint8_t page_value : 8;
+} lsm6dso32x_page_value_t;
+
+#define LSM6DSO32X_EMB_FUNC_INT1 0x0AU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t not_used_01 : 3;
+ uint8_t int1_step_detector : 1;
+ uint8_t int1_tilt : 1;
+ uint8_t int1_sig_mot : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t int1_fsm_lc : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_fsm_lc : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t int1_sig_mot : 1;
+ uint8_t int1_tilt : 1;
+ uint8_t int1_step_detector : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_emb_func_int1_t;
+
+#define LSM6DSO32X_FSM_INT1_A 0x0BU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t int1_fsm1 : 1;
+ uint8_t int1_fsm2 : 1;
+ uint8_t int1_fsm3 : 1;
+ uint8_t int1_fsm4 : 1;
+ uint8_t int1_fsm5 : 1;
+ uint8_t int1_fsm6 : 1;
+ uint8_t int1_fsm7 : 1;
+ uint8_t int1_fsm8 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_fsm8 : 1;
+ uint8_t int1_fsm7 : 1;
+ uint8_t int1_fsm6 : 1;
+ uint8_t int1_fsm5 : 1;
+ uint8_t int1_fsm4 : 1;
+ uint8_t int1_fsm3 : 1;
+ uint8_t int1_fsm2 : 1;
+ uint8_t int1_fsm1 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fsm_int1_a_t;
+
+#define LSM6DSO32X_FSM_INT1_B 0x0CU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t int1_fsm16 : 1;
+ uint8_t int1_fsm15 : 1;
+ uint8_t int1_fsm14 : 1;
+ uint8_t int1_fsm13 : 1;
+ uint8_t int1_fsm12 : 1;
+ uint8_t int1_fsm11 : 1;
+ uint8_t int1_fsm10 : 1;
+ uint8_t int1_fsm9 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fsm_int1_b_t;
+
+#define LSM6DSO32X_MLC_INT1 0x0DU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t int1_mlc1 : 1;
+ uint8_t int1_mlc2 : 1;
+ uint8_t int1_mlc3 : 1;
+ uint8_t int1_mlc4 : 1;
+ uint8_t int1_mlc5 : 1;
+ uint8_t int1_mlc6 : 1;
+ uint8_t int1_mlc7 : 1;
+ uint8_t int1_mlc8 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_mlc8 : 1;
+ uint8_t int1_mlc7 : 1;
+ uint8_t int1_mlc6 : 1;
+ uint8_t int1_mlc5 : 1;
+ uint8_t int1_mlc4 : 1;
+ uint8_t int1_mlc3 : 1;
+ uint8_t int1_mlc2 : 1;
+ uint8_t int1_mlc1 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_mlc_int1_t;
+
+#define LSM6DSO32X_EMB_FUNC_INT2 0x0EU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t not_used_01 : 3;
+ uint8_t int2_step_detector : 1;
+ uint8_t int2_tilt : 1;
+ uint8_t int2_sig_mot : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t int2_fsm_lc : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_fsm_lc : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t int2_sig_mot : 1;
+ uint8_t int2_tilt : 1;
+ uint8_t int2_step_detector : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_emb_func_int2_t;
+
+#define LSM6DSO32X_FSM_INT2_A 0x0FU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t int2_fsm1 : 1;
+ uint8_t int2_fsm2 : 1;
+ uint8_t int2_fsm3 : 1;
+ uint8_t int2_fsm4 : 1;
+ uint8_t int2_fsm5 : 1;
+ uint8_t int2_fsm6 : 1;
+ uint8_t int2_fsm7 : 1;
+ uint8_t int2_fsm8 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_fsm8 : 1;
+ uint8_t int2_fsm7 : 1;
+ uint8_t int2_fsm6 : 1;
+ uint8_t int2_fsm5 : 1;
+ uint8_t int2_fsm4 : 1;
+ uint8_t int2_fsm3 : 1;
+ uint8_t int2_fsm2 : 1;
+ uint8_t int2_fsm1 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fsm_int2_a_t;
+
+#define LSM6DSO32X_FSM_INT2_B 0x10U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t int2_fsm9 : 1;
+ uint8_t int2_fsm10 : 1;
+ uint8_t int2_fsm11 : 1;
+ uint8_t int2_fsm12 : 1;
+ uint8_t int2_fsm13 : 1;
+ uint8_t int2_fsm14 : 1;
+ uint8_t int2_fsm15 : 1;
+ uint8_t int2_fsm16 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_fsm16 : 1;
+ uint8_t int2_fsm15 : 1;
+ uint8_t int2_fsm14 : 1;
+ uint8_t int2_fsm13 : 1;
+ uint8_t int2_fsm12 : 1;
+ uint8_t int2_fsm11 : 1;
+ uint8_t int2_fsm10 : 1;
+ uint8_t int2_fsm9 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fsm_int2_b_t;
+
+#define LSM6DSO32X_MLC_INT2 0x11U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t int2_mlc1 : 1;
+ uint8_t int2_mlc2 : 1;
+ uint8_t int2_mlc3 : 1;
+ uint8_t int2_mlc4 : 1;
+ uint8_t int2_mlc5 : 1;
+ uint8_t int2_mlc6 : 1;
+ uint8_t int2_mlc7 : 1;
+ uint8_t int2_mlc8 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_mlc8 : 1;
+ uint8_t int2_mlc7 : 1;
+ uint8_t int2_mlc6 : 1;
+ uint8_t int2_mlc5 : 1;
+ uint8_t int2_mlc4 : 1;
+ uint8_t int2_mlc3 : 1;
+ uint8_t int2_mlc2 : 1;
+ uint8_t int2_mlc1 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_mlc_int2_t;
+
+#define LSM6DSO32X_EMB_FUNC_STATUS 0x12U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t not_used_01 : 3;
+ uint8_t is_step_det : 1;
+ uint8_t is_tilt : 1;
+ uint8_t is_sigmot : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t is_fsm_lc : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_fsm_lc : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t is_sigmot : 1;
+ uint8_t is_tilt : 1;
+ uint8_t is_step_det : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_emb_func_status_t;
+
+#define LSM6DSO32X_FSM_STATUS_A 0x13U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t is_fsm1 : 1;
+ uint8_t is_fsm2 : 1;
+ uint8_t is_fsm3 : 1;
+ uint8_t is_fsm4 : 1;
+ uint8_t is_fsm5 : 1;
+ uint8_t is_fsm6 : 1;
+ uint8_t is_fsm7 : 1;
+ uint8_t is_fsm8 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_fsm8 : 1;
+ uint8_t is_fsm7 : 1;
+ uint8_t is_fsm6 : 1;
+ uint8_t is_fsm5 : 1;
+ uint8_t is_fsm4 : 1;
+ uint8_t is_fsm3 : 1;
+ uint8_t is_fsm2 : 1;
+ uint8_t is_fsm1 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fsm_status_a_t;
+
+#define LSM6DSO32X_FSM_STATUS_B 0x14U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t is_fsm9 : 1;
+ uint8_t is_fsm10 : 1;
+ uint8_t is_fsm11 : 1;
+ uint8_t is_fsm12 : 1;
+ uint8_t is_fsm13 : 1;
+ uint8_t is_fsm14 : 1;
+ uint8_t is_fsm15 : 1;
+ uint8_t is_fsm16 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_fsm16 : 1;
+ uint8_t is_fsm15 : 1;
+ uint8_t is_fsm14 : 1;
+ uint8_t is_fsm13 : 1;
+ uint8_t is_fsm12 : 1;
+ uint8_t is_fsm11 : 1;
+ uint8_t is_fsm10 : 1;
+ uint8_t is_fsm9 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fsm_status_b_t;
+
+#define LSM6DSO32X_MLC_STATUS 0x15U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t is_mlc1 : 1;
+ uint8_t is_mlc2 : 1;
+ uint8_t is_mlc3 : 1;
+ uint8_t is_mlc4 : 1;
+ uint8_t is_mlc5 : 1;
+ uint8_t is_mlc6 : 1;
+ uint8_t is_mlc7 : 1;
+ uint8_t is_mlc8 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_mlc8 : 1;
+ uint8_t is_mlc7 : 1;
+ uint8_t is_mlc6 : 1;
+ uint8_t is_mlc5 : 1;
+ uint8_t is_mlc4 : 1;
+ uint8_t is_mlc3 : 1;
+ uint8_t is_mlc2 : 1;
+ uint8_t is_mlc1 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_mlc_status_t;
+
+#define LSM6DSO32X_PAGE_RW 0x17U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t not_used_01 : 5;
+ uint8_t page_rw : 2; /* page_write + page_read */
+ uint8_t emb_func_lir : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t emb_func_lir : 1;
+ uint8_t page_rw : 2; /* page_write + page_read */
+ uint8_t not_used_01 : 5;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_page_rw_t;
+
+#define LSM6DSO32X_EMB_FUNC_FIFO_CFG 0x44U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t not_used_00 : 6;
+ uint8_t pedo_fifo_en : 1;
+ uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t pedo_fifo_en : 1;
+ uint8_t not_used_00 : 6;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_emb_func_fifo_cfg_t;
+
+#define LSM6DSO32X_FSM_ENABLE_A 0x46U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t fsm1_en : 1;
+ uint8_t fsm2_en : 1;
+ uint8_t fsm3_en : 1;
+ uint8_t fsm4_en : 1;
+ uint8_t fsm5_en : 1;
+ uint8_t fsm6_en : 1;
+ uint8_t fsm7_en : 1;
+ uint8_t fsm8_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fsm8_en : 1;
+ uint8_t fsm7_en : 1;
+ uint8_t fsm6_en : 1;
+ uint8_t fsm5_en : 1;
+ uint8_t fsm4_en : 1;
+ uint8_t fsm3_en : 1;
+ uint8_t fsm2_en : 1;
+ uint8_t fsm1_en : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fsm_enable_a_t;
+
+#define LSM6DSO32X_FSM_ENABLE_B 0x47U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t fsm9_en : 1;
+ uint8_t fsm10_en : 1;
+ uint8_t fsm11_en : 1;
+ uint8_t fsm12_en : 1;
+ uint8_t fsm13_en : 1;
+ uint8_t fsm14_en : 1;
+ uint8_t fsm15_en : 1;
+ uint8_t fsm16_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fsm16_en : 1;
+ uint8_t fsm15_en : 1;
+ uint8_t fsm14_en : 1;
+ uint8_t fsm13_en : 1;
+ uint8_t fsm12_en : 1;
+ uint8_t fsm11_en : 1;
+ uint8_t fsm10_en : 1;
+ uint8_t fsm9_en : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fsm_enable_b_t;
+
+#define LSM6DSO32X_FSM_LONG_COUNTER_L 0x48U
+#define LSM6DSO32X_FSM_LONG_COUNTER_H 0x49U
+#define LSM6DSO32X_FSM_LONG_COUNTER_CLEAR 0x4AU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+uint8_t fsm_lc_clr :
+ 2; /* fsm_lc_cleared + fsm_lc_clear */
+ uint8_t not_used_01 : 6;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 6;
+uint8_t fsm_lc_clr :
+ 2; /* fsm_lc_cleared + fsm_lc_clear */
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fsm_long_counter_clear_t;
+
+#define LSM6DSO32X_FSM_OUTS1 0x4CU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t n_v : 1;
+ uint8_t p_v : 1;
+ uint8_t n_z : 1;
+ uint8_t p_z : 1;
+ uint8_t n_y : 1;
+ uint8_t p_y : 1;
+ uint8_t n_x : 1;
+ uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fsm_outs1_t;
+
+#define LSM6DSO32X_FSM_OUTS2 0x4DU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t n_v : 1;
+ uint8_t p_v : 1;
+ uint8_t n_z : 1;
+ uint8_t p_z : 1;
+ uint8_t n_y : 1;
+ uint8_t p_y : 1;
+ uint8_t n_x : 1;
+ uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fsm_outs2_t;
+
+#define LSM6DSO32X_FSM_OUTS3 0x4EU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t n_v : 1;
+ uint8_t p_v : 1;
+ uint8_t n_z : 1;
+ uint8_t p_z : 1;
+ uint8_t n_y : 1;
+ uint8_t p_y : 1;
+ uint8_t n_x : 1;
+ uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fsm_outs3_t;
+
+#define LSM6DSO32X_FSM_OUTS4 0x4FU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t n_v : 1;
+ uint8_t p_v : 1;
+ uint8_t n_z : 1;
+ uint8_t p_z : 1;
+ uint8_t n_y : 1;
+ uint8_t p_y : 1;
+ uint8_t n_x : 1;
+ uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fsm_outs4_t;
+
+#define LSM6DSO32X_FSM_OUTS5 0x50U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t n_v : 1;
+ uint8_t p_v : 1;
+ uint8_t n_z : 1;
+ uint8_t p_z : 1;
+ uint8_t n_y : 1;
+ uint8_t p_y : 1;
+ uint8_t n_x : 1;
+ uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fsm_outs5_t;
+
+#define LSM6DSO32X_FSM_OUTS6 0x51U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t n_v : 1;
+ uint8_t p_v : 1;
+ uint8_t n_z : 1;
+ uint8_t p_z : 1;
+ uint8_t n_y : 1;
+ uint8_t p_y : 1;
+ uint8_t n_x : 1;
+ uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fsm_outs6_t;
+
+#define LSM6DSO32X_FSM_OUTS7 0x52U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t n_v : 1;
+ uint8_t p_v : 1;
+ uint8_t n_z : 1;
+ uint8_t p_z : 1;
+ uint8_t n_y : 1;
+ uint8_t p_y : 1;
+ uint8_t n_x : 1;
+ uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fsm_outs7_t;
+
+#define LSM6DSO32X_FSM_OUTS8 0x53U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t n_v : 1;
+ uint8_t p_v : 1;
+ uint8_t n_z : 1;
+ uint8_t p_z : 1;
+ uint8_t n_y : 1;
+ uint8_t p_y : 1;
+ uint8_t n_x : 1;
+ uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fsm_outs8_t;
+
+#define LSM6DSO32X_FSM_OUTS9 0x54U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t n_v : 1;
+ uint8_t p_v : 1;
+ uint8_t n_z : 1;
+ uint8_t p_z : 1;
+ uint8_t n_y : 1;
+ uint8_t p_y : 1;
+ uint8_t n_x : 1;
+ uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fsm_outs9_t;
+
+#define LSM6DSO32X_FSM_OUTS10 0x55U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t n_v : 1;
+ uint8_t p_v : 1;
+ uint8_t n_z : 1;
+ uint8_t p_z : 1;
+ uint8_t n_y : 1;
+ uint8_t p_y : 1;
+ uint8_t n_x : 1;
+ uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fsm_outs10_t;
+
+#define LSM6DSO32X_FSM_OUTS11 0x56U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t n_v : 1;
+ uint8_t p_v : 1;
+ uint8_t n_z : 1;
+ uint8_t p_z : 1;
+ uint8_t n_y : 1;
+ uint8_t p_y : 1;
+ uint8_t n_x : 1;
+ uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fsm_outs11_t;
+
+#define LSM6DSO32X_FSM_OUTS12 0x57U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t n_v : 1;
+ uint8_t p_v : 1;
+ uint8_t n_z : 1;
+ uint8_t p_z : 1;
+ uint8_t n_y : 1;
+ uint8_t p_y : 1;
+ uint8_t n_x : 1;
+ uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fsm_outs12_t;
+
+#define LSM6DSO32X_FSM_OUTS13 0x58U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t n_v : 1;
+ uint8_t p_v : 1;
+ uint8_t n_z : 1;
+ uint8_t p_z : 1;
+ uint8_t n_y : 1;
+ uint8_t p_y : 1;
+ uint8_t n_x : 1;
+ uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fsm_outs13_t;
+
+#define LSM6DSO32X_FSM_OUTS14 0x59U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t n_v : 1;
+ uint8_t p_v : 1;
+ uint8_t n_z : 1;
+ uint8_t p_z : 1;
+ uint8_t n_y : 1;
+ uint8_t p_y : 1;
+ uint8_t n_x : 1;
+ uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fsm_outs14_t;
+
+#define LSM6DSO32X_FSM_OUTS15 0x5AU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t n_v : 1;
+ uint8_t p_v : 1;
+ uint8_t n_z : 1;
+ uint8_t p_z : 1;
+ uint8_t n_y : 1;
+ uint8_t p_y : 1;
+ uint8_t n_x : 1;
+ uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fsm_outs15_t;
+
+#define LSM6DSO32X_FSM_OUTS16 0x5BU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t n_v : 1;
+ uint8_t p_v : 1;
+ uint8_t n_z : 1;
+ uint8_t p_z : 1;
+ uint8_t n_y : 1;
+ uint8_t p_y : 1;
+ uint8_t n_x : 1;
+ uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_fsm_outs16_t;
+
+#define LSM6DSO32X_EMB_FUNC_ODR_CFG_B 0x5FU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t not_used_01 : 3;
+ uint8_t fsm_odr : 2;
+ uint8_t not_used_02 : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 3;
+ uint8_t fsm_odr : 2;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_emb_func_odr_cfg_b_t;
+
+#define LSM6DSO32X_EMB_FUNC_ODR_CFG_C 0x60U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t not_used_01 : 4;
+ uint8_t mlc_odr : 2;
+ uint8_t not_used_02 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 2;
+ uint8_t mlc_odr : 2;
+ uint8_t not_used_01 : 4;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_emb_func_odr_cfg_c_t;
+
+#define LSM6DSO32X_STEP_COUNTER_L 0x62U
+#define LSM6DSO32X_STEP_COUNTER_H 0x63U
+#define LSM6DSO32X_EMB_FUNC_SRC 0x64U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t not_used_01 : 2;
+ uint8_t stepcounter_bit_set : 1;
+ uint8_t step_overflow : 1;
+ uint8_t step_count_delta_ia : 1;
+ uint8_t step_detected : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t pedo_rst_step : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t pedo_rst_step : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t step_detected : 1;
+ uint8_t step_count_delta_ia : 1;
+ uint8_t step_overflow : 1;
+ uint8_t stepcounter_bit_set : 1;
+ uint8_t not_used_01 : 2;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_emb_func_src_t;
+
+#define LSM6DSO32X_EMB_FUNC_INIT_A 0x66U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t not_used_01 : 3;
+ uint8_t step_det_init : 1;
+ uint8_t tilt_init : 1;
+ uint8_t sig_mot_init : 1;
+ uint8_t not_used_02 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 2;
+ uint8_t sig_mot_init : 1;
+ uint8_t tilt_init : 1;
+ uint8_t step_det_init : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_emb_func_init_a_t;
+
+#define LSM6DSO32X_EMB_FUNC_INIT_B 0x67U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t fsm_init : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t fifo_compr_init : 1;
+ uint8_t mlc_init : 1;
+ uint8_t not_used_02 : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 3;
+ uint8_t mlc_init : 1;
+ uint8_t fifo_compr_init : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t fsm_init : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_emb_func_init_b_t;
+
+#define LSM6DSO32X_MLC0_SRC 0x70U
+#define LSM6DSO32X_MLC1_SRC 0x71U
+#define LSM6DSO32X_MLC2_SRC 0x72U
+#define LSM6DSO32X_MLC3_SRC 0x73U
+#define LSM6DSO32X_MLC4_SRC 0x74U
+#define LSM6DSO32X_MLC5_SRC 0x75U
+#define LSM6DSO32X_MLC6_SRC 0x76U
+#define LSM6DSO32X_MLC7_SRC 0x77U
+#define LSM6DSO32X_MAG_SENSITIVITY_L 0xBAU
+#define LSM6DSO32X_MAG_SENSITIVITY_H 0xBBU
+#define LSM6DSO32X_MAG_OFFX_L 0xC0U
+#define LSM6DSO32X_MAG_OFFX_H 0xC1U
+#define LSM6DSO32X_MAG_OFFY_L 0xC2U
+#define LSM6DSO32X_MAG_OFFY_H 0xC3U
+#define LSM6DSO32X_MAG_OFFZ_L 0xC4U
+#define LSM6DSO32X_MAG_OFFZ_H 0xC5U
+#define LSM6DSO32X_MAG_SI_XX_L 0xC6U
+#define LSM6DSO32X_MAG_SI_XX_H 0xC7U
+#define LSM6DSO32X_MAG_SI_XY_L 0xC8U
+#define LSM6DSO32X_MAG_SI_XY_H 0xC9U
+#define LSM6DSO32X_MAG_SI_XZ_L 0xCAU
+#define LSM6DSO32X_MAG_SI_XZ_H 0xCBU
+#define LSM6DSO32X_MAG_SI_YY_L 0xCCU
+#define LSM6DSO32X_MAG_SI_YY_H 0xCDU
+#define LSM6DSO32X_MAG_SI_YZ_L 0xCEU
+#define LSM6DSO32X_MAG_SI_YZ_H 0xCFU
+#define LSM6DSO32X_MAG_SI_ZZ_L 0xD0U
+#define LSM6DSO32X_MAG_SI_ZZ_H 0xD1U
+#define LSM6DSO32X_MAG_CFG_A 0xD4U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t mag_z_axis : 3;
+ uint8_t not_used_01 : 1;
+ uint8_t mag_y_axis : 3;
+ uint8_t not_used_02 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 1;
+ uint8_t mag_y_axis : 3;
+ uint8_t not_used_01 : 1;
+ uint8_t mag_z_axis : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_mag_cfg_a_t;
+
+#define LSM6DSO32X_MAG_CFG_B 0xD5U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t mag_x_axis : 3;
+ uint8_t not_used_01 : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 5;
+ uint8_t mag_x_axis : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_mag_cfg_b_t;
+
+#define LSM6DSO32X_FSM_LC_TIMEOUT_L 0x17AU
+#define LSM6DSO32X_FSM_LC_TIMEOUT_H 0x17BU
+#define LSM6DSO32X_FSM_PROGRAMS 0x17CU
+#define LSM6DSO32X_FSM_START_ADD_L 0x17EU
+#define LSM6DSO32X_FSM_START_ADD_H 0x17FU
+#define LSM6DSO32X_PEDO_CMD_REG 0x183U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t ad_det_en : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t fp_rejection_en : 1;
+ uint8_t carry_count_en : 1;
+ uint8_t not_used_02 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 4;
+ uint8_t carry_count_en : 1;
+ uint8_t fp_rejection_en : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t ad_det_en : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_pedo_cmd_reg_t;
+
+#define LSM6DSO32X_PEDO_DEB_STEPS_CONF 0x184U
+#define LSM6DSO32X_PEDO_SC_DELTAT_L 0x1D0U
+#define LSM6DSO32X_PEDO_SC_DELTAT_H 0x1D1U
+
+#define LSM6DSO32X_MLC_MAG_SENSITIVITY_L 0x1E8U
+#define LSM6DSO32X_MLC_MAG_SENSITIVITY_H 0x1E9U
+
+#define LSM6DSO32X_SENSOR_HUB_1 0x02U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_sensor_hub_1_t;
+
+#define LSM6DSO32X_SENSOR_HUB_2 0x03U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_sensor_hub_2_t;
+
+#define LSM6DSO32X_SENSOR_HUB_3 0x04U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_sensor_hub_3_t;
+
+#define LSM6DSO32X_SENSOR_HUB_4 0x05U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_sensor_hub_4_t;
+
+#define LSM6DSO32X_SENSOR_HUB_5 0x06U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_sensor_hub_5_t;
+
+#define LSM6DSO32X_SENSOR_HUB_6 0x07U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_sensor_hub_6_t;
+
+#define LSM6DSO32X_SENSOR_HUB_7 0x08U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_sensor_hub_7_t;
+
+#define LSM6DSO32X_SENSOR_HUB_8 0x09U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_sensor_hub_8_t;
+
+#define LSM6DSO32X_SENSOR_HUB_9 0x0AU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_sensor_hub_9_t;
+
+#define LSM6DSO32X_SENSOR_HUB_10 0x0BU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_sensor_hub_10_t;
+
+#define LSM6DSO32X_SENSOR_HUB_11 0x0CU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_sensor_hub_11_t;
+
+#define LSM6DSO32X_SENSOR_HUB_12 0x0DU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_sensor_hub_12_t;
+
+#define LSM6DSO32X_SENSOR_HUB_13 0x0EU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_sensor_hub_13_t;
+
+#define LSM6DSO32X_SENSOR_HUB_14 0x0FU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_sensor_hub_14_t;
+
+#define LSM6DSO32X_SENSOR_HUB_15 0x10U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_sensor_hub_15_t;
+
+#define LSM6DSO32X_SENSOR_HUB_16 0x11U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_sensor_hub_16_t;
+
+#define LSM6DSO32X_SENSOR_HUB_17 0x12U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_sensor_hub_17_t;
+
+#define LSM6DSO32X_SENSOR_HUB_18 0x13U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_sensor_hub_18_t;
+
+#define LSM6DSO32X_MASTER_CONFIG 0x14U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t aux_sens_on : 2;
+ uint8_t master_on : 1;
+ uint8_t shub_pu_en : 1;
+ uint8_t pass_through_mode : 1;
+ uint8_t start_config : 1;
+ uint8_t write_once : 1;
+ uint8_t rst_master_regs : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t rst_master_regs : 1;
+ uint8_t write_once : 1;
+ uint8_t start_config : 1;
+ uint8_t pass_through_mode : 1;
+ uint8_t shub_pu_en : 1;
+ uint8_t master_on : 1;
+ uint8_t aux_sens_on : 2;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_master_config_t;
+
+#define LSM6DSO32X_SLV0_ADD 0x15U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t rw_0 : 1;
+ uint8_t slave0 : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave0 : 7;
+ uint8_t rw_0 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_slv0_add_t;
+
+#define LSM6DSO32X_SLV0_SUBADD 0x16U
+typedef struct
+{
+ uint8_t slave0_reg : 8;
+} lsm6dso32x_slv0_subadd_t;
+
+#define LSM6DSO32X_SLV0_CONFIG 0x17U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t slave0_numop : 3;
+ uint8_t batch_ext_sens_0_en : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t shub_odr : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t shub_odr : 2;
+ uint8_t not_used_01 : 2;
+ uint8_t batch_ext_sens_0_en : 1;
+ uint8_t slave0_numop : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_slv0_config_t;
+
+#define LSM6DSO32X_SLV1_ADD 0x18U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t r_1 : 1;
+ uint8_t slave1_add : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave1_add : 7;
+ uint8_t r_1 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_slv1_add_t;
+
+#define LSM6DSO32X_SLV1_SUBADD 0x19U
+typedef struct
+{
+ uint8_t slave1_reg : 8;
+} lsm6dso32x_slv1_subadd_t;
+
+#define LSM6DSO32X_SLV1_CONFIG 0x1AU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t slave1_numop : 3;
+ uint8_t batch_ext_sens_1_en : 1;
+ uint8_t not_used_01 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 4;
+ uint8_t batch_ext_sens_1_en : 1;
+ uint8_t slave1_numop : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_slv1_config_t;
+
+#define LSM6DSO32X_SLV2_ADD 0x1BU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t r_2 : 1;
+ uint8_t slave2_add : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave2_add : 7;
+ uint8_t r_2 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_slv2_add_t;
+
+#define LSM6DSO32X_SLV2_SUBADD 0x1CU
+typedef struct
+{
+ uint8_t slave2_reg : 8;
+} lsm6dso32x_slv2_subadd_t;
+
+#define LSM6DSO32X_SLV2_CONFIG 0x1DU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t slave2_numop : 3;
+ uint8_t batch_ext_sens_2_en : 1;
+ uint8_t not_used_01 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 4;
+ uint8_t batch_ext_sens_2_en : 1;
+ uint8_t slave2_numop : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_slv2_config_t;
+
+#define LSM6DSO32X_SLV3_ADD 0x1EU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t r_3 : 1;
+ uint8_t slave3_add : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave3_add : 7;
+ uint8_t r_3 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_slv3_add_t;
+
+#define LSM6DSO32X_SLV3_SUBADD 0x1FU
+typedef struct
+{
+ uint8_t slave3_reg : 8;
+} lsm6dso32x_slv3_subadd_t;
+
+#define LSM6DSO32X_SLV3_CONFIG 0x20U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t slave3_numop : 3;
+ uint8_t batch_ext_sens_3_en : 1;
+ uint8_t not_used_01 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 4;
+ uint8_t batch_ext_sens_3_en : 1;
+ uint8_t slave3_numop : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_slv3_config_t;
+
+#define LSM6DSO32X_DATAWRITE_SLV0 0x21U
+typedef struct
+{
+ uint8_t slave0_dataw : 8;
+} lsm6dso32x_datawrite_slv0_t;
+
+#define LSM6DSO32X_STATUS_MASTER 0x22U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t sens_hub_endop : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t slave0_nack : 1;
+ uint8_t slave1_nack : 1;
+ uint8_t slave2_nack : 1;
+ uint8_t slave3_nack : 1;
+ uint8_t wr_once_done : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t wr_once_done : 1;
+ uint8_t slave3_nack : 1;
+ uint8_t slave2_nack : 1;
+ uint8_t slave1_nack : 1;
+ uint8_t slave0_nack : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t sens_hub_endop : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso32x_status_master_t;
+
+#define LSM6DSO32X_START_FSM_ADD 0x0400U
+
+/**
+ * @defgroup LSM6DSO32X_Register_Union
+ * @brief This union group all the registers that has a bitfield
+ * description.
+ * This union is useful but not need by the driver.
+ *
+ * REMOVING this union you are compliant with:
+ * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
+ *
+ * @{
+ *
+ */
+typedef union
+{
+ lsm6dso32x_func_cfg_access_t func_cfg_access;
+ lsm6dso32x_pin_ctrl_t pin_ctrl;
+ lsm6dso32x_fifo_ctrl1_t fifo_ctrl1;
+ lsm6dso32x_fifo_ctrl2_t fifo_ctrl2;
+ lsm6dso32x_fifo_ctrl3_t fifo_ctrl3;
+ lsm6dso32x_fifo_ctrl4_t fifo_ctrl4;
+ lsm6dso32x_counter_bdr_reg1_t counter_bdr_reg1;
+ lsm6dso32x_counter_bdr_reg2_t counter_bdr_reg2;
+ lsm6dso32x_int1_ctrl_t int1_ctrl;
+ lsm6dso32x_int2_ctrl_t int2_ctrl;
+ lsm6dso32x_ctrl1_xl_t ctrl1_xl;
+ lsm6dso32x_ctrl2_g_t ctrl2_g;
+ lsm6dso32x_ctrl3_c_t ctrl3_c;
+ lsm6dso32x_ctrl4_c_t ctrl4_c;
+ lsm6dso32x_ctrl5_c_t ctrl5_c;
+ lsm6dso32x_ctrl6_c_t ctrl6_c;
+ lsm6dso32x_ctrl7_g_t ctrl7_g;
+ lsm6dso32x_ctrl8_xl_t ctrl8_xl;
+ lsm6dso32x_ctrl9_xl_t ctrl9_xl;
+ lsm6dso32x_ctrl10_c_t ctrl10_c;
+ lsm6dso32x_all_int_src_t all_int_src;
+ lsm6dso32x_wake_up_src_t wake_up_src;
+ lsm6dso32x_tap_src_t tap_src;
+ lsm6dso32x_d6d_src_t d6d_src;
+ lsm6dso32x_status_reg_t status_reg;
+ lsm6dso32x_fifo_status1_t fifo_status1;
+ lsm6dso32x_fifo_status2_t fifo_status2;
+ lsm6dso32x_tap_cfg0_t tap_cfg0;
+ lsm6dso32x_tap_cfg1_t tap_cfg1;
+ lsm6dso32x_tap_cfg2_t tap_cfg2;
+ lsm6dso32x_tap_ths_6d_t tap_ths_6d;
+ lsm6dso32x_int_dur2_t int_dur2;
+ lsm6dso32x_wake_up_ths_t wake_up_ths;
+ lsm6dso32x_wake_up_dur_t wake_up_dur;
+ lsm6dso32x_free_fall_t free_fall;
+ lsm6dso32x_md1_cfg_t md1_cfg;
+ lsm6dso32x_md2_cfg_t md2_cfg;
+ lsm6dso32x_i3c_bus_avb_t i3c_bus_avb;
+ lsm6dso32x_internal_freq_fine_t internal_freq_fine;
+ lsm6dso32x_fifo_data_out_tag_t fifo_data_out_tag;
+ lsm6dso32x_page_sel_t page_sel;
+ lsm6dso32x_emb_func_en_a_t emb_func_en_a;
+ lsm6dso32x_emb_func_en_b_t emb_func_en_b;
+ lsm6dso32x_page_address_t page_address;
+ lsm6dso32x_page_value_t page_value;
+ lsm6dso32x_emb_func_int1_t emb_func_int1;
+ lsm6dso32x_fsm_int1_a_t fsm_int1_a;
+ lsm6dso32x_fsm_int1_b_t fsm_int1_b;
+ lsm6dso32x_emb_func_int2_t emb_func_int2;
+ lsm6dso32x_fsm_int2_a_t fsm_int2_a;
+ lsm6dso32x_fsm_int2_b_t fsm_int2_b;
+ lsm6dso32x_emb_func_status_t emb_func_status;
+ lsm6dso32x_fsm_status_a_t fsm_status_a;
+ lsm6dso32x_fsm_status_b_t fsm_status_b;
+ lsm6dso32x_page_rw_t page_rw;
+ lsm6dso32x_emb_func_fifo_cfg_t emb_func_fifo_cfg;
+ lsm6dso32x_fsm_enable_a_t fsm_enable_a;
+ lsm6dso32x_fsm_enable_b_t fsm_enable_b;
+ lsm6dso32x_fsm_long_counter_clear_t fsm_long_counter_clear;
+ lsm6dso32x_fsm_outs1_t fsm_outs1;
+ lsm6dso32x_fsm_outs2_t fsm_outs2;
+ lsm6dso32x_fsm_outs3_t fsm_outs3;
+ lsm6dso32x_fsm_outs4_t fsm_outs4;
+ lsm6dso32x_fsm_outs5_t fsm_outs5;
+ lsm6dso32x_fsm_outs6_t fsm_outs6;
+ lsm6dso32x_fsm_outs7_t fsm_outs7;
+ lsm6dso32x_fsm_outs8_t fsm_outs8;
+ lsm6dso32x_fsm_outs9_t fsm_outs9;
+ lsm6dso32x_fsm_outs10_t fsm_outs10;
+ lsm6dso32x_fsm_outs11_t fsm_outs11;
+ lsm6dso32x_fsm_outs12_t fsm_outs12;
+ lsm6dso32x_fsm_outs13_t fsm_outs13;
+ lsm6dso32x_fsm_outs14_t fsm_outs14;
+ lsm6dso32x_fsm_outs15_t fsm_outs15;
+ lsm6dso32x_fsm_outs16_t fsm_outs16;
+ lsm6dso32x_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
+ lsm6dso32x_emb_func_odr_cfg_c_t emb_func_odr_cfg_c;
+ lsm6dso32x_emb_func_src_t emb_func_src;
+ lsm6dso32x_emb_func_init_a_t emb_func_init_a;
+ lsm6dso32x_emb_func_init_b_t emb_func_init_b;
+ lsm6dso32x_mag_cfg_a_t mag_cfg_a;
+ lsm6dso32x_mag_cfg_b_t mag_cfg_b;
+ lsm6dso32x_pedo_cmd_reg_t pedo_cmd_reg;
+ lsm6dso32x_sensor_hub_1_t sensor_hub_1;
+ lsm6dso32x_sensor_hub_2_t sensor_hub_2;
+ lsm6dso32x_sensor_hub_3_t sensor_hub_3;
+ lsm6dso32x_sensor_hub_4_t sensor_hub_4;
+ lsm6dso32x_sensor_hub_5_t sensor_hub_5;
+ lsm6dso32x_sensor_hub_6_t sensor_hub_6;
+ lsm6dso32x_sensor_hub_7_t sensor_hub_7;
+ lsm6dso32x_sensor_hub_8_t sensor_hub_8;
+ lsm6dso32x_sensor_hub_9_t sensor_hub_9;
+ lsm6dso32x_sensor_hub_10_t sensor_hub_10;
+ lsm6dso32x_sensor_hub_11_t sensor_hub_11;
+ lsm6dso32x_sensor_hub_12_t sensor_hub_12;
+ lsm6dso32x_sensor_hub_13_t sensor_hub_13;
+ lsm6dso32x_sensor_hub_14_t sensor_hub_14;
+ lsm6dso32x_sensor_hub_15_t sensor_hub_15;
+ lsm6dso32x_sensor_hub_16_t sensor_hub_16;
+ lsm6dso32x_sensor_hub_17_t sensor_hub_17;
+ lsm6dso32x_sensor_hub_18_t sensor_hub_18;
+ lsm6dso32x_master_config_t master_config;
+ lsm6dso32x_slv0_add_t slv0_add;
+ lsm6dso32x_slv0_subadd_t slv0_subadd;
+ lsm6dso32x_slv0_config_t slv0_config;
+ lsm6dso32x_slv1_add_t slv1_add;
+ lsm6dso32x_slv1_subadd_t slv1_subadd;
+ lsm6dso32x_slv1_config_t slv1_config;
+ lsm6dso32x_slv2_add_t slv2_add;
+ lsm6dso32x_slv2_subadd_t slv2_subadd;
+ lsm6dso32x_slv2_config_t slv2_config;
+ lsm6dso32x_slv3_add_t slv3_add;
+ lsm6dso32x_slv3_subadd_t slv3_subadd;
+ lsm6dso32x_slv3_config_t slv3_config;
+ lsm6dso32x_datawrite_slv0_t datawrite_slv0;
+ lsm6dso32x_status_master_t status_master;
+ bitwise_t bitwise;
+ uint8_t byte;
+} lsm6dso32x_reg_t;
+
+/**
+ * @}
+ *
+ */
+
+int32_t lsm6dso32x_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
+ uint16_t len);
+int32_t lsm6dso32x_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
+ uint16_t len);
+
+float_t lsm6dso32x_from_fs4_to_mg(int16_t lsb);
+float_t lsm6dso32x_from_fs8_to_mg(int16_t lsb);
+float_t lsm6dso32x_from_fs16_to_mg(int16_t lsb);
+float_t lsm6dso32x_from_fs32_to_mg(int16_t lsb);
+float_t lsm6dso32x_from_fs125_to_mdps(int16_t lsb);
+float_t lsm6dso32x_from_fs500_to_mdps(int16_t lsb);
+float_t lsm6dso32x_from_fs250_to_mdps(int16_t lsb);
+float_t lsm6dso32x_from_fs1000_to_mdps(int16_t lsb);
+float_t lsm6dso32x_from_fs2000_to_mdps(int16_t lsb);
+float_t lsm6dso32x_from_lsb_to_celsius(int16_t lsb);
+float_t lsm6dso32x_from_lsb_to_nsec(int16_t lsb);
+
+typedef enum
+{
+ LSM6DSO32X_4g = 0,
+ LSM6DSO32X_32g = 1,
+ LSM6DSO32X_8g = 2,
+ LSM6DSO32X_16g = 3,
+} lsm6dso32x_fs_xl_t;
+int32_t lsm6dso32x_xl_full_scale_set(stmdev_ctx_t *ctx, lsm6dso32x_fs_xl_t val);
+int32_t lsm6dso32x_xl_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_fs_xl_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_XL_ODR_OFF = 0,
+ LSM6DSO32X_XL_ODR_12Hz5 = 1,
+ LSM6DSO32X_XL_ODR_26Hz = 2,
+ LSM6DSO32X_XL_ODR_52Hz = 3,
+ LSM6DSO32X_XL_ODR_104Hz = 4,
+ LSM6DSO32X_XL_ODR_208Hz = 5,
+ LSM6DSO32X_XL_ODR_417Hz = 6,
+ LSM6DSO32X_XL_ODR_833Hz = 7,
+ LSM6DSO32X_XL_ODR_1667Hz = 8,
+ LSM6DSO32X_XL_ODR_3333Hz = 9,
+ LSM6DSO32X_XL_ODR_6667Hz = 10,
+ LSM6DSO32X_XL_ODR_1Hz6 = 11, /* (low power only) */
+} lsm6dso32x_odr_xl_t;
+int32_t lsm6dso32x_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6dso32x_odr_xl_t val);
+int32_t lsm6dso32x_xl_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_odr_xl_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_250dps = 0,
+ LSM6DSO32X_125dps = 1,
+ LSM6DSO32X_500dps = 2,
+ LSM6DSO32X_1000dps = 4,
+ LSM6DSO32X_2000dps = 6,
+} lsm6dso32x_fs_g_t;
+int32_t lsm6dso32x_gy_full_scale_set(stmdev_ctx_t *ctx, lsm6dso32x_fs_g_t val);
+int32_t lsm6dso32x_gy_full_scale_get(stmdev_ctx_t *ctx, lsm6dso32x_fs_g_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_GY_ODR_OFF = 0,
+ LSM6DSO32X_GY_ODR_12Hz5 = 1,
+ LSM6DSO32X_GY_ODR_26Hz = 2,
+ LSM6DSO32X_GY_ODR_52Hz = 3,
+ LSM6DSO32X_GY_ODR_104Hz = 4,
+ LSM6DSO32X_GY_ODR_208Hz = 5,
+ LSM6DSO32X_GY_ODR_417Hz = 6,
+ LSM6DSO32X_GY_ODR_833Hz = 7,
+ LSM6DSO32X_GY_ODR_1667Hz = 8,
+ LSM6DSO32X_GY_ODR_3333Hz = 9,
+ LSM6DSO32X_GY_ODR_6667Hz = 10,
+} lsm6dso32x_odr_g_t;
+int32_t lsm6dso32x_gy_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_odr_g_t val);
+int32_t lsm6dso32x_gy_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_odr_g_t *val);
+
+int32_t lsm6dso32x_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32x_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_LSb_1mg = 0,
+ LSM6DSO32X_LSb_16mg = 1,
+} lsm6dso32x_usr_off_w_t;
+int32_t lsm6dso32x_xl_offset_weight_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_usr_off_w_t val);
+int32_t lsm6dso32x_xl_offset_weight_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_usr_off_w_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_HIGH_PERFORMANCE_MD = 0,
+ LSM6DSO32X_LOW_NORMAL_POWER_MD = 1,
+ LSM6DSO32X_ULTRA_LOW_POWER_MD = 2,
+} lsm6dso32x_xl_hm_mode_t;
+int32_t lsm6dso32x_xl_power_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_xl_hm_mode_t val);
+int32_t lsm6dso32x_xl_power_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_xl_hm_mode_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_GY_HIGH_PERFORMANCE = 0,
+ LSM6DSO32X_GY_NORMAL = 1,
+} lsm6dso32x_g_hm_mode_t;
+int32_t lsm6dso32x_gy_power_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_g_hm_mode_t val);
+int32_t lsm6dso32x_gy_power_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_g_hm_mode_t *val);
+
+int32_t lsm6dso32x_status_reg_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_status_reg_t *val);
+
+int32_t lsm6dso32x_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6dso32x_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6dso32x_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6dso32x_xl_usr_offset_x_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lsm6dso32x_xl_usr_offset_x_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+
+int32_t lsm6dso32x_xl_usr_offset_y_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lsm6dso32x_xl_usr_offset_y_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+
+int32_t lsm6dso32x_xl_usr_offset_z_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lsm6dso32x_xl_usr_offset_z_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+
+int32_t lsm6dso32x_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso32x_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso32x_timestamp_rst(stmdev_ctx_t *ctx);
+
+int32_t lsm6dso32x_timestamp_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso32x_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso32x_timestamp_raw_get(stmdev_ctx_t *ctx,
+ uint32_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_NO_ROUND = 0,
+ LSM6DSO32X_ROUND_XL = 1,
+ LSM6DSO32X_ROUND_GY = 2,
+ LSM6DSO32X_ROUND_GY_XL = 3,
+} lsm6dso32x_rounding_t;
+int32_t lsm6dso32x_rounding_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_rounding_t val);
+int32_t lsm6dso32x_rounding_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_rounding_t *val);
+
+int32_t lsm6dso32x_temperature_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
+
+int32_t lsm6dso32x_angular_rate_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
+
+int32_t lsm6dso32x_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
+
+int32_t lsm6dso32x_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+
+int32_t lsm6dso32x_number_of_steps_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
+
+int32_t lsm6dso32x_steps_reset(stmdev_ctx_t *ctx);
+
+int32_t lsm6dso32x_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff);
+
+int32_t lsm6dso32x_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso32x_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_USER_BANK = 0,
+ LSM6DSO32X_SENSOR_HUB_BANK = 1,
+ LSM6DSO32X_EMBEDDED_FUNC_BANK = 2,
+} lsm6dso32x_reg_access_t;
+int32_t lsm6dso32x_mem_bank_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_reg_access_t val);
+int32_t lsm6dso32x_mem_bank_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_reg_access_t *val);
+
+int32_t lsm6dso32x_ln_pg_write_byte(stmdev_ctx_t *ctx,
+ uint16_t address,
+ uint8_t *val);
+int32_t lsm6dso32x_ln_pg_read_byte(stmdev_ctx_t *ctx,
+ uint16_t address,
+ uint8_t *val);
+
+int32_t lsm6dso32x_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address,
+ uint8_t *buf, uint8_t len);
+int32_t lsm6dso32x_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address,
+ uint8_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_DRDY_LATCHED = 0,
+ LSM6DSO32X_DRDY_PULSED = 1,
+} lsm6dso32x_dataready_pulsed_t;
+int32_t lsm6dso32x_data_ready_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_dataready_pulsed_t val);
+int32_t lsm6dso32x_data_ready_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_dataready_pulsed_t *val);
+
+int32_t lsm6dso32x_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
+
+int32_t lsm6dso32x_reset_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso32x_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso32x_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso32x_auto_increment_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6dso32x_boot_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso32x_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_XL_ST_DISABLE = 0,
+ LSM6DSO32X_XL_ST_POSITIVE = 1,
+ LSM6DSO32X_XL_ST_NEGATIVE = 2,
+} lsm6dso32x_st_xl_t;
+int32_t lsm6dso32x_xl_self_test_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_st_xl_t val);
+int32_t lsm6dso32x_xl_self_test_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_st_xl_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_GY_ST_DISABLE = 0,
+ LSM6DSO32X_GY_ST_POSITIVE = 1,
+ LSM6DSO32X_GY_ST_NEGATIVE = 3,
+} lsm6dso32x_st_g_t;
+int32_t lsm6dso32x_gy_self_test_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_st_g_t val);
+int32_t lsm6dso32x_gy_self_test_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_st_g_t *val);
+
+int32_t lsm6dso32x_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso32x_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso32x_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso32x_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso32x_filter_settling_mask_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32x_filter_settling_mask_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_ULTRA_LIGHT = 0,
+ LSM6DSO32X_VERY_LIGHT = 1,
+ LSM6DSO32X_LIGHT = 2,
+ LSM6DSO32X_MEDIUM = 3,
+ LSM6DSO32X_STRONG = 4,
+ LSM6DSO32X_VERY_STRONG = 5,
+ LSM6DSO32X_AGGRESSIVE = 6,
+ LSM6DSO32X_XTREME = 7,
+} lsm6dso32x_ftype_t;
+int32_t lsm6dso32x_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_ftype_t val);
+int32_t lsm6dso32x_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_ftype_t *val);
+
+int32_t lsm6dso32x_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso32x_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_HP_PATH_DISABLE_ON_OUT = 0x00,
+ LSM6DSO32X_SLOPE_ODR_DIV_4 = 0x10,
+ LSM6DSO32X_HP_ODR_DIV_10 = 0x11,
+ LSM6DSO32X_HP_ODR_DIV_20 = 0x12,
+ LSM6DSO32X_HP_ODR_DIV_45 = 0x13,
+ LSM6DSO32X_HP_ODR_DIV_100 = 0x14,
+ LSM6DSO32X_HP_ODR_DIV_200 = 0x15,
+ LSM6DSO32X_HP_ODR_DIV_400 = 0x16,
+ LSM6DSO32X_HP_ODR_DIV_800 = 0x17,
+ LSM6DSO32X_HP_REF_MD_ODR_DIV_10 = 0x31,
+ LSM6DSO32X_HP_REF_MD_ODR_DIV_20 = 0x32,
+ LSM6DSO32X_HP_REF_MD_ODR_DIV_45 = 0x33,
+ LSM6DSO32X_HP_REF_MD_ODR_DIV_100 = 0x34,
+ LSM6DSO32X_HP_REF_MD_ODR_DIV_200 = 0x35,
+ LSM6DSO32X_HP_REF_MD_ODR_DIV_400 = 0x36,
+ LSM6DSO32X_HP_REF_MD_ODR_DIV_800 = 0x37,
+ LSM6DSO32X_LP_ODR_DIV_10 = 0x01,
+ LSM6DSO32X_LP_ODR_DIV_20 = 0x02,
+ LSM6DSO32X_LP_ODR_DIV_45 = 0x03,
+ LSM6DSO32X_LP_ODR_DIV_100 = 0x04,
+ LSM6DSO32X_LP_ODR_DIV_200 = 0x05,
+ LSM6DSO32X_LP_ODR_DIV_400 = 0x06,
+ LSM6DSO32X_LP_ODR_DIV_800 = 0x07,
+} lsm6dso32x_hp_slope_xl_en_t;
+int32_t lsm6dso32x_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_hp_slope_xl_en_t val);
+int32_t lsm6dso32x_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_hp_slope_xl_en_t *val);
+
+int32_t lsm6dso32x_xl_fast_settling_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32x_xl_fast_settling_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_USE_SLOPE = 0,
+ LSM6DSO32X_USE_HPF = 1,
+} lsm6dso32x_slope_fds_t;
+int32_t lsm6dso32x_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_slope_fds_t val);
+int32_t lsm6dso32x_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_slope_fds_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_HP_FILTER_NONE = 0x00,
+ LSM6DSO32X_HP_FILTER_16mHz = 0x80,
+ LSM6DSO32X_HP_FILTER_65mHz = 0x81,
+ LSM6DSO32X_HP_FILTER_260mHz = 0x82,
+ LSM6DSO32X_HP_FILTER_1Hz04 = 0x83,
+} lsm6dso32x_hpm_g_t;
+int32_t lsm6dso32x_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_hpm_g_t val);
+int32_t lsm6dso32x_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_hpm_g_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_PULL_UP_DISC = 0,
+ LSM6DSO32X_PULL_UP_CONNECT = 1,
+} lsm6dso32x_sdo_pu_en_t;
+int32_t lsm6dso32x_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_sdo_pu_en_t val);
+int32_t lsm6dso32x_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_sdo_pu_en_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_SPI_4_WIRE = 0,
+ LSM6DSO32X_SPI_3_WIRE = 1,
+} lsm6dso32x_sim_t;
+int32_t lsm6dso32x_spi_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_sim_t val);
+int32_t lsm6dso32x_spi_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_sim_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_I2C_ENABLE = 0,
+ LSM6DSO32X_I2C_DISABLE = 1,
+} lsm6dso32x_i2c_disable_t;
+int32_t lsm6dso32x_i2c_interface_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_i2c_disable_t val);
+int32_t lsm6dso32x_i2c_interface_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_i2c_disable_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_I3C_DISABLE = 0x80,
+ LSM6DSO32X_I3C_ENABLE_T_50us = 0x00,
+ LSM6DSO32X_I3C_ENABLE_T_2us = 0x01,
+ LSM6DSO32X_I3C_ENABLE_T_1ms = 0x02,
+ LSM6DSO32X_I3C_ENABLE_T_25ms = 0x03,
+} lsm6dso32x_i3c_disable_t;
+int32_t lsm6dso32x_i3c_disable_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_i3c_disable_t val);
+int32_t lsm6dso32x_i3c_disable_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_i3c_disable_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_PUSH_PULL = 0x00,
+ LSM6DSO32X_OPEN_DRAIN = 0x01,
+ LSM6DSO32X_INT1_NOPULL_DOWN_INT2_PUSH_PULL = 0x02,
+ LSM6DSO32X_INT1_NOPULL_DOWN_INT2_OPEN_DRAIN = 0x03,
+} lsm6dso32x_pp_od_t;
+int32_t lsm6dso32x_pin_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_pp_od_t val);
+int32_t lsm6dso32x_pin_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_pp_od_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_ACTIVE_HIGH = 0,
+ LSM6DSO32X_ACTIVE_LOW = 1,
+} lsm6dso32x_h_lactive_t;
+int32_t lsm6dso32x_pin_polarity_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_h_lactive_t val);
+int32_t lsm6dso32x_pin_polarity_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_h_lactive_t *val);
+
+int32_t lsm6dso32x_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso32x_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_ALL_INT_PULSED = 0,
+ LSM6DSO32X_BASE_LATCHED_EMB_PULSED = 1,
+ LSM6DSO32X_BASE_PULSED_EMB_LATCHED = 2,
+ LSM6DSO32X_ALL_INT_LATCHED = 3,
+} lsm6dso32x_lir_t;
+int32_t lsm6dso32x_int_notification_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_lir_t val);
+int32_t lsm6dso32x_int_notification_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_lir_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_LSb_FS_DIV_64 = 0,
+ LSM6DSO32X_LSb_FS_DIV_256 = 1,
+} lsm6dso32x_wake_ths_w_t;
+int32_t lsm6dso32x_wkup_ths_weight_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_wake_ths_w_t val);
+int32_t lsm6dso32x_wkup_ths_weight_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_wake_ths_w_t *val);
+
+int32_t lsm6dso32x_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso32x_wkup_threshold_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6dso32x_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32x_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6dso32x_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso32x_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso32x_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso32x_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_DRIVE_SLEEP_CHG_EVENT = 0,
+ LSM6DSO32X_DRIVE_SLEEP_STATUS = 1,
+} lsm6dso32x_sleep_status_on_int_t;
+int32_t lsm6dso32x_act_pin_notification_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_sleep_status_on_int_t val);
+int32_t lsm6dso32x_act_pin_notification_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_sleep_status_on_int_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_XL_AND_GY_NOT_AFFECTED = 0,
+ LSM6DSO32X_XL_12Hz5_GY_NOT_AFFECTED = 1,
+ LSM6DSO32X_XL_12Hz5_GY_SLEEP = 2,
+ LSM6DSO32X_XL_12Hz5_GY_PD = 3,
+} lsm6dso32x_inact_en_t;
+int32_t lsm6dso32x_act_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_inact_en_t val);
+int32_t lsm6dso32x_act_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_inact_en_t *val);
+
+int32_t lsm6dso32x_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso32x_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso32x_tap_detection_on_z_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32x_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6dso32x_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32x_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6dso32x_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32x_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6dso32x_tap_threshold_x_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32x_tap_threshold_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_XYZ = 0,
+ LSM6DSO32X_YXZ = 1,
+ LSM6DSO32X_XZY = 2,
+ LSM6DSO32X_ZYX = 3,
+ LSM6DSO32X_YZX = 5,
+ LSM6DSO32X_ZXY = 6,
+} lsm6dso32x_tap_priority_t;
+int32_t lsm6dso32x_tap_axis_priority_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_tap_priority_t val);
+int32_t lsm6dso32x_tap_axis_priority_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_tap_priority_t *val);
+
+int32_t lsm6dso32x_tap_threshold_y_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32x_tap_threshold_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6dso32x_tap_threshold_z_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32x_tap_threshold_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6dso32x_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso32x_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso32x_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso32x_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso32x_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso32x_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_ONLY_SINGLE = 0,
+ LSM6DSO32X_BOTH_SINGLE_DOUBLE = 1,
+} lsm6dso32x_single_double_tap_t;
+int32_t lsm6dso32x_tap_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_single_double_tap_t val);
+int32_t lsm6dso32x_tap_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_single_double_tap_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_DEG_80 = 0,
+ LSM6DSO32X_DEG_70 = 1,
+ LSM6DSO32X_DEG_60 = 2,
+ LSM6DSO32X_DEG_50 = 3,
+} lsm6dso32x_sixd_ths_t;
+int32_t lsm6dso32x_6d_threshold_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_sixd_ths_t val);
+int32_t lsm6dso32x_6d_threshold_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_sixd_ths_t *val);
+
+int32_t lsm6dso32x_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso32x_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_FF_TSH_312mg = 0,
+ LSM6DSO32X_FF_TSH_438mg = 1,
+ LSM6DSO32X_FF_TSH_500mg = 2,
+} lsm6dso32x_ff_ths_t;
+int32_t lsm6dso32x_ff_threshold_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_ff_ths_t val);
+int32_t lsm6dso32x_ff_threshold_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_ff_ths_t *val);
+
+int32_t lsm6dso32x_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso32x_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso32x_fifo_watermark_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t lsm6dso32x_fifo_watermark_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
+
+int32_t lsm6dso32x_compression_algo_init_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32x_compression_algo_init_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_CMP_DISABLE = 0x00,
+ LSM6DSO32X_CMP_ALWAYS = 0x04,
+ LSM6DSO32X_CMP_8_TO_1 = 0x05,
+ LSM6DSO32X_CMP_16_TO_1 = 0x06,
+ LSM6DSO32X_CMP_32_TO_1 = 0x07,
+} lsm6dso32x_uncoptr_rate_t;
+int32_t lsm6dso32x_compression_algo_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_uncoptr_rate_t val);
+int32_t lsm6dso32x_compression_algo_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_uncoptr_rate_t *val);
+
+int32_t lsm6dso32x_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32x_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6dso32x_compression_algo_real_time_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32x_compression_algo_real_time_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6dso32x_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32x_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_XL_NOT_BATCHED = 0,
+ LSM6DSO32X_XL_BATCHED_AT_12Hz5 = 1,
+ LSM6DSO32X_XL_BATCHED_AT_26Hz = 2,
+ LSM6DSO32X_XL_BATCHED_AT_52Hz = 3,
+ LSM6DSO32X_XL_BATCHED_AT_104Hz = 4,
+ LSM6DSO32X_XL_BATCHED_AT_208Hz = 5,
+ LSM6DSO32X_XL_BATCHED_AT_417Hz = 6,
+ LSM6DSO32X_XL_BATCHED_AT_833Hz = 7,
+ LSM6DSO32X_XL_BATCHED_AT_1667Hz = 8,
+ LSM6DSO32X_XL_BATCHED_AT_3333Hz = 9,
+ LSM6DSO32X_XL_BATCHED_AT_6667Hz = 10,
+ LSM6DSO32X_XL_BATCHED_AT_6Hz5 = 11,
+} lsm6dso32x_bdr_xl_t;
+int32_t lsm6dso32x_fifo_xl_batch_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_bdr_xl_t val);
+int32_t lsm6dso32x_fifo_xl_batch_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_bdr_xl_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_GY_NOT_BATCHED = 0,
+ LSM6DSO32X_GY_BATCHED_AT_12Hz5 = 1,
+ LSM6DSO32X_GY_BATCHED_AT_26Hz = 2,
+ LSM6DSO32X_GY_BATCHED_AT_52Hz = 3,
+ LSM6DSO32X_GY_BATCHED_AT_104Hz = 4,
+ LSM6DSO32X_GY_BATCHED_AT_208Hz = 5,
+ LSM6DSO32X_GY_BATCHED_AT_417Hz = 6,
+ LSM6DSO32X_GY_BATCHED_AT_833Hz = 7,
+ LSM6DSO32X_GY_BATCHED_AT_1667Hz = 8,
+ LSM6DSO32X_GY_BATCHED_AT_3333Hz = 9,
+ LSM6DSO32X_GY_BATCHED_AT_6667Hz = 10,
+ LSM6DSO32X_GY_BATCHED_AT_6Hz5 = 11,
+} lsm6dso32x_bdr_gy_t;
+int32_t lsm6dso32x_fifo_gy_batch_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_bdr_gy_t val);
+int32_t lsm6dso32x_fifo_gy_batch_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_bdr_gy_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_BYPASS_MODE = 0,
+ LSM6DSO32X_FIFO_MODE = 1,
+ LSM6DSO32X_STREAM_TO_FIFO_MODE = 3,
+ LSM6DSO32X_BYPASS_TO_STREAM_MODE = 4,
+ LSM6DSO32X_STREAM_MODE = 6,
+ LSM6DSO32X_BYPASS_TO_FIFO_MODE = 7,
+} lsm6dso32x_fifo_mode_t;
+int32_t lsm6dso32x_fifo_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_fifo_mode_t val);
+int32_t lsm6dso32x_fifo_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_fifo_mode_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_TEMP_NOT_BATCHED = 0,
+ LSM6DSO32X_TEMP_BATCHED_AT_1Hz6 = 1,
+ LSM6DSO32X_TEMP_BATCHED_AT_12Hz5 = 2,
+ LSM6DSO32X_TEMP_BATCHED_AT_52Hz = 3,
+} lsm6dso32x_odr_t_batch_t;
+int32_t lsm6dso32x_fifo_temp_batch_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_odr_t_batch_t val);
+int32_t lsm6dso32x_fifo_temp_batch_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_odr_t_batch_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_NO_DECIMATION = 0,
+ LSM6DSO32X_DEC_1 = 1,
+ LSM6DSO32X_DEC_8 = 2,
+ LSM6DSO32X_DEC_32 = 3,
+} lsm6dso32x_odr_ts_batch_t;
+int32_t lsm6dso32x_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_odr_ts_batch_t val);
+int32_t lsm6dso32x_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_odr_ts_batch_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_XL_BATCH_EVENT = 0,
+ LSM6DSO32X_GYRO_BATCH_EVENT = 1,
+} lsm6dso32x_trig_counter_bdr_t;
+
+typedef enum
+{
+ LSM6DSO32X_GYRO_NC_TAG = 1,
+ LSM6DSO32X_XL_NC_TAG,
+ LSM6DSO32X_TEMPERATURE_TAG,
+ LSM6DSO32X_TIMESTAMP_TAG,
+ LSM6DSO32X_CFG_CHANGE_TAG,
+ LSM6DSO32X_XL_NC_T_2_TAG,
+ LSM6DSO32X_XL_NC_T_1_TAG,
+ LSM6DSO32X_XL_2XC_TAG,
+ LSM6DSO32X_XL_3XC_TAG,
+ LSM6DSO32X_GYRO_NC_T_2_TAG,
+ LSM6DSO32X_GYRO_NC_T_1_TAG,
+ LSM6DSO32X_GYRO_2XC_TAG,
+ LSM6DSO32X_GYRO_3XC_TAG,
+ LSM6DSO32X_SENSORHUB_SLAVE0_TAG,
+ LSM6DSO32X_SENSORHUB_SLAVE1_TAG,
+ LSM6DSO32X_SENSORHUB_SLAVE2_TAG,
+ LSM6DSO32X_SENSORHUB_SLAVE3_TAG,
+ LSM6DSO32X_STEP_CPUNTER_TAG,
+ LSM6DSO32X_GAME_ROTATION_TAG,
+ LSM6DSO32X_GEOMAG_ROTATION_TAG,
+ LSM6DSO32X_ROTATION_TAG,
+ LSM6DSO32X_SENSORHUB_NACK_TAG = 0x19,
+} lsm6dso32x_fifo_tag_t;
+int32_t lsm6dso32x_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_trig_counter_bdr_t val);
+int32_t lsm6dso32x_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_trig_counter_bdr_t *val);
+
+int32_t lsm6dso32x_rst_batch_counter_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32x_rst_batch_counter_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6dso32x_batch_counter_threshold_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t lsm6dso32x_batch_counter_threshold_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
+
+int32_t lsm6dso32x_fifo_data_level_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
+
+int32_t lsm6dso32x_fifo_status_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_fifo_status2_t *val);
+
+int32_t lsm6dso32x_fifo_full_flag_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6dso32x_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso32x_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso32x_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_fifo_tag_t *val);
+
+int32_t lsm6dso32x_fifo_pedo_batch_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32x_fifo_pedo_batch_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6dso32x_sh_batch_slave_0_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32x_sh_batch_slave_0_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6dso32x_sh_batch_slave_1_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32x_sh_batch_slave_1_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6dso32x_sh_batch_slave_2_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32x_sh_batch_slave_2_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6dso32x_sh_batch_slave_3_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32x_sh_batch_slave_3_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_DEN_DISABLE = 0,
+ LSM6DSO32X_LEVEL_FIFO = 6,
+ LSM6DSO32X_LEVEL_LETCHED = 3,
+ LSM6DSO32X_LEVEL_TRIGGER = 2,
+ LSM6DSO32X_EDGE_TRIGGER = 4,
+} lsm6dso32x_den_mode_t;
+int32_t lsm6dso32x_den_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_den_mode_t val);
+int32_t lsm6dso32x_den_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_den_mode_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_DEN_ACT_LOW = 0,
+ LSM6DSO32X_DEN_ACT_HIGH = 1,
+} lsm6dso32x_den_lh_t;
+int32_t lsm6dso32x_den_polarity_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_den_lh_t val);
+int32_t lsm6dso32x_den_polarity_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_den_lh_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_STAMP_IN_GY_DATA = 0,
+ LSM6DSO32X_STAMP_IN_XL_DATA = 1,
+ LSM6DSO32X_STAMP_IN_GY_XL_DATA = 2,
+} lsm6dso32x_den_xl_g_t;
+int32_t lsm6dso32x_den_enable_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_den_xl_g_t val);
+int32_t lsm6dso32x_den_enable_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_den_xl_g_t *val);
+
+int32_t lsm6dso32x_den_mark_axis_x_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32x_den_mark_axis_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6dso32x_den_mark_axis_y_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32x_den_mark_axis_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6dso32x_den_mark_axis_z_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32x_den_mark_axis_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_PEDO_BASE_MODE = 0x00,
+ LSM6DSO32X_FALSE_STEP_REJ = 0x10,
+ LSM6DSO32X_FALSE_STEP_REJ_ADV_MODE = 0x30,
+} lsm6dso32x_pedo_md_t;
+int32_t lsm6dso32x_pedo_sens_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_pedo_md_t val);
+int32_t lsm6dso32x_pedo_sens_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_pedo_md_t *val);
+
+int32_t lsm6dso32x_pedo_step_detect_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6dso32x_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lsm6dso32x_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+
+int32_t lsm6dso32x_pedo_steps_period_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t lsm6dso32x_pedo_steps_period_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
+
+int32_t lsm6dso32x_pedo_adv_detection_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32x_pedo_adv_detection_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6dso32x_pedo_false_step_rejection_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32x_pedo_false_step_rejection_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_EVERY_STEP = 0,
+ LSM6DSO32X_COUNT_OVERFLOW = 1,
+} lsm6dso32x_carry_count_en_t;
+int32_t lsm6dso32x_pedo_int_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_carry_count_en_t val);
+int32_t lsm6dso32x_pedo_int_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_carry_count_en_t *val);
+
+int32_t lsm6dso32x_motion_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6dso32x_tilt_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6dso32x_sh_mag_sensitivity_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t lsm6dso32x_sh_mag_sensitivity_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
+
+int32_t lsm6dso32x_mlc_mag_sensitivity_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t lsm6dso32x_mlc_mag_sensitivity_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
+
+int32_t lsm6dso32x_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val);
+int32_t lsm6dso32x_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val);
+
+int32_t lsm6dso32x_mag_soft_iron_set(stmdev_ctx_t *ctx,
+ uint16_t *val);
+int32_t lsm6dso32x_mag_soft_iron_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_Z_EQ_Y = 0,
+ LSM6DSO32X_Z_EQ_MIN_Y = 1,
+ LSM6DSO32X_Z_EQ_X = 2,
+ LSM6DSO32X_Z_EQ_MIN_X = 3,
+ LSM6DSO32X_Z_EQ_MIN_Z = 4,
+ LSM6DSO32X_Z_EQ_Z = 5,
+} lsm6dso32x_mag_z_axis_t;
+int32_t lsm6dso32x_mag_z_orient_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_mag_z_axis_t val);
+int32_t lsm6dso32x_mag_z_orient_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_mag_z_axis_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_Y_EQ_Y = 0,
+ LSM6DSO32X_Y_EQ_MIN_Y = 1,
+ LSM6DSO32X_Y_EQ_X = 2,
+ LSM6DSO32X_Y_EQ_MIN_X = 3,
+ LSM6DSO32X_Y_EQ_MIN_Z = 4,
+ LSM6DSO32X_Y_EQ_Z = 5,
+} lsm6dso32x_mag_y_axis_t;
+int32_t lsm6dso32x_mag_y_orient_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_mag_y_axis_t val);
+int32_t lsm6dso32x_mag_y_orient_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_mag_y_axis_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_X_EQ_Y = 0,
+ LSM6DSO32X_X_EQ_MIN_Y = 1,
+ LSM6DSO32X_X_EQ_X = 2,
+ LSM6DSO32X_X_EQ_MIN_X = 3,
+ LSM6DSO32X_X_EQ_MIN_Z = 4,
+ LSM6DSO32X_X_EQ_Z = 5,
+} lsm6dso32x_mag_x_axis_t;
+int32_t lsm6dso32x_mag_x_orient_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_mag_x_axis_t val);
+int32_t lsm6dso32x_mag_x_orient_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_mag_x_axis_t *val);
+
+int32_t lsm6dso32x_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+typedef struct
+{
+ lsm6dso32x_fsm_enable_a_t fsm_enable_a;
+ lsm6dso32x_fsm_enable_b_t fsm_enable_b;
+} lsm6dso32x_emb_fsm_enable_t;
+int32_t lsm6dso32x_fsm_enable_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_emb_fsm_enable_t *val);
+int32_t lsm6dso32x_fsm_enable_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_emb_fsm_enable_t *val);
+
+int32_t lsm6dso32x_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val);
+int32_t lsm6dso32x_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_LC_NORMAL = 0,
+ LSM6DSO32X_LC_CLEAR = 1,
+ LSM6DSO32X_LC_CLEAR_DONE = 2,
+} lsm6dso32x_fsm_lc_clr_t;
+int32_t lsm6dso32x_long_clr_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_fsm_lc_clr_t val);
+int32_t lsm6dso32x_long_clr_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_fsm_lc_clr_t *val);
+
+typedef struct
+{
+ lsm6dso32x_fsm_outs1_t fsm_outs1;
+ lsm6dso32x_fsm_outs2_t fsm_outs2;
+ lsm6dso32x_fsm_outs3_t fsm_outs3;
+ lsm6dso32x_fsm_outs4_t fsm_outs4;
+ lsm6dso32x_fsm_outs5_t fsm_outs5;
+ lsm6dso32x_fsm_outs6_t fsm_outs6;
+ lsm6dso32x_fsm_outs7_t fsm_outs7;
+ lsm6dso32x_fsm_outs8_t fsm_outs8;
+ lsm6dso32x_fsm_outs1_t fsm_outs9;
+ lsm6dso32x_fsm_outs2_t fsm_outs10;
+ lsm6dso32x_fsm_outs3_t fsm_outs11;
+ lsm6dso32x_fsm_outs4_t fsm_outs12;
+ lsm6dso32x_fsm_outs5_t fsm_outs13;
+ lsm6dso32x_fsm_outs6_t fsm_outs14;
+ lsm6dso32x_fsm_outs7_t fsm_outs15;
+ lsm6dso32x_fsm_outs8_t fsm_outs16;
+} lsm6dso32x_fsm_out_t;
+int32_t lsm6dso32x_fsm_out_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_fsm_out_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_ODR_FSM_12Hz5 = 0,
+ LSM6DSO32X_ODR_FSM_26Hz = 1,
+ LSM6DSO32X_ODR_FSM_52Hz = 2,
+ LSM6DSO32X_ODR_FSM_104Hz = 3,
+} lsm6dso32x_fsm_odr_t;
+int32_t lsm6dso32x_fsm_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_fsm_odr_t val);
+int32_t lsm6dso32x_fsm_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_fsm_odr_t *val);
+
+int32_t lsm6dso32x_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso32x_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso32x_long_cnt_int_value_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t lsm6dso32x_long_cnt_int_value_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
+
+int32_t lsm6dso32x_fsm_number_of_programs_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32x_fsm_number_of_programs_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+int32_t lsm6dso32x_fsm_start_address_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t lsm6dso32x_fsm_start_address_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
+
+int32_t lsm6dso32x_mlc_status_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_mlc_status_mainpage_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_ODR_PRGS_12Hz5 = 0,
+ LSM6DSO32X_ODR_PRGS_26Hz = 1,
+ LSM6DSO32X_ODR_PRGS_52Hz = 2,
+ LSM6DSO32X_ODR_PRGS_104Hz = 3,
+} lsm6dso32x_mlc_odr_t;
+int32_t lsm6dso32x_mlc_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_mlc_odr_t val);
+int32_t lsm6dso32x_mlc_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_mlc_odr_t *val);
+
+typedef struct
+{
+ lsm6dso32x_sensor_hub_1_t sh_byte_1;
+ lsm6dso32x_sensor_hub_2_t sh_byte_2;
+ lsm6dso32x_sensor_hub_3_t sh_byte_3;
+ lsm6dso32x_sensor_hub_4_t sh_byte_4;
+ lsm6dso32x_sensor_hub_5_t sh_byte_5;
+ lsm6dso32x_sensor_hub_6_t sh_byte_6;
+ lsm6dso32x_sensor_hub_7_t sh_byte_7;
+ lsm6dso32x_sensor_hub_8_t sh_byte_8;
+ lsm6dso32x_sensor_hub_9_t sh_byte_9;
+ lsm6dso32x_sensor_hub_10_t sh_byte_10;
+ lsm6dso32x_sensor_hub_11_t sh_byte_11;
+ lsm6dso32x_sensor_hub_12_t sh_byte_12;
+ lsm6dso32x_sensor_hub_13_t sh_byte_13;
+ lsm6dso32x_sensor_hub_14_t sh_byte_14;
+ lsm6dso32x_sensor_hub_15_t sh_byte_15;
+ lsm6dso32x_sensor_hub_16_t sh_byte_16;
+ lsm6dso32x_sensor_hub_17_t sh_byte_17;
+ lsm6dso32x_sensor_hub_18_t sh_byte_18;
+} lsm6dso32x_emb_sh_read_t;
+int32_t lsm6dso32x_sh_read_data_raw_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_emb_sh_read_t *val,
+ uint8_t len);
+
+typedef enum
+{
+ LSM6DSO32X_SLV_0 = 0,
+ LSM6DSO32X_SLV_0_1 = 1,
+ LSM6DSO32X_SLV_0_1_2 = 2,
+ LSM6DSO32X_SLV_0_1_2_3 = 3,
+} lsm6dso32x_aux_sens_on_t;
+int32_t lsm6dso32x_sh_slave_connected_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_aux_sens_on_t val);
+int32_t lsm6dso32x_sh_slave_connected_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_aux_sens_on_t *val);
+
+int32_t lsm6dso32x_sh_master_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso32x_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_EXT_PULL_UP = 0,
+ LSM6DSO32X_INTERNAL_PULL_UP = 1,
+} lsm6dso32x_shub_pu_en_t;
+int32_t lsm6dso32x_sh_pin_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_shub_pu_en_t val);
+int32_t lsm6dso32x_sh_pin_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_shub_pu_en_t *val);
+
+int32_t lsm6dso32x_sh_pass_through_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso32x_sh_pass_through_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_EXT_ON_INT2_PIN = 1,
+ LSM6DSO32X_XL_GY_DRDY = 0,
+} lsm6dso32x_start_config_t;
+int32_t lsm6dso32x_sh_syncro_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_start_config_t val);
+int32_t lsm6dso32x_sh_syncro_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_start_config_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_EACH_SH_CYCLE = 0,
+ LSM6DSO32X_ONLY_FIRST_CYCLE = 1,
+} lsm6dso32x_write_once_t;
+int32_t lsm6dso32x_sh_write_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_write_once_t val);
+int32_t lsm6dso32x_sh_write_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_write_once_t *val);
+
+int32_t lsm6dso32x_sh_reset_set(stmdev_ctx_t *ctx);
+int32_t lsm6dso32x_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_SH_ODR_104Hz = 0,
+ LSM6DSO32X_SH_ODR_52Hz = 1,
+ LSM6DSO32X_SH_ODR_26Hz = 2,
+ LSM6DSO32X_SH_ODR_13Hz = 3,
+} lsm6dso32x_shub_odr_t;
+int32_t lsm6dso32x_sh_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_shub_odr_t val);
+int32_t lsm6dso32x_sh_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_shub_odr_t *val);
+
+typedef struct
+{
+ uint8_t slv0_add;
+ uint8_t slv0_subadd;
+ uint8_t slv0_data;
+} lsm6dso32x_sh_cfg_write_t;
+int32_t lsm6dso32x_sh_cfg_write(stmdev_ctx_t *ctx,
+ lsm6dso32x_sh_cfg_write_t *val);
+
+typedef struct
+{
+ uint8_t slv_add;
+ uint8_t slv_subadd;
+ uint8_t slv_len;
+} lsm6dso32x_sh_cfg_read_t;
+int32_t lsm6dso32x_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
+ lsm6dso32x_sh_cfg_read_t *val);
+int32_t lsm6dso32x_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
+ lsm6dso32x_sh_cfg_read_t *val);
+int32_t lsm6dso32x_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
+ lsm6dso32x_sh_cfg_read_t *val);
+int32_t lsm6dso32x_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
+ lsm6dso32x_sh_cfg_read_t *val);
+
+int32_t lsm6dso32x_sh_status_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_status_master_t *val);
+typedef struct
+{
+ uint8_t ui;
+ uint8_t aux;
+} lsm6dso32x_id_t;
+int32_t lsm6dso32x_id_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_id_t *val);
+
+typedef struct
+{
+ enum
+ {
+ LSM6DSO32X_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */
+ LSM6DSO32X_SPI_4W = 0x06, /* Only SPI: SDO / SDI separated pins */
+ LSM6DSO32X_SPI_3W = 0x07, /* Only SPI: SDO / SDI share the same pin */
+ LSM6DSO32X_I2C = 0x04, /* Only I2C */
+ LSM6DSO32X_I3C_T_50us = 0x02, /* I3C: available time equal to 50 μs */
+ LSM6DSO32X_I3C_T_2us = 0x12, /* I3C: available time equal to 2 μs */
+ LSM6DSO32X_I3C_T_1ms = 0x22, /* I3C: available time equal to 1 ms */
+ LSM6DSO32X_I3C_T_25ms = 0x32, /* I3C: available time equal to 25 ms */
+ } ui_bus_md;
+ enum
+ {
+ LSM6DSO32X_SPI_4W_AUX = 0x00,
+ LSM6DSO32X_SPI_3W_AUX = 0x01,
+ } aux_bus_md;
+} lsm6dso32x_bus_mode_t;
+int32_t lsm6dso32x_bus_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_bus_mode_t val);
+int32_t lsm6dso32x_bus_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_bus_mode_t *val);
+
+typedef enum
+{
+ LSM6DSO32X_DRV_RDY = 0x00, /* Initialize the device for driver usage */
+ LSM6DSO32X_BOOT = 0x01, /* Restore calib. param. ( it takes 10ms ) */
+ LSM6DSO32X_RESET = 0x02, /* Reset configuration registers */
+ LSM6DSO32X_FIFO_COMP = 0x04, /* FIFO compression initialization request. */
+ LSM6DSO32X_FSM = 0x08, /* Finite State Machine initialization request */
+ LSM6DSO32X_MLC = 0x10, /* Machine Learning Core initialization request */
+ LSM6DSO32X_PEDO = 0x20, /* Pedometer algo initialization request. */
+ LSM6DSO32X_TILT = 0x40, /* Tilt algo initialization request */
+ LSM6DSO32X_SMOTION = 0x80, /* Significant Motion initialization request */
+} lsm6dso32x_init_t;
+int32_t lsm6dso32x_init_set(stmdev_ctx_t *ctx, lsm6dso32x_init_t val);
+
+typedef struct
+{
+uint8_t sw_reset :
+ 1; /* Restoring configuration registers */
+ uint8_t boot : 1; /* Restoring calibration parameters */
+ uint8_t drdy_xl : 1; /* Accelerometer data ready */
+ uint8_t drdy_g : 1; /* Gyroscope data ready */
+ uint8_t drdy_temp : 1; /* Temperature data ready */
+} lsm6dso32x_status_t;
+int32_t lsm6dso32x_status_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_status_t *val);
+
+typedef struct
+{
+ uint8_t sdo_sa0_pull_up : 1; /* 1 = pull-up on SDO/SA0 pin */
+uint8_t aux_sdo_ocs_pull_up :
+ 1; /* 1 = pull-up on OCS_Aux/SDO_Aux pins */
+ uint8_t int1_int2_push_pull : 1; /* 1 = push-pull / 0 = open-drain*/
+uint8_t int1_pull_down :
+ 1; /* 1 = pull-down always disabled (0=auto) */
+} lsm6dso32x_pin_conf_t;
+int32_t lsm6dso32x_pin_conf_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_pin_conf_t val);
+int32_t lsm6dso32x_pin_conf_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_pin_conf_t *val);
+
+typedef struct
+{
+ uint8_t active_low : 1; /* 1 = active low / 0 = active high */
+uint8_t base_latched :
+ 1; /* base functions are: FF, WU, 6D, Tap, Act/Inac */
+uint8_t emb_latched :
+ 1; /* emb functions are: Pedo, Tilt, SMot, Timestamp */
+} lsm6dso32x_int_mode_t;
+int32_t lsm6dso32x_interrupt_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_int_mode_t val);
+int32_t lsm6dso32x_interrupt_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_int_mode_t *val);
+
+typedef struct
+{
+ uint8_t drdy_xl : 1; /* Accelerometer data ready */
+ uint8_t drdy_g : 1; /* Gyroscope data ready */
+uint8_t drdy_temp :
+ 1; /* Temperature data ready (1 = int2 pin disable) */
+ uint8_t boot : 1; /* Restoring calibration parameters */
+ uint8_t fifo_th : 1; /* FIFO threshold reached */
+ uint8_t fifo_ovr : 1; /* FIFO overrun */
+ uint8_t fifo_full : 1; /* FIFO full */
+ uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */
+uint8_t den_flag :
+ 1; /* external trigger level recognition (DEN) */
+ uint8_t sh_endop : 1; /* sensor hub end operation */
+uint8_t timestamp :
+ 1; /* timestamp overflow (1 = int2 pin disable) */
+ uint8_t six_d : 1; /* orientation change (6D/4D detection) */
+ uint8_t double_tap : 1; /* double-tap event */
+ uint8_t free_fall : 1; /* free fall event */
+ uint8_t wake_up : 1; /* wake up event */
+ uint8_t single_tap : 1; /* single-tap event */
+uint8_t sleep_change :
+ 1; /* Act/Inact (or Vice-versa) status changed */
+ uint8_t step_detector : 1; /* Step detected */
+ uint8_t tilt : 1; /* Relative tilt event detected */
+ uint8_t sig_mot : 1; /* "significant motion" event detected */
+uint8_t fsm_lc :
+ 1; /* fsm long counter timeout interrupt event */
+ uint8_t fsm1 : 1; /* fsm 1 interrupt event */
+ uint8_t fsm2 : 1; /* fsm 2 interrupt event */
+ uint8_t fsm3 : 1; /* fsm 3 interrupt event */
+ uint8_t fsm4 : 1; /* fsm 4 interrupt event */
+ uint8_t fsm5 : 1; /* fsm 5 interrupt event */
+ uint8_t fsm6 : 1; /* fsm 6 interrupt event */
+ uint8_t fsm7 : 1; /* fsm 7 interrupt event */
+ uint8_t fsm8 : 1; /* fsm 8 interrupt event */
+ uint8_t fsm9 : 1; /* fsm 9 interrupt event */
+ uint8_t fsm10 : 1; /* fsm 10 interrupt event */
+ uint8_t fsm11 : 1; /* fsm 11 interrupt event */
+ uint8_t fsm12 : 1; /* fsm 12 interrupt event */
+ uint8_t fsm13 : 1; /* fsm 13 interrupt event */
+ uint8_t fsm14 : 1; /* fsm 14 interrupt event */
+ uint8_t fsm15 : 1; /* fsm 15 interrupt event */
+ uint8_t fsm16 : 1; /* fsm 16 interrupt event */
+ uint8_t mlc1 : 1; /* mlc 1 interrupt event */
+ uint8_t mlc2 : 1; /* mlc 2 interrupt event */
+ uint8_t mlc3 : 1; /* mlc 3 interrupt event */
+ uint8_t mlc4 : 1; /* mlc 4 interrupt event */
+ uint8_t mlc5 : 1; /* mlc 5 interrupt event */
+ uint8_t mlc6 : 1; /* mlc 6 interrupt event */
+ uint8_t mlc7 : 1; /* mlc 7 interrupt event */
+ uint8_t mlc8 : 1; /* mlc 8 interrupt event */
+} lsm6dso32x_pin_int1_route_t;
+
+int32_t lsm6dso32x_pin_int1_route_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_pin_int1_route_t val);
+int32_t lsm6dso32x_pin_int1_route_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_pin_int1_route_t *val);
+
+typedef struct
+{
+ uint8_t drdy_xl : 1; /* Accelerometer data ready */
+ uint8_t drdy_g : 1; /* Gyroscope data ready */
+ uint8_t drdy_temp : 1; /* Temperature data ready */
+ uint8_t fifo_th : 1; /* FIFO threshold reached */
+ uint8_t fifo_ovr : 1; /* FIFO overrun */
+ uint8_t fifo_full : 1; /* FIFO full */
+ uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */
+ uint8_t timestamp : 1; /* timestamp overflow */
+ uint8_t six_d : 1; /* orientation change (6D/4D detection) */
+ uint8_t double_tap : 1; /* double-tap event */
+ uint8_t free_fall : 1; /* free fall event */
+ uint8_t wake_up : 1; /* wake up event */
+ uint8_t single_tap : 1; /* single-tap event */
+uint8_t sleep_change :
+ 1; /* Act/Inact (or Vice-versa) status changed */
+ uint8_t step_detector : 1; /* Step detected */
+ uint8_t tilt : 1; /* Relative tilt event detected */
+ uint8_t sig_mot : 1; /* "significant motion" event detected */
+uint8_t fsm_lc :
+ 1; /* fsm long counter timeout interrupt event */
+ uint8_t fsm1 : 1; /* fsm 1 interrupt event */
+ uint8_t fsm2 : 1; /* fsm 2 interrupt event */
+ uint8_t fsm3 : 1; /* fsm 3 interrupt event */
+ uint8_t fsm4 : 1; /* fsm 4 interrupt event */
+ uint8_t fsm5 : 1; /* fsm 5 interrupt event */
+ uint8_t fsm6 : 1; /* fsm 6 interrupt event */
+ uint8_t fsm7 : 1; /* fsm 7 interrupt event */
+ uint8_t fsm8 : 1; /* fsm 8 interrupt event */
+ uint8_t fsm9 : 1; /* fsm 9 interrupt event */
+ uint8_t fsm10 : 1; /* fsm 10 interrupt event */
+ uint8_t fsm11 : 1; /* fsm 11 interrupt event */
+ uint8_t fsm12 : 1; /* fsm 12 interrupt event */
+ uint8_t fsm13 : 1; /* fsm 13 interrupt event */
+ uint8_t fsm14 : 1; /* fsm 14 interrupt event */
+ uint8_t fsm15 : 1; /* fsm 15 interrupt event */
+ uint8_t fsm16 : 1; /* fsm 16 interrupt event */
+ uint8_t mlc1 : 1; /* mlc 1 interrupt event */
+ uint8_t mlc2 : 1; /* mlc 2 interrupt event */
+ uint8_t mlc3 : 1; /* mlc 3 interrupt event */
+ uint8_t mlc4 : 1; /* mlc 4 interrupt event */
+ uint8_t mlc5 : 1; /* mlc 5 interrupt event */
+ uint8_t mlc6 : 1; /* mlc 6 interrupt event */
+ uint8_t mlc7 : 1; /* mlc 7 interrupt event */
+ uint8_t mlc8 : 1; /* mlc 8 interrupt event */
+} lsm6dso32x_pin_int2_route_t;
+
+int32_t lsm6dso32x_pin_int2_route_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_pin_int2_route_t val);
+int32_t lsm6dso32x_pin_int2_route_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_pin_int2_route_t *val);
+
+typedef struct
+{
+ uint8_t drdy_xl : 1; /* Accelerometer data ready */
+ uint8_t drdy_g : 1; /* Gyroscope data ready */
+ uint8_t drdy_temp : 1; /* Temperature data ready */
+uint8_t den_flag :
+ 1; /* external trigger level recognition (DEN) */
+uint8_t timestamp :
+ 1; /* timestamp overflow (1 = int2 pin disable) */
+ uint8_t free_fall : 1; /* free fall event */
+ uint8_t wake_up : 1; /* wake up event */
+ uint8_t wake_up_z : 1; /* wake up on Z axis event */
+ uint8_t wake_up_y : 1; /* wake up on Y axis event */
+ uint8_t wake_up_x : 1; /* wake up on X axis event */
+ uint8_t single_tap : 1; /* single-tap event */
+ uint8_t double_tap : 1; /* double-tap event */
+ uint8_t tap_z : 1; /* single-tap on Z axis event */
+ uint8_t tap_y : 1; /* single-tap on Y axis event */
+ uint8_t tap_x : 1; /* single-tap on X axis event */
+ uint8_t tap_sign : 1; /* sign of tap event (0-pos / 1-neg) */
+uint8_t six_d :
+ 1; /* orientation change (6D/4D detection) */
+uint8_t six_d_xl :
+ 1; /* X-axis low 6D/4D event (under threshold) */
+uint8_t six_d_xh :
+ 1; /* X-axis high 6D/4D event (over threshold) */
+uint8_t six_d_yl :
+ 1; /* Y-axis low 6D/4D event (under threshold) */
+uint8_t six_d_yh :
+ 1; /* Y-axis high 6D/4D event (over threshold) */
+uint8_t six_d_zl :
+ 1; /* Z-axis low 6D/4D event (under threshold) */
+uint8_t six_d_zh :
+ 1; /* Z-axis high 6D/4D event (over threshold) */
+uint8_t sleep_change :
+ 1; /* Act/Inact (or Vice-versa) status changed */
+uint8_t sleep_state :
+ 1; /* Act/Inact status flag (0-Act / 1-Inact) */
+ uint8_t step_detector : 1; /* Step detected */
+ uint8_t tilt : 1; /* Relative tilt event detected */
+uint8_t sig_mot :
+ 1; /* "significant motion" event detected */
+uint8_t fsm_lc :
+ 1; /* fsm long counter timeout interrupt event */
+ uint8_t fsm1 : 1; /* fsm 1 interrupt event */
+ uint8_t fsm2 : 1; /* fsm 2 interrupt event */
+ uint8_t fsm3 : 1; /* fsm 3 interrupt event */
+ uint8_t fsm4 : 1; /* fsm 4 interrupt event */
+ uint8_t fsm5 : 1; /* fsm 5 interrupt event */
+ uint8_t fsm6 : 1; /* fsm 6 interrupt event */
+ uint8_t fsm7 : 1; /* fsm 7 interrupt event */
+ uint8_t fsm8 : 1; /* fsm 8 interrupt event */
+ uint8_t fsm9 : 1; /* fsm 9 interrupt event */
+ uint8_t fsm10 : 1; /* fsm 10 interrupt event */
+ uint8_t fsm11 : 1; /* fsm 11 interrupt event */
+ uint8_t fsm12 : 1; /* fsm 12 interrupt event */
+ uint8_t fsm13 : 1; /* fsm 13 interrupt event */
+ uint8_t fsm14 : 1; /* fsm 14 interrupt event */
+ uint8_t fsm15 : 1; /* fsm 15 interrupt event */
+ uint8_t fsm16 : 1; /* fsm 16 interrupt event */
+ uint8_t mlc1 : 1; /* mlc 1 interrupt event */
+ uint8_t mlc2 : 1; /* mlc 2 interrupt event */
+ uint8_t mlc3 : 1; /* mlc 3 interrupt event */
+ uint8_t mlc4 : 1; /* mlc 4 interrupt event */
+ uint8_t mlc5 : 1; /* mlc 5 interrupt event */
+ uint8_t mlc6 : 1; /* mlc 6 interrupt event */
+ uint8_t mlc7 : 1; /* mlc 7 interrupt event */
+ uint8_t mlc8 : 1; /* mlc 8 interrupt event */
+ uint8_t sh_endop : 1; /* sensor hub end operation */
+uint8_t sh_slave0_nack :
+ 1; /* Not acknowledge on sensor hub slave 0 */
+uint8_t sh_slave1_nack :
+ 1; /* Not acknowledge on sensor hub slave 1 */
+uint8_t sh_slave2_nack :
+ 1; /* Not acknowledge on sensor hub slave 2 */
+uint8_t sh_slave3_nack :
+ 1; /* Not acknowledge on sensor hub slave 3 */
+uint8_t sh_wr_once :
+ 1; /* "WRITE_ONCE" end on sensor hub slave 0 */
+uint16_t fifo_diff :
+ 10; /* Number of unread sensor data in FIFO*/
+ uint8_t fifo_ovr_latched : 1; /* Latched FIFO overrun status */
+uint8_t fifo_bdr :
+ 1; /* FIFO Batch counter threshold reached */
+ uint8_t fifo_full : 1; /* FIFO full */
+ uint8_t fifo_ovr : 1; /* FIFO overrun */
+ uint8_t fifo_th : 1; /* FIFO threshold reached */
+} lsm6dso32x_all_sources_t;
+int32_t lsm6dso32x_all_sources_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_all_sources_t *val);
+
+typedef struct
+{
+ uint8_t odr_fine_tune;
+} lsm6dso32x_dev_cal_t;
+int32_t lsm6dso32x_calibration_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_dev_cal_t *val);
+
+typedef struct
+{
+ struct
+ {
+ struct
+ {
+ enum
+ {
+ LSM6DSO32X_XL_UI_OFF = 0x00, /* in power down */
+ LSM6DSO32X_XL_UI_1Hz6_LP = 0x1B, /* @1Hz6 (low power) */
+ LSM6DSO32X_XL_UI_1Hz6_ULP = 0x2B, /* @1Hz6 (ultra low/Gy) */
+ LSM6DSO32X_XL_UI_12Hz5_HP = 0x01, /* @12Hz5 (high performance) */
+ LSM6DSO32X_XL_UI_12Hz5_LP = 0x11, /* @12Hz5 (low power) */
+ LSM6DSO32X_XL_UI_12Hz5_ULP = 0x21, /* @12Hz5 (ultra low/Gy) */
+ LSM6DSO32X_XL_UI_26Hz_HP = 0x02, /* @26Hz (high performance) */
+ LSM6DSO32X_XL_UI_26Hz_LP = 0x12, /* @26Hz (low power) */
+ LSM6DSO32X_XL_UI_26Hz_ULP = 0x22, /* @26Hz (ultra low/Gy) */
+ LSM6DSO32X_XL_UI_52Hz_HP = 0x03, /* @52Hz (high performance) */
+ LSM6DSO32X_XL_UI_52Hz_LP = 0x13, /* @52Hz (low power) */
+ LSM6DSO32X_XL_UI_52Hz_ULP = 0x23, /* @52Hz (ultra low/Gy) */
+ LSM6DSO32X_XL_UI_104Hz_HP = 0x04, /* @104Hz (high performance) */
+ LSM6DSO32X_XL_UI_104Hz_NM = 0x14, /* @104Hz (normal mode) */
+ LSM6DSO32X_XL_UI_104Hz_ULP = 0x24, /* @104Hz (ultra low/Gy) */
+ LSM6DSO32X_XL_UI_208Hz_HP = 0x05, /* @208Hz (high performance) */
+ LSM6DSO32X_XL_UI_208Hz_NM = 0x15, /* @208Hz (normal mode) */
+ LSM6DSO32X_XL_UI_208Hz_ULP = 0x25, /* @208Hz (ultra low/Gy) */
+ LSM6DSO32X_XL_UI_416Hz_HP = 0x06, /* @416Hz (high performance) */
+ LSM6DSO32X_XL_UI_833Hz_HP = 0x07, /* @833Hz (high performance) */
+ LSM6DSO32X_XL_UI_1667Hz_HP = 0x08, /* @1kHz66 (high performance) */
+ LSM6DSO32X_XL_UI_3333Hz_HP = 0x09, /* @3kHz33 (high performance) */
+ LSM6DSO32X_XL_UI_6667Hz_HP = 0x0A, /* @6kHz66 (high performance) */
+ } odr;
+ enum
+ {
+ LSM6DSO32X_XL_UI_4g = 0,
+ LSM6DSO32X_XL_UI_32g = 1,
+ LSM6DSO32X_XL_UI_8g = 2,
+ LSM6DSO32X_XL_UI_16g = 3,
+ } fs;
+ } xl;
+ struct
+ {
+ enum
+ {
+ LSM6DSO32X_GY_UI_OFF = 0x00, /* gy in power down */
+ LSM6DSO32X_GY_UI_12Hz5_LP = 0x11, /* gy @12Hz5 (low power) */
+ LSM6DSO32X_GY_UI_12Hz5_HP = 0x01, /* gy @12Hz5 (high performance) */
+ LSM6DSO32X_GY_UI_26Hz_LP = 0x12, /* gy @26Hz (low power) */
+ LSM6DSO32X_GY_UI_26Hz_HP = 0x02, /* gy @26Hz (high performance) */
+ LSM6DSO32X_GY_UI_52Hz_LP = 0x13, /* gy @52Hz (low power) */
+ LSM6DSO32X_GY_UI_52Hz_HP = 0x03, /* gy @52Hz (high performance) */
+ LSM6DSO32X_GY_UI_104Hz_NM = 0x14, /* gy @104Hz (low power) */
+ LSM6DSO32X_GY_UI_104Hz_HP = 0x04, /* gy @104Hz (high performance) */
+ LSM6DSO32X_GY_UI_208Hz_NM = 0x15, /* gy @208Hz (low power) */
+ LSM6DSO32X_GY_UI_208Hz_HP = 0x05, /* gy @208Hz (high performance) */
+ LSM6DSO32X_GY_UI_416Hz_HP = 0x06, /* gy @416Hz (high performance) */
+ LSM6DSO32X_GY_UI_833Hz_HP = 0x07, /* gy @833Hz (high performance) */
+ LSM6DSO32X_GY_UI_1667Hz_HP = 0x08, /* gy @1kHz66 (high performance) */
+ LSM6DSO32X_GY_UI_3333Hz_HP = 0x09, /* gy @3kHz33 (high performance) */
+ LSM6DSO32X_GY_UI_6667Hz_HP = 0x0A, /* gy @6kHz66 (high performance) */
+ } odr;
+ enum
+ {
+ LSM6DSO32X_GY_UI_250dps = 0,
+ LSM6DSO32X_GY_UI_125dps = 1,
+ LSM6DSO32X_GY_UI_500dps = 2,
+ LSM6DSO32X_GY_UI_1000dps = 4,
+ LSM6DSO32X_GY_UI_2000dps = 6,
+ } fs;
+ } gy;
+ } ui;
+ struct
+ {
+ enum
+ {
+ LSM6DSO32X_FSM_DISABLE = 0x00,
+ LSM6DSO32X_FSM_XL = 0x01,
+ LSM6DSO32X_FSM_GY = 0x02,
+ LSM6DSO32X_FSM_XL_GY = 0x03,
+ } sens;
+ enum
+ {
+ LSM6DSO32X_FSM_12Hz5 = 0x00,
+ LSM6DSO32X_FSM_26Hz = 0x01,
+ LSM6DSO32X_FSM_52Hz = 0x02,
+ LSM6DSO32X_FSM_104Hz = 0x03,
+ } odr;
+ } fsm;
+ struct
+ {
+ enum
+ {
+ LSM6DSO32X_MLC_DISABLE = 0x00,
+ LSM6DSO32X_MLC_XL = 0x01,
+ LSM6DSO32X_MLC_XL_GY = 0x03,
+ } sens;
+ enum
+ {
+ LSM6DSO32X_MLC_12Hz5 = 0x00,
+ LSM6DSO32X_MLC_26Hz = 0x01,
+ LSM6DSO32X_MLC_52Hz = 0x02,
+ LSM6DSO32X_MLC_104Hz = 0x03,
+ } odr;
+ } mlc;
+} lsm6dso32x_md_t;
+int32_t lsm6dso32x_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_md_t *val);
+int32_t lsm6dso32x_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_md_t *val);
+
+typedef struct
+{
+ struct
+ {
+ struct
+ {
+ float mg[3];
+ int16_t raw[3];
+ } xl;
+ struct
+ {
+ float mdps[3];
+ int16_t raw[3];
+ } gy;
+ struct
+ {
+ float deg_c;
+ int16_t raw;
+ } heat;
+ } ui;
+} lsm6dso32x_data_t;
+int32_t lsm6dso32x_data_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_md_t *md,
+ lsm6dso32x_data_t *data);
+
+typedef struct
+{
+ uint8_t sig_mot : 1; /* significant motion */
+ uint8_t tilt : 1; /* tilt detection */
+ uint8_t step : 1; /* step counter/detector */
+ uint8_t mlc : 1; /* machine learning core */
+ uint8_t fsm : 1; /* finite state machine */
+ uint8_t fifo_compr : 1; /* mlc 8 interrupt event */
+} lsm6dso32x_emb_sens_t;
+int32_t lsm6dso32x_embedded_sens_set(stmdev_ctx_t *ctx,
+ lsm6dso32x_emb_sens_t *emb_sens);
+int32_t lsm6dso32x_embedded_sens_get(stmdev_ctx_t *ctx,
+ lsm6dso32x_emb_sens_t *emb_sens);
+int32_t lsm6dso32x_embedded_sens_off(stmdev_ctx_t *ctx);
+
+/**
+ * @}
+ *
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*LSM6DSO32X_DRIVER_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.c b/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.c
index 3e4d4c30faad0f68d4fb2a9a2741aed18dc24758..8b4837650b101c5283f084696786667eb9a36e0d 100644
--- a/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.c
+++ b/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.c
@@ -1,23 +1,24 @@
-/*
- ******************************************************************************
- * @file lsm6dso_reg.c
- * @author Sensors Software Solution Team
- * @brief LSM6DSO driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lsm6dso_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LSM6DSO driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lsm6dso_reg.h"
+#include
/**
* @defgroup LSM6DSO
@@ -25,7 +26,7 @@
* lsm6dso enhanced inertial module.
* @{
*
-*/
+ */
/**
* @defgroup LSM6DSO_Interfaces_Functions
@@ -34,7 +35,7 @@
* MANDATORY: return 0 -> no Error.
* @{
*
-*/
+ */
/**
* @brief Read generic device register
@@ -46,11 +47,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lsm6dso_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,18 +68,21 @@ int32_t lsm6dso_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lsm6dso_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
/**
* @}
*
-*/
+ */
/**
* @defgroup LSM6DSOX_Private_functions
@@ -86,7 +93,8 @@ int32_t lsm6dso_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
static void bytecpy(uint8_t *target, uint8_t *source)
{
- if ( (target != NULL) && (source != NULL) ) {
+ if ((target != NULL) && (source != NULL))
+ {
*target = *source;
}
}
@@ -96,7 +104,7 @@ static void bytecpy(uint8_t *target, uint8_t *source)
* @brief These functions convert raw-data into engineering units.
* @{
*
-*/
+ */
float_t lsm6dso_from_fs2_to_mg(int16_t lsb)
{
return ((float_t)lsb) * 0.061f;
@@ -114,32 +122,32 @@ float_t lsm6dso_from_fs8_to_mg(int16_t lsb)
float_t lsm6dso_from_fs16_to_mg(int16_t lsb)
{
- return ((float_t)lsb) *0.488f;
+ return ((float_t)lsb) * 0.488f;
}
float_t lsm6dso_from_fs125_to_mdps(int16_t lsb)
{
- return ((float_t)lsb) *4.375f;
+ return ((float_t)lsb) * 4.375f;
}
float_t lsm6dso_from_fs500_to_mdps(int16_t lsb)
{
- return ((float_t)lsb) *17.50f;
+ return ((float_t)lsb) * 17.50f;
}
float_t lsm6dso_from_fs250_to_mdps(int16_t lsb)
{
- return ((float_t)lsb) *8.750f;
+ return ((float_t)lsb) * 8.750f;
}
float_t lsm6dso_from_fs1000_to_mdps(int16_t lsb)
{
- return ((float_t)lsb) *35.0f;
+ return ((float_t)lsb) * 35.0f;
}
float_t lsm6dso_from_fs2000_to_mdps(int16_t lsb)
{
- return ((float_t)lsb) *70.0f;
+ return ((float_t)lsb) * 70.0f;
}
float_t lsm6dso_from_lsb_to_celsius(int16_t lsb)
@@ -155,20 +163,21 @@ float_t lsm6dso_from_lsb_to_nsec(int16_t lsb)
/**
* @}
*
-*/
+ */
/**
* @defgroup LSM6DSO_Data_Generation
* @brief This section groups all the functions concerning
* data generation.
*
-*/
+ */
/**
* @brief Accelerometer full-scale selection.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of fs_xl in reg CTRL1_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_xl_full_scale_set(stmdev_ctx_t *ctx,
@@ -177,11 +186,14 @@ int32_t lsm6dso_xl_full_scale_set(stmdev_ctx_t *ctx,
lsm6dso_ctrl1_xl_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.fs_xl = (uint8_t) val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -190,27 +202,35 @@ int32_t lsm6dso_xl_full_scale_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of fs_xl in reg CTRL1_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_xl_full_scale_get(stmdev_ctx_t *ctx, lsm6dso_fs_xl_t *val)
+int32_t lsm6dso_xl_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6dso_fs_xl_t *val)
{
lsm6dso_ctrl1_xl_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)®, 1);
- switch (reg.fs_xl) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1);
+
+ switch (reg.fs_xl)
+ {
case LSM6DSO_2g:
*val = LSM6DSO_2g;
break;
+
case LSM6DSO_16g:
*val = LSM6DSO_16g;
break;
+
case LSM6DSO_4g:
*val = LSM6DSO_4g;
break;
+
case LSM6DSO_8g:
*val = LSM6DSO_8g;
break;
+
default:
*val = LSM6DSO_2g;
break;
@@ -224,9 +244,11 @@ int32_t lsm6dso_xl_full_scale_get(stmdev_ctx_t *ctx, lsm6dso_fs_xl_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of odr_xl in reg CTRL1_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6dso_odr_xl_t val)
+int32_t lsm6dso_xl_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dso_odr_xl_t val)
{
lsm6dso_odr_xl_t odr_xl = val;
lsm6dso_emb_fsm_enable_t fsm_enable;
@@ -236,81 +258,114 @@ int32_t lsm6dso_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6dso_odr_xl_t val)
/* Check the Finite State Machine data rate constraints */
ret = lsm6dso_fsm_enable_get(ctx, &fsm_enable);
- if (ret == 0) {
- if ( (fsm_enable.fsm_enable_a.fsm1_en |
- fsm_enable.fsm_enable_a.fsm2_en |
- fsm_enable.fsm_enable_a.fsm3_en |
- fsm_enable.fsm_enable_a.fsm4_en |
- fsm_enable.fsm_enable_a.fsm5_en |
- fsm_enable.fsm_enable_a.fsm6_en |
- fsm_enable.fsm_enable_a.fsm7_en |
- fsm_enable.fsm_enable_a.fsm8_en |
- fsm_enable.fsm_enable_b.fsm9_en |
- fsm_enable.fsm_enable_b.fsm10_en |
- fsm_enable.fsm_enable_b.fsm11_en |
- fsm_enable.fsm_enable_b.fsm12_en |
- fsm_enable.fsm_enable_b.fsm13_en |
- fsm_enable.fsm_enable_b.fsm14_en |
- fsm_enable.fsm_enable_b.fsm15_en |
- fsm_enable.fsm_enable_b.fsm16_en ) == PROPERTY_ENABLE ){
+ if (ret == 0)
+ {
+ if ((fsm_enable.fsm_enable_a.fsm1_en |
+ fsm_enable.fsm_enable_a.fsm2_en |
+ fsm_enable.fsm_enable_a.fsm3_en |
+ fsm_enable.fsm_enable_a.fsm4_en |
+ fsm_enable.fsm_enable_a.fsm5_en |
+ fsm_enable.fsm_enable_a.fsm6_en |
+ fsm_enable.fsm_enable_a.fsm7_en |
+ fsm_enable.fsm_enable_a.fsm8_en |
+ fsm_enable.fsm_enable_b.fsm9_en |
+ fsm_enable.fsm_enable_b.fsm10_en |
+ fsm_enable.fsm_enable_b.fsm11_en |
+ fsm_enable.fsm_enable_b.fsm12_en |
+ fsm_enable.fsm_enable_b.fsm13_en |
+ fsm_enable.fsm_enable_b.fsm14_en |
+ fsm_enable.fsm_enable_b.fsm15_en |
+ fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
+ {
ret = lsm6dso_fsm_data_rate_get(ctx, &fsm_odr);
- if (ret == 0) {
- switch (fsm_odr) {
- case LSM6DSO_ODR_FSM_12Hz5:
- if (val == LSM6DSO_XL_ODR_OFF){
+ if (ret == 0)
+ {
+ switch (fsm_odr)
+ {
+ case LSM6DSO_ODR_FSM_12Hz5:
+ if (val == LSM6DSO_XL_ODR_OFF)
+ {
odr_xl = LSM6DSO_XL_ODR_12Hz5;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
- case LSM6DSO_ODR_FSM_26Hz:
- if (val == LSM6DSO_XL_ODR_OFF){
+ case LSM6DSO_ODR_FSM_26Hz:
+ if (val == LSM6DSO_XL_ODR_OFF)
+ {
odr_xl = LSM6DSO_XL_ODR_26Hz;
+ }
- } else if (val == LSM6DSO_XL_ODR_12Hz5){
+ else if (val == LSM6DSO_XL_ODR_12Hz5)
+ {
odr_xl = LSM6DSO_XL_ODR_26Hz;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
- case LSM6DSO_ODR_FSM_52Hz:
- if (val == LSM6DSO_XL_ODR_OFF){
+ case LSM6DSO_ODR_FSM_52Hz:
+ if (val == LSM6DSO_XL_ODR_OFF)
+ {
odr_xl = LSM6DSO_XL_ODR_52Hz;
+ }
- } else if (val == LSM6DSO_XL_ODR_12Hz5){
+ else if (val == LSM6DSO_XL_ODR_12Hz5)
+ {
odr_xl = LSM6DSO_XL_ODR_52Hz;
+ }
- } else if (val == LSM6DSO_XL_ODR_26Hz){
+ else if (val == LSM6DSO_XL_ODR_26Hz)
+ {
odr_xl = LSM6DSO_XL_ODR_52Hz;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
- case LSM6DSO_ODR_FSM_104Hz:
- if (val == LSM6DSO_XL_ODR_OFF){
+ case LSM6DSO_ODR_FSM_104Hz:
+ if (val == LSM6DSO_XL_ODR_OFF)
+ {
odr_xl = LSM6DSO_XL_ODR_104Hz;
+ }
- } else if (val == LSM6DSO_XL_ODR_12Hz5){
+ else if (val == LSM6DSO_XL_ODR_12Hz5)
+ {
odr_xl = LSM6DSO_XL_ODR_104Hz;
+ }
- } else if (val == LSM6DSO_XL_ODR_26Hz){
+ else if (val == LSM6DSO_XL_ODR_26Hz)
+ {
odr_xl = LSM6DSO_XL_ODR_104Hz;
+ }
- } else if (val == LSM6DSO_XL_ODR_52Hz){
+ else if (val == LSM6DSO_XL_ODR_52Hz)
+ {
odr_xl = LSM6DSO_XL_ODR_104Hz;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
+
default:
odr_xl = val;
break;
@@ -318,13 +373,18 @@ int32_t lsm6dso_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6dso_odr_xl_t val)
}
}
}
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.odr_xl = (uint8_t) odr_xl;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -333,56 +393,72 @@ int32_t lsm6dso_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6dso_odr_xl_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of odr_xl in reg CTRL1_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_xl_data_rate_get(stmdev_ctx_t *ctx, lsm6dso_odr_xl_t *val)
+int32_t lsm6dso_xl_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dso_odr_xl_t *val)
{
lsm6dso_ctrl1_xl_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1);
- switch (reg.odr_xl) {
+ switch (reg.odr_xl)
+ {
case LSM6DSO_XL_ODR_OFF:
*val = LSM6DSO_XL_ODR_OFF;
break;
+
case LSM6DSO_XL_ODR_12Hz5:
*val = LSM6DSO_XL_ODR_12Hz5;
break;
+
case LSM6DSO_XL_ODR_26Hz:
*val = LSM6DSO_XL_ODR_26Hz;
break;
+
case LSM6DSO_XL_ODR_52Hz:
*val = LSM6DSO_XL_ODR_52Hz;
break;
+
case LSM6DSO_XL_ODR_104Hz:
*val = LSM6DSO_XL_ODR_104Hz;
break;
+
case LSM6DSO_XL_ODR_208Hz:
*val = LSM6DSO_XL_ODR_208Hz;
break;
+
case LSM6DSO_XL_ODR_417Hz:
*val = LSM6DSO_XL_ODR_417Hz;
break;
+
case LSM6DSO_XL_ODR_833Hz:
*val = LSM6DSO_XL_ODR_833Hz;
break;
+
case LSM6DSO_XL_ODR_1667Hz:
*val = LSM6DSO_XL_ODR_1667Hz;
break;
+
case LSM6DSO_XL_ODR_3333Hz:
*val = LSM6DSO_XL_ODR_3333Hz;
break;
+
case LSM6DSO_XL_ODR_6667Hz:
*val = LSM6DSO_XL_ODR_6667Hz;
break;
+
case LSM6DSO_XL_ODR_1Hz6:
*val = LSM6DSO_XL_ODR_1Hz6;
break;
+
default:
*val = LSM6DSO_XL_ODR_OFF;
break;
}
+
return ret;
}
@@ -391,17 +467,21 @@ int32_t lsm6dso_xl_data_rate_get(stmdev_ctx_t *ctx, lsm6dso_odr_xl_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of fs_g in reg CTRL2_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_gy_full_scale_set(stmdev_ctx_t *ctx, lsm6dso_fs_g_t val)
+int32_t lsm6dso_gy_full_scale_set(stmdev_ctx_t *ctx,
+ lsm6dso_fs_g_t val)
{
lsm6dso_ctrl2_g_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.fs_g = (uint8_t) val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)®, 1);
}
return ret;
@@ -412,30 +492,39 @@ int32_t lsm6dso_gy_full_scale_set(stmdev_ctx_t *ctx, lsm6dso_fs_g_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of fs_g in reg CTRL2_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_gy_full_scale_get(stmdev_ctx_t *ctx, lsm6dso_fs_g_t *val)
+int32_t lsm6dso_gy_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6dso_fs_g_t *val)
{
lsm6dso_ctrl2_g_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t*)®, 1);
- switch (reg.fs_g) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)®, 1);
+
+ switch (reg.fs_g)
+ {
case LSM6DSO_250dps:
*val = LSM6DSO_250dps;
break;
+
case LSM6DSO_125dps:
*val = LSM6DSO_125dps;
break;
+
case LSM6DSO_500dps:
*val = LSM6DSO_500dps;
break;
+
case LSM6DSO_1000dps:
*val = LSM6DSO_1000dps;
break;
+
case LSM6DSO_2000dps:
*val = LSM6DSO_2000dps;
break;
+
default:
*val = LSM6DSO_250dps;
break;
@@ -449,9 +538,11 @@ int32_t lsm6dso_gy_full_scale_get(stmdev_ctx_t *ctx, lsm6dso_fs_g_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of odr_g in reg CTRL2_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_gy_data_rate_set(stmdev_ctx_t *ctx, lsm6dso_odr_g_t val)
+int32_t lsm6dso_gy_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dso_odr_g_t val)
{
lsm6dso_odr_g_t odr_gy = val;
lsm6dso_emb_fsm_enable_t fsm_enable;
@@ -461,81 +552,114 @@ int32_t lsm6dso_gy_data_rate_set(stmdev_ctx_t *ctx, lsm6dso_odr_g_t val)
/* Check the Finite State Machine data rate constraints */
ret = lsm6dso_fsm_enable_get(ctx, &fsm_enable);
- if (ret == 0) {
- if ( (fsm_enable.fsm_enable_a.fsm1_en |
- fsm_enable.fsm_enable_a.fsm2_en |
- fsm_enable.fsm_enable_a.fsm3_en |
- fsm_enable.fsm_enable_a.fsm4_en |
- fsm_enable.fsm_enable_a.fsm5_en |
- fsm_enable.fsm_enable_a.fsm6_en |
- fsm_enable.fsm_enable_a.fsm7_en |
- fsm_enable.fsm_enable_a.fsm8_en |
- fsm_enable.fsm_enable_b.fsm9_en |
- fsm_enable.fsm_enable_b.fsm10_en |
- fsm_enable.fsm_enable_b.fsm11_en |
- fsm_enable.fsm_enable_b.fsm12_en |
- fsm_enable.fsm_enable_b.fsm13_en |
- fsm_enable.fsm_enable_b.fsm14_en |
- fsm_enable.fsm_enable_b.fsm15_en |
- fsm_enable.fsm_enable_b.fsm16_en ) == PROPERTY_ENABLE ){
+ if (ret == 0)
+ {
+ if ((fsm_enable.fsm_enable_a.fsm1_en |
+ fsm_enable.fsm_enable_a.fsm2_en |
+ fsm_enable.fsm_enable_a.fsm3_en |
+ fsm_enable.fsm_enable_a.fsm4_en |
+ fsm_enable.fsm_enable_a.fsm5_en |
+ fsm_enable.fsm_enable_a.fsm6_en |
+ fsm_enable.fsm_enable_a.fsm7_en |
+ fsm_enable.fsm_enable_a.fsm8_en |
+ fsm_enable.fsm_enable_b.fsm9_en |
+ fsm_enable.fsm_enable_b.fsm10_en |
+ fsm_enable.fsm_enable_b.fsm11_en |
+ fsm_enable.fsm_enable_b.fsm12_en |
+ fsm_enable.fsm_enable_b.fsm13_en |
+ fsm_enable.fsm_enable_b.fsm14_en |
+ fsm_enable.fsm_enable_b.fsm15_en |
+ fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
+ {
ret = lsm6dso_fsm_data_rate_get(ctx, &fsm_odr);
- if (ret == 0) {
- switch (fsm_odr) {
- case LSM6DSO_ODR_FSM_12Hz5:
- if (val == LSM6DSO_GY_ODR_OFF){
+ if (ret == 0)
+ {
+ switch (fsm_odr)
+ {
+ case LSM6DSO_ODR_FSM_12Hz5:
+ if (val == LSM6DSO_GY_ODR_OFF)
+ {
odr_gy = LSM6DSO_GY_ODR_12Hz5;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
- case LSM6DSO_ODR_FSM_26Hz:
- if (val == LSM6DSO_GY_ODR_OFF){
+ case LSM6DSO_ODR_FSM_26Hz:
+ if (val == LSM6DSO_GY_ODR_OFF)
+ {
odr_gy = LSM6DSO_GY_ODR_26Hz;
+ }
- } else if (val == LSM6DSO_GY_ODR_12Hz5){
+ else if (val == LSM6DSO_GY_ODR_12Hz5)
+ {
odr_gy = LSM6DSO_GY_ODR_26Hz;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
- case LSM6DSO_ODR_FSM_52Hz:
- if (val == LSM6DSO_GY_ODR_OFF){
+ case LSM6DSO_ODR_FSM_52Hz:
+ if (val == LSM6DSO_GY_ODR_OFF)
+ {
odr_gy = LSM6DSO_GY_ODR_52Hz;
+ }
- } else if (val == LSM6DSO_GY_ODR_12Hz5){
+ else if (val == LSM6DSO_GY_ODR_12Hz5)
+ {
odr_gy = LSM6DSO_GY_ODR_52Hz;
+ }
- } else if (val == LSM6DSO_GY_ODR_26Hz){
+ else if (val == LSM6DSO_GY_ODR_26Hz)
+ {
odr_gy = LSM6DSO_GY_ODR_52Hz;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
- case LSM6DSO_ODR_FSM_104Hz:
- if (val == LSM6DSO_GY_ODR_OFF){
+ case LSM6DSO_ODR_FSM_104Hz:
+ if (val == LSM6DSO_GY_ODR_OFF)
+ {
odr_gy = LSM6DSO_GY_ODR_104Hz;
+ }
- } else if (val == LSM6DSO_GY_ODR_12Hz5){
+ else if (val == LSM6DSO_GY_ODR_12Hz5)
+ {
odr_gy = LSM6DSO_GY_ODR_104Hz;
+ }
- } else if (val == LSM6DSO_GY_ODR_26Hz){
+ else if (val == LSM6DSO_GY_ODR_26Hz)
+ {
odr_gy = LSM6DSO_GY_ODR_104Hz;
+ }
- } else if (val == LSM6DSO_GY_ODR_52Hz){
+ else if (val == LSM6DSO_GY_ODR_52Hz)
+ {
odr_gy = LSM6DSO_GY_ODR_104Hz;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
+
default:
odr_gy = val;
break;
@@ -544,12 +668,15 @@ int32_t lsm6dso_gy_data_rate_set(stmdev_ctx_t *ctx, lsm6dso_odr_g_t val)
}
}
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t*)®, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.odr_g = (uint8_t) odr_gy;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)®, 1);
}
return ret;
@@ -560,52 +687,68 @@ int32_t lsm6dso_gy_data_rate_set(stmdev_ctx_t *ctx, lsm6dso_odr_g_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of odr_g in reg CTRL2_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_gy_data_rate_get(stmdev_ctx_t *ctx, lsm6dso_odr_g_t *val)
+int32_t lsm6dso_gy_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dso_odr_g_t *val)
{
lsm6dso_ctrl2_g_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t*)®, 1);
- switch (reg.odr_g) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)®, 1);
+
+ switch (reg.odr_g)
+ {
case LSM6DSO_GY_ODR_OFF:
*val = LSM6DSO_GY_ODR_OFF;
break;
+
case LSM6DSO_GY_ODR_12Hz5:
*val = LSM6DSO_GY_ODR_12Hz5;
break;
+
case LSM6DSO_GY_ODR_26Hz:
*val = LSM6DSO_GY_ODR_26Hz;
break;
+
case LSM6DSO_GY_ODR_52Hz:
*val = LSM6DSO_GY_ODR_52Hz;
break;
+
case LSM6DSO_GY_ODR_104Hz:
*val = LSM6DSO_GY_ODR_104Hz;
break;
+
case LSM6DSO_GY_ODR_208Hz:
*val = LSM6DSO_GY_ODR_208Hz;
break;
+
case LSM6DSO_GY_ODR_417Hz:
*val = LSM6DSO_GY_ODR_417Hz;
break;
+
case LSM6DSO_GY_ODR_833Hz:
*val = LSM6DSO_GY_ODR_833Hz;
break;
+
case LSM6DSO_GY_ODR_1667Hz:
*val = LSM6DSO_GY_ODR_1667Hz;
break;
+
case LSM6DSO_GY_ODR_3333Hz:
*val = LSM6DSO_GY_ODR_3333Hz;
break;
+
case LSM6DSO_GY_ODR_6667Hz:
*val = LSM6DSO_GY_ODR_6667Hz;
break;
+
default:
*val = LSM6DSO_GY_ODR_OFF;
break;
}
+
return ret;
}
@@ -614,6 +757,7 @@ int32_t lsm6dso_gy_data_rate_get(stmdev_ctx_t *ctx, lsm6dso_odr_g_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of bdu in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -621,11 +765,14 @@ int32_t lsm6dso_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.bdu = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -634,6 +781,7 @@ int32_t lsm6dso_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of bdu in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -641,7 +789,7 @@ int32_t lsm6dso_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
*val = reg.bdu;
return ret;
@@ -653,6 +801,7 @@ int32_t lsm6dso_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of usr_off_w in reg CTRL6_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_xl_offset_weight_set(stmdev_ctx_t *ctx,
@@ -661,11 +810,14 @@ int32_t lsm6dso_xl_offset_weight_set(stmdev_ctx_t *ctx,
lsm6dso_ctrl6_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.usr_off_w = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -675,6 +827,7 @@ int32_t lsm6dso_xl_offset_weight_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of usr_off_w in reg CTRL6_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_xl_offset_weight_get(stmdev_ctx_t *ctx,
@@ -683,19 +836,23 @@ int32_t lsm6dso_xl_offset_weight_get(stmdev_ctx_t *ctx,
lsm6dso_ctrl6_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1);
- switch (reg.usr_off_w) {
+ switch (reg.usr_off_w)
+ {
case LSM6DSO_LSb_1mg:
*val = LSM6DSO_LSb_1mg;
break;
+
case LSM6DSO_LSb_16mg:
*val = LSM6DSO_LSb_16mg;
break;
+
default:
*val = LSM6DSO_LSb_1mg;
break;
}
+
return ret;
}
@@ -705,6 +862,7 @@ int32_t lsm6dso_xl_offset_weight_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of xl_hm_mode in
* reg CTRL6_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_xl_power_mode_set(stmdev_ctx_t *ctx,
@@ -714,18 +872,25 @@ int32_t lsm6dso_xl_power_mode_set(stmdev_ctx_t *ctx,
lsm6dso_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*) &ctrl5_c, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *) &ctrl5_c, 1);
+
+ if (ret == 0)
+ {
ctrl5_c.xl_ulp_en = ((uint8_t)val & 0x02U) >> 1;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*) &ctrl5_c, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *) &ctrl5_c, 1);
}
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*) &ctrl6_c, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *) &ctrl6_c, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*) &ctrl6_c, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *) &ctrl6_c, 1);
}
+
return ret;
}
@@ -734,6 +899,7 @@ int32_t lsm6dso_xl_power_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of xl_hm_mode in reg CTRL6_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_xl_power_mode_get(stmdev_ctx_t *ctx,
@@ -743,24 +909,32 @@ int32_t lsm6dso_xl_power_mode_get(stmdev_ctx_t *ctx,
lsm6dso_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*) &ctrl5_c, 1);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*) &ctrl6_c, 1);
- switch ( (ctrl5_c.xl_ulp_en << 1) | ctrl6_c.xl_hm_mode) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *) &ctrl5_c, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *) &ctrl6_c, 1);
+
+ switch ((ctrl5_c.xl_ulp_en << 1) | ctrl6_c.xl_hm_mode)
+ {
case LSM6DSO_HIGH_PERFORMANCE_MD:
*val = LSM6DSO_HIGH_PERFORMANCE_MD;
break;
+
case LSM6DSO_LOW_NORMAL_POWER_MD:
*val = LSM6DSO_LOW_NORMAL_POWER_MD;
break;
+
case LSM6DSO_ULTRA_LOW_POWER_MD:
*val = LSM6DSO_ULTRA_LOW_POWER_MD;
break;
+
default:
*val = LSM6DSO_HIGH_PERFORMANCE_MD;
break;
}
}
+
return ret;
}
@@ -769,6 +943,7 @@ int32_t lsm6dso_xl_power_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of g_hm_mode in reg CTRL7_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_gy_power_mode_set(stmdev_ctx_t *ctx,
@@ -777,11 +952,14 @@ int32_t lsm6dso_gy_power_mode_set(stmdev_ctx_t *ctx,
lsm6dso_ctrl7_g_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.g_hm_mode = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -790,6 +968,7 @@ int32_t lsm6dso_gy_power_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of g_hm_mode in reg CTRL7_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_gy_power_mode_get(stmdev_ctx_t *ctx,
@@ -798,18 +977,23 @@ int32_t lsm6dso_gy_power_mode_get(stmdev_ctx_t *ctx,
lsm6dso_ctrl7_g_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)®, 1);
- switch (reg.g_hm_mode) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
+
+ switch (reg.g_hm_mode)
+ {
case LSM6DSO_GY_HIGH_PERFORMANCE:
*val = LSM6DSO_GY_HIGH_PERFORMANCE;
break;
+
case LSM6DSO_GY_NORMAL:
*val = LSM6DSO_GY_NORMAL;
break;
+
default:
*val = LSM6DSO_GY_HIGH_PERFORMANCE;
break;
}
+
return ret;
}
@@ -818,12 +1002,16 @@ int32_t lsm6dso_gy_power_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val register STATUS_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_status_reg_get(stmdev_ctx_t *ctx, lsm6dso_status_reg_t *val)
+int32_t lsm6dso_status_reg_get(stmdev_ctx_t *ctx,
+ lsm6dso_status_reg_t *val)
{
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t*) val, 1);
+
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t *) val, 1);
+
return ret;
}
@@ -832,14 +1020,16 @@ int32_t lsm6dso_status_reg_get(stmdev_ctx_t *ctx, lsm6dso_status_reg_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of xlda in reg STATUS_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso_status_reg_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t *)®, 1);
*val = reg.xlda;
return ret;
@@ -850,14 +1040,16 @@ int32_t lsm6dso_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of gda in reg STATUS_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso_status_reg_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t *)®, 1);
*val = reg.gda;
return ret;
@@ -868,14 +1060,16 @@ int32_t lsm6dso_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of tda in reg STATUS_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso_status_reg_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t *)®, 1);
*val = reg.tda;
return ret;
@@ -888,12 +1082,15 @@ int32_t lsm6dso_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dso_write_reg(ctx, LSM6DSO_X_OFS_USR, buff, 1);
+
return ret;
}
@@ -904,12 +1101,15 @@ int32_t lsm6dso_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dso_read_reg(ctx, LSM6DSO_X_OFS_USR, buff, 1);
+
return ret;
}
@@ -920,12 +1120,15 @@ int32_t lsm6dso_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dso_write_reg(ctx, LSM6DSO_Y_OFS_USR, buff, 1);
+
return ret;
}
@@ -936,12 +1139,15 @@ int32_t lsm6dso_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dso_read_reg(ctx, LSM6DSO_Y_OFS_USR, buff, 1);
+
return ret;
}
@@ -952,12 +1158,15 @@ int32_t lsm6dso_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dso_write_reg(ctx, LSM6DSO_Z_OFS_USR, buff, 1);
+
return ret;
}
@@ -968,12 +1177,15 @@ int32_t lsm6dso_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dso_read_reg(ctx, LSM6DSO_Z_OFS_USR, buff, 1);
+
return ret;
}
@@ -982,6 +1194,7 @@ int32_t lsm6dso_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param val change the values of usr_off_on_out in reg CTRL7_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -989,11 +1202,14 @@ int32_t lsm6dso_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_ctrl7_g_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.usr_off_on_out = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1002,6 +1218,7 @@ int32_t lsm6dso_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val values of usr_off_on_out in reg CTRL7_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1009,7 +1226,7 @@ int32_t lsm6dso_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_ctrl7_g_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
*val = reg.usr_off_on_out;
return ret;
@@ -1032,13 +1249,12 @@ int32_t lsm6dso_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val)
* @brief Reset timestamp counter.[set]
*
* @param ctx Read / write interface definitions.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_timestamp_rst(stmdev_ctx_t *ctx)
{
uint8_t rst_val = 0xAA;
-
return lsm6dso_write_reg(ctx, LSM6DSO_TIMESTAMP2, &rst_val, 1);
}
@@ -1047,6 +1263,7 @@ int32_t lsm6dso_timestamp_rst(stmdev_ctx_t *ctx)
*
* @param ctx read / write interface definitions
* @param val change the values of timestamp_en in reg CTRL10_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1054,11 +1271,14 @@ int32_t lsm6dso_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_ctrl10_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.timestamp_en = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1067,6 +1287,7 @@ int32_t lsm6dso_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of timestamp_en in reg CTRL10_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1074,7 +1295,7 @@ int32_t lsm6dso_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_ctrl10_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t *)®, 1);
*val = reg.timestamp_en;
return ret;
@@ -1087,12 +1308,20 @@ int32_t lsm6dso_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_timestamp_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val)
{
+ uint8_t buff[4];
int32_t ret;
+
ret = lsm6dso_read_reg(ctx, LSM6DSO_TIMESTAMP0, buff, 4);
+ *val = buff[3];
+ *val = (*val * 256U) + buff[2];
+ *val = (*val * 256U) + buff[1];
+ *val = (*val * 256U) + buff[0];
+
return ret;
}
@@ -1106,7 +1335,7 @@ int32_t lsm6dso_timestamp_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @brief This section groups all the data output functions.
* @{
*
-*/
+ */
/**
* @brief Circular burst-mode (rounding) read of the output
@@ -1114,6 +1343,7 @@ int32_t lsm6dso_timestamp_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param val change the values of rounding in reg CTRL5_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_rounding_mode_set(stmdev_ctx_t *ctx,
@@ -1122,11 +1352,14 @@ int32_t lsm6dso_rounding_mode_set(stmdev_ctx_t *ctx,
lsm6dso_ctrl5_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.rounding = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1135,6 +1368,7 @@ int32_t lsm6dso_rounding_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of rounding in reg CTRL5_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_rounding_mode_get(stmdev_ctx_t *ctx,
@@ -1143,24 +1377,31 @@ int32_t lsm6dso_rounding_mode_get(stmdev_ctx_t *ctx,
lsm6dso_ctrl5_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)®, 1);
- switch (reg.rounding) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1);
+
+ switch (reg.rounding)
+ {
case LSM6DSO_NO_ROUND:
*val = LSM6DSO_NO_ROUND;
break;
+
case LSM6DSO_ROUND_XL:
*val = LSM6DSO_ROUND_XL;
break;
+
case LSM6DSO_ROUND_GY:
*val = LSM6DSO_ROUND_GY;
break;
+
case LSM6DSO_ROUND_GY_XL:
*val = LSM6DSO_ROUND_GY_XL;
break;
+
default:
*val = LSM6DSO_NO_ROUND;
break;
}
+
return ret;
}
@@ -1171,12 +1412,18 @@ int32_t lsm6dso_rounding_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
+
ret = lsm6dso_read_reg(ctx, LSM6DSO_OUT_TEMP_L, buff, 2);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+
return ret;
}
@@ -1186,12 +1433,22 @@ int32_t lsm6dso_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lsm6dso_read_reg(ctx, LSM6DSO_OUTX_L_G, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -1201,12 +1458,22 @@ int32_t lsm6dso_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lsm6dso_read_reg(ctx, LSM6DSO_OUTX_L_A, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -1215,12 +1482,15 @@ int32_t lsm6dso_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_DATA_OUT_X_L, buff, 6);
+
return ret;
}
@@ -1229,19 +1499,28 @@ int32_t lsm6dso_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_number_of_steps_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_STEP_COUNTER_L, buff, 2);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
+
return ret;
}
@@ -1249,6 +1528,7 @@ int32_t lsm6dso_number_of_steps_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @brief Reset step counter register.[get]
*
* @param ctx read / write interface definitions
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_steps_reset(stmdev_ctx_t *ctx)
@@ -1257,16 +1537,23 @@ int32_t lsm6dso_steps_reset(stmdev_ctx_t *ctx)
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_SRC, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_SRC, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.pedo_rst_step = PROPERTY_ENABLE;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_SRC, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_SRC, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
+
return ret;
}
@@ -1277,10 +1564,10 @@ int32_t lsm6dso_steps_reset(stmdev_ctx_t *ctx)
/**
* @defgroup LSM6DSO_common
- * @brief This section groups common usefull functions.
+ * @brief This section groups common useful functions.
* @{
*
-*/
+ */
/**
* @brief Difference in percentage of the effective ODR(and timestamp rate)
@@ -1290,6 +1577,7 @@ int32_t lsm6dso_steps_reset(stmdev_ctx_t *ctx)
* @param ctx read / write interface definitions
* @param val change the values of freq_fine in reg
* INTERNAL_FREQ_FINE
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1297,12 +1585,16 @@ int32_t lsm6dso_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_internal_freq_fine_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE,
+ (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.freq_fine = val;
ret = lsm6dso_write_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1313,6 +1605,7 @@ int32_t lsm6dso_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of freq_fine in reg INTERNAL_FREQ_FINE
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1320,7 +1613,8 @@ int32_t lsm6dso_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_internal_freq_fine_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE,
+ (uint8_t *)®, 1);
*val = reg.freq_fine;
return ret;
@@ -1334,18 +1628,23 @@ int32_t lsm6dso_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val)
* @param ctx read / write interface definitions
* @param val change the values of reg_access in
* reg FUNC_CFG_ACCESS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_mem_bank_set(stmdev_ctx_t *ctx, lsm6dso_reg_access_t val)
+int32_t lsm6dso_mem_bank_set(stmdev_ctx_t *ctx,
+ lsm6dso_reg_access_t val)
{
lsm6dso_func_cfg_access_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.reg_access = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1356,28 +1655,36 @@ int32_t lsm6dso_mem_bank_set(stmdev_ctx_t *ctx, lsm6dso_reg_access_t val)
* @param ctx read / write interface definitions
* @param val Get the values of reg_access in
* reg FUNC_CFG_ACCESS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_mem_bank_get(stmdev_ctx_t *ctx, lsm6dso_reg_access_t *val)
+int32_t lsm6dso_mem_bank_get(stmdev_ctx_t *ctx,
+ lsm6dso_reg_access_t *val)
{
lsm6dso_func_cfg_access_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t*)®, 1);
- switch (reg.reg_access) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t *)®, 1);
+
+ switch (reg.reg_access)
+ {
case LSM6DSO_USER_BANK:
*val = LSM6DSO_USER_BANK;
break;
+
case LSM6DSO_SENSOR_HUB_BANK:
*val = LSM6DSO_SENSOR_HUB_BANK;
break;
+
case LSM6DSO_EMBEDDED_FUNC_BANK:
*val = LSM6DSO_EMBEDDED_FUNC_BANK;
break;
+
default:
*val = LSM6DSO_USER_BANK;
break;
}
+
return ret;
}
@@ -1387,6 +1694,7 @@ int32_t lsm6dso_mem_bank_get(stmdev_ctx_t *ctx, lsm6dso_reg_access_t *val)
* @param ctx read / write interface definitions
* @param uint8_t address: page line address
* @param val value to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address,
@@ -1399,41 +1707,57 @@ int32_t lsm6dso_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address,
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x02; /* page_write enable */
- ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
page_sel.not_used_01 = 1;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_address.page_addr = (uint8_t)address & 0xFFU;
ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_ADDRESS,
- (uint8_t*)&page_address, 1);
+ (uint8_t *)&page_address, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_VALUE, val, 1);
}
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x00; /* page_write disable */
- ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
+
return ret;
}
@@ -1444,6 +1768,7 @@ int32_t lsm6dso_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address,
* @param uint8_t address: page line address
* @param uint8_t *buf: buffer to write
* @param uint8_t len: buffer len
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address,
@@ -1454,62 +1779,84 @@ int32_t lsm6dso_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address,
lsm6dso_page_address_t page_address;
uint16_t addr_pointed;
int32_t ret;
- uint8_t i ;
+ uint8_t i ;
addr_pointed = address;
-
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x02; /* page_write enable*/
- ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_sel.page_sel = ((uint8_t)(addr_pointed >> 8) & 0x0FU);
page_sel.not_used_01 = 1;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_address.page_addr = (uint8_t)(addr_pointed & 0x00FFU);
ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_ADDRESS,
- (uint8_t*)&page_address, 1);
+ (uint8_t *)&page_address, 1);
}
- if (ret == 0) {
- for (i = 0; ( (i < len) && (ret == 0) ); i++) {
+ if (ret == 0)
+ {
+ for (i = 0; ((i < len) && (ret == 0)); i++)
+ {
ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_VALUE, &buf[i], 1);
addr_pointed++;
+
/* Check if page wrap */
- if ( ( (addr_pointed % 0x0100U) == 0x00U ) && (ret == 0) ) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*)&page_sel, 1);
- if (ret == 0) {
+ if (((addr_pointed % 0x0100U) == 0x00U) && (ret == 0))
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *)&page_sel, 1);
+
+ if (ret == 0)
+ {
page_sel.page_sel = ((uint8_t)(addr_pointed >> 8) & 0x0FU);
page_sel.not_used_01 = 1;
ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
+ (uint8_t *)&page_sel, 1);
}
}
}
+
page_sel.page_sel = 0;
page_sel.not_used_01 = 1;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
}
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x00; /* page_write disable */
- ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
+
return ret;
}
@@ -1519,6 +1866,7 @@ int32_t lsm6dso_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address,
* @param ctx read / write interface definitions
* @param uint8_t address: page line address
* @param val read value
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t address,
@@ -1530,40 +1878,55 @@ int32_t lsm6dso_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t address,
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x01; /* page_read enable*/
- ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
page_sel.not_used_01 = 1;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_address.page_addr = (uint8_t)address & 0x00FFU;
ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_ADDRESS,
- (uint8_t*)&page_address, 1);
+ (uint8_t *)&page_address, 1);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_VALUE, val, 1);
}
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x00; /* page_read disable */
- ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -1577,6 +1940,7 @@ int32_t lsm6dso_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t address,
* @param val change the values of
* dataready_pulsed in
* reg COUNTER_BDR_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_data_ready_mode_set(stmdev_ctx_t *ctx,
@@ -1585,11 +1949,15 @@ int32_t lsm6dso_data_ready_mode_set(stmdev_ctx_t *ctx,
lsm6dso_counter_bdr_reg1_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.dataready_pulsed = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1,
+ (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1600,6 +1968,7 @@ int32_t lsm6dso_data_ready_mode_set(stmdev_ctx_t *ctx,
* @param val Get the values of
* dataready_pulsed in
* reg COUNTER_BDR_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_data_ready_mode_get(stmdev_ctx_t *ctx,
@@ -1608,18 +1977,23 @@ int32_t lsm6dso_data_ready_mode_get(stmdev_ctx_t *ctx,
lsm6dso_counter_bdr_reg1_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)®, 1);
- switch (reg.dataready_pulsed) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)®, 1);
+
+ switch (reg.dataready_pulsed)
+ {
case LSM6DSO_DRDY_LATCHED:
*val = LSM6DSO_DRDY_LATCHED;
break;
+
case LSM6DSO_DRDY_PULSED:
*val = LSM6DSO_DRDY_PULSED;
break;
+
default:
*val = LSM6DSO_DRDY_LATCHED;
break;
}
+
return ret;
}
@@ -1628,12 +2002,15 @@ int32_t lsm6dso_data_ready_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dso_read_reg(ctx, LSM6DSO_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -1643,6 +2020,7 @@ int32_t lsm6dso_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param val change the values of sw_reset in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_reset_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1650,10 +2028,12 @@ int32_t lsm6dso_reset_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.sw_reset = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
}
return ret;
@@ -1664,6 +2044,7 @@ int32_t lsm6dso_reset_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of sw_reset in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1671,7 +2052,7 @@ int32_t lsm6dso_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
*val = reg.sw_reset;
return ret;
@@ -1683,6 +2064,7 @@ int32_t lsm6dso_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of if_inc in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1690,11 +2072,14 @@ int32_t lsm6dso_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.if_inc = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1704,6 +2089,7 @@ int32_t lsm6dso_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of if_inc in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1711,7 +2097,7 @@ int32_t lsm6dso_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
*val = reg.if_inc;
return ret;
@@ -1722,6 +2108,7 @@ int32_t lsm6dso_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of boot in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_boot_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1729,11 +2116,14 @@ int32_t lsm6dso_boot_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.boot = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1742,6 +2132,7 @@ int32_t lsm6dso_boot_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of boot in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1749,7 +2140,7 @@ int32_t lsm6dso_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
*val = reg.boot;
return ret;
@@ -1760,18 +2151,23 @@ int32_t lsm6dso_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of st_xl in reg CTRL5_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_xl_self_test_set(stmdev_ctx_t *ctx, lsm6dso_st_xl_t val)
+int32_t lsm6dso_xl_self_test_set(stmdev_ctx_t *ctx,
+ lsm6dso_st_xl_t val)
{
lsm6dso_ctrl5_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.st_xl = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1780,28 +2176,36 @@ int32_t lsm6dso_xl_self_test_set(stmdev_ctx_t *ctx, lsm6dso_st_xl_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of st_xl in reg CTRL5_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_xl_self_test_get(stmdev_ctx_t *ctx, lsm6dso_st_xl_t *val)
+int32_t lsm6dso_xl_self_test_get(stmdev_ctx_t *ctx,
+ lsm6dso_st_xl_t *val)
{
lsm6dso_ctrl5_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)®, 1);
- switch (reg.st_xl) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1);
+
+ switch (reg.st_xl)
+ {
case LSM6DSO_XL_ST_DISABLE:
*val = LSM6DSO_XL_ST_DISABLE;
break;
+
case LSM6DSO_XL_ST_POSITIVE:
*val = LSM6DSO_XL_ST_POSITIVE;
break;
+
case LSM6DSO_XL_ST_NEGATIVE:
*val = LSM6DSO_XL_ST_NEGATIVE;
break;
+
default:
*val = LSM6DSO_XL_ST_DISABLE;
break;
}
+
return ret;
}
@@ -1810,18 +2214,23 @@ int32_t lsm6dso_xl_self_test_get(stmdev_ctx_t *ctx, lsm6dso_st_xl_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of st_g in reg CTRL5_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_gy_self_test_set(stmdev_ctx_t *ctx, lsm6dso_st_g_t val)
+int32_t lsm6dso_gy_self_test_set(stmdev_ctx_t *ctx,
+ lsm6dso_st_g_t val)
{
lsm6dso_ctrl5_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.st_g = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1830,28 +2239,36 @@ int32_t lsm6dso_gy_self_test_set(stmdev_ctx_t *ctx, lsm6dso_st_g_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of st_g in reg CTRL5_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_gy_self_test_get(stmdev_ctx_t *ctx, lsm6dso_st_g_t *val)
+int32_t lsm6dso_gy_self_test_get(stmdev_ctx_t *ctx,
+ lsm6dso_st_g_t *val)
{
lsm6dso_ctrl5_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)®, 1);
- switch (reg.st_g) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1);
+
+ switch (reg.st_g)
+ {
case LSM6DSO_GY_ST_DISABLE:
*val = LSM6DSO_GY_ST_DISABLE;
break;
+
case LSM6DSO_GY_ST_POSITIVE:
*val = LSM6DSO_GY_ST_POSITIVE;
break;
+
case LSM6DSO_GY_ST_NEGATIVE:
*val = LSM6DSO_GY_ST_NEGATIVE;
break;
+
default:
*val = LSM6DSO_GY_ST_DISABLE;
break;
}
+
return ret;
}
@@ -1866,13 +2283,14 @@ int32_t lsm6dso_gy_self_test_get(stmdev_ctx_t *ctx, lsm6dso_st_g_t *val)
* filters configuration
* @{
*
-*/
+ */
/**
* @brief Accelerometer output from LPF2 filtering stage selection.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of lpf2_xl_en in reg CTRL1_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1880,11 +2298,14 @@ int32_t lsm6dso_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_ctrl1_xl_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.lpf2_xl_en = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1893,6 +2314,7 @@ int32_t lsm6dso_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of lpf2_xl_en in reg CTRL1_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1900,7 +2322,7 @@ int32_t lsm6dso_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_ctrl1_xl_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1);
*val = reg.lpf2_xl_en;
return ret;
@@ -1913,6 +2335,7 @@ int32_t lsm6dso_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of lpf1_sel_g in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1920,11 +2343,14 @@ int32_t lsm6dso_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_ctrl4_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.lpf1_sel_g = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1935,6 +2361,7 @@ int32_t lsm6dso_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of lpf1_sel_g in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1942,7 +2369,7 @@ int32_t lsm6dso_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_ctrl4_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
*val = reg.lpf1_sel_g;
return ret;
@@ -1954,18 +2381,23 @@ int32_t lsm6dso_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of drdy_mask in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dso_filter_settling_mask_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dso_ctrl4_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.drdy_mask = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1975,14 +2407,16 @@ int32_t lsm6dso_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of drdy_mask in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso_filter_settling_mask_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso_ctrl4_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
*val = reg.drdy_mask;
return ret;
@@ -1993,18 +2427,23 @@ int32_t lsm6dso_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of ftype in reg CTRL6_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, lsm6dso_ftype_t val)
+int32_t lsm6dso_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
+ lsm6dso_ftype_t val)
{
lsm6dso_ctrl6_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.ftype = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2013,43 +2452,56 @@ int32_t lsm6dso_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, lsm6dso_ftype_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of ftype in reg CTRL6_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, lsm6dso_ftype_t *val)
+int32_t lsm6dso_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
+ lsm6dso_ftype_t *val)
{
lsm6dso_ctrl6_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)®, 1);
- switch (reg.ftype) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1);
+
+ switch (reg.ftype)
+ {
case LSM6DSO_ULTRA_LIGHT:
*val = LSM6DSO_ULTRA_LIGHT;
break;
+
case LSM6DSO_VERY_LIGHT:
*val = LSM6DSO_VERY_LIGHT;
break;
+
case LSM6DSO_LIGHT:
*val = LSM6DSO_LIGHT;
break;
+
case LSM6DSO_MEDIUM:
*val = LSM6DSO_MEDIUM;
break;
+
case LSM6DSO_STRONG:
*val = LSM6DSO_STRONG;
break;
+
case LSM6DSO_VERY_STRONG:
*val = LSM6DSO_VERY_STRONG;
break;
+
case LSM6DSO_AGGRESSIVE:
*val = LSM6DSO_AGGRESSIVE;
break;
+
case LSM6DSO_XTREME:
*val = LSM6DSO_XTREME;
break;
+
default:
*val = LSM6DSO_ULTRA_LIGHT;
break;
}
+
return ret;
}
@@ -2058,6 +2510,7 @@ int32_t lsm6dso_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, lsm6dso_ftype_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of low_pass_on_6d in reg CTRL8_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -2065,11 +2518,14 @@ int32_t lsm6dso_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_ctrl8_xl_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.low_pass_on_6d = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2078,6 +2534,7 @@ int32_t lsm6dso_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of low_pass_on_6d in reg CTRL8_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -2085,7 +2542,7 @@ int32_t lsm6dso_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_ctrl8_xl_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
*val = reg.low_pass_on_6d;
return ret;
@@ -2098,6 +2555,7 @@ int32_t lsm6dso_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val)
* @param ctx read / write interface definitions
* @param val change the values of hp_slope_xl_en
* in reg CTRL8_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
@@ -2106,13 +2564,16 @@ int32_t lsm6dso_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
lsm6dso_ctrl8_xl_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.hp_slope_xl_en = ((uint8_t)val & 0x10U) >> 4;
reg.hp_ref_mode_xl = ((uint8_t)val & 0x20U) >> 5;
reg.hpcf_xl = (uint8_t)val & 0x07U;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2123,6 +2584,7 @@ int32_t lsm6dso_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val Get the values of hp_slope_xl_en
* in reg CTRL8_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
@@ -2131,78 +2593,103 @@ int32_t lsm6dso_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
lsm6dso_ctrl8_xl_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
+
switch ((reg.hp_ref_mode_xl << 5) | (reg.hp_slope_xl_en << 4) |
- reg.hpcf_xl) {
+ reg.hpcf_xl)
+ {
case LSM6DSO_HP_PATH_DISABLE_ON_OUT:
*val = LSM6DSO_HP_PATH_DISABLE_ON_OUT;
break;
+
case LSM6DSO_SLOPE_ODR_DIV_4:
*val = LSM6DSO_SLOPE_ODR_DIV_4;
break;
+
case LSM6DSO_HP_ODR_DIV_10:
*val = LSM6DSO_HP_ODR_DIV_10;
break;
+
case LSM6DSO_HP_ODR_DIV_20:
*val = LSM6DSO_HP_ODR_DIV_20;
break;
+
case LSM6DSO_HP_ODR_DIV_45:
*val = LSM6DSO_HP_ODR_DIV_45;
break;
+
case LSM6DSO_HP_ODR_DIV_100:
*val = LSM6DSO_HP_ODR_DIV_100;
break;
+
case LSM6DSO_HP_ODR_DIV_200:
*val = LSM6DSO_HP_ODR_DIV_200;
break;
+
case LSM6DSO_HP_ODR_DIV_400:
*val = LSM6DSO_HP_ODR_DIV_400;
break;
+
case LSM6DSO_HP_ODR_DIV_800:
*val = LSM6DSO_HP_ODR_DIV_800;
break;
+
case LSM6DSO_HP_REF_MD_ODR_DIV_10:
*val = LSM6DSO_HP_REF_MD_ODR_DIV_10;
break;
+
case LSM6DSO_HP_REF_MD_ODR_DIV_20:
*val = LSM6DSO_HP_REF_MD_ODR_DIV_20;
break;
+
case LSM6DSO_HP_REF_MD_ODR_DIV_45:
*val = LSM6DSO_HP_REF_MD_ODR_DIV_45;
break;
+
case LSM6DSO_HP_REF_MD_ODR_DIV_100:
*val = LSM6DSO_HP_REF_MD_ODR_DIV_100;
break;
+
case LSM6DSO_HP_REF_MD_ODR_DIV_200:
*val = LSM6DSO_HP_REF_MD_ODR_DIV_200;
break;
+
case LSM6DSO_HP_REF_MD_ODR_DIV_400:
*val = LSM6DSO_HP_REF_MD_ODR_DIV_400;
break;
+
case LSM6DSO_HP_REF_MD_ODR_DIV_800:
*val = LSM6DSO_HP_REF_MD_ODR_DIV_800;
break;
+
case LSM6DSO_LP_ODR_DIV_10:
*val = LSM6DSO_LP_ODR_DIV_10;
break;
+
case LSM6DSO_LP_ODR_DIV_20:
*val = LSM6DSO_LP_ODR_DIV_20;
break;
+
case LSM6DSO_LP_ODR_DIV_45:
*val = LSM6DSO_LP_ODR_DIV_45;
break;
+
case LSM6DSO_LP_ODR_DIV_100:
*val = LSM6DSO_LP_ODR_DIV_100;
break;
+
case LSM6DSO_LP_ODR_DIV_200:
*val = LSM6DSO_LP_ODR_DIV_200;
break;
+
case LSM6DSO_LP_ODR_DIV_400:
*val = LSM6DSO_LP_ODR_DIV_400;
break;
+
case LSM6DSO_LP_ODR_DIV_800:
*val = LSM6DSO_LP_ODR_DIV_800;
break;
+
default:
*val = LSM6DSO_HP_PATH_DISABLE_ON_OUT;
break;
@@ -2219,6 +2706,7 @@ int32_t lsm6dso_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of fastsettl_mode_xl in
* reg CTRL8_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -2226,11 +2714,14 @@ int32_t lsm6dso_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_ctrl8_xl_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.fastsettl_mode_xl = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2241,6 +2732,7 @@ int32_t lsm6dso_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of fastsettl_mode_xl in reg CTRL8_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -2248,7 +2740,7 @@ int32_t lsm6dso_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_ctrl8_xl_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
*val = reg.fastsettl_mode_xl;
return ret;
@@ -2260,6 +2752,7 @@ int32_t lsm6dso_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of slope_fds in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
@@ -2268,11 +2761,14 @@ int32_t lsm6dso_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
lsm6dso_tap_cfg0_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.slope_fds = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2282,6 +2778,7 @@ int32_t lsm6dso_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of slope_fds in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
@@ -2290,18 +2787,23 @@ int32_t lsm6dso_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
lsm6dso_tap_cfg0_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)®, 1);
- switch (reg.slope_fds) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
+
+ switch (reg.slope_fds)
+ {
case LSM6DSO_USE_SLOPE:
*val = LSM6DSO_USE_SLOPE;
break;
+
case LSM6DSO_USE_HPF:
*val = LSM6DSO_USE_HPF;
break;
+
default:
*val = LSM6DSO_USE_SLOPE;
break;
}
+
return ret;
}
@@ -2312,6 +2814,7 @@ int32_t lsm6dso_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val Get the values of hp_en_g and hp_en_g
* in reg CTRL7_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
@@ -2320,12 +2823,15 @@ int32_t lsm6dso_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
lsm6dso_ctrl7_g_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.hp_en_g = ((uint8_t)val & 0x80U) >> 7;
reg.hpm_g = (uint8_t)val & 0x03U;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2336,6 +2842,7 @@ int32_t lsm6dso_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val Get the values of hp_en_g and hp_en_g
* in reg CTRL7_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
@@ -2344,27 +2851,35 @@ int32_t lsm6dso_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
lsm6dso_ctrl7_g_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)®, 1);
- switch ((reg.hp_en_g << 7) + reg.hpm_g) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
+
+ switch ((reg.hp_en_g << 7) + reg.hpm_g)
+ {
case LSM6DSO_HP_FILTER_NONE:
*val = LSM6DSO_HP_FILTER_NONE;
break;
+
case LSM6DSO_HP_FILTER_16mHz:
*val = LSM6DSO_HP_FILTER_16mHz;
break;
+
case LSM6DSO_HP_FILTER_65mHz:
*val = LSM6DSO_HP_FILTER_65mHz;
break;
+
case LSM6DSO_HP_FILTER_260mHz:
*val = LSM6DSO_HP_FILTER_260mHz;
break;
+
case LSM6DSO_HP_FILTER_1Hz04:
*val = LSM6DSO_HP_FILTER_1Hz04;
break;
+
default:
*val = LSM6DSO_HP_FILTER_NONE;
break;
}
+
return ret;
}
@@ -2379,7 +2894,7 @@ int32_t lsm6dso_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
* auxiliary interface.
* @{
*
-*/
+ */
/**
* @brief aOn auxiliary interface connect/disconnect SDO and OCS
@@ -2388,6 +2903,7 @@ int32_t lsm6dso_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of ois_pu_dis in
* reg PIN_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx,
@@ -2396,11 +2912,14 @@ int32_t lsm6dso_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx,
lsm6dso_pin_ctrl_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.ois_pu_dis = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2410,6 +2929,7 @@ int32_t lsm6dso_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of ois_pu_dis in reg PIN_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx,
@@ -2418,18 +2938,23 @@ int32_t lsm6dso_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx,
lsm6dso_pin_ctrl_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)®, 1);
- switch (reg.ois_pu_dis) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)®, 1);
+
+ switch (reg.ois_pu_dis)
+ {
case LSM6DSO_AUX_PULL_UP_DISC:
*val = LSM6DSO_AUX_PULL_UP_DISC;
break;
+
case LSM6DSO_AUX_PULL_UP_CONNECT:
*val = LSM6DSO_AUX_PULL_UP_CONNECT;
break;
+
default:
*val = LSM6DSO_AUX_PULL_UP_DISC;
break;
}
+
return ret;
}
@@ -2438,19 +2963,24 @@ int32_t lsm6dso_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of ois_on in reg CTRL7_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx, lsm6dso_ois_on_t val)
+int32_t lsm6dso_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx,
+ lsm6dso_ois_on_t val)
{
lsm6dso_ctrl7_g_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.ois_on_en = (uint8_t)val & 0x01U;
reg.ois_on = (uint8_t)val & 0x01U;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2459,21 +2989,27 @@ int32_t lsm6dso_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx, lsm6dso_ois_on_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of ois_on in reg CTRL7_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx, lsm6dso_ois_on_t *val)
+int32_t lsm6dso_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx,
+ lsm6dso_ois_on_t *val)
{
lsm6dso_ctrl7_g_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)®, 1);
- switch (reg.ois_on) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
+
+ switch (reg.ois_on)
+ {
case LSM6DSO_AUX_ON:
*val = LSM6DSO_AUX_ON;
break;
+
case LSM6DSO_AUX_ON_BY_AUX_INTERFACE:
*val = LSM6DSO_AUX_ON_BY_AUX_INTERFACE;
break;
+
default:
*val = LSM6DSO_AUX_ON;
break;
@@ -2493,6 +3029,7 @@ int32_t lsm6dso_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx, lsm6dso_ois_on_t *val)
* @param ctx read / write interface definitions
* @param val change the values of xl_fs_mode in
* reg CTRL8_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_aux_xl_fs_mode_set(stmdev_ctx_t *ctx,
@@ -2501,11 +3038,14 @@ int32_t lsm6dso_aux_xl_fs_mode_set(stmdev_ctx_t *ctx,
lsm6dso_ctrl8_xl_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.xl_fs_mode = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2519,6 +3059,7 @@ int32_t lsm6dso_aux_xl_fs_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of xl_fs_mode in reg CTRL8_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_aux_xl_fs_mode_get(stmdev_ctx_t *ctx,
@@ -2527,14 +3068,18 @@ int32_t lsm6dso_aux_xl_fs_mode_get(stmdev_ctx_t *ctx,
lsm6dso_ctrl8_xl_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)®, 1);
- switch (reg.xl_fs_mode) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
+
+ switch (reg.xl_fs_mode)
+ {
case LSM6DSO_USE_SAME_XL_FS:
*val = LSM6DSO_USE_SAME_XL_FS;
break;
+
case LSM6DSO_USE_DIFFERENT_XL_FS:
*val = LSM6DSO_USE_DIFFERENT_XL_FS;
break;
+
default:
*val = LSM6DSO_USE_SAME_XL_FS;
break;
@@ -2548,13 +3093,16 @@ int32_t lsm6dso_aux_xl_fs_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param lsm6dso_status_spiaux_t: registers STATUS_SPIAUX
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_aux_status_reg_get(stmdev_ctx_t *ctx,
lsm6dso_status_spiaux_t *val)
{
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t*) val, 1);
+
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t *) val, 1);
+
return ret;
}
@@ -2563,14 +3111,16 @@ int32_t lsm6dso_aux_status_reg_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of xlda in reg STATUS_SPIAUX
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso_status_spiaux_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t *)®, 1);
*val = reg.xlda;
return ret;
@@ -2581,14 +3131,16 @@ int32_t lsm6dso_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of gda in reg STATUS_SPIAUX
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso_status_spiaux_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t *)®, 1);
*val = reg.gda;
return ret;
@@ -2599,14 +3151,16 @@ int32_t lsm6dso_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of gyro_settling in reg STATUS_SPIAUX
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso_aux_gy_flag_settling_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso_status_spiaux_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t *)®, 1);
*val = reg.gyro_settling;
return ret;
@@ -2618,6 +3172,7 @@ int32_t lsm6dso_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of st_xl_ois in reg INT_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_aux_xl_self_test_set(stmdev_ctx_t *ctx,
@@ -2626,11 +3181,14 @@ int32_t lsm6dso_aux_xl_self_test_set(stmdev_ctx_t *ctx,
lsm6dso_int_ois_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.st_xl_ois = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2640,6 +3198,7 @@ int32_t lsm6dso_aux_xl_self_test_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of st_xl_ois in reg INT_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_aux_xl_self_test_get(stmdev_ctx_t *ctx,
@@ -2648,21 +3207,27 @@ int32_t lsm6dso_aux_xl_self_test_get(stmdev_ctx_t *ctx,
lsm6dso_int_ois_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)®, 1);
- switch (reg.st_xl_ois) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1);
+
+ switch (reg.st_xl_ois)
+ {
case LSM6DSO_AUX_XL_DISABLE:
*val = LSM6DSO_AUX_XL_DISABLE;
break;
+
case LSM6DSO_AUX_XL_POS:
*val = LSM6DSO_AUX_XL_POS;
break;
+
case LSM6DSO_AUX_XL_NEG:
*val = LSM6DSO_AUX_XL_NEG;
break;
+
default:
*val = LSM6DSO_AUX_XL_DISABLE;
break;
}
+
return ret;
}
@@ -2672,6 +3237,7 @@ int32_t lsm6dso_aux_xl_self_test_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of den_lh_ois in
* reg INT_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_aux_den_polarity_set(stmdev_ctx_t *ctx,
@@ -2680,11 +3246,14 @@ int32_t lsm6dso_aux_den_polarity_set(stmdev_ctx_t *ctx,
lsm6dso_int_ois_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.den_lh_ois = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2693,6 +3262,7 @@ int32_t lsm6dso_aux_den_polarity_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of den_lh_ois in reg INT_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_aux_den_polarity_get(stmdev_ctx_t *ctx,
@@ -2701,18 +3271,23 @@ int32_t lsm6dso_aux_den_polarity_get(stmdev_ctx_t *ctx,
lsm6dso_int_ois_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)®, 1);
- switch (reg.den_lh_ois) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1);
+
+ switch (reg.den_lh_ois)
+ {
case LSM6DSO_AUX_DEN_ACTIVE_LOW:
*val = LSM6DSO_AUX_DEN_ACTIVE_LOW;
break;
+
case LSM6DSO_AUX_DEN_ACTIVE_HIGH:
*val = LSM6DSO_AUX_DEN_ACTIVE_HIGH;
break;
+
default:
*val = LSM6DSO_AUX_DEN_ACTIVE_LOW;
break;
}
+
return ret;
}
@@ -2721,26 +3296,36 @@ int32_t lsm6dso_aux_den_polarity_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of lvl2_ois in reg INT_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_aux_den_mode_set(stmdev_ctx_t *ctx, lsm6dso_lvl2_ois_t val)
+int32_t lsm6dso_aux_den_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso_lvl2_ois_t val)
{
lsm6dso_ctrl1_ois_t ctrl1_ois;
lsm6dso_int_ois_t int_ois;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*) &int_ois, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *) &int_ois, 1);
+
+ if (ret == 0)
+ {
int_ois.lvl2_ois = (uint8_t)val & 0x01U;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*) &int_ois, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *) &int_ois, 1);
}
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*) &ctrl1_ois, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *) &ctrl1_ois, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ctrl1_ois.lvl1_ois = ((uint8_t)val & 0x02U) >> 1;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*) &ctrl1_ois, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS,
+ (uint8_t *) &ctrl1_ois, 1);
}
+
return ret;
}
@@ -2749,32 +3334,42 @@ int32_t lsm6dso_aux_den_mode_set(stmdev_ctx_t *ctx, lsm6dso_lvl2_ois_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of lvl2_ois in reg INT_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_aux_den_mode_get(stmdev_ctx_t *ctx, lsm6dso_lvl2_ois_t *val)
+int32_t lsm6dso_aux_den_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso_lvl2_ois_t *val)
{
lsm6dso_ctrl1_ois_t ctrl1_ois;
lsm6dso_int_ois_t int_ois;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*) &int_ois, 1);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*) &ctrl1_ois, 1);
- switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *) &int_ois, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *) &ctrl1_ois, 1);
+
+ switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois)
+ {
case LSM6DSO_AUX_DEN_DISABLE:
*val = LSM6DSO_AUX_DEN_DISABLE;
break;
+
case LSM6DSO_AUX_DEN_LEVEL_LATCH:
*val = LSM6DSO_AUX_DEN_LEVEL_LATCH;
break;
+
case LSM6DSO_AUX_DEN_LEVEL_TRIG:
*val = LSM6DSO_AUX_DEN_LEVEL_TRIG;
break;
+
default:
*val = LSM6DSO_AUX_DEN_DISABLE;
break;
}
}
+
return ret;
}
@@ -2784,6 +3379,7 @@ int32_t lsm6dso_aux_den_mode_get(stmdev_ctx_t *ctx, lsm6dso_lvl2_ois_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of int2_drdy_ois in reg INT_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -2791,11 +3387,14 @@ int32_t lsm6dso_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_int_ois_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.int2_drdy_ois = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2805,6 +3404,7 @@ int32_t lsm6dso_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of int2_drdy_ois in reg INT_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -2812,7 +3412,7 @@ int32_t lsm6dso_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_int_ois_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1);
*val = reg.int2_drdy_ois;
return ret;
@@ -2829,19 +3429,24 @@ int32_t lsm6dso_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val)
* @param ctx read / write interface definitions
* @param val change the values of ois_en_spi2 in
* reg CTRL1_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_aux_mode_set(stmdev_ctx_t *ctx, lsm6dso_ois_en_spi2_t val)
+int32_t lsm6dso_aux_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso_ois_en_spi2_t val)
{
lsm6dso_ctrl1_ois_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.ois_en_spi2 = (uint8_t)val & 0x01U;
reg.mode4_en = ((uint8_t)val & 0x02U) >> 1;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2856,28 +3461,36 @@ int32_t lsm6dso_aux_mode_set(stmdev_ctx_t *ctx, lsm6dso_ois_en_spi2_t val)
* @param ctx read / write interface definitions
* @param val Get the values of ois_en_spi2 in
* reg CTRL1_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_aux_mode_get(stmdev_ctx_t *ctx, lsm6dso_ois_en_spi2_t *val)
+int32_t lsm6dso_aux_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso_ois_en_spi2_t *val)
{
lsm6dso_ctrl1_ois_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)®, 1);
- switch ((reg.mode4_en << 1) | reg.ois_en_spi2) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1);
+
+ switch ((reg.mode4_en << 1) | reg.ois_en_spi2)
+ {
case LSM6DSO_AUX_DISABLE:
*val = LSM6DSO_AUX_DISABLE;
break;
+
case LSM6DSO_MODE_3_GY:
*val = LSM6DSO_MODE_3_GY;
break;
+
case LSM6DSO_MODE_4_GY_XL:
*val = LSM6DSO_MODE_4_GY_XL;
break;
+
default:
*val = LSM6DSO_AUX_DISABLE;
break;
}
+
return ret;
}
@@ -2886,6 +3499,7 @@ int32_t lsm6dso_aux_mode_get(stmdev_ctx_t *ctx, lsm6dso_ois_en_spi2_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of fs_g_ois in reg CTRL1_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_aux_gy_full_scale_set(stmdev_ctx_t *ctx,
@@ -2894,11 +3508,14 @@ int32_t lsm6dso_aux_gy_full_scale_set(stmdev_ctx_t *ctx,
lsm6dso_ctrl1_ois_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.fs_g_ois = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2907,6 +3524,7 @@ int32_t lsm6dso_aux_gy_full_scale_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of fs_g_ois in reg CTRL1_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_aux_gy_full_scale_get(stmdev_ctx_t *ctx,
@@ -2915,27 +3533,35 @@ int32_t lsm6dso_aux_gy_full_scale_get(stmdev_ctx_t *ctx,
lsm6dso_ctrl1_ois_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)®, 1);
- switch (reg.fs_g_ois) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1);
+
+ switch (reg.fs_g_ois)
+ {
case LSM6DSO_250dps_AUX:
*val = LSM6DSO_250dps_AUX;
break;
+
case LSM6DSO_125dps_AUX:
*val = LSM6DSO_125dps_AUX;
break;
+
case LSM6DSO_500dps_AUX:
*val = LSM6DSO_500dps_AUX;
break;
+
case LSM6DSO_1000dps_AUX:
*val = LSM6DSO_1000dps_AUX;
break;
+
case LSM6DSO_2000dps_AUX:
*val = LSM6DSO_2000dps_AUX;
break;
+
default:
*val = LSM6DSO_250dps_AUX;
break;
}
+
return ret;
}
@@ -2944,18 +3570,23 @@ int32_t lsm6dso_aux_gy_full_scale_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of sim_ois in reg CTRL1_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_aux_spi_mode_set(stmdev_ctx_t *ctx, lsm6dso_sim_ois_t val)
+int32_t lsm6dso_aux_spi_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso_sim_ois_t val)
{
lsm6dso_ctrl1_ois_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.sim_ois = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2964,25 +3595,32 @@ int32_t lsm6dso_aux_spi_mode_set(stmdev_ctx_t *ctx, lsm6dso_sim_ois_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of sim_ois in reg CTRL1_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_aux_spi_mode_get(stmdev_ctx_t *ctx, lsm6dso_sim_ois_t *val)
+int32_t lsm6dso_aux_spi_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso_sim_ois_t *val)
{
lsm6dso_ctrl1_ois_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)®, 1);
- switch (reg.sim_ois) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1);
+
+ switch (reg.sim_ois)
+ {
case LSM6DSO_AUX_SPI_4_WIRE:
*val = LSM6DSO_AUX_SPI_4_WIRE;
break;
+
case LSM6DSO_AUX_SPI_3_WIRE:
*val = LSM6DSO_AUX_SPI_3_WIRE;
break;
+
default:
*val = LSM6DSO_AUX_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -2992,6 +3630,7 @@ int32_t lsm6dso_aux_spi_mode_get(stmdev_ctx_t *ctx, lsm6dso_sim_ois_t *val)
* @param ctx read / write interface definitions
* @param val change the values of ftype_ois in
* reg CTRL2_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
@@ -3000,11 +3639,14 @@ int32_t lsm6dso_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
lsm6dso_ctrl2_ois_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.ftype_ois = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3013,6 +3655,7 @@ int32_t lsm6dso_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of ftype_ois in reg CTRL2_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
@@ -3021,24 +3664,31 @@ int32_t lsm6dso_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
lsm6dso_ctrl2_ois_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t*)®, 1);
- switch (reg.ftype_ois) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)®, 1);
+
+ switch (reg.ftype_ois)
+ {
case LSM6DSO_351Hz39:
*val = LSM6DSO_351Hz39;
break;
+
case LSM6DSO_236Hz63:
*val = LSM6DSO_236Hz63;
break;
+
case LSM6DSO_172Hz70:
*val = LSM6DSO_172Hz70;
break;
+
case LSM6DSO_937Hz91:
*val = LSM6DSO_937Hz91;
break;
+
default:
*val = LSM6DSO_351Hz39;
break;
}
+
return ret;
}
@@ -3047,6 +3697,7 @@ int32_t lsm6dso_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of hpm_ois in reg CTRL2_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx,
@@ -3055,12 +3706,15 @@ int32_t lsm6dso_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx,
lsm6dso_ctrl2_ois_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.hpm_ois = (uint8_t)val & 0x03U;
reg.hp_en_ois = ((uint8_t)val & 0x10U) >> 4;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3069,6 +3723,7 @@ int32_t lsm6dso_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of hpm_ois in reg CTRL2_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx,
@@ -3077,27 +3732,35 @@ int32_t lsm6dso_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx,
lsm6dso_ctrl2_ois_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t*)®, 1);
- switch ((reg.hp_en_ois << 4) | reg.hpm_ois) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)®, 1);
+
+ switch ((reg.hp_en_ois << 4) | reg.hpm_ois)
+ {
case LSM6DSO_AUX_HP_DISABLE:
*val = LSM6DSO_AUX_HP_DISABLE;
break;
+
case LSM6DSO_AUX_HP_Hz016:
*val = LSM6DSO_AUX_HP_Hz016;
break;
+
case LSM6DSO_AUX_HP_Hz065:
*val = LSM6DSO_AUX_HP_Hz065;
break;
+
case LSM6DSO_AUX_HP_Hz260:
*val = LSM6DSO_AUX_HP_Hz260;
break;
+
case LSM6DSO_AUX_HP_1Hz040:
*val = LSM6DSO_AUX_HP_1Hz040;
break;
+
default:
*val = LSM6DSO_AUX_HP_DISABLE;
break;
}
+
return ret;
}
@@ -3111,6 +3774,7 @@ int32_t lsm6dso_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of st_ois_clampdis in
* reg CTRL3_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_aux_gy_clamp_set(stmdev_ctx_t *ctx,
@@ -3119,11 +3783,14 @@ int32_t lsm6dso_aux_gy_clamp_set(stmdev_ctx_t *ctx,
lsm6dso_ctrl3_ois_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.st_ois_clampdis = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3137,6 +3804,7 @@ int32_t lsm6dso_aux_gy_clamp_set(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val Get the values of st_ois_clampdis in
* reg CTRL3_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_aux_gy_clamp_get(stmdev_ctx_t *ctx,
@@ -3145,18 +3813,23 @@ int32_t lsm6dso_aux_gy_clamp_get(stmdev_ctx_t *ctx,
lsm6dso_ctrl3_ois_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)®, 1);
- switch (reg.st_ois_clampdis) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
+
+ switch (reg.st_ois_clampdis)
+ {
case LSM6DSO_ENABLE_CLAMP:
*val = LSM6DSO_ENABLE_CLAMP;
break;
+
case LSM6DSO_DISABLE_CLAMP:
*val = LSM6DSO_DISABLE_CLAMP;
break;
+
default:
*val = LSM6DSO_ENABLE_CLAMP;
break;
}
+
return ret;
}
@@ -3165,18 +3838,23 @@ int32_t lsm6dso_aux_gy_clamp_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of st_ois in reg CTRL3_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_aux_gy_self_test_set(stmdev_ctx_t *ctx, lsm6dso_st_ois_t val)
+int32_t lsm6dso_aux_gy_self_test_set(stmdev_ctx_t *ctx,
+ lsm6dso_st_ois_t val)
{
lsm6dso_ctrl3_ois_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.st_ois = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3185,28 +3863,36 @@ int32_t lsm6dso_aux_gy_self_test_set(stmdev_ctx_t *ctx, lsm6dso_st_ois_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of st_ois in reg CTRL3_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_aux_gy_self_test_get(stmdev_ctx_t *ctx, lsm6dso_st_ois_t *val)
+int32_t lsm6dso_aux_gy_self_test_get(stmdev_ctx_t *ctx,
+ lsm6dso_st_ois_t *val)
{
lsm6dso_ctrl3_ois_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)®, 1);
- switch (reg.st_ois) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
+
+ switch (reg.st_ois)
+ {
case LSM6DSO_AUX_GY_DISABLE:
*val = LSM6DSO_AUX_GY_DISABLE;
break;
+
case LSM6DSO_AUX_GY_POS:
*val = LSM6DSO_AUX_GY_POS;
break;
+
case LSM6DSO_AUX_GY_NEG:
*val = LSM6DSO_AUX_GY_NEG;
break;
+
default:
*val = LSM6DSO_AUX_GY_DISABLE;
break;
}
+
return ret;
}
@@ -3216,6 +3902,7 @@ int32_t lsm6dso_aux_gy_self_test_get(stmdev_ctx_t *ctx, lsm6dso_st_ois_t *val)
* @param ctx read / write interface definitions
* @param val change the values of
* filter_xl_conf_ois in reg CTRL3_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_aux_xl_bandwidth_set(stmdev_ctx_t *ctx,
@@ -3224,11 +3911,14 @@ int32_t lsm6dso_aux_xl_bandwidth_set(stmdev_ctx_t *ctx,
lsm6dso_ctrl3_ois_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.filter_xl_conf_ois = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3238,6 +3928,7 @@ int32_t lsm6dso_aux_xl_bandwidth_set(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val Get the values of
* filter_xl_conf_ois in reg CTRL3_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_aux_xl_bandwidth_get(stmdev_ctx_t *ctx,
@@ -3246,37 +3937,47 @@ int32_t lsm6dso_aux_xl_bandwidth_get(stmdev_ctx_t *ctx,
lsm6dso_ctrl3_ois_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
- switch (reg.filter_xl_conf_ois) {
+ switch (reg.filter_xl_conf_ois)
+ {
case LSM6DSO_289Hz:
*val = LSM6DSO_289Hz;
break;
+
case LSM6DSO_258Hz:
*val = LSM6DSO_258Hz;
break;
+
case LSM6DSO_120Hz:
*val = LSM6DSO_120Hz;
break;
+
case LSM6DSO_65Hz2:
*val = LSM6DSO_65Hz2;
break;
+
case LSM6DSO_33Hz2:
*val = LSM6DSO_33Hz2;
break;
+
case LSM6DSO_16Hz6:
*val = LSM6DSO_16Hz6;
break;
+
case LSM6DSO_8Hz30:
*val = LSM6DSO_8Hz30;
break;
+
case LSM6DSO_4Hz15:
*val = LSM6DSO_4Hz15;
break;
+
default:
*val = LSM6DSO_289Hz;
break;
}
+
return ret;
}
@@ -3286,6 +3987,7 @@ int32_t lsm6dso_aux_xl_bandwidth_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of fs_xl_ois in
* reg CTRL3_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_aux_xl_full_scale_set(stmdev_ctx_t *ctx,
@@ -3294,11 +3996,14 @@ int32_t lsm6dso_aux_xl_full_scale_set(stmdev_ctx_t *ctx,
lsm6dso_ctrl3_ois_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.fs_xl_ois = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3307,6 +4012,7 @@ int32_t lsm6dso_aux_xl_full_scale_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of fs_xl_ois in reg CTRL3_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_aux_xl_full_scale_get(stmdev_ctx_t *ctx,
@@ -3315,24 +4021,31 @@ int32_t lsm6dso_aux_xl_full_scale_get(stmdev_ctx_t *ctx,
lsm6dso_ctrl3_ois_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)®, 1);
- switch (reg.fs_xl_ois) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
+
+ switch (reg.fs_xl_ois)
+ {
case LSM6DSO_AUX_2g:
*val = LSM6DSO_AUX_2g;
break;
+
case LSM6DSO_AUX_16g:
*val = LSM6DSO_AUX_16g;
break;
+
case LSM6DSO_AUX_4g:
*val = LSM6DSO_AUX_4g;
break;
+
case LSM6DSO_AUX_8g:
*val = LSM6DSO_AUX_8g;
break;
+
default:
*val = LSM6DSO_AUX_2g;
break;
}
+
return ret;
}
@@ -3347,7 +4060,7 @@ int32_t lsm6dso_aux_xl_full_scale_get(stmdev_ctx_t *ctx,
* serial interface management (not auxiliary)
* @{
*
-*/
+ */
/**
* @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
@@ -3355,18 +4068,23 @@ int32_t lsm6dso_aux_xl_full_scale_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of sdo_pu_en in
* reg PIN_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_sdo_sa0_mode_set(stmdev_ctx_t *ctx, lsm6dso_sdo_pu_en_t val)
+int32_t lsm6dso_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso_sdo_pu_en_t val)
{
lsm6dso_pin_ctrl_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.sdo_pu_en = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3375,25 +4093,32 @@ int32_t lsm6dso_sdo_sa0_mode_set(stmdev_ctx_t *ctx, lsm6dso_sdo_pu_en_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of sdo_pu_en in reg PIN_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_sdo_sa0_mode_get(stmdev_ctx_t *ctx, lsm6dso_sdo_pu_en_t *val)
+int32_t lsm6dso_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso_sdo_pu_en_t *val)
{
lsm6dso_pin_ctrl_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)®, 1);
- switch (reg.sdo_pu_en) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)®, 1);
+
+ switch (reg.sdo_pu_en)
+ {
case LSM6DSO_PULL_UP_DISC:
*val = LSM6DSO_PULL_UP_DISC;
break;
+
case LSM6DSO_PULL_UP_CONNECT:
*val = LSM6DSO_PULL_UP_CONNECT;
break;
+
default:
*val = LSM6DSO_PULL_UP_DISC;
break;
}
+
return ret;
}
@@ -3402,6 +4127,7 @@ int32_t lsm6dso_sdo_sa0_mode_get(stmdev_ctx_t *ctx, lsm6dso_sdo_pu_en_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of sim in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_spi_mode_set(stmdev_ctx_t *ctx, lsm6dso_sim_t val)
@@ -3409,11 +4135,14 @@ int32_t lsm6dso_spi_mode_set(stmdev_ctx_t *ctx, lsm6dso_sim_t val)
lsm6dso_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.sim = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3422,6 +4151,7 @@ int32_t lsm6dso_spi_mode_set(stmdev_ctx_t *ctx, lsm6dso_sim_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of sim in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_spi_mode_get(stmdev_ctx_t *ctx, lsm6dso_sim_t *val)
@@ -3429,18 +4159,23 @@ int32_t lsm6dso_spi_mode_get(stmdev_ctx_t *ctx, lsm6dso_sim_t *val)
lsm6dso_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1);
- switch (reg.sim) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
+
+ switch (reg.sim)
+ {
case LSM6DSO_SPI_4_WIRE:
*val = LSM6DSO_SPI_4_WIRE;
break;
+
case LSM6DSO_SPI_3_WIRE:
*val = LSM6DSO_SPI_3_WIRE;
break;
+
default:
*val = LSM6DSO_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -3450,6 +4185,7 @@ int32_t lsm6dso_spi_mode_get(stmdev_ctx_t *ctx, lsm6dso_sim_t *val)
* @param ctx read / write interface definitions
* @param val change the values of i2c_disable in
* reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_i2c_interface_set(stmdev_ctx_t *ctx,
@@ -3458,11 +4194,14 @@ int32_t lsm6dso_i2c_interface_set(stmdev_ctx_t *ctx,
lsm6dso_ctrl4_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.i2c_disable = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3472,6 +4211,7 @@ int32_t lsm6dso_i2c_interface_set(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val Get the values of i2c_disable in
* reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_i2c_interface_get(stmdev_ctx_t *ctx,
@@ -3480,18 +4220,23 @@ int32_t lsm6dso_i2c_interface_get(stmdev_ctx_t *ctx,
lsm6dso_ctrl4_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)®, 1);
- switch (reg.i2c_disable) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
+
+ switch (reg.i2c_disable)
+ {
case LSM6DSO_I2C_ENABLE:
*val = LSM6DSO_I2C_ENABLE;
break;
+
case LSM6DSO_I2C_DISABLE:
*val = LSM6DSO_I2C_DISABLE;
break;
+
default:
*val = LSM6DSO_I2C_ENABLE;
break;
}
+
return ret;
}
@@ -3501,28 +4246,35 @@ int32_t lsm6dso_i2c_interface_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of i3c_disable
* in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_i3c_disable_set(stmdev_ctx_t *ctx, lsm6dso_i3c_disable_t val)
+int32_t lsm6dso_i3c_disable_set(stmdev_ctx_t *ctx,
+ lsm6dso_i3c_disable_t val)
{
lsm6dso_i3c_bus_avb_t i3c_bus_avb;
lsm6dso_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U;
ret = lsm6dso_write_reg(ctx, LSM6DSO_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
}
return ret;
@@ -3534,40 +4286,51 @@ int32_t lsm6dso_i3c_disable_set(stmdev_ctx_t *ctx, lsm6dso_i3c_disable_t val)
* @param ctx read / write interface definitions
* @param val change the values of i3c_disable in
* reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_i3c_disable_get(stmdev_ctx_t *ctx, lsm6dso_i3c_disable_t *val)
+int32_t lsm6dso_i3c_disable_get(stmdev_ctx_t *ctx,
+ lsm6dso_i3c_disable_t *val)
{
lsm6dso_ctrl9_xl_t ctrl9_xl;
lsm6dso_i3c_bus_avb_t i3c_bus_avb;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
- switch ((ctrl9_xl.i3c_disable << 7) | i3c_bus_avb.i3c_bus_avb_sel) {
+ switch ((ctrl9_xl.i3c_disable << 7) | i3c_bus_avb.i3c_bus_avb_sel)
+ {
case LSM6DSO_I3C_DISABLE:
*val = LSM6DSO_I3C_DISABLE;
break;
+
case LSM6DSO_I3C_ENABLE_T_50us:
*val = LSM6DSO_I3C_ENABLE_T_50us;
break;
+
case LSM6DSO_I3C_ENABLE_T_2us:
*val = LSM6DSO_I3C_ENABLE_T_2us;
break;
+
case LSM6DSO_I3C_ENABLE_T_1ms:
*val = LSM6DSO_I3C_ENABLE_T_1ms;
break;
+
case LSM6DSO_I3C_ENABLE_T_25ms:
*val = LSM6DSO_I3C_ENABLE_T_25ms;
break;
+
default:
*val = LSM6DSO_I3C_DISABLE;
break;
}
}
+
return ret;
}
@@ -3578,7 +4341,7 @@ int32_t lsm6dso_i3c_disable_get(stmdev_ctx_t *ctx, lsm6dso_i3c_disable_t *val)
/**
* @defgroup LSM6DSO_interrupt_pins
- * @brief This section groups all the functions that manage interrup pins
+ * @brief This section groups all the functions that manage interrupt pins
* @{
*
*/
@@ -3588,18 +4351,23 @@ int32_t lsm6dso_i3c_disable_get(stmdev_ctx_t *ctx, lsm6dso_i3c_disable_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of pd_dis_int1 in reg I3C_BUS_AVB
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_int1_mode_set(stmdev_ctx_t *ctx, lsm6dso_int1_pd_en_t val)
+int32_t lsm6dso_int1_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso_int1_pd_en_t val)
{
lsm6dso_i3c_bus_avb_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.pd_dis_int1 = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3608,25 +4376,32 @@ int32_t lsm6dso_int1_mode_set(stmdev_ctx_t *ctx, lsm6dso_int1_pd_en_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of pd_dis_int1 in reg I3C_BUS_AVB
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_int1_mode_get(stmdev_ctx_t *ctx, lsm6dso_int1_pd_en_t *val)
+int32_t lsm6dso_int1_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso_int1_pd_en_t *val)
{
lsm6dso_i3c_bus_avb_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t*)®, 1);
- switch (reg.pd_dis_int1) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t *)®, 1);
+
+ switch (reg.pd_dis_int1)
+ {
case LSM6DSO_PULL_DOWN_DISC:
*val = LSM6DSO_PULL_DOWN_DISC;
break;
+
case LSM6DSO_PULL_DOWN_CONNECT:
*val = LSM6DSO_PULL_DOWN_CONNECT;
break;
+
default:
*val = LSM6DSO_PULL_DOWN_DISC;
break;
}
+
return ret;
}
@@ -3635,6 +4410,7 @@ int32_t lsm6dso_int1_mode_get(stmdev_ctx_t *ctx, lsm6dso_int1_pd_en_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of pp_od in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_pin_mode_set(stmdev_ctx_t *ctx, lsm6dso_pp_od_t val)
@@ -3642,11 +4418,14 @@ int32_t lsm6dso_pin_mode_set(stmdev_ctx_t *ctx, lsm6dso_pp_od_t val)
lsm6dso_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.pp_od = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3655,6 +4434,7 @@ int32_t lsm6dso_pin_mode_set(stmdev_ctx_t *ctx, lsm6dso_pp_od_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of pp_od in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_pin_mode_get(stmdev_ctx_t *ctx, lsm6dso_pp_od_t *val)
@@ -3662,19 +4442,23 @@ int32_t lsm6dso_pin_mode_get(stmdev_ctx_t *ctx, lsm6dso_pp_od_t *val)
lsm6dso_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
- switch (reg.pp_od) {
+ switch (reg.pp_od)
+ {
case LSM6DSO_PUSH_PULL:
*val = LSM6DSO_PUSH_PULL;
break;
+
case LSM6DSO_OPEN_DRAIN:
*val = LSM6DSO_OPEN_DRAIN;
break;
+
default:
*val = LSM6DSO_PUSH_PULL;
break;
}
+
return ret;
}
@@ -3683,17 +4467,21 @@ int32_t lsm6dso_pin_mode_get(stmdev_ctx_t *ctx, lsm6dso_pp_od_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of h_lactive in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_pin_polarity_set(stmdev_ctx_t *ctx, lsm6dso_h_lactive_t val)
+int32_t lsm6dso_pin_polarity_set(stmdev_ctx_t *ctx,
+ lsm6dso_h_lactive_t val)
{
lsm6dso_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.h_lactive = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
}
return ret;
@@ -3704,26 +4492,32 @@ int32_t lsm6dso_pin_polarity_set(stmdev_ctx_t *ctx, lsm6dso_h_lactive_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of h_lactive in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_pin_polarity_get(stmdev_ctx_t *ctx, lsm6dso_h_lactive_t *val)
+int32_t lsm6dso_pin_polarity_get(stmdev_ctx_t *ctx,
+ lsm6dso_h_lactive_t *val)
{
lsm6dso_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
- switch (reg.h_lactive) {
+ switch (reg.h_lactive)
+ {
case LSM6DSO_ACTIVE_HIGH:
*val = LSM6DSO_ACTIVE_HIGH;
break;
+
case LSM6DSO_ACTIVE_LOW:
*val = LSM6DSO_ACTIVE_LOW;
break;
+
default:
*val = LSM6DSO_ACTIVE_HIGH;
break;
}
+
return ret;
}
@@ -3732,6 +4526,7 @@ int32_t lsm6dso_pin_polarity_get(stmdev_ctx_t *ctx, lsm6dso_h_lactive_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of int2_on_int1 in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -3739,10 +4534,12 @@ int32_t lsm6dso_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_ctrl4_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.int2_on_int1 = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
}
return ret;
@@ -3753,6 +4550,7 @@ int32_t lsm6dso_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of int2_on_int1 in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -3760,7 +4558,7 @@ int32_t lsm6dso_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_ctrl4_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
*val = reg.int2_on_int1;
return ret;
@@ -3771,32 +4569,43 @@ int32_t lsm6dso_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of lir in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_int_notification_set(stmdev_ctx_t *ctx, lsm6dso_lir_t val)
+int32_t lsm6dso_int_notification_set(stmdev_ctx_t *ctx,
+ lsm6dso_lir_t val)
{
lsm6dso_tap_cfg0_t tap_cfg0;
lsm6dso_page_rw_t page_rw;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
+
+ if (ret == 0)
+ {
tap_cfg0.lir = (uint8_t)val & 0x01U;
tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
}
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -3808,50 +4617,68 @@ int32_t lsm6dso_int_notification_set(stmdev_ctx_t *ctx, lsm6dso_lir_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of lir in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_int_notification_get(stmdev_ctx_t *ctx, lsm6dso_lir_t *val)
+int32_t lsm6dso_int_notification_get(stmdev_ctx_t *ctx,
+ lsm6dso_lir_t *val)
{
lsm6dso_tap_cfg0_t tap_cfg0;
lsm6dso_page_rw_t page_rw;
int32_t ret;
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
- ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
- if (ret == 0) {
-
- ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+ if (ret == 0)
+ {
+ ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
}
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
- if (ret == 0) {
- switch ((page_rw.emb_func_lir << 1) | tap_cfg0.lir) {
+
+ if (ret == 0)
+ {
+ switch ((page_rw.emb_func_lir << 1) | tap_cfg0.lir)
+ {
case LSM6DSO_ALL_INT_PULSED:
*val = LSM6DSO_ALL_INT_PULSED;
break;
+
case LSM6DSO_BASE_LATCHED_EMB_PULSED:
*val = LSM6DSO_BASE_LATCHED_EMB_PULSED;
break;
+
case LSM6DSO_BASE_PULSED_EMB_LATCHED:
*val = LSM6DSO_BASE_PULSED_EMB_LATCHED;
break;
+
case LSM6DSO_ALL_INT_LATCHED:
*val = LSM6DSO_ALL_INT_LATCHED;
break;
+
default:
*val = LSM6DSO_ALL_INT_PULSED;
break;
}
+
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
}
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -3869,7 +4696,7 @@ int32_t lsm6dso_int_notification_get(stmdev_ctx_t *ctx, lsm6dso_lir_t *val)
* event generation.
* @{
*
-*/
+ */
/**
* @brief Weight of 1 LSB of wakeup threshold.[set]
@@ -3879,6 +4706,7 @@ int32_t lsm6dso_int_notification_get(stmdev_ctx_t *ctx, lsm6dso_lir_t *val)
* @param ctx read / write interface definitions
* @param val change the values of wake_ths_w in
* reg WAKE_UP_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_wkup_ths_weight_set(stmdev_ctx_t *ctx,
@@ -3887,11 +4715,14 @@ int32_t lsm6dso_wkup_ths_weight_set(stmdev_ctx_t *ctx,
lsm6dso_wake_up_dur_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.wake_ths_w = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3903,6 +4734,7 @@ int32_t lsm6dso_wkup_ths_weight_set(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val Get the values of wake_ths_w in
* reg WAKE_UP_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_wkup_ths_weight_get(stmdev_ctx_t *ctx,
@@ -3911,19 +4743,23 @@ int32_t lsm6dso_wkup_ths_weight_get(stmdev_ctx_t *ctx,
lsm6dso_wake_up_dur_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1);
- switch (reg.wake_ths_w) {
+ switch (reg.wake_ths_w)
+ {
case LSM6DSO_LSb_FS_DIV_64:
*val = LSM6DSO_LSb_FS_DIV_64;
break;
+
case LSM6DSO_LSb_FS_DIV_256:
*val = LSM6DSO_LSb_FS_DIV_256;
break;
+
default:
*val = LSM6DSO_LSb_FS_DIV_64;
break;
}
+
return ret;
}
@@ -3933,6 +4769,7 @@ int32_t lsm6dso_wkup_ths_weight_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of wk_ths in reg WAKE_UP_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -3940,11 +4777,14 @@ int32_t lsm6dso_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_wake_up_ths_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.wk_ths = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3954,6 +4794,7 @@ int32_t lsm6dso_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of wk_ths in reg WAKE_UP_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -3961,7 +4802,7 @@ int32_t lsm6dso_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_wake_up_ths_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1);
*val = reg.wk_ths;
return ret;
@@ -3973,18 +4814,23 @@ int32_t lsm6dso_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of usr_off_on_wu in reg WAKE_UP_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dso_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dso_wake_up_ths_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.usr_off_on_wu = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3994,14 +4840,16 @@ int32_t lsm6dso_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of usr_off_on_wu in reg WAKE_UP_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso_wake_up_ths_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1);
*val = reg.usr_off_on_wu;
return ret;
@@ -4013,6 +4861,7 @@ int32_t lsm6dso_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of wake_dur in reg WAKE_UP_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -4020,11 +4869,14 @@ int32_t lsm6dso_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_wake_up_dur_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.wake_dur = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4034,6 +4886,7 @@ int32_t lsm6dso_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of wake_dur in reg WAKE_UP_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -4041,7 +4894,7 @@ int32_t lsm6dso_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_wake_up_dur_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1);
*val = reg.wake_dur;
return ret;
@@ -4058,13 +4911,14 @@ int32_t lsm6dso_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
* activity/inactivity detection.
* @{
*
-*/
+ */
/**
* @brief Enables gyroscope Sleep mode.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of sleep_g in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -4072,11 +4926,14 @@ int32_t lsm6dso_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_ctrl4_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.sleep_g = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4085,6 +4942,7 @@ int32_t lsm6dso_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of sleep_g in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -4092,7 +4950,7 @@ int32_t lsm6dso_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_ctrl4_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
*val = reg.sleep_g;
return ret;
@@ -4106,6 +4964,7 @@ int32_t lsm6dso_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of sleep_status_on_int in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_act_pin_notification_set(stmdev_ctx_t *ctx,
@@ -4114,11 +4973,14 @@ int32_t lsm6dso_act_pin_notification_set(stmdev_ctx_t *ctx,
lsm6dso_tap_cfg0_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.sleep_status_on_int = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4130,6 +4992,7 @@ int32_t lsm6dso_act_pin_notification_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of sleep_status_on_int in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_act_pin_notification_get(stmdev_ctx_t *ctx,
@@ -4138,18 +5001,23 @@ int32_t lsm6dso_act_pin_notification_get(stmdev_ctx_t *ctx,
lsm6dso_tap_cfg0_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)®, 1);
- switch (reg.sleep_status_on_int) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
+
+ switch (reg.sleep_status_on_int)
+ {
case LSM6DSO_DRIVE_SLEEP_CHG_EVENT:
*val = LSM6DSO_DRIVE_SLEEP_CHG_EVENT;
break;
+
case LSM6DSO_DRIVE_SLEEP_STATUS:
*val = LSM6DSO_DRIVE_SLEEP_STATUS;
break;
+
default:
*val = LSM6DSO_DRIVE_SLEEP_CHG_EVENT;
break;
}
+
return ret;
}
@@ -4158,18 +5026,23 @@ int32_t lsm6dso_act_pin_notification_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of inact_en in reg TAP_CFG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_act_mode_set(stmdev_ctx_t *ctx, lsm6dso_inact_en_t val)
+int32_t lsm6dso_act_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso_inact_en_t val)
{
lsm6dso_tap_cfg2_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.inact_en = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4178,31 +5051,40 @@ int32_t lsm6dso_act_mode_set(stmdev_ctx_t *ctx, lsm6dso_inact_en_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of inact_en in reg TAP_CFG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_act_mode_get(stmdev_ctx_t *ctx, lsm6dso_inact_en_t *val)
+int32_t lsm6dso_act_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso_inact_en_t *val)
{
lsm6dso_tap_cfg2_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*)®, 1);
- switch (reg.inact_en) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)®, 1);
+
+ switch (reg.inact_en)
+ {
case LSM6DSO_XL_AND_GY_NOT_AFFECTED:
*val = LSM6DSO_XL_AND_GY_NOT_AFFECTED;
break;
+
case LSM6DSO_XL_12Hz5_GY_NOT_AFFECTED:
*val = LSM6DSO_XL_12Hz5_GY_NOT_AFFECTED;
break;
+
case LSM6DSO_XL_12Hz5_GY_SLEEP:
*val = LSM6DSO_XL_12Hz5_GY_SLEEP;
break;
+
case LSM6DSO_XL_12Hz5_GY_PD:
*val = LSM6DSO_XL_12Hz5_GY_PD;
break;
+
default:
*val = LSM6DSO_XL_AND_GY_NOT_AFFECTED;
break;
}
+
return ret;
}
@@ -4212,6 +5094,7 @@ int32_t lsm6dso_act_mode_get(stmdev_ctx_t *ctx, lsm6dso_inact_en_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of sleep_dur in reg WAKE_UP_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -4219,11 +5102,14 @@ int32_t lsm6dso_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_wake_up_dur_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.sleep_dur = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4233,6 +5119,7 @@ int32_t lsm6dso_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of sleep_dur in reg WAKE_UP_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -4240,7 +5127,7 @@ int32_t lsm6dso_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_wake_up_dur_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1);
*val = reg.sleep_dur;
return ret;
@@ -4257,13 +5144,14 @@ int32_t lsm6dso_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
* tap and double tap event generation.
* @{
*
-*/
+ */
/**
* @brief Enable Z direction in tap recognition.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of tap_z_en in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -4271,11 +5159,14 @@ int32_t lsm6dso_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_tap_cfg0_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.tap_z_en = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4284,14 +5175,16 @@ int32_t lsm6dso_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_z_en in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso_tap_cfg0_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
*val = reg.tap_z_en;
return ret;
@@ -4302,6 +5195,7 @@ int32_t lsm6dso_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_y_en in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -4309,11 +5203,14 @@ int32_t lsm6dso_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_tap_cfg0_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.tap_y_en = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4322,14 +5219,16 @@ int32_t lsm6dso_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_y_en in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso_tap_cfg0_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
*val = reg.tap_y_en;
return ret;
@@ -4340,6 +5239,7 @@ int32_t lsm6dso_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_x_en in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -4347,11 +5247,14 @@ int32_t lsm6dso_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_tap_cfg0_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.tap_x_en = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4360,14 +5263,16 @@ int32_t lsm6dso_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_x_en in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso_tap_cfg0_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
*val = reg.tap_x_en;
return ret;
@@ -4378,6 +5283,7 @@ int32_t lsm6dso_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_ths_x in reg TAP_CFG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -4385,11 +5291,14 @@ int32_t lsm6dso_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_tap_cfg1_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.tap_ths_x = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4398,6 +5307,7 @@ int32_t lsm6dso_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_ths_x in reg TAP_CFG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -4405,7 +5315,7 @@ int32_t lsm6dso_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_tap_cfg1_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)®, 1);
*val = reg.tap_ths_x;
return ret;
@@ -4417,6 +5327,7 @@ int32_t lsm6dso_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
* @param ctx read / write interface definitions
* @param val change the values of tap_priority in
* reg TAP_CFG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_tap_axis_priority_set(stmdev_ctx_t *ctx,
@@ -4425,11 +5336,14 @@ int32_t lsm6dso_tap_axis_priority_set(stmdev_ctx_t *ctx,
lsm6dso_tap_cfg1_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.tap_priority = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4439,6 +5353,7 @@ int32_t lsm6dso_tap_axis_priority_set(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val Get the values of tap_priority in
* reg TAP_CFG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_tap_axis_priority_get(stmdev_ctx_t *ctx,
@@ -4447,30 +5362,39 @@ int32_t lsm6dso_tap_axis_priority_get(stmdev_ctx_t *ctx,
lsm6dso_tap_cfg1_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t*)®, 1);
- switch (reg.tap_priority) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)®, 1);
+
+ switch (reg.tap_priority)
+ {
case LSM6DSO_XYZ:
*val = LSM6DSO_XYZ;
break;
+
case LSM6DSO_YXZ:
*val = LSM6DSO_YXZ;
break;
+
case LSM6DSO_XZY:
*val = LSM6DSO_XZY;
break;
+
case LSM6DSO_ZYX:
*val = LSM6DSO_ZYX;
break;
+
case LSM6DSO_YZX:
*val = LSM6DSO_YZX;
break;
+
case LSM6DSO_ZXY:
*val = LSM6DSO_ZXY;
break;
+
default:
*val = LSM6DSO_XYZ;
break;
}
+
return ret;
}
@@ -4479,6 +5403,7 @@ int32_t lsm6dso_tap_axis_priority_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of tap_ths_y in reg TAP_CFG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -4486,11 +5411,14 @@ int32_t lsm6dso_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_tap_cfg2_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.tap_ths_y = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4499,6 +5427,7 @@ int32_t lsm6dso_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_ths_y in reg TAP_CFG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -4506,7 +5435,7 @@ int32_t lsm6dso_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_tap_cfg2_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)®, 1);
*val = reg.tap_ths_y;
return ret;
@@ -4517,6 +5446,7 @@ int32_t lsm6dso_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_ths_z in reg TAP_THS_6D
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -4524,11 +5454,14 @@ int32_t lsm6dso_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_tap_ths_6d_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.tap_ths_z = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4537,6 +5470,7 @@ int32_t lsm6dso_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_ths_z in reg TAP_THS_6D
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -4544,7 +5478,7 @@ int32_t lsm6dso_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_tap_ths_6d_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1);
*val = reg.tap_ths_z;
return ret;
@@ -4560,6 +5494,7 @@ int32_t lsm6dso_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of shock in reg INT_DUR2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -4567,11 +5502,14 @@ int32_t lsm6dso_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_int_dur2_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.shock = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4585,6 +5523,7 @@ int32_t lsm6dso_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of shock in reg INT_DUR2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -4592,7 +5531,7 @@ int32_t lsm6dso_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_int_dur2_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1);
*val = reg.shock;
return ret;
@@ -4609,6 +5548,7 @@ int32_t lsm6dso_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of quiet in reg INT_DUR2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -4616,11 +5556,14 @@ int32_t lsm6dso_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_int_dur2_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.quiet = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4635,6 +5578,7 @@ int32_t lsm6dso_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of quiet in reg INT_DUR2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -4642,7 +5586,7 @@ int32_t lsm6dso_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_int_dur2_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1);
*val = reg.quiet;
return ret;
@@ -4660,6 +5604,7 @@ int32_t lsm6dso_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of dur in reg INT_DUR2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -4667,11 +5612,14 @@ int32_t lsm6dso_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_int_dur2_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.dur = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4687,6 +5635,7 @@ int32_t lsm6dso_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of dur in reg INT_DUR2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -4694,7 +5643,7 @@ int32_t lsm6dso_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_int_dur2_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1);
*val = reg.dur;
return ret;
@@ -4705,6 +5654,7 @@ int32_t lsm6dso_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of single_double_tap in reg WAKE_UP_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_tap_mode_set(stmdev_ctx_t *ctx,
@@ -4713,11 +5663,14 @@ int32_t lsm6dso_tap_mode_set(stmdev_ctx_t *ctx,
lsm6dso_wake_up_ths_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.single_double_tap = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4726,6 +5679,7 @@ int32_t lsm6dso_tap_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of single_double_tap in reg WAKE_UP_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_tap_mode_get(stmdev_ctx_t *ctx,
@@ -4734,15 +5688,18 @@ int32_t lsm6dso_tap_mode_get(stmdev_ctx_t *ctx,
lsm6dso_wake_up_ths_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1);
- switch (reg.single_double_tap) {
+ switch (reg.single_double_tap)
+ {
case LSM6DSO_ONLY_SINGLE:
*val = LSM6DSO_ONLY_SINGLE;
break;
+
case LSM6DSO_BOTH_SINGLE_DOUBLE:
*val = LSM6DSO_BOTH_SINGLE_DOUBLE;
break;
+
default:
*val = LSM6DSO_ONLY_SINGLE;
break;
@@ -4762,25 +5719,30 @@ int32_t lsm6dso_tap_mode_get(stmdev_ctx_t *ctx,
* detection (6D).
* @{
*
-*/
+ */
/**
* @brief Threshold for 4D/6D function.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of sixd_ths in reg TAP_THS_6D
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_6d_threshold_set(stmdev_ctx_t *ctx, lsm6dso_sixd_ths_t val)
+int32_t lsm6dso_6d_threshold_set(stmdev_ctx_t *ctx,
+ lsm6dso_sixd_ths_t val)
{
lsm6dso_tap_ths_6d_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.sixd_ths = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4789,31 +5751,40 @@ int32_t lsm6dso_6d_threshold_set(stmdev_ctx_t *ctx, lsm6dso_sixd_ths_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of sixd_ths in reg TAP_THS_6D
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_6d_threshold_get(stmdev_ctx_t *ctx, lsm6dso_sixd_ths_t *val)
+int32_t lsm6dso_6d_threshold_get(stmdev_ctx_t *ctx,
+ lsm6dso_sixd_ths_t *val)
{
lsm6dso_tap_ths_6d_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)®, 1);
- switch (reg.sixd_ths) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1);
+
+ switch (reg.sixd_ths)
+ {
case LSM6DSO_DEG_80:
*val = LSM6DSO_DEG_80;
break;
+
case LSM6DSO_DEG_70:
*val = LSM6DSO_DEG_70;
break;
+
case LSM6DSO_DEG_60:
*val = LSM6DSO_DEG_60;
break;
+
case LSM6DSO_DEG_50:
*val = LSM6DSO_DEG_50;
break;
+
default:
*val = LSM6DSO_DEG_80;
break;
}
+
return ret;
}
@@ -4822,6 +5793,7 @@ int32_t lsm6dso_6d_threshold_get(stmdev_ctx_t *ctx, lsm6dso_sixd_ths_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of d4d_en in reg TAP_THS_6D
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -4829,11 +5801,14 @@ int32_t lsm6dso_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_tap_ths_6d_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.d4d_en = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4842,6 +5817,7 @@ int32_t lsm6dso_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of d4d_en in reg TAP_THS_6D
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -4849,7 +5825,7 @@ int32_t lsm6dso_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_tap_ths_6d_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1);
*val = reg.d4d_en;
return ret;
@@ -4866,24 +5842,29 @@ int32_t lsm6dso_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
* fall detection.
* @{
*
-*/
+ */
/**
* @brief Free fall threshold setting.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of ff_ths in reg FREE_FALL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_ff_threshold_set(stmdev_ctx_t *ctx, lsm6dso_ff_ths_t val)
+int32_t lsm6dso_ff_threshold_set(stmdev_ctx_t *ctx,
+ lsm6dso_ff_ths_t val)
{
lsm6dso_free_fall_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.ff_ths = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4892,43 +5873,56 @@ int32_t lsm6dso_ff_threshold_set(stmdev_ctx_t *ctx, lsm6dso_ff_ths_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of ff_ths in reg FREE_FALL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_ff_threshold_get(stmdev_ctx_t *ctx, lsm6dso_ff_ths_t *val)
+int32_t lsm6dso_ff_threshold_get(stmdev_ctx_t *ctx,
+ lsm6dso_ff_ths_t *val)
{
lsm6dso_free_fall_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t*)®, 1);
- switch (reg.ff_ths) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)®, 1);
+
+ switch (reg.ff_ths)
+ {
case LSM6DSO_FF_TSH_156mg:
*val = LSM6DSO_FF_TSH_156mg;
break;
+
case LSM6DSO_FF_TSH_219mg:
*val = LSM6DSO_FF_TSH_219mg;
break;
+
case LSM6DSO_FF_TSH_250mg:
*val = LSM6DSO_FF_TSH_250mg;
break;
+
case LSM6DSO_FF_TSH_312mg:
*val = LSM6DSO_FF_TSH_312mg;
break;
+
case LSM6DSO_FF_TSH_344mg:
*val = LSM6DSO_FF_TSH_344mg;
break;
+
case LSM6DSO_FF_TSH_406mg:
*val = LSM6DSO_FF_TSH_406mg;
break;
+
case LSM6DSO_FF_TSH_469mg:
*val = LSM6DSO_FF_TSH_469mg;
break;
+
case LSM6DSO_FF_TSH_500mg:
*val = LSM6DSO_FF_TSH_500mg;
break;
+
default:
*val = LSM6DSO_FF_TSH_156mg;
break;
}
+
return ret;
}
@@ -4938,6 +5932,7 @@ int32_t lsm6dso_ff_threshold_get(stmdev_ctx_t *ctx, lsm6dso_ff_ths_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of ff_dur in reg FREE_FALL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -4946,19 +5941,27 @@ int32_t lsm6dso_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_free_fall_t free_fall;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t*)&free_fall, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)&free_fall, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5;
free_fall.ff_dur = (uint8_t)val & 0x1FU;
ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
- if (ret == 0) {
- ret = lsm6dso_write_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t*)&free_fall, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)&free_fall, 1);
}
+
return ret;
}
@@ -4968,6 +5971,7 @@ int32_t lsm6dso_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of ff_dur in reg FREE_FALL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -4976,11 +5980,15 @@ int32_t lsm6dso_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_free_fall_t free_fall;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t*)&free_fall, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)&free_fall, 1);
*val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
}
+
return ret;
}
@@ -4994,13 +6002,14 @@ int32_t lsm6dso_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
* @brief This section group all the functions concerning the fifo usage
* @{
*
-*/
+ */
/**
* @brief FIFO watermark level selection.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of wtm in reg FIFO_CTRL1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
@@ -5009,15 +6018,23 @@ int32_t lsm6dso_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
lsm6dso_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl1.wtm = 0x00FFU & (uint8_t)val;
- fifo_ctrl2.wtm = (uint8_t)(( 0x0100U & val ) >> 8);
- ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1);
+ fifo_ctrl2.wtm = (uint8_t)((0x0100U & val) >> 8);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL1,
+ (uint8_t *)&fifo_ctrl1, 1);
}
- if (ret == 0) {
- ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
}
+
return ret;
}
@@ -5026,6 +6043,7 @@ int32_t lsm6dso_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of wtm in reg FIFO_CTRL1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
@@ -5034,11 +6052,16 @@ int32_t lsm6dso_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
lsm6dso_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL1,
+ (uint8_t *)&fifo_ctrl1, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
*val = ((uint16_t)fifo_ctrl2.wtm << 8) + (uint16_t)fifo_ctrl1.wtm;
}
+
return ret;
}
@@ -5048,22 +6071,30 @@ int32_t lsm6dso_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
* @param ctx read / write interface definitions
* @param val change the values of FIFO_COMPR_INIT in
* reg EMB_FUNC_INIT_B
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_compression_algo_init_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dso_compression_algo_init_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dso_emb_func_init_b_t reg;
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.fifo_compr_init = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -5076,18 +6107,24 @@ int32_t lsm6dso_compression_algo_init_set(stmdev_ctx_t *ctx, uint8_t val)
* @param ctx read / write interface definitions
* @param val change the values of FIFO_COMPR_INIT in
* reg EMB_FUNC_INIT_B
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_compression_algo_init_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso_compression_algo_init_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso_emb_func_init_b_t reg;
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.fifo_compr_init;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -5101,39 +6138,26 @@ int32_t lsm6dso_compression_algo_init_get(stmdev_ctx_t *ctx, uint8_t *val)
* @param ctx read / write interface definitions
* @param val change the values of uncoptr_rate in
* reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_compression_algo_set(stmdev_ctx_t *ctx,
lsm6dso_uncoptr_rate_t val)
{
- lsm6dso_emb_func_en_b_t emb_func_en_b;
lsm6dso_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
- ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
- }
- if (ret == 0) {
- emb_func_en_b.fifo_compr_en = ((uint8_t)val & 0x04U) >> 2;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
- }
- if (ret == 0) {
- ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
- }
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- }
- if (ret == 0) {
+ if (ret == 0)
+ {
fifo_ctrl2.fifo_compr_rt_en = ((uint8_t)val & 0x04U) >> 2;
fifo_ctrl2.uncoptr_rate = (uint8_t)val & 0x03U;
ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
+
return ret;
}
@@ -5143,6 +6167,7 @@ int32_t lsm6dso_compression_algo_set(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val Get the values of uncoptr_rate in
* reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_compression_algo_get(stmdev_ctx_t *ctx,
@@ -5151,28 +6176,35 @@ int32_t lsm6dso_compression_algo_get(stmdev_ctx_t *ctx,
lsm6dso_fifo_ctrl2_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1);
- switch ((reg.fifo_compr_rt_en<<2) | reg.uncoptr_rate) {
+ switch ((reg.fifo_compr_rt_en << 2) | reg.uncoptr_rate)
+ {
case LSM6DSO_CMP_DISABLE:
*val = LSM6DSO_CMP_DISABLE;
break;
+
case LSM6DSO_CMP_ALWAYS:
*val = LSM6DSO_CMP_ALWAYS;
break;
+
case LSM6DSO_CMP_8_TO_1:
*val = LSM6DSO_CMP_8_TO_1;
break;
+
case LSM6DSO_CMP_16_TO_1:
*val = LSM6DSO_CMP_16_TO_1;
break;
+
case LSM6DSO_CMP_32_TO_1:
*val = LSM6DSO_CMP_32_TO_1;
break;
+
default:
*val = LSM6DSO_CMP_DISABLE;
break;
}
+
return ret;
}
@@ -5181,6 +6213,7 @@ int32_t lsm6dso_compression_algo_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of odrchg_en in reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
@@ -5189,11 +6222,14 @@ int32_t lsm6dso_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
lsm6dso_fifo_ctrl2_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.odrchg_en = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -5202,6 +6238,7 @@ int32_t lsm6dso_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of odrchg_en in reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
@@ -5210,7 +6247,7 @@ int32_t lsm6dso_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
lsm6dso_fifo_ctrl2_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1);
*val = reg.odrchg_en;
return ret;
@@ -5222,6 +6259,7 @@ int32_t lsm6dso_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of fifo_compr_rt_en in
* reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_compression_algo_real_time_set(stmdev_ctx_t *ctx,
@@ -5230,11 +6268,14 @@ int32_t lsm6dso_compression_algo_real_time_set(stmdev_ctx_t *ctx,
lsm6dso_fifo_ctrl2_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.fifo_compr_rt_en = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -5243,6 +6284,7 @@ int32_t lsm6dso_compression_algo_real_time_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of fifo_compr_rt_en in reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_compression_algo_real_time_get(stmdev_ctx_t *ctx,
@@ -5251,7 +6293,7 @@ int32_t lsm6dso_compression_algo_real_time_get(stmdev_ctx_t *ctx,
lsm6dso_fifo_ctrl2_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1);
*val = reg.fifo_compr_rt_en;
return ret;
@@ -5263,6 +6305,7 @@ int32_t lsm6dso_compression_algo_real_time_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of stop_on_wtm in reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -5270,11 +6313,14 @@ int32_t lsm6dso_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_fifo_ctrl2_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.stop_on_wtm = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -5284,6 +6330,7 @@ int32_t lsm6dso_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of stop_on_wtm in reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -5291,7 +6338,7 @@ int32_t lsm6dso_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_fifo_ctrl2_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1);
*val = reg.stop_on_wtm;
return ret;
@@ -5303,18 +6350,23 @@ int32_t lsm6dso_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of bdr_xl in reg FIFO_CTRL3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_fifo_xl_batch_set(stmdev_ctx_t *ctx, lsm6dso_bdr_xl_t val)
+int32_t lsm6dso_fifo_xl_batch_set(stmdev_ctx_t *ctx,
+ lsm6dso_bdr_xl_t val)
{
lsm6dso_fifo_ctrl3_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.bdr_xl = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -5324,51 +6376,67 @@ int32_t lsm6dso_fifo_xl_batch_set(stmdev_ctx_t *ctx, lsm6dso_bdr_xl_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of bdr_xl in reg FIFO_CTRL3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_fifo_xl_batch_get(stmdev_ctx_t *ctx, lsm6dso_bdr_xl_t *val)
+int32_t lsm6dso_fifo_xl_batch_get(stmdev_ctx_t *ctx,
+ lsm6dso_bdr_xl_t *val)
{
lsm6dso_fifo_ctrl3_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t*)®, 1);
- switch (reg.bdr_xl) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)®, 1);
+
+ switch (reg.bdr_xl)
+ {
case LSM6DSO_XL_NOT_BATCHED:
*val = LSM6DSO_XL_NOT_BATCHED;
break;
+
case LSM6DSO_XL_BATCHED_AT_12Hz5:
*val = LSM6DSO_XL_BATCHED_AT_12Hz5;
break;
+
case LSM6DSO_XL_BATCHED_AT_26Hz:
*val = LSM6DSO_XL_BATCHED_AT_26Hz;
break;
+
case LSM6DSO_XL_BATCHED_AT_52Hz:
*val = LSM6DSO_XL_BATCHED_AT_52Hz;
break;
+
case LSM6DSO_XL_BATCHED_AT_104Hz:
*val = LSM6DSO_XL_BATCHED_AT_104Hz;
break;
+
case LSM6DSO_XL_BATCHED_AT_208Hz:
*val = LSM6DSO_XL_BATCHED_AT_208Hz;
break;
+
case LSM6DSO_XL_BATCHED_AT_417Hz:
*val = LSM6DSO_XL_BATCHED_AT_417Hz;
break;
+
case LSM6DSO_XL_BATCHED_AT_833Hz:
*val = LSM6DSO_XL_BATCHED_AT_833Hz;
break;
+
case LSM6DSO_XL_BATCHED_AT_1667Hz:
*val = LSM6DSO_XL_BATCHED_AT_1667Hz;
break;
+
case LSM6DSO_XL_BATCHED_AT_3333Hz:
*val = LSM6DSO_XL_BATCHED_AT_3333Hz;
break;
+
case LSM6DSO_XL_BATCHED_AT_6667Hz:
*val = LSM6DSO_XL_BATCHED_AT_6667Hz;
break;
+
case LSM6DSO_XL_BATCHED_AT_6Hz5:
*val = LSM6DSO_XL_BATCHED_AT_6Hz5;
break;
+
default:
*val = LSM6DSO_XL_NOT_BATCHED;
break;
@@ -5383,18 +6451,23 @@ int32_t lsm6dso_fifo_xl_batch_get(stmdev_ctx_t *ctx, lsm6dso_bdr_xl_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of bdr_gy in reg FIFO_CTRL3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_fifo_gy_batch_set(stmdev_ctx_t *ctx, lsm6dso_bdr_gy_t val)
+int32_t lsm6dso_fifo_gy_batch_set(stmdev_ctx_t *ctx,
+ lsm6dso_bdr_gy_t val)
{
lsm6dso_fifo_ctrl3_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.bdr_gy = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -5404,55 +6477,72 @@ int32_t lsm6dso_fifo_gy_batch_set(stmdev_ctx_t *ctx, lsm6dso_bdr_gy_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of bdr_gy in reg FIFO_CTRL3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_fifo_gy_batch_get(stmdev_ctx_t *ctx, lsm6dso_bdr_gy_t *val)
+int32_t lsm6dso_fifo_gy_batch_get(stmdev_ctx_t *ctx,
+ lsm6dso_bdr_gy_t *val)
{
lsm6dso_fifo_ctrl3_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t*)®, 1);
- switch (reg.bdr_gy) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)®, 1);
+
+ switch (reg.bdr_gy)
+ {
case LSM6DSO_GY_NOT_BATCHED:
*val = LSM6DSO_GY_NOT_BATCHED;
break;
+
case LSM6DSO_GY_BATCHED_AT_12Hz5:
*val = LSM6DSO_GY_BATCHED_AT_12Hz5;
break;
+
case LSM6DSO_GY_BATCHED_AT_26Hz:
*val = LSM6DSO_GY_BATCHED_AT_26Hz;
break;
+
case LSM6DSO_GY_BATCHED_AT_52Hz:
*val = LSM6DSO_GY_BATCHED_AT_52Hz;
break;
+
case LSM6DSO_GY_BATCHED_AT_104Hz:
*val = LSM6DSO_GY_BATCHED_AT_104Hz;
break;
+
case LSM6DSO_GY_BATCHED_AT_208Hz:
*val = LSM6DSO_GY_BATCHED_AT_208Hz;
break;
+
case LSM6DSO_GY_BATCHED_AT_417Hz:
*val = LSM6DSO_GY_BATCHED_AT_417Hz;
break;
+
case LSM6DSO_GY_BATCHED_AT_833Hz:
*val = LSM6DSO_GY_BATCHED_AT_833Hz;
break;
+
case LSM6DSO_GY_BATCHED_AT_1667Hz:
*val = LSM6DSO_GY_BATCHED_AT_1667Hz;
break;
+
case LSM6DSO_GY_BATCHED_AT_3333Hz:
*val = LSM6DSO_GY_BATCHED_AT_3333Hz;
break;
+
case LSM6DSO_GY_BATCHED_AT_6667Hz:
*val = LSM6DSO_GY_BATCHED_AT_6667Hz;
break;
+
case LSM6DSO_GY_BATCHED_AT_6Hz5:
*val = LSM6DSO_GY_BATCHED_AT_6Hz5;
break;
+
default:
*val = LSM6DSO_GY_NOT_BATCHED;
break;
}
+
return ret;
}
@@ -5461,18 +6551,23 @@ int32_t lsm6dso_fifo_gy_batch_get(stmdev_ctx_t *ctx, lsm6dso_bdr_gy_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of fifo_mode in reg FIFO_CTRL4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_fifo_mode_set(stmdev_ctx_t *ctx, lsm6dso_fifo_mode_t val)
+int32_t lsm6dso_fifo_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso_fifo_mode_t val)
{
lsm6dso_fifo_ctrl4_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.fifo_mode = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -5481,38 +6576,48 @@ int32_t lsm6dso_fifo_mode_set(stmdev_ctx_t *ctx, lsm6dso_fifo_mode_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of fifo_mode in reg FIFO_CTRL4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_fifo_mode_get(stmdev_ctx_t *ctx, lsm6dso_fifo_mode_t *val)
+int32_t lsm6dso_fifo_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso_fifo_mode_t *val)
{
lsm6dso_fifo_ctrl4_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1);
- switch (reg.fifo_mode) {
+ switch (reg.fifo_mode)
+ {
case LSM6DSO_BYPASS_MODE:
*val = LSM6DSO_BYPASS_MODE;
break;
+
case LSM6DSO_FIFO_MODE:
*val = LSM6DSO_FIFO_MODE;
break;
+
case LSM6DSO_STREAM_TO_FIFO_MODE:
*val = LSM6DSO_STREAM_TO_FIFO_MODE;
break;
+
case LSM6DSO_BYPASS_TO_STREAM_MODE:
*val = LSM6DSO_BYPASS_TO_STREAM_MODE;
break;
+
case LSM6DSO_STREAM_MODE:
*val = LSM6DSO_STREAM_MODE;
break;
+
case LSM6DSO_BYPASS_TO_FIFO_MODE:
*val = LSM6DSO_BYPASS_TO_FIFO_MODE;
break;
+
default:
*val = LSM6DSO_BYPASS_MODE;
break;
}
+
return ret;
}
@@ -5522,6 +6627,7 @@ int32_t lsm6dso_fifo_mode_get(stmdev_ctx_t *ctx, lsm6dso_fifo_mode_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of odr_t_batch in reg FIFO_CTRL4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_fifo_temp_batch_set(stmdev_ctx_t *ctx,
@@ -5530,11 +6636,14 @@ int32_t lsm6dso_fifo_temp_batch_set(stmdev_ctx_t *ctx,
lsm6dso_fifo_ctrl4_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.odr_t_batch = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -5544,6 +6653,7 @@ int32_t lsm6dso_fifo_temp_batch_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of odr_t_batch in reg FIFO_CTRL4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_fifo_temp_batch_get(stmdev_ctx_t *ctx,
@@ -5552,25 +6662,31 @@ int32_t lsm6dso_fifo_temp_batch_get(stmdev_ctx_t *ctx,
lsm6dso_fifo_ctrl4_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1);
- switch (reg.odr_t_batch) {
+ switch (reg.odr_t_batch)
+ {
case LSM6DSO_TEMP_NOT_BATCHED:
*val = LSM6DSO_TEMP_NOT_BATCHED;
break;
+
case LSM6DSO_TEMP_BATCHED_AT_1Hz6:
*val = LSM6DSO_TEMP_BATCHED_AT_1Hz6;
break;
+
case LSM6DSO_TEMP_BATCHED_AT_12Hz5:
*val = LSM6DSO_TEMP_BATCHED_AT_12Hz5;
break;
+
case LSM6DSO_TEMP_BATCHED_AT_52Hz:
*val = LSM6DSO_TEMP_BATCHED_AT_52Hz;
break;
+
default:
*val = LSM6DSO_TEMP_NOT_BATCHED;
break;
}
+
return ret;
}
@@ -5581,6 +6697,7 @@ int32_t lsm6dso_fifo_temp_batch_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of odr_ts_batch in reg FIFO_CTRL4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
@@ -5589,11 +6706,14 @@ int32_t lsm6dso_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
lsm6dso_fifo_ctrl4_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.odr_ts_batch = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -5604,6 +6724,7 @@ int32_t lsm6dso_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of odr_ts_batch in reg FIFO_CTRL4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
@@ -5612,24 +6733,31 @@ int32_t lsm6dso_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
lsm6dso_fifo_ctrl4_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)®, 1);
- switch (reg.odr_ts_batch) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1);
+
+ switch (reg.odr_ts_batch)
+ {
case LSM6DSO_NO_DECIMATION:
*val = LSM6DSO_NO_DECIMATION;
break;
+
case LSM6DSO_DEC_1:
*val = LSM6DSO_DEC_1;
break;
+
case LSM6DSO_DEC_8:
*val = LSM6DSO_DEC_8;
break;
+
case LSM6DSO_DEC_32:
*val = LSM6DSO_DEC_32;
break;
+
default:
*val = LSM6DSO_NO_DECIMATION;
break;
}
+
return ret;
}
@@ -5640,6 +6768,7 @@ int32_t lsm6dso_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of trig_counter_bdr
* in reg COUNTER_BDR_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
@@ -5648,11 +6777,15 @@ int32_t lsm6dso_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
lsm6dso_counter_bdr_reg1_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.trig_counter_bdr = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1,
+ (uint8_t *)®, 1);
}
+
return ret;
}
@@ -5663,6 +6796,7 @@ int32_t lsm6dso_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val Get the values of trig_counter_bdr
* in reg COUNTER_BDR_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
@@ -5671,18 +6805,23 @@ int32_t lsm6dso_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
lsm6dso_counter_bdr_reg1_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)®, 1);
- switch (reg.trig_counter_bdr) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)®, 1);
+
+ switch (reg.trig_counter_bdr)
+ {
case LSM6DSO_XL_BATCH_EVENT:
*val = LSM6DSO_XL_BATCH_EVENT;
break;
+
case LSM6DSO_GYRO_BATCH_EVENT:
*val = LSM6DSO_GYRO_BATCH_EVENT;
break;
+
default:
*val = LSM6DSO_XL_BATCH_EVENT;
break;
}
+
return ret;
}
@@ -5693,6 +6832,7 @@ int32_t lsm6dso_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of rst_counter_bdr in
* reg COUNTER_BDR_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -5700,11 +6840,15 @@ int32_t lsm6dso_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_counter_bdr_reg1_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.rst_counter_bdr = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1,
+ (uint8_t *)®, 1);
}
+
return ret;
}
@@ -5715,6 +6859,7 @@ int32_t lsm6dso_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val)
* @param ctx read / write interface definitions
* @param val change the values of rst_counter_bdr in
* reg COUNTER_BDR_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -5722,7 +6867,7 @@ int32_t lsm6dso_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_counter_bdr_reg1_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)®, 1);
*val = reg.rst_counter_bdr;
return ret;
@@ -5734,26 +6879,33 @@ int32_t lsm6dso_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val)
* @param ctx read / write interface definitions
* @param val change the values of cnt_bdr_th in
* reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_batch_counter_threshold_set(stmdev_ctx_t *ctx, uint16_t val)
+int32_t lsm6dso_batch_counter_threshold_set(stmdev_ctx_t *ctx,
+ uint16_t val)
{
lsm6dso_counter_bdr_reg1_t counter_bdr_reg1;
lsm6dso_counter_bdr_reg2_t counter_bdr_reg2;
int32_t ret;
ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if (ret == 0) {
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
counter_bdr_reg2.cnt_bdr_th = 0x00FFU & (uint8_t)val;
counter_bdr_reg1.cnt_bdr_th = (uint8_t)(0x0700U & val) >> 8;
ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG2,
- (uint8_t*)&counter_bdr_reg2, 1);
+ (uint8_t *)&counter_bdr_reg2, 1);
}
+
return ret;
}
@@ -5763,22 +6915,25 @@ int32_t lsm6dso_batch_counter_threshold_set(stmdev_ctx_t *ctx, uint16_t val)
* @param ctx read / write interface definitions
* @param val change the values of cnt_bdr_th in
* reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_batch_counter_threshold_get(stmdev_ctx_t *ctx, uint16_t *val)
+int32_t lsm6dso_batch_counter_threshold_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
lsm6dso_counter_bdr_reg1_t counter_bdr_reg1;
lsm6dso_counter_bdr_reg2_t counter_bdr_reg2;
int32_t ret;
ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG2,
- (uint8_t*)&counter_bdr_reg2, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG2,
+ (uint8_t *)&counter_bdr_reg2, 1);
*val = ((uint16_t)counter_bdr_reg1.cnt_bdr_th << 8)
- + (uint16_t)counter_bdr_reg2.cnt_bdr_th;
+ + (uint16_t)counter_bdr_reg2.cnt_bdr_th;
}
return ret;
@@ -5789,6 +6944,7 @@ int32_t lsm6dso_batch_counter_threshold_get(stmdev_ctx_t *ctx, uint16_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of diff_fifo in reg FIFO_STATUS1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
@@ -5798,13 +6954,16 @@ int32_t lsm6dso_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
int32_t ret;
ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS1,
- (uint8_t*)&fifo_status1, 1);
- if (ret == 0) {
+ (uint8_t *)&fifo_status1, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
+ (uint8_t *)&fifo_status2, 1);
*val = ((uint16_t)fifo_status2.diff_fifo << 8) +
- (uint16_t)fifo_status1.diff_fifo;
+ (uint16_t)fifo_status1.diff_fifo;
}
+
return ret;
}
@@ -5813,13 +6972,16 @@ int32_t lsm6dso_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
*
* @param ctx read / write interface definitions
* @param val registers FIFO_STATUS2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_fifo_status_get(stmdev_ctx_t *ctx,
lsm6dso_fifo_status2_t *val)
{
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t*) val, 1);
+
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t *) val, 1);
+
return ret;
}
@@ -5828,6 +6990,7 @@ int32_t lsm6dso_fifo_status_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of fifo_full_ia in reg FIFO_STATUS2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -5835,7 +6998,7 @@ int32_t lsm6dso_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_fifo_status2_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t *)®, 1);
*val = reg.fifo_full_ia;
return ret;
@@ -5847,6 +7010,7 @@ int32_t lsm6dso_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
* @param ctx read / write interface definitions
* @param val change the values of fifo_over_run_latched in
* reg FIFO_STATUS2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -5854,7 +7018,7 @@ int32_t lsm6dso_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_fifo_status2_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t *)®, 1);
*val = reg.fifo_ovr_ia;
return ret;
@@ -5865,6 +7029,7 @@ int32_t lsm6dso_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of fifo_wtm_ia in reg FIFO_STATUS2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -5872,7 +7037,7 @@ int32_t lsm6dso_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_fifo_status2_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t *)®, 1);
*val = reg.fifo_wtm_ia;
return ret;
@@ -5883,6 +7048,7 @@ int32_t lsm6dso_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of tag_sensor in reg FIFO_DATA_OUT_TAG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
@@ -5891,75 +7057,100 @@ int32_t lsm6dso_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
lsm6dso_fifo_data_out_tag_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_DATA_OUT_TAG, (uint8_t*)®, 1);
- switch (reg.tag_sensor) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_DATA_OUT_TAG,
+ (uint8_t *)®, 1);
+
+ switch (reg.tag_sensor)
+ {
case LSM6DSO_GYRO_NC_TAG:
*val = LSM6DSO_GYRO_NC_TAG;
break;
+
case LSM6DSO_XL_NC_TAG:
*val = LSM6DSO_XL_NC_TAG;
break;
+
case LSM6DSO_TEMPERATURE_TAG:
*val = LSM6DSO_TEMPERATURE_TAG;
break;
+
case LSM6DSO_CFG_CHANGE_TAG:
*val = LSM6DSO_CFG_CHANGE_TAG;
break;
+
case LSM6DSO_XL_NC_T_2_TAG:
*val = LSM6DSO_XL_NC_T_2_TAG;
break;
+
case LSM6DSO_XL_NC_T_1_TAG:
*val = LSM6DSO_XL_NC_T_1_TAG;
break;
+
case LSM6DSO_XL_2XC_TAG:
*val = LSM6DSO_XL_2XC_TAG;
break;
+
case LSM6DSO_XL_3XC_TAG:
*val = LSM6DSO_XL_3XC_TAG;
break;
+
case LSM6DSO_GYRO_NC_T_2_TAG:
*val = LSM6DSO_GYRO_NC_T_2_TAG;
break;
+
case LSM6DSO_GYRO_NC_T_1_TAG:
*val = LSM6DSO_GYRO_NC_T_1_TAG;
break;
+
case LSM6DSO_GYRO_2XC_TAG:
*val = LSM6DSO_GYRO_2XC_TAG;
break;
+
case LSM6DSO_GYRO_3XC_TAG:
*val = LSM6DSO_GYRO_3XC_TAG;
break;
+
case LSM6DSO_SENSORHUB_SLAVE0_TAG:
*val = LSM6DSO_SENSORHUB_SLAVE0_TAG;
break;
+
case LSM6DSO_SENSORHUB_SLAVE1_TAG:
*val = LSM6DSO_SENSORHUB_SLAVE1_TAG;
break;
+
case LSM6DSO_SENSORHUB_SLAVE2_TAG:
*val = LSM6DSO_SENSORHUB_SLAVE2_TAG;
break;
+
case LSM6DSO_SENSORHUB_SLAVE3_TAG:
*val = LSM6DSO_SENSORHUB_SLAVE3_TAG;
break;
+
case LSM6DSO_STEP_CPUNTER_TAG:
*val = LSM6DSO_STEP_CPUNTER_TAG;
break;
+
case LSM6DSO_GAME_ROTATION_TAG:
*val = LSM6DSO_GAME_ROTATION_TAG;
break;
+
case LSM6DSO_GEOMAG_ROTATION_TAG:
*val = LSM6DSO_GEOMAG_ROTATION_TAG;
break;
+
case LSM6DSO_ROTATION_TAG:
*val = LSM6DSO_ROTATION_TAG;
break;
+
case LSM6DSO_SENSORHUB_NACK_TAG:
*val = LSM6DSO_SENSORHUB_NACK_TAG;
break;
+
default:
*val = LSM6DSO_GYRO_NC_TAG;
break;
}
+
return ret;
}
@@ -5970,6 +7161,7 @@ int32_t lsm6dso_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of gbias_fifo_en in
* reg LSM6DSO_EMB_FUNC_FIFO_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -5978,17 +7170,25 @@ int32_t lsm6dso_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_FIFO_CFG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_FIFO_CFG,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.pedo_fifo_en = val;
ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_FIFO_CFG,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
+
return ret;
}
@@ -5998,6 +7198,7 @@ int32_t lsm6dso_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val)
* @param ctx read / write interface definitions
* @param val change the values of pedo_fifo_en in
* reg LSM6DSO_EMB_FUNC_FIFO_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -6006,13 +7207,19 @@ int32_t lsm6dso_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_FIFO_CFG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_FIFO_CFG,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.pedo_fifo_en;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
+
return ret;
}
@@ -6022,6 +7229,7 @@ int32_t lsm6dso_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
* @param ctx read / write interface definitions
* @param val change the values of batch_ext_sens_0_en in
* reg SLV0_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -6030,16 +7238,23 @@ int32_t lsm6dso_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.batch_ext_sens_0_en = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
+
return ret;
}
@@ -6049,6 +7264,7 @@ int32_t lsm6dso_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val)
* @param ctx read / write interface definitions
* @param val change the values of batch_ext_sens_0_en in
* reg SLV0_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -6057,13 +7273,18 @@ int32_t lsm6dso_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.batch_ext_sens_0_en;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
+
return ret;
}
@@ -6073,6 +7294,7 @@ int32_t lsm6dso_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val)
* @param ctx read / write interface definitions
* @param val change the values of batch_ext_sens_1_en in
* reg SLV1_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -6081,14 +7303,20 @@ int32_t lsm6dso_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.batch_ext_sens_1_en = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -6101,6 +7329,7 @@ int32_t lsm6dso_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val)
* @param ctx read / write interface definitions
* @param val change the values of batch_ext_sens_1_en in
* reg SLV1_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -6109,13 +7338,18 @@ int32_t lsm6dso_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t *)®, 1);
*val = reg.batch_ext_sens_1_en;
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
+
return ret;
}
@@ -6125,6 +7359,7 @@ int32_t lsm6dso_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val)
* @param ctx read / write interface definitions
* @param val change the values of batch_ext_sens_2_en in
* reg SLV2_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -6134,16 +7369,22 @@ int32_t lsm6dso_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val)
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV2_CONFIG, (uint8_t*)®, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV2_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.batch_ext_sens_2_en = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
+
return ret;
}
@@ -6153,6 +7394,7 @@ int32_t lsm6dso_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val)
* @param ctx read / write interface definitions
* @param val change the values of batch_ext_sens_2_en in
* reg SLV2_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -6161,10 +7403,14 @@ int32_t lsm6dso_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV2_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV2_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.batch_ext_sens_2_en;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -6178,6 +7424,7 @@ int32_t lsm6dso_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val)
* @param ctx read / write interface definitions
* @param val change the values of batch_ext_sens_3_en
* in reg SLV3_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -6186,14 +7433,20 @@ int32_t lsm6dso_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV3_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV3_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.batch_ext_sens_3_en = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -6206,6 +7459,7 @@ int32_t lsm6dso_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val)
* @param ctx read / write interface definitions
* @param val change the values of batch_ext_sens_3_en in
* reg SLV3_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -6214,10 +7468,14 @@ int32_t lsm6dso_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV3_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV3_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.batch_ext_sens_3_en;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -6236,24 +7494,28 @@ int32_t lsm6dso_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val)
* DEN functionality.
* @{
*
-*/
+ */
/**
* @brief DEN functionality marking mode.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of den_mode in reg CTRL6_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_den_mode_set(stmdev_ctx_t *ctx, lsm6dso_den_mode_t val)
+int32_t lsm6dso_den_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso_den_mode_t val)
{
lsm6dso_ctrl6_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.den_mode = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1);
}
return ret;
@@ -6264,35 +7526,44 @@ int32_t lsm6dso_den_mode_set(stmdev_ctx_t *ctx, lsm6dso_den_mode_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of den_mode in reg CTRL6_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_den_mode_get(stmdev_ctx_t *ctx, lsm6dso_den_mode_t *val)
+int32_t lsm6dso_den_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso_den_mode_t *val)
{
lsm6dso_ctrl6_c_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1);
- switch (reg.den_mode) {
+ switch (reg.den_mode)
+ {
case LSM6DSO_DEN_DISABLE:
*val = LSM6DSO_DEN_DISABLE;
break;
+
case LSM6DSO_LEVEL_FIFO:
*val = LSM6DSO_LEVEL_FIFO;
break;
+
case LSM6DSO_LEVEL_LETCHED:
*val = LSM6DSO_LEVEL_LETCHED;
break;
+
case LSM6DSO_LEVEL_TRIGGER:
*val = LSM6DSO_LEVEL_TRIGGER;
break;
+
case LSM6DSO_EDGE_TRIGGER:
*val = LSM6DSO_EDGE_TRIGGER;
break;
+
default:
*val = LSM6DSO_DEN_DISABLE;
break;
}
+
return ret;
}
@@ -6301,17 +7572,21 @@ int32_t lsm6dso_den_mode_get(stmdev_ctx_t *ctx, lsm6dso_den_mode_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of den_lh in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_den_polarity_set(stmdev_ctx_t *ctx, lsm6dso_den_lh_t val)
+int32_t lsm6dso_den_polarity_set(stmdev_ctx_t *ctx,
+ lsm6dso_den_lh_t val)
{
lsm6dso_ctrl9_xl_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.den_lh = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
}
return ret;
@@ -6322,26 +7597,32 @@ int32_t lsm6dso_den_polarity_set(stmdev_ctx_t *ctx, lsm6dso_den_lh_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of den_lh in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_den_polarity_get(stmdev_ctx_t *ctx, lsm6dso_den_lh_t *val)
+int32_t lsm6dso_den_polarity_get(stmdev_ctx_t *ctx,
+ lsm6dso_den_lh_t *val)
{
lsm6dso_ctrl9_xl_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
- switch (reg.den_lh) {
+ switch (reg.den_lh)
+ {
case LSM6DSO_DEN_ACT_LOW:
*val = LSM6DSO_DEN_ACT_LOW;
break;
+
case LSM6DSO_DEN_ACT_HIGH:
*val = LSM6DSO_DEN_ACT_HIGH;
break;
+
default:
*val = LSM6DSO_DEN_ACT_LOW;
break;
}
+
return ret;
}
@@ -6350,17 +7631,21 @@ int32_t lsm6dso_den_polarity_get(stmdev_ctx_t *ctx, lsm6dso_den_lh_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of den_xl_g in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_den_enable_set(stmdev_ctx_t *ctx, lsm6dso_den_xl_g_t val)
+int32_t lsm6dso_den_enable_set(stmdev_ctx_t *ctx,
+ lsm6dso_den_xl_g_t val)
{
lsm6dso_ctrl9_xl_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.den_xl_g = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
}
return ret;
@@ -6371,29 +7656,36 @@ int32_t lsm6dso_den_enable_set(stmdev_ctx_t *ctx, lsm6dso_den_xl_g_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of den_xl_g in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_den_enable_get(stmdev_ctx_t *ctx, lsm6dso_den_xl_g_t *val)
+int32_t lsm6dso_den_enable_get(stmdev_ctx_t *ctx,
+ lsm6dso_den_xl_g_t *val)
{
lsm6dso_ctrl9_xl_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
- switch (reg.den_xl_g) {
+ switch (reg.den_xl_g)
+ {
case LSM6DSO_STAMP_IN_GY_DATA:
*val = LSM6DSO_STAMP_IN_GY_DATA;
break;
+
case LSM6DSO_STAMP_IN_XL_DATA:
*val = LSM6DSO_STAMP_IN_XL_DATA;
break;
+
case LSM6DSO_STAMP_IN_GY_XL_DATA:
*val = LSM6DSO_STAMP_IN_GY_XL_DATA;
break;
+
default:
*val = LSM6DSO_STAMP_IN_GY_DATA;
break;
}
+
return ret;
}
@@ -6402,6 +7694,7 @@ int32_t lsm6dso_den_enable_get(stmdev_ctx_t *ctx, lsm6dso_den_xl_g_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of den_z in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -6409,10 +7702,12 @@ int32_t lsm6dso_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_ctrl9_xl_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.den_z = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
}
return ret;
@@ -6423,6 +7718,7 @@ int32_t lsm6dso_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of den_z in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -6430,7 +7726,7 @@ int32_t lsm6dso_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_ctrl9_xl_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
*val = reg.den_z;
return ret;
@@ -6441,6 +7737,7 @@ int32_t lsm6dso_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of den_y in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -6448,10 +7745,12 @@ int32_t lsm6dso_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_ctrl9_xl_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.den_y = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
}
return ret;
@@ -6462,6 +7761,7 @@ int32_t lsm6dso_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of den_y in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -6469,7 +7769,7 @@ int32_t lsm6dso_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_ctrl9_xl_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
*val = reg.den_y;
return ret;
@@ -6480,6 +7780,7 @@ int32_t lsm6dso_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of den_x in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -6487,10 +7788,12 @@ int32_t lsm6dso_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dso_ctrl9_xl_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.den_x = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
}
return ret;
@@ -6501,6 +7804,7 @@ int32_t lsm6dso_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of den_x in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -6508,7 +7812,7 @@ int32_t lsm6dso_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dso_ctrl9_xl_t reg;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)®, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
*val = reg.den_x;
return ret;
@@ -6524,55 +7828,33 @@ int32_t lsm6dso_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val)
* @brief This section groups all the functions that manage pedometer.
* @{
*
-*/
+ */
/**
* @brief Enable pedometer algorithm.[set]
*
* @param ctx read / write interface definitions
* @param val turn on and configure pedometer
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_pedo_sens_set(stmdev_ctx_t *ctx, lsm6dso_pedo_md_t val)
+int32_t lsm6dso_pedo_sens_set(stmdev_ctx_t *ctx,
+ lsm6dso_pedo_md_t val)
{
- lsm6dso_emb_func_en_a_t emb_func_en_a;
- lsm6dso_emb_func_en_b_t emb_func_en_b;
lsm6dso_pedo_cmd_reg_t pedo_cmd_reg;
int32_t ret;
ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG,
- (uint8_t*)&pedo_cmd_reg);
- if (ret == 0) {
- ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+ (uint8_t *)&pedo_cmd_reg);
+
+ if (ret == 0)
+ {
+ pedo_cmd_reg.fp_rejection_en = ((uint8_t)val & 0x10U) >> 4;
+ pedo_cmd_reg.ad_det_en = ((uint8_t)val & 0x20U) >> 5;
+ ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_CMD_REG,
+ (uint8_t *)&pedo_cmd_reg);
}
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
- }
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
- emb_func_en_a.pedo_en = (uint8_t)val & 0x01U;
- emb_func_en_b.pedo_adv_en = ((uint8_t)val & 0x02U)>>1;
- pedo_cmd_reg.fp_rejection_en = ((uint8_t)val & 0x10U)>>4;
- pedo_cmd_reg.ad_det_en = ((uint8_t)val & 0x20U)>>5;
- }
- if (ret == 0) {
- ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
- }
- if (ret == 0) {
- ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
- }
- if (ret == 0) {
- ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
- }
- if (ret == 0) {
- ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_CMD_REG,
- (uint8_t*)&pedo_cmd_reg);
- }
return ret;
}
@@ -6581,49 +7863,38 @@ int32_t lsm6dso_pedo_sens_set(stmdev_ctx_t *ctx, lsm6dso_pedo_md_t val)
*
* @param ctx read / write interface definitions
* @param val turn on and configure pedometer
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_pedo_sens_get(stmdev_ctx_t *ctx, lsm6dso_pedo_md_t *val)
+int32_t lsm6dso_pedo_sens_get(stmdev_ctx_t *ctx,
+ lsm6dso_pedo_md_t *val)
{
- lsm6dso_emb_func_en_a_t emb_func_en_a;
- lsm6dso_emb_func_en_b_t emb_func_en_b;
lsm6dso_pedo_cmd_reg_t pedo_cmd_reg;
int32_t ret;
ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG,
- (uint8_t*)&pedo_cmd_reg);
- if (ret == 0) {
- ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- }
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
- }
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
- }
- if (ret == 0) {
- ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
- }
- switch ( (pedo_cmd_reg.ad_det_en <<5) | (pedo_cmd_reg.fp_rejection_en << 4) |
- (emb_func_en_b.pedo_adv_en << 1) | emb_func_en_a.pedo_en) {
- case LSM6DSO_PEDO_DISABLE:
- *val = LSM6DSO_PEDO_DISABLE;
- break;
+ (uint8_t *)&pedo_cmd_reg);
+
+ switch ((pedo_cmd_reg.ad_det_en << 5) | (pedo_cmd_reg.fp_rejection_en
+ << 4))
+ {
case LSM6DSO_PEDO_BASE_MODE:
*val = LSM6DSO_PEDO_BASE_MODE;
break;
+
case LSM6DSO_FALSE_STEP_REJ:
*val = LSM6DSO_FALSE_STEP_REJ;
break;
+
case LSM6DSO_FALSE_STEP_REJ_ADV_MODE:
*val = LSM6DSO_FALSE_STEP_REJ_ADV_MODE;
break;
+
default:
- *val = LSM6DSO_PEDO_DISABLE;
+ *val = LSM6DSO_PEDO_BASE_MODE;
break;
}
+
return ret;
}
@@ -6632,6 +7903,7 @@ int32_t lsm6dso_pedo_sens_get(stmdev_ctx_t *ctx, lsm6dso_pedo_md_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of is_step_det in reg EMB_FUNC_STATUS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -6640,10 +7912,14 @@ int32_t lsm6dso_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.is_step_det;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -6656,12 +7932,17 @@ int32_t lsm6dso_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
- ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_DEB_STEPS_CONF, buff);
+
+ ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_DEB_STEPS_CONF,
+ buff);
+
return ret;
}
@@ -6670,12 +7951,16 @@ int32_t lsm6dso_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_DEB_STEPS_CONF, buff);
+
return ret;
}
@@ -6684,20 +7969,25 @@ int32_t lsm6dso_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_pedo_steps_period_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso_pedo_steps_period_set(stmdev_ctx_t *ctx, uint16_t val)
{
+ uint8_t buff[2];
int32_t ret;
- uint8_t index;
- index = 0x00U;
- ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_L, &buff[index]);
- if (ret == 0) {
- index++;
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
+ ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_L,
+ &buff[0]);
+
+ if (ret == 0)
+ {
ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_H,
- &buff[index]);
+ &buff[1]);
}
+
return ret;
}
@@ -6706,20 +7996,26 @@ int32_t lsm6dso_pedo_steps_period_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_pedo_steps_period_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso_pedo_steps_period_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
- uint8_t index;
- index = 0x00U;
- ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_L, &buff[index]);
- if (ret == 0) {
- index++;
+ ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_L,
+ &buff[0]);
+
+ if (ret == 0)
+ {
ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_H,
- &buff[index]);
+ &buff[1]);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
}
+
return ret;
}
@@ -6729,6 +8025,7 @@ int32_t lsm6dso_pedo_steps_period_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param val change the values of carry_count_en in reg PEDO_CMD_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_pedo_int_mode_set(stmdev_ctx_t *ctx,
@@ -6737,12 +8034,16 @@ int32_t lsm6dso_pedo_int_mode_set(stmdev_ctx_t *ctx,
lsm6dso_pedo_cmd_reg_t reg;
int32_t ret;
- ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG, (uint8_t*)®);
- if (ret == 0) {
+ ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG,
+ (uint8_t *)®);
+
+ if (ret == 0)
+ {
reg.carry_count_en = (uint8_t)val;
ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_CMD_REG,
- (uint8_t*)®);
+ (uint8_t *)®);
}
+
return ret;
}
@@ -6752,6 +8053,7 @@ int32_t lsm6dso_pedo_int_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of carry_count_en in reg PEDO_CMD_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_pedo_int_mode_get(stmdev_ctx_t *ctx,
@@ -6760,18 +8062,24 @@ int32_t lsm6dso_pedo_int_mode_get(stmdev_ctx_t *ctx,
lsm6dso_pedo_cmd_reg_t reg;
int32_t ret;
- ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG, (uint8_t*)®);
- switch (reg.carry_count_en) {
+ ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG,
+ (uint8_t *)®);
+
+ switch (reg.carry_count_en)
+ {
case LSM6DSO_EVERY_STEP:
*val = LSM6DSO_EVERY_STEP;
break;
+
case LSM6DSO_COUNT_OVERFLOW:
*val = LSM6DSO_COUNT_OVERFLOW;
break;
+
default:
*val = LSM6DSO_EVERY_STEP;
break;
}
+
return ret;
}
@@ -6786,74 +8094,31 @@ int32_t lsm6dso_pedo_int_mode_get(stmdev_ctx_t *ctx,
* significant motion detection.
* @{
*
-*/
-
-/**
- * @brief Enable significant motion detection function.[set]
- *
- * @param ctx read / write interface definitions
- * @param val change the values of sign_motion_en in reg EMB_FUNC_EN_A
- *
- */
-int32_t lsm6dso_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val)
-{
- lsm6dso_emb_func_en_a_t reg;
- int32_t ret;
-
- ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, (uint8_t*)®, 1);
- }
- if (ret == 0) {
- reg.sign_motion_en = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, (uint8_t*)®, 1);
- }
- if (ret == 0) {
- ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
- }
- return ret;
-}
-
-/**
- * @brief Enable significant motion detection function.[get]
- *
- * @param ctx read / write interface definitions
- * @param val change the values of sign_motion_en in reg EMB_FUNC_EN_A
- *
*/
-int32_t lsm6dso_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
-{
- lsm6dso_emb_func_en_a_t reg;
- int32_t ret;
-
- ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, (uint8_t*)®, 1);
- }
- if (ret == 0) {
- *val = reg.sign_motion_en;
- ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
- }
- return ret;
-}
/**
* @brief Interrupt status bit for significant motion detection.[get]
*
* @param ctx read / write interface definitions
* @param val change the values of is_sigmot in reg EMB_FUNC_STATUS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_motion_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso_motion_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso_emb_func_status_t reg;
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.is_sigmot;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -6872,75 +8137,31 @@ int32_t lsm6dso_motion_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* event detection.
* @{
*
-*/
-
-/**
- * @brief Enable tilt calculation.[set]
- *
- * @param ctx read / write interface definitions
- * @param val change the values of tilt_en in reg EMB_FUNC_EN_A
- *
- */
-int32_t lsm6dso_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val)
-{
- lsm6dso_emb_func_en_a_t reg;
- int32_t ret;
-
- ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, (uint8_t*)®, 1);
- }
- if (ret == 0) {
- reg.tilt_en = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, (uint8_t*)®, 1);
- }
- if (ret == 0) {
- ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
- }
- return ret;
-}
-
-/**
- * @brief Enable tilt calculation.[get]
- *
- * @param ctx read / write interface definitions
- * @param val change the values of tilt_en in reg EMB_FUNC_EN_A
- *
*/
-int32_t lsm6dso_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
-{
- lsm6dso_emb_func_en_a_t reg;
- int32_t ret;
-
- ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, (uint8_t*)®, 1);
- }
- if (ret == 0) {
- *val = reg.tilt_en;
- ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
- }
-
- return ret;
-}
/**
* @brief Interrupt status bit for tilt detection.[get]
*
* @param ctx read / write interface definitions
* @param val change the values of is_tilt in reg EMB_FUNC_STATUS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso_tilt_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso_emb_func_status_t reg;
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.is_tilt;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -6959,27 +8180,30 @@ int32_t lsm6dso_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* magnetometer sensor.
* @{
*
-*/
+ */
/**
* @brief External magnetometer sensitivity value register.[set]
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_mag_sensitivity_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val)
{
+ uint8_t buff[2];
int32_t ret;
- uint8_t index;
- index = 0x00U;
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SENSITIVITY_L,
- &buff[index]);
- if (ret == 0) {
- index++;
+ &buff[0]);
+
+ if (ret == 0)
+ {
ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SENSITIVITY_H,
- &buff[index]);
+ &buff[1]);
}
return ret;
@@ -6990,20 +8214,23 @@ int32_t lsm6dso_mag_sensitivity_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_mag_sensitivity_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
- uint8_t index;
- index = 0x00U;
ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SENSITIVITY_L,
- &buff[index]);
- if (ret == 0) {
- index++;
+ &buff[0]);
+
+ if (ret == 0)
+ {
ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SENSITIVITY_H,
- &buff[index]);
+ &buff[1]);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
}
return ret;
@@ -7014,35 +8241,45 @@ int32_t lsm6dso_mag_sensitivity_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_mag_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
- uint8_t index;
- index = 0x00U;
- ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFX_L, &buff[index]);
- if (ret == 0) {
- index++;
- ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFX_H, &buff[index]);
+ buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
+ buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
+ buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
+ buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
+ buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
+ buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
+ ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFX_L, &buff[0]);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFX_H, &buff[1]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFY_L, &buff[index]);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFY_L, &buff[2]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFY_H, &buff[index]);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFY_H, &buff[3]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFZ_L, &buff[index]);
+ if (ret == 0)
+ {
+ ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFZ_L, &buff[4]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFZ_H, &buff[index]);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFZ_H, &buff[5]);
}
return ret;
@@ -7053,37 +8290,47 @@ int32_t lsm6dso_mag_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_mag_offset_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
- uint8_t index;
- index = 0x00U;
- ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFX_L, &buff[index]);
- if (ret == 0) {
- index++;
- ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFX_H, &buff[index]);
+ ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFX_L, &buff[0]);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFX_H, &buff[1]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFY_L, &buff[index]);
+ if (ret == 0)
+ {
+ ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFY_L, &buff[2]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFY_H, &buff[index]);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFY_H, &buff[3]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFZ_L, &buff[index]);
+ if (ret == 0)
+ {
+ ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFZ_L, &buff[4]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFZ_H, &buff[index]);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFZ_H, &buff[5]);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
}
+
return ret;
}
@@ -7098,63 +8345,106 @@ int32_t lsm6dso_mag_offset_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso_mag_soft_iron_set(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[12];
int32_t ret;
- uint8_t index;
+ uint8_t index;
+ buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
+ buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
+ buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
+ buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
+ buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
+ buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
+ buff[7] = (uint8_t)((uint16_t)val[3] / 256U);
+ buff[6] = (uint8_t)((uint16_t)val[3] - (buff[7] * 256U));
+ buff[9] = (uint8_t)((uint16_t)val[4] / 256U);
+ buff[8] = (uint8_t)((uint16_t)val[4] - (buff[9] * 256U));
+ buff[11] = (uint8_t)((uint16_t)val[5] / 256U);
+ buff[10] = (uint8_t)((uint16_t)val[5] - (buff[11] * 256U));
index = 0x00U;
- ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XX_L, &buff[index]);
- if (ret == 0) {
+ ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XX_L,
+ &buff[index]);
+
+ if (ret == 0)
+ {
index++;
- ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XX_H, &buff[index]);
+ ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XX_H,
+ &buff[index]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XY_L, &buff[index]);
- }
- if (ret == 0) {
+ if (ret == 0)
+ {
index++;
- ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XY_H, &buff[index]);
+ ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XY_L,
+ &buff[index]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XZ_L, &buff[index]);
- }
- if (ret == 0) {
+ if (ret == 0)
+ {
index++;
- ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XZ_H, &buff[index]);
+ ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XY_H,
+ &buff[index]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YY_L, &buff[index]);
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XZ_L,
+ &buff[index]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
index++;
- ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YY_H, &buff[index]);
+ ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XZ_H,
+ &buff[index]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
index++;
+ ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YY_L,
+ &buff[index]);
+ }
- ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YZ_L, &buff[index]);
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YY_H,
+ &buff[index]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
index++;
- ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YZ_H, &buff[index]);
+ ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YZ_L,
+ &buff[index]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
index++;
+ ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YZ_H,
+ &buff[index]);
+ }
- ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_ZZ_L, &buff[index]);
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_ZZ_L,
+ &buff[index]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
index++;
- ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_ZZ_H, &buff[index]);
+ ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_ZZ_H,
+ &buff[index]);
}
return ret;
@@ -7172,65 +8462,97 @@ int32_t lsm6dso_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso_mag_soft_iron_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[12];
int32_t ret;
- uint8_t index;
+ uint8_t index;
index = 0x00U;
ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XX_L, &buff[index]);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
index++;
ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XX_H, &buff[index]);
}
- if (ret == 0) {
- index++;
+ if (ret == 0)
+ {
+ index++;
ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XY_L, &buff[index]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
index++;
ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XY_H, &buff[index]);
}
- if (ret == 0) {
- index++;
+ if (ret == 0)
+ {
+ index++;
ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XZ_L, &buff[index]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
index++;
ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XZ_H, &buff[index]);
}
- if (ret == 0) {
- index++;
+ if (ret == 0)
+ {
+ index++;
ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YY_L, &buff[index]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
index++;
ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YY_H, &buff[index]);
}
- if (ret == 0) {
- index++;
+ if (ret == 0)
+ {
+ index++;
ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YZ_L, &buff[index]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
index++;
ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YZ_H, &buff[index]);
}
- if (ret == 0) {
- index++;
+ if (ret == 0)
+ {
+ index++;
ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_ZZ_L, &buff[index]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
index++;
ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_ZZ_H, &buff[index]);
}
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+ val[3] = (int16_t)buff[7];
+ val[3] = (val[3] * 256) + (int16_t)buff[6];
+ val[4] = (int16_t)buff[9];
+ val[4] = (val[4] * 256) + (int16_t)buff[8];
+ val[5] = (int16_t)buff[11];
+ val[5] = (val[5] * 256) + (int16_t)buff[10];
+
return ret;
}
@@ -7242,17 +8564,23 @@ int32_t lsm6dso_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param val change the values of mag_z_axis in reg MAG_CFG_A
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_mag_z_orient_set(stmdev_ctx_t *ctx, lsm6dso_mag_z_axis_t val)
+int32_t lsm6dso_mag_z_orient_set(stmdev_ctx_t *ctx,
+ lsm6dso_mag_z_axis_t val)
{
lsm6dso_mag_cfg_a_t reg;
int32_t ret;
- ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t*)®);
- if (ret == 0) {
+ ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A,
+ (uint8_t *)®);
+
+ if (ret == 0)
+ {
reg.mag_z_axis = (uint8_t) val;
- ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t*)®);
+ ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_CFG_A,
+ (uint8_t *)®);
}
return ret;
@@ -7266,6 +8594,7 @@ int32_t lsm6dso_mag_z_orient_set(stmdev_ctx_t *ctx, lsm6dso_mag_z_axis_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of mag_z_axis in reg MAG_CFG_A
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_mag_z_orient_get(stmdev_ctx_t *ctx,
@@ -7273,30 +8602,41 @@ int32_t lsm6dso_mag_z_orient_get(stmdev_ctx_t *ctx,
{
lsm6dso_mag_cfg_a_t reg;
int32_t ret;
- ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t*)®);
- switch (reg.mag_z_axis) {
+
+ ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A,
+ (uint8_t *)®);
+
+ switch (reg.mag_z_axis)
+ {
case LSM6DSO_Z_EQ_Y:
*val = LSM6DSO_Z_EQ_Y;
break;
+
case LSM6DSO_Z_EQ_MIN_Y:
*val = LSM6DSO_Z_EQ_MIN_Y;
break;
+
case LSM6DSO_Z_EQ_X:
*val = LSM6DSO_Z_EQ_X;
break;
+
case LSM6DSO_Z_EQ_MIN_X:
*val = LSM6DSO_Z_EQ_MIN_X;
break;
+
case LSM6DSO_Z_EQ_MIN_Z:
*val = LSM6DSO_Z_EQ_MIN_Z;
break;
+
case LSM6DSO_Z_EQ_Z:
*val = LSM6DSO_Z_EQ_Z;
break;
+
default:
*val = LSM6DSO_Z_EQ_Y;
break;
}
+
return ret;
}
@@ -7308,6 +8648,7 @@ int32_t lsm6dso_mag_z_orient_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of mag_y_axis in reg MAG_CFG_A
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_mag_y_orient_set(stmdev_ctx_t *ctx,
@@ -7316,11 +8657,16 @@ int32_t lsm6dso_mag_y_orient_set(stmdev_ctx_t *ctx,
lsm6dso_mag_cfg_a_t reg;
int32_t ret;
- ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t*)®);
- if (ret == 0) {
+ ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A,
+ (uint8_t *)®);
+
+ if (ret == 0)
+ {
reg.mag_y_axis = (uint8_t)val;
- ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_CFG_A,(uint8_t*) ®);
+ ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_CFG_A,
+ (uint8_t *) ®);
}
+
return ret;
}
@@ -7332,6 +8678,7 @@ int32_t lsm6dso_mag_y_orient_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of mag_y_axis in reg MAG_CFG_A
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_mag_y_orient_get(stmdev_ctx_t *ctx,
@@ -7340,30 +8687,40 @@ int32_t lsm6dso_mag_y_orient_get(stmdev_ctx_t *ctx,
lsm6dso_mag_cfg_a_t reg;
int32_t ret;
- ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t*)®);
- switch (reg.mag_y_axis) {
+ ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A,
+ (uint8_t *)®);
+
+ switch (reg.mag_y_axis)
+ {
case LSM6DSO_Y_EQ_Y:
*val = LSM6DSO_Y_EQ_Y;
break;
+
case LSM6DSO_Y_EQ_MIN_Y:
*val = LSM6DSO_Y_EQ_MIN_Y;
break;
+
case LSM6DSO_Y_EQ_X:
*val = LSM6DSO_Y_EQ_X;
break;
+
case LSM6DSO_Y_EQ_MIN_X:
*val = LSM6DSO_Y_EQ_MIN_X;
break;
+
case LSM6DSO_Y_EQ_MIN_Z:
*val = LSM6DSO_Y_EQ_MIN_Z;
break;
+
case LSM6DSO_Y_EQ_Z:
*val = LSM6DSO_Y_EQ_Z;
break;
+
default:
*val = LSM6DSO_Y_EQ_Y;
break;
}
+
return ret;
}
@@ -7375,6 +8732,7 @@ int32_t lsm6dso_mag_y_orient_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of mag_x_axis in reg MAG_CFG_B
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_mag_x_orient_set(stmdev_ctx_t *ctx,
@@ -7383,11 +8741,16 @@ int32_t lsm6dso_mag_x_orient_set(stmdev_ctx_t *ctx,
lsm6dso_mag_cfg_b_t reg;
int32_t ret;
- ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_B, (uint8_t*)®);
- if (ret == 0) {
+ ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_B,
+ (uint8_t *)®);
+
+ if (ret == 0)
+ {
reg.mag_x_axis = (uint8_t)val;
- ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_CFG_B, (uint8_t*)®);
+ ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_CFG_B,
+ (uint8_t *)®);
}
+
return ret;
}
@@ -7399,6 +8762,7 @@ int32_t lsm6dso_mag_x_orient_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of mag_x_axis in reg MAG_CFG_B
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_mag_x_orient_get(stmdev_ctx_t *ctx,
@@ -7407,30 +8771,40 @@ int32_t lsm6dso_mag_x_orient_get(stmdev_ctx_t *ctx,
lsm6dso_mag_cfg_b_t reg;
int32_t ret;
- ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_B, (uint8_t*)®);
- switch (reg.mag_x_axis) {
+ ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_B,
+ (uint8_t *)®);
+
+ switch (reg.mag_x_axis)
+ {
case LSM6DSO_X_EQ_Y:
*val = LSM6DSO_X_EQ_Y;
break;
+
case LSM6DSO_X_EQ_MIN_Y:
*val = LSM6DSO_X_EQ_MIN_Y;
break;
+
case LSM6DSO_X_EQ_X:
*val = LSM6DSO_X_EQ_X;
break;
+
case LSM6DSO_X_EQ_MIN_X:
*val = LSM6DSO_X_EQ_MIN_X;
break;
+
case LSM6DSO_X_EQ_MIN_Z:
*val = LSM6DSO_X_EQ_MIN_Z;
break;
+
case LSM6DSO_X_EQ_Z:
*val = LSM6DSO_X_EQ_Z;
break;
+
default:
*val = LSM6DSO_X_EQ_Y;
break;
}
+
return ret;
}
@@ -7445,7 +8819,7 @@ int32_t lsm6dso_mag_x_orient_get(stmdev_ctx_t *ctx,
* state_machine.
* @{
*
-*/
+ */
/**
* @brief Interrupt status bit for FSM long counter
@@ -7453,71 +8827,88 @@ int32_t lsm6dso_mag_x_orient_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of is_fsm_lc in reg EMB_FUNC_STATUS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dso_emb_func_status_t reg;
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.is_fsm_lc;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
+
return ret;
}
/**
- * @brief Final State Machine global enable.[set]
+ * @brief Final State Machine enable.[set]
*
* @param ctx read / write interface definitions
- * @param val change the values of fsm_en in reg EMB_FUNC_EN_B
+ * @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dso_fsm_enable_set(stmdev_ctx_t *ctx,
+ lsm6dso_emb_fsm_enable_t *val)
{
int32_t ret;
- lsm6dso_emb_func_en_b_t reg;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_ENABLE_A,
+ (uint8_t *)&val->fsm_enable_a, 1);
}
- if (ret == 0) {
- reg.fsm_en = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_ENABLE_B,
+ (uint8_t *)&val->fsm_enable_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
+
return ret;
}
/**
- * @brief Final State Machine global enable.[get]
+ * @brief Final State Machine enable.[get]
*
* @param ctx read / write interface definitions
- * @param uint8_t *: return the values of fsm_en in reg EMB_FUNC_EN_B
+ * @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso_fsm_enable_get(stmdev_ctx_t *ctx,
+ lsm6dso_emb_fsm_enable_t *val)
{
int32_t ret;
- lsm6dso_emb_func_en_b_t reg;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, (uint8_t*)®, 1);
- }
- if (ret == 0) {
- *val = reg.fsm_en;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_ENABLE_A, (uint8_t *) val, 2);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -7525,104 +8916,30 @@ int32_t lsm6dso_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val)
}
/**
- * @brief Final State Machine enable.[set]
- *
- * @param ctx read / write interface definitions
- * @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
- *
- */
-int32_t lsm6dso_fsm_enable_set(stmdev_ctx_t *ctx,
- lsm6dso_emb_fsm_enable_t *val)
-{
- int32_t ret;
- lsm6dso_emb_func_en_b_t reg;
-
- ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_ENABLE_A,
- (uint8_t*)&val->fsm_enable_a, 1);
- }
- if (ret == 0) {
- ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_ENABLE_B,
- (uint8_t*)&val->fsm_enable_b, 1);
- }
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, (uint8_t*)®, 1);
- }
- if (ret == 0) {
- if ( (val->fsm_enable_a.fsm1_en |
- val->fsm_enable_a.fsm2_en |
- val->fsm_enable_a.fsm3_en |
- val->fsm_enable_a.fsm4_en |
- val->fsm_enable_a.fsm5_en |
- val->fsm_enable_a.fsm6_en |
- val->fsm_enable_a.fsm7_en |
- val->fsm_enable_a.fsm8_en |
- val->fsm_enable_b.fsm9_en |
- val->fsm_enable_b.fsm10_en |
- val->fsm_enable_b.fsm11_en |
- val->fsm_enable_b.fsm12_en |
- val->fsm_enable_b.fsm13_en |
- val->fsm_enable_b.fsm14_en |
- val->fsm_enable_b.fsm15_en |
- val->fsm_enable_b.fsm16_en )
- != PROPERTY_DISABLE)
- {
- reg.fsm_en = PROPERTY_ENABLE;
- }
- else
- {
- reg.fsm_en = PROPERTY_DISABLE;
- }
-
- ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, (uint8_t*)®, 1);
- }
- if (ret == 0) {
- ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
- }
-
- return ret;
-}
-
-/**
- * @brief Final State Machine enable.[get]
- *
- * @param ctx read / write interface definitions
- * @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
- *
- */
-int32_t lsm6dso_fsm_enable_get(stmdev_ctx_t *ctx,
- lsm6dso_emb_fsm_enable_t *val)
-{
- int32_t ret;
-
- ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_ENABLE_A, (uint8_t*) val, 2);
- }
- if (ret == 0) {
- ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
- }
- return ret;
-}
-
-/**
- * @brief FSM long counter status register. Long counter value is an
- * unsigned integer value (16-bit format).[set]
+ * @brief FSM long counter status register. Long counter value is an
+ * unsigned integer value (16-bit format).[set]
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_long_cnt_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val)
{
+ uint8_t buff[2];
int32_t ret;
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_L, buff, 2);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -7635,18 +8952,26 @@ int32_t lsm6dso_long_cnt_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_long_cnt_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dso_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_L, buff, 2);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
}
return ret;
@@ -7658,26 +8983,35 @@ int32_t lsm6dso_long_cnt_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @param ctx read / write interface definitions
* @param val change the values of fsm_lc_clr in
* reg FSM_LONG_COUNTER_CLEAR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_long_clr_set(stmdev_ctx_t *ctx, lsm6dso_fsm_lc_clr_t val)
+int32_t lsm6dso_long_clr_set(stmdev_ctx_t *ctx,
+ lsm6dso_fsm_lc_clr_t val)
{
lsm6dso_fsm_long_counter_clear_t reg;
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_CLEAR,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg. fsm_lc_clr = (uint8_t)val;
ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_CLEAR,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
+
return ret;
}
@@ -7687,36 +9021,47 @@ int32_t lsm6dso_long_clr_set(stmdev_ctx_t *ctx, lsm6dso_fsm_lc_clr_t val)
* @param ctx read / write interface definitions
* @param val Get the values of fsm_lc_clr in
* reg FSM_LONG_COUNTER_CLEAR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_long_clr_get(stmdev_ctx_t *ctx, lsm6dso_fsm_lc_clr_t *val)
+int32_t lsm6dso_long_clr_get(stmdev_ctx_t *ctx,
+ lsm6dso_fsm_lc_clr_t *val)
{
lsm6dso_fsm_long_counter_clear_t reg;
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_CLEAR,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
- switch (reg.fsm_lc_clr) {
+
+ if (ret == 0)
+ {
+ switch (reg.fsm_lc_clr)
+ {
case LSM6DSO_LC_NORMAL:
*val = LSM6DSO_LC_NORMAL;
break;
+
case LSM6DSO_LC_CLEAR:
*val = LSM6DSO_LC_CLEAR;
break;
+
case LSM6DSO_LC_CLEAR_DONE:
*val = LSM6DSO_LC_CLEAR_DONE;
break;
+
default:
*val = LSM6DSO_LC_NORMAL;
break;
}
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -7728,6 +9073,7 @@ int32_t lsm6dso_long_clr_get(stmdev_ctx_t *ctx, lsm6dso_fsm_lc_clr_t *val)
*
* @param ctx read / write interface definitions
* @param val struct of registers from FSM_OUTS1 to FSM_OUTS16
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_fsm_out_get(stmdev_ctx_t *ctx, lsm6dso_fsm_out_t *val)
@@ -7735,10 +9081,14 @@ int32_t lsm6dso_fsm_out_get(stmdev_ctx_t *ctx, lsm6dso_fsm_out_t *val)
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_OUTS1, (uint8_t*)val, 16);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_OUTS1, (uint8_t *)val, 16);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -7750,28 +9100,37 @@ int32_t lsm6dso_fsm_out_get(stmdev_ctx_t *ctx, lsm6dso_fsm_out_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_fsm_data_rate_set(stmdev_ctx_t *ctx, lsm6dso_fsm_odr_t val)
+int32_t lsm6dso_fsm_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dso_fsm_odr_t val)
{
lsm6dso_emb_func_odr_cfg_b_t reg;
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.not_used_01 = 3; /* set default values */
reg.not_used_02 = 2; /* set default values */
reg.fsm_odr = (uint8_t)val;
ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
+
return ret;
}
@@ -7780,36 +9139,48 @@ int32_t lsm6dso_fsm_data_rate_set(stmdev_ctx_t *ctx, lsm6dso_fsm_odr_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_fsm_data_rate_get(stmdev_ctx_t *ctx, lsm6dso_fsm_odr_t *val)
+int32_t lsm6dso_fsm_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dso_fsm_odr_t *val)
{
lsm6dso_emb_func_odr_cfg_b_t reg;
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
- switch (reg.fsm_odr) {
+
+ if (ret == 0)
+ {
+ switch (reg.fsm_odr)
+ {
case LSM6DSO_ODR_FSM_12Hz5:
*val = LSM6DSO_ODR_FSM_12Hz5;
break;
+
case LSM6DSO_ODR_FSM_26Hz:
*val = LSM6DSO_ODR_FSM_26Hz;
break;
+
case LSM6DSO_ODR_FSM_52Hz:
*val = LSM6DSO_ODR_FSM_52Hz;
break;
+
case LSM6DSO_ODR_FSM_104Hz:
*val = LSM6DSO_ODR_FSM_104Hz;
break;
+
default:
*val = LSM6DSO_ODR_FSM_12Hz5;
break;
}
+
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -7821,6 +9192,7 @@ int32_t lsm6dso_fsm_data_rate_get(stmdev_ctx_t *ctx, lsm6dso_fsm_odr_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of fsm_init in reg FSM_INIT
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -7829,14 +9201,20 @@ int32_t lsm6dso_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.fsm_init = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -7848,6 +9226,7 @@ int32_t lsm6dso_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of fsm_init in reg FSM_INIT
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -7856,13 +9235,18 @@ int32_t lsm6dso_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.fsm_init;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
+
return ret;
}
@@ -7874,20 +9258,24 @@ int32_t lsm6dso_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val the value of long counter
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint16_t val)
+int32_t lsm6dso_long_cnt_int_value_set(stmdev_ctx_t *ctx,
+ uint16_t val)
{
+ uint8_t buff[2];
int32_t ret;
- uint8_t add_l;
- uint8_t add_h;
- add_h = (uint8_t)( ( val & 0xFF00U ) >> 8 );
- add_l = (uint8_t)( val & 0x00FFU );
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
+ ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_L,
+ &buff[0]);
- ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_L, &add_l);
- if (ret == 0) {
- ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_H, &add_h);
+ if (ret == 0)
+ {
+ ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_H,
+ &buff[1]);
}
return ret;
@@ -7901,20 +9289,24 @@ int32_t lsm6dso_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint16_t val)
*
* @param ctx read / write interface definitions
* @param val buffer that stores the value of long counter
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint16_t *val)
+int32_t lsm6dso_long_cnt_int_value_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
- uint8_t add_l;
- uint8_t add_h;
- ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_L, &add_l);
- if (ret == 0) {
- ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_H, &add_h);
- *val = add_h;
- *val = *val << 8;
- *val += add_l;
+ ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_L,
+ &buff[0]);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_H,
+ &buff[1]);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
}
return ret;
@@ -7925,9 +9317,11 @@ int32_t lsm6dso_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint16_t *val)
*
* @param ctx read / write interface definitions
* @param val value to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dso_fsm_number_of_programs_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
int32_t ret;
@@ -7941,9 +9335,11 @@ int32_t lsm6dso_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val buffer that stores data read.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dso_fsm_number_of_programs_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
int32_t ret;
@@ -7958,21 +9354,25 @@ int32_t lsm6dso_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val the value of start address
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val)
{
+ uint8_t buff[2];
int32_t ret;
- uint8_t add_l;
- uint8_t add_h;
- add_h = (uint8_t)( ( val & 0xFF00U ) >> 8 );
- add_l = (uint8_t)( val & 0x00FFU );
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
+ ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_START_ADD_L,
+ &buff[0]);
- ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_START_ADD_L, &add_l);
- if (ret == 0) {
- ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_START_ADD_H, &add_h);
+ if (ret == 0)
+ {
+ ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_START_ADD_H,
+ &buff[1]);
}
+
return ret;
}
@@ -7982,21 +9382,24 @@ int32_t lsm6dso_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val)
*
* @param ctx read / write interface definitions
* @param val buffer the value of start address.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val)
+int32_t lsm6dso_fsm_start_address_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
- uint8_t add_l;
- uint8_t add_h;
- ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_START_ADD_L, &add_l);
- if (ret == 0) {
- ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_START_ADD_H, &add_h);
- *val = add_h;
- *val = *val << 8;
- *val += add_l;
+ ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_START_ADD_L, &buff[0]);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_START_ADD_H, &buff[1]);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
}
+
return ret;
}
@@ -8011,7 +9414,7 @@ int32_t lsm6dso_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val)
* sensor hub.
* @{
*
-*/
+ */
/**
* @brief Sensor hub output registers.[get]
@@ -8019,6 +9422,7 @@ int32_t lsm6dso_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val)
* @param ctx read / write interface definitions
* @param val values read from registers SENSOR_HUB_1 to SENSOR_HUB_18
* @param len number of consecutive register to read (max 18)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_sh_read_data_raw_get(stmdev_ctx_t *ctx, uint8_t *val,
@@ -8027,10 +9431,15 @@ int32_t lsm6dso_sh_read_data_raw_get(stmdev_ctx_t *ctx, uint8_t *val,
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_SENSOR_HUB_1, (uint8_t*) val, len);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_SENSOR_HUB_1, (uint8_t *) val,
+ len);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -8042,6 +9451,7 @@ int32_t lsm6dso_sh_read_data_raw_get(stmdev_ctx_t *ctx, uint8_t *val,
*
* @param ctx read / write interface definitions
* @param val change the values of aux_sens_on in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_sh_slave_connected_set(stmdev_ctx_t *ctx,
@@ -8051,16 +9461,23 @@ int32_t lsm6dso_sh_slave_connected_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.aux_sens_on = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
+
return ret;
}
@@ -8069,6 +9486,7 @@ int32_t lsm6dso_sh_slave_connected_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of aux_sens_on in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_sh_slave_connected_get(stmdev_ctx_t *ctx,
@@ -8078,27 +9496,37 @@ int32_t lsm6dso_sh_slave_connected_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
- switch (reg.aux_sens_on) {
+
+ if (ret == 0)
+ {
+ switch (reg.aux_sens_on)
+ {
case LSM6DSO_SLV_0:
*val = LSM6DSO_SLV_0;
break;
+
case LSM6DSO_SLV_0_1:
*val = LSM6DSO_SLV_0_1;
break;
+
case LSM6DSO_SLV_0_1_2:
*val = LSM6DSO_SLV_0_1_2;
break;
+
case LSM6DSO_SLV_0_1_2_3:
*val = LSM6DSO_SLV_0_1_2_3;
break;
+
default:
*val = LSM6DSO_SLV_0;
break;
}
+
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -8110,6 +9538,7 @@ int32_t lsm6dso_sh_slave_connected_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of master_on in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -8118,16 +9547,23 @@ int32_t lsm6dso_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.master_on = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
+
return ret;
}
@@ -8136,6 +9572,7 @@ int32_t lsm6dso_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of master_on in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -8144,10 +9581,14 @@ int32_t lsm6dso_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.master_on;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -8160,22 +9601,30 @@ int32_t lsm6dso_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of shub_pu_en in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_sh_pin_mode_set(stmdev_ctx_t *ctx, lsm6dso_shub_pu_en_t val)
+int32_t lsm6dso_sh_pin_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso_shub_pu_en_t val)
{
lsm6dso_master_config_t reg;
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.shub_pu_en = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -8187,6 +9636,7 @@ int32_t lsm6dso_sh_pin_mode_set(stmdev_ctx_t *ctx, lsm6dso_shub_pu_en_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of shub_pu_en in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_sh_pin_mode_get(stmdev_ctx_t *ctx,
@@ -8196,21 +9646,29 @@ int32_t lsm6dso_sh_pin_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
- switch (reg.shub_pu_en) {
+
+ if (ret == 0)
+ {
+ switch (reg.shub_pu_en)
+ {
case LSM6DSO_EXT_PULL_UP:
*val = LSM6DSO_EXT_PULL_UP;
break;
+
case LSM6DSO_INTERNAL_PULL_UP:
*val = LSM6DSO_INTERNAL_PULL_UP;
break;
+
default:
*val = LSM6DSO_EXT_PULL_UP;
break;
}
+
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -8223,6 +9681,7 @@ int32_t lsm6dso_sh_pin_mode_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of pass_through_mode in
* reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -8231,14 +9690,20 @@ int32_t lsm6dso_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.pass_through_mode = val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -8251,6 +9716,7 @@ int32_t lsm6dso_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
* @param ctx read / write interface definitions
* @param val change the values of pass_through_mode in
* reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -8259,10 +9725,14 @@ int32_t lsm6dso_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.pass_through_mode;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -8275,6 +9745,7 @@ int32_t lsm6dso_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of start_config in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_sh_syncro_mode_set(stmdev_ctx_t *ctx,
@@ -8284,14 +9755,20 @@ int32_t lsm6dso_sh_syncro_mode_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.start_config = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -8303,6 +9780,7 @@ int32_t lsm6dso_sh_syncro_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of start_config in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_sh_syncro_mode_get(stmdev_ctx_t *ctx,
@@ -8312,23 +9790,32 @@ int32_t lsm6dso_sh_syncro_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
- switch (reg.start_config) {
+
+ if (ret == 0)
+ {
+ switch (reg.start_config)
+ {
case LSM6DSO_EXT_ON_INT2_PIN:
*val = LSM6DSO_EXT_ON_INT2_PIN;
break;
+
case LSM6DSO_XL_GY_DRDY:
*val = LSM6DSO_XL_GY_DRDY;
break;
+
default:
*val = LSM6DSO_EXT_ON_INT2_PIN;
break;
}
+
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
+
return ret;
}
@@ -8338,6 +9825,7 @@ int32_t lsm6dso_sh_syncro_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of write_once in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_sh_write_mode_set(stmdev_ctx_t *ctx,
@@ -8347,14 +9835,20 @@ int32_t lsm6dso_sh_write_mode_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.write_once = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -8367,6 +9861,7 @@ int32_t lsm6dso_sh_write_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of write_once in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_sh_write_mode_get(stmdev_ctx_t *ctx,
@@ -8376,21 +9871,29 @@ int32_t lsm6dso_sh_write_mode_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
- switch (reg.write_once) {
+
+ if (ret == 0)
+ {
+ switch (reg.write_once)
+ {
case LSM6DSO_EACH_SH_CYCLE:
*val = LSM6DSO_EACH_SH_CYCLE;
break;
+
case LSM6DSO_ONLY_FIRST_CYCLE:
*val = LSM6DSO_ONLY_FIRST_CYCLE;
break;
+
default:
*val = LSM6DSO_EACH_SH_CYCLE;
break;
}
+
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -8401,6 +9904,7 @@ int32_t lsm6dso_sh_write_mode_get(stmdev_ctx_t *ctx,
* @brief Reset Master logic and output registers.[set]
*
* @param ctx read / write interface definitions
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_sh_reset_set(stmdev_ctx_t *ctx)
@@ -8409,18 +9913,26 @@ int32_t lsm6dso_sh_reset_set(stmdev_ctx_t *ctx)
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.rst_master_regs = PROPERTY_ENABLE;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.rst_master_regs = PROPERTY_DISABLE;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -8432,6 +9944,7 @@ int32_t lsm6dso_sh_reset_set(stmdev_ctx_t *ctx)
*
* @param ctx read / write interface definitions
* @param val change the values of rst_master_regs in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -8440,13 +9953,18 @@ int32_t lsm6dso_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.rst_master_regs;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
+
return ret;
}
@@ -8455,22 +9973,30 @@ int32_t lsm6dso_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of shub_odr in reg slv1_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_sh_data_rate_set(stmdev_ctx_t *ctx, lsm6dso_shub_odr_t val)
+int32_t lsm6dso_sh_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dso_shub_odr_t val)
{
lsm6dso_slv0_config_t reg;
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.shub_odr = (uint8_t)val;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -8482,6 +10008,7 @@ int32_t lsm6dso_sh_data_rate_set(stmdev_ctx_t *ctx, lsm6dso_shub_odr_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of shub_odr in reg slv1_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_sh_data_rate_get(stmdev_ctx_t *ctx,
@@ -8491,27 +10018,37 @@ int32_t lsm6dso_sh_data_rate_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
- switch (reg.shub_odr) {
+
+ if (ret == 0)
+ {
+ switch (reg.shub_odr)
+ {
case LSM6DSO_SH_ODR_104Hz:
*val = LSM6DSO_SH_ODR_104Hz;
break;
+
case LSM6DSO_SH_ODR_52Hz:
*val = LSM6DSO_SH_ODR_52Hz;
break;
+
case LSM6DSO_SH_ODR_26Hz:
*val = LSM6DSO_SH_ODR_26Hz;
break;
+
case LSM6DSO_SH_ODR_13Hz:
*val = LSM6DSO_SH_ODR_13Hz;
break;
+
default:
*val = LSM6DSO_SH_ODR_104Hz;
break;
}
+
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -8526,30 +10063,41 @@ int32_t lsm6dso_sh_data_rate_get(stmdev_ctx_t *ctx,
* - uint8_t slv1_add; 8 bit i2c device address
* - uint8_t slv1_subadd; 8 bit register device address
* - uint8_t slv1_data; 8 bit data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_sh_cfg_write(stmdev_ctx_t *ctx, lsm6dso_sh_cfg_write_t *val)
+int32_t lsm6dso_sh_cfg_write(stmdev_ctx_t *ctx,
+ lsm6dso_sh_cfg_write_t *val)
{
lsm6dso_slv0_add_t reg;
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.slave0 = val->slv0_add;
reg.rw_0 = 0;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_ADD, (uint8_t*)®, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_ADD, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_SUBADD,
- &(val->slv0_subadd), 1);
+ &(val->slv0_subadd), 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_write_reg(ctx, LSM6DSO_DATAWRITE_SLV0,
- &(val->slv0_data), 1);
+ &(val->slv0_data), 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
+
return ret;
}
@@ -8561,6 +10109,7 @@ int32_t lsm6dso_sh_cfg_write(stmdev_ctx_t *ctx, lsm6dso_sh_cfg_write_t *val)
* - uint8_t slv1_add; 8 bit i2c device address
* - uint8_t slv1_subadd; 8 bit register device address
* - uint8_t slv1_len; num of bit to read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
@@ -8571,25 +10120,35 @@ int32_t lsm6dso_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
slv0_add.slave0 = val->slv_add;
slv0_add.rw_0 = 1;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_ADD, (uint8_t*)&slv0_add, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_ADD, (uint8_t *)&slv0_add, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_SUBADD,
- &(val->slv_subadd), 1);
+ &(val->slv_subadd), 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
slv0_config.slave0_numop = val->slv_len;
ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -8604,6 +10163,7 @@ int32_t lsm6dso_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
* - uint8_t slv1_add; 8 bit i2c device address
* - uint8_t slv1_subadd; 8 bit register device address
* - uint8_t slv1_len; num of bit to read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
@@ -8614,25 +10174,35 @@ int32_t lsm6dso_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
slv1_add.slave1_add = val->slv_add;
slv1_add.r_1 = 1;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_ADD, (uint8_t*)&slv1_add, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_ADD, (uint8_t *)&slv1_add, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_SUBADD,
- &(val->slv_subadd), 1);
+ &(val->slv_subadd), 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG,
- (uint8_t*)&slv1_config, 1);
+ (uint8_t *)&slv1_config, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
slv1_config.slave1_numop = val->slv_len;
ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_CONFIG,
- (uint8_t*)&slv1_config, 1);
+ (uint8_t *)&slv1_config, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -8647,6 +10217,7 @@ int32_t lsm6dso_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
* - uint8_t slv2_add; 8 bit i2c device address
* - uint8_t slv2_subadd; 8 bit register device address
* - uint8_t slv2_len; num of bit to read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
@@ -8657,27 +10228,38 @@ int32_t lsm6dso_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
slv2_add.slave2_add = val->slv_add;
slv2_add.r_2 = 1;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_ADD, (uint8_t*)&slv2_add, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_ADD, (uint8_t *)&slv2_add, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_SUBADD,
- &(val->slv_subadd), 1);
+ &(val->slv_subadd), 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV2_CONFIG,
- (uint8_t*)&slv2_config, 1);
+ (uint8_t *)&slv2_config, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
slv2_config.slave2_numop = val->slv_len;
ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_CONFIG,
- (uint8_t*)&slv2_config, 1);
+ (uint8_t *)&slv2_config, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
+
return ret;
}
@@ -8689,6 +10271,7 @@ int32_t lsm6dso_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
* - uint8_t slv3_add; 8 bit i2c device address
* - uint8_t slv3_subadd; 8 bit register device address
* - uint8_t slv3_len; num of bit to read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
@@ -8699,27 +10282,38 @@ int32_t lsm6dso_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
slv3_add.slave3_add = val->slv_add;
slv3_add.r_3 = 1;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_ADD, (uint8_t*)&slv3_add, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_ADD, (uint8_t *)&slv3_add, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_SUBADD,
- &(val->slv_subadd), 1);
+ &(val->slv_subadd), 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV3_CONFIG,
- (uint8_t*)&slv3_config, 1);
+ (uint8_t *)&slv3_config, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
slv3_config.slave3_numop = val->slv_len;
ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_CONFIG,
- (uint8_t*)&slv3_config, 1);
+ (uint8_t *)&slv3_config, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
+
return ret;
}
@@ -8728,6 +10322,7 @@ int32_t lsm6dso_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val union of registers from STATUS_MASTER to
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_sh_status_get(stmdev_ctx_t *ctx,
@@ -8736,10 +10331,14 @@ int32_t lsm6dso_sh_status_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_MASTER, (uint8_t*) val, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_MASTER, (uint8_t *) val, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
@@ -8762,29 +10361,35 @@ int32_t lsm6dso_sh_status_get(stmdev_ctx_t *ctx,
/**
* @brief Device "Who am I".[get]
*
- * @param ctx communication interface handler. Use NULL to ingnore
+ * @param ctx communication interface handler. Use NULL to ignore
* this interface.(ptr)
* @param aux_ctx auxiliary communication interface handler. Use NULL
- * to ingnore this interface.(ptr)
+ * to ignore this interface.(ptr)
* @param val ID values read from the two interfaces. ID values
* will be the same.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_id_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
- lsm6dso_id_t *val)
+ lsm6dso_id_t *val)
{
int32_t ret = 0;
- if (ctx != NULL){
- ret = lsm6dso_read_reg(ctx, LSM6DSO_WHO_AM_I,
- (uint8_t*)&(val->ui), 1);
+ if (ctx != NULL)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_WHO_AM_I,
+ (uint8_t *) & (val->ui), 1);
}
- if (aux_ctx != NULL){
- if (ret == 0) {
+
+ if (aux_ctx != NULL)
+ {
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_WHO_AM_I,
- (uint8_t*)&(val->aux), 1);
+ (uint8_t *) & (val->aux), 1);
}
}
+
return ret;
}
@@ -8794,8 +10399,9 @@ int32_t lsm6dso_id_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
* @param ctx communication interface handler.(ptr)
* @param val re-initialization mode. Refer to datasheet
* and application note for more information
- * about differencies beetween boot and sw_reset
+ * about differencies between boot and sw_reset
* procedure.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_init_set(stmdev_ctx_t *ctx, lsm6dso_init_t val)
@@ -8806,50 +10412,66 @@ int32_t lsm6dso_init_set(stmdev_ctx_t *ctx, lsm6dso_init_t val)
int32_t ret;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B,
- (uint8_t*)&emb_func_init_b, 1);
+ (uint8_t *)&emb_func_init_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
emb_func_init_b.fifo_compr_init = (uint8_t)val
- & ( (uint8_t)LSM6DSO_FIFO_COMP >> 2 );
+ & ((uint8_t)LSM6DSO_FIFO_COMP >> 2);
emb_func_init_b.fsm_init = (uint8_t)val
- & ( (uint8_t)LSM6DSO_FSM >> 3 );
+ & ((uint8_t)LSM6DSO_FSM >> 3);
ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B,
- (uint8_t*)&emb_func_init_b, 1);
+ (uint8_t *)&emb_func_init_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_A,
- (uint8_t*)&emb_func_init_a, 1);
- }
- if (ret == 0) {
- emb_func_init_a.step_det_init = ( (uint8_t)val
- & (uint8_t)LSM6DSO_PEDO ) >> 5;
- emb_func_init_a.tilt_init = ( (uint8_t)val
- & (uint8_t)LSM6DSO_TILT ) >> 6;
- emb_func_init_a.sig_mot_init = ( (uint8_t)val
- & (uint8_t)LSM6DSO_SMOTION ) >> 7;
+ (uint8_t *)&emb_func_init_a, 1);
+ }
+
+ if (ret == 0)
+ {
+ emb_func_init_a.step_det_init = ((uint8_t)val
+ & (uint8_t)LSM6DSO_PEDO) >> 5;
+ emb_func_init_a.tilt_init = ((uint8_t)val
+ & (uint8_t)LSM6DSO_TILT) >> 6;
+ emb_func_init_a.sig_mot_init = ((uint8_t)val
+ & (uint8_t)LSM6DSO_SMOTION) >> 7;
ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_A,
- (uint8_t*)&emb_func_init_a, 1);
+ (uint8_t *)&emb_func_init_a, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
- if ( ( (val == LSM6DSO_BOOT) || (val == LSM6DSO_RESET) ) && (ret == 0) ) {
+
+ if (((val == LSM6DSO_BOOT) || (val == LSM6DSO_RESET)) &&
+ (ret == 0))
+ {
ctrl3_c.boot = (uint8_t)val & (uint8_t)LSM6DSO_BOOT;
- ctrl3_c.sw_reset = ( (uint8_t)val & (uint8_t)LSM6DSO_RESET) >> 1;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ctrl3_c.sw_reset = ((uint8_t)val & (uint8_t)LSM6DSO_RESET) >> 1;
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
- if ( ( val == LSM6DSO_DRV_RDY )
- && ( (ctrl3_c.bdu == PROPERTY_DISABLE)
- || (ctrl3_c.if_inc == PROPERTY_DISABLE) ) && (ret == 0) ) {
+
+ if ((val == LSM6DSO_DRV_RDY)
+ && ((ctrl3_c.bdu == PROPERTY_DISABLE)
+ || (ctrl3_c.if_inc == PROPERTY_DISABLE)) && (ret == 0))
+ {
ctrl3_c.bdu = PROPERTY_ENABLE;
ctrl3_c.if_inc = PROPERTY_ENABLE;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
return ret;
@@ -8858,16 +10480,17 @@ int32_t lsm6dso_init_set(stmdev_ctx_t *ctx, lsm6dso_init_t val)
/**
* @brief Configures the bus operating mode.[set]
*
- * @param ctx communication interface handler. Use NULL to ingnore
+ * @param ctx communication interface handler. Use NULL to ignore
* this interface.(ptr)
* @param aux_ctx auxiliary communication interface handler. Use NULL
- * to ingnore this interface.(ptr)
+ * to ignore this interface.(ptr)
* @param val configures the bus operating mode for both the
* main and the auxiliary interface.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_bus_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
- lsm6dso_bus_mode_t val)
+ lsm6dso_bus_mode_t val)
{
lsm6dso_ctrl1_ois_t ctrl1_ois;
lsm6dso_i3c_bus_avb_t i3c_bus_avb;
@@ -8879,201 +10502,246 @@ int32_t lsm6dso_bus_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
ret = 0;
- if (aux_ctx != NULL) {
+ if (aux_ctx != NULL)
+ {
ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
+ bit_val = ((uint8_t)val.aux_bus_md & 0x04U) >> 2;
- bit_val = ( (uint8_t)val.aux_bus_md & 0x04U ) >> 2;
- if ( ( ret == 0 ) && ( ctrl1_ois.sim_ois != bit_val ) ) {
+ if ((ret == 0) && (ctrl1_ois.sim_ois != bit_val))
+ {
ctrl1_ois.sim_ois = bit_val;
ret = lsm6dso_write_reg(aux_ctx, LSM6DSO_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
}
}
- if (ctx != NULL) {
- if (ret == 0) {
+ if (ctx != NULL)
+ {
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
+ (uint8_t *)&ctrl9_xl, 1);
}
bit_val = ((uint8_t)val.ui_bus_md & 0x04U) >> 2;
- if ( ( ret == 0 ) && ( ctrl9_xl.i3c_disable != bit_val ) ) {
+
+ if ((ret == 0) && (ctrl9_xl.i3c_disable != bit_val))
+ {
ctrl9_xl.i3c_disable = bit_val;
ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
+ (uint8_t *)&ctrl9_xl, 1);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
}
bit_val = ((uint8_t)val.ui_bus_md & 0x30U) >> 4;
- if ( ( ret == 0 ) && ( i3c_bus_avb.i3c_bus_avb_sel != bit_val ) ) {
+
+ if ((ret == 0) && (i3c_bus_avb.i3c_bus_avb_sel != bit_val))
+ {
i3c_bus_avb.i3c_bus_avb_sel = bit_val;
ret = lsm6dso_write_reg(ctx, LSM6DSO_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C,
- (uint8_t*)&ctrl4_c, 1);
+ (uint8_t *)&ctrl4_c, 1);
}
- bit_val = ( (uint8_t)val.ui_bus_md & 0x02U ) >> 1;
- if ( ( ret == 0 ) && ( ctrl4_c.i2c_disable != bit_val ) ) {
+
+ bit_val = ((uint8_t)val.ui_bus_md & 0x02U) >> 1;
+
+ if ((ret == 0) && (ctrl4_c.i2c_disable != bit_val))
+ {
ctrl4_c.i2c_disable = bit_val;
ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C,
- (uint8_t*)&ctrl4_c, 1);
+ (uint8_t *)&ctrl4_c, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C,
- (uint8_t*)&ctrl3_c, 1);
+ (uint8_t *)&ctrl3_c, 1);
}
+
bit_val = (uint8_t)val.ui_bus_md & 0x01U;
- if ( ( ret == 0 ) && ( ctrl3_c.sim != bit_val ) ) {
+
+ if ((ret == 0) && (ctrl3_c.sim != bit_val))
+ {
ctrl3_c.sim = bit_val;
ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C,
- (uint8_t*)&ctrl3_c, 1);
+ (uint8_t *)&ctrl3_c, 1);
}
}
return ret;
-
}
/**
* @brief Get the bus operating mode.[get]
*
- * @param ctx communication interface handler. Use NULL to ingnore
+ * @param ctx communication interface handler. Use NULL to ignore
* this interface.(ptr)
* @param aux_ctx auxiliary communication interface handler. Use NULL
- * to ingnore this interface.(ptr)
+ * to ignore this interface.(ptr)
* @param val retrieves the bus operating mode for both the main
* and the auxiliary interface.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_bus_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
- lsm6dso_bus_mode_t *val)
+ lsm6dso_bus_mode_t *val)
{
lsm6dso_ctrl1_ois_t ctrl1_ois;
lsm6dso_i3c_bus_avb_t i3c_bus_avb;
lsm6dso_ctrl9_xl_t ctrl9_xl;
lsm6dso_ctrl3_c_t ctrl3_c;
lsm6dso_ctrl4_c_t ctrl4_c;
-
int32_t ret = 0;
- if (aux_ctx != NULL) {
+ if (aux_ctx != NULL)
+ {
ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
- switch ( ctrl1_ois.sim_ois ) {
+ (uint8_t *)&ctrl1_ois, 1);
+
+ switch (ctrl1_ois.sim_ois)
+ {
case LSM6DSO_SPI_4W_AUX:
val->aux_bus_md = LSM6DSO_SPI_4W_AUX;
break;
+
case LSM6DSO_SPI_3W_AUX:
val->aux_bus_md = LSM6DSO_SPI_3W_AUX;
break;
+
default:
val->aux_bus_md = LSM6DSO_SPI_4W_AUX;
break;
}
}
- if (ctx != NULL) {
- if (ret == 0) {
+ if (ctx != NULL)
+ {
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
+ (uint8_t *)&ctrl9_xl, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C,
- (uint8_t*)&ctrl4_c, 1);
+ (uint8_t *)&ctrl4_c, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C,
- (uint8_t*)&ctrl3_c, 1);
+ (uint8_t *)&ctrl3_c, 1);
- switch ( ( i3c_bus_avb.i3c_bus_avb_sel << 4 ) &
- ( ctrl9_xl.i3c_disable << 2 ) &
- ( ctrl4_c.i2c_disable << 1) & ctrl3_c.sim ) {
+ switch ((i3c_bus_avb.i3c_bus_avb_sel << 4) &
+ (ctrl9_xl.i3c_disable << 2) &
+ (ctrl4_c.i2c_disable << 1) & ctrl3_c.sim)
+ {
case LSM6DSO_SEL_BY_HW:
val->ui_bus_md = LSM6DSO_SEL_BY_HW;
break;
+
case LSM6DSO_SPI_4W:
val->ui_bus_md = LSM6DSO_SPI_4W;
break;
+
case LSM6DSO_SPI_3W:
val->ui_bus_md = LSM6DSO_SPI_3W;
break;
+
case LSM6DSO_I2C:
val->ui_bus_md = LSM6DSO_I2C;
break;
+
case LSM6DSO_I3C_T_50us:
val->ui_bus_md = LSM6DSO_I3C_T_50us;
break;
+
case LSM6DSO_I3C_T_2us:
val->ui_bus_md = LSM6DSO_I3C_T_2us;
break;
+
case LSM6DSO_I3C_T_1ms:
val->ui_bus_md = LSM6DSO_I3C_T_1ms;
break;
+
case LSM6DSO_I3C_T_25ms:
val->ui_bus_md = LSM6DSO_I3C_T_25ms;
break;
+
default:
val->ui_bus_md = LSM6DSO_SEL_BY_HW;
break;
}
}
}
+
return ret;
}
/**
* @brief Get the status of the device.[get]
*
- * @param ctx communication interface handler. Use NULL to ingnore
+ * @param ctx communication interface handler. Use NULL to ignore
* this interface.(ptr)
* @param aux_ctx auxiliary communication interface handler. Use NULL
- * to ingnore this interface.(ptr)
+ * to ignore this interface.(ptr)
* @param val the status of the device.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_status_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
- lsm6dso_status_t *val)
+ lsm6dso_status_t *val)
{
lsm6dso_status_spiaux_t status_spiaux;
lsm6dso_status_reg_t status_reg;
lsm6dso_ctrl3_c_t ctrl3_c;
int32_t ret;
-
ret = 0;
- if (aux_ctx != NULL){
+ if (aux_ctx != NULL)
+ {
ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_STATUS_SPIAUX,
- (uint8_t*)&status_spiaux, 1);
+ (uint8_t *)&status_spiaux, 1);
val->ois_drdy_xl = status_spiaux.xlda;
val->ois_drdy_g = status_spiaux.gda;
val->ois_gyro_settling = status_spiaux.gyro_settling;
}
- if (ctx != NULL){
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ if (ctx != NULL)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
val->sw_reset = ctrl3_c.sw_reset;
val->boot = ctrl3_c.boot;
- if ( (ret == 0) && ( ctrl3_c.sw_reset == PROPERTY_DISABLE ) &&
- ( ctrl3_c.boot == PROPERTY_DISABLE ) ) {
+ if ((ret == 0) && (ctrl3_c.sw_reset == PROPERTY_DISABLE) &&
+ (ctrl3_c.boot == PROPERTY_DISABLE))
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG,
- (uint8_t*)&status_reg, 1);
+ (uint8_t *)&status_reg, 1);
val->drdy_xl = status_reg.xlda;
val->drdy_g = status_reg.gda;
val->drdy_temp = status_reg.tda;
}
}
+
return ret;
}
@@ -9083,37 +10751,50 @@ int32_t lsm6dso_status_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
* @param ctx communication interface handler.(ptr)
* @param val the electrical settings for the configurable
* pins.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_pin_conf_set(stmdev_ctx_t *ctx, lsm6dso_pin_conf_t val)
+int32_t lsm6dso_pin_conf_set(stmdev_ctx_t *ctx,
+ lsm6dso_pin_conf_t val)
{
lsm6dso_i3c_bus_avb_t i3c_bus_avb;
lsm6dso_pin_ctrl_t pin_ctrl;
lsm6dso_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
+
+ if (ret == 0)
+ {
pin_ctrl.ois_pu_dis = ~val.aux_sdo_ocs_pull_up;
pin_ctrl.sdo_pu_en = val.sdo_sa0_pull_up;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
}
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ctrl3_c.pp_od = ~val.int1_int2_push_pull;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
i3c_bus_avb.pd_dis_int1 = ~val.int1_pull_down;
ret = lsm6dso_write_reg(ctx, LSM6DSO_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
}
+
return ret;
}
@@ -9123,29 +10804,38 @@ int32_t lsm6dso_pin_conf_set(stmdev_ctx_t *ctx, lsm6dso_pin_conf_t val)
* @param ctx communication interface handler.(ptr)
* @param val the electrical settings for the configurable
* pins.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_pin_conf_get(stmdev_ctx_t *ctx, lsm6dso_pin_conf_t *val)
+int32_t lsm6dso_pin_conf_get(stmdev_ctx_t *ctx,
+ lsm6dso_pin_conf_t *val)
{
lsm6dso_i3c_bus_avb_t i3c_bus_avb;
lsm6dso_pin_ctrl_t pin_ctrl;
lsm6dso_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
+
+ if (ret == 0)
+ {
val->aux_sdo_ocs_pull_up = ~pin_ctrl.ois_pu_dis;
val->aux_sdo_ocs_pull_up = pin_ctrl.sdo_pu_en;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
val->int1_int2_push_pull = ~ctrl3_c.pp_od;
ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
val->int1_pull_down = ~i3c_bus_avb.pd_dis_int1;
}
+
return ret;
}
@@ -9154,42 +10844,58 @@ int32_t lsm6dso_pin_conf_get(stmdev_ctx_t *ctx, lsm6dso_pin_conf_t *val)
*
* @param ctx communication interface handler.(ptr)
* @param val the pins hardware signal settings.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_interrupt_mode_set(stmdev_ctx_t *ctx,
- lsm6dso_int_mode_t val)
+ lsm6dso_int_mode_t val)
{
lsm6dso_tap_cfg0_t tap_cfg0;
lsm6dso_page_rw_t page_rw;
lsm6dso_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.h_lactive = val.active_low;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
tap_cfg0.lir = val.base_latched;
tap_cfg0.int_clr_on_read = val.base_latched | val.emb_latched;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
}
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_rw.emb_func_lir = val.emb_latched;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
+
return ret;
}
@@ -9198,36 +10904,48 @@ int32_t lsm6dso_interrupt_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx communication interface handler.(ptr)
* @param val the pins hardware signal settings.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_interrupt_mode_get(stmdev_ctx_t *ctx,
- lsm6dso_int_mode_t *val)
+ lsm6dso_int_mode_t *val)
{
lsm6dso_tap_cfg0_t tap_cfg0;
lsm6dso_page_rw_t page_rw;
lsm6dso_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if (ret == 0) {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.h_lactive = val->active_low;
- ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
tap_cfg0.lir = val->base_latched;
tap_cfg0.int_clr_on_read = val->base_latched | val->emb_latched;
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
}
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_rw.emb_func_lir = val->emb_latched;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
+
return ret;
}
@@ -9236,10 +10954,11 @@ int32_t lsm6dso_interrupt_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx communication interface handler.(ptr)
* @param val the signals to route on int1 pin.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_pin_int1_route_set(stmdev_ctx_t *ctx,
- lsm6dso_pin_int1_route_t val)
+ lsm6dso_pin_int1_route_t val)
{
lsm6dso_pin_int2_route_t pin_int2_route;
lsm6dso_emb_func_int1_t emb_func_int1;
@@ -9252,7 +10971,6 @@ int32_t lsm6dso_pin_int1_route_set(stmdev_ctx_t *ctx,
lsm6dso_md1_cfg_t md1_cfg;
lsm6dso_ctrl4_c_t ctrl4_c;
int32_t ret;
-
int1_ctrl.int1_drdy_xl = val.drdy_xl;
int1_ctrl.int1_drdy_g = val.drdy_g;
int1_ctrl.int1_boot = val.boot;
@@ -9261,7 +10979,6 @@ int32_t lsm6dso_pin_int1_route_set(stmdev_ctx_t *ctx,
int1_ctrl.int1_fifo_full = val.fifo_full;
int1_ctrl.int1_cnt_bdr = val.fifo_bdr;
int1_ctrl.den_drdy_flag = val.den_flag;
-
md1_cfg.int1_shub = val.sh_endop;
md1_cfg.int1_6d = val.six_d;
md1_cfg.int1_double_tap = val.double_tap;
@@ -9269,12 +10986,12 @@ int32_t lsm6dso_pin_int1_route_set(stmdev_ctx_t *ctx,
md1_cfg.int1_wu = val.wake_up;
md1_cfg.int1_single_tap = val.single_tap;
md1_cfg.int1_sleep_change = val.sleep_change;
-
+ emb_func_int1.not_used_01 = 0;
emb_func_int1.int1_step_detector = val.step_detector;
emb_func_int1.int1_tilt = val.tilt;
emb_func_int1.int1_sig_mot = val.sig_mot;
+ emb_func_int1.not_used_02 = 0;
emb_func_int1.int1_fsm_lc = val.fsm_lc;
-
fsm_int1_a.int1_fsm1 = val.fsm1;
fsm_int1_a.int1_fsm2 = val.fsm2;
fsm_int1_a.int1_fsm3 = val.fsm3;
@@ -9283,7 +11000,6 @@ int32_t lsm6dso_pin_int1_route_set(stmdev_ctx_t *ctx,
fsm_int1_a.int1_fsm6 = val.fsm6;
fsm_int1_a.int1_fsm7 = val.fsm7;
fsm_int1_a.int1_fsm8 = val.fsm8;
-
fsm_int1_b.int1_fsm9 = val.fsm9 ;
fsm_int1_b.int1_fsm10 = val.fsm10;
fsm_int1_b.int1_fsm11 = val.fsm11;
@@ -9292,39 +11008,54 @@ int32_t lsm6dso_pin_int1_route_set(stmdev_ctx_t *ctx,
fsm_int1_b.int1_fsm14 = val.fsm14;
fsm_int1_b.int1_fsm15 = val.fsm15;
fsm_int1_b.int1_fsm16 = val.fsm16;
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if (ret == 0) {
- if( ( val.drdy_temp | val.timestamp ) != PROPERTY_DISABLE) {
+ if (ret == 0)
+ {
+ if ((val.drdy_temp | val.timestamp) != PROPERTY_DISABLE)
+ {
ctrl4_c.int2_on_int1 = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
ctrl4_c.int2_on_int1 = PROPERTY_DISABLE;
}
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INT1,
- (uint8_t*)&emb_func_int1, 1);
+ (uint8_t *)&emb_func_int1, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT1_A,
- (uint8_t*)&fsm_int1_a, 1);
+ (uint8_t *)&fsm_int1_a, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT1_B,
- (uint8_t*)&fsm_int1_b, 1);
+ (uint8_t *)&fsm_int1_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
- if (ret == 0) {
- if ( ( emb_func_int1.int1_fsm_lc
+ if (ret == 0)
+ {
+ if ((emb_func_int1.int1_fsm_lc
| emb_func_int1.int1_sig_mot
| emb_func_int1.int1_step_detector
| emb_func_int1.int1_tilt
@@ -9343,42 +11074,60 @@ int32_t lsm6dso_pin_int1_route_set(stmdev_ctx_t *ctx,
| fsm_int1_b.int1_fsm13
| fsm_int1_b.int1_fsm14
| fsm_int1_b.int1_fsm15
- | fsm_int1_b.int1_fsm16) != PROPERTY_DISABLE){
+ | fsm_int1_b.int1_fsm16) != PROPERTY_DISABLE)
+ {
md1_cfg.int1_emb_func = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
md1_cfg.int1_emb_func = PROPERTY_DISABLE;
}
+
ret = lsm6dso_write_reg(ctx, LSM6DSO_INT1_CTRL,
- (uint8_t*)&int1_ctrl, 1);
+ (uint8_t *)&int1_ctrl, 1);
}
- if (ret == 0) {
- ret = lsm6dso_write_reg(ctx, LSM6DSO_MD1_CFG, (uint8_t*)&md1_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_MD1_CFG, (uint8_t *)&md1_cfg, 1);
}
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
int2_ctrl.int2_drdy_temp = val.drdy_temp;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
}
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t*)&md2_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t *)&md2_cfg, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
md2_cfg.int2_timestamp = val.timestamp;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t*)&md2_cfg, 1);
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t *)&md2_cfg, 1);
}
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_pin_int2_route_get(ctx, NULL, &pin_int2_route);
}
- if (ret == 0) {
- if ( ( pin_int2_route.fifo_bdr
+
+ if (ret == 0)
+ {
+ if ((pin_int2_route.fifo_bdr
| pin_int2_route.drdy_g
| pin_int2_route.drdy_temp
| pin_int2_route.drdy_xl
@@ -9405,14 +11154,19 @@ int32_t lsm6dso_pin_int1_route_set(stmdev_ctx_t *ctx,
| md1_cfg.int1_ff
| md1_cfg.int1_wu
| md1_cfg.int1_single_tap
- | md1_cfg.int1_sleep_change) != PROPERTY_DISABLE) {
+ | md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
+ {
tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
}
- ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
+
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
}
+
return ret;
}
@@ -9421,10 +11175,11 @@ int32_t lsm6dso_pin_int1_route_set(stmdev_ctx_t *ctx,
*
* @param ctx communication interface handler.(ptr)
* @param val the signals that are routed on int1 pin.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_pin_int1_route_get(stmdev_ctx_t *ctx,
- lsm6dso_pin_int1_route_t *val)
+ lsm6dso_pin_int1_route_t *val)
{
lsm6dso_emb_func_int1_t emb_func_int1;
lsm6dso_fsm_int1_a_t fsm_int1_a;
@@ -9435,44 +11190,64 @@ int32_t lsm6dso_pin_int1_route_get(stmdev_ctx_t *ctx,
lsm6dso_md1_cfg_t md1_cfg;
lsm6dso_ctrl4_c_t ctrl4_c;
int32_t ret;
-
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INT1,
- (uint8_t*)&emb_func_int1, 1);
+ (uint8_t *)&emb_func_int1, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT1_A,
- (uint8_t*)&fsm_int1_a, 1);
+ (uint8_t *)&fsm_int1_a, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT1_B,
- (uint8_t*)&fsm_int1_b, 1);
+ (uint8_t *)&fsm_int1_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_INT1_CTRL,
- (uint8_t*)&int1_ctrl, 1);
+ (uint8_t *)&int1_ctrl, 1);
}
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_MD1_CFG, (uint8_t*)&md1_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_MD1_CFG, (uint8_t *)&md1_cfg, 1);
}
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
- if (ctrl4_c.int2_on_int1 == PROPERTY_ENABLE){
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+
+ if (ctrl4_c.int2_on_int1 == PROPERTY_ENABLE)
+ {
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
val->drdy_temp = int2_ctrl.int2_drdy_temp;
}
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t*)&md2_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t *)&md2_cfg, 1);
val->timestamp = md2_cfg.int2_timestamp;
}
}
- else {
+
+ else
+ {
val->drdy_temp = PROPERTY_DISABLE;
val->timestamp = PROPERTY_DISABLE;
}
@@ -9485,7 +11260,6 @@ int32_t lsm6dso_pin_int1_route_get(stmdev_ctx_t *ctx,
val->fifo_full = int1_ctrl.int1_fifo_full;
val->fifo_bdr = int1_ctrl.int1_cnt_bdr;
val->den_flag = int1_ctrl.den_drdy_flag;
-
val->sh_endop = md1_cfg.int1_shub;
val->six_d = md1_cfg.int1_6d;
val->double_tap = md1_cfg.int1_double_tap;
@@ -9493,12 +11267,10 @@ int32_t lsm6dso_pin_int1_route_get(stmdev_ctx_t *ctx,
val->wake_up = md1_cfg.int1_wu;
val->single_tap = md1_cfg.int1_single_tap;
val->sleep_change = md1_cfg.int1_sleep_change;
-
val->step_detector = emb_func_int1.int1_step_detector;
val->tilt = emb_func_int1.int1_tilt;
val->sig_mot = emb_func_int1.int1_sig_mot;
val->fsm_lc = emb_func_int1.int1_fsm_lc;
-
val->fsm1 = fsm_int1_a.int1_fsm1;
val->fsm2 = fsm_int1_a.int1_fsm2;
val->fsm3 = fsm_int1_a.int1_fsm3;
@@ -9507,7 +11279,6 @@ int32_t lsm6dso_pin_int1_route_get(stmdev_ctx_t *ctx,
val->fsm6 = fsm_int1_a.int1_fsm6;
val->fsm7 = fsm_int1_a.int1_fsm7;
val->fsm8 = fsm_int1_a.int1_fsm8;
-
val->fsm9 = fsm_int1_b.int1_fsm9;
val->fsm10 = fsm_int1_b.int1_fsm10;
val->fsm11 = fsm_int1_b.int1_fsm11;
@@ -9523,15 +11294,17 @@ int32_t lsm6dso_pin_int1_route_get(stmdev_ctx_t *ctx,
/**
* @brief Route interrupt signals on int2 pin.[set]
*
- * @param ctx communication interface handler. Use NULL to ingnore
+ * @param ctx communication interface handler. Use NULL to ignore
* this interface.(ptr)
* @param aux_ctx auxiliary communication interface handler. Use NULL
- * to ingnore this interface.(ptr)
+ * to ignore this interface.(ptr)
* @param val the signals to route on int2 pin.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_pin_int2_route_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
- lsm6dso_pin_int2_route_t val)
+int32_t lsm6dso_pin_int2_route_set(stmdev_ctx_t *ctx,
+ stmdev_ctx_t *aux_ctx,
+ lsm6dso_pin_int2_route_t val)
{
lsm6dso_pin_int1_route_t pin_int1_route;
lsm6dso_emb_func_int2_t emb_func_int2;
@@ -9543,20 +11316,23 @@ int32_t lsm6dso_pin_int2_route_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
lsm6dso_ctrl4_c_t ctrl4_c;
lsm6dso_int_ois_t int_ois;
int32_t ret;
-
ret = 0;
- if( aux_ctx != NULL ) {
+ if (aux_ctx != NULL)
+ {
ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_INT_OIS,
- (uint8_t*)&int_ois, 1);
- if (ret == 0) {
+ (uint8_t *)&int_ois, 1);
+
+ if (ret == 0)
+ {
int_ois.int2_drdy_ois = val.drdy_ois;
ret = lsm6dso_write_reg(aux_ctx, LSM6DSO_INT_OIS,
- (uint8_t*)&int_ois, 1);
+ (uint8_t *)&int_ois, 1);
}
}
- if( ctx != NULL ) {
+ if (ctx != NULL)
+ {
int2_ctrl.int2_drdy_xl = val.drdy_xl;
int2_ctrl.int2_drdy_g = val.drdy_g;
int2_ctrl.int2_drdy_temp = val.drdy_temp;
@@ -9564,7 +11340,7 @@ int32_t lsm6dso_pin_int2_route_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
int2_ctrl.int2_fifo_ovr = val.fifo_ovr;
int2_ctrl.int2_fifo_full = val.fifo_full;
int2_ctrl.int2_cnt_bdr = val.fifo_bdr;
-
+ int2_ctrl.not_used_01 = 0;
md2_cfg.int2_timestamp = val.timestamp;
md2_cfg.int2_6d = val.six_d;
md2_cfg.int2_double_tap = val.double_tap;
@@ -9572,11 +11348,12 @@ int32_t lsm6dso_pin_int2_route_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
md2_cfg.int2_wu = val.wake_up;
md2_cfg.int2_single_tap = val.single_tap;
md2_cfg.int2_sleep_change = val.sleep_change;
-
+ emb_func_int2.not_used_01 = 0;
emb_func_int2. int2_step_detector = val.step_detector;
emb_func_int2.int2_tilt = val.tilt;
+ emb_func_int2.int2_sig_mot = val.sig_mot;
+ emb_func_int2.not_used_02 = 0;
emb_func_int2.int2_fsm_lc = val.fsm_lc;
-
fsm_int2_a.int2_fsm1 = val.fsm1;
fsm_int2_a.int2_fsm2 = val.fsm2;
fsm_int2_a.int2_fsm3 = val.fsm3;
@@ -9585,7 +11362,6 @@ int32_t lsm6dso_pin_int2_route_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
fsm_int2_a.int2_fsm6 = val.fsm6;
fsm_int2_a.int2_fsm7 = val.fsm7;
fsm_int2_a.int2_fsm8 = val.fsm8;
-
fsm_int2_b.int2_fsm9 = val.fsm9 ;
fsm_int2_b.int2_fsm10 = val.fsm10;
fsm_int2_b.int2_fsm11 = val.fsm11;
@@ -9595,80 +11371,102 @@ int32_t lsm6dso_pin_int2_route_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
fsm_int2_b.int2_fsm15 = val.fsm15;
fsm_int2_b.int2_fsm16 = val.fsm16;
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if (ret == 0) {
- if ( ( val.drdy_temp | val.timestamp ) != PROPERTY_DISABLE ) {
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ if ((val.drdy_temp | val.timestamp) != PROPERTY_DISABLE)
+ {
ctrl4_c.int2_on_int1 = PROPERTY_DISABLE;
}
- else{
- ctrl4_c.int2_on_int1 = PROPERTY_ENABLE;
- }
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INT2,
- (uint8_t*)&emb_func_int2, 1);
+ (uint8_t *)&emb_func_int2, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT2_A,
- (uint8_t*)&fsm_int2_a, 1);
+ (uint8_t *)&fsm_int2_a, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT2_B,
- (uint8_t*)&fsm_int2_b, 1);
+ (uint8_t *)&fsm_int2_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
- if (ret == 0) {
- if (( emb_func_int2.int2_fsm_lc
- | emb_func_int2.int2_sig_mot
- | emb_func_int2.int2_step_detector
- | emb_func_int2.int2_tilt
- | fsm_int2_a.int2_fsm1
- | fsm_int2_a.int2_fsm2
- | fsm_int2_a.int2_fsm3
- | fsm_int2_a.int2_fsm4
- | fsm_int2_a.int2_fsm5
- | fsm_int2_a.int2_fsm6
- | fsm_int2_a.int2_fsm7
- | fsm_int2_a.int2_fsm8
- | fsm_int2_b.int2_fsm9
- | fsm_int2_b.int2_fsm10
- | fsm_int2_b.int2_fsm11
- | fsm_int2_b.int2_fsm12
- | fsm_int2_b.int2_fsm13
- | fsm_int2_b.int2_fsm14
- | fsm_int2_b.int2_fsm15
- | fsm_int2_b.int2_fsm16)!= PROPERTY_DISABLE ){
+ if (ret == 0)
+ {
+ if ((emb_func_int2.int2_fsm_lc
+ | emb_func_int2.int2_sig_mot
+ | emb_func_int2.int2_step_detector
+ | emb_func_int2.int2_tilt
+ | fsm_int2_a.int2_fsm1
+ | fsm_int2_a.int2_fsm2
+ | fsm_int2_a.int2_fsm3
+ | fsm_int2_a.int2_fsm4
+ | fsm_int2_a.int2_fsm5
+ | fsm_int2_a.int2_fsm6
+ | fsm_int2_a.int2_fsm7
+ | fsm_int2_a.int2_fsm8
+ | fsm_int2_b.int2_fsm9
+ | fsm_int2_b.int2_fsm10
+ | fsm_int2_b.int2_fsm11
+ | fsm_int2_b.int2_fsm12
+ | fsm_int2_b.int2_fsm13
+ | fsm_int2_b.int2_fsm14
+ | fsm_int2_b.int2_fsm15
+ | fsm_int2_b.int2_fsm16) != PROPERTY_DISABLE)
+ {
md2_cfg.int2_emb_func = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
md2_cfg.int2_emb_func = PROPERTY_DISABLE;
}
+
ret = lsm6dso_write_reg(ctx, LSM6DSO_INT2_CTRL,
- (uint8_t*)&int2_ctrl, 1);
+ (uint8_t *)&int2_ctrl, 1);
}
- if (ret == 0) {
- ret = lsm6dso_write_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t*)&md2_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t *)&md2_cfg, 1);
}
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dso_pin_int1_route_get(ctx, &pin_int1_route);
}
- if (ret == 0) {
- if ( ( val.fifo_bdr
+ if (ret == 0)
+ {
+ if ((val.fifo_bdr
| val.drdy_g
| val.drdy_temp
| val.drdy_xl
@@ -9694,30 +11492,37 @@ int32_t lsm6dso_pin_int2_route_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
| pin_int1_route.free_fall
| pin_int1_route.wake_up
| pin_int1_route.single_tap
- | pin_int1_route.sleep_change ) != PROPERTY_DISABLE) {
+ | pin_int1_route.sleep_change) != PROPERTY_DISABLE)
+ {
tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
}
- ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
+
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
}
}
+
return ret;
}
/**
* @brief Route interrupt signals on int2 pin.[get]
*
- * @param ctx communication interface handler. Use NULL to ingnore
+ * @param ctx communication interface handler. Use NULL to ignore
* this interface.(ptr)
* @param aux_ctx auxiliary communication interface handler. Use NULL
- * to ingnore this interface.(ptr)
+ * to ignore this interface.(ptr)
* @param val the signals that are routed on int2 pin.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dso_pin_int2_route_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
- lsm6dso_pin_int2_route_t *val)
+int32_t lsm6dso_pin_int2_route_get(stmdev_ctx_t *ctx,
+ stmdev_ctx_t *aux_ctx,
+ lsm6dso_pin_int2_route_t *val)
{
lsm6dso_emb_func_int2_t emb_func_int2;
lsm6dso_fsm_int2_a_t fsm_int2_a;
@@ -9727,59 +11532,80 @@ int32_t lsm6dso_pin_int2_route_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
lsm6dso_ctrl4_c_t ctrl4_c;
lsm6dso_int_ois_t int_ois;
int32_t ret;
-
ret = 0;
- if( aux_ctx != NULL ) {
+ if (aux_ctx != NULL)
+ {
ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_INT_OIS,
- (uint8_t*)&int_ois, 1);
+ (uint8_t *)&int_ois, 1);
val->drdy_ois = int_ois.int2_drdy_ois;
}
- if( ctx != NULL ) {
- if (ret == 0) {
- ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+ if (ctx != NULL)
+ {
+ if (ret == 0)
+ {
+ ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INT2,
- (uint8_t*)&emb_func_int2, 1);
+ (uint8_t *)&emb_func_int2, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT2_A,
- (uint8_t*)&fsm_int2_a, 1);
+ (uint8_t *)&fsm_int2_a, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT2_B,
- (uint8_t*)&fsm_int2_b, 1);
+ (uint8_t *)&fsm_int2_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_INT2_CTRL,
- (uint8_t*)&int2_ctrl, 1);
+ (uint8_t *)&int2_ctrl, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_MD2_CFG,
- (uint8_t*)&md2_cfg, 1);
+ (uint8_t *)&md2_cfg, 1);
}
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
- if (ctrl4_c.int2_on_int1 == PROPERTY_DISABLE){
- if (ret == 0) {
+
+ if (ctrl4_c.int2_on_int1 == PROPERTY_DISABLE)
+ {
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_INT2_CTRL,
- (uint8_t*)&int2_ctrl, 1);
+ (uint8_t *)&int2_ctrl, 1);
val->drdy_temp = int2_ctrl.int2_drdy_temp;
}
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t*)&md2_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t *)&md2_cfg, 1);
val->timestamp = md2_cfg.int2_timestamp;
}
}
- else {
+
+ else
+ {
val->drdy_temp = PROPERTY_DISABLE;
val->timestamp = PROPERTY_DISABLE;
}
@@ -9791,7 +11617,6 @@ int32_t lsm6dso_pin_int2_route_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
val->fifo_ovr = int2_ctrl.int2_fifo_ovr;
val->fifo_full = int2_ctrl.int2_fifo_full;
val->fifo_bdr = int2_ctrl.int2_cnt_bdr;
-
val->timestamp = md2_cfg.int2_timestamp;
val->six_d = md2_cfg.int2_6d;
val->double_tap = md2_cfg.int2_double_tap;
@@ -9799,11 +11624,9 @@ int32_t lsm6dso_pin_int2_route_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
val->wake_up = md2_cfg.int2_wu;
val->single_tap = md2_cfg.int2_single_tap;
val->sleep_change = md2_cfg.int2_sleep_change;
-
val->step_detector = emb_func_int2. int2_step_detector;
val->tilt = emb_func_int2.int2_tilt;
val->fsm_lc = emb_func_int2.int2_fsm_lc;
-
val->fsm1 = fsm_int2_a.int2_fsm1;
val->fsm2 = fsm_int2_a.int2_fsm2;
val->fsm3 = fsm_int2_a.int2_fsm3;
@@ -9812,7 +11635,6 @@ int32_t lsm6dso_pin_int2_route_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
val->fsm6 = fsm_int2_a.int2_fsm6;
val->fsm7 = fsm_int2_a.int2_fsm7;
val->fsm8 = fsm_int2_a.int2_fsm8;
-
val->fsm9 = fsm_int2_b.int2_fsm9;
val->fsm10 = fsm_int2_b.int2_fsm10;
val->fsm11 = fsm_int2_b.int2_fsm11;
@@ -9821,7 +11643,6 @@ int32_t lsm6dso_pin_int2_route_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
val->fsm14 = fsm_int2_b.int2_fsm14;
val->fsm15 = fsm_int2_b.int2_fsm15;
val->fsm16 = fsm_int2_b.int2_fsm16;
-
}
return ret;
@@ -9832,10 +11653,11 @@ int32_t lsm6dso_pin_int2_route_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
*
* @param ctx communication interface handler.(ptr)
* @param val the status of all the interrupt sources.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_all_sources_get(stmdev_ctx_t *ctx,
- lsm6dso_all_sources_t *val)
+ lsm6dso_all_sources_t *val)
{
lsm6dso_emb_func_status_mainpage_t emb_func_status_mainpage;
lsm6dso_status_master_mainpage_t status_master_mainpage;
@@ -9848,34 +11670,18 @@ int32_t lsm6dso_all_sources_get(stmdev_ctx_t *ctx,
lsm6dso_status_reg_t status_reg;
lsm6dso_tap_src_t tap_src;
lsm6dso_d6d_src_t d6d_src;
- lsm6dso_ctrl5_c_t ctrl5_c;
- uint8_t reg[12];
+ uint8_t reg[5];
int32_t ret;
-
- ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if (ret == 0) {
- ctrl5_c.not_used_01 = PROPERTY_ENABLE;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- }
- if (ret == 0) {
- ret = lsm6dso_read_reg(ctx, LSM6DSO_ALL_INT_SRC, reg, 12);
- }
-
- if (ret == 0) {
- bytecpy(( uint8_t*)&all_int_src, ®[0]);
- bytecpy(( uint8_t*)&wake_up_src, ®[1]);
- bytecpy(( uint8_t*)&tap_src, ®[2]);
- bytecpy(( uint8_t*)&d6d_src, ®[3]);
- bytecpy(( uint8_t*)&status_reg, ®[4]);
- bytecpy(( uint8_t*)&emb_func_status_mainpage, ®[5]);
- bytecpy(( uint8_t*)&fsm_status_a_mainpage, ®[6]);
- bytecpy(( uint8_t*)&fsm_status_b_mainpage, ®[7]);
- bytecpy(( uint8_t*)&status_master_mainpage, ®[9]);
- bytecpy(( uint8_t*)&fifo_status1, ®[10]);
- bytecpy(( uint8_t*)&fifo_status2, ®[11]);
-
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_ALL_INT_SRC, reg, 5);
+
+ if (ret == 0)
+ {
+ bytecpy((uint8_t *)&all_int_src, ®[0]);
+ bytecpy((uint8_t *)&wake_up_src, ®[1]);
+ bytecpy((uint8_t *)&tap_src, ®[2]);
+ bytecpy((uint8_t *)&d6d_src, ®[3]);
+ bytecpy((uint8_t *)&status_reg, ®[4]);
val->timestamp = all_int_src.timestamp_endcount;
-
val->wake_up_z = wake_up_src.z_wu;
val->wake_up_y = wake_up_src.y_wu;
val->wake_up_x = wake_up_src.x_wu;
@@ -9883,14 +11689,12 @@ int32_t lsm6dso_all_sources_get(stmdev_ctx_t *ctx,
val->sleep_state = wake_up_src.sleep_state;
val->free_fall = wake_up_src.ff_ia;
val->sleep_change = wake_up_src.sleep_change_ia;
-
val->tap_x = tap_src.x_tap;
val->tap_y = tap_src.y_tap;
val->tap_z = tap_src.z_tap;
val->tap_sign = tap_src.tap_sign;
val->double_tap = tap_src.double_tap;
val->single_tap = tap_src.single_tap;
-
val->six_d_xl = d6d_src.xl;
val->six_d_xh = d6d_src.xh;
val->six_d_yl = d6d_src.yl;
@@ -9899,16 +11703,25 @@ int32_t lsm6dso_all_sources_get(stmdev_ctx_t *ctx,
val->six_d_zh = d6d_src.zh;
val->six_d = d6d_src.d6d_ia;
val->den_flag = d6d_src.den_drdy;
-
val->drdy_xl = status_reg.xlda;
val->drdy_g = status_reg.gda;
val->drdy_temp = status_reg.tda;
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS_MAINPAGE, reg, 3);
+ }
+ if (ret == 0)
+ {
+ bytecpy((uint8_t *)&emb_func_status_mainpage, ®[0]);
+ bytecpy((uint8_t *)&fsm_status_a_mainpage, ®[1]);
+ bytecpy((uint8_t *)&fsm_status_b_mainpage, ®[2]);
val->step_detector = emb_func_status_mainpage.is_step_det;
val->tilt = emb_func_status_mainpage.is_tilt;
val->sig_mot = emb_func_status_mainpage.is_sigmot;
val->fsm_lc = emb_func_status_mainpage.is_fsm_lc;
-
val->fsm1 = fsm_status_a_mainpage.is_fsm1;
val->fsm2 = fsm_status_a_mainpage.is_fsm2;
val->fsm3 = fsm_status_a_mainpage.is_fsm3;
@@ -9917,7 +11730,6 @@ int32_t lsm6dso_all_sources_get(stmdev_ctx_t *ctx,
val->fsm6 = fsm_status_a_mainpage.is_fsm6;
val->fsm7 = fsm_status_a_mainpage.is_fsm7;
val->fsm8 = fsm_status_a_mainpage.is_fsm8;
-
val->fsm9 = fsm_status_b_mainpage.is_fsm9;
val->fsm10 = fsm_status_b_mainpage.is_fsm10;
val->fsm11 = fsm_status_b_mainpage.is_fsm11;
@@ -9926,25 +11738,31 @@ int32_t lsm6dso_all_sources_get(stmdev_ctx_t *ctx,
val->fsm14 = fsm_status_b_mainpage.is_fsm14;
val->fsm15 = fsm_status_b_mainpage.is_fsm15;
val->fsm16 = fsm_status_b_mainpage.is_fsm16;
+ }
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_MASTER_MAINPAGE, reg, 3);
+ }
+
+ if (ret == 0)
+ {
+ bytecpy((uint8_t *)&status_master_mainpage, ®[0]);
+ bytecpy((uint8_t *)&fifo_status1, ®[1]);
+ bytecpy((uint8_t *)&fifo_status2, ®[2]);
val->sh_endop = status_master_mainpage.sens_hub_endop;
val->sh_slave0_nack = status_master_mainpage.slave0_nack;
val->sh_slave1_nack = status_master_mainpage.slave1_nack;
val->sh_slave2_nack = status_master_mainpage.slave2_nack;
val->sh_slave3_nack = status_master_mainpage.slave3_nack;
val->sh_wr_once = status_master_mainpage.wr_once_done;
-
- val->fifo_diff = (256U * fifo_status2.diff_fifo) + fifo_status1.diff_fifo;
-
+ val->fifo_diff = (256U * fifo_status2.diff_fifo) +
+ fifo_status1.diff_fifo;
val->fifo_ovr_latched = fifo_status2.over_run_latched;
val->fifo_bdr = fifo_status2.counter_bdr_ia;
val->fifo_full = fifo_status2.fifo_full_ia;
val->fifo_ovr = fifo_status2.fifo_ovr_ia;
val->fifo_th = fifo_status2.fifo_wtm_ia;
-
- ctrl5_c.not_used_01 = PROPERTY_DISABLE;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
-
}
return ret;
@@ -9953,16 +11771,17 @@ int32_t lsm6dso_all_sources_get(stmdev_ctx_t *ctx,
/**
* @brief Sensor conversion parameters selection.[set]
*
- * @param ctx communication interface handler. Use NULL to ingnore
+ * @param ctx communication interface handler. Use NULL to ignore
* this interface.(ptr)
* @param aux_ctx auxiliary communication interface handler. Use NULL
- * to ingnore this interface.(ptr)
+ * to ignore this interface.(ptr)
* @param val set the sensor conversion parameters by checking
* the constraints of the device.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
- lsm6dso_md_t *val)
+ lsm6dso_md_t *val)
{
lsm6dso_func_cfg_access_t func_cfg_access;
lsm6dso_ctrl1_ois_t ctrl1_ois;
@@ -9985,107 +11804,148 @@ int32_t lsm6dso_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
int32_t ret;
ret = 0;
-
+ /* FIXME: Remove warnings with STM32CubeIDE */
+ ctrl3_c.not_used_01 = 0;
+ ctrl4_c.not_used_01 = 0;
/* reading input configuration */
- xl_hm_mode = ( (uint8_t)val->ui.xl.odr & 0x10U ) >> 4;
- xl_ulp_en = ( (uint8_t)val->ui.xl.odr & 0x20U ) >> 5;
+ xl_hm_mode = ((uint8_t)val->ui.xl.odr & 0x10U) >> 4;
+ xl_ulp_en = ((uint8_t)val->ui.xl.odr & 0x20U) >> 5;
odr_xl = (uint8_t)val->ui.xl.odr & 0x0FU;
/* if enable xl ultra low power mode disable gy and OIS chain */
- if (xl_ulp_en == PROPERTY_ENABLE) {
+ if (xl_ulp_en == PROPERTY_ENABLE)
+ {
val->ois.xl.odr = LSM6DSO_XL_OIS_OFF;
val->ois.gy.odr = LSM6DSO_GY_OIS_OFF;
val->ui.gy.odr = LSM6DSO_GY_UI_OFF;
}
+
/* if OIS xl is enabled also gyro OIS is enabled */
- if (val->ois.xl.odr == LSM6DSO_XL_OIS_6667Hz_HP){
+ if (val->ois.xl.odr == LSM6DSO_XL_OIS_6667Hz_HP)
+ {
val->ois.gy.odr = LSM6DSO_GY_OIS_6667Hz_HP;
}
- g_hm_mode = ( (uint8_t)val->ui.gy.odr & 0x10U ) >> 4;
+
+ g_hm_mode = ((uint8_t)val->ui.gy.odr & 0x10U) >> 4;
odr_gy = (uint8_t)val->ui.gy.odr & 0x0FU;
/* reading registers to be configured */
- if( ctx != NULL ) {
+ if (ctx != NULL)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, reg, 8);
- bytecpy(( uint8_t*)&ctrl1_xl, ®[0]);
- bytecpy(( uint8_t*)&ctrl2_g, ®[1]);
- bytecpy(( uint8_t*)&ctrl3_c, ®[2]);
- bytecpy(( uint8_t*)&ctrl4_c, ®[3]);
- bytecpy(( uint8_t*)&ctrl5_c, ®[4]);
- bytecpy(( uint8_t*)&ctrl6_c, ®[5]);
- bytecpy(( uint8_t*)&ctrl7_g, ®[6]);
- bytecpy(( uint8_t*)&ctrl8_xl, ®[7]);
- if ( ret == 0 ) {
+ bytecpy((uint8_t *)&ctrl1_xl, ®[0]);
+ bytecpy((uint8_t *)&ctrl2_g, ®[1]);
+ bytecpy((uint8_t *)&ctrl3_c, ®[2]);
+ bytecpy((uint8_t *)&ctrl4_c, ®[3]);
+ bytecpy((uint8_t *)&ctrl5_c, ®[4]);
+ bytecpy((uint8_t *)&ctrl6_c, ®[5]);
+ bytecpy((uint8_t *)&ctrl7_g, ®[6]);
+ bytecpy((uint8_t *)&ctrl8_xl, ®[7]);
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
+ (uint8_t *)&func_cfg_access, 1);
}
+
/* if toggle xl ultra low power mode, turn off xl before reconfigure */
- if (ctrl5_c.xl_ulp_en != xl_ulp_en) {
- ctrl1_xl.odr_xl = (uint8_t) 0x00U;
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
+ if (ctrl5_c.xl_ulp_en != xl_ulp_en)
+ {
+ ctrl1_xl.odr_xl = (uint8_t) 0x00U;
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
}
}
/* reading OIS registers to be configured */
- if( aux_ctx != NULL ) {
- if (ret == 0) {
+ if (aux_ctx != NULL)
+ {
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_CTRL1_OIS, reg, 3);
}
- bytecpy(( uint8_t*)&ctrl1_ois, ®[0]);
- bytecpy(( uint8_t*)&ctrl2_ois, ®[1]);
- bytecpy(( uint8_t*)&ctrl3_ois, ®[2]);
+
+ bytecpy((uint8_t *)&ctrl1_ois, ®[0]);
+ bytecpy((uint8_t *)&ctrl2_ois, ®[1]);
+ bytecpy((uint8_t *)&ctrl3_ois, ®[2]);
}
- else {
- if( ctx != NULL ) {
- if (ret == 0) {
+
+ else
+ {
+ if (ctx != NULL)
+ {
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, reg, 3);
}
- bytecpy(( uint8_t*)&ctrl1_ois, ®[0]);
- bytecpy(( uint8_t*)&ctrl2_ois, ®[1]);
- bytecpy(( uint8_t*)&ctrl3_ois, ®[2]);
+
+ bytecpy((uint8_t *)&ctrl1_ois, ®[0]);
+ bytecpy((uint8_t *)&ctrl2_ois, ®[1]);
+ bytecpy((uint8_t *)&ctrl3_ois, ®[2]);
}
}
/* Check the Finite State Machine data rate constraints */
- if (val->fsm.sens != LSM6DSO_FSM_DISABLE) {
- switch (val->fsm.odr) {
+ if (val->fsm.sens != LSM6DSO_FSM_DISABLE)
+ {
+ switch (val->fsm.odr)
+ {
case LSM6DSO_FSM_12Hz5:
- if ( (val->fsm.sens != LSM6DSO_FSM_GY) && (odr_xl == 0x00U) ) {
+ if ((val->fsm.sens != LSM6DSO_FSM_GY) && (odr_xl == 0x00U))
+ {
odr_xl = 0x01U;
}
- if ( (val->fsm.sens != LSM6DSO_FSM_XL) && (odr_gy == 0x00U) ) {
+
+ if ((val->fsm.sens != LSM6DSO_FSM_XL) && (odr_gy == 0x00U))
+ {
xl_ulp_en = PROPERTY_DISABLE;
odr_gy = 0x01U;
}
+
break;
+
case LSM6DSO_FSM_26Hz:
- if ( (val->fsm.sens != LSM6DSO_FSM_GY) && (odr_xl < 0x02U) ) {
+ if ((val->fsm.sens != LSM6DSO_FSM_GY) && (odr_xl < 0x02U))
+ {
odr_xl = 0x02U;
}
- if ( (val->fsm.sens != LSM6DSO_FSM_XL) && (odr_gy < 0x02U) ) {
+
+ if ((val->fsm.sens != LSM6DSO_FSM_XL) && (odr_gy < 0x02U))
+ {
xl_ulp_en = PROPERTY_DISABLE;
odr_gy = 0x02U;
}
+
break;
+
case LSM6DSO_FSM_52Hz:
- if ( (val->fsm.sens != LSM6DSO_FSM_GY) && (odr_xl < 0x03U) ) {
+ if ((val->fsm.sens != LSM6DSO_FSM_GY) && (odr_xl < 0x03U))
+ {
odr_xl = 0x03U;
}
- if ( (val->fsm.sens != LSM6DSO_FSM_XL) && (odr_gy < 0x03U) ) {
+
+ if ((val->fsm.sens != LSM6DSO_FSM_XL) && (odr_gy < 0x03U))
+ {
xl_ulp_en = PROPERTY_DISABLE;
odr_gy = 0x03U;
}
+
break;
+
case LSM6DSO_FSM_104Hz:
- if ( (val->fsm.sens != LSM6DSO_FSM_GY) && (odr_xl < 0x04U) ) {
+ if ((val->fsm.sens != LSM6DSO_FSM_GY) && (odr_xl < 0x04U))
+ {
odr_xl = 0x04U;
}
- if ( (val->fsm.sens != LSM6DSO_FSM_XL) && (odr_gy < 0x04U) ) {
+
+ if ((val->fsm.sens != LSM6DSO_FSM_XL) && (odr_gy < 0x04U))
+ {
xl_ulp_en = PROPERTY_DISABLE;
odr_gy = 0x04U;
}
+
break;
+
default:
odr_xl = 0x00U;
odr_gy = 0x00U;
@@ -10094,132 +11954,173 @@ int32_t lsm6dso_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
}
/* Updating the accelerometer data rate configuration */
- switch ( ( ctrl5_c.xl_ulp_en << 5 ) | ( ctrl6_c.xl_hm_mode << 4 ) |
- ctrl1_xl.odr_xl ) {
+ switch ((ctrl5_c.xl_ulp_en << 5) | (ctrl6_c.xl_hm_mode << 4) |
+ ctrl1_xl.odr_xl)
+ {
case LSM6DSO_XL_UI_OFF:
val->ui.xl.odr = LSM6DSO_XL_UI_OFF;
break;
+
case LSM6DSO_XL_UI_12Hz5_HP:
val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_HP;
break;
+
case LSM6DSO_XL_UI_26Hz_HP:
val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_HP;
break;
+
case LSM6DSO_XL_UI_52Hz_HP:
val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_HP;
break;
+
case LSM6DSO_XL_UI_104Hz_HP:
val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_HP;
break;
+
case LSM6DSO_XL_UI_208Hz_HP:
val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_HP;
break;
+
case LSM6DSO_XL_UI_416Hz_HP:
val->ui.xl.odr = LSM6DSO_XL_UI_416Hz_HP;
break;
+
case LSM6DSO_XL_UI_833Hz_HP:
val->ui.xl.odr = LSM6DSO_XL_UI_833Hz_HP;
break;
+
case LSM6DSO_XL_UI_1667Hz_HP:
val->ui.xl.odr = LSM6DSO_XL_UI_1667Hz_HP;
break;
+
case LSM6DSO_XL_UI_3333Hz_HP:
val->ui.xl.odr = LSM6DSO_XL_UI_3333Hz_HP;
break;
+
case LSM6DSO_XL_UI_6667Hz_HP:
val->ui.xl.odr = LSM6DSO_XL_UI_6667Hz_HP;
break;
+
case LSM6DSO_XL_UI_1Hz6_LP:
val->ui.xl.odr = LSM6DSO_XL_UI_1Hz6_LP;
break;
+
case LSM6DSO_XL_UI_12Hz5_LP:
val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_LP;
break;
+
case LSM6DSO_XL_UI_26Hz_LP:
val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_LP;
break;
+
case LSM6DSO_XL_UI_52Hz_LP:
val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_LP;
break;
+
case LSM6DSO_XL_UI_104Hz_NM:
val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_NM;
break;
+
case LSM6DSO_XL_UI_208Hz_NM:
val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_NM;
break;
+
case LSM6DSO_XL_UI_1Hz6_ULP:
val->ui.xl.odr = LSM6DSO_XL_UI_1Hz6_ULP;
break;
+
case LSM6DSO_XL_UI_12Hz5_ULP:
val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_ULP;
break;
+
case LSM6DSO_XL_UI_26Hz_ULP:
val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_ULP;
break;
+
case LSM6DSO_XL_UI_52Hz_ULP:
val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_ULP;
break;
+
case LSM6DSO_XL_UI_104Hz_ULP:
val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_ULP;
break;
+
case LSM6DSO_XL_UI_208Hz_ULP:
val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_ULP;
break;
+
default:
val->ui.xl.odr = LSM6DSO_XL_UI_OFF;
break;
}
/* Updating the accelerometer data rate configuration */
- switch ( (ctrl7_g.g_hm_mode << 4) | ctrl2_g.odr_g) {
+ switch ((ctrl7_g.g_hm_mode << 4) | ctrl2_g.odr_g)
+ {
case LSM6DSO_GY_UI_OFF:
val->ui.gy.odr = LSM6DSO_GY_UI_OFF;
break;
+
case LSM6DSO_GY_UI_12Hz5_LP:
val->ui.gy.odr = LSM6DSO_GY_UI_12Hz5_LP;
break;
+
case LSM6DSO_GY_UI_12Hz5_HP:
val->ui.gy.odr = LSM6DSO_GY_UI_12Hz5_HP;
break;
+
case LSM6DSO_GY_UI_26Hz_LP:
val->ui.gy.odr = LSM6DSO_GY_UI_26Hz_LP;
break;
+
case LSM6DSO_GY_UI_26Hz_HP:
val->ui.gy.odr = LSM6DSO_GY_UI_26Hz_HP;
break;
+
case LSM6DSO_GY_UI_52Hz_LP:
val->ui.gy.odr = LSM6DSO_GY_UI_52Hz_LP;
break;
+
case LSM6DSO_GY_UI_52Hz_HP:
val->ui.gy.odr = LSM6DSO_GY_UI_52Hz_HP;
break;
+
case LSM6DSO_GY_UI_104Hz_NM:
val->ui.gy.odr = LSM6DSO_GY_UI_104Hz_NM;
break;
+
case LSM6DSO_GY_UI_104Hz_HP:
val->ui.gy.odr = LSM6DSO_GY_UI_104Hz_HP;
break;
+
case LSM6DSO_GY_UI_208Hz_NM:
val->ui.gy.odr = LSM6DSO_GY_UI_208Hz_NM;
break;
+
case LSM6DSO_GY_UI_208Hz_HP:
val->ui.gy.odr = LSM6DSO_GY_UI_208Hz_HP;
break;
+
case LSM6DSO_GY_UI_416Hz_HP:
val->ui.gy.odr = LSM6DSO_GY_UI_416Hz_HP;
break;
+
case LSM6DSO_GY_UI_833Hz_HP:
val->ui.gy.odr = LSM6DSO_GY_UI_833Hz_HP;
break;
+
case LSM6DSO_GY_UI_1667Hz_HP:
val->ui.gy.odr = LSM6DSO_GY_UI_1667Hz_HP;
break;
+
case LSM6DSO_GY_UI_3333Hz_HP:
val->ui.gy.odr = LSM6DSO_GY_UI_3333Hz_HP;
break;
+
case LSM6DSO_GY_UI_6667Hz_HP:
val->ui.gy.odr = LSM6DSO_GY_UI_6667Hz_HP;
break;
+
default:
val->ui.gy.odr = LSM6DSO_GY_UI_OFF;
break;
@@ -10227,8 +12128,9 @@ int32_t lsm6dso_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
/* Check accelerometer full scale constraints */
/* Full scale of 16g must be the same for UI and OIS */
- if ( (val->ui.xl.fs == LSM6DSO_XL_UI_16g) ||
- (val->ois.xl.fs == LSM6DSO_XL_OIS_16g) ){
+ if ((val->ui.xl.fs == LSM6DSO_XL_UI_16g) ||
+ (val->ois.xl.fs == LSM6DSO_XL_OIS_16g))
+ {
val->ui.xl.fs = LSM6DSO_XL_UI_16g;
val->ois.xl.fs = LSM6DSO_XL_OIS_16g;
}
@@ -10236,32 +12138,40 @@ int32_t lsm6dso_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
/* prapare new configuration */
/* Full scale of 16g must be the same for UI and OIS */
- if (val->ui.xl.fs == LSM6DSO_XL_UI_16g) {
+ if (val->ui.xl.fs == LSM6DSO_XL_UI_16g)
+ {
ctrl8_xl.xl_fs_mode = PROPERTY_DISABLE;
}
- else {
+
+ else
+ {
ctrl8_xl.xl_fs_mode = PROPERTY_ENABLE;
}
/* OIS new configuration */
ctrl7_g.ois_on_en = val->ois.ctrl_md & 0x01U;
- switch (val->ois.ctrl_md) {
+ switch (val->ois.ctrl_md)
+ {
case LSM6DSO_OIS_ONLY_AUX:
ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
- ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr | (uint8_t)val->ois.xl.odr;
+ ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr |
+ (uint8_t)val->ois.xl.odr;
ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr;
ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
break;
+
case LSM6DSO_OIS_MIXED:
ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
ctrl7_g.ois_on = (uint8_t)val->ois.gy.odr | (uint8_t)val->ois.xl.odr;
ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr;
ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
break;
+
default:
ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
- ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr | (uint8_t)val->ois.xl.odr;
+ ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr |
+ (uint8_t)val->ois.xl.odr;
ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr;
ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
break;
@@ -10277,30 +12187,38 @@ int32_t lsm6dso_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
ctrl2_g.fs_g = (uint8_t) val->ui.gy.fs;
/* writing checked configuration */
- if( ctx != NULL ) {
- bytecpy(®[0], ( uint8_t*)&ctrl1_xl);
- bytecpy(®[1], ( uint8_t*)&ctrl2_g);
- bytecpy(®[2], ( uint8_t*)&ctrl3_c);
- bytecpy(®[3], ( uint8_t*)&ctrl4_c);
- bytecpy(®[4], ( uint8_t*)&ctrl5_c);
- bytecpy(®[5], ( uint8_t*)&ctrl6_c);
- bytecpy(®[6], ( uint8_t*)&ctrl7_g);
- bytecpy(®[7], ( uint8_t*)&ctrl8_xl);
- if ( ret == 0 ) {
- ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)®, 8);
+ if (ctx != NULL)
+ {
+ bytecpy(®[0], (uint8_t *)&ctrl1_xl);
+ bytecpy(®[1], (uint8_t *)&ctrl2_g);
+ bytecpy(®[2], (uint8_t *)&ctrl3_c);
+ bytecpy(®[3], (uint8_t *)&ctrl4_c);
+ bytecpy(®[4], (uint8_t *)&ctrl5_c);
+ bytecpy(®[5], (uint8_t *)&ctrl6_c);
+ bytecpy(®[6], (uint8_t *)&ctrl7_g);
+ bytecpy(®[7], (uint8_t *)&ctrl8_xl);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 8);
}
- if ( ret == 0 ) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_write_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
+ (uint8_t *)&func_cfg_access, 1);
}
}
/* writing OIS checked configuration */
- if( aux_ctx != NULL ) {
- bytecpy(®[0], ( uint8_t*)&ctrl1_ois);
- bytecpy(®[1], ( uint8_t*)&ctrl2_ois);
- bytecpy(®[2], ( uint8_t*)&ctrl3_ois);
- if (ret == 0) {
+ if (aux_ctx != NULL)
+ {
+ bytecpy(®[0], (uint8_t *)&ctrl1_ois);
+ bytecpy(®[1], (uint8_t *)&ctrl2_ois);
+ bytecpy(®[2], (uint8_t *)&ctrl3_ois);
+
+ if (ret == 0)
+ {
ret = lsm6dso_write_reg(aux_ctx, LSM6DSO_CTRL1_OIS, reg, 3);
}
}
@@ -10311,17 +12229,17 @@ int32_t lsm6dso_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
/**
* @brief Sensor conversion parameters selection.[get]
*
- * @param ctx communication interface handler. Use NULL to ingnore
+ * @param ctx communication interface handler. Use NULL to ignore
* this interface.(ptr)
* @param aux_ctx auxiliary communication interface handler. Use NULL
- * to ingnore this interface.(ptr)
+ * to ignore this interface.(ptr)
* @param val get the sensor conversion parameters.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
- lsm6dso_md_t *val)
+ lsm6dso_md_t *val)
{
-
lsm6dso_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
lsm6dso_func_cfg_access_t func_cfg_access;
lsm6dso_emb_func_en_b_t emb_func_en_b;
@@ -10337,402 +12255,531 @@ int32_t lsm6dso_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
lsm6dso_ctrl5_c_t ctrl5_c;
lsm6dso_ctrl6_c_t ctrl6_c;
lsm6dso_ctrl7_g_t ctrl7_g;
-
uint8_t reg[8];
int32_t ret;
ret = 0;
/* reading the registers of the device */
- if( ctx != NULL ) {
+ if (ctx != NULL)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, reg, 7);
- bytecpy(( uint8_t*)&ctrl1_xl, ®[0]);
- bytecpy(( uint8_t*)&ctrl2_g, ®[1]);
- bytecpy(( uint8_t*)&ctrl3_c, ®[2]);
- bytecpy(( uint8_t*)&ctrl4_c, ®[3]);
- bytecpy(( uint8_t*)&ctrl5_c, ®[4]);
- bytecpy(( uint8_t*)&ctrl6_c, ®[5]);
- bytecpy(( uint8_t*)&ctrl7_g, ®[6]);
- if ( ret == 0 ) {
+ bytecpy((uint8_t *)&ctrl1_xl, ®[0]);
+ bytecpy((uint8_t *)&ctrl2_g, ®[1]);
+ bytecpy((uint8_t *)&ctrl3_c, ®[2]);
+ bytecpy((uint8_t *)&ctrl4_c, ®[3]);
+ bytecpy((uint8_t *)&ctrl5_c, ®[4]);
+ bytecpy((uint8_t *)&ctrl6_c, ®[5]);
+ bytecpy((uint8_t *)&ctrl7_g, ®[6]);
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
+ (uint8_t *)&func_cfg_access, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B, reg, 1);
- bytecpy(( uint8_t*)&emb_func_odr_cfg_b, ®[0]);
+ bytecpy((uint8_t *)&emb_func_odr_cfg_b, ®[0]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_ENABLE_A, reg, 2);
- bytecpy(( uint8_t*)&fsm_enable_a, ®[0]);
- bytecpy(( uint8_t*)&fsm_enable_b, ®[1]);
+ bytecpy((uint8_t *)&fsm_enable_a, ®[0]);
+ bytecpy((uint8_t *)&fsm_enable_b, ®[1]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
}
}
- if( aux_ctx != NULL ) {
- if (ret == 0) {
+ if (aux_ctx != NULL)
+ {
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_CTRL1_OIS, reg, 3);
}
- bytecpy(( uint8_t*)&ctrl1_ois, ®[0]);
- bytecpy(( uint8_t*)&ctrl2_ois, ®[1]);
- bytecpy(( uint8_t*)&ctrl3_ois, ®[2]);
+
+ bytecpy((uint8_t *)&ctrl1_ois, ®[0]);
+ bytecpy((uint8_t *)&ctrl2_ois, ®[1]);
+ bytecpy((uint8_t *)&ctrl3_ois, ®[2]);
}
- else {
- if( ctx != NULL ) {
- if (ret == 0) {
+
+ else
+ {
+ if (ctx != NULL)
+ {
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, reg, 3);
}
- bytecpy(( uint8_t*)&ctrl1_ois, ®[0]);
- bytecpy(( uint8_t*)&ctrl2_ois, ®[1]);
- bytecpy(( uint8_t*)&ctrl3_ois, ®[2]);
+
+ bytecpy((uint8_t *)&ctrl1_ois, ®[0]);
+ bytecpy((uint8_t *)&ctrl2_ois, ®[1]);
+ bytecpy((uint8_t *)&ctrl3_ois, ®[2]);
}
}
-
+
/* fill the input structure */
/* get accelerometer configuration */
- switch ( (ctrl5_c.xl_ulp_en << 5) | (ctrl6_c.xl_hm_mode << 4) |
- ctrl1_xl.odr_xl ) {
+ switch ((ctrl5_c.xl_ulp_en << 5) | (ctrl6_c.xl_hm_mode << 4) |
+ ctrl1_xl.odr_xl)
+ {
case LSM6DSO_XL_UI_OFF:
val->ui.xl.odr = LSM6DSO_XL_UI_OFF;
break;
+
case LSM6DSO_XL_UI_12Hz5_HP:
val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_HP;
break;
+
case LSM6DSO_XL_UI_26Hz_HP:
val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_HP;
break;
+
case LSM6DSO_XL_UI_52Hz_HP:
val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_HP;
break;
+
case LSM6DSO_XL_UI_104Hz_HP:
val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_HP;
break;
+
case LSM6DSO_XL_UI_208Hz_HP:
val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_HP;
break;
+
case LSM6DSO_XL_UI_416Hz_HP:
val->ui.xl.odr = LSM6DSO_XL_UI_416Hz_HP;
break;
+
case LSM6DSO_XL_UI_833Hz_HP:
val->ui.xl.odr = LSM6DSO_XL_UI_833Hz_HP;
break;
+
case LSM6DSO_XL_UI_1667Hz_HP:
val->ui.xl.odr = LSM6DSO_XL_UI_1667Hz_HP;
break;
+
case LSM6DSO_XL_UI_3333Hz_HP:
val->ui.xl.odr = LSM6DSO_XL_UI_3333Hz_HP;
break;
+
case LSM6DSO_XL_UI_6667Hz_HP:
val->ui.xl.odr = LSM6DSO_XL_UI_6667Hz_HP;
break;
+
case LSM6DSO_XL_UI_1Hz6_LP:
val->ui.xl.odr = LSM6DSO_XL_UI_1Hz6_LP;
break;
+
case LSM6DSO_XL_UI_12Hz5_LP:
val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_LP;
break;
+
case LSM6DSO_XL_UI_26Hz_LP:
val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_LP;
break;
+
case LSM6DSO_XL_UI_52Hz_LP:
val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_LP;
break;
+
case LSM6DSO_XL_UI_104Hz_NM:
val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_NM;
break;
+
case LSM6DSO_XL_UI_208Hz_NM:
val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_NM;
break;
+
case LSM6DSO_XL_UI_1Hz6_ULP:
val->ui.xl.odr = LSM6DSO_XL_UI_1Hz6_ULP;
break;
+
case LSM6DSO_XL_UI_12Hz5_ULP:
val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_ULP;
break;
+
case LSM6DSO_XL_UI_26Hz_ULP:
val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_ULP;
break;
+
case LSM6DSO_XL_UI_52Hz_ULP:
val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_ULP;
break;
+
case LSM6DSO_XL_UI_104Hz_ULP:
val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_ULP;
break;
+
case LSM6DSO_XL_UI_208Hz_ULP:
val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_ULP;
break;
+
default:
val->ui.xl.odr = LSM6DSO_XL_UI_OFF;
break;
}
- switch ( ctrl1_xl.fs_xl ) {
+ switch (ctrl1_xl.fs_xl)
+ {
case LSM6DSO_XL_UI_2g:
val->ui.xl.fs = LSM6DSO_XL_UI_2g;
break;
+
case LSM6DSO_XL_UI_4g:
val->ui.xl.fs = LSM6DSO_XL_UI_4g;
break;
+
case LSM6DSO_XL_UI_8g:
val->ui.xl.fs = LSM6DSO_XL_UI_8g;
break;
+
case LSM6DSO_XL_UI_16g:
val->ui.xl.fs = LSM6DSO_XL_UI_16g;
break;
+
default:
val->ui.xl.fs = LSM6DSO_XL_UI_2g;
break;
}
/* get gyroscope configuration */
- switch ( (ctrl7_g.g_hm_mode << 4) | ctrl2_g.odr_g) {
+ switch ((ctrl7_g.g_hm_mode << 4) | ctrl2_g.odr_g)
+ {
case LSM6DSO_GY_UI_OFF:
val->ui.gy.odr = LSM6DSO_GY_UI_OFF;
break;
+
case LSM6DSO_GY_UI_12Hz5_LP:
val->ui.gy.odr = LSM6DSO_GY_UI_12Hz5_LP;
break;
+
case LSM6DSO_GY_UI_12Hz5_HP:
val->ui.gy.odr = LSM6DSO_GY_UI_12Hz5_HP;
break;
+
case LSM6DSO_GY_UI_26Hz_LP:
val->ui.gy.odr = LSM6DSO_GY_UI_26Hz_LP;
break;
+
case LSM6DSO_GY_UI_26Hz_HP:
val->ui.gy.odr = LSM6DSO_GY_UI_26Hz_HP;
break;
+
case LSM6DSO_GY_UI_52Hz_LP:
val->ui.gy.odr = LSM6DSO_GY_UI_52Hz_LP;
break;
+
case LSM6DSO_GY_UI_52Hz_HP:
val->ui.gy.odr = LSM6DSO_GY_UI_52Hz_HP;
break;
+
case LSM6DSO_GY_UI_104Hz_NM:
val->ui.gy.odr = LSM6DSO_GY_UI_104Hz_NM;
break;
+
case LSM6DSO_GY_UI_104Hz_HP:
val->ui.gy.odr = LSM6DSO_GY_UI_104Hz_HP;
break;
+
case LSM6DSO_GY_UI_208Hz_NM:
val->ui.gy.odr = LSM6DSO_GY_UI_208Hz_NM;
break;
+
case LSM6DSO_GY_UI_208Hz_HP:
val->ui.gy.odr = LSM6DSO_GY_UI_208Hz_HP;
break;
+
case LSM6DSO_GY_UI_416Hz_HP:
val->ui.gy.odr = LSM6DSO_GY_UI_416Hz_HP;
break;
+
case LSM6DSO_GY_UI_833Hz_HP:
val->ui.gy.odr = LSM6DSO_GY_UI_833Hz_HP;
break;
+
case LSM6DSO_GY_UI_1667Hz_HP:
val->ui.gy.odr = LSM6DSO_GY_UI_1667Hz_HP;
break;
+
case LSM6DSO_GY_UI_3333Hz_HP:
val->ui.gy.odr = LSM6DSO_GY_UI_3333Hz_HP;
break;
+
case LSM6DSO_GY_UI_6667Hz_HP:
val->ui.gy.odr = LSM6DSO_GY_UI_6667Hz_HP;
break;
+
default:
val->ui.gy.odr = LSM6DSO_GY_UI_OFF;
break;
}
- switch (ctrl2_g.fs_g) {
+ switch (ctrl2_g.fs_g)
+ {
case LSM6DSO_GY_UI_125dps:
val->ui.gy.fs = LSM6DSO_GY_UI_125dps;
break;
+
case LSM6DSO_GY_UI_250dps:
val->ui.gy.fs = LSM6DSO_GY_UI_250dps;
break;
+
case LSM6DSO_GY_UI_500dps:
val->ui.gy.fs = LSM6DSO_GY_UI_500dps;
break;
+
case LSM6DSO_GY_UI_1000dps:
val->ui.gy.fs = LSM6DSO_GY_UI_1000dps;
break;
+
case LSM6DSO_GY_UI_2000dps:
val->ui.gy.fs = LSM6DSO_GY_UI_2000dps;
break;
+
default:
val->ui.gy.fs = LSM6DSO_GY_UI_125dps;
break;
}
/* get finite state machine configuration */
- if ( (fsm_enable_a.fsm1_en | fsm_enable_a.fsm2_en | fsm_enable_a.fsm3_en |
- fsm_enable_a.fsm4_en | fsm_enable_a.fsm5_en | fsm_enable_a.fsm6_en |
- fsm_enable_a.fsm7_en | fsm_enable_a.fsm8_en | fsm_enable_b.fsm9_en |
- fsm_enable_b.fsm10_en | fsm_enable_b.fsm11_en |
- fsm_enable_b.fsm12_en | fsm_enable_b.fsm13_en |
- fsm_enable_b.fsm14_en | fsm_enable_b.fsm15_en |
- fsm_enable_b.fsm16_en) == PROPERTY_ENABLE ){
- switch (emb_func_odr_cfg_b.fsm_odr) {
+ if ((fsm_enable_a.fsm1_en | fsm_enable_a.fsm2_en |
+ fsm_enable_a.fsm3_en |
+ fsm_enable_a.fsm4_en | fsm_enable_a.fsm5_en | fsm_enable_a.fsm6_en |
+ fsm_enable_a.fsm7_en | fsm_enable_a.fsm8_en | fsm_enable_b.fsm9_en |
+ fsm_enable_b.fsm10_en | fsm_enable_b.fsm11_en |
+ fsm_enable_b.fsm12_en | fsm_enable_b.fsm13_en |
+ fsm_enable_b.fsm14_en | fsm_enable_b.fsm15_en |
+ fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
+ {
+ switch (emb_func_odr_cfg_b.fsm_odr)
+ {
case LSM6DSO_FSM_12Hz5:
val->fsm.odr = LSM6DSO_FSM_12Hz5;
break;
+
case LSM6DSO_FSM_26Hz:
val->fsm.odr = LSM6DSO_FSM_26Hz;
break;
+
case LSM6DSO_FSM_52Hz:
val->fsm.odr = LSM6DSO_FSM_52Hz;
break;
+
case LSM6DSO_FSM_104Hz:
val->fsm.odr = LSM6DSO_FSM_104Hz;
break;
+
default:
val->fsm.odr = LSM6DSO_FSM_12Hz5;
break;
}
-
+
val->fsm.sens = LSM6DSO_FSM_XL_GY;
- if (val->ui.gy.odr == LSM6DSO_GY_UI_OFF) {
+
+ if (val->ui.gy.odr == LSM6DSO_GY_UI_OFF)
+ {
val->fsm.sens = LSM6DSO_FSM_XL;
}
- if (val->ui.xl.odr == LSM6DSO_XL_UI_OFF) {
+
+ if (val->ui.xl.odr == LSM6DSO_XL_UI_OFF)
+ {
val->fsm.sens = LSM6DSO_FSM_GY;
}
}
- else {
+
+ else
+ {
val->fsm.sens = LSM6DSO_FSM_DISABLE;
}
/* get ois configuration */
/* OIS configuration mode */
- switch ( ctrl7_g.ois_on_en ) {
+ switch (ctrl7_g.ois_on_en)
+ {
case LSM6DSO_OIS_ONLY_AUX:
- switch ( ctrl3_ois.fs_xl_ois ) {
+ switch (ctrl3_ois.fs_xl_ois)
+ {
case LSM6DSO_XL_OIS_2g:
val->ois.xl.fs = LSM6DSO_XL_OIS_2g;
break;
+
case LSM6DSO_XL_OIS_4g:
val->ois.xl.fs = LSM6DSO_XL_OIS_4g;
break;
+
case LSM6DSO_XL_OIS_8g:
val->ois.xl.fs = LSM6DSO_XL_OIS_8g;
break;
+
case LSM6DSO_XL_OIS_16g:
val->ois.xl.fs = LSM6DSO_XL_OIS_16g;
break;
+
default:
val->ois.xl.fs = LSM6DSO_XL_OIS_2g;
break;
}
- switch ( ctrl1_ois.mode4_en ) {
+
+ switch (ctrl1_ois.mode4_en)
+ {
case LSM6DSO_XL_OIS_OFF:
val->ois.xl.odr = LSM6DSO_XL_OIS_OFF;
break;
+
case LSM6DSO_XL_OIS_6667Hz_HP:
val->ois.xl.odr = LSM6DSO_XL_OIS_6667Hz_HP;
break;
+
default:
val->ois.xl.odr = LSM6DSO_XL_OIS_OFF;
break;
}
- switch ( ctrl1_ois.fs_g_ois ) {
+
+ switch (ctrl1_ois.fs_g_ois)
+ {
case LSM6DSO_GY_OIS_250dps:
val->ois.gy.fs = LSM6DSO_GY_OIS_250dps;
break;
+
case LSM6DSO_GY_OIS_500dps:
val->ois.gy.fs = LSM6DSO_GY_OIS_500dps;
break;
+
case LSM6DSO_GY_OIS_1000dps:
val->ois.gy.fs = LSM6DSO_GY_OIS_1000dps;
break;
+
case LSM6DSO_GY_OIS_2000dps:
val->ois.gy.fs = LSM6DSO_GY_OIS_2000dps;
break;
+
default:
val->ois.gy.fs = LSM6DSO_GY_OIS_250dps;
break;
}
- switch ( ctrl1_ois.ois_en_spi2 ) {
+
+ switch (ctrl1_ois.ois_en_spi2)
+ {
case LSM6DSO_GY_OIS_OFF:
val->ois.gy.odr = LSM6DSO_GY_OIS_OFF;
break;
+
case LSM6DSO_GY_OIS_6667Hz_HP:
val->ois.gy.odr = LSM6DSO_GY_OIS_6667Hz_HP;
break;
+
default:
val->ois.gy.odr = LSM6DSO_GY_OIS_OFF;
break;
}
+
val->ois.ctrl_md = LSM6DSO_OIS_ONLY_AUX;
break;
+
case LSM6DSO_OIS_MIXED:
- switch ( ctrl3_ois.fs_xl_ois ) {
+ switch (ctrl3_ois.fs_xl_ois)
+ {
case LSM6DSO_XL_OIS_2g:
val->ois.xl.fs = LSM6DSO_XL_OIS_2g;
break;
+
case LSM6DSO_XL_OIS_4g:
val->ois.xl.fs = LSM6DSO_XL_OIS_4g;
break;
+
case LSM6DSO_XL_OIS_8g:
val->ois.xl.fs = LSM6DSO_XL_OIS_8g;
break;
+
case LSM6DSO_XL_OIS_16g:
val->ois.xl.fs = LSM6DSO_XL_OIS_16g;
break;
+
default:
val->ois.xl.fs = LSM6DSO_XL_OIS_2g;
break;
}
- switch ( ctrl1_ois.mode4_en ) {
+
+ switch (ctrl1_ois.mode4_en)
+ {
case LSM6DSO_XL_OIS_OFF:
val->ois.xl.odr = LSM6DSO_XL_OIS_OFF;
break;
+
case LSM6DSO_XL_OIS_6667Hz_HP:
val->ois.xl.odr = LSM6DSO_XL_OIS_6667Hz_HP;
break;
+
default:
val->ois.xl.odr = LSM6DSO_XL_OIS_OFF;
break;
}
- switch ( ctrl1_ois.fs_g_ois ) {
+
+ switch (ctrl1_ois.fs_g_ois)
+ {
case LSM6DSO_GY_OIS_250dps:
val->ois.gy.fs = LSM6DSO_GY_OIS_250dps;
break;
+
case LSM6DSO_GY_OIS_500dps:
val->ois.gy.fs = LSM6DSO_GY_OIS_500dps;
break;
+
case LSM6DSO_GY_OIS_1000dps:
val->ois.gy.fs = LSM6DSO_GY_OIS_1000dps;
break;
+
case LSM6DSO_GY_OIS_2000dps:
val->ois.gy.fs = LSM6DSO_GY_OIS_2000dps;
break;
+
default:
val->ois.gy.fs = LSM6DSO_GY_OIS_250dps;
break;
}
- switch ( ctrl1_ois.ois_en_spi2 ) {
+
+ switch (ctrl1_ois.ois_en_spi2)
+ {
case LSM6DSO_GY_OIS_OFF:
val->ois.gy.odr = LSM6DSO_GY_OIS_OFF;
break;
+
case LSM6DSO_GY_OIS_6667Hz_HP:
val->ois.gy.odr = LSM6DSO_GY_OIS_6667Hz_HP;
break;
+
default:
val->ois.gy.odr = LSM6DSO_GY_OIS_OFF;
break;
}
+
val->ois.ctrl_md = LSM6DSO_OIS_MIXED;
break;
+
default:
ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
- ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr | (uint8_t)val->ois.xl.odr;
+ ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr |
+ (uint8_t)val->ois.xl.odr;
ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr;
ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
val->ois.ctrl_md = LSM6DSO_OIS_ONLY_AUX;
@@ -10747,51 +12794,63 @@ int32_t lsm6dso_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
*
* @param ctx communication interface handler.(ptr)
* @param md the sensor conversion parameters.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dso_data_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
- lsm6dso_md_t *md, lsm6dso_data_t *data)
+ lsm6dso_md_t *md, lsm6dso_data_t *data)
{
uint8_t buff[14];
int32_t ret;
+
uint8_t i;
uint8_t j;
-
ret = 0;
-
+
/* read data */
- if( ctx != NULL ) {
+ if (ctx != NULL)
+ {
ret = lsm6dso_read_reg(ctx, LSM6DSO_OUT_TEMP_L, buff, 14);
}
- j = 0;
+ j = 0;
/* temperature conversion */
- data->ui.heat.raw = (int16_t)buff[j+1U];
- data->ui.heat.raw = ( ((int16_t)data->ui.heat.raw * (int16_t)256) + (int16_t)buff[j] );
- j+=2U;
- data->ui.heat.deg_c = lsm6dso_from_lsb_to_celsius((int16_t)data->ui.heat.raw);
+ data->ui.heat.raw = (int16_t)buff[j + 1U];
+ data->ui.heat.raw = (((int16_t)data->ui.heat.raw * (int16_t)256) +
+ (int16_t)buff[j]);
+ j += 2U;
+ data->ui.heat.deg_c = lsm6dso_from_lsb_to_celsius((
+ int16_t)data->ui.heat.raw);
/* angular rate conversion */
- for (i = 0U; i < 3U; i++) {
- data->ui.gy.raw[i] = (int16_t)buff[j+1U];
+ for (i = 0U; i < 3U; i++)
+ {
+ data->ui.gy.raw[i] = (int16_t)buff[j + 1U];
data->ui.gy.raw[i] = (data->ui.gy.raw[i] * 256) + (int16_t) buff[j];
- j+=2U;
- switch ( md->ui.gy.fs ) {
+ j += 2U;
+
+ switch (md->ui.gy.fs)
+ {
case LSM6DSO_GY_UI_250dps:
data->ui.gy.mdps[i] = lsm6dso_from_fs250_to_mdps(data->ui.gy.raw[i]);
break;
+
case LSM6DSO_GY_UI_125dps:
data->ui.gy.mdps[i] = lsm6dso_from_fs125_to_mdps(data->ui.gy.raw[i]);
break;
+
case LSM6DSO_GY_UI_500dps:
data->ui.gy.mdps[i] = lsm6dso_from_fs500_to_mdps(data->ui.gy.raw[i]);
break;
+
case LSM6DSO_GY_UI_1000dps:
data->ui.gy.mdps[i] = lsm6dso_from_fs1000_to_mdps(data->ui.gy.raw[i]);
break;
+
case LSM6DSO_GY_UI_2000dps:
data->ui.gy.mdps[i] = lsm6dso_from_fs2000_to_mdps(data->ui.gy.raw[i]);
break;
+
default:
data->ui.gy.mdps[i] = 0.0f;
break;
@@ -10799,59 +12858,81 @@ int32_t lsm6dso_data_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
}
/* acceleration conversion */
- for (i = 0U; i < 3U; i++) {
- data->ui.xl.raw[i] = (int16_t)buff[j+1U];
+ for (i = 0U; i < 3U; i++)
+ {
+ data->ui.xl.raw[i] = (int16_t)buff[j + 1U];
data->ui.xl.raw[i] = (data->ui.xl.raw[i] * 256) + (int16_t) buff[j];
- j+=2U;
- switch ( md->ui.xl.fs ) {
+ j += 2U;
+
+ switch (md->ui.xl.fs)
+ {
case LSM6DSO_XL_UI_2g:
- data->ui.xl.mg[i] =lsm6dso_from_fs2_to_mg(data->ui.xl.raw[i]);
+ data->ui.xl.mg[i] = lsm6dso_from_fs2_to_mg(data->ui.xl.raw[i]);
break;
+
case LSM6DSO_XL_UI_4g:
- data->ui.xl.mg[i] =lsm6dso_from_fs4_to_mg(data->ui.xl.raw[i]);
+ data->ui.xl.mg[i] = lsm6dso_from_fs4_to_mg(data->ui.xl.raw[i]);
break;
+
case LSM6DSO_XL_UI_8g:
- data->ui.xl.mg[i] =lsm6dso_from_fs8_to_mg(data->ui.xl.raw[i]);
+ data->ui.xl.mg[i] = lsm6dso_from_fs8_to_mg(data->ui.xl.raw[i]);
break;
+
case LSM6DSO_XL_UI_16g:
- data->ui.xl.mg[i] =lsm6dso_from_fs16_to_mg(data->ui.xl.raw[i]);
+ data->ui.xl.mg[i] = lsm6dso_from_fs16_to_mg(data->ui.xl.raw[i]);
break;
+
default:
data->ui.xl.mg[i] = 0.0f;
break;
}
-
}
/* read data from ois chain */
- if (aux_ctx != NULL) {
- if (ret == 0) {
+ if (aux_ctx != NULL)
+ {
+ if (ret == 0)
+ {
ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_OUTX_L_G, buff, 12);
}
}
+
j = 0;
/* ois angular rate conversion */
- for (i = 0U; i < 3U; i++) {
- data->ois.gy.raw[i] = (int16_t) buff[j+1U];
+ for (i = 0U; i < 3U; i++)
+ {
+ data->ois.gy.raw[i] = (int16_t) buff[j + 1U];
data->ois.gy.raw[i] = (data->ois.gy.raw[i] * 256) + (int16_t) buff[j];
- j+=2U;
- switch ( md->ois.gy.fs ) {
+ j += 2U;
+
+ switch (md->ois.gy.fs)
+ {
case LSM6DSO_GY_UI_250dps:
- data->ois.gy.mdps[i] = lsm6dso_from_fs250_to_mdps(data->ois.gy.raw[i]);
+ data->ois.gy.mdps[i] = lsm6dso_from_fs250_to_mdps(
+ data->ois.gy.raw[i]);
break;
+
case LSM6DSO_GY_UI_125dps:
- data->ois.gy.mdps[i] = lsm6dso_from_fs125_to_mdps(data->ois.gy.raw[i]);
+ data->ois.gy.mdps[i] = lsm6dso_from_fs125_to_mdps(
+ data->ois.gy.raw[i]);
break;
+
case LSM6DSO_GY_UI_500dps:
- data->ois.gy.mdps[i] = lsm6dso_from_fs500_to_mdps(data->ois.gy.raw[i]);
+ data->ois.gy.mdps[i] = lsm6dso_from_fs500_to_mdps(
+ data->ois.gy.raw[i]);
break;
+
case LSM6DSO_GY_UI_1000dps:
- data->ois.gy.mdps[i] = lsm6dso_from_fs1000_to_mdps(data->ois.gy.raw[i]);
+ data->ois.gy.mdps[i] = lsm6dso_from_fs1000_to_mdps(
+ data->ois.gy.raw[i]);
break;
+
case LSM6DSO_GY_UI_2000dps:
- data->ois.gy.mdps[i] = lsm6dso_from_fs2000_to_mdps(data->ois.gy.raw[i]);
+ data->ois.gy.mdps[i] = lsm6dso_from_fs2000_to_mdps(
+ data->ois.gy.raw[i]);
break;
+
default:
data->ois.gy.mdps[i] = 0.0f;
break;
@@ -10859,23 +12940,30 @@ int32_t lsm6dso_data_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
}
/* ois acceleration conversion */
- for (i = 0U; i < 3U; i++) {
- data->ois.xl.raw[i] = (int16_t) buff[j+1U];
+ for (i = 0U; i < 3U; i++)
+ {
+ data->ois.xl.raw[i] = (int16_t) buff[j + 1U];
data->ois.xl.raw[i] = (data->ois.xl.raw[i] * 256) + (int16_t) buff[j];
- j+=2U;
- switch ( md->ois.xl.fs ) {
+ j += 2U;
+
+ switch (md->ois.xl.fs)
+ {
case LSM6DSO_XL_UI_2g:
- data->ois.xl.mg[i] =lsm6dso_from_fs2_to_mg(data->ois.xl.raw[i]);
+ data->ois.xl.mg[i] = lsm6dso_from_fs2_to_mg(data->ois.xl.raw[i]);
break;
+
case LSM6DSO_XL_UI_4g:
- data->ois.xl.mg[i] =lsm6dso_from_fs4_to_mg(data->ois.xl.raw[i]);
+ data->ois.xl.mg[i] = lsm6dso_from_fs4_to_mg(data->ois.xl.raw[i]);
break;
+
case LSM6DSO_XL_UI_8g:
- data->ois.xl.mg[i] =lsm6dso_from_fs8_to_mg(data->ois.xl.raw[i]);
+ data->ois.xl.mg[i] = lsm6dso_from_fs8_to_mg(data->ois.xl.raw[i]);
break;
+
case LSM6DSO_XL_UI_16g:
- data->ois.xl.mg[i] =lsm6dso_from_fs16_to_mg(data->ois.xl.raw[i]);
+ data->ois.xl.mg[i] = lsm6dso_from_fs16_to_mg(data->ois.xl.raw[i]);
break;
+
default:
data->ois.xl.mg[i] = 0.0f;
break;
@@ -10885,6 +12973,161 @@ int32_t lsm6dso_data_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
return ret;
}
+/**
+ * @brief Embedded functions.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of registers
+ * EMB_FUNC_EN_A e EMB_FUNC_EN_B.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lsm6dso_embedded_sens_set(stmdev_ctx_t *ctx,
+ lsm6dso_emb_sens_t *val)
+{
+ lsm6dso_emb_func_en_a_t emb_func_en_a;
+ lsm6dso_emb_func_en_b_t emb_func_en_b;
+ int32_t ret;
+
+ ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A,
+ (uint8_t *)&emb_func_en_a, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
+ (uint8_t *)&emb_func_en_b, 1);
+ emb_func_en_b.fsm_en = val->fsm;
+ emb_func_en_a.tilt_en = val->tilt;
+ emb_func_en_a.pedo_en = val->step;
+ emb_func_en_b.pedo_adv_en = val->step_adv;
+ emb_func_en_a.sign_motion_en = val->sig_mot;
+ emb_func_en_b.fifo_compr_en = val->fifo_compr;
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_A,
+ (uint8_t *)&emb_func_en_a, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
+ (uint8_t *)&emb_func_en_b, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Embedded functions.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val get the values of registers
+ * EMB_FUNC_EN_A e EMB_FUNC_EN_B.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lsm6dso_embedded_sens_get(stmdev_ctx_t *ctx,
+ lsm6dso_emb_sens_t *emb_sens)
+{
+ lsm6dso_emb_func_en_a_t emb_func_en_a;
+ lsm6dso_emb_func_en_b_t emb_func_en_b;
+ int32_t ret;
+
+ ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A,
+ (uint8_t *)&emb_func_en_a, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
+ (uint8_t *)&emb_func_en_b, 1);
+ emb_sens->fsm = emb_func_en_b.fsm_en;
+ emb_sens->tilt = emb_func_en_a.tilt_en;
+ emb_sens->step = emb_func_en_a.pedo_en;
+ emb_sens->step_adv = emb_func_en_b.pedo_adv_en;
+ emb_sens->sig_mot = emb_func_en_a.sign_motion_en;
+ emb_sens->fifo_compr = emb_func_en_b.fifo_compr_en;
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief turn off all embedded functions.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val get the values of registers
+ * EMB_FUNC_EN_A e EMB_FUNC_EN_B.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lsm6dso_embedded_sens_off(stmdev_ctx_t *ctx)
+{
+ lsm6dso_emb_func_en_a_t emb_func_en_a;
+ lsm6dso_emb_func_en_b_t emb_func_en_b;
+ int32_t ret;
+
+ ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A,
+ (uint8_t *)&emb_func_en_a, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
+ (uint8_t *)&emb_func_en_b, 1);
+ emb_func_en_b.fsm_en = PROPERTY_DISABLE;
+ emb_func_en_a.tilt_en = PROPERTY_DISABLE;
+ emb_func_en_a.pedo_en = PROPERTY_DISABLE;
+ emb_func_en_b.pedo_adv_en = PROPERTY_DISABLE;
+ emb_func_en_a.sign_motion_en = PROPERTY_DISABLE;
+ emb_func_en_b.fifo_compr_en = PROPERTY_DISABLE;
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_A,
+ (uint8_t *)&emb_func_en_a, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
+ (uint8_t *)&emb_func_en_b, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+ }
+
+ return ret;
+}
+
/**
* @}
*
diff --git a/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.h b/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.h
index 58dbbc08b48306bea186a2b6ecdc368a51df2b57..b88b36bfe8ad8e0413e31c741042bf776ea1bda7 100644
--- a/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.h
+++ b/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.h
@@ -1,29 +1,29 @@
-/*
- ******************************************************************************
- * @file lsm6dso_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lsm6dso_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lsm6dso_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lsm6dso_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LSM6DSO_REGS_H
#define LSM6DSO_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -36,6 +36,37 @@
*
*/
+/** @defgroup Endianness definitions
+ * @{
+ *
+ */
+
+#ifndef DRV_BYTE_ORDER
+#ifndef __BYTE_ORDER__
+
+#define DRV_LITTLE_ENDIAN 1234
+#define DRV_BIG_ENDIAN 4321
+
+/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
+ * by uncommenting the define which fits your platform endianness
+ */
+//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
+#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
+
+#else /* defined __BYTE_ORDER__ */
+
+#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
+#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
+#define DRV_BYTE_ORDER __BYTE_ORDER__
+
+#endif /* __BYTE_ORDER__*/
+#endif /* DRV_BYTE_ORDER */
+
+/**
+ * @}
+ *
+ */
+
/** @defgroup STMicroelectronics sensors common types
* @{
*
@@ -44,7 +75,9 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -53,6 +86,16 @@ typedef struct{
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} bitwise_t;
#define PROPERTY_DISABLE (0U)
@@ -66,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -98,7 +142,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -133,25 +178,43 @@ typedef struct {
*/
#define LSM6DSO_FUNC_CFG_ACCESS 0x01U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t not_used_01 : 6;
+uint8_t reg_access :
+ 2; /* shub_reg_access + func_cfg_access */
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+uint8_t reg_access :
+ 2; /* shub_reg_access + func_cfg_access */
uint8_t not_used_01 : 6;
- uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_func_cfg_access_t;
#define LSM6DSO_PIN_CTRL 0x02U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 6;
uint8_t sdo_pu_en : 1;
uint8_t ois_pu_dis : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t ois_pu_dis : 1;
+ uint8_t sdo_pu_en : 1;
+ uint8_t not_used_01 : 6;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_pin_ctrl_t;
#define LSM6DSO_FIFO_CTRL1 0x07U
-typedef struct {
+typedef struct
+{
uint8_t wtm : 8;
} lsm6dso_fifo_ctrl1_t;
#define LSM6DSO_FIFO_CTRL2 0x08U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wtm : 1;
uint8_t uncoptr_rate : 2;
uint8_t not_used_01 : 1;
@@ -159,38 +222,73 @@ typedef struct {
uint8_t not_used_02 : 1;
uint8_t fifo_compr_rt_en : 1;
uint8_t stop_on_wtm : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t stop_on_wtm : 1;
+ uint8_t fifo_compr_rt_en : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t odrchg_en : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t uncoptr_rate : 2;
+ uint8_t wtm : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_fifo_ctrl2_t;
#define LSM6DSO_FIFO_CTRL3 0x09U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bdr_xl : 4;
uint8_t bdr_gy : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bdr_gy : 4;
+ uint8_t bdr_xl : 4;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_fifo_ctrl3_t;
#define LSM6DSO_FIFO_CTRL4 0x0AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fifo_mode : 3;
uint8_t not_used_01 : 1;
uint8_t odr_t_batch : 2;
uint8_t odr_ts_batch : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr_ts_batch : 2;
+ uint8_t odr_t_batch : 2;
+ uint8_t not_used_01 : 1;
+ uint8_t fifo_mode : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_fifo_ctrl4_t;
#define LSM6DSO_COUNTER_BDR_REG1 0x0BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t cnt_bdr_th : 3;
uint8_t not_used_01 : 2;
uint8_t trig_counter_bdr : 1;
uint8_t rst_counter_bdr : 1;
uint8_t dataready_pulsed : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t dataready_pulsed : 1;
+ uint8_t rst_counter_bdr : 1;
+ uint8_t trig_counter_bdr : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t cnt_bdr_th : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_counter_bdr_reg1_t;
#define LSM6DSO_COUNTER_BDR_REG2 0x0CU
-typedef struct {
+typedef struct
+{
uint8_t cnt_bdr_th : 8;
} lsm6dso_counter_bdr_reg2_t;
#define LSM6DSO_INT1_CTRL 0x0D
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_drdy_xl : 1;
uint8_t int1_drdy_g : 1;
uint8_t int1_boot : 1;
@@ -199,10 +297,22 @@ typedef struct {
uint8_t int1_fifo_full : 1;
uint8_t int1_cnt_bdr : 1;
uint8_t den_drdy_flag : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t den_drdy_flag : 1;
+ uint8_t int1_cnt_bdr : 1;
+ uint8_t int1_fifo_full : 1;
+ uint8_t int1_fifo_ovr : 1;
+ uint8_t int1_fifo_th : 1;
+ uint8_t int1_boot : 1;
+ uint8_t int1_drdy_g : 1;
+ uint8_t int1_drdy_xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_int1_ctrl_t;
#define LSM6DSO_INT2_CTRL 0x0EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_drdy_xl : 1;
uint8_t int2_drdy_g : 1;
uint8_t int2_drdy_temp : 1;
@@ -211,26 +321,53 @@ typedef struct {
uint8_t int2_fifo_full : 1;
uint8_t int2_cnt_bdr : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t int2_cnt_bdr : 1;
+ uint8_t int2_fifo_full : 1;
+ uint8_t int2_fifo_ovr : 1;
+ uint8_t int2_fifo_th : 1;
+ uint8_t int2_drdy_temp : 1;
+ uint8_t int2_drdy_g : 1;
+ uint8_t int2_drdy_xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_int2_ctrl_t;
#define LSM6DSO_WHO_AM_I 0x0FU
#define LSM6DSO_CTRL1_XL 0x10U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t lpf2_xl_en : 1;
uint8_t fs_xl : 2;
uint8_t odr_xl : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr_xl : 4;
+ uint8_t fs_xl : 2;
+ uint8_t lpf2_xl_en : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_ctrl1_xl_t;
#define LSM6DSO_CTRL2_G 0x11U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t fs_g : 3; /* fs_125 + fs_g */
uint8_t odr_g : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr_g : 4;
+ uint8_t fs_g : 3; /* fs_125 + fs_g */
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_ctrl2_g_t;
#define LSM6DSO_CTRL3_C 0x12U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sw_reset : 1;
uint8_t not_used_01 : 1;
uint8_t if_inc : 1;
@@ -239,10 +376,22 @@ typedef struct {
uint8_t h_lactive : 1;
uint8_t bdu : 1;
uint8_t boot : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t boot : 1;
+ uint8_t bdu : 1;
+ uint8_t h_lactive : 1;
+ uint8_t pp_od : 1;
+ uint8_t sim : 1;
+ uint8_t if_inc : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t sw_reset : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_ctrl3_c_t;
#define LSM6DSO_CTRL4_C 0x13U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t lpf1_sel_g : 1;
uint8_t i2c_disable : 1;
@@ -251,27 +400,58 @@ typedef struct {
uint8_t int2_on_int1 : 1;
uint8_t sleep_g : 1;
uint8_t not_used_03 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_03 : 1;
+ uint8_t sleep_g : 1;
+ uint8_t int2_on_int1 : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t drdy_mask : 1;
+ uint8_t i2c_disable : 1;
+ uint8_t lpf1_sel_g : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_ctrl4_c_t;
#define LSM6DSO_CTRL5_C 0x14U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_xl : 2;
uint8_t st_g : 2;
uint8_t not_used_01 : 1;
uint8_t rounding : 2;
uint8_t xl_ulp_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t xl_ulp_en : 1;
+ uint8_t rounding : 2;
+ uint8_t not_used_01 : 1;
+ uint8_t st_g : 2;
+ uint8_t st_xl : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_ctrl5_c_t;
#define LSM6DSO_CTRL6_C 0x15U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ftype : 3;
uint8_t usr_off_w : 1;
uint8_t xl_hm_mode : 1;
- uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */
+uint8_t den_mode :
+ 3; /* trig_en + lvl1_en + lvl2_en */
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+uint8_t den_mode :
+ 3; /* trig_en + lvl1_en + lvl2_en */
+ uint8_t xl_hm_mode : 1;
+ uint8_t usr_off_w : 1;
+ uint8_t ftype : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_ctrl6_c_t;
#define LSM6DSO_CTRL7_G 0x16U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ois_on : 1;
uint8_t usr_off_on_out : 1;
uint8_t ois_on_en : 1;
@@ -279,20 +459,41 @@ typedef struct {
uint8_t hpm_g : 2;
uint8_t hp_en_g : 1;
uint8_t g_hm_mode : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t g_hm_mode : 1;
+ uint8_t hp_en_g : 1;
+ uint8_t hpm_g : 2;
+ uint8_t not_used_01 : 1;
+ uint8_t ois_on_en : 1;
+ uint8_t usr_off_on_out : 1;
+ uint8_t ois_on : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_ctrl7_g_t;
#define LSM6DSO_CTRL8_XL 0x17U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t low_pass_on_6d : 1;
uint8_t xl_fs_mode : 1;
uint8_t hp_slope_xl_en : 1;
uint8_t fastsettl_mode_xl : 1;
uint8_t hp_ref_mode_xl : 1;
uint8_t hpcf_xl : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t hpcf_xl : 3;
+ uint8_t hp_ref_mode_xl : 1;
+ uint8_t fastsettl_mode_xl : 1;
+ uint8_t hp_slope_xl_en : 1;
+ uint8_t xl_fs_mode : 1;
+ uint8_t low_pass_on_6d : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_ctrl8_xl_t;
#define LSM6DSO_CTRL9_XL 0x18U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t i3c_disable : 1;
uint8_t den_lh : 1;
@@ -300,17 +501,35 @@ typedef struct {
uint8_t den_z : 1;
uint8_t den_y : 1;
uint8_t den_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t den_x : 1;
+ uint8_t den_y : 1;
+ uint8_t den_z : 1;
+ uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */
+ uint8_t den_lh : 1;
+ uint8_t i3c_disable : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_ctrl9_xl_t;
#define LSM6DSO_CTRL10_C 0x19U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 5;
uint8_t timestamp_en : 1;
uint8_t not_used_02 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 2;
+ uint8_t timestamp_en : 1;
+ uint8_t not_used_01 : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_ctrl10_c_t;
#define LSM6DSO_ALL_INT_SRC 0x1AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ia : 1;
uint8_t wu_ia : 1;
uint8_t single_tap : 1;
@@ -319,10 +538,22 @@ typedef struct {
uint8_t sleep_change_ia : 1;
uint8_t not_used_01 : 1;
uint8_t timestamp_endcount : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t timestamp_endcount : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t sleep_change_ia : 1;
+ uint8_t d6d_ia : 1;
+ uint8_t double_tap : 1;
+ uint8_t single_tap : 1;
+ uint8_t wu_ia : 1;
+ uint8_t ff_ia : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_all_int_src_t;
#define LSM6DSO_WAKE_UP_SRC 0x1BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_wu : 1;
uint8_t y_wu : 1;
uint8_t x_wu : 1;
@@ -331,10 +562,22 @@ typedef struct {
uint8_t ff_ia : 1;
uint8_t sleep_change_ia : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t sleep_change_ia : 1;
+ uint8_t ff_ia : 1;
+ uint8_t sleep_state : 1;
+ uint8_t wu_ia : 1;
+ uint8_t x_wu : 1;
+ uint8_t y_wu : 1;
+ uint8_t z_wu : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_wake_up_src_t;
#define LSM6DSO_TAP_SRC 0x1CU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_tap : 1;
uint8_t y_tap : 1;
uint8_t x_tap : 1;
@@ -343,10 +586,22 @@ typedef struct {
uint8_t single_tap : 1;
uint8_t tap_ia : 1;
uint8_t not_used_02 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 1;
+ uint8_t tap_ia : 1;
+ uint8_t single_tap : 1;
+ uint8_t double_tap : 1;
+ uint8_t tap_sign : 1;
+ uint8_t x_tap : 1;
+ uint8_t y_tap : 1;
+ uint8_t z_tap : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_tap_src_t;
#define LSM6DSO_D6D_SRC 0x1DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
uint8_t yl : 1;
@@ -355,22 +610,48 @@ typedef struct {
uint8_t zh : 1;
uint8_t d6d_ia : 1;
uint8_t den_drdy : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t den_drdy : 1;
+ uint8_t d6d_ia : 1;
+ uint8_t zh : 1;
+ uint8_t zl : 1;
+ uint8_t yh : 1;
+ uint8_t yl : 1;
+ uint8_t xh : 1;
+ uint8_t xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_d6d_src_t;
#define LSM6DSO_STATUS_REG 0x1EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlda : 1;
uint8_t gda : 1;
uint8_t tda : 1;
uint8_t not_used_01 : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 5;
+ uint8_t tda : 1;
+ uint8_t gda : 1;
+ uint8_t xlda : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_status_reg_t;
#define LSM6DSO_STATUS_SPIAUX 0x1EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlda : 1;
uint8_t gda : 1;
uint8_t gyro_settling : 1;
uint8_t not_used_01 : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 5;
+ uint8_t gyro_settling : 1;
+ uint8_t gda : 1;
+ uint8_t xlda : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_status_spiaux_t;
#define LSM6DSO_OUT_TEMP_L 0x20U
@@ -388,17 +669,29 @@ typedef struct {
#define LSM6DSO_OUTZ_L_A 0x2CU
#define LSM6DSO_OUTZ_H_A 0x2DU
#define LSM6DSO_EMB_FUNC_STATUS_MAINPAGE 0x35U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t is_step_det : 1;
uint8_t is_tilt : 1;
uint8_t is_sigmot : 1;
uint8_t not_used_02 : 1;
uint8_t is_fsm_lc : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_fsm_lc : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t is_sigmot : 1;
+ uint8_t is_tilt : 1;
+ uint8_t is_step_det : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_emb_func_status_mainpage_t;
#define LSM6DSO_FSM_STATUS_A_MAINPAGE 0x36U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_fsm1 : 1;
uint8_t is_fsm2 : 1;
uint8_t is_fsm3 : 1;
@@ -407,10 +700,22 @@ typedef struct {
uint8_t is_fsm6 : 1;
uint8_t is_fsm7 : 1;
uint8_t is_fsm8 : 1;
- } lsm6dso_fsm_status_a_mainpage_t;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_fsm8 : 1;
+ uint8_t is_fsm7 : 1;
+ uint8_t is_fsm6 : 1;
+ uint8_t is_fsm5 : 1;
+ uint8_t is_fsm4 : 1;
+ uint8_t is_fsm3 : 1;
+ uint8_t is_fsm2 : 1;
+ uint8_t is_fsm1 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fsm_status_a_mainpage_t;
#define LSM6DSO_FSM_STATUS_B_MAINPAGE 0x37U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_fsm9 : 1;
uint8_t is_fsm10 : 1;
uint8_t is_fsm11 : 1;
@@ -419,10 +724,22 @@ typedef struct {
uint8_t is_fsm14 : 1;
uint8_t is_fsm15 : 1;
uint8_t is_fsm16 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_fsm16 : 1;
+ uint8_t is_fsm15 : 1;
+ uint8_t is_fsm14 : 1;
+ uint8_t is_fsm13 : 1;
+ uint8_t is_fsm12 : 1;
+ uint8_t is_fsm11 : 1;
+ uint8_t is_fsm10 : 1;
+ uint8_t is_fsm9 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_fsm_status_b_mainpage_t;
#define LSM6DSO_STATUS_MASTER_MAINPAGE 0x39U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sens_hub_endop : 1;
uint8_t not_used_01 : 2;
uint8_t slave0_nack : 1;
@@ -430,15 +747,27 @@ typedef struct {
uint8_t slave2_nack : 1;
uint8_t slave3_nack : 1;
uint8_t wr_once_done : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t wr_once_done : 1;
+ uint8_t slave3_nack : 1;
+ uint8_t slave2_nack : 1;
+ uint8_t slave1_nack : 1;
+ uint8_t slave0_nack : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t sens_hub_endop : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_status_master_mainpage_t;
#define LSM6DSO_FIFO_STATUS1 0x3AU
-typedef struct {
+typedef struct
+{
uint8_t diff_fifo : 8;
} lsm6dso_fifo_status1_t;
#define LSM6DSO_FIFO_STATUS2 0x3B
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t diff_fifo : 2;
uint8_t not_used_01 : 1;
uint8_t over_run_latched : 1;
@@ -446,6 +775,15 @@ typedef struct {
uint8_t fifo_full_ia : 1;
uint8_t fifo_ovr_ia : 1;
uint8_t fifo_wtm_ia : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fifo_wtm_ia : 1;
+ uint8_t fifo_ovr_ia : 1;
+ uint8_t fifo_full_ia : 1;
+ uint8_t counter_bdr_ia : 1;
+ uint8_t over_run_latched : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t diff_fifo : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_fifo_status2_t;
#define LSM6DSO_TIMESTAMP0 0x40U
@@ -453,7 +791,9 @@ typedef struct {
#define LSM6DSO_TIMESTAMP2 0x42U
#define LSM6DSO_TIMESTAMP3 0x43U
#define LSM6DSO_TAP_CFG0 0x56U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lir : 1;
uint8_t tap_z_en : 1;
uint8_t tap_y_en : 1;
@@ -462,58 +802,118 @@ typedef struct {
uint8_t sleep_status_on_int : 1;
uint8_t int_clr_on_read : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t int_clr_on_read : 1;
+ uint8_t sleep_status_on_int : 1;
+ uint8_t slope_fds : 1;
+ uint8_t tap_x_en : 1;
+ uint8_t tap_y_en : 1;
+ uint8_t tap_z_en : 1;
+ uint8_t lir : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_tap_cfg0_t;
#define LSM6DSO_TAP_CFG1 0x57U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_ths_x : 5;
uint8_t tap_priority : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t tap_priority : 3;
+ uint8_t tap_ths_x : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_tap_cfg1_t;
#define LSM6DSO_TAP_CFG2 0x58U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_ths_y : 5;
uint8_t inact_en : 2;
uint8_t interrupts_enable : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t interrupts_enable : 1;
+ uint8_t inact_en : 2;
+ uint8_t tap_ths_y : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_tap_cfg2_t;
#define LSM6DSO_TAP_THS_6D 0x59U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_ths_z : 5;
uint8_t sixd_ths : 2;
uint8_t d4d_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t d4d_en : 1;
+ uint8_t sixd_ths : 2;
+ uint8_t tap_ths_z : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_tap_ths_6d_t;
#define LSM6DSO_INT_DUR2 0x5AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shock : 2;
uint8_t quiet : 2;
uint8_t dur : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t dur : 4;
+ uint8_t quiet : 2;
+ uint8_t shock : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_int_dur2_t;
#define LSM6DSO_WAKE_UP_THS 0x5BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wk_ths : 6;
uint8_t usr_off_on_wu : 1;
uint8_t single_double_tap : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t single_double_tap : 1;
+ uint8_t usr_off_on_wu : 1;
+ uint8_t wk_ths : 6;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_wake_up_ths_t;
#define LSM6DSO_WAKE_UP_DUR 0x5CU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sleep_dur : 4;
uint8_t wake_ths_w : 1;
uint8_t wake_dur : 2;
uint8_t ff_dur : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t ff_dur : 1;
+ uint8_t wake_dur : 2;
+ uint8_t wake_ths_w : 1;
+ uint8_t sleep_dur : 4;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_wake_up_dur_t;
#define LSM6DSO_FREE_FALL 0x5DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ths : 3;
uint8_t ff_dur : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t ff_dur : 5;
+ uint8_t ff_ths : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_free_fall_t;
#define LSM6DSO_MD1_CFG 0x5EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_shub : 1;
uint8_t int1_emb_func : 1;
uint8_t int1_6d : 1;
@@ -522,10 +922,22 @@ typedef struct {
uint8_t int1_wu : 1;
uint8_t int1_single_tap : 1;
uint8_t int1_sleep_change : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_sleep_change : 1;
+ uint8_t int1_single_tap : 1;
+ uint8_t int1_wu : 1;
+ uint8_t int1_ff : 1;
+ uint8_t int1_double_tap : 1;
+ uint8_t int1_6d : 1;
+ uint8_t int1_emb_func : 1;
+ uint8_t int1_shub : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_md1_cfg_t;
#define LSM6DSO_MD2_CFG 0x5FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_timestamp : 1;
uint8_t int2_emb_func : 1;
uint8_t int2_6d : 1;
@@ -534,65 +946,127 @@ typedef struct {
uint8_t int2_wu : 1;
uint8_t int2_single_tap : 1;
uint8_t int2_sleep_change : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_sleep_change : 1;
+ uint8_t int2_single_tap : 1;
+ uint8_t int2_wu : 1;
+ uint8_t int2_ff : 1;
+ uint8_t int2_double_tap : 1;
+ uint8_t int2_6d : 1;
+ uint8_t int2_emb_func : 1;
+ uint8_t int2_timestamp : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_md2_cfg_t;
#define LSM6DSO_I3C_BUS_AVB 0x62U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t pd_dis_int1 : 1;
uint8_t not_used_01 : 2;
uint8_t i3c_bus_avb_sel : 2;
uint8_t not_used_02 : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 3;
+ uint8_t i3c_bus_avb_sel : 2;
+ uint8_t not_used_01 : 2;
+ uint8_t pd_dis_int1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_i3c_bus_avb_t;
#define LSM6DSO_INTERNAL_FREQ_FINE 0x63U
-typedef struct {
+typedef struct
+{
uint8_t freq_fine : 8;
} lsm6dso_internal_freq_fine_t;
#define LSM6DSO_INT_OIS 0x6FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_xl_ois : 2;
uint8_t not_used_01 : 3;
uint8_t den_lh_ois : 1;
uint8_t lvl2_ois : 1;
uint8_t int2_drdy_ois : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_drdy_ois : 1;
+ uint8_t lvl2_ois : 1;
+ uint8_t den_lh_ois : 1;
+ uint8_t not_used_01 : 3;
+ uint8_t st_xl_ois : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_int_ois_t;
#define LSM6DSO_CTRL1_OIS 0x70U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ois_en_spi2 : 1;
uint8_t fs_g_ois : 3; /* fs_125_ois + fs[1:0]_g_ois */
uint8_t mode4_en : 1;
uint8_t sim_ois : 1;
- uint8_t lvl1_ois : 1;
+ uint8_t lvl1_ois : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t lvl1_ois : 1;
+ uint8_t sim_ois : 1;
+ uint8_t mode4_en : 1;
+ uint8_t fs_g_ois : 3; /* fs_125_ois + fs[1:0]_g_ois */
+ uint8_t ois_en_spi2 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_ctrl1_ois_t;
#define LSM6DSO_CTRL2_OIS 0x71U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t hp_en_ois : 1;
uint8_t ftype_ois : 2;
uint8_t not_used_01 : 1;
uint8_t hpm_ois : 2;
uint8_t not_used_02 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 2;
+ uint8_t hpm_ois : 2;
+ uint8_t not_used_01 : 1;
+ uint8_t ftype_ois : 2;
+ uint8_t hp_en_ois : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_ctrl2_ois_t;
#define LSM6DSO_CTRL3_OIS 0x72U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_ois_clampdis : 1;
uint8_t st_ois : 2;
uint8_t filter_xl_conf_ois : 3;
uint8_t fs_xl_ois : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fs_xl_ois : 2;
+ uint8_t filter_xl_conf_ois : 3;
+ uint8_t st_ois : 2;
+ uint8_t st_ois_clampdis : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_ctrl3_ois_t;
#define LSM6DSO_X_OFS_USR 0x73U
#define LSM6DSO_Y_OFS_USR 0x74U
#define LSM6DSO_Z_OFS_USR 0x75U
#define LSM6DSO_FIFO_DATA_OUT_TAG 0x78U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tag_parity : 1;
uint8_t tag_cnt : 2;
uint8_t tag_sensor : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t tag_sensor : 5;
+ uint8_t tag_cnt : 2;
+ uint8_t tag_parity : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_fifo_data_out_tag_t;
#define LSM6DSO_FIFO_DATA_OUT_X_L 0x79U
@@ -602,51 +1076,89 @@ typedef struct {
#define LSM6DSO_FIFO_DATA_OUT_Z_L 0x7DU
#define LSM6DSO_FIFO_DATA_OUT_Z_H 0x7EU
#define LSM6DSO_PAGE_SEL 0x02U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 4;
uint8_t page_sel : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t page_sel : 4;
+ uint8_t not_used_01 : 4;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_page_sel_t;
#define LSM6DSO_EMB_FUNC_EN_A 0x04U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t pedo_en : 1;
uint8_t tilt_en : 1;
uint8_t sign_motion_en : 1;
uint8_t not_used_02 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 2;
+ uint8_t sign_motion_en : 1;
+ uint8_t tilt_en : 1;
+ uint8_t pedo_en : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_emb_func_en_a_t;
#define LSM6DSO_EMB_FUNC_EN_B 0x05U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fsm_en : 1;
uint8_t not_used_01 : 2;
uint8_t fifo_compr_en : 1;
uint8_t pedo_adv_en : 1;
uint8_t not_used_02 : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 3;
+ uint8_t pedo_adv_en : 1;
+ uint8_t fifo_compr_en : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t fsm_en : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_emb_func_en_b_t;
#define LSM6DSO_PAGE_ADDRESS 0x08U
-typedef struct {
+typedef struct
+{
uint8_t page_addr : 8;
} lsm6dso_page_address_t;
#define LSM6DSO_PAGE_VALUE 0x09U
-typedef struct {
+typedef struct
+{
uint8_t page_value : 8;
} lsm6dso_page_value_t;
#define LSM6DSO_EMB_FUNC_INT1 0x0AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t int1_step_detector : 1;
uint8_t int1_tilt : 1;
uint8_t int1_sig_mot : 1;
uint8_t not_used_02 : 1;
uint8_t int1_fsm_lc : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_fsm_lc : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t int1_sig_mot : 1;
+ uint8_t int1_tilt : 1;
+ uint8_t int1_step_detector : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_emb_func_int1_t;
#define LSM6DSO_FSM_INT1_A 0x0BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_fsm1 : 1;
uint8_t int1_fsm2 : 1;
uint8_t int1_fsm3 : 1;
@@ -655,10 +1167,22 @@ typedef struct {
uint8_t int1_fsm6 : 1;
uint8_t int1_fsm7 : 1;
uint8_t int1_fsm8 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_fsm8 : 1;
+ uint8_t int1_fsm7 : 1;
+ uint8_t int1_fsm6 : 1;
+ uint8_t int1_fsm5 : 1;
+ uint8_t int1_fsm4 : 1;
+ uint8_t int1_fsm3 : 1;
+ uint8_t int1_fsm2 : 1;
+ uint8_t int1_fsm1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_fsm_int1_a_t;
#define LSM6DSO_FSM_INT1_B 0x0CU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_fsm9 : 1;
uint8_t int1_fsm10 : 1;
uint8_t int1_fsm11 : 1;
@@ -667,20 +1191,42 @@ typedef struct {
uint8_t int1_fsm14 : 1;
uint8_t int1_fsm15 : 1;
uint8_t int1_fsm16 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_fsm16 : 1;
+ uint8_t int1_fsm15 : 1;
+ uint8_t int1_fsm14 : 1;
+ uint8_t int1_fsm13 : 1;
+ uint8_t int1_fsm12 : 1;
+ uint8_t int1_fsm11 : 1;
+ uint8_t int1_fsm10 : 1;
+ uint8_t int1_fsm9 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_fsm_int1_b_t;
#define LSM6DSO_EMB_FUNC_INT2 0x0EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t int2_step_detector : 1;
uint8_t int2_tilt : 1;
uint8_t int2_sig_mot : 1;
uint8_t not_used_02 : 1;
uint8_t int2_fsm_lc : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_fsm_lc : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t int2_sig_mot : 1;
+ uint8_t int2_tilt : 1;
+ uint8_t int2_step_detector : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_emb_func_int2_t;
#define LSM6DSO_FSM_INT2_A 0x0FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_fsm1 : 1;
uint8_t int2_fsm2 : 1;
uint8_t int2_fsm3 : 1;
@@ -689,10 +1235,22 @@ typedef struct {
uint8_t int2_fsm6 : 1;
uint8_t int2_fsm7 : 1;
uint8_t int2_fsm8 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_fsm8 : 1;
+ uint8_t int2_fsm7 : 1;
+ uint8_t int2_fsm6 : 1;
+ uint8_t int2_fsm5 : 1;
+ uint8_t int2_fsm4 : 1;
+ uint8_t int2_fsm3 : 1;
+ uint8_t int2_fsm2 : 1;
+ uint8_t int2_fsm1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_fsm_int2_a_t;
#define LSM6DSO_FSM_INT2_B 0x10U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_fsm9 : 1;
uint8_t int2_fsm10 : 1;
uint8_t int2_fsm11 : 1;
@@ -701,20 +1259,42 @@ typedef struct {
uint8_t int2_fsm14 : 1;
uint8_t int2_fsm15 : 1;
uint8_t int2_fsm16 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_fsm16 : 1;
+ uint8_t int2_fsm15 : 1;
+ uint8_t int2_fsm14 : 1;
+ uint8_t int2_fsm13 : 1;
+ uint8_t int2_fsm12 : 1;
+ uint8_t int2_fsm11 : 1;
+ uint8_t int2_fsm10 : 1;
+ uint8_t int2_fsm9 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_fsm_int2_b_t;
#define LSM6DSO_EMB_FUNC_STATUS 0x12U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t is_step_det : 1;
uint8_t is_tilt : 1;
uint8_t is_sigmot : 1;
uint8_t not_used_02 : 1;
uint8_t is_fsm_lc : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_fsm_lc : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t is_sigmot : 1;
+ uint8_t is_tilt : 1;
+ uint8_t is_step_det : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_emb_func_status_t;
#define LSM6DSO_FSM_STATUS_A 0x13U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_fsm1 : 1;
uint8_t is_fsm2 : 1;
uint8_t is_fsm3 : 1;
@@ -723,10 +1303,22 @@ typedef struct {
uint8_t is_fsm6 : 1;
uint8_t is_fsm7 : 1;
uint8_t is_fsm8 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_fsm8 : 1;
+ uint8_t is_fsm7 : 1;
+ uint8_t is_fsm6 : 1;
+ uint8_t is_fsm5 : 1;
+ uint8_t is_fsm4 : 1;
+ uint8_t is_fsm3 : 1;
+ uint8_t is_fsm2 : 1;
+ uint8_t is_fsm1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_fsm_status_a_t;
#define LSM6DSO_FSM_STATUS_B 0x14U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_fsm9 : 1;
uint8_t is_fsm10 : 1;
uint8_t is_fsm11 : 1;
@@ -735,24 +1327,50 @@ typedef struct {
uint8_t is_fsm14 : 1;
uint8_t is_fsm15 : 1;
uint8_t is_fsm16 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_fsm16 : 1;
+ uint8_t is_fsm15 : 1;
+ uint8_t is_fsm14 : 1;
+ uint8_t is_fsm13 : 1;
+ uint8_t is_fsm12 : 1;
+ uint8_t is_fsm11 : 1;
+ uint8_t is_fsm10 : 1;
+ uint8_t is_fsm9 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_fsm_status_b_t;
#define LSM6DSO_PAGE_RW 0x17U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 5;
uint8_t page_rw : 2; /* page_write + page_read */
uint8_t emb_func_lir : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t emb_func_lir : 1;
+ uint8_t page_rw : 2; /* page_write + page_read */
+ uint8_t not_used_01 : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_page_rw_t;
#define LSM6DSO_EMB_FUNC_FIFO_CFG 0x44U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_00 : 6;
uint8_t pedo_fifo_en : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t pedo_fifo_en : 1;
+ uint8_t not_used_00 : 6;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_emb_func_fifo_cfg_t;
#define LSM6DSO_FSM_ENABLE_A 0x46U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fsm1_en : 1;
uint8_t fsm2_en : 1;
uint8_t fsm3_en : 1;
@@ -761,10 +1379,22 @@ typedef struct {
uint8_t fsm6_en : 1;
uint8_t fsm7_en : 1;
uint8_t fsm8_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fsm8_en : 1;
+ uint8_t fsm7_en : 1;
+ uint8_t fsm6_en : 1;
+ uint8_t fsm5_en : 1;
+ uint8_t fsm4_en : 1;
+ uint8_t fsm3_en : 1;
+ uint8_t fsm2_en : 1;
+ uint8_t fsm1_en : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_fsm_enable_a_t;
#define LSM6DSO_FSM_ENABLE_B 0x47U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fsm9_en : 1;
uint8_t fsm10_en : 1;
uint8_t fsm11_en : 1;
@@ -773,18 +1403,38 @@ typedef struct {
uint8_t fsm14_en : 1;
uint8_t fsm15_en : 1;
uint8_t fsm16_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fsm16_en : 1;
+ uint8_t fsm15_en : 1;
+ uint8_t fsm14_en : 1;
+ uint8_t fsm13_en : 1;
+ uint8_t fsm12_en : 1;
+ uint8_t fsm11_en : 1;
+ uint8_t fsm10_en : 1;
+ uint8_t fsm9_en : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_fsm_enable_b_t;
#define LSM6DSO_FSM_LONG_COUNTER_L 0x48U
#define LSM6DSO_FSM_LONG_COUNTER_H 0x49U
#define LSM6DSO_FSM_LONG_COUNTER_CLEAR 0x4AU
-typedef struct {
- uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+uint8_t fsm_lc_clr :
+ 2; /* fsm_lc_cleared + fsm_lc_clear */
uint8_t not_used_01 : 6;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 6;
+uint8_t fsm_lc_clr :
+ 2; /* fsm_lc_cleared + fsm_lc_clear */
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_fsm_long_counter_clear_t;
#define LSM6DSO_FSM_OUTS1 0x4CU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -793,10 +1443,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_fsm_outs1_t;
#define LSM6DSO_FSM_OUTS2 0x4DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -805,10 +1467,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_fsm_outs2_t;
#define LSM6DSO_FSM_OUTS3 0x4EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -817,10 +1491,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_fsm_outs3_t;
#define LSM6DSO_FSM_OUTS4 0x4FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -829,10 +1515,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_fsm_outs4_t;
#define LSM6DSO_FSM_OUTS5 0x50U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -841,10 +1539,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_fsm_outs5_t;
#define LSM6DSO_FSM_OUTS6 0x51U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -853,10 +1563,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_fsm_outs6_t;
#define LSM6DSO_FSM_OUTS7 0x52U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -865,10 +1587,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_fsm_outs7_t;
#define LSM6DSO_FSM_OUTS8 0x53U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -877,10 +1611,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_fsm_outs8_t;
#define LSM6DSO_FSM_OUTS9 0x54U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -889,10 +1635,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_fsm_outs9_t;
#define LSM6DSO_FSM_OUTS10 0x55U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -901,10 +1659,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_fsm_outs10_t;
#define LSM6DSO_FSM_OUTS11 0x56U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -913,10 +1683,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_fsm_outs11_t;
#define LSM6DSO_FSM_OUTS12 0x57U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -925,10 +1707,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_fsm_outs12_t;
#define LSM6DSO_FSM_OUTS13 0x58U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -937,10 +1731,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_fsm_outs13_t;
#define LSM6DSO_FSM_OUTS14 0x59U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -949,10 +1755,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_fsm_outs14_t;
#define LSM6DSO_FSM_OUTS15 0x5AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -961,10 +1779,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_fsm_outs15_t;
#define LSM6DSO_FSM_OUTS16 0x5BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -973,19 +1803,38 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_fsm_outs16_t;
#define LSM6DSO_EMB_FUNC_ODR_CFG_B 0x5FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t fsm_odr : 2;
uint8_t not_used_02 : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 3;
+ uint8_t fsm_odr : 2;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_emb_func_odr_cfg_b_t;
#define LSM6DSO_STEP_COUNTER_L 0x62U
#define LSM6DSO_STEP_COUNTER_H 0x63U
#define LSM6DSO_EMB_FUNC_SRC 0x64U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t stepcounter_bit_set : 1;
uint8_t step_overflow : 1;
@@ -993,23 +1842,49 @@ typedef struct {
uint8_t step_detected : 1;
uint8_t not_used_02 : 1;
uint8_t pedo_rst_step : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t pedo_rst_step : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t step_detected : 1;
+ uint8_t step_count_delta_ia : 1;
+ uint8_t step_overflow : 1;
+ uint8_t stepcounter_bit_set : 1;
+ uint8_t not_used_01 : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_emb_func_src_t;
#define LSM6DSO_EMB_FUNC_INIT_A 0x66U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t step_det_init : 1;
uint8_t tilt_init : 1;
uint8_t sig_mot_init : 1;
uint8_t not_used_02 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 2;
+ uint8_t sig_mot_init : 1;
+ uint8_t tilt_init : 1;
+ uint8_t step_det_init : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_emb_func_init_a_t;
#define LSM6DSO_EMB_FUNC_INIT_B 0x67U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fsm_init : 1;
uint8_t not_used_01 : 2;
uint8_t fifo_compr_init : 1;
uint8_t not_used_02 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 4;
+ uint8_t fifo_compr_init : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t fsm_init : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_emb_func_init_b_t;
#define LSM6DSO_MAG_SENSITIVITY_L 0xBAU
@@ -1033,17 +1908,31 @@ typedef struct {
#define LSM6DSO_MAG_SI_ZZ_L 0xD0U
#define LSM6DSO_MAG_SI_ZZ_H 0xD1U
#define LSM6DSO_MAG_CFG_A 0xD4U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t mag_z_axis : 3;
uint8_t not_used_01 : 1;
uint8_t mag_y_axis : 3;
uint8_t not_used_02 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 1;
+ uint8_t mag_y_axis : 3;
+ uint8_t not_used_01 : 1;
+ uint8_t mag_z_axis : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_mag_cfg_a_t;
#define LSM6DSO_MAG_CFG_B 0xD5U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t mag_x_axis : 3;
uint8_t not_used_01 : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 5;
+ uint8_t mag_x_axis : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_mag_cfg_b_t;
#define LSM6DSO_FSM_LC_TIMEOUT_L 0x17AU
@@ -1052,235 +1941,462 @@ typedef struct {
#define LSM6DSO_FSM_START_ADD_L 0x17EU
#define LSM6DSO_FSM_START_ADD_H 0x17FU
#define LSM6DSO_PEDO_CMD_REG 0x183U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ad_det_en : 1;
uint8_t not_used_01 : 1;
uint8_t fp_rejection_en : 1;
uint8_t carry_count_en : 1;
uint8_t not_used_02 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 4;
+ uint8_t carry_count_en : 1;
+ uint8_t fp_rejection_en : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t ad_det_en : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_pedo_cmd_reg_t;
#define LSM6DSO_PEDO_DEB_STEPS_CONF 0x184U
#define LSM6DSO_PEDO_SC_DELTAT_L 0x1D0U
#define LSM6DSO_PEDO_SC_DELTAT_H 0x1D1U
#define LSM6DSO_SENSOR_HUB_1 0x02U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_sensor_hub_1_t;
#define LSM6DSO_SENSOR_HUB_2 0x03U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_sensor_hub_2_t;
#define LSM6DSO_SENSOR_HUB_3 0x04U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_sensor_hub_3_t;
#define LSM6DSO_SENSOR_HUB_4 0x05U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_sensor_hub_4_t;
#define LSM6DSO_SENSOR_HUB_5 0x06U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_sensor_hub_5_t;
#define LSM6DSO_SENSOR_HUB_6 0x07U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_sensor_hub_6_t;
#define LSM6DSO_SENSOR_HUB_7 0x08U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_sensor_hub_7_t;
#define LSM6DSO_SENSOR_HUB_8 0x09U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_sensor_hub_8_t;
#define LSM6DSO_SENSOR_HUB_9 0x0AU
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_sensor_hub_9_t;
#define LSM6DSO_SENSOR_HUB_10 0x0BU
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_sensor_hub_10_t;
#define LSM6DSO_SENSOR_HUB_11 0x0CU
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_sensor_hub_11_t;
#define LSM6DSO_SENSOR_HUB_12 0x0DU
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_sensor_hub_12_t;
#define LSM6DSO_SENSOR_HUB_13 0x0EU
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_sensor_hub_13_t;
#define LSM6DSO_SENSOR_HUB_14 0x0FU
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_sensor_hub_14_t;
#define LSM6DSO_SENSOR_HUB_15 0x10U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_sensor_hub_15_t;
#define LSM6DSO_SENSOR_HUB_16 0x11U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_sensor_hub_16_t;
#define LSM6DSO_SENSOR_HUB_17 0x12U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_sensor_hub_17_t;
#define LSM6DSO_SENSOR_HUB_18 0x13U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_sensor_hub_18_t;
#define LSM6DSO_MASTER_CONFIG 0x14U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t aux_sens_on : 2;
uint8_t master_on : 1;
uint8_t shub_pu_en : 1;
@@ -1288,88 +2404,157 @@ typedef struct {
uint8_t start_config : 1;
uint8_t write_once : 1;
uint8_t rst_master_regs : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t rst_master_regs : 1;
+ uint8_t write_once : 1;
+ uint8_t start_config : 1;
+ uint8_t pass_through_mode : 1;
+ uint8_t shub_pu_en : 1;
+ uint8_t master_on : 1;
+ uint8_t aux_sens_on : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_master_config_t;
#define LSM6DSO_SLV0_ADD 0x15U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t rw_0 : 1;
uint8_t slave0 : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave0 : 7;
+ uint8_t rw_0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_slv0_add_t;
#define LSM6DSO_SLV0_SUBADD 0x16U
-typedef struct {
+typedef struct
+{
uint8_t slave0_reg : 8;
} lsm6dso_slv0_subadd_t;
#define LSM6DSO_SLV0_CONFIG 0x17U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave0_numop : 3;
uint8_t batch_ext_sens_0_en : 1;
uint8_t not_used_01 : 2;
uint8_t shub_odr : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t shub_odr : 2;
+ uint8_t not_used_01 : 2;
+ uint8_t batch_ext_sens_0_en : 1;
+ uint8_t slave0_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_slv0_config_t;
#define LSM6DSO_SLV1_ADD 0x18U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_1 : 1;
uint8_t slave1_add : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave1_add : 7;
+ uint8_t r_1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_slv1_add_t;
#define LSM6DSO_SLV1_SUBADD 0x19U
-typedef struct {
+typedef struct
+{
uint8_t slave1_reg : 8;
} lsm6dso_slv1_subadd_t;
#define LSM6DSO_SLV1_CONFIG 0x1AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave1_numop : 3;
uint8_t batch_ext_sens_1_en : 1;
uint8_t not_used_01 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 4;
+ uint8_t batch_ext_sens_1_en : 1;
+ uint8_t slave1_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_slv1_config_t;
#define LSM6DSO_SLV2_ADD 0x1BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_2 : 1;
uint8_t slave2_add : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave2_add : 7;
+ uint8_t r_2 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_slv2_add_t;
#define LSM6DSO_SLV2_SUBADD 0x1CU
-typedef struct {
+typedef struct
+{
uint8_t slave2_reg : 8;
} lsm6dso_slv2_subadd_t;
#define LSM6DSO_SLV2_CONFIG 0x1DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave2_numop : 3;
uint8_t batch_ext_sens_2_en : 1;
uint8_t not_used_01 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 4;
+ uint8_t batch_ext_sens_2_en : 1;
+ uint8_t slave2_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_slv2_config_t;
#define LSM6DSO_SLV3_ADD 0x1EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_3 : 1;
uint8_t slave3_add : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave3_add : 7;
+ uint8_t r_3 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_slv3_add_t;
#define LSM6DSO_SLV3_SUBADD 0x1FU
-typedef struct {
+typedef struct
+{
uint8_t slave3_reg : 8;
} lsm6dso_slv3_subadd_t;
#define LSM6DSO_SLV3_CONFIG 0x20U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave3_numop : 3;
uint8_t batch_ext_sens_3_en : 1;
uint8_t not_used_01 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 4;
+ uint8_t batch_ext_sens_3_en : 1;
+ uint8_t slave3_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_slv3_config_t;
#define LSM6DSO_DATAWRITE_SLV0 0x21U
-typedef struct {
+typedef struct
+{
uint8_t slave0_dataw : 8;
} lsm6dso_datawrite_src_mode_sub_slv0_t;
#define LSM6DSO_STATUS_MASTER 0x22U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sens_hub_endop : 1;
uint8_t not_used_01 : 2;
uint8_t slave0_nack : 1;
@@ -1377,15 +2562,24 @@ typedef struct {
uint8_t slave2_nack : 1;
uint8_t slave3_nack : 1;
uint8_t wr_once_done : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t wr_once_done : 1;
+ uint8_t slave3_nack : 1;
+ uint8_t slave2_nack : 1;
+ uint8_t slave1_nack : 1;
+ uint8_t slave0_nack : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t sens_hub_endop : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dso_status_master_t;
#define LSM6DSO_START_FSM_ADD 0x0400U
/**
* @defgroup LSM6DSO_Register_Union
- * @brief This union group all the registers that has a bitfield
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -1393,7 +2587,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
lsm6dso_func_cfg_access_t func_cfg_access;
lsm6dso_pin_ctrl_t pin_ctrl;
lsm6dso_fifo_ctrl1_t fifo_ctrl1;
@@ -1523,33 +2718,42 @@ typedef union{
*
*/
-int32_t lsm6dso_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lsm6dso_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t lsm6dso_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lsm6dso_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-extern float_t lsm6dso_from_fs2_to_mg(int16_t lsb);
-extern float_t lsm6dso_from_fs4_to_mg(int16_t lsb);
-extern float_t lsm6dso_from_fs8_to_mg(int16_t lsb);
-extern float_t lsm6dso_from_fs16_to_mg(int16_t lsb);
-extern float_t lsm6dso_from_fs125_to_mdps(int16_t lsb);
-extern float_t lsm6dso_from_fs500_to_mdps(int16_t lsb);
-extern float_t lsm6dso_from_fs250_to_mdps(int16_t lsb);
-extern float_t lsm6dso_from_fs1000_to_mdps(int16_t lsb);
-extern float_t lsm6dso_from_fs2000_to_mdps(int16_t lsb);
-extern float_t lsm6dso_from_lsb_to_celsius(int16_t lsb);
-extern float_t lsm6dso_from_lsb_to_nsec(int16_t lsb);
-
-typedef enum {
+float_t lsm6dso_from_fs2_to_mg(int16_t lsb);
+float_t lsm6dso_from_fs4_to_mg(int16_t lsb);
+float_t lsm6dso_from_fs8_to_mg(int16_t lsb);
+float_t lsm6dso_from_fs16_to_mg(int16_t lsb);
+
+float_t lsm6dso_from_fs125_to_mdps(int16_t lsb);
+float_t lsm6dso_from_fs500_to_mdps(int16_t lsb);
+float_t lsm6dso_from_fs250_to_mdps(int16_t lsb);
+float_t lsm6dso_from_fs1000_to_mdps(int16_t lsb);
+float_t lsm6dso_from_fs2000_to_mdps(int16_t lsb);
+
+float_t lsm6dso_from_lsb_to_celsius(int16_t lsb);
+
+float_t lsm6dso_from_lsb_to_nsec(int16_t lsb);
+
+typedef enum
+{
LSM6DSO_2g = 0,
LSM6DSO_16g = 1, /* if XL_FS_MODE = ‘1’ -> LSM6DSO_2g */
LSM6DSO_4g = 2,
LSM6DSO_8g = 3,
} lsm6dso_fs_xl_t;
-int32_t lsm6dso_xl_full_scale_set(stmdev_ctx_t *ctx, lsm6dso_fs_xl_t val);
-int32_t lsm6dso_xl_full_scale_get(stmdev_ctx_t *ctx, lsm6dso_fs_xl_t *val);
+int32_t lsm6dso_xl_full_scale_set(stmdev_ctx_t *ctx,
+ lsm6dso_fs_xl_t val);
+int32_t lsm6dso_xl_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6dso_fs_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_XL_ODR_OFF = 0,
LSM6DSO_XL_ODR_12Hz5 = 1,
LSM6DSO_XL_ODR_26Hz = 2,
@@ -1563,20 +2767,26 @@ typedef enum {
LSM6DSO_XL_ODR_6667Hz = 10,
LSM6DSO_XL_ODR_1Hz6 = 11, /* (low power only) */
} lsm6dso_odr_xl_t;
-int32_t lsm6dso_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6dso_odr_xl_t val);
-int32_t lsm6dso_xl_data_rate_get(stmdev_ctx_t *ctx, lsm6dso_odr_xl_t *val);
+int32_t lsm6dso_xl_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dso_odr_xl_t val);
+int32_t lsm6dso_xl_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dso_odr_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_250dps = 0,
LSM6DSO_125dps = 1,
LSM6DSO_500dps = 2,
LSM6DSO_1000dps = 4,
LSM6DSO_2000dps = 6,
} lsm6dso_fs_g_t;
-int32_t lsm6dso_gy_full_scale_set(stmdev_ctx_t *ctx, lsm6dso_fs_g_t val);
-int32_t lsm6dso_gy_full_scale_get(stmdev_ctx_t *ctx, lsm6dso_fs_g_t *val);
+int32_t lsm6dso_gy_full_scale_set(stmdev_ctx_t *ctx,
+ lsm6dso_fs_g_t val);
+int32_t lsm6dso_gy_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6dso_fs_g_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_GY_ODR_OFF = 0,
LSM6DSO_GY_ODR_12Hz5 = 1,
LSM6DSO_GY_ODR_26Hz = 2,
@@ -1589,13 +2799,17 @@ typedef enum {
LSM6DSO_GY_ODR_3333Hz = 9,
LSM6DSO_GY_ODR_6667Hz = 10,
} lsm6dso_odr_g_t;
-int32_t lsm6dso_gy_data_rate_set(stmdev_ctx_t *ctx, lsm6dso_odr_g_t val);
-int32_t lsm6dso_gy_data_rate_get(stmdev_ctx_t *ctx, lsm6dso_odr_g_t *val);
+int32_t lsm6dso_gy_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dso_odr_g_t val);
+int32_t lsm6dso_gy_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dso_odr_g_t *val);
int32_t lsm6dso_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dso_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_LSb_1mg = 0,
LSM6DSO_LSb_16mg = 1,
} lsm6dso_usr_off_w_t;
@@ -1604,7 +2818,8 @@ int32_t lsm6dso_xl_offset_weight_set(stmdev_ctx_t *ctx,
int32_t lsm6dso_xl_offset_weight_get(stmdev_ctx_t *ctx,
lsm6dso_usr_off_w_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_HIGH_PERFORMANCE_MD = 0,
LSM6DSO_LOW_NORMAL_POWER_MD = 1,
LSM6DSO_ULTRA_LOW_POWER_MD = 2,
@@ -1614,7 +2829,8 @@ int32_t lsm6dso_xl_power_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dso_xl_power_mode_get(stmdev_ctx_t *ctx,
lsm6dso_xl_hm_mode_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_GY_HIGH_PERFORMANCE = 0,
LSM6DSO_GY_NORMAL = 1,
} lsm6dso_g_hm_mode_t;
@@ -1626,11 +2842,14 @@ int32_t lsm6dso_gy_power_mode_get(stmdev_ctx_t *ctx,
int32_t lsm6dso_status_reg_get(stmdev_ctx_t *ctx,
lsm6dso_status_reg_t *val);
-int32_t lsm6dso_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dso_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dso_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dso_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t lsm6dso_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff);
@@ -1649,41 +2868,47 @@ int32_t lsm6dso_timestamp_rst(stmdev_ctx_t *ctx);
int32_t lsm6dso_timestamp_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dso_timestamp_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dso_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_NO_ROUND = 0,
LSM6DSO_ROUND_XL = 1,
LSM6DSO_ROUND_GY = 2,
LSM6DSO_ROUND_GY_XL = 3,
} lsm6dso_rounding_t;
int32_t lsm6dso_rounding_mode_set(stmdev_ctx_t *ctx,
- lsm6dso_rounding_t val);
+ lsm6dso_rounding_t val);
int32_t lsm6dso_rounding_mode_get(stmdev_ctx_t *ctx,
- lsm6dso_rounding_t *val);
+ lsm6dso_rounding_t *val);
-int32_t lsm6dso_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dso_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val);
-int32_t lsm6dso_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dso_angular_rate_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
-int32_t lsm6dso_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dso_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
int32_t lsm6dso_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dso_number_of_steps_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dso_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val);
int32_t lsm6dso_steps_reset(stmdev_ctx_t *ctx);
int32_t lsm6dso_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_USER_BANK = 0,
LSM6DSO_SENSOR_HUB_BANK = 1,
LSM6DSO_EMBEDDED_FUNC_BANK = 2,
} lsm6dso_reg_access_t;
-int32_t lsm6dso_mem_bank_set(stmdev_ctx_t *ctx, lsm6dso_reg_access_t val);
-int32_t lsm6dso_mem_bank_get(stmdev_ctx_t *ctx, lsm6dso_reg_access_t *val);
+int32_t lsm6dso_mem_bank_set(stmdev_ctx_t *ctx,
+ lsm6dso_reg_access_t val);
+int32_t lsm6dso_mem_bank_get(stmdev_ctx_t *ctx,
+ lsm6dso_reg_access_t *val);
int32_t lsm6dso_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address,
uint8_t *val);
@@ -1694,7 +2919,8 @@ int32_t lsm6dso_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address,
int32_t lsm6dso_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address,
uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_DRDY_LATCHED = 0,
LSM6DSO_DRDY_PULSED = 1,
} lsm6dso_dataready_pulsed_t;
@@ -1714,21 +2940,27 @@ int32_t lsm6dso_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dso_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_XL_ST_DISABLE = 0,
LSM6DSO_XL_ST_POSITIVE = 1,
LSM6DSO_XL_ST_NEGATIVE = 2,
} lsm6dso_st_xl_t;
-int32_t lsm6dso_xl_self_test_set(stmdev_ctx_t *ctx, lsm6dso_st_xl_t val);
-int32_t lsm6dso_xl_self_test_get(stmdev_ctx_t *ctx, lsm6dso_st_xl_t *val);
+int32_t lsm6dso_xl_self_test_set(stmdev_ctx_t *ctx,
+ lsm6dso_st_xl_t val);
+int32_t lsm6dso_xl_self_test_get(stmdev_ctx_t *ctx,
+ lsm6dso_st_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_GY_ST_DISABLE = 0,
LSM6DSO_GY_ST_POSITIVE = 1,
LSM6DSO_GY_ST_NEGATIVE = 3,
} lsm6dso_st_g_t;
-int32_t lsm6dso_gy_self_test_set(stmdev_ctx_t *ctx, lsm6dso_st_g_t val);
-int32_t lsm6dso_gy_self_test_get(stmdev_ctx_t *ctx, lsm6dso_st_g_t *val);
+int32_t lsm6dso_gy_self_test_set(stmdev_ctx_t *ctx,
+ lsm6dso_st_g_t val);
+int32_t lsm6dso_gy_self_test_get(stmdev_ctx_t *ctx,
+ lsm6dso_st_g_t *val);
int32_t lsm6dso_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1741,7 +2973,8 @@ int32_t lsm6dso_filter_settling_mask_set(stmdev_ctx_t *ctx,
int32_t lsm6dso_filter_settling_mask_get(stmdev_ctx_t *ctx,
uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_ULTRA_LIGHT = 0,
LSM6DSO_VERY_LIGHT = 1,
LSM6DSO_LIGHT = 2,
@@ -1759,7 +2992,8 @@ int32_t lsm6dso_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
int32_t lsm6dso_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_HP_PATH_DISABLE_ON_OUT = 0x00,
LSM6DSO_SLOPE_ODR_DIV_4 = 0x10,
LSM6DSO_HP_ODR_DIV_10 = 0x11,
@@ -1792,16 +3026,18 @@ int32_t lsm6dso_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
int32_t lsm6dso_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_USE_SLOPE = 0,
LSM6DSO_USE_HPF = 1,
} lsm6dso_slope_fds_t;
int32_t lsm6dso_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
- lsm6dso_slope_fds_t val);
+ lsm6dso_slope_fds_t val);
int32_t lsm6dso_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
- lsm6dso_slope_fds_t *val);
+ lsm6dso_slope_fds_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_HP_FILTER_NONE = 0x00,
LSM6DSO_HP_FILTER_16mHz = 0x80,
LSM6DSO_HP_FILTER_65mHz = 0x81,
@@ -1809,11 +3045,12 @@ typedef enum {
LSM6DSO_HP_FILTER_1Hz04 = 0x83,
} lsm6dso_hpm_g_t;
int32_t lsm6dso_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
- lsm6dso_hpm_g_t val);
+ lsm6dso_hpm_g_t val);
int32_t lsm6dso_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
- lsm6dso_hpm_g_t *val);
+ lsm6dso_hpm_g_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_AUX_PULL_UP_DISC = 0,
LSM6DSO_AUX_PULL_UP_CONNECT = 1,
} lsm6dso_ois_pu_dis_t;
@@ -1822,14 +3059,18 @@ int32_t lsm6dso_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dso_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx,
lsm6dso_ois_pu_dis_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_AUX_ON = 1,
LSM6DSO_AUX_ON_BY_AUX_INTERFACE = 0,
} lsm6dso_ois_on_t;
-int32_t lsm6dso_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx, lsm6dso_ois_on_t val);
-int32_t lsm6dso_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx, lsm6dso_ois_on_t *val);
+int32_t lsm6dso_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx,
+ lsm6dso_ois_on_t val);
+int32_t lsm6dso_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx,
+ lsm6dso_ois_on_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_USE_SAME_XL_FS = 0,
LSM6DSO_USE_DIFFERENT_XL_FS = 1,
} lsm6dso_xl_fs_mode_t;
@@ -1841,13 +3082,17 @@ int32_t lsm6dso_aux_xl_fs_mode_get(stmdev_ctx_t *ctx,
int32_t lsm6dso_aux_status_reg_get(stmdev_ctx_t *ctx,
lsm6dso_status_spiaux_t *val);
-int32_t lsm6dso_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dso_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dso_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso_aux_gy_flag_settling_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_AUX_XL_DISABLE = 0,
LSM6DSO_AUX_XL_POS = 1,
LSM6DSO_AUX_XL_NEG = 2,
@@ -1857,7 +3102,8 @@ int32_t lsm6dso_aux_xl_self_test_set(stmdev_ctx_t *ctx,
int32_t lsm6dso_aux_xl_self_test_get(stmdev_ctx_t *ctx,
lsm6dso_st_xl_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_AUX_DEN_ACTIVE_LOW = 0,
LSM6DSO_AUX_DEN_ACTIVE_HIGH = 1,
} lsm6dso_den_lh_ois_t;
@@ -1866,26 +3112,33 @@ int32_t lsm6dso_aux_den_polarity_set(stmdev_ctx_t *ctx,
int32_t lsm6dso_aux_den_polarity_get(stmdev_ctx_t *ctx,
lsm6dso_den_lh_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_AUX_DEN_DISABLE = 0,
LSM6DSO_AUX_DEN_LEVEL_LATCH = 3,
LSM6DSO_AUX_DEN_LEVEL_TRIG = 2,
} lsm6dso_lvl2_ois_t;
-int32_t lsm6dso_aux_den_mode_set(stmdev_ctx_t *ctx, lsm6dso_lvl2_ois_t val);
-int32_t lsm6dso_aux_den_mode_get(stmdev_ctx_t *ctx, lsm6dso_lvl2_ois_t *val);
+int32_t lsm6dso_aux_den_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso_lvl2_ois_t val);
+int32_t lsm6dso_aux_den_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso_lvl2_ois_t *val);
int32_t lsm6dso_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_AUX_DISABLE = 0,
LSM6DSO_MODE_3_GY = 1,
LSM6DSO_MODE_4_GY_XL = 3,
} lsm6dso_ois_en_spi2_t;
-int32_t lsm6dso_aux_mode_set(stmdev_ctx_t *ctx, lsm6dso_ois_en_spi2_t val);
-int32_t lsm6dso_aux_mode_get(stmdev_ctx_t *ctx, lsm6dso_ois_en_spi2_t *val);
+int32_t lsm6dso_aux_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso_ois_en_spi2_t val);
+int32_t lsm6dso_aux_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso_ois_en_spi2_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_250dps_AUX = 0,
LSM6DSO_125dps_AUX = 1,
LSM6DSO_500dps_AUX = 2,
@@ -1897,25 +3150,30 @@ int32_t lsm6dso_aux_gy_full_scale_set(stmdev_ctx_t *ctx,
int32_t lsm6dso_aux_gy_full_scale_get(stmdev_ctx_t *ctx,
lsm6dso_fs_g_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_AUX_SPI_4_WIRE = 0,
LSM6DSO_AUX_SPI_3_WIRE = 1,
} lsm6dso_sim_ois_t;
-int32_t lsm6dso_aux_spi_mode_set(stmdev_ctx_t *ctx, lsm6dso_sim_ois_t val);
-int32_t lsm6dso_aux_spi_mode_get(stmdev_ctx_t *ctx, lsm6dso_sim_ois_t *val);
+int32_t lsm6dso_aux_spi_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso_sim_ois_t val);
+int32_t lsm6dso_aux_spi_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso_sim_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_351Hz39 = 0,
LSM6DSO_236Hz63 = 1,
LSM6DSO_172Hz70 = 2,
LSM6DSO_937Hz91 = 3,
} lsm6dso_ftype_ois_t;
int32_t lsm6dso_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
- lsm6dso_ftype_ois_t val);
+ lsm6dso_ftype_ois_t val);
int32_t lsm6dso_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
- lsm6dso_ftype_ois_t *val);
+ lsm6dso_ftype_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_AUX_HP_DISABLE = 0x00,
LSM6DSO_AUX_HP_Hz016 = 0x10,
LSM6DSO_AUX_HP_Hz065 = 0x11,
@@ -1923,11 +3181,12 @@ typedef enum {
LSM6DSO_AUX_HP_1Hz040 = 0x13,
} lsm6dso_hpm_ois_t;
int32_t lsm6dso_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx,
- lsm6dso_hpm_ois_t val);
+ lsm6dso_hpm_ois_t val);
int32_t lsm6dso_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx,
- lsm6dso_hpm_ois_t *val);
+ lsm6dso_hpm_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_ENABLE_CLAMP = 0,
LSM6DSO_DISABLE_CLAMP = 1,
} lsm6dso_st_ois_clampdis_t;
@@ -1936,7 +3195,8 @@ int32_t lsm6dso_aux_gy_clamp_set(stmdev_ctx_t *ctx,
int32_t lsm6dso_aux_gy_clamp_get(stmdev_ctx_t *ctx,
lsm6dso_st_ois_clampdis_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_AUX_GY_DISABLE = 0,
LSM6DSO_AUX_GY_POS = 1,
LSM6DSO_AUX_GY_NEG = 3,
@@ -1946,7 +3206,8 @@ int32_t lsm6dso_aux_gy_self_test_set(stmdev_ctx_t *ctx,
int32_t lsm6dso_aux_gy_self_test_get(stmdev_ctx_t *ctx,
lsm6dso_st_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_289Hz = 0,
LSM6DSO_258Hz = 1,
LSM6DSO_120Hz = 2,
@@ -1961,7 +3222,8 @@ int32_t lsm6dso_aux_xl_bandwidth_set(stmdev_ctx_t *ctx,
int32_t lsm6dso_aux_xl_bandwidth_get(stmdev_ctx_t *ctx,
lsm6dso_filter_xl_conf_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_AUX_2g = 0,
LSM6DSO_AUX_16g = 1,
LSM6DSO_AUX_4g = 2,
@@ -1972,7 +3234,8 @@ int32_t lsm6dso_aux_xl_full_scale_set(stmdev_ctx_t *ctx,
int32_t lsm6dso_aux_xl_full_scale_get(stmdev_ctx_t *ctx,
lsm6dso_fs_xl_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_PULL_UP_DISC = 0,
LSM6DSO_PULL_UP_CONNECT = 1,
} lsm6dso_sdo_pu_en_t;
@@ -1981,14 +3244,16 @@ int32_t lsm6dso_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dso_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
lsm6dso_sdo_pu_en_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_SPI_4_WIRE = 0,
LSM6DSO_SPI_3_WIRE = 1,
} lsm6dso_sim_t;
int32_t lsm6dso_spi_mode_set(stmdev_ctx_t *ctx, lsm6dso_sim_t val);
int32_t lsm6dso_spi_mode_get(stmdev_ctx_t *ctx, lsm6dso_sim_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_I2C_ENABLE = 0,
LSM6DSO_I2C_DISABLE = 1,
} lsm6dso_i2c_disable_t;
@@ -1997,7 +3262,8 @@ int32_t lsm6dso_i2c_interface_set(stmdev_ctx_t *ctx,
int32_t lsm6dso_i2c_interface_get(stmdev_ctx_t *ctx,
lsm6dso_i2c_disable_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_I3C_DISABLE = 0x80,
LSM6DSO_I3C_ENABLE_T_50us = 0x00,
LSM6DSO_I3C_ENABLE_T_2us = 0x01,
@@ -2009,7 +3275,8 @@ int32_t lsm6dso_i3c_disable_set(stmdev_ctx_t *ctx,
int32_t lsm6dso_i3c_disable_get(stmdev_ctx_t *ctx,
lsm6dso_i3c_disable_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_PULL_DOWN_DISC = 0,
LSM6DSO_PULL_DOWN_CONNECT = 1,
} lsm6dso_int1_pd_en_t;
@@ -2018,14 +3285,16 @@ int32_t lsm6dso_int1_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dso_int1_mode_get(stmdev_ctx_t *ctx,
lsm6dso_int1_pd_en_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_PUSH_PULL = 0,
LSM6DSO_OPEN_DRAIN = 1,
} lsm6dso_pp_od_t;
int32_t lsm6dso_pin_mode_set(stmdev_ctx_t *ctx, lsm6dso_pp_od_t val);
int32_t lsm6dso_pin_mode_get(stmdev_ctx_t *ctx, lsm6dso_pp_od_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_ACTIVE_HIGH = 0,
LSM6DSO_ACTIVE_LOW = 1,
} lsm6dso_h_lactive_t;
@@ -2037,29 +3306,35 @@ int32_t lsm6dso_pin_polarity_get(stmdev_ctx_t *ctx,
int32_t lsm6dso_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_ALL_INT_PULSED = 0,
LSM6DSO_BASE_LATCHED_EMB_PULSED = 1,
LSM6DSO_BASE_PULSED_EMB_LATCHED = 2,
LSM6DSO_ALL_INT_LATCHED = 3,
} lsm6dso_lir_t;
-int32_t lsm6dso_int_notification_set(stmdev_ctx_t *ctx, lsm6dso_lir_t val);
-int32_t lsm6dso_int_notification_get(stmdev_ctx_t *ctx, lsm6dso_lir_t *val);
+int32_t lsm6dso_int_notification_set(stmdev_ctx_t *ctx,
+ lsm6dso_lir_t val);
+int32_t lsm6dso_int_notification_get(stmdev_ctx_t *ctx,
+ lsm6dso_lir_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_LSb_FS_DIV_64 = 0,
LSM6DSO_LSb_FS_DIV_256 = 1,
} lsm6dso_wake_ths_w_t;
int32_t lsm6dso_wkup_ths_weight_set(stmdev_ctx_t *ctx,
- lsm6dso_wake_ths_w_t val);
+ lsm6dso_wake_ths_w_t val);
int32_t lsm6dso_wkup_ths_weight_get(stmdev_ctx_t *ctx,
- lsm6dso_wake_ths_w_t *val);
+ lsm6dso_wake_ths_w_t *val);
int32_t lsm6dso_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dso_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dso_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dso_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -2067,7 +3342,8 @@ int32_t lsm6dso_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dso_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_DRIVE_SLEEP_CHG_EVENT = 0,
LSM6DSO_DRIVE_SLEEP_STATUS = 1,
} lsm6dso_sleep_status_on_int_t;
@@ -2076,31 +3352,41 @@ int32_t lsm6dso_act_pin_notification_set(stmdev_ctx_t *ctx,
int32_t lsm6dso_act_pin_notification_get(stmdev_ctx_t *ctx,
lsm6dso_sleep_status_on_int_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_XL_AND_GY_NOT_AFFECTED = 0,
LSM6DSO_XL_12Hz5_GY_NOT_AFFECTED = 1,
LSM6DSO_XL_12Hz5_GY_SLEEP = 2,
LSM6DSO_XL_12Hz5_GY_PD = 3,
} lsm6dso_inact_en_t;
-int32_t lsm6dso_act_mode_set(stmdev_ctx_t *ctx, lsm6dso_inact_en_t val);
-int32_t lsm6dso_act_mode_get(stmdev_ctx_t *ctx, lsm6dso_inact_en_t *val);
+int32_t lsm6dso_act_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso_inact_en_t val);
+int32_t lsm6dso_act_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso_inact_en_t *val);
int32_t lsm6dso_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dso_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dso_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso_tap_detection_on_z_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dso_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dso_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dso_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dso_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dso_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_XYZ = 0,
LSM6DSO_YXZ = 1,
LSM6DSO_XZY = 2,
@@ -2128,7 +3414,8 @@ int32_t lsm6dso_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dso_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_ONLY_SINGLE = 0,
LSM6DSO_BOTH_SINGLE_DOUBLE = 1,
} lsm6dso_single_double_tap_t;
@@ -2137,19 +3424,23 @@ int32_t lsm6dso_tap_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dso_tap_mode_get(stmdev_ctx_t *ctx,
lsm6dso_single_double_tap_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_DEG_80 = 0,
LSM6DSO_DEG_70 = 1,
LSM6DSO_DEG_60 = 2,
LSM6DSO_DEG_50 = 3,
} lsm6dso_sixd_ths_t;
-int32_t lsm6dso_6d_threshold_set(stmdev_ctx_t *ctx, lsm6dso_sixd_ths_t val);
-int32_t lsm6dso_6d_threshold_get(stmdev_ctx_t *ctx, lsm6dso_sixd_ths_t *val);
+int32_t lsm6dso_6d_threshold_set(stmdev_ctx_t *ctx,
+ lsm6dso_sixd_ths_t val);
+int32_t lsm6dso_6d_threshold_get(stmdev_ctx_t *ctx,
+ lsm6dso_sixd_ths_t *val);
int32_t lsm6dso_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_FF_TSH_156mg = 0,
LSM6DSO_FF_TSH_219mg = 1,
LSM6DSO_FF_TSH_250mg = 2,
@@ -2159,8 +3450,10 @@ typedef enum {
LSM6DSO_FF_TSH_469mg = 6,
LSM6DSO_FF_TSH_500mg = 7,
} lsm6dso_ff_ths_t;
-int32_t lsm6dso_ff_threshold_set(stmdev_ctx_t *ctx, lsm6dso_ff_ths_t val);
-int32_t lsm6dso_ff_threshold_get(stmdev_ctx_t *ctx, lsm6dso_ff_ths_t *val);
+int32_t lsm6dso_ff_threshold_set(stmdev_ctx_t *ctx,
+ lsm6dso_ff_ths_t val);
+int32_t lsm6dso_ff_threshold_get(stmdev_ctx_t *ctx,
+ lsm6dso_ff_ths_t *val);
int32_t lsm6dso_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -2168,10 +3461,13 @@ int32_t lsm6dso_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dso_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val);
int32_t lsm6dso_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val);
-int32_t lsm6dso_compression_algo_init_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dso_compression_algo_init_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso_compression_algo_init_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso_compression_algo_init_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_CMP_DISABLE = 0x00,
LSM6DSO_CMP_ALWAYS = 0x04,
LSM6DSO_CMP_8_TO_1 = 0x05,
@@ -2196,7 +3492,8 @@ int32_t lsm6dso_compression_algo_real_time_get(stmdev_ctx_t *ctx,
int32_t lsm6dso_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_XL_NOT_BATCHED = 0,
LSM6DSO_XL_BATCHED_AT_12Hz5 = 1,
LSM6DSO_XL_BATCHED_AT_26Hz = 2,
@@ -2210,10 +3507,13 @@ typedef enum {
LSM6DSO_XL_BATCHED_AT_6667Hz = 10,
LSM6DSO_XL_BATCHED_AT_6Hz5 = 11,
} lsm6dso_bdr_xl_t;
-int32_t lsm6dso_fifo_xl_batch_set(stmdev_ctx_t *ctx, lsm6dso_bdr_xl_t val);
-int32_t lsm6dso_fifo_xl_batch_get(stmdev_ctx_t *ctx, lsm6dso_bdr_xl_t *val);
+int32_t lsm6dso_fifo_xl_batch_set(stmdev_ctx_t *ctx,
+ lsm6dso_bdr_xl_t val);
+int32_t lsm6dso_fifo_xl_batch_get(stmdev_ctx_t *ctx,
+ lsm6dso_bdr_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_GY_NOT_BATCHED = 0,
LSM6DSO_GY_BATCHED_AT_12Hz5 = 1,
LSM6DSO_GY_BATCHED_AT_26Hz = 2,
@@ -2227,10 +3527,13 @@ typedef enum {
LSM6DSO_GY_BATCHED_AT_6667Hz = 10,
LSM6DSO_GY_BATCHED_AT_6Hz5 = 11,
} lsm6dso_bdr_gy_t;
-int32_t lsm6dso_fifo_gy_batch_set(stmdev_ctx_t *ctx, lsm6dso_bdr_gy_t val);
-int32_t lsm6dso_fifo_gy_batch_get(stmdev_ctx_t *ctx, lsm6dso_bdr_gy_t *val);
+int32_t lsm6dso_fifo_gy_batch_set(stmdev_ctx_t *ctx,
+ lsm6dso_bdr_gy_t val);
+int32_t lsm6dso_fifo_gy_batch_get(stmdev_ctx_t *ctx,
+ lsm6dso_bdr_gy_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_BYPASS_MODE = 0,
LSM6DSO_FIFO_MODE = 1,
LSM6DSO_STREAM_TO_FIFO_MODE = 3,
@@ -2238,10 +3541,13 @@ typedef enum {
LSM6DSO_STREAM_MODE = 6,
LSM6DSO_BYPASS_TO_FIFO_MODE = 7,
} lsm6dso_fifo_mode_t;
-int32_t lsm6dso_fifo_mode_set(stmdev_ctx_t *ctx, lsm6dso_fifo_mode_t val);
-int32_t lsm6dso_fifo_mode_get(stmdev_ctx_t *ctx, lsm6dso_fifo_mode_t *val);
+int32_t lsm6dso_fifo_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso_fifo_mode_t val);
+int32_t lsm6dso_fifo_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso_fifo_mode_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_TEMP_NOT_BATCHED = 0,
LSM6DSO_TEMP_BATCHED_AT_1Hz6 = 1,
LSM6DSO_TEMP_BATCHED_AT_12Hz5 = 2,
@@ -2252,7 +3558,8 @@ int32_t lsm6dso_fifo_temp_batch_set(stmdev_ctx_t *ctx,
int32_t lsm6dso_fifo_temp_batch_get(stmdev_ctx_t *ctx,
lsm6dso_odr_t_batch_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_NO_DECIMATION = 0,
LSM6DSO_DEC_1 = 1,
LSM6DSO_DEC_8 = 2,
@@ -2263,12 +3570,14 @@ int32_t lsm6dso_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
int32_t lsm6dso_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
lsm6dso_odr_ts_batch_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_XL_BATCH_EVENT = 0,
LSM6DSO_GYRO_BATCH_EVENT = 1,
} lsm6dso_trig_counter_bdr_t;
-typedef enum {
+typedef enum
+{
LSM6DSO_GYRO_NC_TAG = 1,
LSM6DSO_XL_NC_TAG,
LSM6DSO_TEMPERATURE_TAG,
@@ -2293,12 +3602,13 @@ typedef enum {
LSM6DSO_SENSORHUB_NACK_TAG = 0x19,
} lsm6dso_fifo_tag_t;
int32_t lsm6dso_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
- lsm6dso_trig_counter_bdr_t val);
+ lsm6dso_trig_counter_bdr_t val);
int32_t lsm6dso_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
- lsm6dso_trig_counter_bdr_t *val);
+ lsm6dso_trig_counter_bdr_t *val);
int32_t lsm6dso_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dso_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso_rst_batch_counter_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dso_batch_counter_threshold_set(stmdev_ctx_t *ctx,
uint16_t val);
@@ -2317,7 +3627,7 @@ int32_t lsm6dso_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dso_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dso_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
- lsm6dso_fifo_tag_t *val);
+ lsm6dso_fifo_tag_t *val);
int32_t lsm6dso_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -2334,30 +3644,39 @@ int32_t lsm6dso_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dso_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_DEN_DISABLE = 0,
LSM6DSO_LEVEL_FIFO = 6,
LSM6DSO_LEVEL_LETCHED = 3,
LSM6DSO_LEVEL_TRIGGER = 2,
LSM6DSO_EDGE_TRIGGER = 4,
} lsm6dso_den_mode_t;
-int32_t lsm6dso_den_mode_set(stmdev_ctx_t *ctx, lsm6dso_den_mode_t val);
-int32_t lsm6dso_den_mode_get(stmdev_ctx_t *ctx, lsm6dso_den_mode_t *val);
+int32_t lsm6dso_den_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso_den_mode_t val);
+int32_t lsm6dso_den_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso_den_mode_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_DEN_ACT_LOW = 0,
LSM6DSO_DEN_ACT_HIGH = 1,
} lsm6dso_den_lh_t;
-int32_t lsm6dso_den_polarity_set(stmdev_ctx_t *ctx, lsm6dso_den_lh_t val);
-int32_t lsm6dso_den_polarity_get(stmdev_ctx_t *ctx, lsm6dso_den_lh_t *val);
+int32_t lsm6dso_den_polarity_set(stmdev_ctx_t *ctx,
+ lsm6dso_den_lh_t val);
+int32_t lsm6dso_den_polarity_get(stmdev_ctx_t *ctx,
+ lsm6dso_den_lh_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_STAMP_IN_GY_DATA = 0,
LSM6DSO_STAMP_IN_XL_DATA = 1,
LSM6DSO_STAMP_IN_GY_XL_DATA = 2,
} lsm6dso_den_xl_g_t;
-int32_t lsm6dso_den_enable_set(stmdev_ctx_t *ctx, lsm6dso_den_xl_g_t val);
-int32_t lsm6dso_den_enable_get(stmdev_ctx_t *ctx, lsm6dso_den_xl_g_t *val);
+int32_t lsm6dso_den_enable_set(stmdev_ctx_t *ctx,
+ lsm6dso_den_xl_g_t val);
+int32_t lsm6dso_den_enable_get(stmdev_ctx_t *ctx,
+ lsm6dso_den_xl_g_t *val);
int32_t lsm6dso_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -2368,26 +3687,31 @@ int32_t lsm6dso_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dso_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
- LSM6DSO_PEDO_DISABLE = 0x00,
- LSM6DSO_PEDO_BASE_MODE = 0x01,
- LSM6DSO_FALSE_STEP_REJ = 0x13,
- LSM6DSO_FALSE_STEP_REJ_ADV_MODE = 0x33,
+typedef enum
+{
+ LSM6DSO_PEDO_BASE_MODE = 0x00,
+ LSM6DSO_FALSE_STEP_REJ = 0x10,
+ LSM6DSO_FALSE_STEP_REJ_ADV_MODE = 0x30,
} lsm6dso_pedo_md_t;
-int32_t lsm6dso_pedo_sens_set(stmdev_ctx_t *ctx, lsm6dso_pedo_md_t val);
-int32_t lsm6dso_pedo_sens_get(stmdev_ctx_t *ctx, lsm6dso_pedo_md_t *val);
+int32_t lsm6dso_pedo_sens_set(stmdev_ctx_t *ctx,
+ lsm6dso_pedo_md_t val);
+int32_t lsm6dso_pedo_sens_get(stmdev_ctx_t *ctx,
+ lsm6dso_pedo_md_t *val);
int32_t lsm6dso_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dso_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
- uint8_t *buff);
+ uint8_t *buff);
int32_t lsm6dso_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
- uint8_t *buff);
+ uint8_t *buff);
-int32_t lsm6dso_pedo_steps_period_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dso_pedo_steps_period_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dso_pedo_steps_period_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t lsm6dso_pedo_steps_period_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_EVERY_STEP = 0,
LSM6DSO_COUNT_OVERFLOW = 1,
} lsm6dso_carry_count_en_t;
@@ -2396,28 +3720,23 @@ int32_t lsm6dso_pedo_int_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dso_pedo_int_mode_get(stmdev_ctx_t *ctx,
lsm6dso_carry_count_en_t *val);
-int32_t lsm6dso_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dso_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
-
int32_t lsm6dso_motion_flag_data_ready_get(stmdev_ctx_t *ctx,
- uint8_t *val);
-
-int32_t lsm6dso_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dso_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
+ uint8_t *val);
int32_t lsm6dso_tilt_flag_data_ready_get(stmdev_ctx_t *ctx,
- uint8_t *val);
+ uint8_t *val);
-int32_t lsm6dso_mag_sensitivity_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dso_mag_sensitivity_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dso_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val);
+int32_t lsm6dso_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val);
-int32_t lsm6dso_mag_offset_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dso_mag_offset_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dso_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val);
+int32_t lsm6dso_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val);
-int32_t lsm6dso_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dso_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dso_mag_soft_iron_set(stmdev_ctx_t *ctx, int16_t *val);
+int32_t lsm6dso_mag_soft_iron_get(stmdev_ctx_t *ctx, int16_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_Z_EQ_Y = 0,
LSM6DSO_Z_EQ_MIN_Y = 1,
LSM6DSO_Z_EQ_X = 2,
@@ -2426,11 +3745,12 @@ typedef enum {
LSM6DSO_Z_EQ_Z = 5,
} lsm6dso_mag_z_axis_t;
int32_t lsm6dso_mag_z_orient_set(stmdev_ctx_t *ctx,
- lsm6dso_mag_z_axis_t val);
+ lsm6dso_mag_z_axis_t val);
int32_t lsm6dso_mag_z_orient_get(stmdev_ctx_t *ctx,
- lsm6dso_mag_z_axis_t *val);
+ lsm6dso_mag_z_axis_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_Y_EQ_Y = 0,
LSM6DSO_Y_EQ_MIN_Y = 1,
LSM6DSO_Y_EQ_X = 2,
@@ -2439,11 +3759,12 @@ typedef enum {
LSM6DSO_Y_EQ_Z = 5,
} lsm6dso_mag_y_axis_t;
int32_t lsm6dso_mag_y_orient_set(stmdev_ctx_t *ctx,
- lsm6dso_mag_y_axis_t val);
+ lsm6dso_mag_y_axis_t val);
int32_t lsm6dso_mag_y_orient_get(stmdev_ctx_t *ctx,
- lsm6dso_mag_y_axis_t *val);
+ lsm6dso_mag_y_axis_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_X_EQ_Y = 0,
LSM6DSO_X_EQ_MIN_Y = 1,
LSM6DSO_X_EQ_X = 2,
@@ -2452,81 +3773,94 @@ typedef enum {
LSM6DSO_X_EQ_Z = 5,
} lsm6dso_mag_x_axis_t;
int32_t lsm6dso_mag_x_orient_set(stmdev_ctx_t *ctx,
- lsm6dso_mag_x_axis_t val);
+ lsm6dso_mag_x_axis_t val);
int32_t lsm6dso_mag_x_orient_get(stmdev_ctx_t *ctx,
- lsm6dso_mag_x_axis_t *val);
+ lsm6dso_mag_x_axis_t *val);
int32_t lsm6dso_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
uint8_t *val);
-int32_t lsm6dso_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dso_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val);
-
-typedef struct {
- lsm6dso_fsm_enable_a_t fsm_enable_a;
- lsm6dso_fsm_enable_b_t fsm_enable_b;
+typedef struct
+{
+ lsm6dso_fsm_enable_a_t fsm_enable_a;
+ lsm6dso_fsm_enable_b_t fsm_enable_b;
} lsm6dso_emb_fsm_enable_t;
int32_t lsm6dso_fsm_enable_set(stmdev_ctx_t *ctx,
lsm6dso_emb_fsm_enable_t *val);
int32_t lsm6dso_fsm_enable_get(stmdev_ctx_t *ctx,
lsm6dso_emb_fsm_enable_t *val);
-int32_t lsm6dso_long_cnt_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dso_long_cnt_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dso_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val);
+int32_t lsm6dso_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_LC_NORMAL = 0,
LSM6DSO_LC_CLEAR = 1,
LSM6DSO_LC_CLEAR_DONE = 2,
} lsm6dso_fsm_lc_clr_t;
-int32_t lsm6dso_long_clr_set(stmdev_ctx_t *ctx, lsm6dso_fsm_lc_clr_t val);
-int32_t lsm6dso_long_clr_get(stmdev_ctx_t *ctx, lsm6dso_fsm_lc_clr_t *val);
-
-typedef struct {
- lsm6dso_fsm_outs1_t fsm_outs1;
- lsm6dso_fsm_outs2_t fsm_outs2;
- lsm6dso_fsm_outs3_t fsm_outs3;
- lsm6dso_fsm_outs4_t fsm_outs4;
- lsm6dso_fsm_outs5_t fsm_outs5;
- lsm6dso_fsm_outs6_t fsm_outs6;
- lsm6dso_fsm_outs7_t fsm_outs7;
- lsm6dso_fsm_outs8_t fsm_outs8;
- lsm6dso_fsm_outs9_t fsm_outs9;
- lsm6dso_fsm_outs10_t fsm_outs10;
- lsm6dso_fsm_outs11_t fsm_outs11;
- lsm6dso_fsm_outs12_t fsm_outs12;
- lsm6dso_fsm_outs13_t fsm_outs13;
- lsm6dso_fsm_outs14_t fsm_outs14;
- lsm6dso_fsm_outs15_t fsm_outs15;
- lsm6dso_fsm_outs16_t fsm_outs16;
+int32_t lsm6dso_long_clr_set(stmdev_ctx_t *ctx,
+ lsm6dso_fsm_lc_clr_t val);
+int32_t lsm6dso_long_clr_get(stmdev_ctx_t *ctx,
+ lsm6dso_fsm_lc_clr_t *val);
+
+typedef struct
+{
+ lsm6dso_fsm_outs1_t fsm_outs1;
+ lsm6dso_fsm_outs2_t fsm_outs2;
+ lsm6dso_fsm_outs3_t fsm_outs3;
+ lsm6dso_fsm_outs4_t fsm_outs4;
+ lsm6dso_fsm_outs5_t fsm_outs5;
+ lsm6dso_fsm_outs6_t fsm_outs6;
+ lsm6dso_fsm_outs7_t fsm_outs7;
+ lsm6dso_fsm_outs8_t fsm_outs8;
+ lsm6dso_fsm_outs9_t fsm_outs9;
+ lsm6dso_fsm_outs10_t fsm_outs10;
+ lsm6dso_fsm_outs11_t fsm_outs11;
+ lsm6dso_fsm_outs12_t fsm_outs12;
+ lsm6dso_fsm_outs13_t fsm_outs13;
+ lsm6dso_fsm_outs14_t fsm_outs14;
+ lsm6dso_fsm_outs15_t fsm_outs15;
+ lsm6dso_fsm_outs16_t fsm_outs16;
} lsm6dso_fsm_out_t;
-int32_t lsm6dso_fsm_out_get(stmdev_ctx_t *ctx, lsm6dso_fsm_out_t *val);
+int32_t lsm6dso_fsm_out_get(stmdev_ctx_t *ctx,
+ lsm6dso_fsm_out_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_ODR_FSM_12Hz5 = 0,
LSM6DSO_ODR_FSM_26Hz = 1,
LSM6DSO_ODR_FSM_52Hz = 2,
LSM6DSO_ODR_FSM_104Hz = 3,
} lsm6dso_fsm_odr_t;
-int32_t lsm6dso_fsm_data_rate_set(stmdev_ctx_t *ctx, lsm6dso_fsm_odr_t val);
-int32_t lsm6dso_fsm_data_rate_get(stmdev_ctx_t *ctx, lsm6dso_fsm_odr_t *val);
+int32_t lsm6dso_fsm_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dso_fsm_odr_t val);
+int32_t lsm6dso_fsm_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dso_fsm_odr_t *val);
int32_t lsm6dso_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dso_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint16_t val);
-int32_t lsm6dso_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t lsm6dso_long_cnt_int_value_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t lsm6dso_long_cnt_int_value_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
-int32_t lsm6dso_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dso_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dso_fsm_number_of_programs_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dso_fsm_number_of_programs_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dso_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val);
-int32_t lsm6dso_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t lsm6dso_fsm_start_address_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t lsm6dso_fsm_start_address_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
int32_t lsm6dso_sh_read_data_raw_get(stmdev_ctx_t *ctx, uint8_t *val,
uint8_t len);
-typedef enum {
+typedef enum
+{
LSM6DSO_SLV_0 = 0,
LSM6DSO_SLV_0_1 = 1,
LSM6DSO_SLV_0_1_2 = 2,
@@ -2540,26 +3874,31 @@ int32_t lsm6dso_sh_slave_connected_get(stmdev_ctx_t *ctx,
int32_t lsm6dso_sh_master_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_EXT_PULL_UP = 0,
LSM6DSO_INTERNAL_PULL_UP = 1,
} lsm6dso_shub_pu_en_t;
-int32_t lsm6dso_sh_pin_mode_set(stmdev_ctx_t *ctx, lsm6dso_shub_pu_en_t val);
-int32_t lsm6dso_sh_pin_mode_get(stmdev_ctx_t *ctx, lsm6dso_shub_pu_en_t *val);
+int32_t lsm6dso_sh_pin_mode_set(stmdev_ctx_t *ctx,
+ lsm6dso_shub_pu_en_t val);
+int32_t lsm6dso_sh_pin_mode_get(stmdev_ctx_t *ctx,
+ lsm6dso_shub_pu_en_t *val);
int32_t lsm6dso_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dso_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
- LSM6DSO_EXT_ON_INT2_PIN = 0,
- LSM6DSO_XL_GY_DRDY = 1,
+typedef enum
+{
+ LSM6DSO_EXT_ON_INT2_PIN = 1,
+ LSM6DSO_XL_GY_DRDY = 0,
} lsm6dso_start_config_t;
int32_t lsm6dso_sh_syncro_mode_set(stmdev_ctx_t *ctx,
lsm6dso_start_config_t val);
int32_t lsm6dso_sh_syncro_mode_get(stmdev_ctx_t *ctx,
lsm6dso_start_config_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_EACH_SH_CYCLE = 0,
LSM6DSO_ONLY_FIRST_CYCLE = 1,
} lsm6dso_write_once_t;
@@ -2571,23 +3910,29 @@ int32_t lsm6dso_sh_write_mode_get(stmdev_ctx_t *ctx,
int32_t lsm6dso_sh_reset_set(stmdev_ctx_t *ctx);
int32_t lsm6dso_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_SH_ODR_104Hz = 0,
LSM6DSO_SH_ODR_52Hz = 1,
LSM6DSO_SH_ODR_26Hz = 2,
LSM6DSO_SH_ODR_13Hz = 3,
} lsm6dso_shub_odr_t;
-int32_t lsm6dso_sh_data_rate_set(stmdev_ctx_t *ctx, lsm6dso_shub_odr_t val);
-int32_t lsm6dso_sh_data_rate_get(stmdev_ctx_t *ctx, lsm6dso_shub_odr_t *val);
+int32_t lsm6dso_sh_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dso_shub_odr_t val);
+int32_t lsm6dso_sh_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dso_shub_odr_t *val);
-typedef struct{
+typedef struct
+{
uint8_t slv0_add;
uint8_t slv0_subadd;
uint8_t slv0_data;
} lsm6dso_sh_cfg_write_t;
-int32_t lsm6dso_sh_cfg_write(stmdev_ctx_t *ctx, lsm6dso_sh_cfg_write_t *val);
+int32_t lsm6dso_sh_cfg_write(stmdev_ctx_t *ctx,
+ lsm6dso_sh_cfg_write_t *val);
-typedef struct{
+typedef struct
+{
uint8_t slv_add;
uint8_t slv_subadd;
uint8_t slv_len;
@@ -2605,15 +3950,18 @@ int32_t lsm6dso_sh_status_get(stmdev_ctx_t *ctx,
lsm6dso_status_master_t *val);
-typedef struct {
+typedef struct
+{
uint8_t ui;
uint8_t aux;
} lsm6dso_id_t;
int32_t lsm6dso_id_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
- lsm6dso_id_t *val);
+ lsm6dso_id_t *val);
-typedef struct {
- enum {
+typedef struct
+{
+ enum
+ {
LSM6DSO_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */
LSM6DSO_SPI_4W = 0x06, /* Only SPI: SDO / SDI separated pins */
LSM6DSO_SPI_3W = 0x07, /* Only SPI: SDO / SDI share the same pin */
@@ -2623,17 +3971,19 @@ typedef struct {
LSM6DSO_I3C_T_1ms = 0x22, /* I3C: available time equal to 1 ms */
LSM6DSO_I3C_T_25ms = 0x32, /* I3C: available time equal to 25 ms */
} ui_bus_md;
- enum {
+ enum
+ {
LSM6DSO_SPI_4W_AUX = 0x00,
LSM6DSO_SPI_3W_AUX = 0x01,
} aux_bus_md;
} lsm6dso_bus_mode_t;
int32_t lsm6dso_bus_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
- lsm6dso_bus_mode_t val);
+ lsm6dso_bus_mode_t val);
int32_t lsm6dso_bus_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
- lsm6dso_bus_mode_t *val);
+ lsm6dso_bus_mode_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSO_DRV_RDY = 0x00, /* Initialize the device for driver usage */
LSM6DSO_BOOT = 0x01, /* Restore calib. param. ( it takes 10ms ) */
LSM6DSO_RESET = 0x02, /* Reset configuration registers */
@@ -2645,60 +3995,77 @@ typedef enum {
} lsm6dso_init_t;
int32_t lsm6dso_init_set(stmdev_ctx_t *ctx, lsm6dso_init_t val);
-typedef struct {
- uint8_t sw_reset : 1; /* Restoring configuration registers */
+typedef struct
+{
+uint8_t sw_reset :
+ 1; /* Restoring configuration registers */
uint8_t boot : 1; /* Restoring calibration parameters */
uint8_t drdy_xl : 1; /* Accelerometer data ready */
uint8_t drdy_g : 1; /* Gyroscope data ready */
uint8_t drdy_temp : 1; /* Temperature data ready */
uint8_t ois_drdy_xl : 1; /* Accelerometer data ready on OIS */
uint8_t ois_drdy_g : 1; /* Gyroscope data ready on OIS */
- uint8_t ois_gyro_settling : 1; /* Gyroscope is in the settling phase */
+uint8_t ois_gyro_settling :
+ 1; /* Gyroscope is in the settling phase */
} lsm6dso_status_t;
int32_t lsm6dso_status_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
- lsm6dso_status_t *val);
+ lsm6dso_status_t *val);
-typedef struct {
+typedef struct
+{
uint8_t sdo_sa0_pull_up : 1; /* 1 = pull-up on SDO/SA0 pin */
- uint8_t aux_sdo_ocs_pull_up : 1; /* 1 = pull-up on OCS_Aux/SDO_Aux pins */
+uint8_t aux_sdo_ocs_pull_up :
+ 1; /* 1 = pull-up on OCS_Aux/SDO_Aux pins */
uint8_t int1_int2_push_pull : 1; /* 1 = push-pull / 0 = open-drain*/
- uint8_t int1_pull_down : 1; /* 1 = pull-down always disabled (0=auto) */
+uint8_t int1_pull_down :
+ 1; /* 1 = pull-down always disabled (0=auto) */
} lsm6dso_pin_conf_t;
-int32_t lsm6dso_pin_conf_set(stmdev_ctx_t *ctx, lsm6dso_pin_conf_t val);
-int32_t lsm6dso_pin_conf_get(stmdev_ctx_t *ctx, lsm6dso_pin_conf_t *val);
+int32_t lsm6dso_pin_conf_set(stmdev_ctx_t *ctx,
+ lsm6dso_pin_conf_t val);
+int32_t lsm6dso_pin_conf_get(stmdev_ctx_t *ctx,
+ lsm6dso_pin_conf_t *val);
-typedef struct {
+typedef struct
+{
uint8_t active_low : 1; /* 1 = active low / 0 = active high */
- uint8_t base_latched : 1; /* base functions are: FF, WU, 6D, Tap, Act/Inac */
- uint8_t emb_latched : 1; /* emb functions are: Pedo, Tilt, SMot, Timestamp */
+uint8_t base_latched :
+ 1; /* base functions are: FF, WU, 6D, Tap, Act/Inac */
+uint8_t emb_latched :
+ 1; /* emb functions are: Pedo, Tilt, SMot, Timestamp */
} lsm6dso_int_mode_t;
int32_t lsm6dso_interrupt_mode_set(stmdev_ctx_t *ctx,
- lsm6dso_int_mode_t val);
+ lsm6dso_int_mode_t val);
int32_t lsm6dso_interrupt_mode_get(stmdev_ctx_t *ctx,
- lsm6dso_int_mode_t *val);
+ lsm6dso_int_mode_t *val);
-typedef struct {
+typedef struct
+{
uint8_t drdy_xl : 1; /* Accelerometer data ready */
uint8_t drdy_g : 1; /* Gyroscope data ready */
- uint8_t drdy_temp : 1; /* Temperature data ready (1 = int2 pin disable) */
+uint8_t drdy_temp :
+ 1; /* Temperature data ready (1 = int2 pin disable) */
uint8_t boot : 1; /* Restoring calibration parameters */
uint8_t fifo_th : 1; /* FIFO threshold reached */
uint8_t fifo_ovr : 1; /* FIFO overrun */
uint8_t fifo_full : 1; /* FIFO full */
uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */
- uint8_t den_flag : 1; /* external trigger level recognition (DEN) */
+uint8_t den_flag :
+ 1; /* external trigger level recognition (DEN) */
uint8_t sh_endop : 1; /* sensor hub end operation */
- uint8_t timestamp : 1; /* timestamp overflow (1 = int2 pin disable) */
+uint8_t timestamp :
+ 1; /* timestamp overflow (1 = int2 pin disable) */
uint8_t six_d : 1; /* orientation change (6D/4D detection) */
uint8_t double_tap : 1; /* double-tap event */
uint8_t free_fall : 1; /* free fall event */
uint8_t wake_up : 1; /* wake up event */
uint8_t single_tap : 1; /* single-tap event */
- uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */
+uint8_t sleep_change :
+ 1; /* Act/Inact (or Vice-versa) status changed */
uint8_t step_detector : 1; /* Step detected */
uint8_t tilt : 1; /* Relative tilt event detected */
uint8_t sig_mot : 1; /* "significant motion" event detected */
- uint8_t fsm_lc : 1; /* fsm long counter timeout interrupt event */
+uint8_t fsm_lc :
+ 1; /* fsm long counter timeout interrupt event */
uint8_t fsm1 : 1; /* fsm 1 interrupt event */
uint8_t fsm2 : 1; /* fsm 2 interrupt event */
uint8_t fsm3 : 1; /* fsm 3 interrupt event */
@@ -2730,7 +4097,8 @@ int32_t lsm6dso_pin_int1_route_set(stmdev_ctx_t *ctx,
int32_t lsm6dso_pin_int1_route_get(stmdev_ctx_t *ctx,
lsm6dso_pin_int1_route_t *val);
-typedef struct {
+typedef struct
+{
uint8_t drdy_ois : 1; /* OIS chain data ready */
uint8_t drdy_xl : 1; /* Accelerometer data ready */
uint8_t drdy_g : 1; /* Gyroscope data ready */
@@ -2745,11 +4113,13 @@ typedef struct {
uint8_t free_fall : 1; /* free fall event */
uint8_t wake_up : 1; /* wake up event */
uint8_t single_tap : 1; /* single-tap event */
- uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */
+uint8_t sleep_change :
+ 1; /* Act/Inact (or Vice-versa) status changed */
uint8_t step_detector : 1; /* Step detected */
uint8_t tilt : 1; /* Relative tilt event detected */
uint8_t sig_mot : 1; /* "significant motion" event detected */
- uint8_t fsm_lc : 1; /* fsm long counter timeout interrupt event */
+uint8_t fsm_lc :
+ 1; /* fsm long counter timeout interrupt event */
uint8_t fsm1 : 1; /* fsm 1 interrupt event */
uint8_t fsm2 : 1; /* fsm 2 interrupt event */
uint8_t fsm3 : 1; /* fsm 3 interrupt event */
@@ -2776,17 +4146,22 @@ typedef struct {
uint8_t mlc8 : 1; /* mlc 8 interrupt event */
} lsm6dso_pin_int2_route_t;
-int32_t lsm6dso_pin_int2_route_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
- lsm6dso_pin_int2_route_t val);
-int32_t lsm6dso_pin_int2_route_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
- lsm6dso_pin_int2_route_t *val);
+int32_t lsm6dso_pin_int2_route_set(stmdev_ctx_t *ctx,
+ stmdev_ctx_t *aux_ctx,
+ lsm6dso_pin_int2_route_t val);
+int32_t lsm6dso_pin_int2_route_get(stmdev_ctx_t *ctx,
+ stmdev_ctx_t *aux_ctx,
+ lsm6dso_pin_int2_route_t *val);
-typedef struct {
+typedef struct
+{
uint8_t drdy_xl : 1; /* Accelerometer data ready */
uint8_t drdy_g : 1; /* Gyroscope data ready */
uint8_t drdy_temp : 1; /* Temperature data ready */
- uint8_t den_flag : 1; /* external trigger level recognition (DEN) */
- uint8_t timestamp : 1; /* timestamp overflow (1 = int2 pin disable) */
+uint8_t den_flag :
+ 1; /* external trigger level recognition (DEN) */
+uint8_t timestamp :
+ 1; /* timestamp overflow (1 = int2 pin disable) */
uint8_t free_fall : 1; /* free fall event */
uint8_t wake_up : 1; /* wake up event */
uint8_t wake_up_z : 1; /* wake up on Z axis event */
@@ -2798,19 +4173,30 @@ typedef struct {
uint8_t tap_y : 1; /* single-tap on Y axis event */
uint8_t tap_x : 1; /* single-tap on X axis event */
uint8_t tap_sign : 1; /* sign of tap event (0-pos / 1-neg) */
- uint8_t six_d : 1; /* orientation change (6D/4D detection) */
- uint8_t six_d_xl : 1; /* X-axis low 6D/4D event (under threshold) */
- uint8_t six_d_xh : 1; /* X-axis high 6D/4D event (over threshold) */
- uint8_t six_d_yl : 1; /* Y-axis low 6D/4D event (under threshold) */
- uint8_t six_d_yh : 1; /* Y-axis high 6D/4D event (over threshold) */
- uint8_t six_d_zl : 1; /* Z-axis low 6D/4D event (under threshold) */
- uint8_t six_d_zh : 1; /* Z-axis high 6D/4D event (over threshold) */
- uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */
- uint8_t sleep_state : 1; /* Act/Inact status flag (0-Act / 1-Inact) */
+uint8_t six_d :
+ 1; /* orientation change (6D/4D detection) */
+uint8_t six_d_xl :
+ 1; /* X-axis low 6D/4D event (under threshold) */
+uint8_t six_d_xh :
+ 1; /* X-axis high 6D/4D event (over threshold) */
+uint8_t six_d_yl :
+ 1; /* Y-axis low 6D/4D event (under threshold) */
+uint8_t six_d_yh :
+ 1; /* Y-axis high 6D/4D event (over threshold) */
+uint8_t six_d_zl :
+ 1; /* Z-axis low 6D/4D event (under threshold) */
+uint8_t six_d_zh :
+ 1; /* Z-axis high 6D/4D event (over threshold) */
+uint8_t sleep_change :
+ 1; /* Act/Inact (or Vice-versa) status changed */
+uint8_t sleep_state :
+ 1; /* Act/Inact status flag (0-Act / 1-Inact) */
uint8_t step_detector : 1; /* Step detected */
uint8_t tilt : 1; /* Relative tilt event detected */
- uint8_t sig_mot : 1; /* "significant motion" event detected */
- uint8_t fsm_lc : 1; /* fsm long counter timeout interrupt event */
+uint8_t sig_mot :
+ 1; /* "significant motion" event detected */
+uint8_t fsm_lc :
+ 1; /* fsm long counter timeout interrupt event */
uint8_t fsm1 : 1; /* fsm 1 interrupt event */
uint8_t fsm2 : 1; /* fsm 2 interrupt event */
uint8_t fsm3 : 1; /* fsm 3 interrupt event */
@@ -2836,30 +4222,42 @@ typedef struct {
uint8_t mlc7 : 1; /* mlc 7 interrupt event */
uint8_t mlc8 : 1; /* mlc 8 interrupt event */
uint8_t sh_endop : 1; /* sensor hub end operation */
- uint8_t sh_slave0_nack : 1; /* Not acknowledge on sensor hub slave 0 */
- uint8_t sh_slave1_nack : 1; /* Not acknowledge on sensor hub slave 1 */
- uint8_t sh_slave2_nack : 1; /* Not acknowledge on sensor hub slave 2 */
- uint8_t sh_slave3_nack : 1; /* Not acknowledge on sensor hub slave 3 */
- uint8_t sh_wr_once : 1; /* "WRITE_ONCE" end on sensor hub slave 0 */
- uint16_t fifo_diff : 10; /* Number of unread sensor data in FIFO*/
+uint8_t sh_slave0_nack :
+ 1; /* Not acknowledge on sensor hub slave 0 */
+uint8_t sh_slave1_nack :
+ 1; /* Not acknowledge on sensor hub slave 1 */
+uint8_t sh_slave2_nack :
+ 1; /* Not acknowledge on sensor hub slave 2 */
+uint8_t sh_slave3_nack :
+ 1; /* Not acknowledge on sensor hub slave 3 */
+uint8_t sh_wr_once :
+ 1; /* "WRITE_ONCE" end on sensor hub slave 0 */
+uint16_t fifo_diff :
+ 10; /* Number of unread sensor data in FIFO*/
uint8_t fifo_ovr_latched : 1; /* Latched FIFO overrun status */
- uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */
+uint8_t fifo_bdr :
+ 1; /* FIFO Batch counter threshold reached */
uint8_t fifo_full : 1; /* FIFO full */
uint8_t fifo_ovr : 1; /* FIFO overrun */
uint8_t fifo_th : 1; /* FIFO threshold reached */
} lsm6dso_all_sources_t;
int32_t lsm6dso_all_sources_get(stmdev_ctx_t *ctx,
- lsm6dso_all_sources_t *val);
+ lsm6dso_all_sources_t *val);
-typedef struct{
+typedef struct
+{
uint8_t odr_fine_tune;
} dev_cal_t;
int32_t lsm6dso_calibration_get(stmdev_ctx_t *ctx, dev_cal_t *val);
-typedef struct {
- struct {
- struct {
- enum {
+typedef struct
+{
+ struct
+ {
+ struct
+ {
+ enum
+ {
LSM6DSO_XL_UI_OFF = 0x00, /* in power down */
LSM6DSO_XL_UI_1Hz6_LP = 0x1B, /* @1Hz6 (low power) */
LSM6DSO_XL_UI_1Hz6_ULP = 0x2B, /* @1Hz6 (ultra low/Gy, OIS imu off) */
@@ -2884,15 +4282,18 @@ typedef struct {
LSM6DSO_XL_UI_3333Hz_HP = 0x09, /* @3kHz33 (high performance) */
LSM6DSO_XL_UI_6667Hz_HP = 0x0A, /* @6kHz66 (high performance) */
} odr;
- enum {
+ enum
+ {
LSM6DSO_XL_UI_2g = 0,
LSM6DSO_XL_UI_4g = 2,
LSM6DSO_XL_UI_8g = 3,
LSM6DSO_XL_UI_16g = 1, /* OIS full scale is also forced to be 16g */
} fs;
} xl;
- struct {
- enum {
+ struct
+ {
+ enum
+ {
LSM6DSO_GY_UI_OFF = 0x00, /* gy in power down */
LSM6DSO_GY_UI_12Hz5_LP = 0x11, /* gy @12Hz5 (low power) */
LSM6DSO_GY_UI_12Hz5_HP = 0x01, /* gy @12Hz5 (high performance) */
@@ -2910,38 +4311,47 @@ typedef struct {
LSM6DSO_GY_UI_3333Hz_HP = 0x09, /* gy @3kHz33 (high performance) */
LSM6DSO_GY_UI_6667Hz_HP = 0x0A, /* gy @6kHz66 (high performance) */
} odr;
- enum {
+ enum
+ {
LSM6DSO_GY_UI_250dps = 0,
LSM6DSO_GY_UI_125dps = 1,
LSM6DSO_GY_UI_500dps = 2,
LSM6DSO_GY_UI_1000dps = 4,
LSM6DSO_GY_UI_2000dps = 6,
} fs;
- }gy;
+ } gy;
} ui;
- struct {
- enum {
+ struct
+ {
+ enum
+ {
LSM6DSO_OIS_ONLY_AUX = 0x00, /* Auxiliary SPI full control */
LSM6DSO_OIS_MIXED = 0x01, /* Enabling by UI / read-config by AUX */
} ctrl_md;
- struct {
- enum {
+ struct
+ {
+ enum
+ {
LSM6DSO_XL_OIS_OFF = 0x00, /* in power down */
LSM6DSO_XL_OIS_6667Hz_HP = 0x01, /* @6kHz OIS imu active/NO ULP on UI */
} odr;
- enum {
+ enum
+ {
LSM6DSO_XL_OIS_2g = 0,
LSM6DSO_XL_OIS_4g = 2,
LSM6DSO_XL_OIS_8g = 3,
LSM6DSO_XL_OIS_16g = 1, /* UI full scale is also forced to be 16g */
} fs;
} xl;
- struct {
- enum {
+ struct
+ {
+ enum
+ {
LSM6DSO_GY_OIS_OFF = 0x00, /* in power down */
LSM6DSO_GY_OIS_6667Hz_HP = 0x01, /* @6kHz No Ultra Low Power*/
} odr;
- enum {
+ enum
+ {
LSM6DSO_GY_OIS_250dps = 0,
LSM6DSO_GY_OIS_125dps = 1,
LSM6DSO_GY_OIS_500dps = 2,
@@ -2950,14 +4360,17 @@ typedef struct {
} fs;
} gy;
} ois;
- struct {
- enum {
+ struct
+ {
+ enum
+ {
LSM6DSO_FSM_DISABLE = 0x00,
LSM6DSO_FSM_XL = 0x01,
LSM6DSO_FSM_GY = 0x02,
LSM6DSO_FSM_XL_GY = 0x03,
} sens;
- enum {
+ enum
+ {
LSM6DSO_FSM_12Hz5 = 0x00,
LSM6DSO_FSM_26Hz = 0x01,
LSM6DSO_FSM_52Hz = 0x02,
@@ -2966,37 +4379,60 @@ typedef struct {
} fsm;
} lsm6dso_md_t;
int32_t lsm6dso_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
- lsm6dso_md_t *val);
+ lsm6dso_md_t *val);
int32_t lsm6dso_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
- lsm6dso_md_t *val);
-typedef struct {
- struct {
- struct {
- float mg[3];
+ lsm6dso_md_t *val);
+typedef struct
+{
+ struct
+ {
+ struct
+ {
+ float_t mg[3];
int16_t raw[3];
- }xl;
- struct {
- float mdps[3];
+ } xl;
+ struct
+ {
+ float_t mdps[3];
int16_t raw[3];
- }gy;
- struct {
- float deg_c;
+ } gy;
+ struct
+ {
+ float_t deg_c;
int16_t raw;
- }heat;
+ } heat;
} ui;
- struct {
- struct {
- float mg[3];
+ struct
+ {
+ struct
+ {
+ float_t mg[3];
int16_t raw[3];
- }xl;
- struct {
- float mdps[3];
+ } xl;
+ struct
+ {
+ float_t mdps[3];
int16_t raw[3];
- }gy;
+ } gy;
} ois;
} lsm6dso_data_t;
int32_t lsm6dso_data_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
- lsm6dso_md_t *md, lsm6dso_data_t *data);
+ lsm6dso_md_t *md, lsm6dso_data_t *data);
+
+typedef struct
+{
+ uint8_t sig_mot : 1; /* significant motion */
+ uint8_t tilt : 1; /* tilt detection */
+ uint8_t step : 1; /* step counter/detector */
+ uint8_t step_adv : 1; /* step counter advanced mode */
+ uint8_t fsm : 1; /* finite state machine */
+ uint8_t fifo_compr : 1; /* FIFO compression */
+} lsm6dso_emb_sens_t;
+int32_t lsm6dso_embedded_sens_set(stmdev_ctx_t *ctx,
+ lsm6dso_emb_sens_t *emb_sens);
+int32_t lsm6dso_embedded_sens_get(stmdev_ctx_t *ctx,
+ lsm6dso_emb_sens_t *emb_sens);
+int32_t lsm6dso_embedded_sens_off(stmdev_ctx_t *ctx);
/**
* @}
diff --git a/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.c b/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.c
index c3524c02f2d3e96e419173e933c036557e65d3d4..105707d7e0e0bde79ac713103c873e6657dadf0d 100644
--- a/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.c
+++ b/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file lsm6dsox_reg.c
- * @author Sensors Software Solution Team
- * @brief LSM6DSOX driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lsm6dsox_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LSM6DSOX driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lsm6dsox_reg.h"
@@ -43,14 +43,17 @@
* @param reg first register address to read.
* @param data buffer for data read.(ptr)
* @param len number of consecutive register to read.
- * @retval interface status (MANDATORY: return 0 -> no Error).
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lsm6dsox_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -61,14 +64,17 @@ int32_t lsm6dsox_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @param reg first register address to write.
* @param data the buffer contains data to be written.(ptr)
* @param len number of consecutive register to write.
- * @retval interface status (MANDATORY: return 0 -> no Error).
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lsm6dsox_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -86,7 +92,8 @@ int32_t lsm6dsox_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
static void bytecpy(uint8_t *target, uint8_t *source)
{
- if ( (target != NULL) && (source != NULL) ) {
+ if ((target != NULL) && (source != NULL))
+ {
*target = *source;
}
}
@@ -119,32 +126,32 @@ float_t lsm6dsox_from_fs8_to_mg(int16_t lsb)
float_t lsm6dsox_from_fs16_to_mg(int16_t lsb)
{
- return ((float_t)lsb) *0.488f;
+ return ((float_t)lsb) * 0.488f;
}
float_t lsm6dsox_from_fs125_to_mdps(int16_t lsb)
{
- return ((float_t)lsb) *4.375f;
+ return ((float_t)lsb) * 4.375f;
}
float_t lsm6dsox_from_fs500_to_mdps(int16_t lsb)
{
- return ((float_t)lsb) *17.50f;
+ return ((float_t)lsb) * 17.50f;
}
float_t lsm6dsox_from_fs250_to_mdps(int16_t lsb)
{
- return ((float_t)lsb) *8.750f;
+ return ((float_t)lsb) * 8.750f;
}
float_t lsm6dsox_from_fs1000_to_mdps(int16_t lsb)
{
- return ((float_t)lsb) *35.0f;
+ return ((float_t)lsb) * 35.0f;
}
float_t lsm6dsox_from_fs2000_to_mdps(int16_t lsb)
{
- return ((float_t)lsb) *70.0f;
+ return ((float_t)lsb) * 70.0f;
}
float_t lsm6dsox_from_lsb_to_celsius(int16_t lsb)
@@ -174,19 +181,23 @@ float_t lsm6dsox_from_lsb_to_nsec(int16_t lsb)
*
* @param ctx read / write interface definitions
* @param val change the values of fs_xl in reg CTRL1_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_xl_full_scale_set(stmdev_ctx_t *ctx,
- lsm6dsox_fs_xl_t val)
+ lsm6dsox_fs_xl_t val)
{
lsm6dsox_ctrl1_xl_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.fs_xl = (uint8_t) val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -195,27 +206,35 @@ int32_t lsm6dsox_xl_full_scale_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of fs_xl in reg CTRL1_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_xl_full_scale_get(stmdev_ctx_t *ctx, lsm6dsox_fs_xl_t *val)
+int32_t lsm6dsox_xl_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6dsox_fs_xl_t *val)
{
lsm6dsox_ctrl1_xl_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)®, 1);
- switch (reg.fs_xl) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t *)®, 1);
+
+ switch (reg.fs_xl)
+ {
case LSM6DSOX_2g:
*val = LSM6DSOX_2g;
break;
+
case LSM6DSOX_16g:
*val = LSM6DSOX_16g;
break;
+
case LSM6DSOX_4g:
*val = LSM6DSOX_4g;
break;
+
case LSM6DSOX_8g:
*val = LSM6DSOX_8g;
break;
+
default:
*val = LSM6DSOX_2g;
break;
@@ -229,95 +248,130 @@ int32_t lsm6dsox_xl_full_scale_get(stmdev_ctx_t *ctx, lsm6dsox_fs_xl_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of odr_xl in reg CTRL1_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6dsox_odr_xl_t val)
+int32_t lsm6dsox_xl_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dsox_odr_xl_t val)
{
lsm6dsox_odr_xl_t odr_xl = val;
lsm6dsox_emb_fsm_enable_t fsm_enable;
lsm6dsox_fsm_odr_t fsm_odr;
- uint8_t mlc_enable;
+ lsm6dsox_emb_sens_t emb_sens;
lsm6dsox_mlc_odr_t mlc_odr;
lsm6dsox_ctrl1_xl_t reg;
int32_t ret;
/* Check the Finite State Machine data rate constraints */
ret = lsm6dsox_fsm_enable_get(ctx, &fsm_enable);
- if (ret == 0) {
- if ( (fsm_enable.fsm_enable_a.fsm1_en |
- fsm_enable.fsm_enable_a.fsm2_en |
- fsm_enable.fsm_enable_a.fsm3_en |
- fsm_enable.fsm_enable_a.fsm4_en |
- fsm_enable.fsm_enable_a.fsm5_en |
- fsm_enable.fsm_enable_a.fsm6_en |
- fsm_enable.fsm_enable_a.fsm7_en |
- fsm_enable.fsm_enable_a.fsm8_en |
- fsm_enable.fsm_enable_b.fsm9_en |
- fsm_enable.fsm_enable_b.fsm10_en |
- fsm_enable.fsm_enable_b.fsm11_en |
- fsm_enable.fsm_enable_b.fsm12_en |
- fsm_enable.fsm_enable_b.fsm13_en |
- fsm_enable.fsm_enable_b.fsm14_en |
- fsm_enable.fsm_enable_b.fsm15_en |
- fsm_enable.fsm_enable_b.fsm16_en ) == PROPERTY_ENABLE ){
+ if (ret == 0)
+ {
+ if ((fsm_enable.fsm_enable_a.fsm1_en |
+ fsm_enable.fsm_enable_a.fsm2_en |
+ fsm_enable.fsm_enable_a.fsm3_en |
+ fsm_enable.fsm_enable_a.fsm4_en |
+ fsm_enable.fsm_enable_a.fsm5_en |
+ fsm_enable.fsm_enable_a.fsm6_en |
+ fsm_enable.fsm_enable_a.fsm7_en |
+ fsm_enable.fsm_enable_a.fsm8_en |
+ fsm_enable.fsm_enable_b.fsm9_en |
+ fsm_enable.fsm_enable_b.fsm10_en |
+ fsm_enable.fsm_enable_b.fsm11_en |
+ fsm_enable.fsm_enable_b.fsm12_en |
+ fsm_enable.fsm_enable_b.fsm13_en |
+ fsm_enable.fsm_enable_b.fsm14_en |
+ fsm_enable.fsm_enable_b.fsm15_en |
+ fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
+ {
ret = lsm6dsox_fsm_data_rate_get(ctx, &fsm_odr);
- if (ret == 0) {
- switch (fsm_odr) {
- case LSM6DSOX_ODR_FSM_12Hz5:
- if (val == LSM6DSOX_XL_ODR_OFF){
+ if (ret == 0)
+ {
+ switch (fsm_odr)
+ {
+ case LSM6DSOX_ODR_FSM_12Hz5:
+ if (val == LSM6DSOX_XL_ODR_OFF)
+ {
odr_xl = LSM6DSOX_XL_ODR_12Hz5;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
- case LSM6DSOX_ODR_FSM_26Hz:
- if (val == LSM6DSOX_XL_ODR_OFF){
+ case LSM6DSOX_ODR_FSM_26Hz:
+ if (val == LSM6DSOX_XL_ODR_OFF)
+ {
odr_xl = LSM6DSOX_XL_ODR_26Hz;
+ }
- } else if (val == LSM6DSOX_XL_ODR_12Hz5){
+ else if (val == LSM6DSOX_XL_ODR_12Hz5)
+ {
odr_xl = LSM6DSOX_XL_ODR_26Hz;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
- case LSM6DSOX_ODR_FSM_52Hz:
- if (val == LSM6DSOX_XL_ODR_OFF){
+ case LSM6DSOX_ODR_FSM_52Hz:
+ if (val == LSM6DSOX_XL_ODR_OFF)
+ {
odr_xl = LSM6DSOX_XL_ODR_52Hz;
+ }
- } else if (val == LSM6DSOX_XL_ODR_12Hz5){
+ else if (val == LSM6DSOX_XL_ODR_12Hz5)
+ {
odr_xl = LSM6DSOX_XL_ODR_52Hz;
+ }
- } else if (val == LSM6DSOX_XL_ODR_26Hz){
+ else if (val == LSM6DSOX_XL_ODR_26Hz)
+ {
odr_xl = LSM6DSOX_XL_ODR_52Hz;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
- case LSM6DSOX_ODR_FSM_104Hz:
- if (val == LSM6DSOX_XL_ODR_OFF){
+ case LSM6DSOX_ODR_FSM_104Hz:
+ if (val == LSM6DSOX_XL_ODR_OFF)
+ {
odr_xl = LSM6DSOX_XL_ODR_104Hz;
+ }
- } else if (val == LSM6DSOX_XL_ODR_12Hz5){
+ else if (val == LSM6DSOX_XL_ODR_12Hz5)
+ {
odr_xl = LSM6DSOX_XL_ODR_104Hz;
+ }
- } else if (val == LSM6DSOX_XL_ODR_26Hz){
+ else if (val == LSM6DSOX_XL_ODR_26Hz)
+ {
odr_xl = LSM6DSOX_XL_ODR_104Hz;
+ }
- } else if (val == LSM6DSOX_XL_ODR_52Hz){
+ else if (val == LSM6DSOX_XL_ODR_52Hz)
+ {
odr_xl = LSM6DSOX_XL_ODR_104Hz;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
+
default:
odr_xl = val;
break;
@@ -327,66 +381,102 @@ int32_t lsm6dsox_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6dsox_odr_xl_t val)
}
/* Check the Machine Learning Core data rate constraints */
- mlc_enable = PROPERTY_DISABLE;
- if (ret == 0) {
- ret = lsm6dsox_mlc_get(ctx, &mlc_enable);
- if ( mlc_enable == PROPERTY_ENABLE ){
+ emb_sens.mlc = PROPERTY_DISABLE;
+ if (ret == 0)
+ {
+ lsm6dsox_embedded_sens_get(ctx, &emb_sens);
+
+ if (emb_sens.mlc == PROPERTY_ENABLE)
+ {
ret = lsm6dsox_mlc_data_rate_get(ctx, &mlc_odr);
- if (ret == 0) {
- switch (mlc_odr) {
- case LSM6DSOX_ODR_PRGS_12Hz5:
- if (val == LSM6DSOX_XL_ODR_OFF){
+ if (ret == 0)
+ {
+ switch (mlc_odr)
+ {
+ case LSM6DSOX_ODR_PRGS_12Hz5:
+ if (val == LSM6DSOX_XL_ODR_OFF)
+ {
odr_xl = LSM6DSOX_XL_ODR_12Hz5;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
+
case LSM6DSOX_ODR_PRGS_26Hz:
- if (val == LSM6DSOX_XL_ODR_OFF){
+ if (val == LSM6DSOX_XL_ODR_OFF)
+ {
odr_xl = LSM6DSOX_XL_ODR_26Hz;
+ }
- } else if (val == LSM6DSOX_XL_ODR_12Hz5){
+ else if (val == LSM6DSOX_XL_ODR_12Hz5)
+ {
odr_xl = LSM6DSOX_XL_ODR_26Hz;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
- case LSM6DSOX_ODR_PRGS_52Hz:
- if (val == LSM6DSOX_XL_ODR_OFF){
+ case LSM6DSOX_ODR_PRGS_52Hz:
+ if (val == LSM6DSOX_XL_ODR_OFF)
+ {
odr_xl = LSM6DSOX_XL_ODR_52Hz;
+ }
- } else if (val == LSM6DSOX_XL_ODR_12Hz5){
+ else if (val == LSM6DSOX_XL_ODR_12Hz5)
+ {
odr_xl = LSM6DSOX_XL_ODR_52Hz;
+ }
- } else if (val == LSM6DSOX_XL_ODR_26Hz){
+ else if (val == LSM6DSOX_XL_ODR_26Hz)
+ {
odr_xl = LSM6DSOX_XL_ODR_52Hz;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
+
case LSM6DSOX_ODR_PRGS_104Hz:
- if (val == LSM6DSOX_XL_ODR_OFF){
+ if (val == LSM6DSOX_XL_ODR_OFF)
+ {
odr_xl = LSM6DSOX_XL_ODR_104Hz;
+ }
- } else if (val == LSM6DSOX_XL_ODR_12Hz5){
+ else if (val == LSM6DSOX_XL_ODR_12Hz5)
+ {
odr_xl = LSM6DSOX_XL_ODR_104Hz;
+ }
- } else if (val == LSM6DSOX_XL_ODR_26Hz){
+ else if (val == LSM6DSOX_XL_ODR_26Hz)
+ {
odr_xl = LSM6DSOX_XL_ODR_104Hz;
+ }
- } else if (val == LSM6DSOX_XL_ODR_52Hz){
+ else if (val == LSM6DSOX_XL_ODR_52Hz)
+ {
odr_xl = LSM6DSOX_XL_ODR_104Hz;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
+
default:
odr_xl = val;
break;
@@ -394,13 +484,18 @@ int32_t lsm6dsox_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6dsox_odr_xl_t val)
}
}
}
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.odr_xl = (uint8_t) odr_xl;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -409,56 +504,72 @@ int32_t lsm6dsox_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6dsox_odr_xl_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of odr_xl in reg CTRL1_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_xl_data_rate_get(stmdev_ctx_t *ctx, lsm6dsox_odr_xl_t *val)
+int32_t lsm6dsox_xl_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dsox_odr_xl_t *val)
{
lsm6dsox_ctrl1_xl_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t *)®, 1);
- switch (reg.odr_xl) {
+ switch (reg.odr_xl)
+ {
case LSM6DSOX_XL_ODR_OFF:
*val = LSM6DSOX_XL_ODR_OFF;
break;
+
case LSM6DSOX_XL_ODR_12Hz5:
*val = LSM6DSOX_XL_ODR_12Hz5;
break;
+
case LSM6DSOX_XL_ODR_26Hz:
*val = LSM6DSOX_XL_ODR_26Hz;
break;
+
case LSM6DSOX_XL_ODR_52Hz:
*val = LSM6DSOX_XL_ODR_52Hz;
break;
+
case LSM6DSOX_XL_ODR_104Hz:
*val = LSM6DSOX_XL_ODR_104Hz;
break;
+
case LSM6DSOX_XL_ODR_208Hz:
*val = LSM6DSOX_XL_ODR_208Hz;
break;
+
case LSM6DSOX_XL_ODR_417Hz:
*val = LSM6DSOX_XL_ODR_417Hz;
break;
+
case LSM6DSOX_XL_ODR_833Hz:
*val = LSM6DSOX_XL_ODR_833Hz;
break;
+
case LSM6DSOX_XL_ODR_1667Hz:
*val = LSM6DSOX_XL_ODR_1667Hz;
break;
+
case LSM6DSOX_XL_ODR_3333Hz:
*val = LSM6DSOX_XL_ODR_3333Hz;
break;
+
case LSM6DSOX_XL_ODR_6667Hz:
*val = LSM6DSOX_XL_ODR_6667Hz;
break;
+
case LSM6DSOX_XL_ODR_1Hz6:
*val = LSM6DSOX_XL_ODR_1Hz6;
break;
+
default:
*val = LSM6DSOX_XL_ODR_OFF;
break;
}
+
return ret;
}
@@ -467,17 +578,21 @@ int32_t lsm6dsox_xl_data_rate_get(stmdev_ctx_t *ctx, lsm6dsox_odr_xl_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of fs_g in reg CTRL2_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_gy_full_scale_set(stmdev_ctx_t *ctx, lsm6dsox_fs_g_t val)
+int32_t lsm6dsox_gy_full_scale_set(stmdev_ctx_t *ctx,
+ lsm6dsox_fs_g_t val)
{
lsm6dsox_ctrl2_g_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.fs_g = (uint8_t) val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t *)®, 1);
}
return ret;
@@ -488,30 +603,39 @@ int32_t lsm6dsox_gy_full_scale_set(stmdev_ctx_t *ctx, lsm6dsox_fs_g_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of fs_g in reg CTRL2_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_gy_full_scale_get(stmdev_ctx_t *ctx, lsm6dsox_fs_g_t *val)
+int32_t lsm6dsox_gy_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6dsox_fs_g_t *val)
{
lsm6dsox_ctrl2_g_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t*)®, 1);
- switch (reg.fs_g) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t *)®, 1);
+
+ switch (reg.fs_g)
+ {
case LSM6DSOX_250dps:
*val = LSM6DSOX_250dps;
break;
+
case LSM6DSOX_125dps:
*val = LSM6DSOX_125dps;
break;
+
case LSM6DSOX_500dps:
*val = LSM6DSOX_500dps;
break;
+
case LSM6DSOX_1000dps:
*val = LSM6DSOX_1000dps;
break;
+
case LSM6DSOX_2000dps:
*val = LSM6DSOX_2000dps;
break;
+
default:
*val = LSM6DSOX_250dps;
break;
@@ -525,95 +649,130 @@ int32_t lsm6dsox_gy_full_scale_get(stmdev_ctx_t *ctx, lsm6dsox_fs_g_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of odr_g in reg CTRL2_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_gy_data_rate_set(stmdev_ctx_t *ctx, lsm6dsox_odr_g_t val)
+int32_t lsm6dsox_gy_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dsox_odr_g_t val)
{
lsm6dsox_odr_g_t odr_gy = val;
lsm6dsox_emb_fsm_enable_t fsm_enable;
lsm6dsox_fsm_odr_t fsm_odr;
- uint8_t mlc_enable;
+ lsm6dsox_emb_sens_t emb_sens;
lsm6dsox_mlc_odr_t mlc_odr;
lsm6dsox_ctrl2_g_t reg;
int32_t ret;
/* Check the Finite State Machine data rate constraints */
ret = lsm6dsox_fsm_enable_get(ctx, &fsm_enable);
- if (ret == 0) {
- if ( (fsm_enable.fsm_enable_a.fsm1_en |
- fsm_enable.fsm_enable_a.fsm2_en |
- fsm_enable.fsm_enable_a.fsm3_en |
- fsm_enable.fsm_enable_a.fsm4_en |
- fsm_enable.fsm_enable_a.fsm5_en |
- fsm_enable.fsm_enable_a.fsm6_en |
- fsm_enable.fsm_enable_a.fsm7_en |
- fsm_enable.fsm_enable_a.fsm8_en |
- fsm_enable.fsm_enable_b.fsm9_en |
- fsm_enable.fsm_enable_b.fsm10_en |
- fsm_enable.fsm_enable_b.fsm11_en |
- fsm_enable.fsm_enable_b.fsm12_en |
- fsm_enable.fsm_enable_b.fsm13_en |
- fsm_enable.fsm_enable_b.fsm14_en |
- fsm_enable.fsm_enable_b.fsm15_en |
- fsm_enable.fsm_enable_b.fsm16_en ) == PROPERTY_ENABLE ){
+ if (ret == 0)
+ {
+ if ((fsm_enable.fsm_enable_a.fsm1_en |
+ fsm_enable.fsm_enable_a.fsm2_en |
+ fsm_enable.fsm_enable_a.fsm3_en |
+ fsm_enable.fsm_enable_a.fsm4_en |
+ fsm_enable.fsm_enable_a.fsm5_en |
+ fsm_enable.fsm_enable_a.fsm6_en |
+ fsm_enable.fsm_enable_a.fsm7_en |
+ fsm_enable.fsm_enable_a.fsm8_en |
+ fsm_enable.fsm_enable_b.fsm9_en |
+ fsm_enable.fsm_enable_b.fsm10_en |
+ fsm_enable.fsm_enable_b.fsm11_en |
+ fsm_enable.fsm_enable_b.fsm12_en |
+ fsm_enable.fsm_enable_b.fsm13_en |
+ fsm_enable.fsm_enable_b.fsm14_en |
+ fsm_enable.fsm_enable_b.fsm15_en |
+ fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
+ {
ret = lsm6dsox_fsm_data_rate_get(ctx, &fsm_odr);
- if (ret == 0) {
- switch (fsm_odr) {
- case LSM6DSOX_ODR_FSM_12Hz5:
- if (val == LSM6DSOX_GY_ODR_OFF){
+ if (ret == 0)
+ {
+ switch (fsm_odr)
+ {
+ case LSM6DSOX_ODR_FSM_12Hz5:
+ if (val == LSM6DSOX_GY_ODR_OFF)
+ {
odr_gy = LSM6DSOX_GY_ODR_12Hz5;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
- case LSM6DSOX_ODR_FSM_26Hz:
- if (val == LSM6DSOX_GY_ODR_OFF){
+ case LSM6DSOX_ODR_FSM_26Hz:
+ if (val == LSM6DSOX_GY_ODR_OFF)
+ {
odr_gy = LSM6DSOX_GY_ODR_26Hz;
+ }
- } else if (val == LSM6DSOX_GY_ODR_12Hz5){
+ else if (val == LSM6DSOX_GY_ODR_12Hz5)
+ {
odr_gy = LSM6DSOX_GY_ODR_26Hz;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
- case LSM6DSOX_ODR_FSM_52Hz:
- if (val == LSM6DSOX_GY_ODR_OFF){
+ case LSM6DSOX_ODR_FSM_52Hz:
+ if (val == LSM6DSOX_GY_ODR_OFF)
+ {
odr_gy = LSM6DSOX_GY_ODR_52Hz;
+ }
- } else if (val == LSM6DSOX_GY_ODR_12Hz5){
+ else if (val == LSM6DSOX_GY_ODR_12Hz5)
+ {
odr_gy = LSM6DSOX_GY_ODR_52Hz;
+ }
- } else if (val == LSM6DSOX_GY_ODR_26Hz){
+ else if (val == LSM6DSOX_GY_ODR_26Hz)
+ {
odr_gy = LSM6DSOX_GY_ODR_52Hz;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
- case LSM6DSOX_ODR_FSM_104Hz:
- if (val == LSM6DSOX_GY_ODR_OFF){
+ case LSM6DSOX_ODR_FSM_104Hz:
+ if (val == LSM6DSOX_GY_ODR_OFF)
+ {
odr_gy = LSM6DSOX_GY_ODR_104Hz;
+ }
- } else if (val == LSM6DSOX_GY_ODR_12Hz5){
+ else if (val == LSM6DSOX_GY_ODR_12Hz5)
+ {
odr_gy = LSM6DSOX_GY_ODR_104Hz;
+ }
- } else if (val == LSM6DSOX_GY_ODR_26Hz){
+ else if (val == LSM6DSOX_GY_ODR_26Hz)
+ {
odr_gy = LSM6DSOX_GY_ODR_104Hz;
+ }
- } else if (val == LSM6DSOX_GY_ODR_52Hz){
+ else if (val == LSM6DSOX_GY_ODR_52Hz)
+ {
odr_gy = LSM6DSOX_GY_ODR_104Hz;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
+
default:
odr_gy = val;
break;
@@ -623,68 +782,102 @@ int32_t lsm6dsox_gy_data_rate_set(stmdev_ctx_t *ctx, lsm6dsox_odr_g_t val)
}
/* Check the Machine Learning Core data rate constraints */
- mlc_enable = PROPERTY_DISABLE;
- if (ret == 0) {
- ret = lsm6dsox_mlc_get(ctx, &mlc_enable);
- if ( mlc_enable == PROPERTY_ENABLE ){
+ emb_sens.mlc = PROPERTY_DISABLE;
+ if (ret == 0)
+ {
+ ret = lsm6dsox_embedded_sens_get(ctx, &emb_sens);
+
+ if (emb_sens.mlc == PROPERTY_ENABLE)
+ {
ret = lsm6dsox_mlc_data_rate_get(ctx, &mlc_odr);
- if (ret == 0) {
- switch (mlc_odr) {
- case LSM6DSOX_ODR_PRGS_12Hz5:
- if (val == LSM6DSOX_GY_ODR_OFF){
+ if (ret == 0)
+ {
+ switch (mlc_odr)
+ {
+ case LSM6DSOX_ODR_PRGS_12Hz5:
+ if (val == LSM6DSOX_GY_ODR_OFF)
+ {
odr_gy = LSM6DSOX_GY_ODR_12Hz5;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
- case LSM6DSOX_ODR_PRGS_26Hz:
- if (val == LSM6DSOX_GY_ODR_OFF){
+ case LSM6DSOX_ODR_PRGS_26Hz:
+ if (val == LSM6DSOX_GY_ODR_OFF)
+ {
odr_gy = LSM6DSOX_GY_ODR_26Hz;
+ }
- } else if (val == LSM6DSOX_GY_ODR_12Hz5){
+ else if (val == LSM6DSOX_GY_ODR_12Hz5)
+ {
odr_gy = LSM6DSOX_GY_ODR_26Hz;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
- case LSM6DSOX_ODR_PRGS_52Hz:
- if (val == LSM6DSOX_GY_ODR_OFF){
+ case LSM6DSOX_ODR_PRGS_52Hz:
+ if (val == LSM6DSOX_GY_ODR_OFF)
+ {
odr_gy = LSM6DSOX_GY_ODR_52Hz;
+ }
- } else if (val == LSM6DSOX_GY_ODR_12Hz5){
+ else if (val == LSM6DSOX_GY_ODR_12Hz5)
+ {
odr_gy = LSM6DSOX_GY_ODR_52Hz;
+ }
- } else if (val == LSM6DSOX_GY_ODR_26Hz){
+ else if (val == LSM6DSOX_GY_ODR_26Hz)
+ {
odr_gy = LSM6DSOX_GY_ODR_52Hz;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
- case LSM6DSOX_ODR_PRGS_104Hz:
- if (val == LSM6DSOX_GY_ODR_OFF){
+ case LSM6DSOX_ODR_PRGS_104Hz:
+ if (val == LSM6DSOX_GY_ODR_OFF)
+ {
odr_gy = LSM6DSOX_GY_ODR_104Hz;
+ }
- } else if (val == LSM6DSOX_GY_ODR_12Hz5){
+ else if (val == LSM6DSOX_GY_ODR_12Hz5)
+ {
odr_gy = LSM6DSOX_GY_ODR_104Hz;
+ }
- } else if (val == LSM6DSOX_GY_ODR_26Hz){
+ else if (val == LSM6DSOX_GY_ODR_26Hz)
+ {
odr_gy = LSM6DSOX_GY_ODR_104Hz;
+ }
- } else if (val == LSM6DSOX_GY_ODR_52Hz){
+ else if (val == LSM6DSOX_GY_ODR_52Hz)
+ {
odr_gy = LSM6DSOX_GY_ODR_104Hz;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
+
default:
odr_gy = val;
break;
@@ -692,12 +885,16 @@ int32_t lsm6dsox_gy_data_rate_set(stmdev_ctx_t *ctx, lsm6dsox_odr_g_t val)
}
}
}
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.odr_g = (uint8_t) odr_gy;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t *)®, 1);
}
return ret;
@@ -708,52 +905,68 @@ int32_t lsm6dsox_gy_data_rate_set(stmdev_ctx_t *ctx, lsm6dsox_odr_g_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of odr_g in reg CTRL2_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_gy_data_rate_get(stmdev_ctx_t *ctx, lsm6dsox_odr_g_t *val)
+int32_t lsm6dsox_gy_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dsox_odr_g_t *val)
{
lsm6dsox_ctrl2_g_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t*)®, 1);
- switch (reg.odr_g) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t *)®, 1);
+
+ switch (reg.odr_g)
+ {
case LSM6DSOX_GY_ODR_OFF:
*val = LSM6DSOX_GY_ODR_OFF;
break;
+
case LSM6DSOX_GY_ODR_12Hz5:
*val = LSM6DSOX_GY_ODR_12Hz5;
break;
+
case LSM6DSOX_GY_ODR_26Hz:
*val = LSM6DSOX_GY_ODR_26Hz;
break;
+
case LSM6DSOX_GY_ODR_52Hz:
*val = LSM6DSOX_GY_ODR_52Hz;
break;
+
case LSM6DSOX_GY_ODR_104Hz:
*val = LSM6DSOX_GY_ODR_104Hz;
break;
+
case LSM6DSOX_GY_ODR_208Hz:
*val = LSM6DSOX_GY_ODR_208Hz;
break;
+
case LSM6DSOX_GY_ODR_417Hz:
*val = LSM6DSOX_GY_ODR_417Hz;
break;
+
case LSM6DSOX_GY_ODR_833Hz:
*val = LSM6DSOX_GY_ODR_833Hz;
break;
+
case LSM6DSOX_GY_ODR_1667Hz:
*val = LSM6DSOX_GY_ODR_1667Hz;
break;
+
case LSM6DSOX_GY_ODR_3333Hz:
*val = LSM6DSOX_GY_ODR_3333Hz;
break;
+
case LSM6DSOX_GY_ODR_6667Hz:
*val = LSM6DSOX_GY_ODR_6667Hz;
break;
+
default:
*val = LSM6DSOX_GY_ODR_OFF;
break;
}
+
return ret;
}
@@ -762,6 +975,7 @@ int32_t lsm6dsox_gy_data_rate_get(stmdev_ctx_t *ctx, lsm6dsox_odr_g_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of bdu in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -769,11 +983,14 @@ int32_t lsm6dsox_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.bdu = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -782,14 +999,16 @@ int32_t lsm6dsox_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of bdu in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsox_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsox_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
*val = reg.bdu;
return ret;
@@ -801,19 +1020,23 @@ int32_t lsm6dsox_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of usr_off_w in reg CTRL6_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_xl_offset_weight_set(stmdev_ctx_t *ctx,
- lsm6dsox_usr_off_w_t val)
+ lsm6dsox_usr_off_w_t val)
{
lsm6dsox_ctrl6_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.usr_off_w = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -823,27 +1046,32 @@ int32_t lsm6dsox_xl_offset_weight_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of usr_off_w in reg CTRL6_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_xl_offset_weight_get(stmdev_ctx_t *ctx,
- lsm6dsox_usr_off_w_t *val)
+ lsm6dsox_usr_off_w_t *val)
{
lsm6dsox_ctrl6_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t *)®, 1);
- switch (reg.usr_off_w) {
+ switch (reg.usr_off_w)
+ {
case LSM6DSOX_LSb_1mg:
*val = LSM6DSOX_LSb_1mg;
break;
+
case LSM6DSOX_LSb_16mg:
*val = LSM6DSOX_LSb_16mg;
break;
+
default:
*val = LSM6DSOX_LSb_1mg;
break;
}
+
return ret;
}
@@ -853,27 +1081,35 @@ int32_t lsm6dsox_xl_offset_weight_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of xl_hm_mode in
* reg CTRL6_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_xl_power_mode_set(stmdev_ctx_t *ctx,
- lsm6dsox_xl_hm_mode_t val)
+ lsm6dsox_xl_hm_mode_t val)
{
lsm6dsox_ctrl5_c_t ctrl5_c;
lsm6dsox_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*) &ctrl5_c, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *) &ctrl5_c, 1);
+
+ if (ret == 0)
+ {
ctrl5_c.xl_ulp_en = ((uint8_t)val & 0x02U) >> 1;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*) &ctrl5_c, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *) &ctrl5_c, 1);
}
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*) &ctrl6_c, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t *) &ctrl6_c, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*) &ctrl6_c, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t *) &ctrl6_c, 1);
}
+
return ret;
}
@@ -882,33 +1118,42 @@ int32_t lsm6dsox_xl_power_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of xl_hm_mode in reg CTRL6_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_xl_power_mode_get(stmdev_ctx_t *ctx,
- lsm6dsox_xl_hm_mode_t *val)
+ lsm6dsox_xl_hm_mode_t *val)
{
lsm6dsox_ctrl5_c_t ctrl5_c;
lsm6dsox_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*) &ctrl5_c, 1);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*) &ctrl6_c, 1);
- switch ( (ctrl5_c.xl_ulp_en << 1) | ctrl6_c.xl_hm_mode) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *) &ctrl5_c, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t *) &ctrl6_c, 1);
+
+ switch ((ctrl5_c.xl_ulp_en << 1) | ctrl6_c.xl_hm_mode)
+ {
case LSM6DSOX_HIGH_PERFORMANCE_MD:
*val = LSM6DSOX_HIGH_PERFORMANCE_MD;
break;
+
case LSM6DSOX_LOW_NORMAL_POWER_MD:
*val = LSM6DSOX_LOW_NORMAL_POWER_MD;
break;
+
case LSM6DSOX_ULTRA_LOW_POWER_MD:
*val = LSM6DSOX_ULTRA_LOW_POWER_MD;
break;
+
default:
*val = LSM6DSOX_HIGH_PERFORMANCE_MD;
break;
}
}
+
return ret;
}
@@ -917,19 +1162,23 @@ int32_t lsm6dsox_xl_power_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of g_hm_mode in reg CTRL7_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_gy_power_mode_set(stmdev_ctx_t *ctx,
- lsm6dsox_g_hm_mode_t val)
+ lsm6dsox_g_hm_mode_t val)
{
lsm6dsox_ctrl7_g_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.g_hm_mode = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -938,26 +1187,32 @@ int32_t lsm6dsox_gy_power_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of g_hm_mode in reg CTRL7_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_gy_power_mode_get(stmdev_ctx_t *ctx,
- lsm6dsox_g_hm_mode_t *val)
+ lsm6dsox_g_hm_mode_t *val)
{
lsm6dsox_ctrl7_g_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1);
- switch (reg.g_hm_mode) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t *)®, 1);
+
+ switch (reg.g_hm_mode)
+ {
case LSM6DSOX_GY_HIGH_PERFORMANCE:
*val = LSM6DSOX_GY_HIGH_PERFORMANCE;
break;
+
case LSM6DSOX_GY_NORMAL:
*val = LSM6DSOX_GY_NORMAL;
break;
+
default:
*val = LSM6DSOX_GY_HIGH_PERFORMANCE;
break;
}
+
return ret;
}
@@ -966,12 +1221,16 @@ int32_t lsm6dsox_gy_power_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val register STATUS_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_status_reg_get(stmdev_ctx_t *ctx, lsm6dsox_status_reg_t *val)
+int32_t lsm6dsox_status_reg_get(stmdev_ctx_t *ctx,
+ lsm6dsox_status_reg_t *val)
{
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t*) val, 1);
+
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t *) val, 1);
+
return ret;
}
@@ -980,14 +1239,16 @@ int32_t lsm6dsox_status_reg_get(stmdev_ctx_t *ctx, lsm6dsox_status_reg_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of xlda in reg STATUS_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsox_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsox_status_reg_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t *)®, 1);
*val = reg.xlda;
return ret;
@@ -998,14 +1259,16 @@ int32_t lsm6dsox_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of gda in reg STATUS_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsox_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsox_status_reg_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t *)®, 1);
*val = reg.gda;
return ret;
@@ -1016,14 +1279,16 @@ int32_t lsm6dsox_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of tda in reg STATUS_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsox_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsox_status_reg_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t *)®, 1);
*val = reg.tda;
return ret;
@@ -1036,12 +1301,15 @@ int32_t lsm6dsox_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_X_OFS_USR, buff, 1);
+
return ret;
}
@@ -1052,12 +1320,15 @@ int32_t lsm6dsox_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_X_OFS_USR, buff, 1);
+
return ret;
}
@@ -1068,12 +1339,15 @@ int32_t lsm6dsox_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_Y_OFS_USR, buff, 1);
+
return ret;
}
@@ -1084,12 +1358,15 @@ int32_t lsm6dsox_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_Y_OFS_USR, buff, 1);
+
return ret;
}
@@ -1100,12 +1377,15 @@ int32_t lsm6dsox_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_Z_OFS_USR, buff, 1);
+
return ret;
}
@@ -1116,12 +1396,15 @@ int32_t lsm6dsox_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_Z_OFS_USR, buff, 1);
+
return ret;
}
@@ -1130,6 +1413,7 @@ int32_t lsm6dsox_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param val change the values of usr_off_on_out in reg CTRL7_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1137,11 +1421,14 @@ int32_t lsm6dsox_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_ctrl7_g_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.usr_off_on_out = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1150,6 +1437,7 @@ int32_t lsm6dsox_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val values of usr_off_on_out in reg CTRL7_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1157,7 +1445,7 @@ int32_t lsm6dsox_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_ctrl7_g_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t *)®, 1);
*val = reg.usr_off_on_out;
return ret;
@@ -1180,13 +1468,12 @@ int32_t lsm6dsox_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val)
* @brief Reset timestamp counter.[set]
*
* @param ctx Read / write interface definitions.(ptr)
- * @retval Interface status (MANDATORY: return 0 -> no Error).
+ * @retval Interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_timestamp_rst(stmdev_ctx_t *ctx)
{
uint8_t rst_val = 0xAA;
-
return lsm6dsox_write_reg(ctx, LSM6DSOX_TIMESTAMP2, &rst_val, 1);
}
@@ -1195,6 +1482,7 @@ int32_t lsm6dsox_timestamp_rst(stmdev_ctx_t *ctx)
*
* @param ctx read / write interface definitions
* @param val change the values of timestamp_en in reg CTRL10_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1202,11 +1490,14 @@ int32_t lsm6dsox_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_ctrl10_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL10_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL10_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.timestamp_en = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL10_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL10_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1215,6 +1506,7 @@ int32_t lsm6dsox_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of timestamp_en in reg CTRL10_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1222,7 +1514,7 @@ int32_t lsm6dsox_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_ctrl10_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL10_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL10_C, (uint8_t *)®, 1);
*val = reg.timestamp_en;
return ret;
@@ -1235,12 +1527,20 @@ int32_t lsm6dsox_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_timestamp_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsox_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val)
{
+ uint8_t buff[4];
int32_t ret;
+
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TIMESTAMP0, buff, 4);
+ *val = buff[3];
+ *val = (*val * 256U) + buff[2];
+ *val = (*val * 256U) + buff[1];
+ *val = (*val * 256U) + buff[0];
+
return ret;
}
@@ -1262,19 +1562,23 @@ int32_t lsm6dsox_timestamp_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param val change the values of rounding in reg CTRL5_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_rounding_mode_set(stmdev_ctx_t *ctx,
- lsm6dsox_rounding_t val)
+ lsm6dsox_rounding_t val)
{
lsm6dsox_ctrl5_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.rounding = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1283,32 +1587,40 @@ int32_t lsm6dsox_rounding_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of rounding in reg CTRL5_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_rounding_mode_get(stmdev_ctx_t *ctx,
- lsm6dsox_rounding_t *val)
+ lsm6dsox_rounding_t *val)
{
lsm6dsox_ctrl5_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1);
- switch (reg.rounding) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)®, 1);
+
+ switch (reg.rounding)
+ {
case LSM6DSOX_NO_ROUND:
*val = LSM6DSOX_NO_ROUND;
break;
+
case LSM6DSOX_ROUND_XL:
*val = LSM6DSOX_ROUND_XL;
break;
+
case LSM6DSOX_ROUND_GY:
*val = LSM6DSOX_ROUND_GY;
break;
+
case LSM6DSOX_ROUND_GY_XL:
*val = LSM6DSOX_ROUND_GY_XL;
break;
+
default:
*val = LSM6DSOX_NO_ROUND;
break;
}
+
return ret;
}
@@ -1327,18 +1639,21 @@ int32_t lsm6dsox_rounding_mode_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param lsm6dsox_rounding_status_t: change the values of rounding_status
* in reg CTRL7_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_rounding_on_status_set(stmdev_ctx_t *ctx,
- lsm6dsox_rounding_status_t val)
+ lsm6dsox_rounding_status_t val)
{
lsm6dsox_ctrl5_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.rounding_status = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)®, 1);
}
return ret;
@@ -1359,26 +1674,32 @@ int32_t lsm6dsox_rounding_on_status_set(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param lsm6dsox_rounding_status_t: Get the values of rounding_status
* in reg CTRL7_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_rounding_on_status_get(stmdev_ctx_t *ctx,
- lsm6dsox_rounding_status_t *val)
+ lsm6dsox_rounding_status_t *val)
{
lsm6dsox_ctrl5_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1);
- switch (reg.rounding_status) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)®, 1);
+
+ switch (reg.rounding_status)
+ {
case LSM6DSOX_STAT_RND_DISABLE:
*val = LSM6DSOX_STAT_RND_DISABLE;
break;
+
case LSM6DSOX_STAT_RND_ENABLE:
*val = LSM6DSOX_STAT_RND_ENABLE;
break;
+
default:
*val = LSM6DSOX_STAT_RND_DISABLE;
break;
}
+
return ret;
}
@@ -1389,12 +1710,18 @@ int32_t lsm6dsox_rounding_on_status_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsox_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
+
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_OUT_TEMP_L, buff, 2);
+ *val = (int16_t)buff[1];
+ *val = (*val * 256) + (int16_t)buff[0];
+
return ret;
}
@@ -1404,12 +1731,22 @@ int32_t lsm6dsox_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsox_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_OUTX_L_G, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -1419,12 +1756,22 @@ int32_t lsm6dsox_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsox_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_OUTX_L_A, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -1433,12 +1780,15 @@ int32_t lsm6dsox_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_DATA_OUT_X_L, buff, 6);
+
return ret;
}
@@ -1449,11 +1799,24 @@ int32_t lsm6dsox_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param uint8_t * : buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_ois_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsox_ois_angular_rate_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
{
- return lsm6dsox_read_reg(ctx, LSM6DSOX_UI_OUTX_L_G_OIS, buff, 6);
+ uint8_t buff[6];
+ int32_t ret;
+
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_OUTX_L_G_OIS, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
+ return ret;
}
/**
@@ -1463,11 +1826,24 @@ int32_t lsm6dsox_ois_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param uint8_t * : buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_ois_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsox_ois_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
{
- return lsm6dsox_read_reg(ctx, LSM6DSOX_UI_OUTX_L_A_OIS, buff, 6);
+ uint8_t buff[6];
+ int32_t ret;
+
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_OUTX_L_A_OIS, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
+ return ret;
}
/**
@@ -1478,11 +1854,20 @@ int32_t lsm6dsox_ois_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param uint8_t * : buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_aux_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsox_aux_temperature_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
{
- return lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_OUT_TEMP_L, buff, 2);
+ uint8_t buff[2];
+ int32_t ret;
+
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_OUT_TEMP_L, buff, 2);
+ *val = (int16_t)buff[1];
+ *val = (*val * 256) + (int16_t)buff[0];
+
+ return ret;
}
/**
@@ -1493,11 +1878,24 @@ int32_t lsm6dsox_aux_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param uint8_t * : buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_aux_ois_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsox_aux_ois_angular_rate_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
{
- return lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_OUTX_L_G_OIS, buff, 6);
+ uint8_t buff[6];
+ int32_t ret;
+
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_OUTX_L_G_OIS, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
+ return ret;
}
/**
@@ -1508,11 +1906,24 @@ int32_t lsm6dsox_aux_ois_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param uint8_t * : buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_aux_ois_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsox_aux_ois_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val)
{
- return lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_OUTX_L_A_OIS, buff, 6);
+ uint8_t buff[6];
+ int32_t ret;
+
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_OUTX_L_A_OIS, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
+ return ret;
}
/**
@@ -1520,19 +1931,28 @@ int32_t lsm6dsox_aux_ois_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_number_of_steps_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsox_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STEP_COUNTER_L, buff, 2);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
+
return ret;
}
@@ -1540,6 +1960,7 @@ int32_t lsm6dsox_number_of_steps_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @brief Reset step counter register.[get]
*
* @param ctx read / write interface definitions
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_steps_reset(stmdev_ctx_t *ctx)
@@ -1548,16 +1969,23 @@ int32_t lsm6dsox_steps_reset(stmdev_ctx_t *ctx)
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_SRC, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_SRC, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.pedo_rst_step = PROPERTY_ENABLE;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_SRC, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_SRC, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
+
return ret;
}
@@ -1566,18 +1994,25 @@ int32_t lsm6dsox_steps_reset(stmdev_ctx_t *ctx)
*
* @param ctx_t *ctx: read / write interface definitions
* @param uint8_t * : buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MLC0_SRC, buff, 8);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
+
return ret;
}
@@ -1588,7 +2023,7 @@ int32_t lsm6dsox_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff)
/**
* @defgroup LSM6DSOX_common
- * @brief This section groups common usefull functions.
+ * @brief This section groups common useful functions.
* @{
*
*/
@@ -1601,6 +2036,7 @@ int32_t lsm6dsox_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @param ctx read / write interface definitions
* @param val change the values of freq_fine in reg
* INTERNAL_FREQ_FINE
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1608,12 +2044,16 @@ int32_t lsm6dsox_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_internal_freq_fine_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INTERNAL_FREQ_FINE, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INTERNAL_FREQ_FINE,
+ (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.freq_fine = val;
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INTERNAL_FREQ_FINE,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1624,6 +2064,7 @@ int32_t lsm6dsox_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of freq_fine in reg INTERNAL_FREQ_FINE
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1631,7 +2072,8 @@ int32_t lsm6dsox_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_internal_freq_fine_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INTERNAL_FREQ_FINE, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INTERNAL_FREQ_FINE,
+ (uint8_t *)®, 1);
*val = reg.freq_fine;
return ret;
@@ -1645,18 +2087,25 @@ int32_t lsm6dsox_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val)
* @param ctx read / write interface definitions
* @param val change the values of reg_access in
* reg FUNC_CFG_ACCESS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_mem_bank_set(stmdev_ctx_t *ctx, lsm6dsox_reg_access_t val)
+int32_t lsm6dsox_mem_bank_set(stmdev_ctx_t *ctx,
+ lsm6dsox_reg_access_t val)
{
lsm6dsox_func_cfg_access_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS,
+ (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.reg_access = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS,
+ (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1667,28 +2116,37 @@ int32_t lsm6dsox_mem_bank_set(stmdev_ctx_t *ctx, lsm6dsox_reg_access_t val)
* @param ctx read / write interface definitions
* @param val Get the values of reg_access in
* reg FUNC_CFG_ACCESS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_mem_bank_get(stmdev_ctx_t *ctx, lsm6dsox_reg_access_t *val)
+int32_t lsm6dsox_mem_bank_get(stmdev_ctx_t *ctx,
+ lsm6dsox_reg_access_t *val)
{
lsm6dsox_func_cfg_access_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS, (uint8_t*)®, 1);
- switch (reg.reg_access) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS,
+ (uint8_t *)®, 1);
+
+ switch (reg.reg_access)
+ {
case LSM6DSOX_USER_BANK:
*val = LSM6DSOX_USER_BANK;
break;
+
case LSM6DSOX_SENSOR_HUB_BANK:
*val = LSM6DSOX_SENSOR_HUB_BANK;
break;
+
case LSM6DSOX_EMBEDDED_FUNC_BANK:
*val = LSM6DSOX_EMBEDDED_FUNC_BANK;
break;
+
default:
*val = LSM6DSOX_USER_BANK;
break;
}
+
return ret;
}
@@ -1698,10 +2156,11 @@ int32_t lsm6dsox_mem_bank_get(stmdev_ctx_t *ctx, lsm6dsox_reg_access_t *val)
* @param ctx read / write interface definitions
* @param uint8_t address: page line address
* @param val value to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address,
- uint8_t *val)
+ uint8_t *val)
{
lsm6dsox_page_rw_t page_rw;
lsm6dsox_page_sel_t page_sel;
@@ -1710,41 +2169,58 @@ int32_t lsm6dsox_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address,
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x02; /* page_write enable */
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t *) &page_sel, 1);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
page_sel.not_used_01 = 1;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL,
+ (uint8_t *) &page_sel, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_address.page_addr = (uint8_t)address & 0xFFU;
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_ADDRESS,
- (uint8_t*)&page_address, 1);
+ (uint8_t *)&page_address, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_VALUE, val, 1);
}
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x00; /* page_write disable */
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
+
return ret;
}
@@ -1755,6 +2231,7 @@ int32_t lsm6dsox_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address,
* @param uint8_t address: page line address
* @param uint8_t *buf: buffer to write
* @param uint8_t len: buffer len
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address,
@@ -1764,71 +2241,89 @@ int32_t lsm6dsox_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address,
lsm6dsox_page_sel_t page_sel;
lsm6dsox_page_address_t page_address;
int32_t ret;
+
uint8_t msb, lsb;
uint8_t i ;
-
msb = ((uint8_t)(address >> 8) & 0x0FU);
lsb = (uint8_t)address & 0xFFU;
-
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x02; /* page_write enable*/
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t *) &page_sel, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_sel.page_sel = msb;
page_sel.not_used_01 = 1;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL,
+ (uint8_t *) &page_sel, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_address.page_addr = lsb;
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_ADDRESS,
- (uint8_t*)&page_address, 1);
+ (uint8_t *)&page_address, 1);
}
- if (ret == 0) {
-
- for (i = 0; ( (i < len) && (ret == 0) ); i++)
+ if (ret == 0)
+ {
+ for (i = 0; ((i < len) && (ret == 0)); i++)
{
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_VALUE, &buf[i], 1);
+ lsb++;
/* Check if page wrap */
- if ( (lsb == 0x00U) && (ret == 0) ) {
- lsb++;
+ if ((lsb == 0x00U) && (ret == 0))
+ {
msb++;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*)&page_sel, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t *)&page_sel, 1);
+
+ if (ret == 0)
+ {
page_sel.page_sel = msb;
page_sel.not_used_01 = 1;
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
+ (uint8_t *)&page_sel, 1);
}
}
}
- page_sel.page_sel = 0;
- page_sel.not_used_01 = 1;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1);
}
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
+ page_sel.page_sel = 0;
+ page_sel.not_used_01 = 1;
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL,
+ (uint8_t *) &page_sel, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x00; /* page_write disable */
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
-
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
+
return ret;
}
@@ -1838,10 +2333,11 @@ int32_t lsm6dsox_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address,
* @param ctx read / write interface definitions
* @param uint8_t address: page line address
* @param val read value
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t address,
- uint8_t *val)
+ uint8_t *val)
{
lsm6dsox_page_rw_t page_rw;
lsm6dsox_page_sel_t page_sel;
@@ -1849,40 +2345,56 @@ int32_t lsm6dsox_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t address,
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x01; /* page_read enable*/
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t *) &page_sel, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
page_sel.not_used_01 = 1;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL,
+ (uint8_t *) &page_sel, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_address.page_addr = (uint8_t)address & 0x00FFU;
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_ADDRESS,
- (uint8_t*)&page_address, 1);
+ (uint8_t *)&page_address, 1);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_VALUE, val, 1);
}
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x00; /* page_read disable */
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -1896,19 +2408,25 @@ int32_t lsm6dsox_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t address,
* @param val change the values of
* dataready_pulsed in
* reg COUNTER_BDR_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_data_ready_mode_set(stmdev_ctx_t *ctx,
- lsm6dsox_dataready_pulsed_t val)
+ lsm6dsox_dataready_pulsed_t val)
{
lsm6dsox_counter_bdr_reg1_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1,
+ (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.dataready_pulsed = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1,
+ (uint8_t *)®, 1);
}
+
return ret;
}
@@ -1919,26 +2437,33 @@ int32_t lsm6dsox_data_ready_mode_set(stmdev_ctx_t *ctx,
* @param val Get the values of
* dataready_pulsed in
* reg COUNTER_BDR_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_data_ready_mode_get(stmdev_ctx_t *ctx,
- lsm6dsox_dataready_pulsed_t *val)
+ lsm6dsox_dataready_pulsed_t *val)
{
lsm6dsox_counter_bdr_reg1_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)®, 1);
- switch (reg.dataready_pulsed) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1,
+ (uint8_t *)®, 1);
+
+ switch (reg.dataready_pulsed)
+ {
case LSM6DSOX_DRDY_LATCHED:
*val = LSM6DSOX_DRDY_LATCHED;
break;
+
case LSM6DSOX_DRDY_PULSED:
*val = LSM6DSOX_DRDY_PULSED;
break;
+
default:
*val = LSM6DSOX_DRDY_LATCHED;
break;
}
+
return ret;
}
@@ -1947,12 +2472,15 @@ int32_t lsm6dsox_data_ready_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -1962,6 +2490,7 @@ int32_t lsm6dsox_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param val change the values of sw_reset in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_reset_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -1969,10 +2498,12 @@ int32_t lsm6dsox_reset_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.sw_reset = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
}
return ret;
@@ -1983,6 +2514,7 @@ int32_t lsm6dsox_reset_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of sw_reset in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -1990,7 +2522,7 @@ int32_t lsm6dsox_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
*val = reg.sw_reset;
return ret;
@@ -2002,6 +2534,7 @@ int32_t lsm6dsox_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of if_inc in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -2009,11 +2542,14 @@ int32_t lsm6dsox_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.if_inc = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2023,6 +2559,7 @@ int32_t lsm6dsox_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of if_inc in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -2030,7 +2567,7 @@ int32_t lsm6dsox_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
*val = reg.if_inc;
return ret;
@@ -2041,6 +2578,7 @@ int32_t lsm6dsox_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of boot in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_boot_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -2048,11 +2586,14 @@ int32_t lsm6dsox_boot_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.boot = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2061,6 +2602,7 @@ int32_t lsm6dsox_boot_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of boot in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -2068,7 +2610,7 @@ int32_t lsm6dsox_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
*val = reg.boot;
return ret;
@@ -2079,18 +2621,23 @@ int32_t lsm6dsox_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of st_xl in reg CTRL5_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_xl_self_test_set(stmdev_ctx_t *ctx, lsm6dsox_st_xl_t val)
+int32_t lsm6dsox_xl_self_test_set(stmdev_ctx_t *ctx,
+ lsm6dsox_st_xl_t val)
{
lsm6dsox_ctrl5_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.st_xl = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2099,28 +2646,36 @@ int32_t lsm6dsox_xl_self_test_set(stmdev_ctx_t *ctx, lsm6dsox_st_xl_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of st_xl in reg CTRL5_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_xl_self_test_get(stmdev_ctx_t *ctx, lsm6dsox_st_xl_t *val)
+int32_t lsm6dsox_xl_self_test_get(stmdev_ctx_t *ctx,
+ lsm6dsox_st_xl_t *val)
{
lsm6dsox_ctrl5_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1);
- switch (reg.st_xl) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)®, 1);
+
+ switch (reg.st_xl)
+ {
case LSM6DSOX_XL_ST_DISABLE:
*val = LSM6DSOX_XL_ST_DISABLE;
break;
+
case LSM6DSOX_XL_ST_POSITIVE:
*val = LSM6DSOX_XL_ST_POSITIVE;
break;
+
case LSM6DSOX_XL_ST_NEGATIVE:
*val = LSM6DSOX_XL_ST_NEGATIVE;
break;
+
default:
*val = LSM6DSOX_XL_ST_DISABLE;
break;
}
+
return ret;
}
@@ -2129,18 +2684,23 @@ int32_t lsm6dsox_xl_self_test_get(stmdev_ctx_t *ctx, lsm6dsox_st_xl_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of st_g in reg CTRL5_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_gy_self_test_set(stmdev_ctx_t *ctx, lsm6dsox_st_g_t val)
+int32_t lsm6dsox_gy_self_test_set(stmdev_ctx_t *ctx,
+ lsm6dsox_st_g_t val)
{
lsm6dsox_ctrl5_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.st_g = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2149,28 +2709,36 @@ int32_t lsm6dsox_gy_self_test_set(stmdev_ctx_t *ctx, lsm6dsox_st_g_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of st_g in reg CTRL5_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_gy_self_test_get(stmdev_ctx_t *ctx, lsm6dsox_st_g_t *val)
+int32_t lsm6dsox_gy_self_test_get(stmdev_ctx_t *ctx,
+ lsm6dsox_st_g_t *val)
{
lsm6dsox_ctrl5_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1);
- switch (reg.st_g) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)®, 1);
+
+ switch (reg.st_g)
+ {
case LSM6DSOX_GY_ST_DISABLE:
*val = LSM6DSOX_GY_ST_DISABLE;
break;
+
case LSM6DSOX_GY_ST_POSITIVE:
*val = LSM6DSOX_GY_ST_POSITIVE;
break;
+
case LSM6DSOX_GY_ST_NEGATIVE:
*val = LSM6DSOX_GY_ST_NEGATIVE;
break;
+
default:
*val = LSM6DSOX_GY_ST_DISABLE;
break;
}
+
return ret;
}
@@ -2192,6 +2760,7 @@ int32_t lsm6dsox_gy_self_test_get(stmdev_ctx_t *ctx, lsm6dsox_st_g_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of lpf2_xl_en in reg CTRL1_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -2199,11 +2768,14 @@ int32_t lsm6dsox_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_ctrl1_xl_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.lpf2_xl_en = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2212,6 +2784,7 @@ int32_t lsm6dsox_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of lpf2_xl_en in reg CTRL1_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -2219,7 +2792,7 @@ int32_t lsm6dsox_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_ctrl1_xl_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t *)®, 1);
*val = reg.lpf2_xl_en;
return ret;
@@ -2232,6 +2805,7 @@ int32_t lsm6dsox_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of lpf1_sel_g in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -2239,11 +2813,14 @@ int32_t lsm6dsox_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_ctrl4_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.lpf1_sel_g = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2254,6 +2831,7 @@ int32_t lsm6dsox_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of lpf1_sel_g in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -2261,7 +2839,7 @@ int32_t lsm6dsox_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_ctrl4_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1);
*val = reg.lpf1_sel_g;
return ret;
@@ -2273,18 +2851,23 @@ int32_t lsm6dsox_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of drdy_mask in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dsox_filter_settling_mask_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dsox_ctrl4_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.drdy_mask = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2294,14 +2877,16 @@ int32_t lsm6dsox_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of drdy_mask in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsox_filter_settling_mask_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsox_ctrl4_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1);
*val = reg.drdy_mask;
return ret;
@@ -2312,18 +2897,23 @@ int32_t lsm6dsox_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of ftype in reg CTRL6_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, lsm6dsox_ftype_t val)
+int32_t lsm6dsox_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
+ lsm6dsox_ftype_t val)
{
lsm6dsox_ctrl6_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.ftype = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2332,43 +2922,56 @@ int32_t lsm6dsox_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, lsm6dsox_ftype_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of ftype in reg CTRL6_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, lsm6dsox_ftype_t *val)
+int32_t lsm6dsox_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
+ lsm6dsox_ftype_t *val)
{
lsm6dsox_ctrl6_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)®, 1);
- switch (reg.ftype) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t *)®, 1);
+
+ switch (reg.ftype)
+ {
case LSM6DSOX_ULTRA_LIGHT:
*val = LSM6DSOX_ULTRA_LIGHT;
break;
+
case LSM6DSOX_VERY_LIGHT:
*val = LSM6DSOX_VERY_LIGHT;
break;
+
case LSM6DSOX_LIGHT:
*val = LSM6DSOX_LIGHT;
break;
+
case LSM6DSOX_MEDIUM:
*val = LSM6DSOX_MEDIUM;
break;
+
case LSM6DSOX_STRONG:
*val = LSM6DSOX_STRONG;
break;
+
case LSM6DSOX_VERY_STRONG:
*val = LSM6DSOX_VERY_STRONG;
break;
+
case LSM6DSOX_AGGRESSIVE:
*val = LSM6DSOX_AGGRESSIVE;
break;
+
case LSM6DSOX_XTREME:
*val = LSM6DSOX_XTREME;
break;
+
default:
*val = LSM6DSOX_ULTRA_LIGHT;
break;
}
+
return ret;
}
@@ -2377,6 +2980,7 @@ int32_t lsm6dsox_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, lsm6dsox_ftype_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of low_pass_on_6d in reg CTRL8_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -2384,11 +2988,14 @@ int32_t lsm6dsox_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_ctrl8_xl_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.low_pass_on_6d = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2397,6 +3004,7 @@ int32_t lsm6dsox_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of low_pass_on_6d in reg CTRL8_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -2404,7 +3012,7 @@ int32_t lsm6dsox_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_ctrl8_xl_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t *)®, 1);
*val = reg.low_pass_on_6d;
return ret;
@@ -2417,21 +3025,25 @@ int32_t lsm6dsox_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val)
* @param ctx read / write interface definitions
* @param val change the values of hp_slope_xl_en
* in reg CTRL8_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
- lsm6dsox_hp_slope_xl_en_t val)
+ lsm6dsox_hp_slope_xl_en_t val)
{
lsm6dsox_ctrl8_xl_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.hp_slope_xl_en = ((uint8_t)val & 0x10U) >> 4;
reg.hp_ref_mode_xl = ((uint8_t)val & 0x20U) >> 5;
reg.hpcf_xl = (uint8_t)val & 0x07U;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2442,86 +3054,112 @@ int32_t lsm6dsox_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val Get the values of hp_slope_xl_en
* in reg CTRL8_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
- lsm6dsox_hp_slope_xl_en_t *val)
+ lsm6dsox_hp_slope_xl_en_t *val)
{
lsm6dsox_ctrl8_xl_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t *)®, 1);
+
switch ((reg.hp_ref_mode_xl << 5) | (reg.hp_slope_xl_en << 4) |
- reg.hpcf_xl) {
+ reg.hpcf_xl)
+ {
case LSM6DSOX_HP_PATH_DISABLE_ON_OUT:
*val = LSM6DSOX_HP_PATH_DISABLE_ON_OUT;
break;
+
case LSM6DSOX_SLOPE_ODR_DIV_4:
*val = LSM6DSOX_SLOPE_ODR_DIV_4;
break;
+
case LSM6DSOX_HP_ODR_DIV_10:
*val = LSM6DSOX_HP_ODR_DIV_10;
break;
+
case LSM6DSOX_HP_ODR_DIV_20:
*val = LSM6DSOX_HP_ODR_DIV_20;
break;
+
case LSM6DSOX_HP_ODR_DIV_45:
*val = LSM6DSOX_HP_ODR_DIV_45;
break;
+
case LSM6DSOX_HP_ODR_DIV_100:
*val = LSM6DSOX_HP_ODR_DIV_100;
break;
+
case LSM6DSOX_HP_ODR_DIV_200:
*val = LSM6DSOX_HP_ODR_DIV_200;
break;
+
case LSM6DSOX_HP_ODR_DIV_400:
*val = LSM6DSOX_HP_ODR_DIV_400;
break;
+
case LSM6DSOX_HP_ODR_DIV_800:
*val = LSM6DSOX_HP_ODR_DIV_800;
break;
+
case LSM6DSOX_HP_REF_MD_ODR_DIV_10:
*val = LSM6DSOX_HP_REF_MD_ODR_DIV_10;
break;
+
case LSM6DSOX_HP_REF_MD_ODR_DIV_20:
*val = LSM6DSOX_HP_REF_MD_ODR_DIV_20;
break;
+
case LSM6DSOX_HP_REF_MD_ODR_DIV_45:
*val = LSM6DSOX_HP_REF_MD_ODR_DIV_45;
break;
+
case LSM6DSOX_HP_REF_MD_ODR_DIV_100:
*val = LSM6DSOX_HP_REF_MD_ODR_DIV_100;
break;
+
case LSM6DSOX_HP_REF_MD_ODR_DIV_200:
*val = LSM6DSOX_HP_REF_MD_ODR_DIV_200;
break;
+
case LSM6DSOX_HP_REF_MD_ODR_DIV_400:
*val = LSM6DSOX_HP_REF_MD_ODR_DIV_400;
break;
+
case LSM6DSOX_HP_REF_MD_ODR_DIV_800:
*val = LSM6DSOX_HP_REF_MD_ODR_DIV_800;
break;
+
case LSM6DSOX_LP_ODR_DIV_10:
*val = LSM6DSOX_LP_ODR_DIV_10;
break;
+
case LSM6DSOX_LP_ODR_DIV_20:
*val = LSM6DSOX_LP_ODR_DIV_20;
break;
+
case LSM6DSOX_LP_ODR_DIV_45:
*val = LSM6DSOX_LP_ODR_DIV_45;
break;
+
case LSM6DSOX_LP_ODR_DIV_100:
*val = LSM6DSOX_LP_ODR_DIV_100;
break;
+
case LSM6DSOX_LP_ODR_DIV_200:
*val = LSM6DSOX_LP_ODR_DIV_200;
break;
+
case LSM6DSOX_LP_ODR_DIV_400:
*val = LSM6DSOX_LP_ODR_DIV_400;
break;
+
case LSM6DSOX_LP_ODR_DIV_800:
*val = LSM6DSOX_LP_ODR_DIV_800;
break;
+
default:
*val = LSM6DSOX_HP_PATH_DISABLE_ON_OUT;
break;
@@ -2538,6 +3176,7 @@ int32_t lsm6dsox_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of fastsettl_mode_xl in
* reg CTRL8_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -2545,11 +3184,14 @@ int32_t lsm6dsox_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_ctrl8_xl_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.fastsettl_mode_xl = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2560,6 +3202,7 @@ int32_t lsm6dsox_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of fastsettl_mode_xl in reg CTRL8_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -2567,7 +3210,7 @@ int32_t lsm6dsox_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_ctrl8_xl_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t *)®, 1);
*val = reg.fastsettl_mode_xl;
return ret;
@@ -2579,19 +3222,23 @@ int32_t lsm6dsox_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of slope_fds in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
- lsm6dsox_slope_fds_t val)
+ lsm6dsox_slope_fds_t val)
{
lsm6dsox_tap_cfg0_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.slope_fds = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2601,26 +3248,32 @@ int32_t lsm6dsox_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Change the values of slope_fds in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
- lsm6dsox_slope_fds_t *val)
+ lsm6dsox_slope_fds_t *val)
{
lsm6dsox_tap_cfg0_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1);
- switch (reg.slope_fds) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1);
+
+ switch (reg.slope_fds)
+ {
case LSM6DSOX_USE_SLOPE:
*val = LSM6DSOX_USE_SLOPE;
break;
+
case LSM6DSOX_USE_HPF:
*val = LSM6DSOX_USE_HPF;
break;
+
default:
*val = LSM6DSOX_USE_SLOPE;
break;
}
+
return ret;
}
@@ -2631,20 +3284,24 @@ int32_t lsm6dsox_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val Get the values of hp_en_g and hp_en_g
* in reg CTRL7_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
- lsm6dsox_hpm_g_t val)
+ lsm6dsox_hpm_g_t val)
{
lsm6dsox_ctrl7_g_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.hp_en_g = ((uint8_t)val & 0x80U) >> 7;
reg.hpm_g = (uint8_t)val & 0x03U;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2655,35 +3312,44 @@ int32_t lsm6dsox_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val Get the values of hp_en_g and hp_en_g
* in reg CTRL7_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
- lsm6dsox_hpm_g_t *val)
+ lsm6dsox_hpm_g_t *val)
{
lsm6dsox_ctrl7_g_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1);
- switch ((reg.hp_en_g << 7) + reg.hpm_g) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t *)®, 1);
+
+ switch ((reg.hp_en_g << 7) + reg.hpm_g)
+ {
case LSM6DSOX_HP_FILTER_NONE:
*val = LSM6DSOX_HP_FILTER_NONE;
break;
+
case LSM6DSOX_HP_FILTER_16mHz:
*val = LSM6DSOX_HP_FILTER_16mHz;
break;
+
case LSM6DSOX_HP_FILTER_65mHz:
*val = LSM6DSOX_HP_FILTER_65mHz;
break;
+
case LSM6DSOX_HP_FILTER_260mHz:
*val = LSM6DSOX_HP_FILTER_260mHz;
break;
+
case LSM6DSOX_HP_FILTER_1Hz04:
*val = LSM6DSOX_HP_FILTER_1Hz04;
break;
+
default:
*val = LSM6DSOX_HP_FILTER_NONE;
break;
}
+
return ret;
}
@@ -2705,29 +3371,39 @@ int32_t lsm6dsox_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of spi2_read_en in reg UI_INT_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_ois_mode_set(stmdev_ctx_t *ctx, lsm6dsox_spi2_read_en_t val)
+int32_t lsm6dsox_ois_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsox_spi2_read_en_t val)
{
lsm6dsox_func_cfg_access_t func_cfg_access;
lsm6dsox_ui_int_ois_t ui_int_ois;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)&ui_int_ois, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS,
+ (uint8_t *)&ui_int_ois, 1);
+
+ if (ret == 0)
+ {
ui_int_ois.spi2_read_en = ((uint8_t)val & 0x01U);
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_INT_OIS,
- (uint8_t*)&ui_int_ois, 1);
+ (uint8_t *)&ui_int_ois, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
+ (uint8_t *)&func_cfg_access, 1);
}
- if (ret == 0) {
- func_cfg_access.ois_ctrl_from_ui = ( ((uint8_t)val & 0x02U) >> 1 );
+
+ if (ret == 0)
+ {
+ func_cfg_access.ois_ctrl_from_ui = (((uint8_t)val & 0x02U) >> 1);
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
+ (uint8_t *)&func_cfg_access, 1);
}
+
return ret;
}
@@ -2737,37 +3413,49 @@ int32_t lsm6dsox_ois_mode_set(stmdev_ctx_t *ctx, lsm6dsox_spi2_read_en_t val)
* @param ctx read / write interface definitions
* @param val Get the values of spi2_read_en
* in reg UI_INT_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_ois_mode_get(stmdev_ctx_t *ctx,
- lsm6dsox_spi2_read_en_t *val)
+ lsm6dsox_spi2_read_en_t *val)
{
lsm6dsox_func_cfg_access_t func_cfg_access;
lsm6dsox_ui_int_ois_t ui_int_ois;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)&ui_int_ois, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS,
+ (uint8_t *)&ui_int_ois, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
+ (uint8_t *)&func_cfg_access, 1);
}
- switch ((func_cfg_access.ois_ctrl_from_ui << 1) + ui_int_ois.spi2_read_en) {
+
+ switch ((func_cfg_access.ois_ctrl_from_ui << 1) +
+ ui_int_ois.spi2_read_en)
+ {
case LSM6DSOX_OIS_CTRL_AUX_DATA_UI:
*val = LSM6DSOX_OIS_CTRL_AUX_DATA_UI;
break;
+
case LSM6DSOX_OIS_CTRL_AUX_DATA_UI_AUX:
*val = LSM6DSOX_OIS_CTRL_AUX_DATA_UI_AUX;
break;
+
case LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI:
*val = LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI;
break;
+
case LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI_AUX:
*val = LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI_AUX;
break;
+
default:
*val = LSM6DSOX_OIS_CTRL_AUX_DATA_UI;
break;
}
+
return ret;
}
@@ -2778,19 +3466,23 @@ int32_t lsm6dsox_ois_mode_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of ois_pu_dis in
* reg PIN_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx,
- lsm6dsox_ois_pu_dis_t val)
+ lsm6dsox_ois_pu_dis_t val)
{
lsm6dsox_pin_ctrl_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.ois_pu_dis = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2800,26 +3492,32 @@ int32_t lsm6dsox_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of ois_pu_dis in reg PIN_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx,
- lsm6dsox_ois_pu_dis_t *val)
+ lsm6dsox_ois_pu_dis_t *val)
{
lsm6dsox_pin_ctrl_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)®, 1);
- switch (reg.ois_pu_dis) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t *)®, 1);
+
+ switch (reg.ois_pu_dis)
+ {
case LSM6DSOX_AUX_PULL_UP_DISC:
*val = LSM6DSOX_AUX_PULL_UP_DISC;
break;
+
case LSM6DSOX_AUX_PULL_UP_CONNECT:
*val = LSM6DSOX_AUX_PULL_UP_CONNECT;
break;
+
default:
*val = LSM6DSOX_AUX_PULL_UP_DISC;
break;
}
+
return ret;
}
@@ -2828,19 +3526,24 @@ int32_t lsm6dsox_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of ois_on in reg CTRL7_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx, lsm6dsox_ois_on_t val)
+int32_t lsm6dsox_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx,
+ lsm6dsox_ois_on_t val)
{
lsm6dsox_ctrl7_g_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.ois_on_en = (uint8_t)val & 0x01U;
reg.ois_on = (uint8_t)val & 0x01U;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2849,21 +3552,27 @@ int32_t lsm6dsox_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx, lsm6dsox_ois_on_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of ois_on in reg CTRL7_G
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx, lsm6dsox_ois_on_t *val)
+int32_t lsm6dsox_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx,
+ lsm6dsox_ois_on_t *val)
{
lsm6dsox_ctrl7_g_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1);
- switch (reg.ois_on) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t *)®, 1);
+
+ switch (reg.ois_on)
+ {
case LSM6DSOX_AUX_ON:
*val = LSM6DSOX_AUX_ON;
break;
+
case LSM6DSOX_AUX_ON_BY_AUX_INTERFACE:
*val = LSM6DSOX_AUX_ON_BY_AUX_INTERFACE;
break;
+
default:
*val = LSM6DSOX_AUX_ON;
break;
@@ -2883,19 +3592,23 @@ int32_t lsm6dsox_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx, lsm6dsox_ois_on_t *val)
* @param ctx read / write interface definitions
* @param val change the values of xl_fs_mode in
* reg CTRL8_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_aux_xl_fs_mode_set(stmdev_ctx_t *ctx,
- lsm6dsox_xl_fs_mode_t val)
+ lsm6dsox_xl_fs_mode_t val)
{
lsm6dsox_ctrl8_xl_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.xl_fs_mode = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -2909,22 +3622,27 @@ int32_t lsm6dsox_aux_xl_fs_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of xl_fs_mode in reg CTRL8_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_aux_xl_fs_mode_get(stmdev_ctx_t *ctx,
- lsm6dsox_xl_fs_mode_t *val)
+ lsm6dsox_xl_fs_mode_t *val)
{
lsm6dsox_ctrl8_xl_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1);
- switch (reg.xl_fs_mode) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t *)®, 1);
+
+ switch (reg.xl_fs_mode)
+ {
case LSM6DSOX_USE_SAME_XL_FS:
*val = LSM6DSOX_USE_SAME_XL_FS;
break;
+
case LSM6DSOX_USE_DIFFERENT_XL_FS:
*val = LSM6DSOX_USE_DIFFERENT_XL_FS;
break;
+
default:
*val = LSM6DSOX_USE_SAME_XL_FS;
break;
@@ -2938,13 +3656,17 @@ int32_t lsm6dsox_aux_xl_fs_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get registers STATUS_SPIAUX
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_aux_status_reg_get(stmdev_ctx_t *ctx,
- lsm6dsox_spi2_status_reg_ois_t *val)
+ lsm6dsox_spi2_status_reg_ois_t *val)
{
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_STATUS_REG_OIS, (uint8_t*) val, 1);
+
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_STATUS_REG_OIS,
+ (uint8_t *) val, 1);
+
return ret;
}
@@ -2953,14 +3675,17 @@ int32_t lsm6dsox_aux_status_reg_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of xlda in reg STATUS_SPIAUX
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsox_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsox_spi2_status_reg_ois_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_STATUS_REG_OIS, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_STATUS_REG_OIS,
+ (uint8_t *)®, 1);
*val = reg.xlda;
return ret;
@@ -2971,14 +3696,17 @@ int32_t lsm6dsox_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of gda in reg STATUS_SPIAUX
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsox_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsox_spi2_status_reg_ois_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_STATUS_REG_OIS, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_STATUS_REG_OIS,
+ (uint8_t *)®, 1);
*val = reg.gda;
return ret;
@@ -2989,14 +3717,17 @@ int32_t lsm6dsox_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of gyro_settling in reg STATUS_SPIAUX
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsox_aux_gy_flag_settling_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsox_spi2_status_reg_ois_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_STATUS_REG_OIS, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_STATUS_REG_OIS,
+ (uint8_t *)®, 1);
*val = reg.gyro_settling;
return ret;
@@ -3008,19 +3739,23 @@ int32_t lsm6dsox_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
* @param ctx read / write interface definitions
* @param val change the values of den_lh_ois in
* reg INT_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_aux_den_polarity_set(stmdev_ctx_t *ctx,
- lsm6dsox_den_lh_ois_t val)
+ lsm6dsox_den_lh_ois_t val)
{
lsm6dsox_ui_int_ois_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.den_lh_ois = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3029,26 +3764,32 @@ int32_t lsm6dsox_aux_den_polarity_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of den_lh_ois in reg INT_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_aux_den_polarity_get(stmdev_ctx_t *ctx,
- lsm6dsox_den_lh_ois_t *val)
+ lsm6dsox_den_lh_ois_t *val)
{
lsm6dsox_ui_int_ois_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)®, 1);
- switch (reg.den_lh_ois) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t *)®, 1);
+
+ switch (reg.den_lh_ois)
+ {
case LSM6DSOX_AUX_DEN_ACTIVE_LOW:
*val = LSM6DSOX_AUX_DEN_ACTIVE_LOW;
break;
+
case LSM6DSOX_AUX_DEN_ACTIVE_HIGH:
*val = LSM6DSOX_AUX_DEN_ACTIVE_HIGH;
break;
+
default:
*val = LSM6DSOX_AUX_DEN_ACTIVE_LOW;
break;
}
+
return ret;
}
@@ -3057,26 +3798,39 @@ int32_t lsm6dsox_aux_den_polarity_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of lvl2_ois in reg INT_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_aux_den_mode_set(stmdev_ctx_t *ctx, lsm6dsox_lvl2_ois_t val)
+int32_t lsm6dsox_aux_den_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsox_lvl2_ois_t val)
{
lsm6dsox_ui_ctrl1_ois_t ctrl1_ois;
lsm6dsox_ui_int_ois_t int_ois;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*) &int_ois, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS,
+ (uint8_t *) &int_ois, 1);
+
+ if (ret == 0)
+ {
int_ois.lvl2_ois = (uint8_t)val & 0x01U;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*) &int_ois, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_INT_OIS,
+ (uint8_t *) &int_ois, 1);
}
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*) &ctrl1_ois, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS,
+ (uint8_t *) &ctrl1_ois, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ctrl1_ois.lvl1_ois = ((uint8_t)val & 0x02U) >> 1;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*) &ctrl1_ois, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS,
+ (uint8_t *) &ctrl1_ois, 1);
}
+
return ret;
}
@@ -3085,32 +3839,44 @@ int32_t lsm6dsox_aux_den_mode_set(stmdev_ctx_t *ctx, lsm6dsox_lvl2_ois_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of lvl2_ois in reg INT_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_aux_den_mode_get(stmdev_ctx_t *ctx, lsm6dsox_lvl2_ois_t *val)
+int32_t lsm6dsox_aux_den_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsox_lvl2_ois_t *val)
{
lsm6dsox_ui_ctrl1_ois_t ctrl1_ois;
lsm6dsox_ui_int_ois_t int_ois;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*) &int_ois, 1);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*) &ctrl1_ois, 1);
- switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS,
+ (uint8_t *) &int_ois, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS,
+ (uint8_t *) &ctrl1_ois, 1);
+
+ switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois)
+ {
case LSM6DSOX_AUX_DEN_DISABLE:
*val = LSM6DSOX_AUX_DEN_DISABLE;
break;
+
case LSM6DSOX_AUX_DEN_LEVEL_LATCH:
*val = LSM6DSOX_AUX_DEN_LEVEL_LATCH;
break;
+
case LSM6DSOX_AUX_DEN_LEVEL_TRIG:
*val = LSM6DSOX_AUX_DEN_LEVEL_TRIG;
break;
+
default:
*val = LSM6DSOX_AUX_DEN_DISABLE;
break;
}
}
+
return ret;
}
@@ -3120,6 +3886,7 @@ int32_t lsm6dsox_aux_den_mode_get(stmdev_ctx_t *ctx, lsm6dsox_lvl2_ois_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of int2_drdy_ois in reg INT_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -3127,11 +3894,14 @@ int32_t lsm6dsox_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_ui_int_ois_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.int2_drdy_ois = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3141,6 +3911,7 @@ int32_t lsm6dsox_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of int2_drdy_ois in reg INT_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -3148,7 +3919,7 @@ int32_t lsm6dsox_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_ui_int_ois_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t *)®, 1);
*val = reg.int2_drdy_ois;
return ret;
@@ -3165,19 +3936,24 @@ int32_t lsm6dsox_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val)
* @param ctx read / write interface definitions
* @param val change the values of ois_en_spi2 in
* reg CTRL1_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_aux_mode_set(stmdev_ctx_t *ctx, lsm6dsox_ois_en_spi2_t val)
+int32_t lsm6dsox_aux_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsox_ois_en_spi2_t val)
{
lsm6dsox_ui_ctrl1_ois_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.ois_en_spi2 = (uint8_t)val & 0x01U;
reg.mode4_en = ((uint8_t)val & 0x02U) >> 1;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3192,28 +3968,36 @@ int32_t lsm6dsox_aux_mode_set(stmdev_ctx_t *ctx, lsm6dsox_ois_en_spi2_t val)
* @param ctx read / write interface definitions
* @param val Get the values of ois_en_spi2 in
* reg CTRL1_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_aux_mode_get(stmdev_ctx_t *ctx, lsm6dsox_ois_en_spi2_t *val)
+int32_t lsm6dsox_aux_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsox_ois_en_spi2_t *val)
{
lsm6dsox_ui_ctrl1_ois_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)®, 1);
- switch ((reg.mode4_en << 1) | reg.ois_en_spi2) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t *)®, 1);
+
+ switch ((reg.mode4_en << 1) | reg.ois_en_spi2)
+ {
case LSM6DSOX_AUX_DISABLE:
*val = LSM6DSOX_AUX_DISABLE;
break;
+
case LSM6DSOX_MODE_3_GY:
*val = LSM6DSOX_MODE_3_GY;
break;
+
case LSM6DSOX_MODE_4_GY_XL:
*val = LSM6DSOX_MODE_4_GY_XL;
break;
+
default:
*val = LSM6DSOX_AUX_DISABLE;
break;
}
+
return ret;
}
@@ -3222,19 +4006,23 @@ int32_t lsm6dsox_aux_mode_get(stmdev_ctx_t *ctx, lsm6dsox_ois_en_spi2_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of fs_g_ois in reg CTRL1_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_aux_gy_full_scale_set(stmdev_ctx_t *ctx,
- lsm6dsox_fs_g_ois_t val)
+ lsm6dsox_fs_g_ois_t val)
{
lsm6dsox_ui_ctrl1_ois_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.fs_g_ois = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3243,35 +4031,44 @@ int32_t lsm6dsox_aux_gy_full_scale_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of fs_g_ois in reg CTRL1_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_aux_gy_full_scale_get(stmdev_ctx_t *ctx,
- lsm6dsox_fs_g_ois_t *val)
+ lsm6dsox_fs_g_ois_t *val)
{
lsm6dsox_ui_ctrl1_ois_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)®, 1);
- switch (reg.fs_g_ois) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t *)®, 1);
+
+ switch (reg.fs_g_ois)
+ {
case LSM6DSOX_250dps_AUX:
*val = LSM6DSOX_250dps_AUX;
break;
+
case LSM6DSOX_125dps_AUX:
*val = LSM6DSOX_125dps_AUX;
break;
+
case LSM6DSOX_500dps_AUX:
*val = LSM6DSOX_500dps_AUX;
break;
+
case LSM6DSOX_1000dps_AUX:
*val = LSM6DSOX_1000dps_AUX;
break;
+
case LSM6DSOX_2000dps_AUX:
*val = LSM6DSOX_2000dps_AUX;
break;
+
default:
*val = LSM6DSOX_250dps_AUX;
break;
}
+
return ret;
}
@@ -3280,18 +4077,23 @@ int32_t lsm6dsox_aux_gy_full_scale_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of sim_ois in reg CTRL1_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_aux_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsox_sim_ois_t val)
+int32_t lsm6dsox_aux_spi_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsox_sim_ois_t val)
{
lsm6dsox_ui_ctrl1_ois_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.sim_ois = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3300,25 +4102,32 @@ int32_t lsm6dsox_aux_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsox_sim_ois_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of sim_ois in reg CTRL1_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_aux_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsox_sim_ois_t *val)
+int32_t lsm6dsox_aux_spi_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsox_sim_ois_t *val)
{
lsm6dsox_ui_ctrl1_ois_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)®, 1);
- switch (reg.sim_ois) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t *)®, 1);
+
+ switch (reg.sim_ois)
+ {
case LSM6DSOX_AUX_SPI_4_WIRE:
*val = LSM6DSOX_AUX_SPI_4_WIRE;
break;
+
case LSM6DSOX_AUX_SPI_3_WIRE:
*val = LSM6DSOX_AUX_SPI_3_WIRE;
break;
+
default:
*val = LSM6DSOX_AUX_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -3328,19 +4137,23 @@ int32_t lsm6dsox_aux_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsox_sim_ois_t *val)
* @param ctx read / write interface definitions
* @param val change the values of ftype_ois in
* reg CTRL2_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
- lsm6dsox_ftype_ois_t val)
+ lsm6dsox_ftype_ois_t val)
{
lsm6dsox_ui_ctrl2_ois_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.ftype_ois = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3349,32 +4162,40 @@ int32_t lsm6dsox_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of ftype_ois in reg CTRL2_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
- lsm6dsox_ftype_ois_t *val)
+ lsm6dsox_ftype_ois_t *val)
{
lsm6dsox_ui_ctrl2_ois_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t*)®, 1);
- switch (reg.ftype_ois) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t *)®, 1);
+
+ switch (reg.ftype_ois)
+ {
case LSM6DSOX_351Hz39:
*val = LSM6DSOX_351Hz39;
break;
+
case LSM6DSOX_236Hz63:
*val = LSM6DSOX_236Hz63;
break;
+
case LSM6DSOX_172Hz70:
*val = LSM6DSOX_172Hz70;
break;
+
case LSM6DSOX_937Hz91:
*val = LSM6DSOX_937Hz91;
break;
+
default:
*val = LSM6DSOX_351Hz39;
break;
}
+
return ret;
}
@@ -3383,20 +4204,24 @@ int32_t lsm6dsox_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of hpm_ois in reg CTRL2_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx,
- lsm6dsox_hpm_ois_t val)
+ lsm6dsox_hpm_ois_t val)
{
lsm6dsox_ui_ctrl2_ois_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.hpm_ois = (uint8_t)val & 0x03U;
reg.hp_en_ois = ((uint8_t)val & 0x10U) >> 4;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3405,35 +4230,44 @@ int32_t lsm6dsox_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of hpm_ois in reg CTRL2_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx,
- lsm6dsox_hpm_ois_t *val)
+ lsm6dsox_hpm_ois_t *val)
{
lsm6dsox_ui_ctrl2_ois_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t*)®, 1);
- switch ((reg.hp_en_ois << 4) | reg.hpm_ois) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t *)®, 1);
+
+ switch ((reg.hp_en_ois << 4) | reg.hpm_ois)
+ {
case LSM6DSOX_AUX_HP_DISABLE:
*val = LSM6DSOX_AUX_HP_DISABLE;
break;
+
case LSM6DSOX_AUX_HP_Hz016:
*val = LSM6DSOX_AUX_HP_Hz016;
break;
+
case LSM6DSOX_AUX_HP_Hz065:
*val = LSM6DSOX_AUX_HP_Hz065;
break;
+
case LSM6DSOX_AUX_HP_Hz260:
*val = LSM6DSOX_AUX_HP_Hz260;
break;
+
case LSM6DSOX_AUX_HP_1Hz040:
*val = LSM6DSOX_AUX_HP_1Hz040;
break;
+
default:
*val = LSM6DSOX_AUX_HP_DISABLE;
break;
}
+
return ret;
}
@@ -3447,19 +4281,23 @@ int32_t lsm6dsox_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of st_ois_clampdis in
* reg CTRL3_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_aux_gy_clamp_set(stmdev_ctx_t *ctx,
- lsm6dsox_st_ois_clampdis_t val)
+ lsm6dsox_st_ois_clampdis_t val)
{
lsm6dsox_ui_ctrl3_ois_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.st_ois_clampdis = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3473,26 +4311,32 @@ int32_t lsm6dsox_aux_gy_clamp_set(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val Get the values of st_ois_clampdis in
* reg CTRL3_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_aux_gy_clamp_get(stmdev_ctx_t *ctx,
- lsm6dsox_st_ois_clampdis_t *val)
+ lsm6dsox_st_ois_clampdis_t *val)
{
lsm6dsox_ui_ctrl3_ois_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)®, 1);
- switch (reg.st_ois_clampdis) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t *)®, 1);
+
+ switch (reg.st_ois_clampdis)
+ {
case LSM6DSOX_ENABLE_CLAMP:
*val = LSM6DSOX_ENABLE_CLAMP;
break;
+
case LSM6DSOX_DISABLE_CLAMP:
*val = LSM6DSOX_DISABLE_CLAMP;
break;
+
default:
*val = LSM6DSOX_ENABLE_CLAMP;
break;
}
+
return ret;
}
@@ -3502,19 +4346,23 @@ int32_t lsm6dsox_aux_gy_clamp_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of
* filter_xl_conf_ois in reg CTRL3_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_aux_xl_bandwidth_set(stmdev_ctx_t *ctx,
- lsm6dsox_filter_xl_conf_ois_t val)
+ lsm6dsox_filter_xl_conf_ois_t val)
{
lsm6dsox_ui_ctrl3_ois_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.filter_xl_conf_ois = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3524,45 +4372,56 @@ int32_t lsm6dsox_aux_xl_bandwidth_set(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val Get the values of
* filter_xl_conf_ois in reg CTRL3_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_aux_xl_bandwidth_get(stmdev_ctx_t *ctx,
- lsm6dsox_filter_xl_conf_ois_t *val)
+ lsm6dsox_filter_xl_conf_ois_t *val)
{
lsm6dsox_ui_ctrl3_ois_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t *)®, 1);
- switch (reg.filter_xl_conf_ois) {
+ switch (reg.filter_xl_conf_ois)
+ {
case LSM6DSOX_289Hz:
*val = LSM6DSOX_289Hz;
break;
+
case LSM6DSOX_258Hz:
*val = LSM6DSOX_258Hz;
break;
+
case LSM6DSOX_120Hz:
*val = LSM6DSOX_120Hz;
break;
+
case LSM6DSOX_65Hz2:
*val = LSM6DSOX_65Hz2;
break;
+
case LSM6DSOX_33Hz2:
*val = LSM6DSOX_33Hz2;
break;
+
case LSM6DSOX_16Hz6:
*val = LSM6DSOX_16Hz6;
break;
+
case LSM6DSOX_8Hz30:
*val = LSM6DSOX_8Hz30;
break;
+
case LSM6DSOX_4Hz15:
*val = LSM6DSOX_4Hz15;
break;
+
default:
*val = LSM6DSOX_289Hz;
break;
}
+
return ret;
}
@@ -3572,19 +4431,23 @@ int32_t lsm6dsox_aux_xl_bandwidth_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of fs_xl_ois in
* reg CTRL3_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_aux_xl_full_scale_set(stmdev_ctx_t *ctx,
- lsm6dsox_fs_xl_ois_t val)
+ lsm6dsox_fs_xl_ois_t val)
{
lsm6dsox_ui_ctrl3_ois_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.fs_xl_ois = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3593,32 +4456,40 @@ int32_t lsm6dsox_aux_xl_full_scale_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of fs_xl_ois in reg CTRL3_OIS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_aux_xl_full_scale_get(stmdev_ctx_t *ctx,
- lsm6dsox_fs_xl_ois_t *val)
+ lsm6dsox_fs_xl_ois_t *val)
{
lsm6dsox_ui_ctrl3_ois_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)®, 1);
- switch (reg.fs_xl_ois) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t *)®, 1);
+
+ switch (reg.fs_xl_ois)
+ {
case LSM6DSOX_AUX_2g:
*val = LSM6DSOX_AUX_2g;
break;
+
case LSM6DSOX_AUX_16g:
*val = LSM6DSOX_AUX_16g;
break;
+
case LSM6DSOX_AUX_4g:
*val = LSM6DSOX_AUX_4g;
break;
+
case LSM6DSOX_AUX_8g:
*val = LSM6DSOX_AUX_8g;
break;
+
default:
*val = LSM6DSOX_AUX_2g;
break;
}
+
return ret;
}
@@ -3641,18 +4512,23 @@ int32_t lsm6dsox_aux_xl_full_scale_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of sdo_pu_en in
* reg PIN_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_sdo_sa0_mode_set(stmdev_ctx_t *ctx, lsm6dsox_sdo_pu_en_t val)
+int32_t lsm6dsox_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsox_sdo_pu_en_t val)
{
lsm6dsox_pin_ctrl_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.sdo_pu_en = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3661,25 +4537,32 @@ int32_t lsm6dsox_sdo_sa0_mode_set(stmdev_ctx_t *ctx, lsm6dsox_sdo_pu_en_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of sdo_pu_en in reg PIN_CTRL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_sdo_sa0_mode_get(stmdev_ctx_t *ctx, lsm6dsox_sdo_pu_en_t *val)
+int32_t lsm6dsox_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsox_sdo_pu_en_t *val)
{
lsm6dsox_pin_ctrl_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)®, 1);
- switch (reg.sdo_pu_en) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t *)®, 1);
+
+ switch (reg.sdo_pu_en)
+ {
case LSM6DSOX_PULL_UP_DISC:
*val = LSM6DSOX_PULL_UP_DISC;
break;
+
case LSM6DSOX_PULL_UP_CONNECT:
*val = LSM6DSOX_PULL_UP_CONNECT;
break;
+
default:
*val = LSM6DSOX_PULL_UP_DISC;
break;
}
+
return ret;
}
@@ -3688,6 +4571,7 @@ int32_t lsm6dsox_sdo_sa0_mode_get(stmdev_ctx_t *ctx, lsm6dsox_sdo_pu_en_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of sim in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsox_sim_t val)
@@ -3695,11 +4579,14 @@ int32_t lsm6dsox_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsox_sim_t val)
lsm6dsox_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.sim = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3708,6 +4595,7 @@ int32_t lsm6dsox_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsox_sim_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of sim in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsox_sim_t *val)
@@ -3715,18 +4603,23 @@ int32_t lsm6dsox_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsox_sim_t *val)
lsm6dsox_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1);
- switch (reg.sim) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
+
+ switch (reg.sim)
+ {
case LSM6DSOX_SPI_4_WIRE:
*val = LSM6DSOX_SPI_4_WIRE;
break;
+
case LSM6DSOX_SPI_3_WIRE:
*val = LSM6DSOX_SPI_3_WIRE;
break;
+
default:
*val = LSM6DSOX_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -3736,19 +4629,23 @@ int32_t lsm6dsox_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsox_sim_t *val)
* @param ctx read / write interface definitions
* @param val change the values of i2c_disable in
* reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_i2c_interface_set(stmdev_ctx_t *ctx,
- lsm6dsox_i2c_disable_t val)
+ lsm6dsox_i2c_disable_t val)
{
lsm6dsox_ctrl4_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.i2c_disable = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -3758,26 +4655,32 @@ int32_t lsm6dsox_i2c_interface_set(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val Get the values of i2c_disable in
* reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_i2c_interface_get(stmdev_ctx_t *ctx,
- lsm6dsox_i2c_disable_t *val)
+ lsm6dsox_i2c_disable_t *val)
{
lsm6dsox_ctrl4_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1);
- switch (reg.i2c_disable) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1);
+
+ switch (reg.i2c_disable)
+ {
case LSM6DSOX_I2C_ENABLE:
*val = LSM6DSOX_I2C_ENABLE;
break;
+
case LSM6DSOX_I2C_DISABLE:
*val = LSM6DSOX_I2C_DISABLE;
break;
+
default:
*val = LSM6DSOX_I2C_ENABLE;
break;
}
+
return ret;
}
@@ -3787,28 +4690,35 @@ int32_t lsm6dsox_i2c_interface_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of i3c_disable
* in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_i3c_disable_set(stmdev_ctx_t *ctx, lsm6dsox_i3c_disable_t val)
+int32_t lsm6dsox_i3c_disable_set(stmdev_ctx_t *ctx,
+ lsm6dsox_i3c_disable_t val)
{
lsm6dsox_i3c_bus_avb_t i3c_bus_avb;
lsm6dsox_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U;
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
}
return ret;
@@ -3820,40 +4730,51 @@ int32_t lsm6dsox_i3c_disable_set(stmdev_ctx_t *ctx, lsm6dsox_i3c_disable_t val)
* @param ctx read / write interface definitions
* @param val change the values of i3c_disable in
* reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_i3c_disable_get(stmdev_ctx_t *ctx, lsm6dsox_i3c_disable_t *val)
+int32_t lsm6dsox_i3c_disable_get(stmdev_ctx_t *ctx,
+ lsm6dsox_i3c_disable_t *val)
{
lsm6dsox_ctrl9_xl_t ctrl9_xl;
lsm6dsox_i3c_bus_avb_t i3c_bus_avb;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
- switch ((ctrl9_xl.i3c_disable << 7) | i3c_bus_avb.i3c_bus_avb_sel) {
+ switch ((ctrl9_xl.i3c_disable << 7) | i3c_bus_avb.i3c_bus_avb_sel)
+ {
case LSM6DSOX_I3C_DISABLE:
*val = LSM6DSOX_I3C_DISABLE;
break;
+
case LSM6DSOX_I3C_ENABLE_T_50us:
*val = LSM6DSOX_I3C_ENABLE_T_50us;
break;
+
case LSM6DSOX_I3C_ENABLE_T_2us:
*val = LSM6DSOX_I3C_ENABLE_T_2us;
break;
+
case LSM6DSOX_I3C_ENABLE_T_1ms:
*val = LSM6DSOX_I3C_ENABLE_T_1ms;
break;
+
case LSM6DSOX_I3C_ENABLE_T_25ms:
*val = LSM6DSOX_I3C_ENABLE_T_25ms;
break;
+
default:
*val = LSM6DSOX_I3C_DISABLE;
break;
}
}
+
return ret;
}
@@ -3864,7 +4785,7 @@ int32_t lsm6dsox_i3c_disable_get(stmdev_ctx_t *ctx, lsm6dsox_i3c_disable_t *val)
/**
* @defgroup LSM6DSOX_interrupt_pins
- * @brief This section groups all the functions that manage interrup pins
+ * @brief This section groups all the functions that manage interrupt pins
* @{
*
*/
@@ -3874,6 +4795,7 @@ int32_t lsm6dsox_i3c_disable_get(stmdev_ctx_t *ctx, lsm6dsox_i3c_disable_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of pp_od in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsox_pp_od_t val)
@@ -3882,20 +4804,27 @@ int32_t lsm6dsox_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsox_pp_od_t val)
lsm6dsox_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.pp_od = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
}
- if (ret == 0) {
- i3c_bus_avb.pd_dis_int1 = ( (uint8_t) val & 0x02U ) >> 1;
+
+ if (ret == 0)
+ {
+ i3c_bus_avb.pd_dis_int1 = ((uint8_t) val & 0x02U) >> 1;
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
}
+
return ret;
}
@@ -3904,37 +4833,47 @@ int32_t lsm6dsox_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsox_pp_od_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of pp_od in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsox_pp_od_t *val)
+int32_t lsm6dsox_pin_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsox_pp_od_t *val)
{
lsm6dsox_i3c_bus_avb_t i3c_bus_avb;
lsm6dsox_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
}
- switch ( (i3c_bus_avb.pd_dis_int1 << 1) + ctrl3_c.pp_od) {
+ switch ((i3c_bus_avb.pd_dis_int1 << 1) + ctrl3_c.pp_od)
+ {
case LSM6DSOX_PUSH_PULL:
*val = LSM6DSOX_PUSH_PULL;
break;
+
case LSM6DSOX_OPEN_DRAIN:
*val = LSM6DSOX_OPEN_DRAIN;
break;
+
case LSM6DSOX_INT1_NOPULL_DOWN_INT2_PUSH_PULL:
*val = LSM6DSOX_INT1_NOPULL_DOWN_INT2_PUSH_PULL;
break;
+
case LSM6DSOX_INT1_NOPULL_DOWN_INT2_OPEN_DRAIN:
*val = LSM6DSOX_INT1_NOPULL_DOWN_INT2_OPEN_DRAIN;
break;
+
default:
*val = LSM6DSOX_PUSH_PULL;
break;
}
+
return ret;
}
@@ -3943,17 +4882,21 @@ int32_t lsm6dsox_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsox_pp_od_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of h_lactive in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_pin_polarity_set(stmdev_ctx_t *ctx, lsm6dsox_h_lactive_t val)
+int32_t lsm6dsox_pin_polarity_set(stmdev_ctx_t *ctx,
+ lsm6dsox_h_lactive_t val)
{
lsm6dsox_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.h_lactive = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
}
return ret;
@@ -3964,26 +4907,32 @@ int32_t lsm6dsox_pin_polarity_set(stmdev_ctx_t *ctx, lsm6dsox_h_lactive_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of h_lactive in reg CTRL3_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_pin_polarity_get(stmdev_ctx_t *ctx, lsm6dsox_h_lactive_t *val)
+int32_t lsm6dsox_pin_polarity_get(stmdev_ctx_t *ctx,
+ lsm6dsox_h_lactive_t *val)
{
lsm6dsox_ctrl3_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
- switch (reg.h_lactive) {
+ switch (reg.h_lactive)
+ {
case LSM6DSOX_ACTIVE_HIGH:
*val = LSM6DSOX_ACTIVE_HIGH;
break;
+
case LSM6DSOX_ACTIVE_LOW:
*val = LSM6DSOX_ACTIVE_LOW;
break;
+
default:
*val = LSM6DSOX_ACTIVE_HIGH;
break;
}
+
return ret;
}
@@ -3992,6 +4941,7 @@ int32_t lsm6dsox_pin_polarity_get(stmdev_ctx_t *ctx, lsm6dsox_h_lactive_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of int2_on_int1 in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -3999,10 +4949,12 @@ int32_t lsm6dsox_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_ctrl4_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.int2_on_int1 = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1);
}
return ret;
@@ -4013,6 +4965,7 @@ int32_t lsm6dsox_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of int2_on_int1 in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -4020,7 +4973,7 @@ int32_t lsm6dsox_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_ctrl4_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1);
*val = reg.int2_on_int1;
return ret;
@@ -4031,32 +4984,44 @@ int32_t lsm6dsox_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of lir in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_int_notification_set(stmdev_ctx_t *ctx, lsm6dsox_lir_t val)
+int32_t lsm6dsox_int_notification_set(stmdev_ctx_t *ctx,
+ lsm6dsox_lir_t val)
{
lsm6dsox_tap_cfg0_t tap_cfg0;
lsm6dsox_page_rw_t page_rw;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
+
+ if (ret == 0)
+ {
tap_cfg0.lir = (uint8_t)val & 0x01U;
tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0,
+ (uint8_t *) &tap_cfg0, 1);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
}
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -4068,50 +5033,68 @@ int32_t lsm6dsox_int_notification_set(stmdev_ctx_t *ctx, lsm6dsox_lir_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of lir in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_int_notification_get(stmdev_ctx_t *ctx, lsm6dsox_lir_t *val)
+int32_t lsm6dsox_int_notification_get(stmdev_ctx_t *ctx,
+ lsm6dsox_lir_t *val)
{
lsm6dsox_tap_cfg0_t tap_cfg0;
lsm6dsox_page_rw_t page_rw;
int32_t ret;
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
- if (ret == 0) {
-
- ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
+ if (ret == 0)
+ {
+ ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
}
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
- if (ret == 0) {
- switch ((page_rw.emb_func_lir << 1) | tap_cfg0.lir) {
+
+ if (ret == 0)
+ {
+ switch ((page_rw.emb_func_lir << 1) | tap_cfg0.lir)
+ {
case LSM6DSOX_ALL_INT_PULSED:
*val = LSM6DSOX_ALL_INT_PULSED;
break;
+
case LSM6DSOX_BASE_LATCHED_EMB_PULSED:
*val = LSM6DSOX_BASE_LATCHED_EMB_PULSED;
break;
+
case LSM6DSOX_BASE_PULSED_EMB_LATCHED:
*val = LSM6DSOX_BASE_PULSED_EMB_LATCHED;
break;
+
case LSM6DSOX_ALL_INT_LATCHED:
*val = LSM6DSOX_ALL_INT_LATCHED;
break;
+
default:
*val = LSM6DSOX_ALL_INT_PULSED;
break;
}
+
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
}
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -4139,19 +5122,23 @@ int32_t lsm6dsox_int_notification_get(stmdev_ctx_t *ctx, lsm6dsox_lir_t *val)
* @param ctx read / write interface definitions
* @param val change the values of wake_ths_w in
* reg WAKE_UP_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_wkup_ths_weight_set(stmdev_ctx_t *ctx,
- lsm6dsox_wake_ths_w_t val)
+ lsm6dsox_wake_ths_w_t val)
{
lsm6dsox_wake_up_dur_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.wake_ths_w = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4163,27 +5150,32 @@ int32_t lsm6dsox_wkup_ths_weight_set(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val Get the values of wake_ths_w in
* reg WAKE_UP_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_wkup_ths_weight_get(stmdev_ctx_t *ctx,
- lsm6dsox_wake_ths_w_t *val)
+ lsm6dsox_wake_ths_w_t *val)
{
lsm6dsox_wake_up_dur_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t *)®, 1);
- switch (reg.wake_ths_w) {
+ switch (reg.wake_ths_w)
+ {
case LSM6DSOX_LSb_FS_DIV_64:
*val = LSM6DSOX_LSb_FS_DIV_64;
break;
+
case LSM6DSOX_LSb_FS_DIV_256:
*val = LSM6DSOX_LSb_FS_DIV_256;
break;
+
default:
*val = LSM6DSOX_LSb_FS_DIV_64;
break;
}
+
return ret;
}
@@ -4193,6 +5185,7 @@ int32_t lsm6dsox_wkup_ths_weight_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of wk_ths in reg WAKE_UP_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -4200,11 +5193,14 @@ int32_t lsm6dsox_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_wake_up_ths_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.wk_ths = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4214,6 +5210,7 @@ int32_t lsm6dsox_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of wk_ths in reg WAKE_UP_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -4221,7 +5218,7 @@ int32_t lsm6dsox_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_wake_up_ths_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t *)®, 1);
*val = reg.wk_ths;
return ret;
@@ -4233,18 +5230,23 @@ int32_t lsm6dsox_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of usr_off_on_wu in reg WAKE_UP_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dsox_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dsox_wake_up_ths_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.usr_off_on_wu = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4254,14 +5256,16 @@ int32_t lsm6dsox_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of usr_off_on_wu in reg WAKE_UP_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsox_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsox_wake_up_ths_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t *)®, 1);
*val = reg.usr_off_on_wu;
return ret;
@@ -4273,6 +5277,7 @@ int32_t lsm6dsox_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of wake_dur in reg WAKE_UP_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -4280,11 +5285,14 @@ int32_t lsm6dsox_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_wake_up_dur_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.wake_dur = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4294,6 +5302,7 @@ int32_t lsm6dsox_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of wake_dur in reg WAKE_UP_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -4301,7 +5310,7 @@ int32_t lsm6dsox_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_wake_up_dur_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t *)®, 1);
*val = reg.wake_dur;
return ret;
@@ -4325,6 +5334,7 @@ int32_t lsm6dsox_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of sleep_g in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -4332,11 +5342,14 @@ int32_t lsm6dsox_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_ctrl4_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.sleep_g = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4345,6 +5358,7 @@ int32_t lsm6dsox_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of sleep_g in reg CTRL4_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -4352,7 +5366,7 @@ int32_t lsm6dsox_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_ctrl4_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1);
*val = reg.sleep_g;
return ret;
@@ -4366,19 +5380,23 @@ int32_t lsm6dsox_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of sleep_status_on_int in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_act_pin_notification_set(stmdev_ctx_t *ctx,
- lsm6dsox_sleep_status_on_int_t val)
+ lsm6dsox_sleep_status_on_int_t val)
{
lsm6dsox_tap_cfg0_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.sleep_status_on_int = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4390,26 +5408,32 @@ int32_t lsm6dsox_act_pin_notification_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of sleep_status_on_int in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_act_pin_notification_get(stmdev_ctx_t *ctx,
- lsm6dsox_sleep_status_on_int_t *val)
+ lsm6dsox_sleep_status_on_int_t *val)
{
lsm6dsox_tap_cfg0_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1);
- switch (reg.sleep_status_on_int) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1);
+
+ switch (reg.sleep_status_on_int)
+ {
case LSM6DSOX_DRIVE_SLEEP_CHG_EVENT:
*val = LSM6DSOX_DRIVE_SLEEP_CHG_EVENT;
break;
+
case LSM6DSOX_DRIVE_SLEEP_STATUS:
*val = LSM6DSOX_DRIVE_SLEEP_STATUS;
break;
+
default:
*val = LSM6DSOX_DRIVE_SLEEP_CHG_EVENT;
break;
}
+
return ret;
}
@@ -4418,18 +5442,23 @@ int32_t lsm6dsox_act_pin_notification_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of inact_en in reg TAP_CFG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_act_mode_set(stmdev_ctx_t *ctx, lsm6dsox_inact_en_t val)
+int32_t lsm6dsox_act_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsox_inact_en_t val)
{
lsm6dsox_tap_cfg2_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.inact_en = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4438,31 +5467,40 @@ int32_t lsm6dsox_act_mode_set(stmdev_ctx_t *ctx, lsm6dsox_inact_en_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of inact_en in reg TAP_CFG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_act_mode_get(stmdev_ctx_t *ctx, lsm6dsox_inact_en_t *val)
+int32_t lsm6dsox_act_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsox_inact_en_t *val)
{
lsm6dsox_tap_cfg2_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*)®, 1);
- switch (reg.inact_en) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t *)®, 1);
+
+ switch (reg.inact_en)
+ {
case LSM6DSOX_XL_AND_GY_NOT_AFFECTED:
*val = LSM6DSOX_XL_AND_GY_NOT_AFFECTED;
break;
+
case LSM6DSOX_XL_12Hz5_GY_NOT_AFFECTED:
*val = LSM6DSOX_XL_12Hz5_GY_NOT_AFFECTED;
break;
+
case LSM6DSOX_XL_12Hz5_GY_SLEEP:
*val = LSM6DSOX_XL_12Hz5_GY_SLEEP;
break;
+
case LSM6DSOX_XL_12Hz5_GY_PD:
*val = LSM6DSOX_XL_12Hz5_GY_PD;
break;
+
default:
*val = LSM6DSOX_XL_AND_GY_NOT_AFFECTED;
break;
}
+
return ret;
}
@@ -4472,6 +5510,7 @@ int32_t lsm6dsox_act_mode_get(stmdev_ctx_t *ctx, lsm6dsox_inact_en_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of sleep_dur in reg WAKE_UP_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -4479,11 +5518,14 @@ int32_t lsm6dsox_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_wake_up_dur_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.sleep_dur = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4493,6 +5535,7 @@ int32_t lsm6dsox_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of sleep_dur in reg WAKE_UP_DUR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -4500,7 +5543,7 @@ int32_t lsm6dsox_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_wake_up_dur_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t *)®, 1);
*val = reg.sleep_dur;
return ret;
@@ -4524,18 +5567,23 @@ int32_t lsm6dsox_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_z_en in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dsox_tap_detection_on_z_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dsox_tap_cfg0_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.tap_z_en = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4544,14 +5592,16 @@ int32_t lsm6dsox_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_z_en in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsox_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsox_tap_cfg0_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1);
*val = reg.tap_z_en;
return ret;
@@ -4562,18 +5612,23 @@ int32_t lsm6dsox_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_y_en in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dsox_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dsox_tap_cfg0_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.tap_y_en = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4582,14 +5637,16 @@ int32_t lsm6dsox_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_y_en in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsox_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsox_tap_cfg0_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1);
*val = reg.tap_y_en;
return ret;
@@ -4600,18 +5657,23 @@ int32_t lsm6dsox_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_x_en in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dsox_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dsox_tap_cfg0_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.tap_x_en = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4620,14 +5682,16 @@ int32_t lsm6dsox_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_x_en in reg TAP_CFG0
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsox_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsox_tap_cfg0_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1);
*val = reg.tap_x_en;
return ret;
@@ -4638,6 +5702,7 @@ int32_t lsm6dsox_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_ths_x in reg TAP_CFG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -4645,11 +5710,14 @@ int32_t lsm6dsox_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_tap_cfg1_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.tap_ths_x = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4658,6 +5726,7 @@ int32_t lsm6dsox_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_ths_x in reg TAP_CFG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -4665,7 +5734,7 @@ int32_t lsm6dsox_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_tap_cfg1_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t *)®, 1);
*val = reg.tap_ths_x;
return ret;
@@ -4677,19 +5746,23 @@ int32_t lsm6dsox_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
* @param ctx read / write interface definitions
* @param val change the values of tap_priority in
* reg TAP_CFG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_tap_axis_priority_set(stmdev_ctx_t *ctx,
- lsm6dsox_tap_priority_t val)
+ lsm6dsox_tap_priority_t val)
{
lsm6dsox_tap_cfg1_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.tap_priority = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4699,38 +5772,48 @@ int32_t lsm6dsox_tap_axis_priority_set(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val Get the values of tap_priority in
* reg TAP_CFG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_tap_axis_priority_get(stmdev_ctx_t *ctx,
- lsm6dsox_tap_priority_t *val)
+ lsm6dsox_tap_priority_t *val)
{
lsm6dsox_tap_cfg1_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t*)®, 1);
- switch (reg.tap_priority) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t *)®, 1);
+
+ switch (reg.tap_priority)
+ {
case LSM6DSOX_XYZ:
*val = LSM6DSOX_XYZ;
break;
+
case LSM6DSOX_YXZ:
*val = LSM6DSOX_YXZ;
break;
+
case LSM6DSOX_XZY:
*val = LSM6DSOX_XZY;
break;
+
case LSM6DSOX_ZYX:
*val = LSM6DSOX_ZYX;
break;
+
case LSM6DSOX_YZX:
*val = LSM6DSOX_YZX;
break;
+
case LSM6DSOX_ZXY:
*val = LSM6DSOX_ZXY;
break;
+
default:
*val = LSM6DSOX_XYZ;
break;
}
+
return ret;
}
@@ -4739,6 +5822,7 @@ int32_t lsm6dsox_tap_axis_priority_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of tap_ths_y in reg TAP_CFG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -4746,11 +5830,14 @@ int32_t lsm6dsox_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_tap_cfg2_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.tap_ths_y = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4759,6 +5846,7 @@ int32_t lsm6dsox_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_ths_y in reg TAP_CFG2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -4766,7 +5854,7 @@ int32_t lsm6dsox_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_tap_cfg2_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t *)®, 1);
*val = reg.tap_ths_y;
return ret;
@@ -4777,6 +5865,7 @@ int32_t lsm6dsox_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_ths_z in reg TAP_THS_6D
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -4784,11 +5873,14 @@ int32_t lsm6dsox_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_tap_ths_6d_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.tap_ths_z = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4797,6 +5889,7 @@ int32_t lsm6dsox_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of tap_ths_z in reg TAP_THS_6D
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -4804,7 +5897,7 @@ int32_t lsm6dsox_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_tap_ths_6d_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t *)®, 1);
*val = reg.tap_ths_z;
return ret;
@@ -4820,6 +5913,7 @@ int32_t lsm6dsox_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of shock in reg INT_DUR2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -4827,11 +5921,14 @@ int32_t lsm6dsox_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_int_dur2_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.shock = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4845,6 +5942,7 @@ int32_t lsm6dsox_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of shock in reg INT_DUR2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -4852,7 +5950,7 @@ int32_t lsm6dsox_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_int_dur2_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t *)®, 1);
*val = reg.shock;
return ret;
@@ -4869,6 +5967,7 @@ int32_t lsm6dsox_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of quiet in reg INT_DUR2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -4876,11 +5975,14 @@ int32_t lsm6dsox_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_int_dur2_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.quiet = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4895,6 +5997,7 @@ int32_t lsm6dsox_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of quiet in reg INT_DUR2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -4902,7 +6005,7 @@ int32_t lsm6dsox_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_int_dur2_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t *)®, 1);
*val = reg.quiet;
return ret;
@@ -4920,6 +6023,7 @@ int32_t lsm6dsox_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of dur in reg INT_DUR2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -4927,11 +6031,14 @@ int32_t lsm6dsox_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_int_dur2_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.dur = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4947,6 +6054,7 @@ int32_t lsm6dsox_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of dur in reg INT_DUR2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -4954,7 +6062,7 @@ int32_t lsm6dsox_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_int_dur2_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t *)®, 1);
*val = reg.dur;
return ret;
@@ -4965,19 +6073,23 @@ int32_t lsm6dsox_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of single_double_tap in reg WAKE_UP_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_tap_mode_set(stmdev_ctx_t *ctx,
- lsm6dsox_single_double_tap_t val)
+ lsm6dsox_single_double_tap_t val)
{
lsm6dsox_wake_up_ths_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.single_double_tap = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -4986,23 +6098,27 @@ int32_t lsm6dsox_tap_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of single_double_tap in reg WAKE_UP_THS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_tap_mode_get(stmdev_ctx_t *ctx,
- lsm6dsox_single_double_tap_t *val)
+ lsm6dsox_single_double_tap_t *val)
{
lsm6dsox_wake_up_ths_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t *)®, 1);
- switch (reg.single_double_tap) {
+ switch (reg.single_double_tap)
+ {
case LSM6DSOX_ONLY_SINGLE:
*val = LSM6DSOX_ONLY_SINGLE;
break;
+
case LSM6DSOX_BOTH_SINGLE_DOUBLE:
*val = LSM6DSOX_BOTH_SINGLE_DOUBLE;
break;
+
default:
*val = LSM6DSOX_ONLY_SINGLE;
break;
@@ -5029,18 +6145,23 @@ int32_t lsm6dsox_tap_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of sixd_ths in reg TAP_THS_6D
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_6d_threshold_set(stmdev_ctx_t *ctx, lsm6dsox_sixd_ths_t val)
+int32_t lsm6dsox_6d_threshold_set(stmdev_ctx_t *ctx,
+ lsm6dsox_sixd_ths_t val)
{
lsm6dsox_tap_ths_6d_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.sixd_ths = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -5049,31 +6170,40 @@ int32_t lsm6dsox_6d_threshold_set(stmdev_ctx_t *ctx, lsm6dsox_sixd_ths_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of sixd_ths in reg TAP_THS_6D
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_6d_threshold_get(stmdev_ctx_t *ctx, lsm6dsox_sixd_ths_t *val)
+int32_t lsm6dsox_6d_threshold_get(stmdev_ctx_t *ctx,
+ lsm6dsox_sixd_ths_t *val)
{
lsm6dsox_tap_ths_6d_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)®, 1);
- switch (reg.sixd_ths) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t *)®, 1);
+
+ switch (reg.sixd_ths)
+ {
case LSM6DSOX_DEG_80:
*val = LSM6DSOX_DEG_80;
break;
+
case LSM6DSOX_DEG_70:
*val = LSM6DSOX_DEG_70;
break;
+
case LSM6DSOX_DEG_60:
*val = LSM6DSOX_DEG_60;
break;
+
case LSM6DSOX_DEG_50:
*val = LSM6DSOX_DEG_50;
break;
+
default:
*val = LSM6DSOX_DEG_80;
break;
}
+
return ret;
}
@@ -5082,6 +6212,7 @@ int32_t lsm6dsox_6d_threshold_get(stmdev_ctx_t *ctx, lsm6dsox_sixd_ths_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of d4d_en in reg TAP_THS_6D
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -5089,11 +6220,14 @@ int32_t lsm6dsox_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_tap_ths_6d_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.d4d_en = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -5102,6 +6236,7 @@ int32_t lsm6dsox_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of d4d_en in reg TAP_THS_6D
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -5109,7 +6244,7 @@ int32_t lsm6dsox_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_tap_ths_6d_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t *)®, 1);
*val = reg.d4d_en;
return ret;
@@ -5126,24 +6261,29 @@ int32_t lsm6dsox_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
* fall detection.
* @{
*
-*/
+ */
/**
* @brief Free fall threshold setting.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of ff_ths in reg FREE_FALL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_ff_threshold_set(stmdev_ctx_t *ctx, lsm6dsox_ff_ths_t val)
+int32_t lsm6dsox_ff_threshold_set(stmdev_ctx_t *ctx,
+ lsm6dsox_ff_ths_t val)
{
lsm6dsox_free_fall_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.ff_ths = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -5152,43 +6292,56 @@ int32_t lsm6dsox_ff_threshold_set(stmdev_ctx_t *ctx, lsm6dsox_ff_ths_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of ff_ths in reg FREE_FALL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_ff_threshold_get(stmdev_ctx_t *ctx, lsm6dsox_ff_ths_t *val)
+int32_t lsm6dsox_ff_threshold_get(stmdev_ctx_t *ctx,
+ lsm6dsox_ff_ths_t *val)
{
lsm6dsox_free_fall_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t*)®, 1);
- switch (reg.ff_ths) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t *)®, 1);
+
+ switch (reg.ff_ths)
+ {
case LSM6DSOX_FF_TSH_156mg:
*val = LSM6DSOX_FF_TSH_156mg;
break;
+
case LSM6DSOX_FF_TSH_219mg:
*val = LSM6DSOX_FF_TSH_219mg;
break;
+
case LSM6DSOX_FF_TSH_250mg:
*val = LSM6DSOX_FF_TSH_250mg;
break;
+
case LSM6DSOX_FF_TSH_312mg:
*val = LSM6DSOX_FF_TSH_312mg;
break;
+
case LSM6DSOX_FF_TSH_344mg:
*val = LSM6DSOX_FF_TSH_344mg;
break;
+
case LSM6DSOX_FF_TSH_406mg:
*val = LSM6DSOX_FF_TSH_406mg;
break;
+
case LSM6DSOX_FF_TSH_469mg:
*val = LSM6DSOX_FF_TSH_469mg;
break;
+
case LSM6DSOX_FF_TSH_500mg:
*val = LSM6DSOX_FF_TSH_500mg;
break;
+
default:
*val = LSM6DSOX_FF_TSH_156mg;
break;
}
+
return ret;
}
@@ -5198,6 +6351,7 @@ int32_t lsm6dsox_ff_threshold_get(stmdev_ctx_t *ctx, lsm6dsox_ff_ths_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of ff_dur in reg FREE_FALL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -5206,19 +6360,29 @@ int32_t lsm6dsox_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_free_fall_t free_fall;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t*)&free_fall, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL,
+ (uint8_t *)&free_fall, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5;
free_fall.ff_dur = (uint8_t)val & 0x1FU;
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
- if (ret == 0) {
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t*)&free_fall, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FREE_FALL,
+ (uint8_t *)&free_fall, 1);
}
+
return ret;
}
@@ -5228,6 +6392,7 @@ int32_t lsm6dsox_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of ff_dur in reg FREE_FALL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -5236,11 +6401,16 @@ int32_t lsm6dsox_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_free_fall_t free_fall;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t*)&free_fall, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR,
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL,
+ (uint8_t *)&free_fall, 1);
*val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
}
+
return ret;
}
@@ -5261,6 +6431,7 @@ int32_t lsm6dsox_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of wtm in reg FIFO_CTRL1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
@@ -5269,15 +6440,23 @@ int32_t lsm6dsox_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
lsm6dsox_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl1.wtm = 0x00FFU & (uint8_t)val;
- fifo_ctrl2.wtm = (uint8_t)(( 0x0100U & val ) >> 8);
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1);
+ fifo_ctrl2.wtm = (uint8_t)((0x0100U & val) >> 8);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL1,
+ (uint8_t *)&fifo_ctrl1, 1);
}
- if (ret == 0) {
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
}
+
return ret;
}
@@ -5286,6 +6465,7 @@ int32_t lsm6dsox_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of wtm in reg FIFO_CTRL1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
@@ -5294,11 +6474,16 @@ int32_t lsm6dsox_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
lsm6dsox_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL1,
+ (uint8_t *)&fifo_ctrl1, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
*val = ((uint16_t)fifo_ctrl2.wtm << 8) + (uint16_t)fifo_ctrl1.wtm;
}
+
return ret;
}
@@ -5308,22 +6493,32 @@ int32_t lsm6dsox_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
* @param ctx read / write interface definitions
* @param val change the values of FIFO_COMPR_INIT in
* reg EMB_FUNC_INIT_B
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_compression_algo_init_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dsox_compression_algo_init_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dsox_emb_func_init_b_t reg;
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.fifo_compr_init = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -5336,18 +6531,25 @@ int32_t lsm6dsox_compression_algo_init_set(stmdev_ctx_t *ctx, uint8_t val)
* @param ctx read / write interface definitions
* @param val change the values of FIFO_COMPR_INIT in
* reg EMB_FUNC_INIT_B
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_compression_algo_init_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsox_compression_algo_init_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsox_emb_func_init_b_t reg;
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.fifo_compr_init;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -5361,39 +6563,26 @@ int32_t lsm6dsox_compression_algo_init_get(stmdev_ctx_t *ctx, uint8_t *val)
* @param ctx read / write interface definitions
* @param val change the values of uncoptr_rate in
* reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_compression_algo_set(stmdev_ctx_t *ctx,
- lsm6dsox_uncoptr_rate_t val)
+ lsm6dsox_uncoptr_rate_t val)
{
- lsm6dsox_emb_func_en_b_t emb_func_en_b;
lsm6dsox_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
- ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
- }
- if (ret == 0) {
- emb_func_en_b.fifo_compr_en = ((uint8_t)val & 0x04U) >> 2;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
- }
- if (ret == 0) {
- ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
- }
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2,
+ (uint8_t *)&fifo_ctrl2, 1);
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- }
- if (ret == 0) {
+ if (ret == 0)
+ {
fifo_ctrl2.fifo_compr_rt_en = ((uint8_t)val & 0x04U) >> 2;
fifo_ctrl2.uncoptr_rate = (uint8_t)val & 0x03U;
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
+
return ret;
}
@@ -5403,36 +6592,44 @@ int32_t lsm6dsox_compression_algo_set(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val Get the values of uncoptr_rate in
* reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_compression_algo_get(stmdev_ctx_t *ctx,
- lsm6dsox_uncoptr_rate_t *val)
+ lsm6dsox_uncoptr_rate_t *val)
{
lsm6dsox_fifo_ctrl2_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t *)®, 1);
- switch ((reg.fifo_compr_rt_en<<2) | reg.uncoptr_rate) {
+ switch ((reg.fifo_compr_rt_en << 2) | reg.uncoptr_rate)
+ {
case LSM6DSOX_CMP_DISABLE:
*val = LSM6DSOX_CMP_DISABLE;
break;
+
case LSM6DSOX_CMP_ALWAYS:
*val = LSM6DSOX_CMP_ALWAYS;
break;
+
case LSM6DSOX_CMP_8_TO_1:
*val = LSM6DSOX_CMP_8_TO_1;
break;
+
case LSM6DSOX_CMP_16_TO_1:
*val = LSM6DSOX_CMP_16_TO_1;
break;
+
case LSM6DSOX_CMP_32_TO_1:
*val = LSM6DSOX_CMP_32_TO_1;
break;
+
default:
*val = LSM6DSOX_CMP_DISABLE;
break;
}
+
return ret;
}
@@ -5441,19 +6638,23 @@ int32_t lsm6dsox_compression_algo_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of odrchg_en in reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
- uint8_t val)
+ uint8_t val)
{
lsm6dsox_fifo_ctrl2_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.odrchg_en = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -5462,15 +6663,16 @@ int32_t lsm6dsox_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of odrchg_en in reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
lsm6dsox_fifo_ctrl2_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t *)®, 1);
*val = reg.odrchg_en;
return ret;
@@ -5482,19 +6684,23 @@ int32_t lsm6dsox_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of fifo_compr_rt_en in
* reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_compression_algo_real_time_set(stmdev_ctx_t *ctx,
- uint8_t val)
+ uint8_t val)
{
lsm6dsox_fifo_ctrl2_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.fifo_compr_rt_en = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -5503,15 +6709,16 @@ int32_t lsm6dsox_compression_algo_real_time_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of fifo_compr_rt_en in reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_compression_algo_real_time_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
lsm6dsox_fifo_ctrl2_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t *)®, 1);
*val = reg.fifo_compr_rt_en;
return ret;
@@ -5523,6 +6730,7 @@ int32_t lsm6dsox_compression_algo_real_time_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of stop_on_wtm in reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -5530,11 +6738,14 @@ int32_t lsm6dsox_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_fifo_ctrl2_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.stop_on_wtm = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -5544,6 +6755,7 @@ int32_t lsm6dsox_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of stop_on_wtm in reg FIFO_CTRL2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -5551,7 +6763,7 @@ int32_t lsm6dsox_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_fifo_ctrl2_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t *)®, 1);
*val = reg.stop_on_wtm;
return ret;
@@ -5563,18 +6775,23 @@ int32_t lsm6dsox_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of bdr_xl in reg FIFO_CTRL3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_fifo_xl_batch_set(stmdev_ctx_t *ctx, lsm6dsox_bdr_xl_t val)
+int32_t lsm6dsox_fifo_xl_batch_set(stmdev_ctx_t *ctx,
+ lsm6dsox_bdr_xl_t val)
{
lsm6dsox_fifo_ctrl3_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.bdr_xl = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -5584,51 +6801,67 @@ int32_t lsm6dsox_fifo_xl_batch_set(stmdev_ctx_t *ctx, lsm6dsox_bdr_xl_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of bdr_xl in reg FIFO_CTRL3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_fifo_xl_batch_get(stmdev_ctx_t *ctx, lsm6dsox_bdr_xl_t *val)
+int32_t lsm6dsox_fifo_xl_batch_get(stmdev_ctx_t *ctx,
+ lsm6dsox_bdr_xl_t *val)
{
lsm6dsox_fifo_ctrl3_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t*)®, 1);
- switch (reg.bdr_xl) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t *)®, 1);
+
+ switch (reg.bdr_xl)
+ {
case LSM6DSOX_XL_NOT_BATCHED:
*val = LSM6DSOX_XL_NOT_BATCHED;
break;
+
case LSM6DSOX_XL_BATCHED_AT_12Hz5:
*val = LSM6DSOX_XL_BATCHED_AT_12Hz5;
break;
+
case LSM6DSOX_XL_BATCHED_AT_26Hz:
*val = LSM6DSOX_XL_BATCHED_AT_26Hz;
break;
+
case LSM6DSOX_XL_BATCHED_AT_52Hz:
*val = LSM6DSOX_XL_BATCHED_AT_52Hz;
break;
+
case LSM6DSOX_XL_BATCHED_AT_104Hz:
*val = LSM6DSOX_XL_BATCHED_AT_104Hz;
break;
+
case LSM6DSOX_XL_BATCHED_AT_208Hz:
*val = LSM6DSOX_XL_BATCHED_AT_208Hz;
break;
+
case LSM6DSOX_XL_BATCHED_AT_417Hz:
*val = LSM6DSOX_XL_BATCHED_AT_417Hz;
break;
+
case LSM6DSOX_XL_BATCHED_AT_833Hz:
*val = LSM6DSOX_XL_BATCHED_AT_833Hz;
break;
+
case LSM6DSOX_XL_BATCHED_AT_1667Hz:
*val = LSM6DSOX_XL_BATCHED_AT_1667Hz;
break;
+
case LSM6DSOX_XL_BATCHED_AT_3333Hz:
*val = LSM6DSOX_XL_BATCHED_AT_3333Hz;
break;
+
case LSM6DSOX_XL_BATCHED_AT_6667Hz:
*val = LSM6DSOX_XL_BATCHED_AT_6667Hz;
break;
+
case LSM6DSOX_XL_BATCHED_AT_6Hz5:
*val = LSM6DSOX_XL_BATCHED_AT_6Hz5;
break;
+
default:
*val = LSM6DSOX_XL_NOT_BATCHED;
break;
@@ -5643,18 +6876,23 @@ int32_t lsm6dsox_fifo_xl_batch_get(stmdev_ctx_t *ctx, lsm6dsox_bdr_xl_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of bdr_gy in reg FIFO_CTRL3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_fifo_gy_batch_set(stmdev_ctx_t *ctx, lsm6dsox_bdr_gy_t val)
+int32_t lsm6dsox_fifo_gy_batch_set(stmdev_ctx_t *ctx,
+ lsm6dsox_bdr_gy_t val)
{
lsm6dsox_fifo_ctrl3_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.bdr_gy = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -5664,55 +6902,72 @@ int32_t lsm6dsox_fifo_gy_batch_set(stmdev_ctx_t *ctx, lsm6dsox_bdr_gy_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of bdr_gy in reg FIFO_CTRL3
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_fifo_gy_batch_get(stmdev_ctx_t *ctx, lsm6dsox_bdr_gy_t *val)
+int32_t lsm6dsox_fifo_gy_batch_get(stmdev_ctx_t *ctx,
+ lsm6dsox_bdr_gy_t *val)
{
lsm6dsox_fifo_ctrl3_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t*)®, 1);
- switch (reg.bdr_gy) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t *)®, 1);
+
+ switch (reg.bdr_gy)
+ {
case LSM6DSOX_GY_NOT_BATCHED:
*val = LSM6DSOX_GY_NOT_BATCHED;
break;
+
case LSM6DSOX_GY_BATCHED_AT_12Hz5:
*val = LSM6DSOX_GY_BATCHED_AT_12Hz5;
break;
+
case LSM6DSOX_GY_BATCHED_AT_26Hz:
*val = LSM6DSOX_GY_BATCHED_AT_26Hz;
break;
+
case LSM6DSOX_GY_BATCHED_AT_52Hz:
*val = LSM6DSOX_GY_BATCHED_AT_52Hz;
break;
+
case LSM6DSOX_GY_BATCHED_AT_104Hz:
*val = LSM6DSOX_GY_BATCHED_AT_104Hz;
break;
+
case LSM6DSOX_GY_BATCHED_AT_208Hz:
*val = LSM6DSOX_GY_BATCHED_AT_208Hz;
break;
+
case LSM6DSOX_GY_BATCHED_AT_417Hz:
*val = LSM6DSOX_GY_BATCHED_AT_417Hz;
break;
+
case LSM6DSOX_GY_BATCHED_AT_833Hz:
*val = LSM6DSOX_GY_BATCHED_AT_833Hz;
break;
+
case LSM6DSOX_GY_BATCHED_AT_1667Hz:
*val = LSM6DSOX_GY_BATCHED_AT_1667Hz;
break;
+
case LSM6DSOX_GY_BATCHED_AT_3333Hz:
*val = LSM6DSOX_GY_BATCHED_AT_3333Hz;
break;
+
case LSM6DSOX_GY_BATCHED_AT_6667Hz:
*val = LSM6DSOX_GY_BATCHED_AT_6667Hz;
break;
+
case LSM6DSOX_GY_BATCHED_AT_6Hz5:
*val = LSM6DSOX_GY_BATCHED_AT_6Hz5;
break;
+
default:
*val = LSM6DSOX_GY_NOT_BATCHED;
break;
}
+
return ret;
}
@@ -5721,18 +6976,23 @@ int32_t lsm6dsox_fifo_gy_batch_get(stmdev_ctx_t *ctx, lsm6dsox_bdr_gy_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of fifo_mode in reg FIFO_CTRL4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_fifo_mode_set(stmdev_ctx_t *ctx, lsm6dsox_fifo_mode_t val)
+int32_t lsm6dsox_fifo_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsox_fifo_mode_t val)
{
lsm6dsox_fifo_ctrl4_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.fifo_mode = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -5741,38 +7001,48 @@ int32_t lsm6dsox_fifo_mode_set(stmdev_ctx_t *ctx, lsm6dsox_fifo_mode_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of fifo_mode in reg FIFO_CTRL4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_fifo_mode_get(stmdev_ctx_t *ctx, lsm6dsox_fifo_mode_t *val)
+int32_t lsm6dsox_fifo_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsox_fifo_mode_t *val)
{
lsm6dsox_fifo_ctrl4_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t *)®, 1);
- switch (reg.fifo_mode) {
+ switch (reg.fifo_mode)
+ {
case LSM6DSOX_BYPASS_MODE:
*val = LSM6DSOX_BYPASS_MODE;
break;
+
case LSM6DSOX_FIFO_MODE:
*val = LSM6DSOX_FIFO_MODE;
break;
+
case LSM6DSOX_STREAM_TO_FIFO_MODE:
*val = LSM6DSOX_STREAM_TO_FIFO_MODE;
break;
+
case LSM6DSOX_BYPASS_TO_STREAM_MODE:
*val = LSM6DSOX_BYPASS_TO_STREAM_MODE;
break;
+
case LSM6DSOX_STREAM_MODE:
*val = LSM6DSOX_STREAM_MODE;
break;
+
case LSM6DSOX_BYPASS_TO_FIFO_MODE:
*val = LSM6DSOX_BYPASS_TO_FIFO_MODE;
break;
+
default:
*val = LSM6DSOX_BYPASS_MODE;
break;
}
+
return ret;
}
@@ -5782,19 +7052,23 @@ int32_t lsm6dsox_fifo_mode_get(stmdev_ctx_t *ctx, lsm6dsox_fifo_mode_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of odr_t_batch in reg FIFO_CTRL4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_fifo_temp_batch_set(stmdev_ctx_t *ctx,
- lsm6dsox_odr_t_batch_t val)
+ lsm6dsox_odr_t_batch_t val)
{
lsm6dsox_fifo_ctrl4_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.odr_t_batch = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -5804,33 +7078,40 @@ int32_t lsm6dsox_fifo_temp_batch_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of odr_t_batch in reg FIFO_CTRL4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_fifo_temp_batch_get(stmdev_ctx_t *ctx,
- lsm6dsox_odr_t_batch_t *val)
+ lsm6dsox_odr_t_batch_t *val)
{
lsm6dsox_fifo_ctrl4_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t *)®, 1);
- switch (reg.odr_t_batch) {
+ switch (reg.odr_t_batch)
+ {
case LSM6DSOX_TEMP_NOT_BATCHED:
*val = LSM6DSOX_TEMP_NOT_BATCHED;
break;
+
case LSM6DSOX_TEMP_BATCHED_AT_1Hz6:
*val = LSM6DSOX_TEMP_BATCHED_AT_1Hz6;
break;
+
case LSM6DSOX_TEMP_BATCHED_AT_12Hz5:
*val = LSM6DSOX_TEMP_BATCHED_AT_12Hz5;
break;
+
case LSM6DSOX_TEMP_BATCHED_AT_52Hz:
*val = LSM6DSOX_TEMP_BATCHED_AT_52Hz;
break;
+
default:
*val = LSM6DSOX_TEMP_NOT_BATCHED;
break;
}
+
return ret;
}
@@ -5841,19 +7122,23 @@ int32_t lsm6dsox_fifo_temp_batch_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of odr_ts_batch in reg FIFO_CTRL4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
- lsm6dsox_odr_ts_batch_t val)
+ lsm6dsox_odr_ts_batch_t val)
{
lsm6dsox_fifo_ctrl4_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.odr_ts_batch = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -5864,32 +7149,40 @@ int32_t lsm6dsox_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of odr_ts_batch in reg FIFO_CTRL4
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
- lsm6dsox_odr_ts_batch_t *val)
+ lsm6dsox_odr_ts_batch_t *val)
{
lsm6dsox_fifo_ctrl4_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)®, 1);
- switch (reg.odr_ts_batch) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t *)®, 1);
+
+ switch (reg.odr_ts_batch)
+ {
case LSM6DSOX_NO_DECIMATION:
*val = LSM6DSOX_NO_DECIMATION;
break;
+
case LSM6DSOX_DEC_1:
*val = LSM6DSOX_DEC_1;
break;
+
case LSM6DSOX_DEC_8:
*val = LSM6DSOX_DEC_8;
break;
+
case LSM6DSOX_DEC_32:
*val = LSM6DSOX_DEC_32;
break;
+
default:
*val = LSM6DSOX_NO_DECIMATION;
break;
}
+
return ret;
}
@@ -5900,19 +7193,25 @@ int32_t lsm6dsox_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of trig_counter_bdr
* in reg COUNTER_BDR_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
- lsm6dsox_trig_counter_bdr_t val)
+ lsm6dsox_trig_counter_bdr_t val)
{
lsm6dsox_counter_bdr_reg1_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1,
+ (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.trig_counter_bdr = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1,
+ (uint8_t *)®, 1);
}
+
return ret;
}
@@ -5923,26 +7222,33 @@ int32_t lsm6dsox_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val Get the values of trig_counter_bdr
* in reg COUNTER_BDR_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
- lsm6dsox_trig_counter_bdr_t *val)
+ lsm6dsox_trig_counter_bdr_t *val)
{
lsm6dsox_counter_bdr_reg1_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)®, 1);
- switch (reg.trig_counter_bdr) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1,
+ (uint8_t *)®, 1);
+
+ switch (reg.trig_counter_bdr)
+ {
case LSM6DSOX_XL_BATCH_EVENT:
*val = LSM6DSOX_XL_BATCH_EVENT;
break;
+
case LSM6DSOX_GYRO_BATCH_EVENT:
*val = LSM6DSOX_GYRO_BATCH_EVENT;
break;
+
default:
*val = LSM6DSOX_XL_BATCH_EVENT;
break;
}
+
return ret;
}
@@ -5953,6 +7259,7 @@ int32_t lsm6dsox_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of rst_counter_bdr in
* reg COUNTER_BDR_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -5960,11 +7267,16 @@ int32_t lsm6dsox_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_counter_bdr_reg1_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1,
+ (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.rst_counter_bdr = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1,
+ (uint8_t *)®, 1);
}
+
return ret;
}
@@ -5975,14 +7287,17 @@ int32_t lsm6dsox_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val)
* @param ctx read / write interface definitions
* @param val change the values of rst_counter_bdr in
* reg COUNTER_BDR_REG1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsox_rst_batch_counter_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsox_counter_bdr_reg1_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1,
+ (uint8_t *)®, 1);
*val = reg.rst_counter_bdr;
return ret;
@@ -5994,26 +7309,33 @@ int32_t lsm6dsox_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val)
* @param ctx read / write interface definitions
* @param val change the values of cnt_bdr_th in
* reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_batch_counter_threshold_set(stmdev_ctx_t *ctx, uint16_t val)
+int32_t lsm6dsox_batch_counter_threshold_set(stmdev_ctx_t *ctx,
+ uint16_t val)
{
lsm6dsox_counter_bdr_reg1_t counter_bdr_reg1;
lsm6dsox_counter_bdr_reg2_t counter_bdr_reg2;
int32_t ret;
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if (ret == 0) {
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
counter_bdr_reg2.cnt_bdr_th = 0x00FFU & (uint8_t)val;
counter_bdr_reg1.cnt_bdr_th = (uint8_t)(0x0700U & val) >> 8;
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG2,
- (uint8_t*)&counter_bdr_reg2, 1);
+ (uint8_t *)&counter_bdr_reg2, 1);
}
+
return ret;
}
@@ -6023,22 +7345,25 @@ int32_t lsm6dsox_batch_counter_threshold_set(stmdev_ctx_t *ctx, uint16_t val)
* @param ctx read / write interface definitions
* @param val change the values of cnt_bdr_th in
* reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_batch_counter_threshold_get(stmdev_ctx_t *ctx, uint16_t *val)
+int32_t lsm6dsox_batch_counter_threshold_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
lsm6dsox_counter_bdr_reg1_t counter_bdr_reg1;
lsm6dsox_counter_bdr_reg2_t counter_bdr_reg2;
int32_t ret;
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG2,
- (uint8_t*)&counter_bdr_reg2, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG2,
+ (uint8_t *)&counter_bdr_reg2, 1);
*val = ((uint16_t)counter_bdr_reg1.cnt_bdr_th << 8)
- + (uint16_t)counter_bdr_reg2.cnt_bdr_th;
+ + (uint16_t)counter_bdr_reg2.cnt_bdr_th;
}
return ret;
@@ -6049,6 +7374,7 @@ int32_t lsm6dsox_batch_counter_threshold_get(stmdev_ctx_t *ctx, uint16_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of diff_fifo in reg FIFO_STATUS1
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
@@ -6058,13 +7384,16 @@ int32_t lsm6dsox_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
int32_t ret;
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS1,
- (uint8_t*)&fifo_status1, 1);
- if (ret == 0) {
+ (uint8_t *)&fifo_status1, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
+ (uint8_t *)&fifo_status2, 1);
*val = ((uint16_t)fifo_status2.diff_fifo << 8) +
- (uint16_t)fifo_status1.diff_fifo;
+ (uint16_t)fifo_status1.diff_fifo;
}
+
return ret;
}
@@ -6073,13 +7402,16 @@ int32_t lsm6dsox_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
*
* @param ctx read / write interface definitions
* @param val registers FIFO_STATUS2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_fifo_status_get(stmdev_ctx_t *ctx,
- lsm6dsox_fifo_status2_t *val)
+ lsm6dsox_fifo_status2_t *val)
{
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS2, (uint8_t*) val, 1);
+
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS2, (uint8_t *) val, 1);
+
return ret;
}
@@ -6088,6 +7420,7 @@ int32_t lsm6dsox_fifo_status_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of fifo_full_ia in reg FIFO_STATUS2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -6095,7 +7428,7 @@ int32_t lsm6dsox_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_fifo_status2_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS2, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS2, (uint8_t *)®, 1);
*val = reg.fifo_full_ia;
return ret;
@@ -6107,6 +7440,7 @@ int32_t lsm6dsox_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
* @param ctx read / write interface definitions
* @param val change the values of fifo_over_run_latched in
* reg FIFO_STATUS2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -6114,7 +7448,7 @@ int32_t lsm6dsox_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_fifo_status2_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS2, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS2, (uint8_t *)®, 1);
*val = reg.fifo_ovr_ia;
return ret;
@@ -6125,6 +7459,7 @@ int32_t lsm6dsox_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of fifo_wtm_ia in reg FIFO_STATUS2
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -6132,7 +7467,7 @@ int32_t lsm6dsox_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_fifo_status2_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS2, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS2, (uint8_t *)®, 1);
*val = reg.fifo_wtm_ia;
return ret;
@@ -6143,86 +7478,113 @@ int32_t lsm6dsox_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of tag_sensor in reg FIFO_DATA_OUT_TAG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
- lsm6dsox_fifo_tag_t *val)
+ lsm6dsox_fifo_tag_t *val)
{
lsm6dsox_fifo_data_out_tag_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_DATA_OUT_TAG, (uint8_t*)®, 1);
- switch (reg.tag_sensor) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_DATA_OUT_TAG,
+ (uint8_t *)®, 1);
+
+ switch (reg.tag_sensor)
+ {
case LSM6DSOX_GYRO_NC_TAG:
*val = LSM6DSOX_GYRO_NC_TAG;
break;
+
case LSM6DSOX_XL_NC_TAG:
*val = LSM6DSOX_XL_NC_TAG;
break;
+
case LSM6DSOX_TEMPERATURE_TAG:
*val = LSM6DSOX_TEMPERATURE_TAG;
break;
+
case LSM6DSOX_TIMESTAMP_TAG:
*val = LSM6DSOX_TIMESTAMP_TAG;
break;
+
case LSM6DSOX_CFG_CHANGE_TAG:
*val = LSM6DSOX_CFG_CHANGE_TAG;
break;
+
case LSM6DSOX_XL_NC_T_2_TAG:
*val = LSM6DSOX_XL_NC_T_2_TAG;
break;
+
case LSM6DSOX_XL_NC_T_1_TAG:
*val = LSM6DSOX_XL_NC_T_1_TAG;
break;
+
case LSM6DSOX_XL_2XC_TAG:
*val = LSM6DSOX_XL_2XC_TAG;
break;
+
case LSM6DSOX_XL_3XC_TAG:
*val = LSM6DSOX_XL_3XC_TAG;
break;
+
case LSM6DSOX_GYRO_NC_T_2_TAG:
*val = LSM6DSOX_GYRO_NC_T_2_TAG;
break;
+
case LSM6DSOX_GYRO_NC_T_1_TAG:
*val = LSM6DSOX_GYRO_NC_T_1_TAG;
break;
+
case LSM6DSOX_GYRO_2XC_TAG:
*val = LSM6DSOX_GYRO_2XC_TAG;
break;
+
case LSM6DSOX_GYRO_3XC_TAG:
*val = LSM6DSOX_GYRO_3XC_TAG;
break;
+
case LSM6DSOX_SENSORHUB_SLAVE0_TAG:
*val = LSM6DSOX_SENSORHUB_SLAVE0_TAG;
break;
+
case LSM6DSOX_SENSORHUB_SLAVE1_TAG:
*val = LSM6DSOX_SENSORHUB_SLAVE1_TAG;
break;
+
case LSM6DSOX_SENSORHUB_SLAVE2_TAG:
*val = LSM6DSOX_SENSORHUB_SLAVE2_TAG;
break;
+
case LSM6DSOX_SENSORHUB_SLAVE3_TAG:
*val = LSM6DSOX_SENSORHUB_SLAVE3_TAG;
break;
+
case LSM6DSOX_STEP_CPUNTER_TAG:
*val = LSM6DSOX_STEP_CPUNTER_TAG;
break;
+
case LSM6DSOX_GAME_ROTATION_TAG:
*val = LSM6DSOX_GAME_ROTATION_TAG;
break;
+
case LSM6DSOX_GEOMAG_ROTATION_TAG:
*val = LSM6DSOX_GEOMAG_ROTATION_TAG;
break;
+
case LSM6DSOX_ROTATION_TAG:
*val = LSM6DSOX_ROTATION_TAG;
break;
+
case LSM6DSOX_SENSORHUB_NACK_TAG:
*val = LSM6DSOX_SENSORHUB_NACK_TAG;
break;
+
default:
*val = LSM6DSOX_GYRO_NC_TAG;
break;
}
+
return ret;
}
@@ -6233,6 +7595,7 @@ int32_t lsm6dsox_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of gbias_fifo_en in
* reg LSM6DSOX_EMB_FUNC_FIFO_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -6241,17 +7604,25 @@ int32_t lsm6dsox_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_FIFO_CFG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_FIFO_CFG,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.pedo_fifo_en = val;
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_FIFO_CFG,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
+
return ret;
}
@@ -6261,6 +7632,7 @@ int32_t lsm6dsox_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val)
* @param ctx read / write interface definitions
* @param val change the values of pedo_fifo_en in
* reg LSM6DSOX_EMB_FUNC_FIFO_CFG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -6269,13 +7641,19 @@ int32_t lsm6dsox_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_FIFO_CFG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_FIFO_CFG,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.pedo_fifo_en;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
+
return ret;
}
@@ -6285,6 +7663,7 @@ int32_t lsm6dsox_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
* @param ctx read / write interface definitions
* @param val change the values of batch_ext_sens_0_en in
* reg SLV0_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -6293,16 +7672,23 @@ int32_t lsm6dsox_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.batch_ext_sens_0_en = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
+
return ret;
}
@@ -6312,6 +7698,7 @@ int32_t lsm6dsox_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val)
* @param ctx read / write interface definitions
* @param val change the values of batch_ext_sens_0_en in
* reg SLV0_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -6320,13 +7707,18 @@ int32_t lsm6dsox_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.batch_ext_sens_0_en;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
+
return ret;
}
@@ -6336,6 +7728,7 @@ int32_t lsm6dsox_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val)
* @param ctx read / write interface definitions
* @param val change the values of batch_ext_sens_1_en in
* reg SLV1_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -6344,14 +7737,20 @@ int32_t lsm6dsox_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV1_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV1_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.batch_ext_sens_1_en = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV1_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV1_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -6364,6 +7763,7 @@ int32_t lsm6dsox_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val)
* @param ctx read / write interface definitions
* @param val change the values of batch_ext_sens_1_en in
* reg SLV1_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -6372,13 +7772,18 @@ int32_t lsm6dsox_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV1_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV1_CONFIG, (uint8_t *)®, 1);
*val = reg.batch_ext_sens_1_en;
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
+
return ret;
}
@@ -6388,6 +7793,7 @@ int32_t lsm6dsox_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val)
* @param ctx read / write interface definitions
* @param val change the values of batch_ext_sens_2_en in
* reg SLV2_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -6397,16 +7803,22 @@ int32_t lsm6dsox_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val)
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV2_CONFIG, (uint8_t*)®, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV2_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.batch_ext_sens_2_en = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV2_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV2_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
+
return ret;
}
@@ -6416,6 +7828,7 @@ int32_t lsm6dsox_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val)
* @param ctx read / write interface definitions
* @param val change the values of batch_ext_sens_2_en in
* reg SLV2_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -6424,10 +7837,14 @@ int32_t lsm6dsox_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV2_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV2_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.batch_ext_sens_2_en;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -6441,6 +7858,7 @@ int32_t lsm6dsox_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val)
* @param ctx read / write interface definitions
* @param val change the values of batch_ext_sens_3_en
* in reg SLV3_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -6449,14 +7867,20 @@ int32_t lsm6dsox_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV3_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV3_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.batch_ext_sens_3_en = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV3_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV3_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -6469,6 +7893,7 @@ int32_t lsm6dsox_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val)
* @param ctx read / write interface definitions
* @param val change the values of batch_ext_sens_3_en in
* reg SLV3_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -6477,10 +7902,14 @@ int32_t lsm6dsox_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV3_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV3_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.batch_ext_sens_3_en;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -6499,24 +7928,28 @@ int32_t lsm6dsox_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val)
* DEN functionality.
* @{
*
-*/
+ */
/**
* @brief DEN functionality marking mode.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of den_mode in reg CTRL6_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_den_mode_set(stmdev_ctx_t *ctx, lsm6dsox_den_mode_t val)
+int32_t lsm6dsox_den_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsox_den_mode_t val)
{
lsm6dsox_ctrl6_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.den_mode = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t *)®, 1);
}
return ret;
@@ -6527,35 +7960,44 @@ int32_t lsm6dsox_den_mode_set(stmdev_ctx_t *ctx, lsm6dsox_den_mode_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of den_mode in reg CTRL6_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_den_mode_get(stmdev_ctx_t *ctx, lsm6dsox_den_mode_t *val)
+int32_t lsm6dsox_den_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsox_den_mode_t *val)
{
lsm6dsox_ctrl6_c_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t *)®, 1);
- switch (reg.den_mode) {
+ switch (reg.den_mode)
+ {
case LSM6DSOX_DEN_DISABLE:
*val = LSM6DSOX_DEN_DISABLE;
break;
+
case LSM6DSOX_LEVEL_FIFO:
*val = LSM6DSOX_LEVEL_FIFO;
break;
+
case LSM6DSOX_LEVEL_LETCHED:
*val = LSM6DSOX_LEVEL_LETCHED;
break;
+
case LSM6DSOX_LEVEL_TRIGGER:
*val = LSM6DSOX_LEVEL_TRIGGER;
break;
+
case LSM6DSOX_EDGE_TRIGGER:
*val = LSM6DSOX_EDGE_TRIGGER;
break;
+
default:
*val = LSM6DSOX_DEN_DISABLE;
break;
}
+
return ret;
}
@@ -6564,17 +8006,21 @@ int32_t lsm6dsox_den_mode_get(stmdev_ctx_t *ctx, lsm6dsox_den_mode_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of den_lh in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_den_polarity_set(stmdev_ctx_t *ctx, lsm6dsox_den_lh_t val)
+int32_t lsm6dsox_den_polarity_set(stmdev_ctx_t *ctx,
+ lsm6dsox_den_lh_t val)
{
lsm6dsox_ctrl9_xl_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.den_lh = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1);
}
return ret;
@@ -6585,26 +8031,32 @@ int32_t lsm6dsox_den_polarity_set(stmdev_ctx_t *ctx, lsm6dsox_den_lh_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of den_lh in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_den_polarity_get(stmdev_ctx_t *ctx, lsm6dsox_den_lh_t *val)
+int32_t lsm6dsox_den_polarity_get(stmdev_ctx_t *ctx,
+ lsm6dsox_den_lh_t *val)
{
lsm6dsox_ctrl9_xl_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1);
- switch (reg.den_lh) {
+ switch (reg.den_lh)
+ {
case LSM6DSOX_DEN_ACT_LOW:
*val = LSM6DSOX_DEN_ACT_LOW;
break;
+
case LSM6DSOX_DEN_ACT_HIGH:
*val = LSM6DSOX_DEN_ACT_HIGH;
break;
+
default:
*val = LSM6DSOX_DEN_ACT_LOW;
break;
}
+
return ret;
}
@@ -6613,17 +8065,21 @@ int32_t lsm6dsox_den_polarity_get(stmdev_ctx_t *ctx, lsm6dsox_den_lh_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of den_xl_g in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_den_enable_set(stmdev_ctx_t *ctx, lsm6dsox_den_xl_g_t val)
+int32_t lsm6dsox_den_enable_set(stmdev_ctx_t *ctx,
+ lsm6dsox_den_xl_g_t val)
{
lsm6dsox_ctrl9_xl_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.den_xl_g = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1);
}
return ret;
@@ -6634,29 +8090,36 @@ int32_t lsm6dsox_den_enable_set(stmdev_ctx_t *ctx, lsm6dsox_den_xl_g_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of den_xl_g in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_den_enable_get(stmdev_ctx_t *ctx, lsm6dsox_den_xl_g_t *val)
+int32_t lsm6dsox_den_enable_get(stmdev_ctx_t *ctx,
+ lsm6dsox_den_xl_g_t *val)
{
lsm6dsox_ctrl9_xl_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1);
- switch (reg.den_xl_g) {
+ switch (reg.den_xl_g)
+ {
case LSM6DSOX_STAMP_IN_GY_DATA:
*val = LSM6DSOX_STAMP_IN_GY_DATA;
break;
+
case LSM6DSOX_STAMP_IN_XL_DATA:
*val = LSM6DSOX_STAMP_IN_XL_DATA;
break;
+
case LSM6DSOX_STAMP_IN_GY_XL_DATA:
*val = LSM6DSOX_STAMP_IN_GY_XL_DATA;
break;
+
default:
*val = LSM6DSOX_STAMP_IN_GY_DATA;
break;
}
+
return ret;
}
@@ -6665,6 +8128,7 @@ int32_t lsm6dsox_den_enable_get(stmdev_ctx_t *ctx, lsm6dsox_den_xl_g_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of den_z in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -6672,10 +8136,12 @@ int32_t lsm6dsox_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_ctrl9_xl_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.den_z = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1);
}
return ret;
@@ -6686,6 +8152,7 @@ int32_t lsm6dsox_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of den_z in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -6693,7 +8160,7 @@ int32_t lsm6dsox_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_ctrl9_xl_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1);
*val = reg.den_z;
return ret;
@@ -6704,6 +8171,7 @@ int32_t lsm6dsox_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of den_y in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -6711,10 +8179,12 @@ int32_t lsm6dsox_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_ctrl9_xl_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.den_y = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1);
}
return ret;
@@ -6725,6 +8195,7 @@ int32_t lsm6dsox_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of den_y in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -6732,7 +8203,7 @@ int32_t lsm6dsox_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_ctrl9_xl_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1);
*val = reg.den_y;
return ret;
@@ -6743,6 +8214,7 @@ int32_t lsm6dsox_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of den_x in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -6750,10 +8222,12 @@ int32_t lsm6dsox_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_ctrl9_xl_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.den_x = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1);
}
return ret;
@@ -6764,6 +8238,7 @@ int32_t lsm6dsox_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of den_x in reg CTRL9_XL
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -6771,7 +8246,7 @@ int32_t lsm6dsox_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_ctrl9_xl_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1);
*val = reg.den_x;
return ret;
@@ -6787,55 +8262,33 @@ int32_t lsm6dsox_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val)
* @brief This section groups all the functions that manage pedometer.
* @{
*
-*/
+ */
/**
* @brief Enable pedometer algorithm.[set]
*
* @param ctx read / write interface definitions
* @param val turn on and configure pedometer
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_pedo_sens_set(stmdev_ctx_t *ctx, lsm6dsox_pedo_md_t val)
+int32_t lsm6dsox_pedo_sens_set(stmdev_ctx_t *ctx,
+ lsm6dsox_pedo_md_t val)
{
- lsm6dsox_emb_func_en_a_t emb_func_en_a;
- lsm6dsox_emb_func_en_b_t emb_func_en_b;
lsm6dsox_pedo_cmd_reg_t pedo_cmd_reg;
int32_t ret;
ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_CMD_REG,
- (uint8_t*)&pedo_cmd_reg);
- if (ret == 0) {
- ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- }
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
- }
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&pedo_cmd_reg);
- emb_func_en_a.pedo_en = (uint8_t)val & 0x01U;
- emb_func_en_b.mlc_en = ((uint8_t)val & 0x02U)>>1;
- pedo_cmd_reg.fp_rejection_en = ((uint8_t)val & 0x10U)>>4;
- pedo_cmd_reg.ad_det_en = ((uint8_t)val & 0x20U)>>5;
- }
- if (ret == 0) {
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
- }
- if (ret == 0) {
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
- }
- if (ret == 0) {
- ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
- }
- if (ret == 0) {
+ if (ret == 0)
+ {
+ pedo_cmd_reg.fp_rejection_en = ((uint8_t)val & 0x10U) >> 4;
+ pedo_cmd_reg.ad_det_en = ((uint8_t)val & 0x20U) >> 5;
ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_CMD_REG,
- (uint8_t*)&pedo_cmd_reg);
+ (uint8_t *)&pedo_cmd_reg);
}
+
return ret;
}
@@ -6844,49 +8297,38 @@ int32_t lsm6dsox_pedo_sens_set(stmdev_ctx_t *ctx, lsm6dsox_pedo_md_t val)
*
* @param ctx read / write interface definitions
* @param val turn on and configure pedometer
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_pedo_sens_get(stmdev_ctx_t *ctx, lsm6dsox_pedo_md_t *val)
+int32_t lsm6dsox_pedo_sens_get(stmdev_ctx_t *ctx,
+ lsm6dsox_pedo_md_t *val)
{
- lsm6dsox_emb_func_en_a_t emb_func_en_a;
- lsm6dsox_emb_func_en_b_t emb_func_en_b;
lsm6dsox_pedo_cmd_reg_t pedo_cmd_reg;
int32_t ret;
ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_CMD_REG,
- (uint8_t*)&pedo_cmd_reg);
- if (ret == 0) {
- ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- }
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
- }
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
- }
- if (ret == 0) {
- ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
- }
- switch ( (pedo_cmd_reg.ad_det_en <<5) | (pedo_cmd_reg.fp_rejection_en << 4) |
- (emb_func_en_b.mlc_en << 1) | emb_func_en_a.pedo_en) {
- case LSM6DSOX_PEDO_DISABLE:
- *val = LSM6DSOX_PEDO_DISABLE;
- break;
+ (uint8_t *)&pedo_cmd_reg);
+
+ switch ((pedo_cmd_reg.ad_det_en << 5) | (pedo_cmd_reg.fp_rejection_en
+ << 4))
+ {
case LSM6DSOX_PEDO_BASE_MODE:
*val = LSM6DSOX_PEDO_BASE_MODE;
break;
+
case LSM6DSOX_FALSE_STEP_REJ:
*val = LSM6DSOX_FALSE_STEP_REJ;
break;
+
case LSM6DSOX_FALSE_STEP_REJ_ADV_MODE:
*val = LSM6DSOX_FALSE_STEP_REJ_ADV_MODE;
break;
+
default:
- *val = LSM6DSOX_PEDO_DISABLE;
+ *val = LSM6DSOX_PEDO_BASE_MODE;
break;
}
+
return ret;
}
@@ -6895,6 +8337,7 @@ int32_t lsm6dsox_pedo_sens_get(stmdev_ctx_t *ctx, lsm6dsox_pedo_md_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of is_step_det in reg EMB_FUNC_STATUS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -6903,10 +8346,15 @@ int32_t lsm6dsox_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_STATUS, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_STATUS,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.is_step_det;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -6919,12 +8367,17 @@ int32_t lsm6dsox_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsox_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
- ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_DEB_STEPS_CONF, buff);
+
+ ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_DEB_STEPS_CONF,
+ buff);
+
return ret;
}
@@ -6933,12 +8386,17 @@ int32_t lsm6dsox_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsox_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
- ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_DEB_STEPS_CONF, buff);
+
+ ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_DEB_STEPS_CONF,
+ buff);
+
return ret;
}
@@ -6947,20 +8405,26 @@ int32_t lsm6dsox_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_pedo_steps_period_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsox_pedo_steps_period_set(stmdev_ctx_t *ctx,
+ uint16_t val)
{
+ uint8_t buff[2];
int32_t ret;
- uint8_t index;
- index = 0x00U;
- ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_SC_DELTAT_L, &buff[index]);
- if (ret == 0) {
- index++;
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
+ ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_SC_DELTAT_L,
+ &buff[0]);
+
+ if (ret == 0)
+ {
ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_SC_DELTAT_H,
- &buff[index]);
+ &buff[1]);
}
+
return ret;
}
@@ -6969,20 +8433,26 @@ int32_t lsm6dsox_pedo_steps_period_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_pedo_steps_period_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsox_pedo_steps_period_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
- uint8_t index;
- index = 0x00U;
- ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_SC_DELTAT_L, &buff[index]);
- if (ret == 0) {
- index++;
+ ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_SC_DELTAT_L,
+ &buff[0]);
+
+ if (ret == 0)
+ {
ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_SC_DELTAT_H,
- &buff[index]);
+ &buff[1]);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
}
+
return ret;
}
@@ -6992,20 +8462,25 @@ int32_t lsm6dsox_pedo_steps_period_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param val change the values of carry_count_en in reg PEDO_CMD_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_pedo_int_mode_set(stmdev_ctx_t *ctx,
- lsm6dsox_carry_count_en_t val)
+ lsm6dsox_carry_count_en_t val)
{
lsm6dsox_pedo_cmd_reg_t reg;
int32_t ret;
- ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_CMD_REG, (uint8_t*)®);
- if (ret == 0) {
+ ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_CMD_REG,
+ (uint8_t *)®);
+
+ if (ret == 0)
+ {
reg.carry_count_en = (uint8_t)val;
ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_CMD_REG,
- (uint8_t*)®);
+ (uint8_t *)®);
}
+
return ret;
}
@@ -7015,26 +8490,33 @@ int32_t lsm6dsox_pedo_int_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of carry_count_en in reg PEDO_CMD_REG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_pedo_int_mode_get(stmdev_ctx_t *ctx,
- lsm6dsox_carry_count_en_t *val)
+ lsm6dsox_carry_count_en_t *val)
{
lsm6dsox_pedo_cmd_reg_t reg;
int32_t ret;
- ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_CMD_REG, (uint8_t*)®);
- switch (reg.carry_count_en) {
+ ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_CMD_REG,
+ (uint8_t *)®);
+
+ switch (reg.carry_count_en)
+ {
case LSM6DSOX_EVERY_STEP:
*val = LSM6DSOX_EVERY_STEP;
break;
+
case LSM6DSOX_COUNT_OVERFLOW:
*val = LSM6DSOX_COUNT_OVERFLOW;
break;
+
default:
*val = LSM6DSOX_EVERY_STEP;
break;
}
+
return ret;
}
@@ -7051,72 +8533,30 @@ int32_t lsm6dsox_pedo_int_mode_get(stmdev_ctx_t *ctx,
*
*/
-/**
- * @brief Enable significant motion detection function.[set]
- *
- * @param ctx read / write interface definitions
- * @param val change the values of sign_motion_en in reg EMB_FUNC_EN_A
- *
- */
-int32_t lsm6dsox_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val)
-{
- lsm6dsox_emb_func_en_a_t reg;
- int32_t ret;
-
- ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A, (uint8_t*)®, 1);
- }
- if (ret == 0) {
- reg.sign_motion_en = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A, (uint8_t*)®, 1);
- }
- if (ret == 0) {
- ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
- }
- return ret;
-}
-
-/**
- * @brief Enable significant motion detection function.[get]
- *
- * @param ctx read / write interface definitions
- * @param val change the values of sign_motion_en in reg EMB_FUNC_EN_A
- *
- */
-int32_t lsm6dsox_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
-{
- lsm6dsox_emb_func_en_a_t reg;
- int32_t ret;
-
- ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A, (uint8_t*)®, 1);
- }
- if (ret == 0) {
- *val = reg.sign_motion_en;
- ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
- }
- return ret;
-}
-
/**
* @brief Interrupt status bit for significant motion detection.[get]
*
* @param ctx read / write interface definitions
* @param val change the values of is_sigmot in reg EMB_FUNC_STATUS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_motion_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsox_motion_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsox_emb_func_status_t reg;
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_STATUS, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_STATUS,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.is_sigmot;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -7137,73 +8577,30 @@ int32_t lsm6dsox_motion_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
-/**
- * @brief Enable tilt calculation.[set]
- *
- * @param ctx read / write interface definitions
- * @param val change the values of tilt_en in reg EMB_FUNC_EN_A
- *
- */
-int32_t lsm6dsox_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val)
-{
- lsm6dsox_emb_func_en_a_t reg;
- int32_t ret;
-
- ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A, (uint8_t*)®, 1);
- }
- if (ret == 0) {
- reg.tilt_en = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A, (uint8_t*)®, 1);
- }
- if (ret == 0) {
- ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
- }
- return ret;
-}
-
-/**
- * @brief Enable tilt calculation.[get]
- *
- * @param ctx read / write interface definitions
- * @param val change the values of tilt_en in reg EMB_FUNC_EN_A
- *
- */
-int32_t lsm6dsox_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
-{
- lsm6dsox_emb_func_en_a_t reg;
- int32_t ret;
-
- ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A, (uint8_t*)®, 1);
- }
- if (ret == 0) {
- *val = reg.tilt_en;
- ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
- }
-
- return ret;
-}
-
/**
* @brief Interrupt status bit for tilt detection.[get]
*
* @param ctx read / write interface definitions
* @param val change the values of is_tilt in reg EMB_FUNC_STATUS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsox_tilt_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsox_emb_func_status_t reg;
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_STATUS, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_STATUS,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.is_tilt;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -7230,20 +8627,24 @@ int32_t lsm6dsox_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_sh_mag_sensitivity_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsox_sh_mag_sensitivity_set(stmdev_ctx_t *ctx,
+ uint16_t val)
{
+ uint8_t buff[2];
int32_t ret;
- uint8_t index;
- index = 0x00U;
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SENSITIVITY_L,
- &buff[index]);
- if (ret == 0) {
- index++;
+ &buff[0]);
+
+ if (ret == 0)
+ {
ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SENSITIVITY_H,
- &buff[index]);
+ &buff[1]);
}
return ret;
@@ -7255,20 +8656,24 @@ int32_t lsm6dsox_sh_mag_sensitivity_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_sh_mag_sensitivity_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsox_sh_mag_sensitivity_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
- uint8_t index;
- index = 0x00U;
ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SENSITIVITY_L,
- &buff[index]);
- if (ret == 0) {
- index++;
+ &buff[0]);
+
+ if (ret == 0)
+ {
ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SENSITIVITY_H,
- &buff[index]);
+ &buff[1]);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
}
return ret;
@@ -7280,21 +8685,26 @@ int32_t lsm6dsox_sh_mag_sensitivity_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_mlc_mag_sensitivity_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsox_mlc_mag_sensitivity_set(stmdev_ctx_t *ctx,
+ uint16_t val)
{
+ uint8_t buff[2];
int32_t ret;
- uint8_t index;
- index = 0x00U;
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MLC_MAG_SENSITIVITY_L,
- &buff[index]);
- if (ret == 0) {
- index++;
+ &buff[0]);
+
+ if (ret == 0)
+ {
ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MLC_MAG_SENSITIVITY_H,
- &buff[index]);
+ &buff[1]);
}
+
return ret;
}
@@ -7304,21 +8714,26 @@ int32_t lsm6dsox_mlc_mag_sensitivity_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_mlc_mag_sensitivity_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsox_mlc_mag_sensitivity_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
- uint8_t index;
- index = 0x00U;
ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MLC_MAG_SENSITIVITY_L,
- &buff[index]);
- if (ret == 0) {
- index++;
+ &buff[0]);
+
+ if (ret == 0)
+ {
ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MLC_MAG_SENSITIVITY_H,
- &buff[index]);
+ &buff[1]);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
}
+
return ret;
}
@@ -7328,35 +8743,58 @@ int32_t lsm6dsox_mlc_mag_sensitivity_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_mag_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsox_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
- uint8_t index;
- index = 0x00U;
- ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFX_L, &buff[index]);
- if (ret == 0) {
- index++;
- ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFX_H, &buff[index]);
+ uint8_t i;
+ buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
+ buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
+ buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
+ buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
+ buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
+ buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
+ i = 0x00U;
+ ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFX_L,
+ &buff[i]);
+
+ if (ret == 0)
+ {
+ i++;
+ ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFX_H,
+ &buff[i]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFY_L, &buff[index]);
+
+ if (ret == 0)
+ {
+ i++;
+ ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFY_L,
+ &buff[i]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFY_H, &buff[index]);
+
+ if (ret == 0)
+ {
+ i++;
+ ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFY_H,
+ &buff[i]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFZ_L, &buff[index]);
+ if (ret == 0)
+ {
+ i++;
+ ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFZ_L,
+ &buff[i]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFZ_H, &buff[index]);
+
+ if (ret == 0)
+ {
+ i++;
+ ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFZ_H,
+ &buff[i]);
}
return ret;
@@ -7367,37 +8805,61 @@ int32_t lsm6dsox_mag_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_mag_offset_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsox_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
- uint8_t index;
- index = 0x00U;
- ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFX_L, &buff[index]);
- if (ret == 0) {
- index++;
- ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFX_H, &buff[index]);
+ uint8_t i;
+ i = 0x00U;
+ ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFX_L,
+ &buff[i]);
+
+ if (ret == 0)
+ {
+ i++;
+ ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFX_H,
+ &buff[i]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFY_L, &buff[index]);
+ if (ret == 0)
+ {
+ i++;
+ ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFY_L,
+ &buff[i]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFY_H, &buff[index]);
+
+ if (ret == 0)
+ {
+ i++;
+ ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFY_H,
+ &buff[i]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFZ_L, &buff[index]);
+ if (ret == 0)
+ {
+ i++;
+ ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFZ_L,
+ &buff[i]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFZ_H, &buff[index]);
+
+ if (ret == 0)
+ {
+ i++;
+ ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFZ_H,
+ &buff[i]);
}
+
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -7412,63 +8874,106 @@ int32_t lsm6dsox_mag_offset_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsox_mag_soft_iron_set(stmdev_ctx_t *ctx, uint16_t *val)
{
- int32_t ret;
+ uint8_t buff[12];
uint8_t index;
+ int32_t ret;
+ buff[1] = (uint8_t)(val[0] / 256U);
+ buff[0] = (uint8_t)(val[0] - (buff[1] * 256U));
+ buff[3] = (uint8_t)(val[1] / 256U);
+ buff[2] = (uint8_t)(val[1] - (buff[3] * 256U));
+ buff[5] = (uint8_t)(val[2] / 256U);
+ buff[4] = (uint8_t)(val[2] - (buff[5] * 256U));
+ buff[7] = (uint8_t)(val[3] / 256U);
+ buff[6] = (uint8_t)(val[3] - (buff[1] * 256U));
+ buff[9] = (uint8_t)(val[4] / 256U);
+ buff[8] = (uint8_t)(val[4] - (buff[3] * 256U));
+ buff[11] = (uint8_t)(val[5] / 256U);
+ buff[10] = (uint8_t)(val[5] - (buff[5] * 256U));
index = 0x00U;
- ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XX_L, &buff[index]);
- if (ret == 0) {
+ ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XX_L,
+ &buff[index]);
+
+ if (ret == 0)
+ {
index++;
- ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XX_H, &buff[index]);
+ ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XX_H,
+ &buff[index]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XY_L, &buff[index]);
- }
- if (ret == 0) {
+ if (ret == 0)
+ {
index++;
- ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XY_H, &buff[index]);
+ ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XY_L,
+ &buff[index]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XZ_L, &buff[index]);
- }
- if (ret == 0) {
+ if (ret == 0)
+ {
index++;
- ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XZ_H, &buff[index]);
+ ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XY_H,
+ &buff[index]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_YY_L, &buff[index]);
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XZ_L,
+ &buff[index]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
index++;
- ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_YY_H, &buff[index]);
+ ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XZ_H,
+ &buff[index]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
index++;
+ ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_YY_L,
+ &buff[index]);
+ }
- ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_YZ_L, &buff[index]);
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_YY_H,
+ &buff[index]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
index++;
- ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_YZ_H, &buff[index]);
+ ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_YZ_L,
+ &buff[index]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
index++;
+ ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_YZ_H,
+ &buff[index]);
+ }
- ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_ZZ_L, &buff[index]);
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_ZZ_L,
+ &buff[index]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
index++;
- ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_ZZ_H, &buff[index]);
+ ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_ZZ_H,
+ &buff[index]);
}
return ret;
@@ -7486,65 +8991,109 @@ int32_t lsm6dsox_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsox_mag_soft_iron_get(stmdev_ctx_t *ctx, uint16_t *val)
{
- int32_t ret;
+ uint8_t buff[12];
uint8_t index;
+ int32_t ret;
index = 0x00U;
- ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XX_L, &buff[index]);
- if (ret == 0) {
+ ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XX_L,
+ &buff[index]);
+
+ if (ret == 0)
+ {
index++;
- ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XX_H, &buff[index]);
+ ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XX_H,
+ &buff[index]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XY_L, &buff[index]);
- }
- if (ret == 0) {
+ if (ret == 0)
+ {
index++;
- ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XY_H, &buff[index]);
+ ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XY_L,
+ &buff[index]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XZ_L, &buff[index]);
- }
- if (ret == 0) {
+ if (ret == 0)
+ {
index++;
- ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XZ_H, &buff[index]);
+ ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XY_H,
+ &buff[index]);
}
- if (ret == 0) {
- index++;
- ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_YY_L, &buff[index]);
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XZ_L,
+ &buff[index]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
index++;
- ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_YY_H, &buff[index]);
+ ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XZ_H,
+ &buff[index]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
index++;
+ ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_YY_L,
+ &buff[index]);
+ }
- ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_YZ_L, &buff[index]);
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_YY_H,
+ &buff[index]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
index++;
- ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_YZ_H, &buff[index]);
+ ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_YZ_L,
+ &buff[index]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
index++;
+ ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_YZ_H,
+ &buff[index]);
+ }
- ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_ZZ_L, &buff[index]);
+ if (ret == 0)
+ {
+ index++;
+ ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_ZZ_L,
+ &buff[index]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
index++;
- ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_ZZ_H, &buff[index]);
+ ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_ZZ_H,
+ &buff[index]);
}
+ val[0] = buff[1];
+ val[0] = (val[0] * 256U) + buff[0];
+ val[1] = buff[3];
+ val[1] = (val[1] * 256U) + buff[2];
+ val[2] = buff[5];
+ val[2] = (val[2] * 256U) + buff[4];
+ val[3] = buff[7];
+ val[3] = (val[3] * 256U) + buff[6];
+ val[4] = buff[9];
+ val[4] = (val[4] * 256U) + buff[8];
+ val[5] = buff[11];
+ val[6] = (val[5] * 256U) + buff[10];
+
return ret;
}
@@ -7556,17 +9105,23 @@ int32_t lsm6dsox_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param val change the values of mag_z_axis in reg MAG_CFG_A
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_mag_z_orient_set(stmdev_ctx_t *ctx, lsm6dsox_mag_z_axis_t val)
+int32_t lsm6dsox_mag_z_orient_set(stmdev_ctx_t *ctx,
+ lsm6dsox_mag_z_axis_t val)
{
lsm6dsox_mag_cfg_a_t reg;
int32_t ret;
- ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_A, (uint8_t*)®);
- if (ret == 0) {
+ ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_A,
+ (uint8_t *)®);
+
+ if (ret == 0)
+ {
reg.mag_z_axis = (uint8_t) val;
- ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_CFG_A, (uint8_t*)®);
+ ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_CFG_A,
+ (uint8_t *)®);
}
return ret;
@@ -7580,37 +9135,49 @@ int32_t lsm6dsox_mag_z_orient_set(stmdev_ctx_t *ctx, lsm6dsox_mag_z_axis_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of mag_z_axis in reg MAG_CFG_A
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_mag_z_orient_get(stmdev_ctx_t *ctx,
- lsm6dsox_mag_z_axis_t *val)
+ lsm6dsox_mag_z_axis_t *val)
{
lsm6dsox_mag_cfg_a_t reg;
int32_t ret;
- ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_A, (uint8_t*)®);
- switch (reg.mag_z_axis) {
+
+ ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_A,
+ (uint8_t *)®);
+
+ switch (reg.mag_z_axis)
+ {
case LSM6DSOX_Z_EQ_Y:
*val = LSM6DSOX_Z_EQ_Y;
break;
+
case LSM6DSOX_Z_EQ_MIN_Y:
*val = LSM6DSOX_Z_EQ_MIN_Y;
break;
+
case LSM6DSOX_Z_EQ_X:
*val = LSM6DSOX_Z_EQ_X;
break;
+
case LSM6DSOX_Z_EQ_MIN_X:
*val = LSM6DSOX_Z_EQ_MIN_X;
break;
+
case LSM6DSOX_Z_EQ_MIN_Z:
*val = LSM6DSOX_Z_EQ_MIN_Z;
break;
+
case LSM6DSOX_Z_EQ_Z:
*val = LSM6DSOX_Z_EQ_Z;
break;
+
default:
*val = LSM6DSOX_Z_EQ_Y;
break;
}
+
return ret;
}
@@ -7622,19 +9189,25 @@ int32_t lsm6dsox_mag_z_orient_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of mag_y_axis in reg MAG_CFG_A
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_mag_y_orient_set(stmdev_ctx_t *ctx,
- lsm6dsox_mag_y_axis_t val)
+ lsm6dsox_mag_y_axis_t val)
{
lsm6dsox_mag_cfg_a_t reg;
int32_t ret;
- ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_A, (uint8_t*)®);
- if (ret == 0) {
+ ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_A,
+ (uint8_t *)®);
+
+ if (ret == 0)
+ {
reg.mag_y_axis = (uint8_t)val;
- ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_CFG_A,(uint8_t*) ®);
+ ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_CFG_A,
+ (uint8_t *) ®);
}
+
return ret;
}
@@ -7646,38 +9219,49 @@ int32_t lsm6dsox_mag_y_orient_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of mag_y_axis in reg MAG_CFG_A
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_mag_y_orient_get(stmdev_ctx_t *ctx,
- lsm6dsox_mag_y_axis_t *val)
+ lsm6dsox_mag_y_axis_t *val)
{
lsm6dsox_mag_cfg_a_t reg;
int32_t ret;
- ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_A, (uint8_t*)®);
- switch (reg.mag_y_axis) {
+ ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_A,
+ (uint8_t *)®);
+
+ switch (reg.mag_y_axis)
+ {
case LSM6DSOX_Y_EQ_Y:
*val = LSM6DSOX_Y_EQ_Y;
break;
+
case LSM6DSOX_Y_EQ_MIN_Y:
*val = LSM6DSOX_Y_EQ_MIN_Y;
break;
+
case LSM6DSOX_Y_EQ_X:
*val = LSM6DSOX_Y_EQ_X;
break;
+
case LSM6DSOX_Y_EQ_MIN_X:
*val = LSM6DSOX_Y_EQ_MIN_X;
break;
+
case LSM6DSOX_Y_EQ_MIN_Z:
*val = LSM6DSOX_Y_EQ_MIN_Z;
break;
+
case LSM6DSOX_Y_EQ_Z:
*val = LSM6DSOX_Y_EQ_Z;
break;
+
default:
*val = LSM6DSOX_Y_EQ_Y;
break;
}
+
return ret;
}
@@ -7689,19 +9273,25 @@ int32_t lsm6dsox_mag_y_orient_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of mag_x_axis in reg MAG_CFG_B
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_mag_x_orient_set(stmdev_ctx_t *ctx,
- lsm6dsox_mag_x_axis_t val)
+ lsm6dsox_mag_x_axis_t val)
{
lsm6dsox_mag_cfg_b_t reg;
int32_t ret;
- ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_B, (uint8_t*)®);
- if (ret == 0) {
+ ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_B,
+ (uint8_t *)®);
+
+ if (ret == 0)
+ {
reg.mag_x_axis = (uint8_t)val;
- ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_CFG_B, (uint8_t*)®);
+ ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_CFG_B,
+ (uint8_t *)®);
}
+
return ret;
}
@@ -7713,38 +9303,49 @@ int32_t lsm6dsox_mag_x_orient_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of mag_x_axis in reg MAG_CFG_B
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_mag_x_orient_get(stmdev_ctx_t *ctx,
- lsm6dsox_mag_x_axis_t *val)
+ lsm6dsox_mag_x_axis_t *val)
{
lsm6dsox_mag_cfg_b_t reg;
int32_t ret;
- ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_B, (uint8_t*)®);
- switch (reg.mag_x_axis) {
+ ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_B,
+ (uint8_t *)®);
+
+ switch (reg.mag_x_axis)
+ {
case LSM6DSOX_X_EQ_Y:
*val = LSM6DSOX_X_EQ_Y;
break;
+
case LSM6DSOX_X_EQ_MIN_Y:
*val = LSM6DSOX_X_EQ_MIN_Y;
break;
+
case LSM6DSOX_X_EQ_X:
*val = LSM6DSOX_X_EQ_X;
break;
+
case LSM6DSOX_X_EQ_MIN_X:
*val = LSM6DSOX_X_EQ_MIN_X;
break;
+
case LSM6DSOX_X_EQ_MIN_Z:
*val = LSM6DSOX_X_EQ_MIN_Z;
break;
+
case LSM6DSOX_X_EQ_Z:
*val = LSM6DSOX_X_EQ_Z;
break;
+
default:
*val = LSM6DSOX_X_EQ_Y;
break;
}
+
return ret;
}
@@ -7767,71 +9368,26 @@ int32_t lsm6dsox_mag_x_orient_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of is_fsm_lc in reg EMB_FUNC_STATUS
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsox_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsox_emb_func_status_t reg;
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_STATUS, (uint8_t*)®, 1);
- }
- if (ret == 0) {
- *val = reg.is_fsm_lc;
- ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
- }
- return ret;
-}
-
-/**
- * @brief Finite State Machine global enable.[set]
- *
- * @param ctx read / write interface definitions
- * @param val change the values of fsm_en in reg EMB_FUNC_EN_B
- *
- */
-int32_t lsm6dsox_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val)
-{
- int32_t ret;
- lsm6dsox_emb_func_en_b_t reg;
- ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, (uint8_t*)®, 1);
- }
- if (ret == 0) {
- reg.fsm_en = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, (uint8_t*)®, 1);
- }
- if (ret == 0) {
- ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_STATUS,
+ (uint8_t *)®, 1);
}
- return ret;
-}
-
-/**
- * @brief Finite State Machine global enable.[get]
- *
- * @param ctx read / write interface definitions
- * @param uint8_t *: return the values of fsm_en in reg EMB_FUNC_EN_B
- *
- */
-int32_t lsm6dsox_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val)
-{
- int32_t ret;
- lsm6dsox_emb_func_en_b_t reg;
- ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, (uint8_t*)®, 1);
- }
- if (ret == 0) {
- *val = reg.fsm_en;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, (uint8_t*)®, 1);
- }
- if (ret == 0) {
+ if (ret == 0)
+ {
+ *val = reg.is_fsm_lc;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -7843,55 +9399,30 @@ int32_t lsm6dsox_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_fsm_enable_set(stmdev_ctx_t *ctx,
lsm6dsox_emb_fsm_enable_t *val)
{
int32_t ret;
- lsm6dsox_emb_func_en_b_t reg;
-
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_ENABLE_A,
- (uint8_t*)&val->fsm_enable_a, 1);
+ (uint8_t *)&val->fsm_enable_a, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_ENABLE_B,
- (uint8_t*)&val->fsm_enable_b, 1);
+ (uint8_t *)&val->fsm_enable_b, 1);
}
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B,
- (uint8_t*)®, 1);
- }
- if (ret == 0) {
- if ( (val->fsm_enable_a.fsm1_en |
- val->fsm_enable_a.fsm2_en |
- val->fsm_enable_a.fsm3_en |
- val->fsm_enable_a.fsm4_en |
- val->fsm_enable_a.fsm5_en |
- val->fsm_enable_a.fsm6_en |
- val->fsm_enable_a.fsm7_en |
- val->fsm_enable_a.fsm8_en |
- val->fsm_enable_b.fsm9_en |
- val->fsm_enable_b.fsm10_en |
- val->fsm_enable_b.fsm11_en |
- val->fsm_enable_b.fsm12_en |
- val->fsm_enable_b.fsm13_en |
- val->fsm_enable_b.fsm14_en |
- val->fsm_enable_b.fsm15_en |
- val->fsm_enable_b.fsm16_en )
- != PROPERTY_DISABLE){
- reg.fsm_en = PROPERTY_ENABLE;
- }
- else{
- reg.fsm_en = PROPERTY_DISABLE;
- }
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, (uint8_t*)®, 1);
- }
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -7903,20 +9434,27 @@ int32_t lsm6dsox_fsm_enable_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_fsm_enable_get(stmdev_ctx_t *ctx,
- lsm6dsox_emb_fsm_enable_t *val)
+ lsm6dsox_emb_fsm_enable_t *val)
{
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_ENABLE_A, (uint8_t*) val, 2);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_ENABLE_A, (uint8_t *) val,
+ 2);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
+
return ret;
}
@@ -7926,17 +9464,25 @@ int32_t lsm6dsox_fsm_enable_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_long_cnt_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsox_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val)
{
+ uint8_t buff[2];
int32_t ret;
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_L, buff, 2);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -7949,17 +9495,25 @@ int32_t lsm6dsox_long_cnt_set(stmdev_ctx_t *ctx, uint8_t *buff)
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_long_cnt_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsox_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_L, buff, 2);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -7972,26 +9526,35 @@ int32_t lsm6dsox_long_cnt_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @param ctx read / write interface definitions
* @param val change the values of fsm_lc_clr in
* reg FSM_LONG_COUNTER_CLEAR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_long_clr_set(stmdev_ctx_t *ctx, lsm6dsox_fsm_lc_clr_t val)
+int32_t lsm6dsox_long_clr_set(stmdev_ctx_t *ctx,
+ lsm6dsox_fsm_lc_clr_t val)
{
lsm6dsox_fsm_long_counter_clear_t reg;
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_CLEAR,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg. fsm_lc_clr = (uint8_t)val;
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_CLEAR,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
+
return ret;
}
@@ -8001,36 +9564,47 @@ int32_t lsm6dsox_long_clr_set(stmdev_ctx_t *ctx, lsm6dsox_fsm_lc_clr_t val)
* @param ctx read / write interface definitions
* @param val Get the values of fsm_lc_clr in
* reg FSM_LONG_COUNTER_CLEAR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_long_clr_get(stmdev_ctx_t *ctx, lsm6dsox_fsm_lc_clr_t *val)
+int32_t lsm6dsox_long_clr_get(stmdev_ctx_t *ctx,
+ lsm6dsox_fsm_lc_clr_t *val)
{
lsm6dsox_fsm_long_counter_clear_t reg;
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_CLEAR,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
- switch (reg.fsm_lc_clr) {
+
+ if (ret == 0)
+ {
+ switch (reg.fsm_lc_clr)
+ {
case LSM6DSOX_LC_NORMAL:
*val = LSM6DSOX_LC_NORMAL;
break;
+
case LSM6DSOX_LC_CLEAR:
*val = LSM6DSOX_LC_CLEAR;
break;
+
case LSM6DSOX_LC_CLEAR_DONE:
*val = LSM6DSOX_LC_CLEAR_DONE;
break;
+
default:
*val = LSM6DSOX_LC_NORMAL;
break;
}
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -8042,17 +9616,23 @@ int32_t lsm6dsox_long_clr_get(stmdev_ctx_t *ctx, lsm6dsox_fsm_lc_clr_t *val)
*
* @param ctx read / write interface definitions
* @param val struct of registers from FSM_OUTS1 to FSM_OUTS16
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_fsm_out_get(stmdev_ctx_t *ctx, lsm6dsox_fsm_out_t *val)
+int32_t lsm6dsox_fsm_out_get(stmdev_ctx_t *ctx,
+ lsm6dsox_fsm_out_t *val)
{
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_OUTS1, (uint8_t*)val, 16);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_OUTS1, (uint8_t *)val, 16);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -8064,28 +9644,37 @@ int32_t lsm6dsox_fsm_out_get(stmdev_ctx_t *ctx, lsm6dsox_fsm_out_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_fsm_data_rate_set(stmdev_ctx_t *ctx, lsm6dsox_fsm_odr_t val)
+int32_t lsm6dsox_fsm_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dsox_fsm_odr_t val)
{
lsm6dsox_emb_func_odr_cfg_b_t reg;
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_B,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.not_used_01 = 3; /* set default values */
reg.not_used_02 = 2; /* set default values */
reg.fsm_odr = (uint8_t)val;
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_B,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
+
return ret;
}
@@ -8094,36 +9683,48 @@ int32_t lsm6dsox_fsm_data_rate_set(stmdev_ctx_t *ctx, lsm6dsox_fsm_odr_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_fsm_data_rate_get(stmdev_ctx_t *ctx, lsm6dsox_fsm_odr_t *val)
+int32_t lsm6dsox_fsm_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dsox_fsm_odr_t *val)
{
lsm6dsox_emb_func_odr_cfg_b_t reg;
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_B,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
- switch (reg.fsm_odr) {
+
+ if (ret == 0)
+ {
+ switch (reg.fsm_odr)
+ {
case LSM6DSOX_ODR_FSM_12Hz5:
*val = LSM6DSOX_ODR_FSM_12Hz5;
break;
+
case LSM6DSOX_ODR_FSM_26Hz:
*val = LSM6DSOX_ODR_FSM_26Hz;
break;
+
case LSM6DSOX_ODR_FSM_52Hz:
*val = LSM6DSOX_ODR_FSM_52Hz;
break;
+
case LSM6DSOX_ODR_FSM_104Hz:
*val = LSM6DSOX_ODR_FSM_104Hz;
break;
+
default:
*val = LSM6DSOX_ODR_FSM_12Hz5;
break;
}
+
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -8135,6 +9736,7 @@ int32_t lsm6dsox_fsm_data_rate_get(stmdev_ctx_t *ctx, lsm6dsox_fsm_odr_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of fsm_init in reg FSM_INIT
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -8143,14 +9745,22 @@ int32_t lsm6dsox_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.fsm_init = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -8162,6 +9772,7 @@ int32_t lsm6dsox_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of fsm_init in reg FSM_INIT
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -8170,13 +9781,19 @@ int32_t lsm6dsox_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.fsm_init;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
+
return ret;
}
@@ -8188,20 +9805,25 @@ int32_t lsm6dsox_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val the value of long counter
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint16_t val)
+int32_t lsm6dsox_long_cnt_int_value_set(stmdev_ctx_t *ctx,
+ uint16_t val)
{
int32_t ret;
+
uint8_t add_l;
uint8_t add_h;
+ add_h = (uint8_t)((val & 0xFF00U) >> 8);
+ add_l = (uint8_t)(val & 0x00FFU);
+ ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_LC_TIMEOUT_L,
+ &add_l);
- add_h = (uint8_t)( ( val & 0xFF00U ) >> 8 );
- add_l = (uint8_t)( val & 0x00FFU );
-
- ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_LC_TIMEOUT_L, &add_l);
- if (ret == 0) {
- ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_LC_TIMEOUT_H, &add_h);
+ if (ret == 0)
+ {
+ ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_LC_TIMEOUT_H,
+ &add_h);
}
return ret;
@@ -8215,17 +9837,23 @@ int32_t lsm6dsox_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint16_t val)
*
* @param ctx read / write interface definitions
* @param val buffer that stores the value of long counter
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint16_t *val)
+int32_t lsm6dsox_long_cnt_int_value_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
int32_t ret;
+
uint8_t add_l;
uint8_t add_h;
+ ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_LC_TIMEOUT_L,
+ &add_l);
- ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_LC_TIMEOUT_L, &add_l);
- if (ret == 0) {
- ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_LC_TIMEOUT_H, &add_h);
+ if (ret == 0)
+ {
+ ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_LC_TIMEOUT_H,
+ &add_h);
*val = add_h;
*val = *val << 8;
*val += add_l;
@@ -8239,9 +9867,11 @@ int32_t lsm6dsox_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint16_t *val)
*
* @param ctx read / write interface definitions
* @param val value to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dsox_fsm_number_of_programs_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
int32_t ret;
@@ -8255,9 +9885,11 @@ int32_t lsm6dsox_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val buffer that stores data read.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsox_fsm_number_of_programs_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
int32_t ret;
@@ -8272,21 +9904,27 @@ int32_t lsm6dsox_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val the value of start address
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val)
+int32_t lsm6dsox_fsm_start_address_set(stmdev_ctx_t *ctx,
+ uint16_t val)
{
int32_t ret;
+
uint8_t add_l;
uint8_t add_h;
+ add_h = (uint8_t)((val & 0xFF00U) >> 8);
+ add_l = (uint8_t)(val & 0x00FFU);
+ ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_START_ADD_L,
+ &add_l);
- add_h = (uint8_t)( ( val & 0xFF00U ) >> 8 );
- add_l = (uint8_t)( val & 0x00FFU );
-
- ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_START_ADD_L, &add_l);
- if (ret == 0) {
- ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_START_ADD_H, &add_h);
+ if (ret == 0)
+ {
+ ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_START_ADD_H,
+ &add_h);
}
+
return ret;
}
@@ -8296,21 +9934,26 @@ int32_t lsm6dsox_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val)
*
* @param ctx read / write interface definitions
* @param val buffer the value of start address.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val)
+int32_t lsm6dsox_fsm_start_address_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
int32_t ret;
+
uint8_t add_l;
uint8_t add_h;
-
ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_START_ADD_L, &add_l);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_START_ADD_H, &add_h);
*val = add_h;
*val = *val << 8;
*val += add_l;
}
+
return ret;
}
@@ -8327,79 +9970,19 @@ int32_t lsm6dsox_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val)
*
*/
-/**
- * @brief Enable Machine Learning Core.[set]
- *
- * @param ctx read / write interface definitions
- * @param val change the values of mlc_en in
- * reg EMB_FUNC_EN_B and mlc_init
- * in EMB_FUNC_INIT_B
- *
- */
-int32_t lsm6dsox_mlc_set(stmdev_ctx_t *ctx, uint8_t val)
-{
- lsm6dsox_emb_func_en_b_t reg;
- int32_t ret;
-
- ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, (uint8_t*)®, 1);
- }
- if (ret == 0) {
- reg.mlc_en = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, (uint8_t*)®, 1);
- }
- if ((val != PROPERTY_DISABLE) && (ret == 0)){
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B,
- (uint8_t*)®, 1);
- if (ret == 0) {
- reg.mlc_en = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B,
- (uint8_t*)®, 1);
- }
- }
- if (ret == 0) {
- ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
- }
- return ret;
-}
-
-/**
- * @brief Enable Machine Learning Core.[get]
- *
- * @param ctx read / write interface definitions
- * @param val Get the values of mlc_en in
- * reg EMB_FUNC_EN_B
- *
- */
-int32_t lsm6dsox_mlc_get(stmdev_ctx_t *ctx, uint8_t *val)
-{
- lsm6dsox_emb_func_en_b_t reg;
- int32_t ret;
-
- ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, (uint8_t*)®, 1);
- }
- if (ret == 0) {
- ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
- *val = reg.mlc_en;
- }
- return ret;
-}
-
/**
* @brief Machine Learning Core status register[get]
*
* @param ctx read / write interface definitions
* @param val register MLC_STATUS_MAINPAGE
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_mlc_status_get(stmdev_ctx_t *ctx,
lsm6dsox_mlc_status_mainpage_t *val)
{
return lsm6dsox_read_reg(ctx, LSM6DSOX_MLC_STATUS_MAINPAGE,
- (uint8_t*) val, 1);
+ (uint8_t *) val, 1);
}
/**
@@ -8408,24 +9991,32 @@ int32_t lsm6dsox_mlc_status_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val get the values of mlc_odr in
* reg EMB_FUNC_ODR_CFG_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_mlc_data_rate_set(stmdev_ctx_t *ctx,
- lsm6dsox_mlc_odr_t val)
+ lsm6dsox_mlc_odr_t val)
{
lsm6dsox_emb_func_odr_cfg_c_t reg;
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_C,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.mlc_odr = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_C, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_C,
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -8438,6 +10029,7 @@ int32_t lsm6dsox_mlc_data_rate_set(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of mlc_odr in
* reg EMB_FUNC_ODR_CFG_C
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_mlc_data_rate_get(stmdev_ctx_t *ctx,
@@ -8447,30 +10039,41 @@ int32_t lsm6dsox_mlc_data_rate_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_C,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
- switch (reg.mlc_odr) {
+
+ if (ret == 0)
+ {
+ switch (reg.mlc_odr)
+ {
case LSM6DSOX_ODR_PRGS_12Hz5:
*val = LSM6DSOX_ODR_PRGS_12Hz5;
break;
+
case LSM6DSOX_ODR_PRGS_26Hz:
*val = LSM6DSOX_ODR_PRGS_26Hz;
break;
+
case LSM6DSOX_ODR_PRGS_52Hz:
*val = LSM6DSOX_ODR_PRGS_52Hz;
break;
+
case LSM6DSOX_ODR_PRGS_104Hz:
*val = LSM6DSOX_ODR_PRGS_104Hz;
break;
+
default:
*val = LSM6DSOX_ODR_PRGS_12Hz5;
break;
}
+
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
+
return ret;
}
@@ -8488,23 +10091,28 @@ int32_t lsm6dsox_mlc_data_rate_get(stmdev_ctx_t *ctx,
*/
/**
-* @brief Sensor hub output registers.[get]
-*
-* @param ctx read / write interface definitions
-* @param val union of registers from SENSOR_HUB_1 to SENSOR_HUB_18
-*
+ * @brief Sensor hub output registers.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val union of registers from SENSOR_HUB_1 to SENSOR_HUB_18
+ *
*/
int32_t lsm6dsox_sh_read_data_raw_get(stmdev_ctx_t *ctx,
- lsm6dsox_emb_sh_read_t *val,
- uint8_t len)
+ lsm6dsox_emb_sh_read_t *val,
+ uint8_t len)
{
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SENSOR_HUB_1, (uint8_t*) val, len);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SENSOR_HUB_1, (uint8_t *) val,
+ len);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -8516,25 +10124,33 @@ int32_t lsm6dsox_sh_read_data_raw_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of aux_sens_on in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_sh_slave_connected_set(stmdev_ctx_t *ctx,
- lsm6dsox_aux_sens_on_t val)
+ lsm6dsox_aux_sens_on_t val)
{
lsm6dsox_master_config_t reg;
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.aux_sens_on = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
+
return ret;
}
@@ -8543,36 +10159,47 @@ int32_t lsm6dsox_sh_slave_connected_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of aux_sens_on in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_sh_slave_connected_get(stmdev_ctx_t *ctx,
- lsm6dsox_aux_sens_on_t *val)
+ lsm6dsox_aux_sens_on_t *val)
{
lsm6dsox_master_config_t reg;
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
- switch (reg.aux_sens_on) {
+
+ if (ret == 0)
+ {
+ switch (reg.aux_sens_on)
+ {
case LSM6DSOX_SLV_0:
*val = LSM6DSOX_SLV_0;
break;
+
case LSM6DSOX_SLV_0_1:
*val = LSM6DSOX_SLV_0_1;
break;
+
case LSM6DSOX_SLV_0_1_2:
*val = LSM6DSOX_SLV_0_1_2;
break;
+
case LSM6DSOX_SLV_0_1_2_3:
*val = LSM6DSOX_SLV_0_1_2_3;
break;
+
default:
*val = LSM6DSOX_SLV_0;
break;
}
+
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -8584,6 +10211,7 @@ int32_t lsm6dsox_sh_slave_connected_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of master_on in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -8592,16 +10220,23 @@ int32_t lsm6dsox_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.master_on = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
+
return ret;
}
@@ -8610,6 +10245,7 @@ int32_t lsm6dsox_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param ctx read / write interface definitions
* @param val change the values of master_on in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -8618,10 +10254,14 @@ int32_t lsm6dsox_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.master_on;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -8634,22 +10274,30 @@ int32_t lsm6dsox_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of shub_pu_en in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_sh_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsox_shub_pu_en_t val)
+int32_t lsm6dsox_sh_pin_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsox_shub_pu_en_t val)
{
lsm6dsox_master_config_t reg;
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.shub_pu_en = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -8661,30 +10309,39 @@ int32_t lsm6dsox_sh_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsox_shub_pu_en_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of shub_pu_en in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_sh_pin_mode_get(stmdev_ctx_t *ctx,
- lsm6dsox_shub_pu_en_t *val)
+ lsm6dsox_shub_pu_en_t *val)
{
lsm6dsox_master_config_t reg;
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
- switch (reg.shub_pu_en) {
+
+ if (ret == 0)
+ {
+ switch (reg.shub_pu_en)
+ {
case LSM6DSOX_EXT_PULL_UP:
*val = LSM6DSOX_EXT_PULL_UP;
break;
+
case LSM6DSOX_INTERNAL_PULL_UP:
*val = LSM6DSOX_INTERNAL_PULL_UP;
break;
+
default:
*val = LSM6DSOX_EXT_PULL_UP;
break;
}
+
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -8697,6 +10354,7 @@ int32_t lsm6dsox_sh_pin_mode_get(stmdev_ctx_t *ctx,
* @param ctx read / write interface definitions
* @param val change the values of pass_through_mode in
* reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -8705,14 +10363,20 @@ int32_t lsm6dsox_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.pass_through_mode = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -8725,6 +10389,7 @@ int32_t lsm6dsox_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
* @param ctx read / write interface definitions
* @param val change the values of pass_through_mode in
* reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -8733,10 +10398,14 @@ int32_t lsm6dsox_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.pass_through_mode;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -8749,23 +10418,30 @@ int32_t lsm6dsox_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of start_config in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_sh_syncro_mode_set(stmdev_ctx_t *ctx,
- lsm6dsox_start_config_t val)
+ lsm6dsox_start_config_t val)
{
lsm6dsox_master_config_t reg;
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.start_config = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -8777,32 +10453,42 @@ int32_t lsm6dsox_sh_syncro_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of start_config in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_sh_syncro_mode_get(stmdev_ctx_t *ctx,
- lsm6dsox_start_config_t *val)
+ lsm6dsox_start_config_t *val)
{
lsm6dsox_master_config_t reg;
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
- switch (reg.start_config) {
+
+ if (ret == 0)
+ {
+ switch (reg.start_config)
+ {
case LSM6DSOX_EXT_ON_INT2_PIN:
*val = LSM6DSOX_EXT_ON_INT2_PIN;
break;
+
case LSM6DSOX_XL_GY_DRDY:
*val = LSM6DSOX_XL_GY_DRDY;
break;
+
default:
*val = LSM6DSOX_EXT_ON_INT2_PIN;
break;
}
+
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
+
return ret;
}
@@ -8812,23 +10498,30 @@ int32_t lsm6dsox_sh_syncro_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val change the values of write_once in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_sh_write_mode_set(stmdev_ctx_t *ctx,
- lsm6dsox_write_once_t val)
+ lsm6dsox_write_once_t val)
{
lsm6dsox_master_config_t reg;
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.write_once = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -8841,30 +10534,39 @@ int32_t lsm6dsox_sh_write_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val Get the values of write_once in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_sh_write_mode_get(stmdev_ctx_t *ctx,
- lsm6dsox_write_once_t *val)
+ lsm6dsox_write_once_t *val)
{
lsm6dsox_master_config_t reg;
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
- switch (reg.write_once) {
+
+ if (ret == 0)
+ {
+ switch (reg.write_once)
+ {
case LSM6DSOX_EACH_SH_CYCLE:
*val = LSM6DSOX_EACH_SH_CYCLE;
break;
+
case LSM6DSOX_ONLY_FIRST_CYCLE:
*val = LSM6DSOX_ONLY_FIRST_CYCLE;
break;
+
default:
*val = LSM6DSOX_EACH_SH_CYCLE;
break;
}
+
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -8875,6 +10577,7 @@ int32_t lsm6dsox_sh_write_mode_get(stmdev_ctx_t *ctx,
* @brief Reset Master logic and output registers.[set]
*
* @param ctx read / write interface definitions
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_sh_reset_set(stmdev_ctx_t *ctx)
@@ -8883,18 +10586,26 @@ int32_t lsm6dsox_sh_reset_set(stmdev_ctx_t *ctx)
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.rst_master_regs = PROPERTY_ENABLE;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.rst_master_regs = PROPERTY_DISABLE;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -8906,6 +10617,7 @@ int32_t lsm6dsox_sh_reset_set(stmdev_ctx_t *ctx)
*
* @param ctx read / write interface definitions
* @param val change the values of rst_master_regs in reg MASTER_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -8914,13 +10626,18 @@ int32_t lsm6dsox_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
*val = reg.rst_master_regs;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
+
return ret;
}
@@ -8929,22 +10646,30 @@ int32_t lsm6dsox_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param ctx read / write interface definitions
* @param val change the values of shub_odr in reg slv1_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_sh_data_rate_set(stmdev_ctx_t *ctx, lsm6dsox_shub_odr_t val)
+int32_t lsm6dsox_sh_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dsox_shub_odr_t val)
{
lsm6dsox_slv0_config_t reg;
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.shub_odr = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -8956,36 +10681,47 @@ int32_t lsm6dsox_sh_data_rate_set(stmdev_ctx_t *ctx, lsm6dsox_shub_odr_t val)
*
* @param ctx read / write interface definitions
* @param val Get the values of shub_odr in reg slv1_CONFIG
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_sh_data_rate_get(stmdev_ctx_t *ctx,
- lsm6dsox_shub_odr_t *val)
+ lsm6dsox_shub_odr_t *val)
{
lsm6dsox_slv0_config_t reg;
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t *)®, 1);
}
- if (ret == 0) {
- switch (reg.shub_odr) {
+
+ if (ret == 0)
+ {
+ switch (reg.shub_odr)
+ {
case LSM6DSOX_SH_ODR_104Hz:
*val = LSM6DSOX_SH_ODR_104Hz;
break;
+
case LSM6DSOX_SH_ODR_52Hz:
*val = LSM6DSOX_SH_ODR_52Hz;
break;
+
case LSM6DSOX_SH_ODR_26Hz:
*val = LSM6DSOX_SH_ODR_26Hz;
break;
+
case LSM6DSOX_SH_ODR_13Hz:
*val = LSM6DSOX_SH_ODR_13Hz;
break;
+
default:
*val = LSM6DSOX_SH_ODR_104Hz;
break;
}
+
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -9000,30 +10736,41 @@ int32_t lsm6dsox_sh_data_rate_get(stmdev_ctx_t *ctx,
* - uint8_t slv1_add; 8 bit i2c device address
* - uint8_t slv1_subadd; 8 bit register device address
* - uint8_t slv1_data; 8 bit data to write
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_sh_cfg_write(stmdev_ctx_t *ctx, lsm6dsox_sh_cfg_write_t *val)
+int32_t lsm6dsox_sh_cfg_write(stmdev_ctx_t *ctx,
+ lsm6dsox_sh_cfg_write_t *val)
{
lsm6dsox_slv0_add_t reg;
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.slave0 = val->slv0_add;
reg.rw_0 = 0;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_ADD, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_ADD, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_SUBADD,
- &(val->slv0_subadd), 1);
+ &(val->slv0_subadd), 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_DATAWRITE_SLV0,
- &(val->slv0_data), 1);
+ &(val->slv0_data), 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
+
return ret;
}
@@ -9035,35 +10782,46 @@ int32_t lsm6dsox_sh_cfg_write(stmdev_ctx_t *ctx, lsm6dsox_sh_cfg_write_t *val)
* - uint8_t slv1_add; 8 bit i2c device address
* - uint8_t slv1_subadd; 8 bit register device address
* - uint8_t slv1_len; num of bit to read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
- lsm6dsox_sh_cfg_read_t *val)
+ lsm6dsox_sh_cfg_read_t *val)
{
lsm6dsox_slv0_add_t slv0_add;
lsm6dsox_slv0_config_t slv0_config;
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
slv0_add.slave0 = val->slv_add;
slv0_add.rw_0 = 1;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_ADD, (uint8_t*)&slv0_add, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_ADD, (uint8_t *)&slv0_add, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_SUBADD,
- &(val->slv_subadd), 1);
+ &(val->slv_subadd), 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
slv0_config.slave0_numop = val->slv_len;
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -9078,35 +10836,46 @@ int32_t lsm6dsox_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
* - uint8_t slv1_add; 8 bit i2c device address
* - uint8_t slv1_subadd; 8 bit register device address
* - uint8_t slv1_len; num of bit to read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
- lsm6dsox_sh_cfg_read_t *val)
+ lsm6dsox_sh_cfg_read_t *val)
{
lsm6dsox_slv1_add_t slv1_add;
lsm6dsox_slv1_config_t slv1_config;
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
slv1_add.slave1_add = val->slv_add;
slv1_add.r_1 = 1;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV1_ADD, (uint8_t*)&slv1_add, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV1_ADD, (uint8_t *)&slv1_add, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV1_SUBADD,
- &(val->slv_subadd), 1);
+ &(val->slv_subadd), 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV1_CONFIG,
- (uint8_t*)&slv1_config, 1);
+ (uint8_t *)&slv1_config, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
slv1_config.slave1_numop = val->slv_len;
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV1_CONFIG,
- (uint8_t*)&slv1_config, 1);
+ (uint8_t *)&slv1_config, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -9121,37 +10890,49 @@ int32_t lsm6dsox_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
* - uint8_t slv2_add; 8 bit i2c device address
* - uint8_t slv2_subadd; 8 bit register device address
* - uint8_t slv2_len; num of bit to read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
- lsm6dsox_sh_cfg_read_t *val)
+ lsm6dsox_sh_cfg_read_t *val)
{
lsm6dsox_slv2_add_t slv2_add;
lsm6dsox_slv2_config_t slv2_config;
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
slv2_add.slave2_add = val->slv_add;
slv2_add.r_2 = 1;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV2_ADD, (uint8_t*)&slv2_add, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV2_ADD, (uint8_t *)&slv2_add, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV2_SUBADD,
- &(val->slv_subadd), 1);
+ &(val->slv_subadd), 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV2_CONFIG,
- (uint8_t*)&slv2_config, 1);
+ (uint8_t *)&slv2_config, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
slv2_config.slave2_numop = val->slv_len;
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV2_CONFIG,
- (uint8_t*)&slv2_config, 1);
+ (uint8_t *)&slv2_config, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
+
return ret;
}
@@ -9163,37 +10944,49 @@ int32_t lsm6dsox_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
* - uint8_t slv3_add; 8 bit i2c device address
* - uint8_t slv3_subadd; 8 bit register device address
* - uint8_t slv3_len; num of bit to read
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
- lsm6dsox_sh_cfg_read_t *val)
+ lsm6dsox_sh_cfg_read_t *val)
{
lsm6dsox_slv3_add_t slv3_add;
lsm6dsox_slv3_config_t slv3_config;
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
slv3_add.slave3_add = val->slv_add;
slv3_add.r_3 = 1;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV3_ADD, (uint8_t*)&slv3_add, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV3_ADD, (uint8_t *)&slv3_add, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV3_SUBADD,
- &(val->slv_subadd), 1);
+ &(val->slv_subadd), 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV3_CONFIG,
- (uint8_t*)&slv3_config, 1);
+ (uint8_t *)&slv3_config, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
slv3_config.slave3_numop = val->slv_len;
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV3_CONFIG,
- (uint8_t*)&slv3_config, 1);
+ (uint8_t *)&slv3_config, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
+
return ret;
}
@@ -9202,18 +10995,23 @@ int32_t lsm6dsox_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
*
* @param ctx read / write interface definitions
* @param val union of registers from STATUS_MASTER to
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_sh_status_get(stmdev_ctx_t *ctx,
- lsm6dsox_status_master_t *val)
+ lsm6dsox_status_master_t *val)
{
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_MASTER, (uint8_t*) val, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_MASTER, (uint8_t *) val, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
@@ -9225,7 +11023,7 @@ int32_t lsm6dsox_sh_status_get(stmdev_ctx_t *ctx,
*
*/
- /**
+/**
* @addtogroup Sensors for Smart Mobile Devices
* @brief This section groups all the functions that manage the
* Sensors for Smart Mobile Devices.
@@ -9238,19 +11036,23 @@ int32_t lsm6dsox_sh_status_get(stmdev_ctx_t *ctx,
*
* @param *ctx read / write interface definitions
* @param val change the values of tph_h_sel in LSM6DSOX_S4S_TPH_L
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_s4s_tph_res_set(stmdev_ctx_t *ctx,
- lsm6dsox_s4s_tph_res_t val)
+ lsm6dsox_s4s_tph_res_t val)
{
lsm6dsox_s4s_tph_l_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.tph_h_sel = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -9259,26 +11061,31 @@ int32_t lsm6dsox_s4s_tph_res_set(stmdev_ctx_t *ctx,
*
* @param *ctx read / write interface definitions
* @param val get the values of tph_h_sel in LSM6DSOX_S4S_TPH_L
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_s4s_tph_res_get(stmdev_ctx_t *ctx,
- lsm6dsox_s4s_tph_res_t *val)
+ lsm6dsox_s4s_tph_res_t *val)
{
lsm6dsox_s4s_tph_l_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t*)®, 1);
- switch (reg.tph_h_sel) {
- case LSM6DSOX_S4S_TPH_7bit:
- *val = LSM6DSOX_S4S_TPH_7bit;
- break;
- case LSM6DSOX_S4S_TPH_15bit:
- *val = LSM6DSOX_S4S_TPH_15bit;
- break;
- default:
- *val = LSM6DSOX_S4S_TPH_7bit;
- break;
- }
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t *)®, 1);
+
+ switch (reg.tph_h_sel)
+ {
+ case LSM6DSOX_S4S_TPH_7bit:
+ *val = LSM6DSOX_S4S_TPH_7bit;
+ break;
+
+ case LSM6DSOX_S4S_TPH_15bit:
+ *val = LSM6DSOX_S4S_TPH_15bit;
+ break;
+
+ default:
+ *val = LSM6DSOX_S4S_TPH_7bit;
+ break;
+ }
return ret;
}
@@ -9289,6 +11096,7 @@ int32_t lsm6dsox_s4s_tph_res_get(stmdev_ctx_t *ctx,
* @param *ctx read / write interface definitions
* @param val change the values of tph_l in S4S_TPH_L and
* tph_h in S4S_TPH_H
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_s4s_tph_val_set(stmdev_ctx_t *ctx, uint16_t val)
@@ -9297,18 +11105,29 @@ int32_t lsm6dsox_s4s_tph_val_set(stmdev_ctx_t *ctx, uint16_t val)
lsm6dsox_s4s_tph_h_t s4s_tph_h;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t*)&s4s_tph_l, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_L,
+ (uint8_t *)&s4s_tph_l, 1);
+
+ if (ret == 0)
+ {
s4s_tph_l.tph_l = (uint8_t)(val & 0x007FU);
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t*)&s4s_tph_l, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_TPH_L,
+ (uint8_t *)&s4s_tph_l, 1);
}
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_H, (uint8_t*)&s4s_tph_h, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_H,
+ (uint8_t *)&s4s_tph_h, 1);
s4s_tph_h.tph_h = (uint8_t)(val & 0x7F80U) >> 7;
}
- if (ret == 0) {
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_TPH_H, (uint8_t*)&s4s_tph_h, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_TPH_H,
+ (uint8_t *)&s4s_tph_h, 1);
}
+
return ret;
}
@@ -9318,6 +11137,7 @@ int32_t lsm6dsox_s4s_tph_val_set(stmdev_ctx_t *ctx, uint16_t val)
* @param *ctx read / write interface definitions
* @param val get the values of tph_l in S4S_TPH_L and
* tph_h in S4S_TPH_H
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_s4s_tph_val_get(stmdev_ctx_t *ctx, uint16_t *val)
@@ -9326,13 +11146,18 @@ int32_t lsm6dsox_s4s_tph_val_get(stmdev_ctx_t *ctx, uint16_t *val)
lsm6dsox_s4s_tph_h_t s4s_tph_h;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t*)&s4s_tph_l, 1);
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_H, (uint8_t*)&s4s_tph_h, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_L,
+ (uint8_t *)&s4s_tph_l, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_H,
+ (uint8_t *)&s4s_tph_h, 1);
*val = s4s_tph_h.tph_h;
*val = *val << 7;
*val += s4s_tph_l.tph_l;
}
+
return ret;
}
@@ -9342,19 +11167,23 @@ int32_t lsm6dsox_s4s_tph_val_get(stmdev_ctx_t *ctx, uint16_t *val)
*
* @param *ctx read / write interface definitions.
* @param val change the values of rr in S4S_RR.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_s4s_res_ratio_set(stmdev_ctx_t *ctx,
- lsm6dsox_s4s_res_ratio_t val)
+ lsm6dsox_s4s_res_ratio_t val)
{
lsm6dsox_s4s_rr_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_RR, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_RR, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.rr = (uint8_t)val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_RR, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_RR, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -9364,32 +11193,40 @@ int32_t lsm6dsox_s4s_res_ratio_set(stmdev_ctx_t *ctx,
*
* @param *ctx read / write interface definitions
* @param val get the values of rr in S4S_RR
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_s4s_res_ratio_get(stmdev_ctx_t *ctx,
- lsm6dsox_s4s_res_ratio_t *val)
+ lsm6dsox_s4s_res_ratio_t *val)
{
lsm6dsox_s4s_rr_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_RR, (uint8_t*)®, 1);
- switch (reg.rr) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_RR, (uint8_t *)®, 1);
+
+ switch (reg.rr)
+ {
case LSM6DSOX_S4S_DT_RES_11:
*val = LSM6DSOX_S4S_DT_RES_11;
break;
+
case LSM6DSOX_S4S_DT_RES_12:
*val = LSM6DSOX_S4S_DT_RES_12;
break;
+
case LSM6DSOX_S4S_DT_RES_13:
*val = LSM6DSOX_S4S_DT_RES_13;
break;
+
case LSM6DSOX_S4S_DT_RES_14:
*val = LSM6DSOX_S4S_DT_RES_14;
break;
+
default:
*val = LSM6DSOX_S4S_DT_RES_11;
break;
}
+
return ret;
}
@@ -9398,6 +11235,7 @@ int32_t lsm6dsox_s4s_res_ratio_get(stmdev_ctx_t *ctx,
*
* @param *ctx read / write interface definitions.
* @param val change the values of S4S_ST_CMD_CODE.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_s4s_command_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -9405,12 +11243,16 @@ int32_t lsm6dsox_s4s_command_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_s4s_st_cmd_code_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_ST_CMD_CODE, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_ST_CMD_CODE,
+ (uint8_t *)®, 1);
- if (ret == 0) {
+ if (ret == 0)
+ {
reg.s4s_st_cmd_code = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_ST_CMD_CODE, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_ST_CMD_CODE,
+ (uint8_t *)®, 1);
}
+
return ret;
}
@@ -9419,6 +11261,7 @@ int32_t lsm6dsox_s4s_command_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param *ctx read / write interface definitions.
* @param val get the values of S4S_ST_CMD_CODE.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_s4s_command_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -9426,7 +11269,8 @@ int32_t lsm6dsox_s4s_command_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_s4s_st_cmd_code_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_ST_CMD_CODE, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_ST_CMD_CODE,
+ (uint8_t *)®, 1);
*val = reg.s4s_st_cmd_code;
return ret;
@@ -9437,6 +11281,7 @@ int32_t lsm6dsox_s4s_command_get(stmdev_ctx_t *ctx, uint8_t *val)
*
* @param *ctx read / write interface definitions.
* @param val change the values of S4S_DT_REG.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_s4s_dt_set(stmdev_ctx_t *ctx, uint8_t val)
@@ -9444,11 +11289,14 @@ int32_t lsm6dsox_s4s_dt_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsox_s4s_dt_reg_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_DT_REG, (uint8_t*)®, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_DT_REG, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.dt = val;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_DT_REG, (uint8_t*)®, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_DT_REG, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -9457,6 +11305,7 @@ int32_t lsm6dsox_s4s_dt_set(stmdev_ctx_t *ctx, uint8_t val)
*
* @param *ctx read / write interface definitions.
* @param val get the values of S4S_DT_REG.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_s4s_dt_get(stmdev_ctx_t *ctx, uint8_t *val)
@@ -9464,7 +11313,7 @@ int32_t lsm6dsox_s4s_dt_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsox_s4s_dt_reg_t reg;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_DT_REG, (uint8_t*)®, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_DT_REG, (uint8_t *)®, 1);
*val = reg.dt;
return ret;
@@ -9486,12 +11335,13 @@ int32_t lsm6dsox_s4s_dt_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @brief Device "Who am I".[get]
*
- * @param ctx communication interface handler. Use NULL to ingnore
+ * @param ctx communication interface handler. Use NULL to ignore
* this interface.(ptr)
* @param aux_ctx auxiliary communication interface handler. Use NULL
- * to ingnore this interface.(ptr)
+ * to ignore this interface.(ptr)
* @param val ID values read from the two interfaces. ID values
* will be the same.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_id_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
@@ -9499,16 +11349,21 @@ int32_t lsm6dsox_id_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
{
int32_t ret = 0;
- if (ctx != NULL){
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WHO_AM_I,
- (uint8_t*)&(val->ui), 1);
+ if (ctx != NULL)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WHO_AM_I,
+ (uint8_t *) & (val->ui), 1);
}
- if (aux_ctx != NULL){
- if (ret == 0) {
+
+ if (aux_ctx != NULL)
+ {
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_WHO_AM_I,
- (uint8_t*)&(val->aux), 1);
+ (uint8_t *) & (val->aux), 1);
}
}
+
return ret;
}
@@ -9518,8 +11373,9 @@ int32_t lsm6dsox_id_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
* @param ctx communication interface handler.(ptr)
* @param val re-initialization mode. Refer to datasheet
* and application note for more information
- * about differencies beetween boot and sw_reset
+ * about differencies between boot and sw_reset
* procedure.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_init_set(stmdev_ctx_t *ctx, lsm6dsox_init_t val)
@@ -9530,52 +11386,68 @@ int32_t lsm6dsox_init_set(stmdev_ctx_t *ctx, lsm6dsox_init_t val)
int32_t ret;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B,
- (uint8_t*)&emb_func_init_b, 1);
+ (uint8_t *)&emb_func_init_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
emb_func_init_b.fifo_compr_init = (uint8_t)val
- & ( (uint8_t)LSM6DSOX_FIFO_COMP >> 2 );
+ & ((uint8_t)LSM6DSOX_FIFO_COMP >> 2);
emb_func_init_b.fsm_init = (uint8_t)val
- & ( (uint8_t)LSM6DSOX_FSM >> 3 );
+ & ((uint8_t)LSM6DSOX_FSM >> 3);
emb_func_init_b.mlc_init = (uint8_t)val
- & ( (uint8_t)LSM6DSOX_MLC >> 4 );
+ & ((uint8_t)LSM6DSOX_MLC >> 4);
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B,
- (uint8_t*)&emb_func_init_b, 1);
+ (uint8_t *)&emb_func_init_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_A,
- (uint8_t*)&emb_func_init_a, 1);
- }
- if (ret == 0) {
- emb_func_init_a.step_det_init = ( (uint8_t)val
- & (uint8_t)LSM6DSOX_PEDO ) >> 5;
- emb_func_init_a.tilt_init = ( (uint8_t)val
- & (uint8_t)LSM6DSOX_TILT ) >> 6;
- emb_func_init_a.sig_mot_init = ( (uint8_t)val
- & (uint8_t)LSM6DSOX_SMOTION ) >> 7;
+ (uint8_t *)&emb_func_init_a, 1);
+ }
+
+ if (ret == 0)
+ {
+ emb_func_init_a.step_det_init = ((uint8_t)val
+ & (uint8_t)LSM6DSOX_PEDO) >> 5;
+ emb_func_init_a.tilt_init = ((uint8_t)val
+ & (uint8_t)LSM6DSOX_TILT) >> 6;
+ emb_func_init_a.sig_mot_init = ((uint8_t)val
+ & (uint8_t)LSM6DSOX_SMOTION) >> 7;
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_A,
- (uint8_t*)&emb_func_init_a, 1);
+ (uint8_t *)&emb_func_init_a, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
- if ( ( (val == LSM6DSOX_BOOT) || (val == LSM6DSOX_RESET) ) && (ret == 0) ) {
+
+ if (((val == LSM6DSOX_BOOT) || (val == LSM6DSOX_RESET)) &&
+ (ret == 0))
+ {
ctrl3_c.boot = (uint8_t)val & (uint8_t)LSM6DSOX_BOOT;
- ctrl3_c.sw_reset = ( (uint8_t)val & (uint8_t)LSM6DSOX_RESET) >> 1;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ctrl3_c.sw_reset = ((uint8_t)val & (uint8_t)LSM6DSOX_RESET) >> 1;
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
- if ( ( val == LSM6DSOX_DRV_RDY )
- && ( (ctrl3_c.bdu == PROPERTY_DISABLE)
- || (ctrl3_c.if_inc == PROPERTY_DISABLE) ) && (ret == 0) ) {
+
+ if ((val == LSM6DSOX_DRV_RDY)
+ && ((ctrl3_c.bdu == PROPERTY_DISABLE)
+ || (ctrl3_c.if_inc == PROPERTY_DISABLE)) && (ret == 0))
+ {
ctrl3_c.bdu = PROPERTY_ENABLE;
ctrl3_c.if_inc = PROPERTY_ENABLE;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
return ret;
@@ -9584,15 +11456,17 @@ int32_t lsm6dsox_init_set(stmdev_ctx_t *ctx, lsm6dsox_init_t val)
/**
* @brief Configures the bus operating mode.[set]
*
- * @param ctx communication interface handler. Use NULL to ingnore
+ * @param ctx communication interface handler. Use NULL to ignore
* this interface.(ptr)
* @param aux_ctx auxiliary communication interface handler. Use NULL
- * to ingnore this interface.(ptr)
+ * to ignore this interface.(ptr)
* @param val configures the bus operating mode for both the
* main and the auxiliary interface.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_bus_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
+int32_t lsm6dsox_bus_mode_set(stmdev_ctx_t *ctx,
+ stmdev_ctx_t *aux_ctx,
lsm6dsox_bus_mode_t val)
{
lsm6dsox_spi2_ctrl1_ois_t spi2_ctrl1_ois;
@@ -9605,80 +11479,100 @@ int32_t lsm6dsox_bus_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
ret = 0;
- if (aux_ctx != NULL) {
+ if (aux_ctx != NULL)
+ {
ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_CTRL1_OIS,
- (uint8_t*)&spi2_ctrl1_ois, 1);
+ (uint8_t *)&spi2_ctrl1_ois, 1);
+ bit_val = ((uint8_t)val.aux_bus_md & 0x04U) >> 2;
- bit_val = ( (uint8_t)val.aux_bus_md & 0x04U ) >> 2;
- if ( ( ret == 0 ) && ( spi2_ctrl1_ois.sim_ois != bit_val ) ) {
+ if ((ret == 0) && (spi2_ctrl1_ois.sim_ois != bit_val))
+ {
spi2_ctrl1_ois.sim_ois = bit_val;
ret = lsm6dsox_write_reg(aux_ctx, LSM6DSOX_SPI2_CTRL1_OIS,
- (uint8_t*)&spi2_ctrl1_ois, 1);
+ (uint8_t *)&spi2_ctrl1_ois, 1);
}
}
- if (ctx != NULL) {
- if (ret == 0) {
+ if (ctx != NULL)
+ {
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
+ (uint8_t *)&ctrl9_xl, 1);
}
bit_val = ((uint8_t)val.ui_bus_md & 0x04U) >> 2;
- if ( ( ret == 0 ) && ( ctrl9_xl.i3c_disable != bit_val ) ) {
+
+ if ((ret == 0) && (ctrl9_xl.i3c_disable != bit_val))
+ {
ctrl9_xl.i3c_disable = bit_val;
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
+ (uint8_t *)&ctrl9_xl, 1);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
}
bit_val = ((uint8_t)val.ui_bus_md & 0x30U) >> 4;
- if ( ( ret == 0 ) && ( i3c_bus_avb.i3c_bus_avb_sel != bit_val ) ) {
+
+ if ((ret == 0) && (i3c_bus_avb.i3c_bus_avb_sel != bit_val))
+ {
i3c_bus_avb.i3c_bus_avb_sel = bit_val;
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C,
- (uint8_t*)&ctrl4_c, 1);
+ (uint8_t *)&ctrl4_c, 1);
}
- bit_val = ( (uint8_t)val.ui_bus_md & 0x02U ) >> 1;
- if ( ( ret == 0 ) && ( ctrl4_c.i2c_disable != bit_val ) ) {
+
+ bit_val = ((uint8_t)val.ui_bus_md & 0x02U) >> 1;
+
+ if ((ret == 0) && (ctrl4_c.i2c_disable != bit_val))
+ {
ctrl4_c.i2c_disable = bit_val;
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C,
- (uint8_t*)&ctrl4_c, 1);
+ (uint8_t *)&ctrl4_c, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C,
- (uint8_t*)&ctrl3_c, 1);
+ (uint8_t *)&ctrl3_c, 1);
}
+
bit_val = (uint8_t)val.ui_bus_md & 0x01U;
- if ( ( ret == 0 ) && ( ctrl3_c.sim != bit_val ) ) {
+
+ if ((ret == 0) && (ctrl3_c.sim != bit_val))
+ {
ctrl3_c.sim = bit_val;
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C,
- (uint8_t*)&ctrl3_c, 1);
+ (uint8_t *)&ctrl3_c, 1);
}
}
return ret;
-
}
/**
* @brief Get the bus operating mode.[get]
*
- * @param ctx communication interface handler. Use NULL to ingnore
+ * @param ctx communication interface handler. Use NULL to ignore
* this interface.(ptr)
* @param aux_ctx auxiliary communication interface handler. Use NULL
- * to ingnore this interface.(ptr)
+ * to ignore this interface.(ptr)
* @param val retrieves the bus operating mode for both the main
* and the auxiliary interface.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_bus_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
+int32_t lsm6dsox_bus_mode_get(stmdev_ctx_t *ctx,
+ stmdev_ctx_t *aux_ctx,
lsm6dsox_bus_mode_t *val)
{
lsm6dsox_spi2_ctrl1_ois_t spi2_ctrl1_ois;
@@ -9686,86 +11580,109 @@ int32_t lsm6dsox_bus_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
lsm6dsox_ctrl9_xl_t ctrl9_xl;
lsm6dsox_ctrl3_c_t ctrl3_c;
lsm6dsox_ctrl4_c_t ctrl4_c;
-
int32_t ret = 0;
- if (aux_ctx != NULL) {
+ if (aux_ctx != NULL)
+ {
ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_CTRL1_OIS,
- (uint8_t*)&spi2_ctrl1_ois, 1);
- switch ( spi2_ctrl1_ois.sim_ois ) {
+ (uint8_t *)&spi2_ctrl1_ois, 1);
+
+ switch (spi2_ctrl1_ois.sim_ois)
+ {
case LSM6DSOX_SPI_4W_AUX:
val->aux_bus_md = LSM6DSOX_SPI_4W_AUX;
break;
+
case LSM6DSOX_SPI_3W_AUX:
val->aux_bus_md = LSM6DSOX_SPI_3W_AUX;
break;
+
default:
val->aux_bus_md = LSM6DSOX_SPI_4W_AUX;
break;
}
}
- if (ctx != NULL) {
- if (ret == 0) {
+ if (ctx != NULL)
+ {
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
+ (uint8_t *)&ctrl9_xl, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C,
- (uint8_t*)&ctrl4_c, 1);
+ (uint8_t *)&ctrl4_c, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C,
- (uint8_t*)&ctrl3_c, 1);
+ (uint8_t *)&ctrl3_c, 1);
- switch ( ( i3c_bus_avb.i3c_bus_avb_sel << 4 ) &
- ( ctrl9_xl.i3c_disable << 2 ) &
- ( ctrl4_c.i2c_disable << 1) & ctrl3_c.sim ) {
+ switch ((i3c_bus_avb.i3c_bus_avb_sel << 4) &
+ (ctrl9_xl.i3c_disable << 2) &
+ (ctrl4_c.i2c_disable << 1) & ctrl3_c.sim)
+ {
case LSM6DSOX_SEL_BY_HW:
val->ui_bus_md = LSM6DSOX_SEL_BY_HW;
break;
+
case LSM6DSOX_SPI_4W:
val->ui_bus_md = LSM6DSOX_SPI_4W;
break;
+
case LSM6DSOX_SPI_3W:
val->ui_bus_md = LSM6DSOX_SPI_3W;
break;
+
case LSM6DSOX_I2C:
val->ui_bus_md = LSM6DSOX_I2C;
break;
+
case LSM6DSOX_I3C_T_50us:
val->ui_bus_md = LSM6DSOX_I3C_T_50us;
break;
+
case LSM6DSOX_I3C_T_2us:
val->ui_bus_md = LSM6DSOX_I3C_T_2us;
break;
+
case LSM6DSOX_I3C_T_1ms:
val->ui_bus_md = LSM6DSOX_I3C_T_1ms;
break;
+
case LSM6DSOX_I3C_T_25ms:
val->ui_bus_md = LSM6DSOX_I3C_T_25ms;
break;
+
default:
val->ui_bus_md = LSM6DSOX_SEL_BY_HW;
break;
}
}
}
+
return ret;
}
/**
* @brief Get the status of the device.[get]
*
- * @param ctx communication interface handler. Use NULL to ingnore
+ * @param ctx communication interface handler. Use NULL to ignore
* this interface.(ptr)
* @param aux_ctx auxiliary communication interface handler. Use NULL
- * to ingnore this interface.(ptr)
+ * to ignore this interface.(ptr)
* @param val the status of the device.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_status_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
@@ -9776,40 +11693,46 @@ int32_t lsm6dsox_status_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
lsm6dsox_status_reg_t status_reg;
lsm6dsox_ctrl3_c_t ctrl3_c;
int32_t ret;
-
ret = 0;
- if (aux_ctx != NULL){
+ if (aux_ctx != NULL)
+ {
ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_STATUS_REG_OIS,
- (uint8_t*)&spi2_status_reg_ois, 1);
+ (uint8_t *)&spi2_status_reg_ois, 1);
val->ois_drdy_xl = spi2_status_reg_ois.xlda;
val->ois_drdy_g = spi2_status_reg_ois.gda;
val->ois_gyro_settling = spi2_status_reg_ois.gyro_settling;
}
- if (ctx != NULL){
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ if (ctx != NULL)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
val->sw_reset = ctrl3_c.sw_reset;
val->boot = ctrl3_c.boot;
- if ( (ret == 0) && ( ctrl3_c.sw_reset == PROPERTY_DISABLE ) &&
- ( ctrl3_c.boot == PROPERTY_DISABLE ) ) {
+ if ((ret == 0) && (ctrl3_c.sw_reset == PROPERTY_DISABLE) &&
+ (ctrl3_c.boot == PROPERTY_DISABLE))
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG,
- (uint8_t*)&status_reg, 1);
+ (uint8_t *)&status_reg, 1);
val->drdy_xl = status_reg.xlda;
val->drdy_g = status_reg.gda;
val->drdy_temp = status_reg.tda;
}
- if (aux_ctx == NULL){
- if (ret == 0) {
+
+ if (aux_ctx == NULL)
+ {
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_STATUS_REG_OIS,
- (uint8_t*)&ui_status_reg_ois, 1);
+ (uint8_t *)&ui_status_reg_ois, 1);
val->ois_drdy_xl = ui_status_reg_ois.xlda;
val->ois_drdy_g = ui_status_reg_ois.gda;
val->ois_gyro_settling = ui_status_reg_ois.gyro_settling;
}
}
}
+
return ret;
}
@@ -9819,37 +11742,50 @@ int32_t lsm6dsox_status_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
* @param ctx communication interface handler.(ptr)
* @param val the electrical settings for the configurable
* pins.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_pin_conf_set(stmdev_ctx_t *ctx, lsm6dsox_pin_conf_t val)
+int32_t lsm6dsox_pin_conf_set(stmdev_ctx_t *ctx,
+ lsm6dsox_pin_conf_t val)
{
lsm6dsox_i3c_bus_avb_t i3c_bus_avb;
lsm6dsox_pin_ctrl_t pin_ctrl;
lsm6dsox_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
+
+ if (ret == 0)
+ {
pin_ctrl.ois_pu_dis = ~val.aux_sdo_ocs_pull_up;
pin_ctrl.sdo_pu_en = val.sdo_sa0_pull_up;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
}
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ctrl3_c.pp_od = ~val.int1_int2_push_pull;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
i3c_bus_avb.pd_dis_int1 = ~val.int1_pull_down;
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
}
+
return ret;
}
@@ -9859,29 +11795,38 @@ int32_t lsm6dsox_pin_conf_set(stmdev_ctx_t *ctx, lsm6dsox_pin_conf_t val)
* @param ctx communication interface handler.(ptr)
* @param val the electrical settings for the configurable
* pins.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_pin_conf_get(stmdev_ctx_t *ctx, lsm6dsox_pin_conf_t *val)
+int32_t lsm6dsox_pin_conf_get(stmdev_ctx_t *ctx,
+ lsm6dsox_pin_conf_t *val)
{
lsm6dsox_i3c_bus_avb_t i3c_bus_avb;
lsm6dsox_pin_ctrl_t pin_ctrl;
lsm6dsox_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
+
+ if (ret == 0)
+ {
val->aux_sdo_ocs_pull_up = ~pin_ctrl.ois_pu_dis;
val->aux_sdo_ocs_pull_up = pin_ctrl.sdo_pu_en;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
val->int1_int2_push_pull = ~ctrl3_c.pp_od;
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
val->int1_pull_down = ~i3c_bus_avb.pd_dis_int1;
}
+
return ret;
}
@@ -9890,6 +11835,7 @@ int32_t lsm6dsox_pin_conf_get(stmdev_ctx_t *ctx, lsm6dsox_pin_conf_t *val)
*
* @param ctx communication interface handler.(ptr)
* @param val the pins hardware signal settings.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_interrupt_mode_set(stmdev_ctx_t *ctx,
@@ -9900,32 +11846,48 @@ int32_t lsm6dsox_interrupt_mode_set(stmdev_ctx_t *ctx,
lsm6dsox_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.h_lactive = val.active_low;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
tap_cfg0.lir = val.base_latched;
tap_cfg0.int_clr_on_read = val.base_latched | val.emb_latched;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0,
+ (uint8_t *) &tap_cfg0, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
}
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_rw.emb_func_lir = val.emb_latched;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
+
return ret;
}
@@ -9934,6 +11896,7 @@ int32_t lsm6dsox_interrupt_mode_set(stmdev_ctx_t *ctx,
*
* @param ctx communication interface handler.(ptr)
* @param val the pins hardware signal settings.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_interrupt_mode_get(stmdev_ctx_t *ctx,
@@ -9944,26 +11907,37 @@ int32_t lsm6dsox_interrupt_mode_get(stmdev_ctx_t *ctx,
lsm6dsox_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if (ret == 0) {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
ctrl3_c.h_lactive = val->active_low;
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
tap_cfg0.lir = val->base_latched;
tap_cfg0.int_clr_on_read = val->base_latched | val->emb_latched;
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
}
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
page_rw.emb_func_lir = val->emb_latched;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
+
return ret;
}
@@ -9972,6 +11946,7 @@ int32_t lsm6dsox_interrupt_mode_get(stmdev_ctx_t *ctx,
*
* @param ctx communication interface handler.(ptr)
* @param val the signals to route on int1 pin.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_pin_int1_route_set(stmdev_ctx_t *ctx,
@@ -9989,7 +11964,6 @@ int32_t lsm6dsox_pin_int1_route_set(stmdev_ctx_t *ctx,
lsm6dsox_md1_cfg_t md1_cfg;
lsm6dsox_ctrl4_c_t ctrl4_c;
int32_t ret;
-
int1_ctrl.int1_drdy_xl = val.drdy_xl;
int1_ctrl.int1_drdy_g = val.drdy_g;
int1_ctrl.int1_boot = val.boot;
@@ -9998,7 +11972,6 @@ int32_t lsm6dsox_pin_int1_route_set(stmdev_ctx_t *ctx,
int1_ctrl.int1_fifo_full = val.fifo_full;
int1_ctrl.int1_cnt_bdr = val.fifo_bdr;
int1_ctrl.den_drdy_flag = val.den_flag;
-
md1_cfg.int1_shub = val.sh_endop;
md1_cfg.int1_6d = val.six_d;
md1_cfg.int1_double_tap = val.double_tap;
@@ -10006,12 +11979,12 @@ int32_t lsm6dsox_pin_int1_route_set(stmdev_ctx_t *ctx,
md1_cfg.int1_wu = val.wake_up;
md1_cfg.int1_single_tap = val.single_tap;
md1_cfg.int1_sleep_change = val.sleep_change;
-
+ emb_func_int1.not_used_01 = 0;
emb_func_int1.int1_step_detector = val.step_detector;
emb_func_int1.int1_tilt = val.tilt;
emb_func_int1.int1_sig_mot = val.sig_mot;
+ emb_func_int1.not_used_02 = 0;
emb_func_int1.int1_fsm_lc = val.fsm_lc;
-
fsm_int1_a.int1_fsm1 = val.fsm1;
fsm_int1_a.int1_fsm2 = val.fsm2;
fsm_int1_a.int1_fsm3 = val.fsm3;
@@ -10020,7 +11993,6 @@ int32_t lsm6dsox_pin_int1_route_set(stmdev_ctx_t *ctx,
fsm_int1_a.int1_fsm6 = val.fsm6;
fsm_int1_a.int1_fsm7 = val.fsm7;
fsm_int1_a.int1_fsm8 = val.fsm8;
-
fsm_int1_b.int1_fsm9 = val.fsm9 ;
fsm_int1_b.int1_fsm10 = val.fsm10;
fsm_int1_b.int1_fsm11 = val.fsm11;
@@ -10029,7 +12001,6 @@ int32_t lsm6dsox_pin_int1_route_set(stmdev_ctx_t *ctx,
fsm_int1_b.int1_fsm14 = val.fsm14;
fsm_int1_b.int1_fsm15 = val.fsm15;
fsm_int1_b.int1_fsm16 = val.fsm16;
-
mlc_int1.int1_mlc1 = val.mlc1;
mlc_int1.int1_mlc2 = val.mlc2;
mlc_int1.int1_mlc3 = val.mlc3;
@@ -10038,43 +12009,60 @@ int32_t lsm6dsox_pin_int1_route_set(stmdev_ctx_t *ctx,
mlc_int1.int1_mlc6 = val.mlc6;
mlc_int1.int1_mlc7 = val.mlc7;
mlc_int1.int1_mlc8 = val.mlc8;
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if (ret == 0) {
- if( ( val.drdy_temp | val.timestamp ) != PROPERTY_DISABLE) {
+ if (ret == 0)
+ {
+ if ((val.drdy_temp | val.timestamp) != PROPERTY_DISABLE)
+ {
ctrl4_c.int2_on_int1 = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
ctrl4_c.int2_on_int1 = PROPERTY_DISABLE;
}
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MLC_INT1,
- (uint8_t*)&mlc_int1, 1);
+ (uint8_t *)&mlc_int1, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INT1,
- (uint8_t*)&emb_func_int1, 1);
+ (uint8_t *)&emb_func_int1, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT1_A,
- (uint8_t*)&fsm_int1_a, 1);
+ (uint8_t *)&fsm_int1_a, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT1_B,
- (uint8_t*)&fsm_int1_b, 1);
+ (uint8_t *)&fsm_int1_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
- if (ret == 0) {
- if ( ( emb_func_int1.int1_fsm_lc
+ if (ret == 0)
+ {
+ if ((emb_func_int1.int1_fsm_lc
| emb_func_int1.int1_sig_mot
| emb_func_int1.int1_step_detector
| emb_func_int1.int1_tilt
@@ -10101,42 +12089,62 @@ int32_t lsm6dsox_pin_int1_route_set(stmdev_ctx_t *ctx,
| mlc_int1.int1_mlc5
| mlc_int1.int1_mlc6
| mlc_int1.int1_mlc7
- | mlc_int1.int1_mlc8) != PROPERTY_DISABLE){
+ | mlc_int1.int1_mlc8) != PROPERTY_DISABLE)
+ {
md1_cfg.int1_emb_func = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
md1_cfg.int1_emb_func = PROPERTY_DISABLE;
}
+
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT1_CTRL,
- (uint8_t*)&int1_ctrl, 1);
+ (uint8_t *)&int1_ctrl, 1);
}
- if (ret == 0) {
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MD1_CFG, (uint8_t*)&md1_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MD1_CFG, (uint8_t *)&md1_cfg, 1);
}
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT2_CTRL,
+ (uint8_t *)&int2_ctrl, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
int2_ctrl.int2_drdy_temp = val.drdy_temp;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT2_CTRL,
+ (uint8_t *)&int2_ctrl, 1);
}
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MD2_CFG, (uint8_t*)&md2_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MD2_CFG, (uint8_t *)&md2_cfg, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
md2_cfg.int2_timestamp = val.timestamp;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MD2_CFG, (uint8_t*)&md2_cfg, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MD2_CFG, (uint8_t *)&md2_cfg, 1);
}
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_pin_int2_route_get(ctx, NULL, &pin_int2_route);
}
- if (ret == 0) {
- if ( ( pin_int2_route.fifo_bdr
+
+ if (ret == 0)
+ {
+ if ((pin_int2_route.fifo_bdr
| pin_int2_route.drdy_g
| pin_int2_route.drdy_temp
| pin_int2_route.drdy_xl
@@ -10163,14 +12171,20 @@ int32_t lsm6dsox_pin_int1_route_set(stmdev_ctx_t *ctx,
| md1_cfg.int1_ff
| md1_cfg.int1_wu
| md1_cfg.int1_single_tap
- | md1_cfg.int1_sleep_change) != PROPERTY_DISABLE) {
+ | md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
+ {
tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
}
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
+
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG2,
+ (uint8_t *) &tap_cfg2, 1);
}
+
return ret;
}
@@ -10179,6 +12193,7 @@ int32_t lsm6dsox_pin_int1_route_set(stmdev_ctx_t *ctx,
*
* @param ctx communication interface handler.(ptr)
* @param val the signals that are routed on int1 pin.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_pin_int1_route_get(stmdev_ctx_t *ctx,
@@ -10194,48 +12209,71 @@ int32_t lsm6dsox_pin_int1_route_get(stmdev_ctx_t *ctx,
lsm6dsox_md1_cfg_t md1_cfg;
lsm6dsox_ctrl4_c_t ctrl4_c;
int32_t ret;
-
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MLC_INT1,
- (uint8_t*)&mlc_int1, 1);
+ (uint8_t *)&mlc_int1, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INT1,
- (uint8_t*)&emb_func_int1, 1);
+ (uint8_t *)&emb_func_int1, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_INT1_A,
- (uint8_t*)&fsm_int1_a, 1);
+ (uint8_t *)&fsm_int1_a, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_INT1_B,
- (uint8_t*)&fsm_int1_b, 1);
+ (uint8_t *)&fsm_int1_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT1_CTRL,
- (uint8_t*)&int1_ctrl, 1);
+ (uint8_t *)&int1_ctrl, 1);
}
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MD1_CFG, (uint8_t*)&md1_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MD1_CFG, (uint8_t *)&md1_cfg, 1);
}
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
- if (ctrl4_c.int2_on_int1 == PROPERTY_ENABLE){
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+
+ if (ctrl4_c.int2_on_int1 == PROPERTY_ENABLE)
+ {
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT2_CTRL,
+ (uint8_t *)&int2_ctrl, 1);
val->drdy_temp = int2_ctrl.int2_drdy_temp;
}
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MD2_CFG, (uint8_t*)&md2_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MD2_CFG, (uint8_t *)&md2_cfg, 1);
val->timestamp = md2_cfg.int2_timestamp;
}
}
- else {
+
+ else
+ {
val->drdy_temp = PROPERTY_DISABLE;
val->timestamp = PROPERTY_DISABLE;
}
@@ -10248,7 +12286,6 @@ int32_t lsm6dsox_pin_int1_route_get(stmdev_ctx_t *ctx,
val->fifo_full = int1_ctrl.int1_fifo_full;
val->fifo_bdr = int1_ctrl.int1_cnt_bdr;
val->den_flag = int1_ctrl.den_drdy_flag;
-
val->sh_endop = md1_cfg.int1_shub;
val->six_d = md1_cfg.int1_6d;
val->double_tap = md1_cfg.int1_double_tap;
@@ -10256,12 +12293,10 @@ int32_t lsm6dsox_pin_int1_route_get(stmdev_ctx_t *ctx,
val->wake_up = md1_cfg.int1_wu;
val->single_tap = md1_cfg.int1_single_tap;
val->sleep_change = md1_cfg.int1_sleep_change;
-
val->step_detector = emb_func_int1.int1_step_detector;
val->tilt = emb_func_int1.int1_tilt;
val->sig_mot = emb_func_int1.int1_sig_mot;
val->fsm_lc = emb_func_int1.int1_fsm_lc;
-
val->fsm1 = fsm_int1_a.int1_fsm1;
val->fsm2 = fsm_int1_a.int1_fsm2;
val->fsm3 = fsm_int1_a.int1_fsm3;
@@ -10270,7 +12305,6 @@ int32_t lsm6dsox_pin_int1_route_get(stmdev_ctx_t *ctx,
val->fsm6 = fsm_int1_a.int1_fsm6;
val->fsm7 = fsm_int1_a.int1_fsm7;
val->fsm8 = fsm_int1_a.int1_fsm8;
-
val->fsm9 = fsm_int1_b.int1_fsm9;
val->fsm10 = fsm_int1_b.int1_fsm10;
val->fsm11 = fsm_int1_b.int1_fsm11;
@@ -10279,7 +12313,6 @@ int32_t lsm6dsox_pin_int1_route_get(stmdev_ctx_t *ctx,
val->fsm14 = fsm_int1_b.int1_fsm14;
val->fsm15 = fsm_int1_b.int1_fsm15;
val->fsm16 = fsm_int1_b.int1_fsm16;
-
val->mlc1 = mlc_int1.int1_mlc1;
val->mlc2 = mlc_int1.int1_mlc2;
val->mlc3 = mlc_int1.int1_mlc3;
@@ -10295,14 +12328,16 @@ int32_t lsm6dsox_pin_int1_route_get(stmdev_ctx_t *ctx,
/**
* @brief Route interrupt signals on int2 pin.[set]
*
- * @param ctx communication interface handler. Use NULL to ingnore
+ * @param ctx communication interface handler. Use NULL to ignore
* this interface.(ptr)
* @param aux_ctx auxiliary communication interface handler. Use NULL
- * to ingnore this interface.(ptr)
+ * to ignore this interface.(ptr)
* @param val the signals to route on int2 pin.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_pin_int2_route_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
+int32_t lsm6dsox_pin_int2_route_set(stmdev_ctx_t *ctx,
+ stmdev_ctx_t *aux_ctx,
lsm6dsox_pin_int2_route_t val)
{
lsm6dsox_pin_int1_route_t pin_int1_route;
@@ -10316,20 +12351,23 @@ int32_t lsm6dsox_pin_int2_route_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
lsm6dsox_md2_cfg_t md2_cfg;
lsm6dsox_ctrl4_c_t ctrl4_c;
int32_t ret;
-
ret = 0;
- if( aux_ctx != NULL ) {
+ if (aux_ctx != NULL)
+ {
ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_INT_OIS,
- (uint8_t*)&spi2_int_ois, 1);
- if (ret == 0) {
+ (uint8_t *)&spi2_int_ois, 1);
+
+ if (ret == 0)
+ {
spi2_int_ois.int2_drdy_ois = val.drdy_ois;
ret = lsm6dsox_write_reg(aux_ctx, LSM6DSOX_SPI2_INT_OIS,
- (uint8_t*)&spi2_int_ois, 1);
+ (uint8_t *)&spi2_int_ois, 1);
}
}
- if( ctx != NULL ) {
+ if (ctx != NULL)
+ {
int2_ctrl.int2_drdy_xl = val.drdy_xl;
int2_ctrl.int2_drdy_g = val.drdy_g;
int2_ctrl.int2_drdy_temp = val.drdy_temp;
@@ -10337,7 +12375,7 @@ int32_t lsm6dsox_pin_int2_route_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
int2_ctrl.int2_fifo_ovr = val.fifo_ovr;
int2_ctrl.int2_fifo_full = val.fifo_full;
int2_ctrl.int2_cnt_bdr = val.fifo_bdr;
-
+ int2_ctrl.not_used_01 = 0;
md2_cfg.int2_timestamp = val.timestamp;
md2_cfg.int2_6d = val.six_d;
md2_cfg.int2_double_tap = val.double_tap;
@@ -10345,11 +12383,12 @@ int32_t lsm6dsox_pin_int2_route_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
md2_cfg.int2_wu = val.wake_up;
md2_cfg.int2_single_tap = val.single_tap;
md2_cfg.int2_sleep_change = val.sleep_change;
-
+ emb_func_int2.not_used_01 = 0;
emb_func_int2. int2_step_detector = val.step_detector;
emb_func_int2.int2_tilt = val.tilt;
+ emb_func_int2.int2_sig_mot = val.sig_mot;
+ emb_func_int2.not_used_02 = 0;
emb_func_int2.int2_fsm_lc = val.fsm_lc;
-
fsm_int2_a.int2_fsm1 = val.fsm1;
fsm_int2_a.int2_fsm2 = val.fsm2;
fsm_int2_a.int2_fsm3 = val.fsm3;
@@ -10358,7 +12397,6 @@ int32_t lsm6dsox_pin_int2_route_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
fsm_int2_a.int2_fsm6 = val.fsm6;
fsm_int2_a.int2_fsm7 = val.fsm7;
fsm_int2_a.int2_fsm8 = val.fsm8;
-
fsm_int2_b.int2_fsm9 = val.fsm9 ;
fsm_int2_b.int2_fsm10 = val.fsm10;
fsm_int2_b.int2_fsm11 = val.fsm11;
@@ -10367,7 +12405,6 @@ int32_t lsm6dsox_pin_int2_route_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
fsm_int2_b.int2_fsm14 = val.fsm14;
fsm_int2_b.int2_fsm15 = val.fsm15;
fsm_int2_b.int2_fsm16 = val.fsm16;
-
mlc_int2.int2_mlc1 = val.mlc1;
mlc_int2.int2_mlc2 = val.mlc2;
mlc_int2.int2_mlc3 = val.mlc3;
@@ -10377,92 +12414,116 @@ int32_t lsm6dsox_pin_int2_route_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
mlc_int2.int2_mlc7 = val.mlc7;
mlc_int2.int2_mlc8 = val.mlc8;
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if (ret == 0) {
- if ( ( val.drdy_temp | val.timestamp ) != PROPERTY_DISABLE ) {
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ if ((val.drdy_temp | val.timestamp) != PROPERTY_DISABLE)
+ {
ctrl4_c.int2_on_int1 = PROPERTY_DISABLE;
}
- else{
- ctrl4_c.int2_on_int1 = PROPERTY_ENABLE;
- }
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MLC_INT2,
- (uint8_t*)&mlc_int2, 1);
+ (uint8_t *)&mlc_int2, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INT2,
- (uint8_t*)&emb_func_int2, 1);
+ (uint8_t *)&emb_func_int2, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT2_A,
- (uint8_t*)&fsm_int2_a, 1);
+ (uint8_t *)&fsm_int2_a, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT2_B,
- (uint8_t*)&fsm_int2_b, 1);
+ (uint8_t *)&fsm_int2_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
- if (ret == 0) {
- if (( emb_func_int2.int2_fsm_lc
- | emb_func_int2.int2_sig_mot
- | emb_func_int2.int2_step_detector
- | emb_func_int2.int2_tilt
- | fsm_int2_a.int2_fsm1
- | fsm_int2_a.int2_fsm2
- | fsm_int2_a.int2_fsm3
- | fsm_int2_a.int2_fsm4
- | fsm_int2_a.int2_fsm5
- | fsm_int2_a.int2_fsm6
- | fsm_int2_a.int2_fsm7
- | fsm_int2_a.int2_fsm8
- | fsm_int2_b.int2_fsm9
- | fsm_int2_b.int2_fsm10
- | fsm_int2_b.int2_fsm11
- | fsm_int2_b.int2_fsm12
- | fsm_int2_b.int2_fsm13
- | fsm_int2_b.int2_fsm14
- | fsm_int2_b.int2_fsm15
- | fsm_int2_b.int2_fsm16
- | mlc_int2.int2_mlc1
- | mlc_int2.int2_mlc2
- | mlc_int2.int2_mlc3
- | mlc_int2.int2_mlc4
- | mlc_int2.int2_mlc5
- | mlc_int2.int2_mlc6
- | mlc_int2.int2_mlc7
- | mlc_int2.int2_mlc8)!= PROPERTY_DISABLE ){
+ if (ret == 0)
+ {
+ if ((emb_func_int2.int2_fsm_lc
+ | emb_func_int2.int2_sig_mot
+ | emb_func_int2.int2_step_detector
+ | emb_func_int2.int2_tilt
+ | fsm_int2_a.int2_fsm1
+ | fsm_int2_a.int2_fsm2
+ | fsm_int2_a.int2_fsm3
+ | fsm_int2_a.int2_fsm4
+ | fsm_int2_a.int2_fsm5
+ | fsm_int2_a.int2_fsm6
+ | fsm_int2_a.int2_fsm7
+ | fsm_int2_a.int2_fsm8
+ | fsm_int2_b.int2_fsm9
+ | fsm_int2_b.int2_fsm10
+ | fsm_int2_b.int2_fsm11
+ | fsm_int2_b.int2_fsm12
+ | fsm_int2_b.int2_fsm13
+ | fsm_int2_b.int2_fsm14
+ | fsm_int2_b.int2_fsm15
+ | fsm_int2_b.int2_fsm16
+ | mlc_int2.int2_mlc1
+ | mlc_int2.int2_mlc2
+ | mlc_int2.int2_mlc3
+ | mlc_int2.int2_mlc4
+ | mlc_int2.int2_mlc5
+ | mlc_int2.int2_mlc6
+ | mlc_int2.int2_mlc7
+ | mlc_int2.int2_mlc8) != PROPERTY_DISABLE)
+ {
md2_cfg.int2_emb_func = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
md2_cfg.int2_emb_func = PROPERTY_DISABLE;
}
+
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT2_CTRL,
- (uint8_t*)&int2_ctrl, 1);
- }
- if (ret == 0) {
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MD2_CFG, (uint8_t*)&md2_cfg, 1);
+ (uint8_t *)&int2_ctrl, 1);
}
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MD2_CFG, (uint8_t *)&md2_cfg, 1);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
+ }
+
+ if (ret == 0)
+ {
ret = lsm6dsox_pin_int1_route_get(ctx, &pin_int1_route);
}
- if (ret == 0) {
- if ( ( val.fifo_bdr
+ if (ret == 0)
+ {
+ if ((val.fifo_bdr
| val.drdy_g
| val.drdy_temp
| val.drdy_xl
@@ -10488,29 +12549,37 @@ int32_t lsm6dsox_pin_int2_route_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
| pin_int1_route.free_fall
| pin_int1_route.wake_up
| pin_int1_route.single_tap
- | pin_int1_route.sleep_change ) != PROPERTY_DISABLE) {
+ | pin_int1_route.sleep_change) != PROPERTY_DISABLE)
+ {
tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
}
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
+
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG2,
+ (uint8_t *) &tap_cfg2, 1);
}
}
+
return ret;
}
/**
* @brief Route interrupt signals on int2 pin.[get]
*
- * @param ctx communication interface handler. Use NULL to ingnore
+ * @param ctx communication interface handler. Use NULL to ignore
* this interface.(ptr)
* @param aux_ctx auxiliary communication interface handler. Use NULL
- * to ingnore this interface.(ptr)
+ * to ignore this interface.(ptr)
* @param val the signals that are routed on int2 pin.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsox_pin_int2_route_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
+int32_t lsm6dsox_pin_int2_route_get(stmdev_ctx_t *ctx,
+ stmdev_ctx_t *aux_ctx,
lsm6dsox_pin_int2_route_t *val)
{
lsm6dsox_emb_func_int2_t emb_func_int2;
@@ -10522,63 +12591,86 @@ int32_t lsm6dsox_pin_int2_route_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
lsm6dsox_md2_cfg_t md2_cfg;
lsm6dsox_ctrl4_c_t ctrl4_c;
int32_t ret;
-
ret = 0;
- if( aux_ctx != NULL ) {
+ if (aux_ctx != NULL)
+ {
ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_INT_OIS,
- (uint8_t*)&spi2_int_ois, 1);
+ (uint8_t *)&spi2_int_ois, 1);
val->drdy_ois = spi2_int_ois.int2_drdy_ois;
}
- if( ctx != NULL ) {
- if (ret == 0) {
- ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
+ if (ctx != NULL)
+ {
+ if (ret == 0)
+ {
+ ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
}
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MLC_INT2,
- (uint8_t*)&mlc_int2, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MLC_INT2,
+ (uint8_t *)&mlc_int2, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INT2,
- (uint8_t*)&emb_func_int2, 1);
+ (uint8_t *)&emb_func_int2, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_INT2_A,
- (uint8_t*)&fsm_int2_a, 1);
+ (uint8_t *)&fsm_int2_a, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_INT2_B,
- (uint8_t*)&fsm_int2_b, 1);
+ (uint8_t *)&fsm_int2_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT2_CTRL,
- (uint8_t*)&int2_ctrl, 1);
+ (uint8_t *)&int2_ctrl, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MD2_CFG,
- (uint8_t*)&md2_cfg, 1);
+ (uint8_t *)&md2_cfg, 1);
}
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
- if (ctrl4_c.int2_on_int1 == PROPERTY_DISABLE){
- if (ret == 0) {
+
+ if (ctrl4_c.int2_on_int1 == PROPERTY_DISABLE)
+ {
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT2_CTRL,
- (uint8_t*)&int2_ctrl, 1);
+ (uint8_t *)&int2_ctrl, 1);
val->drdy_temp = int2_ctrl.int2_drdy_temp;
}
- if (ret == 0) {
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MD2_CFG, (uint8_t*)&md2_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MD2_CFG, (uint8_t *)&md2_cfg, 1);
val->timestamp = md2_cfg.int2_timestamp;
}
}
- else {
+
+ else
+ {
val->drdy_temp = PROPERTY_DISABLE;
val->timestamp = PROPERTY_DISABLE;
}
@@ -10590,7 +12682,6 @@ int32_t lsm6dsox_pin_int2_route_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
val->fifo_ovr = int2_ctrl.int2_fifo_ovr;
val->fifo_full = int2_ctrl.int2_fifo_full;
val->fifo_bdr = int2_ctrl.int2_cnt_bdr;
-
val->timestamp = md2_cfg.int2_timestamp;
val->six_d = md2_cfg.int2_6d;
val->double_tap = md2_cfg.int2_double_tap;
@@ -10598,11 +12689,9 @@ int32_t lsm6dsox_pin_int2_route_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
val->wake_up = md2_cfg.int2_wu;
val->single_tap = md2_cfg.int2_single_tap;
val->sleep_change = md2_cfg.int2_sleep_change;
-
val->step_detector = emb_func_int2. int2_step_detector;
val->tilt = emb_func_int2.int2_tilt;
val->fsm_lc = emb_func_int2.int2_fsm_lc;
-
val->fsm1 = fsm_int2_a.int2_fsm1;
val->fsm2 = fsm_int2_a.int2_fsm2;
val->fsm3 = fsm_int2_a.int2_fsm3;
@@ -10611,7 +12700,6 @@ int32_t lsm6dsox_pin_int2_route_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
val->fsm6 = fsm_int2_a.int2_fsm6;
val->fsm7 = fsm_int2_a.int2_fsm7;
val->fsm8 = fsm_int2_a.int2_fsm8;
-
val->fsm9 = fsm_int2_b.int2_fsm9;
val->fsm10 = fsm_int2_b.int2_fsm10;
val->fsm11 = fsm_int2_b.int2_fsm11;
@@ -10620,7 +12708,6 @@ int32_t lsm6dsox_pin_int2_route_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
val->fsm14 = fsm_int2_b.int2_fsm14;
val->fsm15 = fsm_int2_b.int2_fsm15;
val->fsm16 = fsm_int2_b.int2_fsm16;
-
val->mlc1 = mlc_int2.int2_mlc1;
val->mlc2 = mlc_int2.int2_mlc2;
val->mlc3 = mlc_int2.int2_mlc3;
@@ -10639,6 +12726,7 @@ int32_t lsm6dsox_pin_int2_route_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
*
* @param ctx communication interface handler.(ptr)
* @param val the status of all the interrupt sources.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_all_sources_get(stmdev_ctx_t *ctx,
@@ -10659,32 +12747,34 @@ int32_t lsm6dsox_all_sources_get(stmdev_ctx_t *ctx,
lsm6dsox_ctrl5_c_t ctrl5_c;
uint8_t reg[12];
int32_t ret;
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
- ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if (ret == 0) {
+ if (ret == 0)
+ {
ctrl5_c.rounding_status = PROPERTY_ENABLE;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_ALL_INT_SRC, reg, 12);
}
- if (ret == 0) {
- bytecpy(( uint8_t*)&all_int_src, ®[0]);
- bytecpy(( uint8_t*)&wake_up_src, ®[1]);
- bytecpy(( uint8_t*)&tap_src, ®[2]);
- bytecpy(( uint8_t*)&d6d_src, ®[3]);
- bytecpy(( uint8_t*)&status_reg, ®[4]);
- bytecpy(( uint8_t*)&emb_func_status_mainpage, ®[5]);
- bytecpy(( uint8_t*)&fsm_status_a_mainpage, ®[6]);
- bytecpy(( uint8_t*)&fsm_status_b_mainpage, ®[7]);
- bytecpy(( uint8_t*)&mlc_status_mainpage, ®[8]);
- bytecpy(( uint8_t*)&status_master_mainpage, ®[9]);
- bytecpy(( uint8_t*)&fifo_status1, ®[10]);
- bytecpy(( uint8_t*)&fifo_status2, ®[11]);
-
+ if (ret == 0)
+ {
+ bytecpy((uint8_t *)&all_int_src, ®[0]);
+ bytecpy((uint8_t *)&wake_up_src, ®[1]);
+ bytecpy((uint8_t *)&tap_src, ®[2]);
+ bytecpy((uint8_t *)&d6d_src, ®[3]);
+ bytecpy((uint8_t *)&status_reg, ®[4]);
+ bytecpy((uint8_t *)&emb_func_status_mainpage, ®[5]);
+ bytecpy((uint8_t *)&fsm_status_a_mainpage, ®[6]);
+ bytecpy((uint8_t *)&fsm_status_b_mainpage, ®[7]);
+ bytecpy((uint8_t *)&mlc_status_mainpage, ®[8]);
+ bytecpy((uint8_t *)&status_master_mainpage, ®[9]);
+ bytecpy((uint8_t *)&fifo_status1, ®[10]);
+ bytecpy((uint8_t *)&fifo_status2, ®[11]);
val->timestamp = all_int_src.timestamp_endcount;
-
val->wake_up_z = wake_up_src.z_wu;
val->wake_up_y = wake_up_src.y_wu;
val->wake_up_x = wake_up_src.x_wu;
@@ -10692,14 +12782,12 @@ int32_t lsm6dsox_all_sources_get(stmdev_ctx_t *ctx,
val->sleep_state = wake_up_src.sleep_state;
val->free_fall = wake_up_src.ff_ia;
val->sleep_change = wake_up_src.sleep_change_ia;
-
val->tap_x = tap_src.x_tap;
val->tap_y = tap_src.y_tap;
val->tap_z = tap_src.z_tap;
val->tap_sign = tap_src.tap_sign;
val->double_tap = tap_src.double_tap;
val->single_tap = tap_src.single_tap;
-
val->six_d_xl = d6d_src.xl;
val->six_d_xh = d6d_src.xh;
val->six_d_yl = d6d_src.yl;
@@ -10708,16 +12796,13 @@ int32_t lsm6dsox_all_sources_get(stmdev_ctx_t *ctx,
val->six_d_zh = d6d_src.zh;
val->six_d = d6d_src.d6d_ia;
val->den_flag = d6d_src.den_drdy;
-
val->drdy_xl = status_reg.xlda;
val->drdy_g = status_reg.gda;
val->drdy_temp = status_reg.tda;
-
val->step_detector = emb_func_status_mainpage.is_step_det;
val->tilt = emb_func_status_mainpage.is_tilt;
val->sig_mot = emb_func_status_mainpage.is_sigmot;
val->fsm_lc = emb_func_status_mainpage.is_fsm_lc;
-
val->fsm1 = fsm_status_a_mainpage.is_fsm1;
val->fsm2 = fsm_status_a_mainpage.is_fsm2;
val->fsm3 = fsm_status_a_mainpage.is_fsm3;
@@ -10726,7 +12811,6 @@ int32_t lsm6dsox_all_sources_get(stmdev_ctx_t *ctx,
val->fsm6 = fsm_status_a_mainpage.is_fsm6;
val->fsm7 = fsm_status_a_mainpage.is_fsm7;
val->fsm8 = fsm_status_a_mainpage.is_fsm8;
-
val->fsm9 = fsm_status_b_mainpage.is_fsm9;
val->fsm10 = fsm_status_b_mainpage.is_fsm10;
val->fsm11 = fsm_status_b_mainpage.is_fsm11;
@@ -10735,7 +12819,6 @@ int32_t lsm6dsox_all_sources_get(stmdev_ctx_t *ctx,
val->fsm14 = fsm_status_b_mainpage.is_fsm14;
val->fsm15 = fsm_status_b_mainpage.is_fsm15;
val->fsm16 = fsm_status_b_mainpage.is_fsm16;
-
val->mlc1 = mlc_status_mainpage.is_mlc1;
val->mlc2 = mlc_status_mainpage.is_mlc2;
val->mlc3 = mlc_status_mainpage.is_mlc3;
@@ -10744,25 +12827,21 @@ int32_t lsm6dsox_all_sources_get(stmdev_ctx_t *ctx,
val->mlc6 = mlc_status_mainpage.is_mlc6;
val->mlc7 = mlc_status_mainpage.is_mlc7;
val->mlc8 = mlc_status_mainpage.is_mlc8;
-
val->sh_endop = status_master_mainpage.sens_hub_endop;
val->sh_slave0_nack = status_master_mainpage.slave0_nack;
val->sh_slave1_nack = status_master_mainpage.slave1_nack;
val->sh_slave2_nack = status_master_mainpage.slave2_nack;
val->sh_slave3_nack = status_master_mainpage.slave3_nack;
val->sh_wr_once = status_master_mainpage.wr_once_done;
-
- val->fifo_diff = (256U * fifo_status2.diff_fifo) + fifo_status1.diff_fifo;
-
+ val->fifo_diff = (256U * fifo_status2.diff_fifo) +
+ fifo_status1.diff_fifo;
val->fifo_ovr_latched = fifo_status2.over_run_latched;
val->fifo_bdr = fifo_status2.counter_bdr_ia;
val->fifo_full = fifo_status2.fifo_full_ia;
val->fifo_ovr = fifo_status2.fifo_ovr_ia;
val->fifo_th = fifo_status2.fifo_wtm_ia;
-
ctrl5_c.rounding_status = PROPERTY_DISABLE;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
-
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
}
return ret;
@@ -10771,12 +12850,13 @@ int32_t lsm6dsox_all_sources_get(stmdev_ctx_t *ctx,
/**
* @brief Sensor conversion parameters selection.[set]
*
- * @param ctx communication interface handler. Use NULL to ingnore
+ * @param ctx communication interface handler. Use NULL to ignore
* this interface.(ptr)
* @param aux_ctx auxiliary communication interface handler. Use NULL
- * to ingnore this interface.(ptr)
+ * to ignore this interface.(ptr)
* @param val set the sensor conversion parameters by checking
* the constraints of the device.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
@@ -10806,107 +12886,148 @@ int32_t lsm6dsox_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
int32_t ret;
ret = 0;
-
+ /* FIXME: Remove warnings with STM32CubeIDE */
+ ctrl3_c.not_used_01 = 0;
+ ctrl4_c.not_used_01 = 0;
/* reading input configuration */
- xl_hm_mode = ( (uint8_t)val->ui.xl.odr & 0x10U ) >> 4;
- xl_ulp_en = ( (uint8_t)val->ui.xl.odr & 0x20U ) >> 5;
+ xl_hm_mode = ((uint8_t)val->ui.xl.odr & 0x10U) >> 4;
+ xl_ulp_en = ((uint8_t)val->ui.xl.odr & 0x20U) >> 5;
odr_xl = (uint8_t)val->ui.xl.odr & 0x0FU;
/* if enable xl ultra low power mode disable gy and OIS chain */
- if (xl_ulp_en == PROPERTY_ENABLE) {
+ if (xl_ulp_en == PROPERTY_ENABLE)
+ {
val->ois.xl.odr = LSM6DSOX_XL_OIS_OFF;
val->ois.gy.odr = LSM6DSOX_GY_OIS_OFF;
val->ui.gy.odr = LSM6DSOX_GY_UI_OFF;
}
+
/* if OIS xl is enabled also gyro OIS is enabled */
- if (val->ois.xl.odr == LSM6DSOX_XL_OIS_6667Hz_HP){
+ if (val->ois.xl.odr == LSM6DSOX_XL_OIS_6667Hz_HP)
+ {
val->ois.gy.odr = LSM6DSOX_GY_OIS_6667Hz_HP;
}
- g_hm_mode = ( (uint8_t)val->ui.gy.odr & 0x10U ) >> 4;
+
+ g_hm_mode = ((uint8_t)val->ui.gy.odr & 0x10U) >> 4;
odr_gy = (uint8_t)val->ui.gy.odr & 0x0FU;
/* reading registers to be configured */
- if( ctx != NULL ) {
+ if (ctx != NULL)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, reg, 8);
- bytecpy(( uint8_t*)&ctrl1_xl, ®[0]);
- bytecpy(( uint8_t*)&ctrl2_g, ®[1]);
- bytecpy(( uint8_t*)&ctrl3_c, ®[2]);
- bytecpy(( uint8_t*)&ctrl4_c, ®[3]);
- bytecpy(( uint8_t*)&ctrl5_c, ®[4]);
- bytecpy(( uint8_t*)&ctrl6_c, ®[5]);
- bytecpy(( uint8_t*)&ctrl7_g, ®[6]);
- bytecpy(( uint8_t*)&ctrl8_xl, ®[7]);
- if ( ret == 0 ) {
+ bytecpy((uint8_t *)&ctrl1_xl, ®[0]);
+ bytecpy((uint8_t *)&ctrl2_g, ®[1]);
+ bytecpy((uint8_t *)&ctrl3_c, ®[2]);
+ bytecpy((uint8_t *)&ctrl4_c, ®[3]);
+ bytecpy((uint8_t *)&ctrl5_c, ®[4]);
+ bytecpy((uint8_t *)&ctrl6_c, ®[5]);
+ bytecpy((uint8_t *)&ctrl7_g, ®[6]);
+ bytecpy((uint8_t *)&ctrl8_xl, ®[7]);
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
+ (uint8_t *)&func_cfg_access, 1);
}
+
/* if toggle xl ultra low power mode, turn off xl before reconfigure */
- if (ctrl5_c.xl_ulp_en != xl_ulp_en) {
- ctrl1_xl.odr_xl = (uint8_t) 0x00U;
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
+ if (ctrl5_c.xl_ulp_en != xl_ulp_en)
+ {
+ ctrl1_xl.odr_xl = (uint8_t) 0x00U;
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL1_XL,
+ (uint8_t *)&ctrl1_xl, 1);
}
}
/* reading OIS registers to be configured */
- if( aux_ctx != NULL ) {
- if (ret == 0) {
+ if (aux_ctx != NULL)
+ {
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_CTRL1_OIS, reg, 3);
}
- bytecpy(( uint8_t*)&spi2_ctrl1_ois, ®[0]);
- bytecpy(( uint8_t*)&spi2_ctrl2_ois, ®[1]);
- bytecpy(( uint8_t*)&spi2_ctrl3_ois, ®[2]);
+
+ bytecpy((uint8_t *)&spi2_ctrl1_ois, ®[0]);
+ bytecpy((uint8_t *)&spi2_ctrl2_ois, ®[1]);
+ bytecpy((uint8_t *)&spi2_ctrl3_ois, ®[2]);
}
- else {
- if( ctx != NULL ) {
- if (ret == 0) {
+
+ else
+ {
+ if (ctx != NULL)
+ {
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, reg, 3);
}
- bytecpy(( uint8_t*)&ui_ctrl1_ois, ®[0]);
- bytecpy(( uint8_t*)&ui_ctrl2_ois, ®[1]);
- bytecpy(( uint8_t*)&ui_ctrl3_ois, ®[2]);
+
+ bytecpy((uint8_t *)&ui_ctrl1_ois, ®[0]);
+ bytecpy((uint8_t *)&ui_ctrl2_ois, ®[1]);
+ bytecpy((uint8_t *)&ui_ctrl3_ois, ®[2]);
}
}
/* Check the Finite State Machine data rate constraints */
- if (val->fsm.sens != LSM6DSOX_FSM_DISABLE) {
- switch (val->fsm.odr) {
+ if (val->fsm.sens != LSM6DSOX_FSM_DISABLE)
+ {
+ switch (val->fsm.odr)
+ {
case LSM6DSOX_FSM_12Hz5:
- if ( (val->fsm.sens != LSM6DSOX_FSM_GY) && (odr_xl == 0x00U) ) {
+ if ((val->fsm.sens != LSM6DSOX_FSM_GY) && (odr_xl == 0x00U))
+ {
odr_xl = 0x01U;
}
- if ( (val->fsm.sens != LSM6DSOX_FSM_XL) && (odr_gy == 0x00U) ) {
+
+ if ((val->fsm.sens != LSM6DSOX_FSM_XL) && (odr_gy == 0x00U))
+ {
xl_ulp_en = PROPERTY_DISABLE;
odr_gy = 0x01U;
}
+
break;
+
case LSM6DSOX_FSM_26Hz:
- if ( (val->fsm.sens != LSM6DSOX_FSM_GY) && (odr_xl < 0x02U) ) {
+ if ((val->fsm.sens != LSM6DSOX_FSM_GY) && (odr_xl < 0x02U))
+ {
odr_xl = 0x02U;
}
- if ( (val->fsm.sens != LSM6DSOX_FSM_XL) && (odr_gy < 0x02U) ) {
+
+ if ((val->fsm.sens != LSM6DSOX_FSM_XL) && (odr_gy < 0x02U))
+ {
xl_ulp_en = PROPERTY_DISABLE;
odr_gy = 0x02U;
}
+
break;
+
case LSM6DSOX_FSM_52Hz:
- if ( (val->fsm.sens != LSM6DSOX_FSM_GY) && (odr_xl < 0x03U) ) {
+ if ((val->fsm.sens != LSM6DSOX_FSM_GY) && (odr_xl < 0x03U))
+ {
odr_xl = 0x03U;
}
- if ( (val->fsm.sens != LSM6DSOX_FSM_XL) && (odr_gy < 0x03U) ) {
+
+ if ((val->fsm.sens != LSM6DSOX_FSM_XL) && (odr_gy < 0x03U))
+ {
xl_ulp_en = PROPERTY_DISABLE;
odr_gy = 0x03U;
}
+
break;
+
case LSM6DSOX_FSM_104Hz:
- if ( (val->fsm.sens != LSM6DSOX_FSM_GY) && (odr_xl < 0x04U) ) {
+ if ((val->fsm.sens != LSM6DSOX_FSM_GY) && (odr_xl < 0x04U))
+ {
odr_xl = 0x04U;
}
- if ( (val->fsm.sens != LSM6DSOX_FSM_XL) && (odr_gy < 0x04U) ) {
+
+ if ((val->fsm.sens != LSM6DSOX_FSM_XL) && (odr_gy < 0x04U))
+ {
xl_ulp_en = PROPERTY_DISABLE;
odr_gy = 0x04U;
}
+
break;
+
default:
odr_xl = 0x00U;
odr_gy = 0x00U;
@@ -10915,44 +13036,66 @@ int32_t lsm6dsox_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
}
/* Check the Machine Learning Core data rate constraints */
- if (val->mlc.sens != LSM6DSOX_MLC_DISABLE) {
- switch (val->mlc.odr) {
+ if (val->mlc.sens != LSM6DSOX_MLC_DISABLE)
+ {
+ switch (val->mlc.odr)
+ {
case LSM6DSOX_MLC_12Hz5:
- if (odr_xl == 0x00U) {
+ if (odr_xl == 0x00U)
+ {
odr_xl = 0x01U;
}
- if ( (val->mlc.sens != LSM6DSOX_MLC_XL) && (odr_gy == 0x00U) ) {
+
+ if ((val->mlc.sens != LSM6DSOX_MLC_XL) && (odr_gy == 0x00U))
+ {
xl_ulp_en = PROPERTY_DISABLE;
odr_gy = 0x01U;
}
+
break;
+
case LSM6DSOX_MLC_26Hz:
- if (odr_xl < 0x02U) {
+ if (odr_xl < 0x02U)
+ {
odr_xl = 0x02U;
}
- if ( (val->mlc.sens != LSM6DSOX_MLC_XL) && (odr_gy < 0x02U) ) {
+
+ if ((val->mlc.sens != LSM6DSOX_MLC_XL) && (odr_gy < 0x02U))
+ {
xl_ulp_en = PROPERTY_DISABLE;
odr_gy = 0x02U;
}
+
break;
+
case LSM6DSOX_MLC_52Hz:
- if (odr_xl < 0x03U) {
+ if (odr_xl < 0x03U)
+ {
odr_xl = 0x03U;
}
- if ( (val->mlc.sens != LSM6DSOX_MLC_XL) && (odr_gy < 0x03U) ) {
+
+ if ((val->mlc.sens != LSM6DSOX_MLC_XL) && (odr_gy < 0x03U))
+ {
xl_ulp_en = PROPERTY_DISABLE;
odr_gy = 0x03U;
}
+
break;
+
case LSM6DSOX_MLC_104Hz:
- if (odr_xl < 0x04U) {
+ if (odr_xl < 0x04U)
+ {
odr_xl = 0x04U;
}
- if ( (val->mlc.sens != LSM6DSOX_MLC_XL) && (odr_gy < 0x04U) ) {
+
+ if ((val->mlc.sens != LSM6DSOX_MLC_XL) && (odr_gy < 0x04U))
+ {
xl_ulp_en = PROPERTY_DISABLE;
odr_gy = 0x04U;
}
+
break;
+
default:
odr_xl = 0x00U;
odr_gy = 0x00U;
@@ -10961,132 +13104,173 @@ int32_t lsm6dsox_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
}
/* Updating the accelerometer data rate configuration */
- switch ( ( ctrl5_c.xl_ulp_en << 5 ) | ( ctrl6_c.xl_hm_mode << 4 ) |
- ctrl1_xl.odr_xl ) {
+ switch ((ctrl5_c.xl_ulp_en << 5) | (ctrl6_c.xl_hm_mode << 4) |
+ ctrl1_xl.odr_xl)
+ {
case LSM6DSOX_XL_UI_OFF:
val->ui.xl.odr = LSM6DSOX_XL_UI_OFF;
break;
+
case LSM6DSOX_XL_UI_12Hz5_HP:
val->ui.xl.odr = LSM6DSOX_XL_UI_12Hz5_HP;
break;
+
case LSM6DSOX_XL_UI_26Hz_HP:
val->ui.xl.odr = LSM6DSOX_XL_UI_26Hz_HP;
break;
+
case LSM6DSOX_XL_UI_52Hz_HP:
val->ui.xl.odr = LSM6DSOX_XL_UI_52Hz_HP;
break;
+
case LSM6DSOX_XL_UI_104Hz_HP:
val->ui.xl.odr = LSM6DSOX_XL_UI_104Hz_HP;
break;
+
case LSM6DSOX_XL_UI_208Hz_HP:
val->ui.xl.odr = LSM6DSOX_XL_UI_208Hz_HP;
break;
+
case LSM6DSOX_XL_UI_416Hz_HP:
val->ui.xl.odr = LSM6DSOX_XL_UI_416Hz_HP;
break;
+
case LSM6DSOX_XL_UI_833Hz_HP:
val->ui.xl.odr = LSM6DSOX_XL_UI_833Hz_HP;
break;
+
case LSM6DSOX_XL_UI_1667Hz_HP:
val->ui.xl.odr = LSM6DSOX_XL_UI_1667Hz_HP;
break;
+
case LSM6DSOX_XL_UI_3333Hz_HP:
val->ui.xl.odr = LSM6DSOX_XL_UI_3333Hz_HP;
break;
+
case LSM6DSOX_XL_UI_6667Hz_HP:
val->ui.xl.odr = LSM6DSOX_XL_UI_6667Hz_HP;
break;
+
case LSM6DSOX_XL_UI_1Hz6_LP:
val->ui.xl.odr = LSM6DSOX_XL_UI_1Hz6_LP;
break;
+
case LSM6DSOX_XL_UI_12Hz5_LP:
val->ui.xl.odr = LSM6DSOX_XL_UI_12Hz5_LP;
break;
+
case LSM6DSOX_XL_UI_26Hz_LP:
val->ui.xl.odr = LSM6DSOX_XL_UI_26Hz_LP;
break;
+
case LSM6DSOX_XL_UI_52Hz_LP:
val->ui.xl.odr = LSM6DSOX_XL_UI_52Hz_LP;
break;
+
case LSM6DSOX_XL_UI_104Hz_NM:
val->ui.xl.odr = LSM6DSOX_XL_UI_104Hz_NM;
break;
+
case LSM6DSOX_XL_UI_208Hz_NM:
val->ui.xl.odr = LSM6DSOX_XL_UI_208Hz_NM;
break;
+
case LSM6DSOX_XL_UI_1Hz6_ULP:
val->ui.xl.odr = LSM6DSOX_XL_UI_1Hz6_ULP;
break;
+
case LSM6DSOX_XL_UI_12Hz5_ULP:
val->ui.xl.odr = LSM6DSOX_XL_UI_12Hz5_ULP;
break;
+
case LSM6DSOX_XL_UI_26Hz_ULP:
val->ui.xl.odr = LSM6DSOX_XL_UI_26Hz_ULP;
break;
+
case LSM6DSOX_XL_UI_52Hz_ULP:
val->ui.xl.odr = LSM6DSOX_XL_UI_52Hz_ULP;
break;
+
case LSM6DSOX_XL_UI_104Hz_ULP:
val->ui.xl.odr = LSM6DSOX_XL_UI_104Hz_ULP;
break;
+
case LSM6DSOX_XL_UI_208Hz_ULP:
val->ui.xl.odr = LSM6DSOX_XL_UI_208Hz_ULP;
break;
+
default:
val->ui.xl.odr = LSM6DSOX_XL_UI_OFF;
break;
}
/* Updating the accelerometer data rate configuration */
- switch ( (ctrl7_g.g_hm_mode << 4) | ctrl2_g.odr_g) {
+ switch ((ctrl7_g.g_hm_mode << 4) | ctrl2_g.odr_g)
+ {
case LSM6DSOX_GY_UI_OFF:
val->ui.gy.odr = LSM6DSOX_GY_UI_OFF;
break;
+
case LSM6DSOX_GY_UI_12Hz5_LP:
val->ui.gy.odr = LSM6DSOX_GY_UI_12Hz5_LP;
break;
+
case LSM6DSOX_GY_UI_12Hz5_HP:
val->ui.gy.odr = LSM6DSOX_GY_UI_12Hz5_HP;
break;
+
case LSM6DSOX_GY_UI_26Hz_LP:
val->ui.gy.odr = LSM6DSOX_GY_UI_26Hz_LP;
break;
+
case LSM6DSOX_GY_UI_26Hz_HP:
val->ui.gy.odr = LSM6DSOX_GY_UI_26Hz_HP;
break;
+
case LSM6DSOX_GY_UI_52Hz_LP:
val->ui.gy.odr = LSM6DSOX_GY_UI_52Hz_LP;
break;
+
case LSM6DSOX_GY_UI_52Hz_HP:
val->ui.gy.odr = LSM6DSOX_GY_UI_52Hz_HP;
break;
+
case LSM6DSOX_GY_UI_104Hz_NM:
val->ui.gy.odr = LSM6DSOX_GY_UI_104Hz_NM;
break;
+
case LSM6DSOX_GY_UI_104Hz_HP:
val->ui.gy.odr = LSM6DSOX_GY_UI_104Hz_HP;
break;
+
case LSM6DSOX_GY_UI_208Hz_NM:
val->ui.gy.odr = LSM6DSOX_GY_UI_208Hz_NM;
break;
+
case LSM6DSOX_GY_UI_208Hz_HP:
val->ui.gy.odr = LSM6DSOX_GY_UI_208Hz_HP;
break;
+
case LSM6DSOX_GY_UI_416Hz_HP:
val->ui.gy.odr = LSM6DSOX_GY_UI_416Hz_HP;
break;
+
case LSM6DSOX_GY_UI_833Hz_HP:
val->ui.gy.odr = LSM6DSOX_GY_UI_833Hz_HP;
break;
+
case LSM6DSOX_GY_UI_1667Hz_HP:
val->ui.gy.odr = LSM6DSOX_GY_UI_1667Hz_HP;
break;
+
case LSM6DSOX_GY_UI_3333Hz_HP:
val->ui.gy.odr = LSM6DSOX_GY_UI_3333Hz_HP;
break;
+
case LSM6DSOX_GY_UI_6667Hz_HP:
val->ui.gy.odr = LSM6DSOX_GY_UI_6667Hz_HP;
break;
+
default:
val->ui.gy.odr = LSM6DSOX_GY_UI_OFF;
break;
@@ -11094,8 +13278,9 @@ int32_t lsm6dsox_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
/* Check accelerometer full scale constraints */
/* Full scale of 16g must be the same for UI and OIS */
- if ( (val->ui.xl.fs == LSM6DSOX_XL_UI_16g) ||
- (val->ois.xl.fs == LSM6DSOX_XL_OIS_16g) ){
+ if ((val->ui.xl.fs == LSM6DSOX_XL_UI_16g) ||
+ (val->ois.xl.fs == LSM6DSOX_XL_OIS_16g))
+ {
val->ui.xl.fs = LSM6DSOX_XL_UI_16g;
val->ois.xl.fs = LSM6DSOX_XL_OIS_16g;
}
@@ -11103,10 +13288,13 @@ int32_t lsm6dsox_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
/* prapare new configuration */
/* Full scale of 16g must be the same for UI and OIS */
- if (val->ui.xl.fs == LSM6DSOX_XL_UI_16g) {
+ if (val->ui.xl.fs == LSM6DSOX_XL_UI_16g)
+ {
ctrl8_xl.xl_fs_mode = PROPERTY_DISABLE;
}
- else {
+
+ else
+ {
ctrl8_xl.xl_fs_mode = PROPERTY_ENABLE;
}
@@ -11114,28 +13302,35 @@ int32_t lsm6dsox_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
ctrl7_g.ois_on_en = val->ois.ctrl_md & 0x01U;
func_cfg_access.ois_ctrl_from_ui = (val->ois.ctrl_md & 0x02U) >> 1;
- switch (val->ois.ctrl_md) {
+ switch (val->ois.ctrl_md)
+ {
case LSM6DSOX_OIS_ONLY_AUX:
spi2_ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
- spi2_ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr | (uint8_t)val->ois.xl.odr;
+ spi2_ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr |
+ (uint8_t)val->ois.xl.odr;
spi2_ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr;
spi2_ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
break;
+
case LSM6DSOX_OIS_ONLY_UI:
ui_ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
- ui_ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr | (uint8_t)val->ois.xl.odr;
+ ui_ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr |
+ (uint8_t)val->ois.xl.odr;
ui_ctrl1_ois.mode4_en = (uint8_t)val->ois.xl.odr;
ui_ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
break;
+
case LSM6DSOX_OIS_MIXED:
spi2_ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
ctrl7_g.ois_on = (uint8_t)val->ois.gy.odr | (uint8_t)val->ois.xl.odr;
spi2_ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr;
spi2_ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
break;
+
default:
spi2_ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
- spi2_ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr | (uint8_t)val->ois.xl.odr;
+ spi2_ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr |
+ (uint8_t)val->ois.xl.odr;
spi2_ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr;
spi2_ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
break;
@@ -11151,39 +13346,52 @@ int32_t lsm6dsox_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
ctrl2_g.fs_g = (uint8_t) val->ui.gy.fs;
/* writing checked configuration */
- if( ctx != NULL ) {
- bytecpy(®[0], ( uint8_t*)&ctrl1_xl);
- bytecpy(®[1], ( uint8_t*)&ctrl2_g);
- bytecpy(®[2], ( uint8_t*)&ctrl3_c);
- bytecpy(®[3], ( uint8_t*)&ctrl4_c);
- bytecpy(®[4], ( uint8_t*)&ctrl5_c);
- bytecpy(®[5], ( uint8_t*)&ctrl6_c);
- bytecpy(®[6], ( uint8_t*)&ctrl7_g);
- bytecpy(®[7], ( uint8_t*)&ctrl8_xl);
- if ( ret == 0 ) {
- ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)®, 8);
+ if (ctx != NULL)
+ {
+ bytecpy(®[0], (uint8_t *)&ctrl1_xl);
+ bytecpy(®[1], (uint8_t *)&ctrl2_g);
+ bytecpy(®[2], (uint8_t *)&ctrl3_c);
+ bytecpy(®[3], (uint8_t *)&ctrl4_c);
+ bytecpy(®[4], (uint8_t *)&ctrl5_c);
+ bytecpy(®[5], (uint8_t *)&ctrl6_c);
+ bytecpy(®[6], (uint8_t *)&ctrl7_g);
+ bytecpy(®[7], (uint8_t *)&ctrl8_xl);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t *)®, 8);
}
- if ( ret == 0 ) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
+ (uint8_t *)&func_cfg_access, 1);
}
}
/* writing OIS checked configuration */
- if( aux_ctx != NULL ) {
- bytecpy(®[0], ( uint8_t*)&spi2_ctrl1_ois);
- bytecpy(®[1], ( uint8_t*)&spi2_ctrl2_ois);
- bytecpy(®[2], ( uint8_t*)&spi2_ctrl3_ois);
- if (ret == 0) {
+ if (aux_ctx != NULL)
+ {
+ bytecpy(®[0], (uint8_t *)&spi2_ctrl1_ois);
+ bytecpy(®[1], (uint8_t *)&spi2_ctrl2_ois);
+ bytecpy(®[2], (uint8_t *)&spi2_ctrl3_ois);
+
+ if (ret == 0)
+ {
ret = lsm6dsox_write_reg(aux_ctx, LSM6DSOX_SPI2_CTRL1_OIS, reg, 3);
}
}
- else {
- if( ctx != NULL ) {
- bytecpy(®[0], ( uint8_t*)&ui_ctrl1_ois);
- bytecpy(®[1], ( uint8_t*)&ui_ctrl2_ois);
- bytecpy(®[2], ( uint8_t*)&ui_ctrl3_ois);
- if (ret == 0) {
+
+ else
+ {
+ if (ctx != NULL)
+ {
+ bytecpy(®[0], (uint8_t *)&ui_ctrl1_ois);
+ bytecpy(®[1], (uint8_t *)&ui_ctrl2_ois);
+ bytecpy(®[2], (uint8_t *)&ui_ctrl3_ois);
+
+ if (ret == 0)
+ {
ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, reg, 3);
}
}
@@ -11195,17 +13403,17 @@ int32_t lsm6dsox_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
/**
* @brief Sensor conversion parameters selection.[get]
*
- * @param ctx communication interface handler. Use NULL to ingnore
+ * @param ctx communication interface handler. Use NULL to ignore
* this interface.(ptr)
* @param aux_ctx auxiliary communication interface handler. Use NULL
- * to ingnore this interface.(ptr)
+ * to ignore this interface.(ptr)
* @param val get the sensor conversion parameters.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
lsm6dsox_md_t *val)
{
-
lsm6dsox_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
lsm6dsox_emb_func_odr_cfg_c_t emb_func_odr_cfg_c;
lsm6dsox_func_cfg_access_t func_cfg_access;
@@ -11225,497 +13433,661 @@ int32_t lsm6dsox_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
lsm6dsox_ctrl5_c_t ctrl5_c;
lsm6dsox_ctrl6_c_t ctrl6_c;
lsm6dsox_ctrl7_g_t ctrl7_g;
-
uint8_t reg[8];
int32_t ret;
ret = 0;
/* reading the registers of the device */
- if( ctx != NULL ) {
+ if (ctx != NULL)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, reg, 7);
- bytecpy(( uint8_t*)&ctrl1_xl, ®[0]);
- bytecpy(( uint8_t*)&ctrl2_g, ®[1]);
- bytecpy(( uint8_t*)&ctrl3_c, ®[2]);
- bytecpy(( uint8_t*)&ctrl4_c, ®[3]);
- bytecpy(( uint8_t*)&ctrl5_c, ®[4]);
- bytecpy(( uint8_t*)&ctrl6_c, ®[5]);
- bytecpy(( uint8_t*)&ctrl7_g, ®[6]);
- if ( ret == 0 ) {
+ bytecpy((uint8_t *)&ctrl1_xl, ®[0]);
+ bytecpy((uint8_t *)&ctrl2_g, ®[1]);
+ bytecpy((uint8_t *)&ctrl3_c, ®[2]);
+ bytecpy((uint8_t *)&ctrl4_c, ®[3]);
+ bytecpy((uint8_t *)&ctrl5_c, ®[4]);
+ bytecpy((uint8_t *)&ctrl6_c, ®[5]);
+ bytecpy((uint8_t *)&ctrl7_g, ®[6]);
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
+ (uint8_t *)&func_cfg_access, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_B, reg, 2);
- bytecpy(( uint8_t*)&emb_func_odr_cfg_b, ®[0]);
- bytecpy(( uint8_t*)&emb_func_odr_cfg_c, ®[1]);
+ bytecpy((uint8_t *)&emb_func_odr_cfg_b, ®[0]);
+ bytecpy((uint8_t *)&emb_func_odr_cfg_c, ®[1]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_ENABLE_A, reg, 2);
- bytecpy(( uint8_t*)&fsm_enable_a, ®[0]);
- bytecpy(( uint8_t*)&fsm_enable_b, ®[1]);
+ bytecpy((uint8_t *)&fsm_enable_a, ®[0]);
+ bytecpy((uint8_t *)&fsm_enable_b, ®[1]);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
}
}
- if( aux_ctx != NULL ) {
- if (ret == 0) {
+ if (aux_ctx != NULL)
+ {
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_CTRL1_OIS, reg, 3);
}
- bytecpy(( uint8_t*)&spi2_ctrl1_ois, ®[0]);
- bytecpy(( uint8_t*)&spi2_ctrl2_ois, ®[1]);
- bytecpy(( uint8_t*)&spi2_ctrl3_ois, ®[2]);
+
+ bytecpy((uint8_t *)&spi2_ctrl1_ois, ®[0]);
+ bytecpy((uint8_t *)&spi2_ctrl2_ois, ®[1]);
+ bytecpy((uint8_t *)&spi2_ctrl3_ois, ®[2]);
}
- else {
- if( ctx != NULL ) {
- if (ret == 0) {
+
+ else
+ {
+ if (ctx != NULL)
+ {
+ if (ret == 0)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, reg, 3);
}
- bytecpy(( uint8_t*)&ui_ctrl1_ois, ®[0]);
- bytecpy(( uint8_t*)&ui_ctrl2_ois, ®[1]);
- bytecpy(( uint8_t*)&ui_ctrl3_ois, ®[2]);
+
+ bytecpy((uint8_t *)&ui_ctrl1_ois, ®[0]);
+ bytecpy((uint8_t *)&ui_ctrl2_ois, ®[1]);
+ bytecpy((uint8_t *)&ui_ctrl3_ois, ®[2]);
}
}
/* fill the input structure */
/* get accelerometer configuration */
- switch ( (ctrl5_c.xl_ulp_en << 5) | (ctrl6_c.xl_hm_mode << 4) |
- ctrl1_xl.odr_xl ) {
+ switch ((ctrl5_c.xl_ulp_en << 5) | (ctrl6_c.xl_hm_mode << 4) |
+ ctrl1_xl.odr_xl)
+ {
case LSM6DSOX_XL_UI_OFF:
val->ui.xl.odr = LSM6DSOX_XL_UI_OFF;
break;
+
case LSM6DSOX_XL_UI_12Hz5_HP:
val->ui.xl.odr = LSM6DSOX_XL_UI_12Hz5_HP;
break;
+
case LSM6DSOX_XL_UI_26Hz_HP:
val->ui.xl.odr = LSM6DSOX_XL_UI_26Hz_HP;
break;
+
case LSM6DSOX_XL_UI_52Hz_HP:
val->ui.xl.odr = LSM6DSOX_XL_UI_52Hz_HP;
break;
+
case LSM6DSOX_XL_UI_104Hz_HP:
val->ui.xl.odr = LSM6DSOX_XL_UI_104Hz_HP;
break;
+
case LSM6DSOX_XL_UI_208Hz_HP:
val->ui.xl.odr = LSM6DSOX_XL_UI_208Hz_HP;
break;
+
case LSM6DSOX_XL_UI_416Hz_HP:
val->ui.xl.odr = LSM6DSOX_XL_UI_416Hz_HP;
break;
+
case LSM6DSOX_XL_UI_833Hz_HP:
val->ui.xl.odr = LSM6DSOX_XL_UI_833Hz_HP;
break;
+
case LSM6DSOX_XL_UI_1667Hz_HP:
val->ui.xl.odr = LSM6DSOX_XL_UI_1667Hz_HP;
break;
+
case LSM6DSOX_XL_UI_3333Hz_HP:
val->ui.xl.odr = LSM6DSOX_XL_UI_3333Hz_HP;
break;
+
case LSM6DSOX_XL_UI_6667Hz_HP:
val->ui.xl.odr = LSM6DSOX_XL_UI_6667Hz_HP;
break;
+
case LSM6DSOX_XL_UI_1Hz6_LP:
val->ui.xl.odr = LSM6DSOX_XL_UI_1Hz6_LP;
break;
+
case LSM6DSOX_XL_UI_12Hz5_LP:
val->ui.xl.odr = LSM6DSOX_XL_UI_12Hz5_LP;
break;
+
case LSM6DSOX_XL_UI_26Hz_LP:
val->ui.xl.odr = LSM6DSOX_XL_UI_26Hz_LP;
break;
+
case LSM6DSOX_XL_UI_52Hz_LP:
val->ui.xl.odr = LSM6DSOX_XL_UI_52Hz_LP;
break;
+
case LSM6DSOX_XL_UI_104Hz_NM:
val->ui.xl.odr = LSM6DSOX_XL_UI_104Hz_NM;
break;
+
case LSM6DSOX_XL_UI_208Hz_NM:
val->ui.xl.odr = LSM6DSOX_XL_UI_208Hz_NM;
break;
+
case LSM6DSOX_XL_UI_1Hz6_ULP:
val->ui.xl.odr = LSM6DSOX_XL_UI_1Hz6_ULP;
break;
+
case LSM6DSOX_XL_UI_12Hz5_ULP:
val->ui.xl.odr = LSM6DSOX_XL_UI_12Hz5_ULP;
break;
+
case LSM6DSOX_XL_UI_26Hz_ULP:
val->ui.xl.odr = LSM6DSOX_XL_UI_26Hz_ULP;
break;
+
case LSM6DSOX_XL_UI_52Hz_ULP:
val->ui.xl.odr = LSM6DSOX_XL_UI_52Hz_ULP;
break;
+
case LSM6DSOX_XL_UI_104Hz_ULP:
val->ui.xl.odr = LSM6DSOX_XL_UI_104Hz_ULP;
break;
+
case LSM6DSOX_XL_UI_208Hz_ULP:
val->ui.xl.odr = LSM6DSOX_XL_UI_208Hz_ULP;
break;
+
default:
val->ui.xl.odr = LSM6DSOX_XL_UI_OFF;
break;
}
- switch ( ctrl1_xl.fs_xl ) {
+ switch (ctrl1_xl.fs_xl)
+ {
case LSM6DSOX_XL_UI_2g:
val->ui.xl.fs = LSM6DSOX_XL_UI_2g;
break;
+
case LSM6DSOX_XL_UI_4g:
val->ui.xl.fs = LSM6DSOX_XL_UI_4g;
break;
+
case LSM6DSOX_XL_UI_8g:
val->ui.xl.fs = LSM6DSOX_XL_UI_8g;
break;
+
case LSM6DSOX_XL_UI_16g:
val->ui.xl.fs = LSM6DSOX_XL_UI_16g;
break;
+
default:
val->ui.xl.fs = LSM6DSOX_XL_UI_2g;
break;
}
/* get gyroscope configuration */
- switch ( (ctrl7_g.g_hm_mode << 4) | ctrl2_g.odr_g) {
+ switch ((ctrl7_g.g_hm_mode << 4) | ctrl2_g.odr_g)
+ {
case LSM6DSOX_GY_UI_OFF:
val->ui.gy.odr = LSM6DSOX_GY_UI_OFF;
break;
+
case LSM6DSOX_GY_UI_12Hz5_LP:
val->ui.gy.odr = LSM6DSOX_GY_UI_12Hz5_LP;
break;
+
case LSM6DSOX_GY_UI_12Hz5_HP:
val->ui.gy.odr = LSM6DSOX_GY_UI_12Hz5_HP;
break;
+
case LSM6DSOX_GY_UI_26Hz_LP:
val->ui.gy.odr = LSM6DSOX_GY_UI_26Hz_LP;
break;
+
case LSM6DSOX_GY_UI_26Hz_HP:
val->ui.gy.odr = LSM6DSOX_GY_UI_26Hz_HP;
break;
+
case LSM6DSOX_GY_UI_52Hz_LP:
val->ui.gy.odr = LSM6DSOX_GY_UI_52Hz_LP;
break;
+
case LSM6DSOX_GY_UI_52Hz_HP:
val->ui.gy.odr = LSM6DSOX_GY_UI_52Hz_HP;
break;
+
case LSM6DSOX_GY_UI_104Hz_NM:
val->ui.gy.odr = LSM6DSOX_GY_UI_104Hz_NM;
break;
+
case LSM6DSOX_GY_UI_104Hz_HP:
val->ui.gy.odr = LSM6DSOX_GY_UI_104Hz_HP;
break;
+
case LSM6DSOX_GY_UI_208Hz_NM:
val->ui.gy.odr = LSM6DSOX_GY_UI_208Hz_NM;
break;
+
case LSM6DSOX_GY_UI_208Hz_HP:
val->ui.gy.odr = LSM6DSOX_GY_UI_208Hz_HP;
break;
+
case LSM6DSOX_GY_UI_416Hz_HP:
val->ui.gy.odr = LSM6DSOX_GY_UI_416Hz_HP;
break;
+
case LSM6DSOX_GY_UI_833Hz_HP:
val->ui.gy.odr = LSM6DSOX_GY_UI_833Hz_HP;
break;
+
case LSM6DSOX_GY_UI_1667Hz_HP:
val->ui.gy.odr = LSM6DSOX_GY_UI_1667Hz_HP;
break;
+
case LSM6DSOX_GY_UI_3333Hz_HP:
val->ui.gy.odr = LSM6DSOX_GY_UI_3333Hz_HP;
break;
+
case LSM6DSOX_GY_UI_6667Hz_HP:
val->ui.gy.odr = LSM6DSOX_GY_UI_6667Hz_HP;
break;
+
default:
val->ui.gy.odr = LSM6DSOX_GY_UI_OFF;
break;
}
- switch (ctrl2_g.fs_g) {
+ switch (ctrl2_g.fs_g)
+ {
case LSM6DSOX_GY_UI_125dps:
val->ui.gy.fs = LSM6DSOX_GY_UI_125dps;
break;
+
case LSM6DSOX_GY_UI_250dps:
val->ui.gy.fs = LSM6DSOX_GY_UI_250dps;
break;
+
case LSM6DSOX_GY_UI_500dps:
val->ui.gy.fs = LSM6DSOX_GY_UI_500dps;
break;
+
case LSM6DSOX_GY_UI_1000dps:
val->ui.gy.fs = LSM6DSOX_GY_UI_1000dps;
break;
+
case LSM6DSOX_GY_UI_2000dps:
val->ui.gy.fs = LSM6DSOX_GY_UI_2000dps;
break;
+
default:
val->ui.gy.fs = LSM6DSOX_GY_UI_125dps;
break;
}
/* get finite state machine configuration */
- if ( (fsm_enable_a.fsm1_en | fsm_enable_a.fsm2_en | fsm_enable_a.fsm3_en |
- fsm_enable_a.fsm4_en | fsm_enable_a.fsm5_en | fsm_enable_a.fsm6_en |
- fsm_enable_a.fsm7_en | fsm_enable_a.fsm8_en | fsm_enable_b.fsm9_en |
- fsm_enable_b.fsm10_en | fsm_enable_b.fsm11_en |
- fsm_enable_b.fsm12_en | fsm_enable_b.fsm13_en |
- fsm_enable_b.fsm14_en | fsm_enable_b.fsm15_en |
- fsm_enable_b.fsm16_en) == PROPERTY_ENABLE ){
- switch (emb_func_odr_cfg_b.fsm_odr) {
+ if ((fsm_enable_a.fsm1_en | fsm_enable_a.fsm2_en |
+ fsm_enable_a.fsm3_en |
+ fsm_enable_a.fsm4_en | fsm_enable_a.fsm5_en | fsm_enable_a.fsm6_en |
+ fsm_enable_a.fsm7_en | fsm_enable_a.fsm8_en | fsm_enable_b.fsm9_en |
+ fsm_enable_b.fsm10_en | fsm_enable_b.fsm11_en |
+ fsm_enable_b.fsm12_en | fsm_enable_b.fsm13_en |
+ fsm_enable_b.fsm14_en | fsm_enable_b.fsm15_en |
+ fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
+ {
+ switch (emb_func_odr_cfg_b.fsm_odr)
+ {
case LSM6DSOX_FSM_12Hz5:
val->fsm.odr = LSM6DSOX_FSM_12Hz5;
break;
+
case LSM6DSOX_FSM_26Hz:
val->fsm.odr = LSM6DSOX_FSM_26Hz;
break;
+
case LSM6DSOX_FSM_52Hz:
val->fsm.odr = LSM6DSOX_FSM_52Hz;
break;
+
case LSM6DSOX_FSM_104Hz:
val->fsm.odr = LSM6DSOX_FSM_104Hz;
break;
+
default:
val->fsm.odr = LSM6DSOX_FSM_12Hz5;
break;
}
val->fsm.sens = LSM6DSOX_FSM_XL_GY;
- if (val->ui.gy.odr == LSM6DSOX_GY_UI_OFF) {
+
+ if (val->ui.gy.odr == LSM6DSOX_GY_UI_OFF)
+ {
val->fsm.sens = LSM6DSOX_FSM_XL;
}
- if (val->ui.xl.odr == LSM6DSOX_XL_UI_OFF) {
+
+ if (val->ui.xl.odr == LSM6DSOX_XL_UI_OFF)
+ {
val->fsm.sens = LSM6DSOX_FSM_GY;
}
}
- else {
+
+ else
+ {
val->fsm.sens = LSM6DSOX_FSM_DISABLE;
}
/* get machine learning core configuration */
- if (emb_func_en_b.mlc_en == PROPERTY_ENABLE) {
- switch (emb_func_odr_cfg_c.mlc_odr) {
+ if (emb_func_en_b.mlc_en == PROPERTY_ENABLE)
+ {
+ switch (emb_func_odr_cfg_c.mlc_odr)
+ {
case LSM6DSOX_MLC_12Hz5:
val->mlc.odr = LSM6DSOX_MLC_12Hz5;
break;
+
case LSM6DSOX_MLC_26Hz:
val->mlc.odr = LSM6DSOX_MLC_26Hz;
break;
+
case LSM6DSOX_MLC_52Hz:
val->mlc.odr = LSM6DSOX_MLC_52Hz;
break;
+
case LSM6DSOX_MLC_104Hz:
val->mlc.odr = LSM6DSOX_MLC_104Hz;
break;
+
default:
val->mlc.odr = LSM6DSOX_MLC_12Hz5;
break;
}
val->mlc.sens = LSM6DSOX_MLC_XL_GY;
- if (val->ui.gy.odr == LSM6DSOX_GY_UI_OFF) {
+
+ if (val->ui.gy.odr == LSM6DSOX_GY_UI_OFF)
+ {
val->mlc.sens = LSM6DSOX_MLC_XL;
}
- if (val->ui.xl.odr == LSM6DSOX_XL_UI_OFF) {
+
+ if (val->ui.xl.odr == LSM6DSOX_XL_UI_OFF)
+ {
val->mlc.sens = LSM6DSOX_MLC_DISABLE;
}
}
- else {
+
+ else
+ {
val->mlc.sens = LSM6DSOX_MLC_DISABLE;
}
/* get ois configuration */
/* OIS configuration mode */
- switch ( (func_cfg_access.ois_ctrl_from_ui << 1) + ctrl7_g.ois_on_en ) {
+ switch ((func_cfg_access.ois_ctrl_from_ui << 1) +
+ ctrl7_g.ois_on_en)
+ {
case LSM6DSOX_OIS_ONLY_AUX:
- switch ( spi2_ctrl3_ois.fs_xl_ois ) {
+ switch (spi2_ctrl3_ois.fs_xl_ois)
+ {
case LSM6DSOX_XL_OIS_2g:
val->ois.xl.fs = LSM6DSOX_XL_OIS_2g;
break;
+
case LSM6DSOX_XL_OIS_4g:
val->ois.xl.fs = LSM6DSOX_XL_OIS_4g;
break;
+
case LSM6DSOX_XL_OIS_8g:
val->ois.xl.fs = LSM6DSOX_XL_OIS_8g;
break;
+
case LSM6DSOX_XL_OIS_16g:
val->ois.xl.fs = LSM6DSOX_XL_OIS_16g;
break;
+
default:
val->ois.xl.fs = LSM6DSOX_XL_OIS_2g;
break;
}
- switch ( spi2_ctrl1_ois.mode4_en ) {
+
+ switch (spi2_ctrl1_ois.mode4_en)
+ {
case LSM6DSOX_XL_OIS_OFF:
val->ois.xl.odr = LSM6DSOX_XL_OIS_OFF;
break;
+
case LSM6DSOX_XL_OIS_6667Hz_HP:
val->ois.xl.odr = LSM6DSOX_XL_OIS_6667Hz_HP;
break;
+
default:
val->ois.xl.odr = LSM6DSOX_XL_OIS_OFF;
break;
}
- switch ( spi2_ctrl1_ois.fs_g_ois ) {
+
+ switch (spi2_ctrl1_ois.fs_g_ois)
+ {
case LSM6DSOX_GY_OIS_250dps:
val->ois.gy.fs = LSM6DSOX_GY_OIS_250dps;
break;
+
case LSM6DSOX_GY_OIS_500dps:
val->ois.gy.fs = LSM6DSOX_GY_OIS_500dps;
break;
+
case LSM6DSOX_GY_OIS_1000dps:
val->ois.gy.fs = LSM6DSOX_GY_OIS_1000dps;
break;
+
case LSM6DSOX_GY_OIS_2000dps:
val->ois.gy.fs = LSM6DSOX_GY_OIS_2000dps;
break;
+
default:
val->ois.gy.fs = LSM6DSOX_GY_OIS_250dps;
break;
}
- switch ( spi2_ctrl1_ois.ois_en_spi2 ) {
+
+ switch (spi2_ctrl1_ois.ois_en_spi2)
+ {
case LSM6DSOX_GY_OIS_OFF:
val->ois.gy.odr = LSM6DSOX_GY_OIS_OFF;
break;
+
case LSM6DSOX_GY_OIS_6667Hz_HP:
val->ois.gy.odr = LSM6DSOX_GY_OIS_6667Hz_HP;
break;
+
default:
val->ois.gy.odr = LSM6DSOX_GY_OIS_OFF;
break;
}
+
val->ois.ctrl_md = LSM6DSOX_OIS_ONLY_AUX;
break;
+
case LSM6DSOX_OIS_ONLY_UI:
- switch ( ui_ctrl3_ois.fs_xl_ois ) {
+ switch (ui_ctrl3_ois.fs_xl_ois)
+ {
case LSM6DSOX_XL_OIS_2g:
val->ois.xl.fs = LSM6DSOX_XL_OIS_2g;
break;
+
case LSM6DSOX_XL_OIS_4g:
val->ois.xl.fs = LSM6DSOX_XL_OIS_4g;
break;
+
case LSM6DSOX_XL_OIS_8g:
val->ois.xl.fs = LSM6DSOX_XL_OIS_8g;
break;
+
case LSM6DSOX_XL_OIS_16g:
val->ois.xl.fs = LSM6DSOX_XL_OIS_16g;
break;
+
default:
val->ois.xl.fs = LSM6DSOX_XL_OIS_2g;
break;
}
- switch ( ui_ctrl1_ois.ois_en_spi2 ) {
+
+ switch (ui_ctrl1_ois.ois_en_spi2)
+ {
case LSM6DSOX_GY_OIS_OFF:
val->ois.gy.odr = LSM6DSOX_GY_OIS_OFF;
break;
+
case LSM6DSOX_GY_OIS_6667Hz_HP:
val->ois.gy.odr = LSM6DSOX_GY_OIS_6667Hz_HP;
break;
+
default:
val->ois.gy.odr = LSM6DSOX_GY_OIS_OFF;
break;
}
- switch ( ui_ctrl1_ois.fs_g_ois ) {
+
+ switch (ui_ctrl1_ois.fs_g_ois)
+ {
case LSM6DSOX_GY_OIS_250dps:
val->ois.gy.fs = LSM6DSOX_GY_OIS_250dps;
break;
+
case LSM6DSOX_GY_OIS_125dps:
val->ois.gy.fs = LSM6DSOX_GY_OIS_125dps;
break;
+
case LSM6DSOX_GY_OIS_500dps:
val->ois.gy.fs = LSM6DSOX_GY_OIS_500dps;
break;
+
case LSM6DSOX_GY_OIS_1000dps:
val->ois.gy.fs = LSM6DSOX_GY_OIS_1000dps;
break;
+
case LSM6DSOX_GY_OIS_2000dps:
val->ois.gy.fs = LSM6DSOX_GY_OIS_2000dps;
break;
+
default:
val->ois.gy.fs = LSM6DSOX_GY_OIS_250dps;
break;
}
- switch ( ui_ctrl1_ois.mode4_en ) {
+
+ switch (ui_ctrl1_ois.mode4_en)
+ {
case LSM6DSOX_XL_OIS_OFF:
val->ois.xl.odr = LSM6DSOX_XL_OIS_OFF;
break;
+
case LSM6DSOX_XL_OIS_6667Hz_HP:
val->ois.xl.odr = LSM6DSOX_XL_OIS_6667Hz_HP;
break;
+
default:
val->ois.xl.odr = LSM6DSOX_XL_OIS_OFF;
break;
}
+
val->ois.ctrl_md = LSM6DSOX_OIS_ONLY_UI;
break;
+
case LSM6DSOX_OIS_MIXED:
- switch ( spi2_ctrl3_ois.fs_xl_ois ) {
+ switch (spi2_ctrl3_ois.fs_xl_ois)
+ {
case LSM6DSOX_XL_OIS_2g:
val->ois.xl.fs = LSM6DSOX_XL_OIS_2g;
break;
+
case LSM6DSOX_XL_OIS_4g:
val->ois.xl.fs = LSM6DSOX_XL_OIS_4g;
break;
+
case LSM6DSOX_XL_OIS_8g:
val->ois.xl.fs = LSM6DSOX_XL_OIS_8g;
break;
+
case LSM6DSOX_XL_OIS_16g:
val->ois.xl.fs = LSM6DSOX_XL_OIS_16g;
break;
+
default:
val->ois.xl.fs = LSM6DSOX_XL_OIS_2g;
break;
}
- switch ( spi2_ctrl1_ois.mode4_en ) {
+
+ switch (spi2_ctrl1_ois.mode4_en)
+ {
case LSM6DSOX_XL_OIS_OFF:
val->ois.xl.odr = LSM6DSOX_XL_OIS_OFF;
break;
+
case LSM6DSOX_XL_OIS_6667Hz_HP:
val->ois.xl.odr = LSM6DSOX_XL_OIS_6667Hz_HP;
break;
+
default:
val->ois.xl.odr = LSM6DSOX_XL_OIS_OFF;
break;
}
- switch ( spi2_ctrl1_ois.fs_g_ois ) {
+
+ switch (spi2_ctrl1_ois.fs_g_ois)
+ {
case LSM6DSOX_GY_OIS_250dps:
val->ois.gy.fs = LSM6DSOX_GY_OIS_250dps;
break;
+
case LSM6DSOX_GY_OIS_500dps:
val->ois.gy.fs = LSM6DSOX_GY_OIS_500dps;
break;
+
case LSM6DSOX_GY_OIS_1000dps:
val->ois.gy.fs = LSM6DSOX_GY_OIS_1000dps;
break;
+
case LSM6DSOX_GY_OIS_2000dps:
val->ois.gy.fs = LSM6DSOX_GY_OIS_2000dps;
break;
+
default:
val->ois.gy.fs = LSM6DSOX_GY_OIS_250dps;
break;
}
- switch ( ui_ctrl1_ois.ois_en_spi2 ) {
+
+ switch (ui_ctrl1_ois.ois_en_spi2)
+ {
case LSM6DSOX_GY_OIS_OFF:
val->ois.gy.odr = LSM6DSOX_GY_OIS_OFF;
break;
+
case LSM6DSOX_GY_OIS_6667Hz_HP:
val->ois.gy.odr = LSM6DSOX_GY_OIS_6667Hz_HP;
break;
+
default:
val->ois.gy.odr = LSM6DSOX_GY_OIS_OFF;
break;
}
+
val->ois.ctrl_md = LSM6DSOX_OIS_MIXED;
break;
+
default:
spi2_ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
- spi2_ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr | (uint8_t)val->ois.xl.odr;
+ spi2_ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr |
+ (uint8_t)val->ois.xl.odr;
spi2_ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr;
spi2_ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
val->ois.ctrl_md = LSM6DSOX_OIS_ONLY_AUX;
@@ -11730,6 +14102,7 @@ int32_t lsm6dsox_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
*
* @param ctx communication interface handler.(ptr)
* @param md the sensor conversion parameters.(ptr)
+ * @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lsm6dsox_data_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
@@ -11737,45 +14110,57 @@ int32_t lsm6dsox_data_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
{
uint8_t buff[14];
int32_t ret;
+
uint8_t i;
uint8_t j;
-
ret = 0;
/* read data */
- if( ctx != NULL ) {
+ if (ctx != NULL)
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_OUT_TEMP_L, buff, 14);
}
- j = 0;
+ j = 0;
/* temperature conversion */
- data->ui.heat.raw = (int16_t)buff[j+1U];
- data->ui.heat.raw = ( ((int16_t)data->ui.heat.raw * (int16_t)256) +
- (int16_t)buff[j] );
- j+=2U;
- data->ui.heat.deg_c = lsm6dsox_from_lsb_to_celsius((int16_t)data->ui.heat.raw);
+ data->ui.heat.raw = (int16_t)buff[j + 1U];
+ data->ui.heat.raw = (((int16_t)data->ui.heat.raw * (int16_t)256) +
+ (int16_t)buff[j]);
+ j += 2U;
+ data->ui.heat.deg_c = lsm6dsox_from_lsb_to_celsius((
+ int16_t)data->ui.heat.raw);
/* angular rate conversion */
- for (i = 0U; i < 3U; i++) {
- data->ui.gy.raw[i] = (int16_t)buff[j+1U];
+ for (i = 0U; i < 3U; i++)
+ {
+ data->ui.gy.raw[i] = (int16_t)buff[j + 1U];
data->ui.gy.raw[i] = (data->ui.gy.raw[i] * 256) + (int16_t) buff[j];
- j+=2U;
- switch ( md->ui.gy.fs ) {
+ j += 2U;
+
+ switch (md->ui.gy.fs)
+ {
case LSM6DSOX_GY_UI_250dps:
data->ui.gy.mdps[i] = lsm6dsox_from_fs250_to_mdps(data->ui.gy.raw[i]);
break;
+
case LSM6DSOX_GY_UI_125dps:
data->ui.gy.mdps[i] = lsm6dsox_from_fs125_to_mdps(data->ui.gy.raw[i]);
break;
+
case LSM6DSOX_GY_UI_500dps:
data->ui.gy.mdps[i] = lsm6dsox_from_fs500_to_mdps(data->ui.gy.raw[i]);
break;
+
case LSM6DSOX_GY_UI_1000dps:
- data->ui.gy.mdps[i] = lsm6dsox_from_fs1000_to_mdps(data->ui.gy.raw[i]);
+ data->ui.gy.mdps[i] = lsm6dsox_from_fs1000_to_mdps(
+ data->ui.gy.raw[i]);
break;
+
case LSM6DSOX_GY_UI_2000dps:
- data->ui.gy.mdps[i] = lsm6dsox_from_fs2000_to_mdps(data->ui.gy.raw[i]);
+ data->ui.gy.mdps[i] = lsm6dsox_from_fs2000_to_mdps(
+ data->ui.gy.raw[i]);
break;
+
default:
data->ui.gy.mdps[i] = 0.0f;
break;
@@ -11783,64 +14168,90 @@ int32_t lsm6dsox_data_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
}
/* acceleration conversion */
- for (i = 0U; i < 3U; i++) {
- data->ui.xl.raw[i] = (int16_t)buff[j+1U];
+ for (i = 0U; i < 3U; i++)
+ {
+ data->ui.xl.raw[i] = (int16_t)buff[j + 1U];
data->ui.xl.raw[i] = (data->ui.xl.raw[i] * 256) + (int16_t) buff[j];
- j+=2U;
- switch ( md->ui.xl.fs ) {
+ j += 2U;
+
+ switch (md->ui.xl.fs)
+ {
case LSM6DSOX_XL_UI_2g:
- data->ui.xl.mg[i] =lsm6dsox_from_fs2_to_mg(data->ui.xl.raw[i]);
+ data->ui.xl.mg[i] = lsm6dsox_from_fs2_to_mg(data->ui.xl.raw[i]);
break;
+
case LSM6DSOX_XL_UI_4g:
- data->ui.xl.mg[i] =lsm6dsox_from_fs4_to_mg(data->ui.xl.raw[i]);
+ data->ui.xl.mg[i] = lsm6dsox_from_fs4_to_mg(data->ui.xl.raw[i]);
break;
+
case LSM6DSOX_XL_UI_8g:
- data->ui.xl.mg[i] =lsm6dsox_from_fs8_to_mg(data->ui.xl.raw[i]);
+ data->ui.xl.mg[i] = lsm6dsox_from_fs8_to_mg(data->ui.xl.raw[i]);
break;
+
case LSM6DSOX_XL_UI_16g:
- data->ui.xl.mg[i] =lsm6dsox_from_fs16_to_mg(data->ui.xl.raw[i]);
+ data->ui.xl.mg[i] = lsm6dsox_from_fs16_to_mg(data->ui.xl.raw[i]);
break;
+
default:
data->ui.xl.mg[i] = 0.0f;
break;
}
-
}
/* read data from ois chain */
- if (aux_ctx != NULL) {
- if (ret == 0) {
- ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_OUTX_L_G_OIS, buff, 12);
+ if (aux_ctx != NULL)
+ {
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_OUTX_L_G_OIS, buff,
+ 12);
}
}
- else {
- if ((ctx != NULL) && (md->ois.ctrl_md == LSM6DSOX_OIS_ONLY_UI)) {
+
+ else
+ {
+ if ((ctx != NULL) && (md->ois.ctrl_md == LSM6DSOX_OIS_ONLY_UI))
+ {
ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_OUTX_L_G_OIS, buff, 12);
}
}
+
j = 0;
/* ois angular rate conversion */
- for (i = 0U; i < 3U; i++) {
- data->ois.gy.raw[i] = (int16_t) buff[j+1U];
+ for (i = 0U; i < 3U; i++)
+ {
+ data->ois.gy.raw[i] = (int16_t) buff[j + 1U];
data->ois.gy.raw[i] = (data->ois.gy.raw[i] * 256) + (int16_t) buff[j];
- j+=2U;
- switch ( md->ois.gy.fs ) {
+ j += 2U;
+
+ switch (md->ois.gy.fs)
+ {
case LSM6DSOX_GY_UI_250dps:
- data->ois.gy.mdps[i] = lsm6dsox_from_fs250_to_mdps(data->ois.gy.raw[i]);
+ data->ois.gy.mdps[i] = lsm6dsox_from_fs250_to_mdps(
+ data->ois.gy.raw[i]);
break;
+
case LSM6DSOX_GY_UI_125dps:
- data->ois.gy.mdps[i] = lsm6dsox_from_fs125_to_mdps(data->ois.gy.raw[i]);
+ data->ois.gy.mdps[i] = lsm6dsox_from_fs125_to_mdps(
+ data->ois.gy.raw[i]);
break;
+
case LSM6DSOX_GY_UI_500dps:
- data->ois.gy.mdps[i] = lsm6dsox_from_fs500_to_mdps(data->ois.gy.raw[i]);
+ data->ois.gy.mdps[i] = lsm6dsox_from_fs500_to_mdps(
+ data->ois.gy.raw[i]);
break;
+
case LSM6DSOX_GY_UI_1000dps:
- data->ois.gy.mdps[i] = lsm6dsox_from_fs1000_to_mdps(data->ois.gy.raw[i]);
+ data->ois.gy.mdps[i] = lsm6dsox_from_fs1000_to_mdps(
+ data->ois.gy.raw[i]);
break;
+
case LSM6DSOX_GY_UI_2000dps:
- data->ois.gy.mdps[i] = lsm6dsox_from_fs2000_to_mdps(data->ois.gy.raw[i]);
+ data->ois.gy.mdps[i] = lsm6dsox_from_fs2000_to_mdps(
+ data->ois.gy.raw[i]);
break;
+
default:
data->ois.gy.mdps[i] = 0.0f;
break;
@@ -11848,23 +14259,30 @@ int32_t lsm6dsox_data_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
}
/* ois acceleration conversion */
- for (i = 0U; i < 3U; i++) {
- data->ois.xl.raw[i] = (int16_t) buff[j+1U];
+ for (i = 0U; i < 3U; i++)
+ {
+ data->ois.xl.raw[i] = (int16_t) buff[j + 1U];
data->ois.xl.raw[i] = (data->ois.xl.raw[i] * 256) + (int16_t) buff[j];
- j+=2U;
- switch ( md->ois.xl.fs ) {
+ j += 2U;
+
+ switch (md->ois.xl.fs)
+ {
case LSM6DSOX_XL_UI_2g:
- data->ois.xl.mg[i] =lsm6dsox_from_fs2_to_mg(data->ois.xl.raw[i]);
+ data->ois.xl.mg[i] = lsm6dsox_from_fs2_to_mg(data->ois.xl.raw[i]);
break;
+
case LSM6DSOX_XL_UI_4g:
- data->ois.xl.mg[i] =lsm6dsox_from_fs4_to_mg(data->ois.xl.raw[i]);
+ data->ois.xl.mg[i] = lsm6dsox_from_fs4_to_mg(data->ois.xl.raw[i]);
break;
+
case LSM6DSOX_XL_UI_8g:
- data->ois.xl.mg[i] =lsm6dsox_from_fs8_to_mg(data->ois.xl.raw[i]);
+ data->ois.xl.mg[i] = lsm6dsox_from_fs8_to_mg(data->ois.xl.raw[i]);
break;
+
case LSM6DSOX_XL_UI_16g:
- data->ois.xl.mg[i] =lsm6dsox_from_fs16_to_mg(data->ois.xl.raw[i]);
+ data->ois.xl.mg[i] = lsm6dsox_from_fs16_to_mg(data->ois.xl.raw[i]);
break;
+
default:
data->ois.xl.mg[i] = 0.0f;
break;
@@ -11874,6 +14292,160 @@ int32_t lsm6dsox_data_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
return ret;
}
+/**
+ * @brief Embedded functions.[set]
+ *
+ * @param ctx read / write interface definitions
+ * @param val change the values of registers
+ * EMB_FUNC_EN_A e EMB_FUNC_EN_B.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lsm6dsox_embedded_sens_set(stmdev_ctx_t *ctx,
+ lsm6dsox_emb_sens_t *val)
+{
+ lsm6dsox_emb_func_en_a_t emb_func_en_a;
+ lsm6dsox_emb_func_en_b_t emb_func_en_b;
+ int32_t ret;
+
+ ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A,
+ (uint8_t *)&emb_func_en_a, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B,
+ (uint8_t *)&emb_func_en_b, 1);
+ emb_func_en_b.mlc_en = val->mlc;
+ emb_func_en_b.fsm_en = val->fsm;
+ emb_func_en_a.tilt_en = val->tilt;
+ emb_func_en_a.pedo_en = val->step;
+ emb_func_en_a.sign_motion_en = val->sig_mot;
+ emb_func_en_b.fifo_compr_en = val->fifo_compr;
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A,
+ (uint8_t *)&emb_func_en_a, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B,
+ (uint8_t *)&emb_func_en_b, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Embedded functions.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val get the values of registers
+ * EMB_FUNC_EN_A e EMB_FUNC_EN_B.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lsm6dsox_embedded_sens_get(stmdev_ctx_t *ctx,
+ lsm6dsox_emb_sens_t *emb_sens)
+{
+ lsm6dsox_emb_func_en_a_t emb_func_en_a;
+ lsm6dsox_emb_func_en_b_t emb_func_en_b;
+ int32_t ret;
+
+ ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A,
+ (uint8_t *)&emb_func_en_a, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B,
+ (uint8_t *)&emb_func_en_b, 1);
+ emb_sens->mlc = emb_func_en_b.mlc_en;
+ emb_sens->fsm = emb_func_en_b.fsm_en;
+ emb_sens->tilt = emb_func_en_a.tilt_en;
+ emb_sens->step = emb_func_en_a.pedo_en;
+ emb_sens->sig_mot = emb_func_en_a.sign_motion_en;
+ emb_sens->fifo_compr = emb_func_en_b.fifo_compr_en;
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief turn off all embedded functions.[get]
+ *
+ * @param ctx read / write interface definitions
+ * @param val get the values of registers
+ * EMB_FUNC_EN_A e EMB_FUNC_EN_B.
+ * @retval interface status (MANDATORY: return 0 -> no Error)
+ *
+ */
+int32_t lsm6dsox_embedded_sens_off(stmdev_ctx_t *ctx)
+{
+ lsm6dsox_emb_func_en_a_t emb_func_en_a;
+ lsm6dsox_emb_func_en_b_t emb_func_en_b;
+ int32_t ret;
+
+ ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A,
+ (uint8_t *)&emb_func_en_a, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B,
+ (uint8_t *)&emb_func_en_b, 1);
+ emb_func_en_b.mlc_en = PROPERTY_DISABLE;
+ emb_func_en_b.fsm_en = PROPERTY_DISABLE;
+ emb_func_en_a.tilt_en = PROPERTY_DISABLE;
+ emb_func_en_a.pedo_en = PROPERTY_DISABLE;
+ emb_func_en_a.sign_motion_en = PROPERTY_DISABLE;
+ emb_func_en_b.fifo_compr_en = PROPERTY_DISABLE;
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A,
+ (uint8_t *)&emb_func_en_a, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B,
+ (uint8_t *)&emb_func_en_b, 1);
+ }
+
+ if (ret == 0)
+ {
+ ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
+ }
+
+ return ret;
+}
/**
* @}
diff --git a/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.h b/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.h
index 8ad64f2290023e8fd90999a721ec116b67edad79..f4e3668aa8651ee8a22c6a2ccbf459050278217e 100644
--- a/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.h
+++ b/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.h
@@ -1,29 +1,29 @@
-/*
- ******************************************************************************
- * @file lsm6dsox_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lsm6dsox_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lsm6dsox_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lsm6dsox_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LSM6DSOX_REGS_H
#define LSM6DSOX_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -36,6 +36,37 @@
*
*/
+/** @defgroup Endianness definitions
+ * @{
+ *
+ */
+
+#ifndef DRV_BYTE_ORDER
+#ifndef __BYTE_ORDER__
+
+#define DRV_LITTLE_ENDIAN 1234
+#define DRV_BIG_ENDIAN 4321
+
+/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
+ * by uncommenting the define which fits your platform endianness
+ */
+//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
+#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
+
+#else /* defined __BYTE_ORDER__ */
+
+#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
+#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
+#define DRV_BYTE_ORDER __BYTE_ORDER__
+
+#endif /* __BYTE_ORDER__*/
+#endif /* DRV_BYTE_ORDER */
+
+/**
+ * @}
+ *
+ */
+
/** @defgroup STMicroelectronics sensors common types
* @{
*
@@ -44,7 +75,9 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -53,6 +86,16 @@ typedef struct{
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} bitwise_t;
#define PROPERTY_DISABLE (0U)
@@ -66,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -98,7 +142,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -133,43 +178,75 @@ typedef struct {
*/
#define LSM6DSOX_FUNC_CFG_ACCESS 0x01U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ois_ctrl_from_ui : 1;
uint8_t not_used_01 : 5;
- uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */
+uint8_t reg_access :
+ 2; /* shub_reg_access + func_cfg_access */
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+uint8_t reg_access :
+ 2; /* shub_reg_access + func_cfg_access */
+ uint8_t not_used_01 : 5;
+ uint8_t ois_ctrl_from_ui : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_func_cfg_access_t;
#define LSM6DSOX_PIN_CTRL 0x02U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 6;
uint8_t sdo_pu_en : 1;
uint8_t ois_pu_dis : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t ois_pu_dis : 1;
+ uint8_t sdo_pu_en : 1;
+ uint8_t not_used_01 : 6;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_pin_ctrl_t;
#define LSM6DSOX_S4S_TPH_L 0x04U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tph_l : 7;
uint8_t tph_h_sel : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t tph_h_sel : 1;
+ uint8_t tph_l : 7;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_s4s_tph_l_t;
#define LSM6DSOX_S4S_TPH_H 0x05U
-typedef struct {
+typedef struct
+{
uint8_t tph_h : 8;
} lsm6dsox_s4s_tph_h_t;
#define LSM6DSOX_S4S_RR 0x06U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t rr : 2;
uint8_t not_used_01 : 6;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 6;
+ uint8_t rr : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_s4s_rr_t;
#define LSM6DSOX_FIFO_CTRL1 0x07U
-typedef struct {
+typedef struct
+{
uint8_t wtm : 8;
} lsm6dsox_fifo_ctrl1_t;
#define LSM6DSOX_FIFO_CTRL2 0x08U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wtm : 1;
uint8_t uncoptr_rate : 2;
uint8_t not_used_01 : 1;
@@ -177,38 +254,73 @@ typedef struct {
uint8_t not_used_02 : 1;
uint8_t fifo_compr_rt_en : 1;
uint8_t stop_on_wtm : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t stop_on_wtm : 1;
+ uint8_t fifo_compr_rt_en : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t odrchg_en : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t uncoptr_rate : 2;
+ uint8_t wtm : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fifo_ctrl2_t;
#define LSM6DSOX_FIFO_CTRL3 0x09U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bdr_xl : 4;
uint8_t bdr_gy : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bdr_gy : 4;
+ uint8_t bdr_xl : 4;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fifo_ctrl3_t;
#define LSM6DSOX_FIFO_CTRL4 0x0AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fifo_mode : 3;
uint8_t not_used_01 : 1;
uint8_t odr_t_batch : 2;
uint8_t odr_ts_batch : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr_ts_batch : 2;
+ uint8_t odr_t_batch : 2;
+ uint8_t not_used_01 : 1;
+ uint8_t fifo_mode : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fifo_ctrl4_t;
#define LSM6DSOX_COUNTER_BDR_REG1 0x0BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t cnt_bdr_th : 3;
uint8_t not_used_01 : 2;
uint8_t trig_counter_bdr : 1;
uint8_t rst_counter_bdr : 1;
uint8_t dataready_pulsed : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t dataready_pulsed : 1;
+ uint8_t rst_counter_bdr : 1;
+ uint8_t trig_counter_bdr : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t cnt_bdr_th : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_counter_bdr_reg1_t;
#define LSM6DSOX_COUNTER_BDR_REG2 0x0CU
-typedef struct {
+typedef struct
+{
uint8_t cnt_bdr_th : 8;
} lsm6dsox_counter_bdr_reg2_t;
#define LSM6DSOX_INT1_CTRL 0x0D
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_drdy_xl : 1;
uint8_t int1_drdy_g : 1;
uint8_t int1_boot : 1;
@@ -217,10 +329,22 @@ typedef struct {
uint8_t int1_fifo_full : 1;
uint8_t int1_cnt_bdr : 1;
uint8_t den_drdy_flag : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t den_drdy_flag : 1;
+ uint8_t int1_cnt_bdr : 1;
+ uint8_t int1_fifo_full : 1;
+ uint8_t int1_fifo_ovr : 1;
+ uint8_t int1_fifo_th : 1;
+ uint8_t int1_boot : 1;
+ uint8_t int1_drdy_g : 1;
+ uint8_t int1_drdy_xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_int1_ctrl_t;
#define LSM6DSOX_INT2_CTRL 0x0EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_drdy_xl : 1;
uint8_t int2_drdy_g : 1;
uint8_t int2_drdy_temp : 1;
@@ -229,26 +353,53 @@ typedef struct {
uint8_t int2_fifo_full : 1;
uint8_t int2_cnt_bdr : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t int2_cnt_bdr : 1;
+ uint8_t int2_fifo_full : 1;
+ uint8_t int2_fifo_ovr : 1;
+ uint8_t int2_fifo_th : 1;
+ uint8_t int2_drdy_temp : 1;
+ uint8_t int2_drdy_g : 1;
+ uint8_t int2_drdy_xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_int2_ctrl_t;
#define LSM6DSOX_WHO_AM_I 0x0FU
#define LSM6DSOX_CTRL1_XL 0x10U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t lpf2_xl_en : 1;
uint8_t fs_xl : 2;
uint8_t odr_xl : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr_xl : 4;
+ uint8_t fs_xl : 2;
+ uint8_t lpf2_xl_en : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_ctrl1_xl_t;
#define LSM6DSOX_CTRL2_G 0x11U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t fs_g : 3; /* fs_125 + fs_g */
uint8_t odr_g : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr_g : 4;
+ uint8_t fs_g : 3; /* fs_125 + fs_g */
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_ctrl2_g_t;
#define LSM6DSOX_CTRL3_C 0x12U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sw_reset : 1;
uint8_t not_used_01 : 1;
uint8_t if_inc : 1;
@@ -257,10 +408,22 @@ typedef struct {
uint8_t h_lactive : 1;
uint8_t bdu : 1;
uint8_t boot : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t boot : 1;
+ uint8_t bdu : 1;
+ uint8_t h_lactive : 1;
+ uint8_t pp_od : 1;
+ uint8_t sim : 1;
+ uint8_t if_inc : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t sw_reset : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_ctrl3_c_t;
#define LSM6DSOX_CTRL4_C 0x13U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t lpf1_sel_g : 1;
uint8_t i2c_disable : 1;
@@ -269,27 +432,58 @@ typedef struct {
uint8_t int2_on_int1 : 1;
uint8_t sleep_g : 1;
uint8_t not_used_03 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_03 : 1;
+ uint8_t sleep_g : 1;
+ uint8_t int2_on_int1 : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t drdy_mask : 1;
+ uint8_t i2c_disable : 1;
+ uint8_t lpf1_sel_g : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_ctrl4_c_t;
#define LSM6DSOX_CTRL5_C 0x14U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_xl : 2;
uint8_t st_g : 2;
uint8_t rounding_status : 1;
uint8_t rounding : 2;
uint8_t xl_ulp_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t xl_ulp_en : 1;
+ uint8_t rounding : 2;
+ uint8_t rounding_status : 1;
+ uint8_t st_g : 2;
+ uint8_t st_xl : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_ctrl5_c_t;
#define LSM6DSOX_CTRL6_C 0x15U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ftype : 3;
uint8_t usr_off_w : 1;
uint8_t xl_hm_mode : 1;
- uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */
+uint8_t den_mode :
+ 3; /* trig_en + lvl1_en + lvl2_en */
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+uint8_t den_mode :
+ 3; /* trig_en + lvl1_en + lvl2_en */
+ uint8_t xl_hm_mode : 1;
+ uint8_t usr_off_w : 1;
+ uint8_t ftype : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_ctrl6_c_t;
#define LSM6DSOX_CTRL7_G 0x16U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ois_on : 1;
uint8_t usr_off_on_out : 1;
uint8_t ois_on_en : 1;
@@ -297,20 +491,41 @@ typedef struct {
uint8_t hpm_g : 2;
uint8_t hp_en_g : 1;
uint8_t g_hm_mode : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t g_hm_mode : 1;
+ uint8_t hp_en_g : 1;
+ uint8_t hpm_g : 2;
+ uint8_t not_used_01 : 1;
+ uint8_t ois_on_en : 1;
+ uint8_t usr_off_on_out : 1;
+ uint8_t ois_on : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_ctrl7_g_t;
#define LSM6DSOX_CTRL8_XL 0x17U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t low_pass_on_6d : 1;
uint8_t xl_fs_mode : 1;
uint8_t hp_slope_xl_en : 1;
uint8_t fastsettl_mode_xl : 1;
uint8_t hp_ref_mode_xl : 1;
uint8_t hpcf_xl : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t hpcf_xl : 3;
+ uint8_t hp_ref_mode_xl : 1;
+ uint8_t fastsettl_mode_xl : 1;
+ uint8_t hp_slope_xl_en : 1;
+ uint8_t xl_fs_mode : 1;
+ uint8_t low_pass_on_6d : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_ctrl8_xl_t;
#define LSM6DSOX_CTRL9_XL 0x18U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t i3c_disable : 1;
uint8_t den_lh : 1;
@@ -318,17 +533,35 @@ typedef struct {
uint8_t den_z : 1;
uint8_t den_y : 1;
uint8_t den_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t den_x : 1;
+ uint8_t den_y : 1;
+ uint8_t den_z : 1;
+ uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */
+ uint8_t den_lh : 1;
+ uint8_t i3c_disable : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_ctrl9_xl_t;
#define LSM6DSOX_CTRL10_C 0x19U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 5;
uint8_t timestamp_en : 1;
uint8_t not_used_02 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 2;
+ uint8_t timestamp_en : 1;
+ uint8_t not_used_01 : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_ctrl10_c_t;
#define LSM6DSOX_ALL_INT_SRC 0x1AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ia : 1;
uint8_t wu_ia : 1;
uint8_t single_tap : 1;
@@ -337,10 +570,22 @@ typedef struct {
uint8_t sleep_change_ia : 1;
uint8_t not_used_01 : 1;
uint8_t timestamp_endcount : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t timestamp_endcount : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t sleep_change_ia : 1;
+ uint8_t d6d_ia : 1;
+ uint8_t double_tap : 1;
+ uint8_t single_tap : 1;
+ uint8_t wu_ia : 1;
+ uint8_t ff_ia : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_all_int_src_t;
#define LSM6DSOX_WAKE_UP_SRC 0x1BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_wu : 1;
uint8_t y_wu : 1;
uint8_t x_wu : 1;
@@ -348,10 +593,21 @@ typedef struct {
uint8_t sleep_state : 1;
uint8_t ff_ia : 1;
uint8_t sleep_change_ia : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t sleep_change_ia : 2;
+ uint8_t ff_ia : 1;
+ uint8_t sleep_state : 1;
+ uint8_t wu_ia : 1;
+ uint8_t x_wu : 1;
+ uint8_t y_wu : 1;
+ uint8_t z_wu : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_wake_up_src_t;
#define LSM6DSOX_TAP_SRC 0x1CU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_tap : 1;
uint8_t y_tap : 1;
uint8_t x_tap : 1;
@@ -360,10 +616,22 @@ typedef struct {
uint8_t single_tap : 1;
uint8_t tap_ia : 1;
uint8_t not_used_02 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 1;
+ uint8_t tap_ia : 1;
+ uint8_t single_tap : 1;
+ uint8_t double_tap : 1;
+ uint8_t tap_sign : 1;
+ uint8_t x_tap : 1;
+ uint8_t y_tap : 1;
+ uint8_t z_tap : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_tap_src_t;
#define LSM6DSOX_D6D_SRC 0x1DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
uint8_t yl : 1;
@@ -372,14 +640,32 @@ typedef struct {
uint8_t zh : 1;
uint8_t d6d_ia : 1;
uint8_t den_drdy : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t den_drdy : 1;
+ uint8_t d6d_ia : 1;
+ uint8_t zh : 1;
+ uint8_t zl : 1;
+ uint8_t yh : 1;
+ uint8_t yl : 1;
+ uint8_t xh : 1;
+ uint8_t xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_d6d_src_t;
#define LSM6DSOX_STATUS_REG 0x1EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlda : 1;
uint8_t gda : 1;
uint8_t tda : 1;
uint8_t not_used_01 : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 5;
+ uint8_t tda : 1;
+ uint8_t gda : 1;
+ uint8_t xlda : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_status_reg_t;
#define LSM6DSOX_OUT_TEMP_L 0x20U
@@ -397,17 +683,29 @@ typedef struct {
#define LSM6DSOX_OUTZ_L_A 0x2CU
#define LSM6DSOX_OUTZ_H_A 0x2DU
#define LSM6DSOX_EMB_FUNC_STATUS_MAINPAGE 0x35U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t is_step_det : 1;
uint8_t is_tilt : 1;
uint8_t is_sigmot : 1;
uint8_t not_used_02 : 1;
uint8_t is_fsm_lc : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_fsm_lc : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t is_sigmot : 1;
+ uint8_t is_tilt : 1;
+ uint8_t is_step_det : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_emb_func_status_mainpage_t;
#define LSM6DSOX_FSM_STATUS_A_MAINPAGE 0x36U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_fsm1 : 1;
uint8_t is_fsm2 : 1;
uint8_t is_fsm3 : 1;
@@ -416,10 +714,22 @@ typedef struct {
uint8_t is_fsm6 : 1;
uint8_t is_fsm7 : 1;
uint8_t is_fsm8 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_fsm8 : 1;
+ uint8_t is_fsm7 : 1;
+ uint8_t is_fsm6 : 1;
+ uint8_t is_fsm5 : 1;
+ uint8_t is_fsm4 : 1;
+ uint8_t is_fsm3 : 1;
+ uint8_t is_fsm2 : 1;
+ uint8_t is_fsm1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fsm_status_a_mainpage_t;
#define LSM6DSOX_FSM_STATUS_B_MAINPAGE 0x37U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_fsm9 : 1;
uint8_t is_fsm10 : 1;
uint8_t is_fsm11 : 1;
@@ -428,10 +738,22 @@ typedef struct {
uint8_t is_fsm14 : 1;
uint8_t is_fsm15 : 1;
uint8_t is_fsm16 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_fsm16 : 1;
+ uint8_t is_fsm15 : 1;
+ uint8_t is_fsm14 : 1;
+ uint8_t is_fsm13 : 1;
+ uint8_t is_fsm12 : 1;
+ uint8_t is_fsm11 : 1;
+ uint8_t is_fsm10 : 1;
+ uint8_t is_fsm9 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fsm_status_b_mainpage_t;
#define LSM6DSOX_MLC_STATUS_MAINPAGE 0x38U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_mlc1 : 1;
uint8_t is_mlc2 : 1;
uint8_t is_mlc3 : 1;
@@ -440,10 +762,22 @@ typedef struct {
uint8_t is_mlc6 : 1;
uint8_t is_mlc7 : 1;
uint8_t is_mlc8 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_mlc8 : 1;
+ uint8_t is_mlc7 : 1;
+ uint8_t is_mlc6 : 1;
+ uint8_t is_mlc5 : 1;
+ uint8_t is_mlc4 : 1;
+ uint8_t is_mlc3 : 1;
+ uint8_t is_mlc2 : 1;
+ uint8_t is_mlc1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_mlc_status_mainpage_t;
#define LSM6DSOX_STATUS_MASTER_MAINPAGE 0x39U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sens_hub_endop : 1;
uint8_t not_used_01 : 2;
uint8_t slave0_nack : 1;
@@ -451,15 +785,27 @@ typedef struct {
uint8_t slave2_nack : 1;
uint8_t slave3_nack : 1;
uint8_t wr_once_done : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t wr_once_done : 1;
+ uint8_t slave3_nack : 1;
+ uint8_t slave2_nack : 1;
+ uint8_t slave1_nack : 1;
+ uint8_t slave0_nack : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t sens_hub_endop : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_status_master_mainpage_t;
#define LSM6DSOX_FIFO_STATUS1 0x3AU
-typedef struct {
+typedef struct
+{
uint8_t diff_fifo : 8;
} lsm6dsox_fifo_status1_t;
#define LSM6DSOX_FIFO_STATUS2 0x3B
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t diff_fifo : 2;
uint8_t not_used_01 : 1;
uint8_t over_run_latched : 1;
@@ -467,6 +813,15 @@ typedef struct {
uint8_t fifo_full_ia : 1;
uint8_t fifo_ovr_ia : 1;
uint8_t fifo_wtm_ia : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fifo_wtm_ia : 1;
+ uint8_t fifo_ovr_ia : 1;
+ uint8_t fifo_full_ia : 1;
+ uint8_t counter_bdr_ia : 1;
+ uint8_t over_run_latched : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t diff_fifo : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fifo_status2_t;
#define LSM6DSOX_TIMESTAMP0 0x40U
@@ -474,11 +829,19 @@ typedef struct {
#define LSM6DSOX_TIMESTAMP2 0x42U
#define LSM6DSOX_TIMESTAMP3 0x43U
#define LSM6DSOX_UI_STATUS_REG_OIS 0x49U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlda : 1;
uint8_t gda : 1;
uint8_t gyro_settling : 1;
uint8_t not_used_01 : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 5;
+ uint8_t gyro_settling : 1;
+ uint8_t gda : 1;
+ uint8_t xlda : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_ui_status_reg_ois_t;
#define LSM6DSOX_UI_OUTX_L_G_OIS 0x4AU
@@ -495,7 +858,9 @@ typedef struct {
#define LSM6DSOX_UI_OUTZ_H_A_OIS 0x55U
#define LSM6DSOX_TAP_CFG0 0x56U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lir : 1;
uint8_t tap_z_en : 1;
uint8_t tap_y_en : 1;
@@ -504,58 +869,118 @@ typedef struct {
uint8_t sleep_status_on_int : 1;
uint8_t int_clr_on_read : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t int_clr_on_read : 1;
+ uint8_t sleep_status_on_int : 1;
+ uint8_t slope_fds : 1;
+ uint8_t tap_x_en : 1;
+ uint8_t tap_y_en : 1;
+ uint8_t tap_z_en : 1;
+ uint8_t lir : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_tap_cfg0_t;
#define LSM6DSOX_TAP_CFG1 0x57U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_ths_x : 5;
uint8_t tap_priority : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t tap_priority : 3;
+ uint8_t tap_ths_x : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_tap_cfg1_t;
#define LSM6DSOX_TAP_CFG2 0x58U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_ths_y : 5;
uint8_t inact_en : 2;
uint8_t interrupts_enable : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t interrupts_enable : 1;
+ uint8_t inact_en : 2;
+ uint8_t tap_ths_y : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_tap_cfg2_t;
#define LSM6DSOX_TAP_THS_6D 0x59U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_ths_z : 5;
uint8_t sixd_ths : 2;
uint8_t d4d_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t d4d_en : 1;
+ uint8_t sixd_ths : 2;
+ uint8_t tap_ths_z : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_tap_ths_6d_t;
#define LSM6DSOX_INT_DUR2 0x5AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shock : 2;
uint8_t quiet : 2;
uint8_t dur : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t dur : 4;
+ uint8_t quiet : 2;
+ uint8_t shock : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_int_dur2_t;
#define LSM6DSOX_WAKE_UP_THS 0x5BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wk_ths : 6;
uint8_t usr_off_on_wu : 1;
uint8_t single_double_tap : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t single_double_tap : 1;
+ uint8_t usr_off_on_wu : 1;
+ uint8_t wk_ths : 6;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_wake_up_ths_t;
#define LSM6DSOX_WAKE_UP_DUR 0x5CU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sleep_dur : 4;
uint8_t wake_ths_w : 1;
uint8_t wake_dur : 2;
uint8_t ff_dur : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t ff_dur : 1;
+ uint8_t wake_dur : 2;
+ uint8_t wake_ths_w : 1;
+ uint8_t sleep_dur : 4;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_wake_up_dur_t;
#define LSM6DSOX_FREE_FALL 0x5DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ths : 3;
uint8_t ff_dur : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t ff_dur : 5;
+ uint8_t ff_ths : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_free_fall_t;
#define LSM6DSOX_MD1_CFG 0x5EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_shub : 1;
uint8_t int1_emb_func : 1;
uint8_t int1_6d : 1;
@@ -564,10 +989,22 @@ typedef struct {
uint8_t int1_wu : 1;
uint8_t int1_single_tap : 1;
uint8_t int1_sleep_change : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_sleep_change : 1;
+ uint8_t int1_single_tap : 1;
+ uint8_t int1_wu : 1;
+ uint8_t int1_ff : 1;
+ uint8_t int1_double_tap : 1;
+ uint8_t int1_6d : 1;
+ uint8_t int1_emb_func : 1;
+ uint8_t int1_shub : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_md1_cfg_t;
#define LSM6DSOX_MD2_CFG 0x5FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_timestamp : 1;
uint8_t int2_emb_func : 1;
uint8_t int2_6d : 1;
@@ -576,76 +1013,141 @@ typedef struct {
uint8_t int2_wu : 1;
uint8_t int2_single_tap : 1;
uint8_t int2_sleep_change : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_sleep_change : 1;
+ uint8_t int2_single_tap : 1;
+ uint8_t int2_wu : 1;
+ uint8_t int2_ff : 1;
+ uint8_t int2_double_tap : 1;
+ uint8_t int2_6d : 1;
+ uint8_t int2_emb_func : 1;
+ uint8_t int2_timestamp : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_md2_cfg_t;
#define LSM6DSOX_S4S_ST_CMD_CODE 0x60U
-typedef struct {
+typedef struct
+{
uint8_t s4s_st_cmd_code : 8;
} lsm6dsox_s4s_st_cmd_code_t;
#define LSM6DSOX_S4S_DT_REG 0x61U
-typedef struct {
+typedef struct
+{
uint8_t dt : 8;
} lsm6dsox_s4s_dt_reg_t;
#define LSM6DSOX_I3C_BUS_AVB 0x62U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t pd_dis_int1 : 1;
uint8_t not_used_01 : 2;
uint8_t i3c_bus_avb_sel : 2;
uint8_t not_used_02 : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 3;
+ uint8_t i3c_bus_avb_sel : 2;
+ uint8_t not_used_01 : 2;
+ uint8_t pd_dis_int1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_i3c_bus_avb_t;
#define LSM6DSOX_INTERNAL_FREQ_FINE 0x63U
-typedef struct {
+typedef struct
+{
uint8_t freq_fine : 8;
} lsm6dsox_internal_freq_fine_t;
#define LSM6DSOX_UI_INT_OIS 0x6F
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t spi2_read_en : 1;
uint8_t not_used_02 : 1;
uint8_t den_lh_ois : 1;
uint8_t lvl2_ois : 1;
uint8_t int2_drdy_ois : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_drdy_ois : 1;
+ uint8_t lvl2_ois : 1;
+ uint8_t den_lh_ois : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t spi2_read_en : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_ui_int_ois_t;
#define LSM6DSOX_UI_CTRL1_OIS 0x70U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ois_en_spi2 : 1;
uint8_t fs_g_ois : 3; /* fs_125_ois + fs[1:0]_g_ois */
uint8_t mode4_en : 1;
uint8_t sim_ois : 1;
uint8_t lvl1_ois : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t lvl1_ois : 1;
+ uint8_t sim_ois : 1;
+ uint8_t mode4_en : 1;
+ uint8_t fs_g_ois : 3; /* fs_125_ois + fs[1:0]_g_ois */
+ uint8_t ois_en_spi2 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_ui_ctrl1_ois_t;
#define LSM6DSOX_UI_CTRL2_OIS 0x71U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t hp_en_ois : 1;
uint8_t ftype_ois : 2;
uint8_t not_used_01 : 1;
uint8_t hpm_ois : 2;
uint8_t not_used_02 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 2;
+ uint8_t hpm_ois : 2;
+ uint8_t not_used_01 : 1;
+ uint8_t ftype_ois : 2;
+ uint8_t hp_en_ois : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_ui_ctrl2_ois_t;
#define LSM6DSOX_UI_CTRL3_OIS 0x72U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_ois_clampdis : 1;
uint8_t not_used_01 : 2;
uint8_t filter_xl_conf_ois : 3;
uint8_t fs_xl_ois : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fs_xl_ois : 2;
+ uint8_t filter_xl_conf_ois : 3;
+ uint8_t not_used_01 : 2;
+ uint8_t st_ois_clampdis : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_ui_ctrl3_ois_t;
#define LSM6DSOX_X_OFS_USR 0x73U
#define LSM6DSOX_Y_OFS_USR 0x74U
#define LSM6DSOX_Z_OFS_USR 0x75U
#define LSM6DSOX_FIFO_DATA_OUT_TAG 0x78U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tag_parity : 1;
uint8_t tag_cnt : 2;
uint8_t tag_sensor : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t tag_sensor : 5;
+ uint8_t tag_cnt : 2;
+ uint8_t tag_parity : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fifo_data_out_tag_t;
#define LSM6DSOX_FIFO_DATA_OUT_X_L 0x79
@@ -657,11 +1159,19 @@ typedef struct {
#define LSM6DSOX_SPI2_WHO_AM_I 0x0F
#define LSM6DSOX_SPI2_STATUS_REG_OIS 0x1E
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlda : 1;
uint8_t gda : 1;
uint8_t gyro_settling : 1;
uint8_t not_used_01 : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 5;
+ uint8_t gyro_settling : 1;
+ uint8_t gda : 1;
+ uint8_t xlda : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_spi2_status_reg_ois_t;
#define LSM6DSOX_SPI2_OUT_TEMP_L 0x20
@@ -679,87 +1189,161 @@ typedef struct {
#define LSM6DSOX_SPI2_OUTZ_L_A_OIS 0x2C
#define LSM6DSOX_SPI2_OUTZ_H_A_OIS 0x2D
#define LSM6DSOX_SPI2_INT_OIS 0x6F
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_xl_ois : 2;
uint8_t not_used_01 : 3;
uint8_t den_lh_ois : 1;
uint8_t lvl2_ois : 1;
uint8_t int2_drdy_ois : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_drdy_ois : 1;
+ uint8_t lvl2_ois : 1;
+ uint8_t den_lh_ois : 1;
+ uint8_t not_used_01 : 3;
+ uint8_t st_xl_ois : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_spi2_int_ois_t;
#define LSM6DSOX_SPI2_CTRL1_OIS 0x70U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ois_en_spi2 : 1;
uint8_t fs_g_ois : 3; /* fs_125_ois + fs[1:0]_g_ois */
uint8_t mode4_en : 1;
uint8_t sim_ois : 1;
uint8_t lvl1_ois : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t lvl1_ois : 1;
+ uint8_t sim_ois : 1;
+ uint8_t mode4_en : 1;
+ uint8_t fs_g_ois : 3; /* fs_125_ois + fs[1:0]_g_ois */
+ uint8_t ois_en_spi2 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_spi2_ctrl1_ois_t;
#define LSM6DSOX_SPI2_CTRL2_OIS 0x71U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t hp_en_ois : 1;
uint8_t ftype_ois : 2;
uint8_t not_used_01 : 1;
uint8_t hpm_ois : 2;
uint8_t not_used_02 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 2;
+ uint8_t hpm_ois : 2;
+ uint8_t not_used_01 : 1;
+ uint8_t ftype_ois : 2;
+ uint8_t hp_en_ois : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_spi2_ctrl2_ois_t;
#define LSM6DSOX_SPI2_CTRL3_OIS 0x72U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_ois_clampdis : 1;
uint8_t st_ois : 2;
uint8_t filter_xl_conf_ois : 3;
uint8_t fs_xl_ois : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fs_xl_ois : 2;
+ uint8_t filter_xl_conf_ois : 3;
+ uint8_t st_ois : 2;
+ uint8_t st_ois_clampdis : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_spi2_ctrl3_ois_t;
#define LSM6DSOX_PAGE_SEL 0x02U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 4;
uint8_t page_sel : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t page_sel : 4;
+ uint8_t not_used_01 : 4;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_page_sel_t;
#define LSM6DSOX_EMB_FUNC_EN_A 0x04U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t pedo_en : 1;
uint8_t tilt_en : 1;
uint8_t sign_motion_en : 1;
uint8_t not_used_02 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 2;
+ uint8_t sign_motion_en : 1;
+ uint8_t tilt_en : 1;
+ uint8_t pedo_en : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_emb_func_en_a_t;
#define LSM6DSOX_EMB_FUNC_EN_B 0x05U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fsm_en : 1;
uint8_t not_used_01 : 2;
uint8_t fifo_compr_en : 1;
uint8_t mlc_en : 1;
uint8_t not_used_02 : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 3;
+ uint8_t mlc_en : 1;
+ uint8_t fifo_compr_en : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t fsm_en : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_emb_func_en_b_t;
#define LSM6DSOX_PAGE_ADDRESS 0x08U
-typedef struct {
+typedef struct
+{
uint8_t page_addr : 8;
} lsm6dsox_page_address_t;
#define LSM6DSOX_PAGE_VALUE 0x09U
-typedef struct {
+typedef struct
+{
uint8_t page_value : 8;
} lsm6dsox_page_value_t;
#define LSM6DSOX_EMB_FUNC_INT1 0x0AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t int1_step_detector : 1;
uint8_t int1_tilt : 1;
uint8_t int1_sig_mot : 1;
uint8_t not_used_02 : 1;
uint8_t int1_fsm_lc : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_fsm_lc : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t int1_sig_mot : 1;
+ uint8_t int1_tilt : 1;
+ uint8_t int1_step_detector : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_emb_func_int1_t;
#define LSM6DSOX_FSM_INT1_A 0x0BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_fsm1 : 1;
uint8_t int1_fsm2 : 1;
uint8_t int1_fsm3 : 1;
@@ -768,22 +1352,38 @@ typedef struct {
uint8_t int1_fsm6 : 1;
uint8_t int1_fsm7 : 1;
uint8_t int1_fsm8 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_fsm8 : 1;
+ uint8_t int1_fsm7 : 1;
+ uint8_t int1_fsm6 : 1;
+ uint8_t int1_fsm5 : 1;
+ uint8_t int1_fsm4 : 1;
+ uint8_t int1_fsm3 : 1;
+ uint8_t int1_fsm2 : 1;
+ uint8_t int1_fsm1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fsm_int1_a_t;
#define LSM6DSOX_FSM_INT1_B 0x0CU
-typedef struct {
- uint8_t int1_fsm9 : 1;
- uint8_t int1_fsm10 : 1;
- uint8_t int1_fsm11 : 1;
- uint8_t int1_fsm12 : 1;
- uint8_t int1_fsm13 : 1;
- uint8_t int1_fsm14 : 1;
- uint8_t int1_fsm15 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_fsm16 : 1;
+ uint8_t int1_fsm15 : 1;
+ uint8_t int1_fsm14 : 1;
+ uint8_t int1_fsm13 : 1;
+ uint8_t int1_fsm12 : 1;
+ uint8_t int1_fsm11 : 1;
+ uint8_t int1_fsm10 : 1;
+ uint8_t int1_fsm9 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fsm_int1_b_t;
#define LSM6DSOX_MLC_INT1 0x0DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_mlc1 : 1;
uint8_t int1_mlc2 : 1;
uint8_t int1_mlc3 : 1;
@@ -792,20 +1392,42 @@ typedef struct {
uint8_t int1_mlc6 : 1;
uint8_t int1_mlc7 : 1;
uint8_t int1_mlc8 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_mlc8 : 1;
+ uint8_t int1_mlc7 : 1;
+ uint8_t int1_mlc6 : 1;
+ uint8_t int1_mlc5 : 1;
+ uint8_t int1_mlc4 : 1;
+ uint8_t int1_mlc3 : 1;
+ uint8_t int1_mlc2 : 1;
+ uint8_t int1_mlc1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_mlc_int1_t;
#define LSM6DSOX_EMB_FUNC_INT2 0x0EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t int2_step_detector : 1;
uint8_t int2_tilt : 1;
uint8_t int2_sig_mot : 1;
uint8_t not_used_02 : 1;
uint8_t int2_fsm_lc : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_fsm_lc : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t int2_sig_mot : 1;
+ uint8_t int2_tilt : 1;
+ uint8_t int2_step_detector : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_emb_func_int2_t;
#define LSM6DSOX_FSM_INT2_A 0x0FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_fsm1 : 1;
uint8_t int2_fsm2 : 1;
uint8_t int2_fsm3 : 1;
@@ -814,10 +1436,22 @@ typedef struct {
uint8_t int2_fsm6 : 1;
uint8_t int2_fsm7 : 1;
uint8_t int2_fsm8 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_fsm8 : 1;
+ uint8_t int2_fsm7 : 1;
+ uint8_t int2_fsm6 : 1;
+ uint8_t int2_fsm5 : 1;
+ uint8_t int2_fsm4 : 1;
+ uint8_t int2_fsm3 : 1;
+ uint8_t int2_fsm2 : 1;
+ uint8_t int2_fsm1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fsm_int2_a_t;
#define LSM6DSOX_FSM_INT2_B 0x10U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_fsm9 : 1;
uint8_t int2_fsm10 : 1;
uint8_t int2_fsm11 : 1;
@@ -826,10 +1460,22 @@ typedef struct {
uint8_t int2_fsm14 : 1;
uint8_t int2_fsm15 : 1;
uint8_t int2_fsm16 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_fsm16 : 1;
+ uint8_t int2_fsm15 : 1;
+ uint8_t int2_fsm14 : 1;
+ uint8_t int2_fsm13 : 1;
+ uint8_t int2_fsm12 : 1;
+ uint8_t int2_fsm11 : 1;
+ uint8_t int2_fsm10 : 1;
+ uint8_t int2_fsm9 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fsm_int2_b_t;
#define LSM6DSOX_MLC_INT2 0x11U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_mlc1 : 1;
uint8_t int2_mlc2 : 1;
uint8_t int2_mlc3 : 1;
@@ -838,20 +1484,42 @@ typedef struct {
uint8_t int2_mlc6 : 1;
uint8_t int2_mlc7 : 1;
uint8_t int2_mlc8 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_mlc8 : 1;
+ uint8_t int2_mlc7 : 1;
+ uint8_t int2_mlc6 : 1;
+ uint8_t int2_mlc5 : 1;
+ uint8_t int2_mlc4 : 1;
+ uint8_t int2_mlc3 : 1;
+ uint8_t int2_mlc2 : 1;
+ uint8_t int2_mlc1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_mlc_int2_t;
#define LSM6DSOX_EMB_FUNC_STATUS 0x12U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t is_step_det : 1;
uint8_t is_tilt : 1;
uint8_t is_sigmot : 1;
uint8_t not_used_02 : 1;
uint8_t is_fsm_lc : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_fsm_lc : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t is_sigmot : 1;
+ uint8_t is_tilt : 1;
+ uint8_t is_step_det : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_emb_func_status_t;
#define LSM6DSOX_FSM_STATUS_A 0x13U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_fsm1 : 1;
uint8_t is_fsm2 : 1;
uint8_t is_fsm3 : 1;
@@ -860,10 +1528,22 @@ typedef struct {
uint8_t is_fsm6 : 1;
uint8_t is_fsm7 : 1;
uint8_t is_fsm8 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_fsm8 : 1;
+ uint8_t is_fsm7 : 1;
+ uint8_t is_fsm6 : 1;
+ uint8_t is_fsm5 : 1;
+ uint8_t is_fsm4 : 1;
+ uint8_t is_fsm3 : 1;
+ uint8_t is_fsm2 : 1;
+ uint8_t is_fsm1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fsm_status_a_t;
#define LSM6DSOX_FSM_STATUS_B 0x14U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_fsm9 : 1;
uint8_t is_fsm10 : 1;
uint8_t is_fsm11 : 1;
@@ -872,10 +1552,22 @@ typedef struct {
uint8_t is_fsm14 : 1;
uint8_t is_fsm15 : 1;
uint8_t is_fsm16 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_fsm16 : 1;
+ uint8_t is_fsm15 : 1;
+ uint8_t is_fsm14 : 1;
+ uint8_t is_fsm13 : 1;
+ uint8_t is_fsm12 : 1;
+ uint8_t is_fsm11 : 1;
+ uint8_t is_fsm10 : 1;
+ uint8_t is_fsm9 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fsm_status_b_t;
#define LSM6DSOX_MLC_STATUS 0x15U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_mlc1 : 1;
uint8_t is_mlc2 : 1;
uint8_t is_mlc3 : 1;
@@ -884,24 +1576,50 @@ typedef struct {
uint8_t is_mlc6 : 1;
uint8_t is_mlc7 : 1;
uint8_t is_mlc8 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_mlc8 : 1;
+ uint8_t is_mlc7 : 1;
+ uint8_t is_mlc6 : 1;
+ uint8_t is_mlc5 : 1;
+ uint8_t is_mlc4 : 1;
+ uint8_t is_mlc3 : 1;
+ uint8_t is_mlc2 : 1;
+ uint8_t is_mlc1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_mlc_status_t;
#define LSM6DSOX_PAGE_RW 0x17U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 5;
uint8_t page_rw : 2; /* page_write + page_read */
uint8_t emb_func_lir : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t emb_func_lir : 1;
+ uint8_t page_rw : 2; /* page_write + page_read */
+ uint8_t not_used_01 : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_page_rw_t;
#define LSM6DSOX_EMB_FUNC_FIFO_CFG 0x44U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_00 : 6;
uint8_t pedo_fifo_en : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t pedo_fifo_en : 1;
+ uint8_t not_used_00 : 6;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_emb_func_fifo_cfg_t;
#define LSM6DSOX_FSM_ENABLE_A 0x46U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fsm1_en : 1;
uint8_t fsm2_en : 1;
uint8_t fsm3_en : 1;
@@ -910,10 +1628,22 @@ typedef struct {
uint8_t fsm6_en : 1;
uint8_t fsm7_en : 1;
uint8_t fsm8_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fsm8_en : 1;
+ uint8_t fsm7_en : 1;
+ uint8_t fsm6_en : 1;
+ uint8_t fsm5_en : 1;
+ uint8_t fsm4_en : 1;
+ uint8_t fsm3_en : 1;
+ uint8_t fsm2_en : 1;
+ uint8_t fsm1_en : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fsm_enable_a_t;
#define LSM6DSOX_FSM_ENABLE_B 0x47U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fsm9_en : 1;
uint8_t fsm10_en : 1;
uint8_t fsm11_en : 1;
@@ -922,18 +1652,38 @@ typedef struct {
uint8_t fsm14_en : 1;
uint8_t fsm15_en : 1;
uint8_t fsm16_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fsm16_en : 1;
+ uint8_t fsm15_en : 1;
+ uint8_t fsm14_en : 1;
+ uint8_t fsm13_en : 1;
+ uint8_t fsm12_en : 1;
+ uint8_t fsm11_en : 1;
+ uint8_t fsm10_en : 1;
+ uint8_t fsm9_en : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fsm_enable_b_t;
#define LSM6DSOX_FSM_LONG_COUNTER_L 0x48U
#define LSM6DSOX_FSM_LONG_COUNTER_H 0x49U
#define LSM6DSOX_FSM_LONG_COUNTER_CLEAR 0x4AU
-typedef struct {
- uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+uint8_t fsm_lc_clr :
+ 2; /* fsm_lc_cleared + fsm_lc_clear */
+ uint8_t not_used_01 : 6;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used_01 : 6;
+uint8_t fsm_lc_clr :
+ 2; /* fsm_lc_cleared + fsm_lc_clear */
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fsm_long_counter_clear_t;
#define LSM6DSOX_FSM_OUTS1 0x4CU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -942,10 +1692,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fsm_outs1_t;
#define LSM6DSOX_FSM_OUTS2 0x4DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -954,10 +1716,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fsm_outs2_t;
#define LSM6DSOX_FSM_OUTS3 0x4EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -966,10 +1740,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fsm_outs3_t;
#define LSM6DSOX_FSM_OUTS4 0x4FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -978,10 +1764,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fsm_outs4_t;
#define LSM6DSOX_FSM_OUTS5 0x50U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -990,10 +1788,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fsm_outs5_t;
#define LSM6DSOX_FSM_OUTS6 0x51U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -1002,10 +1812,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fsm_outs6_t;
#define LSM6DSOX_FSM_OUTS7 0x52U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -1014,10 +1836,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fsm_outs7_t;
#define LSM6DSOX_FSM_OUTS8 0x53U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -1026,10 +1860,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fsm_outs8_t;
#define LSM6DSOX_FSM_OUTS9 0x54U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -1038,10 +1884,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fsm_outs9_t;
#define LSM6DSOX_FSM_OUTS10 0x55U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -1050,10 +1908,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fsm_outs10_t;
#define LSM6DSOX_FSM_OUTS11 0x56U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -1062,10 +1932,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fsm_outs11_t;
#define LSM6DSOX_FSM_OUTS12 0x57U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -1074,10 +1956,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fsm_outs12_t;
#define LSM6DSOX_FSM_OUTS13 0x58U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -1086,10 +1980,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fsm_outs13_t;
#define LSM6DSOX_FSM_OUTS14 0x59U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -1098,10 +2004,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fsm_outs14_t;
#define LSM6DSOX_FSM_OUTS15 0x5AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -1110,10 +2028,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fsm_outs15_t;
#define LSM6DSOX_FSM_OUTS16 0x5BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -1122,26 +2052,52 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_fsm_outs16_t;
#define LSM6DSOX_EMB_FUNC_ODR_CFG_B 0x5FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t fsm_odr : 2;
uint8_t not_used_02 : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 3;
+ uint8_t fsm_odr : 2;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_emb_func_odr_cfg_b_t;
#define LSM6DSOX_EMB_FUNC_ODR_CFG_C 0x60U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 4;
uint8_t mlc_odr : 2;
uint8_t not_used_02 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 2;
+ uint8_t mlc_odr : 2;
+ uint8_t not_used_01 : 4;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_emb_func_odr_cfg_c_t;
#define LSM6DSOX_STEP_COUNTER_L 0x62U
#define LSM6DSOX_STEP_COUNTER_H 0x63U
#define LSM6DSOX_EMB_FUNC_SRC 0x64U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t stepcounter_bit_set : 1;
uint8_t step_overflow : 1;
@@ -1149,24 +2105,51 @@ typedef struct {
uint8_t step_detected : 1;
uint8_t not_used_02 : 1;
uint8_t pedo_rst_step : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t pedo_rst_step : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t step_detected : 1;
+ uint8_t step_count_delta_ia : 1;
+ uint8_t step_overflow : 1;
+ uint8_t stepcounter_bit_set : 1;
+ uint8_t not_used_01 : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_emb_func_src_t;
#define LSM6DSOX_EMB_FUNC_INIT_A 0x66U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t step_det_init : 1;
uint8_t tilt_init : 1;
uint8_t sig_mot_init : 1;
uint8_t not_used_02 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 2;
+ uint8_t sig_mot_init : 1;
+ uint8_t tilt_init : 1;
+ uint8_t step_det_init : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_emb_func_init_a_t;
#define LSM6DSOX_EMB_FUNC_INIT_B 0x67U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fsm_init : 1;
uint8_t not_used_01 : 2;
uint8_t fifo_compr_init : 1;
uint8_t mlc_init : 1;
uint8_t not_used_02 : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 3;
+ uint8_t mlc_init : 1;
+ uint8_t fifo_compr_init : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t fsm_init : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_emb_func_init_b_t;
#define LSM6DSOX_MLC0_SRC 0x70U
@@ -1198,17 +2181,31 @@ typedef struct {
#define LSM6DSOX_MAG_SI_ZZ_L 0xD0U
#define LSM6DSOX_MAG_SI_ZZ_H 0xD1U
#define LSM6DSOX_MAG_CFG_A 0xD4U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t mag_z_axis : 3;
uint8_t not_used_01 : 1;
uint8_t mag_y_axis : 3;
uint8_t not_used_02 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 1;
+ uint8_t mag_y_axis : 3;
+ uint8_t not_used_01 : 1;
+ uint8_t mag_z_axis : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_mag_cfg_a_t;
#define LSM6DSOX_MAG_CFG_B 0xD5U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t mag_x_axis : 3;
uint8_t not_used_01 : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 5;
+ uint8_t mag_x_axis : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_mag_cfg_b_t;
#define LSM6DSOX_FSM_LC_TIMEOUT_L 0x17AU
@@ -1217,12 +2214,21 @@ typedef struct {
#define LSM6DSOX_FSM_START_ADD_L 0x17EU
#define LSM6DSOX_FSM_START_ADD_H 0x17FU
#define LSM6DSOX_PEDO_CMD_REG 0x183U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ad_det_en : 1;
uint8_t not_used_01 : 1;
uint8_t fp_rejection_en : 1;
uint8_t carry_count_en : 1;
uint8_t not_used_02 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 4;
+ uint8_t carry_count_en : 1;
+ uint8_t fp_rejection_en : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t ad_det_en : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_pedo_cmd_reg_t;
#define LSM6DSOX_PEDO_DEB_STEPS_CONF 0x184U
@@ -1233,223 +2239,441 @@ typedef struct {
#define LSM6DSOX_MLC_MAG_SENSITIVITY_H 0x1E9U
#define LSM6DSOX_SENSOR_HUB_1 0x02U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_sensor_hub_1_t;
#define LSM6DSOX_SENSOR_HUB_2 0x03U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_sensor_hub_2_t;
#define LSM6DSOX_SENSOR_HUB_3 0x04U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_sensor_hub_3_t;
#define LSM6DSOX_SENSOR_HUB_4 0x05U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_sensor_hub_4_t;
#define LSM6DSOX_SENSOR_HUB_5 0x06U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_sensor_hub_5_t;
#define LSM6DSOX_SENSOR_HUB_6 0x07U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_sensor_hub_6_t;
#define LSM6DSOX_SENSOR_HUB_7 0x08U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_sensor_hub_7_t;
#define LSM6DSOX_SENSOR_HUB_8 0x09U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_sensor_hub_8_t;
#define LSM6DSOX_SENSOR_HUB_9 0x0AU
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_sensor_hub_9_t;
#define LSM6DSOX_SENSOR_HUB_10 0x0BU
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_sensor_hub_10_t;
#define LSM6DSOX_SENSOR_HUB_11 0x0CU
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_sensor_hub_11_t;
#define LSM6DSOX_SENSOR_HUB_12 0x0DU
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_sensor_hub_12_t;
#define LSM6DSOX_SENSOR_HUB_13 0x0EU
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_sensor_hub_13_t;
#define LSM6DSOX_SENSOR_HUB_14 0x0FU
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_sensor_hub_14_t;
#define LSM6DSOX_SENSOR_HUB_15 0x10U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_sensor_hub_15_t;
#define LSM6DSOX_SENSOR_HUB_16 0x11U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_sensor_hub_16_t;
#define LSM6DSOX_SENSOR_HUB_17 0x12U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_sensor_hub_17_t;
#define LSM6DSOX_SENSOR_HUB_18 0x13U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_sensor_hub_18_t;
#define LSM6DSOX_MASTER_CONFIG 0x14U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t aux_sens_on : 2;
uint8_t master_on : 1;
uint8_t shub_pu_en : 1;
@@ -1457,88 +2681,157 @@ typedef struct {
uint8_t start_config : 1;
uint8_t write_once : 1;
uint8_t rst_master_regs : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t rst_master_regs : 1;
+ uint8_t write_once : 1;
+ uint8_t start_config : 1;
+ uint8_t pass_through_mode : 1;
+ uint8_t shub_pu_en : 1;
+ uint8_t master_on : 1;
+ uint8_t aux_sens_on : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_master_config_t;
#define LSM6DSOX_SLV0_ADD 0x15U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t rw_0 : 1;
uint8_t slave0 : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave0 : 7;
+ uint8_t rw_0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_slv0_add_t;
#define LSM6DSOX_SLV0_SUBADD 0x16U
-typedef struct {
+typedef struct
+{
uint8_t slave0_reg : 8;
} lsm6dsox_slv0_subadd_t;
#define LSM6DSOX_SLV0_CONFIG 0x17U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave0_numop : 3;
uint8_t batch_ext_sens_0_en : 1;
uint8_t not_used_01 : 2;
uint8_t shub_odr : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t shub_odr : 2;
+ uint8_t not_used_01 : 2;
+ uint8_t batch_ext_sens_0_en : 1;
+ uint8_t slave0_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_slv0_config_t;
#define LSM6DSOX_SLV1_ADD 0x18U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_1 : 1;
uint8_t slave1_add : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave1_add : 7;
+ uint8_t r_1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_slv1_add_t;
#define LSM6DSOX_SLV1_SUBADD 0x19U
-typedef struct {
+typedef struct
+{
uint8_t slave1_reg : 8;
} lsm6dsox_slv1_subadd_t;
#define LSM6DSOX_SLV1_CONFIG 0x1AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave1_numop : 3;
uint8_t batch_ext_sens_1_en : 1;
uint8_t not_used_01 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 4;
+ uint8_t batch_ext_sens_1_en : 1;
+ uint8_t slave1_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_slv1_config_t;
#define LSM6DSOX_SLV2_ADD 0x1BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_2 : 1;
uint8_t slave2_add : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave2_add : 7;
+ uint8_t r_2 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_slv2_add_t;
#define LSM6DSOX_SLV2_SUBADD 0x1CU
-typedef struct {
+typedef struct
+{
uint8_t slave2_reg : 8;
} lsm6dsox_slv2_subadd_t;
#define LSM6DSOX_SLV2_CONFIG 0x1DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave2_numop : 3;
uint8_t batch_ext_sens_2_en : 1;
uint8_t not_used_01 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 4;
+ uint8_t batch_ext_sens_2_en : 1;
+ uint8_t slave2_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_slv2_config_t;
#define LSM6DSOX_SLV3_ADD 0x1EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_3 : 1;
uint8_t slave3_add : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave3_add : 7;
+ uint8_t r_3 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_slv3_add_t;
#define LSM6DSOX_SLV3_SUBADD 0x1FU
-typedef struct {
+typedef struct
+{
uint8_t slave3_reg : 8;
} lsm6dsox_slv3_subadd_t;
#define LSM6DSOX_SLV3_CONFIG 0x20U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave3_numop : 3;
uint8_t batch_ext_sens_3_en : 1;
uint8_t not_used_01 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 4;
+ uint8_t batch_ext_sens_3_en : 1;
+ uint8_t slave3_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_slv3_config_t;
#define LSM6DSOX_DATAWRITE_SLV0 0x21U
-typedef struct {
+typedef struct
+{
uint8_t slave0_dataw : 8;
} lsm6dsox_datawrite_slv0_t;
#define LSM6DSOX_STATUS_MASTER 0x22U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sens_hub_endop : 1;
uint8_t not_used_01 : 2;
uint8_t slave0_nack : 1;
@@ -1546,15 +2839,24 @@ typedef struct {
uint8_t slave2_nack : 1;
uint8_t slave3_nack : 1;
uint8_t wr_once_done : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t wr_once_done : 1;
+ uint8_t slave3_nack : 1;
+ uint8_t slave2_nack : 1;
+ uint8_t slave1_nack : 1;
+ uint8_t slave0_nack : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t sens_hub_endop : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsox_status_master_t;
#define LSM6DSOX_START_FSM_ADD 0x0400U
/**
* @defgroup LSM6DSOX_Register_Union
- * @brief This union group all the registers that has a bitfield
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -1562,7 +2864,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
lsm6dsox_func_cfg_access_t func_cfg_access;
lsm6dsox_pin_ctrl_t pin_ctrl;
lsm6dsox_s4s_tph_l_t s4s_tph_l;
@@ -1703,33 +3006,42 @@ typedef union{
*
*/
-int32_t lsm6dsox_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lsm6dsox_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t lsm6dsox_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lsm6dsox_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-extern float_t lsm6dsox_from_fs2_to_mg(int16_t lsb);
-extern float_t lsm6dsox_from_fs4_to_mg(int16_t lsb);
-extern float_t lsm6dsox_from_fs8_to_mg(int16_t lsb);
-extern float_t lsm6dsox_from_fs16_to_mg(int16_t lsb);
-extern float_t lsm6dsox_from_fs125_to_mdps(int16_t lsb);
-extern float_t lsm6dsox_from_fs500_to_mdps(int16_t lsb);
-extern float_t lsm6dsox_from_fs250_to_mdps(int16_t lsb);
-extern float_t lsm6dsox_from_fs1000_to_mdps(int16_t lsb);
-extern float_t lsm6dsox_from_fs2000_to_mdps(int16_t lsb);
-extern float_t lsm6dsox_from_lsb_to_celsius(int16_t lsb);
-extern float_t lsm6dsox_from_lsb_to_nsec(int16_t lsb);
-
-typedef enum {
+float_t lsm6dsox_from_fs2_to_mg(int16_t lsb);
+float_t lsm6dsox_from_fs4_to_mg(int16_t lsb);
+float_t lsm6dsox_from_fs8_to_mg(int16_t lsb);
+float_t lsm6dsox_from_fs16_to_mg(int16_t lsb);
+
+float_t lsm6dsox_from_fs125_to_mdps(int16_t lsb);
+float_t lsm6dsox_from_fs500_to_mdps(int16_t lsb);
+float_t lsm6dsox_from_fs250_to_mdps(int16_t lsb);
+float_t lsm6dsox_from_fs1000_to_mdps(int16_t lsb);
+float_t lsm6dsox_from_fs2000_to_mdps(int16_t lsb);
+
+float_t lsm6dsox_from_lsb_to_celsius(int16_t lsb);
+
+float_t lsm6dsox_from_lsb_to_nsec(int16_t lsb);
+
+typedef enum
+{
LSM6DSOX_2g = 0,
LSM6DSOX_16g = 1, /* if XL_FS_MODE = ‘1’ -> LSM6DSOX_2g */
LSM6DSOX_4g = 2,
LSM6DSOX_8g = 3,
} lsm6dsox_fs_xl_t;
-int32_t lsm6dsox_xl_full_scale_set(stmdev_ctx_t *ctx, lsm6dsox_fs_xl_t val);
-int32_t lsm6dsox_xl_full_scale_get(stmdev_ctx_t *ctx, lsm6dsox_fs_xl_t *val);
+int32_t lsm6dsox_xl_full_scale_set(stmdev_ctx_t *ctx,
+ lsm6dsox_fs_xl_t val);
+int32_t lsm6dsox_xl_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6dsox_fs_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_XL_ODR_OFF = 0,
LSM6DSOX_XL_ODR_12Hz5 = 1,
LSM6DSOX_XL_ODR_26Hz = 2,
@@ -1743,20 +3055,26 @@ typedef enum {
LSM6DSOX_XL_ODR_6667Hz = 10,
LSM6DSOX_XL_ODR_1Hz6 = 11, /* (low power only) */
} lsm6dsox_odr_xl_t;
-int32_t lsm6dsox_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6dsox_odr_xl_t val);
-int32_t lsm6dsox_xl_data_rate_get(stmdev_ctx_t *ctx, lsm6dsox_odr_xl_t *val);
+int32_t lsm6dsox_xl_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dsox_odr_xl_t val);
+int32_t lsm6dsox_xl_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dsox_odr_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_250dps = 0,
LSM6DSOX_125dps = 1,
LSM6DSOX_500dps = 2,
LSM6DSOX_1000dps = 4,
LSM6DSOX_2000dps = 6,
} lsm6dsox_fs_g_t;
-int32_t lsm6dsox_gy_full_scale_set(stmdev_ctx_t *ctx, lsm6dsox_fs_g_t val);
-int32_t lsm6dsox_gy_full_scale_get(stmdev_ctx_t *ctx, lsm6dsox_fs_g_t *val);
+int32_t lsm6dsox_gy_full_scale_set(stmdev_ctx_t *ctx,
+ lsm6dsox_fs_g_t val);
+int32_t lsm6dsox_gy_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6dsox_fs_g_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_GY_ODR_OFF = 0,
LSM6DSOX_GY_ODR_12Hz5 = 1,
LSM6DSOX_GY_ODR_26Hz = 2,
@@ -1769,13 +3087,18 @@ typedef enum {
LSM6DSOX_GY_ODR_3333Hz = 9,
LSM6DSOX_GY_ODR_6667Hz = 10,
} lsm6dsox_odr_g_t;
-int32_t lsm6dsox_gy_data_rate_set(stmdev_ctx_t *ctx, lsm6dsox_odr_g_t val);
-int32_t lsm6dsox_gy_data_rate_get(stmdev_ctx_t *ctx, lsm6dsox_odr_g_t *val);
-
-int32_t lsm6dsox_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsox_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
-
-typedef enum {
+int32_t lsm6dsox_gy_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dsox_odr_g_t val);
+int32_t lsm6dsox_gy_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dsox_odr_g_t *val);
+
+int32_t lsm6dsox_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsox_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
+
+typedef enum
+{
LSM6DSOX_LSb_1mg = 0,
LSM6DSOX_LSb_16mg = 1,
} lsm6dsox_usr_off_w_t;
@@ -1784,7 +3107,8 @@ int32_t lsm6dsox_xl_offset_weight_set(stmdev_ctx_t *ctx,
int32_t lsm6dsox_xl_offset_weight_get(stmdev_ctx_t *ctx,
lsm6dsox_usr_off_w_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_HIGH_PERFORMANCE_MD = 0,
LSM6DSOX_LOW_NORMAL_POWER_MD = 1,
LSM6DSOX_ULTRA_LOW_POWER_MD = 2,
@@ -1794,7 +3118,8 @@ int32_t lsm6dsox_xl_power_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dsox_xl_power_mode_get(stmdev_ctx_t *ctx,
lsm6dsox_xl_hm_mode_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_GY_HIGH_PERFORMANCE = 0,
LSM6DSOX_GY_NORMAL = 1,
} lsm6dsox_g_hm_mode_t;
@@ -1806,20 +3131,29 @@ int32_t lsm6dsox_gy_power_mode_get(stmdev_ctx_t *ctx,
int32_t lsm6dsox_status_reg_get(stmdev_ctx_t *ctx,
lsm6dsox_status_reg_t *val);
-int32_t lsm6dsox_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsox_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsox_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsox_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsox_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsox_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsox_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsox_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsox_xl_usr_offset_x_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lsm6dsox_xl_usr_offset_x_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
-int32_t lsm6dsox_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsox_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsox_xl_usr_offset_y_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lsm6dsox_xl_usr_offset_y_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
-int32_t lsm6dsox_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsox_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsox_xl_usr_offset_z_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lsm6dsox_xl_usr_offset_z_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
int32_t lsm6dsox_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsox_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1829,9 +3163,10 @@ int32_t lsm6dsox_timestamp_rst(stmdev_ctx_t *ctx);
int32_t lsm6dsox_timestamp_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsox_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dsox_timestamp_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsox_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_NO_ROUND = 0,
LSM6DSOX_ROUND_XL = 1,
LSM6DSOX_ROUND_GY = 2,
@@ -1842,7 +3177,8 @@ int32_t lsm6dsox_rounding_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dsox_rounding_mode_get(stmdev_ctx_t *ctx,
lsm6dsox_rounding_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_STAT_RND_DISABLE = 0,
LSM6DSOX_STAT_RND_ENABLE = 1,
} lsm6dsox_rounding_status_t;
@@ -1851,25 +3187,33 @@ int32_t lsm6dsox_rounding_on_status_set(stmdev_ctx_t *ctx,
int32_t lsm6dsox_rounding_on_status_get(stmdev_ctx_t *ctx,
lsm6dsox_rounding_status_t *val);
-int32_t lsm6dsox_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsox_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val);
-int32_t lsm6dsox_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsox_angular_rate_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
-int32_t lsm6dsox_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsox_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
int32_t lsm6dsox_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsox_ois_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsox_ois_angular_rate_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
-int32_t lsm6dsox_ois_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsox_ois_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
-int32_t lsm6dsox_aux_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsox_aux_temperature_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
-int32_t lsm6dsox_aux_ois_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsox_aux_ois_angular_rate_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
-int32_t lsm6dsox_aux_ois_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsox_aux_ois_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
-int32_t lsm6dsox_number_of_steps_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsox_number_of_steps_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
int32_t lsm6dsox_steps_reset(stmdev_ctx_t *ctx);
@@ -1878,13 +3222,16 @@ int32_t lsm6dsox_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t lsm6dsox_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsox_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_USER_BANK = 0,
LSM6DSOX_SENSOR_HUB_BANK = 1,
LSM6DSOX_EMBEDDED_FUNC_BANK = 2,
} lsm6dsox_reg_access_t;
-int32_t lsm6dsox_mem_bank_set(stmdev_ctx_t *ctx, lsm6dsox_reg_access_t val);
-int32_t lsm6dsox_mem_bank_get(stmdev_ctx_t *ctx, lsm6dsox_reg_access_t *val);
+int32_t lsm6dsox_mem_bank_set(stmdev_ctx_t *ctx,
+ lsm6dsox_reg_access_t val);
+int32_t lsm6dsox_mem_bank_get(stmdev_ctx_t *ctx,
+ lsm6dsox_reg_access_t *val);
int32_t lsm6dsox_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address,
uint8_t *val);
@@ -1896,7 +3243,8 @@ int32_t lsm6dsox_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address,
int32_t lsm6dsox_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address,
uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_DRDY_LATCHED = 0,
LSM6DSOX_DRDY_PULSED = 1,
} lsm6dsox_dataready_pulsed_t;
@@ -1916,21 +3264,27 @@ int32_t lsm6dsox_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsox_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsox_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_XL_ST_DISABLE = 0,
LSM6DSOX_XL_ST_POSITIVE = 1,
LSM6DSOX_XL_ST_NEGATIVE = 2,
} lsm6dsox_st_xl_t;
-int32_t lsm6dsox_xl_self_test_set(stmdev_ctx_t *ctx, lsm6dsox_st_xl_t val);
-int32_t lsm6dsox_xl_self_test_get(stmdev_ctx_t *ctx, lsm6dsox_st_xl_t *val);
+int32_t lsm6dsox_xl_self_test_set(stmdev_ctx_t *ctx,
+ lsm6dsox_st_xl_t val);
+int32_t lsm6dsox_xl_self_test_get(stmdev_ctx_t *ctx,
+ lsm6dsox_st_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_GY_ST_DISABLE = 0,
LSM6DSOX_GY_ST_POSITIVE = 1,
LSM6DSOX_GY_ST_NEGATIVE = 3,
} lsm6dsox_st_g_t;
-int32_t lsm6dsox_gy_self_test_set(stmdev_ctx_t *ctx, lsm6dsox_st_g_t val);
-int32_t lsm6dsox_gy_self_test_get(stmdev_ctx_t *ctx, lsm6dsox_st_g_t *val);
+int32_t lsm6dsox_gy_self_test_set(stmdev_ctx_t *ctx,
+ lsm6dsox_st_g_t val);
+int32_t lsm6dsox_gy_self_test_get(stmdev_ctx_t *ctx,
+ lsm6dsox_st_g_t *val);
int32_t lsm6dsox_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsox_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1943,7 +3297,8 @@ int32_t lsm6dsox_filter_settling_mask_set(stmdev_ctx_t *ctx,
int32_t lsm6dsox_filter_settling_mask_get(stmdev_ctx_t *ctx,
uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_ULTRA_LIGHT = 0,
LSM6DSOX_VERY_LIGHT = 1,
LSM6DSOX_LIGHT = 2,
@@ -1961,7 +3316,8 @@ int32_t lsm6dsox_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
int32_t lsm6dsox_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsox_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_HP_PATH_DISABLE_ON_OUT = 0x00,
LSM6DSOX_SLOPE_ODR_DIV_4 = 0x10,
LSM6DSOX_HP_ODR_DIV_10 = 0x11,
@@ -1992,9 +3348,11 @@ int32_t lsm6dsox_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
lsm6dsox_hp_slope_xl_en_t *val);
int32_t lsm6dsox_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsox_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsox_xl_fast_settling_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_USE_SLOPE = 0,
LSM6DSOX_USE_HPF = 1,
} lsm6dsox_slope_fds_t;
@@ -2003,7 +3361,8 @@ int32_t lsm6dsox_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
int32_t lsm6dsox_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
lsm6dsox_slope_fds_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_HP_FILTER_NONE = 0x00,
LSM6DSOX_HP_FILTER_16mHz = 0x80,
LSM6DSOX_HP_FILTER_65mHz = 0x81,
@@ -2015,7 +3374,8 @@ int32_t lsm6dsox_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
int32_t lsm6dsox_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
lsm6dsox_hpm_g_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_OIS_CTRL_AUX_DATA_UI = 0x00,
LSM6DSOX_OIS_CTRL_AUX_DATA_UI_AUX = 0x01,
LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI = 0x02,
@@ -2026,7 +3386,8 @@ int32_t lsm6dsox_ois_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dsox_ois_mode_get(stmdev_ctx_t *ctx,
lsm6dsox_spi2_read_en_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_AUX_PULL_UP_DISC = 0,
LSM6DSOX_AUX_PULL_UP_CONNECT = 1,
} lsm6dsox_ois_pu_dis_t;
@@ -2035,14 +3396,18 @@ int32_t lsm6dsox_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dsox_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx,
lsm6dsox_ois_pu_dis_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_AUX_ON = 1,
LSM6DSOX_AUX_ON_BY_AUX_INTERFACE = 0,
} lsm6dsox_ois_on_t;
-int32_t lsm6dsox_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx, lsm6dsox_ois_on_t val);
-int32_t lsm6dsox_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx, lsm6dsox_ois_on_t *val);
+int32_t lsm6dsox_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx,
+ lsm6dsox_ois_on_t val);
+int32_t lsm6dsox_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx,
+ lsm6dsox_ois_on_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_USE_SAME_XL_FS = 0,
LSM6DSOX_USE_DIFFERENT_XL_FS = 1,
} lsm6dsox_xl_fs_mode_t;
@@ -2054,13 +3419,17 @@ int32_t lsm6dsox_aux_xl_fs_mode_get(stmdev_ctx_t *ctx,
int32_t lsm6dsox_aux_status_reg_get(stmdev_ctx_t *ctx,
lsm6dsox_spi2_status_reg_ois_t *val);
-int32_t lsm6dsox_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsox_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsox_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsox_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsox_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsox_aux_gy_flag_settling_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_AUX_DEN_ACTIVE_LOW = 0,
LSM6DSOX_AUX_DEN_ACTIVE_HIGH = 1,
} lsm6dsox_den_lh_ois_t;
@@ -2069,7 +3438,8 @@ int32_t lsm6dsox_aux_den_polarity_set(stmdev_ctx_t *ctx,
int32_t lsm6dsox_aux_den_polarity_get(stmdev_ctx_t *ctx,
lsm6dsox_den_lh_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_AUX_DEN_DISABLE = 0,
LSM6DSOX_AUX_DEN_LEVEL_LATCH = 3,
LSM6DSOX_AUX_DEN_LEVEL_TRIG = 2,
@@ -2080,9 +3450,11 @@ int32_t lsm6dsox_aux_den_mode_get(stmdev_ctx_t *ctx,
lsm6dsox_lvl2_ois_t *val);
int32_t lsm6dsox_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsox_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsox_aux_drdy_on_int2_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_AUX_DISABLE = 0,
LSM6DSOX_MODE_3_GY = 1,
LSM6DSOX_MODE_4_GY_XL = 3,
@@ -2092,7 +3464,8 @@ int32_t lsm6dsox_aux_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dsox_aux_mode_get(stmdev_ctx_t *ctx,
lsm6dsox_ois_en_spi2_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_250dps_AUX = 0,
LSM6DSOX_125dps_AUX = 1,
LSM6DSOX_500dps_AUX = 2,
@@ -2104,7 +3477,8 @@ int32_t lsm6dsox_aux_gy_full_scale_set(stmdev_ctx_t *ctx,
int32_t lsm6dsox_aux_gy_full_scale_get(stmdev_ctx_t *ctx,
lsm6dsox_fs_g_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_AUX_SPI_4_WIRE = 0,
LSM6DSOX_AUX_SPI_3_WIRE = 1,
} lsm6dsox_sim_ois_t;
@@ -2113,7 +3487,8 @@ int32_t lsm6dsox_aux_spi_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dsox_aux_spi_mode_get(stmdev_ctx_t *ctx,
lsm6dsox_sim_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_351Hz39 = 0,
LSM6DSOX_236Hz63 = 1,
LSM6DSOX_172Hz70 = 2,
@@ -2124,7 +3499,8 @@ int32_t lsm6dsox_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
int32_t lsm6dsox_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
lsm6dsox_ftype_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_AUX_HP_DISABLE = 0x00,
LSM6DSOX_AUX_HP_Hz016 = 0x10,
LSM6DSOX_AUX_HP_Hz065 = 0x11,
@@ -2136,7 +3512,8 @@ int32_t lsm6dsox_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx,
int32_t lsm6dsox_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx,
lsm6dsox_hpm_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_ENABLE_CLAMP = 0,
LSM6DSOX_DISABLE_CLAMP = 1,
} lsm6dsox_st_ois_clampdis_t;
@@ -2145,7 +3522,8 @@ int32_t lsm6dsox_aux_gy_clamp_set(stmdev_ctx_t *ctx,
int32_t lsm6dsox_aux_gy_clamp_get(stmdev_ctx_t *ctx,
lsm6dsox_st_ois_clampdis_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_289Hz = 0,
LSM6DSOX_258Hz = 1,
LSM6DSOX_120Hz = 2,
@@ -2160,7 +3538,8 @@ int32_t lsm6dsox_aux_xl_bandwidth_set(stmdev_ctx_t *ctx,
int32_t lsm6dsox_aux_xl_bandwidth_get(stmdev_ctx_t *ctx,
lsm6dsox_filter_xl_conf_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_AUX_2g = 0,
LSM6DSOX_AUX_16g = 1,
LSM6DSOX_AUX_4g = 2,
@@ -2171,7 +3550,8 @@ int32_t lsm6dsox_aux_xl_full_scale_set(stmdev_ctx_t *ctx,
int32_t lsm6dsox_aux_xl_full_scale_get(stmdev_ctx_t *ctx,
lsm6dsox_fs_xl_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_PULL_UP_DISC = 0,
LSM6DSOX_PULL_UP_CONNECT = 1,
} lsm6dsox_sdo_pu_en_t;
@@ -2180,14 +3560,16 @@ int32_t lsm6dsox_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dsox_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
lsm6dsox_sdo_pu_en_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_SPI_4_WIRE = 0,
LSM6DSOX_SPI_3_WIRE = 1,
} lsm6dsox_sim_t;
int32_t lsm6dsox_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsox_sim_t val);
int32_t lsm6dsox_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsox_sim_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_I2C_ENABLE = 0,
LSM6DSOX_I2C_DISABLE = 1,
} lsm6dsox_i2c_disable_t;
@@ -2196,7 +3578,8 @@ int32_t lsm6dsox_i2c_interface_set(stmdev_ctx_t *ctx,
int32_t lsm6dsox_i2c_interface_get(stmdev_ctx_t *ctx,
lsm6dsox_i2c_disable_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_I3C_DISABLE = 0x80,
LSM6DSOX_I3C_ENABLE_T_50us = 0x00,
LSM6DSOX_I3C_ENABLE_T_2us = 0x01,
@@ -2208,16 +3591,20 @@ int32_t lsm6dsox_i3c_disable_set(stmdev_ctx_t *ctx,
int32_t lsm6dsox_i3c_disable_get(stmdev_ctx_t *ctx,
lsm6dsox_i3c_disable_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_PUSH_PULL = 0x00,
LSM6DSOX_OPEN_DRAIN = 0x01,
LSM6DSOX_INT1_NOPULL_DOWN_INT2_PUSH_PULL = 0x02,
LSM6DSOX_INT1_NOPULL_DOWN_INT2_OPEN_DRAIN = 0x03,
} lsm6dsox_pp_od_t;
-int32_t lsm6dsox_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsox_pp_od_t val);
-int32_t lsm6dsox_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsox_pp_od_t *val);
+int32_t lsm6dsox_pin_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsox_pp_od_t val);
+int32_t lsm6dsox_pin_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsox_pp_od_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_ACTIVE_HIGH = 0,
LSM6DSOX_ACTIVE_LOW = 1,
} lsm6dsox_h_lactive_t;
@@ -2229,16 +3616,20 @@ int32_t lsm6dsox_pin_polarity_get(stmdev_ctx_t *ctx,
int32_t lsm6dsox_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsox_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_ALL_INT_PULSED = 0,
LSM6DSOX_BASE_LATCHED_EMB_PULSED = 1,
LSM6DSOX_BASE_PULSED_EMB_LATCHED = 2,
LSM6DSOX_ALL_INT_LATCHED = 3,
} lsm6dsox_lir_t;
-int32_t lsm6dsox_int_notification_set(stmdev_ctx_t *ctx, lsm6dsox_lir_t val);
-int32_t lsm6dsox_int_notification_get(stmdev_ctx_t *ctx, lsm6dsox_lir_t *val);
+int32_t lsm6dsox_int_notification_set(stmdev_ctx_t *ctx,
+ lsm6dsox_lir_t val);
+int32_t lsm6dsox_int_notification_get(stmdev_ctx_t *ctx,
+ lsm6dsox_lir_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_LSb_FS_DIV_64 = 0,
LSM6DSOX_LSb_FS_DIV_256 = 1,
} lsm6dsox_wake_ths_w_t;
@@ -2250,8 +3641,10 @@ int32_t lsm6dsox_wkup_ths_weight_get(stmdev_ctx_t *ctx,
int32_t lsm6dsox_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsox_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dsox_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsox_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsox_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsox_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dsox_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsox_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -2259,7 +3652,8 @@ int32_t lsm6dsox_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsox_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsox_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_DRIVE_SLEEP_CHG_EVENT = 0,
LSM6DSOX_DRIVE_SLEEP_STATUS = 1,
} lsm6dsox_sleep_status_on_int_t;
@@ -2268,31 +3662,41 @@ int32_t lsm6dsox_act_pin_notification_set(stmdev_ctx_t *ctx,
int32_t lsm6dsox_act_pin_notification_get(stmdev_ctx_t *ctx,
lsm6dsox_sleep_status_on_int_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_XL_AND_GY_NOT_AFFECTED = 0,
LSM6DSOX_XL_12Hz5_GY_NOT_AFFECTED = 1,
LSM6DSOX_XL_12Hz5_GY_SLEEP = 2,
LSM6DSOX_XL_12Hz5_GY_PD = 3,
} lsm6dsox_inact_en_t;
-int32_t lsm6dsox_act_mode_set(stmdev_ctx_t *ctx, lsm6dsox_inact_en_t val);
-int32_t lsm6dsox_act_mode_get(stmdev_ctx_t *ctx, lsm6dsox_inact_en_t *val);
+int32_t lsm6dsox_act_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsox_inact_en_t val);
+int32_t lsm6dsox_act_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsox_inact_en_t *val);
int32_t lsm6dsox_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsox_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dsox_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsox_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsox_tap_detection_on_z_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsox_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsox_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsox_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsox_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsox_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsox_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsox_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsox_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsox_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dsox_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsox_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_XYZ = 0,
LSM6DSOX_YXZ = 1,
LSM6DSOX_XZY = 2,
@@ -2320,7 +3724,8 @@ int32_t lsm6dsox_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsox_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsox_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_ONLY_SINGLE = 0,
LSM6DSOX_BOTH_SINGLE_DOUBLE = 1,
} lsm6dsox_single_double_tap_t;
@@ -2329,7 +3734,8 @@ int32_t lsm6dsox_tap_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dsox_tap_mode_get(stmdev_ctx_t *ctx,
lsm6dsox_single_double_tap_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_DEG_80 = 0,
LSM6DSOX_DEG_70 = 1,
LSM6DSOX_DEG_60 = 2,
@@ -2343,7 +3749,8 @@ int32_t lsm6dsox_6d_threshold_get(stmdev_ctx_t *ctx,
int32_t lsm6dsox_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsox_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_FF_TSH_156mg = 0,
LSM6DSOX_FF_TSH_219mg = 1,
LSM6DSOX_FF_TSH_250mg = 2,
@@ -2353,8 +3760,10 @@ typedef enum {
LSM6DSOX_FF_TSH_469mg = 6,
LSM6DSOX_FF_TSH_500mg = 7,
} lsm6dsox_ff_ths_t;
-int32_t lsm6dsox_ff_threshold_set(stmdev_ctx_t *ctx, lsm6dsox_ff_ths_t val);
-int32_t lsm6dsox_ff_threshold_get(stmdev_ctx_t *ctx, lsm6dsox_ff_ths_t *val);
+int32_t lsm6dsox_ff_threshold_set(stmdev_ctx_t *ctx,
+ lsm6dsox_ff_ths_t val);
+int32_t lsm6dsox_ff_threshold_get(stmdev_ctx_t *ctx,
+ lsm6dsox_ff_ths_t *val);
int32_t lsm6dsox_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsox_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -2362,10 +3771,13 @@ int32_t lsm6dsox_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsox_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val);
int32_t lsm6dsox_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val);
-int32_t lsm6dsox_compression_algo_init_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsox_compression_algo_init_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsox_compression_algo_init_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsox_compression_algo_init_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_CMP_DISABLE = 0x00,
LSM6DSOX_CMP_ALWAYS = 0x04,
LSM6DSOX_CMP_8_TO_1 = 0x05,
@@ -2373,24 +3785,26 @@ typedef enum {
LSM6DSOX_CMP_32_TO_1 = 0x07,
} lsm6dsox_uncoptr_rate_t;
int32_t lsm6dsox_compression_algo_set(stmdev_ctx_t *ctx,
- lsm6dsox_uncoptr_rate_t val);
+ lsm6dsox_uncoptr_rate_t val);
int32_t lsm6dsox_compression_algo_get(stmdev_ctx_t *ctx,
- lsm6dsox_uncoptr_rate_t *val);
+ lsm6dsox_uncoptr_rate_t *val);
int32_t lsm6dsox_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
- uint8_t val);
+ uint8_t val);
int32_t lsm6dsox_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
- uint8_t *val);
+ uint8_t *val);
int32_t lsm6dsox_compression_algo_real_time_set(stmdev_ctx_t *ctx,
- uint8_t val);
+ uint8_t val);
int32_t lsm6dsox_compression_algo_real_time_get(stmdev_ctx_t *ctx,
- uint8_t *val);
+ uint8_t *val);
int32_t lsm6dsox_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsox_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsox_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_XL_NOT_BATCHED = 0,
LSM6DSOX_XL_BATCHED_AT_12Hz5 = 1,
LSM6DSOX_XL_BATCHED_AT_26Hz = 2,
@@ -2404,10 +3818,13 @@ typedef enum {
LSM6DSOX_XL_BATCHED_AT_6667Hz = 10,
LSM6DSOX_XL_BATCHED_AT_6Hz5 = 11,
} lsm6dsox_bdr_xl_t;
-int32_t lsm6dsox_fifo_xl_batch_set(stmdev_ctx_t *ctx, lsm6dsox_bdr_xl_t val);
-int32_t lsm6dsox_fifo_xl_batch_get(stmdev_ctx_t *ctx, lsm6dsox_bdr_xl_t *val);
+int32_t lsm6dsox_fifo_xl_batch_set(stmdev_ctx_t *ctx,
+ lsm6dsox_bdr_xl_t val);
+int32_t lsm6dsox_fifo_xl_batch_get(stmdev_ctx_t *ctx,
+ lsm6dsox_bdr_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_GY_NOT_BATCHED = 0,
LSM6DSOX_GY_BATCHED_AT_12Hz5 = 1,
LSM6DSOX_GY_BATCHED_AT_26Hz = 2,
@@ -2421,10 +3838,13 @@ typedef enum {
LSM6DSOX_GY_BATCHED_AT_6667Hz = 10,
LSM6DSOX_GY_BATCHED_AT_6Hz5 = 11,
} lsm6dsox_bdr_gy_t;
-int32_t lsm6dsox_fifo_gy_batch_set(stmdev_ctx_t *ctx, lsm6dsox_bdr_gy_t val);
-int32_t lsm6dsox_fifo_gy_batch_get(stmdev_ctx_t *ctx, lsm6dsox_bdr_gy_t *val);
+int32_t lsm6dsox_fifo_gy_batch_set(stmdev_ctx_t *ctx,
+ lsm6dsox_bdr_gy_t val);
+int32_t lsm6dsox_fifo_gy_batch_get(stmdev_ctx_t *ctx,
+ lsm6dsox_bdr_gy_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_BYPASS_MODE = 0,
LSM6DSOX_FIFO_MODE = 1,
LSM6DSOX_STREAM_TO_FIFO_MODE = 3,
@@ -2432,37 +3852,43 @@ typedef enum {
LSM6DSOX_STREAM_MODE = 6,
LSM6DSOX_BYPASS_TO_FIFO_MODE = 7,
} lsm6dsox_fifo_mode_t;
-int32_t lsm6dsox_fifo_mode_set(stmdev_ctx_t *ctx, lsm6dsox_fifo_mode_t val);
-int32_t lsm6dsox_fifo_mode_get(stmdev_ctx_t *ctx, lsm6dsox_fifo_mode_t *val);
+int32_t lsm6dsox_fifo_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsox_fifo_mode_t val);
+int32_t lsm6dsox_fifo_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsox_fifo_mode_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_TEMP_NOT_BATCHED = 0,
LSM6DSOX_TEMP_BATCHED_AT_1Hz6 = 1,
LSM6DSOX_TEMP_BATCHED_AT_12Hz5 = 2,
LSM6DSOX_TEMP_BATCHED_AT_52Hz = 3,
} lsm6dsox_odr_t_batch_t;
int32_t lsm6dsox_fifo_temp_batch_set(stmdev_ctx_t *ctx,
- lsm6dsox_odr_t_batch_t val);
+ lsm6dsox_odr_t_batch_t val);
int32_t lsm6dsox_fifo_temp_batch_get(stmdev_ctx_t *ctx,
- lsm6dsox_odr_t_batch_t *val);
+ lsm6dsox_odr_t_batch_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_NO_DECIMATION = 0,
LSM6DSOX_DEC_1 = 1,
LSM6DSOX_DEC_8 = 2,
LSM6DSOX_DEC_32 = 3,
} lsm6dsox_odr_ts_batch_t;
int32_t lsm6dsox_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
- lsm6dsox_odr_ts_batch_t val);
+ lsm6dsox_odr_ts_batch_t val);
int32_t lsm6dsox_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
- lsm6dsox_odr_ts_batch_t *val);
+ lsm6dsox_odr_ts_batch_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_XL_BATCH_EVENT = 0,
LSM6DSOX_GYRO_BATCH_EVENT = 1,
} lsm6dsox_trig_counter_bdr_t;
-typedef enum {
+typedef enum
+{
LSM6DSOX_GYRO_NC_TAG = 1,
LSM6DSOX_XL_NC_TAG,
LSM6DSOX_TEMPERATURE_TAG,
@@ -2491,18 +3917,21 @@ int32_t lsm6dsox_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
int32_t lsm6dsox_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
lsm6dsox_trig_counter_bdr_t *val);
-int32_t lsm6dsox_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsox_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsox_rst_batch_counter_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsox_rst_batch_counter_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dsox_batch_counter_threshold_set(stmdev_ctx_t *ctx,
- uint16_t val);
+ uint16_t val);
int32_t lsm6dsox_batch_counter_threshold_get(stmdev_ctx_t *ctx,
- uint16_t *val);
+ uint16_t *val);
-int32_t lsm6dsox_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t lsm6dsox_fifo_data_level_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
int32_t lsm6dsox_fifo_status_get(stmdev_ctx_t *ctx,
- lsm6dsox_fifo_status2_t *val);
+ lsm6dsox_fifo_status2_t *val);
int32_t lsm6dsox_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -2511,47 +3940,60 @@ int32_t lsm6dsox_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsox_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsox_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
- lsm6dsox_fifo_tag_t *val);
+ lsm6dsox_fifo_tag_t *val);
int32_t lsm6dsox_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsox_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsox_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsox_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsox_sh_batch_slave_0_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dsox_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsox_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsox_sh_batch_slave_1_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dsox_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsox_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsox_sh_batch_slave_2_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dsox_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsox_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsox_sh_batch_slave_3_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_DEN_DISABLE = 0,
LSM6DSOX_LEVEL_FIFO = 6,
LSM6DSOX_LEVEL_LETCHED = 3,
LSM6DSOX_LEVEL_TRIGGER = 2,
LSM6DSOX_EDGE_TRIGGER = 4,
} lsm6dsox_den_mode_t;
-int32_t lsm6dsox_den_mode_set(stmdev_ctx_t *ctx, lsm6dsox_den_mode_t val);
-int32_t lsm6dsox_den_mode_get(stmdev_ctx_t *ctx, lsm6dsox_den_mode_t *val);
+int32_t lsm6dsox_den_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsox_den_mode_t val);
+int32_t lsm6dsox_den_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsox_den_mode_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_DEN_ACT_LOW = 0,
LSM6DSOX_DEN_ACT_HIGH = 1,
} lsm6dsox_den_lh_t;
-int32_t lsm6dsox_den_polarity_set(stmdev_ctx_t *ctx, lsm6dsox_den_lh_t val);
-int32_t lsm6dsox_den_polarity_get(stmdev_ctx_t *ctx, lsm6dsox_den_lh_t *val);
+int32_t lsm6dsox_den_polarity_set(stmdev_ctx_t *ctx,
+ lsm6dsox_den_lh_t val);
+int32_t lsm6dsox_den_polarity_get(stmdev_ctx_t *ctx,
+ lsm6dsox_den_lh_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_STAMP_IN_GY_DATA = 0,
LSM6DSOX_STAMP_IN_XL_DATA = 1,
LSM6DSOX_STAMP_IN_GY_XL_DATA = 2,
} lsm6dsox_den_xl_g_t;
-int32_t lsm6dsox_den_enable_set(stmdev_ctx_t *ctx, lsm6dsox_den_xl_g_t val);
-int32_t lsm6dsox_den_enable_get(stmdev_ctx_t *ctx, lsm6dsox_den_xl_g_t *val);
+int32_t lsm6dsox_den_enable_set(stmdev_ctx_t *ctx,
+ lsm6dsox_den_xl_g_t val);
+int32_t lsm6dsox_den_enable_get(stmdev_ctx_t *ctx,
+ lsm6dsox_den_xl_g_t *val);
int32_t lsm6dsox_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsox_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -2562,67 +4004,74 @@ int32_t lsm6dsox_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsox_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsox_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
- LSM6DSOX_PEDO_DISABLE = 0x00,
- LSM6DSOX_PEDO_BASE_MODE = 0x01,
- LSM6DSOX_FALSE_STEP_REJ = 0x13,
- LSM6DSOX_FALSE_STEP_REJ_ADV_MODE = 0x33,
+typedef enum
+{
+ LSM6DSOX_PEDO_BASE_MODE = 0x00,
+ LSM6DSOX_FALSE_STEP_REJ = 0x10,
+ LSM6DSOX_FALSE_STEP_REJ_ADV_MODE = 0x30,
} lsm6dsox_pedo_md_t;
-int32_t lsm6dsox_pedo_sens_set(stmdev_ctx_t *ctx, lsm6dsox_pedo_md_t val);
-int32_t lsm6dsox_pedo_sens_get(stmdev_ctx_t *ctx, lsm6dsox_pedo_md_t *val);
+int32_t lsm6dsox_pedo_sens_set(stmdev_ctx_t *ctx,
+ lsm6dsox_pedo_md_t val);
+int32_t lsm6dsox_pedo_sens_get(stmdev_ctx_t *ctx,
+ lsm6dsox_pedo_md_t *val);
-int32_t lsm6dsox_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsox_pedo_step_detect_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dsox_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
- uint8_t *buff);
+ uint8_t *buff);
int32_t lsm6dsox_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
- uint8_t *buff);
+ uint8_t *buff);
-int32_t lsm6dsox_pedo_steps_period_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsox_pedo_steps_period_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsox_pedo_steps_period_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t lsm6dsox_pedo_steps_period_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
-int32_t lsm6dsox_pedo_adv_detection_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsox_pedo_adv_detection_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsox_pedo_adv_detection_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsox_pedo_adv_detection_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dsox_pedo_false_step_rejection_set(stmdev_ctx_t *ctx,
- uint8_t val);
+ uint8_t val);
int32_t lsm6dsox_pedo_false_step_rejection_get(stmdev_ctx_t *ctx,
- uint8_t *val);
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_EVERY_STEP = 0,
LSM6DSOX_COUNT_OVERFLOW = 1,
} lsm6dsox_carry_count_en_t;
int32_t lsm6dsox_pedo_int_mode_set(stmdev_ctx_t *ctx,
- lsm6dsox_carry_count_en_t val);
+ lsm6dsox_carry_count_en_t val);
int32_t lsm6dsox_pedo_int_mode_get(stmdev_ctx_t *ctx,
- lsm6dsox_carry_count_en_t *val);
-
-int32_t lsm6dsox_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsox_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
+ lsm6dsox_carry_count_en_t *val);
int32_t lsm6dsox_motion_flag_data_ready_get(stmdev_ctx_t *ctx,
- uint8_t *val);
-
-int32_t lsm6dsox_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsox_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
+ uint8_t *val);
int32_t lsm6dsox_tilt_flag_data_ready_get(stmdev_ctx_t *ctx,
- uint8_t *val);
+ uint8_t *val);
-int32_t lsm6dsox_sh_mag_sensitivity_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsox_sh_mag_sensitivity_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsox_sh_mag_sensitivity_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t lsm6dsox_sh_mag_sensitivity_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
-int32_t lsm6dsox_mlc_mag_sensitivity_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsox_mlc_mag_sensitivity_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsox_mlc_mag_sensitivity_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t lsm6dsox_mlc_mag_sensitivity_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
-int32_t lsm6dsox_mag_offset_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsox_mag_offset_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsox_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val);
+int32_t lsm6dsox_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val);
-int32_t lsm6dsox_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsox_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsox_mag_soft_iron_set(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t lsm6dsox_mag_soft_iron_get(stmdev_ctx_t *ctx, uint16_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_Z_EQ_Y = 0,
LSM6DSOX_Z_EQ_MIN_Y = 1,
LSM6DSOX_Z_EQ_X = 2,
@@ -2631,11 +4080,12 @@ typedef enum {
LSM6DSOX_Z_EQ_Z = 5,
} lsm6dsox_mag_z_axis_t;
int32_t lsm6dsox_mag_z_orient_set(stmdev_ctx_t *ctx,
- lsm6dsox_mag_z_axis_t val);
+ lsm6dsox_mag_z_axis_t val);
int32_t lsm6dsox_mag_z_orient_get(stmdev_ctx_t *ctx,
- lsm6dsox_mag_z_axis_t *val);
+ lsm6dsox_mag_z_axis_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_Y_EQ_Y = 0,
LSM6DSOX_Y_EQ_MIN_Y = 1,
LSM6DSOX_Y_EQ_X = 2,
@@ -2644,11 +4094,12 @@ typedef enum {
LSM6DSOX_Y_EQ_Z = 5,
} lsm6dsox_mag_y_axis_t;
int32_t lsm6dsox_mag_y_orient_set(stmdev_ctx_t *ctx,
- lsm6dsox_mag_y_axis_t val);
+ lsm6dsox_mag_y_axis_t val);
int32_t lsm6dsox_mag_y_orient_get(stmdev_ctx_t *ctx,
- lsm6dsox_mag_y_axis_t *val);
+ lsm6dsox_mag_y_axis_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_X_EQ_Y = 0,
LSM6DSOX_X_EQ_MIN_Y = 1,
LSM6DSOX_X_EQ_X = 2,
@@ -2657,84 +4108,94 @@ typedef enum {
LSM6DSOX_X_EQ_Z = 5,
} lsm6dsox_mag_x_axis_t;
int32_t lsm6dsox_mag_x_orient_set(stmdev_ctx_t *ctx,
- lsm6dsox_mag_x_axis_t val);
+ lsm6dsox_mag_x_axis_t val);
int32_t lsm6dsox_mag_x_orient_get(stmdev_ctx_t *ctx,
- lsm6dsox_mag_x_axis_t *val);
+ lsm6dsox_mag_x_axis_t *val);
int32_t lsm6dsox_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
- uint8_t *val);
-
-int32_t lsm6dsox_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsox_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val);
+ uint8_t *val);
-typedef struct {
- lsm6dsox_fsm_enable_a_t fsm_enable_a;
- lsm6dsox_fsm_enable_b_t fsm_enable_b;
+typedef struct
+{
+ lsm6dsox_fsm_enable_a_t fsm_enable_a;
+ lsm6dsox_fsm_enable_b_t fsm_enable_b;
} lsm6dsox_emb_fsm_enable_t;
int32_t lsm6dsox_fsm_enable_set(stmdev_ctx_t *ctx,
- lsm6dsox_emb_fsm_enable_t *val);
+ lsm6dsox_emb_fsm_enable_t *val);
int32_t lsm6dsox_fsm_enable_get(stmdev_ctx_t *ctx,
- lsm6dsox_emb_fsm_enable_t *val);
+ lsm6dsox_emb_fsm_enable_t *val);
-int32_t lsm6dsox_long_cnt_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsox_long_cnt_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsox_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val);
+int32_t lsm6dsox_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_LC_NORMAL = 0,
LSM6DSOX_LC_CLEAR = 1,
LSM6DSOX_LC_CLEAR_DONE = 2,
} lsm6dsox_fsm_lc_clr_t;
-int32_t lsm6dsox_long_clr_set(stmdev_ctx_t *ctx, lsm6dsox_fsm_lc_clr_t val);
-int32_t lsm6dsox_long_clr_get(stmdev_ctx_t *ctx, lsm6dsox_fsm_lc_clr_t *val);
-
-typedef struct {
- lsm6dsox_fsm_outs1_t fsm_outs1;
- lsm6dsox_fsm_outs2_t fsm_outs2;
- lsm6dsox_fsm_outs3_t fsm_outs3;
- lsm6dsox_fsm_outs4_t fsm_outs4;
- lsm6dsox_fsm_outs5_t fsm_outs5;
- lsm6dsox_fsm_outs6_t fsm_outs6;
- lsm6dsox_fsm_outs7_t fsm_outs7;
- lsm6dsox_fsm_outs8_t fsm_outs8;
- lsm6dsox_fsm_outs1_t fsm_outs9;
- lsm6dsox_fsm_outs2_t fsm_outs10;
- lsm6dsox_fsm_outs3_t fsm_outs11;
- lsm6dsox_fsm_outs4_t fsm_outs12;
- lsm6dsox_fsm_outs5_t fsm_outs13;
- lsm6dsox_fsm_outs6_t fsm_outs14;
- lsm6dsox_fsm_outs7_t fsm_outs15;
- lsm6dsox_fsm_outs8_t fsm_outs16;
+int32_t lsm6dsox_long_clr_set(stmdev_ctx_t *ctx,
+ lsm6dsox_fsm_lc_clr_t val);
+int32_t lsm6dsox_long_clr_get(stmdev_ctx_t *ctx,
+ lsm6dsox_fsm_lc_clr_t *val);
+
+typedef struct
+{
+ lsm6dsox_fsm_outs1_t fsm_outs1;
+ lsm6dsox_fsm_outs2_t fsm_outs2;
+ lsm6dsox_fsm_outs3_t fsm_outs3;
+ lsm6dsox_fsm_outs4_t fsm_outs4;
+ lsm6dsox_fsm_outs5_t fsm_outs5;
+ lsm6dsox_fsm_outs6_t fsm_outs6;
+ lsm6dsox_fsm_outs7_t fsm_outs7;
+ lsm6dsox_fsm_outs8_t fsm_outs8;
+ lsm6dsox_fsm_outs1_t fsm_outs9;
+ lsm6dsox_fsm_outs2_t fsm_outs10;
+ lsm6dsox_fsm_outs3_t fsm_outs11;
+ lsm6dsox_fsm_outs4_t fsm_outs12;
+ lsm6dsox_fsm_outs5_t fsm_outs13;
+ lsm6dsox_fsm_outs6_t fsm_outs14;
+ lsm6dsox_fsm_outs7_t fsm_outs15;
+ lsm6dsox_fsm_outs8_t fsm_outs16;
} lsm6dsox_fsm_out_t;
-int32_t lsm6dsox_fsm_out_get(stmdev_ctx_t *ctx, lsm6dsox_fsm_out_t *val);
+int32_t lsm6dsox_fsm_out_get(stmdev_ctx_t *ctx,
+ lsm6dsox_fsm_out_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_ODR_FSM_12Hz5 = 0,
LSM6DSOX_ODR_FSM_26Hz = 1,
LSM6DSOX_ODR_FSM_52Hz = 2,
LSM6DSOX_ODR_FSM_104Hz = 3,
} lsm6dsox_fsm_odr_t;
-int32_t lsm6dsox_fsm_data_rate_set(stmdev_ctx_t *ctx, lsm6dsox_fsm_odr_t val);
-int32_t lsm6dsox_fsm_data_rate_get(stmdev_ctx_t *ctx, lsm6dsox_fsm_odr_t *val);
+int32_t lsm6dsox_fsm_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dsox_fsm_odr_t val);
+int32_t lsm6dsox_fsm_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dsox_fsm_odr_t *val);
int32_t lsm6dsox_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsox_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dsox_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint16_t val);
-int32_t lsm6dsox_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint16_t *val);
-
-int32_t lsm6dsox_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsox_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsox_long_cnt_int_value_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t lsm6dsox_long_cnt_int_value_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
-int32_t lsm6dsox_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val);
-int32_t lsm6dsox_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t lsm6dsox_fsm_number_of_programs_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsox_fsm_number_of_programs_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsox_mlc_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsox_mlc_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsox_fsm_start_address_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t lsm6dsox_fsm_start_address_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
int32_t lsm6dsox_mlc_status_get(stmdev_ctx_t *ctx,
lsm6dsox_mlc_status_mainpage_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_ODR_PRGS_12Hz5 = 0,
LSM6DSOX_ODR_PRGS_26Hz = 1,
LSM6DSOX_ODR_PRGS_52Hz = 2,
@@ -2745,129 +4206,144 @@ int32_t lsm6dsox_mlc_data_rate_set(stmdev_ctx_t *ctx,
int32_t lsm6dsox_mlc_data_rate_get(stmdev_ctx_t *ctx,
lsm6dsox_mlc_odr_t *val);
-typedef struct {
- lsm6dsox_sensor_hub_1_t sh_byte_1;
- lsm6dsox_sensor_hub_2_t sh_byte_2;
- lsm6dsox_sensor_hub_3_t sh_byte_3;
- lsm6dsox_sensor_hub_4_t sh_byte_4;
- lsm6dsox_sensor_hub_5_t sh_byte_5;
- lsm6dsox_sensor_hub_6_t sh_byte_6;
- lsm6dsox_sensor_hub_7_t sh_byte_7;
- lsm6dsox_sensor_hub_8_t sh_byte_8;
- lsm6dsox_sensor_hub_9_t sh_byte_9;
- lsm6dsox_sensor_hub_10_t sh_byte_10;
- lsm6dsox_sensor_hub_11_t sh_byte_11;
- lsm6dsox_sensor_hub_12_t sh_byte_12;
- lsm6dsox_sensor_hub_13_t sh_byte_13;
- lsm6dsox_sensor_hub_14_t sh_byte_14;
- lsm6dsox_sensor_hub_15_t sh_byte_15;
- lsm6dsox_sensor_hub_16_t sh_byte_16;
- lsm6dsox_sensor_hub_17_t sh_byte_17;
- lsm6dsox_sensor_hub_18_t sh_byte_18;
+typedef struct
+{
+ lsm6dsox_sensor_hub_1_t sh_byte_1;
+ lsm6dsox_sensor_hub_2_t sh_byte_2;
+ lsm6dsox_sensor_hub_3_t sh_byte_3;
+ lsm6dsox_sensor_hub_4_t sh_byte_4;
+ lsm6dsox_sensor_hub_5_t sh_byte_5;
+ lsm6dsox_sensor_hub_6_t sh_byte_6;
+ lsm6dsox_sensor_hub_7_t sh_byte_7;
+ lsm6dsox_sensor_hub_8_t sh_byte_8;
+ lsm6dsox_sensor_hub_9_t sh_byte_9;
+ lsm6dsox_sensor_hub_10_t sh_byte_10;
+ lsm6dsox_sensor_hub_11_t sh_byte_11;
+ lsm6dsox_sensor_hub_12_t sh_byte_12;
+ lsm6dsox_sensor_hub_13_t sh_byte_13;
+ lsm6dsox_sensor_hub_14_t sh_byte_14;
+ lsm6dsox_sensor_hub_15_t sh_byte_15;
+ lsm6dsox_sensor_hub_16_t sh_byte_16;
+ lsm6dsox_sensor_hub_17_t sh_byte_17;
+ lsm6dsox_sensor_hub_18_t sh_byte_18;
} lsm6dsox_emb_sh_read_t;
int32_t lsm6dsox_sh_read_data_raw_get(stmdev_ctx_t *ctx,
- lsm6dsox_emb_sh_read_t *val,
- uint8_t len);
+ lsm6dsox_emb_sh_read_t *val,
+ uint8_t len);
-typedef enum {
+typedef enum
+{
LSM6DSOX_SLV_0 = 0,
LSM6DSOX_SLV_0_1 = 1,
LSM6DSOX_SLV_0_1_2 = 2,
LSM6DSOX_SLV_0_1_2_3 = 3,
} lsm6dsox_aux_sens_on_t;
int32_t lsm6dsox_sh_slave_connected_set(stmdev_ctx_t *ctx,
- lsm6dsox_aux_sens_on_t val);
+ lsm6dsox_aux_sens_on_t val);
int32_t lsm6dsox_sh_slave_connected_get(stmdev_ctx_t *ctx,
- lsm6dsox_aux_sens_on_t *val);
+ lsm6dsox_aux_sens_on_t *val);
int32_t lsm6dsox_sh_master_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsox_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_EXT_PULL_UP = 0,
LSM6DSOX_INTERNAL_PULL_UP = 1,
} lsm6dsox_shub_pu_en_t;
-int32_t lsm6dsox_sh_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsox_shub_pu_en_t val);
-int32_t lsm6dsox_sh_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsox_shub_pu_en_t *val);
+int32_t lsm6dsox_sh_pin_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsox_shub_pu_en_t val);
+int32_t lsm6dsox_sh_pin_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsox_shub_pu_en_t *val);
int32_t lsm6dsox_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsox_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_EXT_ON_INT2_PIN = 1,
LSM6DSOX_XL_GY_DRDY = 0,
} lsm6dsox_start_config_t;
int32_t lsm6dsox_sh_syncro_mode_set(stmdev_ctx_t *ctx,
- lsm6dsox_start_config_t val);
+ lsm6dsox_start_config_t val);
int32_t lsm6dsox_sh_syncro_mode_get(stmdev_ctx_t *ctx,
- lsm6dsox_start_config_t *val);
+ lsm6dsox_start_config_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_EACH_SH_CYCLE = 0,
LSM6DSOX_ONLY_FIRST_CYCLE = 1,
} lsm6dsox_write_once_t;
int32_t lsm6dsox_sh_write_mode_set(stmdev_ctx_t *ctx,
- lsm6dsox_write_once_t val);
+ lsm6dsox_write_once_t val);
int32_t lsm6dsox_sh_write_mode_get(stmdev_ctx_t *ctx,
- lsm6dsox_write_once_t *val);
+ lsm6dsox_write_once_t *val);
int32_t lsm6dsox_sh_reset_set(stmdev_ctx_t *ctx);
int32_t lsm6dsox_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_SH_ODR_104Hz = 0,
LSM6DSOX_SH_ODR_52Hz = 1,
LSM6DSOX_SH_ODR_26Hz = 2,
LSM6DSOX_SH_ODR_13Hz = 3,
} lsm6dsox_shub_odr_t;
-int32_t lsm6dsox_sh_data_rate_set(stmdev_ctx_t *ctx, lsm6dsox_shub_odr_t val);
-int32_t lsm6dsox_sh_data_rate_get(stmdev_ctx_t *ctx, lsm6dsox_shub_odr_t *val);
+int32_t lsm6dsox_sh_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dsox_shub_odr_t val);
+int32_t lsm6dsox_sh_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dsox_shub_odr_t *val);
-typedef struct{
+typedef struct
+{
uint8_t slv0_add;
uint8_t slv0_subadd;
uint8_t slv0_data;
} lsm6dsox_sh_cfg_write_t;
-int32_t lsm6dsox_sh_cfg_write(stmdev_ctx_t *ctx, lsm6dsox_sh_cfg_write_t *val);
+int32_t lsm6dsox_sh_cfg_write(stmdev_ctx_t *ctx,
+ lsm6dsox_sh_cfg_write_t *val);
-typedef struct{
+typedef struct
+{
uint8_t slv_add;
uint8_t slv_subadd;
uint8_t slv_len;
} lsm6dsox_sh_cfg_read_t;
int32_t lsm6dsox_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
- lsm6dsox_sh_cfg_read_t *val);
+ lsm6dsox_sh_cfg_read_t *val);
int32_t lsm6dsox_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
- lsm6dsox_sh_cfg_read_t *val);
+ lsm6dsox_sh_cfg_read_t *val);
int32_t lsm6dsox_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
- lsm6dsox_sh_cfg_read_t *val);
+ lsm6dsox_sh_cfg_read_t *val);
int32_t lsm6dsox_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
- lsm6dsox_sh_cfg_read_t *val);
+ lsm6dsox_sh_cfg_read_t *val);
int32_t lsm6dsox_sh_status_get(stmdev_ctx_t *ctx,
- lsm6dsox_status_master_t *val);
-typedef enum {
+ lsm6dsox_status_master_t *val);
+typedef enum
+{
LSM6DSOX_S4S_TPH_7bit = 0,
LSM6DSOX_S4S_TPH_15bit = 1,
} lsm6dsox_s4s_tph_res_t;
int32_t lsm6dsox_s4s_tph_res_set(stmdev_ctx_t *ctx,
- lsm6dsox_s4s_tph_res_t val);
+ lsm6dsox_s4s_tph_res_t val);
int32_t lsm6dsox_s4s_tph_res_get(stmdev_ctx_t *ctx,
- lsm6dsox_s4s_tph_res_t *val);
+ lsm6dsox_s4s_tph_res_t *val);
int32_t lsm6dsox_s4s_tph_val_set(stmdev_ctx_t *ctx, uint16_t val);
int32_t lsm6dsox_s4s_tph_val_get(stmdev_ctx_t *ctx, uint16_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_S4S_DT_RES_11 = 0,
LSM6DSOX_S4S_DT_RES_12 = 1,
LSM6DSOX_S4S_DT_RES_13 = 2,
LSM6DSOX_S4S_DT_RES_14 = 3,
} lsm6dsox_s4s_res_ratio_t;
int32_t lsm6dsox_s4s_res_ratio_set(stmdev_ctx_t *ctx,
- lsm6dsox_s4s_res_ratio_t val);
+ lsm6dsox_s4s_res_ratio_t val);
int32_t lsm6dsox_s4s_res_ratio_get(stmdev_ctx_t *ctx,
- lsm6dsox_s4s_res_ratio_t *val);
+ lsm6dsox_s4s_res_ratio_t *val);
int32_t lsm6dsox_s4s_command_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsox_s4s_command_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -2875,15 +4351,18 @@ int32_t lsm6dsox_s4s_command_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsox_s4s_dt_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsox_s4s_dt_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef struct {
+typedef struct
+{
uint8_t ui;
uint8_t aux;
} lsm6dsox_id_t;
int32_t lsm6dsox_id_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
lsm6dsox_id_t *val);
-typedef struct {
- enum {
+typedef struct
+{
+ enum
+ {
LSM6DSOX_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */
LSM6DSOX_SPI_4W = 0x06, /* Only SPI: SDO / SDI separated pins */
LSM6DSOX_SPI_3W = 0x07, /* Only SPI: SDO / SDI share the same pin */
@@ -2893,17 +4372,21 @@ typedef struct {
LSM6DSOX_I3C_T_1ms = 0x22, /* I3C: available time equal to 1 ms */
LSM6DSOX_I3C_T_25ms = 0x32, /* I3C: available time equal to 25 ms */
} ui_bus_md;
- enum {
+ enum
+ {
LSM6DSOX_SPI_4W_AUX = 0x00,
LSM6DSOX_SPI_3W_AUX = 0x01,
} aux_bus_md;
} lsm6dsox_bus_mode_t;
-int32_t lsm6dsox_bus_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
+int32_t lsm6dsox_bus_mode_set(stmdev_ctx_t *ctx,
+ stmdev_ctx_t *aux_ctx,
lsm6dsox_bus_mode_t val);
-int32_t lsm6dsox_bus_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
+int32_t lsm6dsox_bus_mode_get(stmdev_ctx_t *ctx,
+ stmdev_ctx_t *aux_ctx,
lsm6dsox_bus_mode_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSOX_DRV_RDY = 0x00, /* Initialize the device for driver usage */
LSM6DSOX_BOOT = 0x01, /* Restore calib. param. ( it takes 10ms ) */
LSM6DSOX_RESET = 0x02, /* Reset configuration registers */
@@ -2916,60 +4399,77 @@ typedef enum {
} lsm6dsox_init_t;
int32_t lsm6dsox_init_set(stmdev_ctx_t *ctx, lsm6dsox_init_t val);
-typedef struct {
- uint8_t sw_reset : 1; /* Restoring configuration registers */
+typedef struct
+{
+uint8_t sw_reset :
+ 1; /* Restoring configuration registers */
uint8_t boot : 1; /* Restoring calibration parameters */
uint8_t drdy_xl : 1; /* Accelerometer data ready */
uint8_t drdy_g : 1; /* Gyroscope data ready */
uint8_t drdy_temp : 1; /* Temperature data ready */
uint8_t ois_drdy_xl : 1; /* Accelerometer data ready on OIS */
uint8_t ois_drdy_g : 1; /* Gyroscope data ready on OIS */
- uint8_t ois_gyro_settling : 1; /* Gyroscope is in the settling phase */
+uint8_t ois_gyro_settling :
+ 1; /* Gyroscope is in the settling phase */
} lsm6dsox_status_t;
int32_t lsm6dsox_status_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
lsm6dsox_status_t *val);
-typedef struct {
+typedef struct
+{
uint8_t sdo_sa0_pull_up : 1; /* 1 = pull-up on SDO/SA0 pin */
- uint8_t aux_sdo_ocs_pull_up : 1; /* 1 = pull-up on OCS_Aux/SDO_Aux pins */
+uint8_t aux_sdo_ocs_pull_up :
+ 1; /* 1 = pull-up on OCS_Aux/SDO_Aux pins */
uint8_t int1_int2_push_pull : 1; /* 1 = push-pull / 0 = open-drain*/
- uint8_t int1_pull_down : 1; /* 1 = pull-down always disabled (0=auto) */
+uint8_t int1_pull_down :
+ 1; /* 1 = pull-down always disabled (0=auto) */
} lsm6dsox_pin_conf_t;
-int32_t lsm6dsox_pin_conf_set(stmdev_ctx_t *ctx, lsm6dsox_pin_conf_t val);
-int32_t lsm6dsox_pin_conf_get(stmdev_ctx_t *ctx, lsm6dsox_pin_conf_t *val);
+int32_t lsm6dsox_pin_conf_set(stmdev_ctx_t *ctx,
+ lsm6dsox_pin_conf_t val);
+int32_t lsm6dsox_pin_conf_get(stmdev_ctx_t *ctx,
+ lsm6dsox_pin_conf_t *val);
-typedef struct {
+typedef struct
+{
uint8_t active_low : 1; /* 1 = active low / 0 = active high */
- uint8_t base_latched : 1; /* base functions are: FF, WU, 6D, Tap, Act/Inac */
- uint8_t emb_latched : 1; /* emb functions are: Pedo, Tilt, SMot, Timestamp */
+uint8_t base_latched :
+ 1; /* base functions are: FF, WU, 6D, Tap, Act/Inac */
+uint8_t emb_latched :
+ 1; /* emb functions are: Pedo, Tilt, SMot, Timestamp */
} lsm6dsox_int_mode_t;
int32_t lsm6dsox_interrupt_mode_set(stmdev_ctx_t *ctx,
lsm6dsox_int_mode_t val);
int32_t lsm6dsox_interrupt_mode_get(stmdev_ctx_t *ctx,
lsm6dsox_int_mode_t *val);
-typedef struct {
+typedef struct
+{
uint8_t drdy_xl : 1; /* Accelerometer data ready */
uint8_t drdy_g : 1; /* Gyroscope data ready */
- uint8_t drdy_temp : 1; /* Temperature data ready (1 = int2 pin disable) */
+uint8_t drdy_temp :
+ 1; /* Temperature data ready (1 = int2 pin disable) */
uint8_t boot : 1; /* Restoring calibration parameters */
uint8_t fifo_th : 1; /* FIFO threshold reached */
uint8_t fifo_ovr : 1; /* FIFO overrun */
uint8_t fifo_full : 1; /* FIFO full */
uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */
- uint8_t den_flag : 1; /* external trigger level recognition (DEN) */
+uint8_t den_flag :
+ 1; /* external trigger level recognition (DEN) */
uint8_t sh_endop : 1; /* sensor hub end operation */
- uint8_t timestamp : 1; /* timestamp overflow (1 = int2 pin disable) */
+uint8_t timestamp :
+ 1; /* timestamp overflow (1 = int2 pin disable) */
uint8_t six_d : 1; /* orientation change (6D/4D detection) */
uint8_t double_tap : 1; /* double-tap event */
uint8_t free_fall : 1; /* free fall event */
uint8_t wake_up : 1; /* wake up event */
uint8_t single_tap : 1; /* single-tap event */
- uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */
+uint8_t sleep_change :
+ 1; /* Act/Inact (or Vice-versa) status changed */
uint8_t step_detector : 1; /* Step detected */
uint8_t tilt : 1; /* Relative tilt event detected */
uint8_t sig_mot : 1; /* "significant motion" event detected */
- uint8_t fsm_lc : 1; /* fsm long counter timeout interrupt event */
+uint8_t fsm_lc :
+ 1; /* fsm long counter timeout interrupt event */
uint8_t fsm1 : 1; /* fsm 1 interrupt event */
uint8_t fsm2 : 1; /* fsm 2 interrupt event */
uint8_t fsm3 : 1; /* fsm 3 interrupt event */
@@ -2997,11 +4497,12 @@ typedef struct {
} lsm6dsox_pin_int1_route_t;
int32_t lsm6dsox_pin_int1_route_set(stmdev_ctx_t *ctx,
- lsm6dsox_pin_int1_route_t val);
+ lsm6dsox_pin_int1_route_t val);
int32_t lsm6dsox_pin_int1_route_get(stmdev_ctx_t *ctx,
- lsm6dsox_pin_int1_route_t *val);
+ lsm6dsox_pin_int1_route_t *val);
-typedef struct {
+typedef struct
+{
uint8_t drdy_ois : 1; /* OIS chain data ready */
uint8_t drdy_xl : 1; /* Accelerometer data ready */
uint8_t drdy_g : 1; /* Gyroscope data ready */
@@ -3016,11 +4517,13 @@ typedef struct {
uint8_t free_fall : 1; /* free fall event */
uint8_t wake_up : 1; /* wake up event */
uint8_t single_tap : 1; /* single-tap event */
- uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */
+uint8_t sleep_change :
+ 1; /* Act/Inact (or Vice-versa) status changed */
uint8_t step_detector : 1; /* Step detected */
uint8_t tilt : 1; /* Relative tilt event detected */
uint8_t sig_mot : 1; /* "significant motion" event detected */
- uint8_t fsm_lc : 1; /* fsm long counter timeout interrupt event */
+uint8_t fsm_lc :
+ 1; /* fsm long counter timeout interrupt event */
uint8_t fsm1 : 1; /* fsm 1 interrupt event */
uint8_t fsm2 : 1; /* fsm 2 interrupt event */
uint8_t fsm3 : 1; /* fsm 3 interrupt event */
@@ -3047,17 +4550,22 @@ typedef struct {
uint8_t mlc8 : 1; /* mlc 8 interrupt event */
} lsm6dsox_pin_int2_route_t;
-int32_t lsm6dsox_pin_int2_route_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
+int32_t lsm6dsox_pin_int2_route_set(stmdev_ctx_t *ctx,
+ stmdev_ctx_t *aux_ctx,
lsm6dsox_pin_int2_route_t val);
-int32_t lsm6dsox_pin_int2_route_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
+int32_t lsm6dsox_pin_int2_route_get(stmdev_ctx_t *ctx,
+ stmdev_ctx_t *aux_ctx,
lsm6dsox_pin_int2_route_t *val);
-typedef struct {
+typedef struct
+{
uint8_t drdy_xl : 1; /* Accelerometer data ready */
uint8_t drdy_g : 1; /* Gyroscope data ready */
uint8_t drdy_temp : 1; /* Temperature data ready */
- uint8_t den_flag : 1; /* external trigger level recognition (DEN) */
- uint8_t timestamp : 1; /* timestamp overflow (1 = int2 pin disable) */
+uint8_t den_flag :
+ 1; /* external trigger level recognition (DEN) */
+uint8_t timestamp :
+ 1; /* timestamp overflow (1 = int2 pin disable) */
uint8_t free_fall : 1; /* free fall event */
uint8_t wake_up : 1; /* wake up event */
uint8_t wake_up_z : 1; /* wake up on Z axis event */
@@ -3069,19 +4577,30 @@ typedef struct {
uint8_t tap_y : 1; /* single-tap on Y axis event */
uint8_t tap_x : 1; /* single-tap on X axis event */
uint8_t tap_sign : 1; /* sign of tap event (0-pos / 1-neg) */
- uint8_t six_d : 1; /* orientation change (6D/4D detection) */
- uint8_t six_d_xl : 1; /* X-axis low 6D/4D event (under threshold) */
- uint8_t six_d_xh : 1; /* X-axis high 6D/4D event (over threshold) */
- uint8_t six_d_yl : 1; /* Y-axis low 6D/4D event (under threshold) */
- uint8_t six_d_yh : 1; /* Y-axis high 6D/4D event (over threshold) */
- uint8_t six_d_zl : 1; /* Z-axis low 6D/4D event (under threshold) */
- uint8_t six_d_zh : 1; /* Z-axis high 6D/4D event (over threshold) */
- uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */
- uint8_t sleep_state : 1; /* Act/Inact status flag (0-Act / 1-Inact) */
+uint8_t six_d :
+ 1; /* orientation change (6D/4D detection) */
+uint8_t six_d_xl :
+ 1; /* X-axis low 6D/4D event (under threshold) */
+uint8_t six_d_xh :
+ 1; /* X-axis high 6D/4D event (over threshold) */
+uint8_t six_d_yl :
+ 1; /* Y-axis low 6D/4D event (under threshold) */
+uint8_t six_d_yh :
+ 1; /* Y-axis high 6D/4D event (over threshold) */
+uint8_t six_d_zl :
+ 1; /* Z-axis low 6D/4D event (under threshold) */
+uint8_t six_d_zh :
+ 1; /* Z-axis high 6D/4D event (over threshold) */
+uint8_t sleep_change :
+ 1; /* Act/Inact (or Vice-versa) status changed */
+uint8_t sleep_state :
+ 1; /* Act/Inact status flag (0-Act / 1-Inact) */
uint8_t step_detector : 1; /* Step detected */
uint8_t tilt : 1; /* Relative tilt event detected */
- uint8_t sig_mot : 1; /* "significant motion" event detected */
- uint8_t fsm_lc : 1; /* fsm long counter timeout interrupt event */
+uint8_t sig_mot :
+ 1; /* "significant motion" event detected */
+uint8_t fsm_lc :
+ 1; /* fsm long counter timeout interrupt event */
uint8_t fsm1 : 1; /* fsm 1 interrupt event */
uint8_t fsm2 : 1; /* fsm 2 interrupt event */
uint8_t fsm3 : 1; /* fsm 3 interrupt event */
@@ -3107,14 +4626,21 @@ typedef struct {
uint8_t mlc7 : 1; /* mlc 7 interrupt event */
uint8_t mlc8 : 1; /* mlc 8 interrupt event */
uint8_t sh_endop : 1; /* sensor hub end operation */
- uint8_t sh_slave0_nack : 1; /* Not acknowledge on sensor hub slave 0 */
- uint8_t sh_slave1_nack : 1; /* Not acknowledge on sensor hub slave 1 */
- uint8_t sh_slave2_nack : 1; /* Not acknowledge on sensor hub slave 2 */
- uint8_t sh_slave3_nack : 1; /* Not acknowledge on sensor hub slave 3 */
- uint8_t sh_wr_once : 1; /* "WRITE_ONCE" end on sensor hub slave 0 */
- uint16_t fifo_diff : 10; /* Number of unread sensor data in FIFO*/
+uint8_t sh_slave0_nack :
+ 1; /* Not acknowledge on sensor hub slave 0 */
+uint8_t sh_slave1_nack :
+ 1; /* Not acknowledge on sensor hub slave 1 */
+uint8_t sh_slave2_nack :
+ 1; /* Not acknowledge on sensor hub slave 2 */
+uint8_t sh_slave3_nack :
+ 1; /* Not acknowledge on sensor hub slave 3 */
+uint8_t sh_wr_once :
+ 1; /* "WRITE_ONCE" end on sensor hub slave 0 */
+uint16_t fifo_diff :
+ 10; /* Number of unread sensor data in FIFO*/
uint8_t fifo_ovr_latched : 1; /* Latched FIFO overrun status */
- uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */
+uint8_t fifo_bdr :
+ 1; /* FIFO Batch counter threshold reached */
uint8_t fifo_full : 1; /* FIFO full */
uint8_t fifo_ovr : 1; /* FIFO overrun */
uint8_t fifo_th : 1; /* FIFO threshold reached */
@@ -3122,15 +4648,21 @@ typedef struct {
int32_t lsm6dsox_all_sources_get(stmdev_ctx_t *ctx,
lsm6dsox_all_sources_t *val);
-typedef struct{
+typedef struct
+{
uint8_t odr_fine_tune;
-} dev_cal_t;
-int32_t lsm6dsox_calibration_get(stmdev_ctx_t *ctx, dev_cal_t *val);
-
-typedef struct {
- struct {
- struct {
- enum {
+} lsm6dsox_dev_cal_t;
+int32_t lsm6dsox_calibration_get(stmdev_ctx_t *ctx,
+ lsm6dsox_dev_cal_t *val);
+
+typedef struct
+{
+ struct
+ {
+ struct
+ {
+ enum
+ {
LSM6DSOX_XL_UI_OFF = 0x00, /* in power down */
LSM6DSOX_XL_UI_1Hz6_LP = 0x1B, /* @1Hz6 (low power) */
LSM6DSOX_XL_UI_1Hz6_ULP = 0x2B, /* @1Hz6 (ultra low/Gy, OIS imu off) */
@@ -3155,15 +4687,18 @@ typedef struct {
LSM6DSOX_XL_UI_3333Hz_HP = 0x09, /* @3kHz33 (high performance) */
LSM6DSOX_XL_UI_6667Hz_HP = 0x0A, /* @6kHz66 (high performance) */
} odr;
- enum {
+ enum
+ {
LSM6DSOX_XL_UI_2g = 0,
LSM6DSOX_XL_UI_4g = 2,
LSM6DSOX_XL_UI_8g = 3,
LSM6DSOX_XL_UI_16g = 1, /* OIS full scale is also forced to be 16g */
} fs;
} xl;
- struct {
- enum {
+ struct
+ {
+ enum
+ {
LSM6DSOX_GY_UI_OFF = 0x00, /* gy in power down */
LSM6DSOX_GY_UI_12Hz5_LP = 0x11, /* gy @12Hz5 (low power) */
LSM6DSOX_GY_UI_12Hz5_HP = 0x01, /* gy @12Hz5 (high performance) */
@@ -3181,39 +4716,48 @@ typedef struct {
LSM6DSOX_GY_UI_3333Hz_HP = 0x09, /* gy @3kHz33 (high performance) */
LSM6DSOX_GY_UI_6667Hz_HP = 0x0A, /* gy @6kHz66 (high performance) */
} odr;
- enum {
+ enum
+ {
LSM6DSOX_GY_UI_250dps = 0,
LSM6DSOX_GY_UI_125dps = 1,
LSM6DSOX_GY_UI_500dps = 2,
LSM6DSOX_GY_UI_1000dps = 4,
LSM6DSOX_GY_UI_2000dps = 6,
} fs;
- }gy;
+ } gy;
} ui;
- struct {
- enum {
+ struct
+ {
+ enum
+ {
LSM6DSOX_OIS_ONLY_AUX = 0x00, /* Auxiliary SPI full control */
LSM6DSOX_OIS_ONLY_UI = 0x02, /* Primary interface full control */
LSM6DSOX_OIS_MIXED = 0x01, /* Enabling by UI / read-config by AUX */
} ctrl_md;
- struct {
- enum {
+ struct
+ {
+ enum
+ {
LSM6DSOX_XL_OIS_OFF = 0x00, /* in power down */
LSM6DSOX_XL_OIS_6667Hz_HP = 0x01, /* @6kHz OIS imu active/NO ULP on UI */
} odr;
- enum {
+ enum
+ {
LSM6DSOX_XL_OIS_2g = 0,
LSM6DSOX_XL_OIS_4g = 2,
LSM6DSOX_XL_OIS_8g = 3,
LSM6DSOX_XL_OIS_16g = 1, /* UI full scale is also forced to be 16g */
} fs;
} xl;
- struct {
- enum {
+ struct
+ {
+ enum
+ {
LSM6DSOX_GY_OIS_OFF = 0x00, /* in power down */
LSM6DSOX_GY_OIS_6667Hz_HP = 0x01, /* @6kHz No Ultra Low Power*/
} odr;
- enum {
+ enum
+ {
LSM6DSOX_GY_OIS_250dps = 0,
LSM6DSOX_GY_OIS_125dps = 1,
LSM6DSOX_GY_OIS_500dps = 2,
@@ -3222,27 +4766,33 @@ typedef struct {
} fs;
} gy;
} ois;
- struct {
- enum {
+ struct
+ {
+ enum
+ {
LSM6DSOX_FSM_DISABLE = 0x00,
LSM6DSOX_FSM_XL = 0x01,
LSM6DSOX_FSM_GY = 0x02,
LSM6DSOX_FSM_XL_GY = 0x03,
} sens;
- enum {
+ enum
+ {
LSM6DSOX_FSM_12Hz5 = 0x00,
LSM6DSOX_FSM_26Hz = 0x01,
LSM6DSOX_FSM_52Hz = 0x02,
LSM6DSOX_FSM_104Hz = 0x03,
} odr;
} fsm;
- struct {
- enum {
+ struct
+ {
+ enum
+ {
LSM6DSOX_MLC_DISABLE = 0x00,
LSM6DSOX_MLC_XL = 0x01,
LSM6DSOX_MLC_XL_GY = 0x03,
} sens;
- enum {
+ enum
+ {
LSM6DSOX_MLC_12Hz5 = 0x00,
LSM6DSOX_MLC_26Hz = 0x01,
LSM6DSOX_MLC_52Hz = 0x02,
@@ -3254,35 +4804,59 @@ int32_t lsm6dsox_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
lsm6dsox_md_t *val);
int32_t lsm6dsox_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
lsm6dsox_md_t *val);
-typedef struct {
- struct {
- struct {
- float mg[3];
+
+typedef struct
+{
+ struct
+ {
+ struct
+ {
+ float_t mg[3];
int16_t raw[3];
- }xl;
- struct {
- float mdps[3];
+ } xl;
+ struct
+ {
+ float_t mdps[3];
int16_t raw[3];
- }gy;
- struct {
- float deg_c;
+ } gy;
+ struct
+ {
+ float_t deg_c;
int16_t raw;
- }heat;
+ } heat;
} ui;
- struct {
- struct {
- float mg[3];
+ struct
+ {
+ struct
+ {
+ float_t mg[3];
int16_t raw[3];
- }xl;
- struct {
- float mdps[3];
+ } xl;
+ struct
+ {
+ float_t mdps[3];
int16_t raw[3];
- }gy;
+ } gy;
} ois;
} lsm6dsox_data_t;
int32_t lsm6dsox_data_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
lsm6dsox_md_t *md, lsm6dsox_data_t *data);
+typedef struct
+{
+ uint8_t sig_mot : 1; /* significant motion */
+ uint8_t tilt : 1; /* tilt detection */
+ uint8_t step : 1; /* step counter/detector */
+ uint8_t mlc : 1; /* machine learning core */
+ uint8_t fsm : 1; /* finite state machine */
+ uint8_t fifo_compr : 1; /* mlc 8 interrupt event */
+} lsm6dsox_emb_sens_t;
+int32_t lsm6dsox_embedded_sens_set(stmdev_ctx_t *ctx,
+ lsm6dsox_emb_sens_t *emb_sens);
+int32_t lsm6dsox_embedded_sens_get(stmdev_ctx_t *ctx,
+ lsm6dsox_emb_sens_t *emb_sens);
+int32_t lsm6dsox_embedded_sens_off(stmdev_ctx_t *ctx);
+
/**
* @}
*
diff --git a/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.c b/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.c
index 7c6e33e95bdecc14dfa9df6af02a83111b54b6af..32319a593e10ffbb8b92e0f3e28e11f68b3d709b 100644
--- a/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.c
+++ b/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file lsm6dsr_reg.c
- * @author Sensors Software Solution Team
- * @brief LSM6DSR driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lsm6dsr_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LSM6DSR driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lsm6dsr_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsr_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t lsm6dsr_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t lsm6dsr_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsr_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t lsm6dsr_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -166,17 +172,20 @@ float_t lsm6dsr_from_lsb_to_nsec(int32_t lsb)
*
*/
int32_t lsm6dsr_xl_full_scale_set(stmdev_ctx_t *ctx,
- lsm6dsr_fs_xl_t val)
+ lsm6dsr_fs_xl_t val)
{
lsm6dsr_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
ctrl1_xl.fs_xl = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
+ (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -189,29 +198,36 @@ int32_t lsm6dsr_xl_full_scale_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_xl_full_scale_get(stmdev_ctx_t *ctx,
- lsm6dsr_fs_xl_t *val)
+ lsm6dsr_fs_xl_t *val)
{
lsm6dsr_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- switch (ctrl1_xl.fs_xl){
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ switch (ctrl1_xl.fs_xl)
+ {
case LSM6DSR_2g:
*val = LSM6DSR_2g;
break;
+
case LSM6DSR_16g:
*val = LSM6DSR_16g;
break;
+
case LSM6DSR_4g:
*val = LSM6DSR_4g;
break;
+
case LSM6DSR_8g:
*val = LSM6DSR_8g;
break;
+
default:
*val = LSM6DSR_2g;
break;
}
+
return ret;
}
@@ -224,7 +240,7 @@ int32_t lsm6dsr_xl_full_scale_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_xl_data_rate_set(stmdev_ctx_t *ctx,
- lsm6dsr_odr_xl_t val)
+ lsm6dsr_odr_xl_t val)
{
lsm6dsr_odr_xl_t odr_xl = val;
lsm6dsr_emb_fsm_enable_t fsm_enable;
@@ -234,81 +250,114 @@ int32_t lsm6dsr_xl_data_rate_set(stmdev_ctx_t *ctx,
/* Check the Finite State Machine data rate constraints */
ret = lsm6dsr_fsm_enable_get(ctx, &fsm_enable);
- if (ret == 0) {
- if ( (fsm_enable.fsm_enable_a.fsm1_en |
- fsm_enable.fsm_enable_a.fsm2_en |
- fsm_enable.fsm_enable_a.fsm3_en |
- fsm_enable.fsm_enable_a.fsm4_en |
- fsm_enable.fsm_enable_a.fsm5_en |
- fsm_enable.fsm_enable_a.fsm6_en |
- fsm_enable.fsm_enable_a.fsm7_en |
- fsm_enable.fsm_enable_a.fsm8_en |
- fsm_enable.fsm_enable_b.fsm9_en |
- fsm_enable.fsm_enable_b.fsm10_en |
- fsm_enable.fsm_enable_b.fsm11_en |
- fsm_enable.fsm_enable_b.fsm12_en |
- fsm_enable.fsm_enable_b.fsm13_en |
- fsm_enable.fsm_enable_b.fsm14_en |
- fsm_enable.fsm_enable_b.fsm15_en |
- fsm_enable.fsm_enable_b.fsm16_en ) == PROPERTY_ENABLE ){
+ if (ret == 0)
+ {
+ if ((fsm_enable.fsm_enable_a.fsm1_en |
+ fsm_enable.fsm_enable_a.fsm2_en |
+ fsm_enable.fsm_enable_a.fsm3_en |
+ fsm_enable.fsm_enable_a.fsm4_en |
+ fsm_enable.fsm_enable_a.fsm5_en |
+ fsm_enable.fsm_enable_a.fsm6_en |
+ fsm_enable.fsm_enable_a.fsm7_en |
+ fsm_enable.fsm_enable_a.fsm8_en |
+ fsm_enable.fsm_enable_b.fsm9_en |
+ fsm_enable.fsm_enable_b.fsm10_en |
+ fsm_enable.fsm_enable_b.fsm11_en |
+ fsm_enable.fsm_enable_b.fsm12_en |
+ fsm_enable.fsm_enable_b.fsm13_en |
+ fsm_enable.fsm_enable_b.fsm14_en |
+ fsm_enable.fsm_enable_b.fsm15_en |
+ fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
+ {
ret = lsm6dsr_fsm_data_rate_get(ctx, &fsm_odr);
- if (ret == 0) {
- switch (fsm_odr) {
- case LSM6DSR_ODR_FSM_12Hz5:
- if (val == LSM6DSR_XL_ODR_OFF){
+ if (ret == 0)
+ {
+ switch (fsm_odr)
+ {
+ case LSM6DSR_ODR_FSM_12Hz5:
+ if (val == LSM6DSR_XL_ODR_OFF)
+ {
odr_xl = LSM6DSR_XL_ODR_12Hz5;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
- case LSM6DSR_ODR_FSM_26Hz:
- if (val == LSM6DSR_XL_ODR_OFF){
+ case LSM6DSR_ODR_FSM_26Hz:
+ if (val == LSM6DSR_XL_ODR_OFF)
+ {
odr_xl = LSM6DSR_XL_ODR_26Hz;
+ }
- } else if (val == LSM6DSR_XL_ODR_12Hz5){
+ else if (val == LSM6DSR_XL_ODR_12Hz5)
+ {
odr_xl = LSM6DSR_XL_ODR_26Hz;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
- case LSM6DSR_ODR_FSM_52Hz:
- if (val == LSM6DSR_XL_ODR_OFF){
+ case LSM6DSR_ODR_FSM_52Hz:
+ if (val == LSM6DSR_XL_ODR_OFF)
+ {
odr_xl = LSM6DSR_XL_ODR_52Hz;
+ }
- } else if (val == LSM6DSR_XL_ODR_12Hz5){
+ else if (val == LSM6DSR_XL_ODR_12Hz5)
+ {
odr_xl = LSM6DSR_XL_ODR_52Hz;
+ }
- } else if (val == LSM6DSR_XL_ODR_26Hz){
+ else if (val == LSM6DSR_XL_ODR_26Hz)
+ {
odr_xl = LSM6DSR_XL_ODR_52Hz;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
- case LSM6DSR_ODR_FSM_104Hz:
- if (val == LSM6DSR_XL_ODR_OFF){
+ case LSM6DSR_ODR_FSM_104Hz:
+ if (val == LSM6DSR_XL_ODR_OFF)
+ {
odr_xl = LSM6DSR_XL_ODR_104Hz;
+ }
- } else if (val == LSM6DSR_XL_ODR_12Hz5){
+ else if (val == LSM6DSR_XL_ODR_12Hz5)
+ {
odr_xl = LSM6DSR_XL_ODR_104Hz;
+ }
- } else if (val == LSM6DSR_XL_ODR_26Hz){
+ else if (val == LSM6DSR_XL_ODR_26Hz)
+ {
odr_xl = LSM6DSR_XL_ODR_104Hz;
+ }
- } else if (val == LSM6DSR_XL_ODR_52Hz){
+ else if (val == LSM6DSR_XL_ODR_52Hz)
+ {
odr_xl = LSM6DSR_XL_ODR_104Hz;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
+
default:
odr_xl = val;
break;
@@ -317,14 +366,18 @@ int32_t lsm6dsr_xl_data_rate_set(stmdev_ctx_t *ctx,
}
}
- if(ret == 0){
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
}
- if(ret == 0){
- ctrl1_xl.odr_xl= (uint8_t)odr_xl;
+
+ if (ret == 0)
+ {
+ ctrl1_xl.odr_xl = (uint8_t)odr_xl;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
+ (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -337,53 +390,68 @@ int32_t lsm6dsr_xl_data_rate_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_xl_data_rate_get(stmdev_ctx_t *ctx,
- lsm6dsr_odr_xl_t *val)
+ lsm6dsr_odr_xl_t *val)
{
lsm6dsr_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- switch (ctrl1_xl.odr_xl){
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ switch (ctrl1_xl.odr_xl)
+ {
case LSM6DSR_XL_ODR_OFF:
*val = LSM6DSR_XL_ODR_OFF;
break;
+
case LSM6DSR_XL_ODR_12Hz5:
*val = LSM6DSR_XL_ODR_12Hz5;
break;
+
case LSM6DSR_XL_ODR_26Hz:
*val = LSM6DSR_XL_ODR_26Hz;
break;
+
case LSM6DSR_XL_ODR_52Hz:
*val = LSM6DSR_XL_ODR_52Hz;
break;
+
case LSM6DSR_XL_ODR_104Hz:
*val = LSM6DSR_XL_ODR_104Hz;
break;
+
case LSM6DSR_XL_ODR_208Hz:
*val = LSM6DSR_XL_ODR_208Hz;
break;
+
case LSM6DSR_XL_ODR_417Hz:
*val = LSM6DSR_XL_ODR_417Hz;
break;
+
case LSM6DSR_XL_ODR_833Hz:
*val = LSM6DSR_XL_ODR_833Hz;
break;
+
case LSM6DSR_XL_ODR_1667Hz:
*val = LSM6DSR_XL_ODR_1667Hz;
break;
+
case LSM6DSR_XL_ODR_3333Hz:
*val = LSM6DSR_XL_ODR_3333Hz;
break;
+
case LSM6DSR_XL_ODR_6667Hz:
*val = LSM6DSR_XL_ODR_6667Hz;
break;
+
case LSM6DSR_XL_ODR_6Hz5:
*val = LSM6DSR_XL_ODR_6Hz5;
break;
+
default:
*val = LSM6DSR_XL_ODR_OFF;
break;
}
+
return ret;
}
@@ -396,16 +464,19 @@ int32_t lsm6dsr_xl_data_rate_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_gy_full_scale_set(stmdev_ctx_t *ctx,
- lsm6dsr_fs_g_t val)
+ lsm6dsr_fs_g_t val)
{
lsm6dsr_ctrl2_g_t ctrl2_g;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- if(ret == 0){
- ctrl2_g.fs_g= (uint8_t)val;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
+
+ if (ret == 0)
+ {
+ ctrl2_g.fs_g = (uint8_t)val;
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
}
+
return ret;
}
@@ -418,35 +489,44 @@ int32_t lsm6dsr_gy_full_scale_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_gy_full_scale_get(stmdev_ctx_t *ctx,
- lsm6dsr_fs_g_t *val)
+ lsm6dsr_fs_g_t *val)
{
lsm6dsr_ctrl2_g_t ctrl2_g;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- switch (ctrl2_g.fs_g){
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
+
+ switch (ctrl2_g.fs_g)
+ {
case LSM6DSR_125dps:
*val = LSM6DSR_125dps;
break;
+
case LSM6DSR_250dps:
*val = LSM6DSR_250dps;
break;
+
case LSM6DSR_500dps:
*val = LSM6DSR_500dps;
break;
+
case LSM6DSR_1000dps:
*val = LSM6DSR_1000dps;
break;
+
case LSM6DSR_2000dps:
*val = LSM6DSR_2000dps;
break;
+
case LSM6DSR_4000dps:
*val = LSM6DSR_4000dps;
break;
+
default:
*val = LSM6DSR_125dps;
break;
}
+
return ret;
}
@@ -459,7 +539,7 @@ int32_t lsm6dsr_gy_full_scale_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_gy_data_rate_set(stmdev_ctx_t *ctx,
- lsm6dsr_odr_g_t val)
+ lsm6dsr_odr_g_t val)
{
lsm6dsr_odr_g_t odr_gy = val;
lsm6dsr_emb_fsm_enable_t fsm_enable;
@@ -469,81 +549,114 @@ int32_t lsm6dsr_gy_data_rate_set(stmdev_ctx_t *ctx,
/* Check the Finite State Machine data rate constraints */
ret = lsm6dsr_fsm_enable_get(ctx, &fsm_enable);
- if (ret == 0) {
- if ( (fsm_enable.fsm_enable_a.fsm1_en |
- fsm_enable.fsm_enable_a.fsm2_en |
- fsm_enable.fsm_enable_a.fsm3_en |
- fsm_enable.fsm_enable_a.fsm4_en |
- fsm_enable.fsm_enable_a.fsm5_en |
- fsm_enable.fsm_enable_a.fsm6_en |
- fsm_enable.fsm_enable_a.fsm7_en |
- fsm_enable.fsm_enable_a.fsm8_en |
- fsm_enable.fsm_enable_b.fsm9_en |
- fsm_enable.fsm_enable_b.fsm10_en |
- fsm_enable.fsm_enable_b.fsm11_en |
- fsm_enable.fsm_enable_b.fsm12_en |
- fsm_enable.fsm_enable_b.fsm13_en |
- fsm_enable.fsm_enable_b.fsm14_en |
- fsm_enable.fsm_enable_b.fsm15_en |
- fsm_enable.fsm_enable_b.fsm16_en ) == PROPERTY_ENABLE ){
+ if (ret == 0)
+ {
+ if ((fsm_enable.fsm_enable_a.fsm1_en |
+ fsm_enable.fsm_enable_a.fsm2_en |
+ fsm_enable.fsm_enable_a.fsm3_en |
+ fsm_enable.fsm_enable_a.fsm4_en |
+ fsm_enable.fsm_enable_a.fsm5_en |
+ fsm_enable.fsm_enable_a.fsm6_en |
+ fsm_enable.fsm_enable_a.fsm7_en |
+ fsm_enable.fsm_enable_a.fsm8_en |
+ fsm_enable.fsm_enable_b.fsm9_en |
+ fsm_enable.fsm_enable_b.fsm10_en |
+ fsm_enable.fsm_enable_b.fsm11_en |
+ fsm_enable.fsm_enable_b.fsm12_en |
+ fsm_enable.fsm_enable_b.fsm13_en |
+ fsm_enable.fsm_enable_b.fsm14_en |
+ fsm_enable.fsm_enable_b.fsm15_en |
+ fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
+ {
ret = lsm6dsr_fsm_data_rate_get(ctx, &fsm_odr);
- if (ret == 0) {
- switch (fsm_odr) {
- case LSM6DSR_ODR_FSM_12Hz5:
- if (val == LSM6DSR_GY_ODR_OFF){
+ if (ret == 0)
+ {
+ switch (fsm_odr)
+ {
+ case LSM6DSR_ODR_FSM_12Hz5:
+ if (val == LSM6DSR_GY_ODR_OFF)
+ {
odr_gy = LSM6DSR_GY_ODR_12Hz5;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
- case LSM6DSR_ODR_FSM_26Hz:
- if (val == LSM6DSR_GY_ODR_OFF){
+ case LSM6DSR_ODR_FSM_26Hz:
+ if (val == LSM6DSR_GY_ODR_OFF)
+ {
odr_gy = LSM6DSR_GY_ODR_26Hz;
+ }
- } else if (val == LSM6DSR_GY_ODR_12Hz5){
+ else if (val == LSM6DSR_GY_ODR_12Hz5)
+ {
odr_gy = LSM6DSR_GY_ODR_26Hz;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
- case LSM6DSR_ODR_FSM_52Hz:
- if (val == LSM6DSR_GY_ODR_OFF){
+ case LSM6DSR_ODR_FSM_52Hz:
+ if (val == LSM6DSR_GY_ODR_OFF)
+ {
odr_gy = LSM6DSR_GY_ODR_52Hz;
+ }
- } else if (val == LSM6DSR_GY_ODR_12Hz5){
+ else if (val == LSM6DSR_GY_ODR_12Hz5)
+ {
odr_gy = LSM6DSR_GY_ODR_52Hz;
+ }
- } else if (val == LSM6DSR_GY_ODR_26Hz){
+ else if (val == LSM6DSR_GY_ODR_26Hz)
+ {
odr_gy = LSM6DSR_GY_ODR_52Hz;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
- case LSM6DSR_ODR_FSM_104Hz:
- if (val == LSM6DSR_GY_ODR_OFF){
+ case LSM6DSR_ODR_FSM_104Hz:
+ if (val == LSM6DSR_GY_ODR_OFF)
+ {
odr_gy = LSM6DSR_GY_ODR_104Hz;
+ }
- } else if (val == LSM6DSR_GY_ODR_12Hz5){
+ else if (val == LSM6DSR_GY_ODR_12Hz5)
+ {
odr_gy = LSM6DSR_GY_ODR_104Hz;
+ }
- } else if (val == LSM6DSR_GY_ODR_26Hz){
+ else if (val == LSM6DSR_GY_ODR_26Hz)
+ {
odr_gy = LSM6DSR_GY_ODR_104Hz;
+ }
- } else if (val == LSM6DSR_GY_ODR_52Hz){
+ else if (val == LSM6DSR_GY_ODR_52Hz)
+ {
odr_gy = LSM6DSR_GY_ODR_104Hz;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
+
default:
odr_gy = val;
break;
@@ -551,13 +664,18 @@ int32_t lsm6dsr_gy_data_rate_set(stmdev_ctx_t *ctx,
}
}
}
- if(ret == 0){
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
}
- if(ret == 0){
- ctrl2_g.odr_g= (uint8_t)odr_gy;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
+
+ if (ret == 0)
+ {
+ ctrl2_g.odr_g = (uint8_t)odr_gy;
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
}
+
return ret;
}
@@ -570,50 +688,64 @@ int32_t lsm6dsr_gy_data_rate_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_gy_data_rate_get(stmdev_ctx_t *ctx,
- lsm6dsr_odr_g_t *val)
+ lsm6dsr_odr_g_t *val)
{
lsm6dsr_ctrl2_g_t ctrl2_g;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- switch (ctrl2_g.odr_g){
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
+
+ switch (ctrl2_g.odr_g)
+ {
case LSM6DSR_GY_ODR_OFF:
*val = LSM6DSR_GY_ODR_OFF;
break;
+
case LSM6DSR_GY_ODR_12Hz5:
*val = LSM6DSR_GY_ODR_12Hz5;
break;
+
case LSM6DSR_GY_ODR_26Hz:
*val = LSM6DSR_GY_ODR_26Hz;
break;
+
case LSM6DSR_GY_ODR_52Hz:
*val = LSM6DSR_GY_ODR_52Hz;
break;
+
case LSM6DSR_GY_ODR_104Hz:
*val = LSM6DSR_GY_ODR_104Hz;
break;
+
case LSM6DSR_GY_ODR_208Hz:
*val = LSM6DSR_GY_ODR_208Hz;
break;
+
case LSM6DSR_GY_ODR_417Hz:
*val = LSM6DSR_GY_ODR_417Hz;
break;
+
case LSM6DSR_GY_ODR_833Hz:
*val = LSM6DSR_GY_ODR_833Hz;
break;
+
case LSM6DSR_GY_ODR_1667Hz:
*val = LSM6DSR_GY_ODR_1667Hz;
break;
+
case LSM6DSR_GY_ODR_3333Hz:
*val = LSM6DSR_GY_ODR_3333Hz;
break;
+
case LSM6DSR_GY_ODR_6667Hz:
*val = LSM6DSR_GY_ODR_6667Hz;
break;
+
default:
*val = LSM6DSR_GY_ODR_OFF;
break;
}
+
return ret;
}
@@ -630,11 +762,14 @@ int32_t lsm6dsr_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsr_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.bdu= (uint8_t)val;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.bdu = (uint8_t)val;
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -651,7 +786,7 @@ int32_t lsm6dsr_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsr_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.bdu;
return ret;
@@ -672,11 +807,14 @@ int32_t lsm6dsr_xl_offset_weight_set(stmdev_ctx_t *ctx,
lsm6dsr_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
- ctrl6_c.usr_off_w= (uint8_t)val;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl6_c.usr_off_w = (uint8_t)val;
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -690,24 +828,28 @@ int32_t lsm6dsr_xl_offset_weight_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_xl_offset_weight_get(stmdev_ctx_t *ctx,
- lsm6dsr_usr_off_w_t *val)
+ lsm6dsr_usr_off_w_t *val)
{
lsm6dsr_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
- switch (ctrl6_c.usr_off_w){
+ switch (ctrl6_c.usr_off_w)
+ {
case LSM6DSR_LSb_1mg:
*val = LSM6DSR_LSb_1mg;
break;
+
case LSM6DSR_LSb_16mg:
*val = LSM6DSR_LSb_16mg;
break;
+
default:
*val = LSM6DSR_LSb_1mg;
break;
}
+
return ret;
}
@@ -720,16 +862,19 @@ int32_t lsm6dsr_xl_offset_weight_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_xl_power_mode_set(stmdev_ctx_t *ctx,
- lsm6dsr_xl_hm_mode_t val)
+ lsm6dsr_xl_hm_mode_t val)
{
lsm6dsr_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -742,23 +887,28 @@ int32_t lsm6dsr_xl_power_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_xl_power_mode_get(stmdev_ctx_t *ctx,
- lsm6dsr_xl_hm_mode_t *val)
+ lsm6dsr_xl_hm_mode_t *val)
{
lsm6dsr_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- switch (ctrl6_c.xl_hm_mode){
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ switch (ctrl6_c.xl_hm_mode)
+ {
case LSM6DSR_HIGH_PERFORMANCE_MD:
*val = LSM6DSR_HIGH_PERFORMANCE_MD;
break;
+
case LSM6DSR_LOW_NORMAL_POWER_MD:
*val = LSM6DSR_LOW_NORMAL_POWER_MD;
break;
+
default:
*val = LSM6DSR_HIGH_PERFORMANCE_MD;
break;
}
+
return ret;
}
@@ -771,16 +921,19 @@ int32_t lsm6dsr_xl_power_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_gy_power_mode_set(stmdev_ctx_t *ctx,
- lsm6dsr_g_hm_mode_t val)
+ lsm6dsr_g_hm_mode_t val)
{
lsm6dsr_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
- ctrl7_g.g_hm_mode= (uint8_t)val;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
+ ctrl7_g.g_hm_mode = (uint8_t)val;
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
}
+
return ret;
}
@@ -793,23 +946,28 @@ int32_t lsm6dsr_gy_power_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_gy_power_mode_get(stmdev_ctx_t *ctx,
- lsm6dsr_g_hm_mode_t *val)
+ lsm6dsr_g_hm_mode_t *val)
{
lsm6dsr_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- switch (ctrl7_g.g_hm_mode){
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ switch (ctrl7_g.g_hm_mode)
+ {
case LSM6DSR_GY_HIGH_PERFORMANCE:
*val = LSM6DSR_GY_HIGH_PERFORMANCE;
break;
+
case LSM6DSR_GY_NORMAL:
*val = LSM6DSR_GY_NORMAL;
break;
+
default:
*val = LSM6DSR_GY_HIGH_PERFORMANCE;
break;
}
+
return ret;
}
@@ -824,44 +982,62 @@ int32_t lsm6dsr_gy_power_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_all_sources_get(stmdev_ctx_t *ctx,
- lsm6dsr_all_sources_t *val)
+ lsm6dsr_all_sources_t *val)
{
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_ALL_INT_SRC,
- (uint8_t*)&val->all_int_src, 1);
- if(ret == 0){
+ (uint8_t *)&val->all_int_src, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_SRC,
- (uint8_t*)&val->wake_up_src, 1);
+ (uint8_t *)&val->wake_up_src, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_SRC,
- (uint8_t*)&val->tap_src, 1);
+ (uint8_t *)&val->tap_src, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_D6D_SRC,
- (uint8_t*)&val->d6d_src, 1);
+ (uint8_t *)&val->d6d_src, 1);
}
- if(ret == 0){
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_REG,
- (uint8_t*)&val->status_reg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_REG,
+ (uint8_t *)&val->status_reg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_STATUS,
- (uint8_t*)&val->emb_func_status, 1);
+ (uint8_t *)&val->emb_func_status, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_STATUS_A,
- (uint8_t*)&val->fsm_status_a, 1);
+ (uint8_t *)&val->fsm_status_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_STATUS_B,
- (uint8_t*)&val->fsm_status_b, 1);
+ (uint8_t *)&val->fsm_status_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
@@ -877,10 +1053,12 @@ int32_t lsm6dsr_all_sources_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_status_reg_get(stmdev_ctx_t *ctx,
- lsm6dsr_status_reg_t *val)
+ lsm6dsr_status_reg_t *val)
{
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_REG, (uint8_t*) val, 1);
+
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_REG, (uint8_t *) val, 1);
+
return ret;
}
@@ -892,13 +1070,14 @@ int32_t lsm6dsr_status_reg_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsr_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsr_status_reg_t status_reg;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_REG,
- (uint8_t*)&status_reg, 1);
+ (uint8_t *)&status_reg, 1);
*val = status_reg.xlda;
return ret;
@@ -912,13 +1091,14 @@ int32_t lsm6dsr_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsr_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsr_status_reg_t status_reg;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_REG,
- (uint8_t*)&status_reg, 1);
+ (uint8_t *)&status_reg, 1);
*val = status_reg.gda;
return ret;
@@ -932,13 +1112,14 @@ int32_t lsm6dsr_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsr_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsr_status_reg_t status_reg;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_REG,
- (uint8_t*)&status_reg, 1);
+ (uint8_t *)&status_reg, 1);
*val = status_reg.tda;
return ret;
@@ -957,7 +1138,9 @@ int32_t lsm6dsr_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t lsm6dsr_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsr_write_reg(ctx, LSM6DSR_X_OFS_USR, buff, 1);
+
return ret;
}
@@ -974,7 +1157,9 @@ int32_t lsm6dsr_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lsm6dsr_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsr_read_reg(ctx, LSM6DSR_X_OFS_USR, buff, 1);
+
return ret;
}
@@ -991,7 +1176,9 @@ int32_t lsm6dsr_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lsm6dsr_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsr_write_reg(ctx, LSM6DSR_Y_OFS_USR, buff, 1);
+
return ret;
}
@@ -1008,7 +1195,9 @@ int32_t lsm6dsr_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lsm6dsr_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsr_read_reg(ctx, LSM6DSR_Y_OFS_USR, buff, 1);
+
return ret;
}
@@ -1025,7 +1214,9 @@ int32_t lsm6dsr_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lsm6dsr_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsr_write_reg(ctx, LSM6DSR_Z_OFS_USR, buff, 1);
+
return ret;
}
@@ -1042,7 +1233,9 @@ int32_t lsm6dsr_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lsm6dsr_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsr_read_reg(ctx, LSM6DSR_Z_OFS_USR, buff, 1);
+
return ret;
}
@@ -1059,11 +1252,14 @@ int32_t lsm6dsr_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsr_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
- ctrl7_g.usr_off_on_out= (uint8_t)val;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
+ ctrl7_g.usr_off_on_out = (uint8_t)val;
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
}
+
return ret;
}
@@ -1080,7 +1276,7 @@ int32_t lsm6dsr_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsr_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
*val = ctrl7_g.usr_off_on_out;
return ret;
@@ -1109,7 +1305,6 @@ int32_t lsm6dsr_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t lsm6dsr_timestamp_rst(stmdev_ctx_t *ctx)
{
uint8_t rst_val = 0xAA;
-
return lsm6dsr_write_reg(ctx, LSM6DSR_TIMESTAMP2, &rst_val, 1);
}
@@ -1126,12 +1321,15 @@ int32_t lsm6dsr_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsr_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
- ctrl10_c.timestamp_en= (uint8_t)val;
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl10_c.timestamp_en = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL10_C,
- (uint8_t*)&ctrl10_c, 1);
+ (uint8_t *)&ctrl10_c, 1);
}
+
return ret;
}
@@ -1148,7 +1346,7 @@ int32_t lsm6dsr_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsr_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
*val = ctrl10_c.timestamp_en;
return ret;
@@ -1164,10 +1362,17 @@ int32_t lsm6dsr_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_timestamp_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsr_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val)
{
+ uint8_t buff[4];
int32_t ret;
+
ret = lsm6dsr_read_reg(ctx, LSM6DSR_TIMESTAMP0, buff, 4);
+ *val = buff[3];
+ *val = (*val * 256U) + buff[2];
+ *val = (*val * 256U) + buff[1];
+ *val = (*val * 256U) + buff[0];
+
return ret;
}
@@ -1192,16 +1397,19 @@ int32_t lsm6dsr_timestamp_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
*/
int32_t lsm6dsr_rounding_mode_set(stmdev_ctx_t *ctx,
- lsm6dsr_rounding_t val)
+ lsm6dsr_rounding_t val)
{
lsm6dsr_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
- ctrl5_c.rounding= (uint8_t)val;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl5_c.rounding = (uint8_t)val;
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -1214,29 +1422,36 @@ int32_t lsm6dsr_rounding_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_rounding_mode_get(stmdev_ctx_t *ctx,
- lsm6dsr_rounding_t *val)
+ lsm6dsr_rounding_t *val)
{
lsm6dsr_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- switch (ctrl5_c.rounding){
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ switch (ctrl5_c.rounding)
+ {
case LSM6DSR_NO_ROUND:
*val = LSM6DSR_NO_ROUND;
break;
+
case LSM6DSR_ROUND_XL:
*val = LSM6DSR_ROUND_XL;
break;
+
case LSM6DSR_ROUND_GY:
*val = LSM6DSR_ROUND_GY;
break;
+
case LSM6DSR_ROUND_GY_XL:
*val = LSM6DSR_ROUND_GY_XL;
break;
+
default:
*val = LSM6DSR_NO_ROUND;
break;
}
+
return ret;
}
@@ -1250,10 +1465,15 @@ int32_t lsm6dsr_rounding_mode_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsr_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
+
ret = lsm6dsr_read_reg(ctx, LSM6DSR_OUT_TEMP_L, buff, 2);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+
return ret;
}
@@ -1266,10 +1486,19 @@ int32_t lsm6dsr_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsr_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lsm6dsr_read_reg(ctx, LSM6DSR_OUTX_L_G, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -1282,10 +1511,19 @@ int32_t lsm6dsr_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsr_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lsm6dsr_read_reg(ctx, LSM6DSR_OUTX_L_A, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -1300,7 +1538,9 @@ int32_t lsm6dsr_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lsm6dsr_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_DATA_OUT_X_L, buff, 6);
+
return ret;
}
@@ -1312,15 +1552,22 @@ int32_t lsm6dsr_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_number_of_steps_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsr_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_STEP_COUNTER_L, buff, 2);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
@@ -1340,18 +1587,25 @@ int32_t lsm6dsr_steps_reset(stmdev_ctx_t *ctx)
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_SRC,
- (uint8_t*)&emb_func_src, 1);
+ (uint8_t *)&emb_func_src, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
emb_func_src.pedo_rst_step = PROPERTY_ENABLE;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_SRC,
- (uint8_t*)&emb_func_src, 1);
+ (uint8_t *)&emb_func_src, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -1362,7 +1616,7 @@ int32_t lsm6dsr_steps_reset(stmdev_ctx_t *ctx)
/**
* @defgroup LSM6DSR_common
- * @brief This section groups common usefull functions.
+ * @brief This section groups common useful functions.
* @{
*
*/
@@ -1383,12 +1637,15 @@ int32_t lsm6dsr_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_INTERNAL_FREQ_FINE,
- (uint8_t*)&internal_freq_fine, 1);
- if(ret == 0){
- internal_freq_fine.freq_fine= (uint8_t)val;
+ (uint8_t *)&internal_freq_fine, 1);
+
+ if (ret == 0)
+ {
+ internal_freq_fine.freq_fine = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_INTERNAL_FREQ_FINE,
- (uint8_t*)&internal_freq_fine, 1);
+ (uint8_t *)&internal_freq_fine, 1);
}
+
return ret;
}
@@ -1408,7 +1665,7 @@ int32_t lsm6dsr_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_INTERNAL_FREQ_FINE,
- (uint8_t*)&internal_freq_fine, 1);
+ (uint8_t *)&internal_freq_fine, 1);
*val = internal_freq_fine.freq_fine;
return ret;
@@ -1424,18 +1681,21 @@ int32_t lsm6dsr_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsr_mem_bank_set(stmdev_ctx_t *ctx,
- lsm6dsr_reg_access_t val)
+ lsm6dsr_reg_access_t val)
{
lsm6dsr_func_cfg_access_t func_cfg_access;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
- if(ret == 0){
- func_cfg_access.reg_access= (uint8_t)val;
+ (uint8_t *)&func_cfg_access, 1);
+
+ if (ret == 0)
+ {
+ func_cfg_access.reg_access = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
+ (uint8_t *)&func_cfg_access, 1);
}
+
return ret;
}
@@ -1449,27 +1709,33 @@ int32_t lsm6dsr_mem_bank_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_mem_bank_get(stmdev_ctx_t *ctx,
- lsm6dsr_reg_access_t *val)
+ lsm6dsr_reg_access_t *val)
{
lsm6dsr_func_cfg_access_t func_cfg_access;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
- switch (func_cfg_access.reg_access){
+ (uint8_t *)&func_cfg_access, 1);
+
+ switch (func_cfg_access.reg_access)
+ {
case LSM6DSR_USER_BANK:
*val = LSM6DSR_USER_BANK;
break;
+
case LSM6DSR_SENSOR_HUB_BANK:
*val = LSM6DSR_SENSOR_HUB_BANK;
break;
+
case LSM6DSR_EMBEDDED_FUNC_BANK:
*val = LSM6DSR_EMBEDDED_FUNC_BANK;
break;
+
default:
*val = LSM6DSR_USER_BANK;
break;
}
+
return ret;
}
@@ -1483,7 +1749,7 @@ int32_t lsm6dsr_mem_bank_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t add,
- uint8_t *val)
+ uint8_t *val)
{
lsm6dsr_page_rw_t page_rw;
lsm6dsr_page_sel_t page_sel;
@@ -1491,40 +1757,59 @@ int32_t lsm6dsr_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t add,
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t*)&page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x02U; /* page_write enable */
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t*)&page_rw, 1);
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_SEL, (uint8_t*)&page_sel, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_SEL, (uint8_t *)&page_sel, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_sel.page_sel = (uint8_t)((add >> 8) & 0x0FU);
page_sel.not_used_01 = 1;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
+ (uint8_t *)&page_sel, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_address.page_addr = (uint8_t)(add & 0xFFU);
ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_ADDRESS,
- (uint8_t*)&page_address, 1);
+ (uint8_t *)&page_address, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_VALUE, val, 1);
}
- if(ret == 0){
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t*)&page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x00; /* page_write disable */
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t*)&page_rw, 1);
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -1534,82 +1819,108 @@ int32_t lsm6dsr_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t add,
* @param ctx Read / write interface definitions.(ptr)
* @param buf Page line address.(ptr)
* @param val Value to write.
- * @param len buffer lengh.
+ * @param len buffer length.
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
int32_t lsm6dsr_ln_pg_write(stmdev_ctx_t *ctx, uint16_t add,
- uint8_t *buf, uint8_t len)
+ uint8_t *buf, uint8_t len)
{
lsm6dsr_page_rw_t page_rw;
lsm6dsr_page_sel_t page_sel;
lsm6dsr_page_address_t page_address;
int32_t ret;
+
uint8_t msb, lsb;
uint8_t i ;
-
msb = (uint8_t)((add >> 8) & 0x0FU);
lsb = (uint8_t)(add & 0xFFU);
-
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t*)&page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x02U; /* page_write enable*/
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t*)&page_rw, 1);
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_SEL, (uint8_t*)&page_sel, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_SEL, (uint8_t *)&page_sel, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_sel.page_sel = msb;
page_sel.not_used_01 = 1;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
+ (uint8_t *)&page_sel, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_address.page_addr = lsb;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_ADDRESS,
- (uint8_t*)&page_address, 1);
+ (uint8_t *)&page_address, 1);
}
- for (i = 0; i < len; i++){
- if(ret == 0){
+
+ for (i = 0; i < len; i++)
+ {
+ if (ret == 0)
+ {
ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_VALUE, &buf[i], 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
/* Check if page wrap */
- if (lsb == 0x00U){
+ if (lsb == 0x00U)
+ {
msb++;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
+ (uint8_t *)&page_sel, 1);
}
+
lsb++;
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_sel.page_sel = msb;
page_sel.not_used_01 = 1;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
+ (uint8_t *)&page_sel, 1);
}
}
}
- if(ret == 0){
+ if (ret == 0)
+ {
page_sel.page_sel = 0;
page_sel.not_used_01 = 1;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
+ (uint8_t *)&page_sel, 1);
}
- if(ret == 0){
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t*)&page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x00U; /* page_write disable */
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t*)&page_rw, 1);
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -1623,7 +1934,7 @@ int32_t lsm6dsr_ln_pg_write(stmdev_ctx_t *ctx, uint16_t add,
*
*/
int32_t lsm6dsr_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add,
- uint8_t *val)
+ uint8_t *val)
{
lsm6dsr_page_rw_t page_rw;
lsm6dsr_page_sel_t page_sel;
@@ -1631,40 +1942,59 @@ int32_t lsm6dsr_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add,
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t*)&page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x01U; /* page_read enable*/
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t*)&page_rw, 1);
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_SEL, (uint8_t*)&page_sel, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_SEL, (uint8_t *)&page_sel, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_sel.page_sel = (uint8_t)((add >> 8) & 0x0FU);
page_sel.not_used_01 = 1;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
+ (uint8_t *)&page_sel, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_address.page_addr = (uint8_t)(add & 0x00FFU);
ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_ADDRESS,
- (uint8_t*)&page_address, 1);
+ (uint8_t *)&page_address, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_VALUE, val, 2);
}
- if(ret == 0){
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t*)&page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x00U; /* page_read disable */
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t*)&page_rw, 1);
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -1678,18 +2008,21 @@ int32_t lsm6dsr_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add,
*
*/
int32_t lsm6dsr_data_ready_mode_set(stmdev_ctx_t *ctx,
- lsm6dsr_dataready_pulsed_t val)
+ lsm6dsr_dataready_pulsed_t val)
{
lsm6dsr_counter_bdr_reg1_t counter_bdr_reg1;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if(ret == 0){
- counter_bdr_reg1.dataready_pulsed= (uint8_t)val;
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
+ counter_bdr_reg1.dataready_pulsed = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
}
+
return ret;
}
@@ -1703,24 +2036,29 @@ int32_t lsm6dsr_data_ready_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_data_ready_mode_get(stmdev_ctx_t *ctx,
- lsm6dsr_dataready_pulsed_t *val)
+ lsm6dsr_dataready_pulsed_t *val)
{
lsm6dsr_counter_bdr_reg1_t counter_bdr_reg1;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- switch (counter_bdr_reg1.dataready_pulsed){
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ switch (counter_bdr_reg1.dataready_pulsed)
+ {
case LSM6DSR_DRDY_LATCHED:
*val = LSM6DSR_DRDY_LATCHED;
break;
+
case LSM6DSR_DRDY_PULSED:
*val = LSM6DSR_DRDY_PULSED;
break;
+
default:
*val = LSM6DSR_DRDY_LATCHED;
break;
}
+
return ret;
}
@@ -1735,7 +2073,9 @@ int32_t lsm6dsr_data_ready_mode_get(stmdev_ctx_t *ctx,
int32_t lsm6dsr_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsr_read_reg(ctx, LSM6DSR_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -1752,11 +2092,14 @@ int32_t lsm6dsr_reset_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsr_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.sw_reset= (uint8_t)val;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.sw_reset = (uint8_t)val;
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1773,7 +2116,7 @@ int32_t lsm6dsr_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsr_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.sw_reset;
return ret;
@@ -1793,11 +2136,14 @@ int32_t lsm6dsr_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsr_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.if_inc= (uint8_t)val;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.if_inc = (uint8_t)val;
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1815,7 +2161,7 @@ int32_t lsm6dsr_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsr_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.if_inc;
return ret;
@@ -1834,11 +2180,14 @@ int32_t lsm6dsr_boot_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsr_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.boot= (uint8_t)val;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.boot = (uint8_t)val;
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1855,7 +2204,7 @@ int32_t lsm6dsr_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsr_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.boot;
return ret;
@@ -1872,16 +2221,19 @@ int32_t lsm6dsr_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsr_xl_self_test_set(stmdev_ctx_t *ctx,
- lsm6dsr_st_xl_t val)
+ lsm6dsr_st_xl_t val)
{
lsm6dsr_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
- ctrl5_c.st_xl= (uint8_t)val;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl5_c.st_xl = (uint8_t)val;
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -1894,27 +2246,32 @@ int32_t lsm6dsr_xl_self_test_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_xl_self_test_get(stmdev_ctx_t *ctx,
- lsm6dsr_st_xl_t *val)
+ lsm6dsr_st_xl_t *val)
{
lsm6dsr_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
- switch (ctrl5_c.st_xl){
+ switch (ctrl5_c.st_xl)
+ {
case LSM6DSR_XL_ST_DISABLE:
*val = LSM6DSR_XL_ST_DISABLE;
break;
+
case LSM6DSR_XL_ST_POSITIVE:
*val = LSM6DSR_XL_ST_POSITIVE;
break;
+
case LSM6DSR_XL_ST_NEGATIVE:
*val = LSM6DSR_XL_ST_NEGATIVE;
break;
+
default:
*val = LSM6DSR_XL_ST_DISABLE;
break;
}
+
return ret;
}
@@ -1927,16 +2284,19 @@ int32_t lsm6dsr_xl_self_test_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_gy_self_test_set(stmdev_ctx_t *ctx,
- lsm6dsr_st_g_t val)
+ lsm6dsr_st_g_t val)
{
lsm6dsr_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
- ctrl5_c.st_g= (uint8_t)val;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl5_c.st_g = (uint8_t)val;
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -1949,27 +2309,32 @@ int32_t lsm6dsr_gy_self_test_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_gy_self_test_get(stmdev_ctx_t *ctx,
- lsm6dsr_st_g_t *val)
+ lsm6dsr_st_g_t *val)
{
lsm6dsr_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
- switch (ctrl5_c.st_g){
+ switch (ctrl5_c.st_g)
+ {
case LSM6DSR_GY_ST_DISABLE:
*val = LSM6DSR_GY_ST_DISABLE;
break;
+
case LSM6DSR_GY_ST_POSITIVE:
*val = LSM6DSR_GY_ST_POSITIVE;
break;
+
case LSM6DSR_GY_ST_NEGATIVE:
*val = LSM6DSR_GY_ST_NEGATIVE;
break;
+
default:
*val = LSM6DSR_GY_ST_DISABLE;
break;
}
+
return ret;
}
@@ -1999,12 +2364,15 @@ int32_t lsm6dsr_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsr_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
- ctrl1_xl.lpf2_xl_en= (uint8_t)val;
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl1_xl.lpf2_xl_en = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
+ (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -2021,7 +2389,7 @@ int32_t lsm6dsr_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsr_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
*val = ctrl1_xl.lpf2_xl_en;
return ret;
@@ -2041,11 +2409,14 @@ int32_t lsm6dsr_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsr_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ctrl4_c.lpf1_sel_g= (uint8_t)val;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl4_c.lpf1_sel_g = (uint8_t)val;
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -2063,7 +2434,7 @@ int32_t lsm6dsr_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsr_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.lpf1_sel_g;
return ret;
@@ -2078,16 +2449,20 @@ int32_t lsm6dsr_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dsr_filter_settling_mask_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dsr_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ctrl4_c.drdy_mask= (uint8_t)val;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl4_c.drdy_mask = (uint8_t)val;
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -2101,12 +2476,12 @@ int32_t lsm6dsr_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val)
*
*/
int32_t lsm6dsr_filter_settling_mask_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
lsm6dsr_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.drdy_mask;
return ret;
@@ -2121,16 +2496,19 @@ int32_t lsm6dsr_filter_settling_mask_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
- lsm6dsr_ftype_t val)
+ lsm6dsr_ftype_t val)
{
lsm6dsr_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
- ctrl6_c.ftype= (uint8_t)val;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl6_c.ftype = (uint8_t)val;
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -2143,42 +2521,52 @@ int32_t lsm6dsr_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
- lsm6dsr_ftype_t *val)
+ lsm6dsr_ftype_t *val)
{
lsm6dsr_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
- switch (ctrl6_c.ftype){
+ switch (ctrl6_c.ftype)
+ {
case LSM6DSR_ULTRA_LIGHT:
*val = LSM6DSR_ULTRA_LIGHT;
break;
+
case LSM6DSR_VERY_LIGHT:
*val = LSM6DSR_VERY_LIGHT;
break;
+
case LSM6DSR_LIGHT:
*val = LSM6DSR_LIGHT;
break;
+
case LSM6DSR_MEDIUM:
*val = LSM6DSR_MEDIUM;
break;
+
case LSM6DSR_STRONG:
*val = LSM6DSR_STRONG;
break;
+
case LSM6DSR_VERY_STRONG:
*val = LSM6DSR_VERY_STRONG;
break;
+
case LSM6DSR_AGGRESSIVE:
*val = LSM6DSR_AGGRESSIVE;
break;
+
case LSM6DSR_XTREME:
*val = LSM6DSR_XTREME;
break;
+
default:
*val = LSM6DSR_ULTRA_LIGHT;
break;
}
+
return ret;
}
@@ -2195,12 +2583,15 @@ int32_t lsm6dsr_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsr_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
- ctrl8_xl.low_pass_on_6d= (uint8_t)val;
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl8_xl.low_pass_on_6d = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL8_XL,
- (uint8_t*)&ctrl8_xl, 1);
+ (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -2217,7 +2608,7 @@ int32_t lsm6dsr_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsr_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
*val = ctrl8_xl.low_pass_on_6d;
return ret;
@@ -2233,19 +2624,22 @@ int32_t lsm6dsr_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsr_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
- lsm6dsr_hp_slope_xl_en_t val)
+ lsm6dsr_hp_slope_xl_en_t val)
{
lsm6dsr_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
ctrl8_xl.hp_slope_xl_en = (((uint8_t)val & 0x10U) >> 4);
ctrl8_xl.hp_ref_mode_xl = (((uint8_t)val & 0x20U) >> 5);
ctrl8_xl.hpcf_xl = (uint8_t)val & 0x07U;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL8_XL,
- (uint8_t*)&ctrl8_xl, 1);
+ (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -2259,87 +2653,114 @@ int32_t lsm6dsr_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
- lsm6dsr_hp_slope_xl_en_t *val)
+ lsm6dsr_hp_slope_xl_en_t *val)
{
lsm6dsr_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- switch (( (ctrl8_xl.hp_ref_mode_xl << 5) +(ctrl8_xl.hp_slope_xl_en << 4) +
- ctrl8_xl.hpcf_xl )){
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ switch (((ctrl8_xl.hp_ref_mode_xl << 5) + (ctrl8_xl.hp_slope_xl_en <<
+ 4) +
+ ctrl8_xl.hpcf_xl))
+ {
case LSM6DSR_HP_PATH_DISABLE_ON_OUT:
*val = LSM6DSR_HP_PATH_DISABLE_ON_OUT;
break;
+
case LSM6DSR_SLOPE_ODR_DIV_4:
*val = LSM6DSR_SLOPE_ODR_DIV_4;
break;
+
case LSM6DSR_HP_ODR_DIV_10:
*val = LSM6DSR_HP_ODR_DIV_10;
break;
+
case LSM6DSR_HP_ODR_DIV_20:
*val = LSM6DSR_HP_ODR_DIV_20;
break;
+
case LSM6DSR_HP_ODR_DIV_45:
*val = LSM6DSR_HP_ODR_DIV_45;
break;
+
case LSM6DSR_HP_ODR_DIV_100:
*val = LSM6DSR_HP_ODR_DIV_100;
break;
+
case LSM6DSR_HP_ODR_DIV_200:
*val = LSM6DSR_HP_ODR_DIV_200;
break;
+
case LSM6DSR_HP_ODR_DIV_400:
*val = LSM6DSR_HP_ODR_DIV_400;
break;
+
case LSM6DSR_HP_ODR_DIV_800:
*val = LSM6DSR_HP_ODR_DIV_800;
break;
+
case LSM6DSR_HP_REF_MD_ODR_DIV_10:
*val = LSM6DSR_HP_REF_MD_ODR_DIV_10;
break;
+
case LSM6DSR_HP_REF_MD_ODR_DIV_20:
*val = LSM6DSR_HP_REF_MD_ODR_DIV_20;
break;
+
case LSM6DSR_HP_REF_MD_ODR_DIV_45:
*val = LSM6DSR_HP_REF_MD_ODR_DIV_45;
break;
+
case LSM6DSR_HP_REF_MD_ODR_DIV_100:
*val = LSM6DSR_HP_REF_MD_ODR_DIV_100;
break;
+
case LSM6DSR_HP_REF_MD_ODR_DIV_200:
*val = LSM6DSR_HP_REF_MD_ODR_DIV_200;
break;
+
case LSM6DSR_HP_REF_MD_ODR_DIV_400:
*val = LSM6DSR_HP_REF_MD_ODR_DIV_400;
break;
+
case LSM6DSR_HP_REF_MD_ODR_DIV_800:
*val = LSM6DSR_HP_REF_MD_ODR_DIV_800;
break;
+
case LSM6DSR_LP_ODR_DIV_10:
*val = LSM6DSR_LP_ODR_DIV_10;
break;
+
case LSM6DSR_LP_ODR_DIV_20:
*val = LSM6DSR_LP_ODR_DIV_20;
break;
+
case LSM6DSR_LP_ODR_DIV_45:
*val = LSM6DSR_LP_ODR_DIV_45;
break;
+
case LSM6DSR_LP_ODR_DIV_100:
*val = LSM6DSR_LP_ODR_DIV_100;
break;
+
case LSM6DSR_LP_ODR_DIV_200:
*val = LSM6DSR_LP_ODR_DIV_200;
break;
+
case LSM6DSR_LP_ODR_DIV_400:
*val = LSM6DSR_LP_ODR_DIV_400;
break;
+
case LSM6DSR_LP_ODR_DIV_800:
*val = LSM6DSR_LP_ODR_DIV_800;
break;
+
default:
*val = LSM6DSR_HP_PATH_DISABLE_ON_OUT;
break;
}
+
return ret;
}
@@ -2358,12 +2779,15 @@ int32_t lsm6dsr_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsr_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
- ctrl8_xl.fastsettl_mode_xl= (uint8_t)val;
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl8_xl.fastsettl_mode_xl = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL8_XL,
- (uint8_t*)&ctrl8_xl, 1);
+ (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -2382,7 +2806,7 @@ int32_t lsm6dsr_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsr_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
*val = ctrl8_xl.fastsettl_mode_xl;
return ret;
@@ -2398,17 +2822,20 @@ int32_t lsm6dsr_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsr_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
- lsm6dsr_slope_fds_t val)
+ lsm6dsr_slope_fds_t val)
{
lsm6dsr_tap_cfg0_t tap_cfg0;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
- if(ret == 0){
- tap_cfg0.slope_fds= (uint8_t)val;
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
+
+ if (ret == 0)
+ {
+ tap_cfg0.slope_fds = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG0,
- (uint8_t*)&tap_cfg0, 1);
+ (uint8_t *)&tap_cfg0, 1);
}
+
return ret;
}
@@ -2422,23 +2849,28 @@ int32_t lsm6dsr_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
- lsm6dsr_slope_fds_t *val)
+ lsm6dsr_slope_fds_t *val)
{
lsm6dsr_tap_cfg0_t tap_cfg0;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
- switch (tap_cfg0.slope_fds){
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
+
+ switch (tap_cfg0.slope_fds)
+ {
case LSM6DSR_USE_SLOPE:
*val = LSM6DSR_USE_SLOPE;
break;
+
case LSM6DSR_USE_HPF:
*val = LSM6DSR_USE_HPF;
break;
+
default:
*val = LSM6DSR_USE_SLOPE;
break;
}
+
return ret;
}
@@ -2452,17 +2884,20 @@ int32_t lsm6dsr_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
- lsm6dsr_hpm_g_t val)
+ lsm6dsr_hpm_g_t val)
{
lsm6dsr_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
ctrl7_g.hp_en_g = (((uint8_t)val & 0x80U) >> 7);
ctrl7_g.hpm_g = (uint8_t)val & 0x03U;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
}
+
return ret;
}
@@ -2476,33 +2911,40 @@ int32_t lsm6dsr_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
- lsm6dsr_hpm_g_t *val)
+ lsm6dsr_hpm_g_t *val)
{
lsm6dsr_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
- switch ((ctrl7_g.hp_en_g << 7) + ctrl7_g.hpm_g){
+ switch ((ctrl7_g.hp_en_g << 7) + ctrl7_g.hpm_g)
+ {
case LSM6DSR_HP_FILTER_NONE:
*val = LSM6DSR_HP_FILTER_NONE;
break;
+
case LSM6DSR_HP_FILTER_16mHz:
*val = LSM6DSR_HP_FILTER_16mHz;
break;
+
case LSM6DSR_HP_FILTER_65mHz:
*val = LSM6DSR_HP_FILTER_65mHz;
break;
+
case LSM6DSR_HP_FILTER_260mHz:
*val = LSM6DSR_HP_FILTER_260mHz;
break;
+
case LSM6DSR_HP_FILTER_1Hz04:
*val = LSM6DSR_HP_FILTER_1Hz04;
break;
+
default:
*val = LSM6DSR_HP_FILTER_NONE;
break;
}
+
return ret;
}
@@ -2529,17 +2971,20 @@ int32_t lsm6dsr_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx,
- lsm6dsr_ois_pu_dis_t val)
+ lsm6dsr_ois_pu_dis_t val)
{
lsm6dsr_pin_ctrl_t pin_ctrl;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
- if(ret == 0){
- pin_ctrl.ois_pu_dis= (uint8_t)val;
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
+
+ if (ret == 0)
+ {
+ pin_ctrl.ois_pu_dis = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_PIN_CTRL,
- (uint8_t*)&pin_ctrl, 1);
+ (uint8_t *)&pin_ctrl, 1);
}
+
return ret;
}
@@ -2553,24 +2998,28 @@ int32_t lsm6dsr_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx,
- lsm6dsr_ois_pu_dis_t *val)
+ lsm6dsr_ois_pu_dis_t *val)
{
lsm6dsr_pin_ctrl_t pin_ctrl;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
- switch (pin_ctrl.ois_pu_dis){
+ switch (pin_ctrl.ois_pu_dis)
+ {
case LSM6DSR_AUX_PULL_UP_DISC:
*val = LSM6DSR_AUX_PULL_UP_DISC;
break;
+
case LSM6DSR_AUX_PULL_UP_CONNECT:
*val = LSM6DSR_AUX_PULL_UP_CONNECT;
break;
+
default:
*val = LSM6DSR_AUX_PULL_UP_DISC;
break;
}
+
return ret;
}
@@ -2583,17 +3032,20 @@ int32_t lsm6dsr_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx,
- lsm6dsr_ois_on_t val)
+ lsm6dsr_ois_on_t val)
{
lsm6dsr_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
ctrl7_g.ois_on_en = (uint8_t)val & 0x01U;
ctrl7_g.ois_on = (uint8_t)val & 0x01U;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
}
+
return ret;
}
@@ -2606,24 +3058,28 @@ int32_t lsm6dsr_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx,
- lsm6dsr_ois_on_t *val)
+ lsm6dsr_ois_on_t *val)
{
lsm6dsr_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
- switch (ctrl7_g.ois_on){
+ switch (ctrl7_g.ois_on)
+ {
case LSM6DSR_AUX_ON:
*val = LSM6DSR_AUX_ON;
break;
+
case LSM6DSR_AUX_ON_BY_AUX_INTERFACE:
*val = LSM6DSR_AUX_ON_BY_AUX_INTERFACE;
break;
+
default:
*val = LSM6DSR_AUX_ON;
break;
}
+
return ret;
}
@@ -2636,10 +3092,12 @@ int32_t lsm6dsr_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_aux_status_reg_get(stmdev_ctx_t *ctx,
- lsm6dsr_status_spiaux_t *val)
+ lsm6dsr_status_spiaux_t *val)
{
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_SPIAUX, (uint8_t*)val, 1);
+
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_SPIAUX, (uint8_t *)val, 1);
+
return ret;
}
@@ -2652,13 +3110,13 @@ int32_t lsm6dsr_aux_status_reg_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
lsm6dsr_status_spiaux_t status_spiaux;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_SPIAUX,
- (uint8_t*)&status_spiaux, 1);
+ (uint8_t *)&status_spiaux, 1);
*val = status_spiaux.xlda;
return ret;
@@ -2673,13 +3131,13 @@ int32_t lsm6dsr_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
lsm6dsr_status_spiaux_t status_spiaux;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_SPIAUX,
- (uint8_t*)&status_spiaux, 1);
+ (uint8_t *)&status_spiaux, 1);
*val = status_spiaux.gda;
return ret;
@@ -2693,13 +3151,14 @@ int32_t lsm6dsr_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsr_aux_gy_flag_settling_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsr_status_spiaux_t status_spiaux;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_SPIAUX,
- (uint8_t*)&status_spiaux, 1);
+ (uint8_t *)&status_spiaux, 1);
*val = status_spiaux.gyro_settling;
return ret;
@@ -2715,16 +3174,19 @@ int32_t lsm6dsr_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsr_aux_xl_self_test_set(stmdev_ctx_t *ctx,
- lsm6dsr_st_xl_ois_t val)
+ lsm6dsr_st_xl_ois_t val)
{
lsm6dsr_int_ois_t int_ois;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS, (uint8_t*)&int_ois, 1);
- if(ret == 0){
- int_ois.st_xl_ois= (uint8_t)val;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT_OIS, (uint8_t*)&int_ois, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS, (uint8_t *)&int_ois, 1);
+
+ if (ret == 0)
+ {
+ int_ois.st_xl_ois = (uint8_t)val;
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT_OIS, (uint8_t *)&int_ois, 1);
}
+
return ret;
}
@@ -2738,27 +3200,32 @@ int32_t lsm6dsr_aux_xl_self_test_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_aux_xl_self_test_get(stmdev_ctx_t *ctx,
- lsm6dsr_st_xl_ois_t *val)
+ lsm6dsr_st_xl_ois_t *val)
{
lsm6dsr_int_ois_t int_ois;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS, (uint8_t*)&int_ois, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS, (uint8_t *)&int_ois, 1);
- switch (int_ois.st_xl_ois){
+ switch (int_ois.st_xl_ois)
+ {
case LSM6DSR_AUX_XL_DISABLE:
*val = LSM6DSR_AUX_XL_DISABLE;
break;
+
case LSM6DSR_AUX_XL_POS:
*val = LSM6DSR_AUX_XL_POS;
break;
+
case LSM6DSR_AUX_XL_NEG:
*val = LSM6DSR_AUX_XL_NEG;
break;
+
default:
*val = LSM6DSR_AUX_XL_DISABLE;
break;
}
+
return ret;
}
@@ -2771,16 +3238,19 @@ int32_t lsm6dsr_aux_xl_self_test_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_aux_den_polarity_set(stmdev_ctx_t *ctx,
- lsm6dsr_den_lh_ois_t val)
+ lsm6dsr_den_lh_ois_t val)
{
lsm6dsr_int_ois_t int_ois;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS, (uint8_t*)&int_ois, 1);
- if(ret == 0){
- int_ois.den_lh_ois= (uint8_t)val;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT_OIS, (uint8_t*)&int_ois, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS, (uint8_t *)&int_ois, 1);
+
+ if (ret == 0)
+ {
+ int_ois.den_lh_ois = (uint8_t)val;
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT_OIS, (uint8_t *)&int_ois, 1);
}
+
return ret;
}
@@ -2793,24 +3263,28 @@ int32_t lsm6dsr_aux_den_polarity_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_aux_den_polarity_get(stmdev_ctx_t *ctx,
- lsm6dsr_den_lh_ois_t *val)
+ lsm6dsr_den_lh_ois_t *val)
{
lsm6dsr_int_ois_t int_ois;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS, (uint8_t*)&int_ois, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS, (uint8_t *)&int_ois, 1);
- switch (int_ois.den_lh_ois){
+ switch (int_ois.den_lh_ois)
+ {
case LSM6DSR_AUX_DEN_ACTIVE_LOW:
*val = LSM6DSR_AUX_DEN_ACTIVE_LOW;
break;
+
case LSM6DSR_AUX_DEN_ACTIVE_HIGH:
*val = LSM6DSR_AUX_DEN_ACTIVE_HIGH;
break;
+
default:
*val = LSM6DSR_AUX_DEN_ACTIVE_LOW;
break;
}
+
return ret;
}
@@ -2823,26 +3297,33 @@ int32_t lsm6dsr_aux_den_polarity_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_aux_den_mode_set(stmdev_ctx_t *ctx,
- lsm6dsr_lvl2_ois_t val)
+ lsm6dsr_lvl2_ois_t val)
{
lsm6dsr_int_ois_t int_ois;
lsm6dsr_ctrl1_ois_t ctrl1_ois;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS, (uint8_t*)&int_ois, 1);
- if(ret == 0){
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS, (uint8_t *)&int_ois, 1);
+
+ if (ret == 0)
+ {
int_ois.lvl2_ois = (uint8_t)val & 0x01U;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT_OIS, (uint8_t*)&int_ois, 1);
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT_OIS, (uint8_t *)&int_ois, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ctrl1_ois.lvl1_ois = ((uint8_t)val & 0x02U) >> 1;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
}
+
return ret;
}
@@ -2855,32 +3336,39 @@ int32_t lsm6dsr_aux_den_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_aux_den_mode_get(stmdev_ctx_t *ctx,
- lsm6dsr_lvl2_ois_t *val)
+ lsm6dsr_lvl2_ois_t *val)
{
lsm6dsr_int_ois_t int_ois;
lsm6dsr_ctrl1_ois_t ctrl1_ois;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS, (uint8_t*)&int_ois, 1);
- if(ret == 0){
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS, (uint8_t *)&int_ois, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
}
- switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois){
+ switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois)
+ {
case LSM6DSR_AUX_DEN_DISABLE:
*val = LSM6DSR_AUX_DEN_DISABLE;
break;
+
case LSM6DSR_AUX_DEN_LEVEL_LATCH:
*val = LSM6DSR_AUX_DEN_LEVEL_LATCH;
break;
+
case LSM6DSR_AUX_DEN_LEVEL_TRIG:
*val = LSM6DSR_AUX_DEN_LEVEL_TRIG;
break;
+
default:
*val = LSM6DSR_AUX_DEN_DISABLE;
break;
}
+
return ret;
}
@@ -2898,11 +3386,14 @@ int32_t lsm6dsr_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsr_int_ois_t int_ois;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS, (uint8_t*)&int_ois, 1);
- if(ret == 0){
- int_ois.int2_drdy_ois= (uint8_t)val;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT_OIS, (uint8_t*)&int_ois, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS, (uint8_t *)&int_ois, 1);
+
+ if (ret == 0)
+ {
+ int_ois.int2_drdy_ois = (uint8_t)val;
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT_OIS, (uint8_t *)&int_ois, 1);
}
+
return ret;
}
@@ -2920,7 +3411,7 @@ int32_t lsm6dsr_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsr_int_ois_t int_ois;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS, (uint8_t*)&int_ois, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS, (uint8_t *)&int_ois, 1);
*val = int_ois.int2_drdy_ois;
return ret;
@@ -2940,18 +3431,21 @@ int32_t lsm6dsr_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsr_aux_mode_set(stmdev_ctx_t *ctx,
- lsm6dsr_ois_en_spi2_t val)
+ lsm6dsr_ois_en_spi2_t val)
{
lsm6dsr_ctrl1_ois_t ctrl1_ois;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
- if(ret == 0){
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
+
+ if (ret == 0)
+ {
ctrl1_ois.ois_en_spi2 = (uint8_t)val & 0x01U;
ctrl1_ois.mode4_en = ((uint8_t)val & 0x02U) >> 1;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
}
+
return ret;
}
@@ -2970,27 +3464,32 @@ int32_t lsm6dsr_aux_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_aux_mode_get(stmdev_ctx_t *ctx,
- lsm6dsr_ois_en_spi2_t *val)
+ lsm6dsr_ois_en_spi2_t *val)
{
lsm6dsr_ctrl1_ois_t ctrl1_ois;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
- switch (((ctrl1_ois.mode4_en << 1) + ctrl1_ois.ois_en_spi2)){
+ switch (((ctrl1_ois.mode4_en << 1) + ctrl1_ois.ois_en_spi2))
+ {
case LSM6DSR_AUX_DISABLE:
*val = LSM6DSR_AUX_DISABLE;
break;
+
case LSM6DSR_MODE_3_GY:
*val = LSM6DSR_MODE_3_GY;
break;
+
case LSM6DSR_MODE_4_GY_XL:
*val = LSM6DSR_MODE_4_GY_XL;
break;
+
default:
*val = LSM6DSR_AUX_DISABLE;
break;
}
+
return ret;
}
@@ -3003,18 +3502,21 @@ int32_t lsm6dsr_aux_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_aux_gy_full_scale_set(stmdev_ctx_t *ctx,
- lsm6dsr_fs_g_ois_t val)
+ lsm6dsr_fs_g_ois_t val)
{
lsm6dsr_ctrl1_ois_t ctrl1_ois;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
- if(ret == 0){
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
+
+ if (ret == 0)
+ {
ctrl1_ois.fs_g_ois = (uint8_t)val & 0x03U;
ctrl1_ois.fs_125_ois = ((uint8_t)val & 0x04U) >> 2;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
}
+
return ret;
}
@@ -3033,28 +3535,35 @@ int32_t lsm6dsr_aux_gy_full_scale_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
- switch ( ( ctrl1_ois.fs_125_ois << 2 ) + ctrl1_ois.fs_g_ois ){
+ switch ((ctrl1_ois.fs_125_ois << 2) + ctrl1_ois.fs_g_ois)
+ {
case LSM6DSR_250dps_AUX:
*val = LSM6DSR_250dps_AUX;
break;
+
case LSM6DSR_125dps_AUX:
*val = LSM6DSR_125dps_AUX;
break;
+
case LSM6DSR_500dps_AUX:
*val = LSM6DSR_500dps_AUX;
break;
+
case LSM6DSR_1000dps_AUX:
*val = LSM6DSR_1000dps_AUX;
break;
+
case LSM6DSR_2000dps_AUX:
*val = LSM6DSR_2000dps_AUX;
break;
+
default:
*val = LSM6DSR_250dps_AUX;
break;
}
+
return ret;
}
@@ -3067,17 +3576,20 @@ int32_t lsm6dsr_aux_gy_full_scale_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_aux_spi_mode_set(stmdev_ctx_t *ctx,
- lsm6dsr_sim_ois_t val)
+ lsm6dsr_sim_ois_t val)
{
lsm6dsr_ctrl1_ois_t ctrl1_ois;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
- if(ret == 0){
- ctrl1_ois.sim_ois= (uint8_t)val;
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
+
+ if (ret == 0)
+ {
+ ctrl1_ois.sim_ois = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
}
+
return ret;
}
@@ -3090,24 +3602,28 @@ int32_t lsm6dsr_aux_spi_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_aux_spi_mode_get(stmdev_ctx_t *ctx,
- lsm6dsr_sim_ois_t *val)
+ lsm6dsr_sim_ois_t *val)
{
lsm6dsr_ctrl1_ois_t ctrl1_ois;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
- switch (ctrl1_ois.sim_ois){
+ switch (ctrl1_ois.sim_ois)
+ {
case LSM6DSR_AUX_SPI_4_WIRE:
*val = LSM6DSR_AUX_SPI_4_WIRE;
break;
+
case LSM6DSR_AUX_SPI_3_WIRE:
*val = LSM6DSR_AUX_SPI_3_WIRE;
break;
+
default:
*val = LSM6DSR_AUX_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -3120,17 +3636,20 @@ int32_t lsm6dsr_aux_spi_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
- lsm6dsr_ftype_ois_t val)
+ lsm6dsr_ftype_ois_t val)
{
lsm6dsr_ctrl2_ois_t ctrl2_ois;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_OIS, (uint8_t*)&ctrl2_ois, 1);
- if(ret == 0){
- ctrl2_ois.ftype_ois= (uint8_t)val;
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_OIS, (uint8_t *)&ctrl2_ois, 1);
+
+ if (ret == 0)
+ {
+ ctrl2_ois.ftype_ois = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL2_OIS,
- (uint8_t*)&ctrl2_ois, 1);
+ (uint8_t *)&ctrl2_ois, 1);
}
+
return ret;
}
@@ -3143,30 +3662,36 @@ int32_t lsm6dsr_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
- lsm6dsr_ftype_ois_t *val)
+ lsm6dsr_ftype_ois_t *val)
{
lsm6dsr_ctrl2_ois_t ctrl2_ois;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_OIS, (uint8_t*)&ctrl2_ois, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_OIS, (uint8_t *)&ctrl2_ois, 1);
- switch (ctrl2_ois.ftype_ois){
+ switch (ctrl2_ois.ftype_ois)
+ {
case LSM6DSR_351Hz39:
*val = LSM6DSR_351Hz39;
break;
+
case LSM6DSR_236Hz63:
*val = LSM6DSR_236Hz63;
break;
+
case LSM6DSR_172Hz70:
*val = LSM6DSR_172Hz70;
break;
+
case LSM6DSR_937Hz91:
*val = LSM6DSR_937Hz91;
break;
+
default:
*val = LSM6DSR_351Hz39;
break;
}
+
return ret;
}
@@ -3179,18 +3704,21 @@ int32_t lsm6dsr_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx,
- lsm6dsr_hpm_ois_t val)
+ lsm6dsr_hpm_ois_t val)
{
lsm6dsr_ctrl2_ois_t ctrl2_ois;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_OIS, (uint8_t*)&ctrl2_ois, 1);
- if(ret == 0){
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_OIS, (uint8_t *)&ctrl2_ois, 1);
+
+ if (ret == 0)
+ {
ctrl2_ois.hpm_ois = (uint8_t)val & 0x03U;
ctrl2_ois.hp_en_ois = ((uint8_t)val & 0x10U) >> 4;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL2_OIS,
- (uint8_t*)&ctrl2_ois, 1);
+ (uint8_t *)&ctrl2_ois, 1);
}
+
return ret;
}
@@ -3203,33 +3731,40 @@ int32_t lsm6dsr_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx,
- lsm6dsr_hpm_ois_t *val)
+ lsm6dsr_hpm_ois_t *val)
{
lsm6dsr_ctrl2_ois_t ctrl2_ois;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_OIS, (uint8_t*)&ctrl2_ois, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_OIS, (uint8_t *)&ctrl2_ois, 1);
- switch ((ctrl2_ois.hp_en_ois << 4) + ctrl2_ois.hpm_ois){
+ switch ((ctrl2_ois.hp_en_ois << 4) + ctrl2_ois.hpm_ois)
+ {
case LSM6DSR_AUX_HP_DISABLE:
*val = LSM6DSR_AUX_HP_DISABLE;
break;
+
case LSM6DSR_AUX_HP_Hz016:
*val = LSM6DSR_AUX_HP_Hz016;
break;
+
case LSM6DSR_AUX_HP_Hz065:
*val = LSM6DSR_AUX_HP_Hz065;
break;
+
case LSM6DSR_AUX_HP_Hz260:
*val = LSM6DSR_AUX_HP_Hz260;
break;
+
case LSM6DSR_AUX_HP_1Hz040:
*val = LSM6DSR_AUX_HP_1Hz040;
break;
+
default:
*val = LSM6DSR_AUX_HP_DISABLE;
break;
}
+
return ret;
}
@@ -3244,17 +3779,20 @@ int32_t lsm6dsr_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_aux_gy_clamp_set(stmdev_ctx_t *ctx,
- lsm6dsr_st_ois_clampdis_t val)
+ lsm6dsr_st_ois_clampdis_t val)
{
lsm6dsr_ctrl3_ois_t ctrl3_ois;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
- if(ret == 0){
- ctrl3_ois.st_ois_clampdis= (uint8_t)val;
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_ois.st_ois_clampdis = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_OIS,
- (uint8_t*)&ctrl3_ois, 1);
+ (uint8_t *)&ctrl3_ois, 1);
}
+
return ret;
}
@@ -3274,19 +3812,23 @@ int32_t lsm6dsr_aux_gy_clamp_get(stmdev_ctx_t *ctx,
lsm6dsr_ctrl3_ois_t ctrl3_ois;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
- switch (ctrl3_ois.st_ois_clampdis){
+ switch (ctrl3_ois.st_ois_clampdis)
+ {
case LSM6DSR_ENABLE_CLAMP:
*val = LSM6DSR_ENABLE_CLAMP;
break;
+
case LSM6DSR_DISABLE_CLAMP:
*val = LSM6DSR_DISABLE_CLAMP;
break;
+
default:
*val = LSM6DSR_ENABLE_CLAMP;
break;
}
+
return ret;
}
@@ -3299,17 +3841,20 @@ int32_t lsm6dsr_aux_gy_clamp_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_aux_gy_self_test_set(stmdev_ctx_t *ctx,
- lsm6dsr_st_ois_t val)
+ lsm6dsr_st_ois_t val)
{
lsm6dsr_ctrl3_ois_t ctrl3_ois;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
- if(ret == 0){
- ctrl3_ois.st_ois= (uint8_t)val;
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_ois.st_ois = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_OIS,
- (uint8_t*)&ctrl3_ois, 1);
+ (uint8_t *)&ctrl3_ois, 1);
}
+
return ret;
}
@@ -3322,27 +3867,32 @@ int32_t lsm6dsr_aux_gy_self_test_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_aux_gy_self_test_get(stmdev_ctx_t *ctx,
- lsm6dsr_st_ois_t *val)
+ lsm6dsr_st_ois_t *val)
{
lsm6dsr_ctrl3_ois_t ctrl3_ois;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
- switch (ctrl3_ois.st_ois){
+ switch (ctrl3_ois.st_ois)
+ {
case LSM6DSR_AUX_GY_DISABLE:
*val = LSM6DSR_AUX_GY_DISABLE;
break;
+
case LSM6DSR_AUX_GY_POS:
*val = LSM6DSR_AUX_GY_POS;
break;
+
case LSM6DSR_AUX_GY_NEG:
*val = LSM6DSR_AUX_GY_NEG;
break;
+
default:
*val = LSM6DSR_AUX_GY_DISABLE;
break;
}
+
return ret;
}
@@ -3355,17 +3905,20 @@ int32_t lsm6dsr_aux_gy_self_test_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_aux_xl_bandwidth_set(stmdev_ctx_t *ctx,
- lsm6dsr_filter_xl_conf_ois_t val)
+ lsm6dsr_filter_xl_conf_ois_t val)
{
lsm6dsr_ctrl3_ois_t ctrl3_ois;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
- if(ret == 0){
- ctrl3_ois.filter_xl_conf_ois= (uint8_t)val;
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_ois.filter_xl_conf_ois = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_OIS,
- (uint8_t*)&ctrl3_ois, 1);
+ (uint8_t *)&ctrl3_ois, 1);
}
+
return ret;
}
@@ -3378,42 +3931,52 @@ int32_t lsm6dsr_aux_xl_bandwidth_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_aux_xl_bandwidth_get(stmdev_ctx_t *ctx,
- lsm6dsr_filter_xl_conf_ois_t *val)
+ lsm6dsr_filter_xl_conf_ois_t *val)
{
lsm6dsr_ctrl3_ois_t ctrl3_ois;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
- switch (ctrl3_ois.filter_xl_conf_ois){
+ switch (ctrl3_ois.filter_xl_conf_ois)
+ {
case LSM6DSR_631Hz:
*val = LSM6DSR_631Hz;
break;
+
case LSM6DSR_295Hz:
*val = LSM6DSR_295Hz;
break;
+
case LSM6DSR_140Hz:
*val = LSM6DSR_140Hz;
break;
+
case LSM6DSR_68Hz2:
*val = LSM6DSR_68Hz2;
break;
+
case LSM6DSR_33Hz6:
*val = LSM6DSR_33Hz6;
break;
+
case LSM6DSR_16Hz7:
*val = LSM6DSR_16Hz7;
break;
+
case LSM6DSR_8Hz3:
*val = LSM6DSR_8Hz3;
break;
+
case LSM6DSR_4Hz11:
*val = LSM6DSR_4Hz11;
break;
+
default:
*val = LSM6DSR_631Hz;
break;
}
+
return ret;
}
@@ -3426,17 +3989,20 @@ int32_t lsm6dsr_aux_xl_bandwidth_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_aux_xl_full_scale_set(stmdev_ctx_t *ctx,
- lsm6dsr_fs_xl_ois_t val)
+ lsm6dsr_fs_xl_ois_t val)
{
lsm6dsr_ctrl3_ois_t ctrl3_ois;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
- if(ret == 0){
- ctrl3_ois.fs_xl_ois= (uint8_t)val;
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_ois.fs_xl_ois = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_OIS,
- (uint8_t*)&ctrl3_ois, 1);
+ (uint8_t *)&ctrl3_ois, 1);
}
+
return ret;
}
@@ -3449,30 +4015,36 @@ int32_t lsm6dsr_aux_xl_full_scale_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_aux_xl_full_scale_get(stmdev_ctx_t *ctx,
- lsm6dsr_fs_xl_ois_t *val)
+ lsm6dsr_fs_xl_ois_t *val)
{
lsm6dsr_ctrl3_ois_t ctrl3_ois;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
- switch (ctrl3_ois.fs_xl_ois){
+ switch (ctrl3_ois.fs_xl_ois)
+ {
case LSM6DSR_AUX_2g:
*val = LSM6DSR_AUX_2g;
break;
+
case LSM6DSR_AUX_16g:
*val = LSM6DSR_AUX_16g;
break;
+
case LSM6DSR_AUX_4g:
*val = LSM6DSR_AUX_4g;
break;
+
case LSM6DSR_AUX_8g:
*val = LSM6DSR_AUX_8g;
break;
+
default:
*val = LSM6DSR_AUX_2g;
break;
}
+
return ret;
}
@@ -3498,16 +4070,19 @@ int32_t lsm6dsr_aux_xl_full_scale_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
- lsm6dsr_sdo_pu_en_t val)
+ lsm6dsr_sdo_pu_en_t val)
{
lsm6dsr_pin_ctrl_t pin_ctrl;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
- if(ret == 0){
- pin_ctrl.sdo_pu_en= (uint8_t)val;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
+
+ if (ret == 0)
+ {
+ pin_ctrl.sdo_pu_en = (uint8_t)val;
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
}
+
return ret;
}
@@ -3520,24 +4095,28 @@ int32_t lsm6dsr_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
- lsm6dsr_sdo_pu_en_t *val)
+ lsm6dsr_sdo_pu_en_t *val)
{
lsm6dsr_pin_ctrl_t pin_ctrl;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
- switch (pin_ctrl.sdo_pu_en){
+ switch (pin_ctrl.sdo_pu_en)
+ {
case LSM6DSR_PULL_UP_DISC:
*val = LSM6DSR_PULL_UP_DISC;
break;
+
case LSM6DSR_PULL_UP_CONNECT:
*val = LSM6DSR_PULL_UP_CONNECT;
break;
+
default:
*val = LSM6DSR_PULL_UP_DISC;
break;
}
+
return ret;
}
@@ -3549,17 +4128,22 @@ int32_t lsm6dsr_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_int1_mode_set(stmdev_ctx_t *ctx, lsm6dsr_pd_dis_int1_t val)
+int32_t lsm6dsr_int1_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsr_pd_dis_int1_t val)
{
lsm6dsr_i3c_bus_avb_t i3c_bus_avb;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_I3C_BUS_AVB, (uint8_t*)&i3c_bus_avb, 1);
- if(ret == 0){
- i3c_bus_avb.pd_dis_int1= (uint8_t)val;
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_I3C_BUS_AVB,
+ (uint8_t *)&i3c_bus_avb, 1);
+
+ if (ret == 0)
+ {
+ i3c_bus_avb.pd_dis_int1 = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
}
+
return ret;
}
@@ -3571,24 +4155,30 @@ int32_t lsm6dsr_int1_mode_set(stmdev_ctx_t *ctx, lsm6dsr_pd_dis_int1_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_int1_mode_get(stmdev_ctx_t *ctx, lsm6dsr_pd_dis_int1_t *val)
+int32_t lsm6dsr_int1_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsr_pd_dis_int1_t *val)
{
lsm6dsr_i3c_bus_avb_t i3c_bus_avb;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_I3C_BUS_AVB, (uint8_t*)&i3c_bus_avb, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_I3C_BUS_AVB,
+ (uint8_t *)&i3c_bus_avb, 1);
- switch (i3c_bus_avb.pd_dis_int1){
+ switch (i3c_bus_avb.pd_dis_int1)
+ {
case LSM6DSR_PULL_DOWN_CONNECT:
*val = LSM6DSR_PULL_DOWN_CONNECT;
break;
+
case LSM6DSR_PULL_DOWN_DISC:
*val = LSM6DSR_PULL_DOWN_DISC;
break;
+
default:
*val = LSM6DSR_PULL_DOWN_CONNECT;
break;
}
+
return ret;
}
@@ -3605,11 +4195,14 @@ int32_t lsm6dsr_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsr_sim_t val)
lsm6dsr_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.sim= (uint8_t)val;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.sim = (uint8_t)val;
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -3626,19 +4219,23 @@ int32_t lsm6dsr_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsr_sim_t *val)
lsm6dsr_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
- switch (ctrl3_c.sim){
+ switch (ctrl3_c.sim)
+ {
case LSM6DSR_SPI_4_WIRE:
*val = LSM6DSR_SPI_4_WIRE;
break;
+
case LSM6DSR_SPI_3_WIRE:
*val = LSM6DSR_SPI_3_WIRE;
break;
+
default:
*val = LSM6DSR_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -3651,16 +4248,19 @@ int32_t lsm6dsr_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsr_sim_t *val)
*
*/
int32_t lsm6dsr_i2c_interface_set(stmdev_ctx_t *ctx,
- lsm6dsr_i2c_disable_t val)
+ lsm6dsr_i2c_disable_t val)
{
lsm6dsr_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ctrl4_c.i2c_disable= (uint8_t)val;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl4_c.i2c_disable = (uint8_t)val;
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -3673,24 +4273,28 @@ int32_t lsm6dsr_i2c_interface_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_i2c_interface_get(stmdev_ctx_t *ctx,
- lsm6dsr_i2c_disable_t *val)
+ lsm6dsr_i2c_disable_t *val)
{
lsm6dsr_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
- switch (ctrl4_c.i2c_disable){
+ switch (ctrl4_c.i2c_disable)
+ {
case LSM6DSR_I2C_ENABLE:
*val = LSM6DSR_I2C_ENABLE;
break;
+
case LSM6DSR_I2C_DISABLE:
*val = LSM6DSR_I2C_DISABLE;
break;
+
default:
*val = LSM6DSR_I2C_ENABLE;
break;
}
+
return ret;
}
@@ -3709,21 +4313,28 @@ int32_t lsm6dsr_i3c_disable_set(stmdev_ctx_t *ctx,
lsm6dsr_i3c_bus_avb_t i3c_bus_avb;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
+ (uint8_t *)&ctrl9_xl, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
}
+
return ret;
}
@@ -3736,37 +4347,47 @@ int32_t lsm6dsr_i3c_disable_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_i3c_disable_get(stmdev_ctx_t *ctx,
- lsm6dsr_i3c_disable_t *val)
+ lsm6dsr_i3c_disable_t *val)
{
lsm6dsr_ctrl9_xl_t ctrl9_xl;
lsm6dsr_i3c_bus_avb_t i3c_bus_avb;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
}
- switch ((ctrl9_xl.i3c_disable << 7) + i3c_bus_avb.i3c_bus_avb_sel){
+
+ switch ((ctrl9_xl.i3c_disable << 7) + i3c_bus_avb.i3c_bus_avb_sel)
+ {
case LSM6DSR_I3C_DISABLE:
*val = LSM6DSR_I3C_DISABLE;
break;
+
case LSM6DSR_I3C_ENABLE_T_50us:
*val = LSM6DSR_I3C_ENABLE_T_50us;
break;
+
case LSM6DSR_I3C_ENABLE_T_2us:
*val = LSM6DSR_I3C_ENABLE_T_2us;
break;
+
case LSM6DSR_I3C_ENABLE_T_1ms:
*val = LSM6DSR_I3C_ENABLE_T_1ms;
break;
+
case LSM6DSR_I3C_ENABLE_T_25ms:
*val = LSM6DSR_I3C_ENABLE_T_25ms;
break;
+
default:
*val = LSM6DSR_I3C_DISABLE;
break;
}
+
return ret;
}
@@ -3778,7 +4399,7 @@ int32_t lsm6dsr_i3c_disable_get(stmdev_ctx_t *ctx,
/**
* @defgroup LSM6DSR_interrupt_pins
* @brief This section groups all the functions that manage
- * interrup pins
+ * interrupt pins
* @{
*
*/
@@ -3793,28 +4414,38 @@ int32_t lsm6dsr_i3c_disable_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_pin_int1_route_set(stmdev_ctx_t *ctx,
- lsm6dsr_pin_int1_route_t *val)
+ lsm6dsr_pin_int1_route_t *val)
{
lsm6dsr_tap_cfg2_t tap_cfg2;
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_INT1,
- (uint8_t*)&val->emb_func_int1, 1);
+ (uint8_t *)&val->emb_func_int1, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_write_reg(ctx, LSM6DSR_FSM_INT1_A,
- (uint8_t*)&val->fsm_int1_a, 1);
+ (uint8_t *)&val->fsm_int1_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_write_reg(ctx, LSM6DSR_FSM_INT1_B,
- (uint8_t*)&val->fsm_int1_b, 1);
+ (uint8_t *)&val->fsm_int1_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
if ((val->emb_func_int1.int1_fsm_lc |
val->emb_func_int1.int1_sig_mot |
val->emb_func_int1.int1_step_detector |
@@ -3834,21 +4465,30 @@ int32_t lsm6dsr_pin_int1_route_set(stmdev_ctx_t *ctx,
val->fsm_int1_b.int1_fsm13 |
val->fsm_int1_b.int1_fsm14 |
val->fsm_int1_b.int1_fsm15 |
- val->fsm_int1_b.int1_fsm16) != PROPERTY_DISABLE){
+ val->fsm_int1_b.int1_fsm16) != PROPERTY_DISABLE)
+ {
val->md1_cfg.int1_emb_func = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
val->md1_cfg.int1_emb_func = PROPERTY_DISABLE;
}
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT1_CTRL,
- (uint8_t*)&val->int1_ctrl, 1);
+
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT1_CTRL,
+ (uint8_t *)&val->int1_ctrl, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_write_reg(ctx, LSM6DSR_MD1_CFG,
- (uint8_t*)&val->md1_cfg, 1);
+ (uint8_t *)&val->md1_cfg, 1);
}
- if(ret == 0){
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG2, (uint8_t*)&tap_cfg2, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
+
if ((val->int1_ctrl.den_drdy_flag |
val->int1_ctrl.int1_boot |
val->int1_ctrl.int1_cnt_bdr |
@@ -3862,17 +4502,23 @@ int32_t lsm6dsr_pin_int1_route_set(stmdev_ctx_t *ctx,
val->md1_cfg.int1_ff |
val->md1_cfg.int1_wu |
val->md1_cfg.int1_single_tap |
- val->md1_cfg.int1_sleep_change)!= PROPERTY_DISABLE){
+ val->md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
+ {
tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
}
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG2,
- (uint8_t*)&tap_cfg2, 1);
+ (uint8_t *)&tap_cfg2, 1);
}
+
return ret;
}
@@ -3886,34 +4532,47 @@ int32_t lsm6dsr_pin_int1_route_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_pin_int1_route_get(stmdev_ctx_t *ctx,
- lsm6dsr_pin_int1_route_t *val)
+ lsm6dsr_pin_int1_route_t *val)
{
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_INT1,
- (uint8_t*)&val->emb_func_int1, 1);
+ (uint8_t *)&val->emb_func_int1, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_INT1_A,
- (uint8_t*)&val->fsm_int1_a, 1);
+ (uint8_t *)&val->fsm_int1_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_INT1_B,
- (uint8_t*)&val->fsm_int1_b, 1);
+ (uint8_t *)&val->fsm_int1_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT1_CTRL,
- (uint8_t*)&val->int1_ctrl, 1);
+ (uint8_t *)&val->int1_ctrl, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_MD1_CFG,
- (uint8_t*)&val->md1_cfg, 1);
+ (uint8_t *)&val->md1_cfg, 1);
}
+
return ret;
}
@@ -3927,29 +4586,38 @@ int32_t lsm6dsr_pin_int1_route_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_pin_int2_route_set(stmdev_ctx_t *ctx,
- lsm6dsr_pin_int2_route_t *val)
+ lsm6dsr_pin_int2_route_t *val)
{
lsm6dsr_tap_cfg2_t tap_cfg2;
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_INT2,
- (uint8_t*)&val->emb_func_int2, 1);
+ (uint8_t *)&val->emb_func_int2, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_write_reg(ctx, LSM6DSR_FSM_INT2_A,
- (uint8_t*)&val->fsm_int2_a, 1);
+ (uint8_t *)&val->fsm_int2_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_write_reg(ctx, LSM6DSR_FSM_INT2_B,
- (uint8_t*)&val->fsm_int2_b, 1);
+ (uint8_t *)&val->fsm_int2_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
if ((val->emb_func_int2.int2_step_detector |
val->emb_func_int2.int2_tilt |
val->emb_func_int2.int2_sig_mot |
@@ -3969,24 +4637,34 @@ int32_t lsm6dsr_pin_int2_route_set(stmdev_ctx_t *ctx,
val->fsm_int2_b.int2_fsm13 |
val->fsm_int2_b.int2_fsm14 |
val->fsm_int2_b.int2_fsm15 |
- val->fsm_int2_b.int2_fsm16) != PROPERTY_DISABLE){
+ val->fsm_int2_b.int2_fsm16) != PROPERTY_DISABLE)
+ {
val->md2_cfg.int2_emb_func = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
val->md2_cfg.int2_emb_func = PROPERTY_DISABLE;
}
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT2_CTRL,
- (uint8_t*)&val->int2_ctrl, 1);
+
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT2_CTRL,
+ (uint8_t *)&val->int2_ctrl, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_write_reg(ctx, LSM6DSR_MD2_CFG,
- (uint8_t*)&val->md2_cfg, 1);
+ (uint8_t *)&val->md2_cfg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG2,
- (uint8_t*)&tap_cfg2, 1);
+ (uint8_t *)&tap_cfg2, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
if ((val->int2_ctrl.int2_drdy_xl |
val->int2_ctrl.int2_drdy_g |
val->int2_ctrl.int2_drdy_temp |
@@ -3999,15 +4677,20 @@ int32_t lsm6dsr_pin_int2_route_set(stmdev_ctx_t *ctx,
val->md2_cfg.int2_ff |
val->md2_cfg.int2_wu |
val->md2_cfg.int2_single_tap |
- val->md2_cfg.int2_sleep_change) != PROPERTY_DISABLE){
+ val->md2_cfg.int2_sleep_change) != PROPERTY_DISABLE)
+ {
tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
}
+
ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG2,
- (uint8_t*)&tap_cfg2, 1);
+ (uint8_t *)&tap_cfg2, 1);
}
+
return ret;
}
@@ -4021,35 +4704,47 @@ int32_t lsm6dsr_pin_int2_route_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_pin_int2_route_get(stmdev_ctx_t *ctx,
- lsm6dsr_pin_int2_route_t *val)
+ lsm6dsr_pin_int2_route_t *val)
{
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_INT2,
- (uint8_t*)&val->emb_func_int2, 1);
+ (uint8_t *)&val->emb_func_int2, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_INT2_A,
- (uint8_t*)&val->fsm_int2_a, 1);
+ (uint8_t *)&val->fsm_int2_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_INT2_B,
- (uint8_t*)&val->fsm_int2_b, 1);
+ (uint8_t *)&val->fsm_int2_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT2_CTRL,
- (uint8_t*)&val->int2_ctrl, 1);
+ (uint8_t *)&val->int2_ctrl, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_MD2_CFG,
- (uint8_t*)&val->md2_cfg, 1);
+ (uint8_t *)&val->md2_cfg, 1);
}
+
return ret;
}
@@ -4066,11 +4761,14 @@ int32_t lsm6dsr_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsr_pp_od_t val)
lsm6dsr_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.pp_od= (uint8_t)val;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.pp_od = (uint8_t)val;
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -4087,19 +4785,23 @@ int32_t lsm6dsr_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsr_pp_od_t *val)
lsm6dsr_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
- switch (ctrl3_c.pp_od){
+ switch (ctrl3_c.pp_od)
+ {
case LSM6DSR_PUSH_PULL:
*val = LSM6DSR_PUSH_PULL;
break;
+
case LSM6DSR_OPEN_DRAIN:
*val = LSM6DSR_OPEN_DRAIN;
break;
+
default:
*val = LSM6DSR_PUSH_PULL;
break;
}
+
return ret;
}
@@ -4112,16 +4814,19 @@ int32_t lsm6dsr_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsr_pp_od_t *val)
*
*/
int32_t lsm6dsr_pin_polarity_set(stmdev_ctx_t *ctx,
- lsm6dsr_h_lactive_t val)
+ lsm6dsr_h_lactive_t val)
{
lsm6dsr_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.h_lactive= (uint8_t)val;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.h_lactive = (uint8_t)val;
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -4134,24 +4839,28 @@ int32_t lsm6dsr_pin_polarity_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_pin_polarity_get(stmdev_ctx_t *ctx,
- lsm6dsr_h_lactive_t *val)
+ lsm6dsr_h_lactive_t *val)
{
lsm6dsr_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
- switch (ctrl3_c.h_lactive){
+ switch (ctrl3_c.h_lactive)
+ {
case LSM6DSR_ACTIVE_HIGH:
*val = LSM6DSR_ACTIVE_HIGH;
break;
+
case LSM6DSR_ACTIVE_LOW:
*val = LSM6DSR_ACTIVE_LOW;
break;
+
default:
*val = LSM6DSR_ACTIVE_HIGH;
break;
}
+
return ret;
}
@@ -4168,11 +4877,14 @@ int32_t lsm6dsr_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsr_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ctrl4_c.int2_on_int1= (uint8_t)val;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl4_c.int2_on_int1 = (uint8_t)val;
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -4189,7 +4901,7 @@ int32_t lsm6dsr_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsr_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.int2_on_int1;
return ret;
@@ -4204,32 +4916,43 @@ int32_t lsm6dsr_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsr_int_notification_set(stmdev_ctx_t *ctx,
- lsm6dsr_lir_t val)
+ lsm6dsr_lir_t val)
{
lsm6dsr_tap_cfg0_t tap_cfg0;
lsm6dsr_page_rw_t page_rw;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
- if(ret == 0){
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
+
+ if (ret == 0)
+ {
tap_cfg0.lir = (uint8_t)val & 0x01U;
tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG0,
- (uint8_t*)&tap_cfg0, 1);
+ (uint8_t *)&tap_cfg0, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
}
- if(ret == 0){
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t*)&page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t*)&page_rw, 1);
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -4242,41 +4965,53 @@ int32_t lsm6dsr_int_notification_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_int_notification_get(stmdev_ctx_t *ctx,
- lsm6dsr_lir_t *val)
+ lsm6dsr_lir_t *val)
{
lsm6dsr_tap_cfg0_t tap_cfg0;
lsm6dsr_page_rw_t page_rw;
int32_t ret;
*val = LSM6DSR_ALL_INT_PULSED;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
}
- if(ret == 0){
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t*)&page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
- switch ((page_rw.emb_func_lir << 1) + tap_cfg0.lir){
+
+ switch ((page_rw.emb_func_lir << 1) + tap_cfg0.lir)
+ {
case LSM6DSR_ALL_INT_PULSED:
*val = LSM6DSR_ALL_INT_PULSED;
break;
+
case LSM6DSR_BASE_LATCHED_EMB_PULSED:
*val = LSM6DSR_BASE_LATCHED_EMB_PULSED;
break;
+
case LSM6DSR_BASE_PULSED_EMB_LATCHED:
*val = LSM6DSR_BASE_PULSED_EMB_LATCHED;
break;
+
case LSM6DSR_ALL_INT_LATCHED:
*val = LSM6DSR_ALL_INT_LATCHED;
break;
+
default:
*val = LSM6DSR_ALL_INT_PULSED;
break;
}
+
return ret;
}
@@ -4304,18 +5039,21 @@ int32_t lsm6dsr_int_notification_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_wkup_ths_weight_set(stmdev_ctx_t *ctx,
- lsm6dsr_wake_ths_w_t val)
+ lsm6dsr_wake_ths_w_t val)
{
lsm6dsr_wake_up_dur_t wake_up_dur;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
- wake_up_dur.wake_ths_w= (uint8_t)val;
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ wake_up_dur.wake_ths_w = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -4330,25 +5068,29 @@ int32_t lsm6dsr_wkup_ths_weight_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_wkup_ths_weight_get(stmdev_ctx_t *ctx,
- lsm6dsr_wake_ths_w_t *val)
+ lsm6dsr_wake_ths_w_t *val)
{
lsm6dsr_wake_up_dur_t wake_up_dur;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
- switch (wake_up_dur.wake_ths_w){
+ switch (wake_up_dur.wake_ths_w)
+ {
case LSM6DSR_LSb_FS_DIV_64:
*val = LSM6DSR_LSb_FS_DIV_64;
break;
+
case LSM6DSR_LSb_FS_DIV_256:
*val = LSM6DSR_LSb_FS_DIV_256;
break;
+
default:
*val = LSM6DSR_LSb_FS_DIV_64;
break;
}
+
return ret;
}
@@ -4367,12 +5109,15 @@ int32_t lsm6dsr_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
- if(ret == 0){
- wake_up_ths.wk_ths= (uint8_t)val;
+ (uint8_t *)&wake_up_ths, 1);
+
+ if (ret == 0)
+ {
+ wake_up_ths.wk_ths = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
}
+
return ret;
}
@@ -4391,7 +5136,7 @@ int32_t lsm6dsr_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
*val = wake_up_ths.wk_ths;
return ret;
@@ -4405,18 +5150,22 @@ int32_t lsm6dsr_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dsr_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dsr_wake_up_ths_t wake_up_ths;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
- if(ret == 0){
- wake_up_ths.usr_off_on_wu= (uint8_t)val;
+ (uint8_t *)&wake_up_ths, 1);
+
+ if (ret == 0)
+ {
+ wake_up_ths.usr_off_on_wu = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
}
+
return ret;
}
@@ -4429,13 +5178,13 @@ int32_t lsm6dsr_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, uint8_t val)
*
*/
int32_t lsm6dsr_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
lsm6dsr_wake_up_ths_t wake_up_ths;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
*val = wake_up_ths.usr_off_on_wu;
return ret;
@@ -4455,12 +5204,15 @@ int32_t lsm6dsr_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
- wake_up_dur.wake_dur= (uint8_t)val;
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ wake_up_dur.wake_dur = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -4478,7 +5230,7 @@ int32_t lsm6dsr_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
*val = wake_up_dur.wake_dur;
return ret;
@@ -4510,11 +5262,14 @@ int32_t lsm6dsr_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsr_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ctrl4_c.sleep_g= (uint8_t)val;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl4_c.sleep_g = (uint8_t)val;
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -4531,7 +5286,7 @@ int32_t lsm6dsr_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsr_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.sleep_g;
return ret;
@@ -4548,17 +5303,20 @@ int32_t lsm6dsr_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsr_act_pin_notification_set(stmdev_ctx_t *ctx,
- lsm6dsr_sleep_status_on_int_t val)
+ lsm6dsr_sleep_status_on_int_t val)
{
lsm6dsr_tap_cfg0_t tap_cfg0;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
- if(ret == 0){
- tap_cfg0. sleep_status_on_int= (uint8_t)val;
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
+
+ if (ret == 0)
+ {
+ tap_cfg0. sleep_status_on_int = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG0,
- (uint8_t*)&tap_cfg0, 1);
+ (uint8_t *)&tap_cfg0, 1);
}
+
return ret;
}
@@ -4573,23 +5331,28 @@ int32_t lsm6dsr_act_pin_notification_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_act_pin_notification_get(stmdev_ctx_t *ctx,
- lsm6dsr_sleep_status_on_int_t *val)
+ lsm6dsr_sleep_status_on_int_t *val)
{
lsm6dsr_tap_cfg0_t tap_cfg0;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
- switch (tap_cfg0. sleep_status_on_int){
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
+
+ switch (tap_cfg0. sleep_status_on_int)
+ {
case LSM6DSR_DRIVE_SLEEP_CHG_EVENT:
*val = LSM6DSR_DRIVE_SLEEP_CHG_EVENT;
break;
+
case LSM6DSR_DRIVE_SLEEP_STATUS:
*val = LSM6DSR_DRIVE_SLEEP_STATUS;
break;
+
default:
*val = LSM6DSR_DRIVE_SLEEP_CHG_EVENT;
break;
}
+
return ret;
}
@@ -4601,16 +5364,20 @@ int32_t lsm6dsr_act_pin_notification_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_act_mode_set(stmdev_ctx_t *ctx, lsm6dsr_inact_en_t val)
+int32_t lsm6dsr_act_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsr_inact_en_t val)
{
lsm6dsr_tap_cfg2_t tap_cfg2;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG2, (uint8_t*)&tap_cfg2, 1);
- if(ret == 0){
- tap_cfg2.inact_en= (uint8_t)val;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG2, (uint8_t*)&tap_cfg2, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
+
+ if (ret == 0)
+ {
+ tap_cfg2.inact_en = (uint8_t)val;
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
}
+
return ret;
}
@@ -4623,30 +5390,36 @@ int32_t lsm6dsr_act_mode_set(stmdev_ctx_t *ctx, lsm6dsr_inact_en_t val)
*
*/
int32_t lsm6dsr_act_mode_get(stmdev_ctx_t *ctx,
- lsm6dsr_inact_en_t *val)
+ lsm6dsr_inact_en_t *val)
{
lsm6dsr_tap_cfg2_t tap_cfg2;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG2, (uint8_t*)&tap_cfg2, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
- switch (tap_cfg2.inact_en){
+ switch (tap_cfg2.inact_en)
+ {
case LSM6DSR_XL_AND_GY_NOT_AFFECTED:
*val = LSM6DSR_XL_AND_GY_NOT_AFFECTED;
break;
+
case LSM6DSR_XL_12Hz5_GY_NOT_AFFECTED:
*val = LSM6DSR_XL_12Hz5_GY_NOT_AFFECTED;
break;
+
case LSM6DSR_XL_12Hz5_GY_SLEEP:
*val = LSM6DSR_XL_12Hz5_GY_SLEEP;
break;
+
case LSM6DSR_XL_12Hz5_GY_PD:
*val = LSM6DSR_XL_12Hz5_GY_PD;
break;
+
default:
*val = LSM6DSR_XL_AND_GY_NOT_AFFECTED;
break;
}
+
return ret;
}
@@ -4664,12 +5437,15 @@ int32_t lsm6dsr_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
- wake_up_dur.sleep_dur= (uint8_t)val;
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ wake_up_dur.sleep_dur = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -4687,7 +5463,7 @@ int32_t lsm6dsr_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
*val = wake_up_dur.sleep_dur;
return ret;
@@ -4719,12 +5495,15 @@ int32_t lsm6dsr_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsr_tap_cfg0_t tap_cfg0;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
- if(ret == 0){
- tap_cfg0.tap_z_en= (uint8_t)val;
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
+
+ if (ret == 0)
+ {
+ tap_cfg0.tap_z_en = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG0,
- (uint8_t*)&tap_cfg0, 1);
+ (uint8_t *)&tap_cfg0, 1);
}
+
return ret;
}
@@ -4736,12 +5515,13 @@ int32_t lsm6dsr_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsr_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsr_tap_cfg0_t tap_cfg0;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
*val = tap_cfg0.tap_z_en;
return ret;
@@ -4760,12 +5540,15 @@ int32_t lsm6dsr_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsr_tap_cfg0_t tap_cfg0;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
- if(ret == 0){
- tap_cfg0.tap_y_en= (uint8_t)val;
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
+
+ if (ret == 0)
+ {
+ tap_cfg0.tap_y_en = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG0,
- (uint8_t*)&tap_cfg0, 1);
+ (uint8_t *)&tap_cfg0, 1);
}
+
return ret;
}
@@ -4777,12 +5560,13 @@ int32_t lsm6dsr_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsr_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsr_tap_cfg0_t tap_cfg0;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
*val = tap_cfg0.tap_y_en;
return ret;
@@ -4801,12 +5585,15 @@ int32_t lsm6dsr_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsr_tap_cfg0_t tap_cfg0;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
- if(ret == 0){
- tap_cfg0.tap_x_en= (uint8_t)val;
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
+
+ if (ret == 0)
+ {
+ tap_cfg0.tap_x_en = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG0,
- (uint8_t*)&tap_cfg0, 1);
+ (uint8_t *)&tap_cfg0, 1);
}
+
return ret;
}
@@ -4818,12 +5605,13 @@ int32_t lsm6dsr_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsr_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsr_tap_cfg0_t tap_cfg0;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
*val = tap_cfg0.tap_x_en;
return ret;
@@ -4842,12 +5630,15 @@ int32_t lsm6dsr_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsr_tap_cfg1_t tap_cfg1;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG1, (uint8_t*)&tap_cfg1, 1);
- if(ret == 0){
- tap_cfg1.tap_ths_x= (uint8_t)val;
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
+
+ if (ret == 0)
+ {
+ tap_cfg1.tap_ths_x = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG1,
- (uint8_t*)&tap_cfg1, 1);
+ (uint8_t *)&tap_cfg1, 1);
}
+
return ret;
}
@@ -4864,7 +5655,7 @@ int32_t lsm6dsr_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsr_tap_cfg1_t tap_cfg1;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG1, (uint8_t*)&tap_cfg1, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
*val = tap_cfg1.tap_ths_x;
return ret;
@@ -4879,16 +5670,19 @@ int32_t lsm6dsr_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsr_tap_axis_priority_set(stmdev_ctx_t *ctx,
- lsm6dsr_tap_priority_t val)
+ lsm6dsr_tap_priority_t val)
{
lsm6dsr_tap_cfg1_t tap_cfg1;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG1, (uint8_t*)&tap_cfg1, 1);
- if(ret == 0){
- tap_cfg1.tap_priority= (uint8_t)val;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG1, (uint8_t*)&tap_cfg1, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
+
+ if (ret == 0)
+ {
+ tap_cfg1.tap_priority = (uint8_t)val;
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
}
+
return ret;
}
@@ -4901,36 +5695,44 @@ int32_t lsm6dsr_tap_axis_priority_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_tap_axis_priority_get(stmdev_ctx_t *ctx,
- lsm6dsr_tap_priority_t *val)
+ lsm6dsr_tap_priority_t *val)
{
lsm6dsr_tap_cfg1_t tap_cfg1;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG1, (uint8_t*)&tap_cfg1, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
- switch (tap_cfg1.tap_priority){
+ switch (tap_cfg1.tap_priority)
+ {
case LSM6DSR_XYZ:
*val = LSM6DSR_XYZ;
break;
+
case LSM6DSR_YXZ:
*val = LSM6DSR_YXZ;
break;
+
case LSM6DSR_XZY:
*val = LSM6DSR_XZY;
break;
+
case LSM6DSR_ZYX:
*val = LSM6DSR_ZYX;
break;
+
case LSM6DSR_YZX:
*val = LSM6DSR_YZX;
break;
+
case LSM6DSR_ZXY:
*val = LSM6DSR_ZXY;
break;
+
default:
*val = LSM6DSR_XYZ;
break;
}
+
return ret;
}
@@ -4947,12 +5749,15 @@ int32_t lsm6dsr_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsr_tap_cfg2_t tap_cfg2;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG2, (uint8_t*)&tap_cfg2, 1);
- if(ret == 0){
- tap_cfg2.tap_ths_y= (uint8_t)val;
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
+
+ if (ret == 0)
+ {
+ tap_cfg2.tap_ths_y = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG2,
- (uint8_t*)&tap_cfg2, 1);
+ (uint8_t *)&tap_cfg2, 1);
}
+
return ret;
}
@@ -4969,7 +5774,7 @@ int32_t lsm6dsr_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsr_tap_cfg2_t tap_cfg2;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG2, (uint8_t*)&tap_cfg2, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
*val = tap_cfg2.tap_ths_y;
return ret;
@@ -4989,12 +5794,15 @@ int32_t lsm6dsr_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
- if(ret == 0){
- tap_ths_6d.tap_ths_z= (uint8_t)val;
+ (uint8_t *)&tap_ths_6d, 1);
+
+ if (ret == 0)
+ {
+ tap_ths_6d.tap_ths_z = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
+ (uint8_t *)&tap_ths_6d, 1);
}
+
return ret;
}
@@ -5012,7 +5820,7 @@ int32_t lsm6dsr_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
+ (uint8_t *)&tap_ths_6d, 1);
*val = tap_ths_6d.tap_ths_z;
return ret;
@@ -5035,12 +5843,15 @@ int32_t lsm6dsr_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsr_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_DUR2, (uint8_t*)&int_dur2, 1);
- if(ret == 0){
- int_dur2.shock= (uint8_t)val;
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_DUR2, (uint8_t *)&int_dur2, 1);
+
+ if (ret == 0)
+ {
+ int_dur2.shock = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT_DUR2,
- (uint8_t*)&int_dur2, 1);
+ (uint8_t *)&int_dur2, 1);
}
+
return ret;
}
@@ -5061,7 +5872,7 @@ int32_t lsm6dsr_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsr_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_DUR2, (uint8_t *)&int_dur2, 1);
*val = int_dur2.shock;
return ret;
@@ -5084,12 +5895,15 @@ int32_t lsm6dsr_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsr_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_DUR2, (uint8_t*)&int_dur2, 1);
- if(ret == 0){
- int_dur2.quiet= (uint8_t)val;
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_DUR2, (uint8_t *)&int_dur2, 1);
+
+ if (ret == 0)
+ {
+ int_dur2.quiet = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT_DUR2,
- (uint8_t*)&int_dur2, 1);
+ (uint8_t *)&int_dur2, 1);
}
+
return ret;
}
@@ -5110,7 +5924,7 @@ int32_t lsm6dsr_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsr_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_DUR2, (uint8_t *)&int_dur2, 1);
*val = int_dur2.quiet;
return ret;
@@ -5135,12 +5949,15 @@ int32_t lsm6dsr_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsr_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_DUR2, (uint8_t*)&int_dur2, 1);
- if(ret == 0){
- int_dur2.dur= (uint8_t)val;
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_DUR2, (uint8_t *)&int_dur2, 1);
+
+ if (ret == 0)
+ {
+ int_dur2.dur = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT_DUR2,
- (uint8_t*)&int_dur2, 1);
+ (uint8_t *)&int_dur2, 1);
}
+
return ret;
}
@@ -5161,7 +5978,7 @@ int32_t lsm6dsr_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsr_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_DUR2, (uint8_t *)&int_dur2, 1);
*val = int_dur2.dur;
return ret;
@@ -5176,18 +5993,21 @@ int32_t lsm6dsr_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsr_tap_mode_set(stmdev_ctx_t *ctx,
- lsm6dsr_single_double_tap_t val)
+ lsm6dsr_single_double_tap_t val)
{
lsm6dsr_wake_up_ths_t wake_up_ths;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
- if(ret == 0){
- wake_up_ths.single_double_tap= (uint8_t)val;
+ (uint8_t *)&wake_up_ths, 1);
+
+ if (ret == 0)
+ {
+ wake_up_ths.single_double_tap = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
}
+
return ret;
}
@@ -5200,25 +6020,29 @@ int32_t lsm6dsr_tap_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_tap_mode_get(stmdev_ctx_t *ctx,
- lsm6dsr_single_double_tap_t *val)
+ lsm6dsr_single_double_tap_t *val)
{
lsm6dsr_wake_up_ths_t wake_up_ths;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
- switch (wake_up_ths.single_double_tap){
+ switch (wake_up_ths.single_double_tap)
+ {
case LSM6DSR_ONLY_SINGLE:
*val = LSM6DSR_ONLY_SINGLE;
break;
+
case LSM6DSR_BOTH_SINGLE_DOUBLE:
*val = LSM6DSR_BOTH_SINGLE_DOUBLE;
break;
+
default:
*val = LSM6DSR_ONLY_SINGLE;
break;
}
+
return ret;
}
@@ -5244,18 +6068,21 @@ int32_t lsm6dsr_tap_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_6d_threshold_set(stmdev_ctx_t *ctx,
- lsm6dsr_sixd_ths_t val)
+ lsm6dsr_sixd_ths_t val)
{
lsm6dsr_tap_ths_6d_t tap_ths_6d;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
- if(ret == 0){
- tap_ths_6d.sixd_ths= (uint8_t)val;
+ (uint8_t *)&tap_ths_6d, 1);
+
+ if (ret == 0)
+ {
+ tap_ths_6d.sixd_ths = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
+ (uint8_t *)&tap_ths_6d, 1);
}
+
return ret;
}
@@ -5268,31 +6095,37 @@ int32_t lsm6dsr_6d_threshold_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_6d_threshold_get(stmdev_ctx_t *ctx,
- lsm6dsr_sixd_ths_t *val)
+ lsm6dsr_sixd_ths_t *val)
{
lsm6dsr_tap_ths_6d_t tap_ths_6d;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
+ (uint8_t *)&tap_ths_6d, 1);
- switch (tap_ths_6d.sixd_ths){
+ switch (tap_ths_6d.sixd_ths)
+ {
case LSM6DSR_DEG_80:
*val = LSM6DSR_DEG_80;
break;
+
case LSM6DSR_DEG_70:
*val = LSM6DSR_DEG_70;
break;
+
case LSM6DSR_DEG_60:
*val = LSM6DSR_DEG_60;
break;
+
case LSM6DSR_DEG_50:
*val = LSM6DSR_DEG_50;
break;
+
default:
*val = LSM6DSR_DEG_80;
break;
}
+
return ret;
}
@@ -5310,12 +6143,15 @@ int32_t lsm6dsr_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
- if(ret == 0){
- tap_ths_6d.d4d_en= (uint8_t)val;
+ (uint8_t *)&tap_ths_6d, 1);
+
+ if (ret == 0)
+ {
+ tap_ths_6d.d4d_en = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
+ (uint8_t *)&tap_ths_6d, 1);
}
+
return ret;
}
@@ -5333,7 +6169,7 @@ int32_t lsm6dsr_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
+ (uint8_t *)&tap_ths_6d, 1);
*val = tap_ths_6d.d4d_en;
return ret;
@@ -5361,17 +6197,20 @@ int32_t lsm6dsr_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsr_ff_threshold_set(stmdev_ctx_t *ctx,
- lsm6dsr_ff_ths_t val)
+ lsm6dsr_ff_ths_t val)
{
lsm6dsr_free_fall_t free_fall;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_FREE_FALL, (uint8_t*)&free_fall, 1);
- if(ret == 0){
- free_fall.ff_ths= (uint8_t)val;
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_FREE_FALL, (uint8_t *)&free_fall, 1);
+
+ if (ret == 0)
+ {
+ free_fall.ff_ths = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_FREE_FALL,
- (uint8_t*)&free_fall, 1);
+ (uint8_t *)&free_fall, 1);
}
+
return ret;
}
@@ -5384,42 +6223,52 @@ int32_t lsm6dsr_ff_threshold_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_ff_threshold_get(stmdev_ctx_t *ctx,
- lsm6dsr_ff_ths_t *val)
+ lsm6dsr_ff_ths_t *val)
{
lsm6dsr_free_fall_t free_fall;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_FREE_FALL, (uint8_t*)&free_fall, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_FREE_FALL, (uint8_t *)&free_fall, 1);
- switch (free_fall.ff_ths){
+ switch (free_fall.ff_ths)
+ {
case LSM6DSR_FF_TSH_156mg:
*val = LSM6DSR_FF_TSH_156mg;
break;
+
case LSM6DSR_FF_TSH_219mg:
*val = LSM6DSR_FF_TSH_219mg;
break;
+
case LSM6DSR_FF_TSH_250mg:
*val = LSM6DSR_FF_TSH_250mg;
break;
+
case LSM6DSR_FF_TSH_312mg:
*val = LSM6DSR_FF_TSH_312mg;
break;
+
case LSM6DSR_FF_TSH_344mg:
*val = LSM6DSR_FF_TSH_344mg;
break;
+
case LSM6DSR_FF_TSH_406mg:
*val = LSM6DSR_FF_TSH_406mg;
break;
+
case LSM6DSR_FF_TSH_469mg:
*val = LSM6DSR_FF_TSH_469mg;
break;
+
case LSM6DSR_FF_TSH_500mg:
*val = LSM6DSR_FF_TSH_500mg;
break;
+
default:
*val = LSM6DSR_FF_TSH_156mg;
break;
}
+
return ret;
}
@@ -5438,21 +6287,28 @@ int32_t lsm6dsr_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
wake_up_dur.ff_dur = (val & 0x20U) >> 5;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FREE_FALL,
- (uint8_t*)&free_fall, 1);
+ (uint8_t *)&free_fall, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
free_fall.ff_dur = val & 0x1FU;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_FREE_FALL,
- (uint8_t*)&free_fall, 1);
+ (uint8_t *)&free_fall, 1);
}
+
return ret;
}
@@ -5471,12 +6327,14 @@ int32_t lsm6dsr_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FREE_FALL,
- (uint8_t*)&free_fall, 1);
+ (uint8_t *)&free_fall, 1);
}
+
*val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
return ret;
@@ -5510,17 +6368,22 @@ int32_t lsm6dsr_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl1.wtm = (uint8_t)(0x00FFU & val);
ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL1,
- (uint8_t*)&fifo_ctrl1, 1);
+ (uint8_t *)&fifo_ctrl1, 1);
}
- if(ret == 0){
- fifo_ctrl2.wtm = (uint8_t)(( 0x0100U & val ) >> 8);
+
+ if (ret == 0)
+ {
+ fifo_ctrl2.wtm = (uint8_t)((0x0100U & val) >> 8);
ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
+
return ret;
}
@@ -5539,14 +6402,18 @@ int32_t lsm6dsr_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL1,
- (uint8_t*)&fifo_ctrl1, 1);
+ (uint8_t *)&fifo_ctrl1, 1);
}
+
*val = fifo_ctrl2.wtm;
*val = *val << 8;
*val += fifo_ctrl1.wtm;
+
return ret;
}
@@ -5558,24 +6425,32 @@ int32_t lsm6dsr_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_compression_algo_init_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dsr_compression_algo_init_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dsr_emb_func_init_b_t emb_func_init_b;
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_INIT_B,
- (uint8_t*)&emb_func_init_b, 1);
+ (uint8_t *)&emb_func_init_b, 1);
}
- if(ret == 0){
- emb_func_init_b.fifo_compr_init= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ emb_func_init_b.fifo_compr_init = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_INIT_B,
- (uint8_t*)&emb_func_init_b, 1);
+ (uint8_t *)&emb_func_init_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -5589,20 +6464,25 @@ int32_t lsm6dsr_compression_algo_init_set(stmdev_ctx_t *ctx, uint8_t val)
*
*/
int32_t lsm6dsr_compression_algo_init_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
lsm6dsr_emb_func_init_b_t emb_func_init_b;
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_INIT_B,
- (uint8_t*)&emb_func_init_b, 1);
+ (uint8_t *)&emb_func_init_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = emb_func_init_b.fifo_compr_init;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -5615,7 +6495,7 @@ int32_t lsm6dsr_compression_algo_init_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_compression_algo_set(stmdev_ctx_t *ctx,
- lsm6dsr_uncoptr_rate_t val)
+ lsm6dsr_uncoptr_rate_t val)
{
lsm6dsr_fifo_ctrl2_t fifo_ctrl2;
lsm6dsr_emb_func_en_b_t emb_func_en_b;
@@ -5623,30 +6503,42 @@ int32_t lsm6dsr_compression_algo_set(stmdev_ctx_t *ctx,
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
emb_func_en_b.fifo_compr_en = ((uint8_t)val & 0x04U) >> 2;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
fifo_ctrl2.fifo_compr_rt_en = ((uint8_t)val & 0x04U) >> 2;
fifo_ctrl2.uncoptr_rate = (uint8_t)val & 0x03U;
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
+
return ret;
}
@@ -5659,34 +6551,42 @@ int32_t lsm6dsr_compression_algo_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_compression_algo_get(stmdev_ctx_t *ctx,
- lsm6dsr_uncoptr_rate_t *val)
+ lsm6dsr_uncoptr_rate_t *val)
{
lsm6dsr_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
- switch (( fifo_ctrl2.fifo_compr_rt_en << 2) + fifo_ctrl2.uncoptr_rate ){
+ switch ((fifo_ctrl2.fifo_compr_rt_en << 2) +
+ fifo_ctrl2.uncoptr_rate)
+ {
case LSM6DSR_CMP_DISABLE:
*val = LSM6DSR_CMP_DISABLE;
break;
+
case LSM6DSR_CMP_ALWAYS:
*val = LSM6DSR_CMP_ALWAYS;
break;
+
case LSM6DSR_CMP_8_TO_1:
*val = LSM6DSR_CMP_8_TO_1;
break;
+
case LSM6DSR_CMP_16_TO_1:
*val = LSM6DSR_CMP_16_TO_1;
break;
+
case LSM6DSR_CMP_32_TO_1:
*val = LSM6DSR_CMP_32_TO_1;
break;
+
default:
*val = LSM6DSR_CMP_DISABLE;
break;
}
+
return ret;
}
@@ -5699,17 +6599,19 @@ int32_t lsm6dsr_compression_algo_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
- uint8_t val)
+ uint8_t val)
{
lsm6dsr_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
- fifo_ctrl2.odrchg_en= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl2.odrchg_en = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
return ret;
@@ -5724,13 +6626,13 @@ int32_t lsm6dsr_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
lsm6dsr_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
*val = fifo_ctrl2.odrchg_en;
return ret;
@@ -5745,18 +6647,21 @@ int32_t lsm6dsr_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_compression_algo_real_time_set(stmdev_ctx_t *ctx,
- uint8_t val)
+ uint8_t val)
{
lsm6dsr_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
- fifo_ctrl2.fifo_compr_rt_en= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl2.fifo_compr_rt_en = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
+
return ret;
}
@@ -5769,13 +6674,13 @@ int32_t lsm6dsr_compression_algo_real_time_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_compression_algo_real_time_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
lsm6dsr_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
*val = fifo_ctrl2.fifo_compr_rt_en;
return ret;
@@ -5796,12 +6701,15 @@ int32_t lsm6dsr_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
- fifo_ctrl2.stop_on_wtm= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl2.stop_on_wtm = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
+
return ret;
}
@@ -5820,7 +6728,7 @@ int32_t lsm6dsr_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
*val = fifo_ctrl2.stop_on_wtm;
return ret;
@@ -5836,18 +6744,21 @@ int32_t lsm6dsr_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsr_fifo_xl_batch_set(stmdev_ctx_t *ctx,
- lsm6dsr_bdr_xl_t val)
+ lsm6dsr_bdr_xl_t val)
{
lsm6dsr_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
- if(ret == 0){
- fifo_ctrl3.bdr_xl= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl3, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl3.bdr_xl = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
+ (uint8_t *)&fifo_ctrl3, 1);
}
+
return ret;
}
@@ -5861,55 +6772,69 @@ int32_t lsm6dsr_fifo_xl_batch_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_fifo_xl_batch_get(stmdev_ctx_t *ctx,
- lsm6dsr_bdr_xl_t *val)
+ lsm6dsr_bdr_xl_t *val)
{
lsm6dsr_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
+ (uint8_t *)&fifo_ctrl3, 1);
- switch (fifo_ctrl3.bdr_xl){
+ switch (fifo_ctrl3.bdr_xl)
+ {
case LSM6DSR_XL_NOT_BATCHED:
*val = LSM6DSR_XL_NOT_BATCHED;
break;
+
case LSM6DSR_XL_BATCHED_AT_12Hz5:
*val = LSM6DSR_XL_BATCHED_AT_12Hz5;
break;
+
case LSM6DSR_XL_BATCHED_AT_26Hz:
*val = LSM6DSR_XL_BATCHED_AT_26Hz;
break;
+
case LSM6DSR_XL_BATCHED_AT_52Hz:
*val = LSM6DSR_XL_BATCHED_AT_52Hz;
break;
+
case LSM6DSR_XL_BATCHED_AT_104Hz:
*val = LSM6DSR_XL_BATCHED_AT_104Hz;
break;
+
case LSM6DSR_XL_BATCHED_AT_208Hz:
*val = LSM6DSR_XL_BATCHED_AT_208Hz;
break;
+
case LSM6DSR_XL_BATCHED_AT_417Hz:
*val = LSM6DSR_XL_BATCHED_AT_417Hz;
break;
+
case LSM6DSR_XL_BATCHED_AT_833Hz:
*val = LSM6DSR_XL_BATCHED_AT_833Hz;
break;
+
case LSM6DSR_XL_BATCHED_AT_1667Hz:
*val = LSM6DSR_XL_BATCHED_AT_1667Hz;
break;
+
case LSM6DSR_XL_BATCHED_AT_3333Hz:
*val = LSM6DSR_XL_BATCHED_AT_3333Hz;
break;
+
case LSM6DSR_XL_BATCHED_AT_6667Hz:
*val = LSM6DSR_XL_BATCHED_AT_6667Hz;
break;
+
case LSM6DSR_XL_BATCHED_AT_6Hz5:
*val = LSM6DSR_XL_BATCHED_AT_6Hz5;
break;
+
default:
*val = LSM6DSR_XL_NOT_BATCHED;
break;
}
+
return ret;
}
@@ -5923,18 +6848,21 @@ int32_t lsm6dsr_fifo_xl_batch_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_fifo_gy_batch_set(stmdev_ctx_t *ctx,
- lsm6dsr_bdr_gy_t val)
+ lsm6dsr_bdr_gy_t val)
{
lsm6dsr_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
- if(ret == 0){
- fifo_ctrl3.bdr_gy= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl3, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl3.bdr_gy = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
+ (uint8_t *)&fifo_ctrl3, 1);
}
+
return ret;
}
@@ -5948,55 +6876,69 @@ int32_t lsm6dsr_fifo_gy_batch_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_fifo_gy_batch_get(stmdev_ctx_t *ctx,
- lsm6dsr_bdr_gy_t *val)
+ lsm6dsr_bdr_gy_t *val)
{
lsm6dsr_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
+ (uint8_t *)&fifo_ctrl3, 1);
- switch (fifo_ctrl3.bdr_gy){
+ switch (fifo_ctrl3.bdr_gy)
+ {
case LSM6DSR_GY_NOT_BATCHED:
*val = LSM6DSR_GY_NOT_BATCHED;
break;
+
case LSM6DSR_GY_BATCHED_AT_12Hz5:
*val = LSM6DSR_GY_BATCHED_AT_12Hz5;
break;
+
case LSM6DSR_GY_BATCHED_AT_26Hz:
*val = LSM6DSR_GY_BATCHED_AT_26Hz;
break;
+
case LSM6DSR_GY_BATCHED_AT_52Hz:
*val = LSM6DSR_GY_BATCHED_AT_52Hz;
break;
+
case LSM6DSR_GY_BATCHED_AT_104Hz:
*val = LSM6DSR_GY_BATCHED_AT_104Hz;
break;
+
case LSM6DSR_GY_BATCHED_AT_208Hz:
*val = LSM6DSR_GY_BATCHED_AT_208Hz;
break;
+
case LSM6DSR_GY_BATCHED_AT_417Hz:
*val = LSM6DSR_GY_BATCHED_AT_417Hz;
break;
+
case LSM6DSR_GY_BATCHED_AT_833Hz:
*val = LSM6DSR_GY_BATCHED_AT_833Hz;
break;
+
case LSM6DSR_GY_BATCHED_AT_1667Hz:
*val = LSM6DSR_GY_BATCHED_AT_1667Hz;
break;
+
case LSM6DSR_GY_BATCHED_AT_3333Hz:
*val = LSM6DSR_GY_BATCHED_AT_3333Hz;
break;
+
case LSM6DSR_GY_BATCHED_AT_6667Hz:
*val = LSM6DSR_GY_BATCHED_AT_6667Hz;
break;
+
case LSM6DSR_GY_BATCHED_6Hz5:
*val = LSM6DSR_GY_BATCHED_6Hz5;
break;
+
default:
*val = LSM6DSR_GY_NOT_BATCHED;
break;
}
+
return ret;
}
@@ -6009,18 +6951,21 @@ int32_t lsm6dsr_fifo_gy_batch_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_fifo_mode_set(stmdev_ctx_t *ctx,
- lsm6dsr_fifo_mode_t val)
+ lsm6dsr_fifo_mode_t val)
{
lsm6dsr_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
- fifo_ctrl4.fifo_mode= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl4.fifo_mode = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -6033,37 +6978,45 @@ int32_t lsm6dsr_fifo_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_fifo_mode_get(stmdev_ctx_t *ctx,
- lsm6dsr_fifo_mode_t *val)
+ lsm6dsr_fifo_mode_t *val)
{
lsm6dsr_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
- switch (fifo_ctrl4.fifo_mode){
+ switch (fifo_ctrl4.fifo_mode)
+ {
case LSM6DSR_BYPASS_MODE:
*val = LSM6DSR_BYPASS_MODE;
break;
+
case LSM6DSR_FIFO_MODE:
*val = LSM6DSR_FIFO_MODE;
break;
+
case LSM6DSR_STREAM_TO_FIFO_MODE:
*val = LSM6DSR_STREAM_TO_FIFO_MODE;
break;
+
case LSM6DSR_BYPASS_TO_STREAM_MODE:
*val = LSM6DSR_BYPASS_TO_STREAM_MODE;
break;
+
case LSM6DSR_STREAM_MODE:
*val = LSM6DSR_STREAM_MODE;
break;
+
case LSM6DSR_BYPASS_TO_FIFO_MODE:
*val = LSM6DSR_BYPASS_TO_FIFO_MODE;
break;
+
default:
*val = LSM6DSR_BYPASS_MODE;
break;
}
+
return ret;
}
@@ -6077,18 +7030,21 @@ int32_t lsm6dsr_fifo_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_fifo_temp_batch_set(stmdev_ctx_t *ctx,
- lsm6dsr_odr_t_batch_t val)
+ lsm6dsr_odr_t_batch_t val)
{
lsm6dsr_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
- fifo_ctrl4.odr_t_batch= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl4.odr_t_batch = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -6102,31 +7058,37 @@ int32_t lsm6dsr_fifo_temp_batch_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_fifo_temp_batch_get(stmdev_ctx_t *ctx,
- lsm6dsr_odr_t_batch_t *val)
+ lsm6dsr_odr_t_batch_t *val)
{
lsm6dsr_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
- switch (fifo_ctrl4.odr_t_batch){
+ switch (fifo_ctrl4.odr_t_batch)
+ {
case LSM6DSR_TEMP_NOT_BATCHED:
*val = LSM6DSR_TEMP_NOT_BATCHED;
break;
+
case LSM6DSR_TEMP_BATCHED_AT_52Hz:
*val = LSM6DSR_TEMP_BATCHED_AT_52Hz;
break;
+
case LSM6DSR_TEMP_BATCHED_AT_12Hz5:
*val = LSM6DSR_TEMP_BATCHED_AT_12Hz5;
break;
+
case LSM6DSR_TEMP_BATCHED_AT_1Hz6:
*val = LSM6DSR_TEMP_BATCHED_AT_1Hz6;
break;
+
default:
*val = LSM6DSR_TEMP_NOT_BATCHED;
break;
}
+
return ret;
}
@@ -6141,18 +7103,21 @@ int32_t lsm6dsr_fifo_temp_batch_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
- lsm6dsr_odr_ts_batch_t val)
+ lsm6dsr_odr_ts_batch_t val)
{
lsm6dsr_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
- fifo_ctrl4.odr_ts_batch= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl4.odr_ts_batch = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -6168,31 +7133,37 @@ int32_t lsm6dsr_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
- lsm6dsr_odr_ts_batch_t *val)
+ lsm6dsr_odr_ts_batch_t *val)
{
lsm6dsr_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
- switch (fifo_ctrl4.odr_ts_batch){
+ switch (fifo_ctrl4.odr_ts_batch)
+ {
case LSM6DSR_NO_DECIMATION:
*val = LSM6DSR_NO_DECIMATION;
break;
+
case LSM6DSR_DEC_1:
*val = LSM6DSR_DEC_1;
break;
+
case LSM6DSR_DEC_8:
*val = LSM6DSR_DEC_8;
break;
+
case LSM6DSR_DEC_32:
*val = LSM6DSR_DEC_32;
break;
+
default:
*val = LSM6DSR_NO_DECIMATION;
break;
}
+
return ret;
}
@@ -6207,18 +7178,21 @@ int32_t lsm6dsr_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
- lsm6dsr_trig_counter_bdr_t val)
+ lsm6dsr_trig_counter_bdr_t val)
{
lsm6dsr_counter_bdr_reg1_t counter_bdr_reg1;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if(ret == 0){
- counter_bdr_reg1.trig_counter_bdr= (uint8_t)val;
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
+ counter_bdr_reg1.trig_counter_bdr = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
}
+
return ret;
}
@@ -6233,25 +7207,29 @@ int32_t lsm6dsr_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
- lsm6dsr_trig_counter_bdr_t *val)
+ lsm6dsr_trig_counter_bdr_t *val)
{
lsm6dsr_counter_bdr_reg1_t counter_bdr_reg1;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
- switch (counter_bdr_reg1.trig_counter_bdr){
+ switch (counter_bdr_reg1.trig_counter_bdr)
+ {
case LSM6DSR_XL_BATCH_EVENT:
*val = LSM6DSR_XL_BATCH_EVENT;
break;
+
case LSM6DSR_GYRO_BATCH_EVENT:
*val = LSM6DSR_GYRO_BATCH_EVENT;
break;
+
default:
*val = LSM6DSR_XL_BATCH_EVENT;
break;
}
+
return ret;
}
@@ -6270,12 +7248,15 @@ int32_t lsm6dsr_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if(ret == 0){
- counter_bdr_reg1.rst_counter_bdr= (uint8_t)val;
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
+ counter_bdr_reg1.rst_counter_bdr = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
}
+
return ret;
}
@@ -6294,7 +7275,7 @@ int32_t lsm6dsr_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
*val = counter_bdr_reg1.rst_counter_bdr;
return ret;
@@ -6310,23 +7291,29 @@ int32_t lsm6dsr_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsr_batch_counter_threshold_set(stmdev_ctx_t *ctx,
- uint16_t val)
+ uint16_t val)
{
lsm6dsr_counter_bdr_reg2_t counter_bdr_reg1;
lsm6dsr_counter_bdr_reg2_t counter_bdr_reg2;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if (ret == 0){
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
counter_bdr_reg1.cnt_bdr_th = (uint8_t)((0x0700U & val) >> 8);
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_COUNTER_BDR_REG1, (uint8_t*)&counter_bdr_reg1, 1);
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
+ (uint8_t *)&counter_bdr_reg1, 1);
}
- if (ret == 0){
+
+ if (ret == 0)
+ {
counter_bdr_reg2.cnt_bdr_th = (uint8_t)(0x00FFU & val);
ret = lsm6dsr_write_reg(ctx, LSM6DSR_COUNTER_BDR_REG2,
- (uint8_t*)&counter_bdr_reg2, 1);
+ (uint8_t *)&counter_bdr_reg2, 1);
}
+
return ret;
}
@@ -6340,22 +7327,25 @@ int32_t lsm6dsr_batch_counter_threshold_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_batch_counter_threshold_get(stmdev_ctx_t *ctx,
- uint16_t *val)
+ uint16_t *val)
{
lsm6dsr_counter_bdr_reg1_t counter_bdr_reg1;
lsm6dsr_counter_bdr_reg2_t counter_bdr_reg2;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if (ret == 0){
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG2,
- (uint8_t*)&counter_bdr_reg2, 1);
+ (uint8_t *)&counter_bdr_reg2, 1);
}
*val = counter_bdr_reg1.cnt_bdr_th;
*val = *val << 8;
*val += counter_bdr_reg2.cnt_bdr_th;
+
return ret;
}
@@ -6374,14 +7364,17 @@ int32_t lsm6dsr_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_STATUS1,
- (uint8_t*)&fifo_status1, 1);
- if (ret == 0){
+ (uint8_t *)&fifo_status1, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
+ (uint8_t *)&fifo_status2, 1);
*val = fifo_status2.diff_fifo;
*val = *val << 8;
*val += fifo_status1.diff_fifo;
}
+
return ret;
}
@@ -6394,10 +7387,12 @@ int32_t lsm6dsr_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
*
*/
int32_t lsm6dsr_fifo_status_get(stmdev_ctx_t *ctx,
- lsm6dsr_fifo_status2_t *val)
+ lsm6dsr_fifo_status2_t *val)
{
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_STATUS2, (uint8_t*)val, 1);
+
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_STATUS2, (uint8_t *)val, 1);
+
return ret;
}
@@ -6415,7 +7410,7 @@ int32_t lsm6dsr_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
+ (uint8_t *)&fifo_status2, 1);
*val = fifo_status2.fifo_full_ia;
return ret;
@@ -6436,7 +7431,7 @@ int32_t lsm6dsr_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
+ (uint8_t *)&fifo_status2, 1);
*val = fifo_status2. fifo_ovr_ia;
return ret;
@@ -6456,7 +7451,7 @@ int32_t lsm6dsr_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
+ (uint8_t *)&fifo_status2, 1);
*val = fifo_status2.fifo_wtm_ia;
return ret;
@@ -6471,85 +7466,109 @@ int32_t lsm6dsr_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsr_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
- lsm6dsr_fifo_tag_t *val)
+ lsm6dsr_fifo_tag_t *val)
{
lsm6dsr_fifo_data_out_tag_t fifo_data_out_tag;
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_DATA_OUT_TAG,
- (uint8_t*)&fifo_data_out_tag, 1);
+ (uint8_t *)&fifo_data_out_tag, 1);
- switch (fifo_data_out_tag.tag_sensor){
+ switch (fifo_data_out_tag.tag_sensor)
+ {
case LSM6DSR_GYRO_NC_TAG:
*val = LSM6DSR_GYRO_NC_TAG;
break;
+
case LSM6DSR_XL_NC_TAG:
*val = LSM6DSR_XL_NC_TAG;
break;
+
case LSM6DSR_TEMPERATURE_TAG:
*val = LSM6DSR_TEMPERATURE_TAG;
break;
+
case LSM6DSR_TIMESTAMP_TAG:
*val = LSM6DSR_TIMESTAMP_TAG;
break;
+
case LSM6DSR_CFG_CHANGE_TAG:
*val = LSM6DSR_CFG_CHANGE_TAG;
break;
+
case LSM6DSR_XL_NC_T_2_TAG:
*val = LSM6DSR_XL_NC_T_2_TAG;
break;
+
case LSM6DSR_XL_NC_T_1_TAG:
*val = LSM6DSR_XL_NC_T_1_TAG;
break;
+
case LSM6DSR_XL_2XC_TAG:
*val = LSM6DSR_XL_2XC_TAG;
break;
+
case LSM6DSR_XL_3XC_TAG:
*val = LSM6DSR_XL_3XC_TAG;
break;
+
case LSM6DSR_GYRO_NC_T_2_TAG:
*val = LSM6DSR_GYRO_NC_T_2_TAG;
break;
+
case LSM6DSR_GYRO_NC_T_1_TAG:
*val = LSM6DSR_GYRO_NC_T_1_TAG;
break;
+
case LSM6DSR_GYRO_2XC_TAG:
*val = LSM6DSR_GYRO_2XC_TAG;
break;
+
case LSM6DSR_GYRO_3XC_TAG:
*val = LSM6DSR_GYRO_3XC_TAG;
break;
+
case LSM6DSR_SENSORHUB_SLAVE0_TAG:
*val = LSM6DSR_SENSORHUB_SLAVE0_TAG;
break;
+
case LSM6DSR_SENSORHUB_SLAVE1_TAG:
*val = LSM6DSR_SENSORHUB_SLAVE1_TAG;
break;
+
case LSM6DSR_SENSORHUB_SLAVE2_TAG:
*val = LSM6DSR_SENSORHUB_SLAVE2_TAG;
break;
+
case LSM6DSR_SENSORHUB_SLAVE3_TAG:
*val = LSM6DSR_SENSORHUB_SLAVE3_TAG;
break;
+
case LSM6DSR_STEP_CPUNTER_TAG:
*val = LSM6DSR_STEP_CPUNTER_TAG;
break;
+
case LSM6DSR_GAME_ROTATION_TAG:
*val = LSM6DSR_GAME_ROTATION_TAG;
break;
+
case LSM6DSR_GEOMAG_ROTATION_TAG:
*val = LSM6DSR_GEOMAG_ROTATION_TAG;
break;
+
case LSM6DSR_ROTATION_TAG:
*val = LSM6DSR_ROTATION_TAG;
break;
+
case LSM6DSR_SENSORHUB_NACK_TAG:
*val = LSM6DSR_SENSORHUB_NACK_TAG;
break;
+
default:
*val = LSM6DSR_SENSORHUB_NACK_TAG;
break;
}
+
return ret;
}
@@ -6568,18 +7587,25 @@ int32_t lsm6dsr_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_FIFO_CFG,
- (uint8_t*)&emb_func_fifo_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_FIFO_CFG,
+ (uint8_t *)&emb_func_fifo_cfg, 1);
}
- if(ret == 0){
- emb_func_fifo_cfg.pedo_fifo_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ emb_func_fifo_cfg.pedo_fifo_en = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_FIFO_CFG,
- (uint8_t*)&emb_func_fifo_cfg, 1);
+ (uint8_t *)&emb_func_fifo_cfg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -6598,14 +7624,19 @@ int32_t lsm6dsr_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_FIFO_CFG,
- (uint8_t*)&emb_func_fifo_cfg, 1);
+ (uint8_t *)&emb_func_fifo_cfg, 1);
*val = emb_func_fifo_cfg.pedo_fifo_en;
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -6624,18 +7655,24 @@ int32_t lsm6dsr_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val)
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
- slv0_config. batch_ext_sens_0_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ slv0_config. batch_ext_sens_0_en = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -6655,14 +7692,18 @@ int32_t lsm6dsr_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val)
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = slv0_config. batch_ext_sens_0_en;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -6681,18 +7722,25 @@ int32_t lsm6dsr_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV1_CONFIG,
- (uint8_t*)&slv1_config, 1);
+ (uint8_t *)&slv1_config, 1);
}
- if(ret == 0){
- slv1_config. batch_ext_sens_1_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ slv1_config. batch_ext_sens_1_en = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV1_CONFIG,
- (uint8_t*)&slv1_config, 1);
+ (uint8_t *)&slv1_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -6712,14 +7760,18 @@ int32_t lsm6dsr_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val)
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV1_CONFIG,
- (uint8_t*)&slv1_config, 1);
+ (uint8_t *)&slv1_config, 1);
*val = slv1_config. batch_ext_sens_1_en;
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -6739,18 +7791,24 @@ int32_t lsm6dsr_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val)
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV2_CONFIG,
- (uint8_t*)&slv2_config, 1);
+ (uint8_t *)&slv2_config, 1);
}
- if(ret == 0){
- slv2_config. batch_ext_sens_2_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ slv2_config. batch_ext_sens_2_en = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV2_CONFIG,
- (uint8_t*)&slv2_config, 1);
+ (uint8_t *)&slv2_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -6769,14 +7827,19 @@ int32_t lsm6dsr_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV2_CONFIG,
- (uint8_t*)&slv2_config, 1);
+ (uint8_t *)&slv2_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = slv2_config. batch_ext_sens_2_en;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -6795,18 +7858,25 @@ int32_t lsm6dsr_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV3_CONFIG,
- (uint8_t*)&slv3_config, 1);
+ (uint8_t *)&slv3_config, 1);
}
- if(ret == 0){
- slv3_config. batch_ext_sens_3_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ slv3_config. batch_ext_sens_3_en = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV3_CONFIG,
- (uint8_t*)&slv3_config, 1);
+ (uint8_t *)&slv3_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -6826,14 +7896,18 @@ int32_t lsm6dsr_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val)
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV3_CONFIG,
- (uint8_t*)&slv3_config, 1);
+ (uint8_t *)&slv3_config, 1);
*val = slv3_config. batch_ext_sens_3_en;
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -6858,16 +7932,20 @@ int32_t lsm6dsr_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_den_mode_set(stmdev_ctx_t *ctx, lsm6dsr_den_mode_t val)
+int32_t lsm6dsr_den_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsr_den_mode_t val)
{
lsm6dsr_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
- ctrl6_c.den_mode= (uint8_t)val;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl6_c.den_mode = (uint8_t)val;
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -6880,33 +7958,40 @@ int32_t lsm6dsr_den_mode_set(stmdev_ctx_t *ctx, lsm6dsr_den_mode_t val)
*
*/
int32_t lsm6dsr_den_mode_get(stmdev_ctx_t *ctx,
- lsm6dsr_den_mode_t *val)
+ lsm6dsr_den_mode_t *val)
{
lsm6dsr_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
- switch (ctrl6_c.den_mode){
+ switch (ctrl6_c.den_mode)
+ {
case LSM6DSR_DEN_DISABLE:
*val = LSM6DSR_DEN_DISABLE;
break;
+
case LSM6DSR_LEVEL_FIFO:
*val = LSM6DSR_LEVEL_FIFO;
break;
+
case LSM6DSR_LEVEL_LETCHED:
*val = LSM6DSR_LEVEL_LETCHED;
break;
+
case LSM6DSR_LEVEL_TRIGGER:
*val = LSM6DSR_LEVEL_TRIGGER;
break;
+
case LSM6DSR_EDGE_TRIGGER:
*val = LSM6DSR_EDGE_TRIGGER;
break;
+
default:
*val = LSM6DSR_DEN_DISABLE;
break;
}
+
return ret;
}
@@ -6919,17 +8004,20 @@ int32_t lsm6dsr_den_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_den_polarity_set(stmdev_ctx_t *ctx,
- lsm6dsr_den_lh_t val)
+ lsm6dsr_den_lh_t val)
{
lsm6dsr_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
- ctrl9_xl.den_lh= (uint8_t)val;
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl9_xl.den_lh = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
+ (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -6942,24 +8030,28 @@ int32_t lsm6dsr_den_polarity_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_den_polarity_get(stmdev_ctx_t *ctx,
- lsm6dsr_den_lh_t *val)
+ lsm6dsr_den_lh_t *val)
{
lsm6dsr_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
- switch (ctrl9_xl.den_lh){
+ switch (ctrl9_xl.den_lh)
+ {
case LSM6DSR_DEN_ACT_LOW:
*val = LSM6DSR_DEN_ACT_LOW;
break;
+
case LSM6DSR_DEN_ACT_HIGH:
*val = LSM6DSR_DEN_ACT_HIGH;
break;
+
default:
*val = LSM6DSR_DEN_ACT_LOW;
break;
}
+
return ret;
}
@@ -6972,17 +8064,20 @@ int32_t lsm6dsr_den_polarity_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_den_enable_set(stmdev_ctx_t *ctx,
- lsm6dsr_den_xl_g_t val)
+ lsm6dsr_den_xl_g_t val)
{
lsm6dsr_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
- ctrl9_xl.den_xl_g= (uint8_t)val;
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl9_xl.den_xl_g = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
+ (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -6995,27 +8090,32 @@ int32_t lsm6dsr_den_enable_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_den_enable_get(stmdev_ctx_t *ctx,
- lsm6dsr_den_xl_g_t *val)
+ lsm6dsr_den_xl_g_t *val)
{
lsm6dsr_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
- switch (ctrl9_xl.den_xl_g){
+ switch (ctrl9_xl.den_xl_g)
+ {
case LSM6DSR_STAMP_IN_GY_DATA:
*val = LSM6DSR_STAMP_IN_GY_DATA;
break;
+
case LSM6DSR_STAMP_IN_XL_DATA:
*val = LSM6DSR_STAMP_IN_XL_DATA;
break;
+
case LSM6DSR_STAMP_IN_GY_XL_DATA:
*val = LSM6DSR_STAMP_IN_GY_XL_DATA;
break;
+
default:
*val = LSM6DSR_STAMP_IN_GY_DATA;
break;
}
+
return ret;
}
@@ -7032,12 +8132,15 @@ int32_t lsm6dsr_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsr_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
- ctrl9_xl.den_z= (uint8_t)val;
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl9_xl.den_z = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
+ (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -7054,7 +8157,7 @@ int32_t lsm6dsr_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsr_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
*val = ctrl9_xl.den_z;
return ret;
@@ -7073,12 +8176,15 @@ int32_t lsm6dsr_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsr_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
- ctrl9_xl.den_y= (uint8_t)val;
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl9_xl.den_y = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
+ (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -7095,7 +8201,7 @@ int32_t lsm6dsr_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsr_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
*val = ctrl9_xl.den_y;
return ret;
@@ -7114,11 +8220,14 @@ int32_t lsm6dsr_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsr_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
- ctrl9_xl.den_x= (uint8_t)val;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl9_xl.den_x = (uint8_t)val;
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -7135,7 +8244,7 @@ int32_t lsm6dsr_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsr_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
*val = ctrl9_xl.den_x;
return ret;
@@ -7168,18 +8277,24 @@ int32_t lsm6dsr_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val)
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
+ (uint8_t *)&emb_func_en_a, 1);
}
- if(ret == 0){
- emb_func_en_a.pedo_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ emb_func_en_a.pedo_en = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
+ (uint8_t *)&emb_func_en_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -7198,14 +8313,18 @@ int32_t lsm6dsr_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
+ (uint8_t *)&emb_func_en_a, 1);
*val = emb_func_en_a.pedo_en;
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -7220,7 +8339,8 @@ int32_t lsm6dsr_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_pedo_mode_set(stmdev_ctx_t *ctx, lsm6dsr_pedo_mode_t val)
+int32_t lsm6dsr_pedo_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsr_pedo_mode_t val)
{
lsm6dsr_adv_pedo_t adv_pedo;
lsm6dsr_emb_func_en_b_t emb_func_en_b;
@@ -7228,35 +8348,50 @@ int32_t lsm6dsr_pedo_mode_set(stmdev_ctx_t *ctx, lsm6dsr_pedo_mode_t val)
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_ADV_PEDO, (uint8_t*)&adv_pedo, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_ADV_PEDO, (uint8_t *)&adv_pedo, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
adv_pedo.pedo_fpr_adf_dis = (~((uint8_t)val) & 0x01U);
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_ADV_PEDO, (uint8_t*)&adv_pedo, 1);
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_ADV_PEDO, (uint8_t *)&adv_pedo, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
emb_func_en_b.pedo_adv_en = (uint8_t)val & 0x01U;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_CMD_REG,
- (uint8_t*)&pedo_cmd_reg);
+ (uint8_t *)&pedo_cmd_reg);
pedo_cmd_reg.fp_rejection_en = ((uint8_t)val & 0x01U);
- pedo_cmd_reg.ad_det_en = ((uint8_t)val & 0x02U)>>1;
+ pedo_cmd_reg.ad_det_en = ((uint8_t)val & 0x02U) >> 1;
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_PEDO_CMD_REG,
- (uint8_t*)&pedo_cmd_reg);
+ (uint8_t *)&pedo_cmd_reg);
}
+
return ret;
}
@@ -7271,28 +8406,35 @@ int32_t lsm6dsr_pedo_mode_set(stmdev_ctx_t *ctx, lsm6dsr_pedo_mode_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_pedo_mode_get(stmdev_ctx_t *ctx, lsm6dsr_pedo_mode_t *val)
+int32_t lsm6dsr_pedo_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsr_pedo_mode_t *val)
{
lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg;
int32_t ret;
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_CMD_REG,
- (uint8_t*)&pedo_cmd_reg);
+ (uint8_t *)&pedo_cmd_reg);
- switch ((pedo_cmd_reg.ad_det_en << 1) | pedo_cmd_reg.fp_rejection_en){
+ switch ((pedo_cmd_reg.ad_det_en << 1) |
+ pedo_cmd_reg.fp_rejection_en)
+ {
case LSM6DSR_PEDO_BASE:
*val = LSM6DSR_PEDO_BASE;
break;
+
case LSM6DSR_PEDO_BASE_FALSE_STEP_REJ:
*val = LSM6DSR_PEDO_BASE_FALSE_STEP_REJ;
break;
+
case LSM6DSR_PEDO_ADV_FALSE_STEP_REJ:
*val = LSM6DSR_PEDO_ADV_FALSE_STEP_REJ;
break;
+
default:
*val = LSM6DSR_PEDO_BASE;
break;
}
+
return ret;
}
@@ -7311,14 +8453,18 @@ int32_t lsm6dsr_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val)
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_STATUS,
- (uint8_t*)&emb_func_status, 1);
+ (uint8_t *)&emb_func_status, 1);
*val = emb_func_status.is_step_det;
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -7330,10 +8476,14 @@ int32_t lsm6dsr_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsr_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
- ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_PEDO_DEB_STEPS_CONF, buff);
+
+ ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_PEDO_DEB_STEPS_CONF,
+ buff);
+
return ret;
}
@@ -7345,10 +8495,13 @@ int32_t lsm6dsr_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsr_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_DEB_STEPS_CONF, buff);
+
return ret;
}
@@ -7360,18 +8513,22 @@ int32_t lsm6dsr_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_pedo_steps_period_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsr_pedo_steps_period_set(stmdev_ctx_t *ctx, uint16_t val)
{
+ uint8_t buff[2];
int32_t ret;
- uint8_t i;
- i = 0x00U;
- ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_PEDO_SC_DELTAT_L, &buff[i]);
- if(ret == 0){
- i++;
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
+ ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_PEDO_SC_DELTAT_L,
+ &buff[0]);
+
+ if (ret == 0)
+ {
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_PEDO_SC_DELTAT_H,
- &buff[i]);
+ &buff[1]);
}
+
return ret;
}
@@ -7383,17 +8540,23 @@ int32_t lsm6dsr_pedo_steps_period_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_pedo_steps_period_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsr_pedo_steps_period_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
- uint8_t i;
- i = 0x00U;
- ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_SC_DELTAT_L, &buff[i]);
- if(ret == 0){
- i++;
- ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_SC_DELTAT_H, &buff[i]);
+ ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_SC_DELTAT_L,
+ &buff[0]);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_SC_DELTAT_H,
+ &buff[1]);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
}
+
return ret;
}
@@ -7411,13 +8574,15 @@ int32_t lsm6dsr_pedo_adv_detection_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_CMD_REG,
- (uint8_t*)&pedo_cmd_reg);
+ (uint8_t *)&pedo_cmd_reg);
- if(ret == 0){
- pedo_cmd_reg.ad_det_en= (uint8_t)val;
+ if (ret == 0)
+ {
+ pedo_cmd_reg.ad_det_en = (uint8_t)val;
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_PEDO_CMD_REG,
- (uint8_t*)&pedo_cmd_reg);
+ (uint8_t *)&pedo_cmd_reg);
}
+
return ret;
}
@@ -7429,12 +8594,14 @@ int32_t lsm6dsr_pedo_adv_detection_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_pedo_adv_detection_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsr_pedo_adv_detection_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg;
int32_t ret;
- ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_CMD_REG, (uint8_t*)&pedo_cmd_reg);
+ ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_CMD_REG,
+ (uint8_t *)&pedo_cmd_reg);
*val = pedo_cmd_reg.ad_det_en;
return ret;
@@ -7449,19 +8616,21 @@ int32_t lsm6dsr_pedo_adv_detection_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsr_pedo_false_step_rejection_set(stmdev_ctx_t *ctx,
- uint8_t val)
+ uint8_t val)
{
lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg;
int32_t ret;
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_CMD_REG,
- (uint8_t*)&pedo_cmd_reg);
+ (uint8_t *)&pedo_cmd_reg);
- if(ret == 0){
- pedo_cmd_reg.fp_rejection_en= (uint8_t)val;
+ if (ret == 0)
+ {
+ pedo_cmd_reg.fp_rejection_en = (uint8_t)val;
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_PEDO_CMD_REG,
- (uint8_t*)&pedo_cmd_reg);
+ (uint8_t *)&pedo_cmd_reg);
}
+
return ret;
}
@@ -7474,13 +8643,13 @@ int32_t lsm6dsr_pedo_false_step_rejection_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_pedo_false_step_rejection_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg;
int32_t ret;
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_CMD_REG,
- (uint8_t*)&pedo_cmd_reg);
+ (uint8_t *)&pedo_cmd_reg);
*val = pedo_cmd_reg.fp_rejection_en;
return ret;
@@ -7496,19 +8665,21 @@ int32_t lsm6dsr_pedo_false_step_rejection_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_pedo_int_mode_set(stmdev_ctx_t *ctx,
- lsm6dsr_carry_count_en_t val)
+ lsm6dsr_carry_count_en_t val)
{
lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg;
int32_t ret;
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_CMD_REG,
- (uint8_t*)&pedo_cmd_reg);
+ (uint8_t *)&pedo_cmd_reg);
- if(ret == 0){
- pedo_cmd_reg.carry_count_en= (uint8_t)val;
+ if (ret == 0)
+ {
+ pedo_cmd_reg.carry_count_en = (uint8_t)val;
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_PEDO_CMD_REG,
- (uint8_t*)&pedo_cmd_reg);
+ (uint8_t *)&pedo_cmd_reg);
}
+
return ret;
}
@@ -7522,25 +8693,29 @@ int32_t lsm6dsr_pedo_int_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_pedo_int_mode_get(stmdev_ctx_t *ctx,
- lsm6dsr_carry_count_en_t *val)
+ lsm6dsr_carry_count_en_t *val)
{
lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg;
int32_t ret;
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_CMD_REG,
- (uint8_t*)&pedo_cmd_reg);
+ (uint8_t *)&pedo_cmd_reg);
- switch (pedo_cmd_reg.carry_count_en){
+ switch (pedo_cmd_reg.carry_count_en)
+ {
case LSM6DSR_EVERY_STEP:
*val = LSM6DSR_EVERY_STEP;
break;
+
case LSM6DSR_COUNT_OVERFLOW:
*val = LSM6DSR_COUNT_OVERFLOW;
break;
+
default:
*val = LSM6DSR_EVERY_STEP;
break;
}
+
return ret;
}
@@ -7572,18 +8747,24 @@ int32_t lsm6dsr_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val)
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
+ (uint8_t *)&emb_func_en_a, 1);
}
- if(ret == 0){
- emb_func_en_a.sign_motion_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ emb_func_en_a.sign_motion_en = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
+ (uint8_t *)&emb_func_en_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -7602,14 +8783,18 @@ int32_t lsm6dsr_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
+ (uint8_t *)&emb_func_en_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = emb_func_en_a.sign_motion_en;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -7622,20 +8807,25 @@ int32_t lsm6dsr_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsr_motion_flag_data_ready_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
lsm6dsr_emb_func_status_t emb_func_status;
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_STATUS,
- (uint8_t*)&emb_func_status, 1);
+ (uint8_t *)&emb_func_status, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = emb_func_status.is_sigmot;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -7666,18 +8856,25 @@ int32_t lsm6dsr_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
+ (uint8_t *)&emb_func_en_a, 1);
}
- if(ret == 0){
- emb_func_en_a.tilt_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ emb_func_en_a.tilt_en = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
+ (uint8_t *)&emb_func_en_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -7695,13 +8892,19 @@ int32_t lsm6dsr_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_A, (uint8_t*)&emb_func_en_a, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_A,
+ (uint8_t *)&emb_func_en_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = emb_func_en_a.tilt_en;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -7713,20 +8916,26 @@ int32_t lsm6dsr_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsr_tilt_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsr_emb_func_status_t emb_func_status;
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_STATUS,
- (uint8_t*)&emb_func_status, 1);
+ (uint8_t *)&emb_func_status, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = emb_func_status.is_tilt;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -7751,20 +8960,22 @@ int32_t lsm6dsr_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_mag_sensitivity_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsr_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val)
{
+ uint8_t buff[2];
int32_t ret;
- uint8_t i;
- i = 0x00U;
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SENSITIVITY_L,
- &buff[i]);
+ &buff[0]);
- if(ret == 0){
- i++;
+ if (ret == 0)
+ {
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SENSITIVITY_H,
- &buff[i]);
+ &buff[1]);
}
+
return ret;
}
@@ -7776,18 +8987,22 @@ int32_t lsm6dsr_mag_sensitivity_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_mag_sensitivity_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsr_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
- uint8_t i;
- i = 0x00U;
- ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SENSITIVITY_L, &buff[i]);
+ ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SENSITIVITY_L,
+ &buff[0]);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SENSITIVITY_H,
+ &buff[1]);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
+ }
-if(ret == 0){
- i++;
- ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SENSITIVITY_H, &buff[i]);
-}
return ret;
}
@@ -7799,33 +9014,51 @@ if(ret == 0){
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_mag_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsr_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
- uint8_t i;
+ uint8_t i;
+ buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
+ buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
+ buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
+ buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
+ buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
+ buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
i = 0x00U;
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_OFFX_L, &buff[i]);
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_OFFX_H, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_OFFY_L, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_OFFY_H, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_OFFZ_L, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_OFFZ_H, &buff[i]);
}
+
return ret;
}
@@ -7837,34 +9070,51 @@ int32_t lsm6dsr_mag_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_mag_offset_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsr_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
- uint8_t i;
+ uint8_t i;
i = 0x00U;
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_OFFX_L, &buff[i]);
- if(ret == 0){
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_OFFX_H, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_OFFY_L, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_OFFY_H, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_OFFZ_L, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_OFFZ_H, &buff[i]);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
}
+
return ret;
}
@@ -7881,57 +9131,93 @@ int32_t lsm6dsr_mag_offset_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsr_mag_soft_iron_set(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[12];
int32_t ret;
- uint8_t i;
+ buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
+ buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
+ buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
+ buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
+ buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
+ buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
+ buff[7] = (uint8_t)((uint16_t)val[3] / 256U);
+ buff[6] = (uint8_t)((uint16_t)val[3] - (buff[7] * 256U));
+ buff[9] = (uint8_t)((uint16_t)val[4] / 256U);
+ buff[8] = (uint8_t)((uint16_t)val[4] - (buff[9] * 256U));
+ buff[11] = (uint8_t)((uint16_t)val[5] / 256U);
+ buff[10] = (uint8_t)((uint16_t)val[5] - (buff[11] * 256U));
+ uint8_t i;
i = 0x00U;
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_XX_L, &buff[i]);
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_XX_H, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_XY_L, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_XY_H, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_XZ_L, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_XZ_H, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_YY_L, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_YY_H, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_YZ_L, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_YZ_H, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_ZZ_L, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_ZZ_H, &buff[i]);
}
+
return ret;
}
@@ -7948,57 +9234,94 @@ int32_t lsm6dsr_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsr_mag_soft_iron_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[12];
int32_t ret;
- uint8_t i;
+ uint8_t i;
i = 0x00U;
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_XX_L, &buff[i]);
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_XX_H, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_XY_L, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_XY_H, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_XZ_L, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_XZ_H, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_YY_L, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_YY_H, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_YZ_L, &buff[i]);
- }
- if(ret == 0){
+ }
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_YZ_H, &buff[i]);
- }
- if(ret == 0){
+ }
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_ZZ_L, &buff[i]);
- }
- if(ret == 0){
+ }
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_ZZ_H, &buff[i]);
}
+
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+ val[3] = (int16_t)buff[7];
+ val[3] = (val[3] * 256) + (int16_t)buff[6];
+ val[4] = (int16_t)buff[9];
+ val[4] = (val[4] * 256) + (int16_t)buff[8];
+ val[5] = (int16_t)buff[11];
+ val[5] = (val[5] * 256) + (int16_t)buff[10];
+
return ret;
}
@@ -8012,19 +9335,21 @@ int32_t lsm6dsr_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
*/
int32_t lsm6dsr_mag_z_orient_set(stmdev_ctx_t *ctx,
- lsm6dsr_mag_z_axis_t val)
+ lsm6dsr_mag_z_axis_t val)
{
lsm6dsr_mag_cfg_a_t mag_cfg_a;
int32_t ret;
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_CFG_A,
- (uint8_t*)&mag_cfg_a);
+ (uint8_t *)&mag_cfg_a);
- if(ret == 0){
- mag_cfg_a.mag_z_axis= (uint8_t)val;
+ if (ret == 0)
+ {
+ mag_cfg_a.mag_z_axis = (uint8_t)val;
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_CFG_A,
- (uint8_t*)&mag_cfg_a);
+ (uint8_t *)&mag_cfg_a);
}
+
return ret;
}
@@ -8038,36 +9363,45 @@ int32_t lsm6dsr_mag_z_orient_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_mag_z_orient_get(stmdev_ctx_t *ctx,
- lsm6dsr_mag_z_axis_t *val)
+ lsm6dsr_mag_z_axis_t *val)
{
lsm6dsr_mag_cfg_a_t mag_cfg_a;
int32_t ret;
+
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_CFG_A,
- (uint8_t*)&mag_cfg_a);
+ (uint8_t *)&mag_cfg_a);
- switch (mag_cfg_a.mag_z_axis){
+ switch (mag_cfg_a.mag_z_axis)
+ {
case LSM6DSR_Z_EQ_Y:
*val = LSM6DSR_Z_EQ_Y;
break;
+
case LSM6DSR_Z_EQ_MIN_Y:
*val = LSM6DSR_Z_EQ_MIN_Y;
break;
+
case LSM6DSR_Z_EQ_X:
*val = LSM6DSR_Z_EQ_X;
break;
+
case LSM6DSR_Z_EQ_MIN_X:
*val = LSM6DSR_Z_EQ_MIN_X;
break;
+
case LSM6DSR_Z_EQ_MIN_Z:
*val = LSM6DSR_Z_EQ_MIN_Z;
break;
+
case LSM6DSR_Z_EQ_Z:
*val = LSM6DSR_Z_EQ_Z;
break;
+
default:
*val = LSM6DSR_Z_EQ_Y;
break;
}
+
return ret;
}
@@ -8082,18 +9416,21 @@ int32_t lsm6dsr_mag_z_orient_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_mag_y_orient_set(stmdev_ctx_t *ctx,
- lsm6dsr_mag_y_axis_t val)
+ lsm6dsr_mag_y_axis_t val)
{
lsm6dsr_mag_cfg_a_t mag_cfg_a;
int32_t ret;
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_CFG_A,
- (uint8_t*)&mag_cfg_a);
- if(ret == 0){
- mag_cfg_a.mag_y_axis= (uint8_t)val;
+ (uint8_t *)&mag_cfg_a);
+
+ if (ret == 0)
+ {
+ mag_cfg_a.mag_y_axis = (uint8_t)val;
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_CFG_A,
- (uint8_t*)&mag_cfg_a);
+ (uint8_t *)&mag_cfg_a);
}
+
return ret;
}
@@ -8107,37 +9444,45 @@ int32_t lsm6dsr_mag_y_orient_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_mag_y_orient_get(stmdev_ctx_t *ctx,
- lsm6dsr_mag_y_axis_t *val)
+ lsm6dsr_mag_y_axis_t *val)
{
lsm6dsr_mag_cfg_a_t mag_cfg_a;
int32_t ret;
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_CFG_A,
- (uint8_t*)&mag_cfg_a);
+ (uint8_t *)&mag_cfg_a);
- switch (mag_cfg_a.mag_y_axis){
+ switch (mag_cfg_a.mag_y_axis)
+ {
case LSM6DSR_Y_EQ_Y:
*val = LSM6DSR_Y_EQ_Y;
break;
+
case LSM6DSR_Y_EQ_MIN_Y:
*val = LSM6DSR_Y_EQ_MIN_Y;
break;
+
case LSM6DSR_Y_EQ_X:
*val = LSM6DSR_Y_EQ_X;
break;
+
case LSM6DSR_Y_EQ_MIN_X:
*val = LSM6DSR_Y_EQ_MIN_X;
break;
+
case LSM6DSR_Y_EQ_MIN_Z:
*val = LSM6DSR_Y_EQ_MIN_Z;
break;
+
case LSM6DSR_Y_EQ_Z:
*val = LSM6DSR_Y_EQ_Z;
break;
+
default:
*val = LSM6DSR_Y_EQ_Y;
break;
}
+
return ret;
}
@@ -8151,18 +9496,21 @@ int32_t lsm6dsr_mag_y_orient_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_mag_x_orient_set(stmdev_ctx_t *ctx,
- lsm6dsr_mag_x_axis_t val)
+ lsm6dsr_mag_x_axis_t val)
{
lsm6dsr_mag_cfg_b_t mag_cfg_b;
int32_t ret;
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_CFG_B,
- (uint8_t*)&mag_cfg_b);
- if(ret == 0){
- mag_cfg_b.mag_x_axis= (uint8_t)val;
+ (uint8_t *)&mag_cfg_b);
+
+ if (ret == 0)
+ {
+ mag_cfg_b.mag_x_axis = (uint8_t)val;
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_CFG_B,
- (uint8_t*)&mag_cfg_b);
+ (uint8_t *)&mag_cfg_b);
}
+
return ret;
}
@@ -8176,37 +9524,45 @@ int32_t lsm6dsr_mag_x_orient_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_mag_x_orient_get(stmdev_ctx_t *ctx,
- lsm6dsr_mag_x_axis_t *val)
+ lsm6dsr_mag_x_axis_t *val)
{
lsm6dsr_mag_cfg_b_t mag_cfg_b;
int32_t ret;
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_CFG_B,
- (uint8_t*)&mag_cfg_b);
+ (uint8_t *)&mag_cfg_b);
- switch (mag_cfg_b.mag_x_axis){
+ switch (mag_cfg_b.mag_x_axis)
+ {
case LSM6DSR_X_EQ_Y:
*val = LSM6DSR_X_EQ_Y;
break;
+
case LSM6DSR_X_EQ_MIN_Y:
*val = LSM6DSR_X_EQ_MIN_Y;
break;
+
case LSM6DSR_X_EQ_X:
*val = LSM6DSR_X_EQ_X;
break;
+
case LSM6DSR_X_EQ_MIN_X:
*val = LSM6DSR_X_EQ_MIN_X;
break;
+
case LSM6DSR_X_EQ_MIN_Z:
*val = LSM6DSR_X_EQ_MIN_Z;
break;
+
case LSM6DSR_X_EQ_Z:
*val = LSM6DSR_X_EQ_Z;
break;
+
default:
*val = LSM6DSR_X_EQ_Y;
break;
}
+
return ret;
}
@@ -8233,20 +9589,25 @@ int32_t lsm6dsr_mag_x_orient_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
lsm6dsr_emb_func_status_t emb_func_status;
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_STATUS,
- (uint8_t*)&emb_func_status, 1);
+ (uint8_t *)&emb_func_status, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = emb_func_status.is_fsm_lc;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -8261,22 +9622,28 @@ int32_t lsm6dsr_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
int32_t lsm6dsr_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val)
{
int32_t ret;
- lsm6dsr_emb_func_en_b_t emb_func_en_b;
+ lsm6dsr_emb_func_en_b_t emb_func_en_b;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if(ret == 0){
- emb_func_en_b.fsm_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ emb_func_en_b.fsm_en = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -8291,21 +9658,28 @@ int32_t lsm6dsr_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t lsm6dsr_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val)
{
int32_t ret;
- lsm6dsr_emb_func_en_b_t emb_func_en_b;
+ lsm6dsr_emb_func_en_b_t emb_func_en_b;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = emb_func_en_b.fsm_en;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -8318,54 +9692,70 @@ int32_t lsm6dsr_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsr_fsm_enable_set(stmdev_ctx_t *ctx,
- lsm6dsr_emb_fsm_enable_t *val)
+ lsm6dsr_emb_fsm_enable_t *val)
{
lsm6dsr_emb_func_en_b_t emb_func_en_b;
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_write_reg(ctx, LSM6DSR_FSM_ENABLE_A,
- (uint8_t*)&val->fsm_enable_a, 1);
+ (uint8_t *)&val->fsm_enable_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_write_reg(ctx, LSM6DSR_FSM_ENABLE_B,
- (uint8_t*)&val->fsm_enable_b, 1);
+ (uint8_t *)&val->fsm_enable_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
- }
- if(ret == 0){
- if ( (val->fsm_enable_a.fsm1_en |
- val->fsm_enable_a.fsm2_en |
- val->fsm_enable_a.fsm3_en |
- val->fsm_enable_a.fsm4_en |
- val->fsm_enable_a.fsm5_en |
- val->fsm_enable_a.fsm6_en |
- val->fsm_enable_a.fsm7_en |
- val->fsm_enable_a.fsm8_en |
- val->fsm_enable_b.fsm9_en |
- val->fsm_enable_b.fsm10_en |
- val->fsm_enable_b.fsm11_en |
- val->fsm_enable_b.fsm12_en |
- val->fsm_enable_b.fsm13_en |
- val->fsm_enable_b.fsm14_en |
- val->fsm_enable_b.fsm15_en |
- val->fsm_enable_b.fsm16_en ) != PROPERTY_DISABLE){
+ (uint8_t *)&emb_func_en_b, 1);
+ }
+
+ if (ret == 0)
+ {
+ if ((val->fsm_enable_a.fsm1_en |
+ val->fsm_enable_a.fsm2_en |
+ val->fsm_enable_a.fsm3_en |
+ val->fsm_enable_a.fsm4_en |
+ val->fsm_enable_a.fsm5_en |
+ val->fsm_enable_a.fsm6_en |
+ val->fsm_enable_a.fsm7_en |
+ val->fsm_enable_a.fsm8_en |
+ val->fsm_enable_b.fsm9_en |
+ val->fsm_enable_b.fsm10_en |
+ val->fsm_enable_b.fsm11_en |
+ val->fsm_enable_b.fsm12_en |
+ val->fsm_enable_b.fsm13_en |
+ val->fsm_enable_b.fsm14_en |
+ val->fsm_enable_b.fsm15_en |
+ val->fsm_enable_b.fsm16_en) != PROPERTY_DISABLE)
+ {
emb_func_en_b.fsm_en = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
emb_func_en_b.fsm_en = PROPERTY_DISABLE;
}
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -8378,22 +9768,29 @@ int32_t lsm6dsr_fsm_enable_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_fsm_enable_get(stmdev_ctx_t *ctx,
- lsm6dsr_emb_fsm_enable_t *val)
+ lsm6dsr_emb_fsm_enable_t *val)
{
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_ENABLE_A,
- (uint8_t*)&val->fsm_enable_a, 1);
+ (uint8_t *)&val->fsm_enable_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_ENABLE_B,
- (uint8_t*)&val->fsm_enable_b, 1);
+ (uint8_t *)&val->fsm_enable_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -8406,17 +9803,25 @@ int32_t lsm6dsr_fsm_enable_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_long_cnt_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsr_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val)
{
+ uint8_t buff[2];
int32_t ret;
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_write_reg(ctx, LSM6DSR_FSM_LONG_COUNTER_L, buff, 2);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -8429,17 +9834,25 @@ int32_t lsm6dsr_long_cnt_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_long_cnt_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsr_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_LONG_COUNTER_L, buff, 2);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
}
+
return ret;
}
@@ -8453,24 +9866,31 @@ int32_t lsm6dsr_long_cnt_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
*/
int32_t lsm6dsr_long_clr_set(stmdev_ctx_t *ctx,
- lsm6dsr_fsm_lc_clr_t val)
+ lsm6dsr_fsm_lc_clr_t val)
{
lsm6dsr_fsm_long_counter_clear_t fsm_long_counter_clear;
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_LONG_COUNTER_CLEAR,
- (uint8_t*)&fsm_long_counter_clear, 1);
+ (uint8_t *)&fsm_long_counter_clear, 1);
}
- if(ret == 0){
- fsm_long_counter_clear.fsm_lc_clr= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ fsm_long_counter_clear.fsm_lc_clr = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_FSM_LONG_COUNTER_CLEAR,
- (uint8_t*)&fsm_long_counter_clear, 1);
+ (uint8_t *)&fsm_long_counter_clear, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -8483,34 +9903,43 @@ int32_t lsm6dsr_long_clr_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_long_clr_get(stmdev_ctx_t *ctx,
- lsm6dsr_fsm_lc_clr_t *val)
+ lsm6dsr_fsm_lc_clr_t *val)
{
lsm6dsr_fsm_long_counter_clear_t fsm_long_counter_clear;
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_LONG_COUNTER_CLEAR,
- (uint8_t*)&fsm_long_counter_clear, 1);
+ (uint8_t *)&fsm_long_counter_clear, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
- switch (fsm_long_counter_clear.fsm_lc_clr){
+
+ switch (fsm_long_counter_clear.fsm_lc_clr)
+ {
case LSM6DSR_LC_NORMAL:
*val = LSM6DSR_LC_NORMAL;
break;
+
case LSM6DSR_LC_CLEAR:
*val = LSM6DSR_LC_CLEAR;
break;
+
case LSM6DSR_LC_CLEAR_DONE:
*val = LSM6DSR_LC_CLEAR_DONE;
break;
+
default:
*val = LSM6DSR_LC_NORMAL;
break;
}
+
return ret;
}
@@ -8528,13 +9957,17 @@ int32_t lsm6dsr_fsm_out_get(stmdev_ctx_t *ctx, lsm6dsr_fsm_out_t *val)
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_OUTS1,
- (uint8_t*)&val->fsm_outs1, 16);
+ (uint8_t *)&val->fsm_outs1, 16);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -8547,27 +9980,33 @@ int32_t lsm6dsr_fsm_out_get(stmdev_ctx_t *ctx, lsm6dsr_fsm_out_t *val)
*
*/
int32_t lsm6dsr_fsm_data_rate_set(stmdev_ctx_t *ctx,
- lsm6dsr_fsm_odr_t val)
+ lsm6dsr_fsm_odr_t val)
{
lsm6dsr_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_ODR_CFG_B,
- (uint8_t*)&emb_func_odr_cfg_b, 1);
+ (uint8_t *)&emb_func_odr_cfg_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
emb_func_odr_cfg_b.not_used_01 = 3; /* set default values */
emb_func_odr_cfg_b.not_used_02 = 1; /* set default values */
- emb_func_odr_cfg_b.fsm_odr= (uint8_t)val;
+ emb_func_odr_cfg_b.fsm_odr = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_ODR_CFG_B,
- (uint8_t*)&emb_func_odr_cfg_b, 1);
- }
- if(ret == 0){
+ (uint8_t *)&emb_func_odr_cfg_b, 1);
+ }
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -8580,37 +10019,47 @@ int32_t lsm6dsr_fsm_data_rate_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_fsm_data_rate_get(stmdev_ctx_t *ctx,
- lsm6dsr_fsm_odr_t *val)
+ lsm6dsr_fsm_odr_t *val)
{
lsm6dsr_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_ODR_CFG_B,
- (uint8_t*)&emb_func_odr_cfg_b, 1);
+ (uint8_t *)&emb_func_odr_cfg_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
- switch (emb_func_odr_cfg_b.fsm_odr){
+
+ switch (emb_func_odr_cfg_b.fsm_odr)
+ {
case LSM6DSR_ODR_FSM_12Hz5:
*val = LSM6DSR_ODR_FSM_12Hz5;
break;
+
case LSM6DSR_ODR_FSM_26Hz:
*val = LSM6DSR_ODR_FSM_26Hz;
break;
+
case LSM6DSR_ODR_FSM_52Hz:
*val = LSM6DSR_ODR_FSM_52Hz;
break;
+
case LSM6DSR_ODR_FSM_104Hz:
*val = LSM6DSR_ODR_FSM_104Hz;
break;
+
default:
*val = LSM6DSR_ODR_FSM_12Hz5;
break;
}
+
return ret;
}
@@ -8629,18 +10078,24 @@ int32_t lsm6dsr_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val)
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_INIT_B,
- (uint8_t*)&emb_func_init_b, 1);
+ (uint8_t *)&emb_func_init_b, 1);
}
- if(ret == 0){
- emb_func_init_b.fsm_init= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ emb_func_init_b.fsm_init = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_INIT_B,
- (uint8_t*)&emb_func_init_b, 1);
+ (uint8_t *)&emb_func_init_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -8658,14 +10113,19 @@ int32_t lsm6dsr_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_INIT_B,
- (uint8_t*)&emb_func_init_b, 1);
+ (uint8_t *)&emb_func_init_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = emb_func_init_b.fsm_init;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -8680,19 +10140,23 @@ int32_t lsm6dsr_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsr_long_cnt_int_value_set(stmdev_ctx_t *ctx,
+ uint16_t val)
{
+ uint8_t buff[2];
int32_t ret;
- uint8_t i;
- i = 0x00U;
- ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_FSM_LC_TIMEOUT_L, &buff[i]);
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
+ ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_FSM_LC_TIMEOUT_L,
+ &buff[0]);
- if(ret == 0){
- i++;
+ if (ret == 0)
+ {
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_FSM_LC_TIMEOUT_H,
- &buff[i]);
+ &buff[1]);
}
+
return ret;
}
@@ -8707,19 +10171,23 @@ int32_t lsm6dsr_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsr_long_cnt_int_value_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
- uint8_t i;
- i = 0x00U;
- ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_FSM_LC_TIMEOUT_L, &buff[i]);
+ ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_FSM_LC_TIMEOUT_L,
+ &buff[0]);
- if(ret == 0){
- i++;
+ if (ret == 0)
+ {
ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_FSM_LC_TIMEOUT_H,
- &buff[i]);
+ &buff[1]);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
}
+
return ret;
}
@@ -8732,16 +10200,18 @@ int32_t lsm6dsr_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
*/
int32_t lsm6dsr_fsm_number_of_programs_set(stmdev_ctx_t *ctx,
- uint8_t *buff)
+ uint8_t *buff)
{
int32_t ret;
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_FSM_PROGRAMS, buff);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_FSM_PROGRAMS + 0x01U,
- buff);
+ buff);
}
+
return ret;
}
@@ -8754,7 +10224,7 @@ int32_t lsm6dsr_fsm_number_of_programs_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_fsm_number_of_programs_get(stmdev_ctx_t *ctx,
- uint8_t *buff)
+ uint8_t *buff)
{
int32_t ret;
@@ -8772,19 +10242,22 @@ int32_t lsm6dsr_fsm_number_of_programs_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_fsm_start_address_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsr_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val)
{
+ uint8_t buff[2];
int32_t ret;
- uint8_t i;
- i = 0x00U;
- ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_FSM_START_ADD_L, &buff[i]);
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
+ ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_FSM_START_ADD_L,
+ &buff[0]);
- if(ret == 0){
- i++;
+ if (ret == 0)
+ {
ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_FSM_START_ADD_H,
- &buff[i]);
+ &buff[1]);
}
+
return ret;
}
@@ -8797,18 +10270,21 @@ int32_t lsm6dsr_fsm_start_address_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsr_fsm_start_address_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsr_fsm_start_address_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
- uint8_t i;
- i = 0x00U;
- ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_FSM_START_ADD_L, &buff[i]);
+ ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_FSM_START_ADD_L, &buff[0]);
- if(ret == 0){
- i++;
- ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_FSM_START_ADD_H, &buff[i]);
+ if (ret == 0)
+ {
+ ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_FSM_START_ADD_H, &buff[1]);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
}
+
return ret;
}
@@ -8834,18 +10310,22 @@ int32_t lsm6dsr_fsm_start_address_get(stmdev_ctx_t *ctx, uint8_t *buff)
*
*/
int32_t lsm6dsr_sh_read_data_raw_get(stmdev_ctx_t *ctx,
- lsm6dsr_emb_sh_read_t *val)
+ lsm6dsr_emb_sh_read_t *val)
{
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
- if(ret == 0){
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_SENSOR_HUB_1, (uint8_t*)val, 18);
+ if (ret == 0)
+ {
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_SENSOR_HUB_1, (uint8_t *)val, 18);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -8858,25 +10338,31 @@ int32_t lsm6dsr_sh_read_data_raw_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_sh_slave_connected_set(stmdev_ctx_t *ctx,
- lsm6dsr_aux_sens_on_t val)
+ lsm6dsr_aux_sens_on_t val)
{
lsm6dsr_master_config_t master_config;
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- master_config.aux_sens_on= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ master_config.aux_sens_on = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -8889,37 +10375,47 @@ int32_t lsm6dsr_sh_slave_connected_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_sh_slave_connected_get(stmdev_ctx_t *ctx,
- lsm6dsr_aux_sens_on_t *val)
+ lsm6dsr_aux_sens_on_t *val)
{
lsm6dsr_master_config_t master_config;
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
- switch (master_config.aux_sens_on){
+
+ switch (master_config.aux_sens_on)
+ {
case LSM6DSR_SLV_0:
*val = LSM6DSR_SLV_0;
break;
+
case LSM6DSR_SLV_0_1:
*val = LSM6DSR_SLV_0_1;
break;
+
case LSM6DSR_SLV_0_1_2:
*val = LSM6DSR_SLV_0_1_2;
break;
+
case LSM6DSR_SLV_0_1_2_3:
*val = LSM6DSR_SLV_0_1_2_3;
break;
+
default:
*val = LSM6DSR_SLV_0;
break;
}
+
return ret;
}
@@ -8938,18 +10434,24 @@ int32_t lsm6dsr_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- master_config.master_on= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ master_config.master_on = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -8968,14 +10470,18 @@ int32_t lsm6dsr_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = master_config.master_on;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -8988,25 +10494,31 @@ int32_t lsm6dsr_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsr_sh_pin_mode_set(stmdev_ctx_t *ctx,
- lsm6dsr_shub_pu_en_t val)
+ lsm6dsr_shub_pu_en_t val)
{
lsm6dsr_master_config_t master_config;
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- master_config.shub_pu_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ master_config.shub_pu_en = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -9019,30 +10531,39 @@ int32_t lsm6dsr_sh_pin_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_sh_pin_mode_get(stmdev_ctx_t *ctx,
- lsm6dsr_shub_pu_en_t *val)
+ lsm6dsr_shub_pu_en_t *val)
{
lsm6dsr_master_config_t master_config;
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
- switch (master_config.shub_pu_en){
+
+ switch (master_config.shub_pu_en)
+ {
case LSM6DSR_EXT_PULL_UP:
*val = LSM6DSR_EXT_PULL_UP;
break;
+
case LSM6DSR_INTERNAL_PULL_UP:
*val = LSM6DSR_INTERNAL_PULL_UP;
break;
+
default:
*val = LSM6DSR_EXT_PULL_UP;
break;
}
+
return ret;
}
@@ -9061,18 +10582,24 @@ int32_t lsm6dsr_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- master_config.pass_through_mode= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ master_config.pass_through_mode = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -9091,14 +10618,18 @@ int32_t lsm6dsr_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = master_config.pass_through_mode;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -9111,25 +10642,31 @@ int32_t lsm6dsr_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsr_sh_syncro_mode_set(stmdev_ctx_t *ctx,
- lsm6dsr_start_config_t val)
+ lsm6dsr_start_config_t val)
{
lsm6dsr_master_config_t master_config;
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- master_config.start_config= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ master_config.start_config = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -9142,31 +10679,39 @@ int32_t lsm6dsr_sh_syncro_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_sh_syncro_mode_get(stmdev_ctx_t *ctx,
- lsm6dsr_start_config_t *val)
+ lsm6dsr_start_config_t *val)
{
lsm6dsr_master_config_t master_config;
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
- switch (master_config.start_config){
+
+ switch (master_config.start_config)
+ {
case LSM6DSR_EXT_ON_INT2_PIN:
*val = LSM6DSR_EXT_ON_INT2_PIN;
break;
+
case LSM6DSR_XL_GY_DRDY:
*val = LSM6DSR_XL_GY_DRDY;
break;
+
default:
*val = LSM6DSR_EXT_ON_INT2_PIN;
break;
}
+
return ret;
}
@@ -9180,25 +10725,31 @@ int32_t lsm6dsr_sh_syncro_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_sh_write_mode_set(stmdev_ctx_t *ctx,
- lsm6dsr_write_once_t val)
+ lsm6dsr_write_once_t val)
{
lsm6dsr_master_config_t master_config;
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- master_config.write_once= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ master_config.write_once = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -9212,31 +10763,39 @@ int32_t lsm6dsr_sh_write_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_sh_write_mode_get(stmdev_ctx_t *ctx,
- lsm6dsr_write_once_t *val)
+ lsm6dsr_write_once_t *val)
{
lsm6dsr_master_config_t master_config;
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
- switch (master_config.write_once){
+
+ switch (master_config.write_once)
+ {
case LSM6DSR_EACH_SH_CYCLE:
*val = LSM6DSR_EACH_SH_CYCLE;
break;
+
case LSM6DSR_ONLY_FIRST_CYCLE:
*val = LSM6DSR_ONLY_FIRST_CYCLE;
break;
+
default:
*val = LSM6DSR_EACH_SH_CYCLE;
break;
}
+
return ret;
}
@@ -9254,23 +10813,31 @@ int32_t lsm6dsr_sh_reset_set(stmdev_ctx_t *ctx)
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
master_config.rst_master_regs = PROPERTY_ENABLE;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
master_config.rst_master_regs = PROPERTY_DISABLE;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -9289,14 +10856,18 @@ int32_t lsm6dsr_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
*val = master_config.rst_master_regs;
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -9309,25 +10880,31 @@ int32_t lsm6dsr_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsr_sh_data_rate_set(stmdev_ctx_t *ctx,
- lsm6dsr_shub_odr_t val)
+ lsm6dsr_shub_odr_t val)
{
lsm6dsr_slv0_config_t slv0_config;
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv0_config.shub_odr = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -9340,37 +10917,47 @@ int32_t lsm6dsr_sh_data_rate_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_sh_data_rate_get(stmdev_ctx_t *ctx,
- lsm6dsr_shub_odr_t *val)
+ lsm6dsr_shub_odr_t *val)
{
lsm6dsr_slv0_config_t slv0_config;
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
- switch (slv0_config.shub_odr){
+
+ switch (slv0_config.shub_odr)
+ {
case LSM6DSR_SH_ODR_104Hz:
*val = LSM6DSR_SH_ODR_104Hz;
break;
+
case LSM6DSR_SH_ODR_52Hz:
*val = LSM6DSR_SH_ODR_52Hz;
break;
+
case LSM6DSR_SH_ODR_26Hz:
*val = LSM6DSR_SH_ODR_26Hz;
break;
+
case LSM6DSR_SH_ODR_13Hz:
*val = LSM6DSR_SH_ODR_13Hz;
break;
+
default:
*val = LSM6DSR_SH_ODR_104Hz;
break;
}
+
return ret;
}
@@ -9386,30 +10973,38 @@ int32_t lsm6dsr_sh_data_rate_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_sh_cfg_write(stmdev_ctx_t *ctx,
- lsm6dsr_sh_cfg_write_t *val)
+ lsm6dsr_sh_cfg_write_t *val)
{
lsm6dsr_slv0_add_t slv0_add;
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
- if(ret == 0){
- slv0_add.slave0 = (uint8_t) (val->slv0_add >> 1);
+ if (ret == 0)
+ {
+ slv0_add.slave0 = (uint8_t)(val->slv0_add >> 1);
slv0_add.rw_0 = 0;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV0_ADD,
- (uint8_t*)&(slv0_add), 1);
+ (uint8_t *) & (slv0_add), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV0_SUBADD,
- (uint8_t*)&(val->slv0_subadd), 1);
+ (uint8_t *) & (val->slv0_subadd), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_write_reg(ctx, LSM6DSR_DATAWRITE_SLV0,
- (uint8_t*)&(val->slv0_data), 1);
+ (uint8_t *) & (val->slv0_data), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -9425,7 +11020,7 @@ int32_t lsm6dsr_sh_cfg_write(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
- lsm6dsr_sh_cfg_read_t *val)
+ lsm6dsr_sh_cfg_read_t *val)
{
lsm6dsr_slv0_config_t slv0_config;
lsm6dsr_slv0_add_t slv0_add;
@@ -9433,28 +11028,38 @@ int32_t lsm6dsr_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
slv0_add.slave0 = (uint8_t) val->slv_add >> 1;
slv0_add.rw_0 = 1;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV0_ADD,
- (uint8_t*)&(slv0_add), 1);
+ (uint8_t *) & (slv0_add), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV0_SUBADD,
- &(val->slv_subadd), 1);
+ &(val->slv_subadd), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv0_config.slave0_numop = val->slv_len;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -9470,34 +11075,45 @@ int32_t lsm6dsr_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
- lsm6dsr_sh_cfg_read_t *val)
+ lsm6dsr_sh_cfg_read_t *val)
{
lsm6dsr_slv1_config_t slv1_config;
lsm6dsr_slv1_add_t slv1_add;
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
- if(ret == 0){
- slv1_add.slave1_add = (uint8_t) (val->slv_add >> 1);
+
+ if (ret == 0)
+ {
+ slv1_add.slave1_add = (uint8_t)(val->slv_add >> 1);
slv1_add.r_1 = 1;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV1_ADD, (uint8_t*)&slv1_add, 1);
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV1_ADD, (uint8_t *)&slv1_add, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV1_SUBADD,
- &(val->slv_subadd), 1);
+ &(val->slv_subadd), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV1_CONFIG,
- (uint8_t*)&slv1_config, 1);
+ (uint8_t *)&slv1_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv1_config.slave1_numop = val->slv_len;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV1_CONFIG,
- (uint8_t*)&slv1_config, 1);
+ (uint8_t *)&slv1_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
-}
+ }
+
return ret;
}
@@ -9513,7 +11129,7 @@ int32_t lsm6dsr_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
- lsm6dsr_sh_cfg_read_t *val)
+ lsm6dsr_sh_cfg_read_t *val)
{
lsm6dsr_slv2_config_t slv2_config;
lsm6dsr_slv2_add_t slv2_add;
@@ -9521,28 +11137,38 @@ int32_t lsm6dsr_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
- if(ret == 0){
- slv2_add.slave2_add = (uint8_t) (val->slv_add >> 1);
+ if (ret == 0)
+ {
+ slv2_add.slave2_add = (uint8_t)(val->slv_add >> 1);
slv2_add.r_2 = 1;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV2_ADD,
- (uint8_t*)&slv2_add, 1);
+ (uint8_t *)&slv2_add, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV2_SUBADD,
- (uint8_t*)&(val->slv_subadd), 1);
+ (uint8_t *) & (val->slv_subadd), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV2_CONFIG,
- (uint8_t*)&slv2_config, 1);
+ (uint8_t *)&slv2_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv2_config.slave2_numop = val->slv_len;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV2_CONFIG,
- (uint8_t*)&slv2_config, 1);
+ (uint8_t *)&slv2_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -9558,7 +11184,7 @@ int32_t lsm6dsr_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
- lsm6dsr_sh_cfg_read_t *val)
+ lsm6dsr_sh_cfg_read_t *val)
{
lsm6dsr_slv3_config_t slv3_config;
lsm6dsr_slv3_add_t slv3_add;
@@ -9566,28 +11192,38 @@ int32_t lsm6dsr_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
- if(ret == 0){
- slv3_add.slave3_add = (uint8_t) (val->slv_add >> 1);
+ if (ret == 0)
+ {
+ slv3_add.slave3_add = (uint8_t)(val->slv_add >> 1);
slv3_add.r_3 = 1;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV3_ADD,
- (uint8_t*)&slv3_add, 1);
+ (uint8_t *)&slv3_add, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV3_SUBADD,
- &(val->slv_subadd), 1);
+ &(val->slv_subadd), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV3_CONFIG,
- (uint8_t*)&slv3_config, 1);
+ (uint8_t *)&slv3_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv3_config.slave3_numop = val->slv_len;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV3_CONFIG,
- (uint8_t*)&slv3_config, 1);
+ (uint8_t *)&slv3_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -9600,18 +11236,22 @@ int32_t lsm6dsr_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_sh_status_get(stmdev_ctx_t *ctx,
- lsm6dsr_status_master_t *val)
+ lsm6dsr_status_master_t *val)
{
int32_t ret;
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
- if(ret == 0){
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_MASTER, (uint8_t*)val, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_MASTER, (uint8_t *)val, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
}
+
return ret;
}
@@ -9637,17 +11277,20 @@ int32_t lsm6dsr_sh_status_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_s4s_tph_res_set(stmdev_ctx_t *ctx,
- lsm6dsr_s4s_tph_res_t val)
+ lsm6dsr_s4s_tph_res_t val)
{
lsm6dsr_s4s_tph_l_t s4s_tph_l;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_TPH_L, (uint8_t*)&s4s_tph_l, 1);
- if(ret == 0){
- s4s_tph_l.tph_h_sel= (uint8_t)val;
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_TPH_L, (uint8_t *)&s4s_tph_l, 1);
+
+ if (ret == 0)
+ {
+ s4s_tph_l.tph_h_sel = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_S4S_TPH_L,
- (uint8_t*)&s4s_tph_l, 1);
+ (uint8_t *)&s4s_tph_l, 1);
}
+
return ret;
}
@@ -9660,24 +11303,28 @@ int32_t lsm6dsr_s4s_tph_res_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_s4s_tph_res_get(stmdev_ctx_t *ctx,
- lsm6dsr_s4s_tph_res_t *val)
+ lsm6dsr_s4s_tph_res_t *val)
{
lsm6dsr_s4s_tph_l_t s4s_tph_l;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_TPH_L, (uint8_t*)&s4s_tph_l, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_TPH_L, (uint8_t *)&s4s_tph_l, 1);
- switch (s4s_tph_l.tph_h_sel){
+ switch (s4s_tph_l.tph_h_sel)
+ {
case LSM6DSR_S4S_TPH_7bit:
*val = LSM6DSR_S4S_TPH_7bit;
break;
+
case LSM6DSR_S4S_TPH_15bit:
*val = LSM6DSR_S4S_TPH_15bit;
break;
+
default:
*val = LSM6DSR_S4S_TPH_7bit;
break;
}
+
return ret;
}
@@ -9696,21 +11343,28 @@ int32_t lsm6dsr_s4s_tph_val_set(stmdev_ctx_t *ctx, uint16_t val)
lsm6dsr_s4s_tph_h_t s4s_tph_h;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_TPH_L, (uint8_t*)&s4s_tph_l, 1);
- if(ret == 0){
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_TPH_L, (uint8_t *)&s4s_tph_l, 1);
+
+ if (ret == 0)
+ {
s4s_tph_l.tph_l = (uint8_t)(val & 0x007FU);
ret = lsm6dsr_write_reg(ctx, LSM6DSR_S4S_TPH_L,
- (uint8_t*)&s4s_tph_l, 1);
+ (uint8_t *)&s4s_tph_l, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_TPH_H,
- (uint8_t*)&s4s_tph_h, 1);
+ (uint8_t *)&s4s_tph_h, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
s4s_tph_h.tph_h = (uint8_t)((val & 0x7F80U) >> 7);
ret = lsm6dsr_write_reg(ctx, LSM6DSR_S4S_TPH_H,
- (uint8_t*)&s4s_tph_h, 1);
+ (uint8_t *)&s4s_tph_h, 1);
}
+
return ret;
}
@@ -9728,11 +11382,14 @@ int32_t lsm6dsr_s4s_tph_val_get(stmdev_ctx_t *ctx, uint16_t *val)
lsm6dsr_s4s_tph_h_t s4s_tph_h;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_TPH_L, (uint8_t*)&s4s_tph_l, 1);
- if(ret == 0){
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_TPH_L, (uint8_t *)&s4s_tph_l, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_TPH_H,
- (uint8_t*)&s4s_tph_h, 1);
+ (uint8_t *)&s4s_tph_h, 1);
}
+
*val = s4s_tph_h.tph_h;
*val = *val << 7;
*val += s4s_tph_l.tph_l;
@@ -9749,16 +11406,19 @@ int32_t lsm6dsr_s4s_tph_val_get(stmdev_ctx_t *ctx, uint16_t *val)
*
*/
int32_t lsm6dsr_s4s_res_ratio_set(stmdev_ctx_t *ctx,
- lsm6dsr_s4s_res_ratio_t val)
+ lsm6dsr_s4s_res_ratio_t val)
{
lsm6dsr_s4s_rr_t s4s_rr;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_RR, (uint8_t*)&s4s_rr, 1);
- if(ret == 0){
- s4s_rr.rr= (uint8_t)val;
- ret = lsm6dsr_write_reg(ctx, LSM6DSR_S4S_RR, (uint8_t*)&s4s_rr, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_RR, (uint8_t *)&s4s_rr, 1);
+
+ if (ret == 0)
+ {
+ s4s_rr.rr = (uint8_t)val;
+ ret = lsm6dsr_write_reg(ctx, LSM6DSR_S4S_RR, (uint8_t *)&s4s_rr, 1);
}
+
return ret;
}
@@ -9771,30 +11431,36 @@ int32_t lsm6dsr_s4s_res_ratio_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsr_s4s_res_ratio_get(stmdev_ctx_t *ctx,
- lsm6dsr_s4s_res_ratio_t *val)
+ lsm6dsr_s4s_res_ratio_t *val)
{
lsm6dsr_s4s_rr_t s4s_rr;
int32_t ret;
- ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_RR, (uint8_t*)&s4s_rr, 1);
+ ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_RR, (uint8_t *)&s4s_rr, 1);
- switch ( s4s_rr.rr){
+ switch (s4s_rr.rr)
+ {
case LSM6DSR_S4S_DT_RES_11:
*val = LSM6DSR_S4S_DT_RES_11;
break;
+
case LSM6DSR_S4S_DT_RES_12:
*val = LSM6DSR_S4S_DT_RES_12;
break;
+
case LSM6DSR_S4S_DT_RES_13:
*val = LSM6DSR_S4S_DT_RES_13;
break;
+
case LSM6DSR_S4S_DT_RES_14:
*val = LSM6DSR_S4S_DT_RES_14;
break;
+
default:
*val = LSM6DSR_S4S_DT_RES_11;
break;
}
+
return ret;
}
@@ -9812,12 +11478,15 @@ int32_t lsm6dsr_s4s_command_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_ST_CMD_CODE,
- (uint8_t*)&s4s_st_cmd_code, 1);
- if(ret == 0){
- s4s_st_cmd_code.s4s_st_cmd_code= (uint8_t)val;
+ (uint8_t *)&s4s_st_cmd_code, 1);
+
+ if (ret == 0)
+ {
+ s4s_st_cmd_code.s4s_st_cmd_code = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_S4S_ST_CMD_CODE,
- (uint8_t*)&s4s_st_cmd_code, 1);
+ (uint8_t *)&s4s_st_cmd_code, 1);
}
+
return ret;
}
@@ -9835,7 +11504,7 @@ int32_t lsm6dsr_s4s_command_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_ST_CMD_CODE,
- (uint8_t*)&s4s_st_cmd_code, 1);
+ (uint8_t *)&s4s_st_cmd_code, 1);
*val = s4s_st_cmd_code.s4s_st_cmd_code;
return ret;
@@ -9855,12 +11524,15 @@ int32_t lsm6dsr_s4s_dt_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_DT_REG,
- (uint8_t*)&s4s_dt_reg, 1);
- if(ret == 0){
+ (uint8_t *)&s4s_dt_reg, 1);
+
+ if (ret == 0)
+ {
s4s_dt_reg.dt = (uint8_t)val;
ret = lsm6dsr_write_reg(ctx, LSM6DSR_S4S_DT_REG,
- (uint8_t*)&s4s_dt_reg, 1);
+ (uint8_t *)&s4s_dt_reg, 1);
}
+
return ret;
}
@@ -9878,7 +11550,7 @@ int32_t lsm6dsr_s4s_dt_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_DT_REG,
- (uint8_t*)&s4s_dt_reg, 1);
+ (uint8_t *)&s4s_dt_reg, 1);
*val = s4s_dt_reg.dt;
return ret;
diff --git a/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.h b/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.h
index d692ff12d9c7d42994d523d0c56e6f7b57f61883..ac0a80e7c2cc4210ba59b0a00c34286f298f9db1 100644
--- a/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.h
+++ b/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file lsm6dsr_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lsm6dsr_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lsm6dsr_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lsm6dsr_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LSM6DSR_REGS_H
#define LSM6DSR_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup LSM6DSR
@@ -35,6 +36,37 @@
*
*/
+/** @defgroup Endianness definitions
+ * @{
+ *
+ */
+
+#ifndef DRV_BYTE_ORDER
+#ifndef __BYTE_ORDER__
+
+#define DRV_LITTLE_ENDIAN 1234
+#define DRV_BIG_ENDIAN 4321
+
+/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
+ * by uncommenting the define which fits your platform endianness
+ */
+//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
+#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
+
+#else /* defined __BYTE_ORDER__ */
+
+#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
+#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
+#define DRV_BYTE_ORDER __BYTE_ORDER__
+
+#endif /* __BYTE_ORDER__*/
+#endif /* DRV_BYTE_ORDER */
+
+/**
+ * @}
+ *
+ */
+
/** @defgroup STMicroelectronics sensors common types
* @{
*
@@ -43,7 +75,9 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -52,6 +86,16 @@ typedef struct{
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} bitwise_t;
#define PROPERTY_DISABLE (0U)
@@ -65,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -89,15 +134,16 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
- * Unico / Unicleo tools available on STMicroelectronics
- * web site.
+ * You can create a sensor configuration by your own or using
+ * Unico / Unicleo tools available on STMicroelectronics
+ * web site.
*
* @{
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -132,42 +178,73 @@ typedef struct {
*/
#define LSM6DSR_FUNC_CFG_ACCESS 0x01U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t not_used_01 : 6;
+uint8_t reg_access :
+ 2; /* shub_reg_access + func_cfg_access */
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+uint8_t reg_access :
+ 2; /* shub_reg_access + func_cfg_access */
uint8_t not_used_01 : 6;
- uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_func_cfg_access_t;
#define LSM6DSR_PIN_CTRL 0x02U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 6;
uint8_t sdo_pu_en : 1;
uint8_t ois_pu_dis : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t ois_pu_dis : 1;
+ uint8_t sdo_pu_en : 1;
+ uint8_t not_used_01 : 6;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_pin_ctrl_t;
#define LSM6DSR_S4S_TPH_L 0x04U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tph_l : 7;
uint8_t tph_h_sel : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t tph_h_sel : 1;
+ uint8_t tph_l : 7;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_s4s_tph_l_t;
#define LSM6DSR_S4S_TPH_H 0x05U
-typedef struct {
+typedef struct
+{
uint8_t tph_h : 8;
} lsm6dsr_s4s_tph_h_t;
#define LSM6DSR_S4S_RR 0x06U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t rr : 2;
uint8_t not_used_01 : 6;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 6;
+ uint8_t rr : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_s4s_rr_t;
#define LSM6DSR_FIFO_CTRL1 0x07U
-typedef struct {
+typedef struct
+{
uint8_t wtm : 8;
} lsm6dsr_fifo_ctrl1_t;
#define LSM6DSR_FIFO_CTRL2 0x08U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wtm : 1;
uint8_t uncoptr_rate : 2;
uint8_t not_used_01 : 1;
@@ -175,38 +252,73 @@ typedef struct {
uint8_t not_used_02 : 1;
uint8_t fifo_compr_rt_en : 1;
uint8_t stop_on_wtm : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t stop_on_wtm : 1;
+ uint8_t fifo_compr_rt_en : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t odrchg_en : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t uncoptr_rate : 2;
+ uint8_t wtm : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fifo_ctrl2_t;
#define LSM6DSR_FIFO_CTRL3 0x09U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bdr_xl : 4;
uint8_t bdr_gy : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bdr_gy : 4;
+ uint8_t bdr_xl : 4;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fifo_ctrl3_t;
#define LSM6DSR_FIFO_CTRL4 0x0AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fifo_mode : 3;
uint8_t not_used_01 : 1;
uint8_t odr_t_batch : 2;
uint8_t odr_ts_batch : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr_ts_batch : 2;
+ uint8_t odr_t_batch : 2;
+ uint8_t not_used_01 : 1;
+ uint8_t fifo_mode : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fifo_ctrl4_t;
#define LSM6DSR_COUNTER_BDR_REG1 0x0BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t cnt_bdr_th : 3;
uint8_t not_used_01 : 2;
uint8_t trig_counter_bdr : 1;
uint8_t rst_counter_bdr : 1;
uint8_t dataready_pulsed : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t dataready_pulsed : 1;
+ uint8_t rst_counter_bdr : 1;
+ uint8_t trig_counter_bdr : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t cnt_bdr_th : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_counter_bdr_reg1_t;
#define LSM6DSR_COUNTER_BDR_REG2 0x0CU
-typedef struct {
+typedef struct
+{
uint8_t cnt_bdr_th : 8;
} lsm6dsr_counter_bdr_reg2_t;
#define LSM6DSR_INT1_CTRL 0x0DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_drdy_xl : 1;
uint8_t int1_drdy_g : 1;
uint8_t int1_boot : 1;
@@ -215,10 +327,22 @@ typedef struct {
uint8_t int1_fifo_full : 1;
uint8_t int1_cnt_bdr : 1;
uint8_t den_drdy_flag : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t den_drdy_flag : 1;
+ uint8_t int1_cnt_bdr : 1;
+ uint8_t int1_fifo_full : 1;
+ uint8_t int1_fifo_ovr : 1;
+ uint8_t int1_fifo_th : 1;
+ uint8_t int1_boot : 1;
+ uint8_t int1_drdy_g : 1;
+ uint8_t int1_drdy_xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_int1_ctrl_t;
#define LSM6DSR_INT2_CTRL 0x0EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_drdy_xl : 1;
uint8_t int2_drdy_g : 1;
uint8_t int2_drdy_temp : 1;
@@ -227,25 +351,51 @@ typedef struct {
uint8_t int2_fifo_full : 1;
uint8_t int2_cnt_bdr : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t int2_cnt_bdr : 1;
+ uint8_t int2_fifo_full : 1;
+ uint8_t int2_fifo_ovr : 1;
+ uint8_t int2_fifo_th : 1;
+ uint8_t int2_drdy_temp : 1;
+ uint8_t int2_drdy_g : 1;
+ uint8_t int2_drdy_xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_int2_ctrl_t;
#define LSM6DSR_WHO_AM_I 0x0FU
#define LSM6DSR_CTRL1_XL 0x10U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t lpf2_xl_en : 1;
uint8_t fs_xl : 2;
uint8_t odr_xl : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr_xl : 4;
+ uint8_t fs_xl : 2;
+ uint8_t lpf2_xl_en : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_ctrl1_xl_t;
#define LSM6DSR_CTRL2_G 0x11U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fs_g : 4; /* fs_4000 + fs_125 + fs_g */
uint8_t odr_g : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr_g : 4;
+ uint8_t fs_g : 4; /* fs_4000 + fs_125 + fs_g */
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_ctrl2_g_t;
#define LSM6DSR_CTRL3_C 0x12U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sw_reset : 1;
uint8_t not_used_01 : 1;
uint8_t if_inc : 1;
@@ -254,10 +404,22 @@ typedef struct {
uint8_t h_lactive : 1;
uint8_t bdu : 1;
uint8_t boot : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t boot : 1;
+ uint8_t bdu : 1;
+ uint8_t h_lactive : 1;
+ uint8_t pp_od : 1;
+ uint8_t sim : 1;
+ uint8_t if_inc : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t sw_reset : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_ctrl3_c_t;
#define LSM6DSR_CTRL4_C 0x13U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t lpf1_sel_g : 1;
uint8_t i2c_disable : 1;
@@ -266,27 +428,58 @@ typedef struct {
uint8_t int2_on_int1 : 1;
uint8_t sleep_g : 1;
uint8_t not_used_03 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_03 : 1;
+ uint8_t sleep_g : 1;
+ uint8_t int2_on_int1 : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t drdy_mask : 1;
+ uint8_t i2c_disable : 1;
+ uint8_t lpf1_sel_g : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_ctrl4_c_t;
#define LSM6DSR_CTRL5_C 0x14U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_xl : 2;
uint8_t st_g : 2;
uint8_t not_used_01 : 1;
uint8_t rounding : 2;
uint8_t not_used_02 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 1;
+ uint8_t rounding : 2;
+ uint8_t not_used_01 : 1;
+ uint8_t st_g : 2;
+ uint8_t st_xl : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_ctrl5_c_t;
#define LSM6DSR_CTRL6_C 0x15U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ftype : 3;
uint8_t usr_off_w : 1;
uint8_t xl_hm_mode : 1;
- uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */
+uint8_t den_mode :
+ 3; /* trig_en + lvl1_en + lvl2_en */
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+uint8_t den_mode :
+ 3; /* trig_en + lvl1_en + lvl2_en */
+ uint8_t xl_hm_mode : 1;
+ uint8_t usr_off_w : 1;
+ uint8_t ftype : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_ctrl6_c_t;
#define LSM6DSR_CTRL7_G 0x16U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ois_on : 1;
uint8_t usr_off_on_out : 1;
uint8_t ois_on_en : 1;
@@ -294,20 +487,41 @@ typedef struct {
uint8_t hpm_g : 2;
uint8_t hp_en_g : 1;
uint8_t g_hm_mode : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t g_hm_mode : 1;
+ uint8_t hp_en_g : 1;
+ uint8_t hpm_g : 2;
+ uint8_t not_used_01 : 1;
+ uint8_t ois_on_en : 1;
+ uint8_t usr_off_on_out : 1;
+ uint8_t ois_on : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_ctrl7_g_t;
#define LSM6DSR_CTRL8_XL 0x17U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t low_pass_on_6d : 1;
uint8_t not_used_01 : 1;
uint8_t hp_slope_xl_en : 1;
uint8_t fastsettl_mode_xl : 1;
uint8_t hp_ref_mode_xl : 1;
uint8_t hpcf_xl : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t hpcf_xl : 3;
+ uint8_t hp_ref_mode_xl : 1;
+ uint8_t fastsettl_mode_xl : 1;
+ uint8_t hp_slope_xl_en : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t low_pass_on_6d : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_ctrl8_xl_t;
#define LSM6DSR_CTRL9_XL 0x18U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t i3c_disable : 1;
uint8_t den_lh : 1;
@@ -315,17 +529,35 @@ typedef struct {
uint8_t den_z : 1;
uint8_t den_y : 1;
uint8_t den_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t den_x : 1;
+ uint8_t den_y : 1;
+ uint8_t den_z : 1;
+ uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */
+ uint8_t den_lh : 1;
+ uint8_t i3c_disable : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_ctrl9_xl_t;
#define LSM6DSR_CTRL10_C 0x19U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 5;
uint8_t timestamp_en : 1;
uint8_t not_used_02 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 2;
+ uint8_t timestamp_en : 1;
+ uint8_t not_used_01 : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_ctrl10_c_t;
#define LSM6DSR_ALL_INT_SRC 0x1AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ia : 1;
uint8_t wu_ia : 1;
uint8_t single_tap : 1;
@@ -334,10 +566,22 @@ typedef struct {
uint8_t sleep_change_ia : 1;
uint8_t not_used_01 : 1;
uint8_t timestamp_endcount : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t timestamp_endcount : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t sleep_change_ia : 1;
+ uint8_t d6d_ia : 1;
+ uint8_t double_tap : 1;
+ uint8_t single_tap : 1;
+ uint8_t wu_ia : 1;
+ uint8_t ff_ia : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_all_int_src_t;
#define LSM6DSR_WAKE_UP_SRC 0x1BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_wu : 1;
uint8_t y_wu : 1;
uint8_t x_wu : 1;
@@ -346,10 +590,22 @@ typedef struct {
uint8_t ff_ia : 1;
uint8_t sleep_change_ia : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t sleep_change_ia : 1;
+ uint8_t ff_ia : 1;
+ uint8_t sleep_state : 1;
+ uint8_t wu_ia : 1;
+ uint8_t x_wu : 1;
+ uint8_t y_wu : 1;
+ uint8_t z_wu : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_wake_up_src_t;
#define LSM6DSR_TAP_SRC 0x1CU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_tap : 1;
uint8_t y_tap : 1;
uint8_t x_tap : 1;
@@ -358,10 +614,22 @@ typedef struct {
uint8_t single_tap : 1;
uint8_t tap_ia : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t tap_ia : 1;
+ uint8_t single_tap : 1;
+ uint8_t double_tap : 1;
+ uint8_t tap_sign : 1;
+ uint8_t x_tap : 1;
+ uint8_t y_tap : 1;
+ uint8_t z_tap : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_tap_src_t;
#define LSM6DSR_D6D_SRC 0x1DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
uint8_t yl : 1;
@@ -370,22 +638,48 @@ typedef struct {
uint8_t zh : 1;
uint8_t d6d_ia : 1;
uint8_t den_drdy : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t den_drdy : 1;
+ uint8_t d6d_ia : 1;
+ uint8_t zh : 1;
+ uint8_t zl : 1;
+ uint8_t yh : 1;
+ uint8_t yl : 1;
+ uint8_t xh : 1;
+ uint8_t xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_d6d_src_t;
#define LSM6DSR_STATUS_REG 0x1EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlda : 1;
uint8_t gda : 1;
uint8_t tda : 1;
uint8_t not_used_01 : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 5;
+ uint8_t tda : 1;
+ uint8_t gda : 1;
+ uint8_t xlda : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_status_reg_t;
#define LSM6DSR_STATUS_SPIAUX 0x1EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlda : 1;
uint8_t gda : 1;
uint8_t gyro_settling : 1;
uint8_t not_used_01 : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 5;
+ uint8_t gyro_settling : 1;
+ uint8_t gda : 1;
+ uint8_t xlda : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_status_spiaux_t;
#define LSM6DSR_OUT_TEMP_L 0x20U
@@ -403,17 +697,29 @@ typedef struct {
#define LSM6DSR_OUTZ_L_A 0x2CU
#define LSM6DSR_OUTZ_H_A 0x2DU
#define LSM6DSR_EMB_FUNC_STATUS_MAINPAGE 0x35U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t is_step_det : 1;
uint8_t is_tilt : 1;
uint8_t is_sigmot : 1;
uint8_t not_used_02 : 1;
uint8_t is_fsm_lc : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_fsm_lc : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t is_sigmot : 1;
+ uint8_t is_tilt : 1;
+ uint8_t is_step_det : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_emb_func_status_mainpage_t;
#define LSM6DSR_FSM_STATUS_A_MAINPAGE 0x36U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_fsm1 : 1;
uint8_t is_fsm2 : 1;
uint8_t is_fsm3 : 1;
@@ -422,10 +728,22 @@ typedef struct {
uint8_t is_fsm6 : 1;
uint8_t is_fsm7 : 1;
uint8_t is_fsm8 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_fsm8 : 1;
+ uint8_t is_fsm7 : 1;
+ uint8_t is_fsm6 : 1;
+ uint8_t is_fsm5 : 1;
+ uint8_t is_fsm4 : 1;
+ uint8_t is_fsm3 : 1;
+ uint8_t is_fsm2 : 1;
+ uint8_t is_fsm1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fsm_status_a_mainpage_t;
#define LSM6DSR_FSM_STATUS_B_MAINPAGE 0x37U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_fsm9 : 1;
uint8_t is_fsm10 : 1;
uint8_t is_fsm11 : 1;
@@ -434,10 +752,22 @@ typedef struct {
uint8_t is_fsm14 : 1;
uint8_t is_fsm15 : 1;
uint8_t is_fsm16 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_fsm16 : 1;
+ uint8_t is_fsm15 : 1;
+ uint8_t is_fsm14 : 1;
+ uint8_t is_fsm13 : 1;
+ uint8_t is_fsm12 : 1;
+ uint8_t is_fsm11 : 1;
+ uint8_t is_fsm10 : 1;
+ uint8_t is_fsm9 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fsm_status_b_mainpage_t;
#define LSM6DSR_STATUS_MASTER_MAINPAGE 0x39U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sens_hub_endop : 1;
uint8_t not_used_01 : 2;
uint8_t slave0_nack : 1;
@@ -445,15 +775,27 @@ typedef struct {
uint8_t slave2_nack : 1;
uint8_t slave3_nack : 1;
uint8_t wr_once_done : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t wr_once_done : 1;
+ uint8_t slave3_nack : 1;
+ uint8_t slave2_nack : 1;
+ uint8_t slave1_nack : 1;
+ uint8_t slave0_nack : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t sens_hub_endop : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_status_master_mainpage_t;
#define LSM6DSR_FIFO_STATUS1 0x3AU
-typedef struct {
+typedef struct
+{
uint8_t diff_fifo : 8;
} lsm6dsr_fifo_status1_t;
#define LSM6DSR_FIFO_STATUS2 0x3BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t diff_fifo : 2;
uint8_t not_used_01 : 1;
uint8_t over_run_latched : 1;
@@ -461,6 +803,15 @@ typedef struct {
uint8_t fifo_full_ia : 1;
uint8_t fifo_ovr_ia : 1;
uint8_t fifo_wtm_ia : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fifo_wtm_ia : 1;
+ uint8_t fifo_ovr_ia : 1;
+ uint8_t fifo_full_ia : 1;
+ uint8_t counter_bdr_ia : 1;
+ uint8_t over_run_latched : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t diff_fifo : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fifo_status2_t;
#define LSM6DSR_TIMESTAMP0 0x40U
@@ -468,7 +819,9 @@ typedef struct {
#define LSM6DSR_TIMESTAMP2 0x42U
#define LSM6DSR_TIMESTAMP3 0x43U
#define LSM6DSR_TAP_CFG0 0x56U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lir : 1;
uint8_t tap_z_en : 1;
uint8_t tap_y_en : 1;
@@ -477,58 +830,118 @@ typedef struct {
uint8_t sleep_status_on_int : 1;
uint8_t int_clr_on_read : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t int_clr_on_read : 1;
+ uint8_t sleep_status_on_int : 1;
+ uint8_t slope_fds : 1;
+ uint8_t tap_x_en : 1;
+ uint8_t tap_y_en : 1;
+ uint8_t tap_z_en : 1;
+ uint8_t lir : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_tap_cfg0_t;
#define LSM6DSR_TAP_CFG1 0x57U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_ths_x : 5;
uint8_t tap_priority : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t tap_priority : 3;
+ uint8_t tap_ths_x : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_tap_cfg1_t;
#define LSM6DSR_TAP_CFG2 0x58U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_ths_y : 5;
uint8_t inact_en : 2;
uint8_t interrupts_enable : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t interrupts_enable : 1;
+ uint8_t inact_en : 2;
+ uint8_t tap_ths_y : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_tap_cfg2_t;
#define LSM6DSR_TAP_THS_6D 0x59U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_ths_z : 5;
uint8_t sixd_ths : 2;
uint8_t d4d_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t d4d_en : 1;
+ uint8_t sixd_ths : 2;
+ uint8_t tap_ths_z : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_tap_ths_6d_t;
#define LSM6DSR_INT_DUR2 0x5AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shock : 2;
uint8_t quiet : 2;
uint8_t dur : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t dur : 4;
+ uint8_t quiet : 2;
+ uint8_t shock : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_int_dur2_t;
#define LSM6DSR_WAKE_UP_THS 0x5BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wk_ths : 6;
uint8_t usr_off_on_wu : 1;
uint8_t single_double_tap : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t single_double_tap : 1;
+ uint8_t usr_off_on_wu : 1;
+ uint8_t wk_ths : 6;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_wake_up_ths_t;
#define LSM6DSR_WAKE_UP_DUR 0x5CU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sleep_dur : 4;
uint8_t wake_ths_w : 1;
uint8_t wake_dur : 2;
uint8_t ff_dur : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t ff_dur : 1;
+ uint8_t wake_dur : 2;
+ uint8_t wake_ths_w : 1;
+ uint8_t sleep_dur : 4;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_wake_up_dur_t;
#define LSM6DSR_FREE_FALL 0x5DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ths : 3;
uint8_t ff_dur : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t ff_dur : 5;
+ uint8_t ff_ths : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_free_fall_t;
#define LSM6DSR_MD1_CFG 0x5EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_shub : 1;
uint8_t int1_emb_func : 1;
uint8_t int1_6d : 1;
@@ -537,10 +950,22 @@ typedef struct {
uint8_t int1_wu : 1;
uint8_t int1_single_tap : 1;
uint8_t int1_sleep_change : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_sleep_change : 1;
+ uint8_t int1_single_tap : 1;
+ uint8_t int1_wu : 1;
+ uint8_t int1_ff : 1;
+ uint8_t int1_double_tap : 1;
+ uint8_t int1_6d : 1;
+ uint8_t int1_emb_func : 1;
+ uint8_t int1_shub : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_md1_cfg_t;
#define LSM6DSR_MD2_CFG 0x5FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_timestamp : 1;
uint8_t int2_emb_func : 1;
uint8_t int2_6d : 1;
@@ -549,42 +974,74 @@ typedef struct {
uint8_t int2_wu : 1;
uint8_t int2_single_tap : 1;
uint8_t int2_sleep_change : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_sleep_change : 1;
+ uint8_t int2_single_tap : 1;
+ uint8_t int2_wu : 1;
+ uint8_t int2_ff : 1;
+ uint8_t int2_double_tap : 1;
+ uint8_t int2_6d : 1;
+ uint8_t int2_emb_func : 1;
+ uint8_t int2_timestamp : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_md2_cfg_t;
#define LSM6DSR_S4S_ST_CMD_CODE 0x60U
-typedef struct {
+typedef struct
+{
uint8_t s4s_st_cmd_code : 8;
} lsm6dsr_s4s_st_cmd_code_t;
#define LSM6DSR_S4S_DT_REG 0x61U
-typedef struct {
+typedef struct
+{
uint8_t dt : 8;
} lsm6dsr_s4s_dt_reg_t;
#define LSM6DSR_I3C_BUS_AVB 0x62U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t pd_dis_int1 : 1;
uint8_t not_used_01 : 2;
uint8_t i3c_bus_avb_sel : 2;
uint8_t not_used_02 : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 3;
+ uint8_t i3c_bus_avb_sel : 2;
+ uint8_t not_used_01 : 2;
+ uint8_t pd_dis_int1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_i3c_bus_avb_t;
#define LSM6DSR_INTERNAL_FREQ_FINE 0x63U
-typedef struct {
+typedef struct
+{
uint8_t freq_fine : 8;
} lsm6dsr_internal_freq_fine_t;
#define LSM6DSR_INT_OIS 0x6FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_xl_ois : 2;
uint8_t not_used_01 : 3;
uint8_t den_lh_ois : 1;
uint8_t lvl2_ois : 1;
uint8_t int2_drdy_ois : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_drdy_ois : 1;
+ uint8_t lvl2_ois : 1;
+ uint8_t den_lh_ois : 1;
+ uint8_t not_used_01 : 3;
+ uint8_t st_xl_ois : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_int_ois_t;
#define LSM6DSR_CTRL1_OIS 0x70U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ois_en_spi2 : 1;
uint8_t fs_125_ois : 1;
uint8_t fs_g_ois : 2;
@@ -592,33 +1049,66 @@ typedef struct {
uint8_t sim_ois : 1;
uint8_t lvl1_ois : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t lvl1_ois : 1;
+ uint8_t sim_ois : 1;
+ uint8_t mode4_en : 1;
+ uint8_t fs_g_ois : 2;
+ uint8_t fs_125_ois : 1;
+ uint8_t ois_en_spi2 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_ctrl1_ois_t;
#define LSM6DSR_CTRL2_OIS 0x71U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t hp_en_ois : 1;
uint8_t ftype_ois : 2;
uint8_t not_used_01 : 1;
uint8_t hpm_ois : 2;
uint8_t not_used_02 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 2;
+ uint8_t hpm_ois : 2;
+ uint8_t not_used_01 : 1;
+ uint8_t ftype_ois : 2;
+ uint8_t hp_en_ois : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_ctrl2_ois_t;
#define LSM6DSR_CTRL3_OIS 0x72U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_ois_clampdis : 1;
uint8_t st_ois : 2;
uint8_t filter_xl_conf_ois : 3;
uint8_t fs_xl_ois : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fs_xl_ois : 2;
+ uint8_t filter_xl_conf_ois : 3;
+ uint8_t st_ois : 2;
+ uint8_t st_ois_clampdis : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_ctrl3_ois_t;
#define LSM6DSR_X_OFS_USR 0x73U
#define LSM6DSR_Y_OFS_USR 0x74U
#define LSM6DSR_Z_OFS_USR 0x75U
#define LSM6DSR_FIFO_DATA_OUT_TAG 0x78U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tag_parity : 1;
uint8_t tag_cnt : 2;
uint8_t tag_sensor : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t tag_sensor : 5;
+ uint8_t tag_cnt : 2;
+ uint8_t tag_parity : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fifo_data_out_tag_t;
#define LSM6DSR_FIFO_DATA_OUT_X_L 0x79U
@@ -628,58 +1118,103 @@ typedef struct {
#define LSM6DSR_FIFO_DATA_OUT_Z_L 0x7DU
#define LSM6DSR_FIFO_DATA_OUT_Z_H 0x7EU
#define LSM6DSR_PAGE_SEL 0x02U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 4;
uint8_t page_sel : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t page_sel : 4;
+ uint8_t not_used_01 : 4;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_page_sel_t;
#define LSM6DSR_ADV_PEDO 0x03U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t pedo_fpr_adf_dis : 1;
uint8_t not_used_02 : 6;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 6;
+ uint8_t pedo_fpr_adf_dis : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_adv_pedo_t;
#define LSM6DSR_EMB_FUNC_EN_A 0x04U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t pedo_en : 1;
uint8_t tilt_en : 1;
uint8_t sign_motion_en : 1;
uint8_t not_used_02 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 2;
+ uint8_t sign_motion_en : 1;
+ uint8_t tilt_en : 1;
+ uint8_t pedo_en : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_emb_func_en_a_t;
#define LSM6DSR_EMB_FUNC_EN_B 0x05U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fsm_en : 1;
uint8_t not_used_01 : 2;
uint8_t fifo_compr_en : 1;
uint8_t pedo_adv_en : 1;
uint8_t not_used_02 : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 3;
+ uint8_t pedo_adv_en : 1;
+ uint8_t fifo_compr_en : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t fsm_en : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_emb_func_en_b_t;
#define LSM6DSR_PAGE_ADDRESS 0x08U
-typedef struct {
+typedef struct
+{
uint8_t page_addr : 8;
} lsm6dsr_page_address_t;
#define LSM6DSR_PAGE_VALUE 0x09U
-typedef struct {
+typedef struct
+{
uint8_t page_value : 8;
} lsm6dsr_page_value_t;
#define LSM6DSR_EMB_FUNC_INT1 0x0AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t int1_step_detector : 1;
uint8_t int1_tilt : 1;
uint8_t int1_sig_mot : 1;
uint8_t not_used_02 : 1;
uint8_t int1_fsm_lc : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_fsm_lc : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t int1_sig_mot : 1;
+ uint8_t int1_tilt : 1;
+ uint8_t int1_step_detector : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_emb_func_int1_t;
#define LSM6DSR_FSM_INT1_A 0x0BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_fsm1 : 1;
uint8_t int1_fsm2 : 1;
uint8_t int1_fsm3 : 1;
@@ -688,10 +1223,22 @@ typedef struct {
uint8_t int1_fsm6 : 1;
uint8_t int1_fsm7 : 1;
uint8_t int1_fsm8 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_fsm8 : 1;
+ uint8_t int1_fsm7 : 1;
+ uint8_t int1_fsm6 : 1;
+ uint8_t int1_fsm5 : 1;
+ uint8_t int1_fsm4 : 1;
+ uint8_t int1_fsm3 : 1;
+ uint8_t int1_fsm2 : 1;
+ uint8_t int1_fsm1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fsm_int1_a_t;
#define LSM6DSR_FSM_INT1_B 0x0CU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_fsm9 : 1;
uint8_t int1_fsm10 : 1;
uint8_t int1_fsm11 : 1;
@@ -700,20 +1247,42 @@ typedef struct {
uint8_t int1_fsm14 : 1;
uint8_t int1_fsm15 : 1;
uint8_t int1_fsm16 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_fsm16 : 1;
+ uint8_t int1_fsm15 : 1;
+ uint8_t int1_fsm14 : 1;
+ uint8_t int1_fsm13 : 1;
+ uint8_t int1_fsm12 : 1;
+ uint8_t int1_fsm11 : 1;
+ uint8_t int1_fsm10 : 1;
+ uint8_t int1_fsm9 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fsm_int1_b_t;
#define LSM6DSR_EMB_FUNC_INT2 0x0EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t int2_step_detector : 1;
uint8_t int2_tilt : 1;
uint8_t int2_sig_mot : 1;
uint8_t not_used_02 : 1;
uint8_t int2_fsm_lc : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_fsm_lc : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t int2_sig_mot : 1;
+ uint8_t int2_tilt : 1;
+ uint8_t int2_step_detector : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_emb_func_int2_t;
#define LSM6DSR_FSM_INT2_A 0x0FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_fsm1 : 1;
uint8_t int2_fsm2 : 1;
uint8_t int2_fsm3 : 1;
@@ -722,10 +1291,22 @@ typedef struct {
uint8_t int2_fsm6 : 1;
uint8_t int2_fsm7 : 1;
uint8_t int2_fsm8 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_fsm8 : 1;
+ uint8_t int2_fsm7 : 1;
+ uint8_t int2_fsm6 : 1;
+ uint8_t int2_fsm5 : 1;
+ uint8_t int2_fsm4 : 1;
+ uint8_t int2_fsm3 : 1;
+ uint8_t int2_fsm2 : 1;
+ uint8_t int2_fsm1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fsm_int2_a_t;
#define LSM6DSR_FSM_INT2_B 0x10U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_fsm9 : 1;
uint8_t int2_fsm10 : 1;
uint8_t int2_fsm11 : 1;
@@ -734,20 +1315,42 @@ typedef struct {
uint8_t int2_fsm14 : 1;
uint8_t int2_fsm15 : 1;
uint8_t int2_fsm16 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_fsm16 : 1;
+ uint8_t int2_fsm15 : 1;
+ uint8_t int2_fsm14 : 1;
+ uint8_t int2_fsm13 : 1;
+ uint8_t int2_fsm12 : 1;
+ uint8_t int2_fsm11 : 1;
+ uint8_t int2_fsm10 : 1;
+ uint8_t int2_fsm9 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fsm_int2_b_t;
#define LSM6DSR_EMB_FUNC_STATUS 0x12U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t is_step_det : 1;
uint8_t is_tilt : 1;
uint8_t is_sigmot : 1;
uint8_t not_used_02 : 1;
uint8_t is_fsm_lc : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_fsm_lc : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t is_sigmot : 1;
+ uint8_t is_tilt : 1;
+ uint8_t is_step_det : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_emb_func_status_t;
#define LSM6DSR_FSM_STATUS_A 0x13U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_fsm1 : 1;
uint8_t is_fsm2 : 1;
uint8_t is_fsm3 : 1;
@@ -756,10 +1359,22 @@ typedef struct {
uint8_t is_fsm6 : 1;
uint8_t is_fsm7 : 1;
uint8_t is_fsm8 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_fsm8 : 1;
+ uint8_t is_fsm7 : 1;
+ uint8_t is_fsm6 : 1;
+ uint8_t is_fsm5 : 1;
+ uint8_t is_fsm4 : 1;
+ uint8_t is_fsm3 : 1;
+ uint8_t is_fsm2 : 1;
+ uint8_t is_fsm1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fsm_status_a_t;
#define LSM6DSR_FSM_STATUS_B 0x14U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_fsm9 : 1;
uint8_t is_fsm10 : 1;
uint8_t is_fsm11 : 1;
@@ -768,24 +1383,50 @@ typedef struct {
uint8_t is_fsm14 : 1;
uint8_t is_fsm15 : 1;
uint8_t is_fsm16 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t is_fsm16 : 1;
+ uint8_t is_fsm15 : 1;
+ uint8_t is_fsm14 : 1;
+ uint8_t is_fsm13 : 1;
+ uint8_t is_fsm12 : 1;
+ uint8_t is_fsm11 : 1;
+ uint8_t is_fsm10 : 1;
+ uint8_t is_fsm9 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fsm_status_b_t;
#define LSM6DSR_PAGE_RW 0x17U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 5;
uint8_t page_rw : 2; /* page_write + page_read */
uint8_t emb_func_lir : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t emb_func_lir : 1;
+ uint8_t page_rw : 2; /* page_write + page_read */
+ uint8_t not_used_01 : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_page_rw_t;
#define LSM6DSR_EMB_FUNC_FIFO_CFG 0x44U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 6;
uint8_t pedo_fifo_en : 1;
uint8_t not_used_02 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 1;
+ uint8_t pedo_fifo_en : 1;
+ uint8_t not_used_01 : 6;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_emb_func_fifo_cfg_t;
#define LSM6DSR_FSM_ENABLE_A 0x46U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fsm1_en : 1;
uint8_t fsm2_en : 1;
uint8_t fsm3_en : 1;
@@ -794,10 +1435,22 @@ typedef struct {
uint8_t fsm6_en : 1;
uint8_t fsm7_en : 1;
uint8_t fsm8_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fsm8_en : 1;
+ uint8_t fsm7_en : 1;
+ uint8_t fsm6_en : 1;
+ uint8_t fsm5_en : 1;
+ uint8_t fsm4_en : 1;
+ uint8_t fsm3_en : 1;
+ uint8_t fsm2_en : 1;
+ uint8_t fsm1_en : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fsm_enable_a_t;
#define LSM6DSR_FSM_ENABLE_B 0x47U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fsm9_en : 1;
uint8_t fsm10_en : 1;
uint8_t fsm11_en : 1;
@@ -806,18 +1459,38 @@ typedef struct {
uint8_t fsm14_en : 1;
uint8_t fsm15_en : 1;
uint8_t fsm16_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fsm16_en : 1;
+ uint8_t fsm15_en : 1;
+ uint8_t fsm14_en : 1;
+ uint8_t fsm13_en : 1;
+ uint8_t fsm12_en : 1;
+ uint8_t fsm11_en : 1;
+ uint8_t fsm10_en : 1;
+ uint8_t fsm9_en : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fsm_enable_b_t;
#define LSM6DSR_FSM_LONG_COUNTER_L 0x48U
#define LSM6DSR_FSM_LONG_COUNTER_H 0x49U
#define LSM6DSR_FSM_LONG_COUNTER_CLEAR 0x4AU
-typedef struct {
- uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+uint8_t fsm_lc_clr :
+ 2; /* fsm_lc_cleared + fsm_lc_clear */
uint8_t not_used_01 : 6;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 6;
+uint8_t fsm_lc_clr :
+ 2; /* fsm_lc_cleared + fsm_lc_clear */
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fsm_long_counter_clear_t;
#define LSM6DSR_FSM_OUTS1 0x4CU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -826,10 +1499,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fsm_outs1_t;
#define LSM6DSR_FSM_OUTS2 0x4DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -838,10 +1523,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fsm_outs2_t;
#define LSM6DSR_FSM_OUTS3 0x4EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -850,10 +1547,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fsm_outs3_t;
#define LSM6DSR_FSM_OUTS4 0x4FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -862,10 +1571,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fsm_outs4_t;
#define LSM6DSR_FSM_OUTS5 0x50U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -874,10 +1595,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fsm_outs5_t;
#define LSM6DSR_FSM_OUTS6 0x51U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -886,10 +1619,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fsm_outs6_t;
#define LSM6DSR_FSM_OUTS7 0x52U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -898,10 +1643,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fsm_outs7_t;
#define LSM6DSR_FSM_OUTS8 0x53U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -910,10 +1667,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fsm_outs8_t;
#define LSM6DSR_FSM_OUTS9 0x54U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -922,10 +1691,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fsm_outs9_t;
#define LSM6DSR_FSM_OUTS10 0x55U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -934,10 +1715,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fsm_outs10_t;
#define LSM6DSR_FSM_OUTS11 0x56U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -946,10 +1739,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fsm_outs11_t;
#define LSM6DSR_FSM_OUTS12 0x57U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -958,10 +1763,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fsm_outs12_t;
#define LSM6DSR_FSM_OUTS13 0x58U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -970,10 +1787,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fsm_outs13_t;
#define LSM6DSR_FSM_OUTS14 0x59U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -982,10 +1811,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fsm_outs14_t;
#define LSM6DSR_FSM_OUTS15 0x5AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -994,10 +1835,22 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fsm_outs15_t;
#define LSM6DSR_FSM_OUTS16 0x5BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
uint8_t n_z : 1;
@@ -1006,19 +1859,38 @@ typedef struct {
uint8_t p_y : 1;
uint8_t n_x : 1;
uint8_t p_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t p_x : 1;
+ uint8_t n_x : 1;
+ uint8_t p_y : 1;
+ uint8_t n_y : 1;
+ uint8_t p_z : 1;
+ uint8_t n_z : 1;
+ uint8_t p_v : 1;
+ uint8_t n_v : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_fsm_outs16_t;
#define LSM6DSR_EMB_FUNC_ODR_CFG_B 0x5FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t fsm_odr : 2;
uint8_t not_used_02 : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 3;
+ uint8_t fsm_odr : 2;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_emb_func_odr_cfg_b_t;
#define LSM6DSR_STEP_COUNTER_L 0x62U
#define LSM6DSR_STEP_COUNTER_H 0x63U
#define LSM6DSR_EMB_FUNC_SRC 0x64U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t stepcounter_bit_set : 1;
uint8_t step_overflow : 1;
@@ -1026,23 +1898,49 @@ typedef struct {
uint8_t step_detected : 1;
uint8_t not_used_02 : 1;
uint8_t pedo_rst_step : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t pedo_rst_step : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t step_detected : 1;
+ uint8_t step_count_delta_ia : 1;
+ uint8_t step_overflow : 1;
+ uint8_t stepcounter_bit_set : 1;
+ uint8_t not_used_01 : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_emb_func_src_t;
#define LSM6DSR_EMB_FUNC_INIT_A 0x66U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t step_det_init : 1;
uint8_t tilt_init : 1;
uint8_t sig_mot_init : 1;
uint8_t not_used_02 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 2;
+ uint8_t sig_mot_init : 1;
+ uint8_t tilt_init : 1;
+ uint8_t step_det_init : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_emb_func_init_a_t;
#define LSM6DSR_EMB_FUNC_INIT_B 0x67U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fsm_init : 1;
uint8_t not_used_01 : 2;
uint8_t fifo_compr_init : 1;
uint8_t not_used_02 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 4;
+ uint8_t fifo_compr_init : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t fsm_init : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_emb_func_init_b_t;
#define LSM6DSR_MAG_SENSITIVITY_L 0xBAU
@@ -1066,17 +1964,31 @@ typedef struct {
#define LSM6DSR_MAG_SI_ZZ_L 0xD0U
#define LSM6DSR_MAG_SI_ZZ_H 0xD1U
#define LSM6DSR_MAG_CFG_A 0xD4U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t mag_z_axis : 3;
uint8_t not_used_01 : 1;
uint8_t mag_y_axis : 3;
uint8_t not_used_02 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 1;
+ uint8_t mag_y_axis : 3;
+ uint8_t not_used_01 : 1;
+ uint8_t mag_z_axis : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_mag_cfg_a_t;
#define LSM6DSR_MAG_CFG_B 0xD5U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t mag_x_axis : 3;
uint8_t not_used_01 : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 5;
+ uint8_t mag_x_axis : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_mag_cfg_b_t;
#define LSM6DSR_FSM_LC_TIMEOUT_L 0x17AU
@@ -1085,235 +1997,462 @@ typedef struct {
#define LSM6DSR_FSM_START_ADD_L 0x17EU
#define LSM6DSR_FSM_START_ADD_H 0x17FU
#define LSM6DSR_PEDO_CMD_REG 0x183U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ad_det_en : 1;
uint8_t not_used_01 : 1;
uint8_t fp_rejection_en : 1;
uint8_t carry_count_en : 1;
uint8_t not_used_02 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 4;
+ uint8_t carry_count_en : 1;
+ uint8_t fp_rejection_en : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t ad_det_en : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_pedo_cmd_reg_t;
#define LSM6DSR_PEDO_DEB_STEPS_CONF 0x184U
#define LSM6DSR_PEDO_SC_DELTAT_L 0x1D0U
#define LSM6DSR_PEDO_SC_DELTAT_H 0x1D1U
#define LSM6DSR_SENSOR_HUB_1 0x02U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_sensor_hub_1_t;
#define LSM6DSR_SENSOR_HUB_2 0x03U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_sensor_hub_2_t;
#define LSM6DSR_SENSOR_HUB_3 0x04U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_sensor_hub_3_t;
#define LSM6DSR_SENSOR_HUB_4 0x05U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_sensor_hub_4_t;
#define LSM6DSR_SENSOR_HUB_5 0x06U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_sensor_hub_5_t;
#define LSM6DSR_SENSOR_HUB_6 0x07U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_sensor_hub_6_t;
#define LSM6DSR_SENSOR_HUB_7 0x08U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_sensor_hub_7_t;
#define LSM6DSR_SENSOR_HUB_8 0x09U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_sensor_hub_8_t;
#define LSM6DSR_SENSOR_HUB_9 0x0AU
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_sensor_hub_9_t;
#define LSM6DSR_SENSOR_HUB_10 0x0BU
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_sensor_hub_10_t;
#define LSM6DSR_SENSOR_HUB_11 0x0CU
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_sensor_hub_11_t;
#define LSM6DSR_SENSOR_HUB_12 0x0DU
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_sensor_hub_12_t;
#define LSM6DSR_SENSOR_HUB_13 0x0EU
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_sensor_hub_13_t;
#define LSM6DSR_SENSOR_HUB_14 0x0FU
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_sensor_hub_14_t;
#define LSM6DSR_SENSOR_HUB_15 0x10U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_sensor_hub_15_t;
#define LSM6DSR_SENSOR_HUB_16 0x11U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_sensor_hub_16_t;
#define LSM6DSR_SENSOR_HUB_17 0x12U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_sensor_hub_17_t;
#define LSM6DSR_SENSOR_HUB_18 0x13U
-typedef struct {
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_sensor_hub_18_t;
#define LSM6DSR_MASTER_CONFIG 0x14U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t aux_sens_on : 2;
uint8_t master_on : 1;
uint8_t shub_pu_en : 1;
@@ -1321,88 +2460,157 @@ typedef struct {
uint8_t start_config : 1;
uint8_t write_once : 1;
uint8_t rst_master_regs : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t rst_master_regs : 1;
+ uint8_t write_once : 1;
+ uint8_t start_config : 1;
+ uint8_t pass_through_mode : 1;
+ uint8_t shub_pu_en : 1;
+ uint8_t master_on : 1;
+ uint8_t aux_sens_on : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_master_config_t;
#define LSM6DSR_SLV0_ADD 0x15U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t rw_0 : 1;
uint8_t slave0 : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave0 : 7;
+ uint8_t rw_0 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_slv0_add_t;
#define LSM6DSR_SLV0_SUBADD 0x16U
-typedef struct {
+typedef struct
+{
uint8_t slave0_reg : 8;
} lsm6dsr_slv0_subadd_t;
#define LSM6DSR_SLV0_CONFIG 0x17U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave0_numop : 3;
uint8_t batch_ext_sens_0_en : 1;
uint8_t not_used_01 : 2;
uint8_t shub_odr : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t shub_odr : 2;
+ uint8_t not_used_01 : 2;
+ uint8_t batch_ext_sens_0_en : 1;
+ uint8_t slave0_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_slv0_config_t;
#define LSM6DSR_SLV1_ADD 0x18U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_1 : 1;
uint8_t slave1_add : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave1_add : 7;
+ uint8_t r_1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_slv1_add_t;
#define LSM6DSR_SLV1_SUBADD 0x19U
-typedef struct {
+typedef struct
+{
uint8_t slave1_reg : 8;
} lsm6dsr_slv1_subadd_t;
#define LSM6DSR_SLV1_CONFIG 0x1AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave1_numop : 3;
uint8_t batch_ext_sens_1_en : 1;
uint8_t not_used_01 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 4;
+ uint8_t batch_ext_sens_1_en : 1;
+ uint8_t slave1_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_slv1_config_t;
#define LSM6DSR_SLV2_ADD 0x1BU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_2 : 1;
uint8_t slave2_add : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave2_add : 7;
+ uint8_t r_2 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_slv2_add_t;
#define LSM6DSR_SLV2_SUBADD 0x1CU
-typedef struct {
+typedef struct
+{
uint8_t slave2_reg : 8;
} lsm6dsr_slv2_subadd_t;
#define LSM6DSR_SLV2_CONFIG 0x1DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave2_numop : 3;
uint8_t batch_ext_sens_2_en : 1;
uint8_t not_used_01 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 4;
+ uint8_t batch_ext_sens_2_en : 1;
+ uint8_t slave2_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_slv2_config_t;
#define LSM6DSR_SLV3_ADD 0x1EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_3 : 1;
uint8_t slave3_add : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t slave3_add : 7;
+ uint8_t r_3 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_slv3_add_t;
#define LSM6DSR_SLV3_SUBADD 0x1FU
-typedef struct {
+typedef struct
+{
uint8_t slave3_reg : 8;
} lsm6dsr_slv3_subadd_t;
#define LSM6DSR_SLV3_CONFIG 0x20U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave3_numop : 3;
uint8_t batch_ext_sens_3_en : 1;
uint8_t not_used_01 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 4;
+ uint8_t batch_ext_sens_3_en : 1;
+ uint8_t slave3_numop : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_slv3_config_t;
#define LSM6DSR_DATAWRITE_SLV0 0x21U
-typedef struct {
+typedef struct
+{
uint8_t slave0_dataw : 8;
} lsm6dsr_datawrite_slv0_t;
#define LSM6DSR_STATUS_MASTER 0x22U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sens_hub_endop : 1;
uint8_t not_used_01 : 2;
uint8_t slave0_nack : 1;
@@ -1410,13 +2618,22 @@ typedef struct {
uint8_t slave2_nack : 1;
uint8_t slave3_nack : 1;
uint8_t wr_once_done : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t wr_once_done : 1;
+ uint8_t slave3_nack : 1;
+ uint8_t slave2_nack : 1;
+ uint8_t slave1_nack : 1;
+ uint8_t slave0_nack : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t sens_hub_endop : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm6dsr_status_master_t;
/**
* @defgroup LSM6DSR_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -1424,7 +2641,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
lsm6dsr_func_cfg_access_t func_cfg_access;
lsm6dsr_pin_ctrl_t pin_ctrl;
lsm6dsr_s4s_tph_l_t s4s_tph_l;
@@ -1490,7 +2708,7 @@ typedef union{
lsm6dsr_fsm_status_a_t fsm_status_a;
lsm6dsr_fsm_status_b_t fsm_status_b;
lsm6dsr_page_rw_t page_rw;
- lsm6dsr_emb_func_fifo_cfg_t emb_func_fifo_cfg;
+ lsm6dsr_emb_func_fifo_cfg_t emb_func_fifo_cfg;
lsm6dsr_fsm_enable_a_t fsm_enable_a;
lsm6dsr_fsm_enable_b_t fsm_enable_b;
lsm6dsr_fsm_long_counter_clear_t fsm_long_counter_clear;
@@ -1559,34 +2777,43 @@ typedef union{
*
*/
-int32_t lsm6dsr_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lsm6dsr_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t lsm6dsr_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lsm6dsr_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-extern float_t lsm6dsr_from_fs2g_to_mg(int16_t lsb);
-extern float_t lsm6dsr_from_fs4g_to_mg(int16_t lsb);
-extern float_t lsm6dsr_from_fs8g_to_mg(int16_t lsb);
-extern float_t lsm6dsr_from_fs16g_to_mg(int16_t lsb);
-extern float_t lsm6dsr_from_fs125dps_to_mdps(int16_t lsb);
-extern float_t lsm6dsr_from_fs250dps_to_mdps(int16_t lsb);
-extern float_t lsm6dsr_from_fs500dps_to_mdps(int16_t lsb);
-extern float_t lsm6dsr_from_fs1000dps_to_mdps(int16_t lsb);
-extern float_t lsm6dsr_from_fs2000dps_to_mdps(int16_t lsb);
-extern float_t lsm6dsr_from_fs4000dps_to_mdps(int16_t lsb);
-extern float_t lsm6dsr_from_lsb_to_celsius(int16_t lsb);
-extern float_t lsm6dsr_from_lsb_to_nsec(int32_t lsb);
-
-typedef enum {
+float_t lsm6dsr_from_fs2g_to_mg(int16_t lsb);
+float_t lsm6dsr_from_fs4g_to_mg(int16_t lsb);
+float_t lsm6dsr_from_fs8g_to_mg(int16_t lsb);
+float_t lsm6dsr_from_fs16g_to_mg(int16_t lsb);
+
+float_t lsm6dsr_from_fs125dps_to_mdps(int16_t lsb);
+float_t lsm6dsr_from_fs250dps_to_mdps(int16_t lsb);
+float_t lsm6dsr_from_fs500dps_to_mdps(int16_t lsb);
+float_t lsm6dsr_from_fs1000dps_to_mdps(int16_t lsb);
+float_t lsm6dsr_from_fs2000dps_to_mdps(int16_t lsb);
+float_t lsm6dsr_from_fs4000dps_to_mdps(int16_t lsb);
+
+float_t lsm6dsr_from_lsb_to_celsius(int16_t lsb);
+
+float_t lsm6dsr_from_lsb_to_nsec(int32_t lsb);
+
+typedef enum
+{
LSM6DSR_2g = 0,
LSM6DSR_16g = 1, /* if XL_FS_MODE = '1' -> LSM6DSR_2g */
LSM6DSR_4g = 2,
LSM6DSR_8g = 3,
} lsm6dsr_fs_xl_t;
-int32_t lsm6dsr_xl_full_scale_set(stmdev_ctx_t *ctx, lsm6dsr_fs_xl_t val);
-int32_t lsm6dsr_xl_full_scale_get(stmdev_ctx_t *ctx, lsm6dsr_fs_xl_t *val);
+int32_t lsm6dsr_xl_full_scale_set(stmdev_ctx_t *ctx,
+ lsm6dsr_fs_xl_t val);
+int32_t lsm6dsr_xl_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6dsr_fs_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_XL_ODR_OFF = 0,
LSM6DSR_XL_ODR_12Hz5 = 1,
LSM6DSR_XL_ODR_26Hz = 2,
@@ -1600,10 +2827,13 @@ typedef enum {
LSM6DSR_XL_ODR_6667Hz = 10,
LSM6DSR_XL_ODR_6Hz5 = 11, /* (low power only) */
} lsm6dsr_odr_xl_t;
-int32_t lsm6dsr_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6dsr_odr_xl_t val);
-int32_t lsm6dsr_xl_data_rate_get(stmdev_ctx_t *ctx, lsm6dsr_odr_xl_t *val);
+int32_t lsm6dsr_xl_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dsr_odr_xl_t val);
+int32_t lsm6dsr_xl_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dsr_odr_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_125dps = 2,
LSM6DSR_250dps = 0,
LSM6DSR_500dps = 4,
@@ -1611,10 +2841,13 @@ typedef enum {
LSM6DSR_2000dps = 12,
LSM6DSR_4000dps = 1,
} lsm6dsr_fs_g_t;
-int32_t lsm6dsr_gy_full_scale_set(stmdev_ctx_t *ctx, lsm6dsr_fs_g_t val);
-int32_t lsm6dsr_gy_full_scale_get(stmdev_ctx_t *ctx, lsm6dsr_fs_g_t *val);
+int32_t lsm6dsr_gy_full_scale_set(stmdev_ctx_t *ctx,
+ lsm6dsr_fs_g_t val);
+int32_t lsm6dsr_gy_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6dsr_fs_g_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_GY_ODR_OFF = 0,
LSM6DSR_GY_ODR_12Hz5 = 1,
LSM6DSR_GY_ODR_26Hz = 2,
@@ -1633,9 +2866,11 @@ int32_t lsm6dsr_gy_data_rate_get(stmdev_ctx_t *ctx,
lsm6dsr_odr_g_t *val);
int32_t lsm6dsr_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsr_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsr_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_LSb_1mg = 0,
LSM6DSR_LSb_16mg = 1,
} lsm6dsr_usr_off_w_t;
@@ -1644,7 +2879,8 @@ int32_t lsm6dsr_xl_offset_weight_set(stmdev_ctx_t *ctx,
int32_t lsm6dsr_xl_offset_weight_get(stmdev_ctx_t *ctx,
lsm6dsr_usr_off_w_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_HIGH_PERFORMANCE_MD = 0,
LSM6DSR_LOW_NORMAL_POWER_MD = 1,
} lsm6dsr_xl_hm_mode_t;
@@ -1653,7 +2889,8 @@ int32_t lsm6dsr_xl_power_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dsr_xl_power_mode_get(stmdev_ctx_t *ctx,
lsm6dsr_xl_hm_mode_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_GY_HIGH_PERFORMANCE = 0,
LSM6DSR_GY_NORMAL = 1,
} lsm6dsr_g_hm_mode_t;
@@ -1662,7 +2899,8 @@ int32_t lsm6dsr_gy_power_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dsr_gy_power_mode_get(stmdev_ctx_t *ctx,
lsm6dsr_g_hm_mode_t *val);
-typedef struct {
+typedef struct
+{
lsm6dsr_all_int_src_t all_int_src;
lsm6dsr_wake_up_src_t wake_up_src;
lsm6dsr_tap_src_t tap_src;
@@ -1671,18 +2909,21 @@ typedef struct {
lsm6dsr_emb_func_status_t emb_func_status;
lsm6dsr_fsm_status_a_t fsm_status_a;
lsm6dsr_fsm_status_b_t fsm_status_b;
- } lsm6dsr_all_sources_t;
+} lsm6dsr_all_sources_t;
int32_t lsm6dsr_all_sources_get(stmdev_ctx_t *ctx,
lsm6dsr_all_sources_t *val);
int32_t lsm6dsr_status_reg_get(stmdev_ctx_t *ctx,
- lsm6dsr_status_reg_t *val);
+ lsm6dsr_status_reg_t *val);
-int32_t lsm6dsr_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsr_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsr_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsr_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsr_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsr_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dsr_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t lsm6dsr_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff);
@@ -1701,9 +2942,10 @@ int32_t lsm6dsr_timestamp_rst(stmdev_ctx_t *ctx);
int32_t lsm6dsr_timestamp_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsr_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dsr_timestamp_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsr_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_NO_ROUND = 0,
LSM6DSR_ROUND_XL = 1,
LSM6DSR_ROUND_GY = 2,
@@ -1714,28 +2956,31 @@ int32_t lsm6dsr_rounding_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dsr_rounding_mode_get(stmdev_ctx_t *ctx,
lsm6dsr_rounding_t *val);
-int32_t lsm6dsr_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsr_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val);
-int32_t lsm6dsr_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsr_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val);
-int32_t lsm6dsr_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsr_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val);
int32_t lsm6dsr_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t lsm6dsr_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsr_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dsr_number_of_steps_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsr_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val);
int32_t lsm6dsr_steps_reset(stmdev_ctx_t *ctx);
-typedef enum {
+typedef enum
+{
LSM6DSR_USER_BANK = 0,
LSM6DSR_SENSOR_HUB_BANK = 1,
LSM6DSR_EMBEDDED_FUNC_BANK = 2,
} lsm6dsr_reg_access_t;
-int32_t lsm6dsr_mem_bank_set(stmdev_ctx_t *ctx, lsm6dsr_reg_access_t val);
-int32_t lsm6dsr_mem_bank_get(stmdev_ctx_t *ctx, lsm6dsr_reg_access_t *val);
+int32_t lsm6dsr_mem_bank_set(stmdev_ctx_t *ctx,
+ lsm6dsr_reg_access_t val);
+int32_t lsm6dsr_mem_bank_get(stmdev_ctx_t *ctx,
+ lsm6dsr_reg_access_t *val);
int32_t lsm6dsr_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address,
uint8_t *val);
@@ -1743,9 +2988,11 @@ int32_t lsm6dsr_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address,
uint8_t *buf, uint8_t len);
int32_t lsm6dsr_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add,
uint8_t *val);
-int32_t lsm6dsr_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *val);
+int32_t lsm6dsr_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_DRDY_LATCHED = 0,
LSM6DSR_DRDY_PULSED = 1,
} lsm6dsr_dataready_pulsed_t;
@@ -1765,21 +3012,27 @@ int32_t lsm6dsr_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsr_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsr_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_XL_ST_DISABLE = 0,
LSM6DSR_XL_ST_POSITIVE = 1,
LSM6DSR_XL_ST_NEGATIVE = 2,
} lsm6dsr_st_xl_t;
-int32_t lsm6dsr_xl_self_test_set(stmdev_ctx_t *ctx, lsm6dsr_st_xl_t val);
-int32_t lsm6dsr_xl_self_test_get(stmdev_ctx_t *ctx, lsm6dsr_st_xl_t *val);
+int32_t lsm6dsr_xl_self_test_set(stmdev_ctx_t *ctx,
+ lsm6dsr_st_xl_t val);
+int32_t lsm6dsr_xl_self_test_get(stmdev_ctx_t *ctx,
+ lsm6dsr_st_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_GY_ST_DISABLE = 0,
LSM6DSR_GY_ST_POSITIVE = 1,
LSM6DSR_GY_ST_NEGATIVE = 3,
} lsm6dsr_st_g_t;
-int32_t lsm6dsr_gy_self_test_set(stmdev_ctx_t *ctx, lsm6dsr_st_g_t val);
-int32_t lsm6dsr_gy_self_test_get(stmdev_ctx_t *ctx, lsm6dsr_st_g_t *val);
+int32_t lsm6dsr_gy_self_test_set(stmdev_ctx_t *ctx,
+ lsm6dsr_st_g_t val);
+int32_t lsm6dsr_gy_self_test_get(stmdev_ctx_t *ctx,
+ lsm6dsr_st_g_t *val);
int32_t lsm6dsr_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsr_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -1787,10 +3040,13 @@ int32_t lsm6dsr_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsr_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsr_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dsr_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsr_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsr_filter_settling_mask_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsr_filter_settling_mask_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_ULTRA_LIGHT = 0,
LSM6DSR_VERY_LIGHT = 1,
LSM6DSR_LIGHT = 2,
@@ -1800,13 +3056,16 @@ typedef enum {
LSM6DSR_AGGRESSIVE = 6,
LSM6DSR_XTREME = 7,
} lsm6dsr_ftype_t;
-int32_t lsm6dsr_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, lsm6dsr_ftype_t val);
-int32_t lsm6dsr_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, lsm6dsr_ftype_t *val);
+int32_t lsm6dsr_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
+ lsm6dsr_ftype_t val);
+int32_t lsm6dsr_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
+ lsm6dsr_ftype_t *val);
int32_t lsm6dsr_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsr_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_HP_PATH_DISABLE_ON_OUT = 0x00,
LSM6DSR_SLOPE_ODR_DIV_4 = 0x10,
LSM6DSR_HP_ODR_DIV_10 = 0x11,
@@ -1839,7 +3098,8 @@ int32_t lsm6dsr_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
int32_t lsm6dsr_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsr_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_USE_SLOPE = 0,
LSM6DSR_USE_HPF = 1,
} lsm6dsr_slope_fds_t;
@@ -1848,7 +3108,8 @@ int32_t lsm6dsr_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
int32_t lsm6dsr_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
lsm6dsr_slope_fds_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_HP_FILTER_NONE = 0x00,
LSM6DSR_HP_FILTER_16mHz = 0x80,
LSM6DSR_HP_FILTER_65mHz = 0x81,
@@ -1860,7 +3121,8 @@ int32_t lsm6dsr_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
int32_t lsm6dsr_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
lsm6dsr_hpm_g_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_AUX_PULL_UP_DISC = 0,
LSM6DSR_AUX_PULL_UP_CONNECT = 1,
} lsm6dsr_ois_pu_dis_t;
@@ -1869,23 +3131,30 @@ int32_t lsm6dsr_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dsr_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx,
lsm6dsr_ois_pu_dis_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_AUX_ON = 1,
LSM6DSR_AUX_ON_BY_AUX_INTERFACE = 0,
} lsm6dsr_ois_on_t;
-int32_t lsm6dsr_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx, lsm6dsr_ois_on_t val);
-int32_t lsm6dsr_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx, lsm6dsr_ois_on_t *val);
+int32_t lsm6dsr_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx,
+ lsm6dsr_ois_on_t val);
+int32_t lsm6dsr_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx,
+ lsm6dsr_ois_on_t *val);
int32_t lsm6dsr_aux_status_reg_get(stmdev_ctx_t *ctx,
lsm6dsr_status_spiaux_t *val);
-int32_t lsm6dsr_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsr_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsr_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsr_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsr_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsr_aux_gy_flag_settling_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_AUX_XL_DISABLE = 0,
LSM6DSR_AUX_XL_POS = 1,
LSM6DSR_AUX_XL_NEG = 2,
@@ -1895,7 +3164,8 @@ int32_t lsm6dsr_aux_xl_self_test_set(stmdev_ctx_t *ctx,
int32_t lsm6dsr_aux_xl_self_test_get(stmdev_ctx_t *ctx,
lsm6dsr_st_xl_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_AUX_DEN_ACTIVE_LOW = 0,
LSM6DSR_AUX_DEN_ACTIVE_HIGH = 1,
} lsm6dsr_den_lh_ois_t;
@@ -1904,26 +3174,33 @@ int32_t lsm6dsr_aux_den_polarity_set(stmdev_ctx_t *ctx,
int32_t lsm6dsr_aux_den_polarity_get(stmdev_ctx_t *ctx,
lsm6dsr_den_lh_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_AUX_DEN_DISABLE = 0,
LSM6DSR_AUX_DEN_LEVEL_LATCH = 3,
LSM6DSR_AUX_DEN_LEVEL_TRIG = 2,
} lsm6dsr_lvl2_ois_t;
-int32_t lsm6dsr_aux_den_mode_set(stmdev_ctx_t *ctx, lsm6dsr_lvl2_ois_t val);
-int32_t lsm6dsr_aux_den_mode_get(stmdev_ctx_t *ctx, lsm6dsr_lvl2_ois_t *val);
+int32_t lsm6dsr_aux_den_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsr_lvl2_ois_t val);
+int32_t lsm6dsr_aux_den_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsr_lvl2_ois_t *val);
int32_t lsm6dsr_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsr_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_AUX_DISABLE = 0,
LSM6DSR_MODE_3_GY = 1,
LSM6DSR_MODE_4_GY_XL = 3,
} lsm6dsr_ois_en_spi2_t;
-int32_t lsm6dsr_aux_mode_set(stmdev_ctx_t *ctx, lsm6dsr_ois_en_spi2_t val);
-int32_t lsm6dsr_aux_mode_get(stmdev_ctx_t *ctx, lsm6dsr_ois_en_spi2_t *val);
+int32_t lsm6dsr_aux_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsr_ois_en_spi2_t val);
+int32_t lsm6dsr_aux_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsr_ois_en_spi2_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_125dps_AUX = 0x04,
LSM6DSR_250dps_AUX = 0x00,
LSM6DSR_500dps_AUX = 0x01,
@@ -1935,14 +3212,18 @@ int32_t lsm6dsr_aux_gy_full_scale_set(stmdev_ctx_t *ctx,
int32_t lsm6dsr_aux_gy_full_scale_get(stmdev_ctx_t *ctx,
lsm6dsr_fs_g_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_AUX_SPI_4_WIRE = 0,
LSM6DSR_AUX_SPI_3_WIRE = 1,
} lsm6dsr_sim_ois_t;
-int32_t lsm6dsr_aux_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsr_sim_ois_t val);
-int32_t lsm6dsr_aux_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsr_sim_ois_t *val);
+int32_t lsm6dsr_aux_spi_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsr_sim_ois_t val);
+int32_t lsm6dsr_aux_spi_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsr_sim_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_351Hz39 = 0,
LSM6DSR_236Hz63 = 1,
LSM6DSR_172Hz70 = 2,
@@ -1953,7 +3234,8 @@ int32_t lsm6dsr_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
int32_t lsm6dsr_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
lsm6dsr_ftype_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_AUX_HP_DISABLE = 0x00,
LSM6DSR_AUX_HP_Hz016 = 0x10,
LSM6DSR_AUX_HP_Hz065 = 0x11,
@@ -1965,7 +3247,8 @@ int32_t lsm6dsr_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx,
int32_t lsm6dsr_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx,
lsm6dsr_hpm_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_ENABLE_CLAMP = 0,
LSM6DSR_DISABLE_CLAMP = 1,
} lsm6dsr_st_ois_clampdis_t;
@@ -1974,7 +3257,8 @@ int32_t lsm6dsr_aux_gy_clamp_set(stmdev_ctx_t *ctx,
int32_t lsm6dsr_aux_gy_clamp_get(stmdev_ctx_t *ctx,
lsm6dsr_st_ois_clampdis_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_AUX_GY_DISABLE = 0,
LSM6DSR_AUX_GY_POS = 1,
LSM6DSR_AUX_GY_NEG = 3,
@@ -1984,7 +3268,8 @@ int32_t lsm6dsr_aux_gy_self_test_set(stmdev_ctx_t *ctx,
int32_t lsm6dsr_aux_gy_self_test_get(stmdev_ctx_t *ctx,
lsm6dsr_st_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_631Hz = 0,
LSM6DSR_295Hz = 1,
LSM6DSR_140Hz = 2,
@@ -1999,7 +3284,8 @@ int32_t lsm6dsr_aux_xl_bandwidth_set(stmdev_ctx_t *ctx,
int32_t lsm6dsr_aux_xl_bandwidth_get(stmdev_ctx_t *ctx,
lsm6dsr_filter_xl_conf_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_AUX_2g = 0,
LSM6DSR_AUX_16g = 1,
LSM6DSR_AUX_4g = 2,
@@ -2010,28 +3296,36 @@ int32_t lsm6dsr_aux_xl_full_scale_set(stmdev_ctx_t *ctx,
int32_t lsm6dsr_aux_xl_full_scale_get(stmdev_ctx_t *ctx,
lsm6dsr_fs_xl_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_PULL_UP_DISC = 0,
LSM6DSR_PULL_UP_CONNECT = 1,
} lsm6dsr_sdo_pu_en_t;
-int32_t lsm6dsr_sdo_sa0_mode_set(stmdev_ctx_t *ctx, lsm6dsr_sdo_pu_en_t val);
-int32_t lsm6dsr_sdo_sa0_mode_get(stmdev_ctx_t *ctx, lsm6dsr_sdo_pu_en_t *val);
+int32_t lsm6dsr_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsr_sdo_pu_en_t val);
+int32_t lsm6dsr_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsr_sdo_pu_en_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_PULL_DOWN_CONNECT = 0,
LSM6DSR_PULL_DOWN_DISC = 1,
} lsm6dsr_pd_dis_int1_t;
-int32_t lsm6dsr_int1_mode_set(stmdev_ctx_t *ctx, lsm6dsr_pd_dis_int1_t val);
-int32_t lsm6dsr_int1_mode_get(stmdev_ctx_t *ctx, lsm6dsr_pd_dis_int1_t *val);
+int32_t lsm6dsr_int1_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsr_pd_dis_int1_t val);
+int32_t lsm6dsr_int1_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsr_pd_dis_int1_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_SPI_4_WIRE = 0,
LSM6DSR_SPI_3_WIRE = 1,
} lsm6dsr_sim_t;
int32_t lsm6dsr_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsr_sim_t val);
int32_t lsm6dsr_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsr_sim_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_I2C_ENABLE = 0,
LSM6DSR_I2C_DISABLE = 1,
} lsm6dsr_i2c_disable_t;
@@ -2040,7 +3334,8 @@ int32_t lsm6dsr_i2c_interface_set(stmdev_ctx_t *ctx,
int32_t lsm6dsr_i2c_interface_get(stmdev_ctx_t *ctx,
lsm6dsr_i2c_disable_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_I3C_DISABLE = 0x80,
LSM6DSR_I3C_ENABLE_T_50us = 0x00,
LSM6DSR_I3C_ENABLE_T_2us = 0x01,
@@ -2052,19 +3347,21 @@ int32_t lsm6dsr_i3c_disable_set(stmdev_ctx_t *ctx,
int32_t lsm6dsr_i3c_disable_get(stmdev_ctx_t *ctx,
lsm6dsr_i3c_disable_t *val);
-typedef struct {
- lsm6dsr_int1_ctrl_t int1_ctrl;
- lsm6dsr_md1_cfg_t md1_cfg;
- lsm6dsr_emb_func_int1_t emb_func_int1;
- lsm6dsr_fsm_int1_a_t fsm_int1_a;
- lsm6dsr_fsm_int1_b_t fsm_int1_b;
+typedef struct
+{
+ lsm6dsr_int1_ctrl_t int1_ctrl;
+ lsm6dsr_md1_cfg_t md1_cfg;
+ lsm6dsr_emb_func_int1_t emb_func_int1;
+ lsm6dsr_fsm_int1_a_t fsm_int1_a;
+ lsm6dsr_fsm_int1_b_t fsm_int1_b;
} lsm6dsr_pin_int1_route_t;
int32_t lsm6dsr_pin_int1_route_set(stmdev_ctx_t *ctx,
lsm6dsr_pin_int1_route_t *val);
int32_t lsm6dsr_pin_int1_route_get(stmdev_ctx_t *ctx,
lsm6dsr_pin_int1_route_t *val);
-typedef struct {
+typedef struct
+{
lsm6dsr_int2_ctrl_t int2_ctrl;
lsm6dsr_md2_cfg_t md2_cfg;
lsm6dsr_emb_func_int2_t emb_func_int2;
@@ -2076,33 +3373,41 @@ int32_t lsm6dsr_pin_int2_route_set(stmdev_ctx_t *ctx,
int32_t lsm6dsr_pin_int2_route_get(stmdev_ctx_t *ctx,
lsm6dsr_pin_int2_route_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_PUSH_PULL = 0,
LSM6DSR_OPEN_DRAIN = 1,
} lsm6dsr_pp_od_t;
int32_t lsm6dsr_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsr_pp_od_t val);
int32_t lsm6dsr_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsr_pp_od_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_ACTIVE_HIGH = 0,
LSM6DSR_ACTIVE_LOW = 1,
} lsm6dsr_h_lactive_t;
-int32_t lsm6dsr_pin_polarity_set(stmdev_ctx_t *ctx, lsm6dsr_h_lactive_t val);
-int32_t lsm6dsr_pin_polarity_get(stmdev_ctx_t *ctx, lsm6dsr_h_lactive_t *val);
+int32_t lsm6dsr_pin_polarity_set(stmdev_ctx_t *ctx,
+ lsm6dsr_h_lactive_t val);
+int32_t lsm6dsr_pin_polarity_get(stmdev_ctx_t *ctx,
+ lsm6dsr_h_lactive_t *val);
int32_t lsm6dsr_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsr_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_ALL_INT_PULSED = 0,
LSM6DSR_BASE_LATCHED_EMB_PULSED = 1,
LSM6DSR_BASE_PULSED_EMB_LATCHED = 2,
LSM6DSR_ALL_INT_LATCHED = 3,
} lsm6dsr_lir_t;
-int32_t lsm6dsr_int_notification_set(stmdev_ctx_t *ctx, lsm6dsr_lir_t val);
-int32_t lsm6dsr_int_notification_get(stmdev_ctx_t *ctx, lsm6dsr_lir_t *val);
+int32_t lsm6dsr_int_notification_set(stmdev_ctx_t *ctx,
+ lsm6dsr_lir_t val);
+int32_t lsm6dsr_int_notification_get(stmdev_ctx_t *ctx,
+ lsm6dsr_lir_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_LSb_FS_DIV_64 = 0,
LSM6DSR_LSb_FS_DIV_256 = 1,
} lsm6dsr_wake_ths_w_t;
@@ -2125,7 +3430,8 @@ int32_t lsm6dsr_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsr_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsr_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_DRIVE_SLEEP_CHG_EVENT = 0,
LSM6DSR_DRIVE_SLEEP_STATUS = 1,
} lsm6dsr_sleep_status_on_int_t;
@@ -2134,7 +3440,8 @@ int32_t lsm6dsr_act_pin_notification_set(stmdev_ctx_t *ctx,
int32_t lsm6dsr_act_pin_notification_get(stmdev_ctx_t *ctx,
lsm6dsr_sleep_status_on_int_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_XL_AND_GY_NOT_AFFECTED = 0,
LSM6DSR_XL_12Hz5_GY_NOT_AFFECTED = 1,
LSM6DSR_XL_12Hz5_GY_SLEEP = 2,
@@ -2148,19 +3455,26 @@ int32_t lsm6dsr_act_mode_get(stmdev_ctx_t *ctx,
int32_t lsm6dsr_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsr_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dsr_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsr_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsr_tap_detection_on_z_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsr_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsr_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsr_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsr_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsr_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsr_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsr_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsr_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsr_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dsr_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsr_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_XYZ = 0,
LSM6DSR_YXZ = 1,
LSM6DSR_XZY = 2,
@@ -2188,7 +3502,8 @@ int32_t lsm6dsr_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsr_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsr_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_ONLY_SINGLE = 0,
LSM6DSR_BOTH_SINGLE_DOUBLE = 1,
} lsm6dsr_single_double_tap_t;
@@ -2197,7 +3512,8 @@ int32_t lsm6dsr_tap_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dsr_tap_mode_get(stmdev_ctx_t *ctx,
lsm6dsr_single_double_tap_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_DEG_80 = 0,
LSM6DSR_DEG_70 = 1,
LSM6DSR_DEG_60 = 2,
@@ -2211,7 +3527,8 @@ int32_t lsm6dsr_6d_threshold_get(stmdev_ctx_t *ctx,
int32_t lsm6dsr_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsr_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_FF_TSH_156mg = 0,
LSM6DSR_FF_TSH_219mg = 1,
LSM6DSR_FF_TSH_250mg = 2,
@@ -2237,7 +3554,8 @@ int32_t lsm6dsr_compression_algo_init_set(stmdev_ctx_t *ctx,
int32_t lsm6dsr_compression_algo_init_get(stmdev_ctx_t *ctx,
uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_CMP_DISABLE = 0x00,
LSM6DSR_CMP_ALWAYS = 0x04,
LSM6DSR_CMP_8_TO_1 = 0x05,
@@ -2262,8 +3580,9 @@ int32_t lsm6dsr_compression_algo_real_time_get(stmdev_ctx_t *ctx,
int32_t lsm6dsr_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsr_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
- LSM6DSR_XL_NOT_BATCHED = 0,
+typedef enum
+{
+ LSM6DSR_XL_NOT_BATCHED = 0,
LSM6DSR_XL_BATCHED_AT_12Hz5 = 1,
LSM6DSR_XL_BATCHED_AT_26Hz = 2,
LSM6DSR_XL_BATCHED_AT_52Hz = 3,
@@ -2276,10 +3595,13 @@ typedef enum {
LSM6DSR_XL_BATCHED_AT_6667Hz = 10,
LSM6DSR_XL_BATCHED_AT_6Hz5 = 11,
} lsm6dsr_bdr_xl_t;
-int32_t lsm6dsr_fifo_xl_batch_set(stmdev_ctx_t *ctx, lsm6dsr_bdr_xl_t val);
-int32_t lsm6dsr_fifo_xl_batch_get(stmdev_ctx_t *ctx, lsm6dsr_bdr_xl_t *val);
+int32_t lsm6dsr_fifo_xl_batch_set(stmdev_ctx_t *ctx,
+ lsm6dsr_bdr_xl_t val);
+int32_t lsm6dsr_fifo_xl_batch_get(stmdev_ctx_t *ctx,
+ lsm6dsr_bdr_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_GY_NOT_BATCHED = 0,
LSM6DSR_GY_BATCHED_AT_12Hz5 = 1,
LSM6DSR_GY_BATCHED_AT_26Hz = 2,
@@ -2293,10 +3615,13 @@ typedef enum {
LSM6DSR_GY_BATCHED_AT_6667Hz = 10,
LSM6DSR_GY_BATCHED_6Hz5 = 11,
} lsm6dsr_bdr_gy_t;
-int32_t lsm6dsr_fifo_gy_batch_set(stmdev_ctx_t *ctx, lsm6dsr_bdr_gy_t val);
-int32_t lsm6dsr_fifo_gy_batch_get(stmdev_ctx_t *ctx, lsm6dsr_bdr_gy_t *val);
+int32_t lsm6dsr_fifo_gy_batch_set(stmdev_ctx_t *ctx,
+ lsm6dsr_bdr_gy_t val);
+int32_t lsm6dsr_fifo_gy_batch_get(stmdev_ctx_t *ctx,
+ lsm6dsr_bdr_gy_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_BYPASS_MODE = 0,
LSM6DSR_FIFO_MODE = 1,
LSM6DSR_STREAM_TO_FIFO_MODE = 3,
@@ -2304,10 +3629,13 @@ typedef enum {
LSM6DSR_STREAM_MODE = 6,
LSM6DSR_BYPASS_TO_FIFO_MODE = 7,
} lsm6dsr_fifo_mode_t;
-int32_t lsm6dsr_fifo_mode_set(stmdev_ctx_t *ctx, lsm6dsr_fifo_mode_t val);
-int32_t lsm6dsr_fifo_mode_get(stmdev_ctx_t *ctx, lsm6dsr_fifo_mode_t *val);
+int32_t lsm6dsr_fifo_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsr_fifo_mode_t val);
+int32_t lsm6dsr_fifo_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsr_fifo_mode_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_TEMP_NOT_BATCHED = 0,
LSM6DSR_TEMP_BATCHED_AT_52Hz = 1,
LSM6DSR_TEMP_BATCHED_AT_12Hz5 = 2,
@@ -2318,7 +3646,8 @@ int32_t lsm6dsr_fifo_temp_batch_set(stmdev_ctx_t *ctx,
int32_t lsm6dsr_fifo_temp_batch_get(stmdev_ctx_t *ctx,
lsm6dsr_odr_t_batch_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_NO_DECIMATION = 0,
LSM6DSR_DEC_1 = 1,
LSM6DSR_DEC_8 = 2,
@@ -2329,7 +3658,8 @@ int32_t lsm6dsr_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
int32_t lsm6dsr_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
lsm6dsr_odr_ts_batch_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_XL_BATCH_EVENT = 0,
LSM6DSR_GYRO_BATCH_EVENT = 1,
} lsm6dsr_trig_counter_bdr_t;
@@ -2339,7 +3669,8 @@ int32_t lsm6dsr_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
lsm6dsr_trig_counter_bdr_t *val);
int32_t lsm6dsr_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsr_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsr_rst_batch_counter_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dsr_batch_counter_threshold_set(stmdev_ctx_t *ctx,
uint16_t val);
@@ -2357,7 +3688,8 @@ int32_t lsm6dsr_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsr_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_GYRO_NC_TAG = 1,
LSM6DSR_XL_NC_TAG,
LSM6DSR_TEMPERATURE_TAG,
@@ -2399,7 +3731,8 @@ int32_t lsm6dsr_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsr_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsr_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_DEN_DISABLE = 0,
LSM6DSR_LEVEL_FIFO = 6,
LSM6DSR_LEVEL_LETCHED = 3,
@@ -2411,7 +3744,8 @@ int32_t lsm6dsr_den_mode_set(stmdev_ctx_t *ctx,
int32_t lsm6dsr_den_mode_get(stmdev_ctx_t *ctx,
lsm6dsr_den_mode_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_DEN_ACT_LOW = 0,
LSM6DSR_DEN_ACT_HIGH = 1,
} lsm6dsr_den_lh_t;
@@ -2420,7 +3754,8 @@ int32_t lsm6dsr_den_polarity_set(stmdev_ctx_t *ctx,
int32_t lsm6dsr_den_polarity_get(stmdev_ctx_t *ctx,
lsm6dsr_den_lh_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_STAMP_IN_GY_DATA = 0,
LSM6DSR_STAMP_IN_XL_DATA = 1,
LSM6DSR_STAMP_IN_GY_XL_DATA = 2,
@@ -2442,31 +3777,41 @@ int32_t lsm6dsr_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsr_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsr_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_PEDO_BASE = 0x00,
LSM6DSR_PEDO_BASE_FALSE_STEP_REJ = 0x01,
LSM6DSR_PEDO_ADV_FALSE_STEP_REJ = 0x03,
} lsm6dsr_pedo_mode_t;
-int32_t lsm6dsr_pedo_mode_set(stmdev_ctx_t *ctx, lsm6dsr_pedo_mode_t val);
-int32_t lsm6dsr_pedo_mode_get(stmdev_ctx_t *ctx, lsm6dsr_pedo_mode_t *val);
+int32_t lsm6dsr_pedo_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsr_pedo_mode_t val);
+int32_t lsm6dsr_pedo_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsr_pedo_mode_t *val);
int32_t lsm6dsr_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dsr_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsr_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsr_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lsm6dsr_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
-int32_t lsm6dsr_pedo_steps_period_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsr_pedo_steps_period_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsr_pedo_steps_period_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t lsm6dsr_pedo_steps_period_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
-int32_t lsm6dsr_pedo_adv_detection_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsr_pedo_adv_detection_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsr_pedo_adv_detection_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsr_pedo_adv_detection_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dsr_pedo_false_step_rejection_set(stmdev_ctx_t *ctx,
uint8_t val);
int32_t lsm6dsr_pedo_false_step_rejection_get(stmdev_ctx_t *ctx,
uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_EVERY_STEP = 0,
LSM6DSR_COUNT_OVERFLOW = 1,
} lsm6dsr_carry_count_en_t;
@@ -2484,18 +3829,20 @@ int32_t lsm6dsr_motion_flag_data_ready_get(stmdev_ctx_t *ctx,
int32_t lsm6dsr_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsr_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dsr_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsr_tilt_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsr_mag_sensitivity_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsr_mag_sensitivity_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsr_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val);
+int32_t lsm6dsr_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val);
-int32_t lsm6dsr_mag_offset_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsr_mag_offset_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsr_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val);
+int32_t lsm6dsr_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val);
-int32_t lsm6dsr_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsr_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsr_mag_soft_iron_set(stmdev_ctx_t *ctx, int16_t *val);
+int32_t lsm6dsr_mag_soft_iron_get(stmdev_ctx_t *ctx, int16_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_Z_EQ_Y = 0,
LSM6DSR_Z_EQ_MIN_Y = 1,
LSM6DSR_Z_EQ_X = 2,
@@ -2508,7 +3855,8 @@ int32_t lsm6dsr_mag_z_orient_set(stmdev_ctx_t *ctx,
int32_t lsm6dsr_mag_z_orient_get(stmdev_ctx_t *ctx,
lsm6dsr_mag_z_axis_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_Y_EQ_Y = 0,
LSM6DSR_Y_EQ_MIN_Y = 1,
LSM6DSR_Y_EQ_X = 2,
@@ -2521,7 +3869,8 @@ int32_t lsm6dsr_mag_y_orient_set(stmdev_ctx_t *ctx,
int32_t lsm6dsr_mag_y_orient_get(stmdev_ctx_t *ctx,
lsm6dsr_mag_y_axis_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_X_EQ_Y = 0,
LSM6DSR_X_EQ_MIN_Y = 1,
LSM6DSR_X_EQ_X = 2,
@@ -2540,19 +3889,21 @@ int32_t lsm6dsr_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
int32_t lsm6dsr_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsr_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef struct {
- lsm6dsr_fsm_enable_a_t fsm_enable_a;
- lsm6dsr_fsm_enable_b_t fsm_enable_b;
+typedef struct
+{
+ lsm6dsr_fsm_enable_a_t fsm_enable_a;
+ lsm6dsr_fsm_enable_b_t fsm_enable_b;
} lsm6dsr_emb_fsm_enable_t;
int32_t lsm6dsr_fsm_enable_set(stmdev_ctx_t *ctx,
lsm6dsr_emb_fsm_enable_t *val);
int32_t lsm6dsr_fsm_enable_get(stmdev_ctx_t *ctx,
lsm6dsr_emb_fsm_enable_t *val);
-int32_t lsm6dsr_long_cnt_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsr_long_cnt_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsr_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val);
+int32_t lsm6dsr_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_LC_NORMAL = 0,
LSM6DSR_LC_CLEAR = 1,
LSM6DSR_LC_CLEAR_DONE = 2,
@@ -2562,27 +3913,30 @@ int32_t lsm6dsr_long_clr_set(stmdev_ctx_t *ctx,
int32_t lsm6dsr_long_clr_get(stmdev_ctx_t *ctx,
lsm6dsr_fsm_lc_clr_t *val);
-typedef struct {
- lsm6dsr_fsm_outs1_t fsm_outs1;
- lsm6dsr_fsm_outs2_t fsm_outs2;
- lsm6dsr_fsm_outs3_t fsm_outs3;
- lsm6dsr_fsm_outs4_t fsm_outs4;
- lsm6dsr_fsm_outs5_t fsm_outs5;
- lsm6dsr_fsm_outs6_t fsm_outs6;
- lsm6dsr_fsm_outs7_t fsm_outs7;
- lsm6dsr_fsm_outs8_t fsm_outs8;
- lsm6dsr_fsm_outs9_t fsm_outs9;
- lsm6dsr_fsm_outs10_t fsm_outs10;
- lsm6dsr_fsm_outs11_t fsm_outs11;
- lsm6dsr_fsm_outs12_t fsm_outs12;
- lsm6dsr_fsm_outs13_t fsm_outs13;
- lsm6dsr_fsm_outs14_t fsm_outs14;
- lsm6dsr_fsm_outs15_t fsm_outs15;
- lsm6dsr_fsm_outs16_t fsm_outs16;
+typedef struct
+{
+ lsm6dsr_fsm_outs1_t fsm_outs1;
+ lsm6dsr_fsm_outs2_t fsm_outs2;
+ lsm6dsr_fsm_outs3_t fsm_outs3;
+ lsm6dsr_fsm_outs4_t fsm_outs4;
+ lsm6dsr_fsm_outs5_t fsm_outs5;
+ lsm6dsr_fsm_outs6_t fsm_outs6;
+ lsm6dsr_fsm_outs7_t fsm_outs7;
+ lsm6dsr_fsm_outs8_t fsm_outs8;
+ lsm6dsr_fsm_outs9_t fsm_outs9;
+ lsm6dsr_fsm_outs10_t fsm_outs10;
+ lsm6dsr_fsm_outs11_t fsm_outs11;
+ lsm6dsr_fsm_outs12_t fsm_outs12;
+ lsm6dsr_fsm_outs13_t fsm_outs13;
+ lsm6dsr_fsm_outs14_t fsm_outs14;
+ lsm6dsr_fsm_outs15_t fsm_outs15;
+ lsm6dsr_fsm_outs16_t fsm_outs16;
} lsm6dsr_fsm_out_t;
-int32_t lsm6dsr_fsm_out_get(stmdev_ctx_t *ctx, lsm6dsr_fsm_out_t *val);
+int32_t lsm6dsr_fsm_out_get(stmdev_ctx_t *ctx,
+ lsm6dsr_fsm_out_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_ODR_FSM_12Hz5 = 0,
LSM6DSR_ODR_FSM_26Hz = 1,
LSM6DSR_ODR_FSM_52Hz = 2,
@@ -2596,41 +3950,47 @@ int32_t lsm6dsr_fsm_data_rate_get(stmdev_ctx_t *ctx,
int32_t lsm6dsr_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsr_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dsr_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsr_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsr_long_cnt_int_value_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t lsm6dsr_long_cnt_int_value_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
int32_t lsm6dsr_fsm_number_of_programs_set(stmdev_ctx_t *ctx,
uint8_t *buff);
int32_t lsm6dsr_fsm_number_of_programs_get(stmdev_ctx_t *ctx,
uint8_t *buff);
-int32_t lsm6dsr_fsm_start_address_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsr_fsm_start_address_get(stmdev_ctx_t *ctx, uint8_t *buff);
-
-typedef struct {
- lsm6dsr_sensor_hub_1_t sh_byte_1;
- lsm6dsr_sensor_hub_2_t sh_byte_2;
- lsm6dsr_sensor_hub_3_t sh_byte_3;
- lsm6dsr_sensor_hub_4_t sh_byte_4;
- lsm6dsr_sensor_hub_5_t sh_byte_5;
- lsm6dsr_sensor_hub_6_t sh_byte_6;
- lsm6dsr_sensor_hub_7_t sh_byte_7;
- lsm6dsr_sensor_hub_8_t sh_byte_8;
- lsm6dsr_sensor_hub_9_t sh_byte_9;
- lsm6dsr_sensor_hub_10_t sh_byte_10;
- lsm6dsr_sensor_hub_11_t sh_byte_11;
- lsm6dsr_sensor_hub_12_t sh_byte_12;
- lsm6dsr_sensor_hub_13_t sh_byte_13;
- lsm6dsr_sensor_hub_14_t sh_byte_14;
- lsm6dsr_sensor_hub_15_t sh_byte_15;
- lsm6dsr_sensor_hub_16_t sh_byte_16;
- lsm6dsr_sensor_hub_17_t sh_byte_17;
- lsm6dsr_sensor_hub_18_t sh_byte_18;
+int32_t lsm6dsr_fsm_start_address_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t lsm6dsr_fsm_start_address_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
+
+typedef struct
+{
+ lsm6dsr_sensor_hub_1_t sh_byte_1;
+ lsm6dsr_sensor_hub_2_t sh_byte_2;
+ lsm6dsr_sensor_hub_3_t sh_byte_3;
+ lsm6dsr_sensor_hub_4_t sh_byte_4;
+ lsm6dsr_sensor_hub_5_t sh_byte_5;
+ lsm6dsr_sensor_hub_6_t sh_byte_6;
+ lsm6dsr_sensor_hub_7_t sh_byte_7;
+ lsm6dsr_sensor_hub_8_t sh_byte_8;
+ lsm6dsr_sensor_hub_9_t sh_byte_9;
+ lsm6dsr_sensor_hub_10_t sh_byte_10;
+ lsm6dsr_sensor_hub_11_t sh_byte_11;
+ lsm6dsr_sensor_hub_12_t sh_byte_12;
+ lsm6dsr_sensor_hub_13_t sh_byte_13;
+ lsm6dsr_sensor_hub_14_t sh_byte_14;
+ lsm6dsr_sensor_hub_15_t sh_byte_15;
+ lsm6dsr_sensor_hub_16_t sh_byte_16;
+ lsm6dsr_sensor_hub_17_t sh_byte_17;
+ lsm6dsr_sensor_hub_18_t sh_byte_18;
} lsm6dsr_emb_sh_read_t;
int32_t lsm6dsr_sh_read_data_raw_get(stmdev_ctx_t *ctx,
lsm6dsr_emb_sh_read_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_SLV_0 = 0,
LSM6DSR_SLV_0_1 = 1,
LSM6DSR_SLV_0_1_2 = 2,
@@ -2644,7 +4004,8 @@ int32_t lsm6dsr_sh_slave_connected_get(stmdev_ctx_t *ctx,
int32_t lsm6dsr_sh_master_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsr_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_EXT_PULL_UP = 0,
LSM6DSR_INTERNAL_PULL_UP = 1,
} lsm6dsr_shub_pu_en_t;
@@ -2656,16 +4017,18 @@ int32_t lsm6dsr_sh_pin_mode_get(stmdev_ctx_t *ctx,
int32_t lsm6dsr_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsr_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
- LSM6DSR_EXT_ON_INT2_PIN = 0,
- LSM6DSR_XL_GY_DRDY = 1,
+typedef enum
+{
+ LSM6DSR_EXT_ON_INT2_PIN = 1,
+ LSM6DSR_XL_GY_DRDY = 0,
} lsm6dsr_start_config_t;
int32_t lsm6dsr_sh_syncro_mode_set(stmdev_ctx_t *ctx,
lsm6dsr_start_config_t val);
int32_t lsm6dsr_sh_syncro_mode_get(stmdev_ctx_t *ctx,
lsm6dsr_start_config_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_EACH_SH_CYCLE = 0,
LSM6DSR_ONLY_FIRST_CYCLE = 1,
} lsm6dsr_write_once_t;
@@ -2677,7 +4040,8 @@ int32_t lsm6dsr_sh_write_mode_get(stmdev_ctx_t *ctx,
int32_t lsm6dsr_sh_reset_set(stmdev_ctx_t *ctx);
int32_t lsm6dsr_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_SH_ODR_104Hz = 0,
LSM6DSR_SH_ODR_52Hz = 1,
LSM6DSR_SH_ODR_26Hz = 2,
@@ -2688,7 +4052,8 @@ int32_t lsm6dsr_sh_data_rate_set(stmdev_ctx_t *ctx,
int32_t lsm6dsr_sh_data_rate_get(stmdev_ctx_t *ctx,
lsm6dsr_shub_odr_t *val);
-typedef struct{
+typedef struct
+{
uint8_t slv0_add;
uint8_t slv0_subadd;
uint8_t slv0_data;
@@ -2696,7 +4061,8 @@ typedef struct{
int32_t lsm6dsr_sh_cfg_write(stmdev_ctx_t *ctx,
lsm6dsr_sh_cfg_write_t *val);
-typedef struct{
+typedef struct
+{
uint8_t slv_add;
uint8_t slv_subadd;
uint8_t slv_len;
@@ -2713,7 +4079,8 @@ int32_t lsm6dsr_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
int32_t lsm6dsr_sh_status_get(stmdev_ctx_t *ctx,
lsm6dsr_status_master_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_S4S_TPH_7bit = 0,
LSM6DSR_S4S_TPH_15bit = 1,
} lsm6dsr_s4s_tph_res_t;
@@ -2725,7 +4092,8 @@ int32_t lsm6dsr_s4s_tph_res_get(stmdev_ctx_t *ctx,
int32_t lsm6dsr_s4s_tph_val_set(stmdev_ctx_t *ctx, uint16_t val);
int32_t lsm6dsr_s4s_tph_val_get(stmdev_ctx_t *ctx, uint16_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSR_S4S_DT_RES_11 = 0,
LSM6DSR_S4S_DT_RES_12 = 1,
LSM6DSR_S4S_DT_RES_13 = 2,
diff --git a/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.c b/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.c
index 24a4c78b8f122f6eea2d946c629b0973594e59dd..f39ec324dcf2daf826a9407c854a5610846659d4 100644
--- a/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.c
+++ b/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file lsm6dsrx_reg.c
- * @author Sensors Software Solution Team
- * @brief LSM6DSRX driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lsm6dsrx_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LSM6DSRX driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lsm6dsrx_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsrx_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t lsm6dsrx_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t lsm6dsrx_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm6dsrx_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t lsm6dsrx_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -166,17 +172,20 @@ float_t lsm6dsrx_from_lsb_to_nsec(int32_t lsb)
*
*/
int32_t lsm6dsrx_xl_full_scale_set(stmdev_ctx_t *ctx,
- lsm6dsrx_fs_xl_t val)
+ lsm6dsrx_fs_xl_t val)
{
lsm6dsrx_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
ctrl1_xl.fs_xl = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
+ (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -189,29 +198,36 @@ int32_t lsm6dsrx_xl_full_scale_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_xl_full_scale_get(stmdev_ctx_t *ctx,
- lsm6dsrx_fs_xl_t *val)
+ lsm6dsrx_fs_xl_t *val)
{
lsm6dsrx_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- switch (ctrl1_xl.fs_xl){
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ switch (ctrl1_xl.fs_xl)
+ {
case LSM6DSRX_2g:
*val = LSM6DSRX_2g;
break;
+
case LSM6DSRX_16g:
*val = LSM6DSRX_16g;
break;
+
case LSM6DSRX_4g:
*val = LSM6DSRX_4g;
break;
+
case LSM6DSRX_8g:
*val = LSM6DSRX_8g;
break;
+
default:
*val = LSM6DSRX_2g;
break;
}
+
return ret;
}
@@ -224,7 +240,7 @@ int32_t lsm6dsrx_xl_full_scale_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_xl_data_rate_set(stmdev_ctx_t *ctx,
- lsm6dsrx_odr_xl_t val)
+ lsm6dsrx_odr_xl_t val)
{
lsm6dsrx_odr_xl_t odr_xl = val;
lsm6dsrx_emb_fsm_enable_t fsm_enable;
@@ -236,81 +252,114 @@ int32_t lsm6dsrx_xl_data_rate_set(stmdev_ctx_t *ctx,
/* Check the Finite State Machine data rate constraints */
ret = lsm6dsrx_fsm_enable_get(ctx, &fsm_enable);
- if (ret == 0) {
- if ( (fsm_enable.fsm_enable_a.fsm1_en |
- fsm_enable.fsm_enable_a.fsm2_en |
- fsm_enable.fsm_enable_a.fsm3_en |
- fsm_enable.fsm_enable_a.fsm4_en |
- fsm_enable.fsm_enable_a.fsm5_en |
- fsm_enable.fsm_enable_a.fsm6_en |
- fsm_enable.fsm_enable_a.fsm7_en |
- fsm_enable.fsm_enable_a.fsm8_en |
- fsm_enable.fsm_enable_b.fsm9_en |
- fsm_enable.fsm_enable_b.fsm10_en |
- fsm_enable.fsm_enable_b.fsm11_en |
- fsm_enable.fsm_enable_b.fsm12_en |
- fsm_enable.fsm_enable_b.fsm13_en |
- fsm_enable.fsm_enable_b.fsm14_en |
- fsm_enable.fsm_enable_b.fsm15_en |
- fsm_enable.fsm_enable_b.fsm16_en ) == PROPERTY_ENABLE ){
+ if (ret == 0)
+ {
+ if ((fsm_enable.fsm_enable_a.fsm1_en |
+ fsm_enable.fsm_enable_a.fsm2_en |
+ fsm_enable.fsm_enable_a.fsm3_en |
+ fsm_enable.fsm_enable_a.fsm4_en |
+ fsm_enable.fsm_enable_a.fsm5_en |
+ fsm_enable.fsm_enable_a.fsm6_en |
+ fsm_enable.fsm_enable_a.fsm7_en |
+ fsm_enable.fsm_enable_a.fsm8_en |
+ fsm_enable.fsm_enable_b.fsm9_en |
+ fsm_enable.fsm_enable_b.fsm10_en |
+ fsm_enable.fsm_enable_b.fsm11_en |
+ fsm_enable.fsm_enable_b.fsm12_en |
+ fsm_enable.fsm_enable_b.fsm13_en |
+ fsm_enable.fsm_enable_b.fsm14_en |
+ fsm_enable.fsm_enable_b.fsm15_en |
+ fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
+ {
ret = lsm6dsrx_fsm_data_rate_get(ctx, &fsm_odr);
- if (ret == 0) {
- switch (fsm_odr) {
- case LSM6DSRX_ODR_FSM_12Hz5:
- if (val == LSM6DSRX_XL_ODR_OFF){
+ if (ret == 0)
+ {
+ switch (fsm_odr)
+ {
+ case LSM6DSRX_ODR_FSM_12Hz5:
+ if (val == LSM6DSRX_XL_ODR_OFF)
+ {
odr_xl = LSM6DSRX_XL_ODR_12Hz5;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
- case LSM6DSRX_ODR_FSM_26Hz:
- if (val == LSM6DSRX_XL_ODR_OFF){
+ case LSM6DSRX_ODR_FSM_26Hz:
+ if (val == LSM6DSRX_XL_ODR_OFF)
+ {
odr_xl = LSM6DSRX_XL_ODR_26Hz;
+ }
- } else if (val == LSM6DSRX_XL_ODR_12Hz5){
+ else if (val == LSM6DSRX_XL_ODR_12Hz5)
+ {
odr_xl = LSM6DSRX_XL_ODR_26Hz;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
- case LSM6DSRX_ODR_FSM_52Hz:
- if (val == LSM6DSRX_XL_ODR_OFF){
+ case LSM6DSRX_ODR_FSM_52Hz:
+ if (val == LSM6DSRX_XL_ODR_OFF)
+ {
odr_xl = LSM6DSRX_XL_ODR_52Hz;
+ }
- } else if (val == LSM6DSRX_XL_ODR_12Hz5){
+ else if (val == LSM6DSRX_XL_ODR_12Hz5)
+ {
odr_xl = LSM6DSRX_XL_ODR_52Hz;
+ }
- } else if (val == LSM6DSRX_XL_ODR_26Hz){
+ else if (val == LSM6DSRX_XL_ODR_26Hz)
+ {
odr_xl = LSM6DSRX_XL_ODR_52Hz;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
- case LSM6DSRX_ODR_FSM_104Hz:
- if (val == LSM6DSRX_XL_ODR_OFF){
+ case LSM6DSRX_ODR_FSM_104Hz:
+ if (val == LSM6DSRX_XL_ODR_OFF)
+ {
odr_xl = LSM6DSRX_XL_ODR_104Hz;
+ }
- } else if (val == LSM6DSRX_XL_ODR_12Hz5){
+ else if (val == LSM6DSRX_XL_ODR_12Hz5)
+ {
odr_xl = LSM6DSRX_XL_ODR_104Hz;
+ }
- } else if (val == LSM6DSRX_XL_ODR_26Hz){
+ else if (val == LSM6DSRX_XL_ODR_26Hz)
+ {
odr_xl = LSM6DSRX_XL_ODR_104Hz;
+ }
- } else if (val == LSM6DSRX_XL_ODR_52Hz){
+ else if (val == LSM6DSRX_XL_ODR_52Hz)
+ {
odr_xl = LSM6DSRX_XL_ODR_104Hz;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
+
default:
odr_xl = val;
break;
@@ -321,65 +370,101 @@ int32_t lsm6dsrx_xl_data_rate_set(stmdev_ctx_t *ctx,
/* Check the Machine Learning Core data rate constraints */
mlc_enable = PROPERTY_DISABLE;
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mlc_get(ctx, &mlc_enable);
- if ( mlc_enable == PROPERTY_ENABLE ){
+ if (mlc_enable == PROPERTY_ENABLE)
+ {
ret = lsm6dsrx_mlc_data_rate_get(ctx, &mlc_odr);
- if (ret == 0) {
- switch (mlc_odr) {
- case LSM6DSRX_ODR_PRGS_12Hz5:
- if (val == LSM6DSRX_XL_ODR_OFF){
+ if (ret == 0)
+ {
+ switch (mlc_odr)
+ {
+ case LSM6DSRX_ODR_PRGS_12Hz5:
+ if (val == LSM6DSRX_XL_ODR_OFF)
+ {
odr_xl = LSM6DSRX_XL_ODR_12Hz5;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
+
case LSM6DSRX_ODR_PRGS_26Hz:
- if (val == LSM6DSRX_XL_ODR_OFF){
+ if (val == LSM6DSRX_XL_ODR_OFF)
+ {
odr_xl = LSM6DSRX_XL_ODR_26Hz;
+ }
- } else if (val == LSM6DSRX_XL_ODR_12Hz5){
+ else if (val == LSM6DSRX_XL_ODR_12Hz5)
+ {
odr_xl = LSM6DSRX_XL_ODR_26Hz;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
- case LSM6DSRX_ODR_PRGS_52Hz:
- if (val == LSM6DSRX_XL_ODR_OFF){
+ case LSM6DSRX_ODR_PRGS_52Hz:
+ if (val == LSM6DSRX_XL_ODR_OFF)
+ {
odr_xl = LSM6DSRX_XL_ODR_52Hz;
+ }
- } else if (val == LSM6DSRX_XL_ODR_12Hz5){
+ else if (val == LSM6DSRX_XL_ODR_12Hz5)
+ {
odr_xl = LSM6DSRX_XL_ODR_52Hz;
+ }
- } else if (val == LSM6DSRX_XL_ODR_26Hz){
+ else if (val == LSM6DSRX_XL_ODR_26Hz)
+ {
odr_xl = LSM6DSRX_XL_ODR_52Hz;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
+
case LSM6DSRX_ODR_PRGS_104Hz:
- if (val == LSM6DSRX_XL_ODR_OFF){
+ if (val == LSM6DSRX_XL_ODR_OFF)
+ {
odr_xl = LSM6DSRX_XL_ODR_104Hz;
+ }
- } else if (val == LSM6DSRX_XL_ODR_12Hz5){
+ else if (val == LSM6DSRX_XL_ODR_12Hz5)
+ {
odr_xl = LSM6DSRX_XL_ODR_104Hz;
+ }
- } else if (val == LSM6DSRX_XL_ODR_26Hz){
+ else if (val == LSM6DSRX_XL_ODR_26Hz)
+ {
odr_xl = LSM6DSRX_XL_ODR_104Hz;
+ }
- } else if (val == LSM6DSRX_XL_ODR_52Hz){
+ else if (val == LSM6DSRX_XL_ODR_52Hz)
+ {
odr_xl = LSM6DSRX_XL_ODR_104Hz;
+ }
- } else {
+ else
+ {
odr_xl = val;
}
+
break;
+
default:
odr_xl = val;
break;
@@ -388,14 +473,18 @@ int32_t lsm6dsrx_xl_data_rate_set(stmdev_ctx_t *ctx,
}
}
- if(ret == 0){
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
}
- if(ret == 0){
- ctrl1_xl.odr_xl= (uint8_t)odr_xl;
+
+ if (ret == 0)
+ {
+ ctrl1_xl.odr_xl = (uint8_t)odr_xl;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
+ (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -408,53 +497,68 @@ int32_t lsm6dsrx_xl_data_rate_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_xl_data_rate_get(stmdev_ctx_t *ctx,
- lsm6dsrx_odr_xl_t *val)
+ lsm6dsrx_odr_xl_t *val)
{
lsm6dsrx_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- switch (ctrl1_xl.odr_xl){
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ switch (ctrl1_xl.odr_xl)
+ {
case LSM6DSRX_XL_ODR_OFF:
*val = LSM6DSRX_XL_ODR_OFF;
break;
+
case LSM6DSRX_XL_ODR_12Hz5:
*val = LSM6DSRX_XL_ODR_12Hz5;
break;
+
case LSM6DSRX_XL_ODR_26Hz:
*val = LSM6DSRX_XL_ODR_26Hz;
break;
+
case LSM6DSRX_XL_ODR_52Hz:
*val = LSM6DSRX_XL_ODR_52Hz;
break;
+
case LSM6DSRX_XL_ODR_104Hz:
*val = LSM6DSRX_XL_ODR_104Hz;
break;
+
case LSM6DSRX_XL_ODR_208Hz:
*val = LSM6DSRX_XL_ODR_208Hz;
break;
+
case LSM6DSRX_XL_ODR_417Hz:
*val = LSM6DSRX_XL_ODR_417Hz;
break;
+
case LSM6DSRX_XL_ODR_833Hz:
*val = LSM6DSRX_XL_ODR_833Hz;
break;
+
case LSM6DSRX_XL_ODR_1667Hz:
*val = LSM6DSRX_XL_ODR_1667Hz;
break;
+
case LSM6DSRX_XL_ODR_3333Hz:
*val = LSM6DSRX_XL_ODR_3333Hz;
break;
+
case LSM6DSRX_XL_ODR_6667Hz:
*val = LSM6DSRX_XL_ODR_6667Hz;
break;
+
case LSM6DSRX_XL_ODR_6Hz5:
*val = LSM6DSRX_XL_ODR_6Hz5;
break;
+
default:
*val = LSM6DSRX_XL_ODR_OFF;
break;
}
+
return ret;
}
@@ -467,16 +571,19 @@ int32_t lsm6dsrx_xl_data_rate_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_gy_full_scale_set(stmdev_ctx_t *ctx,
- lsm6dsrx_fs_g_t val)
+ lsm6dsrx_fs_g_t val)
{
lsm6dsrx_ctrl2_g_t ctrl2_g;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- if(ret == 0){
- ctrl2_g.fs_g= (uint8_t)val;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
+
+ if (ret == 0)
+ {
+ ctrl2_g.fs_g = (uint8_t)val;
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
}
+
return ret;
}
@@ -489,35 +596,44 @@ int32_t lsm6dsrx_gy_full_scale_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_gy_full_scale_get(stmdev_ctx_t *ctx,
- lsm6dsrx_fs_g_t *val)
+ lsm6dsrx_fs_g_t *val)
{
lsm6dsrx_ctrl2_g_t ctrl2_g;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- switch (ctrl2_g.fs_g){
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
+
+ switch (ctrl2_g.fs_g)
+ {
case LSM6DSRX_125dps:
*val = LSM6DSRX_125dps;
break;
+
case LSM6DSRX_250dps:
*val = LSM6DSRX_250dps;
break;
+
case LSM6DSRX_500dps:
*val = LSM6DSRX_500dps;
break;
+
case LSM6DSRX_1000dps:
*val = LSM6DSRX_1000dps;
break;
+
case LSM6DSRX_2000dps:
*val = LSM6DSRX_2000dps;
break;
+
case LSM6DSRX_4000dps:
*val = LSM6DSRX_4000dps;
break;
+
default:
*val = LSM6DSRX_125dps;
break;
}
+
return ret;
}
@@ -530,7 +646,7 @@ int32_t lsm6dsrx_gy_full_scale_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_gy_data_rate_set(stmdev_ctx_t *ctx,
- lsm6dsrx_odr_g_t val)
+ lsm6dsrx_odr_g_t val)
{
lsm6dsrx_odr_g_t odr_gy = val;
lsm6dsrx_emb_fsm_enable_t fsm_enable;
@@ -542,81 +658,114 @@ int32_t lsm6dsrx_gy_data_rate_set(stmdev_ctx_t *ctx,
/* Check the Finite State Machine data rate constraints */
ret = lsm6dsrx_fsm_enable_get(ctx, &fsm_enable);
- if (ret == 0) {
- if ( (fsm_enable.fsm_enable_a.fsm1_en |
- fsm_enable.fsm_enable_a.fsm2_en |
- fsm_enable.fsm_enable_a.fsm3_en |
- fsm_enable.fsm_enable_a.fsm4_en |
- fsm_enable.fsm_enable_a.fsm5_en |
- fsm_enable.fsm_enable_a.fsm6_en |
- fsm_enable.fsm_enable_a.fsm7_en |
- fsm_enable.fsm_enable_a.fsm8_en |
- fsm_enable.fsm_enable_b.fsm9_en |
- fsm_enable.fsm_enable_b.fsm10_en |
- fsm_enable.fsm_enable_b.fsm11_en |
- fsm_enable.fsm_enable_b.fsm12_en |
- fsm_enable.fsm_enable_b.fsm13_en |
- fsm_enable.fsm_enable_b.fsm14_en |
- fsm_enable.fsm_enable_b.fsm15_en |
- fsm_enable.fsm_enable_b.fsm16_en ) == PROPERTY_ENABLE ){
+ if (ret == 0)
+ {
+ if ((fsm_enable.fsm_enable_a.fsm1_en |
+ fsm_enable.fsm_enable_a.fsm2_en |
+ fsm_enable.fsm_enable_a.fsm3_en |
+ fsm_enable.fsm_enable_a.fsm4_en |
+ fsm_enable.fsm_enable_a.fsm5_en |
+ fsm_enable.fsm_enable_a.fsm6_en |
+ fsm_enable.fsm_enable_a.fsm7_en |
+ fsm_enable.fsm_enable_a.fsm8_en |
+ fsm_enable.fsm_enable_b.fsm9_en |
+ fsm_enable.fsm_enable_b.fsm10_en |
+ fsm_enable.fsm_enable_b.fsm11_en |
+ fsm_enable.fsm_enable_b.fsm12_en |
+ fsm_enable.fsm_enable_b.fsm13_en |
+ fsm_enable.fsm_enable_b.fsm14_en |
+ fsm_enable.fsm_enable_b.fsm15_en |
+ fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
+ {
ret = lsm6dsrx_fsm_data_rate_get(ctx, &fsm_odr);
- if (ret == 0) {
- switch (fsm_odr) {
- case LSM6DSRX_ODR_FSM_12Hz5:
- if (val == LSM6DSRX_GY_ODR_OFF){
+ if (ret == 0)
+ {
+ switch (fsm_odr)
+ {
+ case LSM6DSRX_ODR_FSM_12Hz5:
+ if (val == LSM6DSRX_GY_ODR_OFF)
+ {
odr_gy = LSM6DSRX_GY_ODR_12Hz5;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
- case LSM6DSRX_ODR_FSM_26Hz:
- if (val == LSM6DSRX_GY_ODR_OFF){
+ case LSM6DSRX_ODR_FSM_26Hz:
+ if (val == LSM6DSRX_GY_ODR_OFF)
+ {
odr_gy = LSM6DSRX_GY_ODR_26Hz;
+ }
- } else if (val == LSM6DSRX_GY_ODR_12Hz5){
+ else if (val == LSM6DSRX_GY_ODR_12Hz5)
+ {
odr_gy = LSM6DSRX_GY_ODR_26Hz;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
- case LSM6DSRX_ODR_FSM_52Hz:
- if (val == LSM6DSRX_GY_ODR_OFF){
+ case LSM6DSRX_ODR_FSM_52Hz:
+ if (val == LSM6DSRX_GY_ODR_OFF)
+ {
odr_gy = LSM6DSRX_GY_ODR_52Hz;
+ }
- } else if (val == LSM6DSRX_GY_ODR_12Hz5){
+ else if (val == LSM6DSRX_GY_ODR_12Hz5)
+ {
odr_gy = LSM6DSRX_GY_ODR_52Hz;
+ }
- } else if (val == LSM6DSRX_GY_ODR_26Hz){
+ else if (val == LSM6DSRX_GY_ODR_26Hz)
+ {
odr_gy = LSM6DSRX_GY_ODR_52Hz;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
- case LSM6DSRX_ODR_FSM_104Hz:
- if (val == LSM6DSRX_GY_ODR_OFF){
+ case LSM6DSRX_ODR_FSM_104Hz:
+ if (val == LSM6DSRX_GY_ODR_OFF)
+ {
odr_gy = LSM6DSRX_GY_ODR_104Hz;
+ }
- } else if (val == LSM6DSRX_GY_ODR_12Hz5){
+ else if (val == LSM6DSRX_GY_ODR_12Hz5)
+ {
odr_gy = LSM6DSRX_GY_ODR_104Hz;
+ }
- } else if (val == LSM6DSRX_GY_ODR_26Hz){
+ else if (val == LSM6DSRX_GY_ODR_26Hz)
+ {
odr_gy = LSM6DSRX_GY_ODR_104Hz;
+ }
- } else if (val == LSM6DSRX_GY_ODR_52Hz){
+ else if (val == LSM6DSRX_GY_ODR_52Hz)
+ {
odr_gy = LSM6DSRX_GY_ODR_104Hz;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
+
default:
odr_gy = val;
break;
@@ -627,67 +776,101 @@ int32_t lsm6dsrx_gy_data_rate_set(stmdev_ctx_t *ctx,
/* Check the Machine Learning Core data rate constraints */
mlc_enable = PROPERTY_DISABLE;
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mlc_get(ctx, &mlc_enable);
- if ( mlc_enable == PROPERTY_ENABLE ){
+ if (mlc_enable == PROPERTY_ENABLE)
+ {
ret = lsm6dsrx_mlc_data_rate_get(ctx, &mlc_odr);
- if (ret == 0) {
- switch (mlc_odr) {
- case LSM6DSRX_ODR_PRGS_12Hz5:
- if (val == LSM6DSRX_GY_ODR_OFF){
+ if (ret == 0)
+ {
+ switch (mlc_odr)
+ {
+ case LSM6DSRX_ODR_PRGS_12Hz5:
+ if (val == LSM6DSRX_GY_ODR_OFF)
+ {
odr_gy = LSM6DSRX_GY_ODR_12Hz5;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
- case LSM6DSRX_ODR_PRGS_26Hz:
- if (val == LSM6DSRX_GY_ODR_OFF){
+ case LSM6DSRX_ODR_PRGS_26Hz:
+ if (val == LSM6DSRX_GY_ODR_OFF)
+ {
odr_gy = LSM6DSRX_GY_ODR_26Hz;
+ }
- } else if (val == LSM6DSRX_GY_ODR_12Hz5){
+ else if (val == LSM6DSRX_GY_ODR_12Hz5)
+ {
odr_gy = LSM6DSRX_GY_ODR_26Hz;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
- case LSM6DSRX_ODR_PRGS_52Hz:
- if (val == LSM6DSRX_GY_ODR_OFF){
+ case LSM6DSRX_ODR_PRGS_52Hz:
+ if (val == LSM6DSRX_GY_ODR_OFF)
+ {
odr_gy = LSM6DSRX_GY_ODR_52Hz;
+ }
- } else if (val == LSM6DSRX_GY_ODR_12Hz5){
+ else if (val == LSM6DSRX_GY_ODR_12Hz5)
+ {
odr_gy = LSM6DSRX_GY_ODR_52Hz;
+ }
- } else if (val == LSM6DSRX_GY_ODR_26Hz){
+ else if (val == LSM6DSRX_GY_ODR_26Hz)
+ {
odr_gy = LSM6DSRX_GY_ODR_52Hz;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
- case LSM6DSRX_ODR_PRGS_104Hz:
- if (val == LSM6DSRX_GY_ODR_OFF){
+ case LSM6DSRX_ODR_PRGS_104Hz:
+ if (val == LSM6DSRX_GY_ODR_OFF)
+ {
odr_gy = LSM6DSRX_GY_ODR_104Hz;
+ }
- } else if (val == LSM6DSRX_GY_ODR_12Hz5){
+ else if (val == LSM6DSRX_GY_ODR_12Hz5)
+ {
odr_gy = LSM6DSRX_GY_ODR_104Hz;
+ }
- } else if (val == LSM6DSRX_GY_ODR_26Hz){
+ else if (val == LSM6DSRX_GY_ODR_26Hz)
+ {
odr_gy = LSM6DSRX_GY_ODR_104Hz;
+ }
- } else if (val == LSM6DSRX_GY_ODR_52Hz){
+ else if (val == LSM6DSRX_GY_ODR_52Hz)
+ {
odr_gy = LSM6DSRX_GY_ODR_104Hz;
+ }
- } else {
+ else
+ {
odr_gy = val;
}
+
break;
+
default:
odr_gy = val;
break;
@@ -696,13 +879,17 @@ int32_t lsm6dsrx_gy_data_rate_set(stmdev_ctx_t *ctx,
}
}
- if(ret == 0){
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
}
- if(ret == 0){
- ctrl2_g.odr_g= (uint8_t)odr_gy;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
+
+ if (ret == 0)
+ {
+ ctrl2_g.odr_g = (uint8_t)odr_gy;
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
}
+
return ret;
}
@@ -715,50 +902,64 @@ int32_t lsm6dsrx_gy_data_rate_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_gy_data_rate_get(stmdev_ctx_t *ctx,
- lsm6dsrx_odr_g_t *val)
+ lsm6dsrx_odr_g_t *val)
{
lsm6dsrx_ctrl2_g_t ctrl2_g;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_G, (uint8_t*)&ctrl2_g, 1);
- switch (ctrl2_g.odr_g){
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
+
+ switch (ctrl2_g.odr_g)
+ {
case LSM6DSRX_GY_ODR_OFF:
*val = LSM6DSRX_GY_ODR_OFF;
break;
+
case LSM6DSRX_GY_ODR_12Hz5:
*val = LSM6DSRX_GY_ODR_12Hz5;
break;
+
case LSM6DSRX_GY_ODR_26Hz:
*val = LSM6DSRX_GY_ODR_26Hz;
break;
+
case LSM6DSRX_GY_ODR_52Hz:
*val = LSM6DSRX_GY_ODR_52Hz;
break;
+
case LSM6DSRX_GY_ODR_104Hz:
*val = LSM6DSRX_GY_ODR_104Hz;
break;
+
case LSM6DSRX_GY_ODR_208Hz:
*val = LSM6DSRX_GY_ODR_208Hz;
break;
+
case LSM6DSRX_GY_ODR_417Hz:
*val = LSM6DSRX_GY_ODR_417Hz;
break;
+
case LSM6DSRX_GY_ODR_833Hz:
*val = LSM6DSRX_GY_ODR_833Hz;
break;
+
case LSM6DSRX_GY_ODR_1667Hz:
*val = LSM6DSRX_GY_ODR_1667Hz;
break;
+
case LSM6DSRX_GY_ODR_3333Hz:
*val = LSM6DSRX_GY_ODR_3333Hz;
break;
+
case LSM6DSRX_GY_ODR_6667Hz:
*val = LSM6DSRX_GY_ODR_6667Hz;
break;
+
default:
*val = LSM6DSRX_GY_ODR_OFF;
break;
}
+
return ret;
}
@@ -775,11 +976,14 @@ int32_t lsm6dsrx_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsrx_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.bdu= (uint8_t)val;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.bdu = (uint8_t)val;
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -791,12 +995,13 @@ int32_t lsm6dsrx_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsrx_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsrx_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.bdu;
return ret;
@@ -812,16 +1017,19 @@ int32_t lsm6dsrx_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsrx_xl_offset_weight_set(stmdev_ctx_t *ctx,
- lsm6dsrx_usr_off_w_t val)
+ lsm6dsrx_usr_off_w_t val)
{
lsm6dsrx_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
- ctrl6_c.usr_off_w= (uint8_t)val;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl6_c.usr_off_w = (uint8_t)val;
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -835,24 +1043,28 @@ int32_t lsm6dsrx_xl_offset_weight_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_xl_offset_weight_get(stmdev_ctx_t *ctx,
- lsm6dsrx_usr_off_w_t *val)
+ lsm6dsrx_usr_off_w_t *val)
{
lsm6dsrx_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
- switch (ctrl6_c.usr_off_w){
+ switch (ctrl6_c.usr_off_w)
+ {
case LSM6DSRX_LSb_1mg:
*val = LSM6DSRX_LSb_1mg;
break;
+
case LSM6DSRX_LSb_16mg:
*val = LSM6DSRX_LSb_16mg;
break;
+
default:
*val = LSM6DSRX_LSb_1mg;
break;
}
+
return ret;
}
@@ -865,16 +1077,19 @@ int32_t lsm6dsrx_xl_offset_weight_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_xl_power_mode_set(stmdev_ctx_t *ctx,
- lsm6dsrx_xl_hm_mode_t val)
+ lsm6dsrx_xl_hm_mode_t val)
{
lsm6dsrx_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -887,23 +1102,28 @@ int32_t lsm6dsrx_xl_power_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_xl_power_mode_get(stmdev_ctx_t *ctx,
- lsm6dsrx_xl_hm_mode_t *val)
+ lsm6dsrx_xl_hm_mode_t *val)
{
lsm6dsrx_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- switch (ctrl6_c.xl_hm_mode){
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ switch (ctrl6_c.xl_hm_mode)
+ {
case LSM6DSRX_HIGH_PERFORMANCE_MD:
*val = LSM6DSRX_HIGH_PERFORMANCE_MD;
break;
+
case LSM6DSRX_LOW_NORMAL_POWER_MD:
*val = LSM6DSRX_LOW_NORMAL_POWER_MD;
break;
+
default:
*val = LSM6DSRX_HIGH_PERFORMANCE_MD;
break;
}
+
return ret;
}
@@ -916,16 +1136,19 @@ int32_t lsm6dsrx_xl_power_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_gy_power_mode_set(stmdev_ctx_t *ctx,
- lsm6dsrx_g_hm_mode_t val)
+ lsm6dsrx_g_hm_mode_t val)
{
lsm6dsrx_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
- ctrl7_g.g_hm_mode= (uint8_t)val;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
+ ctrl7_g.g_hm_mode = (uint8_t)val;
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
}
+
return ret;
}
@@ -938,23 +1161,28 @@ int32_t lsm6dsrx_gy_power_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_gy_power_mode_get(stmdev_ctx_t *ctx,
- lsm6dsrx_g_hm_mode_t *val)
+ lsm6dsrx_g_hm_mode_t *val)
{
lsm6dsrx_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- switch (ctrl7_g.g_hm_mode){
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ switch (ctrl7_g.g_hm_mode)
+ {
case LSM6DSRX_GY_HIGH_PERFORMANCE:
*val = LSM6DSRX_GY_HIGH_PERFORMANCE;
break;
+
case LSM6DSRX_GY_NORMAL:
*val = LSM6DSRX_GY_NORMAL;
break;
+
default:
*val = LSM6DSRX_GY_HIGH_PERFORMANCE;
break;
}
+
return ret;
}
@@ -969,48 +1197,68 @@ int32_t lsm6dsrx_gy_power_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_all_sources_get(stmdev_ctx_t *ctx,
- lsm6dsrx_all_sources_t *val)
+ lsm6dsrx_all_sources_t *val)
{
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_ALL_INT_SRC,
- (uint8_t*)&val->all_int_src, 1);
- if(ret == 0){
+ (uint8_t *)&val->all_int_src, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_SRC,
- (uint8_t*)&val->wake_up_src, 1);
+ (uint8_t *)&val->wake_up_src, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_SRC,
- (uint8_t*)&val->tap_src, 1);
+ (uint8_t *)&val->tap_src, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_D6D_SRC,
- (uint8_t*)&val->d6d_src, 1);
+ (uint8_t *)&val->d6d_src, 1);
}
- if(ret == 0){
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_REG,
- (uint8_t*)&val->status_reg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_REG,
+ (uint8_t *)&val->status_reg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_STATUS,
- (uint8_t*)&val->emb_func_status, 1);
+ (uint8_t *)&val->emb_func_status, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_STATUS_A,
- (uint8_t*)&val->fsm_status_a, 1);
+ (uint8_t *)&val->fsm_status_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_STATUS_B,
- (uint8_t*)&val->fsm_status_b, 1);
+ (uint8_t *)&val->fsm_status_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MLC_STATUS,
- (uint8_t*)&val->mlc_status, 1);
+ (uint8_t *)&val->mlc_status, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
@@ -1026,10 +1274,12 @@ int32_t lsm6dsrx_all_sources_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_status_reg_get(stmdev_ctx_t *ctx,
- lsm6dsrx_status_reg_t *val)
+ lsm6dsrx_status_reg_t *val)
{
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_REG, (uint8_t*) val, 1);
+
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_REG, (uint8_t *) val, 1);
+
return ret;
}
@@ -1041,13 +1291,14 @@ int32_t lsm6dsrx_status_reg_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsrx_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsrx_status_reg_t status_reg;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_REG,
- (uint8_t*)&status_reg, 1);
+ (uint8_t *)&status_reg, 1);
*val = status_reg.xlda;
return ret;
@@ -1061,13 +1312,14 @@ int32_t lsm6dsrx_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsrx_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsrx_status_reg_t status_reg;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_REG,
- (uint8_t*)&status_reg, 1);
+ (uint8_t *)&status_reg, 1);
*val = status_reg.gda;
return ret;
@@ -1081,13 +1333,14 @@ int32_t lsm6dsrx_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsrx_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsrx_status_reg_t status_reg;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_REG,
- (uint8_t*)&status_reg, 1);
+ (uint8_t *)&status_reg, 1);
*val = status_reg.tda;
return ret;
@@ -1106,7 +1359,9 @@ int32_t lsm6dsrx_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t lsm6dsrx_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_X_OFS_USR, buff, 1);
+
return ret;
}
@@ -1123,7 +1378,9 @@ int32_t lsm6dsrx_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lsm6dsrx_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_X_OFS_USR, buff, 1);
+
return ret;
}
@@ -1140,7 +1397,9 @@ int32_t lsm6dsrx_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lsm6dsrx_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_Y_OFS_USR, buff, 1);
+
return ret;
}
@@ -1157,7 +1416,9 @@ int32_t lsm6dsrx_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lsm6dsrx_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_Y_OFS_USR, buff, 1);
+
return ret;
}
@@ -1174,7 +1435,9 @@ int32_t lsm6dsrx_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lsm6dsrx_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_Z_OFS_USR, buff, 1);
+
return ret;
}
@@ -1191,7 +1454,9 @@ int32_t lsm6dsrx_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lsm6dsrx_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_Z_OFS_USR, buff, 1);
+
return ret;
}
@@ -1208,11 +1473,14 @@ int32_t lsm6dsrx_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsrx_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
- ctrl7_g.usr_off_on_out= (uint8_t)val;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
+ ctrl7_g.usr_off_on_out = (uint8_t)val;
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
}
+
return ret;
}
@@ -1229,7 +1497,7 @@ int32_t lsm6dsrx_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsrx_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
*val = ctrl7_g.usr_off_on_out;
return ret;
@@ -1258,7 +1526,6 @@ int32_t lsm6dsrx_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t lsm6dsrx_timestamp_rst(stmdev_ctx_t *ctx)
{
uint8_t rst_val = 0xAA;
-
return lsm6dsrx_write_reg(ctx, LSM6DSRX_TIMESTAMP2, &rst_val, 1);
}
@@ -1275,12 +1542,15 @@ int32_t lsm6dsrx_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsrx_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
- if(ret == 0){
- ctrl10_c.timestamp_en= (uint8_t)val;
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl10_c.timestamp_en = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL10_C,
- (uint8_t*)&ctrl10_c, 1);
+ (uint8_t *)&ctrl10_c, 1);
}
+
return ret;
}
@@ -1297,7 +1567,7 @@ int32_t lsm6dsrx_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsrx_ctrl10_c_t ctrl10_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL10_C, (uint8_t*)&ctrl10_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
*val = ctrl10_c.timestamp_en;
return ret;
@@ -1348,16 +1618,19 @@ int32_t lsm6dsrx_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val)
*
*/
int32_t lsm6dsrx_rounding_mode_set(stmdev_ctx_t *ctx,
- lsm6dsrx_rounding_t val)
+ lsm6dsrx_rounding_t val)
{
lsm6dsrx_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
- ctrl5_c.rounding= (uint8_t)val;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl5_c.rounding = (uint8_t)val;
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -1370,29 +1643,36 @@ int32_t lsm6dsrx_rounding_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_rounding_mode_get(stmdev_ctx_t *ctx,
- lsm6dsrx_rounding_t *val)
+ lsm6dsrx_rounding_t *val)
{
lsm6dsrx_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- switch (ctrl5_c.rounding){
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ switch (ctrl5_c.rounding)
+ {
case LSM6DSRX_NO_ROUND:
*val = LSM6DSRX_NO_ROUND;
break;
+
case LSM6DSRX_ROUND_XL:
*val = LSM6DSRX_ROUND_XL;
break;
+
case LSM6DSRX_ROUND_GY:
*val = LSM6DSRX_ROUND_GY;
break;
+
case LSM6DSRX_ROUND_GY_XL:
*val = LSM6DSRX_ROUND_GY_XL;
break;
+
default:
*val = LSM6DSRX_NO_ROUND;
break;
}
+
return ret;
}
@@ -1431,8 +1711,8 @@ int32_t lsm6dsrx_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
uint8_t buff[6];
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_OUTX_L_G, buff, 6);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_OUTX_L_G, buff, 6);
val[0] = (int16_t)buff[1];
val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
@@ -1456,8 +1736,8 @@ int32_t lsm6dsrx_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
uint8_t buff[6];
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_OUTX_L_A, buff, 6);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_OUTX_L_A, buff, 6);
val[0] = (int16_t)buff[1];
val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
@@ -1479,7 +1759,9 @@ int32_t lsm6dsrx_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
int32_t lsm6dsrx_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *val)
{
int32_t ret;
+
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_DATA_OUT_X_L, val, 6);
+
return ret;
}
@@ -1497,10 +1779,16 @@ int32_t lsm6dsrx_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val)
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STEP_COUNTER_L, buff, 2);
+ *val = buff[1];
+ *val = (*val * 256U) + buff[0];
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
@@ -1520,18 +1808,25 @@ int32_t lsm6dsrx_steps_reset(stmdev_ctx_t *ctx)
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_SRC,
- (uint8_t*)&emb_func_src, 1);
+ (uint8_t *)&emb_func_src, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
emb_func_src.pedo_rst_step = PROPERTY_ENABLE;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_SRC,
- (uint8_t*)&emb_func_src, 1);
+ (uint8_t *)&emb_func_src, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -1542,7 +1837,7 @@ int32_t lsm6dsrx_steps_reset(stmdev_ctx_t *ctx)
/**
* @defgroup LSM6DSRX_common
- * @brief This section groups common usefull functions.
+ * @brief This section groups common useful functions.
* @{
*
*/
@@ -1563,12 +1858,15 @@ int32_t lsm6dsrx_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INTERNAL_FREQ_FINE,
- (uint8_t*)&internal_freq_fine, 1);
- if(ret == 0){
- internal_freq_fine.freq_fine= (uint8_t)val;
+ (uint8_t *)&internal_freq_fine, 1);
+
+ if (ret == 0)
+ {
+ internal_freq_fine.freq_fine = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INTERNAL_FREQ_FINE,
- (uint8_t*)&internal_freq_fine, 1);
+ (uint8_t *)&internal_freq_fine, 1);
}
+
return ret;
}
@@ -1588,7 +1886,7 @@ int32_t lsm6dsrx_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INTERNAL_FREQ_FINE,
- (uint8_t*)&internal_freq_fine, 1);
+ (uint8_t *)&internal_freq_fine, 1);
*val = internal_freq_fine.freq_fine;
return ret;
@@ -1604,18 +1902,21 @@ int32_t lsm6dsrx_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsrx_mem_bank_set(stmdev_ctx_t *ctx,
- lsm6dsrx_reg_access_t val)
+ lsm6dsrx_reg_access_t val)
{
lsm6dsrx_func_cfg_access_t func_cfg_access;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
- if(ret == 0){
- func_cfg_access.reg_access= (uint8_t)val;
+ (uint8_t *)&func_cfg_access, 1);
+
+ if (ret == 0)
+ {
+ func_cfg_access.reg_access = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
+ (uint8_t *)&func_cfg_access, 1);
}
+
return ret;
}
@@ -1629,27 +1930,33 @@ int32_t lsm6dsrx_mem_bank_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_mem_bank_get(stmdev_ctx_t *ctx,
- lsm6dsrx_reg_access_t *val)
+ lsm6dsrx_reg_access_t *val)
{
lsm6dsrx_func_cfg_access_t func_cfg_access;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FUNC_CFG_ACCESS,
- (uint8_t*)&func_cfg_access, 1);
- switch (func_cfg_access.reg_access){
+ (uint8_t *)&func_cfg_access, 1);
+
+ switch (func_cfg_access.reg_access)
+ {
case LSM6DSRX_USER_BANK:
*val = LSM6DSRX_USER_BANK;
break;
+
case LSM6DSRX_SENSOR_HUB_BANK:
*val = LSM6DSRX_SENSOR_HUB_BANK;
break;
+
case LSM6DSRX_EMBEDDED_FUNC_BANK:
*val = LSM6DSRX_EMBEDDED_FUNC_BANK;
break;
+
default:
*val = LSM6DSRX_USER_BANK;
break;
}
+
return ret;
}
@@ -1663,7 +1970,7 @@ int32_t lsm6dsrx_mem_bank_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t add,
- uint8_t *val)
+ uint8_t *val)
{
lsm6dsrx_page_rw_t page_rw;
lsm6dsrx_page_sel_t page_sel;
@@ -1671,40 +1978,59 @@ int32_t lsm6dsrx_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t add,
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t*)&page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x02U; /* page_write enable */
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t*)&page_rw, 1);
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_SEL, (uint8_t*)&page_sel, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_SEL, (uint8_t *)&page_sel, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU);
page_sel.not_used_01 = 1;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
+ (uint8_t *)&page_sel, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U));
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_ADDRESS,
- (uint8_t*)&page_address, 1);
+ (uint8_t *)&page_address, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_VALUE, val, 1);
}
- if(ret == 0){
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t*)&page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x00; /* page_write disable */
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t*)&page_rw, 1);
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -1714,82 +2040,108 @@ int32_t lsm6dsrx_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t add,
* @param ctx Read / write interface definitions.(ptr)
* @param buf Page line address.(ptr)
* @param val Value to write.
- * @param len buffer lengh.
+ * @param len buffer length.
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
int32_t lsm6dsrx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t add,
- uint8_t *buf, uint8_t len)
+ uint8_t *buf, uint8_t len)
{
lsm6dsrx_page_rw_t page_rw;
lsm6dsrx_page_sel_t page_sel;
lsm6dsrx_page_address_t page_address;
int32_t ret;
+
uint8_t msb, lsb;
uint8_t i ;
-
- msb = (uint8_t) (add / 256U);
- lsb = (uint8_t) (add - (msb * 256U));
-
+ msb = (uint8_t)(add / 256U);
+ lsb = (uint8_t)(add - (msb * 256U));
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t*)&page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x02U; /* page_write enable*/
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t*)&page_rw, 1);
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_SEL, (uint8_t*)&page_sel, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_SEL, (uint8_t *)&page_sel, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_sel.page_sel = msb;
page_sel.not_used_01 = 1;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
+ (uint8_t *)&page_sel, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_address.page_addr = lsb;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_ADDRESS,
- (uint8_t*)&page_address, 1);
+ (uint8_t *)&page_address, 1);
}
- for (i = 0; i < len; i++){
- if(ret == 0){
+
+ for (i = 0; i < len; i++)
+ {
+ if (ret == 0)
+ {
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_VALUE, &buf[i], 1);
- if(ret == 0){
+
+ if (ret == 0)
+ {
/* Check if page wrap */
- if (lsb == 0x00U){
+ if (lsb == 0x00U)
+ {
msb++;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
+ (uint8_t *)&page_sel, 1);
}
+
lsb++;
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_sel.page_sel = msb;
page_sel.not_used_01 = 1;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
+ (uint8_t *)&page_sel, 1);
}
}
}
- if(ret == 0){
+ if (ret == 0)
+ {
page_sel.page_sel = 0;
page_sel.not_used_01 = 1;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
+ (uint8_t *)&page_sel, 1);
}
- if(ret == 0){
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t*)&page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x00U; /* page_write disable */
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t*)&page_rw, 1);
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -1803,7 +2155,7 @@ int32_t lsm6dsrx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t add,
*
*/
int32_t lsm6dsrx_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add,
- uint8_t *val)
+ uint8_t *val)
{
lsm6dsrx_page_rw_t page_rw;
lsm6dsrx_page_sel_t page_sel;
@@ -1811,40 +2163,59 @@ int32_t lsm6dsrx_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add,
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t*)&page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x01U; /* page_read enable*/
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t*)&page_rw, 1);
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_SEL, (uint8_t*)&page_sel, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_SEL, (uint8_t *)&page_sel, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU);
page_sel.not_used_01 = 1;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_SEL,
- (uint8_t*)&page_sel, 1);
+ (uint8_t *)&page_sel, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U));
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_ADDRESS,
- (uint8_t*)&page_address, 1);
+ (uint8_t *)&page_address, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_VALUE, val, 2);
}
- if(ret == 0){
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t*)&page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_rw.page_rw = 0x00U; /* page_read disable */
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t*)&page_rw, 1);
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -1858,18 +2229,21 @@ int32_t lsm6dsrx_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add,
*
*/
int32_t lsm6dsrx_data_ready_mode_set(stmdev_ctx_t *ctx,
- lsm6dsrx_dataready_pulsed_t val)
+ lsm6dsrx_dataready_pulsed_t val)
{
lsm6dsrx_counter_bdr_reg1_t counter_bdr_reg1;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if(ret == 0){
- counter_bdr_reg1.dataready_pulsed= (uint8_t)val;
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
+ counter_bdr_reg1.dataready_pulsed = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
}
+
return ret;
}
@@ -1883,24 +2257,29 @@ int32_t lsm6dsrx_data_ready_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_data_ready_mode_get(stmdev_ctx_t *ctx,
- lsm6dsrx_dataready_pulsed_t *val)
+ lsm6dsrx_dataready_pulsed_t *val)
{
lsm6dsrx_counter_bdr_reg1_t counter_bdr_reg1;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- switch (counter_bdr_reg1.dataready_pulsed){
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ switch (counter_bdr_reg1.dataready_pulsed)
+ {
case LSM6DSRX_DRDY_LATCHED:
*val = LSM6DSRX_DRDY_LATCHED;
break;
+
case LSM6DSRX_DRDY_PULSED:
*val = LSM6DSRX_DRDY_PULSED;
break;
+
default:
*val = LSM6DSRX_DRDY_LATCHED;
break;
}
+
return ret;
}
@@ -1915,7 +2294,9 @@ int32_t lsm6dsrx_data_ready_mode_get(stmdev_ctx_t *ctx,
int32_t lsm6dsrx_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WHO_AM_I, buff, 1);
+
return ret;
}
@@ -1932,11 +2313,14 @@ int32_t lsm6dsrx_reset_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsrx_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.sw_reset= (uint8_t)val;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.sw_reset = (uint8_t)val;
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1953,7 +2337,7 @@ int32_t lsm6dsrx_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsrx_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.sw_reset;
return ret;
@@ -1973,11 +2357,14 @@ int32_t lsm6dsrx_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsrx_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.if_inc= (uint8_t)val;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.if_inc = (uint8_t)val;
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -1995,7 +2382,7 @@ int32_t lsm6dsrx_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsrx_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.if_inc;
return ret;
@@ -2014,11 +2401,14 @@ int32_t lsm6dsrx_boot_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsrx_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.boot= (uint8_t)val;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.boot = (uint8_t)val;
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -2035,7 +2425,7 @@ int32_t lsm6dsrx_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsrx_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
*val = ctrl3_c.boot;
return ret;
@@ -2052,16 +2442,19 @@ int32_t lsm6dsrx_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsrx_xl_self_test_set(stmdev_ctx_t *ctx,
- lsm6dsrx_st_xl_t val)
+ lsm6dsrx_st_xl_t val)
{
lsm6dsrx_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
- ctrl5_c.st_xl= (uint8_t)val;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl5_c.st_xl = (uint8_t)val;
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -2074,27 +2467,32 @@ int32_t lsm6dsrx_xl_self_test_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_xl_self_test_get(stmdev_ctx_t *ctx,
- lsm6dsrx_st_xl_t *val)
+ lsm6dsrx_st_xl_t *val)
{
lsm6dsrx_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
- switch (ctrl5_c.st_xl){
+ switch (ctrl5_c.st_xl)
+ {
case LSM6DSRX_XL_ST_DISABLE:
*val = LSM6DSRX_XL_ST_DISABLE;
break;
+
case LSM6DSRX_XL_ST_POSITIVE:
*val = LSM6DSRX_XL_ST_POSITIVE;
break;
+
case LSM6DSRX_XL_ST_NEGATIVE:
*val = LSM6DSRX_XL_ST_NEGATIVE;
break;
+
default:
*val = LSM6DSRX_XL_ST_DISABLE;
break;
}
+
return ret;
}
@@ -2107,16 +2505,19 @@ int32_t lsm6dsrx_xl_self_test_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_gy_self_test_set(stmdev_ctx_t *ctx,
- lsm6dsrx_st_g_t val)
+ lsm6dsrx_st_g_t val)
{
lsm6dsrx_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
- if(ret == 0){
- ctrl5_c.st_g= (uint8_t)val;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl5_c.st_g = (uint8_t)val;
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
}
+
return ret;
}
@@ -2129,27 +2530,32 @@ int32_t lsm6dsrx_gy_self_test_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_gy_self_test_get(stmdev_ctx_t *ctx,
- lsm6dsrx_st_g_t *val)
+ lsm6dsrx_st_g_t *val)
{
lsm6dsrx_ctrl5_c_t ctrl5_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
- switch (ctrl5_c.st_g){
+ switch (ctrl5_c.st_g)
+ {
case LSM6DSRX_GY_ST_DISABLE:
*val = LSM6DSRX_GY_ST_DISABLE;
break;
+
case LSM6DSRX_GY_ST_POSITIVE:
*val = LSM6DSRX_GY_ST_POSITIVE;
break;
+
case LSM6DSRX_GY_ST_NEGATIVE:
*val = LSM6DSRX_GY_ST_NEGATIVE;
break;
+
default:
*val = LSM6DSRX_GY_ST_DISABLE;
break;
}
+
return ret;
}
@@ -2179,12 +2585,15 @@ int32_t lsm6dsrx_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsrx_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
- if(ret == 0){
- ctrl1_xl.lpf2_xl_en= (uint8_t)val;
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl1_xl.lpf2_xl_en = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL1_XL,
- (uint8_t*)&ctrl1_xl, 1);
+ (uint8_t *)&ctrl1_xl, 1);
}
+
return ret;
}
@@ -2201,7 +2610,7 @@ int32_t lsm6dsrx_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsrx_ctrl1_xl_t ctrl1_xl;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
*val = ctrl1_xl.lpf2_xl_en;
return ret;
@@ -2221,11 +2630,14 @@ int32_t lsm6dsrx_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsrx_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ctrl4_c.lpf1_sel_g= (uint8_t)val;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl4_c.lpf1_sel_g = (uint8_t)val;
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -2243,7 +2655,7 @@ int32_t lsm6dsrx_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsrx_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.lpf1_sel_g;
return ret;
@@ -2258,16 +2670,20 @@ int32_t lsm6dsrx_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dsrx_filter_settling_mask_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dsrx_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ctrl4_c.drdy_mask= (uint8_t)val;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl4_c.drdy_mask = (uint8_t)val;
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -2281,12 +2697,12 @@ int32_t lsm6dsrx_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val)
*
*/
int32_t lsm6dsrx_filter_settling_mask_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
lsm6dsrx_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.drdy_mask;
return ret;
@@ -2301,16 +2717,19 @@ int32_t lsm6dsrx_filter_settling_mask_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
- lsm6dsrx_ftype_t val)
+ lsm6dsrx_ftype_t val)
{
lsm6dsrx_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
- ctrl6_c.ftype= (uint8_t)val;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl6_c.ftype = (uint8_t)val;
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -2323,42 +2742,52 @@ int32_t lsm6dsrx_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
- lsm6dsrx_ftype_t *val)
+ lsm6dsrx_ftype_t *val)
{
lsm6dsrx_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
- switch (ctrl6_c.ftype){
+ switch (ctrl6_c.ftype)
+ {
case LSM6DSRX_ULTRA_LIGHT:
*val = LSM6DSRX_ULTRA_LIGHT;
break;
+
case LSM6DSRX_VERY_LIGHT:
*val = LSM6DSRX_VERY_LIGHT;
break;
+
case LSM6DSRX_LIGHT:
*val = LSM6DSRX_LIGHT;
break;
+
case LSM6DSRX_MEDIUM:
*val = LSM6DSRX_MEDIUM;
break;
+
case LSM6DSRX_STRONG:
*val = LSM6DSRX_STRONG;
break;
+
case LSM6DSRX_VERY_STRONG:
*val = LSM6DSRX_VERY_STRONG;
break;
+
case LSM6DSRX_AGGRESSIVE:
*val = LSM6DSRX_AGGRESSIVE;
break;
+
case LSM6DSRX_XTREME:
*val = LSM6DSRX_XTREME;
break;
+
default:
*val = LSM6DSRX_ULTRA_LIGHT;
break;
}
+
return ret;
}
@@ -2375,12 +2804,15 @@ int32_t lsm6dsrx_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsrx_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
- ctrl8_xl.low_pass_on_6d= (uint8_t)val;
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl8_xl.low_pass_on_6d = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL8_XL,
- (uint8_t*)&ctrl8_xl, 1);
+ (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -2397,7 +2829,7 @@ int32_t lsm6dsrx_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsrx_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
*val = ctrl8_xl.low_pass_on_6d;
return ret;
@@ -2413,19 +2845,22 @@ int32_t lsm6dsrx_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsrx_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
- lsm6dsrx_hp_slope_xl_en_t val)
+ lsm6dsrx_hp_slope_xl_en_t val)
{
lsm6dsrx_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
ctrl8_xl.hp_slope_xl_en = (((uint8_t)val & 0x10U) >> 4);
ctrl8_xl.hp_ref_mode_xl = (((uint8_t)val & 0x20U) >> 5);
ctrl8_xl.hpcf_xl = (uint8_t)val & 0x07U;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL8_XL,
- (uint8_t*)&ctrl8_xl, 1);
+ (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -2439,87 +2874,114 @@ int32_t lsm6dsrx_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
- lsm6dsrx_hp_slope_xl_en_t *val)
+ lsm6dsrx_hp_slope_xl_en_t *val)
{
lsm6dsrx_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- switch (( (ctrl8_xl.hp_ref_mode_xl << 5) +(ctrl8_xl.hp_slope_xl_en << 4) +
- ctrl8_xl.hpcf_xl )){
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ switch (((ctrl8_xl.hp_ref_mode_xl << 5) + (ctrl8_xl.hp_slope_xl_en <<
+ 4) +
+ ctrl8_xl.hpcf_xl))
+ {
case LSM6DSRX_HP_PATH_DISABLE_ON_OUT:
*val = LSM6DSRX_HP_PATH_DISABLE_ON_OUT;
break;
+
case LSM6DSRX_SLOPE_ODR_DIV_4:
*val = LSM6DSRX_SLOPE_ODR_DIV_4;
break;
+
case LSM6DSRX_HP_ODR_DIV_10:
*val = LSM6DSRX_HP_ODR_DIV_10;
break;
+
case LSM6DSRX_HP_ODR_DIV_20:
*val = LSM6DSRX_HP_ODR_DIV_20;
break;
+
case LSM6DSRX_HP_ODR_DIV_45:
*val = LSM6DSRX_HP_ODR_DIV_45;
break;
+
case LSM6DSRX_HP_ODR_DIV_100:
*val = LSM6DSRX_HP_ODR_DIV_100;
break;
+
case LSM6DSRX_HP_ODR_DIV_200:
*val = LSM6DSRX_HP_ODR_DIV_200;
break;
+
case LSM6DSRX_HP_ODR_DIV_400:
*val = LSM6DSRX_HP_ODR_DIV_400;
break;
+
case LSM6DSRX_HP_ODR_DIV_800:
*val = LSM6DSRX_HP_ODR_DIV_800;
break;
+
case LSM6DSRX_HP_REF_MD_ODR_DIV_10:
*val = LSM6DSRX_HP_REF_MD_ODR_DIV_10;
break;
+
case LSM6DSRX_HP_REF_MD_ODR_DIV_20:
*val = LSM6DSRX_HP_REF_MD_ODR_DIV_20;
break;
+
case LSM6DSRX_HP_REF_MD_ODR_DIV_45:
*val = LSM6DSRX_HP_REF_MD_ODR_DIV_45;
break;
+
case LSM6DSRX_HP_REF_MD_ODR_DIV_100:
*val = LSM6DSRX_HP_REF_MD_ODR_DIV_100;
break;
+
case LSM6DSRX_HP_REF_MD_ODR_DIV_200:
*val = LSM6DSRX_HP_REF_MD_ODR_DIV_200;
break;
+
case LSM6DSRX_HP_REF_MD_ODR_DIV_400:
*val = LSM6DSRX_HP_REF_MD_ODR_DIV_400;
break;
+
case LSM6DSRX_HP_REF_MD_ODR_DIV_800:
*val = LSM6DSRX_HP_REF_MD_ODR_DIV_800;
break;
+
case LSM6DSRX_LP_ODR_DIV_10:
*val = LSM6DSRX_LP_ODR_DIV_10;
break;
+
case LSM6DSRX_LP_ODR_DIV_20:
*val = LSM6DSRX_LP_ODR_DIV_20;
break;
+
case LSM6DSRX_LP_ODR_DIV_45:
*val = LSM6DSRX_LP_ODR_DIV_45;
break;
+
case LSM6DSRX_LP_ODR_DIV_100:
*val = LSM6DSRX_LP_ODR_DIV_100;
break;
+
case LSM6DSRX_LP_ODR_DIV_200:
*val = LSM6DSRX_LP_ODR_DIV_200;
break;
+
case LSM6DSRX_LP_ODR_DIV_400:
*val = LSM6DSRX_LP_ODR_DIV_400;
break;
+
case LSM6DSRX_LP_ODR_DIV_800:
*val = LSM6DSRX_LP_ODR_DIV_800;
break;
+
default:
*val = LSM6DSRX_HP_PATH_DISABLE_ON_OUT;
break;
}
+
return ret;
}
@@ -2538,12 +3000,15 @@ int32_t lsm6dsrx_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsrx_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
- if(ret == 0){
- ctrl8_xl.fastsettl_mode_xl= (uint8_t)val;
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl8_xl.fastsettl_mode_xl = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL8_XL,
- (uint8_t*)&ctrl8_xl, 1);
+ (uint8_t *)&ctrl8_xl, 1);
}
+
return ret;
}
@@ -2562,7 +3027,7 @@ int32_t lsm6dsrx_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsrx_ctrl8_xl_t ctrl8_xl;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
*val = ctrl8_xl.fastsettl_mode_xl;
return ret;
@@ -2578,17 +3043,20 @@ int32_t lsm6dsrx_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsrx_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
- lsm6dsrx_slope_fds_t val)
+ lsm6dsrx_slope_fds_t val)
{
lsm6dsrx_tap_cfg0_t tap_cfg0;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
- if(ret == 0){
- tap_cfg0.slope_fds= (uint8_t)val;
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
+
+ if (ret == 0)
+ {
+ tap_cfg0.slope_fds = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG0,
- (uint8_t*)&tap_cfg0, 1);
+ (uint8_t *)&tap_cfg0, 1);
}
+
return ret;
}
@@ -2602,23 +3070,28 @@ int32_t lsm6dsrx_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
- lsm6dsrx_slope_fds_t *val)
+ lsm6dsrx_slope_fds_t *val)
{
lsm6dsrx_tap_cfg0_t tap_cfg0;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
- switch (tap_cfg0.slope_fds){
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
+
+ switch (tap_cfg0.slope_fds)
+ {
case LSM6DSRX_USE_SLOPE:
*val = LSM6DSRX_USE_SLOPE;
break;
+
case LSM6DSRX_USE_HPF:
*val = LSM6DSRX_USE_HPF;
break;
+
default:
*val = LSM6DSRX_USE_SLOPE;
break;
}
+
return ret;
}
@@ -2632,17 +3105,20 @@ int32_t lsm6dsrx_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
- lsm6dsrx_hpm_g_t val)
+ lsm6dsrx_hpm_g_t val)
{
lsm6dsrx_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
ctrl7_g.hp_en_g = (((uint8_t)val & 0x80U) >> 7);
ctrl7_g.hpm_g = (uint8_t)val & 0x03U;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
}
+
return ret;
}
@@ -2656,33 +3132,40 @@ int32_t lsm6dsrx_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
- lsm6dsrx_hpm_g_t *val)
+ lsm6dsrx_hpm_g_t *val)
{
lsm6dsrx_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
- switch ((ctrl7_g.hp_en_g << 7) + ctrl7_g.hpm_g){
+ switch ((ctrl7_g.hp_en_g << 7) + ctrl7_g.hpm_g)
+ {
case LSM6DSRX_HP_FILTER_NONE:
*val = LSM6DSRX_HP_FILTER_NONE;
break;
+
case LSM6DSRX_HP_FILTER_16mHz:
*val = LSM6DSRX_HP_FILTER_16mHz;
break;
+
case LSM6DSRX_HP_FILTER_65mHz:
*val = LSM6DSRX_HP_FILTER_65mHz;
break;
+
case LSM6DSRX_HP_FILTER_260mHz:
*val = LSM6DSRX_HP_FILTER_260mHz;
break;
+
case LSM6DSRX_HP_FILTER_1Hz04:
*val = LSM6DSRX_HP_FILTER_1Hz04;
break;
+
default:
*val = LSM6DSRX_HP_FILTER_NONE;
break;
}
+
return ret;
}
@@ -2709,17 +3192,20 @@ int32_t lsm6dsrx_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx,
- lsm6dsrx_ois_pu_dis_t val)
+ lsm6dsrx_ois_pu_dis_t val)
{
lsm6dsrx_pin_ctrl_t pin_ctrl;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
- if(ret == 0){
- pin_ctrl.ois_pu_dis= (uint8_t)val;
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
+
+ if (ret == 0)
+ {
+ pin_ctrl.ois_pu_dis = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PIN_CTRL,
- (uint8_t*)&pin_ctrl, 1);
+ (uint8_t *)&pin_ctrl, 1);
}
+
return ret;
}
@@ -2733,24 +3219,28 @@ int32_t lsm6dsrx_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx,
- lsm6dsrx_ois_pu_dis_t *val)
+ lsm6dsrx_ois_pu_dis_t *val)
{
lsm6dsrx_pin_ctrl_t pin_ctrl;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
- switch (pin_ctrl.ois_pu_dis){
+ switch (pin_ctrl.ois_pu_dis)
+ {
case LSM6DSRX_AUX_PULL_UP_DISC:
*val = LSM6DSRX_AUX_PULL_UP_DISC;
break;
+
case LSM6DSRX_AUX_PULL_UP_CONNECT:
*val = LSM6DSRX_AUX_PULL_UP_CONNECT;
break;
+
default:
*val = LSM6DSRX_AUX_PULL_UP_DISC;
break;
}
+
return ret;
}
@@ -2763,17 +3253,20 @@ int32_t lsm6dsrx_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx,
- lsm6dsrx_ois_on_t val)
+ lsm6dsrx_ois_on_t val)
{
lsm6dsrx_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
- if(ret == 0){
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
+
+ if (ret == 0)
+ {
ctrl7_g.ois_on_en = (uint8_t)val & 0x01U;
ctrl7_g.ois_on = (uint8_t)val & 0x01U;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
}
+
return ret;
}
@@ -2786,24 +3279,28 @@ int32_t lsm6dsrx_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx,
- lsm6dsrx_ois_on_t *val)
+ lsm6dsrx_ois_on_t *val)
{
lsm6dsrx_ctrl7_g_t ctrl7_g;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t*)&ctrl7_g, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
- switch (ctrl7_g.ois_on){
+ switch (ctrl7_g.ois_on)
+ {
case LSM6DSRX_AUX_ON:
*val = LSM6DSRX_AUX_ON;
break;
+
case LSM6DSRX_AUX_ON_BY_AUX_INTERFACE:
*val = LSM6DSRX_AUX_ON_BY_AUX_INTERFACE;
break;
+
default:
*val = LSM6DSRX_AUX_ON;
break;
}
+
return ret;
}
@@ -2816,10 +3313,12 @@ int32_t lsm6dsrx_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_aux_status_reg_get(stmdev_ctx_t *ctx,
- lsm6dsrx_status_spiaux_t *val)
+ lsm6dsrx_status_spiaux_t *val)
{
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_SPIAUX, (uint8_t*)val, 1);
+
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_SPIAUX, (uint8_t *)val, 1);
+
return ret;
}
@@ -2832,13 +3331,13 @@ int32_t lsm6dsrx_aux_status_reg_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
lsm6dsrx_status_spiaux_t status_spiaux;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_SPIAUX,
- (uint8_t*)&status_spiaux, 1);
+ (uint8_t *)&status_spiaux, 1);
*val = status_spiaux.xlda;
return ret;
@@ -2853,13 +3352,13 @@ int32_t lsm6dsrx_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
lsm6dsrx_status_spiaux_t status_spiaux;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_SPIAUX,
- (uint8_t*)&status_spiaux, 1);
+ (uint8_t *)&status_spiaux, 1);
*val = status_spiaux.gda;
return ret;
@@ -2873,13 +3372,14 @@ int32_t lsm6dsrx_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsrx_aux_gy_flag_settling_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsrx_status_spiaux_t status_spiaux;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_SPIAUX,
- (uint8_t*)&status_spiaux, 1);
+ (uint8_t *)&status_spiaux, 1);
*val = status_spiaux.gyro_settling;
return ret;
@@ -2895,16 +3395,19 @@ int32_t lsm6dsrx_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsrx_aux_xl_self_test_set(stmdev_ctx_t *ctx,
- lsm6dsrx_st_xl_ois_t val)
+ lsm6dsrx_st_xl_ois_t val)
{
lsm6dsrx_int_ois_t int_ois;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t*)&int_ois, 1);
- if(ret == 0){
- int_ois.st_xl_ois= (uint8_t)val;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t*)&int_ois, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t *)&int_ois, 1);
+
+ if (ret == 0)
+ {
+ int_ois.st_xl_ois = (uint8_t)val;
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t *)&int_ois, 1);
}
+
return ret;
}
@@ -2918,27 +3421,32 @@ int32_t lsm6dsrx_aux_xl_self_test_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_aux_xl_self_test_get(stmdev_ctx_t *ctx,
- lsm6dsrx_st_xl_ois_t *val)
+ lsm6dsrx_st_xl_ois_t *val)
{
lsm6dsrx_int_ois_t int_ois;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t*)&int_ois, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t *)&int_ois, 1);
- switch (int_ois.st_xl_ois){
+ switch (int_ois.st_xl_ois)
+ {
case LSM6DSRX_AUX_XL_DISABLE:
*val = LSM6DSRX_AUX_XL_DISABLE;
break;
+
case LSM6DSRX_AUX_XL_POS:
*val = LSM6DSRX_AUX_XL_POS;
break;
+
case LSM6DSRX_AUX_XL_NEG:
*val = LSM6DSRX_AUX_XL_NEG;
break;
+
default:
*val = LSM6DSRX_AUX_XL_DISABLE;
break;
}
+
return ret;
}
@@ -2951,16 +3459,19 @@ int32_t lsm6dsrx_aux_xl_self_test_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_aux_den_polarity_set(stmdev_ctx_t *ctx,
- lsm6dsrx_den_lh_ois_t val)
+ lsm6dsrx_den_lh_ois_t val)
{
lsm6dsrx_int_ois_t int_ois;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t*)&int_ois, 1);
- if(ret == 0){
- int_ois.den_lh_ois= (uint8_t)val;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t*)&int_ois, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t *)&int_ois, 1);
+
+ if (ret == 0)
+ {
+ int_ois.den_lh_ois = (uint8_t)val;
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t *)&int_ois, 1);
}
+
return ret;
}
@@ -2973,24 +3484,28 @@ int32_t lsm6dsrx_aux_den_polarity_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_aux_den_polarity_get(stmdev_ctx_t *ctx,
- lsm6dsrx_den_lh_ois_t *val)
+ lsm6dsrx_den_lh_ois_t *val)
{
lsm6dsrx_int_ois_t int_ois;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t*)&int_ois, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t *)&int_ois, 1);
- switch (int_ois.den_lh_ois){
+ switch (int_ois.den_lh_ois)
+ {
case LSM6DSRX_AUX_DEN_ACTIVE_LOW:
*val = LSM6DSRX_AUX_DEN_ACTIVE_LOW;
break;
+
case LSM6DSRX_AUX_DEN_ACTIVE_HIGH:
*val = LSM6DSRX_AUX_DEN_ACTIVE_HIGH;
break;
+
default:
*val = LSM6DSRX_AUX_DEN_ACTIVE_LOW;
break;
}
+
return ret;
}
@@ -3003,26 +3518,33 @@ int32_t lsm6dsrx_aux_den_polarity_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_aux_den_mode_set(stmdev_ctx_t *ctx,
- lsm6dsrx_lvl2_ois_t val)
+ lsm6dsrx_lvl2_ois_t val)
{
lsm6dsrx_int_ois_t int_ois;
lsm6dsrx_ctrl1_ois_t ctrl1_ois;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t*)&int_ois, 1);
- if(ret == 0){
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t *)&int_ois, 1);
+
+ if (ret == 0)
+ {
int_ois.lvl2_ois = (uint8_t)val & 0x01U;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t*)&int_ois, 1);
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t *)&int_ois, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ctrl1_ois.lvl1_ois = ((uint8_t)val & 0x02U) >> 1;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
}
+
return ret;
}
@@ -3035,32 +3557,39 @@ int32_t lsm6dsrx_aux_den_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_aux_den_mode_get(stmdev_ctx_t *ctx,
- lsm6dsrx_lvl2_ois_t *val)
+ lsm6dsrx_lvl2_ois_t *val)
{
lsm6dsrx_int_ois_t int_ois;
lsm6dsrx_ctrl1_ois_t ctrl1_ois;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t*)&int_ois, 1);
- if(ret == 0){
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t *)&int_ois, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
}
- switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois){
+ switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois)
+ {
case LSM6DSRX_AUX_DEN_DISABLE:
*val = LSM6DSRX_AUX_DEN_DISABLE;
break;
+
case LSM6DSRX_AUX_DEN_LEVEL_LATCH:
*val = LSM6DSRX_AUX_DEN_LEVEL_LATCH;
break;
+
case LSM6DSRX_AUX_DEN_LEVEL_TRIG:
*val = LSM6DSRX_AUX_DEN_LEVEL_TRIG;
break;
+
default:
*val = LSM6DSRX_AUX_DEN_DISABLE;
break;
}
+
return ret;
}
@@ -3078,11 +3607,14 @@ int32_t lsm6dsrx_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsrx_int_ois_t int_ois;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t*)&int_ois, 1);
- if(ret == 0){
- int_ois.int2_drdy_ois= (uint8_t)val;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t*)&int_ois, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t *)&int_ois, 1);
+
+ if (ret == 0)
+ {
+ int_ois.int2_drdy_ois = (uint8_t)val;
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t *)&int_ois, 1);
}
+
return ret;
}
@@ -3100,7 +3632,7 @@ int32_t lsm6dsrx_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsrx_int_ois_t int_ois;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t*)&int_ois, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t *)&int_ois, 1);
*val = int_ois.int2_drdy_ois;
return ret;
@@ -3120,18 +3652,22 @@ int32_t lsm6dsrx_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsrx_aux_mode_set(stmdev_ctx_t *ctx,
- lsm6dsrx_ois_en_spi2_t val)
+ lsm6dsrx_ois_en_spi2_t val)
{
lsm6dsrx_ctrl1_ois_t ctrl1_ois;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
- if(ret == 0){
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS,
+ (uint8_t *)&ctrl1_ois, 1);
+
+ if (ret == 0)
+ {
ctrl1_ois.ois_en_spi2 = (uint8_t)val & 0x01U;
ctrl1_ois.mode4_en = ((uint8_t)val & 0x02U) >> 1;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
}
+
return ret;
}
@@ -3150,27 +3686,33 @@ int32_t lsm6dsrx_aux_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_aux_mode_get(stmdev_ctx_t *ctx,
- lsm6dsrx_ois_en_spi2_t *val)
+ lsm6dsrx_ois_en_spi2_t *val)
{
lsm6dsrx_ctrl1_ois_t ctrl1_ois;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS,
+ (uint8_t *)&ctrl1_ois, 1);
- switch (((ctrl1_ois.mode4_en << 1) + ctrl1_ois.ois_en_spi2)){
+ switch (((ctrl1_ois.mode4_en << 1) + ctrl1_ois.ois_en_spi2))
+ {
case LSM6DSRX_AUX_DISABLE:
*val = LSM6DSRX_AUX_DISABLE;
break;
+
case LSM6DSRX_MODE_3_GY:
*val = LSM6DSRX_MODE_3_GY;
break;
+
case LSM6DSRX_MODE_4_GY_XL:
*val = LSM6DSRX_MODE_4_GY_XL;
break;
+
default:
*val = LSM6DSRX_AUX_DISABLE;
break;
}
+
return ret;
}
@@ -3183,18 +3725,22 @@ int32_t lsm6dsrx_aux_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_aux_gy_full_scale_set(stmdev_ctx_t *ctx,
- lsm6dsrx_fs_g_ois_t val)
+ lsm6dsrx_fs_g_ois_t val)
{
lsm6dsrx_ctrl1_ois_t ctrl1_ois;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
- if(ret == 0){
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS,
+ (uint8_t *)&ctrl1_ois, 1);
+
+ if (ret == 0)
+ {
ctrl1_ois.fs_g_ois = (uint8_t)val & 0x03U;
ctrl1_ois.fs_125_ois = ((uint8_t)val & 0x04U) >> 2;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
}
+
return ret;
}
@@ -3207,34 +3753,41 @@ int32_t lsm6dsrx_aux_gy_full_scale_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_aux_gy_full_scale_get(stmdev_ctx_t *ctx,
- lsm6dsrx_fs_g_ois_t *val)
+ lsm6dsrx_fs_g_ois_t *val)
{
lsm6dsrx_ctrl1_ois_t ctrl1_ois;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
- switch ( ( ctrl1_ois.fs_125_ois << 2 ) + ctrl1_ois.fs_g_ois ){
+ switch ((ctrl1_ois.fs_125_ois << 2) + ctrl1_ois.fs_g_ois)
+ {
case LSM6DSRX_250dps_AUX:
*val = LSM6DSRX_250dps_AUX;
break;
+
case LSM6DSRX_125dps_AUX:
*val = LSM6DSRX_125dps_AUX;
break;
+
case LSM6DSRX_500dps_AUX:
*val = LSM6DSRX_500dps_AUX;
break;
+
case LSM6DSRX_1000dps_AUX:
*val = LSM6DSRX_1000dps_AUX;
break;
+
case LSM6DSRX_2000dps_AUX:
*val = LSM6DSRX_2000dps_AUX;
break;
+
default:
*val = LSM6DSRX_250dps_AUX;
break;
}
+
return ret;
}
@@ -3247,17 +3800,21 @@ int32_t lsm6dsrx_aux_gy_full_scale_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_aux_spi_mode_set(stmdev_ctx_t *ctx,
- lsm6dsrx_sim_ois_t val)
+ lsm6dsrx_sim_ois_t val)
{
lsm6dsrx_ctrl1_ois_t ctrl1_ois;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
- if(ret == 0){
- ctrl1_ois.sim_ois= (uint8_t)val;
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS,
+ (uint8_t *)&ctrl1_ois, 1);
+
+ if (ret == 0)
+ {
+ ctrl1_ois.sim_ois = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL1_OIS,
- (uint8_t*)&ctrl1_ois, 1);
+ (uint8_t *)&ctrl1_ois, 1);
}
+
return ret;
}
@@ -3270,24 +3827,29 @@ int32_t lsm6dsrx_aux_spi_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_aux_spi_mode_get(stmdev_ctx_t *ctx,
- lsm6dsrx_sim_ois_t *val)
+ lsm6dsrx_sim_ois_t *val)
{
lsm6dsrx_ctrl1_ois_t ctrl1_ois;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS, (uint8_t*)&ctrl1_ois, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS,
+ (uint8_t *)&ctrl1_ois, 1);
- switch (ctrl1_ois.sim_ois){
+ switch (ctrl1_ois.sim_ois)
+ {
case LSM6DSRX_AUX_SPI_4_WIRE:
*val = LSM6DSRX_AUX_SPI_4_WIRE;
break;
+
case LSM6DSRX_AUX_SPI_3_WIRE:
*val = LSM6DSRX_AUX_SPI_3_WIRE;
break;
+
default:
*val = LSM6DSRX_AUX_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -3300,17 +3862,21 @@ int32_t lsm6dsrx_aux_spi_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
- lsm6dsrx_ftype_ois_t val)
+ lsm6dsrx_ftype_ois_t val)
{
lsm6dsrx_ctrl2_ois_t ctrl2_ois;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_OIS, (uint8_t*)&ctrl2_ois, 1);
- if(ret == 0){
- ctrl2_ois.ftype_ois= (uint8_t)val;
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_OIS,
+ (uint8_t *)&ctrl2_ois, 1);
+
+ if (ret == 0)
+ {
+ ctrl2_ois.ftype_ois = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL2_OIS,
- (uint8_t*)&ctrl2_ois, 1);
+ (uint8_t *)&ctrl2_ois, 1);
}
+
return ret;
}
@@ -3323,30 +3889,37 @@ int32_t lsm6dsrx_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
- lsm6dsrx_ftype_ois_t *val)
+ lsm6dsrx_ftype_ois_t *val)
{
lsm6dsrx_ctrl2_ois_t ctrl2_ois;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_OIS, (uint8_t*)&ctrl2_ois, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_OIS,
+ (uint8_t *)&ctrl2_ois, 1);
- switch (ctrl2_ois.ftype_ois){
+ switch (ctrl2_ois.ftype_ois)
+ {
case LSM6DSRX_351Hz39:
*val = LSM6DSRX_351Hz39;
break;
+
case LSM6DSRX_236Hz63:
*val = LSM6DSRX_236Hz63;
break;
+
case LSM6DSRX_172Hz70:
*val = LSM6DSRX_172Hz70;
break;
+
case LSM6DSRX_937Hz91:
*val = LSM6DSRX_937Hz91;
break;
+
default:
*val = LSM6DSRX_351Hz39;
break;
}
+
return ret;
}
@@ -3359,18 +3932,22 @@ int32_t lsm6dsrx_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx,
- lsm6dsrx_hpm_ois_t val)
+ lsm6dsrx_hpm_ois_t val)
{
lsm6dsrx_ctrl2_ois_t ctrl2_ois;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_OIS, (uint8_t*)&ctrl2_ois, 1);
- if(ret == 0){
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_OIS,
+ (uint8_t *)&ctrl2_ois, 1);
+
+ if (ret == 0)
+ {
ctrl2_ois.hpm_ois = (uint8_t)val & 0x03U;
ctrl2_ois.hp_en_ois = ((uint8_t)val & 0x10U) >> 4;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL2_OIS,
- (uint8_t*)&ctrl2_ois, 1);
+ (uint8_t *)&ctrl2_ois, 1);
}
+
return ret;
}
@@ -3383,33 +3960,41 @@ int32_t lsm6dsrx_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx,
- lsm6dsrx_hpm_ois_t *val)
+ lsm6dsrx_hpm_ois_t *val)
{
lsm6dsrx_ctrl2_ois_t ctrl2_ois;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_OIS, (uint8_t*)&ctrl2_ois, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_OIS,
+ (uint8_t *)&ctrl2_ois, 1);
- switch ((ctrl2_ois.hp_en_ois << 4) + ctrl2_ois.hpm_ois){
+ switch ((ctrl2_ois.hp_en_ois << 4) + ctrl2_ois.hpm_ois)
+ {
case LSM6DSRX_AUX_HP_DISABLE:
*val = LSM6DSRX_AUX_HP_DISABLE;
break;
+
case LSM6DSRX_AUX_HP_Hz016:
*val = LSM6DSRX_AUX_HP_Hz016;
break;
+
case LSM6DSRX_AUX_HP_Hz065:
*val = LSM6DSRX_AUX_HP_Hz065;
break;
+
case LSM6DSRX_AUX_HP_Hz260:
*val = LSM6DSRX_AUX_HP_Hz260;
break;
+
case LSM6DSRX_AUX_HP_1Hz040:
*val = LSM6DSRX_AUX_HP_1Hz040;
break;
+
default:
*val = LSM6DSRX_AUX_HP_DISABLE;
break;
}
+
return ret;
}
@@ -3424,17 +4009,21 @@ int32_t lsm6dsrx_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_aux_gy_clamp_set(stmdev_ctx_t *ctx,
- lsm6dsrx_st_ois_clampdis_t val)
+ lsm6dsrx_st_ois_clampdis_t val)
{
lsm6dsrx_ctrl3_ois_t ctrl3_ois;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
- if(ret == 0){
- ctrl3_ois.st_ois_clampdis= (uint8_t)val;
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS,
+ (uint8_t *)&ctrl3_ois, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_ois.st_ois_clampdis = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_OIS,
- (uint8_t*)&ctrl3_ois, 1);
+ (uint8_t *)&ctrl3_ois, 1);
}
+
return ret;
}
@@ -3449,24 +4038,29 @@ int32_t lsm6dsrx_aux_gy_clamp_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_aux_gy_clamp_get(stmdev_ctx_t *ctx,
- lsm6dsrx_st_ois_clampdis_t *val)
+ lsm6dsrx_st_ois_clampdis_t *val)
{
lsm6dsrx_ctrl3_ois_t ctrl3_ois;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS,
+ (uint8_t *)&ctrl3_ois, 1);
- switch (ctrl3_ois.st_ois_clampdis){
+ switch (ctrl3_ois.st_ois_clampdis)
+ {
case LSM6DSRX_ENABLE_CLAMP:
*val = LSM6DSRX_ENABLE_CLAMP;
break;
+
case LSM6DSRX_DISABLE_CLAMP:
*val = LSM6DSRX_DISABLE_CLAMP;
break;
+
default:
*val = LSM6DSRX_ENABLE_CLAMP;
break;
}
+
return ret;
}
@@ -3479,17 +4073,21 @@ int32_t lsm6dsrx_aux_gy_clamp_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_aux_gy_self_test_set(stmdev_ctx_t *ctx,
- lsm6dsrx_st_ois_t val)
+ lsm6dsrx_st_ois_t val)
{
lsm6dsrx_ctrl3_ois_t ctrl3_ois;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
- if(ret == 0){
- ctrl3_ois.st_ois= (uint8_t)val;
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS,
+ (uint8_t *)&ctrl3_ois, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_ois.st_ois = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_OIS,
- (uint8_t*)&ctrl3_ois, 1);
+ (uint8_t *)&ctrl3_ois, 1);
}
+
return ret;
}
@@ -3502,27 +4100,33 @@ int32_t lsm6dsrx_aux_gy_self_test_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_aux_gy_self_test_get(stmdev_ctx_t *ctx,
- lsm6dsrx_st_ois_t *val)
+ lsm6dsrx_st_ois_t *val)
{
lsm6dsrx_ctrl3_ois_t ctrl3_ois;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS,
+ (uint8_t *)&ctrl3_ois, 1);
- switch (ctrl3_ois.st_ois){
+ switch (ctrl3_ois.st_ois)
+ {
case LSM6DSRX_AUX_GY_DISABLE:
*val = LSM6DSRX_AUX_GY_DISABLE;
break;
+
case LSM6DSRX_AUX_GY_POS:
*val = LSM6DSRX_AUX_GY_POS;
break;
+
case LSM6DSRX_AUX_GY_NEG:
*val = LSM6DSRX_AUX_GY_NEG;
break;
+
default:
*val = LSM6DSRX_AUX_GY_DISABLE;
break;
}
+
return ret;
}
@@ -3535,17 +4139,21 @@ int32_t lsm6dsrx_aux_gy_self_test_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_aux_xl_bandwidth_set(stmdev_ctx_t *ctx,
- lsm6dsrx_filter_xl_conf_ois_t val)
+ lsm6dsrx_filter_xl_conf_ois_t val)
{
lsm6dsrx_ctrl3_ois_t ctrl3_ois;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
- if(ret == 0){
- ctrl3_ois.filter_xl_conf_ois= (uint8_t)val;
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS,
+ (uint8_t *)&ctrl3_ois, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_ois.filter_xl_conf_ois = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_OIS,
- (uint8_t*)&ctrl3_ois, 1);
+ (uint8_t *)&ctrl3_ois, 1);
}
+
return ret;
}
@@ -3558,42 +4166,53 @@ int32_t lsm6dsrx_aux_xl_bandwidth_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_aux_xl_bandwidth_get(stmdev_ctx_t *ctx,
- lsm6dsrx_filter_xl_conf_ois_t *val)
+ lsm6dsrx_filter_xl_conf_ois_t *val)
{
lsm6dsrx_ctrl3_ois_t ctrl3_ois;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS,
+ (uint8_t *)&ctrl3_ois, 1);
- switch (ctrl3_ois.filter_xl_conf_ois){
+ switch (ctrl3_ois.filter_xl_conf_ois)
+ {
case LSM6DSRX_631Hz:
*val = LSM6DSRX_631Hz;
break;
+
case LSM6DSRX_295Hz:
*val = LSM6DSRX_295Hz;
break;
+
case LSM6DSRX_140Hz:
*val = LSM6DSRX_140Hz;
break;
+
case LSM6DSRX_68Hz2:
*val = LSM6DSRX_68Hz2;
break;
+
case LSM6DSRX_33Hz6:
*val = LSM6DSRX_33Hz6;
break;
+
case LSM6DSRX_16Hz7:
*val = LSM6DSRX_16Hz7;
break;
+
case LSM6DSRX_8Hz3:
*val = LSM6DSRX_8Hz3;
break;
+
case LSM6DSRX_4Hz11:
*val = LSM6DSRX_4Hz11;
break;
+
default:
*val = LSM6DSRX_631Hz;
break;
}
+
return ret;
}
@@ -3606,17 +4225,21 @@ int32_t lsm6dsrx_aux_xl_bandwidth_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_aux_xl_full_scale_set(stmdev_ctx_t *ctx,
- lsm6dsrx_fs_xl_ois_t val)
+ lsm6dsrx_fs_xl_ois_t val)
{
lsm6dsrx_ctrl3_ois_t ctrl3_ois;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
- if(ret == 0){
- ctrl3_ois.fs_xl_ois= (uint8_t)val;
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS,
+ (uint8_t *)&ctrl3_ois, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_ois.fs_xl_ois = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_OIS,
- (uint8_t*)&ctrl3_ois, 1);
+ (uint8_t *)&ctrl3_ois, 1);
}
+
return ret;
}
@@ -3629,30 +4252,37 @@ int32_t lsm6dsrx_aux_xl_full_scale_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_aux_xl_full_scale_get(stmdev_ctx_t *ctx,
- lsm6dsrx_fs_xl_ois_t *val)
+ lsm6dsrx_fs_xl_ois_t *val)
{
lsm6dsrx_ctrl3_ois_t ctrl3_ois;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS, (uint8_t*)&ctrl3_ois, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS,
+ (uint8_t *)&ctrl3_ois, 1);
- switch (ctrl3_ois.fs_xl_ois){
+ switch (ctrl3_ois.fs_xl_ois)
+ {
case LSM6DSRX_AUX_2g:
*val = LSM6DSRX_AUX_2g;
break;
+
case LSM6DSRX_AUX_16g:
*val = LSM6DSRX_AUX_16g;
break;
+
case LSM6DSRX_AUX_4g:
*val = LSM6DSRX_AUX_4g;
break;
+
case LSM6DSRX_AUX_8g:
*val = LSM6DSRX_AUX_8g;
break;
+
default:
*val = LSM6DSRX_AUX_2g;
break;
}
+
return ret;
}
@@ -3678,16 +4308,19 @@ int32_t lsm6dsrx_aux_xl_full_scale_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
- lsm6dsrx_sdo_pu_en_t val)
+ lsm6dsrx_sdo_pu_en_t val)
{
lsm6dsrx_pin_ctrl_t pin_ctrl;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
- if(ret == 0){
- pin_ctrl.sdo_pu_en= (uint8_t)val;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
+
+ if (ret == 0)
+ {
+ pin_ctrl.sdo_pu_en = (uint8_t)val;
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
}
+
return ret;
}
@@ -3700,24 +4333,28 @@ int32_t lsm6dsrx_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
- lsm6dsrx_sdo_pu_en_t *val)
+ lsm6dsrx_sdo_pu_en_t *val)
{
lsm6dsrx_pin_ctrl_t pin_ctrl;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
- switch (pin_ctrl.sdo_pu_en){
+ switch (pin_ctrl.sdo_pu_en)
+ {
case LSM6DSRX_PULL_UP_DISC:
*val = LSM6DSRX_PULL_UP_DISC;
break;
+
case LSM6DSRX_PULL_UP_CONNECT:
*val = LSM6DSRX_PULL_UP_CONNECT;
break;
+
default:
*val = LSM6DSRX_PULL_UP_DISC;
break;
}
+
return ret;
}
@@ -3729,17 +4366,22 @@ int32_t lsm6dsrx_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_int1_mode_set(stmdev_ctx_t *ctx, lsm6dsrx_pd_dis_int1_t val)
+int32_t lsm6dsrx_int1_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsrx_pd_dis_int1_t val)
{
lsm6dsrx_i3c_bus_avb_t i3c_bus_avb;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_I3C_BUS_AVB, (uint8_t*)&i3c_bus_avb, 1);
- if(ret == 0){
- i3c_bus_avb.pd_dis_int1= (uint8_t)val;
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_I3C_BUS_AVB,
+ (uint8_t *)&i3c_bus_avb, 1);
+
+ if (ret == 0)
+ {
+ i3c_bus_avb.pd_dis_int1 = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
}
+
return ret;
}
@@ -3751,24 +4393,30 @@ int32_t lsm6dsrx_int1_mode_set(stmdev_ctx_t *ctx, lsm6dsrx_pd_dis_int1_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_int1_mode_get(stmdev_ctx_t *ctx, lsm6dsrx_pd_dis_int1_t *val)
+int32_t lsm6dsrx_int1_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsrx_pd_dis_int1_t *val)
{
lsm6dsrx_i3c_bus_avb_t i3c_bus_avb;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_I3C_BUS_AVB, (uint8_t*)&i3c_bus_avb, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_I3C_BUS_AVB,
+ (uint8_t *)&i3c_bus_avb, 1);
- switch (i3c_bus_avb.pd_dis_int1){
+ switch (i3c_bus_avb.pd_dis_int1)
+ {
case LSM6DSRX_PULL_DOWN_CONNECT:
*val = LSM6DSRX_PULL_DOWN_CONNECT;
break;
+
case LSM6DSRX_PULL_DOWN_DISC:
*val = LSM6DSRX_PULL_DOWN_DISC;
break;
+
default:
*val = LSM6DSRX_PULL_DOWN_CONNECT;
break;
}
+
return ret;
}
@@ -3785,11 +4433,14 @@ int32_t lsm6dsrx_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsrx_sim_t val)
lsm6dsrx_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.sim= (uint8_t)val;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.sim = (uint8_t)val;
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -3806,19 +4457,23 @@ int32_t lsm6dsrx_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsrx_sim_t *val)
lsm6dsrx_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
- switch (ctrl3_c.sim){
+ switch (ctrl3_c.sim)
+ {
case LSM6DSRX_SPI_4_WIRE:
*val = LSM6DSRX_SPI_4_WIRE;
break;
+
case LSM6DSRX_SPI_3_WIRE:
*val = LSM6DSRX_SPI_3_WIRE;
break;
+
default:
*val = LSM6DSRX_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -3831,16 +4486,19 @@ int32_t lsm6dsrx_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsrx_sim_t *val)
*
*/
int32_t lsm6dsrx_i2c_interface_set(stmdev_ctx_t *ctx,
- lsm6dsrx_i2c_disable_t val)
+ lsm6dsrx_i2c_disable_t val)
{
lsm6dsrx_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ctrl4_c.i2c_disable= (uint8_t)val;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl4_c.i2c_disable = (uint8_t)val;
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -3853,24 +4511,28 @@ int32_t lsm6dsrx_i2c_interface_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_i2c_interface_get(stmdev_ctx_t *ctx,
- lsm6dsrx_i2c_disable_t *val)
+ lsm6dsrx_i2c_disable_t *val)
{
lsm6dsrx_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
- switch (ctrl4_c.i2c_disable){
+ switch (ctrl4_c.i2c_disable)
+ {
case LSM6DSRX_I2C_ENABLE:
*val = LSM6DSRX_I2C_ENABLE;
break;
+
case LSM6DSRX_I2C_DISABLE:
*val = LSM6DSRX_I2C_DISABLE;
break;
+
default:
*val = LSM6DSRX_I2C_ENABLE;
break;
}
+
return ret;
}
@@ -3883,27 +4545,34 @@ int32_t lsm6dsrx_i2c_interface_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_i3c_disable_set(stmdev_ctx_t *ctx,
- lsm6dsrx_i3c_disable_t val)
+ lsm6dsrx_i3c_disable_t val)
{
lsm6dsrx_ctrl9_xl_t ctrl9_xl;
lsm6dsrx_i3c_bus_avb_t i3c_bus_avb;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
+ (uint8_t *)&ctrl9_xl, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
}
+
return ret;
}
@@ -3916,37 +4585,47 @@ int32_t lsm6dsrx_i3c_disable_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_i3c_disable_get(stmdev_ctx_t *ctx,
- lsm6dsrx_i3c_disable_t *val)
+ lsm6dsrx_i3c_disable_t *val)
{
lsm6dsrx_ctrl9_xl_t ctrl9_xl;
lsm6dsrx_i3c_bus_avb_t i3c_bus_avb;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_I3C_BUS_AVB,
- (uint8_t*)&i3c_bus_avb, 1);
+ (uint8_t *)&i3c_bus_avb, 1);
}
- switch ((ctrl9_xl.i3c_disable << 7) + i3c_bus_avb.i3c_bus_avb_sel){
+
+ switch ((ctrl9_xl.i3c_disable << 7) + i3c_bus_avb.i3c_bus_avb_sel)
+ {
case LSM6DSRX_I3C_DISABLE:
*val = LSM6DSRX_I3C_DISABLE;
break;
+
case LSM6DSRX_I3C_ENABLE_T_50us:
*val = LSM6DSRX_I3C_ENABLE_T_50us;
break;
+
case LSM6DSRX_I3C_ENABLE_T_2us:
*val = LSM6DSRX_I3C_ENABLE_T_2us;
break;
+
case LSM6DSRX_I3C_ENABLE_T_1ms:
*val = LSM6DSRX_I3C_ENABLE_T_1ms;
break;
+
case LSM6DSRX_I3C_ENABLE_T_25ms:
*val = LSM6DSRX_I3C_ENABLE_T_25ms;
break;
+
default:
*val = LSM6DSRX_I3C_DISABLE;
break;
}
+
return ret;
}
@@ -3958,7 +4637,7 @@ int32_t lsm6dsrx_i3c_disable_get(stmdev_ctx_t *ctx,
/**
* @defgroup LSM6DSRX_interrupt_pins
* @brief This section groups all the functions that manage
- * interrup pins
+ * interrupt pins
* @{
*
*/
@@ -3973,35 +4652,46 @@ int32_t lsm6dsrx_i3c_disable_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_pin_int1_route_set(stmdev_ctx_t *ctx,
- lsm6dsrx_pin_int1_route_t *val)
+ lsm6dsrx_pin_int1_route_t *val)
{
lsm6dsrx_pin_int2_route_t pin_int2_route;
lsm6dsrx_tap_cfg2_t tap_cfg2;
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MLC_INT1,
- (uint8_t*)&val->mlc_int1, 1);
+ (uint8_t *)&val->mlc_int1, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_INT1,
- (uint8_t*)&val->emb_func_int1, 1);
+ (uint8_t *)&val->emb_func_int1, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FSM_INT1_A,
- (uint8_t*)&val->fsm_int1_a, 1);
+ (uint8_t *)&val->fsm_int1_a, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FSM_INT1_B,
- (uint8_t*)&val->fsm_int1_b, 1);
+ (uint8_t *)&val->fsm_int1_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
- if (ret == 0) {
- if ( ( val->emb_func_int1.int1_fsm_lc
+ if (ret == 0)
+ {
+ if ((val->emb_func_int1.int1_fsm_lc
| val->emb_func_int1.int1_sig_mot
| val->emb_func_int1.int1_step_detector
| val->emb_func_int1.int1_tilt
@@ -4028,27 +4718,39 @@ int32_t lsm6dsrx_pin_int1_route_set(stmdev_ctx_t *ctx,
| val->mlc_int1.int1_mlc5
| val->mlc_int1.int1_mlc6
| val->mlc_int1.int1_mlc7
- | val->mlc_int1.int1_mlc8) != PROPERTY_DISABLE){
+ | val->mlc_int1.int1_mlc8) != PROPERTY_DISABLE)
+ {
val->md1_cfg.int1_emb_func = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
val->md1_cfg.int1_emb_func = PROPERTY_DISABLE;
}
+
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INT1_CTRL,
- (uint8_t*)&val->int1_ctrl, 1);
+ (uint8_t *)&val->int1_ctrl, 1);
}
- if (ret == 0) {
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MD1_CFG, (uint8_t*)&val->md1_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MD1_CFG,
+ (uint8_t *)&val->md1_cfg, 1);
}
- if (ret == 0) {
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dsrx_pin_int2_route_get(ctx, &pin_int2_route);
}
- if (ret == 0) {
- if ( ( pin_int2_route.int2_ctrl.int2_cnt_bdr
+
+ if (ret == 0)
+ {
+ if ((pin_int2_route.int2_ctrl.int2_cnt_bdr
| pin_int2_route.int2_ctrl.int2_drdy_g
| pin_int2_route.int2_ctrl.int2_drdy_temp
| pin_int2_route.int2_ctrl.int2_drdy_xl
@@ -4075,14 +4777,20 @@ int32_t lsm6dsrx_pin_int1_route_set(stmdev_ctx_t *ctx,
| val->md1_cfg.int1_ff
| val->md1_cfg.int1_wu
| val->md1_cfg.int1_single_tap
- | val->md1_cfg.int1_sleep_change) != PROPERTY_DISABLE) {
+ | val->md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
+ {
tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
}
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
+
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG2,
+ (uint8_t *) &tap_cfg2, 1);
}
+
return ret;
}
@@ -4095,37 +4803,51 @@ int32_t lsm6dsrx_pin_int1_route_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_pin_int1_route_get(stmdev_ctx_t *ctx,
- lsm6dsrx_pin_int1_route_t *val)
+ lsm6dsrx_pin_int1_route_t *val)
{
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MLC_INT1,
- (uint8_t*)&val->mlc_int1, 1);
+ (uint8_t *)&val->mlc_int1, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_INT1,
- (uint8_t*)&val->emb_func_int1, 1);
+ (uint8_t *)&val->emb_func_int1, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_INT1_A,
- (uint8_t*)&val->fsm_int1_a, 1);
+ (uint8_t *)&val->fsm_int1_a, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_INT1_B,
- (uint8_t*)&val->fsm_int1_b, 1);
+ (uint8_t *)&val->fsm_int1_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT1_CTRL,
- (uint8_t*)&val->int1_ctrl, 1);
+ (uint8_t *)&val->int1_ctrl, 1);
}
- if (ret == 0) {
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MD1_CFG, (uint8_t*)&val->md1_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MD1_CFG,
+ (uint8_t *)&val->md1_cfg, 1);
}
return ret;
@@ -4140,83 +4862,105 @@ int32_t lsm6dsrx_pin_int1_route_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_pin_int2_route_set(stmdev_ctx_t *ctx,
- lsm6dsrx_pin_int2_route_t *val)
+ lsm6dsrx_pin_int2_route_t *val)
{
lsm6dsrx_pin_int1_route_t pin_int1_route;
lsm6dsrx_tap_cfg2_t tap_cfg2;
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MLC_INT2,
- (uint8_t*)&val->mlc_int2, 1);
+ (uint8_t *)&val->mlc_int2, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_INT2,
- (uint8_t*)&val->emb_func_int2, 1);
+ (uint8_t *)&val->emb_func_int2, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FSM_INT2_A,
- (uint8_t*)&val->fsm_int2_a, 1);
+ (uint8_t *)&val->fsm_int2_a, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FSM_INT2_B,
- (uint8_t*)&val->fsm_int2_b, 1);
+ (uint8_t *)&val->fsm_int2_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
- if (ret == 0) {
- if (( val->emb_func_int2.int2_fsm_lc
- | val->emb_func_int2.int2_sig_mot
- | val->emb_func_int2.int2_step_detector
- | val->emb_func_int2.int2_tilt
- | val->fsm_int2_a.int2_fsm1
- | val->fsm_int2_a.int2_fsm2
- | val->fsm_int2_a.int2_fsm3
- | val->fsm_int2_a.int2_fsm4
- | val->fsm_int2_a.int2_fsm5
- | val->fsm_int2_a.int2_fsm6
- | val->fsm_int2_a.int2_fsm7
- | val->fsm_int2_a.int2_fsm8
- | val->fsm_int2_b.int2_fsm9
- | val->fsm_int2_b.int2_fsm10
- | val->fsm_int2_b.int2_fsm11
- | val->fsm_int2_b.int2_fsm12
- | val->fsm_int2_b.int2_fsm13
- | val->fsm_int2_b.int2_fsm14
- | val->fsm_int2_b.int2_fsm15
- | val->fsm_int2_b.int2_fsm16
- | val->mlc_int2.int2_mlc1
- | val->mlc_int2.int2_mlc2
- | val->mlc_int2.int2_mlc3
- | val->mlc_int2.int2_mlc4
- | val->mlc_int2.int2_mlc5
- | val->mlc_int2.int2_mlc6
- | val->mlc_int2.int2_mlc7
- | val->mlc_int2.int2_mlc8)!= PROPERTY_DISABLE ){
+ if (ret == 0)
+ {
+ if ((val->emb_func_int2.int2_fsm_lc
+ | val->emb_func_int2.int2_sig_mot
+ | val->emb_func_int2.int2_step_detector
+ | val->emb_func_int2.int2_tilt
+ | val->fsm_int2_a.int2_fsm1
+ | val->fsm_int2_a.int2_fsm2
+ | val->fsm_int2_a.int2_fsm3
+ | val->fsm_int2_a.int2_fsm4
+ | val->fsm_int2_a.int2_fsm5
+ | val->fsm_int2_a.int2_fsm6
+ | val->fsm_int2_a.int2_fsm7
+ | val->fsm_int2_a.int2_fsm8
+ | val->fsm_int2_b.int2_fsm9
+ | val->fsm_int2_b.int2_fsm10
+ | val->fsm_int2_b.int2_fsm11
+ | val->fsm_int2_b.int2_fsm12
+ | val->fsm_int2_b.int2_fsm13
+ | val->fsm_int2_b.int2_fsm14
+ | val->fsm_int2_b.int2_fsm15
+ | val->fsm_int2_b.int2_fsm16
+ | val->mlc_int2.int2_mlc1
+ | val->mlc_int2.int2_mlc2
+ | val->mlc_int2.int2_mlc3
+ | val->mlc_int2.int2_mlc4
+ | val->mlc_int2.int2_mlc5
+ | val->mlc_int2.int2_mlc6
+ | val->mlc_int2.int2_mlc7
+ | val->mlc_int2.int2_mlc8) != PROPERTY_DISABLE)
+ {
val->md2_cfg.int2_emb_func = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
val->md2_cfg.int2_emb_func = PROPERTY_DISABLE;
}
+
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INT2_CTRL,
- (uint8_t*)&val->int2_ctrl, 1);
+ (uint8_t *)&val->int2_ctrl, 1);
}
- if (ret == 0) {
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MD2_CFG, (uint8_t*)&val->md2_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MD2_CFG,
+ (uint8_t *)&val->md2_cfg, 1);
}
- if (ret == 0) {
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dsrx_pin_int1_route_get(ctx, &pin_int1_route);
}
- if (ret == 0) {
- if ( ( val->int2_ctrl.int2_cnt_bdr
+ if (ret == 0)
+ {
+ if ((val->int2_ctrl.int2_cnt_bdr
| val->int2_ctrl.int2_drdy_g
| val->int2_ctrl.int2_drdy_temp
| val->int2_ctrl.int2_drdy_xl
@@ -4242,14 +4986,20 @@ int32_t lsm6dsrx_pin_int2_route_set(stmdev_ctx_t *ctx,
| pin_int1_route.md1_cfg.int1_ff
| pin_int1_route.md1_cfg.int1_wu
| pin_int1_route.md1_cfg.int1_single_tap
- | pin_int1_route.md1_cfg.int1_sleep_change ) != PROPERTY_DISABLE) {
+ | pin_int1_route.md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
+ {
tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
}
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
+
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG2,
+ (uint8_t *) &tap_cfg2, 1);
}
+
return ret;
}
@@ -4262,38 +5012,53 @@ int32_t lsm6dsrx_pin_int2_route_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_pin_int2_route_get(stmdev_ctx_t *ctx,
- lsm6dsrx_pin_int2_route_t *val)
+ lsm6dsrx_pin_int2_route_t *val)
{
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MLC_INT2,
- (uint8_t*)&val->mlc_int2, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MLC_INT2,
+ (uint8_t *)&val->mlc_int2, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_INT2,
- (uint8_t*)&val->emb_func_int2, 1);
+ (uint8_t *)&val->emb_func_int2, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_INT2_A,
- (uint8_t*)&val->fsm_int2_a, 1);
+ (uint8_t *)&val->fsm_int2_a, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_INT2_B,
- (uint8_t*)&val->fsm_int2_b, 1);
+ (uint8_t *)&val->fsm_int2_b, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
- if (ret == 0) {
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT2_CTRL,
- (uint8_t*)&val->int2_ctrl, 1);
+ (uint8_t *)&val->int2_ctrl, 1);
}
- if (ret == 0) {
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MD2_CFG, (uint8_t*)&val->md2_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MD2_CFG,
+ (uint8_t *)&val->md2_cfg, 1);
}
+
return ret;
}
@@ -4310,11 +5075,14 @@ int32_t lsm6dsrx_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsrx_pp_od_t val)
lsm6dsrx_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.pp_od= (uint8_t)val;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.pp_od = (uint8_t)val;
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -4326,24 +5094,29 @@ int32_t lsm6dsrx_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsrx_pp_od_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsrx_pp_od_t *val)
+int32_t lsm6dsrx_pin_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsrx_pp_od_t *val)
{
lsm6dsrx_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
- switch (ctrl3_c.pp_od){
+ switch (ctrl3_c.pp_od)
+ {
case LSM6DSRX_PUSH_PULL:
*val = LSM6DSRX_PUSH_PULL;
break;
+
case LSM6DSRX_OPEN_DRAIN:
*val = LSM6DSRX_OPEN_DRAIN;
break;
+
default:
*val = LSM6DSRX_PUSH_PULL;
break;
}
+
return ret;
}
@@ -4356,16 +5129,19 @@ int32_t lsm6dsrx_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsrx_pp_od_t *val)
*
*/
int32_t lsm6dsrx_pin_polarity_set(stmdev_ctx_t *ctx,
- lsm6dsrx_h_lactive_t val)
+ lsm6dsrx_h_lactive_t val)
{
lsm6dsrx_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
- if(ret == 0){
- ctrl3_c.h_lactive= (uint8_t)val;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl3_c.h_lactive = (uint8_t)val;
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
}
+
return ret;
}
@@ -4378,24 +5154,28 @@ int32_t lsm6dsrx_pin_polarity_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_pin_polarity_get(stmdev_ctx_t *ctx,
- lsm6dsrx_h_lactive_t *val)
+ lsm6dsrx_h_lactive_t *val)
{
lsm6dsrx_ctrl3_c_t ctrl3_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
- switch (ctrl3_c.h_lactive){
+ switch (ctrl3_c.h_lactive)
+ {
case LSM6DSRX_ACTIVE_HIGH:
*val = LSM6DSRX_ACTIVE_HIGH;
break;
+
case LSM6DSRX_ACTIVE_LOW:
*val = LSM6DSRX_ACTIVE_LOW;
break;
+
default:
*val = LSM6DSRX_ACTIVE_HIGH;
break;
}
+
return ret;
}
@@ -4412,11 +5192,14 @@ int32_t lsm6dsrx_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsrx_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ctrl4_c.int2_on_int1= (uint8_t)val;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl4_c.int2_on_int1 = (uint8_t)val;
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -4433,7 +5216,7 @@ int32_t lsm6dsrx_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsrx_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.int2_on_int1;
return ret;
@@ -4448,32 +5231,43 @@ int32_t lsm6dsrx_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsrx_int_notification_set(stmdev_ctx_t *ctx,
- lsm6dsrx_lir_t val)
+ lsm6dsrx_lir_t val)
{
lsm6dsrx_tap_cfg0_t tap_cfg0;
lsm6dsrx_page_rw_t page_rw;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
- if(ret == 0){
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
+
+ if (ret == 0)
+ {
tap_cfg0.lir = (uint8_t)val & 0x01U;
tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG0,
- (uint8_t*)&tap_cfg0, 1);
+ (uint8_t *)&tap_cfg0, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
}
- if(ret == 0){
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t*)&page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t*)&page_rw, 1);
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -4486,41 +5280,53 @@ int32_t lsm6dsrx_int_notification_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_int_notification_get(stmdev_ctx_t *ctx,
- lsm6dsrx_lir_t *val)
+ lsm6dsrx_lir_t *val)
{
lsm6dsrx_tap_cfg0_t tap_cfg0;
lsm6dsrx_page_rw_t page_rw;
int32_t ret;
*val = LSM6DSRX_ALL_INT_PULSED;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
}
- if(ret == 0){
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t*)&page_rw, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t *)&page_rw, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
- switch ((page_rw.emb_func_lir << 1) + tap_cfg0.lir){
+
+ switch ((page_rw.emb_func_lir << 1) + tap_cfg0.lir)
+ {
case LSM6DSRX_ALL_INT_PULSED:
*val = LSM6DSRX_ALL_INT_PULSED;
break;
+
case LSM6DSRX_BASE_LATCHED_EMB_PULSED:
*val = LSM6DSRX_BASE_LATCHED_EMB_PULSED;
break;
+
case LSM6DSRX_BASE_PULSED_EMB_LATCHED:
*val = LSM6DSRX_BASE_PULSED_EMB_LATCHED;
break;
+
case LSM6DSRX_ALL_INT_LATCHED:
*val = LSM6DSRX_ALL_INT_LATCHED;
break;
+
default:
*val = LSM6DSRX_ALL_INT_PULSED;
break;
}
+
return ret;
}
@@ -4548,18 +5354,21 @@ int32_t lsm6dsrx_int_notification_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_wkup_ths_weight_set(stmdev_ctx_t *ctx,
- lsm6dsrx_wake_ths_w_t val)
+ lsm6dsrx_wake_ths_w_t val)
{
lsm6dsrx_wake_up_dur_t wake_up_dur;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
- wake_up_dur.wake_ths_w= (uint8_t)val;
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ wake_up_dur.wake_ths_w = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -4574,25 +5383,29 @@ int32_t lsm6dsrx_wkup_ths_weight_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_wkup_ths_weight_get(stmdev_ctx_t *ctx,
- lsm6dsrx_wake_ths_w_t *val)
+ lsm6dsrx_wake_ths_w_t *val)
{
lsm6dsrx_wake_up_dur_t wake_up_dur;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
- switch (wake_up_dur.wake_ths_w){
+ switch (wake_up_dur.wake_ths_w)
+ {
case LSM6DSRX_LSb_FS_DIV_64:
*val = LSM6DSRX_LSb_FS_DIV_64;
break;
+
case LSM6DSRX_LSb_FS_DIV_256:
*val = LSM6DSRX_LSb_FS_DIV_256;
break;
+
default:
*val = LSM6DSRX_LSb_FS_DIV_64;
break;
}
+
return ret;
}
@@ -4611,12 +5424,15 @@ int32_t lsm6dsrx_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
- if(ret == 0){
- wake_up_ths.wk_ths= (uint8_t)val;
+ (uint8_t *)&wake_up_ths, 1);
+
+ if (ret == 0)
+ {
+ wake_up_ths.wk_ths = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
}
+
return ret;
}
@@ -4635,7 +5451,7 @@ int32_t lsm6dsrx_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
*val = wake_up_ths.wk_ths;
return ret;
@@ -4649,18 +5465,22 @@ int32_t lsm6dsrx_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dsrx_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dsrx_wake_up_ths_t wake_up_ths;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
- if(ret == 0){
- wake_up_ths.usr_off_on_wu= (uint8_t)val;
+ (uint8_t *)&wake_up_ths, 1);
+
+ if (ret == 0)
+ {
+ wake_up_ths.usr_off_on_wu = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
}
+
return ret;
}
@@ -4673,13 +5493,13 @@ int32_t lsm6dsrx_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, uint8_t val)
*
*/
int32_t lsm6dsrx_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
lsm6dsrx_wake_up_ths_t wake_up_ths;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
*val = wake_up_ths.usr_off_on_wu;
return ret;
@@ -4699,12 +5519,15 @@ int32_t lsm6dsrx_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
- wake_up_dur.wake_dur= (uint8_t)val;
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ wake_up_dur.wake_dur = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -4722,7 +5545,7 @@ int32_t lsm6dsrx_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
*val = wake_up_dur.wake_dur;
return ret;
@@ -4754,11 +5577,14 @@ int32_t lsm6dsrx_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsrx_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
- if(ret == 0){
- ctrl4_c.sleep_g= (uint8_t)val;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl4_c.sleep_g = (uint8_t)val;
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
}
+
return ret;
}
@@ -4775,7 +5601,7 @@ int32_t lsm6dsrx_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsrx_ctrl4_c_t ctrl4_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
*val = ctrl4_c.sleep_g;
return ret;
@@ -4792,17 +5618,20 @@ int32_t lsm6dsrx_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsrx_act_pin_notification_set(stmdev_ctx_t *ctx,
- lsm6dsrx_sleep_status_on_int_t val)
+ lsm6dsrx_sleep_status_on_int_t val)
{
lsm6dsrx_tap_cfg0_t tap_cfg0;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
- if(ret == 0){
- tap_cfg0. sleep_status_on_int= (uint8_t)val;
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
+
+ if (ret == 0)
+ {
+ tap_cfg0. sleep_status_on_int = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG0,
- (uint8_t*)&tap_cfg0, 1);
+ (uint8_t *)&tap_cfg0, 1);
}
+
return ret;
}
@@ -4817,23 +5646,28 @@ int32_t lsm6dsrx_act_pin_notification_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_act_pin_notification_get(stmdev_ctx_t *ctx,
- lsm6dsrx_sleep_status_on_int_t *val)
+ lsm6dsrx_sleep_status_on_int_t *val)
{
lsm6dsrx_tap_cfg0_t tap_cfg0;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
- switch (tap_cfg0. sleep_status_on_int){
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
+
+ switch (tap_cfg0. sleep_status_on_int)
+ {
case LSM6DSRX_DRIVE_SLEEP_CHG_EVENT:
*val = LSM6DSRX_DRIVE_SLEEP_CHG_EVENT;
break;
+
case LSM6DSRX_DRIVE_SLEEP_STATUS:
*val = LSM6DSRX_DRIVE_SLEEP_STATUS;
break;
+
default:
*val = LSM6DSRX_DRIVE_SLEEP_CHG_EVENT;
break;
}
+
return ret;
}
@@ -4845,16 +5679,20 @@ int32_t lsm6dsrx_act_pin_notification_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_act_mode_set(stmdev_ctx_t *ctx, lsm6dsrx_inact_en_t val)
+int32_t lsm6dsrx_act_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsrx_inact_en_t val)
{
lsm6dsrx_tap_cfg2_t tap_cfg2;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG2, (uint8_t*)&tap_cfg2, 1);
- if(ret == 0){
- tap_cfg2.inact_en= (uint8_t)val;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG2, (uint8_t*)&tap_cfg2, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
+
+ if (ret == 0)
+ {
+ tap_cfg2.inact_en = (uint8_t)val;
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
}
+
return ret;
}
@@ -4867,30 +5705,36 @@ int32_t lsm6dsrx_act_mode_set(stmdev_ctx_t *ctx, lsm6dsrx_inact_en_t val)
*
*/
int32_t lsm6dsrx_act_mode_get(stmdev_ctx_t *ctx,
- lsm6dsrx_inact_en_t *val)
+ lsm6dsrx_inact_en_t *val)
{
lsm6dsrx_tap_cfg2_t tap_cfg2;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG2, (uint8_t*)&tap_cfg2, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
- switch (tap_cfg2.inact_en){
+ switch (tap_cfg2.inact_en)
+ {
case LSM6DSRX_XL_AND_GY_NOT_AFFECTED:
*val = LSM6DSRX_XL_AND_GY_NOT_AFFECTED;
break;
+
case LSM6DSRX_XL_12Hz5_GY_NOT_AFFECTED:
*val = LSM6DSRX_XL_12Hz5_GY_NOT_AFFECTED;
break;
+
case LSM6DSRX_XL_12Hz5_GY_SLEEP:
*val = LSM6DSRX_XL_12Hz5_GY_SLEEP;
break;
+
case LSM6DSRX_XL_12Hz5_GY_PD:
*val = LSM6DSRX_XL_12Hz5_GY_PD;
break;
+
default:
*val = LSM6DSRX_XL_AND_GY_NOT_AFFECTED;
break;
}
+
return ret;
}
@@ -4908,12 +5752,15 @@ int32_t lsm6dsrx_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
- wake_up_dur.sleep_dur= (uint8_t)val;
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
+ wake_up_dur.sleep_dur = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
+
return ret;
}
@@ -4931,7 +5778,7 @@ int32_t lsm6dsrx_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
*val = wake_up_dur.sleep_dur;
return ret;
@@ -4958,17 +5805,21 @@ int32_t lsm6dsrx_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dsrx_tap_detection_on_z_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dsrx_tap_cfg0_t tap_cfg0;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
- if(ret == 0){
- tap_cfg0.tap_z_en= (uint8_t)val;
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
+
+ if (ret == 0)
+ {
+ tap_cfg0.tap_z_en = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG0,
- (uint8_t*)&tap_cfg0, 1);
+ (uint8_t *)&tap_cfg0, 1);
}
+
return ret;
}
@@ -4980,12 +5831,13 @@ int32_t lsm6dsrx_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsrx_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsrx_tap_cfg0_t tap_cfg0;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
*val = tap_cfg0.tap_z_en;
return ret;
@@ -4999,17 +5851,21 @@ int32_t lsm6dsrx_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dsrx_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dsrx_tap_cfg0_t tap_cfg0;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
- if(ret == 0){
- tap_cfg0.tap_y_en= (uint8_t)val;
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
+
+ if (ret == 0)
+ {
+ tap_cfg0.tap_y_en = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG0,
- (uint8_t*)&tap_cfg0, 1);
+ (uint8_t *)&tap_cfg0, 1);
}
+
return ret;
}
@@ -5021,12 +5877,13 @@ int32_t lsm6dsrx_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsrx_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsrx_tap_cfg0_t tap_cfg0;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
*val = tap_cfg0.tap_y_en;
return ret;
@@ -5040,17 +5897,21 @@ int32_t lsm6dsrx_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dsrx_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dsrx_tap_cfg0_t tap_cfg0;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
- if(ret == 0){
- tap_cfg0.tap_x_en= (uint8_t)val;
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
+
+ if (ret == 0)
+ {
+ tap_cfg0.tap_x_en = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG0,
- (uint8_t*)&tap_cfg0, 1);
+ (uint8_t *)&tap_cfg0, 1);
}
+
return ret;
}
@@ -5062,12 +5923,13 @@ int32_t lsm6dsrx_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsrx_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsrx_tap_cfg0_t tap_cfg0;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t*)&tap_cfg0, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
*val = tap_cfg0.tap_x_en;
return ret;
@@ -5086,12 +5948,15 @@ int32_t lsm6dsrx_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsrx_tap_cfg1_t tap_cfg1;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG1, (uint8_t*)&tap_cfg1, 1);
- if(ret == 0){
- tap_cfg1.tap_ths_x= (uint8_t)val;
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
+
+ if (ret == 0)
+ {
+ tap_cfg1.tap_ths_x = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG1,
- (uint8_t*)&tap_cfg1, 1);
+ (uint8_t *)&tap_cfg1, 1);
}
+
return ret;
}
@@ -5108,7 +5973,7 @@ int32_t lsm6dsrx_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsrx_tap_cfg1_t tap_cfg1;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG1, (uint8_t*)&tap_cfg1, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
*val = tap_cfg1.tap_ths_x;
return ret;
@@ -5123,16 +5988,19 @@ int32_t lsm6dsrx_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsrx_tap_axis_priority_set(stmdev_ctx_t *ctx,
- lsm6dsrx_tap_priority_t val)
+ lsm6dsrx_tap_priority_t val)
{
lsm6dsrx_tap_cfg1_t tap_cfg1;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG1, (uint8_t*)&tap_cfg1, 1);
- if(ret == 0){
- tap_cfg1.tap_priority= (uint8_t)val;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG1, (uint8_t*)&tap_cfg1, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
+
+ if (ret == 0)
+ {
+ tap_cfg1.tap_priority = (uint8_t)val;
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
}
+
return ret;
}
@@ -5145,36 +6013,44 @@ int32_t lsm6dsrx_tap_axis_priority_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_tap_axis_priority_get(stmdev_ctx_t *ctx,
- lsm6dsrx_tap_priority_t *val)
+ lsm6dsrx_tap_priority_t *val)
{
lsm6dsrx_tap_cfg1_t tap_cfg1;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG1, (uint8_t*)&tap_cfg1, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
- switch (tap_cfg1.tap_priority){
+ switch (tap_cfg1.tap_priority)
+ {
case LSM6DSRX_XYZ:
*val = LSM6DSRX_XYZ;
break;
+
case LSM6DSRX_YXZ:
*val = LSM6DSRX_YXZ;
break;
+
case LSM6DSRX_XZY:
*val = LSM6DSRX_XZY;
break;
+
case LSM6DSRX_ZYX:
*val = LSM6DSRX_ZYX;
break;
+
case LSM6DSRX_YZX:
*val = LSM6DSRX_YZX;
break;
+
case LSM6DSRX_ZXY:
*val = LSM6DSRX_ZXY;
break;
+
default:
*val = LSM6DSRX_XYZ;
break;
}
+
return ret;
}
@@ -5191,12 +6067,15 @@ int32_t lsm6dsrx_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsrx_tap_cfg2_t tap_cfg2;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG2, (uint8_t*)&tap_cfg2, 1);
- if(ret == 0){
- tap_cfg2.tap_ths_y= (uint8_t)val;
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
+
+ if (ret == 0)
+ {
+ tap_cfg2.tap_ths_y = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG2,
- (uint8_t*)&tap_cfg2, 1);
+ (uint8_t *)&tap_cfg2, 1);
}
+
return ret;
}
@@ -5213,7 +6092,7 @@ int32_t lsm6dsrx_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsrx_tap_cfg2_t tap_cfg2;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG2, (uint8_t*)&tap_cfg2, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
*val = tap_cfg2.tap_ths_y;
return ret;
@@ -5233,12 +6112,15 @@ int32_t lsm6dsrx_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
- if(ret == 0){
- tap_ths_6d.tap_ths_z= (uint8_t)val;
+ (uint8_t *)&tap_ths_6d, 1);
+
+ if (ret == 0)
+ {
+ tap_ths_6d.tap_ths_z = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
+ (uint8_t *)&tap_ths_6d, 1);
}
+
return ret;
}
@@ -5256,7 +6138,7 @@ int32_t lsm6dsrx_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
+ (uint8_t *)&tap_ths_6d, 1);
*val = tap_ths_6d.tap_ths_z;
return ret;
@@ -5279,12 +6161,15 @@ int32_t lsm6dsrx_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsrx_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_DUR2, (uint8_t*)&int_dur2, 1);
- if(ret == 0){
- int_dur2.shock= (uint8_t)val;
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_DUR2, (uint8_t *)&int_dur2, 1);
+
+ if (ret == 0)
+ {
+ int_dur2.shock = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INT_DUR2,
- (uint8_t*)&int_dur2, 1);
+ (uint8_t *)&int_dur2, 1);
}
+
return ret;
}
@@ -5305,7 +6190,7 @@ int32_t lsm6dsrx_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsrx_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_DUR2, (uint8_t *)&int_dur2, 1);
*val = int_dur2.shock;
return ret;
@@ -5328,12 +6213,15 @@ int32_t lsm6dsrx_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsrx_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_DUR2, (uint8_t*)&int_dur2, 1);
- if(ret == 0){
- int_dur2.quiet= (uint8_t)val;
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_DUR2, (uint8_t *)&int_dur2, 1);
+
+ if (ret == 0)
+ {
+ int_dur2.quiet = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INT_DUR2,
- (uint8_t*)&int_dur2, 1);
+ (uint8_t *)&int_dur2, 1);
}
+
return ret;
}
@@ -5354,7 +6242,7 @@ int32_t lsm6dsrx_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsrx_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_DUR2, (uint8_t *)&int_dur2, 1);
*val = int_dur2.quiet;
return ret;
@@ -5379,12 +6267,15 @@ int32_t lsm6dsrx_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsrx_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_DUR2, (uint8_t*)&int_dur2, 1);
- if(ret == 0){
- int_dur2.dur= (uint8_t)val;
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_DUR2, (uint8_t *)&int_dur2, 1);
+
+ if (ret == 0)
+ {
+ int_dur2.dur = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INT_DUR2,
- (uint8_t*)&int_dur2, 1);
+ (uint8_t *)&int_dur2, 1);
}
+
return ret;
}
@@ -5405,7 +6296,7 @@ int32_t lsm6dsrx_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsrx_int_dur2_t int_dur2;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_DUR2, (uint8_t*)&int_dur2, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_DUR2, (uint8_t *)&int_dur2, 1);
*val = int_dur2.dur;
return ret;
@@ -5420,18 +6311,21 @@ int32_t lsm6dsrx_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsrx_tap_mode_set(stmdev_ctx_t *ctx,
- lsm6dsrx_single_double_tap_t val)
+ lsm6dsrx_single_double_tap_t val)
{
lsm6dsrx_wake_up_ths_t wake_up_ths;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
- if(ret == 0){
- wake_up_ths.single_double_tap= (uint8_t)val;
+ (uint8_t *)&wake_up_ths, 1);
+
+ if (ret == 0)
+ {
+ wake_up_ths.single_double_tap = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
}
+
return ret;
}
@@ -5444,25 +6338,29 @@ int32_t lsm6dsrx_tap_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_tap_mode_get(stmdev_ctx_t *ctx,
- lsm6dsrx_single_double_tap_t *val)
+ lsm6dsrx_single_double_tap_t *val)
{
lsm6dsrx_wake_up_ths_t wake_up_ths;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_THS,
- (uint8_t*)&wake_up_ths, 1);
+ (uint8_t *)&wake_up_ths, 1);
- switch (wake_up_ths.single_double_tap){
+ switch (wake_up_ths.single_double_tap)
+ {
case LSM6DSRX_ONLY_SINGLE:
*val = LSM6DSRX_ONLY_SINGLE;
break;
+
case LSM6DSRX_BOTH_SINGLE_DOUBLE:
*val = LSM6DSRX_BOTH_SINGLE_DOUBLE;
break;
+
default:
*val = LSM6DSRX_ONLY_SINGLE;
break;
}
+
return ret;
}
@@ -5488,18 +6386,21 @@ int32_t lsm6dsrx_tap_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_6d_threshold_set(stmdev_ctx_t *ctx,
- lsm6dsrx_sixd_ths_t val)
+ lsm6dsrx_sixd_ths_t val)
{
lsm6dsrx_tap_ths_6d_t tap_ths_6d;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
- if(ret == 0){
- tap_ths_6d.sixd_ths= (uint8_t)val;
+ (uint8_t *)&tap_ths_6d, 1);
+
+ if (ret == 0)
+ {
+ tap_ths_6d.sixd_ths = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
+ (uint8_t *)&tap_ths_6d, 1);
}
+
return ret;
}
@@ -5512,31 +6413,37 @@ int32_t lsm6dsrx_6d_threshold_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_6d_threshold_get(stmdev_ctx_t *ctx,
- lsm6dsrx_sixd_ths_t *val)
+ lsm6dsrx_sixd_ths_t *val)
{
lsm6dsrx_tap_ths_6d_t tap_ths_6d;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
+ (uint8_t *)&tap_ths_6d, 1);
- switch (tap_ths_6d.sixd_ths){
+ switch (tap_ths_6d.sixd_ths)
+ {
case LSM6DSRX_DEG_80:
*val = LSM6DSRX_DEG_80;
break;
+
case LSM6DSRX_DEG_70:
*val = LSM6DSRX_DEG_70;
break;
+
case LSM6DSRX_DEG_60:
*val = LSM6DSRX_DEG_60;
break;
+
case LSM6DSRX_DEG_50:
*val = LSM6DSRX_DEG_50;
break;
+
default:
*val = LSM6DSRX_DEG_80;
break;
}
+
return ret;
}
@@ -5554,12 +6461,15 @@ int32_t lsm6dsrx_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
- if(ret == 0){
- tap_ths_6d.d4d_en= (uint8_t)val;
+ (uint8_t *)&tap_ths_6d, 1);
+
+ if (ret == 0)
+ {
+ tap_ths_6d.d4d_en = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
+ (uint8_t *)&tap_ths_6d, 1);
}
+
return ret;
}
@@ -5577,7 +6487,7 @@ int32_t lsm6dsrx_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_THS_6D,
- (uint8_t*)&tap_ths_6d, 1);
+ (uint8_t *)&tap_ths_6d, 1);
*val = tap_ths_6d.d4d_en;
return ret;
@@ -5605,17 +6515,21 @@ int32_t lsm6dsrx_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsrx_ff_threshold_set(stmdev_ctx_t *ctx,
- lsm6dsrx_ff_ths_t val)
+ lsm6dsrx_ff_ths_t val)
{
lsm6dsrx_free_fall_t free_fall;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FREE_FALL, (uint8_t*)&free_fall, 1);
- if(ret == 0){
- free_fall.ff_ths= (uint8_t)val;
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FREE_FALL,
+ (uint8_t *)&free_fall, 1);
+
+ if (ret == 0)
+ {
+ free_fall.ff_ths = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FREE_FALL,
- (uint8_t*)&free_fall, 1);
+ (uint8_t *)&free_fall, 1);
}
+
return ret;
}
@@ -5628,42 +6542,53 @@ int32_t lsm6dsrx_ff_threshold_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_ff_threshold_get(stmdev_ctx_t *ctx,
- lsm6dsrx_ff_ths_t *val)
+ lsm6dsrx_ff_ths_t *val)
{
lsm6dsrx_free_fall_t free_fall;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FREE_FALL, (uint8_t*)&free_fall, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FREE_FALL,
+ (uint8_t *)&free_fall, 1);
- switch (free_fall.ff_ths){
+ switch (free_fall.ff_ths)
+ {
case LSM6DSRX_FF_TSH_156mg:
*val = LSM6DSRX_FF_TSH_156mg;
break;
+
case LSM6DSRX_FF_TSH_219mg:
*val = LSM6DSRX_FF_TSH_219mg;
break;
+
case LSM6DSRX_FF_TSH_250mg:
*val = LSM6DSRX_FF_TSH_250mg;
break;
+
case LSM6DSRX_FF_TSH_312mg:
*val = LSM6DSRX_FF_TSH_312mg;
break;
+
case LSM6DSRX_FF_TSH_344mg:
*val = LSM6DSRX_FF_TSH_344mg;
break;
+
case LSM6DSRX_FF_TSH_406mg:
*val = LSM6DSRX_FF_TSH_406mg;
break;
+
case LSM6DSRX_FF_TSH_469mg:
*val = LSM6DSRX_FF_TSH_469mg;
break;
+
case LSM6DSRX_FF_TSH_500mg:
*val = LSM6DSRX_FF_TSH_500mg;
break;
+
default:
*val = LSM6DSRX_FF_TSH_156mg;
break;
}
+
return ret;
}
@@ -5682,21 +6607,28 @@ int32_t lsm6dsrx_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
- if(ret == 0){
+ (uint8_t *)&wake_up_dur, 1);
+
+ if (ret == 0)
+ {
wake_up_dur.ff_dur = (val & 0x20U) >> 5;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FREE_FALL,
- (uint8_t*)&free_fall, 1);
+ (uint8_t *)&free_fall, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
free_fall.ff_dur = val & 0x1FU;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FREE_FALL,
- (uint8_t*)&free_fall, 1);
+ (uint8_t *)&free_fall, 1);
}
+
return ret;
}
@@ -5715,12 +6647,14 @@ int32_t lsm6dsrx_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
- (uint8_t*)&wake_up_dur, 1);
+ (uint8_t *)&wake_up_dur, 1);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FREE_FALL,
- (uint8_t*)&free_fall, 1);
+ (uint8_t *)&free_fall, 1);
}
+
*val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
return ret;
@@ -5754,16 +6688,20 @@ int32_t lsm6dsrx_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl2.wtm = (uint8_t)((val / 256U) & 0x01U);
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
fifo_ctrl1.wtm = (uint8_t)(val - (fifo_ctrl2.wtm * 256U));
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL1,
- (uint8_t*)&fifo_ctrl1, 1);
+ (uint8_t *)&fifo_ctrl1, 1);
}
return ret;
@@ -5784,13 +6722,17 @@ int32_t lsm6dsrx_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL1,
- (uint8_t*)&fifo_ctrl1, 1);
+ (uint8_t *)&fifo_ctrl1, 1);
}
+
*val = fifo_ctrl2.wtm;
*val = (*val * 256U) + fifo_ctrl1.wtm;
+
return ret;
}
@@ -5802,24 +6744,32 @@ int32_t lsm6dsrx_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_compression_algo_init_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm6dsrx_compression_algo_init_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm6dsrx_emb_func_init_b_t emb_func_init_b;
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_INIT_B,
- (uint8_t*)&emb_func_init_b, 1);
+ (uint8_t *)&emb_func_init_b, 1);
}
- if(ret == 0){
- emb_func_init_b.fifo_compr_init= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ emb_func_init_b.fifo_compr_init = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_INIT_B,
- (uint8_t*)&emb_func_init_b, 1);
+ (uint8_t *)&emb_func_init_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -5833,20 +6783,25 @@ int32_t lsm6dsrx_compression_algo_init_set(stmdev_ctx_t *ctx, uint8_t val)
*
*/
int32_t lsm6dsrx_compression_algo_init_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
lsm6dsrx_emb_func_init_b_t emb_func_init_b;
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_INIT_B,
- (uint8_t*)&emb_func_init_b, 1);
+ (uint8_t *)&emb_func_init_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = emb_func_init_b.fifo_compr_init;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -5859,7 +6814,7 @@ int32_t lsm6dsrx_compression_algo_init_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_compression_algo_set(stmdev_ctx_t *ctx,
- lsm6dsrx_uncoptr_rate_t val)
+ lsm6dsrx_uncoptr_rate_t val)
{
lsm6dsrx_fifo_ctrl2_t fifo_ctrl2;
lsm6dsrx_emb_func_en_b_t emb_func_en_b;
@@ -5867,30 +6822,42 @@ int32_t lsm6dsrx_compression_algo_set(stmdev_ctx_t *ctx,
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
emb_func_en_b.fifo_compr_en = ((uint8_t)val & 0x04U) >> 2;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
fifo_ctrl2.fifo_compr_rt_en = ((uint8_t)val & 0x04U) >> 2;
fifo_ctrl2.uncoptr_rate = (uint8_t)val & 0x03U;
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
+
return ret;
}
@@ -5903,34 +6870,42 @@ int32_t lsm6dsrx_compression_algo_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_compression_algo_get(stmdev_ctx_t *ctx,
- lsm6dsrx_uncoptr_rate_t *val)
+ lsm6dsrx_uncoptr_rate_t *val)
{
lsm6dsrx_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
- switch (( fifo_ctrl2.fifo_compr_rt_en << 2) + fifo_ctrl2.uncoptr_rate ){
+ switch ((fifo_ctrl2.fifo_compr_rt_en << 2) +
+ fifo_ctrl2.uncoptr_rate)
+ {
case LSM6DSRX_CMP_DISABLE:
*val = LSM6DSRX_CMP_DISABLE;
break;
+
case LSM6DSRX_CMP_ALWAYS:
*val = LSM6DSRX_CMP_ALWAYS;
break;
+
case LSM6DSRX_CMP_8_TO_1:
*val = LSM6DSRX_CMP_8_TO_1;
break;
+
case LSM6DSRX_CMP_16_TO_1:
*val = LSM6DSRX_CMP_16_TO_1;
break;
+
case LSM6DSRX_CMP_32_TO_1:
*val = LSM6DSRX_CMP_32_TO_1;
break;
+
default:
*val = LSM6DSRX_CMP_DISABLE;
break;
}
+
return ret;
}
@@ -5943,17 +6918,19 @@ int32_t lsm6dsrx_compression_algo_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
- uint8_t val)
+ uint8_t val)
{
lsm6dsrx_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
- fifo_ctrl2.odrchg_en= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl2.odrchg_en = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
return ret;
@@ -5968,13 +6945,13 @@ int32_t lsm6dsrx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
lsm6dsrx_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
*val = fifo_ctrl2.odrchg_en;
return ret;
@@ -5989,18 +6966,21 @@ int32_t lsm6dsrx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_compression_algo_real_time_set(stmdev_ctx_t *ctx,
- uint8_t val)
+ uint8_t val)
{
lsm6dsrx_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
- fifo_ctrl2.fifo_compr_rt_en= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl2.fifo_compr_rt_en = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
+
return ret;
}
@@ -6013,13 +6993,13 @@ int32_t lsm6dsrx_compression_algo_real_time_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_compression_algo_real_time_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
lsm6dsrx_fifo_ctrl2_t fifo_ctrl2;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
*val = fifo_ctrl2.fifo_compr_rt_en;
return ret;
@@ -6040,12 +7020,15 @@ int32_t lsm6dsrx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
- if(ret == 0){
- fifo_ctrl2.stop_on_wtm= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl2, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl2.stop_on_wtm = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
}
+
return ret;
}
@@ -6064,7 +7047,7 @@ int32_t lsm6dsrx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2,
- (uint8_t*)&fifo_ctrl2, 1);
+ (uint8_t *)&fifo_ctrl2, 1);
*val = fifo_ctrl2.stop_on_wtm;
return ret;
@@ -6080,18 +7063,21 @@ int32_t lsm6dsrx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsrx_fifo_xl_batch_set(stmdev_ctx_t *ctx,
- lsm6dsrx_bdr_xl_t val)
+ lsm6dsrx_bdr_xl_t val)
{
lsm6dsrx_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
- if(ret == 0){
- fifo_ctrl3.bdr_xl= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl3, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl3.bdr_xl = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
+ (uint8_t *)&fifo_ctrl3, 1);
}
+
return ret;
}
@@ -6105,55 +7091,69 @@ int32_t lsm6dsrx_fifo_xl_batch_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_fifo_xl_batch_get(stmdev_ctx_t *ctx,
- lsm6dsrx_bdr_xl_t *val)
+ lsm6dsrx_bdr_xl_t *val)
{
lsm6dsrx_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
+ (uint8_t *)&fifo_ctrl3, 1);
- switch (fifo_ctrl3.bdr_xl){
+ switch (fifo_ctrl3.bdr_xl)
+ {
case LSM6DSRX_XL_NOT_BATCHED:
*val = LSM6DSRX_XL_NOT_BATCHED;
break;
+
case LSM6DSRX_XL_BATCHED_AT_12Hz5:
*val = LSM6DSRX_XL_BATCHED_AT_12Hz5;
break;
+
case LSM6DSRX_XL_BATCHED_AT_26Hz:
*val = LSM6DSRX_XL_BATCHED_AT_26Hz;
break;
+
case LSM6DSRX_XL_BATCHED_AT_52Hz:
*val = LSM6DSRX_XL_BATCHED_AT_52Hz;
break;
+
case LSM6DSRX_XL_BATCHED_AT_104Hz:
*val = LSM6DSRX_XL_BATCHED_AT_104Hz;
break;
+
case LSM6DSRX_XL_BATCHED_AT_208Hz:
*val = LSM6DSRX_XL_BATCHED_AT_208Hz;
break;
+
case LSM6DSRX_XL_BATCHED_AT_417Hz:
*val = LSM6DSRX_XL_BATCHED_AT_417Hz;
break;
+
case LSM6DSRX_XL_BATCHED_AT_833Hz:
*val = LSM6DSRX_XL_BATCHED_AT_833Hz;
break;
+
case LSM6DSRX_XL_BATCHED_AT_1667Hz:
*val = LSM6DSRX_XL_BATCHED_AT_1667Hz;
break;
+
case LSM6DSRX_XL_BATCHED_AT_3333Hz:
*val = LSM6DSRX_XL_BATCHED_AT_3333Hz;
break;
+
case LSM6DSRX_XL_BATCHED_AT_6667Hz:
*val = LSM6DSRX_XL_BATCHED_AT_6667Hz;
break;
+
case LSM6DSRX_XL_BATCHED_AT_6Hz5:
*val = LSM6DSRX_XL_BATCHED_AT_6Hz5;
break;
+
default:
*val = LSM6DSRX_XL_NOT_BATCHED;
break;
}
+
return ret;
}
@@ -6167,18 +7167,21 @@ int32_t lsm6dsrx_fifo_xl_batch_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_fifo_gy_batch_set(stmdev_ctx_t *ctx,
- lsm6dsrx_bdr_gy_t val)
+ lsm6dsrx_bdr_gy_t val)
{
lsm6dsrx_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
- if(ret == 0){
- fifo_ctrl3.bdr_gy= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl3, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl3.bdr_gy = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
+ (uint8_t *)&fifo_ctrl3, 1);
}
+
return ret;
}
@@ -6192,55 +7195,69 @@ int32_t lsm6dsrx_fifo_gy_batch_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_fifo_gy_batch_get(stmdev_ctx_t *ctx,
- lsm6dsrx_bdr_gy_t *val)
+ lsm6dsrx_bdr_gy_t *val)
{
lsm6dsrx_fifo_ctrl3_t fifo_ctrl3;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL3,
- (uint8_t*)&fifo_ctrl3, 1);
+ (uint8_t *)&fifo_ctrl3, 1);
- switch (fifo_ctrl3.bdr_gy){
+ switch (fifo_ctrl3.bdr_gy)
+ {
case LSM6DSRX_GY_NOT_BATCHED:
*val = LSM6DSRX_GY_NOT_BATCHED;
break;
+
case LSM6DSRX_GY_BATCHED_AT_12Hz5:
*val = LSM6DSRX_GY_BATCHED_AT_12Hz5;
break;
+
case LSM6DSRX_GY_BATCHED_AT_26Hz:
*val = LSM6DSRX_GY_BATCHED_AT_26Hz;
break;
+
case LSM6DSRX_GY_BATCHED_AT_52Hz:
*val = LSM6DSRX_GY_BATCHED_AT_52Hz;
break;
+
case LSM6DSRX_GY_BATCHED_AT_104Hz:
*val = LSM6DSRX_GY_BATCHED_AT_104Hz;
break;
+
case LSM6DSRX_GY_BATCHED_AT_208Hz:
*val = LSM6DSRX_GY_BATCHED_AT_208Hz;
break;
+
case LSM6DSRX_GY_BATCHED_AT_417Hz:
*val = LSM6DSRX_GY_BATCHED_AT_417Hz;
break;
+
case LSM6DSRX_GY_BATCHED_AT_833Hz:
*val = LSM6DSRX_GY_BATCHED_AT_833Hz;
break;
+
case LSM6DSRX_GY_BATCHED_AT_1667Hz:
*val = LSM6DSRX_GY_BATCHED_AT_1667Hz;
break;
+
case LSM6DSRX_GY_BATCHED_AT_3333Hz:
*val = LSM6DSRX_GY_BATCHED_AT_3333Hz;
break;
+
case LSM6DSRX_GY_BATCHED_AT_6667Hz:
*val = LSM6DSRX_GY_BATCHED_AT_6667Hz;
break;
+
case LSM6DSRX_GY_BATCHED_6Hz5:
*val = LSM6DSRX_GY_BATCHED_6Hz5;
break;
+
default:
*val = LSM6DSRX_GY_NOT_BATCHED;
break;
}
+
return ret;
}
@@ -6253,18 +7270,21 @@ int32_t lsm6dsrx_fifo_gy_batch_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_fifo_mode_set(stmdev_ctx_t *ctx,
- lsm6dsrx_fifo_mode_t val)
+ lsm6dsrx_fifo_mode_t val)
{
lsm6dsrx_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
- fifo_ctrl4.fifo_mode= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl4.fifo_mode = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -6277,37 +7297,45 @@ int32_t lsm6dsrx_fifo_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_fifo_mode_get(stmdev_ctx_t *ctx,
- lsm6dsrx_fifo_mode_t *val)
+ lsm6dsrx_fifo_mode_t *val)
{
lsm6dsrx_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
- switch (fifo_ctrl4.fifo_mode){
+ switch (fifo_ctrl4.fifo_mode)
+ {
case LSM6DSRX_BYPASS_MODE:
*val = LSM6DSRX_BYPASS_MODE;
break;
+
case LSM6DSRX_FIFO_MODE:
*val = LSM6DSRX_FIFO_MODE;
break;
+
case LSM6DSRX_STREAM_TO_FIFO_MODE:
*val = LSM6DSRX_STREAM_TO_FIFO_MODE;
break;
+
case LSM6DSRX_BYPASS_TO_STREAM_MODE:
*val = LSM6DSRX_BYPASS_TO_STREAM_MODE;
break;
+
case LSM6DSRX_STREAM_MODE:
*val = LSM6DSRX_STREAM_MODE;
break;
+
case LSM6DSRX_BYPASS_TO_FIFO_MODE:
*val = LSM6DSRX_BYPASS_TO_FIFO_MODE;
break;
+
default:
*val = LSM6DSRX_BYPASS_MODE;
break;
}
+
return ret;
}
@@ -6321,18 +7349,21 @@ int32_t lsm6dsrx_fifo_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_fifo_temp_batch_set(stmdev_ctx_t *ctx,
- lsm6dsrx_odr_t_batch_t val)
+ lsm6dsrx_odr_t_batch_t val)
{
lsm6dsrx_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
- fifo_ctrl4.odr_t_batch= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl4.odr_t_batch = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -6346,31 +7377,37 @@ int32_t lsm6dsrx_fifo_temp_batch_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_fifo_temp_batch_get(stmdev_ctx_t *ctx,
- lsm6dsrx_odr_t_batch_t *val)
+ lsm6dsrx_odr_t_batch_t *val)
{
lsm6dsrx_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
- switch (fifo_ctrl4.odr_t_batch){
+ switch (fifo_ctrl4.odr_t_batch)
+ {
case LSM6DSRX_TEMP_NOT_BATCHED:
*val = LSM6DSRX_TEMP_NOT_BATCHED;
break;
+
case LSM6DSRX_TEMP_BATCHED_AT_52Hz:
*val = LSM6DSRX_TEMP_BATCHED_AT_52Hz;
break;
+
case LSM6DSRX_TEMP_BATCHED_AT_12Hz5:
*val = LSM6DSRX_TEMP_BATCHED_AT_12Hz5;
break;
+
case LSM6DSRX_TEMP_BATCHED_AT_1Hz6:
*val = LSM6DSRX_TEMP_BATCHED_AT_1Hz6;
break;
+
default:
*val = LSM6DSRX_TEMP_NOT_BATCHED;
break;
}
+
return ret;
}
@@ -6385,18 +7422,21 @@ int32_t lsm6dsrx_fifo_temp_batch_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
- lsm6dsrx_odr_ts_batch_t val)
+ lsm6dsrx_odr_ts_batch_t val)
{
lsm6dsrx_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
- if(ret == 0){
- fifo_ctrl4.odr_ts_batch= (uint8_t)val;
+ (uint8_t *)&fifo_ctrl4, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl4.odr_ts_batch = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
}
+
return ret;
}
@@ -6412,31 +7452,37 @@ int32_t lsm6dsrx_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
- lsm6dsrx_odr_ts_batch_t *val)
+ lsm6dsrx_odr_ts_batch_t *val)
{
lsm6dsrx_fifo_ctrl4_t fifo_ctrl4;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL4,
- (uint8_t*)&fifo_ctrl4, 1);
+ (uint8_t *)&fifo_ctrl4, 1);
- switch (fifo_ctrl4.odr_ts_batch){
+ switch (fifo_ctrl4.odr_ts_batch)
+ {
case LSM6DSRX_NO_DECIMATION:
*val = LSM6DSRX_NO_DECIMATION;
break;
+
case LSM6DSRX_DEC_1:
*val = LSM6DSRX_DEC_1;
break;
+
case LSM6DSRX_DEC_8:
*val = LSM6DSRX_DEC_8;
break;
+
case LSM6DSRX_DEC_32:
*val = LSM6DSRX_DEC_32;
break;
+
default:
*val = LSM6DSRX_NO_DECIMATION;
break;
}
+
return ret;
}
@@ -6451,18 +7497,21 @@ int32_t lsm6dsrx_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
- lsm6dsrx_trig_counter_bdr_t val)
+ lsm6dsrx_trig_counter_bdr_t val)
{
lsm6dsrx_counter_bdr_reg1_t counter_bdr_reg1;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if(ret == 0){
- counter_bdr_reg1.trig_counter_bdr= (uint8_t)val;
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
+ counter_bdr_reg1.trig_counter_bdr = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
}
+
return ret;
}
@@ -6477,25 +7526,29 @@ int32_t lsm6dsrx_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
- lsm6dsrx_trig_counter_bdr_t *val)
+ lsm6dsrx_trig_counter_bdr_t *val)
{
lsm6dsrx_counter_bdr_reg1_t counter_bdr_reg1;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
- switch (counter_bdr_reg1.trig_counter_bdr){
+ switch (counter_bdr_reg1.trig_counter_bdr)
+ {
case LSM6DSRX_XL_BATCH_EVENT:
*val = LSM6DSRX_XL_BATCH_EVENT;
break;
+
case LSM6DSRX_GYRO_BATCH_EVENT:
*val = LSM6DSRX_GYRO_BATCH_EVENT;
break;
+
default:
*val = LSM6DSRX_XL_BATCH_EVENT;
break;
}
+
return ret;
}
@@ -6514,12 +7567,15 @@ int32_t lsm6dsrx_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if(ret == 0){
- counter_bdr_reg1.rst_counter_bdr= (uint8_t)val;
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
+ counter_bdr_reg1.rst_counter_bdr = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
}
+
return ret;
}
@@ -6532,13 +7588,14 @@ int32_t lsm6dsrx_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsrx_rst_batch_counter_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsrx_counter_bdr_reg1_t counter_bdr_reg1;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
*val = counter_bdr_reg1.rst_counter_bdr;
return ret;
@@ -6553,24 +7610,31 @@ int32_t lsm6dsrx_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_batch_counter_threshold_set(stmdev_ctx_t *ctx, uint16_t val)
+int32_t lsm6dsrx_batch_counter_threshold_set(stmdev_ctx_t *ctx,
+ uint16_t val)
{
lsm6dsrx_counter_bdr_reg2_t counter_bdr_reg1;
lsm6dsrx_counter_bdr_reg2_t counter_bdr_reg2;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if (ret == 0){
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
counter_bdr_reg1.cnt_bdr_th = (uint8_t)((val / 256U) & 0x07U);
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
+ (uint8_t *)&counter_bdr_reg1, 1);
}
- if (ret == 0){
- counter_bdr_reg2.cnt_bdr_th = (uint8_t)(val - (counter_bdr_reg1.cnt_bdr_th * 256U));
+
+ if (ret == 0)
+ {
+ counter_bdr_reg2.cnt_bdr_th = (uint8_t)(val -
+ (counter_bdr_reg1.cnt_bdr_th * 256U));
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_COUNTER_BDR_REG2,
- (uint8_t*)&counter_bdr_reg2, 1);
+ (uint8_t *)&counter_bdr_reg2, 1);
}
+
return ret;
}
@@ -6584,21 +7648,24 @@ int32_t lsm6dsrx_batch_counter_threshold_set(stmdev_ctx_t *ctx, uint16_t val)
*
*/
int32_t lsm6dsrx_batch_counter_threshold_get(stmdev_ctx_t *ctx,
- uint16_t *val)
+ uint16_t *val)
{
lsm6dsrx_counter_bdr_reg1_t counter_bdr_reg1;
lsm6dsrx_counter_bdr_reg2_t counter_bdr_reg2;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
- (uint8_t*)&counter_bdr_reg1, 1);
- if (ret == 0){
+ (uint8_t *)&counter_bdr_reg1, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG2,
- (uint8_t*)&counter_bdr_reg2, 1);
+ (uint8_t *)&counter_bdr_reg2, 1);
}
*val = counter_bdr_reg1.cnt_bdr_th;
*val = (*val * 256U) + counter_bdr_reg2.cnt_bdr_th;
+
return ret;
}
@@ -6617,14 +7684,16 @@ int32_t lsm6dsrx_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_STATUS1,
- (uint8_t*)&fifo_status1, 1);
- if (ret == 0){
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
+ (uint8_t *)&fifo_status1, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_STATUS2,
+ (uint8_t *)&fifo_status2, 1);
*val = fifo_status2.diff_fifo;
*val = (*val * 256U) + fifo_status1.diff_fifo;
}
+
return ret;
}
@@ -6637,10 +7706,12 @@ int32_t lsm6dsrx_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
*
*/
int32_t lsm6dsrx_fifo_status_get(stmdev_ctx_t *ctx,
- lsm6dsrx_fifo_status2_t *val)
+ lsm6dsrx_fifo_status2_t *val)
{
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_STATUS2, (uint8_t*)val, 1);
+
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_STATUS2, (uint8_t *)val, 1);
+
return ret;
}
@@ -6658,7 +7729,7 @@ int32_t lsm6dsrx_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
+ (uint8_t *)&fifo_status2, 1);
*val = fifo_status2.fifo_full_ia;
return ret;
@@ -6679,7 +7750,7 @@ int32_t lsm6dsrx_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
+ (uint8_t *)&fifo_status2, 1);
*val = fifo_status2. fifo_ovr_ia;
return ret;
@@ -6699,7 +7770,7 @@ int32_t lsm6dsrx_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_STATUS2,
- (uint8_t*)&fifo_status2, 1);
+ (uint8_t *)&fifo_status2, 1);
*val = fifo_status2.fifo_wtm_ia;
return ret;
@@ -6714,85 +7785,109 @@ int32_t lsm6dsrx_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsrx_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
- lsm6dsrx_fifo_tag_t *val)
+ lsm6dsrx_fifo_tag_t *val)
{
lsm6dsrx_fifo_data_out_tag_t fifo_data_out_tag;
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_DATA_OUT_TAG,
- (uint8_t*)&fifo_data_out_tag, 1);
+ (uint8_t *)&fifo_data_out_tag, 1);
- switch (fifo_data_out_tag.tag_sensor){
+ switch (fifo_data_out_tag.tag_sensor)
+ {
case LSM6DSRX_GYRO_NC_TAG:
*val = LSM6DSRX_GYRO_NC_TAG;
break;
+
case LSM6DSRX_XL_NC_TAG:
*val = LSM6DSRX_XL_NC_TAG;
break;
+
case LSM6DSRX_TEMPERATURE_TAG:
*val = LSM6DSRX_TEMPERATURE_TAG;
break;
+
case LSM6DSRX_TIMESTAMP_TAG:
*val = LSM6DSRX_TIMESTAMP_TAG;
break;
+
case LSM6DSRX_CFG_CHANGE_TAG:
*val = LSM6DSRX_CFG_CHANGE_TAG;
break;
+
case LSM6DSRX_XL_NC_T_2_TAG:
*val = LSM6DSRX_XL_NC_T_2_TAG;
break;
+
case LSM6DSRX_XL_NC_T_1_TAG:
*val = LSM6DSRX_XL_NC_T_1_TAG;
break;
+
case LSM6DSRX_XL_2XC_TAG:
*val = LSM6DSRX_XL_2XC_TAG;
break;
+
case LSM6DSRX_XL_3XC_TAG:
*val = LSM6DSRX_XL_3XC_TAG;
break;
+
case LSM6DSRX_GYRO_NC_T_2_TAG:
*val = LSM6DSRX_GYRO_NC_T_2_TAG;
break;
+
case LSM6DSRX_GYRO_NC_T_1_TAG:
*val = LSM6DSRX_GYRO_NC_T_1_TAG;
break;
+
case LSM6DSRX_GYRO_2XC_TAG:
*val = LSM6DSRX_GYRO_2XC_TAG;
break;
+
case LSM6DSRX_GYRO_3XC_TAG:
*val = LSM6DSRX_GYRO_3XC_TAG;
break;
+
case LSM6DSRX_SENSORHUB_SLAVE0_TAG:
*val = LSM6DSRX_SENSORHUB_SLAVE0_TAG;
break;
+
case LSM6DSRX_SENSORHUB_SLAVE1_TAG:
*val = LSM6DSRX_SENSORHUB_SLAVE1_TAG;
break;
+
case LSM6DSRX_SENSORHUB_SLAVE2_TAG:
*val = LSM6DSRX_SENSORHUB_SLAVE2_TAG;
break;
+
case LSM6DSRX_SENSORHUB_SLAVE3_TAG:
*val = LSM6DSRX_SENSORHUB_SLAVE3_TAG;
break;
+
case LSM6DSRX_STEP_CPUNTER_TAG:
*val = LSM6DSRX_STEP_CPUNTER_TAG;
break;
+
case LSM6DSRX_GAME_ROTATION_TAG:
*val = LSM6DSRX_GAME_ROTATION_TAG;
break;
+
case LSM6DSRX_GEOMAG_ROTATION_TAG:
*val = LSM6DSRX_GEOMAG_ROTATION_TAG;
break;
+
case LSM6DSRX_ROTATION_TAG:
*val = LSM6DSRX_ROTATION_TAG;
break;
+
case LSM6DSRX_SENSORHUB_NACK_TAG:
*val = LSM6DSRX_SENSORHUB_NACK_TAG;
break;
+
default:
*val = LSM6DSRX_SENSORHUB_NACK_TAG;
break;
}
+
return ret;
}
@@ -6811,18 +7906,25 @@ int32_t lsm6dsrx_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_FIFO_CFG,
- (uint8_t*)&emb_func_fifo_cfg, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_FIFO_CFG,
+ (uint8_t *)&emb_func_fifo_cfg, 1);
}
- if(ret == 0){
- emb_func_fifo_cfg.pedo_fifo_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ emb_func_fifo_cfg.pedo_fifo_en = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_FIFO_CFG,
- (uint8_t*)&emb_func_fifo_cfg, 1);
+ (uint8_t *)&emb_func_fifo_cfg, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -6841,14 +7943,19 @@ int32_t lsm6dsrx_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_FIFO_CFG,
- (uint8_t*)&emb_func_fifo_cfg, 1);
+ (uint8_t *)&emb_func_fifo_cfg, 1);
*val = emb_func_fifo_cfg.pedo_fifo_en;
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -6867,18 +7974,24 @@ int32_t lsm6dsrx_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val)
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
- slv0_config. batch_ext_sens_0_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ slv0_config. batch_ext_sens_0_en = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -6898,14 +8011,18 @@ int32_t lsm6dsrx_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val)
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = slv0_config. batch_ext_sens_0_en;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -6924,18 +8041,25 @@ int32_t lsm6dsrx_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV1_CONFIG,
- (uint8_t*)&slv1_config, 1);
+ (uint8_t *)&slv1_config, 1);
}
- if(ret == 0){
- slv1_config. batch_ext_sens_1_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ slv1_config. batch_ext_sens_1_en = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV1_CONFIG,
- (uint8_t*)&slv1_config, 1);
+ (uint8_t *)&slv1_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -6955,14 +8079,18 @@ int32_t lsm6dsrx_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val)
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV1_CONFIG,
- (uint8_t*)&slv1_config, 1);
+ (uint8_t *)&slv1_config, 1);
*val = slv1_config. batch_ext_sens_1_en;
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -6982,18 +8110,24 @@ int32_t lsm6dsrx_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val)
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV2_CONFIG,
- (uint8_t*)&slv2_config, 1);
+ (uint8_t *)&slv2_config, 1);
}
- if(ret == 0){
- slv2_config. batch_ext_sens_2_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ slv2_config. batch_ext_sens_2_en = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV2_CONFIG,
- (uint8_t*)&slv2_config, 1);
+ (uint8_t *)&slv2_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -7012,14 +8146,19 @@ int32_t lsm6dsrx_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV2_CONFIG,
- (uint8_t*)&slv2_config, 1);
+ (uint8_t *)&slv2_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = slv2_config. batch_ext_sens_2_en;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -7038,18 +8177,25 @@ int32_t lsm6dsrx_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV3_CONFIG,
- (uint8_t*)&slv3_config, 1);
+ (uint8_t *)&slv3_config, 1);
}
- if(ret == 0){
- slv3_config. batch_ext_sens_3_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ slv3_config. batch_ext_sens_3_en = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV3_CONFIG,
- (uint8_t*)&slv3_config, 1);
+ (uint8_t *)&slv3_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -7069,14 +8215,18 @@ int32_t lsm6dsrx_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val)
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV3_CONFIG,
- (uint8_t*)&slv3_config, 1);
+ (uint8_t *)&slv3_config, 1);
*val = slv3_config. batch_ext_sens_3_en;
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -7101,16 +8251,20 @@ int32_t lsm6dsrx_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_den_mode_set(stmdev_ctx_t *ctx, lsm6dsrx_den_mode_t val)
+int32_t lsm6dsrx_den_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsrx_den_mode_t val)
{
lsm6dsrx_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
- if(ret == 0){
- ctrl6_c.den_mode= (uint8_t)val;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
+
+ if (ret == 0)
+ {
+ ctrl6_c.den_mode = (uint8_t)val;
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
}
+
return ret;
}
@@ -7123,33 +8277,40 @@ int32_t lsm6dsrx_den_mode_set(stmdev_ctx_t *ctx, lsm6dsrx_den_mode_t val)
*
*/
int32_t lsm6dsrx_den_mode_get(stmdev_ctx_t *ctx,
- lsm6dsrx_den_mode_t *val)
+ lsm6dsrx_den_mode_t *val)
{
lsm6dsrx_ctrl6_c_t ctrl6_c;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t*)&ctrl6_c, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
- switch (ctrl6_c.den_mode){
+ switch (ctrl6_c.den_mode)
+ {
case LSM6DSRX_DEN_DISABLE:
*val = LSM6DSRX_DEN_DISABLE;
break;
+
case LSM6DSRX_LEVEL_FIFO:
*val = LSM6DSRX_LEVEL_FIFO;
break;
+
case LSM6DSRX_LEVEL_LETCHED:
*val = LSM6DSRX_LEVEL_LETCHED;
break;
+
case LSM6DSRX_LEVEL_TRIGGER:
*val = LSM6DSRX_LEVEL_TRIGGER;
break;
+
case LSM6DSRX_EDGE_TRIGGER:
*val = LSM6DSRX_EDGE_TRIGGER;
break;
+
default:
*val = LSM6DSRX_DEN_DISABLE;
break;
}
+
return ret;
}
@@ -7162,17 +8323,20 @@ int32_t lsm6dsrx_den_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_den_polarity_set(stmdev_ctx_t *ctx,
- lsm6dsrx_den_lh_t val)
+ lsm6dsrx_den_lh_t val)
{
lsm6dsrx_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
- ctrl9_xl.den_lh= (uint8_t)val;
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl9_xl.den_lh = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
+ (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -7185,24 +8349,28 @@ int32_t lsm6dsrx_den_polarity_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_den_polarity_get(stmdev_ctx_t *ctx,
- lsm6dsrx_den_lh_t *val)
+ lsm6dsrx_den_lh_t *val)
{
lsm6dsrx_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
- switch (ctrl9_xl.den_lh){
+ switch (ctrl9_xl.den_lh)
+ {
case LSM6DSRX_DEN_ACT_LOW:
*val = LSM6DSRX_DEN_ACT_LOW;
break;
+
case LSM6DSRX_DEN_ACT_HIGH:
*val = LSM6DSRX_DEN_ACT_HIGH;
break;
+
default:
*val = LSM6DSRX_DEN_ACT_LOW;
break;
}
+
return ret;
}
@@ -7215,17 +8383,20 @@ int32_t lsm6dsrx_den_polarity_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_den_enable_set(stmdev_ctx_t *ctx,
- lsm6dsrx_den_xl_g_t val)
+ lsm6dsrx_den_xl_g_t val)
{
lsm6dsrx_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
- ctrl9_xl.den_xl_g= (uint8_t)val;
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl9_xl.den_xl_g = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
+ (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -7238,27 +8409,32 @@ int32_t lsm6dsrx_den_enable_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_den_enable_get(stmdev_ctx_t *ctx,
- lsm6dsrx_den_xl_g_t *val)
+ lsm6dsrx_den_xl_g_t *val)
{
lsm6dsrx_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
- switch (ctrl9_xl.den_xl_g){
+ switch (ctrl9_xl.den_xl_g)
+ {
case LSM6DSRX_STAMP_IN_GY_DATA:
*val = LSM6DSRX_STAMP_IN_GY_DATA;
break;
+
case LSM6DSRX_STAMP_IN_XL_DATA:
*val = LSM6DSRX_STAMP_IN_XL_DATA;
break;
+
case LSM6DSRX_STAMP_IN_GY_XL_DATA:
*val = LSM6DSRX_STAMP_IN_GY_XL_DATA;
break;
+
default:
*val = LSM6DSRX_STAMP_IN_GY_DATA;
break;
}
+
return ret;
}
@@ -7275,12 +8451,15 @@ int32_t lsm6dsrx_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsrx_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
- ctrl9_xl.den_z= (uint8_t)val;
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl9_xl.den_z = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
+ (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -7297,7 +8476,7 @@ int32_t lsm6dsrx_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsrx_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
*val = ctrl9_xl.den_z;
return ret;
@@ -7316,12 +8495,15 @@ int32_t lsm6dsrx_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsrx_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
- ctrl9_xl.den_y= (uint8_t)val;
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl9_xl.den_y = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL9_XL,
- (uint8_t*)&ctrl9_xl, 1);
+ (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -7338,7 +8520,7 @@ int32_t lsm6dsrx_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsrx_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
*val = ctrl9_xl.den_y;
return ret;
@@ -7357,11 +8539,14 @@ int32_t lsm6dsrx_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val)
lsm6dsrx_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
- if(ret == 0){
- ctrl9_xl.den_x= (uint8_t)val;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+ if (ret == 0)
+ {
+ ctrl9_xl.den_x = (uint8_t)val;
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
}
+
return ret;
}
@@ -7378,7 +8563,7 @@ int32_t lsm6dsrx_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm6dsrx_ctrl9_xl_t ctrl9_xl;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
*val = ctrl9_xl.den_x;
return ret;
@@ -7411,18 +8596,24 @@ int32_t lsm6dsrx_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val)
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
+ (uint8_t *)&emb_func_en_a, 1);
}
- if(ret == 0){
- emb_func_en_a.pedo_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ emb_func_en_a.pedo_en = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
+ (uint8_t *)&emb_func_en_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -7441,14 +8632,18 @@ int32_t lsm6dsrx_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
+ (uint8_t *)&emb_func_en_a, 1);
*val = emb_func_en_a.pedo_en;
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -7467,14 +8662,18 @@ int32_t lsm6dsrx_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val)
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_STATUS,
- (uint8_t*)&emb_func_status, 1);
+ (uint8_t *)&emb_func_status, 1);
*val = emb_func_status.is_step_det;
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -7486,10 +8685,14 @@ int32_t lsm6dsrx_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsrx_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
- ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_PEDO_DEB_STEPS_CONF, buff);
+
+ ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_PEDO_DEB_STEPS_CONF,
+ buff);
+
return ret;
}
@@ -7501,10 +8704,14 @@ int32_t lsm6dsrx_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsrx_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
- ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_PEDO_DEB_STEPS_CONF, buff);
+
+ ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_PEDO_DEB_STEPS_CONF,
+ buff);
+
return ret;
}
@@ -7516,18 +8723,23 @@ int32_t lsm6dsrx_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_pedo_steps_period_set(stmdev_ctx_t *ctx, uint16_t val)
+int32_t lsm6dsrx_pedo_steps_period_set(stmdev_ctx_t *ctx,
+ uint16_t val)
{
uint8_t buff[2];
int32_t ret;
- buff[1] = (uint8_t) (val / 256U);
- buff[0] = (uint8_t) (val - (buff[1] * 256U));
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
+ ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_PEDO_SC_DELTAT_L,
+ &buff[0]);
- ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_PEDO_SC_DELTAT_L, &buff[0]);
- if(ret == 0){
- ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_PEDO_SC_DELTAT_H, &buff[1]);
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_PEDO_SC_DELTAT_H,
+ &buff[1]);
}
+
return ret;
}
@@ -7539,17 +8751,23 @@ int32_t lsm6dsrx_pedo_steps_period_set(stmdev_ctx_t *ctx, uint16_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_pedo_steps_period_get(stmdev_ctx_t *ctx, uint16_t *val)
+int32_t lsm6dsrx_pedo_steps_period_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
uint8_t buff[2];
int32_t ret;
- ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_PEDO_SC_DELTAT_L, &buff[0]);
- if(ret == 0){
- ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_PEDO_SC_DELTAT_H, &buff[1]);
+ ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_PEDO_SC_DELTAT_L,
+ &buff[0]);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_PEDO_SC_DELTAT_H,
+ &buff[1]);
*val = buff[1];
*val = (*val * 256U) + buff[0];
}
+
return ret;
}
@@ -7563,19 +8781,21 @@ int32_t lsm6dsrx_pedo_steps_period_get(stmdev_ctx_t *ctx, uint16_t *val)
*
*/
int32_t lsm6dsrx_pedo_int_mode_set(stmdev_ctx_t *ctx,
- lsm6dsrx_carry_count_en_t val)
+ lsm6dsrx_carry_count_en_t val)
{
lsm6dsrx_pedo_cmd_reg_t pedo_cmd_reg;
int32_t ret;
ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_PEDO_CMD_REG,
- (uint8_t*)&pedo_cmd_reg);
+ (uint8_t *)&pedo_cmd_reg);
- if(ret == 0){
- pedo_cmd_reg.carry_count_en= (uint8_t)val;
+ if (ret == 0)
+ {
+ pedo_cmd_reg.carry_count_en = (uint8_t)val;
ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_PEDO_CMD_REG,
- (uint8_t*)&pedo_cmd_reg);
+ (uint8_t *)&pedo_cmd_reg);
}
+
return ret;
}
@@ -7589,25 +8809,29 @@ int32_t lsm6dsrx_pedo_int_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_pedo_int_mode_get(stmdev_ctx_t *ctx,
- lsm6dsrx_carry_count_en_t *val)
+ lsm6dsrx_carry_count_en_t *val)
{
lsm6dsrx_pedo_cmd_reg_t pedo_cmd_reg;
int32_t ret;
ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_PEDO_CMD_REG,
- (uint8_t*)&pedo_cmd_reg);
+ (uint8_t *)&pedo_cmd_reg);
- switch (pedo_cmd_reg.carry_count_en){
+ switch (pedo_cmd_reg.carry_count_en)
+ {
case LSM6DSRX_EVERY_STEP:
*val = LSM6DSRX_EVERY_STEP;
break;
+
case LSM6DSRX_COUNT_OVERFLOW:
*val = LSM6DSRX_COUNT_OVERFLOW;
break;
+
default:
*val = LSM6DSRX_EVERY_STEP;
break;
}
+
return ret;
}
@@ -7639,18 +8863,24 @@ int32_t lsm6dsrx_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val)
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
+ (uint8_t *)&emb_func_en_a, 1);
}
- if(ret == 0){
- emb_func_en_a.sign_motion_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ emb_func_en_a.sign_motion_en = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
+ (uint8_t *)&emb_func_en_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -7669,14 +8899,18 @@ int32_t lsm6dsrx_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
+ (uint8_t *)&emb_func_en_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = emb_func_en_a.sign_motion_en;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -7689,20 +8923,25 @@ int32_t lsm6dsrx_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsrx_motion_flag_data_ready_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
lsm6dsrx_emb_func_status_t emb_func_status;
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_STATUS,
- (uint8_t*)&emb_func_status, 1);
+ (uint8_t *)&emb_func_status, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = emb_func_status.is_sigmot;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -7733,18 +8972,25 @@ int32_t lsm6dsrx_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
+ (uint8_t *)&emb_func_en_a, 1);
}
- if(ret == 0){
- emb_func_en_a.tilt_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ emb_func_en_a.tilt_en = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_EN_A,
- (uint8_t*)&emb_func_en_a, 1);
+ (uint8_t *)&emb_func_en_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -7762,13 +9008,19 @@ int32_t lsm6dsrx_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_A, (uint8_t*)&emb_func_en_a, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_A,
+ (uint8_t *)&emb_func_en_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = emb_func_en_a.tilt_en;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -7780,20 +9032,26 @@ int32_t lsm6dsrx_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm6dsrx_tilt_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm6dsrx_emb_func_status_t emb_func_status;
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_STATUS,
- (uint8_t*)&emb_func_status, 1);
+ (uint8_t *)&emb_func_status, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = emb_func_status.is_tilt;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -7823,12 +9081,17 @@ int32_t lsm6dsrx_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val)
uint8_t buff[2];
int32_t ret;
- buff[1] = (uint8_t) (val / 256U);
- buff[0] = (uint8_t) (val - (buff[1] * 256U));
- ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SENSITIVITY_L, &buff[0]);
- if(ret == 0){
- ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SENSITIVITY_H, &buff[1]);
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
+ ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SENSITIVITY_L,
+ &buff[0]);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SENSITIVITY_H,
+ &buff[1]);
}
+
return ret;
}
@@ -7845,12 +9108,17 @@ int32_t lsm6dsrx_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val)
uint8_t buff[2];
int32_t ret;
- ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SENSITIVITY_L, &buff[0]);
- if(ret == 0){
- ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SENSITIVITY_H, &buff[1]);
+ ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SENSITIVITY_L,
+ &buff[0]);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SENSITIVITY_H,
+ &buff[1]);
*val = buff[1];
*val = (*val * 256U) + buff[0];
}
+
return ret;
}
@@ -7866,37 +9134,47 @@ int32_t lsm6dsrx_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val)
{
uint8_t buff[6];
int32_t ret;
- uint8_t i;
-
- buff[1] = (uint8_t) ((uint16_t)val[0] / 256U);
- buff[0] = (uint8_t) ((uint16_t)val[0] - (buff[1] * 256U));
- buff[3] = (uint8_t) ((uint16_t)val[1] / 256U);
- buff[2] = (uint8_t) ((uint16_t)val[1] - (buff[3] * 256U));
- buff[5] = (uint8_t) ((uint16_t)val[2] / 256U);
- buff[4] = (uint8_t) ((uint16_t)val[2] - (buff[5] * 256U));
+ uint8_t i;
+ buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
+ buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
+ buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
+ buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
+ buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
+ buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
i = 0x00U;
ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_OFFX_L, &buff[i]);
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_OFFX_H, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_OFFY_L, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_OFFY_H, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_OFFZ_L, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_OFFZ_H, &buff[i]);
}
+
return ret;
}
@@ -7912,31 +9190,41 @@ int32_t lsm6dsrx_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val)
{
uint8_t buff[6];
int32_t ret;
- uint8_t i;
+ uint8_t i;
i = 0x00U;
ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_OFFX_L, &buff[i]);
- if(ret == 0){
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_OFFX_H, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_OFFY_L, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_OFFY_H, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_OFFZ_L, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_OFFZ_H, &buff[i]);
}
+
val[0] = (int16_t)buff[1];
val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
@@ -7964,67 +9252,89 @@ int32_t lsm6dsrx_mag_soft_iron_set(stmdev_ctx_t *ctx, uint16_t *val)
{
uint8_t buff[12];
int32_t ret;
- uint8_t i;
-
- buff[1] = (uint8_t) (val[0] / 256U);
- buff[0] = (uint8_t) (val[0] - (buff[1] * 256U));
- buff[3] = (uint8_t) (val[1] / 256U);
- buff[2] = (uint8_t) (val[1] - (buff[3] * 256U));
- buff[5] = (uint8_t) (val[2] / 256U);
- buff[4] = (uint8_t) (val[2] - (buff[5] * 256U));
- buff[7] = (uint8_t) (val[3] / 256U);
- buff[6] = (uint8_t) (val[3] - (buff[1] * 256U));
- buff[9] = (uint8_t) (val[4] / 256U);
- buff[8] = (uint8_t) (val[4] - (buff[3] * 256U));
- buff[11] = (uint8_t) (val[5] / 256U);
- buff[10] = (uint8_t) (val[5] - (buff[5] * 256U));
+ uint8_t i;
+ buff[1] = (uint8_t)(val[0] / 256U);
+ buff[0] = (uint8_t)(val[0] - (buff[1] * 256U));
+ buff[3] = (uint8_t)(val[1] / 256U);
+ buff[2] = (uint8_t)(val[1] - (buff[3] * 256U));
+ buff[5] = (uint8_t)(val[2] / 256U);
+ buff[4] = (uint8_t)(val[2] - (buff[5] * 256U));
+ buff[7] = (uint8_t)(val[3] / 256U);
+ buff[6] = (uint8_t)(val[3] - (buff[1] * 256U));
+ buff[9] = (uint8_t)(val[4] / 256U);
+ buff[8] = (uint8_t)(val[4] - (buff[3] * 256U));
+ buff[11] = (uint8_t)(val[5] / 256U);
+ buff[10] = (uint8_t)(val[5] - (buff[5] * 256U));
i = 0x00U;
ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_XX_L, &buff[i]);
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_XX_H, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_XY_L, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_XY_H, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_XZ_L, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_XZ_H, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_YY_L, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_YY_H, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_YZ_L, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_YZ_H, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_ZZ_L, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_ZZ_H, &buff[i]);
}
+
return ret;
}
@@ -8045,51 +9355,73 @@ int32_t lsm6dsrx_mag_soft_iron_get(stmdev_ctx_t *ctx, uint16_t *val)
{
uint8_t buff[12];
int32_t ret;
- uint8_t i;
+ uint8_t i;
i = 0x00U;
ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_XX_L, &buff[i]);
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_XX_H, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_XY_L, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_XY_H, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_XZ_L, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_XZ_H, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_YY_L, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_YY_H, &buff[i]);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_YZ_L, &buff[i]);
- }
- if(ret == 0){
+ }
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_YZ_H, &buff[i]);
- }
- if(ret == 0){
+ }
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_ZZ_L, &buff[i]);
- }
- if(ret == 0){
+ }
+
+ if (ret == 0)
+ {
i++;
ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_ZZ_H, &buff[i]);
}
@@ -8120,19 +9452,21 @@ int32_t lsm6dsrx_mag_soft_iron_get(stmdev_ctx_t *ctx, uint16_t *val)
*
*/
int32_t lsm6dsrx_mag_z_orient_set(stmdev_ctx_t *ctx,
- lsm6dsrx_mag_z_axis_t val)
+ lsm6dsrx_mag_z_axis_t val)
{
lsm6dsrx_mag_cfg_a_t mag_cfg_a;
int32_t ret;
ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_CFG_A,
- (uint8_t*)&mag_cfg_a);
+ (uint8_t *)&mag_cfg_a);
- if(ret == 0){
- mag_cfg_a.mag_z_axis= (uint8_t)val;
+ if (ret == 0)
+ {
+ mag_cfg_a.mag_z_axis = (uint8_t)val;
ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_CFG_A,
- (uint8_t*)&mag_cfg_a);
+ (uint8_t *)&mag_cfg_a);
}
+
return ret;
}
@@ -8150,32 +9484,41 @@ int32_t lsm6dsrx_mag_z_orient_get(stmdev_ctx_t *ctx,
{
lsm6dsrx_mag_cfg_a_t mag_cfg_a;
int32_t ret;
+
ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_CFG_A,
- (uint8_t*)&mag_cfg_a);
+ (uint8_t *)&mag_cfg_a);
- switch (mag_cfg_a.mag_z_axis){
+ switch (mag_cfg_a.mag_z_axis)
+ {
case LSM6DSRX_Z_EQ_Y:
*val = LSM6DSRX_Z_EQ_Y;
break;
+
case LSM6DSRX_Z_EQ_MIN_Y:
*val = LSM6DSRX_Z_EQ_MIN_Y;
break;
+
case LSM6DSRX_Z_EQ_X:
*val = LSM6DSRX_Z_EQ_X;
break;
+
case LSM6DSRX_Z_EQ_MIN_X:
*val = LSM6DSRX_Z_EQ_MIN_X;
break;
+
case LSM6DSRX_Z_EQ_MIN_Z:
*val = LSM6DSRX_Z_EQ_MIN_Z;
break;
+
case LSM6DSRX_Z_EQ_Z:
*val = LSM6DSRX_Z_EQ_Z;
break;
+
default:
*val = LSM6DSRX_Z_EQ_Y;
break;
}
+
return ret;
}
@@ -8196,12 +9539,15 @@ int32_t lsm6dsrx_mag_y_orient_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_CFG_A,
- (uint8_t*)&mag_cfg_a);
- if(ret == 0){
- mag_cfg_a.mag_y_axis= (uint8_t)val;
+ (uint8_t *)&mag_cfg_a);
+
+ if (ret == 0)
+ {
+ mag_cfg_a.mag_y_axis = (uint8_t)val;
ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_CFG_A,
- (uint8_t*)&mag_cfg_a);
+ (uint8_t *)&mag_cfg_a);
}
+
return ret;
}
@@ -8221,31 +9567,39 @@ int32_t lsm6dsrx_mag_y_orient_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_CFG_A,
- (uint8_t*)&mag_cfg_a);
+ (uint8_t *)&mag_cfg_a);
- switch (mag_cfg_a.mag_y_axis){
+ switch (mag_cfg_a.mag_y_axis)
+ {
case LSM6DSRX_Y_EQ_Y:
*val = LSM6DSRX_Y_EQ_Y;
break;
+
case LSM6DSRX_Y_EQ_MIN_Y:
*val = LSM6DSRX_Y_EQ_MIN_Y;
break;
+
case LSM6DSRX_Y_EQ_X:
*val = LSM6DSRX_Y_EQ_X;
break;
+
case LSM6DSRX_Y_EQ_MIN_X:
*val = LSM6DSRX_Y_EQ_MIN_X;
break;
+
case LSM6DSRX_Y_EQ_MIN_Z:
*val = LSM6DSRX_Y_EQ_MIN_Z;
break;
+
case LSM6DSRX_Y_EQ_Z:
*val = LSM6DSRX_Y_EQ_Z;
break;
+
default:
*val = LSM6DSRX_Y_EQ_Y;
break;
}
+
return ret;
}
@@ -8259,18 +9613,21 @@ int32_t lsm6dsrx_mag_y_orient_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_mag_x_orient_set(stmdev_ctx_t *ctx,
- lsm6dsrx_mag_x_axis_t val)
+ lsm6dsrx_mag_x_axis_t val)
{
lsm6dsrx_mag_cfg_b_t mag_cfg_b;
int32_t ret;
ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_CFG_B,
- (uint8_t*)&mag_cfg_b);
- if(ret == 0){
- mag_cfg_b.mag_x_axis= (uint8_t)val;
+ (uint8_t *)&mag_cfg_b);
+
+ if (ret == 0)
+ {
+ mag_cfg_b.mag_x_axis = (uint8_t)val;
ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_CFG_B,
- (uint8_t*)&mag_cfg_b);
+ (uint8_t *)&mag_cfg_b);
}
+
return ret;
}
@@ -8284,37 +9641,45 @@ int32_t lsm6dsrx_mag_x_orient_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_mag_x_orient_get(stmdev_ctx_t *ctx,
- lsm6dsrx_mag_x_axis_t *val)
+ lsm6dsrx_mag_x_axis_t *val)
{
lsm6dsrx_mag_cfg_b_t mag_cfg_b;
int32_t ret;
ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_CFG_B,
- (uint8_t*)&mag_cfg_b);
+ (uint8_t *)&mag_cfg_b);
- switch (mag_cfg_b.mag_x_axis){
+ switch (mag_cfg_b.mag_x_axis)
+ {
case LSM6DSRX_X_EQ_Y:
*val = LSM6DSRX_X_EQ_Y;
break;
+
case LSM6DSRX_X_EQ_MIN_Y:
*val = LSM6DSRX_X_EQ_MIN_Y;
break;
+
case LSM6DSRX_X_EQ_X:
*val = LSM6DSRX_X_EQ_X;
break;
+
case LSM6DSRX_X_EQ_MIN_X:
*val = LSM6DSRX_X_EQ_MIN_X;
break;
+
case LSM6DSRX_X_EQ_MIN_Z:
*val = LSM6DSRX_X_EQ_MIN_Z;
break;
+
case LSM6DSRX_X_EQ_Z:
*val = LSM6DSRX_X_EQ_Z;
break;
+
default:
*val = LSM6DSRX_X_EQ_Y;
break;
}
+
return ret;
}
@@ -8341,20 +9706,25 @@ int32_t lsm6dsrx_mag_x_orient_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
- uint8_t *val)
+ uint8_t *val)
{
lsm6dsrx_emb_func_status_t emb_func_status;
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_STATUS,
- (uint8_t*)&emb_func_status, 1);
+ (uint8_t *)&emb_func_status, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = emb_func_status.is_fsm_lc;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -8369,22 +9739,28 @@ int32_t lsm6dsrx_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
int32_t lsm6dsrx_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val)
{
int32_t ret;
- lsm6dsrx_emb_func_en_b_t emb_func_en_b;
+ lsm6dsrx_emb_func_en_b_t emb_func_en_b;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if(ret == 0){
- emb_func_en_b.fsm_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ emb_func_en_b.fsm_en = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -8399,21 +9775,28 @@ int32_t lsm6dsrx_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t lsm6dsrx_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val)
{
int32_t ret;
- lsm6dsrx_emb_func_en_b_t emb_func_en_b;
+ lsm6dsrx_emb_func_en_b_t emb_func_en_b;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = emb_func_en_b.fsm_en;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -8426,54 +9809,70 @@ int32_t lsm6dsrx_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsrx_fsm_enable_set(stmdev_ctx_t *ctx,
- lsm6dsrx_emb_fsm_enable_t *val)
+ lsm6dsrx_emb_fsm_enable_t *val)
{
lsm6dsrx_emb_func_en_b_t emb_func_en_b;
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FSM_ENABLE_A,
- (uint8_t*)&val->fsm_enable_a, 1);
+ (uint8_t *)&val->fsm_enable_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FSM_ENABLE_B,
- (uint8_t*)&val->fsm_enable_b, 1);
+ (uint8_t *)&val->fsm_enable_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
- }
- if(ret == 0){
- if ( (val->fsm_enable_a.fsm1_en |
- val->fsm_enable_a.fsm2_en |
- val->fsm_enable_a.fsm3_en |
- val->fsm_enable_a.fsm4_en |
- val->fsm_enable_a.fsm5_en |
- val->fsm_enable_a.fsm6_en |
- val->fsm_enable_a.fsm7_en |
- val->fsm_enable_a.fsm8_en |
- val->fsm_enable_b.fsm9_en |
- val->fsm_enable_b.fsm10_en |
- val->fsm_enable_b.fsm11_en |
- val->fsm_enable_b.fsm12_en |
- val->fsm_enable_b.fsm13_en |
- val->fsm_enable_b.fsm14_en |
- val->fsm_enable_b.fsm15_en |
- val->fsm_enable_b.fsm16_en ) != PROPERTY_DISABLE){
+ (uint8_t *)&emb_func_en_b, 1);
+ }
+
+ if (ret == 0)
+ {
+ if ((val->fsm_enable_a.fsm1_en |
+ val->fsm_enable_a.fsm2_en |
+ val->fsm_enable_a.fsm3_en |
+ val->fsm_enable_a.fsm4_en |
+ val->fsm_enable_a.fsm5_en |
+ val->fsm_enable_a.fsm6_en |
+ val->fsm_enable_a.fsm7_en |
+ val->fsm_enable_a.fsm8_en |
+ val->fsm_enable_b.fsm9_en |
+ val->fsm_enable_b.fsm10_en |
+ val->fsm_enable_b.fsm11_en |
+ val->fsm_enable_b.fsm12_en |
+ val->fsm_enable_b.fsm13_en |
+ val->fsm_enable_b.fsm14_en |
+ val->fsm_enable_b.fsm15_en |
+ val->fsm_enable_b.fsm16_en) != PROPERTY_DISABLE)
+ {
emb_func_en_b.fsm_en = PROPERTY_ENABLE;
}
- else{
+
+ else
+ {
emb_func_en_b.fsm_en = PROPERTY_DISABLE;
}
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B,
- (uint8_t*)&emb_func_en_b, 1);
+ (uint8_t *)&emb_func_en_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -8486,22 +9885,29 @@ int32_t lsm6dsrx_fsm_enable_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_fsm_enable_get(stmdev_ctx_t *ctx,
- lsm6dsrx_emb_fsm_enable_t *val)
+ lsm6dsrx_emb_fsm_enable_t *val)
{
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_ENABLE_A,
- (uint8_t*)&val->fsm_enable_a, 1);
+ (uint8_t *)&val->fsm_enable_a, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_ENABLE_B,
- (uint8_t*)&val->fsm_enable_b, 1);
+ (uint8_t *)&val->fsm_enable_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -8519,16 +9925,20 @@ int32_t lsm6dsrx_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val)
uint8_t buff[2];
int32_t ret;
- buff[1] = (uint8_t) (val / 256U);
- buff[0] = (uint8_t) (val - (buff[1] * 256U));
-
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FSM_LONG_COUNTER_L, buff, 2);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -8547,14 +9957,19 @@ int32_t lsm6dsrx_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val)
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_LONG_COUNTER_L, buff, 2);
*val = buff[1];
*val = (*val * 256U) + buff[0];
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -8574,18 +9989,25 @@ int32_t lsm6dsrx_long_clr_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_LONG_COUNTER_CLEAR,
- (uint8_t*)&fsm_long_counter_clear, 1);
+ (uint8_t *)&fsm_long_counter_clear, 1);
}
- if(ret == 0){
- fsm_long_counter_clear.fsm_lc_clr= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ fsm_long_counter_clear.fsm_lc_clr = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FSM_LONG_COUNTER_CLEAR,
- (uint8_t*)&fsm_long_counter_clear, 1);
+ (uint8_t *)&fsm_long_counter_clear, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -8598,34 +10020,43 @@ int32_t lsm6dsrx_long_clr_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_long_clr_get(stmdev_ctx_t *ctx,
- lsm6dsrx_fsm_lc_clr_t *val)
+ lsm6dsrx_fsm_lc_clr_t *val)
{
lsm6dsrx_fsm_long_counter_clear_t fsm_long_counter_clear;
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_LONG_COUNTER_CLEAR,
- (uint8_t*)&fsm_long_counter_clear, 1);
+ (uint8_t *)&fsm_long_counter_clear, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
- switch (fsm_long_counter_clear.fsm_lc_clr){
+
+ switch (fsm_long_counter_clear.fsm_lc_clr)
+ {
case LSM6DSRX_LC_NORMAL:
*val = LSM6DSRX_LC_NORMAL;
break;
+
case LSM6DSRX_LC_CLEAR:
*val = LSM6DSRX_LC_CLEAR;
break;
+
case LSM6DSRX_LC_CLEAR_DONE:
*val = LSM6DSRX_LC_CLEAR_DONE;
break;
+
default:
*val = LSM6DSRX_LC_NORMAL;
break;
}
+
return ret;
}
@@ -8637,19 +10068,24 @@ int32_t lsm6dsrx_long_clr_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_fsm_out_get(stmdev_ctx_t *ctx, lsm6dsrx_fsm_out_t *val)
+int32_t lsm6dsrx_fsm_out_get(stmdev_ctx_t *ctx,
+ lsm6dsrx_fsm_out_t *val)
{
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_OUTS1,
- (uint8_t*)&val->fsm_outs1, 16);
+ (uint8_t *)&val->fsm_outs1, 16);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -8662,27 +10098,33 @@ int32_t lsm6dsrx_fsm_out_get(stmdev_ctx_t *ctx, lsm6dsrx_fsm_out_t *val)
*
*/
int32_t lsm6dsrx_fsm_data_rate_set(stmdev_ctx_t *ctx,
- lsm6dsrx_fsm_odr_t val)
+ lsm6dsrx_fsm_odr_t val)
{
lsm6dsrx_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_ODR_CFG_B,
- (uint8_t*)&emb_func_odr_cfg_b, 1);
+ (uint8_t *)&emb_func_odr_cfg_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
emb_func_odr_cfg_b.not_used_01 = 3; /* set default values */
emb_func_odr_cfg_b.not_used_02 = 1; /* set default values */
- emb_func_odr_cfg_b.fsm_odr= (uint8_t)val;
+ emb_func_odr_cfg_b.fsm_odr = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_ODR_CFG_B,
- (uint8_t*)&emb_func_odr_cfg_b, 1);
- }
- if(ret == 0){
+ (uint8_t *)&emb_func_odr_cfg_b, 1);
+ }
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -8695,37 +10137,47 @@ int32_t lsm6dsrx_fsm_data_rate_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_fsm_data_rate_get(stmdev_ctx_t *ctx,
- lsm6dsrx_fsm_odr_t *val)
+ lsm6dsrx_fsm_odr_t *val)
{
lsm6dsrx_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_ODR_CFG_B,
- (uint8_t*)&emb_func_odr_cfg_b, 1);
+ (uint8_t *)&emb_func_odr_cfg_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
- switch (emb_func_odr_cfg_b.fsm_odr){
+
+ switch (emb_func_odr_cfg_b.fsm_odr)
+ {
case LSM6DSRX_ODR_FSM_12Hz5:
*val = LSM6DSRX_ODR_FSM_12Hz5;
break;
+
case LSM6DSRX_ODR_FSM_26Hz:
*val = LSM6DSRX_ODR_FSM_26Hz;
break;
+
case LSM6DSRX_ODR_FSM_52Hz:
*val = LSM6DSRX_ODR_FSM_52Hz;
break;
+
case LSM6DSRX_ODR_FSM_104Hz:
*val = LSM6DSRX_ODR_FSM_104Hz;
break;
+
default:
*val = LSM6DSRX_ODR_FSM_12Hz5;
break;
}
+
return ret;
}
@@ -8744,18 +10196,24 @@ int32_t lsm6dsrx_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val)
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_INIT_B,
- (uint8_t*)&emb_func_init_b, 1);
+ (uint8_t *)&emb_func_init_b, 1);
}
- if(ret == 0){
- emb_func_init_b.fsm_init= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ emb_func_init_b.fsm_init = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_INIT_B,
- (uint8_t*)&emb_func_init_b, 1);
+ (uint8_t *)&emb_func_init_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -8773,14 +10231,19 @@ int32_t lsm6dsrx_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_INIT_B,
- (uint8_t*)&emb_func_init_b, 1);
+ (uint8_t *)&emb_func_init_b, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = emb_func_init_b.fsm_init;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -8795,19 +10258,23 @@ int32_t lsm6dsrx_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint16_t val)
+int32_t lsm6dsrx_long_cnt_int_value_set(stmdev_ctx_t *ctx,
+ uint16_t val)
{
uint8_t buff[2];
int32_t ret;
- buff[1] = (uint8_t) (val / 256U);
- buff[0] = (uint8_t) (val - (buff[1] * 256U));
- ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_FSM_LC_TIMEOUT_L, &buff[0]);
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
+ ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_FSM_LC_TIMEOUT_L,
+ &buff[0]);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_FSM_LC_TIMEOUT_H,
- &buff[1]);
+ &buff[1]);
}
+
return ret;
}
@@ -8822,19 +10289,23 @@ int32_t lsm6dsrx_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint16_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint16_t *val)
+int32_t lsm6dsrx_long_cnt_int_value_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
uint8_t buff[2];
int32_t ret;
- ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_FSM_LC_TIMEOUT_L, &buff[0]);
+ ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_FSM_LC_TIMEOUT_L,
+ &buff[0]);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_FSM_LC_TIMEOUT_H,
- &buff[1]);
+ &buff[1]);
*val = buff[1];
*val = (*val * 256U) + buff[0];
}
+
return ret;
}
@@ -8846,16 +10317,19 @@ int32_t lsm6dsrx_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint16_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsrx_fsm_number_of_programs_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_FSM_PROGRAMS, buff);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_FSM_PROGRAMS + 0x01U,
- buff);
+ buff);
}
+
return ret;
}
@@ -8867,7 +10341,8 @@ int32_t lsm6dsrx_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm6dsrx_fsm_number_of_programs_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
@@ -8885,18 +10360,23 @@ int32_t lsm6dsrx_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val)
+int32_t lsm6dsrx_fsm_start_address_set(stmdev_ctx_t *ctx,
+ uint16_t val)
{
uint8_t buff[2];
int32_t ret;
- buff[1] = (uint8_t) (val / 256U);
- buff[0] = (uint8_t) (val - (buff[1] * 256U));
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
+ ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_FSM_START_ADD_L,
+ &buff[0]);
- ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_FSM_START_ADD_L, &buff[0]);
- if(ret == 0){
- ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_FSM_START_ADD_H, &buff[1]);
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_FSM_START_ADD_H,
+ &buff[1]);
}
+
return ret;
}
@@ -8909,17 +10389,23 @@ int32_t lsm6dsrx_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm6dsrx_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val)
+int32_t lsm6dsrx_fsm_start_address_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
uint8_t buff[2];
int32_t ret;
- ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_FSM_START_ADD_L, &buff[0]);
- if(ret == 0){
- ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_FSM_START_ADD_H, &buff[1]);
+ ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_FSM_START_ADD_L,
+ &buff[0]);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_FSM_START_ADD_H,
+ &buff[1]);
*val = buff[1];
*val = (*val * 256U) + buff[0];
}
+
return ret;
}
@@ -8951,25 +10437,36 @@ int32_t lsm6dsrx_mlc_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.mlc_en = val;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B, (uint8_t*)®, 1);
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B, (uint8_t *)®, 1);
}
- if ((val != PROPERTY_DISABLE) && (ret == 0)){
+
+ if ((val != PROPERTY_DISABLE) && (ret == 0))
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_INIT_B,
- (uint8_t*)®, 1);
- if (ret == 0) {
+ (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.mlc_en = val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_INIT_B,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -8987,13 +10484,18 @@ int32_t lsm6dsrx_mlc_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B, (uint8_t*)®, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B, (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
*val = reg.mlc_en;
}
+
return ret;
}
@@ -9008,7 +10510,7 @@ int32_t lsm6dsrx_mlc_status_get(stmdev_ctx_t *ctx,
lsm6dsrx_mlc_status_mainpage_t *val)
{
return lsm6dsrx_read_reg(ctx, LSM6DSRX_MLC_STATUS_MAINPAGE,
- (uint8_t*) val, 1);
+ (uint8_t *) val, 1);
}
/**
@@ -9019,22 +10521,29 @@ int32_t lsm6dsrx_mlc_status_get(stmdev_ctx_t *ctx,
* reg EMB_FUNC_ODR_CFG_C
*
*/
-int32_t lsm6dsrx_mlc_data_rate_set(stmdev_ctx_t *ctx, lsm6dsrx_mlc_odr_t val)
+int32_t lsm6dsrx_mlc_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dsrx_mlc_odr_t val)
{
lsm6dsrx_emb_func_odr_cfg_c_t reg;
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_ODR_CFG_C,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
reg.mlc_odr = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_ODR_CFG_C,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
@@ -9049,36 +10558,48 @@ int32_t lsm6dsrx_mlc_data_rate_set(stmdev_ctx_t *ctx, lsm6dsrx_mlc_odr_t val)
* reg EMB_FUNC_ODR_CFG_C
*
*/
-int32_t lsm6dsrx_mlc_data_rate_get(stmdev_ctx_t *ctx, lsm6dsrx_mlc_odr_t *val)
+int32_t lsm6dsrx_mlc_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dsrx_mlc_odr_t *val)
{
lsm6dsrx_emb_func_odr_cfg_c_t reg;
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_ODR_CFG_C,
- (uint8_t*)®, 1);
+ (uint8_t *)®, 1);
}
- if (ret == 0) {
- switch (reg.mlc_odr) {
+
+ if (ret == 0)
+ {
+ switch (reg.mlc_odr)
+ {
case LSM6DSRX_ODR_PRGS_12Hz5:
*val = LSM6DSRX_ODR_PRGS_12Hz5;
break;
+
case LSM6DSRX_ODR_PRGS_26Hz:
*val = LSM6DSRX_ODR_PRGS_26Hz;
break;
+
case LSM6DSRX_ODR_PRGS_52Hz:
*val = LSM6DSRX_ODR_PRGS_52Hz;
break;
+
case LSM6DSRX_ODR_PRGS_104Hz:
*val = LSM6DSRX_ODR_PRGS_104Hz;
break;
+
default:
*val = LSM6DSRX_ODR_PRGS_12Hz5;
break;
}
+
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -9092,13 +10613,19 @@ int32_t lsm6dsrx_mlc_data_rate_get(stmdev_ctx_t *ctx, lsm6dsrx_mlc_odr_t *val)
int32_t lsm6dsrx_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MLC0_SRC, buff, 8);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -9110,19 +10637,23 @@ int32_t lsm6dsrx_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @param buff buffer that contains data to write
*
*/
-int32_t lsm6dsrx_mlc_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val)
+int32_t lsm6dsrx_mlc_mag_sensitivity_set(stmdev_ctx_t *ctx,
+ uint16_t val)
{
uint8_t buff[2];
int32_t ret;
- buff[1] = (uint8_t) (val / 256U);
- buff[0] = (uint8_t) (val - (buff[1] * 256U));
+ buff[1] = (uint8_t)(val / 256U);
+ buff[0] = (uint8_t)(val - (buff[1] * 256U));
ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MLC_MAG_SENSITIVITY_L,
&buff[0]);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MLC_MAG_SENSITIVITY_H,
&buff[1]);
}
+
return ret;
}
@@ -9134,19 +10665,23 @@ int32_t lsm6dsrx_mlc_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val)
* @param buff buffer that stores data read
*
*/
-int32_t lsm6dsrx_mlc_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val)
+int32_t lsm6dsrx_mlc_mag_sensitivity_get(stmdev_ctx_t *ctx,
+ uint16_t *val)
{
uint8_t buff[2];
int32_t ret;
ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MLC_MAG_SENSITIVITY_L,
&buff[0]);
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MLC_MAG_SENSITIVITY_H,
&buff[1]);
*val = buff[1];
*val = (*val * 256U) + buff[0];
}
+
return ret;
}
@@ -9172,18 +10707,23 @@ int32_t lsm6dsrx_mlc_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val)
*
*/
int32_t lsm6dsrx_sh_read_data_raw_get(stmdev_ctx_t *ctx,
- lsm6dsrx_emb_sh_read_t *val)
+ lsm6dsrx_emb_sh_read_t *val)
{
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
- if(ret == 0){
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SENSOR_HUB_1, (uint8_t*)val, 18);
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SENSOR_HUB_1, (uint8_t *)val,
+ 18);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -9196,25 +10736,31 @@ int32_t lsm6dsrx_sh_read_data_raw_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_sh_slave_connected_set(stmdev_ctx_t *ctx,
- lsm6dsrx_aux_sens_on_t val)
+ lsm6dsrx_aux_sens_on_t val)
{
lsm6dsrx_master_config_t master_config;
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- master_config.aux_sens_on= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ master_config.aux_sens_on = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -9227,37 +10773,47 @@ int32_t lsm6dsrx_sh_slave_connected_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_sh_slave_connected_get(stmdev_ctx_t *ctx,
- lsm6dsrx_aux_sens_on_t *val)
+ lsm6dsrx_aux_sens_on_t *val)
{
lsm6dsrx_master_config_t master_config;
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
- switch (master_config.aux_sens_on){
+
+ switch (master_config.aux_sens_on)
+ {
case LSM6DSRX_SLV_0:
*val = LSM6DSRX_SLV_0;
break;
+
case LSM6DSRX_SLV_0_1:
*val = LSM6DSRX_SLV_0_1;
break;
+
case LSM6DSRX_SLV_0_1_2:
*val = LSM6DSRX_SLV_0_1_2;
break;
+
case LSM6DSRX_SLV_0_1_2_3:
*val = LSM6DSRX_SLV_0_1_2_3;
break;
+
default:
*val = LSM6DSRX_SLV_0;
break;
}
+
return ret;
}
@@ -9276,18 +10832,24 @@ int32_t lsm6dsrx_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- master_config.master_on= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ master_config.master_on = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -9306,14 +10868,18 @@ int32_t lsm6dsrx_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = master_config.master_on;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -9326,25 +10892,31 @@ int32_t lsm6dsrx_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsrx_sh_pin_mode_set(stmdev_ctx_t *ctx,
- lsm6dsrx_shub_pu_en_t val)
+ lsm6dsrx_shub_pu_en_t val)
{
lsm6dsrx_master_config_t master_config;
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- master_config.shub_pu_en= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ master_config.shub_pu_en = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -9357,30 +10929,39 @@ int32_t lsm6dsrx_sh_pin_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_sh_pin_mode_get(stmdev_ctx_t *ctx,
- lsm6dsrx_shub_pu_en_t *val)
+ lsm6dsrx_shub_pu_en_t *val)
{
lsm6dsrx_master_config_t master_config;
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
- switch (master_config.shub_pu_en){
+
+ switch (master_config.shub_pu_en)
+ {
case LSM6DSRX_EXT_PULL_UP:
*val = LSM6DSRX_EXT_PULL_UP;
break;
+
case LSM6DSRX_INTERNAL_PULL_UP:
*val = LSM6DSRX_INTERNAL_PULL_UP;
break;
+
default:
*val = LSM6DSRX_EXT_PULL_UP;
break;
}
+
return ret;
}
@@ -9399,18 +10980,24 @@ int32_t lsm6dsrx_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- master_config.pass_through_mode= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ master_config.pass_through_mode = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -9429,14 +11016,18 @@ int32_t lsm6dsrx_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
*val = master_config.pass_through_mode;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -9449,25 +11040,31 @@ int32_t lsm6dsrx_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsrx_sh_syncro_mode_set(stmdev_ctx_t *ctx,
- lsm6dsrx_start_config_t val)
+ lsm6dsrx_start_config_t val)
{
lsm6dsrx_master_config_t master_config;
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- master_config.start_config= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ master_config.start_config = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -9480,31 +11077,39 @@ int32_t lsm6dsrx_sh_syncro_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_sh_syncro_mode_get(stmdev_ctx_t *ctx,
- lsm6dsrx_start_config_t *val)
+ lsm6dsrx_start_config_t *val)
{
lsm6dsrx_master_config_t master_config;
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
- switch (master_config.start_config){
+
+ switch (master_config.start_config)
+ {
case LSM6DSRX_EXT_ON_INT2_PIN:
*val = LSM6DSRX_EXT_ON_INT2_PIN;
break;
+
case LSM6DSRX_XL_GY_DRDY:
*val = LSM6DSRX_XL_GY_DRDY;
break;
+
default:
*val = LSM6DSRX_EXT_ON_INT2_PIN;
break;
}
+
return ret;
}
@@ -9518,25 +11123,31 @@ int32_t lsm6dsrx_sh_syncro_mode_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_sh_write_mode_set(stmdev_ctx_t *ctx,
- lsm6dsrx_write_once_t val)
+ lsm6dsrx_write_once_t val)
{
lsm6dsrx_master_config_t master_config;
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
- master_config.write_once= (uint8_t)val;
+
+ if (ret == 0)
+ {
+ master_config.write_once = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -9550,31 +11161,39 @@ int32_t lsm6dsrx_sh_write_mode_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_sh_write_mode_get(stmdev_ctx_t *ctx,
- lsm6dsrx_write_once_t *val)
+ lsm6dsrx_write_once_t *val)
{
lsm6dsrx_master_config_t master_config;
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
- switch (master_config.write_once){
+
+ switch (master_config.write_once)
+ {
case LSM6DSRX_EACH_SH_CYCLE:
*val = LSM6DSRX_EACH_SH_CYCLE;
break;
+
case LSM6DSRX_ONLY_FIRST_CYCLE:
*val = LSM6DSRX_ONLY_FIRST_CYCLE;
break;
+
default:
*val = LSM6DSRX_EACH_SH_CYCLE;
break;
}
+
return ret;
}
@@ -9592,23 +11211,31 @@ int32_t lsm6dsrx_sh_reset_set(stmdev_ctx_t *ctx)
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
master_config.rst_master_regs = PROPERTY_ENABLE;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
master_config.rst_master_regs = PROPERTY_DISABLE;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -9627,14 +11254,18 @@ int32_t lsm6dsrx_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
- (uint8_t*)&master_config, 1);
+ (uint8_t *)&master_config, 1);
*val = master_config.rst_master_regs;
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -9647,25 +11278,31 @@ int32_t lsm6dsrx_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t lsm6dsrx_sh_data_rate_set(stmdev_ctx_t *ctx,
- lsm6dsrx_shub_odr_t val)
+ lsm6dsrx_shub_odr_t val)
{
lsm6dsrx_slv0_config_t slv0_config;
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv0_config.shub_odr = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -9678,37 +11315,47 @@ int32_t lsm6dsrx_sh_data_rate_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_sh_data_rate_get(stmdev_ctx_t *ctx,
- lsm6dsrx_shub_odr_t *val)
+ lsm6dsrx_shub_odr_t *val)
{
lsm6dsrx_slv0_config_t slv0_config;
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
- switch (slv0_config.shub_odr){
+
+ switch (slv0_config.shub_odr)
+ {
case LSM6DSRX_SH_ODR_104Hz:
*val = LSM6DSRX_SH_ODR_104Hz;
break;
+
case LSM6DSRX_SH_ODR_52Hz:
*val = LSM6DSRX_SH_ODR_52Hz;
break;
+
case LSM6DSRX_SH_ODR_26Hz:
*val = LSM6DSRX_SH_ODR_26Hz;
break;
+
case LSM6DSRX_SH_ODR_13Hz:
*val = LSM6DSRX_SH_ODR_13Hz;
break;
+
default:
*val = LSM6DSRX_SH_ODR_104Hz;
break;
}
+
return ret;
}
@@ -9724,30 +11371,38 @@ int32_t lsm6dsrx_sh_data_rate_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_sh_cfg_write(stmdev_ctx_t *ctx,
- lsm6dsrx_sh_cfg_write_t *val)
+ lsm6dsrx_sh_cfg_write_t *val)
{
lsm6dsrx_slv0_add_t slv0_add;
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
- if(ret == 0){
- slv0_add.slave0 = (uint8_t) (val->slv0_add >> 1);
+ if (ret == 0)
+ {
+ slv0_add.slave0 = (uint8_t)(val->slv0_add >> 1);
slv0_add.rw_0 = 0;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV0_ADD,
- (uint8_t*)&(slv0_add), 1);
+ (uint8_t *) & (slv0_add), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV0_SUBADD,
- (uint8_t*)&(val->slv0_subadd), 1);
+ (uint8_t *) & (val->slv0_subadd), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_DATAWRITE_SLV0,
- (uint8_t*)&(val->slv0_data), 1);
+ (uint8_t *) & (val->slv0_data), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -9763,7 +11418,7 @@ int32_t lsm6dsrx_sh_cfg_write(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
- lsm6dsrx_sh_cfg_read_t *val)
+ lsm6dsrx_sh_cfg_read_t *val)
{
lsm6dsrx_slv0_config_t slv0_config;
lsm6dsrx_slv0_add_t slv0_add;
@@ -9771,28 +11426,38 @@ int32_t lsm6dsrx_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
- if(ret == 0){
+ if (ret == 0)
+ {
slv0_add.slave0 = (uint8_t) val->slv_add >> 1;
slv0_add.rw_0 = 1;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV0_ADD,
- (uint8_t*)&(slv0_add), 1);
+ (uint8_t *) & (slv0_add), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV0_SUBADD,
- &(val->slv_subadd), 1);
+ &(val->slv_subadd), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv0_config.slave0_numop = val->slv_len;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV0_CONFIG,
- (uint8_t*)&slv0_config, 1);
+ (uint8_t *)&slv0_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -9808,34 +11473,45 @@ int32_t lsm6dsrx_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
- lsm6dsrx_sh_cfg_read_t *val)
+ lsm6dsrx_sh_cfg_read_t *val)
{
lsm6dsrx_slv1_config_t slv1_config;
lsm6dsrx_slv1_add_t slv1_add;
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
- if(ret == 0){
- slv1_add.slave1_add = (uint8_t) (val->slv_add >> 1);
+
+ if (ret == 0)
+ {
+ slv1_add.slave1_add = (uint8_t)(val->slv_add >> 1);
slv1_add.r_1 = 1;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV1_ADD, (uint8_t*)&slv1_add, 1);
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV1_ADD, (uint8_t *)&slv1_add, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV1_SUBADD,
- &(val->slv_subadd), 1);
+ &(val->slv_subadd), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV1_CONFIG,
- (uint8_t*)&slv1_config, 1);
+ (uint8_t *)&slv1_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv1_config.slave1_numop = val->slv_len;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV1_CONFIG,
- (uint8_t*)&slv1_config, 1);
+ (uint8_t *)&slv1_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
-}
+ }
+
return ret;
}
@@ -9851,7 +11527,7 @@ int32_t lsm6dsrx_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
- lsm6dsrx_sh_cfg_read_t *val)
+ lsm6dsrx_sh_cfg_read_t *val)
{
lsm6dsrx_slv2_config_t slv2_config;
lsm6dsrx_slv2_add_t slv2_add;
@@ -9859,28 +11535,38 @@ int32_t lsm6dsrx_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
- if(ret == 0){
- slv2_add.slave2_add = (uint8_t) (val->slv_add >> 1);
+ if (ret == 0)
+ {
+ slv2_add.slave2_add = (uint8_t)(val->slv_add >> 1);
slv2_add.r_2 = 1;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV2_ADD,
- (uint8_t*)&slv2_add, 1);
+ (uint8_t *)&slv2_add, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV2_SUBADD,
- (uint8_t*)&(val->slv_subadd), 1);
+ (uint8_t *) & (val->slv_subadd), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV2_CONFIG,
- (uint8_t*)&slv2_config, 1);
+ (uint8_t *)&slv2_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv2_config.slave2_numop = val->slv_len;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV2_CONFIG,
- (uint8_t*)&slv2_config, 1);
+ (uint8_t *)&slv2_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -9896,7 +11582,7 @@ int32_t lsm6dsrx_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
- lsm6dsrx_sh_cfg_read_t *val)
+ lsm6dsrx_sh_cfg_read_t *val)
{
lsm6dsrx_slv3_config_t slv3_config;
lsm6dsrx_slv3_add_t slv3_add;
@@ -9904,28 +11590,38 @@ int32_t lsm6dsrx_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
- if(ret == 0){
- slv3_add.slave3_add = (uint8_t) (val->slv_add >> 1);
+ if (ret == 0)
+ {
+ slv3_add.slave3_add = (uint8_t)(val->slv_add >> 1);
slv3_add.r_3 = 1;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV3_ADD,
- (uint8_t*)&slv3_add, 1);
+ (uint8_t *)&slv3_add, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV3_SUBADD,
- &(val->slv_subadd), 1);
+ &(val->slv_subadd), 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV3_CONFIG,
- (uint8_t*)&slv3_config, 1);
+ (uint8_t *)&slv3_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
slv3_config.slave3_numop = val->slv_len;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV3_CONFIG,
- (uint8_t*)&slv3_config, 1);
+ (uint8_t *)&slv3_config, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -9938,18 +11634,22 @@ int32_t lsm6dsrx_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_sh_status_get(stmdev_ctx_t *ctx,
- lsm6dsrx_status_master_t *val)
+ lsm6dsrx_status_master_t *val)
{
int32_t ret;
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
- if(ret == 0){
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_MASTER, (uint8_t*)val, 1);
+ if (ret == 0)
+ {
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_MASTER, (uint8_t *)val, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
}
+
return ret;
}
@@ -9975,17 +11675,21 @@ int32_t lsm6dsrx_sh_status_get(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_s4s_tph_res_set(stmdev_ctx_t *ctx,
- lsm6dsrx_s4s_tph_res_t val)
+ lsm6dsrx_s4s_tph_res_t val)
{
lsm6dsrx_s4s_tph_l_t s4s_tph_l;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_TPH_L, (uint8_t*)&s4s_tph_l, 1);
- if(ret == 0){
- s4s_tph_l.tph_h_sel= (uint8_t)val;
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_TPH_L,
+ (uint8_t *)&s4s_tph_l, 1);
+
+ if (ret == 0)
+ {
+ s4s_tph_l.tph_h_sel = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_S4S_TPH_L,
- (uint8_t*)&s4s_tph_l, 1);
+ (uint8_t *)&s4s_tph_l, 1);
}
+
return ret;
}
@@ -9998,24 +11702,29 @@ int32_t lsm6dsrx_s4s_tph_res_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_s4s_tph_res_get(stmdev_ctx_t *ctx,
- lsm6dsrx_s4s_tph_res_t *val)
+ lsm6dsrx_s4s_tph_res_t *val)
{
lsm6dsrx_s4s_tph_l_t s4s_tph_l;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_TPH_L, (uint8_t*)&s4s_tph_l, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_TPH_L,
+ (uint8_t *)&s4s_tph_l, 1);
- switch (s4s_tph_l.tph_h_sel){
+ switch (s4s_tph_l.tph_h_sel)
+ {
case LSM6DSRX_S4S_TPH_7bit:
*val = LSM6DSRX_S4S_TPH_7bit;
break;
+
case LSM6DSRX_S4S_TPH_15bit:
*val = LSM6DSRX_S4S_TPH_15bit;
break;
+
default:
*val = LSM6DSRX_S4S_TPH_7bit;
break;
}
+
return ret;
}
@@ -10034,21 +11743,29 @@ int32_t lsm6dsrx_s4s_tph_val_set(stmdev_ctx_t *ctx, uint16_t val)
lsm6dsrx_s4s_tph_h_t s4s_tph_h;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_TPH_L, (uint8_t*)&s4s_tph_l, 1);
- if(ret == 0){
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_TPH_L,
+ (uint8_t *)&s4s_tph_l, 1);
+
+ if (ret == 0)
+ {
s4s_tph_l.tph_l = (uint8_t)(val & 0x007FU);
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_S4S_TPH_L,
- (uint8_t*)&s4s_tph_l, 1);
+ (uint8_t *)&s4s_tph_l, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_TPH_H,
- (uint8_t*)&s4s_tph_h, 1);
+ (uint8_t *)&s4s_tph_h, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
s4s_tph_h.tph_h = (uint8_t)((val & 0x7F80U) >> 7);
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_S4S_TPH_H,
- (uint8_t*)&s4s_tph_h, 1);
+ (uint8_t *)&s4s_tph_h, 1);
}
+
return ret;
}
@@ -10066,11 +11783,15 @@ int32_t lsm6dsrx_s4s_tph_val_get(stmdev_ctx_t *ctx, uint16_t *val)
lsm6dsrx_s4s_tph_h_t s4s_tph_h;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_TPH_L, (uint8_t*)&s4s_tph_l, 1);
- if(ret == 0){
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_TPH_L,
+ (uint8_t *)&s4s_tph_l, 1);
+
+ if (ret == 0)
+ {
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_TPH_H,
- (uint8_t*)&s4s_tph_h, 1);
+ (uint8_t *)&s4s_tph_h, 1);
}
+
*val = s4s_tph_h.tph_h;
*val = *val << 7;
*val += s4s_tph_l.tph_l;
@@ -10087,16 +11808,19 @@ int32_t lsm6dsrx_s4s_tph_val_get(stmdev_ctx_t *ctx, uint16_t *val)
*
*/
int32_t lsm6dsrx_s4s_res_ratio_set(stmdev_ctx_t *ctx,
- lsm6dsrx_s4s_res_ratio_t val)
+ lsm6dsrx_s4s_res_ratio_t val)
{
lsm6dsrx_s4s_rr_t s4s_rr;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_RR, (uint8_t*)&s4s_rr, 1);
- if(ret == 0){
- s4s_rr.rr= (uint8_t)val;
- ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_S4S_RR, (uint8_t*)&s4s_rr, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_RR, (uint8_t *)&s4s_rr, 1);
+
+ if (ret == 0)
+ {
+ s4s_rr.rr = (uint8_t)val;
+ ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_S4S_RR, (uint8_t *)&s4s_rr, 1);
}
+
return ret;
}
@@ -10109,30 +11833,36 @@ int32_t lsm6dsrx_s4s_res_ratio_set(stmdev_ctx_t *ctx,
*
*/
int32_t lsm6dsrx_s4s_res_ratio_get(stmdev_ctx_t *ctx,
- lsm6dsrx_s4s_res_ratio_t *val)
+ lsm6dsrx_s4s_res_ratio_t *val)
{
lsm6dsrx_s4s_rr_t s4s_rr;
int32_t ret;
- ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_RR, (uint8_t*)&s4s_rr, 1);
+ ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_RR, (uint8_t *)&s4s_rr, 1);
- switch ( s4s_rr.rr){
+ switch (s4s_rr.rr)
+ {
case LSM6DSRX_S4S_DT_RES_11:
*val = LSM6DSRX_S4S_DT_RES_11;
break;
+
case LSM6DSRX_S4S_DT_RES_12:
*val = LSM6DSRX_S4S_DT_RES_12;
break;
+
case LSM6DSRX_S4S_DT_RES_13:
*val = LSM6DSRX_S4S_DT_RES_13;
break;
+
case LSM6DSRX_S4S_DT_RES_14:
*val = LSM6DSRX_S4S_DT_RES_14;
break;
+
default:
*val = LSM6DSRX_S4S_DT_RES_11;
break;
}
+
return ret;
}
@@ -10150,12 +11880,15 @@ int32_t lsm6dsrx_s4s_command_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_ST_CMD_CODE,
- (uint8_t*)&s4s_st_cmd_code, 1);
- if(ret == 0){
- s4s_st_cmd_code.s4s_st_cmd_code= (uint8_t)val;
+ (uint8_t *)&s4s_st_cmd_code, 1);
+
+ if (ret == 0)
+ {
+ s4s_st_cmd_code.s4s_st_cmd_code = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_S4S_ST_CMD_CODE,
- (uint8_t*)&s4s_st_cmd_code, 1);
+ (uint8_t *)&s4s_st_cmd_code, 1);
}
+
return ret;
}
@@ -10173,7 +11906,7 @@ int32_t lsm6dsrx_s4s_command_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_ST_CMD_CODE,
- (uint8_t*)&s4s_st_cmd_code, 1);
+ (uint8_t *)&s4s_st_cmd_code, 1);
*val = s4s_st_cmd_code.s4s_st_cmd_code;
return ret;
@@ -10193,12 +11926,15 @@ int32_t lsm6dsrx_s4s_dt_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_DT_REG,
- (uint8_t*)&s4s_dt_reg, 1);
- if(ret == 0){
+ (uint8_t *)&s4s_dt_reg, 1);
+
+ if (ret == 0)
+ {
s4s_dt_reg.dt = (uint8_t)val;
ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_S4S_DT_REG,
- (uint8_t*)&s4s_dt_reg, 1);
+ (uint8_t *)&s4s_dt_reg, 1);
}
+
return ret;
}
@@ -10216,7 +11952,7 @@ int32_t lsm6dsrx_s4s_dt_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_DT_REG,
- (uint8_t*)&s4s_dt_reg, 1);
+ (uint8_t *)&s4s_dt_reg, 1);
*val = s4s_dt_reg.dt;
return ret;
diff --git a/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.h b/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.h
index f9334b5e0f0e9997265431b12c48f67074201d14..9b52bf99903829f02f62aa33ce0ccaa81ae8680f 100644
--- a/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.h
+++ b/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file lsm6dsrx_reg.h
- * @author Sensor Solutions Software Team
- * @brief This file contains all the functions prototypes for the
- * lsm6dsrx_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lsm6dsrx_reg.h
+ * @author Sensor Solutions Software Team
+ * @brief This file contains all the functions prototypes for the
+ * lsm6dsrx_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LSM6DSRX_REGS_H
#define LSM6DSRX_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup LSM6DSRX
@@ -74,7 +75,8 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
@@ -107,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -139,7 +142,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -174,18 +178,22 @@ typedef struct {
*/
#define LSM6DSRX_FUNC_CFG_ACCESS 0x01U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 6;
- uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */
+uint8_t reg_access :
+ 2; /* shub_reg_access + func_cfg_access */
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */
+uint8_t reg_access :
+ 2; /* shub_reg_access + func_cfg_access */
uint8_t not_used_01 : 6;
#endif /* DRV_BYTE_ORDER */
} lsm6dsrx_func_cfg_access_t;
#define LSM6DSRX_PIN_CTRL 0x02U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 6;
uint8_t sdo_pu_en : 1;
@@ -198,7 +206,8 @@ typedef struct {
} lsm6dsrx_pin_ctrl_t;
#define LSM6DSRX_S4S_TPH_L 0x04U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tph_l : 7;
uint8_t tph_h_sel : 1;
@@ -209,12 +218,14 @@ typedef struct {
} lsm6dsrx_s4s_tph_l_t;
#define LSM6DSRX_S4S_TPH_H 0x05U
-typedef struct {
+typedef struct
+{
uint8_t tph_h : 8;
} lsm6dsrx_s4s_tph_h_t;
#define LSM6DSRX_S4S_RR 0x06U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t rr : 2;
uint8_t not_used_01 : 6;
@@ -225,12 +236,14 @@ typedef struct {
} lsm6dsrx_s4s_rr_t;
#define LSM6DSRX_FIFO_CTRL1 0x07U
-typedef struct {
+typedef struct
+{
uint8_t wtm : 8;
} lsm6dsrx_fifo_ctrl1_t;
#define LSM6DSRX_FIFO_CTRL2 0x08U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wtm : 1;
uint8_t uncoptr_rate : 2;
@@ -251,7 +264,8 @@ typedef struct {
} lsm6dsrx_fifo_ctrl2_t;
#define LSM6DSRX_FIFO_CTRL3 0x09U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bdr_xl : 4;
uint8_t bdr_gy : 4;
@@ -262,7 +276,8 @@ typedef struct {
} lsm6dsrx_fifo_ctrl3_t;
#define LSM6DSRX_FIFO_CTRL4 0x0AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fifo_mode : 3;
uint8_t not_used_01 : 1;
@@ -277,7 +292,8 @@ typedef struct {
} lsm6dsrx_fifo_ctrl4_t;
#define LSM6DSRX_COUNTER_BDR_REG1 0x0BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t cnt_bdr_th : 3;
uint8_t not_used_01 : 2;
@@ -294,12 +310,14 @@ typedef struct {
} lsm6dsrx_counter_bdr_reg1_t;
#define LSM6DSRX_COUNTER_BDR_REG2 0x0CU
-typedef struct {
+typedef struct
+{
uint8_t cnt_bdr_th : 8;
} lsm6dsrx_counter_bdr_reg2_t;
#define LSM6DSRX_INT1_CTRL 0x0DU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_drdy_xl : 1;
uint8_t int1_drdy_g : 1;
@@ -322,7 +340,8 @@ typedef struct {
} lsm6dsrx_int1_ctrl_t;
#define LSM6DSRX_INT2_CTRL 0x0EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_drdy_xl : 1;
uint8_t int2_drdy_g : 1;
@@ -346,7 +365,8 @@ typedef struct {
#define LSM6DSRX_WHO_AM_I 0x0FU
#define LSM6DSRX_CTRL1_XL 0x10U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t lpf2_xl_en : 1;
@@ -361,7 +381,8 @@ typedef struct {
} lsm6dsrx_ctrl1_xl_t;
#define LSM6DSRX_CTRL2_G 0x11U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fs_g : 4; /* fs_4000 + fs_125 + fs_g */
uint8_t odr_g : 4;
@@ -372,7 +393,8 @@ typedef struct {
} lsm6dsrx_ctrl2_g_t;
#define LSM6DSRX_CTRL3_C 0x12U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sw_reset : 1;
uint8_t not_used_01 : 1;
@@ -395,7 +417,8 @@ typedef struct {
} lsm6dsrx_ctrl3_c_t;
#define LSM6DSRX_CTRL4_C 0x13U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t lpf1_sel_g : 1;
@@ -418,7 +441,8 @@ typedef struct {
} lsm6dsrx_ctrl4_c_t;
#define LSM6DSRX_CTRL5_C 0x14U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_xl : 2;
uint8_t st_g : 2;
@@ -435,14 +459,17 @@ typedef struct {
} lsm6dsrx_ctrl5_c_t;
#define LSM6DSRX_CTRL6_C 0x15U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ftype : 3;
uint8_t usr_off_w : 1;
uint8_t xl_hm_mode : 1;
- uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */
+uint8_t den_mode :
+ 3; /* trig_en + lvl1_en + lvl2_en */
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */
+uint8_t den_mode :
+ 3; /* trig_en + lvl1_en + lvl2_en */
uint8_t xl_hm_mode : 1;
uint8_t usr_off_w : 1;
uint8_t ftype : 3;
@@ -450,7 +477,8 @@ typedef struct {
} lsm6dsrx_ctrl6_c_t;
#define LSM6DSRX_CTRL7_G 0x16U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ois_on : 1;
uint8_t usr_off_on_out : 1;
@@ -471,7 +499,8 @@ typedef struct {
} lsm6dsrx_ctrl7_g_t;
#define LSM6DSRX_CTRL8_XL 0x17U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t low_pass_on_6d : 1;
uint8_t not_used_01 : 1;
@@ -490,7 +519,8 @@ typedef struct {
} lsm6dsrx_ctrl8_xl_t;
#define LSM6DSRX_CTRL9_XL 0x18U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t i3c_disable : 1;
@@ -511,7 +541,8 @@ typedef struct {
} lsm6dsrx_ctrl9_xl_t;
#define LSM6DSRX_CTRL10_C 0x19U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 5;
uint8_t timestamp_en : 1;
@@ -524,7 +555,8 @@ typedef struct {
} lsm6dsrx_ctrl10_c_t;
#define LSM6DSRX_ALL_INT_SRC 0x1AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ia : 1;
uint8_t wu_ia : 1;
@@ -547,7 +579,8 @@ typedef struct {
} lsm6dsrx_all_int_src_t;
#define LSM6DSRX_WAKE_UP_SRC 0x1BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_wu : 1;
uint8_t y_wu : 1;
@@ -570,7 +603,8 @@ typedef struct {
} lsm6dsrx_wake_up_src_t;
#define LSM6DSRX_TAP_SRC 0x1CU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_tap : 1;
uint8_t y_tap : 1;
@@ -593,7 +627,8 @@ typedef struct {
} lsm6dsrx_tap_src_t;
#define LSM6DSRX_D6D_SRC 0x1DU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
@@ -616,7 +651,8 @@ typedef struct {
} lsm6dsrx_d6d_src_t;
#define LSM6DSRX_STATUS_REG 0x1EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlda : 1;
uint8_t gda : 1;
@@ -631,7 +667,8 @@ typedef struct {
} lsm6dsrx_status_reg_t;
#define LSM6DSRX_STATUS_SPIAUX 0x1EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlda : 1;
uint8_t gda : 1;
@@ -660,7 +697,8 @@ typedef struct {
#define LSM6DSRX_OUTZ_L_A 0x2CU
#define LSM6DSRX_OUTZ_H_A 0x2DU
#define LSM6DSRX_EMB_FUNC_STATUS_MAINPAGE 0x35U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t is_step_det : 1;
@@ -679,7 +717,8 @@ typedef struct {
} lsm6dsrx_emb_func_status_mainpage_t;
#define LSM6DSRX_FSM_STATUS_A_MAINPAGE 0x36U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_fsm1 : 1;
uint8_t is_fsm2 : 1;
@@ -702,7 +741,8 @@ typedef struct {
} lsm6dsrx_fsm_status_a_mainpage_t;
#define LSM6DSRX_FSM_STATUS_B_MAINPAGE 0x37U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_fsm9 : 1;
uint8_t is_fsm10 : 1;
@@ -725,7 +765,8 @@ typedef struct {
} lsm6dsrx_fsm_status_b_mainpage_t;
#define LSM6DSRX_MLC_STATUS_MAINPAGE 0x38U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_mlc1 : 1;
uint8_t is_mlc2 : 1;
@@ -748,7 +789,8 @@ typedef struct {
} lsm6dsrx_mlc_status_mainpage_t;
#define LSM6DSRX_STATUS_MASTER_MAINPAGE 0x39U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sens_hub_endop : 1;
uint8_t not_used_01 : 2;
@@ -769,12 +811,14 @@ typedef struct {
} lsm6dsrx_status_master_mainpage_t;
#define LSM6DSRX_FIFO_STATUS1 0x3AU
-typedef struct {
+typedef struct
+{
uint8_t diff_fifo : 8;
} lsm6dsrx_fifo_status1_t;
#define LSM6DSRX_FIFO_STATUS2 0x3BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t diff_fifo : 2;
uint8_t not_used_01 : 1;
@@ -799,7 +843,8 @@ typedef struct {
#define LSM6DSRX_TIMESTAMP2 0x42U
#define LSM6DSRX_TIMESTAMP3 0x43U
#define LSM6DSRX_TAP_CFG0 0x56U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lir : 1;
uint8_t tap_z_en : 1;
@@ -822,7 +867,8 @@ typedef struct {
} lsm6dsrx_tap_cfg0_t;
#define LSM6DSRX_TAP_CFG1 0x57U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_ths_x : 5;
uint8_t tap_priority : 3;
@@ -833,7 +879,8 @@ typedef struct {
} lsm6dsrx_tap_cfg1_t;
#define LSM6DSRX_TAP_CFG2 0x58U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_ths_y : 5;
uint8_t inact_en : 2;
@@ -846,7 +893,8 @@ typedef struct {
} lsm6dsrx_tap_cfg2_t;
#define LSM6DSRX_TAP_THS_6D 0x59U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_ths_z : 5;
uint8_t sixd_ths : 2;
@@ -859,7 +907,8 @@ typedef struct {
} lsm6dsrx_tap_ths_6d_t;
#define LSM6DSRX_INT_DUR2 0x5AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shock : 2;
uint8_t quiet : 2;
@@ -872,7 +921,8 @@ typedef struct {
} lsm6dsrx_int_dur2_t;
#define LSM6DSRX_WAKE_UP_THS 0x5BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wk_ths : 6;
uint8_t usr_off_on_wu : 1;
@@ -885,7 +935,8 @@ typedef struct {
} lsm6dsrx_wake_up_ths_t;
#define LSM6DSRX_WAKE_UP_DUR 0x5CU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sleep_dur : 4;
uint8_t wake_ths_w : 1;
@@ -900,7 +951,8 @@ typedef struct {
} lsm6dsrx_wake_up_dur_t;
#define LSM6DSRX_FREE_FALL 0x5DU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ths : 3;
uint8_t ff_dur : 5;
@@ -911,7 +963,8 @@ typedef struct {
} lsm6dsrx_free_fall_t;
#define LSM6DSRX_MD1_CFG 0x5EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_shub : 1;
uint8_t int1_emb_func : 1;
@@ -934,7 +987,8 @@ typedef struct {
} lsm6dsrx_md1_cfg_t;
#define LSM6DSRX_MD2_CFG 0x5FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_timestamp : 1;
uint8_t int2_emb_func : 1;
@@ -957,17 +1011,20 @@ typedef struct {
} lsm6dsrx_md2_cfg_t;
#define LSM6DSRX_S4S_ST_CMD_CODE 0x60U
-typedef struct {
+typedef struct
+{
uint8_t s4s_st_cmd_code : 8;
} lsm6dsrx_s4s_st_cmd_code_t;
#define LSM6DSRX_S4S_DT_REG 0x61U
-typedef struct {
+typedef struct
+{
uint8_t dt : 8;
} lsm6dsrx_s4s_dt_reg_t;
#define LSM6DSRX_I3C_BUS_AVB 0x62U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t pd_dis_int1 : 1;
uint8_t not_used_01 : 2;
@@ -982,12 +1039,14 @@ typedef struct {
} lsm6dsrx_i3c_bus_avb_t;
#define LSM6DSRX_INTERNAL_FREQ_FINE 0x63U
-typedef struct {
+typedef struct
+{
uint8_t freq_fine : 8;
} lsm6dsrx_internal_freq_fine_t;
#define LSM6DSRX_INT_OIS 0x6FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_xl_ois : 2;
uint8_t not_used_01 : 3;
@@ -1004,7 +1063,8 @@ typedef struct {
} lsm6dsrx_int_ois_t;
#define LSM6DSRX_CTRL1_OIS 0x70U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ois_en_spi2 : 1;
uint8_t fs_125_ois : 1;
@@ -1025,7 +1085,8 @@ typedef struct {
} lsm6dsrx_ctrl1_ois_t;
#define LSM6DSRX_CTRL2_OIS 0x71U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t hp_en_ois : 1;
uint8_t ftype_ois : 2;
@@ -1042,7 +1103,8 @@ typedef struct {
} lsm6dsrx_ctrl2_ois_t;
#define LSM6DSRX_CTRL3_OIS 0x72U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_ois_clampdis : 1;
uint8_t st_ois : 2;
@@ -1060,7 +1122,8 @@ typedef struct {
#define LSM6DSRX_Y_OFS_USR 0x74U
#define LSM6DSRX_Z_OFS_USR 0x75U
#define LSM6DSRX_FIFO_DATA_OUT_TAG 0x78U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tag_parity : 1;
uint8_t tag_cnt : 2;
@@ -1079,7 +1142,8 @@ typedef struct {
#define LSM6DSRX_FIFO_DATA_OUT_Z_L 0x7DU
#define LSM6DSRX_FIFO_DATA_OUT_Z_H 0x7EU
#define LSM6DSRX_PAGE_SEL 0x02U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 4;
uint8_t page_sel : 4;
@@ -1090,7 +1154,8 @@ typedef struct {
} lsm6dsrx_page_sel_t;
#define LSM6DSRX_EMB_FUNC_EN_A 0x04U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t pedo_en : 1;
@@ -1107,7 +1172,8 @@ typedef struct {
} lsm6dsrx_emb_func_en_a_t;
#define LSM6DSRX_EMB_FUNC_EN_B 0x05U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fsm_en : 1;
uint8_t not_used_01 : 2;
@@ -1124,17 +1190,20 @@ typedef struct {
} lsm6dsrx_emb_func_en_b_t;
#define LSM6DSRX_PAGE_ADDRESS 0x08U
-typedef struct {
+typedef struct
+{
uint8_t page_addr : 8;
} lsm6dsrx_page_address_t;
#define LSM6DSRX_PAGE_VALUE 0x09U
-typedef struct {
+typedef struct
+{
uint8_t page_value : 8;
} lsm6dsrx_page_value_t;
#define LSM6DSRX_EMB_FUNC_INT1 0x0AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t int1_step_detector : 1;
@@ -1153,7 +1222,8 @@ typedef struct {
} lsm6dsrx_emb_func_int1_t;
#define LSM6DSRX_FSM_INT1_A 0x0BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_fsm1 : 1;
uint8_t int1_fsm2 : 1;
@@ -1176,7 +1246,8 @@ typedef struct {
} lsm6dsrx_fsm_int1_a_t;
#define LSM6DSRX_FSM_INT1_B 0x0CU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_fsm9 : 1;
uint8_t int1_fsm10 : 1;
@@ -1199,7 +1270,8 @@ typedef struct {
} lsm6dsrx_fsm_int1_b_t;
#define LSM6DSRX_MLC_INT1 0x0DU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_mlc1 : 1;
uint8_t int1_mlc2 : 1;
@@ -1222,7 +1294,8 @@ typedef struct {
} lsm6dsrx_mlc_int1_t;
#define LSM6DSRX_EMB_FUNC_INT2 0x0EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t int2_step_detector : 1;
@@ -1241,7 +1314,8 @@ typedef struct {
} lsm6dsrx_emb_func_int2_t;
#define LSM6DSRX_FSM_INT2_A 0x0FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_fsm1 : 1;
uint8_t int2_fsm2 : 1;
@@ -1264,7 +1338,8 @@ typedef struct {
} lsm6dsrx_fsm_int2_a_t;
#define LSM6DSRX_FSM_INT2_B 0x10U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_fsm9 : 1;
uint8_t int2_fsm10 : 1;
@@ -1287,7 +1362,8 @@ typedef struct {
} lsm6dsrx_fsm_int2_b_t;
#define LSM6DSRX_MLC_INT2 0x11U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_mlc1 : 1;
uint8_t int2_mlc2 : 1;
@@ -1310,7 +1386,8 @@ typedef struct {
} lsm6dsrx_mlc_int2_t;
#define LSM6DSRX_EMB_FUNC_STATUS 0x12U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t is_step_det : 1;
@@ -1329,7 +1406,8 @@ typedef struct {
} lsm6dsrx_emb_func_status_t;
#define LSM6DSRX_FSM_STATUS_A 0x13U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_fsm1 : 1;
uint8_t is_fsm2 : 1;
@@ -1352,7 +1430,8 @@ typedef struct {
} lsm6dsrx_fsm_status_a_t;
#define LSM6DSRX_FSM_STATUS_B 0x14U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_fsm9 : 1;
uint8_t is_fsm10 : 1;
@@ -1375,7 +1454,8 @@ typedef struct {
} lsm6dsrx_fsm_status_b_t;
#define LSM6DSRX_MLC_STATUS 0x15U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_mlc1 : 1;
uint8_t is_mlc2 : 1;
@@ -1398,7 +1478,8 @@ typedef struct {
} lsm6dsrx_mlc_status_t;
#define LSM6DSRX_PAGE_RW 0x17U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 5;
uint8_t page_rw : 2; /* page_write + page_read */
@@ -1411,7 +1492,8 @@ typedef struct {
} lsm6dsrx_page_rw_t;
#define LSM6DSRX_EMB_FUNC_FIFO_CFG 0x44U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 6;
uint8_t pedo_fifo_en : 1;
@@ -1424,7 +1506,8 @@ typedef struct {
} lsm6dsrx_emb_func_fifo_cfg_t;
#define LSM6DSRX_FSM_ENABLE_A 0x46U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fsm1_en : 1;
uint8_t fsm2_en : 1;
@@ -1447,7 +1530,8 @@ typedef struct {
} lsm6dsrx_fsm_enable_a_t;
#define LSM6DSRX_FSM_ENABLE_B 0x47U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fsm9_en : 1;
uint8_t fsm10_en : 1;
@@ -1472,18 +1556,22 @@ typedef struct {
#define LSM6DSRX_FSM_LONG_COUNTER_L 0x48U
#define LSM6DSRX_FSM_LONG_COUNTER_H 0x49U
#define LSM6DSRX_FSM_LONG_COUNTER_CLEAR 0x4AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */
+uint8_t fsm_lc_clr :
+ 2; /* fsm_lc_cleared + fsm_lc_clear */
uint8_t not_used_01 : 6;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used_01 : 6;
- uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */
+uint8_t fsm_lc_clr :
+ 2; /* fsm_lc_cleared + fsm_lc_clear */
#endif /* DRV_BYTE_ORDER */
} lsm6dsrx_fsm_long_counter_clear_t;
#define LSM6DSRX_FSM_OUTS1 0x4CU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1506,7 +1594,8 @@ typedef struct {
} lsm6dsrx_fsm_outs1_t;
#define LSM6DSRX_FSM_OUTS2 0x4DU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1529,7 +1618,8 @@ typedef struct {
} lsm6dsrx_fsm_outs2_t;
#define LSM6DSRX_FSM_OUTS3 0x4EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1552,7 +1642,8 @@ typedef struct {
} lsm6dsrx_fsm_outs3_t;
#define LSM6DSRX_FSM_OUTS4 0x4FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1575,7 +1666,8 @@ typedef struct {
} lsm6dsrx_fsm_outs4_t;
#define LSM6DSRX_FSM_OUTS5 0x50U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1598,7 +1690,8 @@ typedef struct {
} lsm6dsrx_fsm_outs5_t;
#define LSM6DSRX_FSM_OUTS6 0x51U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1621,7 +1714,8 @@ typedef struct {
} lsm6dsrx_fsm_outs6_t;
#define LSM6DSRX_FSM_OUTS7 0x52U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1644,7 +1738,8 @@ typedef struct {
} lsm6dsrx_fsm_outs7_t;
#define LSM6DSRX_FSM_OUTS8 0x53U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1667,7 +1762,8 @@ typedef struct {
} lsm6dsrx_fsm_outs8_t;
#define LSM6DSRX_FSM_OUTS9 0x54U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1690,7 +1786,8 @@ typedef struct {
} lsm6dsrx_fsm_outs9_t;
#define LSM6DSRX_FSM_OUTS10 0x55U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1713,7 +1810,8 @@ typedef struct {
} lsm6dsrx_fsm_outs10_t;
#define LSM6DSRX_FSM_OUTS11 0x56U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1736,7 +1834,8 @@ typedef struct {
} lsm6dsrx_fsm_outs11_t;
#define LSM6DSRX_FSM_OUTS12 0x57U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1759,7 +1858,8 @@ typedef struct {
} lsm6dsrx_fsm_outs12_t;
#define LSM6DSRX_FSM_OUTS13 0x58U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1782,7 +1882,8 @@ typedef struct {
} lsm6dsrx_fsm_outs13_t;
#define LSM6DSRX_FSM_OUTS14 0x59U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1805,7 +1906,8 @@ typedef struct {
} lsm6dsrx_fsm_outs14_t;
#define LSM6DSRX_FSM_OUTS15 0x5AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1828,7 +1930,8 @@ typedef struct {
} lsm6dsrx_fsm_outs15_t;
#define LSM6DSRX_FSM_OUTS16 0x5BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t n_v : 1;
uint8_t p_v : 1;
@@ -1851,7 +1954,8 @@ typedef struct {
} lsm6dsrx_fsm_outs16_t;
#define LSM6DSRX_EMB_FUNC_ODR_CFG_B 0x5FU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t fsm_odr : 2;
@@ -1864,7 +1968,8 @@ typedef struct {
} lsm6dsrx_emb_func_odr_cfg_b_t;
#define LSM6DSRX_EMB_FUNC_ODR_CFG_C 0x60U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 4;
uint8_t mlc_odr : 2;
@@ -1879,7 +1984,8 @@ typedef struct {
#define LSM6DSRX_STEP_COUNTER_L 0x62U
#define LSM6DSRX_STEP_COUNTER_H 0x63U
#define LSM6DSRX_EMB_FUNC_SRC 0x64U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t stepcounter_bit_set : 1;
@@ -1900,7 +2006,8 @@ typedef struct {
} lsm6dsrx_emb_func_src_t;
#define LSM6DSRX_EMB_FUNC_INIT_A 0x66U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t step_det_init : 1;
@@ -1917,7 +2024,8 @@ typedef struct {
} lsm6dsrx_emb_func_init_a_t;
#define LSM6DSRX_EMB_FUNC_INIT_B 0x67U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fsm_init : 1;
uint8_t not_used_01 : 2;
@@ -1960,7 +2068,8 @@ typedef struct {
#define LSM6DSRX_MAG_SI_ZZ_L 0xD0U
#define LSM6DSRX_MAG_SI_ZZ_H 0xD1U
#define LSM6DSRX_MAG_CFG_A 0xD4U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t mag_z_axis : 3;
uint8_t not_used_01 : 1;
@@ -1975,7 +2084,8 @@ typedef struct {
} lsm6dsrx_mag_cfg_a_t;
#define LSM6DSRX_MAG_CFG_B 0xD5U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t mag_x_axis : 3;
uint8_t not_used_01 : 5;
@@ -1991,7 +2101,8 @@ typedef struct {
#define LSM6DSRX_FSM_START_ADD_L 0x17EU
#define LSM6DSRX_FSM_START_ADD_H 0x17FU
#define LSM6DSRX_PEDO_CMD_REG 0x183U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t carry_count_en : 1;
@@ -2011,421 +2122,440 @@ typedef struct {
#define LSM6DSRX_MLC_MAG_SENSITIVITY_H 0x1E9U
#define LSM6DSRX_SENSOR_HUB_1 0x02U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} lsm6dsrx_sensor_hub_1_t;
#define LSM6DSRX_SENSOR_HUB_2 0x03U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} lsm6dsrx_sensor_hub_2_t;
#define LSM6DSRX_SENSOR_HUB_3 0x04U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} lsm6dsrx_sensor_hub_3_t;
#define LSM6DSRX_SENSOR_HUB_4 0x05U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} lsm6dsrx_sensor_hub_4_t;
#define LSM6DSRX_SENSOR_HUB_5 0x06U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} lsm6dsrx_sensor_hub_5_t;
#define LSM6DSRX_SENSOR_HUB_6 0x07U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} lsm6dsrx_sensor_hub_6_t;
#define LSM6DSRX_SENSOR_HUB_7 0x08U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} lsm6dsrx_sensor_hub_7_t;
#define LSM6DSRX_SENSOR_HUB_8 0x09U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} lsm6dsrx_sensor_hub_8_t;
#define LSM6DSRX_SENSOR_HUB_9 0x0AU
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} lsm6dsrx_sensor_hub_9_t;
#define LSM6DSRX_SENSOR_HUB_10 0x0BU
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} lsm6dsrx_sensor_hub_10_t;
#define LSM6DSRX_SENSOR_HUB_11 0x0CU
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} lsm6dsrx_sensor_hub_11_t;
#define LSM6DSRX_SENSOR_HUB_12 0x0DU
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} lsm6dsrx_sensor_hub_12_t;
#define LSM6DSRX_SENSOR_HUB_13 0x0EU
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} lsm6dsrx_sensor_hub_13_t;
#define LSM6DSRX_SENSOR_HUB_14 0x0FU
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} lsm6dsrx_sensor_hub_14_t;
#define LSM6DSRX_SENSOR_HUB_15 0x10U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} lsm6dsrx_sensor_hub_15_t;
#define LSM6DSRX_SENSOR_HUB_16 0x11U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} lsm6dsrx_sensor_hub_16_t;
#define LSM6DSRX_SENSOR_HUB_17 0x12U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} lsm6dsrx_sensor_hub_17_t;
#define LSM6DSRX_SENSOR_HUB_18 0x13U
-typedef struct {
-#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
- uint8_t bit0 : 1;
- uint8_t bit1 : 1;
- uint8_t bit2 : 1;
- uint8_t bit3 : 1;
- uint8_t bit4 : 1;
- uint8_t bit5 : 1;
- uint8_t bit6 : 1;
- uint8_t bit7 : 1;
-#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
- uint8_t bit7 : 1;
- uint8_t bit6 : 1;
- uint8_t bit5 : 1;
- uint8_t bit4 : 1;
- uint8_t bit3 : 1;
- uint8_t bit2 : 1;
- uint8_t bit1 : 1;
- uint8_t bit0 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t bit0 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} lsm6dsrx_sensor_hub_18_t;
#define LSM6DSRX_MASTER_CONFIG 0x14U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t aux_sens_on : 2;
uint8_t master_on : 1;
@@ -2446,7 +2576,8 @@ typedef struct {
} lsm6dsrx_master_config_t;
#define LSM6DSRX_SLV0_ADD 0x15U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t rw_0 : 1;
uint8_t slave0 : 7;
@@ -2457,12 +2588,14 @@ typedef struct {
} lsm6dsrx_slv0_add_t;
#define LSM6DSRX_SLV0_SUBADD 0x16U
-typedef struct {
+typedef struct
+{
uint8_t slave0_reg : 8;
} lsm6dsrx_slv0_subadd_t;
#define LSM6DSRX_SLV0_CONFIG 0x17U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave0_numop : 3;
uint8_t batch_ext_sens_0_en : 1;
@@ -2477,7 +2610,8 @@ typedef struct {
} lsm6dsrx_slv0_config_t;
#define LSM6DSRX_SLV1_ADD 0x18U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_1 : 1;
uint8_t slave1_add : 7;
@@ -2488,12 +2622,14 @@ typedef struct {
} lsm6dsrx_slv1_add_t;
#define LSM6DSRX_SLV1_SUBADD 0x19U
-typedef struct {
+typedef struct
+{
uint8_t slave1_reg : 8;
} lsm6dsrx_slv1_subadd_t;
#define LSM6DSRX_SLV1_CONFIG 0x1AU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave1_numop : 3;
uint8_t batch_ext_sens_1_en : 1;
@@ -2506,7 +2642,8 @@ typedef struct {
} lsm6dsrx_slv1_config_t;
#define LSM6DSRX_SLV2_ADD 0x1BU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_2 : 1;
uint8_t slave2_add : 7;
@@ -2517,12 +2654,14 @@ typedef struct {
} lsm6dsrx_slv2_add_t;
#define LSM6DSRX_SLV2_SUBADD 0x1CU
-typedef struct {
+typedef struct
+{
uint8_t slave2_reg : 8;
} lsm6dsrx_slv2_subadd_t;
#define LSM6DSRX_SLV2_CONFIG 0x1DU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave2_numop : 3;
uint8_t batch_ext_sens_2_en : 1;
@@ -2535,7 +2674,8 @@ typedef struct {
} lsm6dsrx_slv2_config_t;
#define LSM6DSRX_SLV3_ADD 0x1EU
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t r_3 : 1;
uint8_t slave3_add : 7;
@@ -2546,12 +2686,14 @@ typedef struct {
} lsm6dsrx_slv3_add_t;
#define LSM6DSRX_SLV3_SUBADD 0x1FU
-typedef struct {
+typedef struct
+{
uint8_t slave3_reg : 8;
} lsm6dsrx_slv3_subadd_t;
#define LSM6DSRX_SLV3_CONFIG 0x20U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slave3_numop : 3;
uint8_t batch_ext_sens_3_en : 1;
@@ -2564,12 +2706,14 @@ typedef struct {
} lsm6dsrx_slv3_config_t;
#define LSM6DSRX_DATAWRITE_SLV0 0x21U
-typedef struct {
+typedef struct
+{
uint8_t slave0_dataw : 8;
} lsm6dsrx_datawrite_slv0_t;
#define LSM6DSRX_STATUS_MASTER 0x22U
-typedef struct {
+typedef struct
+{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sens_hub_endop : 1;
uint8_t not_used_01 : 2;
@@ -2591,9 +2735,9 @@ typedef struct {
/**
* @defgroup LSM6DSRX_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -2601,7 +2745,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
lsm6dsrx_func_cfg_access_t func_cfg_access;
lsm6dsrx_pin_ctrl_t pin_ctrl;
lsm6dsrx_s4s_tph_l_t s4s_tph_l;
@@ -2740,34 +2885,43 @@ typedef union{
*
*/
-int32_t lsm6dsrx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
- uint16_t len);
-int32_t lsm6dsrx_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lsm6dsrx_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
+int32_t lsm6dsrx_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len);
float_t lsm6dsrx_from_fs2g_to_mg(int16_t lsb);
float_t lsm6dsrx_from_fs4g_to_mg(int16_t lsb);
float_t lsm6dsrx_from_fs8g_to_mg(int16_t lsb);
float_t lsm6dsrx_from_fs16g_to_mg(int16_t lsb);
+
float_t lsm6dsrx_from_fs125dps_to_mdps(int16_t lsb);
float_t lsm6dsrx_from_fs250dps_to_mdps(int16_t lsb);
float_t lsm6dsrx_from_fs500dps_to_mdps(int16_t lsb);
float_t lsm6dsrx_from_fs1000dps_to_mdps(int16_t lsb);
float_t lsm6dsrx_from_fs2000dps_to_mdps(int16_t lsb);
float_t lsm6dsrx_from_fs4000dps_to_mdps(int16_t lsb);
+
float_t lsm6dsrx_from_lsb_to_celsius(int16_t lsb);
+
float_t lsm6dsrx_from_lsb_to_nsec(int32_t lsb);
-typedef enum {
+typedef enum
+{
LSM6DSRX_2g = 0,
LSM6DSRX_16g = 1, /* if XL_FS_MODE = '1' -> LSM6DSRX_2g */
LSM6DSRX_4g = 2,
LSM6DSRX_8g = 3,
} lsm6dsrx_fs_xl_t;
-int32_t lsm6dsrx_xl_full_scale_set(stmdev_ctx_t *ctx, lsm6dsrx_fs_xl_t val);
-int32_t lsm6dsrx_xl_full_scale_get(stmdev_ctx_t *ctx, lsm6dsrx_fs_xl_t *val);
+int32_t lsm6dsrx_xl_full_scale_set(stmdev_ctx_t *ctx,
+ lsm6dsrx_fs_xl_t val);
+int32_t lsm6dsrx_xl_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6dsrx_fs_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_XL_ODR_OFF = 0,
LSM6DSRX_XL_ODR_12Hz5 = 1,
LSM6DSRX_XL_ODR_26Hz = 2,
@@ -2781,10 +2935,13 @@ typedef enum {
LSM6DSRX_XL_ODR_6667Hz = 10,
LSM6DSRX_XL_ODR_6Hz5 = 11, /* (low power only) */
} lsm6dsrx_odr_xl_t;
-int32_t lsm6dsrx_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6dsrx_odr_xl_t val);
-int32_t lsm6dsrx_xl_data_rate_get(stmdev_ctx_t *ctx, lsm6dsrx_odr_xl_t *val);
+int32_t lsm6dsrx_xl_data_rate_set(stmdev_ctx_t *ctx,
+ lsm6dsrx_odr_xl_t val);
+int32_t lsm6dsrx_xl_data_rate_get(stmdev_ctx_t *ctx,
+ lsm6dsrx_odr_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_125dps = 2,
LSM6DSRX_250dps = 0,
LSM6DSRX_500dps = 4,
@@ -2792,10 +2949,13 @@ typedef enum {
LSM6DSRX_2000dps = 12,
LSM6DSRX_4000dps = 1,
} lsm6dsrx_fs_g_t;
-int32_t lsm6dsrx_gy_full_scale_set(stmdev_ctx_t *ctx, lsm6dsrx_fs_g_t val);
-int32_t lsm6dsrx_gy_full_scale_get(stmdev_ctx_t *ctx, lsm6dsrx_fs_g_t *val);
+int32_t lsm6dsrx_gy_full_scale_set(stmdev_ctx_t *ctx,
+ lsm6dsrx_fs_g_t val);
+int32_t lsm6dsrx_gy_full_scale_get(stmdev_ctx_t *ctx,
+ lsm6dsrx_fs_g_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_GY_ODR_OFF = 0,
LSM6DSRX_GY_ODR_12Hz5 = 1,
LSM6DSRX_GY_ODR_26Hz = 2,
@@ -2809,41 +2969,47 @@ typedef enum {
LSM6DSRX_GY_ODR_6667Hz = 10,
} lsm6dsrx_odr_g_t;
int32_t lsm6dsrx_gy_data_rate_set(stmdev_ctx_t *ctx,
- lsm6dsrx_odr_g_t val);
+ lsm6dsrx_odr_g_t val);
int32_t lsm6dsrx_gy_data_rate_get(stmdev_ctx_t *ctx,
- lsm6dsrx_odr_g_t *val);
+ lsm6dsrx_odr_g_t *val);
-int32_t lsm6dsrx_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsrx_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsrx_block_data_update_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsrx_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_LSb_1mg = 0,
LSM6DSRX_LSb_16mg = 1,
} lsm6dsrx_usr_off_w_t;
int32_t lsm6dsrx_xl_offset_weight_set(stmdev_ctx_t *ctx,
- lsm6dsrx_usr_off_w_t val);
+ lsm6dsrx_usr_off_w_t val);
int32_t lsm6dsrx_xl_offset_weight_get(stmdev_ctx_t *ctx,
- lsm6dsrx_usr_off_w_t *val);
+ lsm6dsrx_usr_off_w_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_HIGH_PERFORMANCE_MD = 0,
LSM6DSRX_LOW_NORMAL_POWER_MD = 1,
} lsm6dsrx_xl_hm_mode_t;
int32_t lsm6dsrx_xl_power_mode_set(stmdev_ctx_t *ctx,
- lsm6dsrx_xl_hm_mode_t val);
+ lsm6dsrx_xl_hm_mode_t val);
int32_t lsm6dsrx_xl_power_mode_get(stmdev_ctx_t *ctx,
- lsm6dsrx_xl_hm_mode_t *val);
+ lsm6dsrx_xl_hm_mode_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_GY_HIGH_PERFORMANCE = 0,
LSM6DSRX_GY_NORMAL = 1,
} lsm6dsrx_g_hm_mode_t;
int32_t lsm6dsrx_gy_power_mode_set(stmdev_ctx_t *ctx,
- lsm6dsrx_g_hm_mode_t val);
+ lsm6dsrx_g_hm_mode_t val);
int32_t lsm6dsrx_gy_power_mode_get(stmdev_ctx_t *ctx,
- lsm6dsrx_g_hm_mode_t *val);
+ lsm6dsrx_g_hm_mode_t *val);
-typedef struct {
+typedef struct
+{
lsm6dsrx_all_int_src_t all_int_src;
lsm6dsrx_wake_up_src_t wake_up_src;
lsm6dsrx_tap_src_t tap_src;
@@ -2853,27 +3019,36 @@ typedef struct {
lsm6dsrx_fsm_status_a_t fsm_status_a;
lsm6dsrx_fsm_status_b_t fsm_status_b;
lsm6dsrx_mlc_status_mainpage_t mlc_status;
- } lsm6dsrx_all_sources_t;
+} lsm6dsrx_all_sources_t;
int32_t lsm6dsrx_all_sources_get(stmdev_ctx_t *ctx,
- lsm6dsrx_all_sources_t *val);
+ lsm6dsrx_all_sources_t *val);
int32_t lsm6dsrx_status_reg_get(stmdev_ctx_t *ctx,
- lsm6dsrx_status_reg_t *val);
+ lsm6dsrx_status_reg_t *val);
-int32_t lsm6dsrx_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsrx_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsrx_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsrx_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsrx_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsrx_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsrx_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsrx_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsrx_xl_usr_offset_x_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lsm6dsrx_xl_usr_offset_x_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
-int32_t lsm6dsrx_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsrx_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsrx_xl_usr_offset_y_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lsm6dsrx_xl_usr_offset_y_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
-int32_t lsm6dsrx_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsrx_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsrx_xl_usr_offset_z_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lsm6dsrx_xl_usr_offset_z_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
int32_t lsm6dsrx_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsrx_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -2885,56 +3060,65 @@ int32_t lsm6dsrx_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsrx_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_NO_ROUND = 0,
LSM6DSRX_ROUND_XL = 1,
LSM6DSRX_ROUND_GY = 2,
LSM6DSRX_ROUND_GY_XL = 3,
} lsm6dsrx_rounding_t;
int32_t lsm6dsrx_rounding_mode_set(stmdev_ctx_t *ctx,
- lsm6dsrx_rounding_t val);
+ lsm6dsrx_rounding_t val);
int32_t lsm6dsrx_rounding_mode_get(stmdev_ctx_t *ctx,
- lsm6dsrx_rounding_t *val);
+ lsm6dsrx_rounding_t *val);
int32_t lsm6dsrx_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val);
-int32_t lsm6dsrx_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t lsm6dsrx_angular_rate_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
-int32_t lsm6dsrx_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val);
+int32_t lsm6dsrx_acceleration_raw_get(stmdev_ctx_t *ctx,
+ int16_t *val);
int32_t lsm6dsrx_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsrx_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsrx_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dsrx_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t lsm6dsrx_number_of_steps_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
int32_t lsm6dsrx_steps_reset(stmdev_ctx_t *ctx);
-typedef enum {
+typedef enum
+{
LSM6DSRX_USER_BANK = 0,
LSM6DSRX_SENSOR_HUB_BANK = 1,
LSM6DSRX_EMBEDDED_FUNC_BANK = 2,
} lsm6dsrx_reg_access_t;
-int32_t lsm6dsrx_mem_bank_set(stmdev_ctx_t *ctx, lsm6dsrx_reg_access_t val);
-int32_t lsm6dsrx_mem_bank_get(stmdev_ctx_t *ctx, lsm6dsrx_reg_access_t *val);
+int32_t lsm6dsrx_mem_bank_set(stmdev_ctx_t *ctx,
+ lsm6dsrx_reg_access_t val);
+int32_t lsm6dsrx_mem_bank_get(stmdev_ctx_t *ctx,
+ lsm6dsrx_reg_access_t *val);
int32_t lsm6dsrx_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address,
- uint8_t *val);
+ uint8_t *val);
int32_t lsm6dsrx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address,
- uint8_t *buf, uint8_t len);
+ uint8_t *buf, uint8_t len);
int32_t lsm6dsrx_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add,
- uint8_t *val);
-int32_t lsm6dsrx_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *val);
+ uint8_t *val);
+int32_t lsm6dsrx_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_DRDY_LATCHED = 0,
LSM6DSRX_DRDY_PULSED = 1,
} lsm6dsrx_dataready_pulsed_t;
int32_t lsm6dsrx_data_ready_mode_set(stmdev_ctx_t *ctx,
- lsm6dsrx_dataready_pulsed_t val);
+ lsm6dsrx_dataready_pulsed_t val);
int32_t lsm6dsrx_data_ready_mode_get(stmdev_ctx_t *ctx,
- lsm6dsrx_dataready_pulsed_t *val);
+ lsm6dsrx_dataready_pulsed_t *val);
int32_t lsm6dsrx_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
@@ -2947,21 +3131,27 @@ int32_t lsm6dsrx_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsrx_boot_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsrx_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_XL_ST_DISABLE = 0,
LSM6DSRX_XL_ST_POSITIVE = 1,
LSM6DSRX_XL_ST_NEGATIVE = 2,
} lsm6dsrx_st_xl_t;
-int32_t lsm6dsrx_xl_self_test_set(stmdev_ctx_t *ctx, lsm6dsrx_st_xl_t val);
-int32_t lsm6dsrx_xl_self_test_get(stmdev_ctx_t *ctx, lsm6dsrx_st_xl_t *val);
+int32_t lsm6dsrx_xl_self_test_set(stmdev_ctx_t *ctx,
+ lsm6dsrx_st_xl_t val);
+int32_t lsm6dsrx_xl_self_test_get(stmdev_ctx_t *ctx,
+ lsm6dsrx_st_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_GY_ST_DISABLE = 0,
LSM6DSRX_GY_ST_POSITIVE = 1,
LSM6DSRX_GY_ST_NEGATIVE = 3,
} lsm6dsrx_st_g_t;
-int32_t lsm6dsrx_gy_self_test_set(stmdev_ctx_t *ctx, lsm6dsrx_st_g_t val);
-int32_t lsm6dsrx_gy_self_test_get(stmdev_ctx_t *ctx, lsm6dsrx_st_g_t *val);
+int32_t lsm6dsrx_gy_self_test_set(stmdev_ctx_t *ctx,
+ lsm6dsrx_st_g_t val);
+int32_t lsm6dsrx_gy_self_test_get(stmdev_ctx_t *ctx,
+ lsm6dsrx_st_g_t *val);
int32_t lsm6dsrx_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsrx_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -2969,10 +3159,13 @@ int32_t lsm6dsrx_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsrx_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsrx_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dsrx_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsrx_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsrx_filter_settling_mask_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsrx_filter_settling_mask_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_ULTRA_LIGHT = 0,
LSM6DSRX_VERY_LIGHT = 1,
LSM6DSRX_LIGHT = 2,
@@ -2982,13 +3175,16 @@ typedef enum {
LSM6DSRX_AGGRESSIVE = 6,
LSM6DSRX_XTREME = 7,
} lsm6dsrx_ftype_t;
-int32_t lsm6dsrx_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, lsm6dsrx_ftype_t val);
-int32_t lsm6dsrx_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, lsm6dsrx_ftype_t *val);
+int32_t lsm6dsrx_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
+ lsm6dsrx_ftype_t val);
+int32_t lsm6dsrx_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
+ lsm6dsrx_ftype_t *val);
int32_t lsm6dsrx_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsrx_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_HP_PATH_DISABLE_ON_OUT = 0x00,
LSM6DSRX_SLOPE_ODR_DIV_4 = 0x10,
LSM6DSRX_HP_ODR_DIV_10 = 0x11,
@@ -3014,23 +3210,26 @@ typedef enum {
LSM6DSRX_LP_ODR_DIV_800 = 0x07,
} lsm6dsrx_hp_slope_xl_en_t;
int32_t lsm6dsrx_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
- lsm6dsrx_hp_slope_xl_en_t val);
+ lsm6dsrx_hp_slope_xl_en_t val);
int32_t lsm6dsrx_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
- lsm6dsrx_hp_slope_xl_en_t *val);
+ lsm6dsrx_hp_slope_xl_en_t *val);
int32_t lsm6dsrx_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsrx_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsrx_xl_fast_settling_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_USE_SLOPE = 0,
LSM6DSRX_USE_HPF = 1,
} lsm6dsrx_slope_fds_t;
int32_t lsm6dsrx_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
- lsm6dsrx_slope_fds_t val);
+ lsm6dsrx_slope_fds_t val);
int32_t lsm6dsrx_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
- lsm6dsrx_slope_fds_t *val);
+ lsm6dsrx_slope_fds_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_HP_FILTER_NONE = 0x00,
LSM6DSRX_HP_FILTER_16mHz = 0x80,
LSM6DSRX_HP_FILTER_65mHz = 0x81,
@@ -3038,74 +3237,91 @@ typedef enum {
LSM6DSRX_HP_FILTER_1Hz04 = 0x83,
} lsm6dsrx_hpm_g_t;
int32_t lsm6dsrx_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
- lsm6dsrx_hpm_g_t val);
+ lsm6dsrx_hpm_g_t val);
int32_t lsm6dsrx_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
- lsm6dsrx_hpm_g_t *val);
+ lsm6dsrx_hpm_g_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_AUX_PULL_UP_DISC = 0,
LSM6DSRX_AUX_PULL_UP_CONNECT = 1,
} lsm6dsrx_ois_pu_dis_t;
int32_t lsm6dsrx_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx,
- lsm6dsrx_ois_pu_dis_t val);
+ lsm6dsrx_ois_pu_dis_t val);
int32_t lsm6dsrx_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx,
- lsm6dsrx_ois_pu_dis_t *val);
+ lsm6dsrx_ois_pu_dis_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_AUX_ON = 1,
LSM6DSRX_AUX_ON_BY_AUX_INTERFACE = 0,
} lsm6dsrx_ois_on_t;
-int32_t lsm6dsrx_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx, lsm6dsrx_ois_on_t val);
-int32_t lsm6dsrx_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx, lsm6dsrx_ois_on_t *val);
+int32_t lsm6dsrx_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx,
+ lsm6dsrx_ois_on_t val);
+int32_t lsm6dsrx_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx,
+ lsm6dsrx_ois_on_t *val);
int32_t lsm6dsrx_aux_status_reg_get(stmdev_ctx_t *ctx,
- lsm6dsrx_status_spiaux_t *val);
+ lsm6dsrx_status_spiaux_t *val);
-int32_t lsm6dsrx_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsrx_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsrx_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsrx_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsrx_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsrx_aux_gy_flag_settling_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_AUX_XL_DISABLE = 0,
LSM6DSRX_AUX_XL_POS = 1,
LSM6DSRX_AUX_XL_NEG = 2,
} lsm6dsrx_st_xl_ois_t;
int32_t lsm6dsrx_aux_xl_self_test_set(stmdev_ctx_t *ctx,
- lsm6dsrx_st_xl_ois_t val);
+ lsm6dsrx_st_xl_ois_t val);
int32_t lsm6dsrx_aux_xl_self_test_get(stmdev_ctx_t *ctx,
- lsm6dsrx_st_xl_ois_t *val);
+ lsm6dsrx_st_xl_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_AUX_DEN_ACTIVE_LOW = 0,
LSM6DSRX_AUX_DEN_ACTIVE_HIGH = 1,
} lsm6dsrx_den_lh_ois_t;
int32_t lsm6dsrx_aux_den_polarity_set(stmdev_ctx_t *ctx,
- lsm6dsrx_den_lh_ois_t val);
+ lsm6dsrx_den_lh_ois_t val);
int32_t lsm6dsrx_aux_den_polarity_get(stmdev_ctx_t *ctx,
- lsm6dsrx_den_lh_ois_t *val);
+ lsm6dsrx_den_lh_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_AUX_DEN_DISABLE = 0,
LSM6DSRX_AUX_DEN_LEVEL_LATCH = 3,
LSM6DSRX_AUX_DEN_LEVEL_TRIG = 2,
} lsm6dsrx_lvl2_ois_t;
-int32_t lsm6dsrx_aux_den_mode_set(stmdev_ctx_t *ctx, lsm6dsrx_lvl2_ois_t val);
-int32_t lsm6dsrx_aux_den_mode_get(stmdev_ctx_t *ctx, lsm6dsrx_lvl2_ois_t *val);
+int32_t lsm6dsrx_aux_den_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsrx_lvl2_ois_t val);
+int32_t lsm6dsrx_aux_den_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsrx_lvl2_ois_t *val);
int32_t lsm6dsrx_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsrx_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsrx_aux_drdy_on_int2_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_AUX_DISABLE = 0,
LSM6DSRX_MODE_3_GY = 1,
LSM6DSRX_MODE_4_GY_XL = 3,
} lsm6dsrx_ois_en_spi2_t;
-int32_t lsm6dsrx_aux_mode_set(stmdev_ctx_t *ctx, lsm6dsrx_ois_en_spi2_t val);
-int32_t lsm6dsrx_aux_mode_get(stmdev_ctx_t *ctx, lsm6dsrx_ois_en_spi2_t *val);
+int32_t lsm6dsrx_aux_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsrx_ois_en_spi2_t val);
+int32_t lsm6dsrx_aux_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsrx_ois_en_spi2_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_125dps_AUX = 0x04,
LSM6DSRX_250dps_AUX = 0x00,
LSM6DSRX_500dps_AUX = 0x01,
@@ -3113,29 +3329,34 @@ typedef enum {
LSM6DSRX_2000dps_AUX = 0x03,
} lsm6dsrx_fs_g_ois_t;
int32_t lsm6dsrx_aux_gy_full_scale_set(stmdev_ctx_t *ctx,
- lsm6dsrx_fs_g_ois_t val);
+ lsm6dsrx_fs_g_ois_t val);
int32_t lsm6dsrx_aux_gy_full_scale_get(stmdev_ctx_t *ctx,
- lsm6dsrx_fs_g_ois_t *val);
+ lsm6dsrx_fs_g_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_AUX_SPI_4_WIRE = 0,
LSM6DSRX_AUX_SPI_3_WIRE = 1,
} lsm6dsrx_sim_ois_t;
-int32_t lsm6dsrx_aux_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsrx_sim_ois_t val);
-int32_t lsm6dsrx_aux_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsrx_sim_ois_t *val);
+int32_t lsm6dsrx_aux_spi_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsrx_sim_ois_t val);
+int32_t lsm6dsrx_aux_spi_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsrx_sim_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_351Hz39 = 0,
LSM6DSRX_236Hz63 = 1,
LSM6DSRX_172Hz70 = 2,
LSM6DSRX_937Hz91 = 3,
} lsm6dsrx_ftype_ois_t;
int32_t lsm6dsrx_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
- lsm6dsrx_ftype_ois_t val);
+ lsm6dsrx_ftype_ois_t val);
int32_t lsm6dsrx_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
- lsm6dsrx_ftype_ois_t *val);
+ lsm6dsrx_ftype_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_AUX_HP_DISABLE = 0x00,
LSM6DSRX_AUX_HP_Hz016 = 0x10,
LSM6DSRX_AUX_HP_Hz065 = 0x11,
@@ -3143,30 +3364,33 @@ typedef enum {
LSM6DSRX_AUX_HP_1Hz040 = 0x13,
} lsm6dsrx_hpm_ois_t;
int32_t lsm6dsrx_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx,
- lsm6dsrx_hpm_ois_t val);
+ lsm6dsrx_hpm_ois_t val);
int32_t lsm6dsrx_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx,
- lsm6dsrx_hpm_ois_t *val);
+ lsm6dsrx_hpm_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_ENABLE_CLAMP = 0,
LSM6DSRX_DISABLE_CLAMP = 1,
} lsm6dsrx_st_ois_clampdis_t;
int32_t lsm6dsrx_aux_gy_clamp_set(stmdev_ctx_t *ctx,
- lsm6dsrx_st_ois_clampdis_t val);
+ lsm6dsrx_st_ois_clampdis_t val);
int32_t lsm6dsrx_aux_gy_clamp_get(stmdev_ctx_t *ctx,
- lsm6dsrx_st_ois_clampdis_t *val);
+ lsm6dsrx_st_ois_clampdis_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_AUX_GY_DISABLE = 0,
LSM6DSRX_AUX_GY_POS = 1,
LSM6DSRX_AUX_GY_NEG = 3,
} lsm6dsrx_st_ois_t;
int32_t lsm6dsrx_aux_gy_self_test_set(stmdev_ctx_t *ctx,
- lsm6dsrx_st_ois_t val);
+ lsm6dsrx_st_ois_t val);
int32_t lsm6dsrx_aux_gy_self_test_get(stmdev_ctx_t *ctx,
- lsm6dsrx_st_ois_t *val);
+ lsm6dsrx_st_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_631Hz = 0,
LSM6DSRX_295Hz = 1,
LSM6DSRX_140Hz = 2,
@@ -3177,52 +3401,62 @@ typedef enum {
LSM6DSRX_4Hz11 = 7,
} lsm6dsrx_filter_xl_conf_ois_t;
int32_t lsm6dsrx_aux_xl_bandwidth_set(stmdev_ctx_t *ctx,
- lsm6dsrx_filter_xl_conf_ois_t val);
+ lsm6dsrx_filter_xl_conf_ois_t val);
int32_t lsm6dsrx_aux_xl_bandwidth_get(stmdev_ctx_t *ctx,
- lsm6dsrx_filter_xl_conf_ois_t *val);
+ lsm6dsrx_filter_xl_conf_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_AUX_2g = 0,
LSM6DSRX_AUX_16g = 1,
LSM6DSRX_AUX_4g = 2,
LSM6DSRX_AUX_8g = 3,
} lsm6dsrx_fs_xl_ois_t;
int32_t lsm6dsrx_aux_xl_full_scale_set(stmdev_ctx_t *ctx,
- lsm6dsrx_fs_xl_ois_t val);
+ lsm6dsrx_fs_xl_ois_t val);
int32_t lsm6dsrx_aux_xl_full_scale_get(stmdev_ctx_t *ctx,
- lsm6dsrx_fs_xl_ois_t *val);
+ lsm6dsrx_fs_xl_ois_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_PULL_UP_DISC = 0,
LSM6DSRX_PULL_UP_CONNECT = 1,
} lsm6dsrx_sdo_pu_en_t;
-int32_t lsm6dsrx_sdo_sa0_mode_set(stmdev_ctx_t *ctx, lsm6dsrx_sdo_pu_en_t val);
-int32_t lsm6dsrx_sdo_sa0_mode_get(stmdev_ctx_t *ctx, lsm6dsrx_sdo_pu_en_t *val);
+int32_t lsm6dsrx_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsrx_sdo_pu_en_t val);
+int32_t lsm6dsrx_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsrx_sdo_pu_en_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_PULL_DOWN_CONNECT = 0,
LSM6DSRX_PULL_DOWN_DISC = 1,
} lsm6dsrx_pd_dis_int1_t;
-int32_t lsm6dsrx_int1_mode_set(stmdev_ctx_t *ctx, lsm6dsrx_pd_dis_int1_t val);
-int32_t lsm6dsrx_int1_mode_get(stmdev_ctx_t *ctx, lsm6dsrx_pd_dis_int1_t *val);
+int32_t lsm6dsrx_int1_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsrx_pd_dis_int1_t val);
+int32_t lsm6dsrx_int1_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsrx_pd_dis_int1_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_SPI_4_WIRE = 0,
LSM6DSRX_SPI_3_WIRE = 1,
} lsm6dsrx_sim_t;
int32_t lsm6dsrx_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsrx_sim_t val);
int32_t lsm6dsrx_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsrx_sim_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_I2C_ENABLE = 0,
LSM6DSRX_I2C_DISABLE = 1,
} lsm6dsrx_i2c_disable_t;
int32_t lsm6dsrx_i2c_interface_set(stmdev_ctx_t *ctx,
- lsm6dsrx_i2c_disable_t val);
+ lsm6dsrx_i2c_disable_t val);
int32_t lsm6dsrx_i2c_interface_get(stmdev_ctx_t *ctx,
- lsm6dsrx_i2c_disable_t *val);
+ lsm6dsrx_i2c_disable_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_I3C_DISABLE = 0x80,
LSM6DSRX_I3C_ENABLE_T_50us = 0x00,
LSM6DSRX_I3C_ENABLE_T_2us = 0x01,
@@ -3230,11 +3464,12 @@ typedef enum {
LSM6DSRX_I3C_ENABLE_T_25ms = 0x03,
} lsm6dsrx_i3c_disable_t;
int32_t lsm6dsrx_i3c_disable_set(stmdev_ctx_t *ctx,
- lsm6dsrx_i3c_disable_t val);
+ lsm6dsrx_i3c_disable_t val);
int32_t lsm6dsrx_i3c_disable_get(stmdev_ctx_t *ctx,
- lsm6dsrx_i3c_disable_t *val);
+ lsm6dsrx_i3c_disable_t *val);
-typedef struct {
+typedef struct
+{
lsm6dsrx_int1_ctrl_t int1_ctrl;
lsm6dsrx_md1_cfg_t md1_cfg;
lsm6dsrx_emb_func_int1_t emb_func_int1;
@@ -3243,11 +3478,12 @@ typedef struct {
lsm6dsrx_mlc_int1_t mlc_int1;
} lsm6dsrx_pin_int1_route_t;
int32_t lsm6dsrx_pin_int1_route_set(stmdev_ctx_t *ctx,
- lsm6dsrx_pin_int1_route_t *val);
+ lsm6dsrx_pin_int1_route_t *val);
int32_t lsm6dsrx_pin_int1_route_get(stmdev_ctx_t *ctx,
- lsm6dsrx_pin_int1_route_t *val);
+ lsm6dsrx_pin_int1_route_t *val);
-typedef struct {
+typedef struct
+{
lsm6dsrx_int2_ctrl_t int2_ctrl;
lsm6dsrx_md2_cfg_t md2_cfg;
lsm6dsrx_emb_func_int2_t emb_func_int2;
@@ -3256,52 +3492,62 @@ typedef struct {
lsm6dsrx_mlc_int2_t mlc_int2;
} lsm6dsrx_pin_int2_route_t;
int32_t lsm6dsrx_pin_int2_route_set(stmdev_ctx_t *ctx,
- lsm6dsrx_pin_int2_route_t *val);
+ lsm6dsrx_pin_int2_route_t *val);
int32_t lsm6dsrx_pin_int2_route_get(stmdev_ctx_t *ctx,
- lsm6dsrx_pin_int2_route_t *val);
+ lsm6dsrx_pin_int2_route_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_PUSH_PULL = 0,
LSM6DSRX_OPEN_DRAIN = 1,
} lsm6dsrx_pp_od_t;
-int32_t lsm6dsrx_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsrx_pp_od_t val);
-int32_t lsm6dsrx_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsrx_pp_od_t *val);
+int32_t lsm6dsrx_pin_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsrx_pp_od_t val);
+int32_t lsm6dsrx_pin_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsrx_pp_od_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_ACTIVE_HIGH = 0,
LSM6DSRX_ACTIVE_LOW = 1,
} lsm6dsrx_h_lactive_t;
-int32_t lsm6dsrx_pin_polarity_set(stmdev_ctx_t *ctx, lsm6dsrx_h_lactive_t val);
-int32_t lsm6dsrx_pin_polarity_get(stmdev_ctx_t *ctx, lsm6dsrx_h_lactive_t *val);
+int32_t lsm6dsrx_pin_polarity_set(stmdev_ctx_t *ctx,
+ lsm6dsrx_h_lactive_t val);
+int32_t lsm6dsrx_pin_polarity_get(stmdev_ctx_t *ctx,
+ lsm6dsrx_h_lactive_t *val);
int32_t lsm6dsrx_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsrx_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_ALL_INT_PULSED = 0,
LSM6DSRX_BASE_LATCHED_EMB_PULSED = 1,
LSM6DSRX_BASE_PULSED_EMB_LATCHED = 2,
LSM6DSRX_ALL_INT_LATCHED = 3,
} lsm6dsrx_lir_t;
-int32_t lsm6dsrx_int_notification_set(stmdev_ctx_t *ctx, lsm6dsrx_lir_t val);
-int32_t lsm6dsrx_int_notification_get(stmdev_ctx_t *ctx, lsm6dsrx_lir_t *val);
+int32_t lsm6dsrx_int_notification_set(stmdev_ctx_t *ctx,
+ lsm6dsrx_lir_t val);
+int32_t lsm6dsrx_int_notification_get(stmdev_ctx_t *ctx,
+ lsm6dsrx_lir_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_LSb_FS_DIV_64 = 0,
LSM6DSRX_LSb_FS_DIV_256 = 1,
} lsm6dsrx_wake_ths_w_t;
int32_t lsm6dsrx_wkup_ths_weight_set(stmdev_ctx_t *ctx,
- lsm6dsrx_wake_ths_w_t val);
+ lsm6dsrx_wake_ths_w_t val);
int32_t lsm6dsrx_wkup_ths_weight_get(stmdev_ctx_t *ctx,
- lsm6dsrx_wake_ths_w_t *val);
+ lsm6dsrx_wake_ths_w_t *val);
int32_t lsm6dsrx_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsrx_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsrx_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx,
- uint8_t val);
+ uint8_t val);
int32_t lsm6dsrx_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx,
- uint8_t *val);
+ uint8_t *val);
int32_t lsm6dsrx_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsrx_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -3309,42 +3555,51 @@ int32_t lsm6dsrx_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsrx_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsrx_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_DRIVE_SLEEP_CHG_EVENT = 0,
LSM6DSRX_DRIVE_SLEEP_STATUS = 1,
} lsm6dsrx_sleep_status_on_int_t;
int32_t lsm6dsrx_act_pin_notification_set(stmdev_ctx_t *ctx,
- lsm6dsrx_sleep_status_on_int_t val);
+ lsm6dsrx_sleep_status_on_int_t val);
int32_t lsm6dsrx_act_pin_notification_get(stmdev_ctx_t *ctx,
- lsm6dsrx_sleep_status_on_int_t *val);
+ lsm6dsrx_sleep_status_on_int_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_XL_AND_GY_NOT_AFFECTED = 0,
LSM6DSRX_XL_12Hz5_GY_NOT_AFFECTED = 1,
LSM6DSRX_XL_12Hz5_GY_SLEEP = 2,
LSM6DSRX_XL_12Hz5_GY_PD = 3,
} lsm6dsrx_inact_en_t;
int32_t lsm6dsrx_act_mode_set(stmdev_ctx_t *ctx,
- lsm6dsrx_inact_en_t val);
+ lsm6dsrx_inact_en_t val);
int32_t lsm6dsrx_act_mode_get(stmdev_ctx_t *ctx,
- lsm6dsrx_inact_en_t *val);
+ lsm6dsrx_inact_en_t *val);
int32_t lsm6dsrx_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsrx_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dsrx_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsrx_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsrx_tap_detection_on_z_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsrx_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsrx_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsrx_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsrx_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsrx_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsrx_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsrx_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsrx_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsrx_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dsrx_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsrx_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_XYZ = 0,
LSM6DSRX_YXZ = 1,
LSM6DSRX_XZY = 2,
@@ -3353,9 +3608,9 @@ typedef enum {
LSM6DSRX_ZXY = 6,
} lsm6dsrx_tap_priority_t;
int32_t lsm6dsrx_tap_axis_priority_set(stmdev_ctx_t *ctx,
- lsm6dsrx_tap_priority_t val);
+ lsm6dsrx_tap_priority_t val);
int32_t lsm6dsrx_tap_axis_priority_get(stmdev_ctx_t *ctx,
- lsm6dsrx_tap_priority_t *val);
+ lsm6dsrx_tap_priority_t *val);
int32_t lsm6dsrx_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsrx_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -3372,30 +3627,33 @@ int32_t lsm6dsrx_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsrx_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsrx_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_ONLY_SINGLE = 0,
LSM6DSRX_BOTH_SINGLE_DOUBLE = 1,
} lsm6dsrx_single_double_tap_t;
int32_t lsm6dsrx_tap_mode_set(stmdev_ctx_t *ctx,
- lsm6dsrx_single_double_tap_t val);
+ lsm6dsrx_single_double_tap_t val);
int32_t lsm6dsrx_tap_mode_get(stmdev_ctx_t *ctx,
- lsm6dsrx_single_double_tap_t *val);
+ lsm6dsrx_single_double_tap_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_DEG_80 = 0,
LSM6DSRX_DEG_70 = 1,
LSM6DSRX_DEG_60 = 2,
LSM6DSRX_DEG_50 = 3,
} lsm6dsrx_sixd_ths_t;
int32_t lsm6dsrx_6d_threshold_set(stmdev_ctx_t *ctx,
- lsm6dsrx_sixd_ths_t val);
+ lsm6dsrx_sixd_ths_t val);
int32_t lsm6dsrx_6d_threshold_get(stmdev_ctx_t *ctx,
- lsm6dsrx_sixd_ths_t *val);
+ lsm6dsrx_sixd_ths_t *val);
int32_t lsm6dsrx_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsrx_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_FF_TSH_156mg = 0,
LSM6DSRX_FF_TSH_219mg = 1,
LSM6DSRX_FF_TSH_250mg = 2,
@@ -3406,9 +3664,9 @@ typedef enum {
LSM6DSRX_FF_TSH_500mg = 7,
} lsm6dsrx_ff_ths_t;
int32_t lsm6dsrx_ff_threshold_set(stmdev_ctx_t *ctx,
- lsm6dsrx_ff_ths_t val);
+ lsm6dsrx_ff_ths_t val);
int32_t lsm6dsrx_ff_threshold_get(stmdev_ctx_t *ctx,
- lsm6dsrx_ff_ths_t *val);
+ lsm6dsrx_ff_ths_t *val);
int32_t lsm6dsrx_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsrx_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -3417,11 +3675,12 @@ int32_t lsm6dsrx_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val);
int32_t lsm6dsrx_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val);
int32_t lsm6dsrx_compression_algo_init_set(stmdev_ctx_t *ctx,
- uint8_t val);
+ uint8_t val);
int32_t lsm6dsrx_compression_algo_init_get(stmdev_ctx_t *ctx,
- uint8_t *val);
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_CMP_DISABLE = 0x00,
LSM6DSRX_CMP_ALWAYS = 0x04,
LSM6DSRX_CMP_8_TO_1 = 0x05,
@@ -3429,24 +3688,26 @@ typedef enum {
LSM6DSRX_CMP_32_TO_1 = 0x07,
} lsm6dsrx_uncoptr_rate_t;
int32_t lsm6dsrx_compression_algo_set(stmdev_ctx_t *ctx,
- lsm6dsrx_uncoptr_rate_t val);
+ lsm6dsrx_uncoptr_rate_t val);
int32_t lsm6dsrx_compression_algo_get(stmdev_ctx_t *ctx,
- lsm6dsrx_uncoptr_rate_t *val);
+ lsm6dsrx_uncoptr_rate_t *val);
int32_t lsm6dsrx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
- uint8_t val);
+ uint8_t val);
int32_t lsm6dsrx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
- uint8_t *val);
+ uint8_t *val);
int32_t lsm6dsrx_compression_algo_real_time_set(stmdev_ctx_t *ctx,
- uint8_t val);
+ uint8_t val);
int32_t lsm6dsrx_compression_algo_real_time_get(stmdev_ctx_t *ctx,
- uint8_t *val);
+ uint8_t *val);
int32_t lsm6dsrx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsrx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsrx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_XL_NOT_BATCHED = 0,
LSM6DSRX_XL_BATCHED_AT_12Hz5 = 1,
LSM6DSRX_XL_BATCHED_AT_26Hz = 2,
@@ -3460,10 +3721,13 @@ typedef enum {
LSM6DSRX_XL_BATCHED_AT_6667Hz = 10,
LSM6DSRX_XL_BATCHED_AT_6Hz5 = 11,
} lsm6dsrx_bdr_xl_t;
-int32_t lsm6dsrx_fifo_xl_batch_set(stmdev_ctx_t *ctx, lsm6dsrx_bdr_xl_t val);
-int32_t lsm6dsrx_fifo_xl_batch_get(stmdev_ctx_t *ctx, lsm6dsrx_bdr_xl_t *val);
+int32_t lsm6dsrx_fifo_xl_batch_set(stmdev_ctx_t *ctx,
+ lsm6dsrx_bdr_xl_t val);
+int32_t lsm6dsrx_fifo_xl_batch_get(stmdev_ctx_t *ctx,
+ lsm6dsrx_bdr_xl_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_GY_NOT_BATCHED = 0,
LSM6DSRX_GY_BATCHED_AT_12Hz5 = 1,
LSM6DSRX_GY_BATCHED_AT_26Hz = 2,
@@ -3477,10 +3741,13 @@ typedef enum {
LSM6DSRX_GY_BATCHED_AT_6667Hz = 10,
LSM6DSRX_GY_BATCHED_6Hz5 = 11,
} lsm6dsrx_bdr_gy_t;
-int32_t lsm6dsrx_fifo_gy_batch_set(stmdev_ctx_t *ctx, lsm6dsrx_bdr_gy_t val);
-int32_t lsm6dsrx_fifo_gy_batch_get(stmdev_ctx_t *ctx, lsm6dsrx_bdr_gy_t *val);
+int32_t lsm6dsrx_fifo_gy_batch_set(stmdev_ctx_t *ctx,
+ lsm6dsrx_bdr_gy_t val);
+int32_t lsm6dsrx_fifo_gy_batch_get(stmdev_ctx_t *ctx,
+ lsm6dsrx_bdr_gy_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_BYPASS_MODE = 0,
LSM6DSRX_FIFO_MODE = 1,
LSM6DSRX_STREAM_TO_FIFO_MODE = 3,
@@ -3488,52 +3755,60 @@ typedef enum {
LSM6DSRX_STREAM_MODE = 6,
LSM6DSRX_BYPASS_TO_FIFO_MODE = 7,
} lsm6dsrx_fifo_mode_t;
-int32_t lsm6dsrx_fifo_mode_set(stmdev_ctx_t *ctx, lsm6dsrx_fifo_mode_t val);
-int32_t lsm6dsrx_fifo_mode_get(stmdev_ctx_t *ctx, lsm6dsrx_fifo_mode_t *val);
+int32_t lsm6dsrx_fifo_mode_set(stmdev_ctx_t *ctx,
+ lsm6dsrx_fifo_mode_t val);
+int32_t lsm6dsrx_fifo_mode_get(stmdev_ctx_t *ctx,
+ lsm6dsrx_fifo_mode_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_TEMP_NOT_BATCHED = 0,
LSM6DSRX_TEMP_BATCHED_AT_52Hz = 1,
LSM6DSRX_TEMP_BATCHED_AT_12Hz5 = 2,
LSM6DSRX_TEMP_BATCHED_AT_1Hz6 = 3,
} lsm6dsrx_odr_t_batch_t;
int32_t lsm6dsrx_fifo_temp_batch_set(stmdev_ctx_t *ctx,
- lsm6dsrx_odr_t_batch_t val);
+ lsm6dsrx_odr_t_batch_t val);
int32_t lsm6dsrx_fifo_temp_batch_get(stmdev_ctx_t *ctx,
- lsm6dsrx_odr_t_batch_t *val);
+ lsm6dsrx_odr_t_batch_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_NO_DECIMATION = 0,
LSM6DSRX_DEC_1 = 1,
LSM6DSRX_DEC_8 = 2,
LSM6DSRX_DEC_32 = 3,
} lsm6dsrx_odr_ts_batch_t;
int32_t lsm6dsrx_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
- lsm6dsrx_odr_ts_batch_t val);
+ lsm6dsrx_odr_ts_batch_t val);
int32_t lsm6dsrx_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
- lsm6dsrx_odr_ts_batch_t *val);
+ lsm6dsrx_odr_ts_batch_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_XL_BATCH_EVENT = 0,
LSM6DSRX_GYRO_BATCH_EVENT = 1,
} lsm6dsrx_trig_counter_bdr_t;
int32_t lsm6dsrx_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
- lsm6dsrx_trig_counter_bdr_t val);
+ lsm6dsrx_trig_counter_bdr_t val);
int32_t lsm6dsrx_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
- lsm6dsrx_trig_counter_bdr_t *val);
+ lsm6dsrx_trig_counter_bdr_t *val);
-int32_t lsm6dsrx_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsrx_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsrx_rst_batch_counter_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm6dsrx_rst_batch_counter_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dsrx_batch_counter_threshold_set(stmdev_ctx_t *ctx,
- uint16_t val);
+ uint16_t val);
int32_t lsm6dsrx_batch_counter_threshold_get(stmdev_ctx_t *ctx,
- uint16_t *val);
+ uint16_t *val);
-int32_t lsm6dsrx_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t lsm6dsrx_fifo_data_level_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
int32_t lsm6dsrx_fifo_status_get(stmdev_ctx_t *ctx,
- lsm6dsrx_fifo_status2_t *val);
+ lsm6dsrx_fifo_status2_t *val);
int32_t lsm6dsrx_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -3541,7 +3816,8 @@ int32_t lsm6dsrx_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsrx_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_GYRO_NC_TAG = 1,
LSM6DSRX_XL_NC_TAG,
LSM6DSRX_TEMPERATURE_TAG,
@@ -3566,24 +3842,29 @@ typedef enum {
LSM6DSRX_SENSORHUB_NACK_TAG = 0x19,
} lsm6dsrx_fifo_tag_t;
int32_t lsm6dsrx_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
- lsm6dsrx_fifo_tag_t *val);
+ lsm6dsrx_fifo_tag_t *val);
int32_t lsm6dsrx_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsrx_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsrx_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsrx_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsrx_sh_batch_slave_0_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dsrx_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsrx_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsrx_sh_batch_slave_1_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dsrx_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsrx_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsrx_sh_batch_slave_2_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dsrx_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm6dsrx_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsrx_sh_batch_slave_3_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_DEN_DISABLE = 0,
LSM6DSRX_LEVEL_FIFO = 6,
LSM6DSRX_LEVEL_LETCHED = 3,
@@ -3591,28 +3872,30 @@ typedef enum {
LSM6DSRX_EDGE_TRIGGER = 4,
} lsm6dsrx_den_mode_t;
int32_t lsm6dsrx_den_mode_set(stmdev_ctx_t *ctx,
- lsm6dsrx_den_mode_t val);
+ lsm6dsrx_den_mode_t val);
int32_t lsm6dsrx_den_mode_get(stmdev_ctx_t *ctx,
- lsm6dsrx_den_mode_t *val);
+ lsm6dsrx_den_mode_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_DEN_ACT_LOW = 0,
LSM6DSRX_DEN_ACT_HIGH = 1,
} lsm6dsrx_den_lh_t;
int32_t lsm6dsrx_den_polarity_set(stmdev_ctx_t *ctx,
- lsm6dsrx_den_lh_t val);
+ lsm6dsrx_den_lh_t val);
int32_t lsm6dsrx_den_polarity_get(stmdev_ctx_t *ctx,
- lsm6dsrx_den_lh_t *val);
+ lsm6dsrx_den_lh_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_STAMP_IN_GY_DATA = 0,
LSM6DSRX_STAMP_IN_XL_DATA = 1,
LSM6DSRX_STAMP_IN_GY_XL_DATA = 2,
} lsm6dsrx_den_xl_g_t;
int32_t lsm6dsrx_den_enable_set(stmdev_ctx_t *ctx,
- lsm6dsrx_den_xl_g_t val);
+ lsm6dsrx_den_xl_g_t val);
int32_t lsm6dsrx_den_enable_get(stmdev_ctx_t *ctx,
- lsm6dsrx_den_xl_g_t *val);
+ lsm6dsrx_den_xl_g_t *val);
int32_t lsm6dsrx_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsrx_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -3626,36 +3909,44 @@ int32_t lsm6dsrx_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsrx_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsrx_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dsrx_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsrx_pedo_step_detect_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm6dsrx_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsrx_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dsrx_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lsm6dsrx_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
-int32_t lsm6dsrx_pedo_steps_period_set(stmdev_ctx_t *ctx, uint16_t val);
-int32_t lsm6dsrx_pedo_steps_period_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t lsm6dsrx_pedo_steps_period_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t lsm6dsrx_pedo_steps_period_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_EVERY_STEP = 0,
LSM6DSRX_COUNT_OVERFLOW = 1,
} lsm6dsrx_carry_count_en_t;
int32_t lsm6dsrx_pedo_int_mode_set(stmdev_ctx_t *ctx,
- lsm6dsrx_carry_count_en_t val);
+ lsm6dsrx_carry_count_en_t val);
int32_t lsm6dsrx_pedo_int_mode_get(stmdev_ctx_t *ctx,
- lsm6dsrx_carry_count_en_t *val);
+ lsm6dsrx_carry_count_en_t *val);
int32_t lsm6dsrx_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsrx_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsrx_motion_flag_data_ready_get(stmdev_ctx_t *ctx,
- uint8_t *val);
+ uint8_t *val);
int32_t lsm6dsrx_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsrx_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dsrx_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm6dsrx_tilt_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm6dsrx_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val);
-int32_t lsm6dsrx_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t lsm6dsrx_mag_sensitivity_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
int32_t lsm6dsrx_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val);
int32_t lsm6dsrx_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val);
@@ -3663,7 +3954,8 @@ int32_t lsm6dsrx_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val);
int32_t lsm6dsrx_mag_soft_iron_set(stmdev_ctx_t *ctx, uint16_t *val);
int32_t lsm6dsrx_mag_soft_iron_get(stmdev_ctx_t *ctx, uint16_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_Z_EQ_Y = 0,
LSM6DSRX_Z_EQ_MIN_Y = 1,
LSM6DSRX_Z_EQ_X = 2,
@@ -3672,11 +3964,12 @@ typedef enum {
LSM6DSRX_Z_EQ_Z = 5,
} lsm6dsrx_mag_z_axis_t;
int32_t lsm6dsrx_mag_z_orient_set(stmdev_ctx_t *ctx,
- lsm6dsrx_mag_z_axis_t val);
+ lsm6dsrx_mag_z_axis_t val);
int32_t lsm6dsrx_mag_z_orient_get(stmdev_ctx_t *ctx,
- lsm6dsrx_mag_z_axis_t *val);
+ lsm6dsrx_mag_z_axis_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_Y_EQ_Y = 0,
LSM6DSRX_Y_EQ_MIN_Y = 1,
LSM6DSRX_Y_EQ_X = 2,
@@ -3685,11 +3978,12 @@ typedef enum {
LSM6DSRX_Y_EQ_Z = 5,
} lsm6dsrx_mag_y_axis_t;
int32_t lsm6dsrx_mag_y_orient_set(stmdev_ctx_t *ctx,
- lsm6dsrx_mag_y_axis_t val);
+ lsm6dsrx_mag_y_axis_t val);
int32_t lsm6dsrx_mag_y_orient_get(stmdev_ctx_t *ctx,
- lsm6dsrx_mag_y_axis_t *val);
+ lsm6dsrx_mag_y_axis_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_X_EQ_Y = 0,
LSM6DSRX_X_EQ_MIN_Y = 1,
LSM6DSRX_X_EQ_X = 2,
@@ -3698,82 +3992,91 @@ typedef enum {
LSM6DSRX_X_EQ_Z = 5,
} lsm6dsrx_mag_x_axis_t;
int32_t lsm6dsrx_mag_x_orient_set(stmdev_ctx_t *ctx,
- lsm6dsrx_mag_x_axis_t val);
+ lsm6dsrx_mag_x_axis_t val);
int32_t lsm6dsrx_mag_x_orient_get(stmdev_ctx_t *ctx,
- lsm6dsrx_mag_x_axis_t *val);
+ lsm6dsrx_mag_x_axis_t *val);
int32_t lsm6dsrx_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
- uint8_t *val);
+ uint8_t *val);
int32_t lsm6dsrx_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsrx_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef struct {
- lsm6dsrx_fsm_enable_a_t fsm_enable_a;
- lsm6dsrx_fsm_enable_b_t fsm_enable_b;
+typedef struct
+{
+ lsm6dsrx_fsm_enable_a_t fsm_enable_a;
+ lsm6dsrx_fsm_enable_b_t fsm_enable_b;
} lsm6dsrx_emb_fsm_enable_t;
int32_t lsm6dsrx_fsm_enable_set(stmdev_ctx_t *ctx,
- lsm6dsrx_emb_fsm_enable_t *val);
+ lsm6dsrx_emb_fsm_enable_t *val);
int32_t lsm6dsrx_fsm_enable_get(stmdev_ctx_t *ctx,
- lsm6dsrx_emb_fsm_enable_t *val);
+ lsm6dsrx_emb_fsm_enable_t *val);
int32_t lsm6dsrx_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val);
int32_t lsm6dsrx_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_LC_NORMAL = 0,
LSM6DSRX_LC_CLEAR = 1,
LSM6DSRX_LC_CLEAR_DONE = 2,
} lsm6dsrx_fsm_lc_clr_t;
int32_t lsm6dsrx_long_clr_set(stmdev_ctx_t *ctx,
- lsm6dsrx_fsm_lc_clr_t val);
+ lsm6dsrx_fsm_lc_clr_t val);
int32_t lsm6dsrx_long_clr_get(stmdev_ctx_t *ctx,
- lsm6dsrx_fsm_lc_clr_t *val);
-
-typedef struct {
- lsm6dsrx_fsm_outs1_t fsm_outs1;
- lsm6dsrx_fsm_outs2_t fsm_outs2;
- lsm6dsrx_fsm_outs3_t fsm_outs3;
- lsm6dsrx_fsm_outs4_t fsm_outs4;
- lsm6dsrx_fsm_outs5_t fsm_outs5;
- lsm6dsrx_fsm_outs6_t fsm_outs6;
- lsm6dsrx_fsm_outs7_t fsm_outs7;
- lsm6dsrx_fsm_outs8_t fsm_outs8;
- lsm6dsrx_fsm_outs9_t fsm_outs9;
- lsm6dsrx_fsm_outs10_t fsm_outs10;
- lsm6dsrx_fsm_outs11_t fsm_outs11;
- lsm6dsrx_fsm_outs12_t fsm_outs12;
- lsm6dsrx_fsm_outs13_t fsm_outs13;
- lsm6dsrx_fsm_outs14_t fsm_outs14;
- lsm6dsrx_fsm_outs15_t fsm_outs15;
- lsm6dsrx_fsm_outs16_t fsm_outs16;
+ lsm6dsrx_fsm_lc_clr_t *val);
+
+typedef struct
+{
+ lsm6dsrx_fsm_outs1_t fsm_outs1;
+ lsm6dsrx_fsm_outs2_t fsm_outs2;
+ lsm6dsrx_fsm_outs3_t fsm_outs3;
+ lsm6dsrx_fsm_outs4_t fsm_outs4;
+ lsm6dsrx_fsm_outs5_t fsm_outs5;
+ lsm6dsrx_fsm_outs6_t fsm_outs6;
+ lsm6dsrx_fsm_outs7_t fsm_outs7;
+ lsm6dsrx_fsm_outs8_t fsm_outs8;
+ lsm6dsrx_fsm_outs9_t fsm_outs9;
+ lsm6dsrx_fsm_outs10_t fsm_outs10;
+ lsm6dsrx_fsm_outs11_t fsm_outs11;
+ lsm6dsrx_fsm_outs12_t fsm_outs12;
+ lsm6dsrx_fsm_outs13_t fsm_outs13;
+ lsm6dsrx_fsm_outs14_t fsm_outs14;
+ lsm6dsrx_fsm_outs15_t fsm_outs15;
+ lsm6dsrx_fsm_outs16_t fsm_outs16;
} lsm6dsrx_fsm_out_t;
-int32_t lsm6dsrx_fsm_out_get(stmdev_ctx_t *ctx, lsm6dsrx_fsm_out_t *val);
+int32_t lsm6dsrx_fsm_out_get(stmdev_ctx_t *ctx,
+ lsm6dsrx_fsm_out_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_ODR_FSM_12Hz5 = 0,
LSM6DSRX_ODR_FSM_26Hz = 1,
LSM6DSRX_ODR_FSM_52Hz = 2,
LSM6DSRX_ODR_FSM_104Hz = 3,
} lsm6dsrx_fsm_odr_t;
int32_t lsm6dsrx_fsm_data_rate_set(stmdev_ctx_t *ctx,
- lsm6dsrx_fsm_odr_t val);
+ lsm6dsrx_fsm_odr_t val);
int32_t lsm6dsrx_fsm_data_rate_get(stmdev_ctx_t *ctx,
- lsm6dsrx_fsm_odr_t *val);
+ lsm6dsrx_fsm_odr_t *val);
int32_t lsm6dsrx_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsrx_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t lsm6dsrx_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint16_t val);
-int32_t lsm6dsrx_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t lsm6dsrx_long_cnt_int_value_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t lsm6dsrx_long_cnt_int_value_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
int32_t lsm6dsrx_fsm_number_of_programs_set(stmdev_ctx_t *ctx,
- uint8_t *buff);
+ uint8_t *buff);
int32_t lsm6dsrx_fsm_number_of_programs_get(stmdev_ctx_t *ctx,
- uint8_t *buff);
+ uint8_t *buff);
-int32_t lsm6dsrx_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val);
-int32_t lsm6dsrx_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val);
+int32_t lsm6dsrx_fsm_start_address_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t lsm6dsrx_fsm_start_address_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
int32_t lsm6dsrx_mlc_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsrx_mlc_get(stmdev_ctx_t *ctx, uint8_t *val);
@@ -3781,150 +4084,163 @@ int32_t lsm6dsrx_mlc_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm6dsrx_mlc_status_get(stmdev_ctx_t *ctx,
lsm6dsrx_mlc_status_mainpage_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_ODR_PRGS_12Hz5 = 0,
LSM6DSRX_ODR_PRGS_26Hz = 1,
LSM6DSRX_ODR_PRGS_52Hz = 2,
LSM6DSRX_ODR_PRGS_104Hz = 3,
} lsm6dsrx_mlc_odr_t;
int32_t lsm6dsrx_mlc_data_rate_set(stmdev_ctx_t *ctx,
- lsm6dsrx_mlc_odr_t val);
+ lsm6dsrx_mlc_odr_t val);
int32_t lsm6dsrx_mlc_data_rate_get(stmdev_ctx_t *ctx,
lsm6dsrx_mlc_odr_t *val);
int32_t lsm6dsrx_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm6dsrx_mlc_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val);
-int32_t lsm6dsrx_mlc_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val);
-
-typedef struct {
- lsm6dsrx_sensor_hub_1_t sh_byte_1;
- lsm6dsrx_sensor_hub_2_t sh_byte_2;
- lsm6dsrx_sensor_hub_3_t sh_byte_3;
- lsm6dsrx_sensor_hub_4_t sh_byte_4;
- lsm6dsrx_sensor_hub_5_t sh_byte_5;
- lsm6dsrx_sensor_hub_6_t sh_byte_6;
- lsm6dsrx_sensor_hub_7_t sh_byte_7;
- lsm6dsrx_sensor_hub_8_t sh_byte_8;
- lsm6dsrx_sensor_hub_9_t sh_byte_9;
- lsm6dsrx_sensor_hub_10_t sh_byte_10;
- lsm6dsrx_sensor_hub_11_t sh_byte_11;
- lsm6dsrx_sensor_hub_12_t sh_byte_12;
- lsm6dsrx_sensor_hub_13_t sh_byte_13;
- lsm6dsrx_sensor_hub_14_t sh_byte_14;
- lsm6dsrx_sensor_hub_15_t sh_byte_15;
- lsm6dsrx_sensor_hub_16_t sh_byte_16;
- lsm6dsrx_sensor_hub_17_t sh_byte_17;
- lsm6dsrx_sensor_hub_18_t sh_byte_18;
+int32_t lsm6dsrx_mlc_mag_sensitivity_set(stmdev_ctx_t *ctx,
+ uint16_t val);
+int32_t lsm6dsrx_mlc_mag_sensitivity_get(stmdev_ctx_t *ctx,
+ uint16_t *val);
+
+typedef struct
+{
+ lsm6dsrx_sensor_hub_1_t sh_byte_1;
+ lsm6dsrx_sensor_hub_2_t sh_byte_2;
+ lsm6dsrx_sensor_hub_3_t sh_byte_3;
+ lsm6dsrx_sensor_hub_4_t sh_byte_4;
+ lsm6dsrx_sensor_hub_5_t sh_byte_5;
+ lsm6dsrx_sensor_hub_6_t sh_byte_6;
+ lsm6dsrx_sensor_hub_7_t sh_byte_7;
+ lsm6dsrx_sensor_hub_8_t sh_byte_8;
+ lsm6dsrx_sensor_hub_9_t sh_byte_9;
+ lsm6dsrx_sensor_hub_10_t sh_byte_10;
+ lsm6dsrx_sensor_hub_11_t sh_byte_11;
+ lsm6dsrx_sensor_hub_12_t sh_byte_12;
+ lsm6dsrx_sensor_hub_13_t sh_byte_13;
+ lsm6dsrx_sensor_hub_14_t sh_byte_14;
+ lsm6dsrx_sensor_hub_15_t sh_byte_15;
+ lsm6dsrx_sensor_hub_16_t sh_byte_16;
+ lsm6dsrx_sensor_hub_17_t sh_byte_17;
+ lsm6dsrx_sensor_hub_18_t sh_byte_18;
} lsm6dsrx_emb_sh_read_t;
int32_t lsm6dsrx_sh_read_data_raw_get(stmdev_ctx_t *ctx,
- lsm6dsrx_emb_sh_read_t *val);
+ lsm6dsrx_emb_sh_read_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_SLV_0 = 0,
LSM6DSRX_SLV_0_1 = 1,
LSM6DSRX_SLV_0_1_2 = 2,
LSM6DSRX_SLV_0_1_2_3 = 3,
} lsm6dsrx_aux_sens_on_t;
int32_t lsm6dsrx_sh_slave_connected_set(stmdev_ctx_t *ctx,
- lsm6dsrx_aux_sens_on_t val);
+ lsm6dsrx_aux_sens_on_t val);
int32_t lsm6dsrx_sh_slave_connected_get(stmdev_ctx_t *ctx,
- lsm6dsrx_aux_sens_on_t *val);
+ lsm6dsrx_aux_sens_on_t *val);
int32_t lsm6dsrx_sh_master_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsrx_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_EXT_PULL_UP = 0,
LSM6DSRX_INTERNAL_PULL_UP = 1,
} lsm6dsrx_shub_pu_en_t;
int32_t lsm6dsrx_sh_pin_mode_set(stmdev_ctx_t *ctx,
- lsm6dsrx_shub_pu_en_t val);
+ lsm6dsrx_shub_pu_en_t val);
int32_t lsm6dsrx_sh_pin_mode_get(stmdev_ctx_t *ctx,
- lsm6dsrx_shub_pu_en_t *val);
+ lsm6dsrx_shub_pu_en_t *val);
int32_t lsm6dsrx_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsrx_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
- LSM6DSRX_EXT_ON_INT2_PIN = 0,
- LSM6DSRX_XL_GY_DRDY = 1,
+typedef enum
+{
+ LSM6DSRX_EXT_ON_INT2_PIN = 1,
+ LSM6DSRX_XL_GY_DRDY = 0,
} lsm6dsrx_start_config_t;
int32_t lsm6dsrx_sh_syncro_mode_set(stmdev_ctx_t *ctx,
- lsm6dsrx_start_config_t val);
+ lsm6dsrx_start_config_t val);
int32_t lsm6dsrx_sh_syncro_mode_get(stmdev_ctx_t *ctx,
- lsm6dsrx_start_config_t *val);
+ lsm6dsrx_start_config_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_EACH_SH_CYCLE = 0,
LSM6DSRX_ONLY_FIRST_CYCLE = 1,
} lsm6dsrx_write_once_t;
int32_t lsm6dsrx_sh_write_mode_set(stmdev_ctx_t *ctx,
- lsm6dsrx_write_once_t val);
+ lsm6dsrx_write_once_t val);
int32_t lsm6dsrx_sh_write_mode_get(stmdev_ctx_t *ctx,
- lsm6dsrx_write_once_t *val);
+ lsm6dsrx_write_once_t *val);
int32_t lsm6dsrx_sh_reset_set(stmdev_ctx_t *ctx);
int32_t lsm6dsrx_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_SH_ODR_104Hz = 0,
LSM6DSRX_SH_ODR_52Hz = 1,
LSM6DSRX_SH_ODR_26Hz = 2,
LSM6DSRX_SH_ODR_13Hz = 3,
} lsm6dsrx_shub_odr_t;
int32_t lsm6dsrx_sh_data_rate_set(stmdev_ctx_t *ctx,
- lsm6dsrx_shub_odr_t val);
+ lsm6dsrx_shub_odr_t val);
int32_t lsm6dsrx_sh_data_rate_get(stmdev_ctx_t *ctx,
- lsm6dsrx_shub_odr_t *val);
+ lsm6dsrx_shub_odr_t *val);
-typedef struct{
+typedef struct
+{
uint8_t slv0_add;
uint8_t slv0_subadd;
uint8_t slv0_data;
} lsm6dsrx_sh_cfg_write_t;
int32_t lsm6dsrx_sh_cfg_write(stmdev_ctx_t *ctx,
- lsm6dsrx_sh_cfg_write_t *val);
+ lsm6dsrx_sh_cfg_write_t *val);
-typedef struct{
+typedef struct
+{
uint8_t slv_add;
uint8_t slv_subadd;
uint8_t slv_len;
} lsm6dsrx_sh_cfg_read_t;
int32_t lsm6dsrx_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
- lsm6dsrx_sh_cfg_read_t *val);
+ lsm6dsrx_sh_cfg_read_t *val);
int32_t lsm6dsrx_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
- lsm6dsrx_sh_cfg_read_t *val);
+ lsm6dsrx_sh_cfg_read_t *val);
int32_t lsm6dsrx_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
- lsm6dsrx_sh_cfg_read_t *val);
+ lsm6dsrx_sh_cfg_read_t *val);
int32_t lsm6dsrx_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
- lsm6dsrx_sh_cfg_read_t *val);
+ lsm6dsrx_sh_cfg_read_t *val);
int32_t lsm6dsrx_sh_status_get(stmdev_ctx_t *ctx,
- lsm6dsrx_status_master_t *val);
+ lsm6dsrx_status_master_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_S4S_TPH_7bit = 0,
LSM6DSRX_S4S_TPH_15bit = 1,
} lsm6dsrx_s4s_tph_res_t;
int32_t lsm6dsrx_s4s_tph_res_set(stmdev_ctx_t *ctx,
- lsm6dsrx_s4s_tph_res_t val);
+ lsm6dsrx_s4s_tph_res_t val);
int32_t lsm6dsrx_s4s_tph_res_get(stmdev_ctx_t *ctx,
- lsm6dsrx_s4s_tph_res_t *val);
+ lsm6dsrx_s4s_tph_res_t *val);
int32_t lsm6dsrx_s4s_tph_val_set(stmdev_ctx_t *ctx, uint16_t val);
int32_t lsm6dsrx_s4s_tph_val_get(stmdev_ctx_t *ctx, uint16_t *val);
-typedef enum {
+typedef enum
+{
LSM6DSRX_S4S_DT_RES_11 = 0,
LSM6DSRX_S4S_DT_RES_12 = 1,
LSM6DSRX_S4S_DT_RES_13 = 2,
LSM6DSRX_S4S_DT_RES_14 = 3,
} lsm6dsrx_s4s_res_ratio_t;
int32_t lsm6dsrx_s4s_res_ratio_set(stmdev_ctx_t *ctx,
- lsm6dsrx_s4s_res_ratio_t val);
+ lsm6dsrx_s4s_res_ratio_t val);
int32_t lsm6dsrx_s4s_res_ratio_get(stmdev_ctx_t *ctx,
- lsm6dsrx_s4s_res_ratio_t *val);
+ lsm6dsrx_s4s_res_ratio_t *val);
int32_t lsm6dsrx_s4s_command_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm6dsrx_s4s_command_get(stmdev_ctx_t *ctx, uint8_t *val);
diff --git a/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.c b/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.c
index 72c637c1da345b35ee6b09ab8ee7d8b344e23154..7d319e171a73a953c281c093ae09e530a32b50d7 100644
--- a/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.c
+++ b/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file lsm9ds1_reg.c
- * @author Sensors Software Solution Team
- * @brief LSM9DS1 driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lsm9ds1_reg.c
+ * @author Sensors Software Solution Team
+ * @brief LSM9DS1 driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "lsm9ds1_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm9ds1_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lsm9ds1_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t lsm9ds1_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t lsm9ds1_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
+int32_t lsm9ds1_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -86,57 +92,57 @@ int32_t lsm9ds1_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
float_t lsm9ds1_from_fs2g_to_mg(int16_t lsb)
{
- return ((float_t)lsb *0.061f);
+ return ((float_t)lsb * 0.061f);
}
float_t lsm9ds1_from_fs4g_to_mg(int16_t lsb)
{
- return ((float_t)lsb *0.122f);
+ return ((float_t)lsb * 0.122f);
}
float_t lsm9ds1_from_fs8g_to_mg(int16_t lsb)
{
- return ((float_t)lsb *0.244f);
+ return ((float_t)lsb * 0.244f);
}
float_t lsm9ds1_from_fs16g_to_mg(int16_t lsb)
{
- return ((float_t)lsb *0.732f);
+ return ((float_t)lsb * 0.732f);
}
float_t lsm9ds1_from_fs245dps_to_mdps(int16_t lsb)
{
- return ((float_t)lsb *8.75f);
+ return ((float_t)lsb * 8.75f);
}
float_t lsm9ds1_from_fs500dps_to_mdps(int16_t lsb)
{
- return ((float_t)lsb *17.50f);
+ return ((float_t)lsb * 17.50f);
}
float_t lsm9ds1_from_fs2000dps_to_mdps(int16_t lsb)
{
- return ((float_t)lsb *70.0f);
+ return ((float_t)lsb * 70.0f);
}
float_t lsm9ds1_from_fs4gauss_to_mG(int16_t lsb)
{
- return ((float_t)lsb *0.14f);
+ return ((float_t)lsb * 0.14f);
}
float_t lsm9ds1_from_fs8gauss_to_mG(int16_t lsb)
{
- return ((float_t)lsb *0.29f);
+ return ((float_t)lsb * 0.29f);
}
float_t lsm9ds1_from_fs12gauss_to_mG(int16_t lsb)
{
- return ((float_t)lsb *0.43f);
+ return ((float_t)lsb * 0.43f);
}
float_t lsm9ds1_from_fs16gauss_to_mG(int16_t lsb)
{
- return ((float_t)lsb *0.58f);
+ return ((float_t)lsb * 0.58f);
}
float_t lsm9ds1_from_lsb_to_celsius(int16_t lsb)
@@ -165,17 +171,22 @@ float_t lsm9ds1_from_lsb_to_celsius(int16_t lsb)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_gy_full_scale_set(stmdev_ctx_t *ctx, lsm9ds1_gy_fs_t val)
+int32_t lsm9ds1_gy_full_scale_set(stmdev_ctx_t *ctx,
+ lsm9ds1_gy_fs_t val)
{
lsm9ds1_ctrl_reg1_g_t ctrl_reg1_g;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_G, (uint8_t*)&ctrl_reg1_g, 1);
- if(ret == 0){
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_G,
+ (uint8_t *)&ctrl_reg1_g, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1_g.fs_g = (uint8_t)val;
ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG1_G,
- (uint8_t*)&ctrl_reg1_g, 1);
+ (uint8_t *)&ctrl_reg1_g, 1);
}
+
return ret;
}
@@ -187,26 +198,34 @@ int32_t lsm9ds1_gy_full_scale_set(stmdev_ctx_t *ctx, lsm9ds1_gy_fs_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_gy_full_scale_get(stmdev_ctx_t *ctx, lsm9ds1_gy_fs_t *val)
+int32_t lsm9ds1_gy_full_scale_get(stmdev_ctx_t *ctx,
+ lsm9ds1_gy_fs_t *val)
{
lsm9ds1_ctrl_reg1_g_t ctrl_reg1_g;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_G, (uint8_t*)&ctrl_reg1_g, 1);
- switch (ctrl_reg1_g.fs_g){
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_G,
+ (uint8_t *)&ctrl_reg1_g, 1);
+
+ switch (ctrl_reg1_g.fs_g)
+ {
case LSM9DS1_245dps:
*val = LSM9DS1_245dps;
break;
+
case LSM9DS1_500dps:
*val = LSM9DS1_500dps;
break;
+
case LSM9DS1_2000dps:
*val = LSM9DS1_2000dps;
break;
+
default:
*val = LSM9DS1_245dps;
break;
}
+
return ret;
}
@@ -219,36 +238,48 @@ int32_t lsm9ds1_gy_full_scale_get(stmdev_ctx_t *ctx, lsm9ds1_gy_fs_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_imu_data_rate_set(stmdev_ctx_t *ctx, lsm9ds1_imu_odr_t val)
+int32_t lsm9ds1_imu_data_rate_set(stmdev_ctx_t *ctx,
+ lsm9ds1_imu_odr_t val)
{
lsm9ds1_ctrl_reg1_g_t ctrl_reg1_g;
lsm9ds1_ctrl_reg6_xl_t ctrl_reg6_xl;
lsm9ds1_ctrl_reg3_g_t ctrl_reg3_g;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_G, (uint8_t*)&ctrl_reg1_g, 1);
- if(ret == 0){
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_G,
+ (uint8_t *)&ctrl_reg1_g, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1_g.odr_g = (uint8_t)val & 0x07U;
ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG1_G,
- (uint8_t*)&ctrl_reg1_g, 1);
+ (uint8_t *)&ctrl_reg1_g, 1);
}
- if(ret == 0){
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG6_XL,
- (uint8_t*)&ctrl_reg6_xl, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG6_XL,
+ (uint8_t *)&ctrl_reg6_xl, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ctrl_reg6_xl.odr_xl = (((uint8_t)val & 0x70U) >> 4);
ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG6_XL,
- (uint8_t*)&ctrl_reg6_xl, 1);
+ (uint8_t *)&ctrl_reg6_xl, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG3_G,
- (uint8_t*)&ctrl_reg3_g, 1);
+ (uint8_t *)&ctrl_reg3_g, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ctrl_reg3_g.lp_mode = (((uint8_t)val & 0x80U) >> 7);
ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG3_G,
- (uint8_t*)&ctrl_reg3_g, 1);
+ (uint8_t *)&ctrl_reg3_g, 1);
}
return ret;
@@ -263,102 +294,135 @@ int32_t lsm9ds1_imu_data_rate_set(stmdev_ctx_t *ctx, lsm9ds1_imu_odr_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_imu_data_rate_get(stmdev_ctx_t *ctx, lsm9ds1_imu_odr_t *val)
+int32_t lsm9ds1_imu_data_rate_get(stmdev_ctx_t *ctx,
+ lsm9ds1_imu_odr_t *val)
{
lsm9ds1_ctrl_reg1_g_t ctrl_reg1_g;
lsm9ds1_ctrl_reg6_xl_t ctrl_reg6_xl;
lsm9ds1_ctrl_reg3_g_t ctrl_reg3_g;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_G, (uint8_t*)&ctrl_reg1_g, 1);
- if(ret == 0){
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_G,
+ (uint8_t *)&ctrl_reg1_g, 1);
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG6_XL,
- (uint8_t*)&ctrl_reg6_xl, 1);
+ (uint8_t *)&ctrl_reg6_xl, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG3_G,
- (uint8_t*)&ctrl_reg3_g, 1);
+ (uint8_t *)&ctrl_reg3_g, 1);
}
+
switch ((ctrl_reg3_g.lp_mode << 7) | (ctrl_reg6_xl.odr_xl << 4) |
- ctrl_reg1_g.odr_g){
+ ctrl_reg1_g.odr_g)
+ {
case LSM9DS1_IMU_OFF:
*val = LSM9DS1_IMU_OFF;
break;
+
case LSM9DS1_GY_OFF_XL_10Hz:
*val = LSM9DS1_GY_OFF_XL_10Hz;
break;
+
case LSM9DS1_GY_OFF_XL_50Hz:
*val = LSM9DS1_GY_OFF_XL_50Hz;
break;
+
case LSM9DS1_GY_OFF_XL_119Hz:
*val = LSM9DS1_GY_OFF_XL_119Hz;
break;
+
case LSM9DS1_GY_OFF_XL_238Hz:
*val = LSM9DS1_GY_OFF_XL_238Hz;
break;
+
case LSM9DS1_GY_OFF_XL_476Hz:
*val = LSM9DS1_GY_OFF_XL_476Hz;
break;
+
case LSM9DS1_GY_OFF_XL_952Hz:
*val = LSM9DS1_GY_OFF_XL_952Hz;
break;
+
case LSM9DS1_XL_OFF_GY_14Hz9:
*val = LSM9DS1_XL_OFF_GY_14Hz9;
break;
+
case LSM9DS1_XL_OFF_GY_59Hz5:
*val = LSM9DS1_XL_OFF_GY_59Hz5;
break;
+
case LSM9DS1_XL_OFF_GY_119Hz:
*val = LSM9DS1_XL_OFF_GY_119Hz;
break;
+
case LSM9DS1_XL_OFF_GY_238Hz:
*val = LSM9DS1_XL_OFF_GY_238Hz;
break;
+
case LSM9DS1_XL_OFF_GY_476Hz:
*val = LSM9DS1_XL_OFF_GY_476Hz;
break;
+
case LSM9DS1_XL_OFF_GY_952Hz:
*val = LSM9DS1_XL_OFF_GY_952Hz;
break;
+
case LSM9DS1_IMU_14Hz9:
*val = LSM9DS1_IMU_14Hz9;
break;
+
case LSM9DS1_IMU_59Hz5:
*val = LSM9DS1_IMU_59Hz5;
break;
+
case LSM9DS1_IMU_119Hz:
*val = LSM9DS1_IMU_119Hz;
break;
+
case LSM9DS1_IMU_238Hz:
*val = LSM9DS1_IMU_238Hz;
break;
+
case LSM9DS1_IMU_476Hz:
*val = LSM9DS1_IMU_476Hz;
break;
+
case LSM9DS1_IMU_952Hz:
*val = LSM9DS1_IMU_952Hz;
break;
+
case LSM9DS1_XL_OFF_GY_14Hz9_LP:
*val = LSM9DS1_XL_OFF_GY_14Hz9_LP;
break;
+
case LSM9DS1_XL_OFF_GY_59Hz5_LP:
*val = LSM9DS1_XL_OFF_GY_59Hz5_LP;
break;
+
case LSM9DS1_XL_OFF_GY_119Hz_LP:
*val = LSM9DS1_XL_OFF_GY_119Hz_LP;
break;
+
case LSM9DS1_IMU_14Hz9_LP:
*val = LSM9DS1_IMU_14Hz9_LP;
break;
+
case LSM9DS1_IMU_59Hz5_LP:
*val = LSM9DS1_IMU_59Hz5_LP;
break;
+
case LSM9DS1_IMU_119Hz_LP:
*val = LSM9DS1_IMU_119Hz_LP;
break;
+
default:
*val = LSM9DS1_IMU_OFF;
- break;
+ break;
}
return ret;
@@ -372,20 +436,25 @@ int32_t lsm9ds1_imu_data_rate_get(stmdev_ctx_t *ctx, lsm9ds1_imu_odr_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_gy_orient_set(stmdev_ctx_t *ctx, lsm9ds1_gy_orient_t val)
+int32_t lsm9ds1_gy_orient_set(stmdev_ctx_t *ctx,
+ lsm9ds1_gy_orient_t val)
{
lsm9ds1_orient_cfg_g_t orient_cfg_g;
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_ORIENT_CFG_G,
- (uint8_t*)&orient_cfg_g, 1);
- if(ret == 0) {
+ (uint8_t *)&orient_cfg_g, 1);
+
+ if (ret == 0)
+ {
orient_cfg_g.orient = val.orient;
orient_cfg_g.signx_g = val.signx_g;
orient_cfg_g.signy_g = val.signy_g;
orient_cfg_g.signz_g = val.signz_g;
- ret = lsm9ds1_write_reg(ctx, LSM9DS1_ORIENT_CFG_G, (uint8_t*)&orient_cfg_g, 1);
+ ret = lsm9ds1_write_reg(ctx, LSM9DS1_ORIENT_CFG_G,
+ (uint8_t *)&orient_cfg_g, 1);
}
+
return ret;
}
@@ -397,13 +466,14 @@ int32_t lsm9ds1_gy_orient_set(stmdev_ctx_t *ctx, lsm9ds1_gy_orient_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_gy_orient_get(stmdev_ctx_t *ctx, lsm9ds1_gy_orient_t *val)
+int32_t lsm9ds1_gy_orient_get(stmdev_ctx_t *ctx,
+ lsm9ds1_gy_orient_t *val)
{
lsm9ds1_orient_cfg_g_t orient_cfg_g;
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_ORIENT_CFG_G,
- (uint8_t*)&orient_cfg_g, 1);
+ (uint8_t *)&orient_cfg_g, 1);
val->orient = orient_cfg_g.orient;
val->signz_g = orient_cfg_g.signz_g;
val->signy_g = orient_cfg_g.signy_g;
@@ -420,12 +490,14 @@ int32_t lsm9ds1_gy_orient_get(stmdev_ctx_t *ctx, lsm9ds1_gy_orient_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm9ds1_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm9ds1_status_reg_t status_reg;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_STATUS_REG, (uint8_t*)&status_reg, 1);
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_STATUS_REG,
+ (uint8_t *)&status_reg, 1);
*val = status_reg.xlda;
return ret;
@@ -439,12 +511,14 @@ int32_t lsm9ds1_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm9ds1_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm9ds1_status_reg_t status_reg;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_STATUS_REG, (uint8_t*)&status_reg, 1);
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_STATUS_REG,
+ (uint8_t *)&status_reg, 1);
*val = status_reg.gda;
return ret;
@@ -458,12 +532,14 @@ int32_t lsm9ds1_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm9ds1_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm9ds1_status_reg_t status_reg;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_STATUS_REG, (uint8_t*)&status_reg, 1);
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_STATUS_REG,
+ (uint8_t *)&status_reg, 1);
*val = status_reg.tda;
return ret;
@@ -482,13 +558,16 @@ int32_t lsm9ds1_gy_axis_set(stmdev_ctx_t *ctx, lsm9ds1_gy_axis_t val)
lsm9ds1_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0) {
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.xen_g = val.xen_g;
ctrl_reg4.yen_g = val.yen_g;
ctrl_reg4.zen_g = val.zen_g;
- ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -505,7 +584,7 @@ int32_t lsm9ds1_gy_axis_get(stmdev_ctx_t *ctx, lsm9ds1_gy_axis_t *val)
lsm9ds1_ctrl_reg4_t ctrl_reg4;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
val->xen_g = ctrl_reg4.xen_g;
val->yen_g = ctrl_reg4.yen_g;
val->zen_g = ctrl_reg4.zen_g;
@@ -527,13 +606,17 @@ int32_t lsm9ds1_xl_axis_set(stmdev_ctx_t *ctx, lsm9ds1_xl_axis_t val)
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG5_XL,
- (uint8_t*)&ctrl_reg5_xl, 1);
- if(ret == 0) {
+ (uint8_t *)&ctrl_reg5_xl, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5_xl.xen_xl = val.xen_xl;
ctrl_reg5_xl.yen_xl = val.yen_xl;
ctrl_reg5_xl.zen_xl = val.zen_xl;
- ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG5_XL, (uint8_t*)&ctrl_reg5_xl, 1);
+ ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG5_XL,
+ (uint8_t *)&ctrl_reg5_xl, 1);
}
+
return ret;
}
@@ -551,7 +634,7 @@ int32_t lsm9ds1_xl_axis_get(stmdev_ctx_t *ctx, lsm9ds1_xl_axis_t *val)
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG5_XL,
- (uint8_t*)&ctrl_reg5_xl, 1);
+ (uint8_t *)&ctrl_reg5_xl, 1);
val->xen_xl = ctrl_reg5_xl.xen_xl;
val->yen_xl = ctrl_reg5_xl.yen_xl;
val->zen_xl = ctrl_reg5_xl.zen_xl;
@@ -567,18 +650,22 @@ int32_t lsm9ds1_xl_axis_get(stmdev_ctx_t *ctx, lsm9ds1_xl_axis_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_xl_decimation_set(stmdev_ctx_t *ctx, lsm9ds1_dec_t val)
+int32_t lsm9ds1_xl_decimation_set(stmdev_ctx_t *ctx,
+ lsm9ds1_dec_t val)
{
lsm9ds1_ctrl_reg5_xl_t ctrl_reg5_xl;
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG5_XL,
- (uint8_t*)&ctrl_reg5_xl, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg5_xl, 1);
+
+ if (ret == 0)
+ {
ctrl_reg5_xl.dec = (uint8_t)val;
ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG5_XL,
- (uint8_t*)&ctrl_reg5_xl, 1);
+ (uint8_t *)&ctrl_reg5_xl, 1);
}
+
return ret;
}
@@ -590,30 +677,38 @@ int32_t lsm9ds1_xl_decimation_set(stmdev_ctx_t *ctx, lsm9ds1_dec_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_xl_decimation_get(stmdev_ctx_t *ctx, lsm9ds1_dec_t *val)
+int32_t lsm9ds1_xl_decimation_get(stmdev_ctx_t *ctx,
+ lsm9ds1_dec_t *val)
{
lsm9ds1_ctrl_reg5_xl_t ctrl_reg5_xl;
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG5_XL,
- (uint8_t*)&ctrl_reg5_xl, 1);
- switch (ctrl_reg5_xl.dec){
+ (uint8_t *)&ctrl_reg5_xl, 1);
+
+ switch (ctrl_reg5_xl.dec)
+ {
case LSM9DS1_NO_DECIMATION:
*val = LSM9DS1_NO_DECIMATION;
break;
+
case LSM9DS1_EVERY_2_SAMPLES:
*val = LSM9DS1_EVERY_2_SAMPLES;
break;
+
case LSM9DS1_EVERY_4_SAMPLES:
*val = LSM9DS1_EVERY_4_SAMPLES;
break;
+
case LSM9DS1_EVERY_8_SAMPLES:
*val = LSM9DS1_EVERY_8_SAMPLES;
break;
+
default:
*val = LSM9DS1_NO_DECIMATION;
break;
}
+
return ret;
}
@@ -625,18 +720,22 @@ int32_t lsm9ds1_xl_decimation_get(stmdev_ctx_t *ctx, lsm9ds1_dec_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_xl_full_scale_set(stmdev_ctx_t *ctx, lsm9ds1_xl_fs_t val)
+int32_t lsm9ds1_xl_full_scale_set(stmdev_ctx_t *ctx,
+ lsm9ds1_xl_fs_t val)
{
lsm9ds1_ctrl_reg6_xl_t ctrl_reg6_xl;
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG6_XL,
- (uint8_t*)&ctrl_reg6_xl, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg6_xl, 1);
+
+ if (ret == 0)
+ {
ctrl_reg6_xl.fs_xl = (uint8_t)val;
ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG6_XL,
- (uint8_t*)&ctrl_reg6_xl, 1);
+ (uint8_t *)&ctrl_reg6_xl, 1);
}
+
return ret;
}
@@ -648,30 +747,38 @@ int32_t lsm9ds1_xl_full_scale_set(stmdev_ctx_t *ctx, lsm9ds1_xl_fs_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_xl_full_scale_get(stmdev_ctx_t *ctx, lsm9ds1_xl_fs_t *val)
+int32_t lsm9ds1_xl_full_scale_get(stmdev_ctx_t *ctx,
+ lsm9ds1_xl_fs_t *val)
{
lsm9ds1_ctrl_reg6_xl_t ctrl_reg6_xl;
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG6_XL,
- (uint8_t*)&ctrl_reg6_xl, 1);
- switch (ctrl_reg6_xl.fs_xl){
+ (uint8_t *)&ctrl_reg6_xl, 1);
+
+ switch (ctrl_reg6_xl.fs_xl)
+ {
case LSM9DS1_2g:
*val = LSM9DS1_2g;
break;
+
case LSM9DS1_16g:
*val = LSM9DS1_16g;
break;
+
case LSM9DS1_4g:
*val = LSM9DS1_4g;
break;
+
case LSM9DS1_8g:
*val = LSM9DS1_8g;
break;
+
default:
*val = LSM9DS1_2g;
break;
}
+
return ret;
}
@@ -691,20 +798,28 @@ int32_t lsm9ds1_block_data_update_set(stmdev_ctx_t *ctx_mag,
lsm9ds1_ctrl_reg5_m_t ctrl_reg5_m;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8, (uint8_t*)&ctrl_reg8, 1);
- if(ret == 0){
+ ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8,
+ (uint8_t *)&ctrl_reg8, 1);
+
+ if (ret == 0)
+ {
ctrl_reg8.bdu = (uint8_t)val;
- ret = lsm9ds1_write_reg(ctx_imu, LSM9DS1_CTRL_REG8, (uint8_t*)&ctrl_reg8, 1);
+ ret = lsm9ds1_write_reg(ctx_imu, LSM9DS1_CTRL_REG8,
+ (uint8_t *)&ctrl_reg8, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG5_M,
- (uint8_t*)&ctrl_reg5_m, 1);
+ (uint8_t *)&ctrl_reg5_m, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ctrl_reg5_m.fast_read = (uint8_t)(~val);
ctrl_reg5_m.bdu = (uint8_t)val;
ret = lsm9ds1_write_reg(ctx_mag, LSM9DS1_CTRL_REG5_M,
- (uint8_t*)&ctrl_reg5_m, 1);
+ (uint8_t *)&ctrl_reg5_m, 1);
}
return ret;
@@ -726,11 +841,16 @@ int32_t lsm9ds1_block_data_update_get(stmdev_ctx_t *ctx_mag,
lsm9ds1_ctrl_reg5_m_t ctrl_reg5_m;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8, (uint8_t*)&ctrl_reg8, 1);
- if(ret == 0){
- ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG5_M, (uint8_t*)&ctrl_reg5_m, 1);
+ ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8,
+ (uint8_t *)&ctrl_reg8, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG5_M,
+ (uint8_t *)&ctrl_reg5_m, 1);
*val = (uint8_t)(ctrl_reg5_m.bdu & ctrl_reg8.bdu);
}
+
return ret;
}
@@ -744,10 +864,19 @@ int32_t lsm9ds1_block_data_update_get(stmdev_ctx_t *ctx_mag,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_mag_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm9ds1_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
+ buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
+ buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
+ buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
+ buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
+ buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
+ buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
ret = lsm9ds1_write_reg(ctx, LSM9DS1_OFFSET_X_REG_L_M, buff, 6);
+
return ret;
}
@@ -761,10 +890,19 @@ int32_t lsm9ds1_mag_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_mag_offset_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm9ds1_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lsm9ds1_read_reg(ctx, LSM9DS1_OFFSET_X_REG_L_M, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -784,32 +922,45 @@ int32_t lsm9ds1_mag_data_rate_set(stmdev_ctx_t *ctx,
lsm9ds1_ctrl_reg4_m_t ctrl_reg4_m;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_M, (uint8_t*)&ctrl_reg1_m, 1);
- if(ret == 0){
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_M,
+ (uint8_t *)&ctrl_reg1_m, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1_m.fast_odr = (((uint8_t)val & 0x08U) >> 3);
ctrl_reg1_m._do = ((uint8_t)val & 0x07U);
ctrl_reg1_m.om = (((uint8_t)val & 0x30U) >> 4);
ctrl_reg1_m.temp_comp = PROPERTY_ENABLE;
ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG1_M,
- (uint8_t*)&ctrl_reg1_m, 1);
+ (uint8_t *)&ctrl_reg1_m, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG3_M,
- (uint8_t*)&ctrl_reg3_m, 1);
+ (uint8_t *)&ctrl_reg3_m, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ctrl_reg3_m.md = (((uint8_t)val & 0xC0U) >> 6);
ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG3_M,
- (uint8_t*)&ctrl_reg3_m, 1);
+ (uint8_t *)&ctrl_reg3_m, 1);
}
- if(ret == 0){
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG4_M, (uint8_t*)&ctrl_reg4_m, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG4_M,
+ (uint8_t *)&ctrl_reg4_m, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ctrl_reg4_m.omz = (((uint8_t)val & 0x30U) >> 4);;
ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG4_M,
- (uint8_t*)&ctrl_reg4_m, 1);
+ (uint8_t *)&ctrl_reg4_m, 1);
}
+
return ret;
}
@@ -828,130 +979,175 @@ int32_t lsm9ds1_mag_data_rate_get(stmdev_ctx_t *ctx,
lsm9ds1_ctrl_reg3_m_t ctrl_reg3_m;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_M, (uint8_t*)&ctrl_reg1_m, 1);
- if(ret == 0){
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG3_M, (uint8_t*)&ctrl_reg3_m, 1);
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_M,
+ (uint8_t *)&ctrl_reg1_m, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG3_M,
+ (uint8_t *)&ctrl_reg3_m, 1);
}
+
switch ((ctrl_reg3_m.md << 6) | (ctrl_reg1_m.om << 4) |
- (ctrl_reg1_m.fast_odr << 3) | ctrl_reg1_m._do){
+ (ctrl_reg1_m.fast_odr << 3) | ctrl_reg1_m._do)
+ {
case LSM9DS1_MAG_POWER_DOWN:
*val = LSM9DS1_MAG_POWER_DOWN;
break;
+
case LSM9DS1_MAG_LP_0Hz625:
*val = LSM9DS1_MAG_LP_0Hz625;
break;
+
case LSM9DS1_MAG_LP_1Hz25:
*val = LSM9DS1_MAG_LP_1Hz25;
break;
+
case LSM9DS1_MAG_LP_2Hz5:
*val = LSM9DS1_MAG_LP_2Hz5;
break;
+
case LSM9DS1_MAG_LP_5Hz:
*val = LSM9DS1_MAG_LP_5Hz;
break;
+
case LSM9DS1_MAG_LP_10Hz:
*val = LSM9DS1_MAG_LP_10Hz;
break;
+
case LSM9DS1_MAG_LP_20Hz:
*val = LSM9DS1_MAG_LP_20Hz;
break;
+
case LSM9DS1_MAG_LP_40Hz:
*val = LSM9DS1_MAG_LP_40Hz;
break;
+
case LSM9DS1_MAG_LP_80Hz:
*val = LSM9DS1_MAG_LP_80Hz;
break;
+
case LSM9DS1_MAG_MP_0Hz625:
*val = LSM9DS1_MAG_MP_0Hz625;
break;
+
case LSM9DS1_MAG_MP_1Hz25:
*val = LSM9DS1_MAG_MP_1Hz25;
break;
+
case LSM9DS1_MAG_MP_2Hz5:
*val = LSM9DS1_MAG_MP_2Hz5;
break;
+
case LSM9DS1_MAG_MP_5Hz:
*val = LSM9DS1_MAG_MP_5Hz;
break;
+
case LSM9DS1_MAG_MP_10Hz:
*val = LSM9DS1_MAG_MP_10Hz;
break;
+
case LSM9DS1_MAG_MP_20Hz:
*val = LSM9DS1_MAG_MP_20Hz;
break;
+
case LSM9DS1_MAG_MP_40Hz:
*val = LSM9DS1_MAG_MP_40Hz;
break;
+
case LSM9DS1_MAG_MP_80Hz:
*val = LSM9DS1_MAG_MP_80Hz;
break;
+
case LSM9DS1_MAG_HP_0Hz625:
*val = LSM9DS1_MAG_HP_0Hz625;
break;
+
case LSM9DS1_MAG_HP_1Hz25:
*val = LSM9DS1_MAG_HP_1Hz25;
break;
+
case LSM9DS1_MAG_HP_2Hz5:
*val = LSM9DS1_MAG_HP_2Hz5;
break;
+
case LSM9DS1_MAG_HP_5Hz:
*val = LSM9DS1_MAG_HP_5Hz;
break;
+
case LSM9DS1_MAG_HP_10Hz:
*val = LSM9DS1_MAG_HP_10Hz;
break;
+
case LSM9DS1_MAG_HP_20Hz:
*val = LSM9DS1_MAG_HP_20Hz;
break;
+
case LSM9DS1_MAG_HP_40Hz:
*val = LSM9DS1_MAG_HP_40Hz;
break;
+
case LSM9DS1_MAG_HP_80Hz:
*val = LSM9DS1_MAG_HP_80Hz;
break;
+
case LSM9DS1_MAG_UHP_0Hz625:
*val = LSM9DS1_MAG_UHP_0Hz625;
break;
+
case LSM9DS1_MAG_UHP_1Hz25:
*val = LSM9DS1_MAG_UHP_1Hz25;
break;
+
case LSM9DS1_MAG_UHP_2Hz5:
*val = LSM9DS1_MAG_UHP_2Hz5;
break;
+
case LSM9DS1_MAG_UHP_5Hz:
*val = LSM9DS1_MAG_UHP_5Hz;
break;
+
case LSM9DS1_MAG_UHP_10Hz:
*val = LSM9DS1_MAG_UHP_10Hz;
break;
+
case LSM9DS1_MAG_UHP_20Hz:
*val = LSM9DS1_MAG_UHP_20Hz;
break;
+
case LSM9DS1_MAG_UHP_40Hz:
*val = LSM9DS1_MAG_UHP_40Hz;
break;
+
case LSM9DS1_MAG_UHP_80Hz:
*val = LSM9DS1_MAG_UHP_80Hz;
break;
+
case LSM9DS1_MAG_UHP_155Hz:
*val = LSM9DS1_MAG_UHP_155Hz;
break;
+
case LSM9DS1_MAG_HP_300Hz:
*val = LSM9DS1_MAG_HP_300Hz;
break;
+
case LSM9DS1_MAG_MP_560Hz:
*val = LSM9DS1_MAG_MP_560Hz;
break;
+
case LSM9DS1_MAG_LP_1000Hz:
*val = LSM9DS1_MAG_LP_1000Hz;
break;
+
case LSM9DS1_MAG_ONE_SHOT:
*val = LSM9DS1_MAG_ONE_SHOT;
break;
+
default:
*val = LSM9DS1_MAG_POWER_DOWN;
break;
}
+
return ret;
}
@@ -963,17 +1159,22 @@ int32_t lsm9ds1_mag_data_rate_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_mag_full_scale_set(stmdev_ctx_t *ctx, lsm9ds1_mag_fs_t val)
+int32_t lsm9ds1_mag_full_scale_set(stmdev_ctx_t *ctx,
+ lsm9ds1_mag_fs_t val)
{
lsm9ds1_ctrl_reg2_m_t ctrl_reg2_m;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG2_M, (uint8_t*)&ctrl_reg2_m, 1);
- if(ret == 0){
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG2_M,
+ (uint8_t *)&ctrl_reg2_m, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2_m.fs = (uint8_t)val;
ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG2_M,
- (uint8_t*)&ctrl_reg2_m, 1);
+ (uint8_t *)&ctrl_reg2_m, 1);
}
+
return ret;
}
@@ -985,29 +1186,38 @@ int32_t lsm9ds1_mag_full_scale_set(stmdev_ctx_t *ctx, lsm9ds1_mag_fs_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_mag_full_scale_get(stmdev_ctx_t *ctx, lsm9ds1_mag_fs_t *val)
+int32_t lsm9ds1_mag_full_scale_get(stmdev_ctx_t *ctx,
+ lsm9ds1_mag_fs_t *val)
{
lsm9ds1_ctrl_reg2_m_t ctrl_reg2_m;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG2_M, (uint8_t*)&ctrl_reg2_m, 1);
- switch (ctrl_reg2_m.fs){
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG2_M,
+ (uint8_t *)&ctrl_reg2_m, 1);
+
+ switch (ctrl_reg2_m.fs)
+ {
case LSM9DS1_4Ga:
*val = LSM9DS1_4Ga;
break;
+
case LSM9DS1_8Ga:
*val = LSM9DS1_8Ga;
break;
+
case LSM9DS1_12Ga:
*val = LSM9DS1_12Ga;
break;
+
case LSM9DS1_16Ga:
*val = LSM9DS1_16Ga;
break;
+
default:
*val = LSM9DS1_4Ga;
break;
}
+
return ret;
}
@@ -1019,13 +1229,14 @@ int32_t lsm9ds1_mag_full_scale_get(stmdev_ctx_t *ctx, lsm9ds1_mag_fs_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_mag_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm9ds1_mag_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm9ds1_status_reg_m_t status_reg_m;
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_STATUS_REG_M,
- (uint8_t*)&status_reg_m, 1);
+ (uint8_t *)&status_reg_m, 1);
*val = status_reg_m.zyxda;
return ret;
@@ -1052,10 +1263,15 @@ int32_t lsm9ds1_mag_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm9ds1_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[2];
int32_t ret;
+
ret = lsm9ds1_read_reg(ctx, LSM9DS1_OUT_TEMP_L, buff, 2);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+
return ret;
}
@@ -1068,10 +1284,19 @@ int32_t lsm9ds1_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm9ds1_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lsm9ds1_read_reg(ctx, LSM9DS1_OUT_X_L_G, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -1084,10 +1309,19 @@ int32_t lsm9ds1_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm9ds1_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lsm9ds1_read_reg(ctx, LSM9DS1_OUT_X_L_XL, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -1100,10 +1334,19 @@ int32_t lsm9ds1_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_magnetic_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm9ds1_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
+ uint8_t buff[6];
int32_t ret;
+
ret = lsm9ds1_read_reg(ctx, LSM9DS1_OUT_X_L_M, buff, 6);
+ val[0] = (int16_t)buff[1];
+ val[0] = (val[0] * 256) + (int16_t)buff[0];
+ val[1] = (int16_t)buff[3];
+ val[1] = (val[1] * 256) + (int16_t)buff[2];
+ val[2] = (int16_t)buff[5];
+ val[2] = (val[2] * 256) + (int16_t)buff[4];
+
return ret;
}
@@ -1120,7 +1363,7 @@ int32_t lsm9ds1_magnetic_overflow_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm9ds1_int_src_m_t int_src_m;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_SRC_M, (uint8_t*)&int_src_m, 1);
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_SRC_M, (uint8_t *)&int_src_m, 1);
*val = int_src_m.mroi;
return ret;
@@ -1133,7 +1376,7 @@ int32_t lsm9ds1_magnetic_overflow_get(stmdev_ctx_t *ctx, uint8_t *val)
/**
* @defgroup LSM9DS1_Common
- * @brief This section groups common usefull functions.
+ * @brief This section groups common useful functions.
* @{
*
*/
@@ -1147,16 +1390,21 @@ int32_t lsm9ds1_magnetic_overflow_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_dev_id_get(stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu,
+int32_t lsm9ds1_dev_id_get(stmdev_ctx_t *ctx_mag,
+ stmdev_ctx_t *ctx_imu,
lsm9ds1_id_t *buff)
{
int32_t ret;
+
ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_WHO_AM_I,
- (uint8_t*)&(buff->imu), 1);
- if(ret == 0){
+ (uint8_t *) & (buff->imu), 1);
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_WHO_AM_I_M,
- (uint8_t*)&(buff->mag), 1);
+ (uint8_t *) & (buff->mag), 1);
}
+
return ret;
}
@@ -1169,16 +1417,19 @@ int32_t lsm9ds1_dev_id_get(stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_dev_status_get(stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu,
+int32_t lsm9ds1_dev_status_get(stmdev_ctx_t *ctx_mag,
+ stmdev_ctx_t *ctx_imu,
lsm9ds1_status_t *val)
{
int32_t ret;
ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_STATUS_REG,
- (uint8_t*)&(val->status_imu), 1);
- if(ret == 0){
+ (uint8_t *) & (val->status_imu), 1);
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_STATUS_REG_M,
- (uint8_t*)&(val->status_mag), 1);
+ (uint8_t *) & (val->status_mag), 1);
}
return ret;
@@ -1193,27 +1444,35 @@ int32_t lsm9ds1_dev_status_get(stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_dev_reset_set(stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu,
+int32_t lsm9ds1_dev_reset_set(stmdev_ctx_t *ctx_mag,
+ stmdev_ctx_t *ctx_imu,
uint8_t val)
{
lsm9ds1_ctrl_reg2_m_t ctrl_reg2_m;
lsm9ds1_ctrl_reg8_t ctrl_reg8;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8, (uint8_t*)&ctrl_reg8, 1);
- if(ret == 0){
+ ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8,
+ (uint8_t *)&ctrl_reg8, 1);
+
+ if (ret == 0)
+ {
ctrl_reg8.sw_reset = (uint8_t)val;
ret = lsm9ds1_write_reg(ctx_imu, LSM9DS1_CTRL_REG8,
- (uint8_t*)&ctrl_reg8, 1);
+ (uint8_t *)&ctrl_reg8, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG2_M,
- (uint8_t*)&ctrl_reg2_m, 1);
+ (uint8_t *)&ctrl_reg2_m, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ctrl_reg2_m.soft_rst = (uint8_t)val;
ret = lsm9ds1_write_reg(ctx_mag, LSM9DS1_CTRL_REG2_M,
- (uint8_t*)&ctrl_reg2_m, 1);
+ (uint8_t *)&ctrl_reg2_m, 1);
}
return ret;
@@ -1228,19 +1487,24 @@ int32_t lsm9ds1_dev_reset_set(stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_dev_reset_get(stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu,
+int32_t lsm9ds1_dev_reset_get(stmdev_ctx_t *ctx_mag,
+ stmdev_ctx_t *ctx_imu,
uint8_t *val)
{
lsm9ds1_ctrl_reg2_m_t ctrl_reg2_m;
lsm9ds1_ctrl_reg8_t ctrl_reg8;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8, (uint8_t*)&ctrl_reg8, 1);
- if(ret == 0){
+ ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8,
+ (uint8_t *)&ctrl_reg8, 1);
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG2_M,
- (uint8_t*)&ctrl_reg2_m, 1);
+ (uint8_t *)&ctrl_reg2_m, 1);
*val = (uint8_t)(ctrl_reg2_m.soft_rst | ctrl_reg8.sw_reset);
}
+
return ret;
}
@@ -1262,21 +1526,28 @@ int32_t lsm9ds1_dev_data_format_set(stmdev_ctx_t *ctx_mag,
int32_t ret;
ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8,
- (uint8_t*)&ctrl_reg8, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg8, 1);
+
+ if (ret == 0)
+ {
ctrl_reg8.ble = (uint8_t)val;
ret = lsm9ds1_write_reg(ctx_imu, LSM9DS1_CTRL_REG8,
- (uint8_t*)&ctrl_reg8, 1);
+ (uint8_t *)&ctrl_reg8, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG4_M,
- (uint8_t*)&ctrl_reg4_m, 1);
+ (uint8_t *)&ctrl_reg4_m, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ctrl_reg4_m.ble = (uint8_t)val;
ret = lsm9ds1_write_reg(ctx_mag, LSM9DS1_CTRL_REG4_M,
- (uint8_t*)&ctrl_reg4_m, 1);
+ (uint8_t *)&ctrl_reg4_m, 1);
}
+
return ret;
}
@@ -1297,22 +1568,30 @@ int32_t lsm9ds1_dev_data_format_get(stmdev_ctx_t *ctx_mag,
lsm9ds1_ctrl_reg4_m_t ctrl_reg4_m;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8, (uint8_t*)&ctrl_reg8, 1);
- if(ret == 0){
+ ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8,
+ (uint8_t *)&ctrl_reg8, 1);
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG4_M,
- (uint8_t*)&ctrl_reg4_m, 1);
+ (uint8_t *)&ctrl_reg4_m, 1);
}
- switch (ctrl_reg8.ble & ctrl_reg4_m.ble){
+
+ switch (ctrl_reg8.ble & ctrl_reg4_m.ble)
+ {
case LSM9DS1_LSB_LOW_ADDRESS:
*val = LSM9DS1_LSB_LOW_ADDRESS;
break;
+
case LSM9DS1_MSB_LOW_ADDRESS:
*val = LSM9DS1_MSB_LOW_ADDRESS;
break;
+
default:
*val = LSM9DS1_LSB_LOW_ADDRESS;
break;
}
+
return ret;
}
@@ -1325,7 +1604,8 @@ int32_t lsm9ds1_dev_data_format_get(stmdev_ctx_t *ctx_mag,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_dev_boot_set(stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu,
+int32_t lsm9ds1_dev_boot_set(stmdev_ctx_t *ctx_mag,
+ stmdev_ctx_t *ctx_imu,
uint8_t val)
{
lsm9ds1_ctrl_reg8_t ctrl_reg8;
@@ -1333,21 +1613,28 @@ int32_t lsm9ds1_dev_boot_set(stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu,
int32_t ret;
ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8,
- (uint8_t*)&ctrl_reg8, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg8, 1);
+
+ if (ret == 0)
+ {
ctrl_reg8.boot = (uint8_t)val;
ret = lsm9ds1_write_reg(ctx_imu, LSM9DS1_CTRL_REG8,
- (uint8_t*)&ctrl_reg8, 1);
+ (uint8_t *)&ctrl_reg8, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG2_M,
- (uint8_t*)&ctrl_reg2_m, 1);
+ (uint8_t *)&ctrl_reg2_m, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ctrl_reg2_m.reboot = (uint8_t)val;
ret = lsm9ds1_write_reg(ctx_mag, LSM9DS1_CTRL_REG2_M,
- (uint8_t*)&ctrl_reg2_m, 1);
+ (uint8_t *)&ctrl_reg2_m, 1);
}
+
return ret;
}
@@ -1360,19 +1647,24 @@ int32_t lsm9ds1_dev_boot_set(stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_dev_boot_get(stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu,
+int32_t lsm9ds1_dev_boot_get(stmdev_ctx_t *ctx_mag,
+ stmdev_ctx_t *ctx_imu,
uint8_t *val)
{
lsm9ds1_ctrl_reg2_m_t ctrl_reg2_m;
lsm9ds1_ctrl_reg8_t ctrl_reg8;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8, (uint8_t*)&ctrl_reg8, 1);
- if(ret == 0){
- ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG2_M,
- (uint8_t*)&ctrl_reg2_m, 1);
+ ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8,
+ (uint8_t *)&ctrl_reg8, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG2_M,
+ (uint8_t *)&ctrl_reg2_m, 1);
*val = (uint8_t)ctrl_reg2_m.reboot & ctrl_reg8.boot;
}
+
return ret;
}
@@ -1397,10 +1689,13 @@ int32_t lsm9ds1_dev_boot_get(stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_gy_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm9ds1_gy_filter_reference_set(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
+
ret = lsm9ds1_write_reg(ctx, LSM9DS1_REFERENCE_G, buff, 1);
+
return ret;
}
@@ -1412,10 +1707,13 @@ int32_t lsm9ds1_gy_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_gy_filter_reference_get(stmdev_ctx_t *ctx, uint8_t *buff)
+int32_t lsm9ds1_gy_filter_reference_get(stmdev_ctx_t *ctx,
+ uint8_t *buff)
{
int32_t ret;
+
ret = lsm9ds1_read_reg(ctx, LSM9DS1_REFERENCE_G, buff, 1);
+
return ret;
}
@@ -1433,12 +1731,16 @@ int32_t lsm9ds1_gy_filter_lp_bandwidth_set(stmdev_ctx_t *ctx,
lsm9ds1_ctrl_reg1_g_t ctrl_reg1_g;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_G, (uint8_t*)&ctrl_reg1_g, 1);
- if(ret == 0){
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_G,
+ (uint8_t *)&ctrl_reg1_g, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1_g.bw_g = (uint8_t)val;
ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG1_G,
- (uint8_t*)&ctrl_reg1_g, 1);
+ (uint8_t *)&ctrl_reg1_g, 1);
}
+
return ret;
}
@@ -1456,24 +1758,32 @@ int32_t lsm9ds1_gy_filter_lp_bandwidth_get(stmdev_ctx_t *ctx,
lsm9ds1_ctrl_reg1_g_t ctrl_reg1_g;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_G, (uint8_t*)&ctrl_reg1_g, 1);
- switch (ctrl_reg1_g.bw_g){
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_G,
+ (uint8_t *)&ctrl_reg1_g, 1);
+
+ switch (ctrl_reg1_g.bw_g)
+ {
case LSM9DS1_LP_STRONG:
*val = LSM9DS1_LP_STRONG;
break;
+
case LSM9DS1_LP_MEDIUM:
*val = LSM9DS1_LP_MEDIUM;
break;
+
case LSM9DS1_LP_LIGHT:
*val = LSM9DS1_LP_LIGHT;
break;
+
case LSM9DS1_LP_ULTRA_LIGHT:
*val = LSM9DS1_LP_ULTRA_LIGHT;
break;
+
default:
*val = LSM9DS1_LP_STRONG;
break;
}
+
return ret;
}
@@ -1493,20 +1803,26 @@ int32_t lsm9ds1_gy_filter_out_path_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG2_G,
- (uint8_t*)&ctrl_reg2_g, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg2_g, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2_g.out_sel = ((uint8_t)val & 0x03U);
ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG2_G,
- (uint8_t*)&ctrl_reg2_g, 1);
+ (uint8_t *)&ctrl_reg2_g, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG3_G,
- (uint8_t*)&ctrl_reg3_g, 1);
+ (uint8_t *)&ctrl_reg3_g, 1);
}
- if(ret == 0){
- ctrl_reg3_g.hp_en = (((uint8_t)val & 0x10U) >> 4 );
+
+ if (ret == 0)
+ {
+ ctrl_reg3_g.hp_en = (((uint8_t)val & 0x10U) >> 4);
ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG3_G,
- (uint8_t*)&ctrl_reg3_g, 1);
+ (uint8_t *)&ctrl_reg3_g, 1);
}
return ret;
@@ -1528,24 +1844,32 @@ int32_t lsm9ds1_gy_filter_out_path_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG2_G,
- (uint8_t*)&ctrl_reg2_g, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg2_g, 1);
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG3_G,
- (uint8_t*)&ctrl_reg3_g, 1);
+ (uint8_t *)&ctrl_reg3_g, 1);
}
- switch ( (ctrl_reg3_g.hp_en << 4) | ctrl_reg2_g.out_sel){
+
+ switch ((ctrl_reg3_g.hp_en << 4) | ctrl_reg2_g.out_sel)
+ {
case LSM9DS1_LPF1_OUT:
*val = LSM9DS1_LPF1_OUT;
break;
+
case LSM9DS1_LPF1_HPF_OUT:
*val = LSM9DS1_LPF1_HPF_OUT;
break;
+
case LSM9DS1_LPF1_LPF2_OUT:
*val = LSM9DS1_LPF1_LPF2_OUT;
break;
+
case LSM9DS1_LPF1_HPF_LPF2_OUT:
*val = LSM9DS1_LPF1_HPF_LPF2_OUT;
break;
+
default:
*val = LSM9DS1_LPF1_OUT;
break;
@@ -1570,21 +1894,28 @@ int32_t lsm9ds1_gy_filter_int_path_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG2_G,
- (uint8_t*)&ctrl_reg2_g, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg2_g, 1);
+
+ if (ret == 0)
+ {
ctrl_reg2_g.int_sel = ((uint8_t)val & 0x03U);
ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG2_G,
- (uint8_t*)&ctrl_reg2_g, 1);
+ (uint8_t *)&ctrl_reg2_g, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG3_G,
- (uint8_t*)&ctrl_reg3_g, 1);
+ (uint8_t *)&ctrl_reg3_g, 1);
}
- if(ret == 0){
- ctrl_reg3_g.hp_en = (((uint8_t)val & 0x10U) >> 4 );
+
+ if (ret == 0)
+ {
+ ctrl_reg3_g.hp_en = (((uint8_t)val & 0x10U) >> 4);
ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG3_G,
- (uint8_t*)&ctrl_reg3_g, 1);
+ (uint8_t *)&ctrl_reg3_g, 1);
}
+
return ret;
}
@@ -1604,28 +1935,37 @@ int32_t lsm9ds1_gy_filter_int_path_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG2_G,
- (uint8_t*)&ctrl_reg2_g, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg2_g, 1);
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG3_G,
- (uint8_t*)&ctrl_reg3_g, 1);
+ (uint8_t *)&ctrl_reg3_g, 1);
}
- switch ( (ctrl_reg3_g.hp_en << 4) | ctrl_reg2_g.int_sel){
+
+ switch ((ctrl_reg3_g.hp_en << 4) | ctrl_reg2_g.int_sel)
+ {
case LSM9DS1_LPF1_INT:
*val = LSM9DS1_LPF1_INT;
break;
+
case LSM9DS1_LPF1_HPF_INT:
*val = LSM9DS1_LPF1_HPF_INT;
break;
+
case LSM9DS1_LPF1_LPF2_INT:
*val = LSM9DS1_LPF1_LPF2_INT;
break;
+
case LSM9DS1_LPF1_HPF_LPF2_INT:
*val = LSM9DS1_LPF1_HPF_LPF2_INT;
break;
+
default:
*val = LSM9DS1_LPF1_INT;
break;
}
+
return ret;
}
@@ -1643,12 +1983,16 @@ int32_t lsm9ds1_gy_filter_hp_bandwidth_set(stmdev_ctx_t *ctx,
lsm9ds1_ctrl_reg3_g_t ctrl_reg3_g;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG3_G, (uint8_t*)&ctrl_reg3_g, 1);
- if(ret == 0){
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG3_G,
+ (uint8_t *)&ctrl_reg3_g, 1);
+
+ if (ret == 0)
+ {
ctrl_reg3_g.hpcf_g = (uint8_t)val;
ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG3_G,
- (uint8_t*)&ctrl_reg3_g, 1);
+ (uint8_t *)&ctrl_reg3_g, 1);
}
+
return ret;
}
@@ -1667,42 +2011,55 @@ int32_t lsm9ds1_gy_filter_hp_bandwidth_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG3_G,
- (uint8_t*)&ctrl_reg3_g, 1);
- switch (ctrl_reg3_g.hpcf_g){
+ (uint8_t *)&ctrl_reg3_g, 1);
+
+ switch (ctrl_reg3_g.hpcf_g)
+ {
case LSM9DS1_HP_EXTREME:
*val = LSM9DS1_HP_EXTREME;
break;
+
case LSM9DS1_HP_ULTRA_STRONG:
*val = LSM9DS1_HP_ULTRA_STRONG;
break;
+
case LSM9DS1_HP_STRONG:
*val = LSM9DS1_HP_STRONG;
break;
+
case LSM9DS1_HP_ULTRA_HIGH:
*val = LSM9DS1_HP_ULTRA_HIGH;
break;
+
case LSM9DS1_HP_HIGH:
*val = LSM9DS1_HP_HIGH;
break;
+
case LSM9DS1_HP_MEDIUM:
*val = LSM9DS1_HP_MEDIUM;
break;
+
case LSM9DS1_HP_LOW:
*val = LSM9DS1_HP_LOW;
break;
+
case LSM9DS1_HP_ULTRA_LOW:
*val = LSM9DS1_HP_ULTRA_LOW;
break;
+
case LSM9DS1_HP_LIGHT:
*val = LSM9DS1_HP_LIGHT;
break;
+
case LSM9DS1_HP_ULTRA_LIGHT:
*val = LSM9DS1_HP_ULTRA_LIGHT;
break;
+
default:
*val = LSM9DS1_HP_EXTREME;
break;
}
+
return ret;
}
@@ -1721,13 +2078,16 @@ int32_t lsm9ds1_xl_filter_aalias_bandwidth_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG6_XL,
- (uint8_t*)&ctrl_reg6_xl, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg6_xl, 1);
+
+ if (ret == 0)
+ {
ctrl_reg6_xl.bw_xl = ((uint8_t)val & 0x03U);
- ctrl_reg6_xl.bw_scal_odr = (((uint8_t)val & 0x10U) >> 4 );
+ ctrl_reg6_xl.bw_scal_odr = (((uint8_t)val & 0x10U) >> 4);
ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG6_XL,
- (uint8_t*)&ctrl_reg6_xl, 1);
+ (uint8_t *)&ctrl_reg6_xl, 1);
}
+
return ret;
}
@@ -1746,27 +2106,35 @@ int32_t lsm9ds1_xl_filter_aalias_bandwidth_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG6_XL,
- (uint8_t*)&ctrl_reg6_xl, 1);
- switch ((ctrl_reg6_xl.bw_scal_odr << 4) | ctrl_reg6_xl.bw_xl){
+ (uint8_t *)&ctrl_reg6_xl, 1);
+
+ switch ((ctrl_reg6_xl.bw_scal_odr << 4) | ctrl_reg6_xl.bw_xl)
+ {
case LSM9DS1_AUTO:
*val = LSM9DS1_AUTO;
break;
+
case LSM9DS1_408Hz:
*val = LSM9DS1_408Hz;
break;
+
case LSM9DS1_211Hz:
*val = LSM9DS1_211Hz;
break;
+
case LSM9DS1_105Hz:
*val = LSM9DS1_105Hz;
break;
+
case LSM9DS1_50Hz:
*val = LSM9DS1_50Hz;
break;
+
default:
*val = LSM9DS1_AUTO;
break;
}
+
return ret;
}
@@ -1785,12 +2153,15 @@ int32_t lsm9ds1_xl_filter_int_path_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG7_XL,
- (uint8_t*)&ctrl_reg7_xl, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg7_xl, 1);
+
+ if (ret == 0)
+ {
ctrl_reg7_xl.hpis1 = (uint8_t)val;
ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG7_XL,
- (uint8_t*)&ctrl_reg7_xl, 1);
+ (uint8_t *)&ctrl_reg7_xl, 1);
}
+
return ret;
}
@@ -1809,18 +2180,23 @@ int32_t lsm9ds1_xl_filter_int_path_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG7_XL,
- (uint8_t*)&ctrl_reg7_xl, 1);
- switch (ctrl_reg7_xl.hpis1){
+ (uint8_t *)&ctrl_reg7_xl, 1);
+
+ switch (ctrl_reg7_xl.hpis1)
+ {
case LSM9DS1_HP_DIS:
*val = LSM9DS1_HP_DIS;
break;
+
case LSM9DS1_HP_EN:
*val = LSM9DS1_HP_EN;
break;
+
default:
*val = LSM9DS1_HP_DIS;
break;
}
+
return ret;
}
@@ -1839,12 +2215,15 @@ int32_t lsm9ds1_xl_filter_out_path_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG7_XL,
- (uint8_t*)&ctrl_reg7_xl, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg7_xl, 1);
+
+ if (ret == 0)
+ {
ctrl_reg7_xl.fds = (uint8_t)val;
ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG7_XL,
- (uint8_t*)&ctrl_reg7_xl, 1);
+ (uint8_t *)&ctrl_reg7_xl, 1);
}
+
return ret;
}
@@ -1863,18 +2242,23 @@ int32_t lsm9ds1_xl_filter_out_path_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG7_XL,
- (uint8_t*)&ctrl_reg7_xl, 1);
- switch (ctrl_reg7_xl.fds){
+ (uint8_t *)&ctrl_reg7_xl, 1);
+
+ switch (ctrl_reg7_xl.fds)
+ {
case LSM9DS1_LP_OUT:
*val = LSM9DS1_LP_OUT;
break;
+
case LSM9DS1_HP_OUT:
*val = LSM9DS1_HP_OUT;
break;
+
default:
*val = LSM9DS1_LP_OUT;
break;
}
+
return ret;
}
@@ -1894,13 +2278,16 @@ int32_t lsm9ds1_xl_filter_lp_bandwidth_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG7_XL,
- (uint8_t*)&ctrl_reg7_xl, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg7_xl, 1);
+
+ if (ret == 0)
+ {
ctrl_reg7_xl.hr = ((uint8_t)val & 0x10U) >> 4;
ctrl_reg7_xl.dcf = ((uint8_t)val & 0x03U);
ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG7_XL,
- (uint8_t*)&ctrl_reg7_xl, 1);
+ (uint8_t *)&ctrl_reg7_xl, 1);
}
+
return ret;
}
@@ -1920,27 +2307,35 @@ int32_t lsm9ds1_xl_filter_lp_bandwidth_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG7_XL,
- (uint8_t*)&ctrl_reg7_xl, 1);
- switch ((ctrl_reg7_xl.hr << 4) + ctrl_reg7_xl.dcf){
+ (uint8_t *)&ctrl_reg7_xl, 1);
+
+ switch ((ctrl_reg7_xl.hr << 4) + ctrl_reg7_xl.dcf)
+ {
case LSM9DS1_LP_DISABLE:
*val = LSM9DS1_LP_DISABLE;
break;
+
case LSM9DS1_LP_ODR_DIV_50:
*val = LSM9DS1_LP_ODR_DIV_50;
break;
+
case LSM9DS1_LP_ODR_DIV_100:
*val = LSM9DS1_LP_ODR_DIV_100;
break;
+
case LSM9DS1_LP_ODR_DIV_9:
*val = LSM9DS1_LP_ODR_DIV_9;
break;
+
case LSM9DS1_LP_ODR_DIV_400:
*val = LSM9DS1_LP_ODR_DIV_400;
break;
+
default:
*val = LSM9DS1_LP_DISABLE;
break;
}
+
return ret;
}
@@ -1960,12 +2355,15 @@ int32_t lsm9ds1_xl_filter_hp_bandwidth_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG7_XL,
- (uint8_t*)&ctrl_reg7_xl, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg7_xl, 1);
+
+ if (ret == 0)
+ {
ctrl_reg7_xl.dcf = (uint8_t)val;
ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG7_XL,
- (uint8_t*)&ctrl_reg7_xl, 1);
+ (uint8_t *)&ctrl_reg7_xl, 1);
}
+
return ret;
}
@@ -1985,25 +2383,31 @@ int32_t lsm9ds1_xl_filter_hp_bandwidth_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG7_XL,
- (uint8_t*)&ctrl_reg7_xl, 1);
+ (uint8_t *)&ctrl_reg7_xl, 1);
- switch (ctrl_reg7_xl.dcf){
+ switch (ctrl_reg7_xl.dcf)
+ {
case LSM9DS1_HP_ODR_DIV_50:
*val = LSM9DS1_HP_ODR_DIV_50;
break;
+
case LSM9DS1_HP_ODR_DIV_100:
*val = LSM9DS1_HP_ODR_DIV_100;
break;
+
case LSM9DS1_HP_ODR_DIV_9:
*val = LSM9DS1_HP_ODR_DIV_9;
break;
+
case LSM9DS1_HP_ODR_DIV_400:
*val = LSM9DS1_HP_ODR_DIV_400;
break;
+
default:
*val = LSM9DS1_HP_ODR_DIV_50;
break;
}
+
return ret;
}
@@ -2015,16 +2419,20 @@ int32_t lsm9ds1_xl_filter_hp_bandwidth_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm9ds1_filter_settling_mask_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm9ds1_ctrl_reg9_t ctrl_reg9;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t*)&ctrl_reg9, 1);
- if(ret == 0){
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1);
+
+ if (ret == 0)
+ {
ctrl_reg9.drdy_mask_bit = (uint8_t)val;
- ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t*)&ctrl_reg9, 1);
+ ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1);
}
+
return ret;
}
@@ -2036,12 +2444,13 @@ int32_t lsm9ds1_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm9ds1_filter_settling_mask_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm9ds1_ctrl_reg9_t ctrl_reg9;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t*)&ctrl_reg9, 1);
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1);
*val = (uint8_t)ctrl_reg9.drdy_mask_bit;
return ret;
@@ -2074,11 +2483,14 @@ int32_t lsm9ds1_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
lsm9ds1_ctrl_reg8_t ctrl_reg8;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG8, (uint8_t*)&ctrl_reg8, 1);
- if(ret == 0){
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG8, (uint8_t *)&ctrl_reg8, 1);
+
+ if (ret == 0)
+ {
ctrl_reg8.if_add_inc = (uint8_t)val;
- ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG8, (uint8_t*)&ctrl_reg8, 1);
+ ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG8, (uint8_t *)&ctrl_reg8, 1);
}
+
return ret;
}
@@ -2096,8 +2508,9 @@ int32_t lsm9ds1_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm9ds1_ctrl_reg8_t ctrl_reg8;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG8, (uint8_t*)&ctrl_reg8, 1);
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG8, (uint8_t *)&ctrl_reg8, 1);
*val = (uint8_t)ctrl_reg8.if_add_inc;
+
return ret;
}
@@ -2110,27 +2523,37 @@ int32_t lsm9ds1_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_spi_mode_set(stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu,
+int32_t lsm9ds1_spi_mode_set(stmdev_ctx_t *ctx_mag,
+ stmdev_ctx_t *ctx_imu,
lsm9ds1_sim_t val)
{
lsm9ds1_ctrl_reg3_m_t ctrl_reg3_m;
lsm9ds1_ctrl_reg8_t ctrl_reg8;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8, (uint8_t*)&ctrl_reg8, 1);
- if(ret == 0){
+ ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8,
+ (uint8_t *)&ctrl_reg8, 1);
+
+ if (ret == 0)
+ {
ctrl_reg8.sim = (uint8_t)val;
- ret = lsm9ds1_write_reg(ctx_imu, LSM9DS1_CTRL_REG8, (uint8_t*)&ctrl_reg8, 1);
+ ret = lsm9ds1_write_reg(ctx_imu, LSM9DS1_CTRL_REG8,
+ (uint8_t *)&ctrl_reg8, 1);
}
- if(ret == 0){
- ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG3_M,
- (uint8_t*)&ctrl_reg3_m, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG3_M,
+ (uint8_t *)&ctrl_reg3_m, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ctrl_reg3_m.sim = (uint8_t)val;
ret = lsm9ds1_write_reg(ctx_mag, LSM9DS1_CTRL_REG3_M,
- (uint8_t*)&ctrl_reg3_m, 1);
+ (uint8_t *)&ctrl_reg3_m, 1);
}
+
return ret;
}
@@ -2143,29 +2566,38 @@ int32_t lsm9ds1_spi_mode_set(stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_spi_mode_get(stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu,
+int32_t lsm9ds1_spi_mode_get(stmdev_ctx_t *ctx_mag,
+ stmdev_ctx_t *ctx_imu,
lsm9ds1_sim_t *val)
{
lsm9ds1_ctrl_reg3_m_t ctrl_reg3_m;
lsm9ds1_ctrl_reg8_t ctrl_reg8;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8, (uint8_t*)&ctrl_reg8, 1);
- if(ret == 0){
- ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG3_M,
- (uint8_t*)&ctrl_reg3_m, 1);
+ ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8,
+ (uint8_t *)&ctrl_reg8, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG3_M,
+ (uint8_t *)&ctrl_reg3_m, 1);
}
- switch (ctrl_reg8.sim & ctrl_reg3_m.sim){
+
+ switch (ctrl_reg8.sim & ctrl_reg3_m.sim)
+ {
case LSM9DS1_SPI_4_WIRE:
*val = LSM9DS1_SPI_4_WIRE;
break;
+
case LSM9DS1_SPI_3_WIRE:
*val = LSM9DS1_SPI_3_WIRE;
break;
+
default:
*val = LSM9DS1_SPI_4_WIRE;
break;
}
+
return ret;
}
@@ -2186,21 +2618,29 @@ int32_t lsm9ds1_i2c_interface_set(stmdev_ctx_t *ctx_mag,
lsm9ds1_ctrl_reg9_t ctrl_reg9;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG9, (uint8_t*)&ctrl_reg9, 1);
- if(ret == 0){
+ ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG9,
+ (uint8_t *)&ctrl_reg9, 1);
+
+ if (ret == 0)
+ {
ctrl_reg9.i2c_disable = (uint8_t)val;
ret = lsm9ds1_write_reg(ctx_imu, LSM9DS1_CTRL_REG9,
- (uint8_t*)&ctrl_reg9, 1);
+ (uint8_t *)&ctrl_reg9, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG3_M,
- (uint8_t*)&ctrl_reg3_m, 1);
+ (uint8_t *)&ctrl_reg3_m, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ctrl_reg3_m.i2c_disable = (uint8_t)val;
ret = lsm9ds1_write_reg(ctx_mag, LSM9DS1_CTRL_REG3_M,
- (uint8_t*)&ctrl_reg3_m, 1);
+ (uint8_t *)&ctrl_reg3_m, 1);
}
+
return ret;
}
@@ -2221,22 +2661,30 @@ int32_t lsm9ds1_i2c_interface_get(stmdev_ctx_t *ctx_mag,
lsm9ds1_ctrl_reg9_t ctrl_reg9;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG9, (uint8_t*)&ctrl_reg9, 1);
- if(ret == 0){
+ ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG9,
+ (uint8_t *)&ctrl_reg9, 1);
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG3_M,
- (uint8_t*)&ctrl_reg3_m, 1);
+ (uint8_t *)&ctrl_reg3_m, 1);
}
- switch (ctrl_reg9.i2c_disable & ctrl_reg3_m.i2c_disable){
+
+ switch (ctrl_reg9.i2c_disable & ctrl_reg3_m.i2c_disable)
+ {
case LSM9DS1_I2C_ENABLE:
*val = LSM9DS1_I2C_ENABLE;
break;
+
case LSM9DS1_I2C_DISABLE:
*val = LSM9DS1_I2C_DISABLE;
break;
+
default:
*val = LSM9DS1_I2C_ENABLE;
break;
}
+
return ret;
}
@@ -2261,27 +2709,34 @@ int32_t lsm9ds1_i2c_interface_get(stmdev_ctx_t *ctx_mag,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_pin_logic_set(stmdev_ctx_t *ctx, lsm9ds1_pin_logic_t val)
+int32_t lsm9ds1_pin_logic_set(stmdev_ctx_t *ctx,
+ lsm9ds1_pin_logic_t val)
{
lsm9ds1_int_gen_cfg_xl_t int_gen_cfg_xl;
lsm9ds1_int_gen_cfg_g_t int_gen_cfg_g;
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_CFG_XL,
- (uint8_t*)&int_gen_cfg_xl, 1);
- if(ret == 0){
+ (uint8_t *)&int_gen_cfg_xl, 1);
+
+ if (ret == 0)
+ {
int_gen_cfg_xl.aoi_xl = (uint8_t)val;
ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_CFG_XL,
- (uint8_t*)&int_gen_cfg_xl, 1);
+ (uint8_t *)&int_gen_cfg_xl, 1);
}
- if(ret == 0){
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_CFG_G,
- (uint8_t*)&int_gen_cfg_g, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_CFG_G,
+ (uint8_t *)&int_gen_cfg_g, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
int_gen_cfg_g.aoi_g = (uint8_t)val;
ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_CFG_G,
- (uint8_t*)&int_gen_cfg_g, 1);
+ (uint8_t *)&int_gen_cfg_g, 1);
}
return ret;
@@ -2295,29 +2750,37 @@ int32_t lsm9ds1_pin_logic_set(stmdev_ctx_t *ctx, lsm9ds1_pin_logic_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_pin_logic_get(stmdev_ctx_t *ctx, lsm9ds1_pin_logic_t *val)
+int32_t lsm9ds1_pin_logic_get(stmdev_ctx_t *ctx,
+ lsm9ds1_pin_logic_t *val)
{
lsm9ds1_int_gen_cfg_xl_t int_gen_cfg_xl;
lsm9ds1_int_gen_cfg_g_t int_gen_cfg_g;
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_CFG_XL,
- (uint8_t*)&int_gen_cfg_xl, 1);
- if(ret == 0){
+ (uint8_t *)&int_gen_cfg_xl, 1);
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_CFG_G,
- (uint8_t*)&int_gen_cfg_g, 1);
+ (uint8_t *)&int_gen_cfg_g, 1);
}
- switch (int_gen_cfg_xl.aoi_xl & int_gen_cfg_g.aoi_g){
+
+ switch (int_gen_cfg_xl.aoi_xl & int_gen_cfg_g.aoi_g)
+ {
case LSM9DS1_LOGIC_OR:
*val = LSM9DS1_LOGIC_OR;
break;
+
case LSM9DS1_LOGIC_AND:
*val = LSM9DS1_LOGIC_AND;
break;
+
default:
*val = LSM9DS1_LOGIC_OR;
break;
}
+
return ret;
}
@@ -2335,8 +2798,10 @@ int32_t lsm9ds1_pin_int1_route_set(stmdev_ctx_t *ctx,
lsm9ds1_int1_ctrl_t int1_ctrl;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
- if(ret == 0) {
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
+
+ if (ret == 0)
+ {
int1_ctrl.int1_drdy_xl = val.int1_drdy_xl;
int1_ctrl.int1_drdy_g = val.int1_drdy_g;
int1_ctrl.int1_boot = val.int1_boot;
@@ -2345,8 +2810,9 @@ int32_t lsm9ds1_pin_int1_route_set(stmdev_ctx_t *ctx,
int1_ctrl.int1_fss5 = val.int1_fss5;
int1_ctrl.int1_ig_xl = val.int1_ig_xl;
int1_ctrl.int1_ig_g = val.int1_ig_g;
- ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
+ ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
}
+
return ret;
}
@@ -2364,8 +2830,7 @@ int32_t lsm9ds1_pin_int1_route_get(stmdev_ctx_t *ctx,
lsm9ds1_int1_ctrl_t int1_ctrl;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT1_CTRL, (uint8_t*)&int1_ctrl, 1);
-
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
val->int1_drdy_xl = int1_ctrl.int1_drdy_xl;
val->int1_drdy_g = int1_ctrl.int1_drdy_g;
val->int1_boot = int1_ctrl.int1_boot;
@@ -2392,8 +2857,10 @@ int32_t lsm9ds1_pin_int2_route_set(stmdev_ctx_t *ctx,
lsm9ds1_int2_ctrl_t int2_ctrl;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
- if(ret == 0) {
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
+
+ if (ret == 0)
+ {
int2_ctrl.int2_drdy_xl = val.int2_drdy_xl;
int2_ctrl.int2_inact = val.int2_inact;
int2_ctrl.int2_drdy_g = val.int2_drdy_g;
@@ -2401,8 +2868,9 @@ int32_t lsm9ds1_pin_int2_route_set(stmdev_ctx_t *ctx,
int2_ctrl.int2_fth = val.int2_fth;
int2_ctrl.int2_ovr = val.int2_ovr;
int2_ctrl.int2_fss5 = val.int2_fss5;
- ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+ ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
}
+
return ret;
}
@@ -2420,7 +2888,7 @@ int32_t lsm9ds1_pin_int2_route_get(stmdev_ctx_t *ctx,
lsm9ds1_int2_ctrl_t int2_ctrl;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
val->int2_drdy_xl = int2_ctrl.int2_drdy_xl;
val->int2_inact = int2_ctrl.int2_inact;
val->int2_fss5 = int2_ctrl.int2_fss5;
@@ -2451,29 +2919,39 @@ int32_t lsm9ds1_pin_notification_set(stmdev_ctx_t *ctx_mag,
int32_t ret;
ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ctrl_reg4.lir_xl1 = (uint8_t)val;
ret = lsm9ds1_write_reg(ctx_imu, LSM9DS1_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_INT_GEN_CFG_G,
- (uint8_t*)&int_gen_cfg_g, 1);
+ (uint8_t *)&int_gen_cfg_g, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
int_gen_cfg_g.lir_g = (uint8_t)val;
ret = lsm9ds1_write_reg(ctx_imu, LSM9DS1_INT_GEN_CFG_G,
- (uint8_t*)&int_gen_cfg_g, 1);
+ (uint8_t *)&int_gen_cfg_g, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_INT_CFG_M,
- (uint8_t*)&int_cfg_m, 1);
+ (uint8_t *)&int_cfg_m, 1);
}
- if(ret == 0){
- int_cfg_m.iel = (uint8_t)val;
+
+ if (ret == 0)
+ {
+ int_cfg_m.iel = (uint8_t)(~val);
ret = lsm9ds1_write_reg(ctx_mag, LSM9DS1_INT_CFG_M,
- (uint8_t*)&int_cfg_m, 1);
+ (uint8_t *)&int_cfg_m, 1);
}
return ret;
@@ -2498,22 +2976,30 @@ int32_t lsm9ds1_pin_notification_get(stmdev_ctx_t *ctx_mag,
int32_t ret;
ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
- if(ret == 0){
+ (uint8_t *)&ctrl_reg4, 1);
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_INT_GEN_CFG_G,
- (uint8_t*)&int_gen_cfg_g, 1);
+ (uint8_t *)&int_gen_cfg_g, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_INT_CFG_M,
- (uint8_t*)&int_cfg_m, 1);
+ (uint8_t *)&int_cfg_m, 1);
}
- switch (int_cfg_m.iel & int_gen_cfg_g.lir_g & ctrl_reg4.lir_xl1){
+
+ switch (~int_cfg_m.iel & int_gen_cfg_g.lir_g & ctrl_reg4.lir_xl1)
+ {
case LSM9DS1_INT_LATCHED:
*val = LSM9DS1_INT_LATCHED;
break;
+
case LSM9DS1_INT_PULSED:
*val = LSM9DS1_INT_PULSED;
break;
+
default:
*val = LSM9DS1_INT_LATCHED;
break;
@@ -2534,11 +3020,14 @@ int32_t lsm9ds1_pin_mode_set(stmdev_ctx_t *ctx, lsm9ds1_pp_od_t val)
lsm9ds1_ctrl_reg8_t ctrl_reg8;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG8, (uint8_t*)&ctrl_reg8, 1);
- if(ret == 0){
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG8, (uint8_t *)&ctrl_reg8, 1);
+
+ if (ret == 0)
+ {
ctrl_reg8.pp_od = (uint8_t)val;
- ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG8, (uint8_t*)&ctrl_reg8, 1);
+ ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG8, (uint8_t *)&ctrl_reg8, 1);
}
+
return ret;
}
@@ -2555,18 +3044,23 @@ int32_t lsm9ds1_pin_mode_get(stmdev_ctx_t *ctx, lsm9ds1_pp_od_t *val)
lsm9ds1_ctrl_reg8_t ctrl_reg8;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG8, (uint8_t*)&ctrl_reg8, 1);
- switch (ctrl_reg8.pp_od){
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG8, (uint8_t *)&ctrl_reg8, 1);
+
+ switch (ctrl_reg8.pp_od)
+ {
case LSM9DS1_PUSH_PULL:
*val = LSM9DS1_PUSH_PULL;
break;
+
case LSM9DS1_OPEN_DRAIN:
*val = LSM9DS1_OPEN_DRAIN;
break;
+
default:
*val = LSM9DS1_PUSH_PULL;
break;
}
+
return ret;
}
@@ -2584,11 +3078,14 @@ int32_t lsm9ds1_pin_int_m_route_set(stmdev_ctx_t *ctx,
lsm9ds1_int_cfg_m_t int_cfg_m;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_CFG_M, (uint8_t*)&int_cfg_m, 1);
- if(ret == 0) {
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_CFG_M, (uint8_t *)&int_cfg_m, 1);
+
+ if (ret == 0)
+ {
int_cfg_m.ien = val.ien;
- ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_CFG_M, (uint8_t*)&int_cfg_m, 1);
+ ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_CFG_M, (uint8_t *)&int_cfg_m, 1);
}
+
return ret;
}
@@ -2606,7 +3103,7 @@ int32_t lsm9ds1_pin_int_m_route_get(stmdev_ctx_t *ctx,
lsm9ds1_int_cfg_m_t int_cfg_m;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_CFG_M, (uint8_t*)&int_cfg_m, 1);
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_CFG_M, (uint8_t *)&int_cfg_m, 1);
val->ien = int_cfg_m.ien;
return ret;
@@ -2630,20 +3127,26 @@ int32_t lsm9ds1_pin_polarity_set(stmdev_ctx_t *ctx_mag,
int32_t ret;
ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_INT_CFG_M,
- (uint8_t*)&int_cfg_m, 1);
- if(ret == 0){
+ (uint8_t *)&int_cfg_m, 1);
+
+ if (ret == 0)
+ {
int_cfg_m.iea = (uint8_t)val;
ret = lsm9ds1_write_reg(ctx_mag, LSM9DS1_INT_CFG_M,
- (uint8_t*)&int_cfg_m, 1);
+ (uint8_t *)&int_cfg_m, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8,
- (uint8_t*)&ctrl_reg8, 1);
+ (uint8_t *)&ctrl_reg8, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ctrl_reg8.h_lactive = (uint8_t)(~val);
ret = lsm9ds1_write_reg(ctx_imu, LSM9DS1_CTRL_REG8,
- (uint8_t*)&ctrl_reg8, 1);
+ (uint8_t *)&ctrl_reg8, 1);
}
return ret;
@@ -2666,22 +3169,30 @@ int32_t lsm9ds1_pin_polarity_get(stmdev_ctx_t *ctx_mag,
lsm9ds1_ctrl_reg8_t ctrl_reg8;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_INT_CFG_M, (uint8_t*)&int_cfg_m, 1);
- if(ret == 0){
+ ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_INT_CFG_M,
+ (uint8_t *)&int_cfg_m, 1);
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8,
- (uint8_t*)&ctrl_reg8, 1);
+ (uint8_t *)&ctrl_reg8, 1);
}
- switch (int_cfg_m.iea & (~ctrl_reg8.h_lactive)){
+
+ switch (int_cfg_m.iea & (~ctrl_reg8.h_lactive))
+ {
case LSM9DS1_ACTIVE_LOW:
*val = LSM9DS1_ACTIVE_LOW;
break;
+
case LSM9DS1_ACTIVE_HIGH:
*val = LSM9DS1_ACTIVE_HIGH;
break;
+
default:
*val = LSM9DS1_ACTIVE_LOW;
break;
}
+
return ret;
}
@@ -2714,15 +3225,18 @@ int32_t lsm9ds1_xl_trshld_axis_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_CFG_XL,
- (uint8_t*)&int_gen_cfg_xl, 1);
- if(ret == 0) {
+ (uint8_t *)&int_gen_cfg_xl, 1);
+
+ if (ret == 0)
+ {
int_gen_cfg_xl.xlie_xl = val.xlie_xl;
int_gen_cfg_xl.xhie_xl = val.xhie_xl;
int_gen_cfg_xl.ylie_xl = val.ylie_xl;
int_gen_cfg_xl.zhie_xl = val.zhie_xl;
int_gen_cfg_xl.yhie_xl = val.yhie_xl;
int_gen_cfg_xl.zlie_xl = val.zlie_xl;
- ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_CFG_XL, (uint8_t*)&int_gen_cfg_xl, 1);
+ ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_CFG_XL,
+ (uint8_t *)&int_gen_cfg_xl, 1);
}
return ret;
@@ -2744,7 +3258,7 @@ int32_t lsm9ds1_xl_trshld_axis_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_CFG_XL,
- (uint8_t*)&int_gen_cfg_xl, 1);
+ (uint8_t *)&int_gen_cfg_xl, 1);
val->xlie_xl = int_gen_cfg_xl.xlie_xl;
val->xhie_xl = int_gen_cfg_xl.xhie_xl;
val->ylie_xl = int_gen_cfg_xl.ylie_xl;
@@ -2766,7 +3280,9 @@ int32_t lsm9ds1_xl_trshld_axis_get(stmdev_ctx_t *ctx,
int32_t lsm9ds1_xl_trshld_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_THS_X_XL, buff, 3);
+
return ret;
}
@@ -2781,7 +3297,9 @@ int32_t lsm9ds1_xl_trshld_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lsm9ds1_xl_trshld_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_X_XL, buff, 3);
+
return ret;
}
@@ -2793,22 +3311,31 @@ int32_t lsm9ds1_xl_trshld_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_xl_trshld_min_sample_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm9ds1_xl_trshld_min_sample_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm9ds1_int_gen_dur_xl_t int_gen_dur_xl;
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_DUR_XL,
- (uint8_t*)&int_gen_dur_xl, 1);
- if(ret == 0){
+ (uint8_t *)&int_gen_dur_xl, 1);
+
+ if (ret == 0)
+ {
int_gen_dur_xl.dur_xl = (uint8_t)val;
- if (val != 0x00U){
+
+ if (val != 0x00U)
+ {
int_gen_dur_xl.wait_xl = PROPERTY_ENABLE;
- } else {
+ }
+
+ else
+ {
int_gen_dur_xl.wait_xl = PROPERTY_DISABLE;
}
+
ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_DUR_XL,
- (uint8_t*)&int_gen_dur_xl, 1);
+ (uint8_t *)&int_gen_dur_xl, 1);
}
return ret;
@@ -2822,13 +3349,14 @@ int32_t lsm9ds1_xl_trshld_min_sample_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_xl_trshld_min_sample_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm9ds1_xl_trshld_min_sample_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm9ds1_int_gen_dur_xl_t int_gen_dur_xl;
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_DUR_XL,
- (uint8_t*)&int_gen_dur_xl, 1);
+ (uint8_t *)&int_gen_dur_xl, 1);
*val = (uint8_t)int_gen_dur_xl.dur_xl;
return ret;
@@ -2849,7 +3377,7 @@ int32_t lsm9ds1_gy_trshld_src_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_SRC_G,
- (uint8_t*)&int_gen_src_g, 1);
+ (uint8_t *)&int_gen_src_g, 1);
val->xl_g = int_gen_src_g.xl_g;
val->xh_g = int_gen_src_g.xh_g;
val->yl_g = int_gen_src_g.yl_g;
@@ -2876,7 +3404,7 @@ int32_t lsm9ds1_xl_trshld_src_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_SRC_XL,
- (uint8_t*)&int_gen_src_xl, 1);
+ (uint8_t *)&int_gen_src_xl, 1);
val->xl_xl = int_gen_src_xl.xl_xl;
val->xh_xl = int_gen_src_xl.xh_xl;
val->yl_xl = int_gen_src_xl.yl_xl;
@@ -2904,8 +3432,10 @@ int32_t lsm9ds1_gy_trshld_axis_set(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_CFG_G,
- (uint8_t*)&int_gen_cfg_g, 1);
- if(ret == 0) {
+ (uint8_t *)&int_gen_cfg_g, 1);
+
+ if (ret == 0)
+ {
int_gen_cfg_g.xlie_g = val.xlie_g;
int_gen_cfg_g.xhie_g = val.xhie_g;
int_gen_cfg_g.ylie_g = val.ylie_g;
@@ -2913,8 +3443,9 @@ int32_t lsm9ds1_gy_trshld_axis_set(stmdev_ctx_t *ctx,
int_gen_cfg_g.zlie_g = val.zlie_g;
int_gen_cfg_g.zhie_g = val.zhie_g;
ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_CFG_G,
- (uint8_t*)&int_gen_cfg_g, 1);
+ (uint8_t *)&int_gen_cfg_g, 1);
}
+
return ret;
}
@@ -2934,13 +3465,14 @@ int32_t lsm9ds1_gy_trshld_axis_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_CFG_G,
- (uint8_t*)&int_gen_cfg_g, 1);
+ (uint8_t *)&int_gen_cfg_g, 1);
val->xlie_g = int_gen_cfg_g.xlie_g;
val->xhie_g = int_gen_cfg_g.xhie_g;
val->ylie_g = int_gen_cfg_g.ylie_g;
val->yhie_g = int_gen_cfg_g.yhie_g;
val->zlie_g = int_gen_cfg_g.zlie_g;
val->zhie_g = int_gen_cfg_g.zhie_g;
+
return ret;
}
@@ -2952,18 +3484,22 @@ int32_t lsm9ds1_gy_trshld_axis_get(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_gy_trshld_mode_set(stmdev_ctx_t *ctx, lsm9ds1_dcrm_g_t val)
+int32_t lsm9ds1_gy_trshld_mode_set(stmdev_ctx_t *ctx,
+ lsm9ds1_dcrm_g_t val)
{
lsm9ds1_int_gen_ths_xh_g_t int_gen_ths_xh_g;
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_XH_G,
- (uint8_t*)&int_gen_ths_xh_g, 1);
- if(ret == 0){
+ (uint8_t *)&int_gen_ths_xh_g, 1);
+
+ if (ret == 0)
+ {
int_gen_ths_xh_g.dcrm_g = (uint8_t)val;
ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_THS_XH_G,
- (uint8_t*)&int_gen_ths_xh_g, 1);
+ (uint8_t *)&int_gen_ths_xh_g, 1);
}
+
return ret;
}
@@ -2975,24 +3511,30 @@ int32_t lsm9ds1_gy_trshld_mode_set(stmdev_ctx_t *ctx, lsm9ds1_dcrm_g_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_gy_trshld_mode_get(stmdev_ctx_t *ctx, lsm9ds1_dcrm_g_t *val)
+int32_t lsm9ds1_gy_trshld_mode_get(stmdev_ctx_t *ctx,
+ lsm9ds1_dcrm_g_t *val)
{
lsm9ds1_int_gen_ths_xh_g_t int_gen_ths_xh_g;
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_XH_G,
- (uint8_t*)&int_gen_ths_xh_g, 1);
- switch (int_gen_ths_xh_g.dcrm_g){
+ (uint8_t *)&int_gen_ths_xh_g, 1);
+
+ switch (int_gen_ths_xh_g.dcrm_g)
+ {
case LSM9DS1_RESET_MODE:
*val = LSM9DS1_RESET_MODE;
break;
+
case LSM9DS1_DECREMENT_MODE:
*val = LSM9DS1_DECREMENT_MODE;
break;
+
default:
*val = LSM9DS1_RESET_MODE;
break;
}
+
return ret;
}
@@ -3011,20 +3553,26 @@ int32_t lsm9ds1_gy_trshld_x_set(stmdev_ctx_t *ctx, uint16_t val)
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_XH_G,
- (uint8_t*)&int_gen_ths_xh_g, 1);
- if(ret == 0){
+ (uint8_t *)&int_gen_ths_xh_g, 1);
+
+ if (ret == 0)
+ {
int_gen_ths_xh_g.ths_g_x = (uint8_t)((val & 0x7F00U) >> 8);
ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_THS_XH_G,
- (uint8_t*)&int_gen_ths_xh_g, 1);
+ (uint8_t *)&int_gen_ths_xh_g, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_XL_G,
- (uint8_t*)&int_gen_ths_xl_g, 1);
+ (uint8_t *)&int_gen_ths_xl_g, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
int_gen_ths_xl_g.ths_g_x = (uint8_t)(val & 0x00FFU);
ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_THS_XL_G,
- (uint8_t*)&int_gen_ths_xl_g, 1);
+ (uint8_t *)&int_gen_ths_xl_g, 1);
}
return ret;
@@ -3045,14 +3593,18 @@ int32_t lsm9ds1_gy_trshld_x_get(stmdev_ctx_t *ctx, uint16_t *val)
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_XH_G,
- (uint8_t*)&int_gen_ths_xh_g, 1);
- if(ret == 0){
+ (uint8_t *)&int_gen_ths_xh_g, 1);
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_XL_G,
- (uint8_t*)&int_gen_ths_xl_g, 1);
+ (uint8_t *)&int_gen_ths_xl_g, 1);
}
+
*val = int_gen_ths_xh_g.ths_g_x;
*val = *val << 8;
*val += int_gen_ths_xl_g.ths_g_x;
+
return ret;
}
@@ -3072,20 +3624,26 @@ int32_t lsm9ds1_gy_trshld_y_set(stmdev_ctx_t *ctx, uint16_t val)
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_YH_G,
- (uint8_t*)&int_gen_ths_yh_g, 1);
- if(ret == 0){
+ (uint8_t *)&int_gen_ths_yh_g, 1);
+
+ if (ret == 0)
+ {
int_gen_ths_yh_g.ths_g_y = (uint8_t)((val & 0x7F00U) >> 8);
ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_THS_YH_G,
- (uint8_t*)&int_gen_ths_yh_g, 1);
+ (uint8_t *)&int_gen_ths_yh_g, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_YL_G,
- (uint8_t*)&int_gen_ths_yl_g, 1);
+ (uint8_t *)&int_gen_ths_yl_g, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
int_gen_ths_yl_g.ths_g_y = (uint8_t)(val & 0x00FFU);
ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_THS_YL_G,
- (uint8_t*)&int_gen_ths_yl_g, 1);
+ (uint8_t *)&int_gen_ths_yl_g, 1);
}
return ret;
@@ -3106,14 +3664,18 @@ int32_t lsm9ds1_gy_trshld_y_get(stmdev_ctx_t *ctx, uint16_t *val)
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_YH_G,
- (uint8_t*)&int_gen_ths_yh_g, 1);
- if(ret == 0){
+ (uint8_t *)&int_gen_ths_yh_g, 1);
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_YL_G,
- (uint8_t*)&int_gen_ths_yl_g, 1);
+ (uint8_t *)&int_gen_ths_yl_g, 1);
}
+
*val = (uint8_t)int_gen_ths_yh_g.ths_g_y;
*val = *val << 8;
*val += int_gen_ths_yl_g.ths_g_y;
+
return ret;
}
@@ -3132,20 +3694,26 @@ int32_t lsm9ds1_gy_trshld_z_set(stmdev_ctx_t *ctx, uint16_t val)
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_ZH_G,
- (uint8_t*)&int_gen_ths_zh_g, 1);
- if(ret == 0){
+ (uint8_t *)&int_gen_ths_zh_g, 1);
+
+ if (ret == 0)
+ {
int_gen_ths_zh_g.ths_g_z = (uint8_t)((val & 0x7F00U) >> 8);
ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_THS_ZH_G,
- (uint8_t*)&int_gen_ths_zh_g, 1);
+ (uint8_t *)&int_gen_ths_zh_g, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_ZL_G,
- (uint8_t*)&int_gen_ths_zl_g, 1);
+ (uint8_t *)&int_gen_ths_zl_g, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
int_gen_ths_zl_g.ths_g_z = (uint8_t)(val & 0x00FFU);
ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_THS_ZL_G,
- (uint8_t*)&int_gen_ths_zl_g, 1);
+ (uint8_t *)&int_gen_ths_zl_g, 1);
}
return ret;
@@ -3166,11 +3734,14 @@ int32_t lsm9ds1_gy_trshld_z_get(stmdev_ctx_t *ctx, uint16_t *val)
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_ZH_G,
- (uint8_t*)&int_gen_ths_zh_g, 1);
- if(ret == 0){
+ (uint8_t *)&int_gen_ths_zh_g, 1);
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_ZL_G,
- (uint8_t*)&int_gen_ths_zl_g, 1);
+ (uint8_t *)&int_gen_ths_zl_g, 1);
}
+
*val = int_gen_ths_zh_g.ths_g_z;
*val = *val << 8;
*val += int_gen_ths_zl_g.ths_g_z;
@@ -3186,22 +3757,30 @@ int32_t lsm9ds1_gy_trshld_z_get(stmdev_ctx_t *ctx, uint16_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_gy_trshld_min_sample_set(stmdev_ctx_t *ctx, uint8_t val)
+int32_t lsm9ds1_gy_trshld_min_sample_set(stmdev_ctx_t *ctx,
+ uint8_t val)
{
lsm9ds1_int_gen_dur_g_t int_gen_dur_g;
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_DUR_G,
- (uint8_t*)&int_gen_dur_g, 1);
- if(ret == 0){
- if (val != 0x00U){
+ (uint8_t *)&int_gen_dur_g, 1);
+
+ if (ret == 0)
+ {
+ if (val != 0x00U)
+ {
int_gen_dur_g.wait_g = PROPERTY_ENABLE;
- } else {
+ }
+
+ else
+ {
int_gen_dur_g.wait_g = PROPERTY_DISABLE;
}
+
int_gen_dur_g.dur_g = (uint8_t)val;
ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_DUR_G,
- (uint8_t*)&int_gen_dur_g, 1);
+ (uint8_t *)&int_gen_dur_g, 1);
}
return ret;
@@ -3215,13 +3794,14 @@ int32_t lsm9ds1_gy_trshld_min_sample_set(stmdev_ctx_t *ctx, uint8_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_gy_trshld_min_sample_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t lsm9ds1_gy_trshld_min_sample_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
lsm9ds1_int_gen_dur_g_t int_gen_dur_g;
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_DUR_G,
- (uint8_t*)&int_gen_dur_g, 1);
+ (uint8_t *)&int_gen_dur_g, 1);
*val = (uint8_t)int_gen_dur_g.dur_g;
return ret;
@@ -3241,12 +3821,14 @@ int32_t lsm9ds1_mag_trshld_axis_set(stmdev_ctx_t *ctx,
lsm9ds1_int_cfg_m_t int_cfg_m;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_CFG_M, (uint8_t*)&int_cfg_m, 1);
- if(ret == 0) {
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_CFG_M, (uint8_t *)&int_cfg_m, 1);
+
+ if (ret == 0)
+ {
int_cfg_m.zien = val.zien;
int_cfg_m.xien = val.xien;
int_cfg_m.yien = val.yien;
- ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_CFG_M, (uint8_t*)&int_cfg_m, 1);
+ ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_CFG_M, (uint8_t *)&int_cfg_m, 1);
}
return ret;
@@ -3266,7 +3848,7 @@ int32_t lsm9ds1_mag_trshld_axis_get(stmdev_ctx_t *ctx,
lsm9ds1_int_cfg_m_t int_cfg_m;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_CFG_M, (uint8_t*)&int_cfg_m, 1);
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_CFG_M, (uint8_t *)&int_cfg_m, 1);
val->zien = int_cfg_m.zien;
val->yien = int_cfg_m.yien;
val->xien = int_cfg_m.xien;
@@ -3288,7 +3870,7 @@ int32_t lsm9ds1_mag_trshld_src_get(stmdev_ctx_t *ctx,
lsm9ds1_int_src_m_t int_src_m;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_SRC_M, (uint8_t*)&int_src_m, 1);
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_SRC_M, (uint8_t *)&int_src_m, 1);
val->_int = int_src_m._int;
val->nth_z = int_src_m.nth_z;
val->nth_y = int_src_m.nth_y;
@@ -3315,10 +3897,12 @@ int32_t lsm9ds1_mag_trshld_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_THS_L_M,
- (uint8_t*)&int_ths_l_m, 1);
- if(ret == 0){
+ (uint8_t *)&int_ths_l_m, 1);
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_THS_H_M,
- (uint8_t*)&int_ths_h_m, 1);
+ (uint8_t *)&int_ths_h_m, 1);
}
*val = int_ths_h_m.ths;
@@ -3354,11 +3938,14 @@ int32_t lsm9ds1_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
lsm9ds1_act_ths_t act_ths;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_ACT_THS, (uint8_t*)&act_ths, 1);
- if(ret == 0){
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_ACT_THS, (uint8_t *)&act_ths, 1);
+
+ if (ret == 0)
+ {
act_ths.act_ths = (uint8_t)val;
- ret = lsm9ds1_write_reg(ctx, LSM9DS1_ACT_THS, (uint8_t*)&act_ths, 1);
+ ret = lsm9ds1_write_reg(ctx, LSM9DS1_ACT_THS, (uint8_t *)&act_ths, 1);
}
+
return ret;
}
@@ -3375,7 +3962,7 @@ int32_t lsm9ds1_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm9ds1_act_ths_t act_ths;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_ACT_THS, (uint8_t*)&act_ths, 1);
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_ACT_THS, (uint8_t *)&act_ths, 1);
*val = (uint8_t)act_ths.act_ths;
return ret;
@@ -3389,23 +3976,30 @@ int32_t lsm9ds1_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_act_mode_set(stmdev_ctx_t *ctx, lsm9ds1_act_mode_t val)
+int32_t lsm9ds1_act_mode_set(stmdev_ctx_t *ctx,
+ lsm9ds1_act_mode_t val)
{
lsm9ds1_act_ths_t act_ths;
lsm9ds1_ctrl_reg9_t ctrl_reg9;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_ACT_THS, (uint8_t*)&act_ths, 1);
- if(ret == 0){
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_ACT_THS, (uint8_t *)&act_ths, 1);
+
+ if (ret == 0)
+ {
act_ths.sleep_on_inact_en = (uint8_t)val;
- ret = lsm9ds1_write_reg(ctx, LSM9DS1_ACT_THS, (uint8_t*)&act_ths, 1);
+ ret = lsm9ds1_write_reg(ctx, LSM9DS1_ACT_THS, (uint8_t *)&act_ths, 1);
}
- if(ret == 0){
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t*)&ctrl_reg9, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ctrl_reg9.sleep_g = (uint8_t)val;
- ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t*)&ctrl_reg9, 1);
+ ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1);
}
return ret;
@@ -3419,23 +4013,30 @@ int32_t lsm9ds1_act_mode_set(stmdev_ctx_t *ctx, lsm9ds1_act_mode_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_act_mode_get(stmdev_ctx_t *ctx, lsm9ds1_act_mode_t *val)
+int32_t lsm9ds1_act_mode_get(stmdev_ctx_t *ctx,
+ lsm9ds1_act_mode_t *val)
{
lsm9ds1_act_ths_t act_ths;
lsm9ds1_ctrl_reg9_t ctrl_reg9;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_ACT_THS, (uint8_t*)&act_ths, 1);
- if(ret == 0){
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t*)&ctrl_reg9, 1);
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_ACT_THS, (uint8_t *)&act_ths, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1);
}
- switch (act_ths.sleep_on_inact_en & ctrl_reg9.sleep_g){
+
+ switch (act_ths.sleep_on_inact_en & ctrl_reg9.sleep_g)
+ {
case LSM9DS1_GYRO_POWER_DOWN:
*val = LSM9DS1_GYRO_POWER_DOWN;
break;
+
case LSM9DS1_GYRO_SLEEP:
*val = LSM9DS1_GYRO_SLEEP;
break;
+
default:
*val = LSM9DS1_GYRO_POWER_DOWN;
break;
@@ -3455,7 +4056,9 @@ int32_t lsm9ds1_act_mode_get(stmdev_ctx_t *ctx, lsm9ds1_act_mode_t *val)
int32_t lsm9ds1_act_duration_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm9ds1_write_reg(ctx, LSM9DS1_ACT_DUR, buff, 1);
+
return ret;
}
@@ -3470,7 +4073,9 @@ int32_t lsm9ds1_act_duration_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lsm9ds1_act_duration_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm9ds1_read_reg(ctx, LSM9DS1_ACT_DUR, buff, 1);
+
return ret;
}
@@ -3487,18 +4092,24 @@ int32_t lsm9ds1_act_src_get(stmdev_ctx_t *ctx, lsm9ds1_inact_t *val)
lsm9ds1_status_reg_t status_reg;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_STATUS_REG, (uint8_t*)&status_reg, 1);
- switch (status_reg.inact){
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_STATUS_REG,
+ (uint8_t *)&status_reg, 1);
+
+ switch (status_reg.inact)
+ {
case LSM9DS1_ACTIVITY:
*val = LSM9DS1_ACTIVITY;
break;
+
case LSM9DS1_INACTIVITY:
*val = LSM9DS1_INACTIVITY;
break;
+
default:
*val = LSM9DS1_ACTIVITY;
break;
}
+
return ret;
}
@@ -3530,22 +4141,29 @@ int32_t lsm9ds1_6d_mode_set(stmdev_ctx_t *ctx, lsm9ds1_6d_mode_t val)
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_CFG_XL,
- (uint8_t*)&int_gen_cfg_xl, 1);
- if(ret == 0){
+ (uint8_t *)&int_gen_cfg_xl, 1);
+
+ if (ret == 0)
+ {
int_gen_cfg_xl._6d = ((uint8_t)val & 0x01U);
- int_gen_cfg_xl.aoi_xl = ( ( (uint8_t)val & 0x02U ) >> 1 );
+ int_gen_cfg_xl.aoi_xl = (((uint8_t)val & 0x02U) >> 1);
ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_CFG_XL,
- (uint8_t*)&int_gen_cfg_xl, 1);
+ (uint8_t *)&int_gen_cfg_xl, 1);
}
- if(ret == 0){
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
}
- if(ret == 0){
- ctrl_reg4._4d_xl1 = ( ( (uint8_t)val & 0x04U ) >> 2 );
+
+ if (ret == 0)
+ {
+ ctrl_reg4._4d_xl1 = (((uint8_t)val & 0x04U) >> 2);
ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
}
+
return ret;
}
@@ -3564,32 +4182,42 @@ int32_t lsm9ds1_6d_mode_get(stmdev_ctx_t *ctx, lsm9ds1_6d_mode_t *val)
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_CFG_XL,
- (uint8_t*)&int_gen_cfg_xl, 1);
- if(ret == 0){
+ (uint8_t *)&int_gen_cfg_xl, 1);
+
+ if (ret == 0)
+ {
ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG4,
- (uint8_t*)&ctrl_reg4, 1);
+ (uint8_t *)&ctrl_reg4, 1);
}
- switch ( (ctrl_reg4._4d_xl1 << 2) | (int_gen_cfg_xl.aoi_xl << 1)
- | int_gen_cfg_xl.aoi_xl ){
+
+ switch ((ctrl_reg4._4d_xl1 << 2) | (int_gen_cfg_xl.aoi_xl << 1)
+ | int_gen_cfg_xl.aoi_xl)
+ {
case LSM9DS1_POS_MOVE_RECO_DISABLE:
*val = LSM9DS1_POS_MOVE_RECO_DISABLE;
break;
+
case LSM9DS1_6D_MOVE_RECO:
*val = LSM9DS1_6D_MOVE_RECO;
break;
+
case LSM9DS1_4D_MOVE_RECO:
*val = LSM9DS1_4D_MOVE_RECO;
break;
+
case LSM9DS1_6D_POS_RECO:
*val = LSM9DS1_6D_POS_RECO;
break;
+
case LSM9DS1_4D_POS_RECO:
*val = LSM9DS1_4D_POS_RECO;
break;
+
default:
*val = LSM9DS1_POS_MOVE_RECO_DISABLE;
break;
}
+
return ret;
}
@@ -3604,7 +4232,9 @@ int32_t lsm9ds1_6d_mode_get(stmdev_ctx_t *ctx, lsm9ds1_6d_mode_t *val)
int32_t lsm9ds1_6d_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_THS_X_XL, buff, 3);
+
return ret;
}
@@ -3619,7 +4249,9 @@ int32_t lsm9ds1_6d_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff)
int32_t lsm9ds1_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_X_XL, buff, 3);
+
return ret;
}
@@ -3637,7 +4269,7 @@ int32_t lsm9ds1_6d_src_get(stmdev_ctx_t *ctx, lsm9ds1_6d_src_t *val)
int32_t ret;
ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_SRC_XL,
- (uint8_t*)&int_gen_src_xl, 1);
+ (uint8_t *)&int_gen_src_xl, 1);
val->xl_xl = int_gen_src_xl.xl_xl;
val->xh_xl = int_gen_src_xl.xh_xl;
val->yl_xl = int_gen_src_xl.yl_xl;
@@ -3676,11 +4308,14 @@ int32_t lsm9ds1_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
lsm9ds1_ctrl_reg9_t ctrl_reg9;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t*)&ctrl_reg9, 1);
- if(ret == 0){
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1);
+
+ if (ret == 0)
+ {
ctrl_reg9.stop_on_fth = (uint8_t)val;
- ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t*)&ctrl_reg9, 1);
+ ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1);
}
+
return ret;
}
@@ -3698,7 +4333,7 @@ int32_t lsm9ds1_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm9ds1_ctrl_reg9_t ctrl_reg9;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t*)&ctrl_reg9, 1);
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1);
*val = (uint8_t)ctrl_reg9.stop_on_fth;
return ret;
@@ -3712,24 +4347,32 @@ int32_t lsm9ds1_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_fifo_mode_set(stmdev_ctx_t *ctx, lsm9ds1_fifo_md_t val)
+int32_t lsm9ds1_fifo_mode_set(stmdev_ctx_t *ctx,
+ lsm9ds1_fifo_md_t val)
{
lsm9ds1_ctrl_reg9_t ctrl_reg9;
lsm9ds1_fifo_ctrl_t fifo_ctrl;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t*)&ctrl_reg9, 1);
- if(ret == 0){
- ctrl_reg9.fifo_en = ( ( (uint8_t)val & 0x10U ) >> 4);
- ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t*)&ctrl_reg9, 1);
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1);
+
+ if (ret == 0)
+ {
+ ctrl_reg9.fifo_en = (((uint8_t)val & 0x10U) >> 4);
+ ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1);
}
- if(ret == 0){
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
}
- if(ret == 0){
- fifo_ctrl.fmode = ( (uint8_t)val & 0x0FU );
- ret = lsm9ds1_write_reg(ctx, LSM9DS1_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
+
+ if (ret == 0)
+ {
+ fifo_ctrl.fmode = ((uint8_t)val & 0x0FU);
+ ret = lsm9ds1_write_reg(ctx, LSM9DS1_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
}
+
return ret;
}
@@ -3741,35 +4384,46 @@ int32_t lsm9ds1_fifo_mode_set(stmdev_ctx_t *ctx, lsm9ds1_fifo_md_t val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t lsm9ds1_fifo_mode_get(stmdev_ctx_t *ctx, lsm9ds1_fifo_md_t *val)
+int32_t lsm9ds1_fifo_mode_get(stmdev_ctx_t *ctx,
+ lsm9ds1_fifo_md_t *val)
{
lsm9ds1_ctrl_reg9_t ctrl_reg9;
lsm9ds1_fifo_ctrl_t fifo_ctrl;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t*)&ctrl_reg9, 1);
- if(ret == 0){
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1);
+
+ if (ret == 0)
+ {
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
}
- switch ((ctrl_reg9.fifo_en << 4) | ctrl_reg9.fifo_en){
+
+ switch ((ctrl_reg9.fifo_en << 4) | ctrl_reg9.fifo_en)
+ {
case LSM9DS1_FIFO_OFF:
*val = LSM9DS1_FIFO_OFF;
break;
+
case LSM9DS1_BYPASS_MODE:
*val = LSM9DS1_BYPASS_MODE;
break;
+
case LSM9DS1_FIFO_MODE:
*val = LSM9DS1_FIFO_MODE;
break;
+
case LSM9DS1_STREAM_TO_FIFO_MODE:
*val = LSM9DS1_STREAM_TO_FIFO_MODE;
break;
+
case LSM9DS1_BYPASS_TO_STREAM_MODE:
*val = LSM9DS1_BYPASS_TO_STREAM_MODE;
break;
+
case LSM9DS1_STREAM_MODE:
*val = LSM9DS1_STREAM_MODE;
break;
+
default:
*val = LSM9DS1_FIFO_OFF;
break;
@@ -3791,11 +4445,14 @@ int32_t lsm9ds1_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val)
lsm9ds1_ctrl_reg9_t ctrl_reg9;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t*)&ctrl_reg9, 1);
- if(ret == 0){
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1);
+
+ if (ret == 0)
+ {
ctrl_reg9.fifo_temp_en = (uint8_t)val;
- ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t*)&ctrl_reg9, 1);
+ ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1);
}
+
return ret;
}
@@ -3812,7 +4469,7 @@ int32_t lsm9ds1_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm9ds1_ctrl_reg9_t ctrl_reg9;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t*)&ctrl_reg9, 1);
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1);
*val = (uint8_t)ctrl_reg9.fifo_temp_en;
return ret;
@@ -3831,11 +4488,14 @@ int32_t lsm9ds1_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
lsm9ds1_fifo_ctrl_t fifo_ctrl;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
- if(ret == 0){
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
+
+ if (ret == 0)
+ {
fifo_ctrl.fth = (uint8_t)val;
- ret = lsm9ds1_write_reg(ctx, LSM9DS1_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
+ ret = lsm9ds1_write_reg(ctx, LSM9DS1_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
}
+
return ret;
}
@@ -3852,7 +4512,7 @@ int32_t lsm9ds1_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm9ds1_fifo_ctrl_t fifo_ctrl;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_FIFO_CTRL, (uint8_t*)&fifo_ctrl, 1);
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
*val = (uint8_t)fifo_ctrl.fth;
return ret;
@@ -3871,7 +4531,7 @@ int32_t lsm9ds1_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm9ds1_fifo_src_t fifo_src;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_FIFO_SRC, (uint8_t*)&fifo_src, 1);
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_FIFO_SRC, (uint8_t *)&fifo_src, 1);
*val = fifo_src.fss;
return ret;
@@ -3890,7 +4550,7 @@ int32_t lsm9ds1_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm9ds1_fifo_src_t fifo_src;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_FIFO_SRC, (uint8_t*)&fifo_src, 1);
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_FIFO_SRC, (uint8_t *)&fifo_src, 1);
*val = fifo_src.fss;
return ret;
@@ -3909,7 +4569,7 @@ int32_t lsm9ds1_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm9ds1_fifo_src_t fifo_src;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_FIFO_SRC, (uint8_t*)&fifo_src, 1);
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_FIFO_SRC, (uint8_t *)&fifo_src, 1);
*val = fifo_src.ovrn;
return ret;
@@ -3928,7 +4588,7 @@ int32_t lsm9ds1_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm9ds1_fifo_src_t fifo_src;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_FIFO_SRC, (uint8_t*)&fifo_src, 1);
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_FIFO_SRC, (uint8_t *)&fifo_src, 1);
*val = fifo_src.fth;
return ret;
@@ -3960,11 +4620,16 @@ int32_t lsm9ds1_xl_self_test_set(stmdev_ctx_t *ctx, uint8_t val)
lsm9ds1_ctrl_reg10_t ctrl_reg10;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG10, (uint8_t*)&ctrl_reg10, 1);
- if(ret == 0){
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG10,
+ (uint8_t *)&ctrl_reg10, 1);
+
+ if (ret == 0)
+ {
ctrl_reg10.st_xl = (uint8_t)val;
- ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG10, (uint8_t*)&ctrl_reg10, 1);
+ ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG10,
+ (uint8_t *)&ctrl_reg10, 1);
}
+
return ret;
}
@@ -3981,7 +4646,8 @@ int32_t lsm9ds1_xl_self_test_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm9ds1_ctrl_reg10_t ctrl_reg10;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG10, (uint8_t*)&ctrl_reg10, 1);
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG10,
+ (uint8_t *)&ctrl_reg10, 1);
*val = (uint8_t)ctrl_reg10.st_xl;
return ret;
@@ -4000,11 +4666,16 @@ int32_t lsm9ds1_gy_self_test_set(stmdev_ctx_t *ctx, uint8_t val)
lsm9ds1_ctrl_reg10_t ctrl_reg10;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG10, (uint8_t*)&ctrl_reg10, 1);
- if(ret == 0){
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG10,
+ (uint8_t *)&ctrl_reg10, 1);
+
+ if (ret == 0)
+ {
ctrl_reg10.st_g = (uint8_t)val;
- ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG10, (uint8_t*)&ctrl_reg10, 1);
+ ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG10,
+ (uint8_t *)&ctrl_reg10, 1);
}
+
return ret;
}
@@ -4021,7 +4692,8 @@ int32_t lsm9ds1_gy_self_test_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm9ds1_ctrl_reg10_t ctrl_reg10;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG10, (uint8_t*)&ctrl_reg10, 1);
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG10,
+ (uint8_t *)&ctrl_reg10, 1);
*val = (uint8_t)ctrl_reg10.st_g;
return ret;
@@ -4040,12 +4712,16 @@ int32_t lsm9ds1_mag_self_test_set(stmdev_ctx_t *ctx, uint8_t val)
lsm9ds1_ctrl_reg1_m_t ctrl_reg1_m;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_M, (uint8_t*)&ctrl_reg1_m, 1);
- if(ret == 0){
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_M,
+ (uint8_t *)&ctrl_reg1_m, 1);
+
+ if (ret == 0)
+ {
ctrl_reg1_m.st = (uint8_t)val;
ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG1_M,
- (uint8_t*)&ctrl_reg1_m, 1);
+ (uint8_t *)&ctrl_reg1_m, 1);
}
+
return ret;
}
@@ -4062,7 +4738,8 @@ int32_t lsm9ds1_mag_self_test_get(stmdev_ctx_t *ctx, uint8_t *val)
lsm9ds1_ctrl_reg1_m_t ctrl_reg1_m;
int32_t ret;
- ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_M, (uint8_t*)&ctrl_reg1_m, 1);
+ ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_M,
+ (uint8_t *)&ctrl_reg1_m, 1);
*val = (uint8_t)ctrl_reg1_m.st;
return ret;
diff --git a/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.h b/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.h
index c571cd3e0f70cdedd74cea229ba6b8e2db1a8d84..800fcaed318c9df5827964ae14cefa4475de5bf9 100644
--- a/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.h
+++ b/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file lsm9ds1_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * lsm9ds1_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file lsm9ds1_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * lsm9ds1_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LSM9DS1_REGS_H
#define LSM9DS1_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup LSM9DS1
@@ -35,6 +36,37 @@
*
*/
+/** @defgroup Endianness definitions
+ * @{
+ *
+ */
+
+#ifndef DRV_BYTE_ORDER
+#ifndef __BYTE_ORDER__
+
+#define DRV_LITTLE_ENDIAN 1234
+#define DRV_BIG_ENDIAN 4321
+
+/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
+ * by uncommenting the define which fits your platform endianness
+ */
+//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
+#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
+
+#else /* defined __BYTE_ORDER__ */
+
+#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
+#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
+#define DRV_BYTE_ORDER __BYTE_ORDER__
+
+#endif /* __BYTE_ORDER__*/
+#endif /* DRV_BYTE_ORDER */
+
+/**
+ * @}
+ *
+ */
+
/** @defgroup STMicroelectronics sensors common types
* @{
*
@@ -43,7 +75,9 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -52,6 +86,16 @@ typedef struct{
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} bitwise_t;
#define PROPERTY_DISABLE (0U)
@@ -65,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -97,7 +142,8 @@ typedef struct {
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -123,7 +169,7 @@ typedef struct {
#define LSM9DS1_IMU_I2C_ADD_L 0xD5U
#define LSM9DS1_IMU_I2C_ADD_H 0xD7U
-/** I2C Device Address 8 bit format if SA0=0 -> 0x39 if SA0=1 -> 0x3D **/
+/** I2C Device Address 8 bit format if SA0=0 -> 0x3D if SA0=1 -> 0x39 **/
#define LSM9DS1_MAG_I2C_ADD_L 0x39U
#define LSM9DS1_MAG_I2C_ADD_H 0x3DU
@@ -139,14 +185,22 @@ typedef struct {
*/
#define LSM9DS1_ACT_THS 0x04U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t act_ths : 7;
uint8_t sleep_on_inact_en : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t sleep_on_inact_en : 1;
+ uint8_t act_ths : 7;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_act_ths_t;
#define LSM9DS1_ACT_DUR 0x05U
#define LSM9DS1_INT_GEN_CFG_XL 0x06U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlie_xl : 1;
uint8_t xhie_xl : 1;
uint8_t ylie_xl : 1;
@@ -155,20 +209,38 @@ typedef struct {
uint8_t zhie_xl : 1;
uint8_t _6d : 1;
uint8_t aoi_xl : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t aoi_xl : 1;
+ uint8_t _6d : 1;
+ uint8_t zhie_xl : 1;
+ uint8_t zlie_xl : 1;
+ uint8_t yhie_xl : 1;
+ uint8_t ylie_xl : 1;
+ uint8_t xhie_xl : 1;
+ uint8_t xlie_xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_int_gen_cfg_xl_t;
#define LSM9DS1_INT_GEN_THS_X_XL 0x07U
#define LSM9DS1_INT_GEN_THS_Y_XL 0x08U
#define LSM9DS1_INT_GEN_THS_Z_XL 0x09U
#define LSM9DS1_INT_GEN_DUR_XL 0x0AU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t dur_xl : 7;
uint8_t wait_xl : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t wait_xl : 1;
+ uint8_t dur_xl : 7;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_int_gen_dur_xl_t;
#define LSM9DS1_REFERENCE_G 0x0BU
#define LSM9DS1_INT1_CTRL 0x0CU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_drdy_xl : 1;
uint8_t int1_drdy_g : 1;
uint8_t int1_boot : 1;
@@ -177,10 +249,22 @@ typedef struct {
uint8_t int1_fss5 : 1;
uint8_t int1_ig_xl : 1;
uint8_t int1_ig_g : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int1_ig_g : 1;
+ uint8_t int1_ig_xl : 1;
+ uint8_t int1_fss5 : 1;
+ uint8_t int1_ovr : 1;
+ uint8_t int1_fth : 1;
+ uint8_t int1_boot : 1;
+ uint8_t int1_drdy_g : 1;
+ uint8_t int1_drdy_xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_int1_ctrl_t;
#define LSM9DS1_INT2_CTRL 0x0DU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_drdy_xl : 1;
uint8_t int2_drdy_g : 1;
uint8_t int2_drdy_temp : 1;
@@ -189,43 +273,87 @@ typedef struct {
uint8_t int2_fss5 : 1;
uint8_t not_used_01 : 1;
uint8_t int2_inact : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t int2_inact : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t int2_fss5 : 1;
+ uint8_t int2_ovr : 1;
+ uint8_t int2_fth : 1;
+ uint8_t int2_drdy_temp : 1;
+ uint8_t int2_drdy_g : 1;
+ uint8_t int2_drdy_xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_int2_ctrl_t;
#define LSM9DS1_WHO_AM_I 0x0FU
#define LSM9DS1_CTRL_REG1_G 0x10U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bw_g : 2;
uint8_t not_used_01 : 1;
uint8_t fs_g : 2;
uint8_t odr_g : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr_g : 3;
+ uint8_t fs_g : 2;
+ uint8_t not_used_01 : 1;
+ uint8_t bw_g : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_ctrl_reg1_g_t;
#define LSM9DS1_CTRL_REG2_G 0x11U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t out_sel : 2;
uint8_t int_sel : 2;
uint8_t not_used_01 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 4;
+ uint8_t int_sel : 2;
+ uint8_t out_sel : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_ctrl_reg2_g_t;
#define LSM9DS1_CTRL_REG3_G 0x12U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t hpcf_g : 4;
uint8_t not_used_01 : 2;
uint8_t hp_en : 1;
uint8_t lp_mode : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t lp_mode : 1;
+ uint8_t hp_en : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t hpcf_g : 4;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_ctrl_reg3_g_t;
#define LSM9DS1_ORIENT_CFG_G 0x13U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t orient : 3;
uint8_t signz_g : 1;
uint8_t signy_g : 1;
uint8_t signx_g : 1;
uint8_t not_used_01 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 2;
+ uint8_t signx_g : 1;
+ uint8_t signy_g : 1;
+ uint8_t signz_g : 1;
+ uint8_t orient : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_orient_cfg_g_t;
#define LSM9DS1_INT_GEN_SRC_G 0x14U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl_g : 1;
uint8_t xh_g : 1;
uint8_t yl_g : 1;
@@ -234,12 +362,24 @@ typedef struct {
uint8_t zh_g : 1;
uint8_t ia_g : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t ia_g : 1;
+ uint8_t zh_g : 1;
+ uint8_t zl_g : 1;
+ uint8_t yh_g : 1;
+ uint8_t yl_g : 1;
+ uint8_t xh_g : 1;
+ uint8_t xl_g : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_int_gen_src_g_t;
#define LSM9DS1_OUT_TEMP_L 0x15U
#define LSM9DS1_OUT_TEMP_H 0x16U
#define LSM9DS1_STATUS_REG 0x17U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlda : 1;
uint8_t gda : 1;
uint8_t tda : 1;
@@ -248,6 +388,16 @@ typedef struct {
uint8_t ig_g : 1;
uint8_t ig_xl : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t ig_xl : 1;
+ uint8_t ig_g : 1;
+ uint8_t inact : 1;
+ uint8_t boot_status : 1;
+ uint8_t tda : 1;
+ uint8_t gda : 1;
+ uint8_t xlda : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_status_reg_t;
#define LSM9DS1_OUT_X_L_G 0x18U
@@ -257,45 +407,85 @@ typedef struct {
#define LSM9DS1_OUT_Z_L_G 0x1CU
#define LSM9DS1_OUT_Z_H_G 0x1DU
#define LSM9DS1_CTRL_REG4 0x1EU
-typedef struct {
- uint8_t _4d_xl1 : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t _4d_xl1 : 1;
uint8_t lir_xl1 : 1;
uint8_t not_used_01 : 1;
uint8_t xen_g : 1;
uint8_t yen_g : 1;
uint8_t zen_g : 1;
uint8_t not_used_02 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 2;
+ uint8_t zen_g : 1;
+ uint8_t yen_g : 1;
+ uint8_t xen_g : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t lir_xl1 : 1;
+ uint8_t _4d_xl1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_ctrl_reg4_t;
#define LSM9DS1_CTRL_REG5_XL 0x1FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t xen_xl : 1;
uint8_t yen_xl : 1;
uint8_t zen_xl : 1;
uint8_t dec : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t dec : 2;
+ uint8_t zen_xl : 1;
+ uint8_t yen_xl : 1;
+ uint8_t xen_xl : 1;
+ uint8_t not_used_01 : 3;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_ctrl_reg5_xl_t;
#define LSM9DS1_CTRL_REG6_XL 0x20U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bw_xl : 2;
uint8_t bw_scal_odr : 1;
uint8_t fs_xl : 2;
uint8_t odr_xl : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t odr_xl : 3;
+ uint8_t fs_xl : 2;
+ uint8_t bw_scal_odr : 1;
+ uint8_t bw_xl : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_ctrl_reg6_xl_t;
#define LSM9DS1_CTRL_REG7_XL 0x21U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t hpis1 : 1;
uint8_t not_used_01 : 1;
uint8_t fds : 1;
uint8_t not_used_02 : 2;
uint8_t dcf : 2;
uint8_t hr : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t hr : 1;
+ uint8_t dcf : 2;
+ uint8_t not_used_02 : 2;
+ uint8_t fds : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t hpis1 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_ctrl_reg7_xl_t;
#define LSM9DS1_CTRL_REG8 0x22U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sw_reset : 1;
uint8_t ble : 1;
uint8_t if_add_inc : 1;
@@ -304,10 +494,22 @@ typedef struct {
uint8_t h_lactive : 1;
uint8_t bdu : 1;
uint8_t boot : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t boot : 1;
+ uint8_t bdu : 1;
+ uint8_t h_lactive : 1;
+ uint8_t pp_od : 1;
+ uint8_t sim : 1;
+ uint8_t if_add_inc : 1;
+ uint8_t ble : 1;
+ uint8_t sw_reset : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_ctrl_reg8_t;
#define LSM9DS1_CTRL_REG9 0x23U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t stop_on_fth : 1;
uint8_t fifo_en : 1;
uint8_t i2c_disable : 1;
@@ -316,18 +518,38 @@ typedef struct {
uint8_t not_used_01 : 1;
uint8_t sleep_g : 1;
uint8_t not_used_02 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 1;
+ uint8_t sleep_g : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t fifo_temp_en : 1;
+ uint8_t drdy_mask_bit : 1;
+ uint8_t i2c_disable : 1;
+ uint8_t fifo_en : 1;
+ uint8_t stop_on_fth : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_ctrl_reg9_t;
#define LSM9DS1_CTRL_REG10 0x24U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_xl : 1;
uint8_t not_used_01 : 1;
uint8_t st_g : 1;
uint8_t not_used_02 : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 5;
+ uint8_t st_g : 1;
+ uint8_t not_used_01 : 1;
+ uint8_t st_xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_ctrl_reg10_t;
#define LSM9DS1_INT_GEN_SRC_XL 0x26U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl_xl : 1;
uint8_t xh_xl : 1;
uint8_t yl_xl : 1;
@@ -336,6 +558,16 @@ typedef struct {
uint8_t zh_xl : 1;
uint8_t ia_xl : 1;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t ia_xl : 1;
+ uint8_t zh_xl : 1;
+ uint8_t zl_xl : 1;
+ uint8_t yh_xl : 1;
+ uint8_t yl_xl : 1;
+ uint8_t xh_xl : 1;
+ uint8_t xl_xl : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_int_gen_src_xl_t;
#define LSM9DS1_OUT_X_L_XL 0x28U
@@ -345,20 +577,35 @@ typedef struct {
#define LSM9DS1_OUT_Z_L_XL 0x2CU
#define LSM9DS1_OUT_Z_H_XL 0x2DU
#define LSM9DS1_FIFO_CTRL 0x2EU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fth : 5;
uint8_t fmode : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fmode : 3;
+ uint8_t fth : 5;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_fifo_ctrl_t;
#define LSM9DS1_FIFO_SRC 0x2FU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fss : 6;
uint8_t ovrn : 1;
uint8_t fth : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fth : 1;
+ uint8_t ovrn : 1;
+ uint8_t fss : 6;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_fifo_src_t;
#define LSM9DS1_INT_GEN_CFG_G 0x30U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlie_g : 1;
uint8_t xhie_g : 1;
uint8_t ylie_g : 1;
@@ -367,42 +614,79 @@ typedef struct {
uint8_t zhie_g : 1;
uint8_t lir_g : 1;
uint8_t aoi_g : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t aoi_g : 1;
+ uint8_t lir_g : 1;
+ uint8_t zhie_g : 1;
+ uint8_t zlie_g : 1;
+ uint8_t yhie_g : 1;
+ uint8_t ylie_g : 1;
+ uint8_t xhie_g : 1;
+ uint8_t xlie_g : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_int_gen_cfg_g_t;
#define LSM9DS1_INT_GEN_THS_XH_G 0x31U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths_g_x : 7;
uint8_t dcrm_g : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t dcrm_g : 1;
+ uint8_t ths_g_x : 7;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_int_gen_ths_xh_g_t;
#define LSM9DS1_INT_GEN_THS_XL_G 0x32U
-typedef struct {
+typedef struct
+{
uint8_t ths_g_x : 8;
} lsm9ds1_int_gen_ths_xl_g_t;
#define LSM9DS1_INT_GEN_THS_YH_G 0x33U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths_g_y : 7;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t ths_g_y : 7;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_int_gen_ths_yh_g_t;
#define LSM9DS1_INT_GEN_THS_YL_G 0x34U
-typedef struct {
+typedef struct
+{
uint8_t ths_g_y : 8;
} lsm9ds1_int_gen_ths_yl_g_t;
#define LSM9DS1_INT_GEN_THS_ZH_G 0x35U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths_g_z : 7;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t ths_g_z : 7;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_int_gen_ths_zh_g_t;
#define LSM9DS1_INT_GEN_THS_ZL_G 0x36U
-typedef struct {
+typedef struct
+{
uint8_t ths_g_z : 8;
} lsm9ds1_int_gen_ths_zl_g_t;
#define LSM9DS1_INT_GEN_DUR_G 0x37U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t dur_g : 7;
uint8_t wait_g : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t wait_g : 1;
+ uint8_t dur_g : 7;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_int_gen_dur_g_t;
#define LSM9DS1_OFFSET_X_REG_L_M 0x05U
@@ -414,51 +698,97 @@ typedef struct {
#define LSM9DS1_WHO_AM_I_M 0x0FU
#define LSM9DS1_CTRL_REG1_M 0x20U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st : 1;
uint8_t fast_odr : 1;
- uint8_t _do : 3;
+ uint8_t _do : 3;
uint8_t om : 2;
uint8_t temp_comp : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t temp_comp : 1;
+ uint8_t om : 2;
+ uint8_t _do : 3;
+ uint8_t fast_odr : 1;
+ uint8_t st : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_ctrl_reg1_m_t;
#define LSM9DS1_CTRL_REG2_M 0x21U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t soft_rst : 1;
uint8_t reboot : 1;
uint8_t not_used_02 : 1;
uint8_t fs : 2;
uint8_t not_used_03 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_03 : 1;
+ uint8_t fs : 2;
+ uint8_t not_used_02 : 1;
+ uint8_t reboot : 1;
+ uint8_t soft_rst : 1;
+ uint8_t not_used_01 : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_ctrl_reg2_m_t;
#define LSM9DS1_CTRL_REG3_M 0x22U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t md : 2;
uint8_t sim : 1;
uint8_t not_used_01 : 2;
uint8_t lp : 1;
uint8_t not_used_02 : 1;
uint8_t i2c_disable : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t i2c_disable : 1;
+ uint8_t not_used_02 : 1;
+ uint8_t lp : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t sim : 1;
+ uint8_t md : 2;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_ctrl_reg3_m_t;
#define LSM9DS1_CTRL_REG4_M 0x23U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t ble : 1;
uint8_t omz : 2;
uint8_t not_used_02 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_02 : 4;
+ uint8_t omz : 2;
+ uint8_t ble : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_ctrl_reg4_m_t;
#define LSM9DS1_CTRL_REG5_M 0x24U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 6;
uint8_t bdu : 1;
uint8_t fast_read : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t fast_read : 1;
+ uint8_t bdu : 1;
+ uint8_t not_used_01 : 6;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_ctrl_reg5_m_t;
#define LSM9DS1_STATUS_REG_M 0x27U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xda : 1;
uint8_t yda : 1;
uint8_t zda : 1;
@@ -467,6 +797,16 @@ typedef struct {
uint8_t yor : 1;
uint8_t zor : 1;
uint8_t zyxor : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t zyxor : 1;
+ uint8_t zor : 1;
+ uint8_t yor : 1;
+ uint8_t _xor : 1;
+ uint8_t zyxda : 1;
+ uint8_t zda : 1;
+ uint8_t yda : 1;
+ uint8_t xda : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_status_reg_m_t;
#define LSM9DS1_OUT_X_L_M 0x28U
@@ -476,7 +816,9 @@ typedef struct {
#define LSM9DS1_OUT_Z_L_M 0x2CU
#define LSM9DS1_OUT_Z_H_M 0x2DU
#define LSM9DS1_INT_CFG_M 0x30U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ien : 1;
uint8_t iel : 1;
uint8_t iea : 1;
@@ -484,11 +826,22 @@ typedef struct {
uint8_t zien : 1;
uint8_t yien : 1;
uint8_t xien : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t xien : 1;
+ uint8_t yien : 1;
+ uint8_t zien : 1;
+ uint8_t not_used_01 : 2;
+ uint8_t iea : 1;
+ uint8_t iel : 1;
+ uint8_t ien : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_int_cfg_m_t;
#define LSM9DS1_INT_SRC_M 0x31U
-typedef struct {
- uint8_t _int : 1;
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+ uint8_t _int : 1;
uint8_t mroi : 1;
uint8_t nth_z : 1;
uint8_t nth_y : 1;
@@ -496,24 +849,41 @@ typedef struct {
uint8_t pth_z : 1;
uint8_t pth_y : 1;
uint8_t pth_x : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t pth_x : 1;
+ uint8_t pth_y : 1;
+ uint8_t pth_z : 1;
+ uint8_t nth_x : 1;
+ uint8_t nth_y : 1;
+ uint8_t nth_z : 1;
+ uint8_t mroi : 1;
+ uint8_t _int : 1;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_int_src_m_t;
#define LSM9DS1_INT_THS_L_M 0x32U
-typedef struct {
+typedef struct
+{
uint8_t ths : 8;
} lsm9ds1_int_ths_l_m_t;
#define LSM9DS1_INT_THS_H_M 0x33U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ths : 7;
uint8_t not_used_01 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 1;
+ uint8_t ths : 7;
+#endif /* DRV_BYTE_ORDER */
} lsm9ds1_int_ths_h_m_t;
/**
* @defgroup LSM9DS1_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -521,7 +891,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
lsm9ds1_act_ths_t act_ths;
lsm9ds1_int_gen_cfg_xl_t int_gen_cfg_xl;
lsm9ds1_int_gen_dur_xl_t int_gen_dur_xl;
@@ -570,36 +941,42 @@ typedef union{
*
*/
-int32_t lsm9ds1_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lsm9ds1_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t lsm9ds1_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t lsm9ds1_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-extern float_t lsm9ds1_from_fs2g_to_mg(int16_t lsb);
-extern float_t lsm9ds1_from_fs4g_to_mg(int16_t lsb);
-extern float_t lsm9ds1_from_fs8g_to_mg(int16_t lsb);
-extern float_t lsm9ds1_from_fs16g_to_mg(int16_t lsb);
+float_t lsm9ds1_from_fs2g_to_mg(int16_t lsb);
+float_t lsm9ds1_from_fs4g_to_mg(int16_t lsb);
+float_t lsm9ds1_from_fs8g_to_mg(int16_t lsb);
+float_t lsm9ds1_from_fs16g_to_mg(int16_t lsb);
-extern float_t lsm9ds1_from_fs245dps_to_mdps(int16_t lsb);
-extern float_t lsm9ds1_from_fs500dps_to_mdps(int16_t lsb);
-extern float_t lsm9ds1_from_fs2000dps_to_mdps(int16_t lsb);
+float_t lsm9ds1_from_fs245dps_to_mdps(int16_t lsb);
+float_t lsm9ds1_from_fs500dps_to_mdps(int16_t lsb);
+float_t lsm9ds1_from_fs2000dps_to_mdps(int16_t lsb);
-extern float_t lsm9ds1_from_fs4gauss_to_mG(int16_t lsb);
-extern float_t lsm9ds1_from_fs8gauss_to_mG(int16_t lsb);
-extern float_t lsm9ds1_from_fs12gauss_to_mG(int16_t lsb);
-extern float_t lsm9ds1_from_fs16gauss_to_mG(int16_t lsb);
+float_t lsm9ds1_from_fs4gauss_to_mG(int16_t lsb);
+float_t lsm9ds1_from_fs8gauss_to_mG(int16_t lsb);
+float_t lsm9ds1_from_fs12gauss_to_mG(int16_t lsb);
+float_t lsm9ds1_from_fs16gauss_to_mG(int16_t lsb);
-extern float_t lsm9ds1_from_lsb_to_celsius(int16_t lsb);
+float_t lsm9ds1_from_lsb_to_celsius(int16_t lsb);
-typedef enum {
+typedef enum
+{
LSM9DS1_245dps = 0,
LSM9DS1_500dps = 1,
LSM9DS1_2000dps = 3,
} lsm9ds1_gy_fs_t;
-int32_t lsm9ds1_gy_full_scale_set(stmdev_ctx_t *ctx, lsm9ds1_gy_fs_t val);
-int32_t lsm9ds1_gy_full_scale_get(stmdev_ctx_t *ctx, lsm9ds1_gy_fs_t *val);
+int32_t lsm9ds1_gy_full_scale_set(stmdev_ctx_t *ctx,
+ lsm9ds1_gy_fs_t val);
+int32_t lsm9ds1_gy_full_scale_get(stmdev_ctx_t *ctx,
+ lsm9ds1_gy_fs_t *val);
-typedef enum {
+typedef enum
+{
LSM9DS1_IMU_OFF = 0x00,
LSM9DS1_GY_OFF_XL_10Hz = 0x10,
LSM9DS1_GY_OFF_XL_50Hz = 0x20,
@@ -631,64 +1008,81 @@ int32_t lsm9ds1_imu_data_rate_set(stmdev_ctx_t *ctx,
int32_t lsm9ds1_imu_data_rate_get(stmdev_ctx_t *ctx,
lsm9ds1_imu_odr_t *val);
-typedef struct {
+typedef struct
+{
uint8_t orient : 3;
uint8_t signz_g : 1; /*(0: positive; 1: negative)*/
uint8_t signy_g : 1; /*(0: positive; 1: negative)*/
uint8_t signx_g : 1; /*(0: positive; 1: negative)*/
} lsm9ds1_gy_orient_t;
-int32_t lsm9ds1_gy_orient_set(stmdev_ctx_t *ctx, lsm9ds1_gy_orient_t val);
-int32_t lsm9ds1_gy_orient_get(stmdev_ctx_t *ctx, lsm9ds1_gy_orient_t *val);
+int32_t lsm9ds1_gy_orient_set(stmdev_ctx_t *ctx,
+ lsm9ds1_gy_orient_t val);
+int32_t lsm9ds1_gy_orient_get(stmdev_ctx_t *ctx,
+ lsm9ds1_gy_orient_t *val);
-int32_t lsm9ds1_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm9ds1_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm9ds1_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm9ds1_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm9ds1_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm9ds1_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef struct {
+typedef struct
+{
uint8_t xen_g : 1;
uint8_t yen_g : 1;
uint8_t zen_g : 1;
} lsm9ds1_gy_axis_t;
int32_t lsm9ds1_gy_axis_set(stmdev_ctx_t *ctx, lsm9ds1_gy_axis_t val);
-int32_t lsm9ds1_gy_axis_get(stmdev_ctx_t *ctx, lsm9ds1_gy_axis_t *val);
+int32_t lsm9ds1_gy_axis_get(stmdev_ctx_t *ctx,
+ lsm9ds1_gy_axis_t *val);
-typedef struct {
+typedef struct
+{
uint8_t xen_xl : 1;
uint8_t yen_xl : 1;
uint8_t zen_xl : 1;
} lsm9ds1_xl_axis_t;
int32_t lsm9ds1_xl_axis_set(stmdev_ctx_t *ctx, lsm9ds1_xl_axis_t val);
-int32_t lsm9ds1_xl_axis_get(stmdev_ctx_t *ctx, lsm9ds1_xl_axis_t *val);
+int32_t lsm9ds1_xl_axis_get(stmdev_ctx_t *ctx,
+ lsm9ds1_xl_axis_t *val);
-typedef enum {
+typedef enum
+{
LSM9DS1_NO_DECIMATION = 0,
LSM9DS1_EVERY_2_SAMPLES = 1,
LSM9DS1_EVERY_4_SAMPLES = 2,
LSM9DS1_EVERY_8_SAMPLES = 3,
} lsm9ds1_dec_t;
-int32_t lsm9ds1_xl_decimation_set(stmdev_ctx_t *ctx, lsm9ds1_dec_t val);
-int32_t lsm9ds1_xl_decimation_get(stmdev_ctx_t *ctx, lsm9ds1_dec_t *val);
+int32_t lsm9ds1_xl_decimation_set(stmdev_ctx_t *ctx,
+ lsm9ds1_dec_t val);
+int32_t lsm9ds1_xl_decimation_get(stmdev_ctx_t *ctx,
+ lsm9ds1_dec_t *val);
-typedef enum {
+typedef enum
+{
LSM9DS1_2g = 0,
LSM9DS1_16g = 1,
LSM9DS1_4g = 2,
LSM9DS1_8g = 3,
} lsm9ds1_xl_fs_t;
-int32_t lsm9ds1_xl_full_scale_set(stmdev_ctx_t *ctx, lsm9ds1_xl_fs_t val);
-int32_t lsm9ds1_xl_full_scale_get(stmdev_ctx_t *ctx, lsm9ds1_xl_fs_t *val);
+int32_t lsm9ds1_xl_full_scale_set(stmdev_ctx_t *ctx,
+ lsm9ds1_xl_fs_t val);
+int32_t lsm9ds1_xl_full_scale_get(stmdev_ctx_t *ctx,
+ lsm9ds1_xl_fs_t *val);
int32_t lsm9ds1_block_data_update_set(stmdev_ctx_t *ctx_mag,
stmdev_ctx_t *ctx_imu, uint8_t val);
int32_t lsm9ds1_block_data_update_get(stmdev_ctx_t *ctx_mag,
stmdev_ctx_t *ctx_imu, uint8_t *val);
-int32_t lsm9ds1_mag_offset_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm9ds1_mag_offset_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm9ds1_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val);
+int32_t lsm9ds1_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val);
-typedef enum {
+typedef enum
+{
LSM9DS1_MAG_POWER_DOWN = 0xC0,
LSM9DS1_MAG_LP_0Hz625 = 0x00,
LSM9DS1_MAG_LP_1Hz25 = 0x01,
@@ -733,7 +1127,8 @@ int32_t lsm9ds1_mag_data_rate_set(stmdev_ctx_t *ctx,
int32_t lsm9ds1_mag_data_rate_get(stmdev_ctx_t *ctx,
lsm9ds1_mag_data_rate_t *val);
-typedef enum {
+typedef enum
+{
LSM9DS1_4Ga = 0,
LSM9DS1_8Ga = 1,
LSM9DS1_12Ga = 2,
@@ -744,38 +1139,47 @@ int32_t lsm9ds1_mag_full_scale_set(stmdev_ctx_t *ctx,
int32_t lsm9ds1_mag_full_scale_get(stmdev_ctx_t *ctx,
lsm9ds1_mag_fs_t *val);
-int32_t lsm9ds1_mag_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm9ds1_mag_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t lsm9ds1_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm9ds1_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val);
-int32_t lsm9ds1_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm9ds1_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val);
-int32_t lsm9ds1_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm9ds1_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val);
-int32_t lsm9ds1_magnetic_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm9ds1_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val);
-int32_t lsm9ds1_magnetic_overflow_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm9ds1_magnetic_overflow_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef struct {
+typedef struct
+{
uint8_t imu;
uint8_t mag;
} lsm9ds1_id_t;
-int32_t lsm9ds1_dev_id_get(stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu,
+int32_t lsm9ds1_dev_id_get(stmdev_ctx_t *ctx_mag,
+ stmdev_ctx_t *ctx_imu,
lsm9ds1_id_t *buff);
-typedef struct {
+typedef struct
+{
lsm9ds1_status_reg_m_t status_mag;
lsm9ds1_status_reg_t status_imu;
} lsm9ds1_status_t;
-int32_t lsm9ds1_dev_status_get(stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu,
+int32_t lsm9ds1_dev_status_get(stmdev_ctx_t *ctx_mag,
+ stmdev_ctx_t *ctx_imu,
lsm9ds1_status_t *val);
-int32_t lsm9ds1_dev_reset_set(stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu,
+int32_t lsm9ds1_dev_reset_set(stmdev_ctx_t *ctx_mag,
+ stmdev_ctx_t *ctx_imu,
uint8_t val);
-int32_t lsm9ds1_dev_reset_get(stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu,
+int32_t lsm9ds1_dev_reset_get(stmdev_ctx_t *ctx_mag,
+ stmdev_ctx_t *ctx_imu,
uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM9DS1_LSB_LOW_ADDRESS = 0,
LSM9DS1_MSB_LOW_ADDRESS = 1,
} lsm9ds1_ble_t;
@@ -786,15 +1190,20 @@ int32_t lsm9ds1_dev_data_format_get(stmdev_ctx_t *ctx_mag,
stmdev_ctx_t *ctx_imu,
lsm9ds1_ble_t *val);
-int32_t lsm9ds1_dev_boot_set(stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu,
+int32_t lsm9ds1_dev_boot_set(stmdev_ctx_t *ctx_mag,
+ stmdev_ctx_t *ctx_imu,
uint8_t val);
-int32_t lsm9ds1_dev_boot_get(stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu,
+int32_t lsm9ds1_dev_boot_get(stmdev_ctx_t *ctx_mag,
+ stmdev_ctx_t *ctx_imu,
uint8_t *val);
-int32_t lsm9ds1_gy_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm9ds1_gy_filter_reference_get(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm9ds1_gy_filter_reference_set(stmdev_ctx_t *ctx,
+ uint8_t *buff);
+int32_t lsm9ds1_gy_filter_reference_get(stmdev_ctx_t *ctx,
+ uint8_t *buff);
-typedef enum {
+typedef enum
+{
LSM9DS1_LP_STRONG = 0,
LSM9DS1_LP_MEDIUM = 1,
LSM9DS1_LP_LIGHT = 2,
@@ -805,7 +1214,8 @@ int32_t lsm9ds1_gy_filter_lp_bandwidth_set(stmdev_ctx_t *ctx,
int32_t lsm9ds1_gy_filter_lp_bandwidth_get(stmdev_ctx_t *ctx,
lsm9ds1_gy_lp_bw_t *val);
-typedef enum {
+typedef enum
+{
LSM9DS1_LPF1_OUT = 0x00,
LSM9DS1_LPF1_HPF_OUT = 0x01,
LSM9DS1_LPF1_LPF2_OUT = 0x02,
@@ -816,7 +1226,8 @@ int32_t lsm9ds1_gy_filter_out_path_set(stmdev_ctx_t *ctx,
int32_t lsm9ds1_gy_filter_out_path_get(stmdev_ctx_t *ctx,
lsm9ds1_gy_out_path_t *val);
-typedef enum {
+typedef enum
+{
LSM9DS1_LPF1_INT = 0x00,
LSM9DS1_LPF1_HPF_INT = 0x01,
LSM9DS1_LPF1_LPF2_INT = 0x02,
@@ -827,7 +1238,8 @@ int32_t lsm9ds1_gy_filter_int_path_set(stmdev_ctx_t *ctx,
int32_t lsm9ds1_gy_filter_int_path_get(stmdev_ctx_t *ctx,
lsm9ds1_gy_int_path_t *val);
-typedef enum {
+typedef enum
+{
LSM9DS1_HP_EXTREME = 0,
LSM9DS1_HP_ULTRA_STRONG = 1,
LSM9DS1_HP_STRONG = 2,
@@ -844,7 +1256,8 @@ int32_t lsm9ds1_gy_filter_hp_bandwidth_set(stmdev_ctx_t *ctx,
int32_t lsm9ds1_gy_filter_hp_bandwidth_get(stmdev_ctx_t *ctx,
lsm9ds1_gy_hp_bw_t *val);
-typedef enum {
+typedef enum
+{
LSM9DS1_AUTO = 0x00,
LSM9DS1_408Hz = 0x10,
LSM9DS1_211Hz = 0x11,
@@ -855,7 +1268,8 @@ int32_t lsm9ds1_xl_filter_aalias_bandwidth_set(stmdev_ctx_t *ctx,
lsm9ds1_xl_aa_bw_t val);
int32_t lsm9ds1_xl_filter_aalias_bandwidth_get(stmdev_ctx_t *ctx,
lsm9ds1_xl_aa_bw_t *val);
-typedef enum {
+typedef enum
+{
LSM9DS1_HP_DIS = 0,
LSM9DS1_HP_EN = 1,
} lsm9ds1_xl_hp_path_t;
@@ -864,7 +1278,8 @@ int32_t lsm9ds1_xl_filter_int_path_set(stmdev_ctx_t *ctx,
int32_t lsm9ds1_xl_filter_int_path_get(stmdev_ctx_t *ctx,
lsm9ds1_xl_hp_path_t *val);
-typedef enum {
+typedef enum
+{
LSM9DS1_LP_OUT = 0,
LSM9DS1_HP_OUT = 1,
} lsm9ds1_xl_out_path_t;
@@ -873,7 +1288,8 @@ int32_t lsm9ds1_xl_filter_out_path_set(stmdev_ctx_t *ctx,
int32_t lsm9ds1_xl_filter_out_path_get(stmdev_ctx_t *ctx,
lsm9ds1_xl_out_path_t *val);
-typedef enum {
+typedef enum
+{
LSM9DS1_LP_DISABLE = 0x00,
LSM9DS1_LP_ODR_DIV_50 = 0x10,
LSM9DS1_LP_ODR_DIV_100 = 0x11,
@@ -885,7 +1301,8 @@ int32_t lsm9ds1_xl_filter_lp_bandwidth_set(stmdev_ctx_t *ctx,
int32_t lsm9ds1_xl_filter_lp_bandwidth_get(stmdev_ctx_t *ctx,
lsm9ds1_xl_lp_bw_t *val);
-typedef enum {
+typedef enum
+{
LSM9DS1_HP_ODR_DIV_50 = 0,
LSM9DS1_HP_ODR_DIV_100 = 1,
LSM9DS1_HP_ODR_DIV_9 = 2,
@@ -896,22 +1313,28 @@ int32_t lsm9ds1_xl_filter_hp_bandwidth_set(stmdev_ctx_t *ctx,
int32_t lsm9ds1_xl_filter_hp_bandwidth_get(stmdev_ctx_t *ctx,
lsm9ds1_xl_hp_bw_t *val);
-int32_t lsm9ds1_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm9ds1_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm9ds1_filter_settling_mask_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm9ds1_filter_settling_mask_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
int32_t lsm9ds1_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm9ds1_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM9DS1_SPI_4_WIRE = 0,
LSM9DS1_SPI_3_WIRE = 1,
} lsm9ds1_sim_t;
-int32_t lsm9ds1_spi_mode_set(stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu,
+int32_t lsm9ds1_spi_mode_set(stmdev_ctx_t *ctx_mag,
+ stmdev_ctx_t *ctx_imu,
lsm9ds1_sim_t val);
-int32_t lsm9ds1_spi_mode_get(stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu,
+int32_t lsm9ds1_spi_mode_get(stmdev_ctx_t *ctx_mag,
+ stmdev_ctx_t *ctx_imu,
lsm9ds1_sim_t *val);
-typedef enum {
+typedef enum
+{
LSM9DS1_I2C_ENABLE = 0,
LSM9DS1_I2C_DISABLE = 1,
} lsm9ds1_i2c_dis_t;
@@ -922,14 +1345,18 @@ int32_t lsm9ds1_i2c_interface_get(stmdev_ctx_t *ctx_mag,
stmdev_ctx_t *ctx_imu,
lsm9ds1_i2c_dis_t *val);
-typedef enum {
+typedef enum
+{
LSM9DS1_LOGIC_OR = 0,
LSM9DS1_LOGIC_AND = 1,
} lsm9ds1_pin_logic_t;
-int32_t lsm9ds1_pin_logic_set(stmdev_ctx_t *ctx, lsm9ds1_pin_logic_t val);
-int32_t lsm9ds1_pin_logic_get(stmdev_ctx_t *ctx, lsm9ds1_pin_logic_t *val);
+int32_t lsm9ds1_pin_logic_set(stmdev_ctx_t *ctx,
+ lsm9ds1_pin_logic_t val);
+int32_t lsm9ds1_pin_logic_get(stmdev_ctx_t *ctx,
+ lsm9ds1_pin_logic_t *val);
-typedef struct {
+typedef struct
+{
uint8_t int1_drdy_xl : 1;
uint8_t int1_drdy_g : 1;
uint8_t int1_boot : 1;
@@ -943,7 +1370,8 @@ int32_t lsm9ds1_pin_int1_route_set(stmdev_ctx_t *ctx,
lsm9ds1_pin_int1_route_t val);
int32_t lsm9ds1_pin_int1_route_get(stmdev_ctx_t *ctx,
lsm9ds1_pin_int1_route_t *val);
-typedef struct {
+typedef struct
+{
uint8_t int2_drdy_xl : 1;
uint8_t int2_drdy_g : 1;
uint8_t int2_drdy_temp : 1;
@@ -957,7 +1385,8 @@ int32_t lsm9ds1_pin_int2_route_set(stmdev_ctx_t *ctx,
int32_t lsm9ds1_pin_int2_route_get(stmdev_ctx_t *ctx,
lsm9ds1_pin_int2_route_t *val);
-typedef enum {
+typedef enum
+{
LSM9DS1_INT_PULSED = 0,
LSM9DS1_INT_LATCHED = 1,
} lsm9ds1_lir_t;
@@ -968,21 +1397,24 @@ int32_t lsm9ds1_pin_notification_get(stmdev_ctx_t *ctx_mag,
stmdev_ctx_t *ctx_imu,
lsm9ds1_lir_t *val);
-typedef enum {
+typedef enum
+{
LSM9DS1_PUSH_PULL = 0,
LSM9DS1_OPEN_DRAIN = 1,
} lsm9ds1_pp_od_t;
int32_t lsm9ds1_pin_mode_set(stmdev_ctx_t *ctx, lsm9ds1_pp_od_t val);
int32_t lsm9ds1_pin_mode_get(stmdev_ctx_t *ctx, lsm9ds1_pp_od_t *val);
-typedef struct {
+typedef struct
+{
uint8_t ien : 1;
} lsm9ds1_pin_m_route_t;
int32_t lsm9ds1_pin_int_m_route_set(stmdev_ctx_t *ctx,
lsm9ds1_pin_m_route_t val);
int32_t lsm9ds1_pin_int_m_route_get(stmdev_ctx_t *ctx,
lsm9ds1_pin_m_route_t *val);
-typedef enum {
+typedef enum
+{
LSM9DS1_ACTIVE_LOW = 0,
LSM9DS1_ACTIVE_HIGH = 1,
} lsm9ds1_polarity_t;
@@ -993,7 +1425,8 @@ int32_t lsm9ds1_pin_polarity_get(stmdev_ctx_t *ctx_mag,
stmdev_ctx_t *ctx_imu,
lsm9ds1_polarity_t *val);
-typedef struct {
+typedef struct
+{
uint8_t xlie_xl : 1;
uint8_t xhie_xl : 1;
uint8_t ylie_xl : 1;
@@ -1009,10 +1442,13 @@ int32_t lsm9ds1_xl_trshld_axis_get(stmdev_ctx_t *ctx,
int32_t lsm9ds1_xl_trshld_set(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t lsm9ds1_xl_trshld_get(stmdev_ctx_t *ctx, uint8_t *buff);
-int32_t lsm9ds1_xl_trshld_min_sample_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm9ds1_xl_trshld_min_sample_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm9ds1_xl_trshld_min_sample_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm9ds1_xl_trshld_min_sample_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef struct {
+typedef struct
+{
uint8_t xl_g : 1;
uint8_t xh_g : 1;
uint8_t yl_g : 1;
@@ -1024,7 +1460,8 @@ typedef struct {
int32_t lsm9ds1_gy_trshld_src_get(stmdev_ctx_t *ctx,
lsm9ds1_gy_trshld_src_t *val);
-typedef struct {
+typedef struct
+{
uint8_t xl_xl : 1;
uint8_t xh_xl : 1;
uint8_t yl_xl : 1;
@@ -1034,9 +1471,10 @@ typedef struct {
uint8_t ia_xl : 1;
} lsm9ds1_xl_trshld_src_t;
int32_t lsm9ds1_xl_trshld_src_get(stmdev_ctx_t *ctx,
- lsm9ds1_xl_trshld_src_t *val);
+ lsm9ds1_xl_trshld_src_t *val);
-typedef struct {
+typedef struct
+{
uint8_t xlie_g : 1;
uint8_t xhie_g : 1;
uint8_t ylie_g : 1;
@@ -1049,7 +1487,8 @@ int32_t lsm9ds1_gy_trshld_axis_set(stmdev_ctx_t *ctx,
int32_t lsm9ds1_gy_trshld_axis_get(stmdev_ctx_t *ctx,
lsm9ds1_gy_trshld_en_t *val);
-typedef enum {
+typedef enum
+{
LSM9DS1_RESET_MODE = 0,
LSM9DS1_DECREMENT_MODE = 1,
} lsm9ds1_dcrm_g_t;
@@ -1067,10 +1506,13 @@ int32_t lsm9ds1_gy_trshld_y_get(stmdev_ctx_t *ctx, uint16_t *val);
int32_t lsm9ds1_gy_trshld_z_set(stmdev_ctx_t *ctx, uint16_t val);
int32_t lsm9ds1_gy_trshld_z_get(stmdev_ctx_t *ctx, uint16_t *val);
-int32_t lsm9ds1_gy_trshld_min_sample_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t lsm9ds1_gy_trshld_min_sample_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t lsm9ds1_gy_trshld_min_sample_set(stmdev_ctx_t *ctx,
+ uint8_t val);
+int32_t lsm9ds1_gy_trshld_min_sample_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-typedef struct {
+typedef struct
+{
uint8_t zien : 1;
uint8_t yien : 1;
uint8_t xien : 1;
@@ -1079,7 +1521,8 @@ int32_t lsm9ds1_mag_trshld_axis_set(stmdev_ctx_t *ctx,
lsm9ds1_mag_trshld_axis_t val);
int32_t lsm9ds1_mag_trshld_axis_get(stmdev_ctx_t *ctx,
lsm9ds1_mag_trshld_axis_t *val);
-typedef struct {
+typedef struct
+{
uint8_t _int : 1;
uint8_t nth_z : 1;
uint8_t nth_y : 1;
@@ -1097,23 +1540,28 @@ int32_t lsm9ds1_mag_trshld_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t lsm9ds1_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm9ds1_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM9DS1_GYRO_POWER_DOWN = 0,
LSM9DS1_GYRO_SLEEP = 1,
} lsm9ds1_act_mode_t;
-int32_t lsm9ds1_act_mode_set(stmdev_ctx_t *ctx, lsm9ds1_act_mode_t val);
-int32_t lsm9ds1_act_mode_get(stmdev_ctx_t *ctx, lsm9ds1_act_mode_t *val);
+int32_t lsm9ds1_act_mode_set(stmdev_ctx_t *ctx,
+ lsm9ds1_act_mode_t val);
+int32_t lsm9ds1_act_mode_get(stmdev_ctx_t *ctx,
+ lsm9ds1_act_mode_t *val);
int32_t lsm9ds1_act_duration_set(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t lsm9ds1_act_duration_get(stmdev_ctx_t *ctx, uint8_t *buff);
-typedef enum {
+typedef enum
+{
LSM9DS1_ACTIVITY = 0,
LSM9DS1_INACTIVITY = 1,
} lsm9ds1_inact_t;
int32_t lsm9ds1_act_src_get(stmdev_ctx_t *ctx, lsm9ds1_inact_t *val);
-typedef enum {
+typedef enum
+{
LSM9DS1_POS_MOVE_RECO_DISABLE = 0x00,
LSM9DS1_6D_MOVE_RECO = 0x01,
LSM9DS1_4D_MOVE_RECO = 0x05,
@@ -1121,12 +1569,14 @@ typedef enum {
LSM9DS1_4D_POS_RECO = 0x07,
} lsm9ds1_6d_mode_t;
int32_t lsm9ds1_6d_mode_set(stmdev_ctx_t *ctx, lsm9ds1_6d_mode_t val);
-int32_t lsm9ds1_6d_mode_get(stmdev_ctx_t *ctx, lsm9ds1_6d_mode_t *val);
+int32_t lsm9ds1_6d_mode_get(stmdev_ctx_t *ctx,
+ lsm9ds1_6d_mode_t *val);
int32_t lsm9ds1_6d_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff);
int32_t lsm9ds1_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff);
-typedef struct {
+typedef struct
+{
uint8_t xl_xl : 1;
uint8_t xh_xl : 1;
uint8_t yl_xl : 1;
@@ -1140,7 +1590,8 @@ int32_t lsm9ds1_6d_src_get(stmdev_ctx_t *ctx, lsm9ds1_6d_src_t *val);
int32_t lsm9ds1_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm9ds1_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef enum {
+typedef enum
+{
LSM9DS1_FIFO_OFF = 0x00,
LSM9DS1_BYPASS_MODE = 0x10,
LSM9DS1_FIFO_MODE = 0x11,
@@ -1148,8 +1599,10 @@ typedef enum {
LSM9DS1_BYPASS_TO_STREAM_MODE = 0x14,
LSM9DS1_STREAM_MODE = 0x16,
} lsm9ds1_fifo_md_t;
-int32_t lsm9ds1_fifo_mode_set(stmdev_ctx_t *ctx, lsm9ds1_fifo_md_t val);
-int32_t lsm9ds1_fifo_mode_get(stmdev_ctx_t *ctx, lsm9ds1_fifo_md_t *val);
+int32_t lsm9ds1_fifo_mode_set(stmdev_ctx_t *ctx,
+ lsm9ds1_fifo_md_t val);
+int32_t lsm9ds1_fifo_mode_get(stmdev_ctx_t *ctx,
+ lsm9ds1_fifo_md_t *val);
int32_t lsm9ds1_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t lsm9ds1_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val);
diff --git a/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.c b/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.c
index 94577e915b0ba579bc75c6a286de9cd1bb469d93..161fc89e73750e01ff2d06b57e392c1e9e00f60e 100644
--- a/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.c
+++ b/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file stts22h_reg.c
- * @author Sensors Software Solution Team
- * @brief STTS22H driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file stts22h_reg.c
+ * @author Sensors Software Solution Team
+ * @brief STTS22H driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "stts22h_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t stts22h_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t stts22h_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t stts22h_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t stts22h_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t stts22h_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -86,7 +92,7 @@ int32_t stts22h_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
float_t stts22h_from_lsb_to_celsius(int16_t lsb)
{
- return ((float_t)lsb /100.0f);
+ return ((float_t)lsb / 100.0f);
}
/**
@@ -110,56 +116,76 @@ float_t stts22h_from_lsb_to_celsius(int16_t lsb)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t stts22h_temp_data_rate_set(stmdev_ctx_t *ctx, stts22h_odr_temp_t val)
+int32_t stts22h_temp_data_rate_set(stmdev_ctx_t *ctx,
+ stts22h_odr_temp_t val)
{
stts22h_software_reset_t software_reset;
stts22h_ctrl_t ctrl;
int32_t ret;
-
- ret = stts22h_read_reg(ctx, STTS22H_CTRL, (uint8_t*)&ctrl, 1);
- if ( ret == 0 ) {
- ret = stts22h_read_reg(ctx, STTS22H_SOFTWARE_RESET, (uint8_t*)&software_reset, 1);
+ ret = stts22h_read_reg(ctx, STTS22H_CTRL, (uint8_t *)&ctrl, 1);
+
+ if (ret == 0)
+ {
+ ret = stts22h_read_reg(ctx, STTS22H_SOFTWARE_RESET,
+ (uint8_t *)&software_reset, 1);
}
-
- if ( ( val == STTS22H_ONE_SHOT ) && ( ret == 0 ) ) {
+
+ if ((val == STTS22H_ONE_SHOT) && (ret == 0))
+ {
software_reset.sw_reset = PROPERTY_ENABLE;
- ret = stts22h_write_reg(ctx, STTS22H_SOFTWARE_RESET, (uint8_t*)&software_reset, 1);
- if ( ret == 0 ) {
+ ret = stts22h_write_reg(ctx, STTS22H_SOFTWARE_RESET,
+ (uint8_t *)&software_reset, 1);
+
+ if (ret == 0)
+ {
software_reset.sw_reset = PROPERTY_DISABLE;
- ret = stts22h_write_reg(ctx, STTS22H_SOFTWARE_RESET, (uint8_t*)&software_reset, 1);
+ ret = stts22h_write_reg(ctx, STTS22H_SOFTWARE_RESET,
+ (uint8_t *)&software_reset, 1);
}
}
- if ( ( ( val == STTS22H_25Hz ) || ( val == STTS22H_50Hz ) ||
- ( val == STTS22H_100Hz ) || ( val == STTS22H_200Hz ) ) &&
- ( ctrl.freerun == PROPERTY_DISABLE ) && ( ret == 0 ) ) {
+ if (((val == STTS22H_25Hz) || (val == STTS22H_50Hz) ||
+ (val == STTS22H_100Hz) || (val == STTS22H_200Hz)) &&
+ (ctrl.freerun == PROPERTY_DISABLE) && (ret == 0))
+ {
software_reset.sw_reset = PROPERTY_ENABLE;
- ret = stts22h_write_reg(ctx, STTS22H_SOFTWARE_RESET, (uint8_t*)&software_reset, 1);
- if ( ret == 0 ) {
+ ret = stts22h_write_reg(ctx, STTS22H_SOFTWARE_RESET,
+ (uint8_t *)&software_reset, 1);
+
+ if (ret == 0)
+ {
software_reset.sw_reset = PROPERTY_DISABLE;
- ret = stts22h_write_reg(ctx, STTS22H_SOFTWARE_RESET, (uint8_t*)&software_reset, 1);
+ ret = stts22h_write_reg(ctx, STTS22H_SOFTWARE_RESET,
+ (uint8_t *)&software_reset, 1);
}
}
- if ( ( val == STTS22H_1Hz ) && ( ret == 0 ) ) {
+ if ((val == STTS22H_1Hz) && (ret == 0))
+ {
software_reset.sw_reset = PROPERTY_ENABLE;
software_reset.low_odr_enable = PROPERTY_ENABLE;
- ret = stts22h_write_reg(ctx, STTS22H_SOFTWARE_RESET, (uint8_t*)&software_reset, 1);
- if ( ret == 0 ) {
+ ret = stts22h_write_reg(ctx, STTS22H_SOFTWARE_RESET,
+ (uint8_t *)&software_reset, 1);
+
+ if (ret == 0)
+ {
software_reset.sw_reset = PROPERTY_DISABLE;
software_reset.low_odr_enable = PROPERTY_ENABLE;
- ret = stts22h_write_reg(ctx, STTS22H_SOFTWARE_RESET, (uint8_t*)&software_reset, 1);
+ ret = stts22h_write_reg(ctx, STTS22H_SOFTWARE_RESET,
+ (uint8_t *)&software_reset, 1);
}
}
- if ( ret == 0 ) {
+ if (ret == 0)
+ {
ctrl.one_shot = (uint8_t)val & 0x01U;
ctrl.freerun = ((uint8_t)val & 0x02U) >> 1;
ctrl.low_odr_start = ((uint8_t)val & 0x04U) >> 2;
ctrl.avg = ((uint8_t)val & 0x30U) >> 4;
- ret = stts22h_write_reg(ctx, STTS22H_CTRL, (uint8_t*)&ctrl, 1);
+ ret = stts22h_write_reg(ctx, STTS22H_CTRL, (uint8_t *)&ctrl, 1);
}
+
return ret;
}
@@ -178,34 +204,45 @@ int32_t stts22h_temp_data_rate_get(stmdev_ctx_t *ctx,
int32_t ret;
ret = stts22h_read_reg(ctx, STTS22H_CTRL,
- (uint8_t*)&ctrl, 1);
- switch ( ctrl.one_shot | (ctrl.freerun << 1) | (ctrl.low_odr_start << 2) |
- (ctrl.avg << 4)){
+ (uint8_t *)&ctrl, 1);
+
+ switch (ctrl.one_shot | (ctrl.freerun << 1) | (ctrl.low_odr_start <<
+ 2) |
+ (ctrl.avg << 4))
+ {
case STTS22H_POWER_DOWN:
*val = STTS22H_POWER_DOWN;
break;
+
case STTS22H_ONE_SHOT:
*val = STTS22H_ONE_SHOT;
break;
+
case STTS22H_1Hz:
*val = STTS22H_1Hz;
break;
+
case STTS22H_25Hz:
*val = STTS22H_25Hz;
break;
+
case STTS22H_50Hz:
*val = STTS22H_50Hz;
break;
+
case STTS22H_100Hz:
*val = STTS22H_100Hz;
break;
+
case STTS22H_200Hz:
*val = STTS22H_200Hz;
break;
+
default:
*val = STTS22H_POWER_DOWN;
break;
}
+
return ret;
}
@@ -222,11 +259,14 @@ int32_t stts22h_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
stts22h_ctrl_t ctrl;
int32_t ret;
- ret = stts22h_read_reg(ctx, STTS22H_CTRL, (uint8_t*)&ctrl, 1);
- if(ret == 0){
+ ret = stts22h_read_reg(ctx, STTS22H_CTRL, (uint8_t *)&ctrl, 1);
+
+ if (ret == 0)
+ {
ctrl.bdu = val;
- ret = stts22h_write_reg(ctx, STTS22H_CTRL, (uint8_t*)&ctrl, 1);
+ ret = stts22h_write_reg(ctx, STTS22H_CTRL, (uint8_t *)&ctrl, 1);
}
+
return ret;
}
@@ -241,7 +281,9 @@ int32_t stts22h_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t stts22h_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
{
int32_t ret;
- ret = stts22h_read_reg(ctx, STTS22H_CTRL, (uint8_t*)val, 1);
+
+ ret = stts22h_read_reg(ctx, STTS22H_CTRL, (uint8_t *)val, 1);
+
return ret;
}
@@ -253,17 +295,24 @@ int32_t stts22h_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t stts22h_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
+int32_t stts22h_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val)
{
stts22h_status_t status;
int32_t ret;
- ret = stts22h_read_reg(ctx, STTS22H_STATUS, (uint8_t*)&status, 1);
- if (status.busy == PROPERTY_DISABLE){
+
+ ret = stts22h_read_reg(ctx, STTS22H_STATUS, (uint8_t *)&status, 1);
+
+ if (status.busy == PROPERTY_DISABLE)
+ {
*val = PROPERTY_ENABLE;
}
- else{
- *val = PROPERTY_DISABLE;
+
+ else
+ {
+ *val = PROPERTY_DISABLE;
}
+
return ret;
}
@@ -288,24 +337,18 @@ int32_t stts22h_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t stts22h_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff)
-{
- uint16_t temperature;
- uint8_t temperature_low;
+int32_t stts22h_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
+{
+ uint8_t buff[2];
int32_t ret;
- ret = stts22h_read_reg(ctx, STTS22H_TEMP_L_OUT,
- &temperature_low, 1);
- if (ret == 0) {
- ret = stts22h_read_reg(ctx, STTS22H_TEMP_H_OUT,
- (uint8_t*)&temperature, 1);
+ ret = stts22h_read_reg(ctx, STTS22H_TEMP_L_OUT, buff, 2);
+ *val = (int16_t)buff[1];
+ *val = (*val * 256) + (int16_t)buff[0];
- temperature = (temperature << 8) + temperature_low;
- *buff = (int16_t)temperature;
- }
-
return ret;
}
+
/**
* @}
*
@@ -313,7 +356,7 @@ int32_t stts22h_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff)
/**
* @defgroup STTS22H_Common
- * @brief This section groups common usefull functions.
+ * @brief This section groups common useful functions.
* @{
*
*/
@@ -329,7 +372,9 @@ int32_t stts22h_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff)
int32_t stts22h_dev_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
+
ret = stts22h_read_reg(ctx, STTS22H_WHOAMI, buff, 1);
+
return ret;
}
/**
@@ -341,12 +386,13 @@ int32_t stts22h_dev_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t stts22h_dev_status_get(stmdev_ctx_t *ctx, stts22h_dev_status_t *val)
+int32_t stts22h_dev_status_get(stmdev_ctx_t *ctx,
+ stts22h_dev_status_t *val)
{
stts22h_status_t status;
int32_t ret;
- ret = stts22h_read_reg(ctx, STTS22H_STATUS, (uint8_t*)&status, 1);
+ ret = stts22h_read_reg(ctx, STTS22H_STATUS, (uint8_t *)&status, 1);
val->busy = status.busy;
return ret;
@@ -379,11 +425,14 @@ int32_t stts22h_smbus_interface_set(stmdev_ctx_t *ctx,
stts22h_ctrl_t ctrl;
int32_t ret;
- ret = stts22h_read_reg(ctx, STTS22H_CTRL, (uint8_t*)&ctrl, 1);
- if(ret == 0){
+ ret = stts22h_read_reg(ctx, STTS22H_CTRL, (uint8_t *)&ctrl, 1);
+
+ if (ret == 0)
+ {
ctrl.time_out_dis = (uint8_t)val;
- ret = stts22h_write_reg(ctx, STTS22H_CTRL, (uint8_t*)&ctrl, 1);
+ ret = stts22h_write_reg(ctx, STTS22H_CTRL, (uint8_t *)&ctrl, 1);
}
+
return ret;
}
@@ -395,25 +444,30 @@ int32_t stts22h_smbus_interface_set(stmdev_ctx_t *ctx,
* @retval Interface status (MANDATORY: return 0 -> no Error).
*
*/
-int32_t stts22h_smbus_interface_get(stmdev_ctx_t *ctx,
+int32_t stts22h_smbus_interface_get(stmdev_ctx_t *ctx,
stts22h_smbus_md_t *val)
{
stts22h_ctrl_t ctrl;
int32_t ret;
ret = stts22h_read_reg(ctx, STTS22H_CTRL,
- (uint8_t*)&ctrl, 1);
- switch (ctrl.time_out_dis){
+ (uint8_t *)&ctrl, 1);
+
+ switch (ctrl.time_out_dis)
+ {
case STTS22H_SMBUS_TIMEOUT_ENABLE:
*val = STTS22H_SMBUS_TIMEOUT_ENABLE;
break;
+
case STTS22H_SMBUS_TIMEOUT_DISABLE:
*val = STTS22H_SMBUS_TIMEOUT_DISABLE;
break;
+
default:
*val = STTS22H_SMBUS_TIMEOUT_ENABLE;
break;
}
+
return ret;
}
@@ -431,11 +485,14 @@ int32_t stts22h_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
stts22h_ctrl_t ctrl;
int32_t ret;
- ret = stts22h_read_reg(ctx, STTS22H_CTRL, (uint8_t*)&ctrl, 1);
- if(ret == 0){
+ ret = stts22h_read_reg(ctx, STTS22H_CTRL, (uint8_t *)&ctrl, 1);
+
+ if (ret == 0)
+ {
ctrl.if_add_inc = (uint8_t)val;
- ret = stts22h_write_reg(ctx, STTS22H_CTRL, (uint8_t*)&ctrl, 1);
+ ret = stts22h_write_reg(ctx, STTS22H_CTRL, (uint8_t *)&ctrl, 1);
}
+
return ret;
}
@@ -451,7 +508,9 @@ int32_t stts22h_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t stts22h_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
{
int32_t ret;
- ret = stts22h_read_reg(ctx, STTS22H_CTRL, (uint8_t*)&val, 1);
+
+ ret = stts22h_read_reg(ctx, STTS22H_CTRL, (uint8_t *)&val, 1);
+
return ret;
}
@@ -482,12 +541,15 @@ int32_t stts22h_temp_trshld_high_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = stts22h_read_reg(ctx, STTS22H_TEMP_H_LIMIT,
- (uint8_t*)&temp_h_limit, 1);
- if(ret == 0){
+ (uint8_t *)&temp_h_limit, 1);
+
+ if (ret == 0)
+ {
temp_h_limit.thl = val;
ret = stts22h_write_reg(ctx, STTS22H_TEMP_H_LIMIT,
- (uint8_t*)&temp_h_limit, 1);
+ (uint8_t *)&temp_h_limit, 1);
}
+
return ret;
}
@@ -505,7 +567,7 @@ int32_t stts22h_temp_trshld_high_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = stts22h_read_reg(ctx, STTS22H_TEMP_H_LIMIT,
- (uint8_t*)&temp_h_limit, 1);
+ (uint8_t *)&temp_h_limit, 1);
*val = temp_h_limit.thl;
return ret;
@@ -525,12 +587,15 @@ int32_t stts22h_temp_trshld_low_set(stmdev_ctx_t *ctx, uint8_t val)
int32_t ret;
ret = stts22h_read_reg(ctx, STTS22H_TEMP_L_LIMIT,
- (uint8_t*)&temp_l_limit, 1);
- if(ret == 0){
+ (uint8_t *)&temp_l_limit, 1);
+
+ if (ret == 0)
+ {
temp_l_limit.tll = val;
ret = stts22h_write_reg(ctx, STTS22H_TEMP_L_LIMIT,
- (uint8_t*)&temp_l_limit, 1);
+ (uint8_t *)&temp_l_limit, 1);
}
+
return ret;
}
@@ -548,7 +613,7 @@ int32_t stts22h_temp_trshld_low_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t ret;
ret = stts22h_read_reg(ctx, STTS22H_TEMP_L_LIMIT,
- (uint8_t*)&temp_l_limit, 1);
+ (uint8_t *)&temp_l_limit, 1);
*val = temp_l_limit.tll;
return ret;
@@ -568,7 +633,7 @@ int32_t stts22h_temp_trshld_src_get(stmdev_ctx_t *ctx,
stts22h_status_t status;
int32_t ret;
- ret = stts22h_read_reg(ctx, STTS22H_STATUS, (uint8_t*)&status, 1);
+ ret = stts22h_read_reg(ctx, STTS22H_STATUS, (uint8_t *)&status, 1);
val->under_thl = status.under_thl;
val->over_thh = status.over_thh;
diff --git a/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.h b/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.h
index b5a8aeaa096248dfec4bc84c4e8519e0a3d620b7..2ed5c4b74a94409218e4cd3865944724615d01a5 100644
--- a/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.h
+++ b/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file stts22h_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * stts22h_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file stts22h_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * stts22h_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STTS22H_REGS_H
#define STTS22H_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup STTS22H
@@ -35,6 +36,37 @@
*
*/
+/** @defgroup Endianness definitions
+ * @{
+ *
+ */
+
+#ifndef DRV_BYTE_ORDER
+#ifndef __BYTE_ORDER__
+
+#define DRV_LITTLE_ENDIAN 1234
+#define DRV_BIG_ENDIAN 4321
+
+/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
+ * by uncommenting the define which fits your platform endianness
+ */
+//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
+#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
+
+#else /* defined __BYTE_ORDER__ */
+
+#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
+#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
+#define DRV_BYTE_ORDER __BYTE_ORDER__
+
+#endif /* __BYTE_ORDER__*/
+#endif /* DRV_BYTE_ORDER */
+
+/**
+ * @}
+ *
+ */
+
/** @defgroup STMicroelectronics sensors common types
* @{
*
@@ -43,7 +75,9 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -52,6 +86,16 @@ typedef struct{
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} bitwise_t;
#define PROPERTY_DISABLE (0U)
@@ -65,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -89,15 +134,16 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
- * Unico / Unicleo tools available on STMicroelectronics
- * web site.
+ * You can create a sensor configuration by your own or using
+ * Unico / Unicleo tools available on STMicroelectronics
+ * web site.
*
* @{
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -133,17 +179,21 @@ typedef struct {
#define STTS22H_WHOAMI 0x01U
#define STTS22H_TEMP_H_LIMIT 0x02U
-typedef struct {
+typedef struct
+{
uint8_t thl : 8;
} stts22h_temp_h_limit_t;
#define STTS22H_TEMP_L_LIMIT 0x03U
-typedef struct {
+typedef struct
+{
uint8_t tll : 8;
} stts22h_temp_l_limit_t;
#define STTS22H_CTRL 0x04U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t one_shot : 1;
uint8_t time_out_dis : 1;
uint8_t freerun : 1;
@@ -151,33 +201,59 @@ typedef struct {
uint8_t avg : 2;
uint8_t bdu : 1;
uint8_t low_odr_start : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t low_odr_start : 1;
+ uint8_t bdu : 1;
+ uint8_t avg : 2;
+ uint8_t if_add_inc : 1;
+ uint8_t freerun : 1;
+ uint8_t time_out_dis : 1;
+ uint8_t one_shot : 1;
+#endif /* DRV_BYTE_ORDER */
} stts22h_ctrl_t;
#define STTS22H_STATUS 0x05U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t busy : 1;
uint8_t over_thh : 1;
uint8_t under_thl : 1;
uint8_t not_used_01 : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 5;
+ uint8_t under_thl : 1;
+ uint8_t over_thh : 1;
+ uint8_t busy : 1;
+#endif /* DRV_BYTE_ORDER */
} stts22h_status_t;
#define STTS22H_TEMP_L_OUT 0x06U
#define STTS22H_TEMP_H_OUT 0x07U
#define STTS22H_SOFTWARE_RESET 0x0CU
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t sw_reset : 1;
uint8_t not_used_02 : 4;
uint8_t low_odr_enable : 1;
uint8_t not_used_03 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_03 : 1;
+ uint8_t low_odr_enable : 1;
+ uint8_t not_used_02 : 4;
+ uint8_t sw_reset : 1;
+ uint8_t not_used_01 : 1;
+#endif /* DRV_BYTE_ORDER */
} stts22h_software_reset_t;
/**
* @defgroup STTS22H_Register_Union
- * @brief This union group all the registers that has a bit-field
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -185,7 +261,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
stts22h_temp_h_limit_t temp_h_limit;
stts22h_temp_l_limit_t temp_l_limit;
stts22h_ctrl_t ctrl;
@@ -200,14 +277,17 @@ typedef union{
*
*/
-int32_t stts22h_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t stts22h_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t stts22h_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t stts22h_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-extern float_t stts22h_from_lsb_to_celsius(int16_t lsb);
+float_t stts22h_from_lsb_to_celsius(int16_t lsb);
-typedef enum {
+typedef enum
+{
STTS22H_POWER_DOWN = 0x00,
STTS22H_ONE_SHOT = 0x01,
STTS22H_1Hz = 0x04,
@@ -222,20 +302,25 @@ int32_t stts22h_temp_data_rate_get(stmdev_ctx_t *ctx,
stts22h_odr_temp_t *val);
int32_t stts22h_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
-int32_t stts22h_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t stts22h_block_data_update_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t stts22h_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
+int32_t stts22h_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+ uint8_t *val);
-int32_t stts22h_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff);
+int32_t stts22h_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val);
int32_t stts22h_dev_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
-typedef struct {
+typedef struct
+{
uint8_t busy : 1;
} stts22h_dev_status_t;
-int32_t stts22h_dev_status_get(stmdev_ctx_t *ctx, stts22h_dev_status_t *val);
+int32_t stts22h_dev_status_get(stmdev_ctx_t *ctx,
+ stts22h_dev_status_t *val);
-typedef enum {
+typedef enum
+{
STTS22H_SMBUS_TIMEOUT_ENABLE = 0,
STTS22H_SMBUS_TIMEOUT_DISABLE = 1,
} stts22h_smbus_md_t;
@@ -253,7 +338,8 @@ int32_t stts22h_temp_trshld_high_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t stts22h_temp_trshld_low_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t stts22h_temp_trshld_low_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef struct {
+typedef struct
+{
uint8_t under_thl : 1;
uint8_t over_thh : 1;
} stts22h_temp_trlhd_src_t;
diff --git a/sensor/stmemsc/stts751_STdC/driver/stts751_reg.c b/sensor/stmemsc/stts751_STdC/driver/stts751_reg.c
index 3cb58c5b7ac47f6b2b23a381728dc54be1b10673..b44227771803c34f3a8cb2e6fba09d1dbbe99840 100644
--- a/sensor/stmemsc/stts751_STdC/driver/stts751_reg.c
+++ b/sensor/stmemsc/stts751_STdC/driver/stts751_reg.c
@@ -1,21 +1,21 @@
-/*
- ******************************************************************************
- * @file stts751_reg.c
- * @author Sensors Software Solution Team
- * @brief STTS751 driver file
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file stts751_reg.c
+ * @author Sensors Software Solution Team
+ * @brief STTS751 driver file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
#include "stts751_reg.h"
@@ -46,11 +46,14 @@
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t stts751_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t stts751_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->read_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -64,11 +67,14 @@ int32_t stts751_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t stts751_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
- uint16_t len)
+int32_t stts751_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len)
{
int32_t ret;
+
ret = ctx->write_reg(ctx->handle, reg, data, len);
+
return ret;
}
@@ -85,9 +91,9 @@ int32_t stts751_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
*
*/
-float stts751_from_lsb_to_celsius(int16_t lsb)
+float_t stts751_from_lsb_to_celsius(int16_t lsb)
{
- return ((float)lsb) / 256.0f;
+ return ((float_t)lsb) / 256.0f;
}
/**
@@ -107,7 +113,7 @@ float stts751_from_lsb_to_celsius(int16_t lsb)
*
*/
-int16_t stts751_from_celsius_to_lsb(float celsius)
+int16_t stts751_from_celsius_to_lsb(float_t celsius)
{
return (int16_t)(celsius * 256.0f);
}
@@ -133,7 +139,8 @@ int16_t stts751_from_celsius_to_lsb(float celsius)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t stts751_temp_data_rate_set(stmdev_ctx_t *ctx, stts751_odr_t val)
+int32_t stts751_temp_data_rate_set(stmdev_ctx_t *ctx,
+ stts751_odr_t val)
{
stts751_configuration_t configuration;
stts751_conversion_rate_t conversion_rate;
@@ -141,24 +148,33 @@ int32_t stts751_temp_data_rate_set(stmdev_ctx_t *ctx, stts751_odr_t val)
int32_t ret;
ret = stts751_read_reg(ctx, STTS751_CONVERSION_RATE,
- (uint8_t*)&conversion_rate, 1);
- if (ret == 0) {
+ (uint8_t *)&conversion_rate, 1);
+
+ if (ret == 0)
+ {
conversion_rate.conv = (uint8_t)val & 0x0FU;
ret = stts751_write_reg(ctx, STTS751_CONVERSION_RATE,
- (uint8_t*)&conversion_rate, 1);
+ (uint8_t *)&conversion_rate, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
ret = stts751_read_reg(ctx, STTS751_CONFIGURATION,
- (uint8_t*)&configuration, 1);
+ (uint8_t *)&configuration, 1);
}
- if (ret == 0) {
+
+ if (ret == 0)
+ {
configuration.stop = ((uint8_t)val & 0x80U) >> 7;
ret = stts751_write_reg(ctx, STTS751_CONFIGURATION,
- (uint8_t*)&configuration, 1);
+ (uint8_t *)&configuration, 1);
}
- if ((ret == 0) && (val == STTS751_TEMP_ODR_ONE_SHOT)) {
+
+ if ((ret == 0) && (val == STTS751_TEMP_ODR_ONE_SHOT))
+ {
ret = stts751_write_reg(ctx, STTS751_ONE_SHOT, &dummy_value, 1);
}
+
return ret;
}
@@ -170,59 +186,77 @@ int32_t stts751_temp_data_rate_set(stmdev_ctx_t *ctx, stts751_odr_t val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t stts751_temp_data_rate_get(stmdev_ctx_t *ctx, stts751_odr_t *val)
+int32_t stts751_temp_data_rate_get(stmdev_ctx_t *ctx,
+ stts751_odr_t *val)
{
stts751_conversion_rate_t conversion_rate;
stts751_configuration_t configuration;
int32_t ret;
ret = stts751_read_reg(ctx, STTS751_CONVERSION_RATE,
- (uint8_t*)&conversion_rate, 1);
- if (ret == 0) {
+ (uint8_t *)&conversion_rate, 1);
+
+ if (ret == 0)
+ {
ret = stts751_read_reg(ctx, STTS751_CONFIGURATION,
- (uint8_t*)&configuration, 1);
+ (uint8_t *)&configuration, 1);
}
- switch ( (configuration.stop << 7) + conversion_rate.conv) {
+
+ switch ((configuration.stop << 7) + conversion_rate.conv)
+ {
case STTS751_TEMP_ODR_OFF:
*val = STTS751_TEMP_ODR_OFF;
break;
+
case STTS751_TEMP_ODR_ONE_SHOT:
*val = STTS751_TEMP_ODR_ONE_SHOT;
break;
+
case STTS751_TEMP_ODR_62mHz5:
*val = STTS751_TEMP_ODR_62mHz5;
break;
+
case STTS751_TEMP_ODR_125mHz:
*val = STTS751_TEMP_ODR_125mHz;
break;
- case STTS751_TEMP_ODR_250mHz:
+
+ case STTS751_TEMP_ODR_250mHz:
*val = STTS751_TEMP_ODR_250mHz;
break;
+
case STTS751_TEMP_ODR_500mHz:
*val = STTS751_TEMP_ODR_500mHz;
break;
+
case STTS751_TEMP_ODR_1Hz:
*val = STTS751_TEMP_ODR_1Hz;
break;
+
case STTS751_TEMP_ODR_2Hz:
*val = STTS751_TEMP_ODR_2Hz;
break;
- case STTS751_TEMP_ODR_4Hz:
+
+ case STTS751_TEMP_ODR_4Hz:
*val = STTS751_TEMP_ODR_4Hz;
break;
+
case STTS751_TEMP_ODR_8Hz:
*val = STTS751_TEMP_ODR_8Hz;
break;
+
case STTS751_TEMP_ODR_16Hz:
*val = STTS751_TEMP_ODR_16Hz;
break;
+
case STTS751_TEMP_ODR_32Hz:
*val = STTS751_TEMP_ODR_32Hz;
break;
+
default:
*val = STTS751_TEMP_ODR_OFF;
break;
}
+
return ret;
}
@@ -239,11 +273,14 @@ int32_t stts751_resolution_set(stmdev_ctx_t *ctx, stts751_tres_t val)
stts751_configuration_t reg;
int32_t ret;
- ret = stts751_read_reg(ctx, STTS751_CONFIGURATION,(uint8_t*) ®, 1);
- if (ret == 0) {
+ ret = stts751_read_reg(ctx, STTS751_CONFIGURATION, (uint8_t *) ®, 1);
+
+ if (ret == 0)
+ {
reg.tres = (uint8_t) val;
- ret = stts751_write_reg(ctx, STTS751_CONFIGURATION,(uint8_t*) ®, 1);
+ ret = stts751_write_reg(ctx, STTS751_CONFIGURATION, (uint8_t *) ®, 1);
}
+
return ret;
}
@@ -260,25 +297,31 @@ int32_t stts751_resolution_get(stmdev_ctx_t *ctx, stts751_tres_t *val)
stts751_configuration_t reg;
int32_t ret;
- ret = stts751_read_reg(ctx, STTS751_CONFIGURATION,(uint8_t*) ®, 1);
+ ret = stts751_read_reg(ctx, STTS751_CONFIGURATION, (uint8_t *) ®, 1);
- switch (reg.tres) {
+ switch (reg.tres)
+ {
case STTS751_9bit:
*val = STTS751_9bit;
break;
+
case STTS751_10bit:
*val = STTS751_10bit;
break;
+
case STTS751_11bit:
*val = STTS751_11bit;
break;
+
case STTS751_12bit:
*val = STTS751_12bit;
break;
+
default:
*val = STTS751_9bit;
break;
}
+
return ret;
}
@@ -290,10 +333,13 @@ int32_t stts751_resolution_get(stmdev_ctx_t *ctx, stts751_tres_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t stts751_status_reg_get(stmdev_ctx_t *ctx, stts751_status_t *val)
+int32_t stts751_status_reg_get(stmdev_ctx_t *ctx,
+ stts751_status_t *val)
{
int32_t ret;
- ret = stts751_read_reg(ctx, STTS751_STATUS, (uint8_t*) val, 1);
+
+ ret = stts751_read_reg(ctx, STTS751_STATUS, (uint8_t *) val, 1);
+
return ret;
}
@@ -310,7 +356,7 @@ int32_t stts751_flag_busy_get(stmdev_ctx_t *ctx, uint8_t *val)
stts751_status_t reg;
int32_t ret;
- ret = stts751_read_reg(ctx, STTS751_STATUS, (uint8_t*)®, 1);
+ ret = stts751_read_reg(ctx, STTS751_STATUS, (uint8_t *)®, 1);
*val = reg.busy;
return ret;
@@ -337,21 +383,22 @@ int32_t stts751_flag_busy_get(stmdev_ctx_t *ctx, uint8_t *val)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
-int32_t stts751_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff)
+int32_t stts751_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
{
- uint16_t temperature;
- uint8_t temperature_low;
+ uint8_t buff[2];
int32_t ret;
ret = stts751_read_reg(ctx, STTS751_TEMPERATURE_HIGH,
- (uint8_t*)&temperature, 1);
- if (ret == 0) {
- ret = stts751_read_reg(ctx, STTS751_TEMPERATURE_LOW,
- &temperature_low, 1);
+ (uint8_t *)&buff[1], 1);
- temperature = (temperature << 8) + temperature_low;
- *buff = (int16_t)temperature;
+ if (ret == 0)
+ {
+ ret = stts751_read_reg(ctx, STTS751_TEMPERATURE_LOW,
+ &buff[0], 1);
+ *val = (int16_t)buff[1];
+ *val = (*val * 256) + (int16_t)buff[0];
}
+
return ret;
}
@@ -380,11 +427,14 @@ int32_t stts751_pin_event_route_set(stmdev_ctx_t *ctx, uint8_t val)
stts751_configuration_t reg;
int32_t ret;
- ret = stts751_read_reg(ctx, STTS751_CONFIGURATION,(uint8_t*)®, 1);
- if (ret == 0) {
+ ret = stts751_read_reg(ctx, STTS751_CONFIGURATION, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.mask1 = val;
- ret = stts751_write_reg(ctx, STTS751_CONFIGURATION, (uint8_t*)®, 1);
+ ret = stts751_write_reg(ctx, STTS751_CONFIGURATION, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -400,8 +450,10 @@ int32_t stts751_pin_event_route_get(stmdev_ctx_t *ctx, uint8_t *val)
{
stts751_configuration_t reg;
int32_t ret;
- ret = stts751_read_reg(ctx, STTS751_CONFIGURATION, (uint8_t*)®, 1);
+
+ ret = stts751_read_reg(ctx, STTS751_CONFIGURATION, (uint8_t *)®, 1);
*val = reg.mask1;
+
return ret;
}
@@ -419,7 +471,7 @@ int32_t stts751_pin_event_route_get(stmdev_ctx_t *ctx, uint8_t *val)
*/
/**
- * @brief high temperature theshold.[set]
+ * @brief high temperature threshold.[set]
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
@@ -427,26 +479,21 @@ int32_t stts751_pin_event_route_get(stmdev_ctx_t *ctx, uint8_t *val)
*
*/
int32_t stts751_high_temperature_threshold_set(stmdev_ctx_t *ctx,
- int16_t buff)
+ int16_t val)
{
- uint8_t *temperature_ptr;
+ uint8_t buff[2];
int32_t ret;
- temperature_ptr = (uint8_t*)&buff;
- ret = stts751_write_reg(ctx, STTS751_TEMPERATURE_HIGH_LIMIT_LOW,
- (uint8_t*)temperature_ptr, 1);
-
- if (ret == 0) {
- temperature_ptr++;
- ret = stts751_write_reg(ctx, STTS751_TEMPERATURE_HIGH_LIMIT_HIGH,
- (uint8_t*)temperature_ptr, 1);
- }
+ buff[0] = (uint8_t)((uint16_t)val / 256U);
+ buff[1] = (uint8_t)((uint16_t)val - (buff[1] * 256U));
+ ret = stts751_write_reg(ctx, STTS751_TEMPERATURE_HIGH_LIMIT_HIGH,
+ buff, 2);
return ret;
}
/**
- * @brief high temperature theshold.[get]
+ * @brief high temperature threshold.[get]
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
@@ -454,26 +501,21 @@ int32_t stts751_high_temperature_threshold_set(stmdev_ctx_t *ctx,
*
*/
int32_t stts751_high_temperature_threshold_get(stmdev_ctx_t *ctx,
- int16_t *buff)
+ int16_t *val)
{
- uint16_t temperature;
- uint8_t temperature_low;
+ uint8_t buff[2];
int32_t ret;
- ret = stts751_read_reg(ctx, STTS751_TEMPERATURE_HIGH_LIMIT_HIGH,
- (uint8_t*)&temperature, 1);
- if (ret == 0) {
- ret = stts751_read_reg(ctx, STTS751_TEMPERATURE_HIGH_LIMIT_LOW,
- &temperature_low, 1);
+ ret = stts751_read_reg(ctx, STTS751_TEMPERATURE_HIGH_LIMIT_HIGH, buff,
+ 2);
+ *val = (int16_t)buff[0];
+ *val = (*val * 256) + (int16_t)buff[1];
- temperature = (temperature << 8) + temperature_low;
- *buff = (int16_t)temperature;
- }
return ret;
}
/**
- * @brief low temperature theshold.[set]
+ * @brief low temperature threshold.[set]
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
@@ -481,27 +523,21 @@ int32_t stts751_high_temperature_threshold_get(stmdev_ctx_t *ctx,
*
*/
int32_t stts751_low_temperature_threshold_set(stmdev_ctx_t *ctx,
- int16_t buff)
+ int16_t val)
{
-
- uint8_t *temperature_ptr;
+ uint8_t buff[2];
int32_t ret;
- temperature_ptr = (uint8_t*)&buff;
- ret = stts751_write_reg(ctx, STTS751_TEMPERATURE_LOW_LIMIT_LOW,
- (uint8_t*)temperature_ptr, 1);
-
- if (ret == 0) {
- temperature_ptr++;
- ret = stts751_write_reg(ctx, STTS751_TEMPERATURE_LOW_LIMIT_HIGH,
- (uint8_t*)temperature_ptr, 1);
- }
+ buff[0] = (uint8_t)((uint16_t)val / 256U);
+ buff[1] = (uint8_t)((uint16_t)val - (buff[1] * 256U));
+ ret = stts751_write_reg(ctx, STTS751_TEMPERATURE_LOW_LIMIT_HIGH, buff,
+ 2);
return ret;
}
/**
- * @brief low temperature theshold.[get]
+ * @brief low temperature threshold.[get]
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
@@ -509,21 +545,15 @@ int32_t stts751_low_temperature_threshold_set(stmdev_ctx_t *ctx,
*
*/
int32_t stts751_low_temperature_threshold_get(stmdev_ctx_t *ctx,
- int16_t *buff)
+ int16_t *val)
{
- uint16_t temperature;
- uint8_t temperature_low;
+ uint8_t buff[2];
int32_t ret;
- ret = stts751_read_reg(ctx, STTS751_TEMPERATURE_LOW_LIMIT_HIGH,
- (uint8_t*)&temperature, 1);
- if (ret == 0) {
- ret = stts751_read_reg(ctx, STTS751_TEMPERATURE_LOW_LIMIT_LOW,
- &temperature_low, 1);
-
- temperature = (temperature << 8) + temperature_low;
- *buff = (int16_t)temperature;
- }
+ ret = stts751_read_reg(ctx, STTS751_TEMPERATURE_LOW_LIMIT_HIGH, buff,
+ 2);
+ *val = (int16_t)buff[0];
+ *val = (*val * 256) + (int16_t)buff[1];
return ret;
}
@@ -533,8 +563,7 @@ int32_t stts751_low_temperature_threshold_get(stmdev_ctx_t *ctx,
*
*/
-
- /**
+/**
* @defgroup STTS751 over temperature alarm
* @brief This section groups all the functions that manage
* over temperature alarm functionality.
@@ -553,7 +582,9 @@ int32_t stts751_low_temperature_threshold_get(stmdev_ctx_t *ctx,
int32_t stts751_ota_thermal_limit_set(stmdev_ctx_t *ctx, int8_t val)
{
int32_t ret;
- ret = stts751_write_reg(ctx, STTS751_THERM_LIMIT, (uint8_t*)&val, 1);
+
+ ret = stts751_write_reg(ctx, STTS751_THERM_LIMIT, (uint8_t *)&val, 1);
+
return ret;
}
@@ -569,7 +600,8 @@ int32_t stts751_ota_thermal_limit_get(stmdev_ctx_t *ctx, int8_t *val)
{
int32_t ret;
- ret = stts751_read_reg(ctx, STTS751_THERM_LIMIT, (uint8_t*)val, 1);
+ ret = stts751_read_reg(ctx, STTS751_THERM_LIMIT, (uint8_t *)val, 1);
+
return ret;
}
@@ -586,7 +618,9 @@ int32_t stts751_ota_thermal_hyst_set(stmdev_ctx_t *ctx, int8_t val)
{
int32_t ret;
- ret = stts751_write_reg(ctx, STTS751_THERM_HYSTERESIS, (uint8_t*)&val, 1);
+ ret = stts751_write_reg(ctx, STTS751_THERM_HYSTERESIS,
+ (uint8_t *)&val, 1);
+
return ret;
}
@@ -603,7 +637,8 @@ int32_t stts751_ota_thermal_hyst_get(stmdev_ctx_t *ctx, int8_t *val)
{
int32_t ret;
- ret = stts751_read_reg(ctx, STTS751_THERM_HYSTERESIS, (uint8_t*)val, 1);
+ ret = stts751_read_reg(ctx, STTS751_THERM_HYSTERESIS, (uint8_t *)val, 1);
+
return ret;
}
@@ -633,11 +668,14 @@ int32_t stts751_smbus_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
stts751_smbus_timeout_t reg;
int32_t ret;
- ret = stts751_read_reg(ctx, STTS751_SMBUS_TIMEOUT,(uint8_t*)®, 1);
- if (ret == 0) {
+ ret = stts751_read_reg(ctx, STTS751_SMBUS_TIMEOUT, (uint8_t *)®, 1);
+
+ if (ret == 0)
+ {
reg.timeout = val;
- ret = stts751_write_reg(ctx, STTS751_SMBUS_TIMEOUT, (uint8_t*)®, 1);
+ ret = stts751_write_reg(ctx, STTS751_SMBUS_TIMEOUT, (uint8_t *)®, 1);
}
+
return ret;
}
@@ -654,8 +692,10 @@ int32_t stts751_smbus_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
{
stts751_smbus_timeout_t reg;
int32_t ret;
- ret = stts751_read_reg(ctx, STTS751_SMBUS_TIMEOUT, (uint8_t*)®, 1);
+
+ ret = stts751_read_reg(ctx, STTS751_SMBUS_TIMEOUT, (uint8_t *)®, 1);
*val = reg.timeout;
+
return ret;
}
@@ -670,16 +710,22 @@ int32_t stts751_smbus_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
int32_t stts751_device_id_get(stmdev_ctx_t *ctx, stts751_id_t *buff)
{
int32_t ret;
+
ret = stts751_read_reg(ctx, STTS751_PRODUCT_ID,
- (uint8_t*)&buff->product_id, 1);
- if (ret == 0){
- ret = stts751_read_reg(ctx, STTS751_MANUFACTURER_ID,
- (uint8_t*)&buff->manufacturer_id, 1);
+ (uint8_t *)&buff->product_id, 1);
+
+ if (ret == 0)
+ {
+ ret = stts751_read_reg(ctx, STTS751_MANUFACTURER_ID,
+ (uint8_t *)&buff->manufacturer_id, 1);
}
- if (ret == 0){
- ret = stts751_read_reg(ctx, STTS751_REVISION_ID,
- (uint8_t*)&buff->revision_id, 1);
+
+ if (ret == 0)
+ {
+ ret = stts751_read_reg(ctx, STTS751_REVISION_ID,
+ (uint8_t *)&buff->revision_id, 1);
}
+
return ret;
}
diff --git a/sensor/stmemsc/stts751_STdC/driver/stts751_reg.h b/sensor/stmemsc/stts751_STdC/driver/stts751_reg.h
index 70b960ec047e613570b08ca912a73aee1de88fe7..9e5318b2447b94478c329ea6c81c757fe769f16b 100644
--- a/sensor/stmemsc/stts751_STdC/driver/stts751_reg.h
+++ b/sensor/stmemsc/stts751_STdC/driver/stts751_reg.h
@@ -1,33 +1,34 @@
-/*
- ******************************************************************************
- * @file stts751_reg.h
- * @author Sensors Software Solution Team
- * @brief This file contains all the functions prototypes for the
- * stts751_reg.c driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+/**
+ ******************************************************************************
+ * @file stts751_reg.h
+ * @author Sensors Software Solution Team
+ * @brief This file contains all the functions prototypes for the
+ * stts751_reg.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STTS751_REGS_H
#define STTS751_REGS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include
+#include
#include
/** @addtogroup STTS751
@@ -35,6 +36,37 @@
*
*/
+/** @defgroup Endianness definitions
+ * @{
+ *
+ */
+
+#ifndef DRV_BYTE_ORDER
+#ifndef __BYTE_ORDER__
+
+#define DRV_LITTLE_ENDIAN 1234
+#define DRV_BIG_ENDIAN 4321
+
+/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
+ * by uncommenting the define which fits your platform endianness
+ */
+//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
+#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
+
+#else /* defined __BYTE_ORDER__ */
+
+#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
+#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
+#define DRV_BYTE_ORDER __BYTE_ORDER__
+
+#endif /* __BYTE_ORDER__*/
+#endif /* DRV_BYTE_ORDER */
+
+/**
+ * @}
+ *
+ */
+
/** @defgroup STMicroelectronics sensors common types
* @{
*
@@ -43,7 +75,9 @@
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
-typedef struct{
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
@@ -52,6 +86,16 @@ typedef struct{
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t bit7 : 1;
+ uint8_t bit6 : 1;
+ uint8_t bit5 : 1;
+ uint8_t bit4 : 1;
+ uint8_t bit3 : 1;
+ uint8_t bit2 : 1;
+ uint8_t bit1 : 1;
+ uint8_t bit0 : 1;
+#endif /* DRV_BYTE_ORDER */
} bitwise_t;
#define PROPERTY_DISABLE (0U)
@@ -65,10 +109,11 @@ typedef struct{
*
*/
-typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
-typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
-typedef struct {
+typedef struct
+{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
@@ -89,15 +134,16 @@ typedef struct {
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
- * You can create a sensor configuration by your own or using
- * Unico / Unicleo tools available on STMicroelectronics
- * web site.
+ * You can create a sensor configuration by your own or using
+ * Unico / Unicleo tools available on STMicroelectronics
+ * web site.
*
* @{
*
*/
-typedef struct {
+typedef struct
+{
uint8_t address;
uint8_t data;
} ucf_line_t;
@@ -146,28 +192,52 @@ typedef struct {
#define STTS751_TEMPERATURE_HIGH 0x00U
#define STTS751_STATUS 0x01U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t thrm : 1;
uint8_t not_used_01 : 4;
uint8_t t_low : 1;
uint8_t t_high : 1;
uint8_t busy : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t busy : 1;
+ uint8_t t_high : 1;
+ uint8_t t_low : 1;
+ uint8_t not_used_01 : 4;
+ uint8_t thrm : 1;
+#endif /* DRV_BYTE_ORDER */
} stts751_status_t;
#define STTS751_TEMPERATURE_LOW 0x02U
#define STTS751_CONFIGURATION 0x03U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t tres : 2;
uint8_t not_used_02 : 2;
uint8_t stop : 1;
uint8_t mask1 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t mask1 : 1;
+ uint8_t stop : 1;
+ uint8_t not_used_02 : 2;
+ uint8_t tres : 2;
+ uint8_t not_used_01 : 2;
+#endif /* DRV_BYTE_ORDER */
} stts751_configuration_t;
#define STTS751_CONVERSION_RATE 0x04U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t conv : 4;
uint8_t not_used_01 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t not_used_01 : 4;
+ uint8_t conv : 4;
+#endif /* DRV_BYTE_ORDER */
} stts751_conversion_rate_t;
#define STTS751_TEMPERATURE_HIGH_LIMIT_HIGH 0x05U
@@ -178,9 +248,15 @@ typedef struct {
#define STTS751_THERM_LIMIT 0x20U
#define STTS751_THERM_HYSTERESIS 0x21U
#define STTS751_SMBUS_TIMEOUT 0x22U
-typedef struct {
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 7;
uint8_t timeout : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+ uint8_t timeout : 1;
+ uint8_t not_used_01 : 7;
+#endif /* DRV_BYTE_ORDER */
} stts751_smbus_timeout_t;
#define STTS751_PRODUCT_ID 0xFDU
@@ -189,9 +265,9 @@ typedef struct {
/**
* @defgroup STTS751_Register_Union
- * @brief This union group all the registers that has a bitfield
+ * @brief This union group all the registers having a bit-field
* description.
- * This union is useful but not need by the driver.
+ * This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
@@ -199,7 +275,8 @@ typedef struct {
* @{
*
*/
-typedef union{
+typedef union
+{
stts751_status_t status;
stts751_configuration_t configuration;
stts751_conversion_rate_t conversion_rate;
@@ -213,15 +290,18 @@ typedef union{
*
*/
-int32_t stts751_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
+int32_t stts751_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
+ uint16_t len);
+int32_t stts751_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+ uint8_t *data,
uint16_t len);
-int32_t stts751_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
- uint16_t len);
-extern float stts751_from_lsb_to_celsius(int16_t lsb);
-extern int16_t stts751_from_celsius_to_lsb(float celsius);
+float_t stts751_from_lsb_to_celsius(int16_t lsb);
+int16_t stts751_from_celsius_to_lsb(float_t celsius);
-typedef enum {
+typedef enum
+{
STTS751_TEMP_ODR_OFF = 0x80,
STTS751_TEMP_ODR_ONE_SHOT = 0x90,
STTS751_TEMP_ODR_62mHz5 = 0x00,
@@ -235,37 +315,42 @@ typedef enum {
STTS751_TEMP_ODR_16Hz = 0x08, /* 9, 10, or 11-bit resolutions only */
STTS751_TEMP_ODR_32Hz = 0x09, /* 9 or 10-bit resolutions only */
} stts751_odr_t;
-int32_t stts751_temp_data_rate_set(stmdev_ctx_t *ctx, stts751_odr_t val);
-int32_t stts751_temp_data_rate_get(stmdev_ctx_t *ctx, stts751_odr_t *val);
+int32_t stts751_temp_data_rate_set(stmdev_ctx_t *ctx,
+ stts751_odr_t val);
+int32_t stts751_temp_data_rate_get(stmdev_ctx_t *ctx,
+ stts751_odr_t *val);
-typedef enum {
+typedef enum
+{
STTS751_9bit = 2,
STTS751_10bit = 0,
STTS751_11bit = 1,
STTS751_12bit = 3,
} stts751_tres_t;
int32_t stts751_resolution_set(stmdev_ctx_t *ctx, stts751_tres_t val);
-int32_t stts751_resolution_get(stmdev_ctx_t *ctx, stts751_tres_t *val);
+int32_t stts751_resolution_get(stmdev_ctx_t *ctx,
+ stts751_tres_t *val);
-int32_t stts751_status_reg_get(stmdev_ctx_t *ctx, stts751_status_t *val);
+int32_t stts751_status_reg_get(stmdev_ctx_t *ctx,
+ stts751_status_t *val);
int32_t stts751_flag_busy_get(stmdev_ctx_t *ctx, uint8_t *val);
-int32_t stts751_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff);
+int32_t stts751_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val);
int32_t stts751_pin_event_route_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t stts751_pin_event_route_get(stmdev_ctx_t *ctx, uint8_t *val);
int32_t stts751_high_temperature_threshold_set(stmdev_ctx_t *ctx,
- int16_t buff);
+ int16_t val);
int32_t stts751_high_temperature_threshold_get(stmdev_ctx_t *ctx,
- int16_t *buff);
+ int16_t *val);
int32_t stts751_low_temperature_threshold_set(stmdev_ctx_t *ctx,
- int16_t buff);
+ int16_t val);
int32_t stts751_low_temperature_threshold_get(stmdev_ctx_t *ctx,
- int16_t *buff);
+ int16_t *val);
int32_t stts751_ota_thermal_limit_set(stmdev_ctx_t *ctx, int8_t val);
int32_t stts751_ota_thermal_limit_get(stmdev_ctx_t *ctx, int8_t *val);
@@ -276,7 +361,8 @@ int32_t stts751_ota_thermal_hyst_get(stmdev_ctx_t *ctx, int8_t *val);
int32_t stts751_smbus_timeout_set(stmdev_ctx_t *ctx, uint8_t val);
int32_t stts751_smbus_timeout_get(stmdev_ctx_t *ctx, uint8_t *val);
-typedef struct {
+typedef struct
+{
uint8_t product_id;
uint8_t manufacturer_id;
uint8_t revision_id;