Commit 05fd4533 authored by Armando Visconti's avatar Armando Visconti
Browse files

sensor/stmemsc: Align stmemsc i/f to v2.8



Align stmemsc HAL i/f to v2.8

Signed-off-by: default avatarArmando Visconti <armando.visconti@st.com>
parent df625871
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+1 −0
Original line number Diff line number Diff line
@@ -78,6 +78,7 @@ set(stmems_pids
  lsm6dsv32x
  lsm6dsv
  lsm9ds1
  st1vafe3bx
  st1vafe6ax
  sths34pf80
  stts22h
+28 −30
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ Origin:
   https://www.st.com/en/embedded-software/c-driver-mems.html

Status:
   version v2.6
   version v2.8

Purpose:
   ST Microelectronics standard C platform-independent drivers for MEMS
@@ -25,7 +25,7 @@ Description:

   The driver is platform-independent, you only need to define the two
   functions for read and write transactions from the sensor hardware bus
   (ie. SPI or I2C). In addition you may define a mdelay (milliseconds) 
   (i.e. SPI or I2C/I3C). In addition you may define a mdelay (milliseconds)
   routine.

   Define in your 'xyz' driver code the read and write functions that use the
@@ -55,10 +55,10 @@ Description:
     - ais2ih_STdC          v2.0.1
     - ais328dq_STdC        v2.0.1
     - ais3624dq_STdC       v2.0.1
     - asm330lhb_STdC       v2.0.1
     - asm330lhbg1_STdC     v1.0.0
     - asm330lhh_STdC       v3.1.0
     - asm330lhhx_STdC      v2.0.0
     - asm330lhb_STdC       v2.1.0
     - asm330lhbg1_STdC     v1.1.0
     - asm330lhh_STdC       v3.2.0
     - asm330lhhx_STdC      v2.1.0
     - asm330lhhxg1_STdC    v2.0.1
     - h3lis100dl_STdC      v2.0.1
     - h3lis331dl_STdC      v2.0.1
@@ -71,11 +71,11 @@ Description:
     - iis328dq_STdC        v2.0.1
     - iis3dhhc_STdC        v2.0.1
     - iis3dwb_STdC         v2.0.1
     - ilps22qs_STdC        v3.1.0
     - ilps28qsw_STdC       v2.1.0
     - ilps22qs_STdC        v3.1.1
     - ilps28qsw_STdC       v2.2.0
     - ism303dac_STdC       v2.0.1
     - ism330bx_STdC        v3.0.0
     - ism330dhcx_STdC      v2.0.2
     - ism330bx_STdC        v3.0.1
     - ism330dhcx_STdC      v2.1.0
     - ism330dlc_STdC       v2.0.1
     - ism330is_STdC        v3.0.1
     - l3gd20h_STdC         v2.0.1
@@ -85,8 +85,8 @@ Description:
     - lis2ds12_STdC        v2.0.1
     - lis2dtw12_STdC       v2.0.1
     - lis2du12_STdC        v2.0.1
     - lis2dux12_STdC       v2.2.0
     - lis2duxs12_STdC      v2.2.0
     - lis2dux12_STdC       v2.3.0
     - lis2duxs12_STdC      v2.3.0
     - lis2dw12_STdC        v2.0.1
     - lis2hh12_STdC        v2.0.1
     - lis2mdl_STdC         v2.0.1
@@ -96,13 +96,13 @@ Description:
     - lis3dhh_STdC         v2.0.1
     - lis3mdl_STdC         v2.0.1
     - lps22ch_STdC         v2.0.1
     - lps22df_STdC         v2.1.0
     - lps22df_STdC         v2.2.0
     - lps22hb_STdC         v2.0.1
     - lps22hh_STdC         v3.0.1
     - lps25hb_STdC         v2.0.1
     - lps27hhtw_STdC       v2.0.1
     - lps27hhw_STdC        v2.0.1
     - lps28dfw_STdC        v2.1.0
     - lps28dfw_STdC        v2.2.0
     - lps33k_STdC          v2.0.1
     - lsm303agr_STdC       v2.0.1
     - lsm303ah_STdC        v2.0.1
@@ -110,19 +110,20 @@ Description:
     - lsm6dsl_STdC         v2.0.1
     - lsm6dsm_STdC         v2.0.1
     - lsm6dso16is_STdC     v3.0.1
     - lsm6dso32_STdC       v2.0.1
     - lsm6dso32x_STdC      v2.0.1
     - lsm6dso_STdC         v3.0.2
     - lsm6dsox_STdC        v3.0.1
     - lsm6dsr_STdC         v2.0.1
     - lsm6dsrx_STdC        v2.0.1
     - lsm6dso32_STdC       v2.1.0
     - lsm6dso32x_STdC      v2.1.0
     - lsm6dso_STdC         v3.1.0
     - lsm6dsox_STdC        v3.1.0
     - lsm6dsr_STdC         v2.1.0
     - lsm6dsrx_STdC        v2.1.0
     - lsm6dsv16b_STdC      v3.0.0
     - lsm6dsv16bx_STdC     v5.0.0
     - lsm6dsv16x_STdC      v4.0.0
     - lsm6dsv32x_STdC      v2.0.0
     - lsm6dsv_STdC         v3.0.0
     - lsm6dsv16bx_STdC     v5.0.1
     - lsm6dsv16x_STdC      v4.3.0
     - lsm6dsv32x_STdC      v2.3.0
     - lsm6dsv_STdC         v3.3.0
     - lsm9ds1_STdC         v2.0.1
     - st1vafe6ax_STdC      v2.0.0
     - st1vafe3bx_STdC      v2.0.0
     - st1vafe6ax_STdC      v2.0.1
     - sths34pf80_STdC      v3.0.1
     - stts22h_STdC         v2.1.0
     - stts751_STdC         v2.0.1
@@ -132,9 +133,10 @@ Dependencies:

URL:
   https://www.st.com/en/embedded-software/c-driver-mems.html
   https://github.com/STMicroelectronics/STMems_Standard_C_drivers/tree/v2.8

commit:
   version v2.3
   1609395 (tag v2.8)

Maintained-by:
   ST Microelectronics
@@ -144,7 +146,3 @@ License:

License Link:
   https://opensource.org/licenses/BSD-3-Clause

Patch List:
   * sensor: lsm6dso: Disable -Wmaybe-uninitialized for lsm6dso_mode_set
     - Modified sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.c
+54 −37
Original line number Diff line number Diff line
@@ -3254,6 +3254,7 @@ int32_t asm330lhb_pin_int1_route_set(const stmdev_ctx_t *ctx,
  {
    ret = asm330lhb_write_reg(ctx, ASM330LHB_MD1_CFG, (uint8_t *)&val->md1_cfg, 1);
  }

  if (ret == 0)
  {
    ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG1, (uint8_t *) &int_cfg1, 1);
@@ -4493,19 +4494,15 @@ int32_t asm330lhb_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val)
  asm330lhb_fifo_ctrl2_t fifo_ctrl2;
  int32_t ret;

  ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL2,
                           (uint8_t *)&fifo_ctrl2, 1);
  ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
  ret += asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);

  if (ret == 0)
  {
    fifo_ctrl1.wtm = (uint8_t)(val  & 0xFFU);
    fifo_ctrl2.wtm = (uint8_t)((val / 256U) & 0x01U);
    ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL2,
                              (uint8_t *)&fifo_ctrl2, 1);
  }
  if (ret == 0)
  {
    fifo_ctrl1.wtm = (uint8_t)(val - (fifo_ctrl2.wtm * 256U));
    ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL1,
                              (uint8_t *)&fifo_ctrl1, 1);
    ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
    ret += asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
  }

  return ret;
@@ -5170,26 +5167,25 @@ int32_t asm330lhb_batch_counter_threshold_get(const stmdev_ctx_t *ctx,
  * @brief  Number of unread sensor data (TAG + 6 bytes) stored in FIFO.[get]
  *
  * @param  ctx    Read / write interface definitions.(ptr)
  * @param  val    Change the values of diff_fifo in reg FIFO_STATUS1
  * @param  val    Read the value of diff_fifo in reg FIFO_STATUS1 and FIFO_STATUS2
  * @retval        Interface status (MANDATORY: return 0 -> no Error).
  *
  */
int32_t asm330lhb_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val)
{
  asm330lhb_fifo_status1_t fifo_status1;
  asm330lhb_fifo_status2_t fifo_status2;
  uint8_t reg[2];
  asm330lhb_fifo_status1_t *fifo_status1 = (asm330lhb_fifo_status1_t *)&reg[0];
  asm330lhb_fifo_status2_t *fifo_status2 = (asm330lhb_fifo_status2_t *)&reg[1];
  int32_t ret;

  ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS1,
                           (uint8_t *)&fifo_status1, 1);
  /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
  ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS1, (uint8_t *)reg, 2);
  if (ret == 0)
  {
    ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS2,
                             (uint8_t *)&fifo_status2, 1);

    *val = fifo_status2.diff_fifo;
    *val = (*val * 256U) + fifo_status1.diff_fifo;
    *val = fifo_status2->diff_fifo;
    *val = (*val * 256U) + fifo_status1->diff_fifo;
  }

  return ret;
}

@@ -5197,15 +5193,24 @@ int32_t asm330lhb_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val)
  * @brief  Smart FIFO status.[get]
  *
  * @param  ctx    Read / write interface definitions.(ptr)
  * @param  val    Registers FIFO_STATUS2
  * @param  val    Read registers FIFO_STATUS2
  * @retval        Interface status (MANDATORY: return 0 -> no Error).
  *
  */
int32_t asm330lhb_fifo_status_get(const stmdev_ctx_t *ctx,
                                  asm330lhb_fifo_status2_t *val)
{
  uint8_t reg[2];
  asm330lhb_fifo_status2_t *fifo_status2 = (asm330lhb_fifo_status2_t *)&reg[1];
  int32_t ret;
  ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS2, (uint8_t *)val, 1);

  /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
  ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS1, (uint8_t *)reg, 2);
  if (ret == 0)
  {
    *val = *fifo_status2;
  }

  return ret;
}

@@ -5213,18 +5218,22 @@ int32_t asm330lhb_fifo_status_get(const stmdev_ctx_t *ctx,
  * @brief  Smart FIFO full status.[get]
  *
  * @param  ctx    Read / write interface definitions.(ptr)
  * @param  val    Change the values of fifo_full_ia in reg FIFO_STATUS2
  * @param  val    Read the values of fifo_full_ia in reg FIFO_STATUS2
  * @retval        Interface status (MANDATORY: return 0 -> no Error).
  *
  */
int32_t asm330lhb_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
  asm330lhb_fifo_status2_t fifo_status2;
  uint8_t reg[2];
  asm330lhb_fifo_status2_t *fifo_status2 = (asm330lhb_fifo_status2_t *)&reg[1];
  int32_t ret;

  ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS2,
                           (uint8_t *)&fifo_status2, 1);
  *val = fifo_status2.fifo_full_ia;
  /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
  ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS1, (uint8_t *)reg, 2);
  if (ret == 0)
  {
    *val = fifo_status2->fifo_full_ia;
  }

  return ret;
}
@@ -5233,19 +5242,23 @@ int32_t asm330lhb_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
  * @brief  FIFO overrun status.[get]
  *
  * @param  ctx    Read / write interface definitions.(ptr)
  * @param  val    Change the values of  fifo_over_run_latched in
  * @param  val    Read the values of  fifo_over_run_latched in
  *                reg FIFO_STATUS2
  * @retval        Interface status (MANDATORY: return 0 -> no Error).
  *
  */
int32_t asm330lhb_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
  asm330lhb_fifo_status2_t fifo_status2;
  uint8_t reg[2];
  asm330lhb_fifo_status2_t *fifo_status2 = (asm330lhb_fifo_status2_t *)&reg[1];
  int32_t ret;

  ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS2,
                           (uint8_t *)&fifo_status2, 1);
  *val = fifo_status2. fifo_ovr_ia;
  /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
  ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS1, (uint8_t *)reg, 2);
  if (ret == 0)
  {
    *val = fifo_status2->fifo_ovr_ia;
  }

  return ret;
}
@@ -5254,18 +5267,22 @@ int32_t asm330lhb_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
  * @brief  FIFO watermark status.[get]
  *
  * @param  ctx    Read / write interface definitions.(ptr)
  * @param  val    Change the values of fifo_wtm_ia in reg FIFO_STATUS2
  * @param  val    Read the values of fifo_wtm_ia in reg FIFO_STATUS2
  * @retval        Interface status (MANDATORY: return 0 -> no Error).
  *
  */
int32_t asm330lhb_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
  asm330lhb_fifo_status2_t fifo_status2;
  uint8_t reg[2];
  asm330lhb_fifo_status2_t *fifo_status2 = (asm330lhb_fifo_status2_t *)&reg[1];
  int32_t ret;

  ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS2,
                           (uint8_t *)&fifo_status2, 1);
  *val = fifo_status2.fifo_wtm_ia;
  /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
  ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS1, (uint8_t *)reg, 2);
  if (ret == 0)
  {
    *val = fifo_status2->fifo_wtm_ia;
  }

  return ret;
}
+54 −37
Original line number Diff line number Diff line
@@ -3254,6 +3254,7 @@ int32_t asm330lhbg1_pin_int1_route_set(const stmdev_ctx_t *ctx,
  {
    ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_MD1_CFG, (uint8_t *)&val->md1_cfg, 1);
  }

  if (ret == 0)
  {
    ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_INT_CFG1, (uint8_t *) &int_cfg1, 1);
@@ -4493,19 +4494,15 @@ int32_t asm330lhbg1_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val)
  asm330lhbg1_fifo_ctrl2_t fifo_ctrl2;
  int32_t ret;

  ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_CTRL2,
                             (uint8_t *)&fifo_ctrl2, 1);
  ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
  ret += asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);

  if (ret == 0)
  {
    fifo_ctrl1.wtm = (uint8_t)(val  & 0xFFU);
    fifo_ctrl2.wtm = (uint8_t)((val / 256U) & 0x01U);
    ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FIFO_CTRL2,
                                (uint8_t *)&fifo_ctrl2, 1);
  }
  if (ret == 0)
  {
    fifo_ctrl1.wtm = (uint8_t)(val - (fifo_ctrl2.wtm * 256U));
    ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FIFO_CTRL1,
                                (uint8_t *)&fifo_ctrl1, 1);
    ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
    ret += asm330lhbg1_write_reg(ctx, ASM330LHBG1_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
  }

  return ret;
@@ -5170,26 +5167,25 @@ int32_t asm330lhbg1_batch_counter_threshold_get(const stmdev_ctx_t *ctx,
  * @brief  Number of unread sensor data (TAG + 6 bytes) stored in FIFO.[get]
  *
  * @param  ctx    Read / write interface definitions.(ptr)
  * @param  val    Change the values of diff_fifo in reg FIFO_STATUS1
  * @param  val    Read the value of diff_fifo in reg FIFO_STATUS1 and FIFO_STATUS2
  * @retval        Interface status (MANDATORY: return 0 -> no Error).
  *
  */
int32_t asm330lhbg1_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val)
{
  asm330lhbg1_fifo_status1_t fifo_status1;
  asm330lhbg1_fifo_status2_t fifo_status2;
  uint8_t reg[2];
  asm330lhbg1_fifo_status1_t *fifo_status1 = (asm330lhbg1_fifo_status1_t *)&reg[0];
  asm330lhbg1_fifo_status2_t *fifo_status2 = (asm330lhbg1_fifo_status2_t *)&reg[1];
  int32_t ret;

  ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_STATUS1,
                             (uint8_t *)&fifo_status1, 1);
  /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
  ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_STATUS1, (uint8_t *)reg, 2);
  if (ret == 0)
  {
    ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_STATUS2,
                               (uint8_t *)&fifo_status2, 1);

    *val = fifo_status2.diff_fifo;
    *val = (*val * 256U) + fifo_status1.diff_fifo;
    *val = fifo_status2->diff_fifo;
    *val = (*val * 256U) + fifo_status1->diff_fifo;
  }

  return ret;
}

@@ -5197,15 +5193,24 @@ int32_t asm330lhbg1_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val)
  * @brief  Smart FIFO status.[get]
  *
  * @param  ctx    Read / write interface definitions.(ptr)
  * @param  val    Registers FIFO_STATUS2
  * @param  val    Read registers FIFO_STATUS2
  * @retval        Interface status (MANDATORY: return 0 -> no Error).
  *
  */
int32_t asm330lhbg1_fifo_status_get(const stmdev_ctx_t *ctx,
                                    asm330lhbg1_fifo_status2_t *val)
{
  uint8_t reg[2];
  asm330lhbg1_fifo_status2_t *fifo_status2 = (asm330lhbg1_fifo_status2_t *)&reg[1];
  int32_t ret;
  ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_STATUS2, (uint8_t *)val, 1);

  /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
  ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_STATUS1, (uint8_t *)reg, 2);
  if (ret == 0)
  {
    *val = *fifo_status2;
  }

  return ret;
}

@@ -5213,18 +5218,22 @@ int32_t asm330lhbg1_fifo_status_get(const stmdev_ctx_t *ctx,
  * @brief  Smart FIFO full status.[get]
  *
  * @param  ctx    Read / write interface definitions.(ptr)
  * @param  val    Change the values of fifo_full_ia in reg FIFO_STATUS2
  * @param  val    Read the values of fifo_full_ia in reg FIFO_STATUS2
  * @retval        Interface status (MANDATORY: return 0 -> no Error).
  *
  */
int32_t asm330lhbg1_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
  asm330lhbg1_fifo_status2_t fifo_status2;
  uint8_t reg[2];
  asm330lhbg1_fifo_status2_t *fifo_status2 = (asm330lhbg1_fifo_status2_t *)&reg[1];
  int32_t ret;

  ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_STATUS2,
                             (uint8_t *)&fifo_status2, 1);
  *val = fifo_status2.fifo_full_ia;
  /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
  ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_STATUS1, (uint8_t *)reg, 2);
  if (ret == 0)
  {
    *val = fifo_status2->fifo_full_ia;
  }

  return ret;
}
@@ -5233,19 +5242,23 @@ int32_t asm330lhbg1_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
  * @brief  FIFO overrun status.[get]
  *
  * @param  ctx    Read / write interface definitions.(ptr)
  * @param  val    Change the values of  fifo_over_run_latched in
  * @param  val    Read the values of  fifo_over_run_latched in
  *                reg FIFO_STATUS2
  * @retval        Interface status (MANDATORY: return 0 -> no Error).
  *
  */
int32_t asm330lhbg1_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
  asm330lhbg1_fifo_status2_t fifo_status2;
  uint8_t reg[2];
  asm330lhbg1_fifo_status2_t *fifo_status2 = (asm330lhbg1_fifo_status2_t *)&reg[1];
  int32_t ret;

  ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_STATUS2,
                             (uint8_t *)&fifo_status2, 1);
  *val = fifo_status2. fifo_ovr_ia;
  /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
  ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_STATUS1, (uint8_t *)reg, 2);
  if (ret == 0)
  {
    *val = fifo_status2->fifo_ovr_ia;
  }

  return ret;
}
@@ -5254,18 +5267,22 @@ int32_t asm330lhbg1_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
  * @brief  FIFO watermark status.[get]
  *
  * @param  ctx    Read / write interface definitions.(ptr)
  * @param  val    Change the values of fifo_wtm_ia in reg FIFO_STATUS2
  * @param  val    Read the values of fifo_wtm_ia in reg FIFO_STATUS2
  * @retval        Interface status (MANDATORY: return 0 -> no Error).
  *
  */
int32_t asm330lhbg1_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
  asm330lhbg1_fifo_status2_t fifo_status2;
  uint8_t reg[2];
  asm330lhbg1_fifo_status2_t *fifo_status2 = (asm330lhbg1_fifo_status2_t *)&reg[1];
  int32_t ret;

  ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_STATUS2,
                             (uint8_t *)&fifo_status2, 1);
  *val = fifo_status2.fifo_wtm_ia;
  /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
  ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_STATUS1, (uint8_t *)reg, 2);
  if (ret == 0)
  {
    *val = fifo_status2->fifo_wtm_ia;
  }

  return ret;
}
+245 −657

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