Loading .devcontainer/ubuntu-22.04/vcpkg-configuration.json +4 −9 Original line number Diff line number Diff line { "registries": [ { "kind": "artifact", "location": "https://aka.ms/vcpkg-ce-default", "name": "microsoft" }, { "kind": "artifact", "location": "https://artifacts.keil.arm.com/vcpkg-ce-registry/registry.zip", Loading @@ -12,13 +7,13 @@ } ], "requires": { "microsoft:tools/kitware/cmake": "^3.25.2", "microsoft:ninja": "^1.10.2", "arm:compilers/arm/armclang":"^6.20.0", "arm:tools/kitware/cmake": "^3.25.2", "arm:ninja": "^1.10.2", "arm:compilers/arm/armclang":"^6.22.0", "arm:compilers/arm/arm-none-eabi-gcc": "^13.2.1", "arm:compilers/arm/llvm-embedded": "^17.0.1-0", "arm:tools/open-cmsis-pack/cmsis-toolbox": "^2.1.0-0", "arm:models/arm/avh-fvp": "^11.22.39", "arm:models/arm/avh-fvp": "11.22.39", "arm:debuggers/arm/armdbg": "^6.0.0" } } CMSIS/CoreValidation/Layer/App/Validation_Cortex-M/App.clayer.yml +3 −0 Original line number Diff line number Diff line Loading @@ -55,6 +55,9 @@ layer: - +CM35P - +CM35PS - +CM35PNS - +CM52 - +CM52S - +CM52NS - +CM55 - +CM55S - +CM55NS Loading CMSIS/CoreValidation/Layer/Target/CM52/RTE/Device/ARMCM52/ac6_linker_script.sct 0 → 100644 +108 −0 Original line number Diff line number Diff line /* * Copyright (c) 2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE 8 #else #define __STACKSEAL_SIZE 0 #endif /*---------------------------------------------------------------------------- Scatter File Definitions definition *----------------------------------------------------------------------------*/ LR_ROM0 __ROM0_BASE __ROM0_SIZE { ER_ROM0 __ROM0_BASE __ROM0_SIZE { *.o (RESET, +First) *(InRoot$$Sections) *(+RO +XO) } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) ER_CMSE_VENEER AlignExpr(+0, 32) (__ROM0_SIZE - AlignExpr(ImageLength(ER_ROM0), 32)) { *(Veneer$$CMSE) } #endif RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) { *(.bss.noinit) } RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { *(+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP (AlignExpr(+0, 8)) EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE { ; Reserve empty region for stack } #if __STACKSEAL_SIZE > 0 STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack } #endif #if __RAM1_SIZE > 0 RW_RAM1 __RAM1_BASE __RAM1_SIZE { .ANY (+RW +ZI) } #endif #if __RAM2_SIZE > 0 RW_RAM2 __RAM2_BASE __RAM2_SIZE { .ANY (+RW +ZI) } #endif #if __RAM3_SIZE > 0 RW_RAM3 __RAM3_BASE __RAM3_SIZE { .ANY (+RW +ZI) } #endif } #if __ROM1_SIZE > 0 LR_ROM1 __ROM1_BASE __ROM1_SIZE { ER_ROM1 +0 __ROM1_SIZE { .ANY (+RO +XO) } } #endif #if __ROM2_SIZE > 0 LR_ROM2 __ROM2_BASE __ROM2_SIZE { ER_ROM2 +0 __ROM2_SIZE { .ANY (+RO +XO) } } #endif #if __ROM3_SIZE > 0 LR_ROM3 __ROM3_BASE __ROM3_SIZE { ER_ROM3 +0 __ROM3_SIZE { .ANY (+RO +XO) } } #endif CMSIS/CoreValidation/Layer/Target/CM52/RTE/Device/ARMCM52/clang_linker_script.ld 0 → 100644 +361 −0 Original line number Diff line number Diff line /* * SPDX-License-Identifier: BSD-3-Clause * * Copyright © 2019 Keith Packard * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials provided * with the distribution. * * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. */ /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE ( 8 ) #else #define __STACKSEAL_SIZE ( 0 ) #endif /* ---------------------------------------------------------------------------- Memory definition *----------------------------------------------------------------------------*/ MEMORY { ROM0 (rx!w) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE #if __ROM1_SIZE > 0 ROM1 (rx!w) : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE #endif #if __ROM2_SIZE > 0 ROM2 (rx!w) : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE #endif #if __ROM3_SIZE > 0 ROM3 (rx!w) : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE #endif RAM0 (w!rx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE #if __RAM1_SIZE > 0 RAM1 (w!rx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE #endif #if __RAM2_SIZE > 0 RAM2 (w!rx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE #endif #if __RAM3_SIZE > 0 RAM3 (w!rx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE #endif } ENTRY(Reset_Handler) PHDRS { text PT_LOAD; ram PT_LOAD; ram_init PT_LOAD; tls PT_TLS; } SECTIONS { .init : { KEEP (*(.vectors)) KEEP (*(.text.init.enter)) KEEP (*(.data.init.enter)) KEEP (*(SORT_BY_NAME(.init) SORT_BY_NAME(.init.*))) } >ROM0 AT>ROM0 :text .text : { /* code */ *(.text.unlikely .text.unlikely.*) *(.text.startup .text.startup.*) *(.text .text.* .opd .opd.*) *(.gnu.linkonce.t.*) KEEP (*(.fini .fini.*)) __text_end = .; PROVIDE (__etext = __text_end); PROVIDE (_etext = __text_end); PROVIDE (etext = __text_end); /* read-only data */ *(.rdata) *(.rodata .rodata.*) *(.gnu.linkonce.r.*) *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) *(.data.rel.ro .data.rel.ro.*) *(.got .got.*) /* Need to pre-align so that the symbols come after padding */ . = ALIGN(8); /* lists of constructors and destructors */ PROVIDE_HIDDEN ( __preinit_array_start = . ); KEEP (*(.preinit_array)) PROVIDE_HIDDEN ( __preinit_array_end = . ); PROVIDE_HIDDEN ( __init_array_start = . ); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array .ctors)) PROVIDE_HIDDEN ( __init_array_end = . ); PROVIDE_HIDDEN ( __fini_array_start = . ); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array .dtors)) PROVIDE_HIDDEN ( __fini_array_end = . ); } >ROM0 AT>ROM0 :text #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) .veneers : { . = ALIGN(32); KEEP(*(.gnu.sgstubs)) } > ROM0 AT>ROM0 :text #endif .toc : { *(.toc .toc.*) } >ROM0 AT>ROM0 :text /* additional sections when compiling with C++ exception support */ .except_ordered : { *(.gcc_except_table *.gcc_except_table.*) KEEP (*(.eh_frame .eh_frame.*)) *(.ARM.extab* .gnu.linkonce.armextab.*) } >ROM0 AT>ROM0 :text .except_unordered : { . = ALIGN(8); PROVIDE(__exidx_start = .); *(.ARM.exidx*) PROVIDE(__exidx_end = .); } >ROM0 AT>ROM0 :text /* * Data values which are preserved across reset */ .preserve (NOLOAD) : { PROVIDE(__preserve_start__ = .); KEEP(*(SORT_BY_NAME(.preserve.*))) KEEP(*(.preserve)) PROVIDE(__preserve_end__ = .); } >RAM0 AT>RAM0 :ram .data : { *(.data .data.*) *(.gnu.linkonce.d.*) /* Need to pre-align so that the symbols come after padding */ . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.* .sdata2.*) *(.gnu.linkonce.s.*) } >RAM0 AT>ROM0 :ram_init PROVIDE(__data_start = ADDR(.data)); PROVIDE(__data_source = LOADADDR(.data)); /* Thread local initialized data. This gets * space allocated as it is expected to be placed * in ram to be used as a template for TLS data blocks * allocated at runtime. We're slightly abusing that * by placing the data in flash where it will be copied * into the allocate ram addresses by the existing * data initialization code in crt0 */ .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) PROVIDE(__data_end = .); PROVIDE(__tdata_end = .); } >RAM0 AT>ROM0 :tls :ram_init PROVIDE( __tls_base = ADDR(.tdata)); PROVIDE( __tdata_start = ADDR(.tdata)); PROVIDE( __tdata_source = LOADADDR(.tdata) ); PROVIDE( __tdata_source_end = LOADADDR(.tdata) + SIZEOF(.tdata) ); PROVIDE( __data_source_end = __tdata_source_end ); PROVIDE( __tdata_size = SIZEOF(.tdata) ); PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); PROVIDE( __edata = __data_end ); PROVIDE( _edata = __data_end ); PROVIDE( edata = __data_end ); PROVIDE( __data_size = __data_end - __data_start ); PROVIDE( __data_source_size = __data_source_end - __data_source ); .tbss (NOLOAD) : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) PROVIDE( __tls_end = . ); PROVIDE( __tbss_end = . ); } >RAM0 AT>RAM0 :tls :ram PROVIDE( __bss_start = ADDR(.tbss)); PROVIDE( __tbss_start = ADDR(.tbss)); PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); PROVIDE( __tbss_size = SIZEOF(.tbss) ); PROVIDE( __tls_size = __tls_end - __tls_base ); PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); /* * The linker special cases .tbss segments which are * identified as segments which are not loaded and are * thread_local. * * For these segments, the linker does not advance 'dot' * across them. We actually need memory allocated for tbss, * so we create a special segment here just to make room */ /* .tbss_space (NOLOAD) : { . = ADDR(.tbss); . = . + SIZEOF(.tbss); } >RAM0 AT>RAM0 :ram */ .bss (NOLOAD) : { *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss .bss.*) *(.gnu.linkonce.b.*) *(COMMON) /* Align the heap */ . = ALIGN(8); __bss_end = .; } >RAM0 AT>RAM0 :ram PROVIDE( __non_tls_bss_start = ADDR(.bss) ); PROVIDE( __end = __bss_end ); PROVIDE( _end = __bss_end ); PROVIDE( end = __bss_end ); PROVIDE( __bss_size = __bss_end - __bss_start ); /* Make the rest of memory available for heap storage */ PROVIDE (__heap_start = __end); #ifdef __HEAP_SIZE PROVIDE (__heap_end = __heap_start + __HEAP_SIZE); PROVIDE (__heap_size = __HEAP_SIZE); #else PROVIDE (__heap_end = __stack - __STACK_SIZE); PROVIDE (__heap_size = __heap_end - __heap_start); #endif .heap (NOLOAD) : { . += __heap_size; } >RAM0 :ram /* Define a stack region to make sure it fits in memory */ PROVIDE(__stack = ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE); PROVIDE(__stack_limit = __stack - __STACK_SIZE); .stack (__stack_limit) (NOLOAD) : { . += __STACK_SIZE; } >RAM0 :ram #if __STACKSEAL_SIZE > 0 PROVIDE(__stack_seal = __stack); .stackseal (__stack) (NOLOAD) : { . += __STACKSEAL_SIZE; } >RAM0 :ram #endif /* Throw away C++ exception handling information */ /* /DISCARD/ : { *(.note .note.*) *(.eh_frame .eh_frame.*) *(.ARM.extab* .gnu.linkonce.armextab.*) *(.ARM.exidx*) } */ /* Stabs debugging sections. */ .stab 0 : { *(.stab) } .stabstr 0 : { *(.stabstr) } .stab.excl 0 : { *(.stab.excl) } .stab.exclstr 0 : { *(.stab.exclstr) } .stab.index 0 : { *(.stab.index) } .stab.indexstr 0 : { *(.stab.indexstr) } .comment 0 : { *(.comment) } .gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) } /* DWARF debug sections. Symbols in the DWARF debugging sections are relative to the beginning of the section so we begin them at 0. */ /* DWARF 1. */ .debug 0 : { *(.debug) } .line 0 : { *(.line) } /* GNU DWARF 1 extensions. */ .debug_srcinfo 0 : { *(.debug_srcinfo) } .debug_sfnames 0 : { *(.debug_sfnames) } /* DWARF 1.1 and DWARF 2. */ .debug_aranges 0 : { *(.debug_aranges) } .debug_pubnames 0 : { *(.debug_pubnames) } /* DWARF 2. */ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } .debug_abbrev 0 : { *(.debug_abbrev) } .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end) } .debug_frame 0 : { *(.debug_frame) } .debug_str 0 : { *(.debug_str) } .debug_loc 0 : { *(.debug_loc) } .debug_macinfo 0 : { *(.debug_macinfo) } /* SGI/MIPS DWARF 2 extensions. */ .debug_weaknames 0 : { *(.debug_weaknames) } .debug_funcnames 0 : { *(.debug_funcnames) } .debug_typenames 0 : { *(.debug_typenames) } .debug_varnames 0 : { *(.debug_varnames) } /* DWARF 3. */ .debug_pubtypes 0 : { *(.debug_pubtypes) } .debug_ranges 0 : { *(.debug_ranges) } /* DWARF 5. */ .debug_addr 0 : { *(.debug_addr) } .debug_line_str 0 : { *(.debug_line_str) } .debug_loclists 0 : { *(.debug_loclists) } .debug_macro 0 : { *(.debug_macro) } .debug_names 0 : { *(.debug_names) } .debug_rnglists 0 : { *(.debug_rnglists) } .debug_str_offsets 0 : { *(.debug_str_offsets) } .debug_sup 0 : { *(.debug_sup) } .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) } } /* * Check that sections that are copied from flash to RAM have matching * padding, so that a single memcpy() of __data_size copies the correct bytes. */ ASSERT( __data_size == __data_source_size, "ERROR: .data/.tdata flash size does not match RAM size"); CMSIS/CoreValidation/Layer/Target/CM52/RTE/Device/ARMCM52/gcc_linker_script.ld 0 → 100644 +294 −0 Original line number Diff line number Diff line /* * Copyright (c) 2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE ( 8 ) #else #define __STACKSEAL_SIZE ( 0 ) #endif /* ---------------------------------------------------------------------------- Memory definition *----------------------------------------------------------------------------*/ MEMORY { ROM0 (rx) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE #if __ROM1_SIZE > 0 ROM1 (rx) : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE #endif #if __ROM2_SIZE > 0 ROM2 (rx) : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE #endif #if __ROM3_SIZE > 0 ROM3 (rx) : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE #endif RAM0 (rwx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE #if __RAM1_SIZE > 0 RAM1 (rwx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE #endif #if __RAM2_SIZE > 0 RAM2 (rwx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE #endif #if __RAM3_SIZE > 0 RAM3 (rwx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE #endif } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext (deprecated) * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack */ ENTRY(Reset_Handler) SECTIONS { .text : { KEEP(*(.vectors)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) } > ROM0 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) .gnu.sgstubs : { . = ALIGN(32); } > ROM0 #endif .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > ROM0 __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > ROM0 __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (LOADADDR(.data)) LONG (ADDR(.data)) LONG (SIZEOF(.data) / 4) /* Add each additional data section here */ /* LONG (LOADADDR(.data2)) LONG (ADDR(.data2)) LONG (SIZEOF(.data2) / 4) */ __copy_table_end__ = .; } > ROM0 .zero.table : { . = ALIGN(4); __zero_table_start__ = .; /* .bss initialization to zero is already done during C Run-Time Startup. LONG (ADDR(.bss)) LONG (SIZEOF(.bss) / 4) */ /* Add each additional bss section here */ /* LONG (ADDR(.bss2)) LONG (SIZEOF(.bss2) / 4) */ __zero_table_end__ = .; } > ROM0 /* * This __etext variable is kept for backward compatibility with older, * ASM based startup files. */ PROVIDE(__etext = LOADADDR(.data)); .data : ALIGN(4) { __data_start__ = .; *(vtable) *(.data) *(.data.*) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM0 AT > ROM0 /* * Secondary data section, optional * * Remember to add each additional data section * to the .copy.table above to assure proper * initialization during startup. */ /* .data2 : ALIGN(4) { . = ALIGN(4); __data2_start__ = .; *(.data2) *(.data2.*) . = ALIGN(4); __data2_end__ = .; } > RAM1 AT > ROM0 */ .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM0 AT > RAM0 /* * Secondary bss section, optional * * Remember to add each additional bss section * to the .zero.table above to assure proper * initialization during startup. */ /* .bss2 : { . = ALIGN(4); __bss2_start__ = .; *(.bss2) *(.bss2.*) . = ALIGN(4); __bss2_end__ = .; } > RAM1 AT > RAM1 */ .heap (NOLOAD) : { . = ALIGN(8); __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; } > RAM0 .stack (ORIGIN(RAM0) + LENGTH(RAM0) - __STACK_SIZE - __STACKSEAL_SIZE) (NOLOAD) : { . = ALIGN(8); __StackLimit = .; . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; } > RAM0 PROVIDE(__stack = __StackTop); #if __STACKSEAL_SIZE > 0 .stackseal (ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE) (NOLOAD) : { . = ALIGN(8); __StackSeal = .; . = . + 8; . = ALIGN(8); } > RAM0 #endif /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } Loading
.devcontainer/ubuntu-22.04/vcpkg-configuration.json +4 −9 Original line number Diff line number Diff line { "registries": [ { "kind": "artifact", "location": "https://aka.ms/vcpkg-ce-default", "name": "microsoft" }, { "kind": "artifact", "location": "https://artifacts.keil.arm.com/vcpkg-ce-registry/registry.zip", Loading @@ -12,13 +7,13 @@ } ], "requires": { "microsoft:tools/kitware/cmake": "^3.25.2", "microsoft:ninja": "^1.10.2", "arm:compilers/arm/armclang":"^6.20.0", "arm:tools/kitware/cmake": "^3.25.2", "arm:ninja": "^1.10.2", "arm:compilers/arm/armclang":"^6.22.0", "arm:compilers/arm/arm-none-eabi-gcc": "^13.2.1", "arm:compilers/arm/llvm-embedded": "^17.0.1-0", "arm:tools/open-cmsis-pack/cmsis-toolbox": "^2.1.0-0", "arm:models/arm/avh-fvp": "^11.22.39", "arm:models/arm/avh-fvp": "11.22.39", "arm:debuggers/arm/armdbg": "^6.0.0" } }
CMSIS/CoreValidation/Layer/App/Validation_Cortex-M/App.clayer.yml +3 −0 Original line number Diff line number Diff line Loading @@ -55,6 +55,9 @@ layer: - +CM35P - +CM35PS - +CM35PNS - +CM52 - +CM52S - +CM52NS - +CM55 - +CM55S - +CM55NS Loading
CMSIS/CoreValidation/Layer/Target/CM52/RTE/Device/ARMCM52/ac6_linker_script.sct 0 → 100644 +108 −0 Original line number Diff line number Diff line /* * Copyright (c) 2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE 8 #else #define __STACKSEAL_SIZE 0 #endif /*---------------------------------------------------------------------------- Scatter File Definitions definition *----------------------------------------------------------------------------*/ LR_ROM0 __ROM0_BASE __ROM0_SIZE { ER_ROM0 __ROM0_BASE __ROM0_SIZE { *.o (RESET, +First) *(InRoot$$Sections) *(+RO +XO) } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) ER_CMSE_VENEER AlignExpr(+0, 32) (__ROM0_SIZE - AlignExpr(ImageLength(ER_ROM0), 32)) { *(Veneer$$CMSE) } #endif RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) { *(.bss.noinit) } RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { *(+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP (AlignExpr(+0, 8)) EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE { ; Reserve empty region for stack } #if __STACKSEAL_SIZE > 0 STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack } #endif #if __RAM1_SIZE > 0 RW_RAM1 __RAM1_BASE __RAM1_SIZE { .ANY (+RW +ZI) } #endif #if __RAM2_SIZE > 0 RW_RAM2 __RAM2_BASE __RAM2_SIZE { .ANY (+RW +ZI) } #endif #if __RAM3_SIZE > 0 RW_RAM3 __RAM3_BASE __RAM3_SIZE { .ANY (+RW +ZI) } #endif } #if __ROM1_SIZE > 0 LR_ROM1 __ROM1_BASE __ROM1_SIZE { ER_ROM1 +0 __ROM1_SIZE { .ANY (+RO +XO) } } #endif #if __ROM2_SIZE > 0 LR_ROM2 __ROM2_BASE __ROM2_SIZE { ER_ROM2 +0 __ROM2_SIZE { .ANY (+RO +XO) } } #endif #if __ROM3_SIZE > 0 LR_ROM3 __ROM3_BASE __ROM3_SIZE { ER_ROM3 +0 __ROM3_SIZE { .ANY (+RO +XO) } } #endif
CMSIS/CoreValidation/Layer/Target/CM52/RTE/Device/ARMCM52/clang_linker_script.ld 0 → 100644 +361 −0 Original line number Diff line number Diff line /* * SPDX-License-Identifier: BSD-3-Clause * * Copyright © 2019 Keith Packard * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials provided * with the distribution. * * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. */ /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE ( 8 ) #else #define __STACKSEAL_SIZE ( 0 ) #endif /* ---------------------------------------------------------------------------- Memory definition *----------------------------------------------------------------------------*/ MEMORY { ROM0 (rx!w) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE #if __ROM1_SIZE > 0 ROM1 (rx!w) : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE #endif #if __ROM2_SIZE > 0 ROM2 (rx!w) : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE #endif #if __ROM3_SIZE > 0 ROM3 (rx!w) : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE #endif RAM0 (w!rx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE #if __RAM1_SIZE > 0 RAM1 (w!rx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE #endif #if __RAM2_SIZE > 0 RAM2 (w!rx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE #endif #if __RAM3_SIZE > 0 RAM3 (w!rx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE #endif } ENTRY(Reset_Handler) PHDRS { text PT_LOAD; ram PT_LOAD; ram_init PT_LOAD; tls PT_TLS; } SECTIONS { .init : { KEEP (*(.vectors)) KEEP (*(.text.init.enter)) KEEP (*(.data.init.enter)) KEEP (*(SORT_BY_NAME(.init) SORT_BY_NAME(.init.*))) } >ROM0 AT>ROM0 :text .text : { /* code */ *(.text.unlikely .text.unlikely.*) *(.text.startup .text.startup.*) *(.text .text.* .opd .opd.*) *(.gnu.linkonce.t.*) KEEP (*(.fini .fini.*)) __text_end = .; PROVIDE (__etext = __text_end); PROVIDE (_etext = __text_end); PROVIDE (etext = __text_end); /* read-only data */ *(.rdata) *(.rodata .rodata.*) *(.gnu.linkonce.r.*) *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) *(.data.rel.ro .data.rel.ro.*) *(.got .got.*) /* Need to pre-align so that the symbols come after padding */ . = ALIGN(8); /* lists of constructors and destructors */ PROVIDE_HIDDEN ( __preinit_array_start = . ); KEEP (*(.preinit_array)) PROVIDE_HIDDEN ( __preinit_array_end = . ); PROVIDE_HIDDEN ( __init_array_start = . ); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array .ctors)) PROVIDE_HIDDEN ( __init_array_end = . ); PROVIDE_HIDDEN ( __fini_array_start = . ); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array .dtors)) PROVIDE_HIDDEN ( __fini_array_end = . ); } >ROM0 AT>ROM0 :text #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) .veneers : { . = ALIGN(32); KEEP(*(.gnu.sgstubs)) } > ROM0 AT>ROM0 :text #endif .toc : { *(.toc .toc.*) } >ROM0 AT>ROM0 :text /* additional sections when compiling with C++ exception support */ .except_ordered : { *(.gcc_except_table *.gcc_except_table.*) KEEP (*(.eh_frame .eh_frame.*)) *(.ARM.extab* .gnu.linkonce.armextab.*) } >ROM0 AT>ROM0 :text .except_unordered : { . = ALIGN(8); PROVIDE(__exidx_start = .); *(.ARM.exidx*) PROVIDE(__exidx_end = .); } >ROM0 AT>ROM0 :text /* * Data values which are preserved across reset */ .preserve (NOLOAD) : { PROVIDE(__preserve_start__ = .); KEEP(*(SORT_BY_NAME(.preserve.*))) KEEP(*(.preserve)) PROVIDE(__preserve_end__ = .); } >RAM0 AT>RAM0 :ram .data : { *(.data .data.*) *(.gnu.linkonce.d.*) /* Need to pre-align so that the symbols come after padding */ . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.* .sdata2.*) *(.gnu.linkonce.s.*) } >RAM0 AT>ROM0 :ram_init PROVIDE(__data_start = ADDR(.data)); PROVIDE(__data_source = LOADADDR(.data)); /* Thread local initialized data. This gets * space allocated as it is expected to be placed * in ram to be used as a template for TLS data blocks * allocated at runtime. We're slightly abusing that * by placing the data in flash where it will be copied * into the allocate ram addresses by the existing * data initialization code in crt0 */ .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) PROVIDE(__data_end = .); PROVIDE(__tdata_end = .); } >RAM0 AT>ROM0 :tls :ram_init PROVIDE( __tls_base = ADDR(.tdata)); PROVIDE( __tdata_start = ADDR(.tdata)); PROVIDE( __tdata_source = LOADADDR(.tdata) ); PROVIDE( __tdata_source_end = LOADADDR(.tdata) + SIZEOF(.tdata) ); PROVIDE( __data_source_end = __tdata_source_end ); PROVIDE( __tdata_size = SIZEOF(.tdata) ); PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); PROVIDE( __edata = __data_end ); PROVIDE( _edata = __data_end ); PROVIDE( edata = __data_end ); PROVIDE( __data_size = __data_end - __data_start ); PROVIDE( __data_source_size = __data_source_end - __data_source ); .tbss (NOLOAD) : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) PROVIDE( __tls_end = . ); PROVIDE( __tbss_end = . ); } >RAM0 AT>RAM0 :tls :ram PROVIDE( __bss_start = ADDR(.tbss)); PROVIDE( __tbss_start = ADDR(.tbss)); PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); PROVIDE( __tbss_size = SIZEOF(.tbss) ); PROVIDE( __tls_size = __tls_end - __tls_base ); PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); /* * The linker special cases .tbss segments which are * identified as segments which are not loaded and are * thread_local. * * For these segments, the linker does not advance 'dot' * across them. We actually need memory allocated for tbss, * so we create a special segment here just to make room */ /* .tbss_space (NOLOAD) : { . = ADDR(.tbss); . = . + SIZEOF(.tbss); } >RAM0 AT>RAM0 :ram */ .bss (NOLOAD) : { *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss .bss.*) *(.gnu.linkonce.b.*) *(COMMON) /* Align the heap */ . = ALIGN(8); __bss_end = .; } >RAM0 AT>RAM0 :ram PROVIDE( __non_tls_bss_start = ADDR(.bss) ); PROVIDE( __end = __bss_end ); PROVIDE( _end = __bss_end ); PROVIDE( end = __bss_end ); PROVIDE( __bss_size = __bss_end - __bss_start ); /* Make the rest of memory available for heap storage */ PROVIDE (__heap_start = __end); #ifdef __HEAP_SIZE PROVIDE (__heap_end = __heap_start + __HEAP_SIZE); PROVIDE (__heap_size = __HEAP_SIZE); #else PROVIDE (__heap_end = __stack - __STACK_SIZE); PROVIDE (__heap_size = __heap_end - __heap_start); #endif .heap (NOLOAD) : { . += __heap_size; } >RAM0 :ram /* Define a stack region to make sure it fits in memory */ PROVIDE(__stack = ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE); PROVIDE(__stack_limit = __stack - __STACK_SIZE); .stack (__stack_limit) (NOLOAD) : { . += __STACK_SIZE; } >RAM0 :ram #if __STACKSEAL_SIZE > 0 PROVIDE(__stack_seal = __stack); .stackseal (__stack) (NOLOAD) : { . += __STACKSEAL_SIZE; } >RAM0 :ram #endif /* Throw away C++ exception handling information */ /* /DISCARD/ : { *(.note .note.*) *(.eh_frame .eh_frame.*) *(.ARM.extab* .gnu.linkonce.armextab.*) *(.ARM.exidx*) } */ /* Stabs debugging sections. */ .stab 0 : { *(.stab) } .stabstr 0 : { *(.stabstr) } .stab.excl 0 : { *(.stab.excl) } .stab.exclstr 0 : { *(.stab.exclstr) } .stab.index 0 : { *(.stab.index) } .stab.indexstr 0 : { *(.stab.indexstr) } .comment 0 : { *(.comment) } .gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) } /* DWARF debug sections. Symbols in the DWARF debugging sections are relative to the beginning of the section so we begin them at 0. */ /* DWARF 1. */ .debug 0 : { *(.debug) } .line 0 : { *(.line) } /* GNU DWARF 1 extensions. */ .debug_srcinfo 0 : { *(.debug_srcinfo) } .debug_sfnames 0 : { *(.debug_sfnames) } /* DWARF 1.1 and DWARF 2. */ .debug_aranges 0 : { *(.debug_aranges) } .debug_pubnames 0 : { *(.debug_pubnames) } /* DWARF 2. */ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } .debug_abbrev 0 : { *(.debug_abbrev) } .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end) } .debug_frame 0 : { *(.debug_frame) } .debug_str 0 : { *(.debug_str) } .debug_loc 0 : { *(.debug_loc) } .debug_macinfo 0 : { *(.debug_macinfo) } /* SGI/MIPS DWARF 2 extensions. */ .debug_weaknames 0 : { *(.debug_weaknames) } .debug_funcnames 0 : { *(.debug_funcnames) } .debug_typenames 0 : { *(.debug_typenames) } .debug_varnames 0 : { *(.debug_varnames) } /* DWARF 3. */ .debug_pubtypes 0 : { *(.debug_pubtypes) } .debug_ranges 0 : { *(.debug_ranges) } /* DWARF 5. */ .debug_addr 0 : { *(.debug_addr) } .debug_line_str 0 : { *(.debug_line_str) } .debug_loclists 0 : { *(.debug_loclists) } .debug_macro 0 : { *(.debug_macro) } .debug_names 0 : { *(.debug_names) } .debug_rnglists 0 : { *(.debug_rnglists) } .debug_str_offsets 0 : { *(.debug_str_offsets) } .debug_sup 0 : { *(.debug_sup) } .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) } } /* * Check that sections that are copied from flash to RAM have matching * padding, so that a single memcpy() of __data_size copies the correct bytes. */ ASSERT( __data_size == __data_source_size, "ERROR: .data/.tdata flash size does not match RAM size");
CMSIS/CoreValidation/Layer/Target/CM52/RTE/Device/ARMCM52/gcc_linker_script.ld 0 → 100644 +294 −0 Original line number Diff line number Diff line /* * Copyright (c) 2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE ( 8 ) #else #define __STACKSEAL_SIZE ( 0 ) #endif /* ---------------------------------------------------------------------------- Memory definition *----------------------------------------------------------------------------*/ MEMORY { ROM0 (rx) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE #if __ROM1_SIZE > 0 ROM1 (rx) : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE #endif #if __ROM2_SIZE > 0 ROM2 (rx) : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE #endif #if __ROM3_SIZE > 0 ROM3 (rx) : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE #endif RAM0 (rwx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE #if __RAM1_SIZE > 0 RAM1 (rwx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE #endif #if __RAM2_SIZE > 0 RAM2 (rwx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE #endif #if __RAM3_SIZE > 0 RAM3 (rwx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE #endif } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext (deprecated) * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack */ ENTRY(Reset_Handler) SECTIONS { .text : { KEEP(*(.vectors)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) } > ROM0 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) .gnu.sgstubs : { . = ALIGN(32); } > ROM0 #endif .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > ROM0 __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > ROM0 __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (LOADADDR(.data)) LONG (ADDR(.data)) LONG (SIZEOF(.data) / 4) /* Add each additional data section here */ /* LONG (LOADADDR(.data2)) LONG (ADDR(.data2)) LONG (SIZEOF(.data2) / 4) */ __copy_table_end__ = .; } > ROM0 .zero.table : { . = ALIGN(4); __zero_table_start__ = .; /* .bss initialization to zero is already done during C Run-Time Startup. LONG (ADDR(.bss)) LONG (SIZEOF(.bss) / 4) */ /* Add each additional bss section here */ /* LONG (ADDR(.bss2)) LONG (SIZEOF(.bss2) / 4) */ __zero_table_end__ = .; } > ROM0 /* * This __etext variable is kept for backward compatibility with older, * ASM based startup files. */ PROVIDE(__etext = LOADADDR(.data)); .data : ALIGN(4) { __data_start__ = .; *(vtable) *(.data) *(.data.*) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM0 AT > ROM0 /* * Secondary data section, optional * * Remember to add each additional data section * to the .copy.table above to assure proper * initialization during startup. */ /* .data2 : ALIGN(4) { . = ALIGN(4); __data2_start__ = .; *(.data2) *(.data2.*) . = ALIGN(4); __data2_end__ = .; } > RAM1 AT > ROM0 */ .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM0 AT > RAM0 /* * Secondary bss section, optional * * Remember to add each additional bss section * to the .zero.table above to assure proper * initialization during startup. */ /* .bss2 : { . = ALIGN(4); __bss2_start__ = .; *(.bss2) *(.bss2.*) . = ALIGN(4); __bss2_end__ = .; } > RAM1 AT > RAM1 */ .heap (NOLOAD) : { . = ALIGN(8); __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; } > RAM0 .stack (ORIGIN(RAM0) + LENGTH(RAM0) - __STACK_SIZE - __STACKSEAL_SIZE) (NOLOAD) : { . = ALIGN(8); __StackLimit = .; . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; } > RAM0 PROVIDE(__stack = __StackTop); #if __STACKSEAL_SIZE > 0 .stackseal (ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE) (NOLOAD) : { . = ALIGN(8); __StackSeal = .; . = . + 8; . = ALIGN(8); } > RAM0 #endif /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") }
Jonatan Antoni <jonatan.antoni@arm.com>Jonatan Antoni <jonatan.antoni@arm.com>