IAR __get_SP_usr/__set_SP_usr fix (#241) (6da4b495) · Commits · Wenxi XU / Cmsis 6

CMSIS/Core/Include/a-profile/cmsis_iccarm_a.h

+4 −4

Original line number	Diff line number	Diff line
		@@ -67,8 +67,8 @@ __IAR_FT uint32_t __get_SP_usr(void)
		"MRS %0, cpsr \n"
		"CPS #0x1F \n" // no effect in USR mode
		"MOV %1, sp \n"
		"MSR cpsr_c, %2 \n" // no effect in USR mode
		"ISB" : "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory"
		"MSR cpsr_c, %0 \n" // no effect in USR mode
		"ISB" : "+r"(cpsr), "=r"(result) :: "memory"
		);
		return result;
		}
		@@ -80,8 +80,8 @@ __IAR_FT void __set_SP_usr(uint32_t topOfProcStack)
		"MRS %0, cpsr \n"
		"CPS #0x1F \n" // no effect in USR mode
		"MOV sp, %1 \n"
		"MSR cpsr_c, %2 \n" // no effect in USR mode
		"ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory"
		"MSR cpsr_c, %0 \n" // no effect in USR mode
		"ISB" : "+r"(cpsr) : "r" (topOfProcStack) : "memory"
		);
		}

+5 −5

Original line number	Diff line number	Diff line
		@@ -69,10 +69,10 @@ __IAR_FT uint32_t __get_SP_usr(void) {
		__ASM volatile("MRS %0, cpsr \n"
		"CPS #0x1F \n" // no effect in USR mode
		"MOV %1, sp \n"
		"MSR cpsr_c, %2 \n" // no effect in USR mode
		"MSR cpsr_c, %0 \n" // no effect in USR mode
		"ISB"
		: "=r"(cpsr), "=r"(result)
		: "r"(cpsr)
		: "+r"(cpsr), "=r"(result)
		:
		: "memory");
		return result;
		}
		@@ -84,8 +84,8 @@ __IAR_FT void __set_SP_usr(uint32_t topOfProcStack) {
		"MOV sp, %1 \n"
		"MSR cpsr_c, %2 \n" // no effect in USR mode
		"ISB"
		: "=r"(cpsr)
		: "r"(topOfProcStack), "r"(cpsr)
		: "+r"(cpsr)
		: "r"(topOfProcStack)
		: "memory");
		}