Commit 63ff2c96 authored by Markus Klein's avatar Markus Klein Committed by Sudan Landge
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Fix documentation of the Register HPPIR_INTID (#233) 

Fix documentation of the Register HPPIR_INTID according to
"ARM Generic Interrupt Controller Architecture version 2.0 Architecture
Specification"
Table 4-41 GICC_HPPIR bit assignments


![409053189-dfa13d3e-1650-489b-a8f2-b061ac9afe17](https://github.com/user-attachments/assets/919edcce-ce77-450b-8839-af6555f2249a)
parent c4fdf052

CMSIS/Documentation/Doxygen/Core_A/src/ref_gic.txt

+3 −2
Original line number Diff line number Diff line
@@ -296,8 +296,9 @@ includes control of the end of interrupt (EOI) behavior. 


| Bits    | Name          | Function                                                       |

| :------ | :------------ | :------------------------------------------------------------- |

| [31:24] | -             | Reserved.                                                      |

| [23:0]  | INTID         | The INTID of the signaled interrupt.                           |

| [31:13] | -             | Reserved.                                                      |

| [12:10] | CPUID         | On a multiprocessor implementation this identifies the processor that generated the interrupt |

|  [9:0]  | INTID         | The INTID of the signaled interrupt.                           |



\var  __IM uint32_t GICInterface_Type::IIDR

\details CPU Interface Identification Register

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